reliable answers. As a consequence, each logical qubit of the algorithm must be encoded in some quantum error-correcting code using several (hundreds of) physical qubits, and each elementary gate in the quantum algorithm is implemented using several (thousands of) elementary gates on the physical hardware [@FMMM12]. Thus, the noisy physical device described in the previous paragraph might at best produce a reliable quantum computer performing a thousand operations per second on a dozen qubits.

One important research area in quantum information science is aimed at lowering this fault-tolerance overheads, i.e. finding better codes and fault-tolerant protocols which require fewer qubits, fewer gates, and achieve a better error suppression. While early studies in this area focused on “featureless” depolarizing noise, it has become clear that substantial gains can be achieved by taking into account specific details of the hardware in the protocol design [@ABD09; @PJ08; @WBP15; @TBF17]. At the moment, this is done at a rather coarse level: the foremost example is biased noise models, where it is assumed that errors corresponding to Pauli $X$ matrices (bit flip) are much less likely than those corresponding to Pauli $Z$ matrices (phase flip). This biased noise model is motivated by qubits built from 