atomic access. We propose aspects and attributes for specifying a particular memory model to be employed for reading/writing [synchronized]{} variables.

Modern multi-core computer architectures are equipped with a memory hierarchy that consist of main memory, caches and registers. It is important to distinguish between memory consistency and coherence. We cite from [@Hill:CSprimer]: [*‘For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date.’*]{}

The purpose of a memory consistency model (or memory model, for short) is to define the set of values a read operation is allowed to return [@Boehm:mem:survey]. To facilitate programmers’ intuition, it would be ideal if all read/write operations of a program’s tasks are sequentially consistent. However, the hardware memory models provided by contemporary CPU architectures relax SC for the sake of performance [@Adve:SMC:tutorial; @Hennessy:acquire:release; @Hill:CSprimer]. Enforcing SC on such architectures may incur a noticeable performance penalty. The workable middle-ground between intuition (SC) and performance 