evaluation results obtained using a set of synthetic and SPEC2006 benchmarks.

Evaluation Setup {#sec:setup}
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Our hardware platform is a quad-core Intel Xeon W3530 (Nehalem) [@molka2009memory] based computer. Each core has a private L1 cache (32K-I/32K-D) and a private L2 cache (256 KiB), and all cores share a 8MiB L3 cache. Shared MSHRs (called Global Queue or GQ [@intel2012optimization]) track the status of up to 32 read requests and 16 write requests from all cores. According to  [@david2012bandit], a single core can generate up to 10 concurrent read requests at a time, which we also experimentally verified to be true in our test platform. The memory controller (MC) is integrated in the processor and clocked at 1066 MHz. The computer equips a single-channel dual-rank 4 GiB PC10666 DDR3 DIMM module which includes 16 DRAM banks. We disabled all hardware prefetchers, dynamic voltage and frequency scaling, and the turbo-boost feature for better predictability.

We use PALLOC [@yun2014rtas] to partition DRAM banks and the L3 cache. For the purpose of our evaluation, we assign one private DRAM bank and 1/4 (2MiB) private L3 cache partition to each core. Therefore, there are neither cache space evictions nor DRAM bank conflicts caused by memory 