constraints are: 1) the latency for accessing a closed row is much longer than accessing a row that is already open; 2) different banks can be operated in parallel since there are no long timing constraints between banks. To maximize memory performance, modern DRAM controllers typically use a first-ready first-come-first-serve (FR-FCFS) [@rixner2000memory] scheduling algorithm that prioritizes:

1.  Ready commands over non-ready commands,

2.  Column (CAS) commands over row (RAS) commands,

3.  Older commands over younger commands.

This means that the algorithm can process memory requests in out-of-order of their arrival times. Note that a DRAM command is said to be *ready* when it can be scheduled immediately as it satisfies all timing constraints imposed by previously scheduled commands and the current DRAM status.

DRAM Bank and Cache Partitioning
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In order to maximize memory level parallelism, most COTS DRAM controllers employ a version of *interleaved bank* addressing strategy. Under this scheme, consecutive memory blocks in physical address space, typically of the size of a memory page, are allocated to different banks. This makes pending memory requests in the DRAM controller are likely to target different banks, thereby maximizing memory level parallelism. In the worst case, however, it is possible that 