---
abstract: |
    In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time. The processing of these parallel requests in the DRAM controller greatly affects the memory interference delay experienced by running tasks on the platform.

    In this paper, we model a modern COTS multicore system which has a non-blocking last-level cache (LLC) and a DRAM controller that prioritizes reads over writes. To minimize interference, we focus on LLC and DRAM bank partitioned systems. Based on the model, we propose an analysis that computes a safe upper bound for the worst-case memory interference delay.

    We validated our analysis on a real COTS multicore platform with a set of carefully designed synthetic benchmarks as well as SPEC2006 benchmarks. Evaluation results show that our analysis is more accurately capture the worst-case memory interference delay and provides safer upper bounds compared to a recently proposed analysis which significantly under-estimate the delay.
author:
- |
    Heechul Yun\
    University of Kansas, USA.\
    heechul.yun@ku.edu\
bibliography:
- 'heechul.bib'
title: 'Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems'
---

Introduction
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In modern Commercial Off-The-Shelf (COTS) multicore systems, many parallel memory requests can be sent to the main memory 