=$ 1 - 10$\mu$m), long ($L =$100 - 700$\mu$m) legs patterned into the membrane, using Deep Reactive Ion Etching (DRIE), to achieve the necessary thermal isolation. The lower the target NEP, the lower the thermal conductance required, and this leads to quite extreme geometries. In the case of ultra-low-noise imaging arrays, long legs ($L =$ 500$\mu$m - 1mm) prevent tight optical packing, and inefficient optical coupling schemes must be used to minimise the effects of the large pixel-to-pixel spacing. In addition, SiN$_{\rm x}$ is a highly disordered dielectric and contains an abundance of Two Level Systems (TLSs) [@anderson1972anomalous; @phillips1972tunneling; @zink2004specific]. TLSs result in a specific heat that is many hundreds of times higher than the Debye value and, when combined with low thermal conductance, this leads to devices that are too slow for some applications. Also, phonon trapping in long, narrow legs causes localised transport, which results in wide variations (at least $\pm$ 15 %) in the performance of even notionally identical devices on the same wafer.

In a previous paper we demonstrated that it is possible to manufacture SiN$_{\rm x}$ TESs having tiny ballistic support legs ($H =$ 200nm, $W <  1\,\mu $m, $L = $ 1 - 4$\mu$m) 