set to the value smaller than $n$, which prevents generating and solving a system of linear equations with $A$ and $b$ treated as unknowns, (2) a part of the configuration is data-dependent and is fed from the output of the CSTN (stateful), so the values of $A$ and $b$ are not the same in any two encryptions, without the need of feeding CSTN with two completely different TRN values, (3) the substitution box added after the CSTN will eliminate all linearity/predictability of the CSTN using the algebraic attack.

Experimental Setup and Analysis {#sec:results}
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For evaluation, all designs have been implemented using Verilog HDL, and have been synthesized for both FPGA and ASIC targets. For ASIC verification, we used Synopsys generic 32nm process. For FPGA verification, we targeted a small FPGA board, Digilent Nexys-4 DDR with Xilinx Artix 7 (XC7A100T-1CSG324). In addition, for SAT evaluation, we employed the Lingling-based SAT attack [@subramanyan2015evaluating] on a Dell PowerEdge R620 equipped with Intel Xeon E5-2670 2.6 GHz and 64GB of RAM. Also, as noted, a run-time limit of $2 \times 10^6$ seconds was set for the SAT solver. For ciphers, we used two side-channel resistant ciphers (AES-GCM128 as a block authenticated cipher, and 