interference delay to a newly arrived read request.

### Data Bus Contention Delay

When the DRAM controller is in the read processing mode, the worst-case to a newly arrived read request occurs when the request buffer is fully occupied by previously arrived $N_{rq}$ read requests from the other competing cores. Furthermore, regardless whether the read request under analysis is row-hit or row-miss, the worst-case interference delay occurs when all the previous reads are pipelined (i.e., overlapped scheduling [@natarajan2004study]).

Reads can be pipelined in two cases: consecutive reads on the same row or reads over different banks (see Figure \[fig:motivation2\]). When reads are pipelined, the data bus is fully occupied and the newly arrived read (the request under analysis) must wait until all the previous reads are processed (because FR-FCFS prioritize older requests). If, however, the previous requests are not pipelined, the read request under analysis (younger request) can be processed ahead of older requests on the other banks (i.e. out-of-order processing). Figure \[fig:timing-reorder\] shows such an example. At time 0, both RD3 and RD1 are ready to be scheduled and FR-FCFS schedules RD1 as it is older than RD3. At time 4, both PRE1 and RD3 are ready, but this 