MRAMs). Such memories are fast and compact non volatile memories, which can be embedded at the core of CMOS processes, and therefore provide an ideal technology for realizing in-memory neural networks [@yu2018neuro; @ielmini2018memory; @burr2017neuromorphic].

A considerable challenge of this approach is that modern neural networks require important amounts of memory [@canziani2016analysis], which is not necessarily compatible with hardware in-memory computing approaches. [Multiple roads have been explored to reduce the precision and memory requirements of neural networks. The quantization of the weights used for inference is the most natural route [@hubara2017quantized]. Architectural optimization can result in considerable reduction in terms of number of parameters and arithmetic operations, with only modest reduction in accuracy [@sandler2018mobilenetv2]. Network pruning [@reagen2016minerva] or network compression [@chen2015compressing; @han2015deep] techniques, sometimes combining different methods, can allow implementing hardware neural networks with reduced memory access and therefore higher energy efficiency.]{}

[ Binarized Neural Networks (BNNs) have recently appeared as one of the most extreme vision of low precision neural networks, as they go further than these approaches [@courbariaux2016binarized; @rastegari2016xnor].]{} In these simple deep neural networks, synaptic weights as well as neuron activations assume Boolean values. These models can nevertheless achieve state-of-the-art performance on image recognition, while being multiplier-less, and 