write) that evicts a modified cache-line in the L3 cache, and program execution can proceed without waiting the write request to be processed in the DRAM. Therefore, for the analysis purpose, we only consider memory interference delay imposed to each read request of the task under analysis $\tau_i$. Note that the number of DRAM read requests $H_i$ is equal to the number of LLC misses because, in a write-back write-allocate cache, a write miss also generates a DRAM read request to allocate the line in the L3 cache and then write to it.

On the DRAM controller side, we assume a modern DRAM controller that supports the FR-FCFS scheduling policy [@rixner2000memory; @wang2005umd] which is connected to a DDR3 DRAM module. At each memory clock tick, we assume a highly efficient FR-FCFS scheduler that picks the highest priority ready command among all requests and can overlap multiple requests simultaneously as long as DRAM bank and channel level timing constraints and the FR-FCFS priority rules are satisfied [@natarajan2004study]. We also assume that the DRAM controller has a read request buffer and a write request buffer, and prioritizes reads over writes. The writes are only serviced when there is no pending read request 