or the write buffer is full. The maximum number of prior read requests queued in the read request buffer is denoted as $N_{rq}$ and we assume it is much bigger than $N_{proc}$. In processing write requests, we assume it processes at least $N_{wq}$ requests in a batch to amortize the cost of the bus turnaround delay  [@chatterjee2012staged]. The values of $N_{rq}$ and $N_{wq}$ are platform specific and determined by the number of MSHRs, the size of read request buffer and the write-scheduling algorithm in the DRAM controller. Table \[tbl:sysparams\] shows the parameters we used throughput this paper which closely model our evaluation platform described in Section \[sec:setup\].  [^1]

All previously mentioned assumptions closely follow common behaviors of commercial COTS DRAM controllers [@natarajan2004study]. We assume open-page policy is used for bank management to maximize data locality. We assume a single rank DRAM module for simplicity but our analysis can be extended to consider a multi-rank DRAM module.

We assume DRAM banks and the LLC space are partitioned on a per-core basis. In other words, each core is assigned its own private DRAM banks and LLC space. This can be easily achieved by using software partitioning techniques on COTS systems [@yun2014rtas; @liu2012software].

