accesses from contending cores.

For measurement, we use Linux kernel’s $perf$ infrastructure to monitor LLC miss hardware performance counter.

Results with Synthetic Benchmarks {#sec:result_syn}
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\[t\] ![Measured and analytic worst-case response times of *Latency* benchmark under high memory interference.[]{data-label="fig:result_syn"}](result_syn "fig:"){width="45.00000%"}

We now investigate the validity of our analysis compared to experimental results obtained using a set of carefully engineered synthetic benchmarks.

In this experiment, our goal is to simulate and measure the worst-case memory interferences on a system in which DRAM banks and the LLC are partitioned. We use *Latency* benchmark [@yun2013rtas] as the task under analysis. The benchmark is a pointer-chasing application over a randomly shuffled linked-list. Due to data dependency, it only can generate one outstanding memory request at a time. Furthermore, because the size of linked list is two times bigger than the size of the LLC, each memory access is likely to result in a cache miss, hence generating a DRAM request. As a result, its execution time highly depends on DRAM performance and any delay in its memory access will directly contribute to its execution time increase. In effect, this benchmark defeats any potential benefits from out-of-order instruction processing and other memory latency hiding techniques 