request at a time and stalls until the memory request is served. Unfortunately, this assumption is far from reality in modern COTS platforms. As outstanding requests can interfere with the memory request under analysis, the actual worst-case depends on the number of outstanding requests, which is typically substantially higher than the core count. For example, a COTS multicore processor used in our evaluation supports up to 32 outstanding reads and 16 outstanding writes while it has only 4 cores. As a result, the computed memory interference bounds can be significantly optimistic than the reality (i.e., underestimating the actual delay), as we experimentally demonstrated in Section  \[sec:result\_syn\].

In this work, we present a parallelism-aware memory interference delay analysis. We model a COTS DRAM controller that has a separate read and a write request buffer. Multiple outstanding memory requests can be queued in the buffers and processed in out-of-order to maximize memory performance. Also, reads are prioritized over writes in our model. These features are commonly found in modern COTS multicore systems and crucially important in understanding memory interference. To minimize interference, we only consider a system in which the LLC and DRAM banks are partitioned. This is easily achievable on COTS 