in one thread synchronizes-with operation [Y]{} in another thread, then [X]{} happens-before [Y]{}. Note that the happens-before relation is transitive, i.e., if [X]{} happens-before [Y]{} and [Y]{} happens-before [Z]{}, then [X]{} happens-before [Z]{}. This is true even if [X]{}, [Y]{}, and [Z]{} are part of different threads.

We define different memory models. These memory models originated from the DRF [@Hill:DRF:SC] and properly-labeled [@Hennessy:acquire:release] hardware memory models. They were formalized for the memory model of C++ [@Boehm:cpp:mem]. The “sequentially consistent” and “acquire-release” memory models provide SC for DRF. The models can have varying costs on different computer architectures. The “acquire-release” memory model is a relaxation of the “sequentially consistent” memory model. As described in Table \[MMcompcpu\], it requires concessions from the programmer to weaken SC in turn for more flexibility for the CPU to re-order memory operations.

Sequentially Consistent Ordering

:   is the most stringent model and the easiest one for programmers to work with. In this case all threads see the same, total order of operations. This means, a sequentially consistent write to a [synchronized]{} variable synchronizes-with a sequentially-consistent read of the same variable.

Relaxed Ordering

:   does not obey synchronizes-with relationships, but operations on the same [synchronized]{} variable within 