networks with minimal energy consumption. To achieve this goal, it brings memory and computation as close as possible, to limit energy consumption related to data transfer. Such an architecture takes special interest with the emergence of new non-volatile memory components such as Spin Torque MRAM, which can be integrated within the CMOS manufacturing process, and which we consider here.

The architecture is described in detail in Appendix \[sec:appendix\_system\], and [can compute following a parallel or a sequential structure]{}. [The full design is made by a basic cell repeated 32x32 times (Fig. \[fig:archi\] (b-c)) that can perform both sequential or parallel calculation. It includes a 2 kbits memory array to stores weights, as well as XNOR gates and popcount logic.]{}

We designed this system using the design kit of a commercial 28 nanometer technology. [Digital circuits were described in synthesizable SystemVerilog description.]{} MRAM memory arrays are modeled in a behavioral fashion, and their characteristics (area, energy consumption) are inspired by [@chun2013scaling]. The system was synthesized to estimate its area and energy consumption. For energy consumption, we employed Value Change Dumps extracted from a Fashion-MNIST inference task, and estimated it using the Cadence Encounter tool.

Energy Consumption and Area Results
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