results highlight the high potential of Binarized Neural Networks for hardware implementation, and that adapting them to hardware constrains can provide important benefits.'
address:
- 'Centre de Nanosciences et de Nanotechnologies, Univ. Paris-Sud, CNRS, France'
- 'Institut Matériaux Microélectronique Nanosciences de Provence, Univ. Aix-Marseille et Toulon, CNRS, France'
author:
- |
    , , , , ,\
    and
bibliography:
- 'biblio.bib'
title: Stochastic Computing for Hardware Implementation of Binarized Neural Networks 
---

Binarized Neural Network, Stochastic Computing, Embedded System, MRAM, In Memory Computing

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Introduction {#sec:introduction}
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advances in deep learning have transformed the field of machine learning, with numerous achievements in image or speech recognition, machine translation and others. However, a considerable challenge of deep neural network remains their energy consumption, which limits their use within embedded systems [@editorial_big_2018]. The hardware implementation of deep neural networks is a widely investigated approach to increase their energy efficiency. A particularly exciting opportunity is to rely on in-memory or near-memory computing implementations [@yu2018neuro; @ielmini2018memory; @querlioz2015bioinspired; @burr2017neuromorphic; @giacomin2018robust], which are highly energy efficient as they avoid the von Neumann bottleneck entirely. This idea takes special meaning today, in particular with the emergence of novel memories such Resistive and Magnetoresistive Random Access Memories (RRAMs and 