-   To the best of our knowledge, our work is the first that considers memory level parallelism and read prioritized DRAM controllers to analyze memory interference delay.

-   We experimentally validate and compare our analysis with a state of art analysis on a real COTS multicore platform with a set of carefully designed synthetic benchmarks as well as SPEC2006 benchmarks.

-   We propose two simple architectural supports that can significantly reduce worst-case memory interference delay on COTS multicore processors.

The remaining sections are organized as follows: Section \[sec:background\] provides background on COTS multicore systems and LLC and DRAM bank partitioning techniques. Section \[sec:motivation\] discusses the state-of-art memory interference delay analysis. We present our analysis in Section \[sec:analysis\] and provide evaluation results in Section \[sec:evaluation\]. Section \[sec:recommendation\] discusses architectural recommendations. Section \[sec:related\] discusses related work. Finally, we conclude in Section \[sec:conclusion\].

Background: Modern COTS Multicore systems {#sec:background}
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A modern COTS multicore system, shown in Figure \[fig:architecture\], supports a high degree of memory level parallelism through a variety of architectural features. In this section, we provide some background on important architectural features of modern COTS multicore systems, and review existing software based resource partitioning techniques.

\[t\] ![Modern COTS multicore architecture[]{data-label="fig:architecture"}](architecture "fig:"){width="40.00000%"}

