locations. Consequently, most schemes will be analyzed using three ratios ($\tilde{p} = p$, $\tilde{p} = p/10$ and $\tilde{p} = p/100$) to highlight the impact of idle qubit locations on the logical failure rate.

The two-qubit gates we consider are: CNOT, XNOT$ = H_1(\text{CNOT})H_1$, and CZ$ = H_2(\text{CNOT})H_2$.

Logical failure rates are estimated using an $N$-run Monte Carlo simulation. During a particular run, errors are added at each location following the noise model described above. Once the error locations are fixed, the errors are propagated through a fault-tolerant error correction circuit and a recovery operation is applied. After performing a correction, the output is ideally decoded to verify if a logical fault occurred. For an error correction protocol implemented using a stabilizer code $C$ and a fixed value of $p$, we define the logical failure rate $$p_{\text{L}}^{(C)}(p) = \lim_{N \to\infty} \frac{N_{\text{fail}}^{(C)}(p)}{N} ,$$ where $N_{\text{fail}}^{(C)}(p)$ is the number of times a logical $X$ *or* logical $Z$ error occurred during the $N$ rounds. In practice we take $N$ sufficiently large to estimate $p_{\text{L}}^{(C)}(p)$, and provide error bars [@AliferisCross07; @CJL16b].

In this paper we are concerned with evaluating the performance of FTEC protocols (i.e. we do not consider performing logical gates fault-tolerantly). We define 