cycles
      $tCCD$       Column-to-Column delay           4   cycles
      $tWTR$          Write to read delay           4   cycles
      $tRRD$   Activate to activate delay           4   cycles
      $tRTP$      Read to precharge delay           4   cycles
      $tFAW$        Four activate windows          20   cycles
       $tRC$               Row cycle time          27   cycles

  : DRAM timing parameters [@micronddr3]

\[tbl:dramparams\]

\[t\]

\[t\] ![image](timing-worst){width="95.00000%"}

Delay Analysis
--------------

We now present our analysis that considers parallel memory requests in modern COTS multicore systems.

As mentioned in the previous section, write memory requests are not in the critical path of program execution in modern COTS systems. Hence, our primary concern is memory interference delay to read requests of the task under analysis.

As we consider a system in which both the LLC cache and DRAM banks are partitioned on a per-core basis, conventional cache space and share bank level contention do not exist. However, because the command and data bus are shared in processing the queued memory requests, DRAM controller’s request scheduling greatly affects memory interference delay. We now detail our delay analysis. Because the DRAM controller prioritize reads and the bus turn-around cost is high, the DRAM controller process requests in a *batch* for either reads or writes. In each processing mode, we analyze the worst-case memory 