Even with a single image presentation $T$, the network approaches the performance of the non stochastic network. The stochastic BNN approach therefore appears especially effective in this situation. ]{}

Hardware Implementation of Stochastic Computing-Based Binarized Neural Network {#sec:hardware}
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In order to investigate the potential of the stochastic BNN approach, we designed a digital ASIC version of it using standard integrated circuit design tools. The architecture, presented in Fig. \[fig:archi\], allows performing the inference of a fully connected binary neural network of any size (up to 1024 neurons for each layer). The only parameter constrained by the hardware design is the number of weights that can be stored.

Design of the Architecture
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(topskip=0pt, botskip=0pt, midskip=0pt) \[scale = 0.17\][archi.png]{} [Design of an MRAM based fully connected binarized neural network, computing both parallel and serial. (a) Full architecture with $32 \times 32$ repeated cells. Each cell (b-c) behaves as a neuron if the input is sequential, or each column behaves as a neuron if the input is parallel. \[fig:archi\]]{}

Our architecture is inspired by the works of [@ando2017brein], with Static RAMs replaced by Spin Torque MRAM [@shum2017cmos], and adaptation to stochastic computing. This architecture aims at performing inference on binarized neuronal 