as it undermines the safety of the computed WCET.

We experimentally validated the former problem on our test platform with carefully engineered synthetic tasks, as we will detail in Section \[sec:result\_syn\]. To summarize the result, the calculated worst-case response time using the stated analysis is up to 53% smaller than the measured worst-case response time. The result motivates our analysis in the next section.

Parallelism-Aware Memory Interference Delay Analysis {#sec:analysis}
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In this section, we present our parallelism-aware memory interference delay analysis that is aimed to support modern COTS multicore systems. We begin by defining the system model on which our analysis is based. We then present the main analysis with examples.

System Model
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We consider a modern multicore architecture described in Section \[sec:background\]. Specifically, there are $N_{proc}$ identical cores in a single processor chip. A single LLC and MSHRs are shared among the cores. When there is a miss in the LLC, an entry is registered on the MSHR and it is removed when the associated DRAM transaction is completed. We assume a typical shared L3 cache that employs write-back write-allocate policy. Hence a write to DRAM only occurs when there is a L3 miss (either read or 