research topic in the real-time systems community.

To this end, software based DRAM bank partitioning  [@yun2014rtas; @liu2012software; @suzuki2013coordinated] and last-level cache (LLC) partitioning  [@zhang2009towards; @mancuso2013rtas; @ding2011srm; @ward2013rtas; @lin2008gaining] have been studied by many researchers. These approaches reduce interference by allocating dedicated cache space and/or DRAM banks. While effective, it is also shown that partitioning these resources alone does not provide ideal isolation due to interference in other parts of the memory hierarchy, most notably in the DRAM controller and the shared memory bus (command and data) which connects the controller and the DRAM module  [@yun2014rtas; @kim2014rtas]. As a result, it is still difficult to understand worst-case memory interference delay, even when the LLC and DRAM banks are partitioned.

Recently, Kim et al. proposed an analysis method that takes the DRAM controller and the shared memory bus into account [@kim2014rtas]. They faithfully model a modern COTS DRAM system, and provide an analytic upper bound on the worst-case memory interference delay of each memory request of the task under analysis. However, their analysis made a significant assumption that makes it difficult to apply it to modern COTS multicore systems. Specifically, the analysis assumes that each core can only generate one outstanding memory 