clock tick (25 ns) from each cell in the HCAL. This defines a “time sample”. The HCAL front-end electronics does not sample the signal instantaneously; rather, the electric current collected from the photodetectors is integrated over each clock period and then sampled. As a consequence, the sample clock is most commonly termed the “integration clock”.

The integration clock can be delayed with respect to the LHC clock on a per-channel basis by programmable settings, referred to as sampling delay settings, that have a resolution of 1 ns. The purpose of these settings is to compensate for channel-dependent timing variations at the hardware level, and to permit the energy estimate from each LHC crossing to be reconstructed consistently for use in the Level-1 trigger for all pulse amplitudes and for all channels. They also provide an initial coarse timing calibration.

Sources of timing variation and uncertainty {#subsec:sources}
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There are two dominant sources of channel-dependent timing variation: the different time-of-flight of particles from the interaction region to each HCAL cell and the different signal propagation times through optical fibers of different lengths. Within the barrel, the first effect tends to skew reconstructed times later for higher $\eta$. The second effect, because 