applicable in modern COTS multicore systems.

The analysis models a modern COTS memory system in great detail. While there has been a similar effort in the past  [@zheng2013worst], this is the first work that considers the DRAM bank level request reordering effect (i.e., out-of-order execution of young row-hit column requests over older row-miss requests). Here, we briefly summarize the assumed system model and part of the memory interference delay analysis, relevant for the purpose of this paper.

The system model assumes a single channel DRAM controller and a DDR3 memory module. The DRAM controller includes request buffers and uses the FR-FCFS scheduling algorithm. At the high level, the analysis computes the worst-case memory interference delay of the task under analysis $\tau_i$ either (1) as a function of number of memory requests $H_i$ of the task (referred as Request driven approach) or (2) as a function of the number of memory requests generated by the other tasks on different cores (referred as Job driven approach)—it takes the minimum of the two—similar to prior work [@yun2012ecrts]. The unique characteristics of the analysis is that it considers both inter-bank and intra-bank (including request reordering) memory interference delay. For the purpose of this paper, 