Finally, we assume that any increase in memory latency is additive to the task’s execution time as in [@kim2014rtas]. This is a pessimistic assumption given that we consider out-of-order cores that can hide much of memory access latency. Modeling reduced memory latencies by OoO cores is, however, out of the scope of this paper.

In short, our system model is similar to  [@kim2014rtas], but significantly differs in that (1) it models multiple parallel memory requests buffered in the DRAM controller, and (2) it maintains separate read and write request queues in the DRAM controller and reads are prioritized over writes. Both are common characteristics of modern COTS multicore memory systems  [@natarajan2004study].

Lastly, Table \[tbl:dramparams\] shows the DRAM parameters we used throughout this paper.

       Symbols                           Description   Value
  ------------ ------------------------------------- -------
      $N_{rq}$    Maximum no. of prior read requests      30
      $N_{wq}$   Maximum no. of prior write requests       4
    $N_{proc}$                       Number of cores       4

  : System parameters for our evaluation platform

\[tbl:sysparams\]

     Symbols                  Description   DDR3-1066    Units
  ---------- ---------------------------- ----------- --------
       $tCK$        DRAM clock cycle time        1.87     nsec
       $tRP$           Row precharge time           7   cycles
      $tRCD$          Row activation time           7   cycles
        $CL$                 Read latency           7   cycles
        $WL$                Write latency           6   cycles
    $tBURST$          Data burst duration           4   