*optimistic* as it assumes each interfering core only can generate one outstanding memory request at a time. Hence, it essentially limits the maximum number of competing requests to the number of cores in the system. However this is far from reality as modern COTS multicore can generate many parallel memory requests at a time. For example, a quad-core processor used in our evaluation can generate up to 48 concurrent DRAM requests at a time (see Section \[sec:setup\] for details). Because DRAM performance is much slower than CPU performance, these requests are queued inside the DRAM controller and can aggravate the overall delay. Figure \[fig:motivation1\] illustrates this problem. In the figure, three parallel requests RD1, RD2, and RD3 are already in the command queue for Bank2, when the request RD4 has arrived at Bank1. Note that the DRAM commands are numbered in the order of their arrival times in the DRAM controller. At memory clock 0, both RD1 and RD4 are ready, but RD1 is scheduled as FR-FCFS policy prioritizes older requests over younger ones. Similarly, RD2 and RD3 are prioritized over RD4 at time 4 and 8, respectively. At other times such as at clock 1, RD4 cannot be scheduled 