due a channel timing constraint ($tCCD$), even though it is ready w.r.t. the Bank1. On the other hand, it is also overly *pessimistic* as a memory request—composed of PRE, ACT, and RD/WR DRAM sub-commands—is assumed to suffer inter-bank interference for each sub-command, while in reality the delays of executing sub-commands of a memory request are not additive on efficient modern COTS memory controllers. Figure \[fig:motivation2\] shows such a case. In the figure, each bank has one row miss DRAM request. Hence, each has to open a new row with a ACT command followed by a RD command. Following the FC-FRFS policy, ACT1 on Bank2 is executed first at clock 0. Even though ACT2 is targeting to a different bank, it is not scheduled immediately due to the required minimum separation time $tRRD$ between two inter-bank ACT commands. At clock 4, however, ACT2 can be issued even though ACT1 on the Bank2 is still in progress. In other words, the two memory requests are *overlapped*. Hence, when RD2 is finally issued at time 11, there is no extra inter-bank delay other than the initial delay of $tRRD$.

From the point of view of WCET analysis, the former problem is more serious 