botskip=0pt, midskip=0pt) \[scale = 0.35\][merged\_cell.png]{} [(a) Area of the basic cell (Fig.  \[fig:archi\] (b-c)) of our ASIC architecture, implemented in a 28 nm CMOS technology, as function of the number of operating bit for a fixed point binary architecture. One-bit corresponds to our stochastic fully binarized architecture. (b) Corresponding energy consumption, per clock cycle. \[fig:area\]]{}

Fig. \[fig:area\](a) shows the area of a basic cell of our architecture (Fig. \[fig:archi\](b-c)), in the case of binary input (one operating bit), and in situations where the input is coded in Fixed Point representation (two, four and eight operating bit), as is required in the first layer of a conventional BNN. [ This Figure separates the area used by registers, logic and MRAM. A cell with binary input uses six times less area than a cell designed for eight bit input. ]{} Interestingly, the difference is mostly due to the $\operatorname*{popcount}$ circuits, which need more depth when the input is non-binary. Similarly, as seen in Fig. \[fig:area\](b), a cell with binary input uses $4.5$ times less energy per cycle than the corresponding one with eight bits input. Again, the difference is mostly due to the $\operatorname*{popcount}$ circuits.

(topskip=0pt, botskip=0pt, midskip=0pt) \[scale = 0.35\][full\_consum.png]{} [Energy 