translated into a corresponding Ising problem of $N$ variables $s_i$, $i = 1,\ldots, N$ with $s_i \in \{+1, -1\}$ given by the following expression: $$\label{eq:IsingObjFun}
O_{\textrm{Ising}}({\bf s}) = \sum_{i=1}^{N} h_i s_i + \sum_{i=1}^{N} 
\sum_{j=i+1}^{N} J_{ij} s_i s_j \; .$$

Ising and QUBO models are related through the transformation $s_i = 2 q_i - 1$, hence the relationship with Eq.(\[eq:QUBO\]) is $J_{ij}=\frac{1}{4}b_{ij}$ and $h_i=(\frac{1}{2}a_i+\sum_{j}b_{ij})$, disregarding an unimportant constant offset.

#### Chimera-embedded Ising representation

In the standard programming practices of the analog D-Wave Quantum Annealer 2000Q^TM^ (DW2000Q) each spin-variable $s_i$ should be ideally assigned to a specific chip element, a superconducting flux qubit, modeled by a quantum two level system that could represent the quantum Hamiltonian $\mathcal{H}_{\textrm{local}}=\sum_i  h_i \sigma_i^z$, with $\sigma_i^z$ being the usual Pauli matrix representation for an Ising quantum spin-$\frac{1}{2}$. Each qubit supports the programming of the $h_i$ terms. Instead, $J_{ij}$ parameters can then be implemented energetically through inductive elements, meant to represent $\mathcal{H}_{\textrm{couplers}}=\sum_{ij}J_{ij}\sigma_i^z\sigma_j^z$, if and only if the required circuitry exists between qubits $i$ and $j$. Couplers cannot be manufactured connecting qubits too far apart in the spatial layout of the processor due to engineering considerations. In other words $J_{ij}=0$ unless $(i,j)\in \chi_{16}$, where $\chi_{16}=(V,E)$ is the *Chimera* graph 