and LLC substantially reduce memory interference among the cores [@yun2014rtas].

However, the LLC cache space and DRAM banks are not the only shared resources contributing to memory interference. Most notably, at the DRAM chip level, all DRAM banks fundamentally share the common command and data bus. Hence, contention in the buses can become a bottleneck. Furthermore, as many memory requests can be buffered inside the DRAM controller’s request buffers, its scheduling policy can greatly affect memory interference delay. Finally, at the LLC level, the MSHRs for the LLC are also shared by all cores even if the cache space is partitioned. We will show its performance impact in Section  \[sec:result\_spec\].

**Goal:** The goal of this paper is to analyze the worst-case memory interference delay in a cache and DRAM bank partitioned system, focusing mainly on delay in the DRAM controller and command and data bus between the controller and the DRAM module.

The State of Art Delay Analysis and the Problem {#sec:motivation}
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In this section, we first review a state of art memory interference delay analysis for COTS memory systems, proposed by Kim et al. [@kim2014rtas]. We then investigate some of its assumptions that are not generally 