however, we focus on their inter-bank delay analysis that assumes each core is assigned *dedicated DRAM bank partitions* using software bank partitioning systems [@yun2014rtas; @liu2012software].

The analysis assumes that each memory request of $\tau_i$ is composed of PRE, ACT, and RD/WR DRAM commands (i.e., a row-miss) and each of the command can be delayed by DRAM commands generated by other tasks on different cores, due to inter-bank timing constraints imposed by the JEDEC DDR3 specification [@jedec]. These timing constraint imposed inter-bank delay for PRE, ACT, and RD/WR commands are denoted as $L_{inter}^{PRE}$, $L_{inter}^{ACT}$, and $L_{inter}^{RW}$, respectively.

One major assumption of the analysis is that each core can generate only *one outstanding memory request* to the DRAM controller. Based on this assumption, the worst-case per-request inter-bank memory interference delay on a core $p$, $RD_p^{inter}$, is simply expressed by $
RD_p^{inter} = \sum_{\forall q: q \neq p} \times ( L_{inter}^{PRE} + L_{inter}^{ACT} + L_{inter}^{RW}).
$

Finally, the total memory interference delay of a task is calculated by multiplying $RD_p^{inter}$ to the number of total LLC misses $H_i$ of $\tau_i$

The analysis, however, has two main problems when it is applied to modern COTS multicore systems. On the one hand, it is overly 