tunnel junction (MTJ) STO, which provides comparatively large output power, show great potential to be used in different applications. This motivates the focus of this work on the MTJ STO. However, unlike for the case of STT-MRAM, very little progress has been achieved in modeling the STOs for circuit- and system-level design, impeding the development of STO-based applications. The only existing MTJ STO models [@MTJSTO_model1], [@MTJSTO_model2] are limited by several factors. For instance, they offer a limited applicable range, inaccurate DC operating point, and utilize expressions that are not fully validated by experiments or theory. A new analytical MTJ STO model, which can overcome these issues, has been proposed in Part I [@Tingsu_2014TEDI]. To further allow being used by a circuit simulator, such as Cadence Spectre-RF, which can analyze the analog and RF performances of STO-based circuits and systems, the analytical MTJ STO model should be implemented in a hardware description language. Verilog-A is a hardware description language, which uses mathematical expressions to model the behaviors of arbitrary types of devices and components, while allowing circuit- and system-level design and analyses. Therefore, Verilog-A is suitable and will be used for modeling MTJ STOs. In the existing MTJ STO models [@MTJSTO_model1], 