multicore systems via software [@liu2012software; @suzuki2013coordinated]. Based on the system model, our analysis provides a safe analytic upper bound on the worst-case memory interference delay for each memory request of the task under analysis.

We evaluate the proposed analysis on a real COTS multicore platform with a set of synthetic benchmarks as well as SPEC2006 benchmarks. The synthetic benchmarks are specially designed to simulate worst possible memory interference delay. As for synthetic benchmarks, our analysis provides a tight and safe upper bound while the analysis in  [@kim2014rtas] significantly under-estimates the actual delay (almost double than the computed delay). As for SPEC2006 benchmarks, we found our analysis provides safe upper bounds for all but two benchmarks, while the compared analysis under-estimates 11 (out of 19) benchmarks. Investigating the two benchmarks that our analysis under-estimated (so did  [@kim2014rtas]), we find that space competition in miss status holding registers (MSHRs) [@kroft1981lockup], which track the status of outstanding cache misses, can be a considerable source of additional interference in modern COTS systems.

Based on our analysis and empirical evaluation, we propose two simple architectural supports, which can be easily incorporated in modern COTS, to effectively reduce worst-case interference delay.

Our contributions are as follows:

