The next level is the shared memory, that is configurable 16KB or 48KB per block having a latency of only 2 cycles. At the top there are 32K registers per block. There are also texture and constant memory, having special addressing capabilities, but they do not bring any performance improvement in our application. The Fermi architecture has also incorporated ECC memory support to eventually deal with internal data corruption.

The programming side of this architecture is a “C for CUDA”, an extension of the C Programming Language [@KR78] that enables the *host* processor to launch *device* kernels [@Kirk10]. A kernel is a (usually small) piece of code that is compiled by `nvcc`, the NVIDIA CUDA Compiler, to the PTX assembler that the architecture is able to execute. The kernel is executed simultaneously by many threads, organized in a two-level hierarchic set of parallel instances indexed as $(\mathit{grid},\mathit{block})$ (a grid of thread blocks). Internally each grid and block can be divided up to two dimensions for the grid and three dimensions for the block, in order to establish a simple thread-to-data mapping. Special variables store the thread position information of block and thread identifier $(\mathit{bid},\mathit{tid})$ that distinguishes the threads executing the 