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As with the cache buffer invalidation signal handling , there is no processor interruption , processor cache disruption , or software task context switch caused as a result of processing the list state transition command . Some problems which could be actual for the design of the proposed device , for previous investigations and for design of computing systems which is this processor included in are discussed . " There is no processor and memory consumption , because the encryption is all happening down in the drive . These communication calls are not needed in a 1d decomposition in latitude because each latitude strip including the cyclic boundary is on processor . As it stands now , the only focus is on processors , with some passing concern for how nodes are linked up . Each simulation runs to completion on a single machine , and there is no processor to processor communication required ( other than between the Head and Compute nodes ) . The lower example illustrates a case where processors 0 and 2 own the particles but the COI is on processor 1 .