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CCD Clocking Schemes - Charge transfer through CCD shift registers occurs after integration to relocate accumulated charge information to the sense amplifier , which is physically separated from the parallel pixel array . So by virtue of the SMARTReverse amplifier , the two upper amplifiers within the amplifier box will reverse . Because this requires the readout amplifier to be optimized for larger pixels at high speeds , the read noise specification is necessarily increased . When voltage is applied to the common source line , the first sense amplifier to which current flows , continues to receive priority in current flow , and the operation of the other sense amplifiers is deferred . As a result , the current flowing through a single source node all flows to an individual sense amplifier , and no delay or difference occurs in operation start-up time of neighboring sense amplifier circuits . Incorporates the light sensitive charge coupled device ( CCD ) with or without cooling , head amplifier and cabling to transfer data to the camera control electronics ( DDE ) . A current sense amplifier is used by the computer in the tractor bridge to detect the 20 Hz pulse on the Blue circuit and then send J1939 communications messages on the Green and Brown circuits . Parasitic oscillation suppression circuits will be designed for integration into the output arms of the klystron , and a detailed layout drawing of the overall assembly will be prepared to assist in the fabrication and high power testing of the klystron in Phase II. Commercial Applications and Other Benefits as described by the awardee : A stable , high gain klystron amplifier should enable existing complex driver systems and associated pulsed helix and filament power supplies to be replaced by simple , low power solid state amplifiers in accelerators for High Energy Physics research . In DRAMs , however , as voltage decreases , signal ( data ) read from the memory cell ( * 2 ) to the sense amplifiers decreases , leading to a delay in the amplifying operation in the sense amplifier circuit , resulting in an overall decrease in DRAM operation speed .