<s> void rs6000_asm_output_dwarf_datarel ( FILE * file , int size , const char * label ) { fputs ( integer_asm_op ( size , FALSE ) , file ) ; assemble_name ( file , label ) ; fputs ( "-__gcc_unwind_dbase" , file ) ; } </s>

Output a symbol offset relative to the dbase for the current object . We use __gcc_unwind_dbase as an arbitrary base for dbase and assume signed offsets . __gcc_unwind_dbase is embedded in all executables/libraries through libgcc/config/rs6000/crtdbase.S .


<s> static bool aarch64_valid_floating_const ( machine_mode mode , rtx x ) { if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( ! ( mode == SFmode || mode == DFmode ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; return aarch64_float_const_representable_p ( x ) ; } </s>

Return true if X holds either a quarter-precision or floating-point +0.0 constant .


<s> bool fusion_p9_p ( rtx addis_reg , rtx addis_value , rtx dest , rtx src ) { rtx addr , mem , offset ; machine_mode mode = GET_MODE ( src ) ; if ( ! base_reg_operand ( addis_reg , GET_MODE ( addis_reg ) ) ) return false ; if ( ! fusion_gpr_addis ( addis_value , GET_MODE ( addis_value ) ) ) return false ; if ( GET_CODE ( src ) == FLOAT_EXTEND || GET_CODE ( src ) == ZERO_EXTEND ) src = XEXP ( src , 0 ) ; if ( fpr_reg_operand ( src , mode ) || int_reg_operand ( src , mode ) ) { if ( ! MEM_P ( dest ) ) return false ; mem = dest ; } else if ( MEM_P ( src ) ) { if ( ! fpr_reg_operand ( dest , mode ) && ! int_reg_operand ( dest , mode ) ) return false ; mem = src ; } else return false ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == PLUS ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , 0 ) ) ) return false ; return satisfies_constraint_I ( XEXP ( addr , 1 ) ) ; } else if ( GET_CODE ( addr ) == LO_SUM ) { if ( ! rtx_equal_p ( addis_reg , XEXP ( addr , 0 ) ) ) return false ; offset = XEXP ( addr , 1 ) ; if ( TARGET_XCOFF || ( TARGET_ELF && TARGET_POWERPC64 ) ) return small_toc_ref ( offset , GET_MODE ( offset ) ) ; else if ( TARGET_ELF && ! TARGET_POWERPC64 ) return CONSTANT_P ( offset ) ; } return false ; } </s>

Return true if the peephole2 can combine a load/store involving a combination of an addis instruction and the memory operation . This was added to the ISA 3.0 ( power9 ) hardware .


<s> bool function_instance :: could_trap_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( CP_READ_MEMORY | CP_WRITE_MEMORY ) ) return true ; return false ; } </s>

Return true if calls to the function could raise a signal .


<s> void R600InstrInfo :: clearFlag ( MachineInstr * MI , unsigned Operand , unsigned Flag ) const { unsigned TargetFlags = get ( MI -> getOpcode ( ) ) . TSFlags ; if ( HAS_NATIVE_OPERANDS ( TargetFlags ) ) { MachineOperand & FlagOp = getFlagOp ( MI , Operand , Flag ) ; FlagOp . setImm ( 0 ) ; } else { MachineOperand & FlagOp = getFlagOp ( MI ) ; unsigned InstFlags = FlagOp . getImm ( ) ; InstFlags &= ~ ( Flag << ( NUM_MO_FLAGS * Operand ) ) ; FlagOp . setImm ( InstFlags ) ; } } </s>

Clear the specified flag on the instruction .


<s> MachineInstr * SPUInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( Ops . size ( ) != 1 ) return 0 ; unsigned OpNum = Ops [ 0 ] ; unsigned Opc = MI -> getOpcode ( ) ; MachineInstr * NewMI = 0 ; switch ( Opc ) { case SPU :: ORv16i8 : case SPU :: ORv8i16 : case SPU :: ORv4i32 : case SPU :: ORv2i64 : case SPU :: ORr8 : case SPU :: ORr16 : case SPU :: ORr32 : case SPU :: ORr64 : case SPU :: ORf32 : case SPU :: ORf64 : if ( OpNum == 0 ) { unsigned InReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; if ( FrameIndex < SPUFrameInfo :: maxFrameOffset ( ) ) { MachineInstrBuilder MIB = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( SPU :: STQDr32 ) ) ; MIB . addReg ( InReg , getKillRegState ( isKill ) ) ; NewMI = addFrameReference ( MIB , FrameIndex ) ; } } else { unsigned OutReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( Opc ) ) ; MIB . addReg ( OutReg , RegState :: Define | getDeadRegState ( isDead ) ) ; Opc = ( FrameIndex < SPUFrameInfo :: maxFrameOffset ( ) ) ? SPU :: STQDr32 : SPU :: STQXr32 ; NewMI = addFrameReference ( MIB , FrameIndex ) ; break ; } } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> void rs6000_emit_popcount ( rtx dst , rtx src ) { machine_mode mode = GET_MODE ( dst ) ; rtx tmp1 , tmp2 ; if ( TARGET_POPCNTD ) { if ( mode == SImode ) emit_insn ( gen_popcntdsi2 ( dst , src ) ) ; else emit_insn ( gen_popcntddi2 ( dst , src ) ) ; return ; } tmp1 = gen_reg_rtx ( mode ) ; if ( mode == SImode ) { emit_insn ( gen_popcntbsi2 ( tmp1 , src ) ) ; tmp2 = expand_mult ( SImode , tmp1 , GEN_INT ( 0x01010101 ) , NULL_RTX , 0 ) ; tmp2 = force_reg ( SImode , tmp2 ) ; emit_insn ( gen_lshrsi3 ( dst , tmp2 , GEN_INT ( 24 ) ) ) ; } else { emit_insn ( gen_popcntbdi2 ( tmp1 , src ) ) ; tmp2 = expand_mult ( DImode , tmp1 , GEN_INT ( ( HOST_WIDE_INT ) 0x01010101 << 32 | 0x01010101 ) , NULL_RTX , 0 ) ; tmp2 = force_reg ( DImode , tmp2 ) ; emit_insn ( gen_lshrdi3 ( dst , tmp2 , GEN_INT ( 56 ) ) ) ; } } </s>

Emit popcount intrinsic on TARGET_POPCNTB ( Power5 ) and TARGET_POPCNTD ( Power7 ) targets . DST is the target , and SRC is the argument operand .


<s> bool Z80PassConfig :: addInstSelector ( ) { addPass ( createZ80ISelDAG ( getZ80TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> SDValue MSP430TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_MSP430 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"SystemZ Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = getDataLayout ( ) . getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; if ( MMI ) { MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; if ( MAI -> doesSupportExceptionHandling ( ) ) { for ( const Function * Personality : MMI -> getPersonalities ( ) ) { if ( Personality ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( Personality , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( Personality ) , true ) ; } } } MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? Align ( 8 ) : Align ( 4 ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static rtx rs6000_legitimize_tls_address_aix ( rtx addr , enum tls_model model ) { rtx sym , mem , tocref , tlsreg , tmpreg , dest , tlsaddr ; const char * name ; char * tlsname ; name = XSTR ( addr , 0 ) ; if ( name [ strlen ( name ) - 1 ] != ']' && ( TREE_PUBLIC ( SYMBOL_REF_DECL ( addr ) ) || bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ) ) { tlsname = XALLOCAVEC ( char , strlen ( name ) + 4 ) ; strcpy ( tlsname , name ) ; strcat ( tlsname , bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ? "[UL]" : "[TL]" ) ; tlsaddr = copy_rtx ( addr ) ; XSTR ( tlsaddr , 0 ) = ggc_strdup ( tlsname ) ; } else tlsaddr = addr ; sym = force_const_mem ( GET_MODE ( tlsaddr ) , tlsaddr ) ; if ( constant_pool_expr_p ( XEXP ( sym , 0 ) ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( XEXP ( sym , 0 ) ) , Pmode ) ) { tocref = create_TOC_reference ( XEXP ( sym , 0 ) , NULL_RTX ) ; mem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( mem , get_TOC_alias_set ( ) ) ; } else return sym ; if ( model == TLS_MODEL_GLOBAL_DYNAMIC || model == TLS_MODEL_LOCAL_DYNAMIC ) { name = XSTR ( XVECEXP ( XEXP ( mem , 0 ) , 0 , 0 ) , 0 ) ; tlsname = XALLOCAVEC ( char , strlen ( name ) + 1 ) ; strcpy ( tlsname , "*LCM" ) ; strcat ( tlsname , name + 3 ) ; rtx modaddr = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( tlsname ) ) ; SYMBOL_REF_FLAGS ( modaddr ) |= SYMBOL_FLAG_LOCAL ; tocref = create_TOC_reference ( modaddr , NULL_RTX ) ; rtx modmem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( modmem , get_TOC_alias_set ( ) ) ; rtx modreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( modreg , modmem ) ) ; tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmpreg , mem ) ) ; dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_32BIT ) emit_insn ( gen_tls_get_addrsi ( dest , modreg , tmpreg ) ) ; else emit_insn ( gen_tls_get_addrdi ( dest , modreg , tmpreg ) ) ; return dest ; } else if ( TARGET_32BIT ) { tlsreg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_tls_get_tpointer ( tlsreg ) ) ; } else tlsreg = gen_rtx_REG ( DImode , 13 ) ; tmpreg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmpreg , mem ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , gen_rtx_MINUS ( Pmode , addr , tlsreg ) ) ; dest = force_reg ( Pmode , gen_rtx_PLUS ( Pmode , tmpreg , tlsreg ) ) ; return dest ; } </s>


<s> unsigned push ( unsigned Opc , MVT Ty , std :: vector < OpRef > && Ops ) { NodeTemplate Res ; Res . Opc = Opc ; Res . Ty = Ty ; Res . Ops = Ops ; return push ( Res ) ; } </s>


<s> void MipsPassConfig :: addPreRegAlloc ( ) { addPass ( createMipsOptimizePICCallPass ( ) ) ; if ( getMipsSubtarget ( ) . isCheri ( ) ) { addPass ( createCheriAddressingModeFolder ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: Level :: None ) addPass ( & DeadMachineInstructionElimID ) ; addPass ( createCheri128FailHardPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
void
ARMConstantIslands
::
verify
(
)
{
assert
(
std
::
is_sorted
(
MF
->
begin
(
)
,
MF
->
end
(
)
,
[
this
]
(
const
MachineBasicBlock
&
LHS
,
const
MachineBasicBlock
&
RHS
)
{
return
BBInfo
[
LHS
.
getNumber
(
)
]
.
postOffset
(
)
<
BBInfo
[
RHS
.
getNumber
(
)
]
.
postOffset
(
)
;
}
)
)
;
DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
unsigned
i
=
0
,
e
=
CPUsers
.
size
(
)
;
i
!=
e
;
++
i
)
{
CPUser
&
U
=
CPUsers
[
i
]
;
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
"Verifying "
" CP users.\n"
0
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> static bool use_toc_relative_ref ( rtx sym , machine_mode mode ) { return ( ( constant_pool_expr_p ( sym ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( sym ) , get_pool_mode ( sym ) ) ) || ( TARGET_CMODEL == CMODEL_MEDIUM && SYMBOL_REF_LOCAL_P ( sym ) && GET_MODE_SIZE ( mode ) <= POWERPC64_TOC_POINTER_ALIGNMENT ) ) ; } </s>

Return true iff the given SYMBOL_REF refers to a constant pool entry that we have put in the TOC , or for cmodel=medium , if the SYMBOL_REF can be addressed relative to the toc pointer .


<s> void output_profile_hook ( int labelno ATTRIBUTE_UNUSED ) { if ( TARGET_PROFILE_KERNEL ) return ; if ( DEFAULT_ABI == ABI_AIX ) { if ( NO_PROFILE_COUNTERS ) emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , 0 , VOIDmode , 0 ) ; else { char buf [ 30 ] ; const char * label_name ; rtx fun ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LP" , labelno ) ; label_name = ( * targetm . strip_name_encoding ) ( ggc_strdup ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , 0 , VOIDmode , 1 , fun , Pmode ) ; } } else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LINK_REGISTER_REGNUM ; current_function_uses_pic_offset_table = 1 ; if ( MACHOPIC_INDIRECT && current_function_uses_pic_offset_table ) caller_addr_regno = 0 ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , mcount_name ) , 0 , VOIDmode , 1 , gen_rtx_REG ( Pmode , caller_addr_regno ) , Pmode ) ; } } </s>


<s> static void mt_emit_save_regs ( enum save_direction direction , struct mt_frame_info info ) { rtx base_reg ; int regno ; int reg_mask = info . reg_mask & ~ ( FP_MASK | LINK_MASK ) ; int offset = info . total_size ; int stack_offset = info . total_size ; if ( ! info . save_fp && ! info . save_lr && ! reg_mask ) return ; if ( CONST_OK_FOR_LETTER_P ( offset , 'O' ) ) base_reg = stack_pointer_rtx ; else { base_reg = gen_rtx_REG ( SImode , GPR_R9 ) ; offset = 0 ; } if ( info . save_fp ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; } if ( info . save_lr ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , GPR_LINK ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( offset ) ) ) , stack_offset ) ; } for ( regno = GPR_R0 ; regno <= GPR_LAST ; regno ++ ) { if ( ( reg_mask & ( 1 << regno ) ) != 0 ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , regno ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( offset ) ) ) , stack_offset ) ; } } } </s>

Emit code to save registers in the prologue and restore register in epilogue .


<s> unsigned MipsMCCodeEmitter :: getBranchTarget26OpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> 1 ; return 0 ; } </s>

getBranchTarget26OpValueMM - Return binary encoding of the branch target operand .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function & F = MF . getFunction ( ) ; if ( ! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( ! Subtarget . isUnalignedMem16Slow ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 && Subtarget . hasAVX ( ) ) { return MVT :: v32i8 ; } if ( Subtarget . hasSSE2 ( ) ) return MVT :: v16i8 ; if ( Subtarget . hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ( ! IsMemset || ZeroMemset ) && ! MemcpyStrSrc && Size >= 8 && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget . is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


"Trying to fill a register in naked function "

Load the specified register of the given register class from the specified stack frame index .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createTOYELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle , Is64Bit ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


Called once at the start of IRA , by ADJUST_REG_ALLOC_ORDER .


<s> virtual bool doInitialization ( Module & ) { if ( ! StatsFile . empty ( ) && ! AppendStatsFile && sys :: fs :: exists ( StatsFile ) ) { sys :: fs :: remove ( StatsFile . c_str ( ) ) ; } return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> TargetPassConfig * VideocoreTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new VideocorePassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void ix86_expand_floorceildf_32 ( rtx operand0 , rtx operand1 , bool do_floor ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , TWO52 , tmp , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( xa , xa , res , mask ) ; one = force_reg ( mode , const_double_from_real_value ( do_floor ? dconst1 : dconstm1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , MINUS , xa , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; emit_move_insn ( res , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing into OPERAND0 .


<s>
const
MCExpr
*
ARMElfTargetObjectFile
::
getTTypeGlobalReference
(
const
GlobalValue
*
GV
,
unsigned
Encoding
,
const
TargetMachine
&
TM
,
MachineModuleInfo
*
MMI
,
MCStreamer
&
Streamer
)
const
{
if
(
TM
.
getMCAsmInfo
(
)
->
getExceptionHandlingType
(
)
!=
ExceptionHandling
::
ARM
)
return
TargetLoweringObjectFileELF
::
getTTypeGlobalReference
(
GV
,
Encoding
,
TM
,
MMI
,
Streamer
)
;
assert
(
Encoding
==
DW_EH_PE_absptr
&&
"Can handle absptr encoding only"
)
;
return
MCSymbolRefExpr
::
create
(
TM
.
getSymbol
(
GV
)
,
MCSymbolRefExpr
::
VK_ARM_TARGET2
,
getContext
(
)
)
;
}
</s>

The mach-o version of this method defaults to returning a stub reference .

ARM
ARM
ARM
"Can handle absptr encoding only"
ARM


<s>
MachineInstr
*
PPCInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMI
)
return
TargetInstrInfoImpl
::
commuteInstruction
(
MI
,
NewMI
)
;
if
(
MI
->
getOperand
(
3
)
.
getImm
(
)
!=
0
)
return
0
;
unsigned
Reg0
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Reg1
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
Reg2
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
bool
Reg1IsKill
=
MI
->
getOperand
(
1
)
.
isKill
(
)
;
bool
Reg2IsKill
=
MI
->
getOperand
(
2
)
.
isKill
(
)
;
bool
ChangeReg0
=
false
;
if
(
Reg0
==
Reg1
)
{
assert
(
MI
->
getDesc
(
)
.
getOperandConstraint
(
0
,
TOI
::
TIED_TO
)
&&
"Expecting a two-address instruction!"
)
;
Reg2IsKill
=
false
;
ChangeReg0
=
true
;
}
unsigned
MB
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
ME
=
MI
->
getOperand
(
5
)
.
getImm
(
)
;
if
(
NewMI
)
{
unsigned
Reg0
=
ChangeReg0
Reg2
:
MI
->
getOperand
(
0
)
.
getReg
(
)
;
bool
Reg0IsDead
=
MI
->
getOperand
(
0
)
.
isDead
(
)
;
return
BuildMI
(
MF
,
MI
->
getDebugLoc
(
)
,
MI
->
getDesc
(
)
)
.
addReg
(
Reg0
,
RegState
::
Define
|
getDeadRegState
(
Reg0IsDead
)
)
.
addReg
(
Reg2
,
getKillRegState
(
Reg2IsKill
)
)
.
addReg
(
Reg1
,
getKillRegState
(
Reg1IsKill
)
)
.
addImm
(
(
ME
+
1
)
&
31
)
.
addImm
(
(
MB
1
)
&
31
)
;
}
if
(
ChangeReg0
)
MI
->
getOperand
(
0
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setReg
(
Reg1
)
;
MI
->
getOperand
(
1
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setIsKill
(
Reg1IsKill
)
;
MI
->
getOperand
(
1
)
.
setIsKill
(
Reg2IsKill
)
;
MI
->
getOperand
(
4
)
.
setImm
(
(
ME
+
1
)
&
31
)
;
MI
->
getOperand
(
5
)
.
setImm
(
(
MB
1
)
&
31
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


<s> int ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { if ( MI -> isCopyLike ( ) || MI -> isInsertSubreg ( ) || MI -> isRegSequence ( ) || MI -> isImplicitDef ( ) ) return 1 ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return 1 ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ; if ( PredCost && MCID . hasImplicitDefOfPhysReg ( ARM :: CPSR ) ) * PredCost = 1 ; if ( UOps ) return ItinData -> getStageLatency ( Class ) ; return getNumMicroOps ( ItinData , MI ) ; } </s>

Compute the instruction latency of a given instruction .


<s>
SDNode
*
rvexDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DebugLoc
dl
=
Node
->
getDebugLoc
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
EVT
NodeTy
=
Node
->
getValueType
(
0
)
;
unsigned
MultOpc
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
MULHS
:
case
ISD
::
MULHU
:
{
MultOpc
=
(
Opcode
==
ISD
::
MULHU
rvex
::
MULTu
:
rvex
::
MULT
)
;
return
SelectMULT
(
Node
,
MultOpc
,
dl
,
NodeTy
,
false
,
true
)
.
second
;
}
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
getGlobalBaseReg
(
)
;
case
ISD
::
Constant
:
{
const
ConstantSDNode
*
CN
=
dyn_cast
<
ConstantSDNode
>
(
Node
)
;
unsigned
Size
=
CN
->
getValueSizeInBits
(
0
)
;
if
(
Size
==
32
)
break
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

rvex
rvex
"Selecting: "
"\n"
"== "
"\n"
0
ISD::MULHS
ISD::MULHU
ISD::MULHU
rvex::MULTu
rvex::MULT
ISD::GLOBAL_OFFSET_TABLE
ISD::Constant
0
32
"=> "
"\n"


<s> static bool arc_vector_mode_supported_p ( machine_mode mode ) { if ( ! TARGET_SIMD_SET ) return false ; if ( ( mode == V4SImode ) || ( mode == V8HImode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> enum tls_model tls_symbolic_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) != SYMBOL_REF ) return TLS_MODEL_NONE ; return SYMBOL_REF_TLS_MODEL ( op ) ; } </s>

Return the TLS type for TLS symbols , 0 for otherwise .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: GHC ) return CSR_AArch64_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> Optional < DestSourcePair > ARMBaseInstrInfo :: isAddImmediate ( const MachineInstr & MI , int64_t & Offset ) const { int Sign = 1 ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == ARM :: SUBri ) Sign = - 1 ; else if ( Opcode != ARM :: ADDri ) return None ; if ( ! MI . getOperand ( 0 ) . isReg ( ) || ! MI . getOperand ( 1 ) . isReg ( ) || ! MI . getOperand ( 2 ) . isImm ( ) ) return None ; Offset = MI . getOperand ( 2 ) . getImm ( ) * Sign ; return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; } </s>

If the specific machine instruction is an instruction that adds an immediate value and a register , and stores the result in the given register Reg , return a pair of the source register and the offset which has been added .


<s> void VEAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case TargetOpcode :: DBG_VALUE : return ; case VE :: GETGOT : lowerGETGOTAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; case VE :: GETFUNPLT : lowerGETFunPLTAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; LowerVEMachineInstrToMCInst ( & * I , TmpInst , * this ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

Targets should implement this to emit instructions .


<s> void NVPTXInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool aarch64_return_in_msb ( const_tree valtype ) { machine_mode dummy_mode ; int dummy_int ; if ( ! BYTES_BIG_ENDIAN ) return false ; if ( ! aarch64_composite_type_p ( valtype , TYPE_MODE ( valtype ) ) || int_size_in_bytes ( valtype ) <= 0 || int_size_in_bytes ( valtype ) > 16 ) return false ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( valtype ) , valtype , & dummy_mode , & dummy_int , NULL , false ) ) return false ; pure_scalable_type_info pst_info ; if ( pst_info . analyze_registers ( valtype ) ) return false ; return true ; } </s>

Return TRUE if VALTYPE is padded to its least significant bits .


<s> static bool h8300_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . For the h8300 , if frame pointer elimination is being done , we would like to convert ap and rp into sp , not fp . All other eliminations are valid .


<s> bool X86FastISel :: isTypeLegal ( Type * Ty , MVT & VT , bool AllowI1 ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f64 && ! X86ScalarSSEf64 ) return false ; if ( VT == MVT :: f32 && ! X86ScalarSSEf32 ) return false ; if ( VT == MVT :: f80 ) return false ; return ( AllowI1 && VT == MVT :: i1 ) || TLI . isTypeLegal ( VT ) ; } </s>


<s> static int n_dregs_to_save ( bool is_inthandler , bool consecutive ) { int count = 0 ; unsigned i ; for ( i = REG_R7 + 1 ; i -- != REG_R0 ; ) { if ( must_save_p ( is_inthandler , i ) ) count ++ ; else if ( consecutive ) return count ; } return count ; } </s>

Compute the number of DREGS to save with a push_multiple operation . This could include registers that are n't modified in the function , since push_multiple only takes a range of registers . If IS_INTHANDLER , then everything that is live must be saved , even if normally call-clobbered .


<s> bool TPCExpandHWRegCopies :: runOnMachineFunction ( MachineFunction & Func ) { if ( skipFunction ( Func . getFunction ( ) ) ) return false ; if ( ! EnableTPCExpandHWRegCopies ) return false ; MF = & Func ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; NumReplaced = 0 ; MachineBasicBlock * MBB ; MachineInstrBuilder MIB ; typedef enum { none , zpreg } TCopyKind ; for ( MachineFunction :: iterator MBBI = MF -> begin ( ) , MBBE = MF -> end ( ) ; MBBI != MBBE ; ++ MBBI ) { MBB = & * MBBI ; for ( MachineBasicBlock :: iterator mi = MBB -> begin ( ) , me = MBB -> end ( ) ; mi != me ; ) { MachineBasicBlock :: iterator nmi = std :: next ( mi ) ; MachineInstr * MI = & * mi ; auto opc = MI -> getOpcode ( ) ; if ( opc == TargetOpcode :: COPY ) { MachineOperand des = MI -> getOperand ( 0 ) ; if ( des . isReg ( ) ) { Register destreg = des . getReg ( ) ; TCopyKind CopyKind = TCopyKind ( none ) ; if ( ! destreg . isPhysical ( ) ) { const TargetRegisterClass * RC ; const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; RC = MRI . getRegClass ( destreg ) ; } } } mi = nmi ; } } return NumReplaced > 0 ; } </s>

runOnMachineFunction - Emit the function body .


<s> Optional < MCFixupKind > RISCVAsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - 1u ) ; if ( Type != - 1u ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return None ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static bool isSafeToMove ( const MachineInstr * Def , const MachineInstr * Insert , AliasAnalysis & AA , const MachineRegisterInfo & MRI ) { assert ( Def -> getParent ( ) == Insert -> getParent ( ) ) ; if ( Def -> getOpcode ( ) == WebAssembly :: CATCH || Def -> getOpcode ( ) == WebAssembly :: EXTRACT_EXCEPTION_I32 ) { const MachineBasicBlock * MBB = Def -> getParent ( ) ; auto NextI = std :: next ( MachineBasicBlock :: const_iterator ( Def ) ) ; for ( auto E = MBB -> end ( ) ; NextI != E && NextI -> isDebugInstr ( ) ; ++ NextI ) ; if ( NextI != Insert ) return false ; } SmallVector < unsigned , 4 > MutableRegisters ; for ( const MachineOperand & MO : Def -> operands ( ) ) { if ( ! MO . isReg ( ) || MO . isUndef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( MO . isDead ( ) && Insert -> definesRegister ( Reg ) && ! Insert -> readsRegister ( Reg ) ) continue ; if ( Register :: isPhysicalRegister ( Reg ) ) { if ( Reg == WebAssembly :: ARGUMENTS ) continue ; if ( ! MRI . isPhysRegModified ( Reg ) ) continue ; return false ; } if ( ! MO . isDef ( ) && ! MRI . hasOneDef ( Reg ) ) MutableRegisters . push_back ( Reg ) ; } bool Read = false , Write = false , Effects = false , StackPointer = false ; query ( * Def , AA , Read , Write , Effects , StackPointer ) ; bool HasMutableRegisters = ! MutableRegisters . empty ( ) ; if ( ! Read && ! Write && ! Effects && ! StackPointer && ! HasMutableRegisters ) return true ; MachineBasicBlock :: const_iterator D ( Def ) , I ( Insert ) ; for ( -- I ; I != D ; -- I ) { bool InterveningRead = false ; bool InterveningWrite = false ; bool InterveningEffects = false ; bool InterveningStackPointer = false ; query ( * I , AA , InterveningRead , InterveningWrite , InterveningEffects , InterveningStackPointer ) ; if ( Effects && InterveningEffects ) return false ; if ( Read && InterveningWrite ) return false ; if ( Write && ( InterveningRead || InterveningWrite ) ) return false ; if ( StackPointer && InterveningStackPointer ) return false ; for ( unsigned Reg : MutableRegisters ) for ( const MachineOperand & MO : I -> operands ( ) ) if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == Reg ) return false ; } return true ; } </s>

Return true if it is safe to move this instruction .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; X86TargetLowering * X86Lowering = ( X86TargetLowering * ) getTargetLowering ( ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> bool SystemZInstrInfo :: isStackSlotCopy ( const MachineInstr * MI , int & DestFrameIndex , int & SrcFrameIndex ) const { const MachineFrameInfo * MFI = MI -> getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; if ( MI -> getOpcode ( ) != SystemZ :: MVC || ! MI -> getOperand ( 0 ) . isFI ( ) || MI -> getOperand ( 1 ) . getImm ( ) != 0 || ! MI -> getOperand ( 3 ) . isFI ( ) || MI -> getOperand ( 4 ) . getImm ( ) != 0 ) return false ; int64_t Length = MI -> getOperand ( 2 ) . getImm ( ) ; unsigned FI1 = MI -> getOperand ( 0 ) . getIndex ( ) ; unsigned FI2 = MI -> getOperand ( 3 ) . getIndex ( ) ; if ( MFI -> getObjectSize ( FI1 ) != Length || MFI -> getObjectSize ( FI2 ) != Length ) return false ; DestFrameIndex = FI1 ; SrcFrameIndex = FI2 ; return true ; } </s>

Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect .


<s> void nios2_adjust_call_address ( rtx * call_op , rtx reg ) { if ( MEM_P ( * call_op ) ) call_op = & XEXP ( * call_op , 0 ) ; rtx addr = * call_op ; if ( flag_pic && CONSTANT_P ( addr ) ) { rtx tmp = reg ? reg : NULL_RTX ; if ( ! reg ) reg = gen_reg_rtx ( Pmode ) ; addr = nios2_load_pic_address ( addr , UNSPEC_PIC_CALL_SYM , tmp ) ; emit_insn ( gen_rtx_SET ( reg , addr ) ) ; * call_op = reg ; } } </s>

The function with address * ADDR is being called . If the address needs to be loaded from the GOT , emit the instruction to do so and update * ADDR to point to the rtx for the loaded value . If REG ! = NULL_RTX , it is used as the target/scratch register in the GOT address calculation .


<s> rtx mep_find_base_term ( rtx x ) { rtx base , term ; int unspec ; if ( GET_CODE ( x ) != PLUS ) return x ; base = XEXP ( x , 0 ) ; term = XEXP ( x , 1 ) ; if ( has_hard_reg_initial_val ( Pmode , TP_REGNO ) && base == mep_tp_rtx ( ) ) unspec = UNS_TPREL ; else if ( has_hard_reg_initial_val ( Pmode , GP_REGNO ) && base == mep_gp_rtx ( ) ) unspec = UNS_GPREL ; else return x ; if ( GET_CODE ( term ) != CONST ) return x ; term = XEXP ( term , 0 ) ; if ( GET_CODE ( term ) != UNSPEC || XINT ( term , 1 ) != unspec ) return x ; return XVECEXP ( term , 0 , 0 ) ; } </s>

If X is a machine specific address ( i.e . a symbol or label being referenced as a displacement from the GOT implemented using an UNSPEC ) , then return the base term . Otherwise return X .


<s> virtual const PIC16InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool GCNTTIImpl :: isSourceOfDivergence ( const Value * V ) const { if ( const Argument * A = dyn_cast < Argument > ( V ) ) return ! isArgPassedInSGPR ( A ) ; if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == ST -> getAMDGPUAS ( ) . PRIVATE_ADDRESS || Load -> getPointerAddressSpace ( ) == ST -> getAMDGPUAS ( ) . FLAT_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) return AMDGPU :: isIntrinsicSourceOfDivergence ( Intrinsic -> getIntrinsicID ( ) ) ; if ( isa < CallInst > ( V ) || isa < InvokeInst > ( V ) ) return true ; return false ; } </s>

Returns whether V is a source of divergence .

AMDGPU AMDGPU AMDGPU AMDGPU::isIntrinsicSourceOfDivergence


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static int function_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( ( arg . mode == BLKmode || GET_MODE_CLASS ( arg . mode ) != MODE_COMPLEX_INT || GET_MODE_CLASS ( arg . mode ) != MODE_COMPLEX_FLOAT ) && cum -> arg_words < MAX_ARGS_IN_REGISTERS ) { int words = ( ( arg . promoted_size_in_bytes ( ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; if ( words + cum -> arg_words <= MAX_ARGS_IN_REGISTERS ) return 0 ; return ( MAX_ARGS_IN_REGISTERS - cum -> arg_words ) * UNITS_PER_WORD ; } else if ( arg . mode == DImode && cum -> arg_words == MAX_ARGS_IN_REGISTERS - 1 ) return UNITS_PER_WORD ; return 0 ; } </s>

Return number of bytes of argument to put in registers .


<s> void Cpu0MCCodeEmitter :: EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; AU . addRequired < DwarfWriter > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> RegisterRef RegisterAggr :: normalize ( RegisterRef RR ) const { RegisterId SuperReg = RR . Reg ; while ( true ) { MCSuperRegIterator SR ( SuperReg , & TRI , false ) ; if ( ! SR . isValid ( ) ) break ; SuperReg = * SR ; } const TargetRegisterClass & RC = * TRI . getMinimalPhysRegClass ( RR . Reg ) ; LaneBitmask Common = RR . Mask & RC . LaneMask ; uint32_t Sub = TRI . getSubRegIndex ( SuperReg , RR . Reg ) ; LaneBitmask SuperMask = TRI . composeSubRegIndexLaneMask ( Sub , Common ) ; return RegisterRef ( SuperReg , SuperMask ) ; } </s>


<s> static bool riscv_is_eh_return_data_register ( unsigned int regno ) { unsigned int i , regnum ; if ( ! crtl -> calls_eh_return ) return false ; for ( i = 0 ; ( regnum = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) if ( regno == regnum ) { return true ; } return false ; } </s>

Return TRUE if provided REGNO is eh return data register .


"invalid instruction size for rip-relative lea"

Given an instruction with a memory operand that could require relocation , returns the offset within the instruction of that relocation .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
override
{
unsigned
Size
=
getFixupKindSize
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
(
Size
==
0
||
isIntN
(
Size
*
8
+
1
,
Value
)
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> std :: pair < unsigned , const TargetRegisterClass * > MipsTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , Mips :: CPURegsRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , Mips :: FGR32RegisterClass ) ; if ( VT == MVT :: f64 ) if ( ( ! Subtarget -> isSingleFloat ( ) ) && ( ! Subtarget -> isFP64bit ( ) ) ) return std :: make_pair ( 0U , Mips :: AFGR64RegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> int arm_attr_length_pop_multi ( rtx * operands , bool return_pc , bool write_back_p ) { if ( TARGET_ARM ) return 4 ; if ( TARGET_THUMB1 ) return 2 ; rtx parallel_op = operands [ 0 ] ; unsigned indx = XVECLEN ( parallel_op , 0 ) - 1 ; unsigned regno = REGNO ( operands [ 1 ] ) ; unsigned first_indx = 0 ; first_indx += return_pc ? 1 : 0 ; first_indx += write_back_p ? 1 : 0 ; bool pop_p = ( regno == SP_REGNUM && write_back_p ) ; bool ldm_p = ! pop_p ; if ( ldm_p && REGNO_REG_CLASS ( regno ) == HI_REGS ) return 4 ; for ( ; indx >= first_indx ; indx -- ) { regno = REGNO ( XEXP ( XVECEXP ( parallel_op , 0 , indx ) , 0 ) ) ; if ( REGNO_REG_CLASS ( regno ) == HI_REGS && ( regno != PC_REGNUM || ldm_p ) ) return 4 ; } return 2 ; } </s>

Compute the attribute `` length '' of insn . Currently , this function is used for `` * load_multiple_with_writeback '' , `` * pop_multiple_with_return '' and `` * pop_multiple_with_writeback_and_return '' . OPERANDS is the toplevel PARALLEL rtx , RETURN_PC is true if OPERANDS contains return insn . WRITE_BACK_P is true if OPERANDS contains insn which explicit updates base register .


"TVM DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Type Rewriter"
;
}
</s>


<s> bool RISCVFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return isInt < 12 > ( MFI -> getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> static bool ix86_lea_outperforms ( rtx_insn * insn , unsigned int regno0 , unsigned int regno1 , unsigned int regno2 , int split_cost , bool has_scale ) { int dist_define , dist_use ; if ( ! TARGET_BONNELL ) { if ( has_scale ) return true ; if ( split_cost < 1 ) return false ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; return true ; } struct recog_data_d recog_data_save = recog_data ; dist_define = distance_non_agu_define ( regno1 , regno2 , insn ) ; dist_use = distance_agu_use ( regno0 , insn ) ; recog_data = recog_data_save ; if ( dist_define < 0 || dist_define >= LEA_MAX_STALL ) { if ( dist_use < 0 && split_cost == 0 ) return TARGET_64BIT || IX86_LEA_PRIORITY ; else return true ; } dist_define += split_cost + IX86_LEA_PRIORITY ; if ( dist_use < 0 ) return dist_define > LEA_MAX_STALL ; return dist_define >= dist_use ; } </s>

Return true if usage of lea INSN has performance advantage over a sequence of instructions . Instructions sequence has SPLIT_COST cycles higher latency than lea latency .


<s> RegisterSet & remove ( const RegisterSet & Rs ) { return static_cast < RegisterSet & > ( BitVector :: reset ( Rs ) ) ; } </s>

remove - Remove the specified key/value pair from the map , but do not erase it .


<s> unsigned getFlatAddressSpace ( ) const { return AddressSpace :: ADDRESS_SPACE_GENERIC ; } </s>

Returns the address space ID for a target 's 'flat ' address space .


<s> static void nios2_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ATTRIBUTE_UNUSED , struct gcc_options * opts_set ATTRIBUTE_UNUSED ) { unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( nios2_fpu_insn ) ; i ++ ) ptr -> saved_fpu_custom_code [ i ] = N2FPU_N ( i ) ; memcpy ( ptr -> saved_custom_code_status , custom_code_status , sizeof ( custom_code_status ) ) ; memcpy ( ptr -> saved_custom_code_index , custom_code_index , sizeof ( custom_code_index ) ) ; } </s>


<s> void arm_emit_fp16_const ( rtx c ) { long bits ; bits = real_to_target ( NULL , CONST_DOUBLE_REAL_VALUE ( c ) , HFmode ) ; if ( WORDS_BIG_ENDIAN ) assemble_zeros ( 2 ) ; assemble_integer ( GEN_INT ( bits ) , 2 , BITS_PER_WORD , 1 ) ; if ( ! WORDS_BIG_ENDIAN ) assemble_zeros ( 2 ) ; } </s>

Emit a fp16 constant appropriately padded to occupy a 4-byte word . HFmode constant pool entries are actually loaded with ldr .


<s> static void mips_avoid_hazard ( rtx after , rtx insn , int * hilo_delay , rtx * delayed_reg , rtx lo_reg ) { rtx pattern , set ; int nops , ninsns ; if ( ! INSN_P ( insn ) ) return ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == ASM_INPUT || asm_noperands ( pattern ) >= 0 ) cfun -> machine -> all_noreorder_p = false ; ninsns = get_attr_length ( insn ) / 4 ; if ( ninsns == 0 ) return ; if ( * hilo_delay < 2 && reg_set_p ( lo_reg , pattern ) ) nops = 2 - * hilo_delay ; else if ( * delayed_reg != 0 && reg_referenced_p ( * delayed_reg , pattern ) ) nops = 1 ; else nops = 0 ; * hilo_delay += nops ; while ( nops -- > 0 ) emit_insn_after ( gen_hazard_nop ( ) , after ) ; * hilo_delay += ninsns ; * delayed_reg = 0 ; if ( INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_HILO : * hilo_delay = 0 ; break ; case HAZARD_DELAY : set = single_set ( insn ) ; gcc_assert ( set != 0 ) ; * delayed_reg = SET_DEST ( set ) ; break ; } } </s>

Subroutine of mips_reorg . If there is a hazard between INSN and a previous instruction , avoid it by inserting nops after instruction AFTER . * DELAYED_REG and * HILO_DELAY describe the hazards that apply at this point . If * DELAYED_REG is non-null , INSN must wait a cycle before using the value of that register . * HILO_DELAY counts the number of instructions since the last hilo hazard ( that is , the number of instructions since the last mflo or mfhi ) . After inserting nops for INSN , update * DELAYED_REG and * HILO_DELAY for the next instruction . LO_REG is an rtx for the LO register , used in dependence checking .


"Callee saved registers requested for unknown architecture "


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
*
MIa
,
MachineInstr
*
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int
OffsetA
=
0
,
OffsetB
=
0
;
int
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
&&
MIa
->
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
&&
MIb
->
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
->
hasUnmodeledSideEffects
(
)
||
MIb
->
hasUnmodeledSideEffects
(
)
||
MIa
->
hasOrderedMemoryRef
(
)
||
MIb
->
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> MCSection * X86WindowsTargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( Kind . isMergeableConst ( ) && C ) { const unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_LNK_COMDAT ; std :: string COMDATSymName ; if ( Kind . isMergeableConst4 ( ) || Kind . isMergeableConst8 ( ) ) COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; else if ( Kind . isMergeableConst16 ( ) ) COMDATSymName = "__xmm@" + scalarConstantToHexString ( C ) ; if ( ! COMDATSymName . empty ( ) ) return getContext ( ) . getCOFFSection ( ".rdata" , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } return TargetLoweringObjectFile :: getSectionForConstant ( Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s>
bool
X86AsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
AsmVariant
,
ExtraCode
,
O
)
;
case
'a'
:
switch
(
MO
.
getType
(
)
)
{
default
:
return
true
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
false
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
*
this
,
MO
,
O
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
"(%rip)"
;
return
false
;
case
MachineOperand
::
MO_Register
:
O
<<
'('
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
O
<<
')'
;
return
false
;
}
case
'c'
:
switch
(
MO
.
getType
(
)
)
{
default
:
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
*
this
,
MO
,
O
)
;
break
;
}
return
false
;
case
'A'
:
if
(
MO
.
isReg
(
)
)
{
O
<<
'*'
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
}
return
true
;
case
'b'
:
case
'h'
:
case
'w'
:
case
'k'
:
case
'q'
:
if
(
MO
.
isReg
(
)
)
return
printAsmMRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
case
'P'
:
printPCRelImm
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
case
'n'
:
if
(
MO
.
isImm
(
)
)
{
O
<<
MO
.
getImm
(
)
;
return
false
;
}
O
<<
'-'
;
}
}
printOperand
(
*
this
,
MI
,
OpNo
,
O
,
0
,
AsmVariant
)
;
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


Implement TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P - return TRUE if MODE is HFmode , and punt to the generic implementation otherwise .


<s> void sparc_va_start ( tree valist , rtx nextarg ) { nextarg = expand_builtin_saveregs ( ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>

Implement ` va_start ' for varargs and stdarg .


<s> void emitWeakReference ( MCSymbol * Alias , const MCSymbol * Symbol ) override { } </s>

Emit an weak reference from Alias to Symbol .


<s> static void nds32_relax_group ( void ) { rtx_insn * insn ; compute_bb_for_insn ( ) ; df_chain_add_problem ( DF_DU_CHAIN | DF_UD_CHAIN ) ; df_insn_rescan_all ( ) ; df_analyze ( ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; calculate_dominance_info ( CDI_DOMINATORS ) ; insn = get_insns ( ) ; gcc_assert ( NOTE_P ( insn ) ) ; for ( insn = next_active_insn ( insn ) ; insn ; insn = next_active_insn ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_sethi && nds32_symbolic_operand ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) , SImode ) ) nds32_group_insns ( insn ) ; } } df_insn_rescan_all ( ) ; df_finish_pass ( false ) ; free_dominance_info ( CDI_DOMINATORS ) ; } </s>

Group the relax candidate instructions for linker .


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilderBase & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; CallInst * CI = Builder . CreateCall ( Strex , { Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; CI -> addParamAttr ( 1 , Attribute :: get ( M -> getContext ( ) , Attribute :: ElementType , Val -> getType ( ) ) ) ; return CI ; } </s>

Perform a store-conditional operation to Addr .


<s>
unsigned
getReg
(
)
const
{
assert
(
(
Kind
==
k_Register
||
Kind
==
k_Memri
)
&&
"Invalid access!"
)
;
return
RegImm
.
Reg
;
}
</s>

Returns the register associated with this edge .


<s>
int
ARM64AsmParser
::
tryParseRegister
(
)
{
const
AsmToken
&
Tok
=
Parser
.
getTok
(
)
;
assert
(
Tok
.
is
(
AsmToken
::
Identifier
)
&&
"Token is not an Identifier"
)
;
std
::
string
lowerCase
=
Tok
.
getString
(
)
.
lower
(
)
;
unsigned
RegNum
=
MatchRegisterName
(
lowerCase
)
;
if
(
RegNum
==
0
)
RegNum
=
StringSwitch
<
unsigned
>
(
lowerCase
)
.
Case
(
"fp"
,
ARM64
::
FP
)
.
Case
(
"lr"
,
ARM64
::
LR
)
.
Case
(
"x31"
,
ARM64
::
XZR
)
.
Case
(
"w31"
,
ARM64
::
WZR
)
.
Default
(
0
)
;
if
(
RegNum
==
0
)
return
1
;
Parser
.
Lex
(
)
;
return
RegNum
;
}
</s>

tryParseRegister - parse one register if possible


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> static unsigned int flags_from_code ( enum rtx_code code ) { switch ( code ) { case LT : case GE : return CC_FLAG_S ; case GT : case LE : return CC_FLAG_S | CC_FLAG_O | CC_FLAG_Z ; case GEU : case LTU : return CC_FLAG_C ; case GTU : case LEU : return CC_FLAG_C | CC_FLAG_Z ; case EQ : case NE : return CC_FLAG_Z ; default : gcc_unreachable ( ) ; } } </s>

Convert an RTX_CODE to the set of flags needed to implement it . This assumes an integer comparison .


<s> bool HexagonInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const { return nonDbgBBSize ( & TMBB ) <= 3 && nonDbgBBSize ( & FMBB ) <= 3 ; } </s>


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const MCPhysReg ReservedGPR32 [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const MCPhysReg ReservedGPR64 [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; for ( MCPhysReg R : ReservedGPR32 ) Reserved . set ( R ) ; if ( Subtarget . isTargetNaCl ( ) ) { Reserved . set ( Mips :: T6 ) ; Reserved . set ( Mips :: T7 ) ; Reserved . set ( Mips :: T8 ) ; } for ( MCPhysReg R : ReservedGPR64 ) Reserved . set ( R ) ; if ( ! Subtarget . isABICalls ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } if ( Subtarget . isFP64bit ( ) ) { for ( MCPhysReg Reg : Mips :: AFGR64RegClass ) Reserved . set ( Reg ) ; } else { for ( MCPhysReg Reg : Mips :: FGR64RegClass ) Reserved . set ( Reg ) ; } if ( Subtarget . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; if ( hasStackRealignment ( MF ) && MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { Reserved . set ( Mips :: S7 ) ; Reserved . set ( Mips :: S7_64 ) ; } } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: DSPPos ) ; Reserved . set ( Mips :: DSPSCount ) ; Reserved . set ( Mips :: DSPCarry ) ; Reserved . set ( Mips :: DSPEFI ) ; Reserved . set ( Mips :: DSPOutFlag ) ; for ( MCPhysReg Reg : Mips :: MSACtrlRegClass ) Reserved . set ( Reg ) ; if ( Subtarget . inMips16Mode ( ) ) { const MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; Reserved . set ( Mips :: T0 ) ; Reserved . set ( Mips :: T1 ) ; if ( MF . getFunction ( ) . hasFnAttribute ( "saveS2" ) || MipsFI -> hasSaveS2 ( ) ) Reserved . set ( Mips :: S2 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> int arm_no_early_alu_shift_dep ( rtx producer , rtx consumer ) { rtx value = PATTERN ( producer ) ; rtx op = PATTERN ( consumer ) ; rtx early_op ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , 0 , 0 ) ; value = XEXP ( value , 0 ) ; if ( GET_CODE ( op ) == COND_EXEC ) op = COND_EXEC_CODE ( op ) ; if ( GET_CODE ( op ) == PARALLEL ) op = XVECEXP ( op , 0 , 0 ) ; op = XEXP ( op , 1 ) ; early_op = XEXP ( op , 0 ) ; if ( GET_CODE ( early_op ) == REG ) early_op = op ; return ! reg_overlap_mentioned_p ( value , early_op ) ; } </s>

Return nonzero if the CONSUMER instruction ( an ALU op ) does not have an early register shift value or amount dependency on the result of PRODUCER .


<s> unsigned getNumFixupKinds ( ) const override { return 1 ; } </s>

Get the number of target specific fixup kinds .


<s> void Thumb2RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: t2LDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) ARMCC :: AL ) . addReg ( 0 ) . setMIFlags ( MIFlags ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> void HexagonSubtarget :: adjustSchedDependency ( SUnit * Src , int SrcOpIdx , SUnit * Dst , int DstOpIdx , SDep & Dep ) const { if ( ! Src -> isInstr ( ) || ! Dst -> isInstr ( ) ) return ; MachineInstr * SrcInst = Src -> getInstr ( ) ; MachineInstr * DstInst = Dst -> getInstr ( ) ; const HexagonInstrInfo * QII = getInstrInfo ( ) ; SmallSet < SUnit * , 4 > ExclSrc ; SmallSet < SUnit * , 4 > ExclDst ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( 0 ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == 1 ) { Register DReg = DstInst -> getOperand ( 0 ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ 0 ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - 1 ; for ( unsigned OpNum = 0 ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , 0 , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , 0 ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } updateLatency ( * SrcInst , * DstInst , Dep ) ; } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s> void ix86_expand_xorsign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , vdest , op0 , op1 , mask , x , temp ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mode = GET_MODE ( dest ) ; if ( mode == HFmode ) vmode = V8HFmode ; else if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else gcc_unreachable ( ) ; temp = gen_reg_rtx ( vmode ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; op1 = lowpart_subreg ( vmode , force_reg ( mode , op1 ) , mode ) ; x = gen_rtx_AND ( vmode , op1 , mask ) ; emit_insn ( gen_rtx_SET ( temp , x ) ) ; op0 = lowpart_subreg ( vmode , force_reg ( mode , op0 ) , mode ) ; x = gen_rtx_XOR ( vmode , temp , op0 ) ; vdest = lowpart_subreg ( vmode , dest , mode ) ; if ( vdest == NULL_RTX ) vdest = gen_reg_rtx ( vmode ) ; else dest = NULL_RTX ; emit_insn ( gen_rtx_SET ( vdest , x ) ) ; if ( dest ) emit_move_insn ( dest , lowpart_subreg ( mode , vdest , vmode ) ) ; } </s>


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> getStackAlignment ( ) >= 32 ) { if ( Subtarget -> hasAVX2 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasAVX ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void x86_emit_floatuns ( rtx operands [ 2 ] ) { rtx_code_label * neglab , * donelab ; rtx i0 , i1 , f0 , in , out ; machine_mode mode , inmode ; inmode = GET_MODE ( operands [ 1 ] ) ; gcc_assert ( inmode == SImode || inmode == DImode ) ; out = operands [ 0 ] ; in = force_reg ( inmode , operands [ 1 ] ) ; mode = GET_MODE ( out ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , inmode , 0 , neglab ) ; expand_float ( out , in , 0 ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( inmode , LSHIFTRT , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i1 = expand_simple_binop ( inmode , AND , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i0 = expand_simple_binop ( inmode , IOR , i0 , i1 , i0 , 1 , OPTAB_DIRECT ) ; expand_float ( f0 , i0 , 0 ) ; emit_insn ( gen_rtx_SET ( out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ; emit_label ( donelab ) ; } </s>

Generate an unsigned DImode/SImode to FP conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s> static bool moxie_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 2 * UNITS_PER_WORD ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> static unsigned int mips_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment ; alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ; return alignment ; } </s>

Implement TARGET_FUNCTION_ARG_BOUNDARY . Every parameter gets at least PARM_BOUNDARY bits of alignment , but will be given anything up to STACK_BOUNDARY bits if the type requires it .


<s> void emitValueToAlignment ( unsigned ByteAlignment , int64_t Value = 0 , unsigned ValueSize = 1 , unsigned MaxBytesToEmit = 0 ) override { } </s>

Emit some number of copies of Value until the byte alignment ByteAlignment is reached .


<s> uint16_t getType ( ) const { return NodeAttrs :: type ( Attrs ) ; } </s>

Overload to return most specific vector type .


<s> static bool ix86_in_large_data_p ( tree exp ) { if ( ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && ! is_global_var ( exp ) ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , ".ldata" ) == 0 || strcmp ( section , ".lbss" ) == 0 ) return true ; return false ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp ) ) ; if ( size <= 0 || size > ix86_section_threshold ) return true ; } return false ; } </s>

Return true if this goes in small data/bss .


<s> static tree rs6000_builtin_mask_for_load ( void ) { if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) || ( TARGET_VSX && ! TARGET_EFFICIENT_UNALIGNED_VSX ) ) return altivec_builtin_mask_for_load ; else return 0 ; } </s>


<s> static bool arm_const_not_ok_for_debug_p ( rtx p ) { tree decl_op0 = NULL ; tree decl_op1 = NULL ; if ( GET_CODE ( p ) == MINUS ) { if ( GET_CODE ( XEXP ( p , 1 ) ) == SYMBOL_REF ) { decl_op1 = SYMBOL_REF_DECL ( XEXP ( p , 1 ) ) ; if ( decl_op1 && GET_CODE ( XEXP ( p , 0 ) ) == SYMBOL_REF && ( decl_op0 = SYMBOL_REF_DECL ( XEXP ( p , 0 ) ) ) ) { if ( ( VAR_P ( decl_op1 ) || TREE_CODE ( decl_op1 ) == CONST_DECL ) && ( VAR_P ( decl_op0 ) || TREE_CODE ( decl_op0 ) == CONST_DECL ) ) return ( get_variable_section ( decl_op1 , false ) != get_variable_section ( decl_op0 , false ) ) ; if ( TREE_CODE ( decl_op1 ) == LABEL_DECL && TREE_CODE ( decl_op0 ) == LABEL_DECL ) return ( DECL_CONTEXT ( decl_op1 ) != DECL_CONTEXT ( decl_op0 ) ) ; } return true ; } } return false ; } </s>

This is a temporary fix for PR60655 . Ideally we need to handle most of these cases in the generic part but currently we reject minus ( .. ) ( sym_ref ) . We try to ameliorate the case with minus ( sym_ref1 ) ( sym_ref2 ) where they are in the same section .


<s> bool Mips16RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> static bool alpha_scalar_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case QImode : case HImode : case SImode : case DImode : case TImode : return true ; case SFmode : case DFmode : return true ; case TFmode : return TARGET_HAS_XFLOATING_LIBS ; default : return false ; } } </s>

The scalar modes supported differs from the default check-what-c-supports version in that sometimes TFmode is available even when long double indicates only DFmode . On unicosmk , we have the situation that HImode does n't map to any C type , but of course we still support that .


<s> SDNode * rvexDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < rvexFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void nvptx_record_libfunc ( rtx callee , rtx retval , rtx pat ) { rtx * slot = declared_libfuncs_htab -> find_slot ( callee , INSERT ) ; if ( * slot == NULL ) { * slot = callee ; const char * name = XSTR ( callee , 0 ) ; write_fn_proto_from_insn ( func_decls , name , retval , pat ) ; } } </s>

Record a libcall or unprototyped external function . CALLEE is the SYMBOL_REF . Insert into the libfunc hash table and emit a ptx declaration for it .


<s> unsigned AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return AArch64II :: MO_GOT | AArch64II :: MO_DLLIMPORT ; if ( getTargetTriple ( ) . isOSWindows ( ) ) return AArch64II :: MO_GOT | AArch64II :: MO_COFFSTUB ; return AArch64II :: MO_GOT ; } if ( ( useSmallAddressing ( ) || TM . getCodeModel ( ) == CodeModel :: Tiny ) && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT ; if ( AllowTaggedGlobals && ! isa < FunctionType > ( GV -> getValueType ( ) ) ) return AArch64II :: MO_NC | AArch64II :: MO_TAGGED ; return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> static bool ix86_expand_vec_one_operand_perm_avx512 ( struct expand_vec_perm_d * d ) { machine_mode mode = GET_MODE ( d -> op0 ) ; machine_mode maskmode = mode ; unsigned inner_size = GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; rtx ( * gen ) ( rtx , rtx , rtx ) = NULL ; rtx target , op0 , mask ; rtx vec [ 64 ] ; if ( ! rtx_equal_p ( d -> op0 , d -> op1 ) ) return false ; if ( ! TARGET_AVX512F ) return false ; if ( ! TARGET_AVX512VL && GET_MODE_SIZE ( mode ) < 64 ) return false ; if ( ! TARGET_AVX512BW && inner_size == 2 ) return false ; if ( ! TARGET_AVX512VBMI && inner_size == 1 ) return false ; switch ( mode ) { case E_V16SImode : gen = gen_avx512f_permvarv16si ; break ; case E_V16SFmode : gen = gen_avx512f_permvarv16sf ; maskmode = V16SImode ; break ; case E_V8DImode : gen = gen_avx512f_permvarv8di ; break ; case E_V8DFmode : gen = gen_avx512f_permvarv8df ; maskmode = V8DImode ; break ; case E_V32HImode : gen = gen_avx512bw_permvarv32hi ; break ; case E_V16HImode : gen = gen_avx512vl_permvarv16hi ; break ; case E_V8HImode : gen = gen_avx512vl_permvarv8hi ; break ; case E_V64QImode : gen = gen_avx512bw_permvarv64qi ; break ; case E_V32QImode : gen = gen_avx512vl_permvarv32qi ; break ; case E_V16QImode : gen = gen_avx512vl_permvarv16qi ; break ; default : return false ; } if ( d -> testing_p ) return true ; target = d -> target ; op0 = d -> op0 ; for ( int i = 0 ; i < d -> nelt ; ++ i ) vec [ i ] = GEN_INT ( d -> perm [ i ] ) ; mask = gen_rtx_CONST_VECTOR ( maskmode , gen_rtvec_v ( d -> nelt , vec ) ) ; emit_insn ( gen ( target , op0 , force_reg ( maskmode , mask ) ) ) ; return true ; } </s>

Try to expand one-operand permutation with constant mask .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnSCC ( CallGraphSCC & SCC ) { bool Changed = false ; for ( CallGraphNode * I : SCC ) { Function * F = I -> getFunction ( ) ; if ( ! F || F -> isDeclaration ( ) || AMDGPU :: isGraphics ( F -> getCallingConv ( ) ) ) continue ; Changed |= addFeatureAttributes ( * F ) ; } return Changed ; } </s>

runOnSCC - This method should be implemented by the subclass to perform whatever action is necessary for the specified SCC .


<s> bool M680x0RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( NonScalarIntSafe && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasXMMInt ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool R600InstrInfo :: fitsReadPortLimitations ( const std :: vector < MachineInstr * > & IG , const DenseMap < unsigned , unsigned > & PV , std :: vector < BankSwizzle > & ValidSwizzle , bool isLastAluTrans ) const { std :: vector < std :: vector < std :: pair < int , unsigned > > > IGSrcs ; ValidSwizzle . clear ( ) ; unsigned ConstCount ; BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = 0 , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , AMDGPU :: OpName :: bank_swizzle ) ; ValidSwizzle . push_back ( ( R600InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned > > TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = IGSrcs . back ( ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const R600InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ; for ( unsigned i = 0 ; i < 4 ; i ++ ) { TransBS = TransSwz [ i ] ; if ( ! isConstCompatible ( TransBS , TransOps , ConstCount ) ) continue ; bool Result = FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; if ( Result ) { ValidSwizzle . push_back ( TransBS ) ; return true ; } } return false ; } </s>

Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ( in lexical order ) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available .


<s> bool AMDGPUTargetLowering :: isFNegFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return VT == MVT :: f32 || VT == MVT :: f64 || ( Subtarget -> has16BitInsts ( ) && VT == MVT :: f16 ) || ( Subtarget -> hasVOP3PInsts ( ) && VT == MVT :: v2f16 ) ; } </s>

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


<s> int is_called_in_ARM_mode ( tree func ) { gcc_assert ( TREE_CODE ( func ) == FUNCTION_DECL ) ; if ( TARGET_CALLEE_INTERWORKING && TREE_PUBLIC ( func ) ) return TRUE ; return lookup_attribute ( "interfacearm" , DECL_ATTRIBUTES ( func ) ) != NULL_TREE ; return FALSE ; } </s>

Return non-zero if FUNC must be entered in ARM mode .


<s> void BTFDebug :: endModule ( ) { if ( MapDefNotCollected ) { processGlobals ( true ) ; MapDefNotCollected = false ; } processGlobals ( false ) ; for ( auto & DataSec : DataSecEntries ) addType ( std :: move ( DataSec . second ) ) ; for ( auto & Fixup : FixupDerivedTypes ) { const DICompositeType * CTy = Fixup . first ; StringRef TypeName = CTy -> getName ( ) ; bool IsUnion = CTy -> getTag ( ) == dwarf :: DW_TAG_union_type ; uint32_t StructTypeId = 0 ; for ( const auto & StructType : StructTypes ) { if ( StructType -> getName ( ) == TypeName ) { StructTypeId = StructType -> getId ( ) ; break ; } } if ( StructTypeId == 0 ) { auto FwdTypeEntry = std :: make_unique < BTFTypeFwd > ( TypeName , IsUnion ) ; StructTypeId = addType ( std :: move ( FwdTypeEntry ) ) ; } for ( auto & TypeInfo : Fixup . second ) { const DIDerivedType * DTy = TypeInfo . first ; BTFTypeDerived * BDType = TypeInfo . second ; int TmpTypeId = genBTFTypeTags ( DTy , StructTypeId ) ; if ( TmpTypeId >= 0 ) BDType -> setPointeeType ( TmpTypeId ) ; else BDType -> setPointeeType ( StructTypeId ) ; } } for ( const auto & TypeEntry : TypeEntries ) TypeEntry -> completeType ( * this ) ; emitBTFSection ( ) ; emitBTFExtSection ( ) ; } </s>

Emit all exception information that should come after the content .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = ArrayRef < SMRange > ( ) ) { return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> bool ix86_expand_vec_shift_qihi_constant ( enum rtx_code code , rtx dest , rtx op1 , rtx op2 ) { machine_mode qimode , himode ; HOST_WIDE_INT and_constant , xor_constant ; HOST_WIDE_INT shift_amount ; rtx vec_const_and , vec_const_xor ; rtx tmp , op1_subreg ; rtx ( * gen_shift ) ( rtx , rtx , rtx ) ; rtx ( * gen_and ) ( rtx , rtx , rtx ) ; rtx ( * gen_xor ) ( rtx , rtx , rtx ) ; rtx ( * gen_sub ) ( rtx , rtx , rtx ) ; if ( ! CONST_INT_P ( op2 ) ) return false ; qimode = GET_MODE ( dest ) ; shift_amount = INTVAL ( op2 ) ; if ( shift_amount > 7 ) return false ; gcc_assert ( code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT ) ; xor_constant = 1 << ( 8 - shift_amount - 1 ) ; and_constant = ( code == ASHIFT ? 256 - ( 1 << shift_amount ) : ( 1 << ( 8 - shift_amount ) ) - 1 ) ; switch ( qimode ) { case V16QImode : himode = V8HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv8hi3 : ( code == ASHIFTRT ) ? gen_ashrv8hi3 : gen_lshrv8hi3 ) ; gen_and = gen_andv16qi3 ; gen_xor = gen_xorv16qi3 ; gen_sub = gen_subv16qi3 ; break ; case V32QImode : himode = V16HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv16hi3 : ( code == ASHIFTRT ) ? gen_ashrv16hi3 : gen_lshrv16hi3 ) ; gen_and = gen_andv32qi3 ; gen_xor = gen_xorv32qi3 ; gen_sub = gen_subv32qi3 ; break ; case V64QImode : himode = V32HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv32hi3 : ( code == ASHIFTRT ) ? gen_ashrv32hi3 : gen_lshrv32hi3 ) ; gen_and = gen_andv64qi3 ; gen_xor = gen_xorv64qi3 ; gen_sub = gen_subv64qi3 ; break ; default : gcc_unreachable ( ) ; } tmp = gen_reg_rtx ( himode ) ; vec_const_and = gen_reg_rtx ( qimode ) ; op1_subreg = lowpart_subreg ( himode , op1 , qimode ) ; emit_insn ( gen_shift ( tmp , op1_subreg , op2 ) ) ; emit_move_insn ( dest , simplify_gen_subreg ( qimode , tmp , himode , 0 ) ) ; emit_move_insn ( vec_const_and , ix86_build_const_vector ( qimode , true , gen_int_mode ( and_constant , QImode ) ) ) ; emit_insn ( gen_and ( dest , dest , vec_const_and ) ) ; if ( code == ASHIFTRT ) { vec_const_xor = gen_reg_rtx ( qimode ) ; emit_move_insn ( vec_const_xor , ix86_build_const_vector ( qimode , true , gen_int_mode ( xor_constant , QImode ) ) ) ; emit_insn ( gen_xor ( dest , dest , vec_const_xor ) ) ; emit_insn ( gen_sub ( dest , dest , vec_const_xor ) ) ; } return true ; } </s>

Expand a vector operation shift by constant for a V * QImode in terms of the same operation on V * HImode . Return true if success .


<s> static void alpha_pad_function_end ( void ) { rtx_insn * insn , * next ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! CALL_P ( insn ) || ! ( SIBLING_CALL_P ( insn ) || find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) ) continue ; next = NEXT_INSN ( insn ) ; if ( next == NULL ) continue ; if ( NOTE_P ( next ) && NOTE_KIND ( next ) == NOTE_INSN_CALL_ARG_LOCATION ) insn = next ; next = next_active_insn ( insn ) ; if ( next ) { rtx pat = PATTERN ( next ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == UNSPEC_VOLATILE && XINT ( SET_SRC ( pat ) , 1 ) == UNSPECV_LDGP1 ) emit_insn_after ( gen_unop ( ) , insn ) ; } } } </s>

Insert an unop between sibcall or noreturn function call and GP load .


<s> bool NVPTXProxyRegErasure :: runOnMachineFunction ( MachineFunction & MF ) { SmallVector < MachineInstr * , 16 > RemoveList ; for ( auto & BB : MF ) { for ( auto & MI : BB ) { switch ( MI . getOpcode ( ) ) { case NVPTX :: ProxyRegI1 : case NVPTX :: ProxyRegI16 : case NVPTX :: ProxyRegI32 : case NVPTX :: ProxyRegI64 : case NVPTX :: ProxyRegF16 : case NVPTX :: ProxyRegF16x2 : case NVPTX :: ProxyRegF32 : case NVPTX :: ProxyRegF64 : replaceMachineInstructionUsage ( MF , MI ) ; RemoveList . push_back ( & MI ) ; break ; } } } for ( auto * MI : RemoveList ) { MI -> eraseFromParent ( ) ; } return ! RemoveList . empty ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool WebAssemblyTargetLowering :: isIntDivCheap ( EVT VT , AttributeSet Attr ) const { return true ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
ATOMIC_LOAD_ADD
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMADD64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_AND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_NAND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMNAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_OR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_SUB
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSUB64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_XOR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMXOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSWAP64_DAG
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMCMPXCHG64_DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
bool
LinuxAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
EmitAlignment
(
MF
.
getAlignment
(
)
,
F
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
llvm_unreachable
(
"Unknown linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
LinkerPrivateLinkage
:
case
Function
::
InternalLinkage
:
break
;
case
Function
::
ExternalLinkage
:
O
<<
"\t.global\t"
<<
CurrentFnName
<<
"\n"
<<
"\t.type\t"
<<
CurrentFnName
<<
", @function\n"
;
break
;
case
Function
::
WeakAnyLinkage
:
case
Function
::
WeakODRLinkage
:
case
Function
::
LinkOnceAnyLinkage
:
case
Function
::
LinkOnceODRLinkage
:
O
<<
"\t.global\t"
<<
CurrentFnName
<<
"\n"
;
O
<<
"\t.weak_definition\t"
<<
CurrentFnName
<<
"\n"
;
break
;
}
O
<<
CurrentFnName
<<
":\n"
;
DW
->
BeginFunction
(
&
MF
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
O
<<
"\t.size\t"
<<
CurrentFnName
<<
",.-"
<<
CurrentFnName
<<
"\n"
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
DW
->
EndFunction
(
&
MF
)
;
return
false
;
}
</s>


<s> SDNode * SparcDAGToDAGISel :: Select ( SDNode * N ) { DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case SPISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: SDIV : case ISD :: UDIV : { SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: WRYrr , dl , MVT :: Glue , TopPart , CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ) , 0 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: Glue , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , SP :: RDY , MVT :: i32 , SDValue ( Mul , 1 ) ) ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static rtx rs6000_mixed_function_arg ( enum machine_mode mode , tree type , int align_words ) { int n_units ; int i , k ; rtx rvec [ GP_ARG_NUM_REG + 1 ] ; if ( align_words >= GP_ARG_NUM_REG ) return NULL_RTX ; n_units = rs6000_arg_size ( mode , type ) ; if ( n_units == 0 || ( n_units == 1 && mode != BLKmode ) ) return gen_rtx_REG ( mode , GP_ARG_MIN_REG + align_words ) ; k = 0 ; if ( align_words + n_units > GP_ARG_NUM_REG ) rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; i = 0 ; do { rtx r = gen_rtx_REG ( SImode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * 4 ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_units != 0 ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( k , rvec ) ) ; } </s>

Determine where to place an argument in 64-bit mode with 32-bit ABI .


<s> void PPCAIXAsmPrinter :: emitFunctionEntryLabel ( ) { if ( ! TM . getFunctionSections ( ) ) PPCAsmPrinter :: emitFunctionEntryLabel ( ) ; llvm :: for_each ( GOAliasMap [ & MF -> getFunction ( ) ] , [ this ] ( const GlobalAlias * Alias ) { OutStreamer -> emitLabel ( getObjFileLowering ( ) . getFunctionEntryPointSymbol ( Alias , TM ) ) ; } ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s> int tilegx_adjust_insn_length ( rtx_insn * insn , int length ) { machine_mode mode = GET_MODE ( insn ) ; if ( mode == SImode ) return 0 ; return length ; } </s>

Return the length of INSN . LENGTH is the initial length computed by attributes in the machine-description file . This is where we account for bundles .


<s> void PPCPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


"Using .cp. section for writeable object."

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s>
MCSection
*
HexagonTargetObjectFile
::
getExplicitSectionGlobal
(
const
GlobalObject
*
GO
,
SectionKind
Kind
,
const
TargetMachine
&
TM
)
const
{
TRACE
(
"[getExplicitSectionGlobal] GO("
<<
GO
->
getName
(
)
<<
") from("
<<
GO
->
getSection
(
)
<<
") "
)
;
TRACE
(
(
GO
->
hasPrivateLinkage
(
)
"private_linkage "
:
""
)
<<
(
GO
->
hasLocalLinkage
(
)
"local_linkage "
:
""
)
<<
(
GO
->
hasInternalLinkage
(
)
"internal "
:
""
)
<<
(
GO
->
hasExternalLinkage
(
)
"external "
:
""
)
<<
(
GO
->
hasCommonLinkage
(
)
"common_linkage "
:
""
)
<<
(
GO
->
hasCommonLinkage
(
)
"common "
:
""
)
<<
(
Kind
.
isCommon
(
)
"kind_common "
:
""
)
<<
(
Kind
.
isBSS
(
)
"kind_bss "
:
""
)
<<
(
Kind
.
isBSSLocal
(
)
"kind_bss_local "
:
""
)
)
;
if
(
GO
->
hasSection
(
)
)
{
StringRef
Section
=
GO
->
getSection
(
)
;
if
(
Section
.
find
(
".access.text.group"
)
!=
StringRef
::
npos
)
return
getContext
(
)
.
getELFSection
(
GO
->
getSection
(
)
,
ELF
::
SHT_PROGBITS
,
ELF
::
SHF_ALLOC
|
ELF
::
SHF_EXECINSTR
)
;
if
(
Section
.
find
(
".access.data.group"
)
!=
StringRef
::
npos
)
return
getContext
(
)
.
getELFSection
(
GO
->
getSection
(
)
,
ELF
::
SHT_PROGBITS
,
ELF
::
SHF_WRITE
|
ELF
::
SHF_ALLOC
)
;
}
if
(
isGlobalInSmallSection
(
GO
,
TM
)
)
return
selectSmallSectionForGlobal
(
GO
,
Kind
,
TM
)
;
TRACE
(
"default_ELF_section\n"
)
;
return
TargetLoweringObjectFileELF
::
getExplicitSectionGlobal
(
GO
,
Kind
,
TM
)
;
}
</s>

Hexagon
Hexagon
"[getExplicitSectionGlobal] GO("
") from("
") "
"private_linkage "
""
"local_linkage "
""
"internal "
""
"external "
""
"common_linkage "
""
"common "
""
"kind_common "
""
"kind_bss "
""
"kind_bss_local "
""
".access.text.group"
".access.data.group"
"default_ELF_section\n"


<s> virtual unsigned getISAEncoding ( ) LLVM_OVERRIDE { if ( ! Subtarget -> isTargetDarwin ( ) ) return 0 ; return Subtarget -> isThumb ( ) ? ARM :: DW_ISA_ARM_thumb : ARM :: DW_ISA_ARM_arm ; } </s>

Get the value for DW_AT_APPLE_isa . Zero if no isa encoding specified .


<s> static int msp430_costs ( rtx src , rtx dst , bool speed , rtx outer_rtx ) { enum rtx_code src_code = GET_CODE ( src ) ; enum rtx_code dst_code = GET_CODE ( dst ) ; enum rtx_code outer_code = GET_CODE ( outer_rtx ) ; machine_mode outer_mode = GET_MODE ( outer_rtx ) ; const struct double_op_cost * cost_p ; cost_p = ( speed ? & cycle_cost_double_op : & size_cost_double_op ) ; if ( outer_code == TRUNCATE && ( outer_mode == QImode || outer_mode == HImode || outer_mode == PSImode ) ) return 0 ; if ( dst_code == SYMBOL_REF || dst_code == LABEL_REF || dst_code == CONST_INT ) return 0 ; switch ( src_code ) { case REG : return ( dst_code == REG ? cost_p -> r2r : ( dst_code == PC ? cost_p -> r2pc : cost_p -> r2m ) ) ; case CONST_INT : case SYMBOL_REF : case LABEL_REF : case CONST : return ( dst_code == REG ? cost_p -> imm2r : ( dst_code == PC ? cost_p -> imm2pc : cost_p -> imm2m ) ) ; case MEM : if ( msp430_is_mem_indirect ( src ) ) return ( dst_code == REG ? cost_p -> ind2r : ( dst_code == PC ? cost_p -> ind2pc : cost_p -> ind2m ) ) ; else return ( dst_code == REG ? cost_p -> mem2r : ( dst_code == PC ? cost_p -> mem2pc : cost_p -> mem2m ) ) ; default : return cost_p -> mem2m ; } } </s>

Costs of MSP430 instructions are generally based on the addressing mode combination of the source and destination operands . Given source operand SRC ( which may be NULL to indicate a single-operand instruction ) and destination operand DST return the cost of this expression .


<s> SDValue AlphaTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Alpha ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( 1 ) ; SDValue RetValue = Chain . getValue ( 0 ) ; InFlag = Chain . getValue ( 2 ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( ISD :: AssertSext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( ISD :: AssertZext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( ISD :: TRUNCATE , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void rs6000_scale_v2df ( rtx tgt , rtx src , int scale ) { HOST_WIDE_INT hwi_scale ( scale ) ; REAL_VALUE_TYPE r_pow ; rtvec v = rtvec_alloc ( 2 ) ; rtx elt ; rtx scale_vec = gen_reg_rtx ( V2DFmode ) ; ( void ) real_powi ( & r_pow , DFmode , & dconst2 , hwi_scale ) ; elt = CONST_DOUBLE_FROM_REAL_VALUE ( r_pow , DFmode ) ; RTVEC_ELT ( v , 0 ) = elt ; RTVEC_ELT ( v , 1 ) = elt ; rs6000_expand_vector_init ( scale_vec , gen_rtx_PARALLEL ( V2DFmode , v ) ) ; emit_insn ( gen_mulv2df3 ( tgt , src , scale_vec ) ) ; } </s>

Scale a V2DF vector SRC by two to the SCALE and place in TGT .


<s> static HOST_WIDE_INT loongarch_starting_frame_offset ( void ) { if ( FRAME_GROWS_DOWNWARD ) return 0 ; return crtl -> outgoing_args_size ; } </s>

Implement TARGET_STARTING_FRAME_OFFSET . See loongarch_compute_frame_info for details about the frame layout .


"VE DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


Return an array that contains the bitmask target flag values and their names .