<s> static void sparc_emit_set_const32 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx temp = op0 ; if ( can_create_pseudo_p ( ) ) temp = gen_reg_rtx ( mode ) ; if ( GET_CODE ( op1 ) == CONST_INT ) { gcc_assert ( ! small_int_operand ( op1 , mode ) && ! const_high_operand ( op1 , mode ) ) ; emit_insn ( gen_rtx_SET ( temp , GEN_INT ( INTVAL ( op1 ) & ~ ( HOST_WIDE_INT ) 0x3ff ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_IOR ( mode , temp , GEN_INT ( INTVAL ( op1 ) & 0x3ff ) ) ) ) ; } else { emit_insn ( gen_rtx_SET ( temp , gen_rtx_HIGH ( mode , op1 ) ) ) ; emit_insn ( gen_rtx_SET ( op0 , gen_rtx_LO_SUM ( mode , temp , op1 ) ) ) ; } } </s>

We know it ca n't be done in one insn when we get here , the movsi expander guarentees this .


<s> static bool rs6000_function_parms_need_stack ( tree fun , bool incoming ) { tree fntype , result ; CUMULATIVE_ARGS args_so_far_v ; cumulative_args_t args_so_far ; if ( ! fun ) return false ; fntype = fun ; if ( ! TYPE_P ( fun ) ) fntype = TREE_TYPE ( fun ) ; if ( ( ! incoming && ! prototype_p ( fntype ) ) || stdarg_p ( fntype ) ) return true ; INIT_CUMULATIVE_INCOMING_ARGS ( args_so_far_v , fntype , NULL_RTX ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; if ( incoming ) { gcc_assert ( DECL_P ( fun ) ) ; result = DECL_RESULT ( fun ) ; } else result = TREE_TYPE ( fntype ) ; if ( result && aggregate_value_p ( result , fntype ) ) { if ( ! TYPE_P ( result ) ) result = TREE_TYPE ( result ) ; result = build_pointer_type ( result ) ; rs6000_parm_needs_stack ( args_so_far , result ) ; } if ( incoming ) { tree parm ; for ( parm = DECL_ARGUMENTS ( fun ) ; parm && parm != void_list_node ; parm = TREE_CHAIN ( parm ) ) if ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( parm ) ) ) return true ; } else { function_args_iterator args_iter ; tree arg_type ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) if ( rs6000_parm_needs_stack ( args_so_far , arg_type ) ) return true ; } return false ; } </s>

Return true if FUN has no prototype , has a variable argument list , or passes any parameter in memory .


<s> const char * NVPTXTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case NVPTXISD :: CALL : return "NVPTXISD::CALL" ; case NVPTXISD :: RET_FLAG : return "NVPTXISD::RET_FLAG" ; case NVPTXISD :: Wrapper : return "NVPTXISD::Wrapper" ; case NVPTXISD :: NVBuiltin : return "NVPTXISD::NVBuiltin" ; case NVPTXISD :: DeclareParam : return "NVPTXISD::DeclareParam" ; case NVPTXISD :: DeclareScalarParam : return "NVPTXISD::DeclareScalarParam" ; case NVPTXISD :: DeclareRet : return "NVPTXISD::DeclareRet" ; case NVPTXISD :: DeclareRetParam : return "NVPTXISD::DeclareRetParam" ; case NVPTXISD :: PrintCall : return "NVPTXISD::PrintCall" ; case NVPTXISD :: LoadParam : return "NVPTXISD::LoadParam" ; case NVPTXISD :: StoreParam : return "NVPTXISD::StoreParam" ; case NVPTXISD :: StoreParamS32 : return "NVPTXISD::StoreParamS32" ; case NVPTXISD :: StoreParamU32 : return "NVPTXISD::StoreParamU32" ; case NVPTXISD :: MoveToParam : return "NVPTXISD::MoveToParam" ; case NVPTXISD :: CallArgBegin : return "NVPTXISD::CallArgBegin" ; case NVPTXISD :: CallArg : return "NVPTXISD::CallArg" ; case NVPTXISD :: LastCallArg : return "NVPTXISD::LastCallArg" ; case NVPTXISD :: CallArgEnd : return "NVPTXISD::CallArgEnd" ; case NVPTXISD :: CallVoid : return "NVPTXISD::CallVoid" ; case NVPTXISD :: CallVal : return "NVPTXISD::CallVal" ; case NVPTXISD :: CallSymbol : return "NVPTXISD::CallSymbol" ; case NVPTXISD :: Prototype : return "NVPTXISD::Prototype" ; case NVPTXISD :: MoveParam : return "NVPTXISD::MoveParam" ; case NVPTXISD :: MoveRetval : return "NVPTXISD::MoveRetval" ; case NVPTXISD :: MoveToRetval : return "NVPTXISD::MoveToRetval" ; case NVPTXISD :: StoreRetval : return "NVPTXISD::StoreRetval" ; case NVPTXISD :: PseudoUseParam : return "NVPTXISD::PseudoUseParam" ; case NVPTXISD :: RETURN : return "NVPTXISD::RETURN" ; case NVPTXISD :: CallSeqBegin : return "NVPTXISD::CallSeqBegin" ; case NVPTXISD :: CallSeqEnd : return "NVPTXISD::CallSeqEnd" ; case NVPTXISD :: LoadV2 : return "NVPTXISD::LoadV2" ; case NVPTXISD :: LoadV4 : return "NVPTXISD::LoadV4" ; case NVPTXISD :: LDGV2 : return "NVPTXISD::LDGV2" ; case NVPTXISD :: LDGV4 : return "NVPTXISD::LDGV4" ; case NVPTXISD :: LDUV2 : return "NVPTXISD::LDUV2" ; case NVPTXISD :: LDUV4 : return "NVPTXISD::LDUV4" ; case NVPTXISD :: StoreV2 : return "NVPTXISD::StoreV2" ; case NVPTXISD :: StoreV4 : return "NVPTXISD::StoreV4" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

NVPTX NVPTX 0 NVPTXISD::CALL "NVPTXISD::CALL" NVPTXISD::RET_FLAG "NVPTXISD::RET_FLAG" NVPTXISD::Wrapper "NVPTXISD::Wrapper" NVPTXISD::NVBuiltin "NVPTXISD::NVBuiltin" NVPTXISD::DeclareParam "NVPTXISD::DeclareParam" NVPTXISD::DeclareScalarParam "NVPTXISD::DeclareScalarParam" NVPTXISD::DeclareRet "NVPTXISD::DeclareRet" NVPTXISD::DeclareRetParam "NVPTXISD::DeclareRetParam" NVPTXISD::PrintCall "NVPTXISD::PrintCall" NVPTXISD::LoadParam "NVPTXISD::LoadParam" NVPTXISD::StoreParam "NVPTXISD::StoreParam" NVPTXISD::StoreParamS32 "NVPTXISD::StoreParamS32" NVPTXISD::StoreParamU32 "NVPTXISD::StoreParamU32" NVPTXISD::MoveToParam "NVPTXISD::MoveToParam" NVPTXISD::CallArgBegin "NVPTXISD::CallArgBegin" NVPTXISD::CallArg "NVPTXISD::CallArg" NVPTXISD::LastCallArg "NVPTXISD::LastCallArg" NVPTXISD::CallArgEnd "NVPTXISD::CallArgEnd" NVPTXISD::CallVoid "NVPTXISD::CallVoid" NVPTXISD::CallVal "NVPTXISD::CallVal" NVPTXISD::CallSymbol "NVPTXISD::CallSymbol" NVPTXISD::Prototype "NVPTXISD::Prototype" NVPTXISD::MoveParam "NVPTXISD::MoveParam" NVPTXISD::MoveRetval "NVPTXISD::MoveRetval" NVPTXISD::MoveToRetval "NVPTXISD::MoveToRetval" NVPTXISD::StoreRetval "NVPTXISD::StoreRetval" NVPTXISD::PseudoUseParam "NVPTXISD::PseudoUseParam" NVPTXISD::RETURN "NVPTXISD::RETURN" NVPTXISD::CallSeqBegin "NVPTXISD::CallSeqBegin" NVPTXISD::CallSeqEnd "NVPTXISD::CallSeqEnd" NVPTXISD::LoadV2 "NVPTXISD::LoadV2" NVPTXISD::LoadV4 "NVPTXISD::LoadV4" NVPTXISD::LDGV2 "NVPTXISD::LDGV2" NVPTXISD::LDGV4 "NVPTXISD::LDGV4" NVPTXISD::LDUV2 "NVPTXISD::LDUV2" NVPTXISD::LDUV4 "NVPTXISD::LDUV4" NVPTXISD::StoreV2 "NVPTXISD::StoreV2" NVPTXISD::StoreV4 "NVPTXISD::StoreV4"


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo . get ( ) ; } </s>

getRegInfo - Return information about the registers currently in use .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void HexagonAsmInstPrinter :: printInst ( MCInst const * MI , raw_ostream & O , StringRef Annot , MCSubtargetInfo const & STI ) { assert ( HexagonMCInstrInfo :: isBundle ( * MI ) ) ; assert ( HexagonMCInstrInfo :: bundleSize ( * MI ) <= HEXAGON_PACKET_SIZE ) ; std :: string Buffer ; { raw_string_ostream TempStream ( Buffer ) ; RawPrinter -> printInst ( MI , TempStream , "" , STI ) ; } StringRef Contents ( Buffer ) ; auto PacketBundle = Contents . rsplit ( '\n' ) ; auto HeadTail = PacketBundle . first . split ( '\n' ) ; auto Preamble = "\t{\n\t\t" ; auto Separator = "" ; while ( ! HeadTail . first . empty ( ) ) { O << Separator ; StringRef Inst ; auto Duplex = HeadTail . first . split ( '\v' ) ; if ( ! Duplex . second . empty ( ) ) { O << Duplex . first << "\n" ; Inst = Duplex . second ; } else Inst = Duplex . first ; O << Preamble ; O << Inst ; HeadTail = HeadTail . second . split ( '\n' ) ; Preamble = "" ; Separator = "\n\t\t" ; } O << "\n\t}" << PacketBundle . second ; } </s>

Print the specified MCInst to the specified raw_ostream .

Hexagon Hexagon Hexagon Hexagon "" "\t{\n\t\t" "" "\n" "" "\n\t\t" "\n\t}"


<s> const TGSISubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned getLinkageSize ( ) const { return LinkageSize ; } </s>

getLinkageSize - Return the size of the PowerPC ABI linkage area .


<s> static void aarch64_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ) { ptr -> x_aarch64_override_tune_string = opts -> x_aarch64_override_tune_string ; } </s>


<s> static void alpha_align_insns_1 ( unsigned int max_align , rtx_insn * ( * next_group ) ( rtx_insn * , int * , int * ) , rtx ( * next_nop ) ( int * ) ) { unsigned int align ; int ofs ; int prev_in_use , in_use , len , ldgp ; rtx_insn * i , * next ; shorten_branches ( get_insns ( ) ) ; if ( align_functions < 4 ) align = 4 ; else if ( ( unsigned int ) align_functions < max_align ) align = align_functions ; else align = max_align ; ofs = prev_in_use = 0 ; i = get_insns ( ) ; if ( NOTE_P ( i ) ) i = next_nonnote_insn ( i ) ; ldgp = alpha_function_needs_gp ? 8 : 0 ; while ( i ) { next = ( * next_group ) ( i , & in_use , & len ) ; if ( LABEL_P ( i ) ) { unsigned int new_align = 1 << label_to_alignment ( i ) ; if ( new_align >= align ) { align = new_align < max_align ? new_align : max_align ; ofs = 0 ; } else if ( ofs & ( new_align - 1 ) ) ofs = ( ofs | ( new_align - 1 ) ) + 1 ; gcc_assert ( ! len ) ; } else if ( in_use == 0 ) { if ( len < 0 ) { ofs = 0 ; align = 4 ; len = 0 ; } } else if ( ( int ) align < len ) { unsigned int new_log_align = len > 8 ? 4 : 3 ; rtx_insn * prev , * where ; where = prev = prev_nonnote_insn ( i ) ; if ( ! where || ! LABEL_P ( where ) ) where = i ; if ( ! ( TARGET_EXPLICIT_RELOCS && prev && CALL_P ( prev ) ) ) { emit_insn_before ( gen_realign ( GEN_INT ( new_log_align ) ) , where ) ; align = 1 << new_log_align ; ofs = 0 ; } } else if ( ldgp > 0 ) ldgp -= len ; else if ( ofs + len > ( int ) align ) { int nop_count = ( align - ofs ) / 4 ; rtx_insn * where ; where = prev_nonnote_insn ( i ) ; if ( where ) { if ( LABEL_P ( where ) ) { rtx_insn * where2 = prev_nonnote_insn ( where ) ; if ( where2 && JUMP_P ( where2 ) ) where = where2 ; } else if ( NONJUMP_INSN_P ( where ) ) where = i ; } else where = i ; do emit_insn_before ( ( * next_nop ) ( & prev_in_use ) , where ) ; while ( -- nop_count ) ; ofs = 0 ; } ofs = ( ofs + len ) & ( align - 1 ) ; prev_in_use = in_use ; i = next ; } } </s>

The instruction group alignment main loop .


<s> static ARMCC :: CondCodes getPredicate ( const MCInst & Inst , const MCInstrInfo & Info , unsigned & PredReg ) { const MCInstrDesc & Desc = Info . get ( Inst . getOpcode ( ) ) ; int PIdx = Desc . findFirstPredOperandIdx ( ) ; if ( PIdx == - 1 ) { PredReg = 0 ; return ARMCC :: AL ; } PredReg = Inst . getOperand ( PIdx + 1 ) . getReg ( ) ; return static_cast < ARMCC :: CondCodes > ( Inst . getOperand ( PIdx ) . getImm ( ) ) ; } </s>

Returns the comparison predicate underlying the intrinsic .


<s>
bool
LinuxAsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
SwitchToTextSection
(
"\t.text"
)
;
DW
=
getAnalysisIfAvailable
<
DwarfWriter
>
(
)
;
assert
(
DW
&&
"Dwarf Writer is not available"
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
DW
->
BeginModule
(
&
M
,
MMI
,
O
,
this
,
TAI
)
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

CellSPU
"\t.text"
"Dwarf Writer is not available"


<s> static bool aarch64_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_SIMD && ( AARCH64_VALID_SIMD_QREG_MODE ( mode ) || AARCH64_VALID_SIMD_DREG_MODE ( mode ) ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; return false ; } </s>

Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P .


<s> static void or1k_save_reg ( int regno , HOST_WIDE_INT offset ) { rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; rtx insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit rtl to save register REGNO contents to stack memory at the given OFFSET from the current stack pointer .


<s> static int ix86_vec_cost ( machine_mode mode , int cost ) { if ( ! VECTOR_MODE_P ( mode ) ) return cost ; if ( GET_MODE_BITSIZE ( mode ) == 128 && TARGET_SSE_SPLIT_REGS ) return cost * GET_MODE_BITSIZE ( mode ) / 64 ; else if ( GET_MODE_BITSIZE ( mode ) > 128 && TARGET_AVX256_SPLIT_REGS ) return cost * GET_MODE_BITSIZE ( mode ) / 128 ; else if ( GET_MODE_BITSIZE ( mode ) > 256 && TARGET_AVX512_SPLIT_REGS ) return cost * GET_MODE_BITSIZE ( mode ) / 256 ; return cost ; } </s>

Return cost of vector operation in MODE given that scalar version has COST . If PARALLEL is true assume that CPU has more than one unit performing the operation .


<s> bool X86TargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { APInt MulC ; if ( ! ISD :: isConstantSplatVector ( C . getNode ( ) , MulC ) ) return false ; while ( getTypeAction ( Context , VT ) != TypeLegal ) VT = getTypeToTransformTo ( Context , VT ) ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; if ( isOperationLegal ( ISD :: MUL , VT ) && EltSizeInBits <= 32 && ( EltSizeInBits != 32 || ! Subtarget . isPMULLDSlow ( ) ) ) return false ; return ( MulC + 1 ) . isPowerOf2 ( ) || ( MulC - 1 ) . isPowerOf2 ( ) || ( 1 - MulC ) . isPowerOf2 ( ) || ( - ( MulC + 1 ) ) . isPowerOf2 ( ) ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


<s> bool M68kFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; M68kMachineFunctionInfo * M68kFI = MF . getInfo < M68kMachineFunctionInfo > ( ) ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + M68kFI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; Register FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i < e ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s>
SDValue
TriCoreTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
Type
*
t
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
->
getReturnType
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_TriCore
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
if
(
t
->
isPointerTy
(
)
)
VA
.
convertToReg
(
TriCore
::
A2
)
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
TriCoreISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool s390_valid_shift_count ( rtx op , HOST_WIDE_INT implicit_mask ) { while ( GET_CODE ( op ) == SUBREG && subreg_lowpart_p ( op ) ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == AND ) { rtx op1 = XEXP ( op , 0 ) ; rtx imm = XEXP ( op , 1 ) ; if ( GET_CODE ( op1 ) == SUBREG && subreg_lowpart_p ( op1 ) ) op1 = XEXP ( op1 , 0 ) ; if ( ! ( register_operand ( op1 , GET_MODE ( op1 ) ) || GET_CODE ( op1 ) == PLUS ) ) return false ; if ( ! immediate_operand ( imm , GET_MODE ( imm ) ) ) return false ; HOST_WIDE_INT val = INTVAL ( imm ) ; if ( implicit_mask > 0 && ( val & implicit_mask ) != implicit_mask ) return false ; op = op1 ; } return s390_decompose_addrstyle_without_index ( op , NULL , NULL ) ; } </s>

Check that OP is a valid shift count operand . It should be of the following structure : ( subreg ( and ( plus ( reg imm_op ) ) 2^k-1 ) 7 ) where subreg , and and plus are optional . If IMPLICIT_MASK is > 0 and OP contains and ( AND ... immediate ) it is checked whether IMPLICIT_MASK and the immediate match . Otherwise , no checking is performed .


<s> static bool bfin_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED ) { return true ; } </s>

Decide whether we can force certain constants to memory . If we decide we ca n't , the caller should be able to cope with it in another way .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s>
static
void
unicosmk_output_ssib
(
FILE
*
file
,
const
char
*
fnname
)
{
int
len
;
int
i
;
rtx
x
;
rtx
ciw
;
struct
machine_function
*
machine
=
cfun
->
machine
;
ssib_section
(
)
;
fprintf
(
file
,
"\t.endp\n\n\t.psect\t%s%s,data\n"
,
user_label_prefix
,
unicosmk_ssib_name
(
)
)
;
len
=
strlen
(
fnname
)
;
fprintf
(
file
,
"\t.quad\t^X20008%2.2X28\n"
,
len
)
;
fputs
(
"\t.quad\t0\n"
,
file
)
;
fputs
(
"\t.quad\t"
,
file
)
;
assemble_name
(
file
,
fnname
)
;
putc
(
'\n'
,
file
)
;
fputs
(
"\t.quad\t0\n"
,
file
)
;
fputs
(
"\t.quad\t0\n"
,
file
)
;
for
(
i
=
0
;
i
<
len
;
i
++
)
fprintf
(
file
,
"\t.byte\t%d\n"
,
(
int
)
(
fnname
[
i
]
)
)
;
if
(
(
len
%
8
)
==
0
)
fputs
(
"\t.quad\t0\n"
,
file
)
;
else
fprintf
(
file
,
"\t.bits\t%d : 0\n"
,
(
8
(
len
%
8
)
)
*
8
)
;
for
(
x
=
machine
->
first_ciw
;
x
;
x
=
XEXP
(
x
,
1
)
)
{
ciw
=
XEXP
(
x
,
0
)
;
fprintf
(
file
,
"\t.quad\t"
HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n"
,
CONST_DOUBLE_HIGH
(
ciw
)
,
CONST_DOUBLE_LOW
(
ciw
)
)
;
fprintf
(
file
,
"\t.quad\t"
HOST_WIDE_INT_PRINT_HEX
"\n"
,
INTVAL
(
ciw
)
)
;
}
}
</s>

Output the static subroutine information block for the current function .


"Only 32/64-bit atomic stores supported"

Perform a store-conditional operation to Addr .


<s> FastISel * PPC :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const TargetMachine & TM = FuncInfo . MF -> getTarget ( ) ; const PPCSubtarget * Subtarget = & TM . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget -> isPPC64 ( ) && Subtarget -> isSVR4ABI ( ) ) return new PPCFastISel ( FuncInfo , LibInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

PowerPC PPC::createFastISel PPC PPC PPC PPC 0


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
SDLoc
&
dl
=
CLI
.
DL
;
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
=
CLI
.
Outs
;
SmallVectorImpl
<
SDValue
>
&
OutVals
=
CLI
.
OutVals
;
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> std :: pair < const TargetRegisterClass * , uint8_t > ARMTargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = 0 ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: f32 : case MVT :: f64 : case MVT :: v8i8 : case MVT :: v4i16 : case MVT :: v2i32 : case MVT :: v1i64 : case MVT :: v2f32 : RRC = & ARM :: DPRRegClass ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = 2 ; break ; case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : RRC = & ARM :: DPRRegClass ; Cost = 2 ; break ; case MVT :: v4i64 : RRC = & ARM :: DPRRegClass ; Cost = 4 ; break ; case MVT :: v8i64 : RRC = & ARM :: DPRRegClass ; Cost = 8 ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> int arc_double_limm_p ( rtx value ) { HOST_WIDE_INT low , high ; gcc_assert ( GET_CODE ( value ) == CONST_DOUBLE ) ; low = CONST_DOUBLE_LOW ( value ) ; high = CONST_DOUBLE_HIGH ( value ) ; if ( low & 0x80000000 ) { return ( ( ( unsigned HOST_WIDE_INT ) low <= 0xffffffff && high == 0 ) || ( ( ( low & - ( unsigned HOST_WIDE_INT ) 0x80000000 ) == - ( unsigned HOST_WIDE_INT ) 0x80000000 ) && high == - 1 ) ) ; } else { return ( unsigned HOST_WIDE_INT ) low <= 0x7fffffff && high == 0 ; } } </s>

Return 1 if VALUE , a const_double , will fit in a limm ( 4 byte number ) . We assume the value can be either signed or unsigned .


<s> bool X86ATTAsmParser :: ParseInstruction ( const StringRef & Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { StringRef PatchedName = StringSwitch < StringRef > ( Name ) . Case ( "sal" , "shl" ) . Case ( "salb" , "shlb" ) . Case ( "sall" , "shll" ) . Case ( "salq" , "shlq" ) . Case ( "salw" , "shlw" ) . Case ( "repe" , "rep" ) . Case ( "repz" , "rep" ) . Case ( "repnz" , "repne" ) . Default ( Name ) ; Operands . push_back ( X86Operand :: CreateToken ( PatchedName , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( getLexer ( ) . is ( AsmToken :: Star ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( X86Operand :: CreateToken ( "*" , Loc ) ) ; Parser . Lex ( ) ; } if ( X86Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( X86Operand * Op = ParseOperand ( ) ) Operands . push_back ( Op ) ; else return true ; } } if ( ( Name . startswith ( "shr" ) || Name . startswith ( "sar" ) || Name . startswith ( "shl" ) ) && Operands . size ( ) == 3 && static_cast < X86Operand * > ( Operands [ 1 ] ) -> isImm ( ) && isa < MCConstantExpr > ( static_cast < X86Operand * > ( Operands [ 1 ] ) -> getImm ( ) ) && cast < MCConstantExpr > ( static_cast < X86Operand * > ( Operands [ 1 ] ) -> getImm ( ) ) -> getValue ( ) == 1 ) { delete Operands [ 1 ] ; Operands . erase ( Operands . begin ( ) + 1 ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .


<s> int arc_label_align ( rtx_insn * label ) { if ( align_labels . levels [ 0 ] . log < 1 ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( INSN_P ( next ) && recog_memoized ( next ) >= 0 ) return 1 ; } return align_labels . levels [ 0 ] . log ; } </s>

Oddly enough , sometimes we get a zero overhead loop that branch shortening does n't think is a loop - observed with compile/pr24883.c -O3 -fomit-frame-pointer -funroll-loops . Make sure to include the alignment visible for branch shortening ( we actually align the loop insn before it , but that is equivalent since the loop insn is 4 byte long . )


<s> void MSP430AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MSP430MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static int tilegx_pic_address_needs_scratch ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF ) && ( CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) return true ; return false ; } </s>

Return true if X requires a scratch register . It is given that flag_pic is on and that X satisfies CONSTANT_P .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s>
SDValue
F2003fTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s>
static
tree
rs6000_handle_struct_attribute
(
tree
*
node
,
tree
name
,
tree
args
ATTRIBUTE_UNUSED
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
tree
*
type
=
;
if
(
DECL_P
(
*
node
)
)
{
if
(
TREE_CODE
(
*
node
)
==
TYPE_DECL
)
type
=
&
TREE_TYPE
(
*
node
)
;
}
else
type
=
node
;
if
(
!
(
type
&&
(
TREE_CODE
(
*
type
)
==
RECORD_TYPE
||
TREE_CODE
(
*
type
)
==
UNION_TYPE
)
)
)
{
warning
(
OPT_Wattributes
,
"%qE attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
else
if
(
(
is_attribute_p
(
"ms_struct"
,
name
)
&&
lookup_attribute
(
"gcc_struct"
,
TYPE_ATTRIBUTES
(
*
type
)
)
)
||
(
(
is_attribute_p
(
"gcc_struct"
,
name
)
&&
lookup_attribute
(
"ms_struct"
,
TYPE_ATTRIBUTES
(
*
type
)
)
)
)
)
{
warning
(
OPT_Wattributes
,
"%qE incompatible attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle a `` ms_struct '' or `` gcc_struct '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool CAHPAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static void mips16_copy_fpr_return_value ( void ) { rtx fn , insn , retval ; tree return_type ; machine_mode return_mode ; const char * name ; return_type = DECL_RESULT ( current_function_decl ) ; return_mode = DECL_MODE ( return_type ) ; name = ACONCAT ( ( "__mips16_ret_" , mips16_call_stub_mode_suffix ( return_mode ) , NULL ) ) ; fn = mips16_stub_function ( name ) ; SYMBOL_REF_FLAGS ( fn ) |= SYMBOL_FLAG_BIND_NOW ; retval = gen_rtx_REG ( return_mode , GP_RETURN ) ; insn = mips_expand_call ( MIPS_CALL_EPILOGUE , retval , fn , const0_rtx , NULL_RTX , false ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , retval ) ; } </s>

The current function is a MIPS16 function that returns a value in an FPR . Copy the return value from its soft-float to its hard-float location . libgcc2 has special non-MIPS16 helper functions for each case .


<s> bool aarch64_pad_reg_upward ( machine_mode mode , const_tree type , bool first ATTRIBUTE_UNUSED ) { if ( BYTES_BIG_ENDIAN && aarch64_composite_type_p ( type , mode ) ) { HOST_WIDE_INT size = ( type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; if ( size < 2 * UNITS_PER_WORD ) return true ; } return ! BYTES_BIG_ENDIAN ; } </s>

Similarly , for use by BLOCK_REG_PADDING ( MODE , TYPE , FIRST ) . It specifies padding for the last ( may also be the only ) element of a block move between registers and memory . If assuming the block is in the memory , padding upward means that the last element is padded after its highest significant byte , while in downward padding , the last element is padded at the its least significant byte side . Small aggregates and small complex types are always padded upwards . We do n't need to worry about homogeneous floating-point or short-vector aggregates ; their move is not affected by the padding direction determined here . Regardless of endianness , each element of such an aggregate is put in the least significant bits of a fp/simd register . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data , and return the opposite if the most significant byte does .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool SITargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; return TII -> isInlineConstant ( Imm ) ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> static bool ix86_use_mask_cmp_p ( machine_mode mode , machine_mode cmp_mode , rtx op_true , rtx op_false ) { if ( GET_MODE_SIZE ( mode ) == 64 ) return true ; gcc_assert ( ! op_true == ! op_false ) ; if ( ! op_true || ! ix86_valid_mask_cmp_mode ( cmp_mode ) ) return false ; if ( op_false == CONST0_RTX ( mode ) || op_true == CONST0_RTX ( mode ) || ( INTEGRAL_MODE_P ( mode ) && ( op_true == CONSTM1_RTX ( mode ) || op_false == CONSTM1_RTX ( mode ) ) ) ) return false ; return true ; } </s>

Return true if integer mask comparison should be used .


<s> bool ARMFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) return false ; if ( MF . getInfo < ARMFunctionInfo > ( ) -> shouldSignReturnAddress ( false ) ) return false ; return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; bool Changed = false ; initialize ( MF ) ; if ( gatherVectorInstructions ( ) ) { formWebs ( ) ; recordUnoptimizableWebs ( ) ; markSwapsForRemoval ( ) ; Changed = removeSwaps ( ) ; } delete EC ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void eco32_option_override ( void ) { init_machine_status = eco32_init_machine_status ; } </s>

The TARGET_OPTION_OVERRIDE worker . All this curently does is set init_machine_status .


<s> unsigned PPCTTIImpl :: getNumberOfRegisters ( bool Vector ) { if ( Vector && ! ST -> hasAltivec ( ) && ! ST -> hasQPX ( ) ) return 0 ; return ST -> hasVSX ( ) ? 64 : 32 ; } </s>


<s>
static
bool
darwin_local_data_pic
(
rtx
disp
)
{
if
(
GET_CODE
(
disp
)
==
MINUS
)
{
if
(
GET_CODE
(
XEXP
(
disp
,
0
)
)
==
LABEL_REF
||
GET_CODE
(
XEXP
(
disp
,
0
)
)
==
SYMBOL_REF
)
if
(
GET_CODE
(
XEXP
(
disp
,
1
)
)
==
SYMBOL_REF
)
{
const
char
*
sym_name
=
XSTR
(
XEXP
(
disp
,
1
)
,
0
)
;
if
(
!
strcmp
(
sym_name
,
"<pic base>"
)
)
return
true
;
}
}
return
false
;
}
</s>

Allow { LABEL | SYMBOL } _REF - SYMBOL_REF-FOR-PICBASE for Mach-O as this is used for to form addresses to local data when -fPIC is in use .


<s> enum machine_mode ix86_fp_compare_mode ( enum rtx_code code ATTRIBUTE_UNUSED ) { return TARGET_IEEE_FP ? CCFPUmode : CCFPmode ; } </s>

Figure out whether to use ordered or unordered fp comparisons . Return the appropriate mode to use .


<s>
bool
TeakRegisterInfo
::
shouldCoalesce
(
MachineInstr
*
MI
,
const
TargetRegisterClass
*
SrcRC
,
unsigned
SubReg
,
const
TargetRegisterClass
*
DstRC
,
unsigned
DstSubReg
,
const
TargetRegisterClass
*
NewRC
,
LiveIntervals
&
LIS
)
const
{
dbgs
(
)
<<
"shouldCoalesce\n"
;
MI
->
dump
(
)
;
dbgs
(
)
<<
"SrcRC: "
<<
SrcRC
->
getID
(
)
<<
"\n"
;
dbgs
(
)
<<
"SubReg: "
<<
SubReg
<<
"\n"
;
dbgs
(
)
<<
"DstRC: "
<<
DstRC
->
getID
(
)
<<
"\n"
;
dbgs
(
)
<<
"DstSubReg: "
<<
DstSubReg
<<
"\n"
;
dbgs
(
)
<<
"NewRC: "
<<
NewRC
->
getID
(
)
<<
"\n"
;
return
true
;
}
</s>

Teak
Teak
"shouldCoalesce\n"
"SrcRC: "
"\n"
"SubReg: "
"\n"
"DstRC: "
"\n"
"DstSubReg: "
"\n"
"NewRC: "
"\n"


<s> const ARMRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> EVT X86TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget -> hasAVX512 ( ) ? MVT :: i1 : MVT :: i8 ; const unsigned NumElts = VT . getVectorNumElements ( ) ; const EVT EltVT = VT . getVectorElementType ( ) ; if ( VT . is512BitVector ( ) ) { if ( Subtarget -> hasAVX512 ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; } if ( Subtarget -> hasBWI ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 32 : return MVT :: v32i1 ; case 64 : return MVT :: v64i1 ; } } if ( VT . is256BitVector ( ) || VT . is128BitVector ( ) ) { if ( Subtarget -> hasVLX ( ) ) if ( EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) switch ( NumElts ) { case 2 : return MVT :: v2i1 ; case 4 : return MVT :: v4i1 ; case 8 : return MVT :: v8i1 ; } if ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) ) if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 ) switch ( NumElts ) { case 8 : return MVT :: v8i1 ; case 16 : return MVT :: v16i1 ; case 32 : return MVT :: v32i1 ; } } return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool shouldTrackPressure ( ) const override { return false ; } </s>

PostRA scheduling does not track pressure .


<s> static rtx construct_plt_address ( rtx symbol ) { rtx tmp , unspec ; gcc_assert ( GET_CODE ( symbol ) == SYMBOL_REF ) ; gcc_assert ( ix86_cmodel == CM_LARGE_PIC && ! TARGET_PECOFF ) ; gcc_assert ( Pmode == DImode ) ; tmp = gen_reg_rtx ( Pmode ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , symbol ) , UNSPEC_PLTOFF ) ; emit_move_insn ( tmp , gen_rtx_CONST ( Pmode , unspec ) ) ; emit_insn ( gen_add2_insn ( tmp , pic_offset_table_rtx ) ) ; return tmp ; } </s>

For given symbol ( function ) construct code to compute address of it 's PLT entry in large x86-64 PIC model .


<s> static void mn10300_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> nbytes += ( arg . promoted_size_in_bytes ( ) + 3 ) & ~ 3 ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> bool HexagonAsmParser :: isLabel ( AsmToken & Token ) { MCAsmLexer & Lexer = getLexer ( ) ; AsmToken const & Second = Lexer . getTok ( ) ; AsmToken Third = Lexer . peekTok ( ) ; StringRef String = Token . getString ( ) ; if ( Token . is ( AsmToken :: TokenKind :: LCurly ) || Token . is ( AsmToken :: TokenKind :: RCurly ) ) return false ; if ( String . lower ( ) == "vwhist256" && Second . is ( AsmToken :: Colon ) && Third . getString ( ) . lower ( ) == "sat" ) return false ; if ( ! Token . is ( AsmToken :: TokenKind :: Identifier ) ) return true ; if ( ! matchRegister ( String . lower ( ) ) ) return true ; assert ( Second . is ( AsmToken :: Colon ) ) ; StringRef Raw ( String . data ( ) , Third . getString ( ) . data ( ) - String . data ( ) + Third . getString ( ) . size ( ) ) ; std :: string Collapsed = std :: string ( Raw ) ; Collapsed . erase ( llvm :: remove_if ( Collapsed , isspace ) , Collapsed . end ( ) ) ; StringRef Whole = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = Whole . split ( '.' ) ; if ( ! matchRegister ( DotSplit . first . lower ( ) ) ) return true ; return false ; } </s>

Returns true if the MachineInstr represents a label .


<s> void rs6000_emit_le_vsx_move ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || SUBREG_P ( dest ) ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ; rs6000_emit_le_vsx_store ( dest , source , mode ) ; } } </s>

Emit a sequence representing a little-endian VSX load or store , moving data from SOURCE to DEST in mode MODE . This is done separately from rs6000_emit_move to ensure it is called only during expand . LE VSX loads and stores introduced later are handled with a split . The expand-time RTL generation allows us to optimize away redundant pairs of register-permutes .


<s> char c6x_get_unit_specifier ( rtx_insn * insn ) { enum attr_units units ; if ( insn_info . exists ( ) ) { int unit = INSN_INFO_ENTRY ( INSN_UID ( insn ) ) . reservation ; return c6x_unit_names [ unit ] [ 0 ] ; } units = get_attr_units ( insn ) ; switch ( units ) { case UNITS_D : case UNITS_DL : case UNITS_DS : case UNITS_DLS : case UNITS_D_ADDR : return 'd' ; break ; case UNITS_L : case UNITS_LS : return 'l' ; break ; case UNITS_S : return 's' ; break ; case UNITS_M : return 'm' ; break ; default : gcc_unreachable ( ) ; } } </s>

Return a single character , which is either ' l ' , 's ' , 'd ' or 'm ' , which specifies the functional unit used by INSN .


<s> static bool aarch64_mode_valid_for_sched_fusion_p ( machine_mode mode ) { return mode == SImode || mode == DImode || mode == SFmode || mode == DFmode || ( aarch64_vector_mode_supported_p ( mode ) && known_eq ( GET_MODE_SIZE ( mode ) , 8 ) ) ; } </s>

Return true if MODE is one of the modes for which we support LDP/STP operations .


<s> static bool contains_string_p ( const char * * arr , const char * str ) { bool res = false ; if ( arr [ 0 ] != NULL ) { res = strstr ( arr [ 0 ] , str ) != NULL ; if ( res ) return res ; if ( arr [ 1 ] != NULL ) return strstr ( arr [ 1 ] , str ) != NULL ; } return false ; } </s>

Return true iff ARR contains STR in one of its two elements .


<s> static int calc_live_regs ( int * count ) { int reg ; int live_regs_mask = 0 ; * count = 0 ; for ( reg = 0 ; reg < FIRST_PSEUDO_REGISTER ; reg ++ ) { if ( df_regs_ever_live_p ( reg ) && ! call_used_or_fixed_reg_p ( reg ) ) { ( * count ) ++ ; live_regs_mask |= ( 1 << reg ) ; } } return live_regs_mask ; } </s>

Work out the registers which need to be saved , both as a mask and a count


<s> bool LanaiRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> unsigned AVRAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned ExpectedKind ) { AVROperand & Op = static_cast < AVROperand & > ( AsmOp ) ; MatchClassKind Expected = static_cast < MatchClassKind > ( ExpectedKind ) ; if ( Op . isImm ( ) ) { if ( MCConstantExpr const * Const = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) { int64_t RegNum = Const -> getValue ( ) ; std :: ostringstream RegName ; RegName << "r" << RegNum ; RegNum = MatchRegisterName ( RegName . str ( ) . c_str ( ) ) ; if ( RegNum != AVR :: NoRegister ) { Op . makeReg ( RegNum ) ; if ( validateOperandClass ( Op , Expected ) == Match_Success ) { return Match_Success ; } } } } if ( Op . isReg ( ) ) { if ( isSubclass ( Expected , MCK_DREGS ) ) { unsigned correspondingDREG = toDREG ( Op . getReg ( ) ) ; if ( correspondingDREG != AVR :: NoRegister ) { Op . makeReg ( correspondingDREG ) ; return validateOperandClass ( Op , Expected ) ; } } } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

AVR AVR AVR AVR "r" AVR::NoRegister AVR::NoRegister


<s> std :: pair < unsigned , const TargetRegisterClass * > ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb1Only ( ) ) return std :: make_pair ( 0U , ARM :: tGPRRegisterClass ) ; else return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'r' : return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , ARM :: DPRRegisterClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static void print_shift_count_operand ( FILE * file , rtx op ) { HOST_WIDE_INT offset ; rtx base ; if ( ! s390_decompose_shift_count ( op , & base , & offset ) ) gcc_unreachable ( ) ; if ( base ) { gcc_assert ( GET_CODE ( base ) == REG ) ; gcc_assert ( REGNO ( base ) < FIRST_PSEUDO_REGISTER ) ; gcc_assert ( REGNO_REG_CLASS ( REGNO ( base ) ) == ADDR_REGS ) ; } fprintf ( file , HOST_WIDE_INT_PRINT_DEC , offset & ( ( 1 << 12 ) - 1 ) ) ; if ( base ) fprintf ( file , "(%s)" , reg_names [ REGNO ( base ) ] ) ; } </s>

Output operand OP to stdio stream FILE . OP is an address ( register + offset ) which is not used to address data ; instead the rightmost bits are interpreted as the value .


<s> static int num_insns_constant_gpr ( HOST_WIDE_INT value ) { if ( ( ( unsigned HOST_WIDE_INT ) value + 0x8000 ) < 0x10000 ) return 1 ; else if ( ( value & 0xffff ) == 0 && ( value >> 31 == - 1 || value >> 31 == 0 ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = ( ( value & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 ) return num_insns_constant_gpr ( high ) + 1 ; else if ( high == 0 ) return num_insns_constant_gpr ( low ) + 1 ; else return ( num_insns_constant_gpr ( high ) + num_insns_constant_gpr ( low ) + 1 ) ; } else return 2 ; } </s>

Helper for num_insns_constant . Calculate number of instructions to load VALUE to a single gpr using combinations of addi , addis , ori , oris , sldi and rldimi instructions .


<s> static rtx nvptx_expand_builtin ( tree exp , rtx target , rtx ARG_UNUSED ( subtarget ) , machine_mode mode , int ignore ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case NVPTX_BUILTIN_SHUFFLE : case NVPTX_BUILTIN_SHUFFLELL : return nvptx_expand_shuffle ( exp , target , mode , ignore ) ; case NVPTX_BUILTIN_WORKER_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , false ) ; case NVPTX_BUILTIN_VECTOR_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , true ) ; case NVPTX_BUILTIN_CMP_SWAP : case NVPTX_BUILTIN_CMP_SWAPLL : return nvptx_expand_cmp_swap ( exp , target , mode , ignore ) ; default : gcc_unreachable ( ) ; } } </s>

Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s> static void mips_save_reg ( rtx reg , rtx mem ) { if ( GET_MODE ( reg ) == DFmode && ( ! TARGET_FLOAT64 || mips_abi == ABI_32 ) ) { rtx x1 , x2 ; mips_emit_move_or_split ( mem , reg , SPLIT_IF_NECESSARY ) ; x1 = mips_frame_set ( mips_subword ( mem , false ) , mips_subword ( reg , false ) ) ; x2 = mips_frame_set ( mips_subword ( mem , true ) , mips_subword ( reg , true ) ) ; mips_set_frame_expr ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x1 , x2 ) ) ) ; } else mips_emit_save_slot_move ( mem , reg , MIPS_PROLOGUE_TEMP ( GET_MODE ( reg ) ) ) ; } </s>

Save register REG to MEM . Make the instruction frame-related .


<s> void OR1KAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void nvptx_goacc_reduction_teardown ( gcall * call ) { gimple_stmt_iterator gsi = gsi_for_stmt ( call ) ; tree lhs = gimple_call_lhs ( call ) ; tree var = gimple_call_arg ( call , 2 ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , 3 ) ) ; gimple_seq seq = NULL ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_WORKER ) { tree offset = gimple_call_arg ( call , 5 ) ; tree call = nvptx_get_worker_red_addr ( TREE_TYPE ( var ) , offset ) ; tree ptr = make_ssa_name ( TREE_TYPE ( call ) ) ; gimplify_assign ( ptr , call , & seq ) ; var = build_simple_mem_ref ( ptr ) ; TREE_THIS_VOLATILE ( var ) = 1 ; } if ( level != GOMP_DIM_GANG ) { tree ref_to_res = gimple_call_arg ( call , 1 ) ; if ( ! integer_zerop ( ref_to_res ) ) gimplify_assign ( build_simple_mem_ref ( ref_to_res ) , var , & seq ) ; } if ( lhs ) gimplify_assign ( lhs , var , & seq ) ; pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( & gsi , seq , true ) ; } </s>

NVPTX implementation of GOACC_REDUCTION_TEARDOWN .


<s> void LEGDAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode ( ) ) { case ISD :: Constant : SelectMoveImmediate ( N ) ; return ; case ISD :: BR_CC : SelectConditionalBranch ( N ) ; return ; } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> const char * arc_short_long ( rtx_insn * insn , const char * s_tmpl , const char * l_tmpl ) { int is_short = arc_verify_short ( insn , cfun -> machine -> unalign , - 1 ) ; extract_constrain_insn_cached ( insn ) ; return is_short ? s_tmpl : l_tmpl ; } </s>

Select between the instruction output templates s_tmpl ( for short INSNs ) and l_tmpl ( for long INSNs ) .


"Cannot load this register from a stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> static bool isShift ( MachineInstr * MI , int Opcode , int64_t Imm ) { return ( MI -> getOpcode ( ) == Opcode && ! MI -> getOperand ( 2 ) . getReg ( ) && MI -> getOperand ( 3 ) . getImm ( ) == Imm ) ; } </s>

Determine if the Opcode is one of the shift instructions .


<s>
unsigned
LC2200InstrInfo
::
loadImmediate
(
unsigned
FrameReg
,
int64_t
Imm
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
II
,
const
DebugLoc
&
DL
,
unsigned
&
NewImm
)
const
{
llvm_unreachable
(
"not yet implemented loadImmediate()"
)
;
}
</s>

Emit a series of instructions to load an immediate .


<s> void AArch64Subtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , unsigned NumRegionInstrs ) const { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; Policy . DisableLatencyHeuristic = DisableLatencySchedHeuristic ; } </s>

Override generic scheduling policy within a region .


<s>
SDValue
rvexTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
DEBUG
(
errs
(
)
<<
"I am here!\n"
)
;
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

rvex
rvex
"I am here!\n"
"Don't know how to custom lower this!"
ISD::GlobalAddress


<s> unsigned PPCTTIImpl :: getCacheLineSize ( ) { if ( CacheLineSize . getNumOccurrences ( ) > 0 ) return CacheLineSize ; unsigned Directive = ST -> getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 ) return 128 ; return 64 ; } </s>

Return the target cache line size in bytes .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> int direct_return ( ) { if ( ! reload_completed ) return FALSE ; if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; return current_frame_info . total_size == 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> void flushPendingInstructions ( MCStreamer & Out ) override { if ( ! inImplicitITBlock ( ) ) { assert ( PendingConditionalInsts . size ( ) == 0 ) ; return ; } unsigned Mask = getITMaskEncoding ( ) ; MCInst ITInst ; ITInst . setOpcode ( ARM :: t2IT ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Cond ) ) ; ITInst . addOperand ( MCOperand :: createImm ( Mask ) ) ; Out . EmitInstruction ( ITInst , getSTI ( ) ) ; assert ( PendingConditionalInsts . size ( ) <= 4 ) ; for ( const MCInst & Inst : PendingConditionalInsts ) { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } PendingConditionalInsts . clear ( ) ; ITState . Mask = 0 ; ITState . CurPosition = ~ 0U ; } </s>

Ensure that all previously parsed instructions have been emitted to the output streamer , if the target does not emit them immediately .


<s> static void c6x_asm_emit_except_personality ( rtx personality ) { fputs ( "\t.personality\t" , asm_out_file ) ; output_addr_const ( asm_out_file , personality ) ; fputc ( '\n' , asm_out_file ) ; } </s>


<s> bool isMem ( ) const override { return isMemImm ( ) || isMemRegImm ( ) || isMemRegReg ( ) ; } </s>


<s> FastISel * AArch64 :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { return new AArch64FastISel ( FuncInfo , LibInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> static bool nios2_symbol_ref_in_r0rel_data_p ( rtx sym ) { tree decl ; gcc_assert ( GET_CODE ( sym ) == SYMBOL_REF ) ; decl = SYMBOL_REF_DECL ( sym ) ; if ( SYMBOL_REF_TLS_MODEL ( sym ) != 0 ) return false ; if ( TARGET_ARCH_R2 && ( TARGET_BYPASS_CACHE || TARGET_BYPASS_CACHE_VOLATILE ) ) return false ; if ( decl && DECL_SECTION_NAME ( decl ) ) return nios2_r0rel_section_name_p ( DECL_SECTION_NAME ( decl ) ) ; return false ; } </s>


<s>
bool
PTXMFInfoExtract
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
PTXMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
PTXMachineFunctionInfo
>
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
i
=
0
;
i
<
MRI
.
getNumVirtRegs
(
)
;
++
i
)
{
unsigned
Reg
=
TargetRegisterInfo
::
index2VirtReg
(
i
)
;
const
TargetRegisterClass
*
TRC
=
MRI
.
getRegClass
(
Reg
)
;
unsigned
RegType
;
if
(
TRC
==
PTX
::
RegPredRegisterClass
)
RegType
=
PTXRegisterType
::
Pred
;
else
if
(
TRC
==
PTX
::
RegI16RegisterClass
)
RegType
=
PTXRegisterType
::
B16
;
else
if
(
TRC
==
PTX
::
RegI32RegisterClass
)
RegType
=
PTXRegisterType
::
B32
;
else
if
(
TRC
==
PTX
::
RegI64RegisterClass
)
RegType
=
PTXRegisterType
::
B64
;
else
if
(
TRC
==
PTX
::
RegF32RegisterClass
)
RegType
=
PTXRegisterType
::
F32
;
else
if
(
TRC
==
PTX
::
RegF64RegisterClass
)
RegType
=
PTXRegisterType
::
F64
;
else
llvm_unreachable
(
"Unkown register class."
)
;
MFI
->
addRegister
(
Reg
,
RegType
,
PTXRegisterSpace
::
Reg
)
;
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool SparcTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createSparcFPMoverPass ( * this ) ) ; PM . add ( createSparcDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool contains ( uint16_t A , uint16_t B ) { if ( type ( A ) != Code ) return false ; uint16_t KB = kind ( B ) ; switch ( kind ( A ) ) { case Func : return KB == Block ; case Block : return KB == Phi || KB == Stmt ; case Phi : case Stmt : return type ( B ) == Ref ; } return false ; } </s>

contains - Returns true if this trace contains the given basic block .


<s> static bool isUnconditionalBranch ( unsigned int Opcode ) { switch ( Opcode ) { default : return false ; case Mips :: Bimm16 : case Mips :: BimmX16 : case Mips :: JalB16 : return true ; } } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool IsBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> int m32c_expand_cmpstr ( rtx * operands ) { rtx src1a , src2a ; src1a = XEXP ( operands [ 1 ] , 0 ) ; src2a = XEXP ( operands [ 2 ] , 0 ) ; if ( GET_CODE ( src1a ) != REG || REGNO ( src1a ) < FIRST_PSEUDO_REGISTER ) src1a = copy_to_mode_reg ( Pmode , src1a ) ; if ( GET_CODE ( src2a ) != REG || REGNO ( src2a ) < FIRST_PSEUDO_REGISTER ) src2a = copy_to_mode_reg ( Pmode , src2a ) ; emit_insn ( gen_cmpstrhi_op ( src1a , src2a , src1a , src2a ) ) ; emit_insn ( gen_cond_to_int ( operands [ 0 ] ) ) ; return 1 ; } </s>

This is a strcmp ( ) opcode . $ 0 is the destination ( HI ) which holds < = > 0 depending on the comparison , $ 1 is one string ( MEM : BLK ) , and $ 2 is the other ( MEM : BLK ) . We must do the comparison , and then convert the flags to a signed integer result .


<s> bool AlphaFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void HexagonPassConfig :: addPreEmitPass ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonNewValueJump ( ) , false ) ; addPass ( createHexagonExpandPredSpillCode ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( createHexagonFixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( createHexagonGenMux ( ) , false ) ; addPass ( createHexagonPacketizer ( ) , false ) ; } } </s>

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> Align X86TargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { if ( ML -> isInnermost ( ) && ExperimentalPrefInnermostLoopAlignment . getNumOccurrences ( ) ) return Align ( 1ULL << ExperimentalPrefInnermostLoopAlignment ) ; return TargetLowering :: getPrefLoopAlignment ( ) ; } </s>


"FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD "

"instructions with NOPs and floating-point store"

getPassName - Return a nice clean name for a pass .


<s> bool sh_dynamicalize_shift_p ( rtx count ) { gcc_assert ( CONST_INT_P ( count ) ) ; const int shift_amount_i = std :: abs ( INTVAL ( count ) ) & 31 ; int insn_count ; if ( shift_amount_i == 31 ) insn_count = 2 ; else insn_count = ashl_lshr_seq [ shift_amount_i ] . insn_count ; return TARGET_DYNSHIFT && ( insn_count > 1 + SH_DYNAMIC_SHIFT_COST ) ; } </s>

Return true if it is potentially beneficial to use a dynamic shift instruction ( shad / shar ) instead of a combination of 1/2/8/16 shift instructions for the specified shift count . If dynamic shifts are not available , always return false .


<s> bool ARMTargetLowering :: shouldAlignPointerArgs ( CallInst * CI , unsigned & MinSize , unsigned & PrefAlign ) const { if ( ! isa < MemIntrinsic > ( CI ) ) return false ; MinSize = 8 ; PrefAlign = ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isMClass ( ) ? 8 : 4 ) ; return true ; } </s>

Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed .


"Cannot handle this call frame pseudo instruction"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
StringRef
getPassName
(
)
const
override
{
return
"R600 Vector Registers Merge Pass"
;
}
</s>

AMDGPU
"R600 Vector Registers Merge Pass"


Return an array that contains the direct target flag values and their names .


<s> int easy_di_const ( rtx op ) { rtx high_rtx , low_rtx ; HOST_WIDE_INT high , low ; split_double ( op , & high_rtx , & low_rtx ) ; high = INTVAL ( high_rtx ) ; low = INTVAL ( low_rtx ) ; if ( high >= - 128 && high <= 127 && low >= - 128 && low <= 127 ) return 1 ; return 0 ; } </s>

Return 1 if OP is a DImode const we want to handle inline . This must match the code in the movdi pattern . It is used by the ' G ' CONST_DOUBLE_OK_FOR_LETTER .


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
DebugLoc
&
dl
=
CLI
.
DL
;
SmallVector
<
ISD
::
OutputArg
,
32
>
&
Outs
=
CLI
.
Outs
;
SmallVector
<
SDValue
,
32
>
&
OutVals
=
CLI
.
OutVals
;
SmallVector
<
ISD
::
InputArg
,
32
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> bool WebAssembly :: mayThrow ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: THROW : case WebAssembly :: THROW_S : case WebAssembly :: RETHROW : case WebAssembly :: RETHROW_S : return true ; } if ( isCallIndirect ( MI . getOpcode ( ) ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = getCalleeOp ( MI ) ; assert ( MO . isGlobal ( ) || MO . isSymbol ( ) ) ; if ( MO . isSymbol ( ) ) { const char * Name = MO . getSymbolName ( ) ; if ( strcmp ( Name , "memcpy" ) == 0 || strcmp ( Name , "memmove" ) == 0 || strcmp ( Name , "memset" ) == 0 ) return false ; return true ; } const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) return true ; if ( F -> doesNotThrow ( ) ) return false ; if ( F -> getName ( ) == CxaBeginCatchFn || F -> getName ( ) == PersonalityWrapperFn || F -> getName ( ) == ClangCallTerminateFn || F -> getName ( ) == StdTerminateFn ) return false ; return true ; } </s>

Return true if this instruction may throw an exception .


"calling %qD with SSE calling convention without "

"this is a GCC bug that can be worked around by adding "

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


"not supported with %<-mabi=ti%> option"

Callback for walk_gimple_seq that checks TP tree for TI ABI compliance .


<s> void rs6000_emit_le_vsx_permute ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! altivec_indexed_or_indirect_operand ( dest , mode ) ) ; gcc_assert ( ! altivec_indexed_or_indirect_operand ( source , mode ) ) ; if ( FLOAT128_VECTOR_P ( mode ) ) { dest = gen_lowpart ( V1TImode , dest ) ; source = gen_lowpart ( V1TImode , source ) ; mode = V1TImode ; } if ( mode == TImode || mode == V1TImode ) emit_insn ( gen_rtx_SET ( dest , gen_rtx_ROTATE ( mode , source , GEN_INT ( 64 ) ) ) ) ; else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_VEC_SELECT ( mode , source , par ) ) ) ; } } </s>

Emit an lxvd2x , stxvd2x , or xxpermdi instruction for a VSX load or store operation .


<s> static void rs6000_darwin64_record_arg_recurse ( CUMULATIVE_ARGS * cum , const_tree type , HOST_WIDE_INT startbitpos , rtx rvec [ ] , int * k ) { tree f ; for ( f = TYPE_FIELDS ( type ) ; f ; f = DECL_CHAIN ( f ) ) if ( TREE_CODE ( f ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; tree ftype = TREE_TYPE ( f ) ; machine_mode mode ; if ( ftype == error_mark_node ) continue ; mode = TYPE_MODE ( ftype ) ; if ( DECL_SIZE ( f ) != 0 && tree_fits_uhwi_p ( bit_position ( f ) ) ) bitpos += int_bit_position ( f ) ; if ( TREE_CODE ( ftype ) == RECORD_TYPE ) rs6000_darwin64_record_arg_recurse ( cum , ftype , bitpos , rvec , k ) ; else if ( cum -> named && USE_FP_FOR_ARG_P ( cum , mode ) ) { unsigned n_fpreg = ( GET_MODE_SIZE ( mode ) + 7 ) >> 3 ; switch ( mode ) { case E_SCmode : mode = SFmode ; break ; case E_DCmode : mode = DFmode ; break ; case E_TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; if ( cum -> fregno + n_fpreg > FP_ARG_MAX_REG + 1 ) { gcc_assert ( cum -> fregno == FP_ARG_MAX_REG && ( mode == TFmode || mode == TDmode ) ) ; mode = DECIMAL_FLOAT_MODE_P ( mode ) ? DDmode : DFmode ; cum -> use_stack = 1 ; } rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( FLOAT128_2REG_P ( mode ) ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , 1 ) ) { rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> vregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; } else if ( cum -> intoffset == - 1 ) cum -> intoffset = bitpos ; } } </s>


<s> const MCExpr * MipsTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( 0x8000 , getContext ( ) ) , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> static rtx avr_function_value ( const_tree type , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { unsigned int offs ; if ( TYPE_MODE ( type ) != BLKmode ) return avr_libcall_value ( TYPE_MODE ( type ) , NULL_RTX ) ; offs = int_size_in_bytes ( type ) ; if ( offs < 2 ) offs = 2 ; if ( offs > 2 && offs < GET_MODE_SIZE ( SImode ) ) offs = GET_MODE_SIZE ( SImode ) ; else if ( offs > GET_MODE_SIZE ( SImode ) && offs < GET_MODE_SIZE ( DImode ) ) offs = GET_MODE_SIZE ( DImode ) ; return gen_rtx_REG ( BLKmode , avr_ret_register ( ) + 2 - offs ) ; } </s>

Create an RTX representing the place where a function returns a value of data type VALTYPE .


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return Hexagon :: R1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


Check whether or not the given MBB can be used as a epilogue for the target .


<s> void PPCTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { if ( ST -> getMcpu ( ) == PPC :: MCPU_A2 ) { UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount = true ; } BaseT :: getUnrollingPreferences ( L , SE , UP ) ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved < StackProtector > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> rtx alpha_gp_save_rtx ( void ) { rtx_insn * seq ; rtx m = cfun -> machine -> gp_save_rtx ; if ( m == NULL ) { start_sequence ( ) ; m = assign_stack_local ( DImode , UNITS_PER_WORD , BITS_PER_WORD ) ; m = validize_mem ( m ) ; emit_move_insn ( m , pic_offset_table_rtx ) ; seq = get_insns ( ) ; end_sequence ( ) ; insert_insn_on_edge ( seq , single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ) ; cfun -> machine -> gp_save_rtx = m ; } return m ; } </s>

Return or create a pseudo containing the gp value for the current function . Needed only if TARGET_LD_BUGGY_LDGP .


<s> const uint32_t * SystemZRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_SystemZ_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_SystemZ_AllRegs_Vector_RegMask : CSR_SystemZ_AllRegs_RegMask ; if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_RegMask ; return CSR_SystemZ_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s>
void
AlphaInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DestReg
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
if
(
RC
==
Alpha
::
F4RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
LDS
)
,
DestReg
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
F8RCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
LDT
)
,
DestReg
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
if
(
RC
==
Alpha
::
GPRCRegisterClass
)
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Alpha
::
LDQ
)
,
DestReg
)
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
Alpha
::
F31
)
;
else
llvm_unreachable
(
"Unhandled register class"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> const LatticeCell & get ( unsigned R ) const { if ( ! Register :: isVirtualRegister ( R ) ) return Bottom ; MapType :: const_iterator F = Map . find ( R ) ; if ( F != Map . end ( ) ) return F -> second ; return Top ; } </s>

Get the generated Value for a given VPValue and given Part and Lane .


<s> static rtx s390_execute_label ( rtx insn ) { if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == PARALLEL && GET_CODE ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) ) == UNSPEC && XINT ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 1 ) == UNSPEC_EXECUTE ) return XVECEXP ( XVECEXP ( PATTERN ( insn ) , 0 , 0 ) , 0 , 2 ) ; return NULL_RTX ; } </s>

Check whether INSN is an execute . Return the label_ref to its execute target template if so , NULL_RTX otherwise .


<s> static void nds32_emit_stack_v3pop ( rtx Rb , rtx Re , rtx En4 ATTRIBUTE_UNUSED , rtx imm8u ) { int regno ; int num_use_regs ; int par_index ; int offset ; rtx reg ; rtx mem ; rtx pop_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; rtx dwarf = NULL_RTX ; num_use_regs = REGNO ( Re ) - REGNO ( Rb ) + 1 + 3 ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + 1 ) ) ; par_index = 0 ; offset = 0 ; for ( regno = REGNO ( Rb ) ; regno <= ( int ) REGNO ( Re ) ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( VOIDmode , reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( VOIDmode , reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( VOIDmode , reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( VOIDmode , reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; adjust_sp_rtx = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset + INTVAL ( imm8u ) ) ) ; XVECEXP ( parallel_insn , 0 , par_index ) = adjust_sp_rtx ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , copy_rtx ( adjust_sp_rtx ) , dwarf ) ; parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = 1 ; REG_NOTES ( parallel_insn ) = dwarf ; } </s>

Function to create a parallel rtx pattern which presents stack v3pop behavior . The overall concept are : `` pop registers from memory '' , `` adjust stack pointer '' .


<s> static void tilegx_expand_unaligned_store ( rtx mem , rtx src , HOST_WIDE_INT bitsize , HOST_WIDE_INT bit_offset ) { HOST_WIDE_INT byte_offset = bit_offset / BITS_PER_UNIT ; HOST_WIDE_INT bytesize = bitsize / BITS_PER_UNIT ; HOST_WIDE_INT shift_init , shift_increment , shift_amt ; HOST_WIDE_INT i ; rtx mem_addr ; rtx store_val ; shift_init = BYTES_BIG_ENDIAN ? ( bitsize - BITS_PER_UNIT ) : 0 ; shift_increment = BYTES_BIG_ENDIAN ? - BITS_PER_UNIT : BITS_PER_UNIT ; for ( i = 0 , shift_amt = shift_init ; i < bytesize ; i ++ , shift_amt += shift_increment ) { mem_addr = adjust_address ( mem , QImode , byte_offset + i ) ; if ( shift_amt ) { store_val = expand_simple_binop ( DImode , LSHIFTRT , gen_lowpart ( DImode , src ) , GEN_INT ( shift_amt ) , NULL , 1 , OPTAB_LIB_WIDEN ) ; store_val = gen_lowpart ( QImode , store_val ) ; } else { store_val = gen_lowpart ( QImode , src ) ; } emit_move_insn ( mem_addr , store_val ) ; } } </s>


<s> void sparc_emit_membar_for_model ( enum memmodel model , int load_store , int before_after ) { const int LoadLoad = 1 ; const int StoreLoad = 2 ; const int LoadStore = 4 ; const int StoreStore = 8 ; int mm = 0 , implied = 0 ; switch ( sparc_memory_model ) { case SMM_SC : implied = LoadLoad | StoreLoad | LoadStore | StoreStore ; break ; case SMM_TSO : implied |= StoreStore ; if ( load_store == 3 && before_after == 1 ) implied |= StoreLoad ; case SMM_PSO : implied |= LoadLoad | LoadStore ; if ( load_store == 3 && before_after == 2 ) implied |= StoreLoad | StoreStore ; case SMM_RMO : break ; default : gcc_unreachable ( ) ; } if ( before_after & 1 ) { if ( model == MEMMODEL_RELEASE || model == MEMMODEL_ACQ_REL || model == MEMMODEL_SEQ_CST ) { if ( load_store & 1 ) mm |= LoadLoad | StoreLoad ; if ( load_store & 2 ) mm |= LoadStore | StoreStore ; } } if ( before_after & 2 ) { if ( model == MEMMODEL_ACQUIRE || model == MEMMODEL_ACQ_REL || model == MEMMODEL_SEQ_CST ) { if ( load_store & 1 ) mm |= LoadLoad | LoadStore ; if ( load_store & 2 ) mm |= StoreLoad | StoreStore ; } } mm &= ~ implied ; if ( mm || before_after == 3 ) emit_insn ( gen_membar ( GEN_INT ( mm ) ) ) ; } </s>

Expand a membar instruction for various use cases . Both the LOAD_STORE and BEFORE_AFTER arguments of the form X_Y . They are two-bit masks where bit 0 indicates that X is true , and bit 1 indicates Y is true .


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_TOCREL : gcc_checking_assert ( GET_CODE ( XVECEXP ( x , 0 , 0 ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , 0 , 1 ) ) && REGNO ( XVECEXP ( x , 0 , 1 ) ) == TOC_REGISTER ) ; output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; if ( x == tocrel_base_oac && tocrel_offset_oac != const0_rtx ) { if ( INTVAL ( tocrel_offset_oac ) >= 0 ) fprintf ( file , "+" ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset_oac ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = 1 ; } else if ( TARGET_ELF ) fputs ( "@toc" , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , 0 , 0 ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ; } </s>


<s> bool aarch64_regno_ok_for_base_p ( int regno , bool strict_p ) { if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; if ( ! reg_renumber ) return false ; regno = reg_renumber [ regno ] ; } return ( GP_REGNUM_P ( regno ) || regno == SP_REGNUM || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ; } </s>

Return true if register REGNO is a valid base register for mode MODE . STRICT_P is true if REG_OK_STRICT is in effect .


<s>
SDValue
TOYTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_TOY
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
TOYISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> rtx function_expander :: use_exact_insn ( insn_code icode ) { unsigned int nops = insn_data [ icode ] . n_operands ; if ( ! function_returns_void_p ( ) ) { add_output_operand ( icode ) ; nops -= 1 ; } for ( unsigned int i = 0 ; i < nops ; ++ i ) add_input_operand ( icode , args [ i ] ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , with a 1:1 mapping between arguments and input operands .


<s>
static
rtx
nds32_expand_builtin_null_ftype_reg_imm
(
enum
insn_code
icode
,
tree
exp
,
rtx
target
)
{
struct
expand_operand
ops
[
2
]
;
tree
arg0
,
arg1
;
rtx
value0
,
value1
;
arg0
=
CALL_EXPR_ARG
(
exp
,
0
)
;
arg1
=
CALL_EXPR_ARG
(
exp
,
1
)
;
value0
=
expand_normal
(
arg0
)
;
value1
=
expand_normal
(
arg1
)
;
create_input_operand
(
&
ops
[
0
]
,
value0
,
TYPE_MODE
(
TREE_TYPE
(
arg0
)
)
)
;
create_input_operand
(
&
ops
[
1
]
,
value1
,
TYPE_MODE
(
TREE_TYPE
(
arg1
)
)
)
;
if
(
!
maybe_expand_insn
(
icode
,
2
,
ops
)
)
error
(
"invalid argument to built-in function"
)
;
return
target
;
}
</s>

Function to expand builtin function for ' [ ( unspec_volatile [ ( reg ) ( imm ) ] ) ] ' pattern .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) || STI . isTargetWatchOS ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
Mips16InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
&&
Mips
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
MoveR3216
;
else
if
(
Mips
::
CPURegsRegClass
.
contains
(
DestReg
)
&&
Mips
::
CPU16RegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
Move32R16
;
else
if
(
(
SrcReg
==
Mips
::
HI
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mfhi16
,
SrcReg
=
0
;
else
if
(
(
SrcReg
==
Mips
::
LO
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mflo16
,
SrcReg
=
0
;
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> bool hasTailCall ( const MachineBasicBlock & MBB ) { MachineBasicBlock :: const_iterator I = MBB . getLastNonDebugInstr ( ) ; unsigned RetOpc = I -> getOpcode ( ) ; return RetOpc == Hexagon :: PS_tailcall_i || RetOpc == Hexagon :: PS_tailcall_r ; } </s>

Returns true if the function contains a tail call .


<s> static rtx function_value_32 ( machine_mode orig_mode , machine_mode mode , const_tree fntype , const_tree fn ) { unsigned int regno ; if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 8 ) regno = FIRST_MMX_REG ; else if ( mode == TImode || ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 16 ) ) regno = FIRST_SSE_REG ; else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 32 ) regno = FIRST_SSE_REG ; else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == 64 ) regno = FIRST_SSE_REG ; else if ( X87_FLOAT_MODE_P ( mode ) && TARGET_FLOAT_RETURNS_IN_80387 ) regno = FIRST_FLOAT_REG ; else regno = AX_REG ; if ( ( fn || fntype ) && ( mode == SFmode || mode == DFmode ) ) { int sse_level = ix86_function_sseregparm ( fntype , fn , false ) ; if ( ( sse_level >= 1 && mode == SFmode ) || ( sse_level == 2 && mode == DFmode ) ) regno = FIRST_SSE_REG ; } gcc_assert ( mode != OImode ) ; return gen_rtx_REG ( orig_mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 .


<s> bool hasAndNotCompare ( SDValue ) const override { return true ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


<s> PreservedAnalyses AMDGPUPropagateAttributesLatePass :: run ( Module & M , ModuleAnalysisManager & AM ) { return AMDGPUPropagateAttributes ( & TM , true ) . process ( M ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s>
void
SystemZInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32mr
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Pmr
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128mr
;
}
else
llvm_unreachable
(
"Unsupported regclass to store"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) -> getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_and_GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC::G8RC_and_G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> bool ARMBaseTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( ExpandMLx && OptLevel != CodeGenOpt :: None && Subtarget . hasVFP2 ( ) ) PM . add ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"binary operator does not support two vector bool operands"

"binary operator does not support vector bool operand"

"binary operator does not support mixing vector "

"bool with floating point vector operands"

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


<s> void MCS51AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { MCS51MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst I ; MCInstLowering . lowerInstruction ( * MI , I ) ; EmitToStreamer ( * OutStreamer , I ) ; } </s>

Targets should implement this to emit instructions .


"Thumb1 does not have ldr to high register"

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> bool nds32_expand_strlen ( rtx result , rtx str , rtx target_char , rtx align ATTRIBUTE_UNUSED ) { rtx base_reg , backup_base_reg ; rtx ffb_result ; rtx target_char_ptr , length ; rtx loop_label , tmp ; if ( optimize_size || optimize < 3 ) return false ; gcc_assert ( MEM_P ( str ) ) ; gcc_assert ( CONST_INT_P ( target_char ) || REG_P ( target_char ) ) ; base_reg = copy_to_mode_reg ( SImode , XEXP ( str , 0 ) ) ; loop_label = gen_label_rtx ( ) ; ffb_result = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( SImode ) ; backup_base_reg = gen_reg_rtx ( SImode ) ; emit_move_insn ( backup_base_reg , base_reg ) ; emit_label ( loop_label ) ; emit_insn ( gen_unaligned_load_update_base_w ( base_reg , tmp , base_reg ) ) ; emit_insn ( gen_unspec_ffb ( ffb_result , tmp , target_char ) ) ; emit_cmp_and_jump_insns ( ffb_result , const0_rtx , EQ , NULL , SImode , 1 , loop_label ) ; target_char_ptr = expand_binop ( Pmode , add_optab , base_reg , ffb_result , NULL_RTX , 0 , OPTAB_WIDEN ) ; length = expand_binop ( Pmode , sub_optab , target_char_ptr , backup_base_reg , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_move_insn ( result , length ) ; return true ; } </s>

Auxiliary function for expand strlen pattern .


<s> static bool aarch64_evpc_rev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev64v16qi ; break ; case V8QImode : gen = gen_aarch64_rev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev32v16qi ; break ; case V8QImode : gen = gen_aarch64_rev32v8qi ; break ; case V8HImode : gen = gen_aarch64_rev64v8hi ; break ; case V4HImode : gen = gen_aarch64_rev64v4hi ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_rev16v16qi ; break ; case V8QImode : gen = gen_aarch64_rev16v8qi ; break ; case V8HImode : gen = gen_aarch64_rev32v8hi ; break ; case V4HImode : gen = gen_aarch64_rev32v4hi ; break ; case V4SImode : gen = gen_aarch64_rev64v4si ; break ; case V2SImode : gen = gen_aarch64_rev64v2si ; break ; case V4SFmode : gen = gen_aarch64_rev64v4sf ; break ; case V2SFmode : gen = gen_aarch64_rev64v2sf ; break ; case V8HFmode : gen = gen_aarch64_rev64v8hf ; break ; case V4HFmode : gen = gen_aarch64_rev64v4hf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


"\tARM::shouldCoalesce - Coalesced Weight: "


<s> SDValue KudeyarTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: SIGN_EXTEND : return LowerSIGN_EXTEND ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: ExternalSymbol : return LowerExternalSymbol ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: BR_CC : return LowerBR_CC ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; default : break ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Kudeyar Kudeyar ISD::SIGN_EXTEND ISD::GlobalAddress ISD::ExternalSymbol ISD::BlockAddress ISD::JumpTable ISD::SETCC ISD::BR_CC ISD::SELECT_CC


<s> static void tilepro_conditional_register_usage ( void ) { global_regs [ TILEPRO_NETORDER_REGNUM ] = 1 ; if ( TILEPRO_PIC_TEXT_LABEL_REGNUM != INVALID_REGNUM ) { fixed_regs [ TILEPRO_PIC_TEXT_LABEL_REGNUM ] = 1 ; call_used_regs [ TILEPRO_PIC_TEXT_LABEL_REGNUM ] = 1 ; } if ( PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; } } </s>


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugValue ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>


"internal error: builtin function %qs already processed"

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> static void rs6000_darwin64_record_arg_recurse ( CUMULATIVE_ARGS * cum , const_tree type , HOST_WIDE_INT startbitpos , rtx rvec [ ] , int * k ) { tree f ; for ( f = TYPE_FIELDS ( type ) ; f ; f = DECL_CHAIN ( f ) ) if ( TREE_CODE ( f ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; tree ftype = TREE_TYPE ( f ) ; machine_mode mode ; if ( ftype == error_mark_node ) continue ; mode = TYPE_MODE ( ftype ) ; if ( DECL_SIZE ( f ) != 0 && tree_fits_uhwi_p ( bit_position ( f ) ) ) bitpos += int_bit_position ( f ) ; if ( TREE_CODE ( ftype ) == RECORD_TYPE ) rs6000_darwin64_record_arg_recurse ( cum , ftype , bitpos , rvec , k ) ; else if ( cum -> named && USE_FP_FOR_ARG_P ( cum , mode ) ) { unsigned n_fpreg = ( GET_MODE_SIZE ( mode ) + 7 ) >> 3 ; switch ( mode ) { case E_SCmode : mode = SFmode ; break ; case E_DCmode : mode = DFmode ; break ; case E_TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; if ( cum -> fregno + n_fpreg > FP_ARG_MAX_REG + 1 ) { gcc_assert ( cum -> fregno == FP_ARG_MAX_REG && ( mode == TFmode || mode == TDmode ) ) ; mode = DECIMAL_FLOAT_MODE_P ( mode ) ? DDmode : DFmode ; cum -> use_stack = 1 ; } rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( FLOAT128_2REG_P ( mode ) ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , 1 ) ) { rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> vregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; } else if ( cum -> intoffset == - 1 ) cum -> intoffset = bitpos ; } } </s>


<s> unsigned ARMInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STR : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: FSTD : case ARM :: FSTS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: tSpill : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> Instruction * SPIRVEmitIntrinsics :: visitInsertValueInst ( InsertValueInst & I ) { SmallVector < Type * , 1 > Types = { I . getInsertedValueOperand ( ) -> getType ( ) } ; SmallVector < Value * > Args ; for ( auto & Op : I . operands ( ) ) if ( isa < UndefValue > ( Op ) ) Args . push_back ( UndefValue :: get ( IRB -> getInt32Ty ( ) ) ) ; else Args . push_back ( Op ) ; for ( auto & Op : I . indices ( ) ) Args . push_back ( IRB -> getInt32 ( Op ) ) ; Instruction * NewI = IRB -> CreateIntrinsic ( Intrinsic :: spv_insertv , { Types } , { Args } ) ; replaceMemInstrUses ( & I , NewI ) ; return NewI ; } </s>

Try to find redundant insertvalue instructions , like the following ones : % 0 = insertvalue { i8 , i32 } undef , i8 x , 0 % 1 = insertvalue { i8 , i32 } % 0 , i8 y , 0 Here the second instruction inserts values at the same indices , as the first one , making the first one redundant .


<s> static int h8300_shift_costs ( rtx x ) { rtx operands [ 3 ] ; if ( GET_MODE ( x ) != QImode && GET_MODE ( x ) != HImode && GET_MODE ( x ) != SImode ) return 100 ; operands [ 0 ] = gen_rtx_REG ( GET_MODE ( x ) , 0 ) ; operands [ 1 ] = NULL ; operands [ 2 ] = XEXP ( x , 1 ) ; return compute_a_shift_length ( operands , GET_CODE ( x ) ) / 2 ; } </s>


<s> bool MipsFastISel :: fastLowerCall ( CallLoweringInfo & CLI ) { CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; MCSymbol * Symbol = CLI . Symbol ; if ( CC == CallingConv :: Fast ) return false ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = MVT :: isVoid ; else if ( ! isTypeSupported ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , 16 > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == MVT :: i1 || VT == MVT :: i8 || VT == MVT :: i16 ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 64 ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; if ( ! Addr . getGlobalValue ( ) ) return false ; unsigned DestAddress ; if ( Symbol ) DestAddress = materializeExternalCallSym ( Symbol ) ; else DestAddress = materializeGV ( Addr . getGlobalValue ( ) , MVT :: i32 ) ; emitInst ( TargetOpcode :: COPY , Mips :: T9 ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Mips :: JALR ) , Mips :: RA ) . addReg ( Mips :: T9 ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call = MIB ; return finishCall ( CLI , RetVT , NumBytes ) ; } </s>

This method is called by target-independent code to do target- specific call lowering .


<s>
const
char
*
getPassName
(
)
const
{
return
"PowerPC Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const int * SIRegisterInfo :: getRegUnitPressureSets ( unsigned RegUnit ) const { static const int Empty [ ] = { - 1 } ; if ( hasRegUnit ( AMDGPU :: M0 , RegUnit ) ) return Empty ; return AMDGPURegisterInfo :: getRegUnitPressureSets ( RegUnit ) ; } </s>

Get the dimensions of register pressure impacted by this register unit .


<s> static bool sparc_vector_mode_supported_p ( enum machine_mode mode ) { return TARGET_VIS && VECTOR_MODE_P ( mode ) ? true : false ; } </s>

Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook . Specify whether the vector mode is supported by the hardware .