<s> bool GBZ80TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == 0 && Offs == 0 ) { return true ; } if ( ! AM . BaseGV && AM . HasBaseReg && AM . Scale == 0 && Offs == 0 ) { return true ; } if ( ! AM . BaseGV && ! AM . HasBaseReg && AM . Scale == 1 && Offs == 0 ) { return true ; } if ( ! AM . BaseGV && ! AM . HasBaseReg && Offs >= 0xFF00 ) { return ( AM . Scale == 1 && Offs == 0xFF00 ) || ( AM . Scale == 0 && Offs <= 0xFFFF ) ; } return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


"relaxInstruction() should not be called"

Relax the instruction in the given fragment to the next wider instruction .


<s>
SDValue
VETargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

VE
VE
"Should not custom lower this!"
ISD::BlockAddress
ISD::GlobalAddress
ISD::VASTART
ISD::VAARG


"FPDelta isn't aligned per the Win64 ABI!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; return false ; } </s>


<s> bool HexagonAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; case 'L' : case 'H' : { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( Hexagon :: DoubleRegsRegClass . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ 0 ] == 'L' ? Hexagon :: isub_lo : Hexagon :: isub_hi ) ; OS << HexagonInstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << "i" ; return false ; } } printOperand ( MI , OpNo , OS ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool bfin_valid_add ( enum machine_mode mode , HOST_WIDE_INT value ) { unsigned HOST_WIDE_INT v = value > 0 ? value : - value ; int sz = GET_MODE_SIZE ( mode ) ; int shift = sz == 1 ? 0 : sz == 2 ? 1 : 2 ; unsigned HOST_WIDE_INT mask = sz == 8 ? 0x7ffe : 0x7fff ; return ( v & ~ ( mask << shift ) ) == 0 ; } </s>

Return true if the legitimate memory address for a memory operand of mode MODE . Return false if not .


<s> static bool s390_return_in_memory ( const_tree type , const_tree fundecl ATTRIBUTE_UNUSED ) { if ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || TREE_CODE ( type ) == OFFSET_TYPE || TREE_CODE ( type ) == REAL_TYPE ) return int_size_in_bytes ( type ) > 8 ; if ( TARGET_VX_ABI && VECTOR_TYPE_P ( type ) && int_size_in_bytes ( type ) <= 16 ) return false ; if ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || VECTOR_TYPE_P ( type ) ) return true ; return true ; } </s>

Return true if return values of type TYPE should be returned in a memory buffer whose address is passed by the caller as hidden first argument .


<s> bool X86TargetLowering :: isLoadBitCastBeneficial ( EVT LoadVT , EVT BitcastVT ) const { if ( ! Subtarget . hasDQI ( ) && BitcastVT == MVT :: v8i1 ) return false ; return TargetLowering :: isLoadBitCastBeneficial ( LoadVT , BitcastVT ) ; } </s>

Return true if the following transform is beneficial : fold ( conv ( load x ) ) - > ( load ( conv * ) x ) On architectures that do n't natively support some vector loads efficiently , casting the load to a smaller vector of larger types and loading is more efficient , however , this can be undone by optimizations in dag combiner .


<s> bool MCS51TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { if ( CallConv == CallingConv :: MCS51_BUILTIN ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_MCS51_BUILTIN ) ; } unsigned TotalBytes = getTotalArgumentsSizeInBytes ( Outs ) ; return TotalBytes <= 8 ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> const uint16_t * AMDGPURegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return & CalleeSavedReg ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"SPIRV Decorations Generation"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
unsigned
J2InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
getOpcode
(
)
!=
J2
::
BRA
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
NumEmitted
++
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
SDValue
OR1KTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void assignValueToAddress ( const CallLowering :: ArgInfo & Arg , unsigned RegIndex , Register Addr , uint64_t MemSize , MachinePointerInfo & MPO , CCValAssign & VA ) override { unsigned MaxSize = MemSize * 8 ; if ( ! Arg . IsFixed ) MaxSize = 0 ; Register ValVReg = Arg . Regs [ RegIndex ] ; if ( VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ) { MVT LocVT = VA . getLocVT ( ) ; MVT ValVT = VA . getValVT ( ) ; if ( VA . getValVT ( ) == MVT :: i8 || VA . getValVT ( ) == MVT :: i16 ) { std :: swap ( ValVT , LocVT ) ; MemSize = VA . getValVT ( ) . getStoreSize ( ) ; } ValVReg = extendRegister ( ValVReg , VA , MaxSize ) ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBits ( ) < LocVT . getSizeInBits ( ) ) ValVReg = MIRBuilder . buildTrunc ( RegTy , ValVReg ) . getReg ( 0 ) ; } else { MemSize = VA . getValVT ( ) . getStoreSize ( ) ; } assignValueToAddress ( ValVReg , Addr , MemSize , MPO , VA ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> bool isTargetEHABICompatible ( ) const { return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: Android ) && ! isTargetDarwin ( ) ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> ArrayRef < MCPhysReg > ARMBaseRegisterInfo :: getIntraCallClobberedRegs ( const MachineFunction * MF ) const { static const MCPhysReg IntraCallClobberedRegs [ ] = { ARM :: R12 } ; return ArrayRef < MCPhysReg > ( IntraCallClobberedRegs ) ; } </s>

Return a list of all of the registers which are clobbered `` inside '' a call to the given function .


"Unexpected data type for Gather/Scatter"

Calculate the cost of Gather / Scatter operation .


"multiple save reg attributes to function %qD"

"multiple nested types attributes to function %qD"

"multiple interrupt attributes to function %qD"

Function for nds32_merge_decl_attributes ( ) and nds32_insert_attributes ( ) to check if there are any conflict isr-specific attributes being set . We need to check : 1 . Only 'save_all ' or 'partial_save ' in the attributes . 2 . Only 'nested ' , 'not_nested ' , or 'nested_ready ' in the attributes . 3 . Only 'interrupt ' , 'exception ' , or 'reset ' in the attributes .


<s> static rtvec rs6000_const_vec ( machine_mode mode ) { int i , subparts ; rtvec v ; switch ( mode ) { case E_V1TImode : subparts = 1 ; break ; case E_V2DFmode : case E_V2DImode : subparts = 2 ; break ; case E_V4SFmode : case E_V4SImode : subparts = 4 ; break ; case E_V8HImode : subparts = 8 ; break ; case E_V16QImode : subparts = 16 ; break ; default : gcc_unreachable ( ) ; } v = rtvec_alloc ( subparts ) ; for ( i = 0 ; i < subparts / 2 ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i + subparts / 2 ) ; for ( i = subparts / 2 ; i < subparts ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i - subparts / 2 ) ; return v ; } </s>

Generate a vector of constants to permute MODE for a little-endian storage operation by swapping the two halves of a vector .


<s> static std :: string getEdgeAttributes ( const void * , GraphTraits < SpillCostAnalysisGraph > :: ChildIteratorType e , const SpillCostAnalysisGraph & G ) { std :: string tmp ; raw_string_ostream s ( tmp ) ; MachineInstr * MI = e . getMI ( ) ; s << "label=\"" ; if ( MI ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; s << "BB#" << MBB -> getNumber ( ) << ":" << std :: distance ( MBB -> instr_begin ( ) , MachineBasicBlock :: instr_iterator ( MI ) ) ; } s << "\"" ; return s . str ( ) ; } </s>

If you want to override the dot attributes printed for a particular edge , override this method .


<s> unsigned MCS51InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case MCS51 :: STDPtrQRr : case MCS51 :: STDWPtrQRr : { if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } break ; } default : break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void PPCPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; if ( TM -> getTargetTriple ( ) . getArch ( ) == Triple :: ppc64le && ! DisableVSXSwapRemoval ) addPass ( createPPCVSXSwapRemovalPass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> const RISCVInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static void emit_store_conditional ( machine_mode mode , rtx res , rtx mem , rtx val ) { rtx ( * fn ) ( rtx , rtx , rtx ) = NULL ; switch ( mode ) { case E_QImode : fn = gen_store_conditionalqi ; break ; case E_HImode : fn = gen_store_conditionalhi ; break ; case E_SImode : fn = gen_store_conditionalsi ; break ; case E_DImode : fn = gen_store_conditionaldi ; break ; case E_TImode : fn = gen_store_conditionalti ; break ; default : gcc_unreachable ( ) ; } if ( PPC405_ERRATUM77 ) emit_insn ( gen_hwsync ( ) ) ; emit_insn ( fn ( res , mem , val ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a store-conditional instruction in MODE .


"Encoding of this operand type is not supported yet."

getMachineOpValue - Return binary encoding of operand .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addRequired < MemorySSAWrapperPass > ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
AVRTargetLowering
::
getRegForInlineAsmConstraint
(
const
TargetRegisterInfo
*
TRI
,
StringRef
Constraint
,
MVT
VT
)
const
{
auto
STI
=
static_cast
<
const
AVRTargetMachine
&
>
(
this
->
getTargetMachine
(
)
)
.
getSubtargetImpl
(
)
;
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'a'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
LD8loRegClass
)
;
case
'b'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
PTRDISPREGSRegClass
)
;
case
'd'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
LD8RegClass
)
;
case
'l'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
GPR8loRegClass
)
;
case
'e'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
PTRREGSRegClass
)
;
case
'q'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
GPRSPRegClass
)
;
case
'r'
:
if
(
VT
==
MVT
::
i8
)
return
std
::
make_pair
(
0U
,
&
AVR
::
GPR8RegClass
)
;
assert
(
VT
==
MVT
::
i16
&&
"inline asm constraint too large"
)
;
return
std
::
make_pair
(
0U
,
&
AVR
::
DREGSRegClass
)
;
case
't'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R0
)
,
&
AVR
::
GPR8RegClass
)
;
case
'w'
:
return
std
::
make_pair
(
0U
,
&
AVR
::
IWREGSRegClass
)
;
case
'x'
:
case
'X'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R27R26
)
,
&
AVR
::
PTRREGSRegClass
)
;
case
'y'
:
case
'Y'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R29R28
)
,
&
AVR
::
PTRREGSRegClass
)
;
case
'z'
:
case
'Z'
:
return
std
::
make_pair
(
unsigned
(
AVR
::
R31R30
)
,
&
AVR
::
PTRREGSRegClass
)
;
default
:
break
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
STI
->
getRegisterInfo
(
)
,
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> bool AMDGPUCFGPerform :: runOnMachineFunction ( MachineFunction & func ) { return llvmCFGStruct :: CFGStructurizer < AMDGPUCFGStructurizer > ( ) . run ( func , * this , TRI ) ; } </s>


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
DestReg
!=
AMDGPU
::
M0
&&
"m0 should not be reloaded into"
)
;
assert
(
DestReg
!=
AMDGPU
::
EXEC_LO
&&
DestReg
!=
AMDGPU
::
EXEC_HI
&&
DestReg
!=
AMDGPU
::
EXEC
&&
"exec should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
DestReg
.
isVirtual
(
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0_XEXECRegClass
)
;
}
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
return
;
}
unsigned
Opcode
=
RI
.
isAGPRClass
(
RC
)
getAGPRSpillRestoreOpcode
(
SpillSize
)
:
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> WeightedLeaf pop ( ) { if ( HaveConst ) { HaveConst = false ; return ConstElt ; } std :: pop_heap ( Q . begin ( ) , Q . end ( ) , WeightedLeaf :: Compare ) ; return Q . pop_back_val ( ) ; } </s>


<s> void WebAssemblyFrameLowering :: writeSPToGlobal ( unsigned SrcReg , MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & InsertStore , const DebugLoc & DL ) const { const auto * TII = MF . getSubtarget < WebAssemblySubtarget > ( ) . getInstrInfo ( ) ; const char * ES = "__stack_pointer" ; auto * SPSymbol = MF . createExternalSymbolName ( ES ) ; BuildMI ( MBB , InsertStore , DL , TII -> get ( WebAssembly :: GLOBAL_SET_I32 ) ) . addExternalSymbol ( SPSymbol , WebAssemblyII :: MO_SYMBOL_GLOBAL ) . addReg ( SrcReg ) ; } </s>

Write SP back to __stack_pointer global .


<s> bool PPCInstrInfo :: isPredicable ( const MachineInstr & MI ) const { unsigned OpC = MI . getOpcode ( ) ; switch ( OpC ) { default : return false ; case PPC :: B : case PPC :: BLR : case PPC :: BLR8 : case PPC :: BCTR : case PPC :: BCTR8 : case PPC :: BCTRL : case PPC :: BCTRL8 : return true ; } } </s>

Return true if the specified instruction can be predicated .

PowerPC PPC PPC::B PPC::BLR PPC::BLR8 PPC::BCTR PPC::BCTR8 PPC::BCTRL PPC::BCTRL8


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void HexagonTargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB , bool DebugPassManager ) { PB . registerLateLoopOptimizationsEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) { LPM . addPass ( HexagonLoopIdiomRecognitionPass ( ) ) ; } ) ; PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , PassBuilder :: OptimizationLevel Level ) { LPM . addPass ( HexagonVectorLoopCarriedReusePass ( ) ) ; } ) ; } </s>

Invoke the PassBuilder callback registration .


<s> static void riscv_extend_comparands ( rtx_code code , rtx * op0 , rtx * op1 ) { if ( GET_MODE_SIZE ( word_mode ) > GET_MODE_SIZE ( GET_MODE ( * op0 ) ) ) { if ( unsigned_condition ( code ) == code && ( GET_MODE ( * op0 ) == QImode && ! ( GET_CODE ( * op0 ) == SUBREG && SUBREG_PROMOTED_VAR_P ( * op0 ) && SUBREG_PROMOTED_SIGNED_P ( * op0 ) && ( CONST_INT_P ( * op1 ) || ( GET_CODE ( * op1 ) == SUBREG && SUBREG_PROMOTED_VAR_P ( * op1 ) && SUBREG_PROMOTED_SIGNED_P ( * op1 ) ) ) ) ) ) { * op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ; if ( CONST_INT_P ( * op1 ) ) * op1 = GEN_INT ( ( uint8_t ) INTVAL ( * op1 ) ) ; else * op1 = gen_rtx_ZERO_EXTEND ( word_mode , * op1 ) ; } else { * op0 = gen_rtx_SIGN_EXTEND ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = gen_rtx_SIGN_EXTEND ( word_mode , * op1 ) ; } } } </s>

Sign- or zero-extend OP0 and OP1 for integer comparisons .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: ARGEXTEND : return "HexagonISD::ARGEXTEND" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: CALLv3nr : return "HexagonISD::CALLv3nr" ; case HexagonISD :: CALLv3 : return "HexagonISD::CALLv3" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: EXTRACTURP : return "HexagonISD::EXTRACTURP" ; case HexagonISD :: FCONST32 : return "HexagonISD::FCONST32" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: INSERTRP : return "HexagonISD::INSERTRP" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: PACKHL : return "HexagonISD::PACKHL" ; case HexagonISD :: POPCOUNT : return "HexagonISD::POPCOUNT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: SHUFFEB : return "HexagonISD::SHUFFEB" ; case HexagonISD :: SHUFFEH : return "HexagonISD::SHUFFEH" ; case HexagonISD :: SHUFFOB : return "HexagonISD::SHUFFOB" ; case HexagonISD :: SHUFFOH : return "HexagonISD::SHUFFOH" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VCMPBEQ : return "HexagonISD::VCMPBEQ" ; case HexagonISD :: VCMPBGT : return "HexagonISD::VCMPBGT" ; case HexagonISD :: VCMPBGTU : return "HexagonISD::VCMPBGTU" ; case HexagonISD :: VCMPHEQ : return "HexagonISD::VCMPHEQ" ; case HexagonISD :: VCMPHGT : return "HexagonISD::VCMPHGT" ; case HexagonISD :: VCMPHGTU : return "HexagonISD::VCMPHGTU" ; case HexagonISD :: VCMPWEQ : return "HexagonISD::VCMPWEQ" ; case HexagonISD :: VCMPWGT : return "HexagonISD::VCMPWGT" ; case HexagonISD :: VCMPWGTU : return "HexagonISD::VCMPWGTU" ; case HexagonISD :: VCOMBINE : return "HexagonISD::VCOMBINE" ; case HexagonISD :: VPACK : return "HexagonISD::VPACK" ; case HexagonISD :: VSHLH : return "HexagonISD::VSHLH" ; case HexagonISD :: VSHLW : return "HexagonISD::VSHLW" ; case HexagonISD :: VSPLATB : return "HexagonISD::VSPLTB" ; case HexagonISD :: VSPLATH : return "HexagonISD::VSPLATH" ; case HexagonISD :: VSRAH : return "HexagonISD::VSRAH" ; case HexagonISD :: VSRAW : return "HexagonISD::VSRAW" ; case HexagonISD :: VSRLH : return "HexagonISD::VSRLH" ; case HexagonISD :: VSRLW : return "HexagonISD::VSRLW" ; case HexagonISD :: VSXTBH : return "HexagonISD::VSXTBH" ; case HexagonISD :: VSXTBW : return "HexagonISD::VSXTBW" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::ARGEXTEND "HexagonISD::ARGEXTEND" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::CALLv3nr "HexagonISD::CALLv3nr" HexagonISD::CALLv3 "HexagonISD::CALLv3" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::EXTRACTURP "HexagonISD::EXTRACTURP" HexagonISD::FCONST32 "HexagonISD::FCONST32" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::INSERTRP "HexagonISD::INSERTRP" HexagonISD::JT "HexagonISD::JT" HexagonISD::PACKHL "HexagonISD::PACKHL" HexagonISD::POPCOUNT "HexagonISD::POPCOUNT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::SHUFFEB "HexagonISD::SHUFFEB" HexagonISD::SHUFFEH "HexagonISD::SHUFFEH" HexagonISD::SHUFFOB "HexagonISD::SHUFFOB" HexagonISD::SHUFFOH "HexagonISD::SHUFFOH" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VCMPBEQ "HexagonISD::VCMPBEQ" HexagonISD::VCMPBGT "HexagonISD::VCMPBGT" HexagonISD::VCMPBGTU "HexagonISD::VCMPBGTU" HexagonISD::VCMPHEQ "HexagonISD::VCMPHEQ" HexagonISD::VCMPHGT "HexagonISD::VCMPHGT" HexagonISD::VCMPHGTU "HexagonISD::VCMPHGTU" HexagonISD::VCMPWEQ "HexagonISD::VCMPWEQ" HexagonISD::VCMPWGT "HexagonISD::VCMPWGT" HexagonISD::VCMPWGTU "HexagonISD::VCMPWGTU" HexagonISD::VCOMBINE "HexagonISD::VCOMBINE" HexagonISD::VPACK "HexagonISD::VPACK" HexagonISD::VSHLH "HexagonISD::VSHLH" HexagonISD::VSHLW "HexagonISD::VSHLW" HexagonISD::VSPLATB "HexagonISD::VSPLTB" HexagonISD::VSPLATH "HexagonISD::VSPLATH" HexagonISD::VSRAH "HexagonISD::VSRAH" HexagonISD::VSRAW "HexagonISD::VSRAW" HexagonISD::VSRLH "HexagonISD::VSRLH" HexagonISD::VSRLW "HexagonISD::VSRLW" HexagonISD::VSXTBH "HexagonISD::VSXTBH" HexagonISD::VSXTBW "HexagonISD::VSXTBW" HexagonISD::OP_END


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createAMDGPUELFObjectWriter ( OS ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static void arm_expand_vec_perm_1 ( rtx target , rtx op0 , rtx op1 , rtx sel ) { machine_mode vmode = GET_MODE ( target ) ; bool one_vector_p = rtx_equal_p ( op0 , op1 ) ; gcc_checking_assert ( vmode == V8QImode || vmode == V16QImode ) ; gcc_checking_assert ( GET_MODE ( op0 ) == vmode ) ; gcc_checking_assert ( GET_MODE ( op1 ) == vmode ) ; gcc_checking_assert ( GET_MODE ( sel ) == vmode ) ; gcc_checking_assert ( TARGET_NEON ) ; if ( one_vector_p ) { if ( vmode == V8QImode ) emit_insn ( gen_neon_vtbl1v8qi ( target , op0 , sel ) ) ; else emit_insn ( gen_neon_vtbl1v16qi ( target , op0 , sel ) ) ; } else { rtx pair ; if ( vmode == V8QImode ) { pair = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_neon_vcombinev8qi ( pair , op0 , op1 ) ) ; pair = gen_lowpart ( TImode , pair ) ; emit_insn ( gen_neon_vtbl2v8qi ( target , pair , sel ) ) ; } else { pair = gen_reg_rtx ( OImode ) ; emit_insn ( gen_neon_vcombinev16qi ( pair , op0 , op1 ) ) ; emit_insn ( gen_neon_vtbl2v16qi ( target , pair , sel ) ) ; } } } </s>


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: TSTBIT : return "HexagonISD::TSTBIT" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VCOMBINE : return "HexagonISD::VCOMBINE" ; case HexagonISD :: VPACKE : return "HexagonISD::VPACKE" ; case HexagonISD :: VPACKO : return "HexagonISD::VPACKO" ; case HexagonISD :: VASL : return "HexagonISD::VASL" ; case HexagonISD :: VASR : return "HexagonISD::VASR" ; case HexagonISD :: VLSR : return "HexagonISD::VLSR" ; case HexagonISD :: VSPLAT : return "HexagonISD::VSPLAT" ; case HexagonISD :: VEXTRACTW : return "HexagonISD::VEXTRACTW" ; case HexagonISD :: VINSERTW0 : return "HexagonISD::VINSERTW0" ; case HexagonISD :: VROR : return "HexagonISD::VROR" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: VZERO : return "HexagonISD::VZERO" ; case HexagonISD :: D2P : return "HexagonISD::D2P" ; case HexagonISD :: P2D : return "HexagonISD::P2D" ; case HexagonISD :: V2Q : return "HexagonISD::V2Q" ; case HexagonISD :: Q2V : return "HexagonISD::Q2V" ; case HexagonISD :: TYPECAST : return "HexagonISD::TYPECAST" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::TSTBIT "HexagonISD::TSTBIT" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::JT "HexagonISD::JT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VCOMBINE "HexagonISD::VCOMBINE" HexagonISD::VPACKE "HexagonISD::VPACKE" HexagonISD::VPACKO "HexagonISD::VPACKO" HexagonISD::VASL "HexagonISD::VASL" HexagonISD::VASR "HexagonISD::VASR" HexagonISD::VLSR "HexagonISD::VLSR" HexagonISD::VSPLAT "HexagonISD::VSPLAT" HexagonISD::VEXTRACTW "HexagonISD::VEXTRACTW" HexagonISD::VINSERTW0 "HexagonISD::VINSERTW0" HexagonISD::VROR "HexagonISD::VROR" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::VZERO "HexagonISD::VZERO" HexagonISD::D2P "HexagonISD::D2P" HexagonISD::P2D "HexagonISD::P2D" HexagonISD::V2Q "HexagonISD::V2Q" HexagonISD::Q2V "HexagonISD::Q2V" HexagonISD::TYPECAST "HexagonISD::TYPECAST" HexagonISD::OP_END


<s> bool X86InstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> rtx function_expander :: use_exact_insn ( insn_code icode ) { machine_mode mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; int arg_offset = 0 ; if ( base -> use_mask_predication_p ( ) ) { if ( use_real_mask_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_all_one_mask_operand ( mask_mode ( ) ) ; } if ( ! function_returns_void_p ( ) && base -> has_merge_operand_p ( ) ) { if ( use_real_merge_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_vundef_operand ( mode ) ; } for ( int argno = arg_offset ; argno < call_expr_nargs ( exp ) ; argno ++ ) add_input_operand ( argno ) ; if ( base -> apply_tail_policy_p ( ) ) add_input_operand ( Pmode , get_tail_policy_for_pred ( pred ) ) ; if ( base -> apply_mask_policy_p ( ) ) add_input_operand ( Pmode , get_mask_policy_for_pred ( pred ) ) ; if ( base -> apply_vl_p ( ) ) add_input_operand ( Pmode , get_avl_type_rtx ( avl_type :: NONVLMAX ) ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , with a 1:1 mapping between arguments and input operands .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) && AMDGPU :: getNamedOperandIdx ( Opcode , AMDGPU :: OpName :: dmask ) != - 1 ) { return adjustWritemask ( Node , DAG ) ; } if ( Opcode == AMDGPU :: INSERT_SUBREG || Opcode == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case AMDGPU :: V_DIV_SCALE_F32 : case AMDGPU :: V_DIV_SCALE_F64 : { SDValue Src0 = Node -> getOperand ( 1 ) ; SDValue Src1 = Node -> getOperand ( 3 ) ; SDValue Src2 = Node -> getOperand ( 5 ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT , Src0 . getNode ( ) -> isDivergent ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != AMDGPU :: IMPLICIT_DEF ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , 9 > Ops ( Node -> op_begin ( ) , Node -> op_end ( ) ) ; Ops [ 1 ] = Src0 ; Ops [ 3 ] = Src1 ; Ops [ 5 ] = Src2 ; Ops . push_back ( ImpDef . getValue ( 1 ) ) ; return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } default : break ; } return Node ; } </s>

Fold the instructions after selecting them .


<s> unsigned ARMTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return Subtarget -> useSjLjEH ( ) ? ARM :: NoRegister : ARM :: R0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> static void xtensa_reorg_loops ( void ) { if ( TARGET_LOOPS ) reorg_loops ( false , & xtensa_doloop_hooks ) ; } </s>

Run from machine_dependent_reorg , this pass looks for doloop_end insns and tries to rewrite the RTL of these loops so that proper Xtensa hardware loops are generated .


<s> rtx aarch64_simd_gen_const_vector_dup ( machine_mode mode , int val ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits ) ; int i ; for ( i = 0 ; i < nunits ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( val ) ; return gen_rtx_CONST_VECTOR ( mode , v ) ; } </s>


<s>
unsigned
RISCVMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unexpected operand type!"
)
;
}
</s>


<s> void MOSFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( MOS :: RC30 ) ; SavedRegs . set ( MOS :: RC31 ) ; } if ( isISR ( MF ) ) { SavedRegs . set ( MOS :: RC16 ) ; SavedRegs . set ( MOS :: RC17 ) ; if ( ! SavedRegs . none ( ) ) SavedRegs . set ( MOS :: A ) ; if ( SavedRegs . size ( ) > 4 ) SavedRegs . set ( MOS :: Y ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> rtx frv_split_scc ( rtx dest , rtx test , rtx cc_reg , rtx cr_reg , HOST_WIDE_INT value ) { rtx ret ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( cr_reg , gen_rtx_fmt_ee ( GET_CODE ( test ) , GET_MODE ( cr_reg ) , cc_reg , const0_rtx ) ) ) ; emit_move_insn ( dest , GEN_INT ( value ) ) ; emit_insn ( gen_rtx_COND_EXEC ( VOIDmode , gen_rtx_EQ ( GET_MODE ( cr_reg ) , cr_reg , const0_rtx ) , gen_rtx_SET ( dest , const0_rtx ) ) ) ; ret = get_insns ( ) ; end_sequence ( ) ; return ret ; } </s>

Split a SCC instruction into component parts , returning a SEQUENCE to hold the separate insns .


<s> virtual bool requiresRegisterScavenging ( const MachineFunction & MF ) const LLVM_OVERRIDE { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createAMDGPUELFObjectWriter ( Is64Bit , HasRelocationAddend , OS ) ; } </s>


<s>
bool
AMDGPULegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
MIRBuilder
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_ADDRSPACE_CAST
:
return
legalizeAddrSpaceCast
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_FRINT
:
return
legalizeFrint
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_FCEIL
:
return
legalizeFceil
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_INTRINSIC_TRUNC
:
return
legalizeIntrinsicTrunc
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_SITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
MIRBuilder
,
true
)
;
case
TargetOpcode
::
G_UITOFP
:
return
legalizeITOFP
(
MI
,
MRI
,
MIRBuilder
,
false
)
;
case
TargetOpcode
::
G_FMINNUM
:
case
TargetOpcode
::
G_FMAXNUM
:
case
TargetOpcode
::
G_FMINNUM_IEEE
:
case
TargetOpcode
::
G_FMAXNUM_IEEE
:
return
legalizeMinNumMaxNum
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_EXTRACT_VECTOR_ELT
:
return
legalizeExtractVectorElt
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_INSERT_VECTOR_ELT
:
return
legalizeInsertVectorElt
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_FSIN
:
case
TargetOpcode
::
G_FCOS
:
return
legalizeSinCos
(
MI
,
MRI
,
MIRBuilder
)
;
default
:
return
false
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .

AMDGPU
AMDGPU
SI
SI
SI
"expected switch to return"


<s> unsigned LanaiMCCodeEmitter :: getMachineOpValue ( const MCInst & Inst , const MCOperand & MCOp , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { if ( MCOp . isReg ( ) ) return getLanaiRegisterNumbering ( MCOp . getReg ( ) ) ; if ( MCOp . isImm ( ) ) < unsigned > ( MCOp . getImm ( ) ) ; assert ( MCOp . isExpr ( ) ) ; const MCExpr * Expr = MCOp . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * BinaryExpr = static_cast < const MCBinaryExpr * > ( Expr ) ; Expr = BinaryExpr -> getLHS ( ) ; } assert ( isa < LanaiMCExpr > ( Expr ) || Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , MCFixupKind ( FixupKind ( Expr ) ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> const TargetRegisterClass * getRepRegClassFor ( MVT VT ) const override { if ( VT == MVT :: Untyped ) return Subtarget -> hasDSP ( ) ? & Mips :: ACC64DSPRegClass : & Mips :: ACC64RegClass ; return TargetLowering :: getRepRegClassFor ( VT ) ; } </s>

Return the 'representative ' register class for the specified value type .


<s> static bool m32r_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { return m32r_pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> void MipsTargetELFStreamer :: emitAssignment ( MCSymbol * Symbol , const MCExpr * Value ) { if ( Value -> getKind ( ) != MCExpr :: SymbolRef ) return ; const MCSymbol & RhsSym = static_cast < const MCSymbolRefExpr * > ( Value ) -> getSymbol ( ) ; MCSymbolData & Data = getStreamer ( ) . getOrCreateSymbolData ( & RhsSym ) ; if ( ! ( MCELF :: getOther ( Data ) & ( ELF :: STO_MIPS_MICROMIPS >> 2 ) ) ) return ; MCSymbolData & SymbolData = getStreamer ( ) . getOrCreateSymbolData ( Symbol ) ; MCELF :: setOther ( SymbolData , ELF :: STO_MIPS_MICROMIPS >> 2 ) ; } </s>


<s>
ArrayRef
<
MCPhysReg
>
MipsABIInfo
::
GetVarArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsN32
(
)
||
IsN64
(
)
)
return
makeArrayRef
(
Mips64IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for the variable argument list .


<s> uint64_t X86TargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget . is64Bit ( ) ) { Align TyAlign = DL . getABITypeAlign ( Ty ) ; if ( TyAlign > 8 ) return TyAlign . value ( ) ; return 8 ; } Align Alignment ( 4 ) ; if ( Subtarget . hasSSE1 ( ) ) getMaxByValAlign ( Ty , Alignment ) ; return Alignment . value ( ) ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s>
int
PPCTTIImpl
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
TTI
::
OperandValueKind
Op1Info
,
TTI
::
OperandValueKind
Op2Info
,
TTI
::
OperandValueProperties
Opd1PropInfo
,
TTI
::
OperandValueProperties
Opd2PropInfo
,
ArrayRef
<
const
Value
*
>
Args
)
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
int
Cost
=
BaseT
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
,
Opd1PropInfo
,
Opd2PropInfo
)
;
return
vectorCostAdjustment
(
Cost
,
Opcode
,
Ty
,
nullptr
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> virtual bool isToken ( ) const LLVM_OVERRIDE { return Kind == KindToken ; } </s>


<s> static bool rs6000_hard_regno_call_part_clobbered ( unsigned int , unsigned int regno , machine_mode mode ) { if ( TARGET_32BIT && TARGET_POWERPC64 && GET_MODE_SIZE ( mode ) > 4 && INT_REGNO_P ( regno ) ) return true ; if ( TARGET_VSX && FP_REGNO_P ( regno ) && GET_MODE_SIZE ( mode ) > 8 && ! FLOAT128_2REG_P ( mode ) ) return true ; return false ; } </s>


<s> virtual const TMS320C64XRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> Register Cpu0RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? ( Cpu0 :: FP ) : ( Cpu0 :: SP ) ; } </s>


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
void
RISCVMCAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
unsigned
Opcode
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
assert
(
Opcode
&&
"Unexpected insn to relax"
)
;
Res
=
Inst
;
Res
.
setOpcode
(
Opcode
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static rtx nvptx_expand_cmp_swap ( tree exp , rtx target , machine_mode ARG_UNUSED ( m ) , int ARG_UNUSED ( ignore ) ) { machine_mode mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; if ( ! target ) target = gen_reg_rtx ( mode ) ; rtx mem = expand_expr ( CALL_EXPR_ARG ( exp , 0 ) , NULL_RTX , Pmode , EXPAND_NORMAL ) ; rtx cmp = expand_expr ( CALL_EXPR_ARG ( exp , 1 ) , NULL_RTX , mode , EXPAND_NORMAL ) ; rtx src = expand_expr ( CALL_EXPR_ARG ( exp , 2 ) , NULL_RTX , mode , EXPAND_NORMAL ) ; rtx pat ; mem = gen_rtx_MEM ( mode , mem ) ; if ( ! REG_P ( cmp ) ) cmp = copy_to_mode_reg ( mode , cmp ) ; if ( ! REG_P ( src ) ) src = copy_to_mode_reg ( mode , src ) ; if ( mode == SImode ) pat = gen_atomic_compare_and_swapsi_1 ( target , mem , cmp , src , const0_rtx ) ; else pat = gen_atomic_compare_and_swapdi_1 ( target , mem , cmp , src , const0_rtx ) ; emit_insn ( pat ) ; return target ; } </s>

Expand the CMP_SWAP PTX builtins . We have our own versions that do not require taking the address of any object , other than the memory cell being operated on .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = MBB -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDrSPi : ARM :: t2ADDri ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , 0 , this ) ) ; MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( MIB ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDrSPi ARM::t2ADDri 0


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".hsa_code_object_version" ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == ".hsa_code_object_isa" ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == ".amd_kernel_code_t" ) return ParseDirectiveAMDKernelCodeT ( ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool riscv_epilogue_uses ( unsigned int regno ) { if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( epilogue_completed && cfun -> machine -> interrupt_handler_p ) { if ( df_regs_ever_live_p ( regno ) || ( ! crtl -> is_leaf && call_used_or_fixed_reg_p ( regno ) ) ) return true ; } return false ; } </s>


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> mayStore ( ) && hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> static char sizetochar ( int size ) { switch ( size ) { case 64 : return 'd' ; case 32 : return 's' ; case 16 : return 'h' ; case 8 : return 'b' ; default : gcc_unreachable ( ) ; } } </s>


<s> bool PPCInstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case PPC :: EXTSW : case PPC :: EXTSW_32_64 : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = PPC :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s> bool XtensaInstrInfo :: isCopyInstr ( const MachineInstr & MI , const MachineOperand * & Src , const MachineOperand * & Dest ) const { if ( ! MI . isMoveReg ( ) ) return false ; Dest = & MI . getOperand ( 0 ) ; Src = & MI . getOperand ( 1 ) ; return true ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> std :: pair < unsigned , const TargetRegisterClass * > NVPTXTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : return std :: make_pair ( 0U , & NVPTX :: Int1RegsRegClass ) ; case 'c' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'h' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'r' : return std :: make_pair ( 0U , & NVPTX :: Int32RegsRegClass ) ; case 'l' : case 'N' : return std :: make_pair ( 0U , & NVPTX :: Int64RegsRegClass ) ; case 'f' : return std :: make_pair ( 0U , & NVPTX :: Float32RegsRegClass ) ; case 'd' : return std :: make_pair ( 0U , & NVPTX :: Float64RegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void XNCMRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { llvm_unreachable ( 0 ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned getEUsPerCU ( const MCSubtargetInfo * STI ) { if ( isGFX10Plus ( * STI ) && STI -> getFeatureBits ( ) . test ( FeatureCuMode ) ) return 2 ; return 4 ; } </s>

Number of SIMDs/EUs ( execution units ) per `` CU '' ( `` compute unit '' ) , where the `` CU '' is the unit onto which workgroups are mapped .


<s> BitVector X86RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( X86 :: RSP ) ; Reserved . set ( X86 :: ESP ) ; Reserved . set ( X86 :: SP ) ; Reserved . set ( X86 :: SPL ) ; if ( hasFP ( MF ) ) { Reserved . set ( X86 :: RBP ) ; Reserved . set ( X86 :: EBP ) ; Reserved . set ( X86 :: BP ) ; Reserved . set ( X86 :: BPL ) ; } Reserved . set ( X86 :: ST0 ) ; Reserved . set ( X86 :: ST1 ) ; Reserved . set ( X86 :: ST2 ) ; Reserved . set ( X86 :: ST3 ) ; Reserved . set ( X86 :: ST4 ) ; Reserved . set ( X86 :: ST5 ) ; Reserved . set ( X86 :: ST6 ) ; Reserved . set ( X86 :: ST7 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> Optional < MCDisassembler :: DecodeStatus > AMDGPUDisassembler :: onSymbolStart ( SymbolInfoTy & Symbol , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { if ( Symbol . Type == ELF :: STT_AMDGPU_HSA_KERNEL ) { Size = 256 ; return MCDisassembler :: Fail ; } StringRef Name = Symbol . Name ; if ( Symbol . Type == ELF :: STT_OBJECT && Name . endswith ( StringRef ( ".kd" ) ) ) { Size = 64 ; return decodeKernelDescriptor ( Name . drop_back ( 3 ) , Bytes , Address ) ; } return None ; } </s>

Used to perform separate target specific disassembly for a particular symbol .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool valid_sf_si_move ( rtx dest , rtx src , machine_mode mode ) { if ( TARGET_ALLOW_SF_SUBREG ) return true ; if ( mode != SFmode && GET_MODE_CLASS ( mode ) != MODE_INT ) return true ; if ( ! SUBREG_P ( src ) || ! sf_subreg_operand ( src , mode ) ) return true ; if ( SUBREG_P ( dest ) ) { rtx dest_subreg = SUBREG_REG ( dest ) ; rtx src_subreg = SUBREG_REG ( src ) ; return GET_MODE ( dest_subreg ) == GET_MODE ( src_subreg ) ; } return false ; } </s>

Return whether a SFmode or SImode move can be done without converting one mode to another . This arrises when we have : ( SUBREG : SF ( REG : SI ... ) ) ( SUBREG : SI ( REG : SF ... ) ) and one of the values is in a floating point/vector register , where SFmode scalars are stored in DFmode format .


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
DataLayout
&
DL
,
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
switch
(
AS
)
{
case
AMDGPUAS
::
GLOBAL_ADDRESS
:
if
(
Subtarget
->
getGeneration
(
)
>=
AMDGPUSubtarget
::
VOLCANIC_ISLANDS
)
{
return
isLegalFlatAddressingMode
(
AM
)
;
}
case
AMDGPUAS
::
PRIVATE_ADDRESS
:
case
AMDGPUAS
::
CONSTANT_ADDRESS
:
case
AMDGPUAS
::
UNKNOWN_ADDRESS_SPACE
:
{
if
(
!
isUInt
<
12
>
(
AM
.
BaseOffs
)
)
return
false
;
switch
(
AM
.
Scale
)
{
case
0
:
return
true
;
case
1
:
return
true
;
case
2
:
if
(
AM
.
HasBaseReg
)
{
return
false
;
}
return
true
;
default
:
return
false
;
}
}
case
AMDGPUAS
::
LOCAL_ADDRESS
:
case
AMDGPUAS
::
REGION_ADDRESS
:
{
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
case
AMDGPUAS
::
FLAT_ADDRESS
:
return
isLegalFlatAddressingMode
(
AM
)
;
default
:
llvm_unreachable
(
"unhandled address space"
)
;
}
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> DecodeStatus BPFDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { bool IsLittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; uint64_t Insn , Hi ; DecodeStatus Result ; Result = readInstruction64 ( Bytes , Address , Size , Insn , IsLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; uint8_t InstClass = getInstClass ( Insn ) ; uint8_t InstMode = getInstMode ( Insn ) ; if ( ( InstClass == BPF_LDX || InstClass == BPF_STX ) && getInstSize ( Insn ) != BPF_DW && ( InstMode == BPF_MEM || InstMode == BPF_XADD ) && STI . getFeatureBits ( ) [ BPF :: ALU32 ] ) Result = decodeInstruction ( DecoderTableBPFALU3264 , Instr , Insn , Address , this , STI ) ; else Result = decodeInstruction ( DecoderTableBPF64 , Instr , Insn , Address , this , STI ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Instr . getOpcode ( ) ) { case BPF :: LD_imm64 : case BPF :: LD_pseudo : { if ( Bytes . size ( ) < 16 ) { Size = 0 ; return MCDisassembler :: Fail ; } Size = 16 ; if ( IsLittleEndian ) Hi = ( Bytes [ 12 ] << 0 ) | ( Bytes [ 13 ] << 8 ) | ( Bytes [ 14 ] << 16 ) | ( Bytes [ 15 ] << 24 ) ; else Hi = ( Bytes [ 12 ] << 24 ) | ( Bytes [ 13 ] << 16 ) | ( Bytes [ 14 ] << 8 ) | ( Bytes [ 15 ] << 0 ) ; auto & Op = Instr . getOperand ( 1 ) ; Op . setImm ( Make_64 ( Hi , Op . getImm ( ) ) ) ; break ; } case BPF :: LD_ABS_B : case BPF :: LD_ABS_H : case BPF :: LD_ABS_W : case BPF :: LD_IND_B : case BPF :: LD_IND_H : case BPF :: LD_IND_W : { auto Op = Instr . getOperand ( 0 ) ; Instr . clear ( ) ; Instr . addOperand ( MCOperand :: createReg ( BPF :: R6 ) ) ; Instr . addOperand ( Op ) ; break ; } } return Result ; } </s>

Returns the disassembly of a single instruction .


<s> rtx extract_pattern_from_insn ( rtx insn ) { if ( INSN_P ( insn ) ) return PATTERN ( insn ) ; return insn ; } </s>

Get the rtx in the PATTERN field of an insn . If INSN is not an insn , the funciton does n't change anything and returns it directly .


<s> HOST_WIDE_INT mips_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; compute_frame_size ( get_frame_size ( ) ) ; switch ( from ) { case FRAME_POINTER_REGNUM : offset = 0 ; break ; case ARG_POINTER_REGNUM : offset = ( cfun -> machine -> frame . total_size - current_function_pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM ) offset -= cfun -> machine -> frame . args_size ; return offset ; } </s>

Implement INITIAL_ELIMINATION_OFFSET . FROM is either the frame pointer or argument pointer . TO is either the stack pointer or hard frame pointer .


<s> bool ok_for_simple_arith_logic_operands ( rtx * , enum machine_mode ) { return ! visium_flags_exposed ; } </s>

Return true if the operands are valid for a simple arithmetic or logical insn .


<s> const char * loongarch_output_division ( const char * division , rtx * operands ) { const char * s ; s = division ; if ( TARGET_CHECK_ZERO_DIV ) { output_asm_insn ( s , operands ) ; s = "bne\t%2,%.,1f\n\tbreak\t7\n1:" ; } return s ; } </s>

Return the assembly code for DIV . { W/D } instruction DIVISION , which has the operands given by OPERANDS . Add in a divide-by-zero check if needed .


<s>
const
char
*
m68k_output_branch_integer
(
rtx_code
code
)
{
switch
(
code
)
{
case
EQ
:
return
"jeq %l3"
;
case
NE
:
return
"jne %l3"
;
case
GT
:
return
"jgt %l3"
;
case
GTU
:
return
"jhi %l3"
;
case
LT
:
return
"jlt %l3"
;
case
LTU
:
return
"jcs %l3"
;
case
GE
:
return
"jge %l3"
;
case
GEU
:
return
"jcc %l3"
;
case
LE
:
return
"jle %l3"
;
case
LEU
:
return
"jls %l3"
;
case
PLUS
:
return
"jpl %l3"
;
case
MINUS
:
return
"jmi %l3"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>

Return an output template for a branch with CODE .

m68k
"jeq %l3"
"jne %l3"
"jgt %l3"
"jhi %l3"
"jlt %l3"
"jcs %l3"
"jge %l3"
"jcc %l3"
"jle %l3"
"jls %l3"
"jpl %l3"
"jmi %l3"


<s> unsigned GBZ80InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = 0 ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) { continue ; } if ( ! isUnconditionalBranch ( * I ) && ! isConditionalBranch ( * I ) ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count ; } </s>

Remove the branching code at the end of the specific MBB .


<s> bool SIInstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { if ( isVOP1 ( MI ) || isVOP2 ( MI ) || isVOP3 ( MI ) || isSDWA ( MI ) ) { return ! MI . hasImplicitDef ( ) && MI . getNumImplicitOperands ( ) == MI . getDesc ( ) . getNumImplicitUses ( ) && ! MI . mayRaiseFPException ( ) ; } return false ; } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> void LanaiPassConfig :: addPreEmitPass ( ) { addPass ( createLanaiDelaySlotFillerPass ( getLanaiTargetMachine ( ) ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool SPUAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
bool
SparcAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
Operands
.
push_back
(
SparcOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
applyMnemonicAliases
(
Name
,
getAvailableFeatures
(
)
,
0
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
if
(
parseBranchModifiers
(
Operands
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Sparc
Sparc
SparcOperand::CreateToken
0
"unexpected token"
"unexpected token"
"unexpected token"
"unexpected token"


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= InsertITBlocks ( MBB ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> int s390_float_const_zero_p ( rtx value ) { return ( GET_MODE_CLASS ( GET_MODE ( value ) ) == MODE_FLOAT && value == CONST0_RTX ( GET_MODE ( value ) ) ) ; } </s>

Returns true if the input parameter VALUE is a float zero .


<s> static enum attr_type s390_safe_attr_type ( rtx_insn * insn ) { if ( recog_memoized ( insn ) >= 0 ) return get_attr_type ( insn ) ; else return TYPE_NONE ; } </s>


<s> void SPIRVAsmPrinter :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < SPIRVModuleAnalysis > ( ) ; AU . addPreserved < SPIRVModuleAnalysis > ( ) ; AsmPrinter :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int load_update_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) != MEM || GET_MODE ( op ) != mode ) return 0 ; op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) != PLUS || GET_MODE ( op ) != Pmode || ! register_operand ( XEXP ( op , 0 ) , Pmode ) || ! nonmemory_operand ( XEXP ( op , 1 ) , Pmode ) ) return 0 ; return 1 ; } </s>

Return true if OP is valid load with update operand .


<s>
void
rs6000_output_tlsargs
(
rtx
*
operands
)
{
rtx
op
[
3
]
;
op
[
0
]
=
operands
[
0
]
;
op
[
1
]
=
XVECEXP
(
operands
[
2
]
,
0
,
0
)
;
if
(
XINT
(
operands
[
2
]
,
1
)
==
UNSPEC_TLSGD
)
{
op
[
2
]
=
XVECEXP
(
operands
[
2
]
,
0
,
1
)
;
if
(
TARGET_CMODEL
!=
CMODEL_SMALL
)
output_asm_insn
(
"addis %0,%2,%1@got@tlsgd@ha\n\t"
"addi %0,%0,%1@got@tlsgd@l"
,
op
)
;
else
output_asm_insn
(
"addi %0,%2,%1@got@tlsgd"
,
op
)
;
}
else
if
(
XINT
(
operands
[
2
]
,
1
)
==
UNSPEC_TLSLD
)
{
if
(
TARGET_CMODEL
!=
CMODEL_SMALL
)
output_asm_insn
(
"addis %0,%1,%&@got@tlsld@ha\n\t"
"addi %0,%0,%&@got@tlsld@l"
,
op
)
;
else
output_asm_insn
(
"addi %0,%1,%&@got@tlsld"
,
op
)
;
}
else
gcc_unreachable
(
)
;
}
</s>

Output arg setup instructions for a ! TARGET_TLS_MARKERS __tls_get_addr call .


<s>
bool
ARMTargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeSizeInBits
(
SubVecTy
)
;
bool
EltIs64Bits
=
DL
.
getTypeSizeInBits
(
EltTy
)
==
64
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
||
EltIs64Bits
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
Op0
->
getType
(
)
->
getVectorNumElements
(
)
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
arm_neon_vst2
,
Intrinsic
::
arm_neon_vst3
,
Intrinsic
::
arm_neon_vst4
}
;
SmallVector
<
Value
*
,
6
>
Ops
;
Type
*
Int8Ptr
=
Builder
.
getInt8PtrTy
(
SI
->
getPointerAddressSpace
(
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
Int8Ptr
)
)
;
Type
*
Tys
[
]
=
{
Int8Ptr
,
SubVecTy
}
;
Function
*
VstNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
getInt32
(
SI
->
getAlignment
(
)
)
)
;
Builder
.
CreateCall
(
VstNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


"  Skipping pass: no machine model present.\n"


<s> bool WebAssemblyPassConfig :: addInstSelector ( ) { addPass ( createWebAssemblyISelDag ( getWebAssemblyTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: M0 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_SHARED_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_BASE ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_PRIVATE_LIMIT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SRC_POPS_EXITING_WAVE_ID ) ; reserveRegisterTuples ( Reserved , AMDGPU :: XNACK_MASK ) ; reserveRegisterTuples ( Reserved , AMDGPU :: LDS_DIRECT ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TBA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TMA ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP0_TTMP1 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP2_TTMP3 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP4_TTMP5 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP6_TTMP7 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP8_TTMP9 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP10_TTMP11 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP12_TTMP13 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: TTMP14_TTMP15 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SGPR_NULL ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = AMDGPU :: VGPR_32RegClass . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = AMDGPU :: VGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } unsigned FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , FrameReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , FrameReg ) ) ; } for ( unsigned Reg : MFI -> WWMReservedRegs ) { reserveRegisterTuples ( Reserved , Reg ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> Register RISCVTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return RISCVABI :: isCheriPureCapABI ( Subtarget . getTargetABI ( ) ) ? RISCV :: C10 : RISCV :: X10 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } if ( getOptLevel ( ) <= EnableGlobalISelAtO ) setGlobalISel ( true ) ; setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; } </s>


<s>
InstructionCost
AArch64TTIImpl
::
getGatherScatterOpCost
(
unsigned
Opcode
,
Type
*
DataTy
,
const
Value
*
Ptr
,
bool
VariableMask
,
Align
Alignment
,
TTI
::
TargetCostKind
CostKind
,
const
Instruction
*
I
)
{
if
(
!
isa
<
ScalableVectorType
>
(
DataTy
)
)
return
BaseT
::
getGatherScatterOpCost
(
Opcode
,
DataTy
,
Ptr
,
VariableMask
,
Alignment
,
CostKind
,
I
)
;
auto
*
VT
=
cast
<
VectorType
>
(
DataTy
)
;
auto
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
DataTy
)
;
ElementCount
LegalVF
=
LT
.
second
.
getVectorElementCount
(
)
;
Optional
<
unsigned
>
MaxNumVScale
=
getMaxVScale
(
)
;
assert
(
MaxNumVScale
&&
"Expected valid max vscale value"
)
;
InstructionCost
MemOpCost
=
getMemoryOpCost
(
Opcode
,
VT
->
getElementType
(
)
,
Alignment
,
0
,
CostKind
,
I
)
;
unsigned
MaxNumElementsPerGather
=
MaxNumVScale
.
getValue
(
)
*
LegalVF
.
getKnownMinValue
(
)
;
return
LT
.
first
*
MaxNumElementsPerGather
*
MemOpCost
;
}
</s>

Calculate the cost of Gather / Scatter operation .


<s> static inline SPIRV :: SpecialTypeDescriptor getEmptyKey ( ) { return SPIRV :: SpecialTypeDescriptor ( SPIRV :: SpecialTypeDescriptor :: STK_Empty ) ; } </s>

Empty key : no key should be generated that has no DILocalVariable .

SPIRV SPIRV::SpecialTypeDescriptor SPIRV::SpecialTypeDescriptor SPIRV::SpecialTypeDescriptor


<s> bool Z80AsmParser :: ParseDirective ( AsmToken DirectiveID ) { llvm_unreachable ( "Unimplemented" ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Z80old Assembly / Object Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> static tree mips_builtin_vectorized_function ( unsigned int fn , tree type_out , tree type_in ) { machine_mode in_mode , out_mode ; int in_n , out_n ; if ( TREE_CODE ( type_out ) != VECTOR_TYPE || TREE_CODE ( type_in ) != VECTOR_TYPE || ! ISA_HAS_MSA ) return NULL_TREE ; out_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; out_n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; mips_builtin_decls [ mips_get_builtin_decl_index [ CODE_FOR_ ## INSN ] ] switch ( fn ) { case BUILT_IN_SQRT : if ( out_mode == DFmode && out_n == 2 && in_mode == DFmode && in_n == 2 ) return MIPS_GET_BUILTIN ( msa_fsqrt_d ) ; break ; case BUILT_IN_SQRTF : if ( out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4 ) return MIPS_GET_BUILTIN ( msa_fsqrt_w ) ; break ; default : break ; } </s>


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { Register VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg ; } </s>

addLiveIn - Add the specified register as a live-in .


"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


Return an array that contains the direct target flag values and their names .

Mips Mips Mips "mips-got" "mips-got-call" "mips-gprel" "mips-abs-hi" "mips-abs-lo" "mips-tlsgd" "mips-tlsldm" "mips-dtprel-hi" "mips-dtprel-lo" "mips-gottprel" "mips-tprel-hi" "mips-tprel-lo" "mips-gpoff-hi" "mips-gpoff-lo" "mips-got-disp" "mips-got-page" "mips-got-ofst" "mips-higher" "mips-highest" "mips-got-hi16" "mips-got-lo16" "mips-call-hi16" "mips-call-lo16"


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - STI -> isTargetDarwin ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> unsigned HexagonInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { return getInstrTimingClassLatency ( ItinData , MI ) ; } </s>

Compute the instruction latency of a given instruction .


<s> void setKind ( BaseKind K ) { Kind = K ; } </s>


<s> const char * BPFTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case BPFISD :: RET_FLAG : return "BPFISD::RET_FLAG" ; case BPFISD :: CALL : return "BPFISD::CALL" ; case BPFISD :: SELECT_CC : return "BPFISD::SELECT_CC" ; case BPFISD :: BR_CC : return "BPFISD::BR_CC" ; case BPFISD :: Wrapper : return "BPFISD::Wrapper" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static const char * rs6000_get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , rs6000_get_some_local_dynamic_name_1 , 0 ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable ( ) ; } </s>

Locate some local-dynamic symbol still in use by this function so that we can print its name in some tls_ld pattern .


<s> bool runOnModule ( Module & M ) override { Context = & M . getContext ( ) ; Int32Type = Type :: getInt32Ty ( M . getContext ( ) ) ; ImageSizeType = ArrayType :: get ( Int32Type , 3 ) ; ImageFormatType = ArrayType :: get ( Int32Type , 2 ) ; return transformKernels ( M ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool analyzeSelect ( const MachineInstr & MI , SmallVectorImpl < MachineOperand > & Cond , unsigned & TrueOp , unsigned & FalseOp , bool & Optimizable ) const override { return false ; } </s>

Analyze the given select instruction , returning true if it can not be understood .


<s> void addPreSched2 ( ) override { addPass ( & IfConverterID , false ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createX86MachObjectWriter ( OS , true , MachO :: CPU_TYPE_X86_64 , Subtype ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


"Encoding of this operand type is not supported yet."

getMachineOpValue - Return binary encoding of operand .


<s>
static
const
char
*
output_branch
(
rtx
label
,
const
char
*
cond
,
rtx_insn
*
insn
)
{
char
str
[
64
]
;
rtx
operands
[
2
]
;
gcc_assert
(
cond
)
;
operands
[
0
]
=
label
;
if
(
get_attr_length
(
insn
)
>
8
)
{
bool
spilled
;
if
(
current_function_saves_lr
(
)
)
{
operands
[
1
]
=
regno_reg_rtx
[
LINK_REGNUM
]
;
spilled
=
false
;
}
else
if
(
!
df_regs_ever_live_p
(
long_branch_regnum
)
)
{
operands
[
1
]
=
regno_reg_rtx
[
long_branch_regnum
]
;
spilled
=
false
;
}
else
{
operands
[
1
]
=
regno_reg_rtx
[
long_branch_regnum
]
;
spilled
=
true
;
gcc_assert
(
current_function_has_lr_slot
(
)
)
;
}
if
(
spilled
)
{
if
(
final_sequence
)
{
rtx_insn
*
delay
=
NEXT_INSN
(
insn
)
;
gcc_assert
(
delay
)
;
final_scan_insn
(
delay
,
asm_out_file
,
optimize
,
0
,
)
;
PATTERN
(
delay
)
=
gen_blockage
(
)
;
INSN_CODE
(
delay
)
=
1
;
}
if
(
current_function_saves_fp
(
)
)
output_asm_insn
(
"write.l 1(sp),%1"
,
operands
)
;
else
output_asm_insn
(
"write.l (sp),%1"
,
operands
)
;
}
output_asm_insn
(
"moviu   %1,%%u %0"
,
operands
)
;
output_asm_insn
(
"movil   %1,%%l %0"
,
operands
)
;
strcpy
(
str
,
"bra     "
)
;
strcat
(
str
,
cond
)
;
strcat
(
str
,
",%1,%1"
)
;
if
(
!
spilled
)
strcat
(
str
,
"%#"
)
;
strcat
(
str
,
"\t\t;long branch"
)
;
output_asm_insn
(
str
,
operands
)
;
if
(
spilled
)
{
if
(
current_function_saves_fp
(
)
)
output_asm_insn
(
" read.l %1,1(sp)"
,
operands
)
;
else
output_asm_insn
(
" read.l %1,(sp)"
,
operands
)
;
}
}
else
if
(
label
==
pc_rtx
)
{
strcpy
(
str
,
"bra     "
)
;
strcat
(
str
,
cond
)
;
strcat
(
str
,
",r21,r0%#\t\t;return"
)
;
output_asm_insn
(
str
,
operands
)
;
}
else
{
strcpy
(
str
,
"brr     "
)
;
strcat
(
str
,
cond
)
;
strcat
(
str
,
",%0%#"
)
;
output_asm_insn
(
str
,
operands
)
;
}
return
""
;
}
</s>

Output a conditional/unconditional branch to LABEL . COND is the string condition . INSN is the instruction .


<s> static inline enum insn_code rs6000_htm_spr_icode ( bool nonvoid ) { if ( nonvoid ) return ( TARGET_POWERPC64 ) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si ; else return ( TARGET_POWERPC64 ) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si ; } </s>

Return the correct ICODE value depending on whether we are setting or reading the HTM SPRs .


<s> bool SystemZInstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & SystemZ :: FP64RegClass ) loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } unsigned LowReg = MFI -> getLowReg ( ) , HighReg = MFI -> getHighReg ( ) ; unsigned StartOffset = RegSpillOffsets [ LowReg ] ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? SystemZ :: MOV64rm : SystemZ :: MOV64rmm ) ) ) ; MIB . addReg ( LowReg , RegState :: Define ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Define ) ; MIB . addReg ( ( RegInfo -> hasFP ( MF ) ? SystemZ :: R11D : SystemZ :: R15D ) ) ; MIB . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( 0 ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static bool m32r_in_small_data_p ( tree decl ) { tree section ; if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( lookup_attribute ( "model" , DECL_ATTRIBUTES ( decl ) ) ) return false ; section = DECL_SECTION_NAME ( decl ) ; if ( section ) { char * name = ( char * ) TREE_STRING_POINTER ( section ) ; if ( strcmp ( name , ".sdata" ) == 0 || strcmp ( name , ".sbss" ) == 0 ) return true ; } else { if ( ! TREE_READONLY ( decl ) && ! TARGET_SDATA_NONE ) { int size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; if ( size > 0 && ( unsigned HOST_WIDE_INT ) size <= g_switch_value ) return true ; } } return false ; } </s>

Only mark the object as being small data area addressable if it has n't been explicitly marked with a code model . The user can explicitly put an object in the small data area with the section attribute . If the object is in sdata/sbss and marked with a code model do both [ put the object in .sdata and mark it as being addressed with a specific code model - do n't mark it as being addressed with an SDA reloc though ] . This is ok and might be useful at times . If the object does n't fit the linker will give an error .


<s> TargetTransformInfo LanaiTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( LanaiTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> inline bool pr_or_ffr_regnum_p ( unsigned int regno ) { return PR_REGNUM_P ( regno ) || regno == FFR_REGNUM || regno == FFRT_REGNUM ; } </s>

Return true if REGNO is P0-P15 or one of the special FFR-related registers .


<s>
bool
MCS51AsmBackend
::
writeNopData
(
raw_ostream
&
OS
,
uint64_t
Count
)
const
{
assert
(
(
Count
%
2
)
==
0
&&
"NOP instructions must be 2 bytes"
)
;
OS
.
write_zeros
(
Count
)
;
return
true
;
}
</s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const SystemZSubtarget & Subtarget = MF -> getSubtarget < SystemZSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return CSR_SystemZ_NoRegs_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_SystemZ_AllRegs_Vector_SaveList : CSR_SystemZ_AllRegs_SaveList ; if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_SaveList ; return CSR_SystemZ_SaveList ; } </s>

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> bool MipsAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count ) ; return true ; } </s>


<s> int m68k_sched_address_bypass_p ( rtx_insn * pro , rtx_insn * con ) { rtx pro_x ; rtx con_mem_read ; pro_x = sched_get_reg_operand ( pro , true ) ; if ( pro_x == NULL ) return 0 ; con_mem_read = sched_get_mem_operand ( con , true , false ) ; gcc_assert ( con_mem_read != NULL ) ; if ( reg_mentioned_p ( pro_x , con_mem_read ) ) return 1 ; return 0 ; } </s>

Return non-zero if PRO modifies register used as part of address in CON .


<s> bool isImm ( ) const { return Kind == k_Immediate ; } </s>


<s> static bool ix86_profile_before_prologue ( void ) { return flag_fentry != 0 ; } </s>

Return true , if profiling code should be emitted before prologue . Otherwise it returns false . Note : For x86 with `` hotfix '' it is sorried .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
TM
=
&
Func
.
getTarget
(
)
;
const
X86Subtarget
&
ST
=
TM
->
getSubtarget
<
X86Subtarget
>
(
)
;
if
(
!
ST
.
LEAusesAG
(
)
&&
!
ST
.
slowLEA
(
)
)
return
false
;
TII
=
static_cast
<
const
X86InstrInfo
*
>
(
TM
->
getInstrInfo
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static arm_stack_offsets * arm_get_frame_offsets ( void ) { struct arm_stack_offsets * offsets ; offsets = & cfun -> machine -> stack_offsets ; return offsets ; } </s>

Calculate stack offsets . These are used to calculate register elimination offsets and in prologue/epilogue code . Also calculates which registers should be saved .


<s> int c6x_nsaved_regs ( void ) { int nregs = 0 ; int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( c6x_save_reg ( regno ) ) nregs ++ ; return nregs ; } </s>

Return number of saved general prupose registers .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute TuneAttr = F . getFnAttribute ( "tune-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) : ( StringRef ) CPU ; StringRef FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; unsigned PreferVectorWidthOverride = 0 ; Attribute PreferVecWidthAttr = F . getFnAttribute ( "prefer-vector-width" ) ; if ( PreferVecWidthAttr . isValid ( ) ) { StringRef Val = PreferVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += 'p' ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; Attribute MinLegalVecWidthAttr = F . getFnAttribute ( "min-legal-vector-width" ) ; if ( MinLegalVecWidthAttr . isValid ( ) ) { StringRef Val = MinLegalVecWidthAttr . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( 0 , Width ) ) { Key += 'm' ; Key += Val ; RequiredVectorWidth = Width ; } } Key += CPU ; Key += TuneCPU ; unsigned FSStart = Key . size ( ) ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : "+soft-float," ; Key += FS ; FS = Key . substr ( FSStart ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < X86Subtarget > ( TargetTriple , CPU , TuneCPU , FS , * this , MaybeAlign ( Options . StackAlignmentOverride ) , PreferVectorWidthOverride , RequiredVectorWidth ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool M88kInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { TBB = FBB = nullptr ; Cond . clear ( ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return false ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = 0 ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > 2 ) return true ; if ( ! isAnalyzableBranchOpc ( I -> getOpcode ( ) ) || ( NumTerminators == 2 && ! isAnalyzableBranchOpc ( std :: prev ( I ) -> getOpcode ( ) ) ) ) return true ; if ( NumTerminators == 1 && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == 1 && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == 2 && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = getBranchDestBlock ( * I ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> MachineBasicBlock :: iterator TOYFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == TOY :: ADJCALLSTACKUP || I -> getOpcode ( ) == TOY :: ADJCALLSTACKDOWN ) { return MBB . erase ( I ) ; } return MBB . end ( ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

TOY TOY TOY::ADJCALLSTACKUP TOY::ADJCALLSTACKDOWN


<s> bool ECLairAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool has ( unsigned R ) const { unsigned Idx = v2x ( R ) ; if ( Idx >= Bits . size ( ) ) return false ; return Bits . test ( Idx ) ; } </s>

Tests whether a library function is available .


<s>
static
SPIRV
::
Scope
getScope
(
SyncScope
::
ID
Ord
)
{
switch
(
Ord
)
{
case
SyncScope
::
SingleThread
:
return
SPIRV
::
Scope
::
Invocation
;
case
SyncScope
::
System
:
return
SPIRV
::
Scope
::
Device
;
default
:
llvm_unreachable
(
"Unsupported synchronization Scope ID."
)
;
}
}
</s>

SPIRV
SPIRV::Scope
SPIRV::Scope
SPIRV::Scope
"Unsupported synchronization Scope ID."


<s> tree gcn_goacc_adjust_propagation_record ( tree record_type , bool sender , const char * name ) { tree type = record_type ; TYPE_ADDR_SPACE ( type ) = ADDR_SPACE_LDS ; if ( ! sender ) type = build_pointer_type ( type ) ; tree decl = create_tmp_var_raw ( type , name ) ; if ( sender ) { DECL_CONTEXT ( decl ) = NULL_TREE ; TREE_STATIC ( decl ) = 1 ; } if ( sender ) varpool_node :: finalize_decl ( decl ) ; return decl ; } </s>

Implement TARGET_GOACC_ADJUST_PROPAGATION_RECORD . Tweak ( worker ) propagation record , e.g . to put it in shared memory .


<s> const WebAssemblyRegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"br_on_exn does not have a reversed condition"

Insert branch code into the end of the specified MachineBasicBlock .


<s>
SDValue
CJGTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

CJG
CJG
ISD::BR_CC
ISD::SELECT_CC
ISD::GlobalAddress
ISD::ExternalSymbol
"unimplemented operand"


<s> int sh2a_get_function_vector_number ( rtx x ) { int num ; tree list , t ; if ( ( GET_CODE ( x ) == SYMBOL_REF ) && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { t = SYMBOL_REF_DECL ( x ) ; if ( TREE_CODE ( t ) != FUNCTION_DECL ) return 0 ; list = SH_ATTRIBUTES ( t ) ; while ( list ) { if ( is_attribute_p ( "function_vector" , TREE_PURPOSE ( list ) ) ) { num = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( list ) ) ) ; return num ; } list = TREE_CHAIN ( list ) ; } return 0 ; } else return 0 ; } </s>

Returns the function vector number , if the attribute 'function_vector ' is assigned , otherwise returns zero .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { uint8_t Bytes [ 4 ] ; Size = 4 ; if ( Region . readBytes ( Address , Size , Bytes ) == - 1 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = ( Bytes [ 0 ] << 24 ) | ( Bytes [ 1 ] << 16 ) | ( Bytes [ 2 ] << 8 ) | ( Bytes [ 3 ] << 0 ) ; return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> static unsigned int compute_saved_regs ( ) { unsigned int saved_regs = 0 ; int regno ; for ( regno = 0 ; regno <= 6 ; regno ++ ) { if ( WORD_REG_USED ( regno ) ) saved_regs |= 1 << regno ; } if ( frame_pointer_needed ) saved_regs &= ~ ( 1 << FRAME_POINTER_REGNUM ) ; return saved_regs ; } </s>

Compute which registers to push/pop . Return a bit vector of registers .


"C++ constructor pointer had zero size!"

"C++ constructor pointer was not a GlobalValue!"

Targets can override this to change how global constants that are part of a C++ static/global constructor list are emitted .


<s>
MCSymbol
*
AAPMCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .

AAP
AAP
"Unknown target flag on GV operand"
0


<s> const RV16KInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void X86FrameLowering :: BuildCFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , MCCFIInstruction CFIInst ) const { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFIIndex = MF . getMMI ( ) . addFrameInst ( CFIInst ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

Wraps up getting a CFI index and building a MachineInstr for it .


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> TargetIRAnalysis AMDGPUTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( AMDGPUTTIImpl ( this , F . getParent ( ) -> getDataLayout ( ) ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> bool SPUFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> getStackSize ( ) && ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .