<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( is64bit ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s> static tree xtensa_build_builtin_va_list ( void ) { tree f_stk , f_reg , f_ndx , record , type_decl ; record = ( * lang_hooks . types . make_type ) ( RECORD_TYPE ) ; type_decl = build_decl ( BUILTINS_LOCATION , TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; f_stk = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__va_stk" ) , ptr_type_node ) ; f_reg = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__va_reg" ) , ptr_type_node ) ; f_ndx = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__va_ndx" ) , integer_type_node ) ; DECL_FIELD_CONTEXT ( f_stk ) = record ; DECL_FIELD_CONTEXT ( f_reg ) = record ; DECL_FIELD_CONTEXT ( f_ndx ) = record ; TYPE_STUB_DECL ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_stk ; DECL_CHAIN ( f_stk ) = f_reg ; DECL_CHAIN ( f_reg ) = f_ndx ; layout_type ( record ) ; return record ; } </s>

Create the va_list data type . This structure is set up by __builtin_saveregs . The __va_reg field points to a stack-allocated region holding the contents of the incoming argument registers . The __va_ndx field is an index initialized to the position of the first unnamed ( variable ) argument . This same index is also used to address the arguments passed in memory . Thus , the __va_stk field is initialized to point to the position of the first argument in memory offset to account for the arguments passed in registers and to account for the size of the argument registers not being 16-byte aligned . E.G. , there are 6 argument registers of 4 bytes each , but we want the __va_ndx for the first stack argument to have the maximal alignment of 16 bytes , so we offset the __va_stk address by 32 bytes so that __va_stk [ 32 ] references the first argument on the stack .


<s> static int aarch64_reassociation_width ( unsigned opc ATTRIBUTE_UNUSED , enum machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) return aarch64_tune_params -> vec_reassoc_width ; if ( INTEGRAL_MODE_P ( mode ) ) return aarch64_tune_params -> int_reassoc_width ; if ( FLOAT_MODE_P ( mode ) ) return aarch64_tune_params -> fp_reassoc_width ; return 1 ; } </s>

Return the reassociation width of treeop OPC with mode MODE .


<s> uint64_t getStackSize ( ) { return StackSize ; } </s>

Return the number of bytes that must be allocated to hold all of the fixed size frame objects .


<s> bool isTarget64BitLP64 ( ) const { return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple :: GNUX32 && ! TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the LP64 programming model ( standard AMD64 , no x32 ) ?


<s> enum reg_class mcore_secondary_reload_class ( enum reg_class rclass , machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( TEST_HARD_REG_BIT ( reg_class_contents [ rclass ] , 15 ) && ! mcore_r15_operand_p ( x ) ) return LRW_REGS ; return NO_REGS ; } </s>

Implement SECONDARY_RELOAD_CLASS . If CLASS contains r15 , and we ca n't directly move X into it , use r1-r14 as a temporary .


<s>
static
bool
Check
(
DecodeStatus
&
Out
,
DecodeStatus
In
)
{
switch
(
In
)
{
case
MCDisassembler
::
Success
:
return
true
;
case
MCDisassembler
::
SoftFail
:
Out
=
In
;
return
true
;
case
MCDisassembler
::
Fail
:
Out
=
In
;
return
false
;
}
llvm_unreachable
(
"Invalid DecodeStatus!"
)
;
}
</s>

Matches check string and its `` not strings '' and/or `` dag strings '' .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU Lower Kernel Calls"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int valid_parallel_load_store ( rtx * operands , enum machine_mode mode ATTRIBUTE_UNUSED ) { rtx op0 = operands [ 0 ] ; rtx op1 = operands [ 1 ] ; rtx op2 = operands [ 2 ] ; rtx op3 = operands [ 3 ] ; if ( GET_CODE ( op0 ) == SUBREG ) op0 = SUBREG_REG ( op0 ) ; if ( GET_CODE ( op1 ) == SUBREG ) op1 = SUBREG_REG ( op1 ) ; if ( GET_CODE ( op2 ) == SUBREG ) op2 = SUBREG_REG ( op2 ) ; if ( GET_CODE ( op3 ) == SUBREG ) op3 = SUBREG_REG ( op3 ) ; if ( GET_CODE ( op0 ) == REG && ( ( GET_CODE ( op2 ) == MEM && reg_mentioned_p ( op0 , XEXP ( op2 , 0 ) ) ) || ( GET_CODE ( op3 ) == MEM && reg_mentioned_p ( op0 , XEXP ( op3 , 0 ) ) ) ) ) return 0 ; if ( GET_CODE ( op0 ) == REG && GET_CODE ( op2 ) == REG ) return ( REGNO ( op0 ) != REGNO ( op2 ) ) && GET_CODE ( op1 ) == MEM && GET_CODE ( op3 ) == MEM && ! c4x_address_conflict ( op1 , op3 , 0 , 0 ) ; if ( GET_CODE ( op1 ) == REG && GET_CODE ( op3 ) == REG ) return GET_CODE ( op0 ) == MEM && GET_CODE ( op2 ) == MEM && ! c4x_address_conflict ( op0 , op2 , 1 , 1 ) ; if ( GET_CODE ( op0 ) == REG && GET_CODE ( op3 ) == REG ) return GET_CODE ( op1 ) == MEM && GET_CODE ( op2 ) == MEM && ! c4x_address_conflict ( op1 , op2 , 0 , 1 ) ; if ( GET_CODE ( op1 ) == REG && GET_CODE ( op2 ) == REG ) return GET_CODE ( op0 ) == MEM && GET_CODE ( op3 ) == MEM && ! c4x_address_conflict ( op0 , op3 , 1 , 0 ) ; return 0 ; } </s>

Validate combination of operands for parallel load/store instructions .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static bool aarch64_evpc_zip ( struct expand_vec_perm_d * d ) { unsigned int high ; poly_uint64 nelt = d -> perm . length ( ) ; rtx out , in0 , in1 , x ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; poly_uint64 first = d -> perm [ 0 ] ; if ( ( maybe_ne ( first , 0U ) && maybe_ne ( first * 2 , nelt ) ) || ! d -> perm . series_p ( 0 , 2 , first , 1 ) || ! d -> perm . series_p ( 1 , 2 , first + nelt , 1 ) ) return false ; high = maybe_ne ( first , 0U ) ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1 , in1 = x ; high = ! high ; } out = d -> target ; emit_set_insn ( out , gen_rtx_UNSPEC ( vmode , gen_rtvec ( 2 , in0 , in1 ) , high ? UNSPEC_ZIP2 : UNSPEC_ZIP1 ) ) ; return true ; } </s>

Recognize patterns suitable for the ZIP instructions .


<s> void X86WinCOFFStreamer :: emitCVFPOData ( const MCSymbol * ProcSym , SMLoc Loc ) { X86TargetStreamer * XTS = static_cast < X86TargetStreamer * > ( getTargetStreamer ( ) ) ; XTS -> emitFPOData ( ProcSym , Loc ) ; } </s>

This implements the CodeView '.cv_fpo_data ' assembler directive .


<s>
void
cris_asm_output_case_end
(
FILE
*
stream
,
int
num
,
rtx_insn
*
table
)
{
rtx_insn
*
whole_jump_insn
=
prev_nonnote_nondebug_insn
(
table
)
;
gcc_assert
(
whole_jump_insn
!=
NULL_RTX
&&
LABEL_P
(
whole_jump_insn
)
)
;
whole_jump_insn
=
prev_nonnote_nondebug_insn
(
whole_jump_insn
)
;
gcc_assert
(
whole_jump_insn
!=
NULL_RTX
&&
JUMP_P
(
whole_jump_insn
)
)
;
rtx
whole_jump_pat
=
PATTERN
(
whole_jump_insn
)
;
asm_fprintf
(
stream
,
"\t.word %LL%d-%LL%d%s\n"
,
CODE_LABEL_NUMBER
(
XEXP
(
XEXP
(
XEXP
(
XVECEXP
(
whole_jump_pat
,
0
,
0
)
,
1
)
,
2
)
,
0
)
)
,
num
,
(
TARGET_PDEBUG
"; default"
:
""
)
)
;
}
</s>


<s> const SpillSlot * getCalleeSavedSpillSlots ( unsigned & NumEntries ) const override { static const SpillSlot Offsets [ ] = { { VE :: SX17 , 40 } , { VE :: SX18 , 48 } , { VE :: SX19 , 56 } , { VE :: SX20 , 64 } , { VE :: SX21 , 72 } , { VE :: SX22 , 80 } , { VE :: SX23 , 88 } , { VE :: SX24 , 96 } , { VE :: SX25 , 104 } , { VE :: SX26 , 112 } , { VE :: SX27 , 120 } , { VE :: SX28 , 128 } , { VE :: SX29 , 136 } , { VE :: SX30 , 144 } , { VE :: SX31 , 152 } , { VE :: SX32 , 160 } , { VE :: SX33 , 168 } } ; NumEntries = array_lengthof ( Offsets ) ; return Offsets ; } </s>

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs , that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool SIDebuggerInsertNops :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; if ( ! ST . debuggerInsertNops ( ) ) return false ; if ( ! MF . getMMI ( ) . hasDebugInfo ( ) ) return false ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; DenseSet < unsigned > NopInserted ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( MI -> isDebugInstr ( ) || ! MI -> getDebugLoc ( ) ) continue ; auto DL = MI -> getDebugLoc ( ) ; if ( NopInserted . find ( DL . getLine ( ) ) == NopInserted . end ( ) ) { BuildMI ( MBB , * MI , DL , TII -> get ( AMDGPU :: S_NOP ) ) . addImm ( 0 ) ; NopInserted . insert ( DL . getLine ( ) ) ; } } } return true ; } </s>


<s> void HexagonPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableExpandCondsets ) insertPass ( & RegisterCoalescerID , & HexagonExpandCondsetsID ) ; if ( ! DisableStoreWidening ) addPass ( createHexagonStoreWidening ( ) , false ) ; if ( ! DisableHardwareLoops ) addPass ( createHexagonHardwareLoops ( ) , false ) ; } if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default ) addPass ( & MachinePipelinerID ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool ARMTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( ! Subtarget -> hasVFP3Base ( ) ) return false ; if ( VT == MVT :: f16 && Subtarget -> hasFullFP16 ( ) ) return ARM_AM :: getFP16Imm ( Imm ) != - 1 ; if ( VT == MVT :: f32 ) return ARM_AM :: getFP32Imm ( Imm ) != - 1 ; if ( VT == MVT :: f64 && Subtarget -> hasFP64 ( ) ) return ARM_AM :: getFP64Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static bool has_memory_op ( rtx_insn * mem_insn ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( mem_insn ) , ALL ) if ( MEM_P ( * iter ) ) return true ; return false ; } </s>

Return true if the rtx_insn contains a MEM RTX somewhere in it .


<s> void TL45DAGToDAGISel :: Select ( SDNode * Node ) { if ( Node -> isMachineOpcode ( ) ) { Node -> setNodeId ( - 1 ) ; return ; } unsigned Opcode = Node -> getOpcode ( ) ; MVT XLenVT = MVT :: i32 ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( 0 ) ; switch ( Opcode ) { case ISD :: Constant : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , TL45 :: r0 , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == MVT :: i32 ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case ISD :: FrameIndex : { SDValue Imm = CurDAG -> getTargetConstant ( 0 , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( TL45 :: ADDI , DL , VT , TFI , Imm ) ) ; return ; } } SelectCode ( Node ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> MCFragment * findAssociatedFragment ( ) const override { return nullptr ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> bool s390_hard_regno_rename_ok ( unsigned int old_reg , unsigned int new_reg ) { if ( cfun -> machine -> base_reg ) if ( REGNO ( cfun -> machine -> base_reg ) == old_reg || REGNO ( cfun -> machine -> base_reg ) == new_reg ) return false ; if ( GENERAL_REGNO_P ( new_reg ) && ! call_used_regs [ new_reg ] && cfun_gpr_save_slot ( new_reg ) == SAVE_SLOT_NONE ) return false ; return true ; } </s>

Return nonzero if register OLD_REG can be renamed to register NEW_REG .


<s> unsigned PPCInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: STD : case PPC :: STW : case PPC :: STFS : case PPC :: STFD : case PPC :: SPILL_CR : case PPC :: SPILL_CRBIT : case PPC :: STVX : case PPC :: STXVD2X : case PPC :: QVSTFDX : case PPC :: QVSTFSXs : case PPC :: QVSTFDXb : case PPC :: SPILL_VRSAVE : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> unsigned MMIXMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; MCFixupKind Kind = static_cast < MCFixupKind > ( MMIX :: fixup_mmix_rel_16 ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , Kind ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> static bool nds32_expand_cpymemsi_loop_unknown_size ( rtx dstmem , rtx srcmem , rtx size , rtx alignment ) { rtx dst_base_reg , src_base_reg ; rtx dst_itr , src_itr ; rtx dstmem_m , srcmem_m , dst_itr_m , src_itr_m ; rtx dst_end ; rtx size_least_3_bit ; rtx double_word_end ; rtx double_word_mode_loop , byte_mode_entry , byte_mode_loop , end_label ; rtx tmp ; rtx mask_least_3_bit ; int start_regno ; bool align_to_4_bytes = ( INTVAL ( alignment ) & 3 ) == 0 ; if ( TARGET_ISA_V3M && ! align_to_4_bytes ) return 0 ; if ( TARGET_REDUCED_REGS ) start_regno = 2 ; else start_regno = 16 ; dst_itr = gen_reg_rtx ( Pmode ) ; src_itr = gen_reg_rtx ( Pmode ) ; dst_end = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( QImode ) ; mask_least_3_bit = GEN_INT ( ~ 7 ) ; double_word_mode_loop = gen_label_rtx ( ) ; byte_mode_entry = gen_label_rtx ( ) ; byte_mode_loop = gen_label_rtx ( ) ; end_label = gen_label_rtx ( ) ; dst_base_reg = copy_to_mode_reg ( Pmode , XEXP ( dstmem , 0 ) ) ; src_base_reg = copy_to_mode_reg ( Pmode , XEXP ( srcmem , 0 ) ) ; size_least_3_bit = expand_binop ( SImode , and_optab , size , mask_least_3_bit , NULL_RTX , 0 , OPTAB_WIDEN ) ; dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_cmp_and_jump_insns ( size_least_3_bit , const0_rtx , EQ , NULL , SImode , 1 , byte_mode_entry ) ; double_word_end = expand_binop ( Pmode , add_optab , dst_base_reg , size_least_3_bit , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_label ( double_word_mode_loop ) ; src_itr_m = src_itr ; dst_itr_m = dst_itr ; srcmem_m = srcmem ; dstmem_m = dstmem ; nds32_emit_mem_move_block ( start_regno , 2 , & dst_itr_m , & dstmem_m , & src_itr_m , & srcmem_m , true ) ; emit_move_insn ( dst_itr , dst_itr_m ) ; emit_move_insn ( src_itr , src_itr_m ) ; emit_cmp_and_jump_insns ( double_word_end , dst_itr , NE , NULL , Pmode , 1 , double_word_mode_loop ) ; emit_label ( byte_mode_entry ) ; emit_cmp_and_jump_insns ( dst_itr , dst_end , EQ , NULL , Pmode , 1 , end_label ) ; emit_label ( byte_mode_loop ) ; nds32_emit_post_inc_load_store ( tmp , src_itr , QImode , true ) ; nds32_emit_post_inc_load_store ( tmp , dst_itr , QImode , false ) ; emit_cmp_and_jump_insns ( dst_itr , dst_end , NE , NULL , SImode , 1 , byte_mode_loop ) ; emit_label ( end_label ) ; return true ; } </s>

Auxiliary function for expand cpymem pattern .


<s> void HexagonFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned TargetAlign = MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = RoundUpToAlignment ( maxCallFrameSize , TargetAlign ) ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = RoundUpToAlignment ( FrameSize , TargetAlign ) ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> int compute_a_shift_cc ( rtx operands [ 3 ] , rtx_code code ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum shift_type shift_type ; enum shift_mode shift_mode ; struct shift_info info ; int n ; switch ( mode ) { case E_QImode : shift_mode = QIshift ; break ; case E_HImode : shift_mode = HIshift ; break ; case E_SImode : shift_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFTRT : shift_type = SHIFT_ASHIFTRT ; break ; case LSHIFTRT : shift_type = SHIFT_LSHIFTRT ; break ; case ASHIFT : shift_type = SHIFT_ASHIFT ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) ; n = INTVAL ( operands [ 2 ] ) ; if ( n < 0 ) n = 0 ; else if ( ( unsigned int ) n > GET_MODE_BITSIZE ( mode ) ) n = GET_MODE_BITSIZE ( mode ) ; get_shift_alg ( shift_type , shift_mode , n , & info ) ; switch ( info . alg ) { case SHIFT_SPECIAL : if ( info . remainder == 0 ) return ( info . cc_special == OLD_CC_SET_ZN || info . cc_special == OLD_CC_SET_ZNV ) ; case SHIFT_INLINE : return ( info . cc_inline == OLD_CC_SET_ZN || info . cc_inline == OLD_CC_SET_ZNV ) ; case SHIFT_ROT_AND : return true ; case SHIFT_LOOP : if ( info . shift2 != NULL ) { if ( n % 2 ) return ( info . cc_inline == OLD_CC_SET_ZN || info . cc_inline == OLD_CC_SET_ZNV ) ; } return false ; default : gcc_unreachable ( ) ; } } </s>

Compute which flag bits are valid after a shift insn .


<s> const PPCRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool arc_check_ior_const ( HOST_WIDE_INT ival ) { unsigned int mask = ( unsigned int ) ( ival & 0xffffffff ) ; if ( UNSIGNED_INT6 ( ival ) || IS_POWEROF2_P ( mask ) ) return false ; if ( __builtin_popcount ( mask ) <= 3 ) return true ; if ( __builtin_popcount ( mask & ~ 0x3f ) <= 1 ) return true ; return false ; } </s>


<s> unsigned getMaxInlineSizeThreshold ( ) const { return isThumb1Only ( ) ? 0 : 64 ; } </s>

Returns the maximum memset / memcpy size that still makes it profitable to inline the call .


<s> static MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new X86MCAsmInfoDarwin ( TheTriple ) ; case Triple :: MinGW32 : case Triple :: Cygwin : case Triple :: Win32 : if ( TheTriple . getEnvironment ( ) == Triple :: MachO ) return new X86MCAsmInfoDarwin ( TheTriple ) ; else return new X86MCAsmInfoCOFF ( TheTriple ) ; default : return new X86ELFMCAsmInfo ( TheTriple ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> bool ARM64PassConfig :: addILPOpts ( ) { if ( EnableCCMP ) addPass ( createARM64ConditionalCompares ( ) ) ; if ( EnableEarlyIfConvert ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createARM64StorePairSuppressPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( & getPPCTargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> unsigned MipsSEInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . mayLoad ( ) ) { if ( ( MI . getOperand ( 1 ) . isFI ( ) ) && ( MI . getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( 2 ) ) ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static void s390_asm_trampoline_template ( FILE * file ) { rtx op [ 2 ] ; op [ 0 ] = gen_rtx_REG ( Pmode , 0 ) ; op [ 1 ] = gen_rtx_REG ( Pmode , 1 ) ; if ( TARGET_64BIT ) { output_asm_insn ( "basr\t%1,0" , op ) ; output_asm_insn ( "lmg\t%0,%1,14(%1)" , op ) ; output_asm_insn ( "br\t%1" , op ) ; ASM_OUTPUT_SKIP ( file , ( HOST_WIDE_INT ) ( TRAMPOLINE_SIZE - 10 ) ) ; } else { output_asm_insn ( "basr\t%1,0" , op ) ; output_asm_insn ( "lm\t%0,%1,6(%1)" , op ) ; output_asm_insn ( "br\t%1" , op ) ; ASM_OUTPUT_SKIP ( file , ( HOST_WIDE_INT ) ( TRAMPOLINE_SIZE - 8 ) ) ; } } </s>

Output assembly code for the trampoline template to stdio stream FILE . On S/390 , we use gpr 1 internally in the trampoline code ; gpr 0 is used to hold the static chain .


<s> static bool mips_expand_vpc_loongson_even_odd ( struct expand_vec_perm_d * d ) { unsigned i , odd , nelt = d -> nelt ; rtx t0 , t1 , t2 , t3 ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI ) ) return false ; if ( nelt < 4 ) return false ; odd = d -> perm [ 0 ] ; if ( odd > 1 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i * 2 + odd ) return false ; if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( d -> vmode ) ; t1 = gen_reg_rtx ( d -> vmode ) ; switch ( d -> vmode ) { case E_V4HImode : emit_insn ( gen_loongson_punpckhhw ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklhw ( t1 , d -> op0 , d -> op1 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhhw ( d -> target , t1 , t0 ) ) ; else emit_insn ( gen_loongson_punpcklhw ( d -> target , t1 , t0 ) ) ; break ; case E_V8QImode : t2 = gen_reg_rtx ( d -> vmode ) ; t3 = gen_reg_rtx ( d -> vmode ) ; emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t1 , d -> op0 , d -> op1 ) ) ; emit_insn ( gen_loongson_punpckhbh ( t2 , t1 , t0 ) ) ; emit_insn ( gen_loongson_punpcklbh ( t3 , t1 , t0 ) ) ; if ( odd ) emit_insn ( gen_loongson_punpckhbh ( d -> target , t3 , t2 ) ) ; else emit_insn ( gen_loongson_punpcklbh ( d -> target , t3 , t2 ) ) ; break ; default : gcc_unreachable ( ) ; } return true ; } </s>

Recognize patterns for even-odd extraction .


<s> int first_reg_to_save ( ) { int first_reg ; for ( first_reg = 6 ; first_reg <= 15 ; first_reg ++ ) if ( regs_ever_live [ first_reg ] ) break ; if ( first_reg > 14 && romp_using_r14 ( ) ) first_reg = 14 ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


"constant argument out of range for %qs"

Return true if OPVAL can be used for operand OPNUM of instruction ICODE . The instruction should require a constant operand of some sort . The function prints an error if OPVAL is not valid .


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for LDP immediate"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { unsigned PredReg = 0 ; return llvm :: getITInstrPredicate ( MBBI , PredReg ) == ARMCC :: AL ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s> static void tilegx_gen_bundles ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn , * next , * prev ; rtx_insn * end = NEXT_INSN ( BB_END ( bb ) ) ; prev = NULL ; for ( insn = next_insn_to_bundle ( BB_HEAD ( bb ) , end ) ; insn ; insn = next ) { next = next_insn_to_bundle ( NEXT_INSN ( insn ) , end ) ; if ( GET_CODE ( PATTERN ( insn ) ) != ASM_INPUT ) { if ( next == NULL_RTX || GET_MODE ( next ) == TImode || CALL_P ( insn ) ) { PUT_MODE ( insn , QImode ) ; } else { PUT_MODE ( insn , SImode ) ; } } if ( get_attr_type ( insn ) == TYPE_NOTHING ) { if ( GET_MODE ( insn ) == QImode && prev != NULL && GET_MODE ( prev ) == SImode ) { PUT_MODE ( prev , QImode ) ; } delete_insn ( insn ) ; } else prev = insn ; } } } </s>

Go through all insns , and use the information generated during scheduling to generate SEQUENCEs to represent bundles of instructions issued simultaneously .


<s> static const char * i386_find_on_wrapper_list ( const char * target ) { static char first_time = 1 ; static hash_table < wrapped_symbol_hasher > * wrappers ; if ( first_time ) { static char wrapper_list_buffer [ ] = CXX_WRAP_SPEC_LIST ; char * bufptr ; wrappers = new hash_table < wrapped_symbol_hasher > ( 8 ) ; for ( bufptr = wrapper_list_buffer ; * bufptr ; ++ bufptr ) { char * found = NULL ; if ( ISSPACE ( * bufptr ) ) continue ; if ( * bufptr == '_' ) found = bufptr ; while ( * bufptr && ! ISSPACE ( * bufptr ) ) ++ bufptr ; if ( * bufptr ) * bufptr = 0 ; if ( found ) * wrappers -> find_slot ( found , INSERT ) = found ; } first_time = 0 ; } return wrappers -> find ( target ) ; } </s>

Search for a function named TARGET in the list of library wrappers we are using , returning a pointer to it if found or NULL if not . This function might be called on quite a few symbols , and we only have the list of names of wrapped functions available to us as a spec string , so first time round we lazily initialise a hash table to make things quicker .


<s> MachineBasicBlock * MipsSETargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { switch ( MI . getOpcode ( ) ) { default : return MipsTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case Mips :: BPOSGE32_PSEUDO : return emitBPOSGE32 ( MI , BB ) ; case Mips :: SNZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_B ) ; case Mips :: SNZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_H ) ; case Mips :: SNZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_W ) ; case Mips :: SNZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_D ) ; case Mips :: SNZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_V ) ; case Mips :: SZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_B ) ; case Mips :: SZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_H ) ; case Mips :: SZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_W ) ; case Mips :: SZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_D ) ; case Mips :: SZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_V ) ; case Mips :: COPY_FW_PSEUDO : return emitCOPY_FW ( MI , BB ) ; case Mips :: COPY_FD_PSEUDO : return emitCOPY_FD ( MI , BB ) ; case Mips :: INSERT_FW_PSEUDO : return emitINSERT_FW ( MI , BB ) ; case Mips :: INSERT_FD_PSEUDO : return emitINSERT_FD ( MI , BB ) ; case Mips :: INSERT_B_VIDX_PSEUDO : case Mips :: INSERT_B_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 1 , false ) ; case Mips :: INSERT_H_VIDX_PSEUDO : case Mips :: INSERT_H_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 2 , false ) ; case Mips :: INSERT_W_VIDX_PSEUDO : case Mips :: INSERT_W_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 4 , false ) ; case Mips :: INSERT_D_VIDX_PSEUDO : case Mips :: INSERT_D_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 8 , false ) ; case Mips :: INSERT_FW_VIDX_PSEUDO : case Mips :: INSERT_FW_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 4 , true ) ; case Mips :: INSERT_FD_VIDX_PSEUDO : case Mips :: INSERT_FD_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 8 , true ) ; case Mips :: FILL_FW_PSEUDO : return emitFILL_FW ( MI , BB ) ; case Mips :: FILL_FD_PSEUDO : return emitFILL_FD ( MI , BB ) ; case Mips :: FEXP2_W_1_PSEUDO : return emitFEXP2_W_1 ( MI , BB ) ; case Mips :: FEXP2_D_1_PSEUDO : return emitFEXP2_D_1 ( MI , BB ) ; } } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static void m68k_set_frame_related ( rtx_insn * insn ) { rtx body ; int i ; RTX_FRAME_RELATED_P ( insn ) = 1 ; body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == PARALLEL ) for ( i = 0 ; i < XVECLEN ( body , 0 ) ; i ++ ) RTX_FRAME_RELATED_P ( XVECEXP ( body , 0 , i ) ) = 1 ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"SPARC Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned CSKYInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 0 ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return 1 ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 1 ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; return 2 ; } </s>

Remove the branching code at the end of the specific MBB .


<s> static bool ix86_check_avx_upper_register ( const_rtx exp ) { return ( SSE_REG_P ( exp ) && ! EXT_REX_SSE_REG_P ( exp ) && GET_MODE_BITSIZE ( GET_MODE ( exp ) ) > 128 ) ; } </s>

Check if a 256bit or 512 bit AVX register is referenced inside of EXP .


"No DAG nodes should be reachable from ExitSU"

Apply the profile inference algorithm for a given function .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createARMWinCOFFObjectWriter ( OS , false ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static unsigned int mips_build_shift ( struct mips_integer_op * codes , HOST_WIDE_INT value ) { unsigned int i , shift ; shift = 0 ; while ( ( value & 1 ) == 0 ) value /= 2 , shift ++ ; i = mips_build_integer ( codes , value ) ; codes [ i ] . code = ASHIFT ; codes [ i ] . value = shift ; return i + 1 ; } </s>

Subroutine of mips_build_integer ( with the same interface ) . Assume that the final action in the sequence should be a left shift .


<s> void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool expand_perm_with_vster ( const struct expand_vec_perm_d & d ) { if ( TARGET_VXE2 && d . op0 == d . op1 && is_reverse_perm_mask ( d ) && ( d . vmode == V2DImode || d . vmode == V2DFmode || d . vmode == V4SImode || d . vmode == V4SFmode || d . vmode == V8HImode ) ) { if ( d . testing_p ) return true ; if ( d . vmode == V2DImode ) emit_insn ( gen_eltswapv2di ( d . target , d . op0 ) ) ; else if ( d . vmode == V2DFmode ) emit_insn ( gen_eltswapv2df ( d . target , d . op0 ) ) ; else if ( d . vmode == V4SImode ) emit_insn ( gen_eltswapv4si ( d . target , d . op0 ) ) ; else if ( d . vmode == V4SFmode ) emit_insn ( gen_eltswapv4sf ( d . target , d . op0 ) ) ; else if ( d . vmode == V8HImode ) emit_insn ( gen_eltswapv8hi ( d . target , d . op0 ) ) ; return true ; } return false ; } </s>

If we just reverse the elements , emit an eltswap if we have vler/vster .


<s> void LoongArchInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( ! printAliasInstr ( MI , Address , STI , O ) ) printInstruction ( MI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
bool
function_resolver
::
check_num_arguments
(
unsigned
int
expected
)
{
if
(
m_arglist
.
length
(
)
<
expected
)
error_at
(
location
,
"too few arguments to function %qE"
,
fndecl
)
;
else
if
(
m_arglist
.
length
(
)
>
expected
)
error_at
(
location
,
"too many arguments to function %qE"
,
fndecl
)
;
return
m_arglist
.
length
(
)
==
expected
;
}
</s>

Require the function to have exactly EXPECTED arguments . Return true if it does , otherwise report an appropriate error .

aarch64
"too few arguments to function %qE"
"too many arguments to function %qE"


<s>
MCSection
*
GBZ80TargetObjectFile
::
getSectionForConstant
(
const
DataLayout
&
DL
,
SectionKind
Kind
,
const
Constant
*
C
,
unsigned
&
Align
)
const
{
assert
(
Kind
.
isReadOnly
(
)
&&
"Writeable constant?"
)
;
return
getSection
(
Kind
,
StringRef
(
)
,
ST_ROM0
,
0
,
~
0U
,
Align
,
nullptr
)
;
}
</s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> bool isFPImm ( ) const { return Kind == k_FPImmediate ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> void WebAssemblyTargetELFStreamer :: emitLocal ( ArrayRef < MVT > Types ) { Streamer . EmitULEB128IntValue ( Types . size ( ) ) ; for ( MVT Type : Types ) Streamer . EmitIntValue ( int64_t ( WebAssembly :: toValType ( Type ) ) , 1 ) ; } </s>

WebAssembly WebAssembly WebAssembly::toValType 1


<s> bool n7_consumed_by_ii_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : if ( movd44_even_dep_p ( consumer , def_reg ) ) return true ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( INSN_CODE ( consumer ) == CODE_FOR_divmodsi4 || INSN_CODE ( consumer ) == CODE_FOR_udivmodsi4 ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_LOAD : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_STORE : if ( post_update_insn_p ( consumer ) ) use_rtx = extract_base_reg ( consumer ) ; else use_rtx = extract_mem_rtx ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_LOAD_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at II .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


<s> void X86FlagsCopyLoweringPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86TargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { bool ShouldPrint = false ; if ( OptLevel != CodeGenOpt :: None && ( Subtarget . hasSSE2 ( ) || Subtarget . hasAVX ( ) ) ) { PM . add ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( Subtarget . hasAVX ( ) && UseVZeroUpper ) { PM . add ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static hashval_t hash ( const char * str ) { return htab_hash_string ( str ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> static void print_shift_count_operand ( FILE * file , rtx op ) { if ( ! s390_valid_shift_count ( op , 0 ) ) gcc_unreachable ( ) ; while ( op && GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( GET_CODE ( op ) == AND ) op = XEXP ( op , 0 ) ; print_addrstyle_operand ( file , op ) ; } </s>

Output operand OP to stdio stream FILE . OP is an address ( register + offset ) which is not used to address data ; instead the rightmost bits are interpreted as the value .


<s> static bool aarch64_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size ; machine_mode ag_mode ; int count ; if ( ! AGGREGATE_TYPE_P ( type ) && TREE_CODE ( type ) != COMPLEX_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) return false ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( type ) , type , & ag_mode , & count , NULL ) ) return false ; size = int_size_in_bytes ( type ) ; return ( size < 0 || size > 2 * UNITS_PER_WORD ) ; } </s>

Implement TARGET_RETURN_IN_MEMORY . If the type T of the result of a function is such that void func ( T arg ) would require that arg be passed as a value in a register ( or set of registers ) according to the parameter passing rules , then the result is returned in the same registers as would be used for such an argument .


<s> void aarch64_d_register_target_info ( void ) { const struct d_target_info_spec handlers [ ] = { { "floatAbi" , aarch64_d_handle_target_float_abi } , { NULL , NULL } , } ; d_add_target_info_handlers ( handlers ) ; } </s>


<s> static void rs6000_eliminate_indexed_memrefs ( rtx operands [ 2 ] ) { if ( MEM_P ( operands [ 0 ] ) && ! REG_P ( XEXP ( operands [ 0 ] , 0 ) ) && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 0 ] , 0 ) , GET_MODE ( operands [ 0 ] ) , false ) ) operands [ 0 ] = replace_equiv_address ( operands [ 0 ] , copy_addr_to_reg ( XEXP ( operands [ 0 ] , 0 ) ) ) ; if ( MEM_P ( operands [ 1 ] ) && ! REG_P ( XEXP ( operands [ 1 ] , 0 ) ) && ! legitimate_constant_pool_address_p ( XEXP ( operands [ 1 ] , 0 ) , GET_MODE ( operands [ 1 ] ) , false ) ) operands [ 1 ] = replace_equiv_address ( operands [ 1 ] , copy_addr_to_reg ( XEXP ( operands [ 1 ] , 0 ) ) ) ; } </s>

Helper for the following . Get rid of [ r+r ] memory refs in cases where it wo n't work ( TImode , TFmode ) .


<s> bool WebAssembly :: mayThrow ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: THROW : case WebAssembly :: THROW_S : case WebAssembly :: RETHROW : case WebAssembly :: RETHROW_S : return true ; } if ( isCallIndirect ( MI . getOpcode ( ) ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = MI . getOperand ( getCalleeOpNo ( MI . getOpcode ( ) ) ) ; assert ( MO . isGlobal ( ) ) ; const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) return true ; if ( F -> doesNotThrow ( ) ) return false ; if ( F -> getName ( ) == CxaBeginCatchFn || F -> getName ( ) == PersonalityWrapperFn || F -> getName ( ) == ClangCallTerminateFn || F -> getName ( ) == StdTerminateFn ) return false ; return true ; } </s>

Return true if this instruction may throw an exception .

WebAssembly WebAssembly::mayThrow WebAssembly::THROW WebAssembly::THROW_S WebAssembly::RETHROW WebAssembly::RETHROW_S


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


Return an RTX representing the place where a function returns or receives a value of data type RET_TYPE .


<s> bool ix86_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ) ; return false ; } </s>

Return true if MODE1 is accessible in a register that can hold MODE2 without copying . That is , all register classes that can hold MODE2 can also hold MODE1 .


<s> static bool loongarch_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM ) ; } </s>

Implement TARGET_CAN_ELIMINATE . Make sure that we 're not trying to eliminate to the wrong hard frame pointer .


"No MachineFunctionInfo for this function!"

runOnMachineFunction - Emit the function body .


<s> ARMProcFamilyEnum getProcFamily ( ) const { return ARMProcFamily ; } </s>


<s> static machine_mode promote_return ( machine_mode mode ) { return promote_arg ( mode , true ) ; } </s>

A non-memory return type of MODE is being returned . Determine the mode it should be promoted to .


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override { return TargetLowering :: shouldFormOverflowOp ( Opcode , VT , true ) ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


<s> static int s390_sched_score ( rtx_insn * insn ) { unsigned int mask = s390_get_sched_attrmask ( insn ) ; int score = 0 ; switch ( s390_sched_state ) { case 0 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) != 0 || ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) != 0 ) score += 5 ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) != 0 ) score += 10 ; case 1 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == 0 ) score += 10 ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) == 0 ) score += 5 ; break ; case 2 : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) == 0 ) score += 10 ; if ( ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) != 0 ) score += 10 ; break ; case S390_SCHED_STATE_NORMAL : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) == 0 && ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) == 0 ) score += 5 ; if ( ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) != 0 ) score += 10 ; break ; case S390_SCHED_STATE_CRACKED : if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) != 0 || ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) != 0 ) score += 5 ; break ; } if ( s390_tune >= PROCESSOR_2964_Z13 ) { int units , i ; unsigned unit_mask , m = 1 ; unit_mask = s390_get_unit_mask ( insn , & units ) ; gcc_assert ( units <= MAX_SCHED_UNITS ) ; for ( i = 0 ; i < units ; i ++ , m <<= 1 ) if ( m & unit_mask ) score += ( last_scheduled_unit_distance [ i ] * MAX_SCHED_MIX_SCORE / MAX_SCHED_MIX_DISTANCE ) ; } return score ; } </s>

Return the scheduling score for INSN . The higher the score the better . The score is calculated from the OOO scheduling attributes of INSN and the scheduling state s390_sched_state .


<s> static reg_class_t mips_canonicalize_move_class ( reg_class_t rclass ) { if ( reg_class_subset_p ( rclass , ACC_REGS ) ) rclass = ACC_REGS ; if ( TARGET_MIPS16 && reg_class_subset_p ( rclass , M16_REGS ) ) rclass = M16_REGS ; else if ( reg_class_subset_p ( rclass , GENERAL_REGS ) ) rclass = GENERAL_REGS ; return rclass ; } </s>

RCLASS is a class involved in a REGISTER_MOVE_COST calculation . Return a `` canonical '' class to represent it in later calculations .


<s> static void build_one ( function_builder & b , const function_group_info & group , unsigned int pred_idx , unsigned int vec_type_idx ) { auto_vec < tree , 21 > argument_types ; function_instance function_instance ( group . base_name , * group . base , * group . shape , group . ops_infos . types [ vec_type_idx ] , group . preds [ pred_idx ] , & group . ops_infos ) ; tree return_type = group . ops_infos . ret . get_tree_type ( group . ops_infos . types [ vec_type_idx ] . index ) ; b . allocate_argument_types ( function_instance , argument_types ) ; b . apply_predication ( function_instance , return_type , argument_types ) ; b . add_unique_function ( function_instance , ( * group . shape ) , return_type , argument_types ) ; } </s>

Add one function instance for GROUP , using operand suffix at index OI , mode suffix at index PAIR & & bi and predication suffix at index pred_idx .


<s> void AArch64TargetStreamer :: emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( char & C : Buffer ) { C = uint8_t ( Inst ) ; Inst >>= 8 ; } getStreamer ( ) . emitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s>
auto
AlignVectors
::
move
(
const
MoveGroup
&
Move
)
const
->
bool
{
assert
(
!
Move
.
Main
.
empty
(
)
&&
"Move group should have non-empty Main"
)
;
Instruction
*
Where
=
Move
.
Main
.
front
(
)
;
if
(
Move
.
IsLoad
)
{
for
(
Instruction
*
D
:
Move
.
Deps
)
D
->
moveBefore
(
Where
)
;
ArrayRef
<
Instruction
*
>
Main
(
Move
.
Main
)
;
for
(
Instruction
*
M
:
Main
.
drop_front
(
1
)
)
{
M
->
moveAfter
(
Where
)
;
Where
=
M
;
}
}
else
{
assert
(
Move
.
Deps
.
empty
(
)
)
;
ArrayRef
<
Instruction
*
>
Main
(
Move
.
Main
)
;
for
(
Instruction
*
M
:
Main
.
drop_front
(
1
)
)
{
M
->
moveBefore
(
Where
)
;
Where
=
M
;
}
}
return
Move
.
Main
.
size
(
)
+
Move
.
Deps
.
size
(
)
>
1
;
}
</s>

Move in the provide values in ValuesToLink from Src .


<s> bool SystemZTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isUInt < 32 > ( Imm ) || isUInt < 32 > ( - Imm ) ; } </s>

Return true if the specified immediate is legal add immediate , that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register .


<s> void AArch64AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( OutStreamer , MI ) ) return ; if ( AArch64FI -> getLOHRelated ( ) . count ( MI ) ) { MCSymbol * LOHLabel = GetTempSymbol ( "loh" , LOHLabelCounter ++ ) ; LOHInstToLabel [ MI ] = LOHLabel ; OutStreamer . EmitLabel ( LOHLabel ) ; } switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: DBG_VALUE : { if ( isVerbose ( ) && OutStreamer . hasRawTextSupport ( ) ) { SmallString < 128 > TmpStr ; raw_svector_ostream OS ( TmpStr ) ; PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; } case AArch64 :: TCRETURNri : { MCInst TmpInst ; TmpInst . setOpcode ( AArch64 :: BR ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case AArch64 :: TCRETURNdi : { MCOperand Dest ; MCInstLowering . lowerOperand ( MI -> getOperand ( 0 ) , Dest ) ; MCInst TmpInst ; TmpInst . setOpcode ( AArch64 :: B ) ; TmpInst . addOperand ( Dest ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case AArch64 :: TLSDESC_BLR : { MCOperand Callee , Sym ; MCInstLowering . lowerOperand ( MI -> getOperand ( 0 ) , Callee ) ; MCInstLowering . lowerOperand ( MI -> getOperand ( 1 ) , Sym ) ; MCInst TLSDescCall ; TLSDescCall . setOpcode ( AArch64 :: TLSDESCCALL ) ; TLSDescCall . addOperand ( Sym ) ; EmitToStreamer ( OutStreamer , TLSDescCall ) ; MCInst BLR ; BLR . setOpcode ( AArch64 :: BLR ) ; BLR . addOperand ( Callee ) ; EmitToStreamer ( OutStreamer , BLR ) ; return ; } case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( OutStreamer , SM , * MI ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( OutStreamer , SM , * MI ) ; } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static bool h8300_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { return ( TYPE_MODE ( type ) == BLKmode || GET_MODE_SIZE ( TYPE_MODE ( type ) ) > ( TARGET_H8300 ? 4 : 8 ) ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s>
void
cris_print_operand_address
(
FILE
*
file
,
rtx
x
)
{
putc
(
'['
,
file
)
;
if
(
CONSTANT_ADDRESS_P
(
x
)
)
cris_output_addr_const
(
file
,
x
)
;
else
if
(
BASE_OR_AUTOINCR_P
(
x
)
)
cris_print_base
(
x
,
file
)
;
else
if
(
GET_CODE
(
x
)
==
PLUS
)
{
rtx
x1
,
x2
;
x1
=
XEXP
(
x
,
0
)
;
x2
=
XEXP
(
x
,
1
)
;
if
(
BASE_P
(
x1
)
)
{
cris_print_base
(
x1
,
file
)
;
cris_print_index
(
x2
,
file
)
;
}
else
if
(
BASE_P
(
x2
)
)
{
cris_print_base
(
x2
,
file
)
;
cris_print_index
(
x1
,
file
)
;
}
else
LOSE_AND_RETURN
(
"unrecognized address"
,
x
)
;
}
else
if
(
GET_CODE
(
x
)
==
MEM
)
{
putc
(
'['
,
file
)
;
cris_print_base
(
XEXP
(
x
,
0
)
,
file
)
;
putc
(
']'
,
file
)
;
}
else
LOSE_AND_RETURN
(
"unrecognized address"
,
x
)
;
putc
(
']'
,
file
)
;
}
</s>


"passing %wd to argument %d of %qE, which expects"

Report that LOCATION has a call to FNDECL in which argument ARGNO has the value ACTUAL , whereas the function requires a value in the range [ MIN , MAX ] . ARGNO counts from zero .


<s> int first_fp_reg_to_save ( void ) { int first_reg ; for ( first_reg = 14 + 32 ; first_reg <= 63 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; return first_reg ; } </s>


<s> static unsigned rs6000_hash_constant ( rtx k ) { enum rtx_code code = GET_CODE ( k ) ; machine_mode mode = GET_MODE ( k ) ; unsigned result = ( code << 3 ) ^ mode ; const char * format ; int flen , fidx ; format = GET_RTX_FORMAT ( code ) ; flen = strlen ( format ) ; fidx = 0 ; switch ( code ) { case LABEL_REF : return result * 1231 + ( unsigned ) INSN_UID ( XEXP ( k , 0 ) ) ; case CONST_WIDE_INT : { int i ; flen = CONST_WIDE_INT_NUNITS ( k ) ; for ( i = 0 ; i < flen ; i ++ ) result = result * 613 + CONST_WIDE_INT_ELT ( k , i ) ; return result ; } case CONST_DOUBLE : return real_hash ( CONST_DOUBLE_REAL_VALUE ( k ) ) * result ; case CODE_LABEL : fidx = 3 ; break ; default : break ; } for ( ; fidx < flen ; fidx ++ ) switch ( format [ fidx ] ) { case 's' : { unsigned i , len ; const char * str = XSTR ( k , fidx ) ; len = strlen ( str ) ; result = result * 613 + len ; for ( i = 0 ; i < len ; i ++ ) result = result * 613 + ( unsigned ) str [ i ] ; break ; } case 'u' : case 'e' : result = result * 1231 + rs6000_hash_constant ( XEXP ( k , fidx ) ) ; break ; case 'i' : case 'n' : result = result * 613 + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * 613 + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = 0 ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * 613 + ( unsigned ) ( XWINT ( k , fidx ) >> CHAR_BIT * i ) ; } break ; case '0' : break ; default : gcc_unreachable ( ) ; } return result ; } </s>


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; TM = & TPC -> getTM < PPCTargetMachine > ( ) ; STI = TM -> getSubtargetImpl ( F ) ; TLI = STI -> getTargetLowering ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool RISCVTTIImpl :: isLoweredToCall ( const Function * F ) { if ( F -> getName ( ) . startswith ( "llvm.riscv.cv" ) ) return false ; return BaseT :: isLoweredToCall ( F ) ; } </s>

Test whether calls to a function lower to actual program function calls .


<s> static void tilegx_conditional_register_usage ( void ) { global_regs [ TILEGX_NETORDER_REGNUM ] = 1 ; if ( TILEGX_PIC_TEXT_LABEL_REGNUM != INVALID_REGNUM ) { fixed_regs [ TILEGX_PIC_TEXT_LABEL_REGNUM ] = 1 ; call_used_regs [ TILEGX_PIC_TEXT_LABEL_REGNUM ] = 1 ; } if ( PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; } } </s>


<s> bool ix86_rip_relative_addr_p ( struct ix86_address * parts ) { rtx base , index , disp ; base = parts -> base ; index = parts -> index ; disp = parts -> disp ; if ( disp && ! base && ! index ) { if ( TARGET_64BIT ) { rtx symbol = disp ; if ( GET_CODE ( disp ) == CONST ) symbol = XEXP ( disp , 0 ) ; if ( GET_CODE ( symbol ) == PLUS && CONST_INT_P ( XEXP ( symbol , 1 ) ) ) symbol = XEXP ( symbol , 0 ) ; if ( GET_CODE ( symbol ) == LABEL_REF || ( GET_CODE ( symbol ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( symbol ) == 0 ) || ( GET_CODE ( symbol ) == UNSPEC && ( XINT ( symbol , 1 ) == UNSPEC_GOTPCREL || XINT ( symbol , 1 ) == UNSPEC_PCREL || XINT ( symbol , 1 ) == UNSPEC_GOTNTPOFF ) ) ) return true ; } } return false ; } </s>

Check whether x86 address PARTS is a pc-relative address .


<s>
void
SystemZFrameInfo
::
emitPrologue
(
MachineFunction
&
MF
)
const
{
MachineBasicBlock
&
MBB
=
MF
.
front
(
)
;
const
TargetFrameInfo
&
TFI
=
*
MF
.
getTarget
(
)
.
getFrameInfo
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
SystemZInstrInfo
&
TII
=
*
static_cast
<
const
SystemZInstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
SystemZMachineFunctionInfo
*
SystemZMFI
=
MF
.
getInfo
<
SystemZMachineFunctionInfo
>
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
MFI
->
getStackSize
(
)
;
StackSize
-=
SystemZMFI
->
getCalleeSavedFrameSize
(
)
;
uint64_t
NumBytes
=
StackSize
TFI
.
getOffsetOfLocalArea
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mr
||
MBBI
->
getOpcode
(
)
==
SystemZ
::
MOV64mrm
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
StackSize
||
MFI
->
hasCalls
(
)
)
{
assert
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
SystemZ
::
R15D
)
&&
"Invalid stack frame calculation!"
)
;
emitSPUpdate
(
MBB
,
MBBI
,
(
int64_t
)
NumBytes
,
TII
)
;
}
if
(
hasFP
(
MF
)
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
SystemZ
::
MOV64rr
)
,
SystemZ
::
R11D
)
.
addReg
(
SystemZ
::
R15D
)
;
for
(
MachineFunction
::
iterator
I
=
llvm
::
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
SystemZ
::
R11D
)
;
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static bool rs6000_function_ok_for_sibcall ( tree decl , tree exp ) { tree fntype ; if ( CALL_EXPR_STATIC_CHAIN ( exp ) ) return false ; if ( decl ) fntype = TREE_TYPE ( decl ) ; else fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE && ! ( decl && decl == current_function_decl ) ) { function_args_iterator args_iter ; tree type ; int nvreg = 0 ; FOREACH_FUNCTION_ARGS ( fntype , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg ++ ; FOREACH_FUNCTION_ARGS ( TREE_TYPE ( current_function_decl ) , type , args_iter ) if ( TREE_CODE ( type ) == VECTOR_TYPE && ALTIVEC_OR_VSX_VECTOR_MODE ( TYPE_MODE ( type ) ) ) nvreg -- ; if ( nvreg > 0 ) return false ; } if ( DEFAULT_ABI == ABI_DARWIN || ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && decl && ! DECL_EXTERNAL ( decl ) && ! DECL_WEAK ( decl ) && ( * targetm . binds_local_p ) ( decl ) ) || ( DEFAULT_ABI == ABI_V4 && ( ! TARGET_SECURE_PLT || ! flag_pic || ( decl && ( * targetm . binds_local_p ) ( decl ) ) ) ) ) { tree attr_list = TYPE_ATTRIBUTES ( fntype ) ; if ( ! lookup_attribute ( "longcall" , attr_list ) || lookup_attribute ( "shortcall" , attr_list ) ) return true ; } return false ; } </s>

Say whether a function is a candidate for sibcall handling or not . We do not allow indirect calls to be optimized into sibling calls . Also , we ca n't do it if there are any vector parameters ; there 's nowhere to put the VRsave code so it works ; note that functions with vector parameters are required to have a prototype , so the argument type info must be available here . ( The tail recursion case can work with vector parameters , but there 's no way to distinguish here . )


<s> tree resolve ( function_resolver & r ) const OVERRIDE { unsigned int i , nargs ; type_suffix_index type ; if ( ! r . check_gp_argument ( 1 , i , nargs ) || ( type = r . infer_vector_type ( i ) ) == NUM_TYPE_SUFFIXES ) return error_mark_node ; if ( type == TYPE_SUFFIX_b ) return r . resolve_to ( r . mode_suffix_id , type ) ; if ( type_suffixes [ type ] . integer_p && type_suffixes [ type ] . element_bits < 64 ) { type_suffix_index wide_suffix = find_type_suffix ( type_suffixes [ type ] . tclass , type_suffixes [ type ] . element_bits * 2 ) ; if ( tree res = r . lookup_form ( r . mode_suffix_id , wide_suffix ) ) return res ; } return r . report_no_such_form ( type ) ; } </s>

If the call is erroneous , report an appropriate error and return error_mark_node . Otherwise , if the function is overloaded , return the decl of the non-overloaded function . Return NULL_TREE otherwise , indicating that the call should be processed in the normal way .


<s> bool X86TTI :: isLegalMaskedLoad ( Type * DataTy , int Consecutive ) const { int DataWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( ( DataWidth < 32 ) || ( Consecutive == 0 ) ) return false ; if ( ST -> hasAVX512 ( ) || ST -> hasAVX2 ( ) ) return true ; return false ; } </s>

Return true if the target supports masked load .


<s>
bool
AArch64AsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
size_t
CondCodePos
=
Name
.
find
(
'.'
)
;
StringRef
Mnemonic
=
Name
.
substr
(
0
,
CondCodePos
)
;
Operands
.
push_back
(
AArch64Operand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
CondCodePos
!=
StringRef
::
npos
)
{
SMLoc
S
=
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
+
CondCodePos
+
1
)
;
StringRef
CondStr
=
Name
.
substr
(
CondCodePos
+
1
,
StringRef
::
npos
)
;
A64CC
::
CondCodes
Code
;
Code
=
A64StringToCondCode
(
CondStr
)
;
if
(
Code
==
A64CC
::
Invalid
)
{
Error
(
S
,
"invalid condition code"
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
SMLoc
DotL
=
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
+
CondCodePos
)
;
Operands
.
push_back
(
AArch64Operand
::
CreateToken
(
"."
,
DotL
)
)
;
SMLoc
E
=
SMLoc
::
getFromPointer
(
NameLoc
.
getPointer
(
)
+
CondCodePos
+
3
)
;
Operands
.
push_back
(
AArch64Operand
::
CreateCondCode
(
Code
,
S
,
E
)
)
;
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Mnemonic
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Mnemonic
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
if
(
Parser
.
getTok
(
)
.
is
(
AsmToken
::
RBrac
)
)
{
SMLoc
Loc
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
Operands
.
push_back
(
AArch64Operand
::
CreateToken
(
"]"
,
Loc
)
)
;
Parser
.
Lex
(
)
;
}
if
(
Parser
.
getTok
(
)
.
is
(
AsmToken
::
Exclaim
)
)
{
SMLoc
Loc
=
Parser
.
getTok
(
)
.
getLoc
(
)
;
Operands
.
push_back
(
AArch64Operand
::
CreateToken
(
"!"
,
Loc
)
)
;
Parser
.
Lex
(
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"expected comma before next operand"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .


<s> bool SystemZFrameLowering :: hasFP ( const MachineFunction & MF ) const { return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MF . getInfo < SystemZMachineFunctionInfo > ( ) -> getManipulatesSP ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool hasFPU ( ) const { return HasFPU ; } </s>


<s>
static
rtx
frv_int_to_acc
(
enum
insn_code
icode
,
int
opnum
,
rtx
opval
)
{
rtx
reg
;
int
i
;
for
(
i
=
0
;
i
<=
ACC_MASK
;
i
++
)
if
(
(
i
&
ACC_MASK
)
==
i
)
global_regs
[
i
+
ACC_FIRST
]
=
global_regs
[
i
+
ACCG_FIRST
]
=
1
;
if
(
GET_CODE
(
opval
)
!=
CONST_INT
)
{
error
(
"accumulator is not a constant integer"
)
;
return
NULL_RTX
;
}
if
(
(
INTVAL
(
opval
)
&
~
ACC_MASK
)
!=
0
)
{
error
(
"accumulator number is out of bounds"
)
;
return
NULL_RTX
;
}
reg
=
gen_rtx_REG
(
insn_data
[
icode
]
.
operand
[
opnum
]
.
mode
,
ACC_FIRST
+
INTVAL
(
opval
)
)
;
if
(
!
(
*
insn_data
[
icode
]
.
operand
[
opnum
]
.
predicate
)
(
reg
,
VOIDmode
)
)
SET_REGNO
(
reg
,
ACCG_FIRST
+
INTVAL
(
opval
)
)
;
if
(
!
(
*
insn_data
[
icode
]
.
operand
[
opnum
]
.
predicate
)
(
reg
,
VOIDmode
)
)
{
error
(
"inappropriate accumulator for %qs"
,
insn_data
[
icode
]
.
name
)
;
return
NULL_RTX
;
}
return
reg
;
}
</s>

Convert an integer constant to an accumulator register . ICODE is the code of the target instruction , OPNUM is the number of the accumulator operand and OPVAL is the constant integer . Try both ACC and ACCG registers ; only report an error if neither fit the instruction .


<s> HOST_WIDE_INT s390_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; int index ; if ( ! s390_can_eliminate ( from , to ) ) return 0 ; switch ( from ) { case FRAME_POINTER_REGNUM : offset = ( get_frame_size ( ) + STACK_POINTER_OFFSET + current_function_outgoing_args_size ) ; break ; case ARG_POINTER_REGNUM : s390_init_frame_layout ( ) ; offset = cfun_frame_layout . frame_size + STACK_POINTER_OFFSET ; break ; case RETURN_ADDRESS_POINTER_REGNUM : s390_init_frame_layout ( ) ; index = RETURN_REGNUM - cfun_frame_layout . first_save_gpr_slot ; gcc_assert ( index >= 0 ) ; offset = cfun_frame_layout . frame_size + cfun_frame_layout . gprs_offset ; offset += index * UNITS_PER_WORD ; break ; case BASE_REGNUM : offset = 0 ; break ; default : gcc_unreachable ( ) ; } return offset ; } </s>

Return offset between register FROM and TO initially after prolog .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) , nullptr ) ) ; SecurityCheckCookie -> setCallingConv ( CallingConv :: X86_FastCall ) ; SecurityCheckCookie -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; return ; } if ( Subtarget . isTargetGlibc ( ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> static machine_mode rs6000_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree , int ) { PROMOTE_MODE ( mode , * punsignedp , type ) ; return mode ; } </s>

On rs6000 , function arguments are promoted , as are function return values .


<s> static void ft32_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * pretend_size , int no_rtl ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int named_size = GET_MODE_SIZE ( SImode ) * ( * cum - FT32_R0 ) + GET_MODE_SIZE ( arg . mode ) ; if ( named_size < 24 ) * pretend_size = 24 - named_size ; else * pretend_size = 0 ; } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> unsigned PPCRegisterInfo :: getRARegister ( ) const { return ! Subtarget . isPPC64 ( ) ? PPC :: LR : PPC :: LR8 ; } </s>

This method should return the register where the return address can be found .


<s>
bool
AMDGPUCallLowering
::
lowerReturn
(
MachineIRBuilder
&
B
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
FunctionLoweringInfo
&
FLI
)
const
{
MachineFunction
&
MF
=
B
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MFI
->
setIfReturnsVoid
(
!
Val
)
;
assert
(
!
Val
==
VRegs
.
empty
(
)
&&
"Return value without a vreg"
)
;
CallingConv
::
ID
CC
=
B
.
getMF
(
)
.
getFunction
(
)
.
getCallingConv
(
)
;
const
bool
IsShader
=
AMDGPU
::
isShader
(
CC
)
;
const
bool
IsWaveEnd
=
(
IsShader
&&
MFI
->
returnsVoid
(
)
)
||
AMDGPU
::
isKernel
(
CC
)
;
if
(
IsWaveEnd
)
{
B
.
buildInstr
(
AMDGPU
::
S_ENDPGM
)
.
addImm
(
0
)
;
return
true
;
}
auto
const
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
unsigned
ReturnOpc
=
IsShader
AMDGPU
::
SI_RETURN_TO_EPILOG
:
AMDGPU
::
S_SETPC_B64_return
;
auto
Ret
=
B
.
buildInstrNoInsert
(
ReturnOpc
)
;
Register
ReturnAddrVReg
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
ReturnAddrVReg
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
CCR_SGPR_64RegClass
)
;
Ret
.
addUse
(
ReturnAddrVReg
)
;
}
if
(
!
lowerReturnVal
(
B
,
Val
,
VRegs
,
Ret
)
)
return
false
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
Register
LiveInReturn
=
MF
.
addLiveIn
(
TRI
->
getReturnAddressReg
(
MF
)
,
&
AMDGPU
::
SGPR_64RegClass
)
;
B
.
buildCopy
(
ReturnAddrVReg
,
LiveInReturn
)
;
}
B
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static rtx alpha_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int basereg ; int num_args ; if ( arg . aggregate_type_p ( ) ) basereg = 16 ; else { gcc_checking_assert ( ! COMPLEX_MODE_P ( arg . mode ) ) ; if ( TARGET_FPREGS && GET_MODE_CLASS ( arg . mode ) == MODE_FLOAT ) basereg = 32 + 16 ; else basereg = 16 ; } { if ( arg . end_marker_p ( ) ) return alpha_arg_info_reg_val ( * cum ) ; num_args = cum -> num_args ; if ( num_args >= 6 || targetm . calls . must_pass_in_stack ( arg ) ) return NULL_RTX ; } { if ( * cum >= 6 ) return NULL_RTX ; num_args = * cum ; if ( arg . end_marker_p ( ) ) basereg = 16 ; else if ( targetm . calls . must_pass_in_stack ( arg ) ) return NULL_RTX ; } return gen_rtx_REG ( arg . mode , num_args + basereg ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On Alpha the first 6 words of args are normally in registers and the rest are pushed .


<s> static int rs6000_hard_regno_nregs_internal ( int regno , machine_mode mode ) { unsigned HOST_WIDE_INT reg_size ; if ( FP_REGNO_P ( regno ) ) reg_size = ( ( VECTOR_MEM_VSX_P ( mode ) && mode != TDmode && mode != TFmode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ; else if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) reg_size = UNITS_PER_SPE_WORD ; else if ( ALTIVEC_REGNO_P ( regno ) ) reg_size = UNITS_PER_ALTIVEC_WORD ; else if ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SCmode && ! DECIMAL_FLOAT_MODE_P ( mode ) && SPE_SIMD_REGNO_P ( regno ) ) reg_size = UNITS_PER_FP_WORD ; else reg_size = UNITS_PER_WORD ; return ( GET_MODE_SIZE ( mode ) + reg_size - 1 ) / reg_size ; } </s>

Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . POWER and PowerPC GPRs hold 32 bits worth ; PowerPC64 GPRs and FPRs point register holds 64 bits worth .


<s> const MOSRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static rtx sparc_function_arg_1 ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named , bool incoming_p ) { const CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regbase = ( incoming_p ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno , regno , padding ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; slotno = function_arg_slotno ( cum , mode , type , named , incoming_p , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 16 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST + 2 * slotno ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH32 ) return gen_rtx_REG ( mode , regno ) ; if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) { if ( ( regno - SPARC_FP_ARG_FIRST ) >= SPARC_INT_ARG_MAX * 2 ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ) ) ; else return reg ; } else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming_p ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else if ( type && AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } return gen_rtx_REG ( mode , regno ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is false for TARGET_FUNCTION_ARG , true for TARGET_FUNCTION_INCOMING_ARG .


<s>
bool
AArch64CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
AArch64
::
RET_ReallyLR
)
;
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
bool
Success
=
true
;
if
(
VReg
)
{
const
AArch64TargetLowering
&
TLI
=
*
getTLI
<
AArch64TargetLowering
>
(
)
;
CCAssignFn
*
AssignFn
=
TLI
.
CCAssignFnForReturn
(
F
.
getCallingConv
(
)
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
F
.
getParent
(
)
->
getDataLayout
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeSet
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
[
&
]
(
ArrayRef
<
unsigned
>
Regs
,
ArrayRef
<
uint64_t
>
Offsets
)
{
MIRBuilder
.
buildExtract
(
Regs
,
Offsets
,
VReg
)
;
}
)
;
OutgoingArgHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
AssignFn
,
AssignFn
)
;
Success
=
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
Success
;
}
</s>


Return an array that contains the bitmask target flag values and their names .


<s> static rtx aarch64_simd_dup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_vec_duplicate ( mode , x ) ; } </s>

If VALS is a vector constant that can be loaded into a register using DUP , generate instructions to do so and return an RTX to assign to the register . Otherwise return NULL_RTX .


<s> void NVPTXInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool riscv_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { enum riscv_symbol_type type ; rtx base , offset ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) if ( GET_CODE ( * iter ) == CONST_POLY_INT ) return true ; if ( GET_CODE ( x ) == HIGH ) return true ; split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > 0 ) return true ; if ( flag_pic ) return true ; } if ( tls_referenced_p ( x ) ) return true ; return false ; } </s>


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s> static enum tls_model tls_symbolic_operand_type ( rtx symbol ) { enum tls_model model ; if ( GET_CODE ( symbol ) != SYMBOL_REF ) return 0 ; model = SYMBOL_REF_TLS_MODEL ( symbol ) ; if ( model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64 ) model = TLS_MODEL_INITIAL_EXEC ; return model ; } </s>

Return the TLS model to use for SYMBOL .


<s> MachinePointerInfo MipsFunctionInfo :: callPtrInfo ( StringRef Name ) { const MipsCallEntry * & E = ExternalCallEntries [ Name ] ; if ( ! E ) E = new MipsCallEntry ( Name ) ; return MachinePointerInfo ( E ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s> DiagnosticInfoUnsupported ( const Function & Fn , const Twine & Desc , DiagnosticSeverity Severity = DS_Error ) : DiagnosticInfo ( getKindID ( ) , Severity ) , Description ( Desc ) , Fn ( Fn ) { } </s>

Fn is the function where the diagnostic is being emitted .


<s> static rtx ia64_gen_spec_load ( rtx insn , ds_t ts , int mode_no ) { rtx pat , new_pat ; gen_func_t gen_load ; gen_load = get_spec_load_gen_function ( ts , mode_no ) ; new_pat = gen_load ( copy_rtx ( recog_data . operand [ 0 ] ) , copy_rtx ( recog_data . operand [ 1 ] ) ) ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) new_pat = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( COND_EXEC_TEST ( pat ) ) , new_pat ) ; return new_pat ; } </s>

If GEN_P is true , calculate the index of needed speculation check and return speculative pattern for INSN with speculative mode TS , machine mode MODE_NO and with ZERO_EXTEND ( if EXTEND_P is true ) . If GEN_P is false , just calculate the index of needed speculation check .


<s> bool runOnModule ( Module & M ) override { DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; if ( skipModule ( M ) ) return false ; bool Changed = false ; PromotionCacheTy PromotionCache ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF , PromotionCache ) ; } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> DiagnosticInfoUnsupported ( SDLoc DLoc , const Function & Fn , const Twine & Desc , SDValue Value ) : DiagnosticInfo ( getKindID ( ) , DS_Error ) , DLoc ( DLoc . getDebugLoc ( ) ) , Description ( Desc ) , Fn ( Fn ) , Value ( Value ) { } </s>


<s> void KudeyarInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( Kudeyar :: MOV_MR32 ) ) . addFrameIndex ( FrameIdx ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> const X86Subtarget & X86MCInstLower :: getSubtarget ( ) const { return AsmPrinter . getSubtarget ( ) ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> bool arm_vector_mode_supported_p ( enum machine_mode mode ) { if ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , IsPPC64 ( is64Bit ) , TargetTriple ( TT ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> const ARMGNULDBackend & getTarget ( ) const { return m_Target ; } </s>

getTarget - Return the target machine this machine code is compiled with


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG , unsigned EncodingAlignment ) const { int16_t imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , imm ) && ( ! EncodingAlignment || ! ( imm % EncodingAlignment ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( 0 ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( 1 ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> bool PPCRegisterInfo :: isCallerPreservedPhysReg ( MCRegister PhysReg , const MachineFunction & MF ) const { assert ( Register :: isPhysicalRegister ( PhysReg ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! Subtarget . is64BitELFABI ( ) && ! Subtarget . isAIXABI ( ) ) return false ; if ( PhysReg == Subtarget . getTOCPointerRegister ( ) ) return ( getReservedRegs ( MF ) . test ( PhysReg ) ) ; if ( StackPtrConst && PhysReg == Subtarget . getStackPointerRegister ( ) && ! MFI . hasVarSizedObjects ( ) && ! MFI . hasOpaqueSPAdjustment ( ) ) return true ; return false ; } </s>

Physical registers that may be modified within a function but are guaranteed to be restored before any uses .


<s> void AnalyzeCallOperands ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , const char * Func ) { PreAnalyzeCallOperands ( Outs , FuncArgs , Func ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; OriginalArgWasF128 . clear ( ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasFloatVector . clear ( ) ; CallOperandIsFixed . clear ( ) ; } </s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .


<s> static void expand_strncmp_align_check ( rtx strncmp_label , rtx src_addr , HOST_WIDE_INT bytes ) { rtx lab_ref = gen_rtx_LABEL_REF ( VOIDmode , strncmp_label ) ; rtx src_pgoff = gen_reg_rtx ( GET_MODE ( src_addr ) ) ; do_and3 ( src_pgoff , src_addr , GEN_INT ( 0xfff ) ) ; rtx cond = gen_reg_rtx ( CCmode ) ; emit_move_insn ( cond , gen_rtx_COMPARE ( CCmode , src_pgoff , GEN_INT ( 4096 - bytes ) ) ) ; rtx cmp_rtx = gen_rtx_GE ( VOIDmode , cond , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , lab_ref , pc_rtx ) ; rtx_insn * j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; add_reg_br_prob_note ( j , profile_probability :: unlikely ( ) ) ; JUMP_LABEL ( j ) = strncmp_label ; LABEL_NUSES ( strncmp_label ) += 1 ; } </s>

Generate page crossing check and branch code to set up for strncmp when we do n't have DI alignment . STRNCMP_LABEL is the label to branch if there is a page crossing . SRC_ADDR is the string address to be examined . BYTES is the max number of bytes to compare .


<s> StringRef HexagonInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return MII . getName ( Opcode ) ; } </s>

Return a string representation for an opcode .


Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> bool LanaiAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OS . write ( "\x15\0\0\0" , 4 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


runOnMachineFunction - Emit the function body .


<s> static unsigned int aarch64_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment = aarch64_function_arg_alignment ( mode , type ) ; return MIN ( MAX ( alignment , PARM_BOUNDARY ) , STACK_BOUNDARY ) ; } </s>

Implement FUNCTION_ARG_BOUNDARY . Every parameter gets at least PARM_BOUNDARY bits of alignment , but will be given anything up to STACK_BOUNDARY bits if the type requires it . This makes sure that both before and after the layout of each argument , the Next Stacked Argument Address ( NSAA ) will have a minimum alignment of 8 bytes .


<s> bool TOYPassConfig :: addPreEmitPass ( ) { addPass ( createTOYPreEmit ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void rl78_expand_movsi ( rtx * operands ) { rtx op00 , op02 , op10 , op12 ; op00 = rl78_subreg ( HImode , operands [ 0 ] , SImode , 0 ) ; op02 = rl78_subreg ( HImode , operands [ 0 ] , SImode , 2 ) ; if ( GET_CODE ( operands [ 1 ] ) == CONST || GET_CODE ( operands [ 1 ] ) == SYMBOL_REF ) { op10 = gen_rtx_ZERO_EXTRACT ( HImode , operands [ 1 ] , GEN_INT ( 16 ) , GEN_INT ( 0 ) ) ; op10 = gen_rtx_CONST ( HImode , op10 ) ; op12 = gen_rtx_ZERO_EXTRACT ( HImode , operands [ 1 ] , GEN_INT ( 16 ) , GEN_INT ( 16 ) ) ; op12 = gen_rtx_CONST ( HImode , op12 ) ; } else { op10 = rl78_subreg ( HImode , operands [ 1 ] , SImode , 0 ) ; op12 = rl78_subreg ( HImode , operands [ 1 ] , SImode , 2 ) ; } if ( rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) ) ; else if ( rtx_equal_p ( op00 , op12 ) ) { emit_move_insn ( op02 , op12 ) ; emit_move_insn ( op00 , op10 ) ; } else { emit_move_insn ( op00 , op10 ) ; emit_move_insn ( op02 , op12 ) ; } } </s>

Used by movsi . Split SImode moves into two HImode moves , using appropriate patterns for the upper and lower halves of symbols .


<s>
bool
LanaiInstrInfo
::
analyzeSelect
(
const
MachineInstr
&
MI
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
unsigned
&
TrueOp
,
unsigned
&
FalseOp
,
bool
&
Optimizable
)
const
{
assert
(
MI
.
getOpcode
(
)
==
Lanai
::
SELECT
&&
"unknown select instruction"
)
;
TrueOp
=
1
;
FalseOp
=
2
;
Cond
.
push_back
(
MI
.
getOperand
(
3
)
)
;
Optimizable
=
true
;
return
false
;
}
</s>

Analyze the given select instruction , returning true if it can not be understood .


<s> const char * riscv_output_move ( rtx dest , rtx src ) { enum rtx_code dest_code , src_code ; enum machine_mode mode ; bool dbl_p ; dest_code = GET_CODE ( dest ) ; src_code = GET_CODE ( src ) ; mode = GET_MODE ( dest ) ; dbl_p = ( GET_MODE_SIZE ( mode ) == 8 ) ; if ( dbl_p && riscv_split_64bit_move_p ( dest , src ) ) return "#" ; if ( dest_code == REG && GP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1" ; if ( src_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return "lbu\t%0,%1" ; case 2 : return "lhu\t%0,%1" ; case 4 : return "lw\t%0,%1" ; case 8 : return "ld\t%0,%1" ; } if ( src_code == CONST_INT ) return "li\t%0,%1" ; if ( src_code == HIGH ) return "lui\t%0,%h1" ; if ( symbolic_operand ( src , VOIDmode ) ) switch ( riscv_classify_symbolic_expression ( src ) ) { case SYMBOL_GOT_DISP : return "la\t%0,%1" ; case SYMBOL_ABSOLUTE : return "lla\t%0,%1" ; case SYMBOL_PCREL : return "lla\t%0,%1" ; default : gcc_unreachable ( ) ; } } if ( ( src_code == REG && GP_REG_P ( REGNO ( src ) ) ) || ( src == CONST0_RTX ( mode ) ) ) { if ( dest_code == REG ) { if ( GP_REG_P ( REGNO ( dest ) ) ) return "mv\t%0,%z1" ; if ( FP_REG_P ( REGNO ( dest ) ) ) { if ( ! dbl_p ) return "fmv.s.x\t%0,%z1" ; if ( TARGET_64BIT ) return "fmv.d.x\t%0,%z1" ; gcc_assert ( src == CONST0_RTX ( mode ) ) ; return "fcvt.d.w\t%0,x0" ; } } if ( dest_code == MEM ) switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return "sb\t%z1,%0" ; case 2 : return "sh\t%z1,%0" ; case 4 : return "sw\t%z1,%0" ; case 8 : return "sd\t%z1,%0" ; } } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) return dbl_p ? "fmv.d\t%0,%1" : "fmv.s\t%0,%1" ; if ( dest_code == MEM ) return dbl_p ? "fsd\t%1,%0" : "fsw\t%1,%0" ; } if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == MEM ) return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1" ; } gcc_unreachable ( ) ; } </s>

Return the appropriate instructions to move SRC into DEST . Assume that SRC is operand 1 and DEST is operand 0 .


<s> static void winnt_d_os_builtins ( void ) { d_add_builtin_version ( "Windows" ) ; EXTRA_TARGET_D_OS_VERSIONS ( ) ; } </s>

Implement TARGET_D_OS_VERSIONS for Windows targets .


<s> bool xtensa_match_CLAMPS_imms_p ( rtx cst_max , rtx cst_min ) { int max , min ; return IN_RANGE ( max = exact_log2 ( - INTVAL ( cst_max ) ) , 7 , 22 ) && IN_RANGE ( min = exact_log2 ( INTVAL ( cst_min ) + 1 ) , 7 , 22 ) && max == min ; } </s>

Return true if the constants used in the application of smin ( ) following smax ( ) meet the specifications of the CLAMPS machine instruction .


<s> bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const override { const MCInstrDesc & MCID = std :: prev ( MBB . end ( ) ) -> getDesc ( ) ; if ( MCID . isReturn ( ) || MCID . isCall ( ) ) return false ; return NumCycles <= 4 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> bool R600TargetLowering :: isZero ( SDValue Op ) const { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op ) ) { return Cst -> isZero ( ) ; } else if ( ConstantFPSDNode * CstFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CstFP -> isZero ( ) ; } else { return false ; } } </s>

Return true if the expression is a constant zero .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"RISCV RI5CY IR pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool frv_function_symbol_referenced_p ( rtx x ) { const char * format ; int length ; int j ; if ( GET_CODE ( x ) == SYMBOL_REF ) return SYMBOL_REF_FUNCTION_P ( x ) ; length = GET_RTX_LENGTH ( GET_CODE ( x ) ) ; format = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( j = 0 ; j < length ; ++ j ) { switch ( format [ j ] ) { case 'e' : if ( frv_function_symbol_referenced_p ( XEXP ( x , j ) ) ) return TRUE ; break ; case 'V' : case 'E' : if ( XVEC ( x , j ) != 0 ) { int k ; for ( k = 0 ; k < XVECLEN ( x , j ) ; ++ k ) if ( frv_function_symbol_referenced_p ( XVECEXP ( x , j , k ) ) ) return TRUE ; } break ; default : break ; } } return FALSE ; } </s>

Look for a SYMBOL_REF of a function in an rtx . We always want to process these separately from any offsets , such that we add any offsets to the function descriptor ( the actual pointer ) , not to the function address .


<s> virtual void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createX86MachObjectWriter ( OS , true , object :: mach :: CTM_x86_64 , object :: mach :: CSX86_ALL ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static rtx ix86_expand_v1ti_to_ti ( rtx x ) { rtx result = gen_reg_rtx ( TImode ) ; if ( TARGET_SSE2 ) { rtx temp = force_reg ( V2DImode , gen_lowpart ( V2DImode , x ) ) ; rtx lo = gen_lowpart ( DImode , result ) ; emit_insn ( gen_vec_extractv2didi ( lo , temp , const0_rtx ) ) ; rtx hi = gen_highpart ( DImode , result ) ; emit_insn ( gen_vec_extractv2didi ( hi , temp , const1_rtx ) ) ; } else emit_move_insn ( result , gen_lowpart ( TImode , x ) ) ; return result ; } </s>

Expand move of V1TI mode register X to a new TI mode register .


<s> static bool m32r_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { cumulative_args_t dummy = pack_cumulative_args ( NULL ) ; function_arg_info arg ( const_cast < tree > ( type ) , false ) ; return m32r_pass_by_reference ( dummy , arg ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> TargetLoweringBase :: LegalizeTypeAction WebAssemblyTargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT . isFixedLengthVector ( ) ) { MVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == MVT :: i8 || EltVT == MVT :: i16 || EltVT == MVT :: i32 || EltVT == MVT :: i64 || EltVT == MVT :: f32 || EltVT == MVT :: f64 ) return TypeWidenVector ; } return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> unsigned Tile64InstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { Tile64MachineFunctionInfo * FI = MF -> getInfo < Tile64MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & T64 :: T64GPRFRegClass ) ; DebugLoc DL ; BuildMI ( FirstMBB , MBBI , DL , get ( T64 :: GBR ) , GlobalBaseReg ) ; FI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8rm : case X86 :: MOV16rm : case X86 :: MOV32rm : case X86 :: MOV64rm : case X86 :: LD_Fp64m : case X86 :: MOVSSrm : case X86 :: MOVSDrm : case X86 :: MOVAPSrm : case X86 :: MOVAPDrm : case X86 :: MOVDQArm : case X86 :: MMX_MOVD64rm : case X86 :: MMX_MOVQ64rm : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 3 ) . isReg ( ) && MI -> getOperand ( 4 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 1 && MI -> getOperand ( 3 ) . getReg ( ) == 0 && MI -> getOperand ( 4 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
void
SPUInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
unsigned
opc
;
bool
isValidFrameIdx
=
(
FrameIdx
<
SPUFrameLowering
::
maxFrameOffset
(
)
)
;
if
(
RC
==
SPU
::
GPRCRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr128
:
SPU
::
STQXr128
)
;
}
else
if
(
RC
==
SPU
::
R64CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R64FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr64
:
SPU
::
STQXr64
)
;
}
else
if
(
RC
==
SPU
::
R32CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R32FPRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr32
:
SPU
::
STQXr32
)
;
}
else
if
(
RC
==
SPU
::
R16CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr16
:
SPU
::
STQXr16
)
;
}
else
if
(
RC
==
SPU
::
R8CRegisterClass
)
{
opc
=
(
isValidFrameIdx
SPU
::
STQDr8
:
SPU
::
STQXr8
)
;
}
else
if
(
RC
==
SPU
::
VECREGRegisterClass
)
{
opc
=
(
isValidFrameIdx
)
SPU
::
STQDv16i8
:
SPU
::
STQXv16i8
;
}
else
{
llvm_unreachable
(
"Unknown regclass!"
)
;
}
DebugLoc
DL
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
,
FrameIdx
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


runOnMachineFunction - Emit the function body .