<s>
SDValue
MSP430TargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
if
(
Ins
.
empty
(
)
)
return
Chain
;
else
{
llvm_report_error
(
"ISRs cannot have arguments"
)
;
return
SDValue
(
)
;
}
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
void
HexagonCommonGEP
::
materialize
(
NodeToValueMap
&
Loc
)
{
DEBUG
(
dbgs
(
)
<<
"Nodes before materialization:\n"
<<
Nodes
<<
'\n'
)
;
NodeChildrenMap
NCM
;
NodeVect
Roots
;
invert_find_roots
(
Nodes
,
NCM
,
Roots
)
;
while
(
!
Roots
.
empty
(
)
)
{
NodeVect
::
iterator
First
=
Roots
.
begin
(
)
;
GepNode
*
Root
=
*
First
,
*
Last
=
*
First
;
Roots
.
erase
(
First
)
;
NodeVect
;
bool
LastUsed
=
false
;
unsigned
LastCN
=
0
;
Value
*
LocV
=
Loc
[
Last
]
;
if
(
!
LocV
)
continue
;
BasicBlock
*
LastB
=
cast
<
BasicBlock
>
(
LocV
)
;
do
{
.
push_back
(
Last
)
;
LastUsed
=
(
Last
->
Flags
&
GepNode
::
Used
)
;
if
(
LastUsed
)
break
;
NodeChildrenMap
::
iterator
CF
=
NCM
.
find
(
Last
)
;
LastCN
=
(
CF
!=
NCM
.
end
(
)
)
CF
->
second
.
size
(
)
:
0
;
if
(
LastCN
!=
1
)
break
;
GepNode
*
Child
=
CF
->
second
.
front
(
)
;
BasicBlock
*
ChildB
=
cast_or_null
<
BasicBlock
>
(
Loc
[
Child
]
)
;
if
(
ChildB
!=
0
&&
LastB
!=
ChildB
)
break
;
Last
=
Child
;
}
while
(
true
)
;
BasicBlock
::
iterator
InsertAt
=
LastB
->
getTerminator
(
)
;
if
(
LastUsed
||
LastCN
>
0
)
{
ValueVect
Urs
;
getAllUsersForNode
(
Root
,
Urs
,
NCM
)
;
BasicBlock
::
iterator
FirstUse
=
first_use_of_in_block
(
Urs
,
LastB
)
;
if
(
FirstUse
!=
LastB
->
end
(
)
)
InsertAt
=
FirstUse
;
}
Value
*
NewInst
=
fabricateGEP
(
,
InsertAt
,
LastB
)
;
if
(
LastCN
>
0
)
{
NodeVect
&
Cs
=
NCM
[
Last
]
;
for
(
NodeVect
::
iterator
I
=
Cs
.
begin
(
)
,
E
=
Cs
.
end
(
)
;
I
!=
E
;
++
I
)
{
GepNode
*
CN
=
*
I
;
CN
->
Flags
&=
~
GepNode
::
Internal
;
CN
->
Flags
|=
GepNode
::
Root
;
CN
->
BaseVal
=
NewInst
;
Roots
.
push_back
(
CN
)
;
}
}
if
(
LastUsed
)
{
NodeToUsesMap
::
iterator
UF
=
Uses
.
find
(
Last
)
;
assert
(
UF
!=
Uses
.
end
(
)
&&
"No use information found"
)
;
UseSet
&
Us
=
UF
->
second
;
for
(
UseSet
::
iterator
I
=
Us
.
begin
(
)
,
E
=
Us
.
end
(
)
;
I
!=
E
;
++
I
)
{
Use
*
U
=
*
I
;
U
->
set
(
NewInst
)
;
}
}
}
}
</s>

This method can be implemented to generate a mapped Value on demand .


<s> static int mips_multipass_dfa_lookahead ( void ) { if ( TUNE_SB1 ) return 4 ; if ( TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E ) return 4 ; if ( TUNE_OCTEON || TUNE_GS264E ) return 2 ; if ( TUNE_P5600 || TUNE_P6600 || TUNE_I6400 ) return 4 ; return 0 ; } </s>


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>


<s> static void ix86_store_returned_bounds ( rtx slot , rtx bounds ) { gcc_assert ( REG_P ( slot ) ) ; emit_move_insn ( slot , bounds ) ; } </s>

Store BOUNDS returned by function into SLOT .


<s> bool SIInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUInstrInfo :: expandPostRAPseudo ( MI ) ; case AMDGPU :: SI_CONSTDATA_PTR : { unsigned Reg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned RegLo = RI . getSubReg ( Reg , AMDGPU :: sub0 ) ; unsigned RegHi = RI . getSubReg ( Reg , AMDGPU :: sub1 ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_GETPC_B64 ) , Reg ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADD_U32 ) , RegLo ) . addReg ( RegLo ) . addTargetIndex ( AMDGPU :: TI_CONSTDATA_START ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADDC_U32 ) , RegHi ) . addReg ( RegHi ) . addImm ( 0 ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) . addReg ( AMDGPU :: SCC , RegState :: Implicit ) ; MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: SGPR_USE : MI -> eraseFromParent ( ) ; break ; } return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static rtx s390_find_constant ( struct constant_pool * pool , rtx val , enum machine_mode mode ) { struct constant * c ; rtx offset ; int i ; for ( i = 0 ; i < NR_C_MODES ; i ++ ) if ( constant_modes [ i ] == mode ) break ; gcc_assert ( i != NR_C_MODES ) ; for ( c = pool -> constants [ i ] ; c != NULL ; c = c -> next ) if ( rtx_equal_p ( val , c -> value ) ) break ; gcc_assert ( c ) ; offset = gen_rtx_MINUS ( Pmode , gen_rtx_LABEL_REF ( Pmode , c -> label ) , gen_rtx_LABEL_REF ( Pmode , pool -> label ) ) ; offset = gen_rtx_CONST ( Pmode , offset ) ; return offset ; } </s>

Find constant VAL of mode MODE in the constant pool POOL . Return an RTX describing the distance from the start of the pool to the location of the new constant .


<s> static bool cris_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { enum cris_symbol_type t = cris_symbol_type_of ( x ) ; return t == cris_unspec || t == cris_got_symbol || t == cris_rel_symbol ; } </s>

Worker function for TARGET_CANNOT_FORCE_CONST_MEM . We ca n't put PIC addresses in the constant pool , not even the ones that can be reached as pc-relative as we ca n't tell when or how to do that .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> unsigned TOYInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode , cmp_mode ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case E_DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_THUMB1 ) cmp_mode = E_SImode ; else cmp_mode = CC_Zmode ; bdst = TARGET_THUMB1 ? bval : gen_rtx_REG ( CC_Zmode , CC_REGNUM ) ; emit_insn ( gen_atomic_compare_and_swap_1 ( cmp_mode , mode , bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; if ( TARGET_THUMB1 ) emit_insn ( gen_cstoresi_eq0_thumb1 ( bval , bdst ) ) ; else { x = gen_rtx_EQ ( SImode , bdst , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } } </s>


<s> bool AMDGPUCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { if ( Val ) return false ; MIRBuilder . buildInstr ( AMDGPU :: S_ENDPGM ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static MachineBasicBlock * getExitingBlock ( MachineLoop * L ) { if ( MachineBasicBlock * Latch = L -> getLoopLatch ( ) ) { if ( L -> isLoopExiting ( Latch ) ) return Latch ; else return L -> getExitingBlock ( ) ; } return nullptr ; } </s>

Return the first block of this region 's single exit edge , if existing .


<s> bool AMDGPUPassConfig :: addPreEmitPass ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createAMDGPUCFGPreparationPass ( * TM ) ) ; addPass ( createAMDGPUCFGStructurizerPass ( * TM ) ) ; addPass ( createR600EmitClauseMarkers ( * TM ) ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) ) ; addPass ( & FinalizeMachineBundlesID ) ; addPass ( createR600Packetizer ( * TM ) ) ; addPass ( createR600ControlFlowFinalizer ( * TM ) ) ; } else { addPass ( createSILowerControlFlowPass ( * TM ) ) ; } return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const TargetRegisterClass * TeakRegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> static void mips_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { rtx this , temp1 , temp2 , insn , fnaddr ; no_new_pseudos = 1 ; reload_completed = 1 ; reset_block_changes ( ) ; if ( TARGET_ABICALLS ) cfun -> machine -> global_pointer = REGNO ( pic_offset_table_rtx ) = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM ; mips_emit_loadgp ( ) ; temp1 = gen_rtx_REG ( Pmode , 2 ) ; temp2 = gen_rtx_REG ( Pmode , 3 ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this = gen_rtx_REG ( Pmode , GP_ARG_FIRST + 1 ) ; else this = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != 0 ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { emit_move_insn ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this , this , offset ) ) ; } if ( vcall_offset != 0 ) { rtx addr ; emit_move_insn ( temp1 , gen_rtx_MEM ( Pmode , this ) ) ; addr = mips_add_offset ( temp2 , temp1 , vcall_offset ) ; emit_move_insn ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this , this , temp1 ) ) ; } fnaddr = XEXP ( DECL_RTL ( function ) , 0 ) ; if ( TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS ) { if ( TARGET_ABICALLS && ! mips_dangerous_for_la25_p ( fnaddr ) ) temp1 = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; mips_load_call_address ( temp1 , fnaddr , true ) ; if ( TARGET_ABICALLS && REGNO ( temp1 ) != PIC_FUNCTION_ADDR_REGNUM ) emit_move_insn ( gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) , temp1 ) ; emit_jump_insn ( gen_indirect_jump ( temp1 ) ) ; } else { insn = emit_call_insn ( gen_sibcall_internal ( fnaddr , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; } insn = get_insns ( ) ; insn_locators_initialize ( ) ; split_all_insns_noflow ( ) ; if ( TARGET_MIPS16 ) mips16_lay_out_constants ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; no_new_pseudos = 0 ; } </s>

Implement TARGET_ASM_OUTPUT_MI_THUNK . Generate rtl rather than asm text in order to avoid duplicating too much logic from elsewhere .


<s> LaneBitmask HexagonExpandCondsets :: getLaneMask ( Register Reg , unsigned Sub ) { assert ( Reg . isVirtual ( ) ) ; return Sub != 0 ? TRI -> getSubRegIndexLaneMask ( Sub ) : MRI -> getMaxLaneMaskForVReg ( Reg ) ; } </s>

Returns the combination of all lane masks of register in this class .


<s> static rtx function_arg_union_value ( int size , machine_mode mode , int slotno , int regno ) { unsigned int nwords ; if ( size <= 0 ) return gen_rtx_REG ( mode , regno ) ; if ( slotno == SPARC_INT_ARG_MAX - 1 ) nwords = 1 ; else nwords = CEIL_NWORDS ( size ) ; rtx regs = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nwords ) ) ; for ( unsigned int i = 0 ; i < nwords ; i ++ ) XVECEXP ( regs , 0 , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno + i ) , GEN_INT ( UNITS_PER_WORD * i ) ) ; return regs ; } </s>

Used by function_arg and sparc_function_value_1 to implement the conventions of the 64-bit ABI for passing and returning unions . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . SIZE is the size in bytes of the union . MODE is the argument 's machine mode . REGNO is the hard register the union will be passed in .


<s> void JVMPassConfig :: addCodeGenPrepare ( ) { } </s>

Add pass to prepare the LLVM IR for code generation .


<s> static int loongarch_symbol_insns ( enum loongarch_symbol_type type , machine_mode mode ) { switch ( type ) { case SYMBOL_GOT_DISP : if ( mode != MAX_MACHINE_MODE ) return 0 ; return 3 ; case SYMBOL_TLSGD : case SYMBOL_TLSLDM : return 1 ; case SYMBOL_TLS : return 0 ; } gcc_unreachable ( ) ; } </s>

Returns the number of instructions necessary to reference a symbol .


<s> bool AMDGPUTTIImpl :: isSourceOfDivergence ( const Value * V ) const { if ( const Argument * A = dyn_cast < Argument > ( V ) ) return ! isArgPassedInSGPR ( A ) ; if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == AMDGPUAS :: PRIVATE_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) return isIntrinsicSourceOfDivergence ( Intrinsic ) ; if ( isa < CallInst > ( V ) || isa < InvokeInst > ( V ) ) return true ; return false ; } </s>

Returns whether V is a source of divergence .


<s> bool AVRAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case AVR :: fixup_7_pcrel : case AVR :: fixup_13_pcrel : case AVR :: fixup_call : return true ; } } </s>

Hook to check if a relocation is needed for some target specific reason .


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'r' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
static
std
::
pair
<
SDValue
,
SDValue
>
splitVector
(
SDValue
Op
,
SelectionDAG
&
DAG
,
const
SDLoc
&
dl
)
{
EVT
VT
=
Op
.
getValueType
(
)
;
unsigned
NumElems
=
VT
.
getVectorNumElements
(
)
;
unsigned
SizeInBits
=
VT
.
getSizeInBits
(
)
;
assert
(
(
NumElems
%
2
)
==
0
&&
(
SizeInBits
%
2
)
==
0
&&
"Can't split odd sized vector"
)
;
SDValue
Lo
=
extractSubVector
(
Op
,
0
,
DAG
,
dl
,
SizeInBits
/
2
)
;
if
(
DAG
.
isSplatValue
(
Op
,
false
)
)
return
std
::
make_pair
(
Lo
,
Lo
)
;
SDValue
Hi
=
extractSubVector
(
Op
,
NumElems
/
2
,
DAG
,
dl
,
SizeInBits
/
2
)
;
return
std
::
make_pair
(
Lo
,
Hi
)
;
}
</s>

Split a vector value into two parts of types LoVT and HiVT .


<s> bool X86AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { static const uint8_t Nops [ 10 ] [ 10 ] = { { 0x90 } , { 0x66 , 0x90 } , { 0x0f , 0x1f , 0x00 } , { 0x0f , 0x1f , 0x40 , 0x00 } , { 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x44 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x80 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , { 0x66 , 0x2e , 0x0f , 0x1f , 0x84 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 } , } ; if ( CPU == "generic" || CPU == "i386" || CPU == "i486" || CPU == "i586" || CPU == "pentium" || CPU == "pentium-mmx" || CPU == "geode" ) { for ( uint64_t i = 0 ; i < Count ; ++ i ) OW -> Write8 ( 0x90 ) ; return true ; } do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , ( uint64_t ) 15 ) ; const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10 ; for ( uint8_t i = 0 ; i < Prefixes ; i ++ ) OW -> Write8 ( 0x66 ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = 0 ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - 1 ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> const char * SNESTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case SNESISD :: name : \ return # name switch ( Opcode ) { default : return nullptr ; NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ; NODE ( ROR ) ; NODE ( ASR ) ; NODE ( LSLLOOP ) ; NODE ( LSRLOOP ) ; NODE ( ASRLOOP ) ; NODE ( BRCOND ) ; NODE ( CMP ) ; NODE ( CMPC ) ; NODE ( TST ) ; NODE ( SELECT_CC ) ; } </s>

getTargetNodeName - This method returns the name of a target specific


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> static rtx ix86_expand_binop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ 2 ] . mode ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! insn_data [ icode ] . operand [ 0 ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( GET_MODE ( op1 ) == SImode && mode1 == TImode ) { rtx x = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_loadd ( x , op1 ) ) ; op1 = gen_lowpart ( TImode , x ) ; } if ( ! insn_data [ icode ] . operand [ 1 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! insn_data [ icode ] . operand [ 2 ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of binop insns .


<s> unsigned OR1KRegisterInfo :: getRARegister ( ) const { return OR1K :: R9 ; } </s>

This method should return the register where the return address can be found .


<s>
unsigned
R600InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
{
return
0
;
}
I
;
switch
(
I
->
getOpcode
(
)
)
{
default
:
return
0
;
case
R600
::
JUMP_COND
:
{
MachineInstr
*
predSet
=
findFirstPredicateSetterFrom
(
MBB
,
I
)
;
clearFlag
(
*
predSet
,
0
,
MO_FLAG_PUSH
)
;
I
->
eraseFromParent
(
)
;
MachineBasicBlock
::
iterator
CfAlu
=
FindLastAluClause
(
MBB
)
;
if
(
CfAlu
==
MBB
.
end
(
)
)
break
;
assert
(
CfAlu
->
getOpcode
(
)
==
R600
::
CF_ALU_PUSH_BEFORE
)
;
CfAlu
->
setDesc
(
get
(
R600
::
CF_ALU
)
)
;
break
;
}
case
R600
::
JUMP
:
I
->
eraseFromParent
(
)
;
break
;
}
I
=
MBB
.
end
(
)
;
if
(
I
==
MBB
.
begin
(
)
)
{
return
1
;
}
I
;
switch
(
I
->
getOpcode
(
)
)
{
default
:
return
1
;
case
R600
::
JUMP_COND
:
{
MachineInstr
*
predSet
=
findFirstPredicateSetterFrom
(
MBB
,
I
)
;
clearFlag
(
*
predSet
,
0
,
MO_FLAG_PUSH
)
;
I
->
eraseFromParent
(
)
;
MachineBasicBlock
::
iterator
CfAlu
=
FindLastAluClause
(
MBB
)
;
if
(
CfAlu
==
MBB
.
end
(
)
)
break
;
assert
(
CfAlu
->
getOpcode
(
)
==
R600
::
CF_ALU_PUSH_BEFORE
)
;
CfAlu
->
setDesc
(
get
(
R600
::
CF_ALU
)
)
;
break
;
}
case
R600
::
JUMP
:
I
->
eraseFromParent
(
)
;
break
;
}
return
2
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s> bool PPCSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_ALL ; CriticalPathRCs . clear ( ) ; if ( isPPC64 ( ) ) CriticalPathRCs . push_back ( & PPC :: G8RCRegClass ) ; else CriticalPathRCs . push_back ( & PPC :: GPRCRegClass ) ; return OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .

PowerPC PPC PPC PPC::G8RCRegClass PPC::GPRCRegClass


<s>
bool
HexagonInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
const
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
int
Opc
=
MI
->
getOpcode
(
)
;
assert
(
isPredicable
(
MI
)
&&
"Expected predicable instruction"
)
;
bool
invertJump
=
(
!
Cond
.
empty
(
)
&&
Cond
[
0
]
.
isImm
(
)
&&
(
Cond
[
0
]
.
getImm
(
)
==
0
)
)
;
MI
->
setDesc
(
get
(
getMatchingCondBranchOpcode
(
Opc
,
invertJump
)
)
)
;
MI
->
addOperand
(
MI
->
getOperand
(
MI
->
getNumOperands
(
)
1
)
)
;
int
oper
;
for
(
oper
=
MI
->
getNumOperands
(
)
3
;
oper
>=
0
;
oper
)
{
MachineOperand
MO
=
MI
->
getOperand
(
oper
)
;
if
(
(
MO
.
isReg
(
)
&&
!
MO
.
isUse
(
)
&&
!
MO
.
isImplicit
(
)
)
)
{
break
;
}
if
(
MO
.
isReg
(
)
)
{
MI
->
getOperand
(
oper
+
1
)
.
ChangeToRegister
(
MO
.
getReg
(
)
,
MO
.
isDef
(
)
,
MO
.
isImplicit
(
)
,
MO
.
isKill
(
)
,
MO
.
isDead
(
)
,
MO
.
isUndef
(
)
,
MO
.
isDebug
(
)
)
;
}
else
if
(
MO
.
isImm
(
)
)
{
MI
->
getOperand
(
oper
+
1
)
.
ChangeToImmediate
(
MO
.
getImm
(
)
)
;
}
else
{
llvm_unreachable
(
"Unexpected operand type"
)
;
}
}
int
regPos
=
invertJump
1
:
0
;
MachineOperand
PredMO
=
Cond
[
regPos
]
;
MI
->
getOperand
(
oper
+
1
)
.
ChangeToRegister
(
PredMO
.
getReg
(
)
,
PredMO
.
isDef
(
)
,
PredMO
.
isImplicit
(
)
,
PredMO
.
isKill
(
)
,
PredMO
.
isDead
(
)
,
PredMO
.
isUndef
(
)
,
PredMO
.
isDebug
(
)
)
;
return
true
;
}
</s>

Convert the instruction into a predicated instruction .


<s> unsigned get231Opcode ( ) const { return Opcodes [ Form231 ] ; } </s>


<s>
void
BlackfinInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD32fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD16fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD8fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
"Cannot load regclass from stack slot"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = 13 ; first_reg <= 31 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; if ( first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic != 0 ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) && rs6000_reg_live_or_pic_offset_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) first_reg = RS6000_PIC_OFFSET_TABLE_REGNUM ; if ( flag_pic && crtl -> uses_pic_offset_table && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM ) return RS6000_PIC_OFFSET_TABLE_REGNUM ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


<s> static bool isShiftedMask ( uint64_t I , uint64_t & Pos , uint64_t & Size ) { if ( ! isShiftedMask_64 ( I ) ) return false ; Size = CountPopulation_64 ( I ) ; Pos = CountTrailingZeros_64 ( I ) ; return true ; } </s>

Return true if this APInt value contains a non-empty sequence of ones with the remainder zero .


<s> void BitcodeWriter :: writeModule ( const Module & M ) { assert ( ! WroteStrtab ) ; assert ( M . isMaterialized ( ) ) ; Mods . push_back ( const_cast < Module * > ( & M ) ) ; DXILBitcodeWriter ModuleWriter ( M , Buffer , StrtabBuilder , * Stream ) ; ModuleWriter . write ( ) ; } </s>

Write the specified module to the buffer specified at construction time .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; const AMDGPUTargetMachine & TM = getAMDGPUTargetMachine ( ) ; addPass ( createAMDGPUAnnotateKernelFeaturesPass ( & TM ) ) ; addPass ( & AMDGPUUnifyDivergentExitNodesID ) ; addPass ( createStructurizeCFGPass ( true ) ) ; addPass ( createSinkingPass ( ) ) ; addPass ( createSITypeRewriter ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; addPass ( createSIAnnotateControlFlowPass ( ) ) ; return false ; } </s>

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU SI AMDGPU SI


<s> CAHPSubtarget & CAHPSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R11W ) ; Reserved . set ( SystemZ :: R10P ) ; Reserved . set ( SystemZ :: R10Q ) ; } Reserved . set ( SystemZ :: R14D ) ; Reserved . set ( SystemZ :: R15D ) ; Reserved . set ( SystemZ :: R14W ) ; Reserved . set ( SystemZ :: R15W ) ; Reserved . set ( SystemZ :: R14P ) ; Reserved . set ( SystemZ :: R14Q ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
unsigned
MipsABIInfo
::
GetCalleeAllocdArgSizeInBytes
(
CallingConv
::
ID
CC
)
const
{
if
(
IsO32
(
)
)
return
CC
!=
CallingConv
::
Fast
16
:
0
;
if
(
IsN32
(
)
||
IsN64
(
)
||
IsEABI
(
)
)
return
0
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

Obtain the size of the area allocated by the callee for arguments .


<s> void XCoreInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s> unsigned SIInstrInfo :: getAddressSpaceForPseudoSourceKind ( PseudoSourceValue :: PSVKind Kind ) const { switch ( Kind ) { case PseudoSourceValue :: Stack : case PseudoSourceValue :: FixedStack : return AMDGPUASI . PRIVATE_ADDRESS ; case PseudoSourceValue :: ConstantPool : case PseudoSourceValue :: GOT : case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom : return AMDGPUASI . CONSTANT_ADDRESS ; } return AMDGPUASI . FLAT_ADDRESS ; } </s>

getAddressSpaceForPseudoSourceKind - Given the kind of memory ( e.g .


<s> void PTXMCAsmStreamer :: AddComment ( const Twine & T ) { if ( ! IsVerboseAsm ) return ; CommentStream . flush ( ) ; T . toVector ( CommentToEmit ) ; CommentToEmit . push_back ( '\n' ) ; CommentStream . resync ( ) ; } </s>


<s> static section * c6x_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( c6x_sdata_mode == C6X_SDATA_ALL || ( c6x_sdata_mode != C6X_SDATA_NONE && GET_MODE_SIZE ( mode ) <= 8 ) ) return sdata_section ; else return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Return a section for X . The only special thing we do here is to honor small data . We do n't have a tree type , so we ca n't use the PLACE_IN_SDATA_P macro we use everywhere else ; we choose to place everything sized 8 bytes or smaller into small data .


<s> const char * nvptx_ptx_type_from_mode ( machine_mode mode , bool promote ) { switch ( mode ) { case E_BLKmode : return ".b8" ; case E_BImode : return ".pred" ; case E_QImode : if ( promote ) return ".u32" ; else return ".u8" ; case E_HImode : return ".u16" ; case E_SImode : return ".u32" ; case E_DImode : return ".u64" ; case E_HFmode : return ".f16" ; case E_SFmode : return ".f32" ; case E_DFmode : return ".f64" ; case E_V2SImode : return ".v2.u32" ; case E_V2DImode : return ".v2.u64" ; default : gcc_unreachable ( ) ; } } </s>

Return a ptx type for MODE . If PROMOTE , then use .u32 for QImode to deal with ptx ideosyncracies .


<s> static void rs6000_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( first + size <= 32768 ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; rtx r0 = gen_rtx_REG ( Pmode , 0 ) ; gcc_assert ( first <= 32768 ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ) ; if ( rounded_size > 32768 ) { emit_move_insn ( r0 , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r0 , gen_rtx_PLUS ( Pmode , r12 , r0 ) ) ) ; } else emit_insn ( gen_rtx_SET ( r0 , plus_constant ( Pmode , r12 , - rounded_size ) ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_probe_stack_rangedi ( r12 , r12 , stack_pointer_rtx , r0 ) ) ; else emit_insn ( gen_probe_stack_rangesi ( r12 , r12 , stack_pointer_rtx , r0 ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; } } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static rtx_insn * get_next_active_insn ( rtx_insn * insn , rtx_insn * tail ) { if ( insn == NULL_RTX || insn == tail ) return NULL ; while ( 1 ) { insn = NEXT_INSN ( insn ) ; if ( insn == NULL_RTX || insn == tail ) return NULL ; if ( CALL_P ( insn ) || JUMP_P ( insn ) || JUMP_TABLE_DATA_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && INSN_CODE ( insn ) != CODE_FOR_stack_tie ) ) break ; } return insn ; } </s>

Return the next insn after INSN that is found before TAIL is reached , skipping any `` non-active '' insns - insns that will not actually occupy an issue slot . Return NULL_RTX if such an insn is not found .


<s> std :: pair < unsigned , const TargetRegisterClass * > BlackfinTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { typedef std :: pair < unsigned , const TargetRegisterClass * > Pair ; using namespace BF ; if ( Constraint . size ( ) != 1 ) return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; switch ( Constraint [ 0 ] ) { case 'r' : return Pair ( 0U , VT == MVT :: i16 ? D16RegisterClass : DPRegisterClass ) ; case 'a' : return Pair ( 0U , PRegisterClass ) ; case 'd' : return Pair ( 0U , DRegisterClass ) ; case 'e' : return Pair ( 0U , AccuRegisterClass ) ; case 'A' : return Pair ( A0 , AccuRegisterClass ) ; case 'B' : return Pair ( A1 , AccuRegisterClass ) ; case 'b' : return Pair ( 0U , IRegisterClass ) ; case 'v' : return Pair ( 0U , BRegisterClass ) ; case 'f' : return Pair ( 0U , MRegisterClass ) ; case 'C' : return Pair ( CC , JustCCRegisterClass ) ; case 'x' : return Pair ( 0U , GRRegisterClass ) ; case 'w' : return Pair ( 0U , ALLRegisterClass ) ; case 'Z' : return Pair ( P3 , PRegisterClass ) ; case 'Y' : return Pair ( P1 , PRegisterClass ) ; } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void setPersonality ( const MCSymbol * Per ) { HasPersonality = 1 ; } </s>


Return true if C is an acceptable character inside a symbol name .


<s> FuncInfo ( ) : MemInstCost ( 0 ) , InstCost ( 0 ) , IAMInstCost ( 0 ) , LSMInstCost ( 0 ) { } </s>

Information about the function as a whole .


<s> bool ix86_target_stack_probe ( void ) { if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) return false ; return TARGET_STACK_PROBE ; } </s>

Decide whether we must probe the stack before any space allocation on this target . It 's essentially TARGET_STACK_PROBE except when -fstack-check causes the stack to be already probed differently .


<s> static bool originalTypeIsF128 ( const Type * Ty , const SDNode * CallNode ) { if ( Ty -> isFP128Ty ( ) ) return true ; if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == 1 && Ty -> getStructElementType ( 0 ) -> isFP128Ty ( ) ) return true ; const ExternalSymbolSDNode * ES = dyn_cast_or_null < const ExternalSymbolSDNode > ( CallNode ) ; return ( ES && Ty -> isIntegerTy ( 128 ) && isF128SoftLibCall ( ES -> getSymbol ( ) ) ) ; } </s>

This function returns true if Ty is fp128 , { f128 } or i128 which was originally a fp128 .


"custom instruction opcode must be compile time "

"constant in the range 0-255 for __builtin_custom_%s"

Helper function for expanding custom builtins .


<s> PPCSubtarget & PPCSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>


<s> void HexagonSubtarget :: adjustSchedDependency ( SUnit * Src , SUnit * Dst , SDep & Dep ) const { MachineInstr * SrcInst = Src -> getInstr ( ) ; MachineInstr * DstInst = Dst -> getInstr ( ) ; if ( ! Src -> isInstr ( ) || ! Dst -> isInstr ( ) ) return ; const HexagonInstrInfo * QII = getInstrInfo ( ) ; SmallSet < SUnit * , 4 > ExclSrc ; SmallSet < SUnit * , 4 > ExclDst ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } if ( ! hasV60TOps ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( 0 ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == 1 ) { unsigned DReg = DstInst -> getOperand ( 0 ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ 0 ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - 1 ; for ( unsigned OpNum = 0 ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , 0 , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , 0 ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } updateLatency ( * SrcInst , * DstInst , Dep ) ; } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ProfileSummaryInfoWrapperPass > ( ) ; AU . addRequired < LazyMachineBlockFrequencyInfoPass > ( ) ; AU . addPreserved < LazyMachineBlockFrequencyInfoPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s>
bool
AMDGPUOpenCLEnqueuedBlockLowering
::
runOnModule
(
Module
&
M
)
{
DenseSet
<
Function
*
>
Callers
;
auto
&
C
=
M
.
getContext
(
)
;
bool
Changed
=
false
;
for
(
auto
&
F
:
M
.
functions
(
)
)
{
if
(
F
.
hasFnAttribute
(
"enqueued-block"
)
)
{
if
(
!
F
.
hasName
(
)
)
{
SmallString
<
64
>
Name
;
Mangler
::
getNameWithPrefix
(
Name
,
"__amdgpu_enqueued_kernel"
,
M
.
getDataLayout
(
)
)
;
F
.
setName
(
Name
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"found enqueued kernel: "
<<
F
.
getName
(
)
<<
'\n'
)
;
auto
RuntimeHandle
=
(
F
.
getName
(
)
+
".runtime_handle"
)
.
str
(
)
;
auto
T
=
Type
::
getInt8Ty
(
C
)
->
getPointerTo
(
AMDGPUAS
::
GLOBAL_ADDRESS
)
;
auto
*
GV
=
new
GlobalVariable
(
M
,
T
,
false
,
GlobalValue
::
ExternalLinkage
,
Constant
::
getNullValue
(
T
)
,
RuntimeHandle
,
nullptr
,
GlobalValue
::
NotThreadLocal
,
AMDGPUAS
::
GLOBAL_ADDRESS
,
false
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"runtime handle created: "
<<
*
GV
<<
'\n'
)
;
for
(
auto
U
:
F
.
users
(
)
)
{
auto
*
UU
=
&
*
U
;
if
(
!
isa
<
ConstantExpr
>
(
UU
)
)
continue
;
collectFunctionUsers
(
UU
,
Callers
)
;
auto
*
BitCast
=
cast
<
ConstantExpr
>
(
UU
)
;
auto
*
NewPtr
=
ConstantExpr
::
getPointerCast
(
GV
,
BitCast
->
getType
(
)
)
;
BitCast
->
replaceAllUsesWith
(
NewPtr
)
;
F
.
addFnAttr
(
"runtime-handle"
,
RuntimeHandle
)
;
F
.
setLinkage
(
GlobalValue
::
ExternalLinkage
)
;
Changed
=
true
;
}
}
}
for
(
auto
F
:
Callers
)
{
if
(
F
->
getCallingConv
(
)
!=
CallingConv
::
AMDGPU_KERNEL
)
continue
;
F
->
addFnAttr
(
"calls-enqueue-kernel"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"mark enqueue_kernel caller:"
<<
F
->
getName
(
)
<<
'\n'
)
;
}
return
Changed
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

AMDGPU
AMDGPU
"enqueued-block"
64
"__amdgpu_enqueued_kernel"
"found enqueued kernel: "
".runtime_handle"
AMDGPU
AMDGPU
"runtime handle created: "
"runtime-handle"
AMDGPU
"calls-enqueue-kernel"
"mark enqueue_kernel caller:"


<s> static bool mips_cfun_call_saved_reg_p ( unsigned int regno ) { if ( global_regs [ regno ] ) return false ; if ( cfun -> machine -> interrupt_handler_p && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return ( regno == GLOBAL_POINTER_REGNUM ? TARGET_CALL_SAVED_GP : ! call_used_regs [ regno ] ) ; } </s>

Return true if the current function should treat register REGNO as call-saved .


<s> rtx h8300_get_index ( rtx x , enum machine_mode mode , int * size ) { int dummy , factor ; if ( size == 0 ) size = & dummy ; factor = ( mode == VOIDmode ? 0 : GET_MODE_SIZE ( mode ) ) ; if ( TARGET_H8300SX && factor <= 4 && ( mode == VOIDmode || GET_MODE_CLASS ( mode ) == MODE_INT || GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) { if ( factor <= 1 && GET_CODE ( x ) == ZERO_EXTEND ) { * size = GET_MODE_SIZE ( GET_MODE ( XEXP ( x , 0 ) ) ) ; return XEXP ( x , 0 ) ; } else { rtx index ; if ( GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( factor == 0 || INTVAL ( XEXP ( x , 1 ) ) == 0xff * factor || INTVAL ( XEXP ( x , 1 ) ) == 0xffff * factor ) ) { index = XEXP ( x , 0 ) ; * size = ( INTVAL ( XEXP ( x , 1 ) ) >= 0xffff ? 2 : 1 ) ; } else { index = x ; * size = 4 ; } if ( GET_CODE ( index ) == MULT && GET_CODE ( XEXP ( index , 1 ) ) == CONST_INT && ( factor == 0 || factor == INTVAL ( XEXP ( index , 1 ) ) ) ) return XEXP ( index , 0 ) ; } } * size = 0 ; return x ; } </s>

Given that X occurs in an address of the form ( plus X constant ) , return the part of X that is expected to be a register . There are four kinds of addressing mode to recognize : @ ( dd , Rn ) @ ( dd , RnL.b ) @ ( dd , Rn.w ) @ ( dd , ERn.l ) If SIZE is nonnull , and the address is one of the last three forms , set * SIZE to the index multiplication factor . Set it to 0 for plain @ ( dd , Rn ) addresses . MODE is the mode of the value being accessed . It can be VOIDmode if the address is known to be valid , but its mode is unknown .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; AArch64GISelActualAccessor * GISel = new AArch64GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new AArch64CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new AArch64LegalizerInfo ( ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> InstSelector . reset ( createAArch64InstructionSelector ( * this , * I , * RBI ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void LanaiFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const LanaiRegisterInfo * LRI = STI . getRegisterInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; Align StackAlign = LRI -> hasStackRealignment ( MF ) ? MFI . getMaxAlign ( ) : getStackAlign ( ) ; unsigned MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> static bool const_vector_equal_evenodd_p ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; int i , nunits = GET_MODE_NUNITS ( mode ) ; if ( GET_CODE ( op ) != CONST_VECTOR || nunits != CONST_VECTOR_NUNITS ( op ) ) return false ; for ( i = 0 ; i < nunits ; i += 2 ) if ( CONST_VECTOR_ELT ( op , i ) != CONST_VECTOR_ELT ( op , i + 1 ) ) return false ; return true ; } </s>

Helper function of ix86_expand_mul_widen_evenodd . Return true if op is CONST_VECTOR with all odd elements equal to their preceding element .


<s> static void block_move_call ( rtx dest_reg , rtx src_reg , rtx bytes_rtx ) { if ( GET_MODE ( bytes_rtx ) != VOIDmode && GET_MODE ( bytes_rtx ) != Pmode ) bytes_rtx = convert_to_mode ( Pmode , bytes_rtx , 1 ) ; emit_library_call ( m32r_function_symbol ( "memcpy" ) , 0 , VOIDmode , 3 , dest_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; } </s>

Use a library function to move some bytes .


<s>
void
M88kIncomingValueHandler
::
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
VA
)
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
uint64_t
ValSize
=
VA
.
getValVT
(
)
.
getFixedSizeInBits
(
)
;
uint64_t
LocSize
=
VA
.
getLocVT
(
)
.
getFixedSizeInBits
(
)
;
assert
(
ValSize
<=
64
&&
"Unsupported value size"
)
;
assert
(
LocSize
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
if
(
ValSize
==
LocSize
)
{
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
else
{
assert
(
ValSize
<
LocSize
&&
"Extensions not supported"
)
;
auto
PhysRegToVReg
=
MIRBuilder
.
buildCopy
(
LLT
::
scalar
(
LocSize
)
,
PhysReg
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
PhysRegToVReg
)
;
}
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static void sh_setup_incoming_varargs ( cumulative_args_t ca , machine_mode mode , tree type , int * pretend_arg_size , int second_time ATTRIBUTE_UNUSED ) { gcc_assert ( cfun -> stdarg ) ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { int named_parm_regs , anon_parm_regs ; named_parm_regs = ( sh_round_reg ( * get_cumulative_args ( ca ) , mode ) + ( mode == BLKmode ? CEIL ( int_size_in_bytes ( type ) , UNITS_PER_WORD ) : CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) - named_parm_regs ; if ( anon_parm_regs > 0 ) * pretend_arg_size = anon_parm_regs * 4 ; } } </s>

We actually emit the code in sh_expand_prologue . We used to use a static variable to flag that we need to emit this code , but that does n't when inlining , when functions are deferred and then emitted later . Fortunately , we already have two flags that are part of struct function that tell if a function uses varargs or stdarg .


<s> bool DCPU16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DCPU16MachineFunctionInfo * MFI = MF . getInfo < DCPU16MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( DCPU16 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void tool_cleanup ( bool from_signal ATTRIBUTE_UNUSED ) { for ( int i = 0 ; i < num_temps ; i ++ ) maybe_unlink ( temp_files [ i ] ) ; } </s>


<s> bool addRange ( uint64_t Start , uint64_t End , Instruction * Inst ) { auto I = llvm :: lower_bound ( Ranges , Start , [ ] ( const Range & LHS , uint64_t RHS ) { return LHS . End <= RHS ; } ) ; if ( I != Ranges . end ( ) && End > I -> Start ) { return false ; } Ranges . insert ( I , { Start , End , Inst } ) ; return true ; } </s>

addRange - Add an address range to the list of ranges for this unit .


"********** Replace Physical Registers **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned opc = N -> getOpcode ( ) ; switch ( opc ) { default : break ; case ISD :: ADDE : return PerformADDECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUBE : return PerformSUBECombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SDIVREM : case ISD :: UDIVREM : return PerformDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return PerformANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return PerformORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return PerformADDCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::ADDE ISD::SUBE ISD::SDIVREM ISD::UDIVREM ISD::SELECT ISD::AND ISD::OR ISD::ADD


<s> void rs6000_expand_vector_extract ( rtx target , rtx vec , rtx elt ) { machine_mode mode = GET_MODE ( vec ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx mem ; if ( VECTOR_MEM_VSX_P ( mode ) && CONST_INT_P ( elt ) ) { switch ( mode ) { default : break ; case V1TImode : gcc_assert ( INTVAL ( elt ) == 0 && inner_mode == TImode ) ; emit_move_insn ( target , gen_lowpart ( TImode , vec ) ) ; break ; case V2DFmode : emit_insn ( gen_vsx_extract_v2df ( target , vec , elt ) ) ; return ; case V2DImode : emit_insn ( gen_vsx_extract_v2di ( target , vec , elt ) ) ; return ; case V4SFmode : emit_insn ( gen_vsx_extract_v4sf ( target , vec , elt ) ) ; return ; case V16QImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v16qi ( target , vec , elt ) ) ; return ; } else break ; case V8HImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v8hi ( target , vec , elt ) ) ; return ; } else break ; case V4SImode : if ( TARGET_DIRECT_MOVE_64BIT ) { emit_insn ( gen_vsx_extract_v4si ( target , vec , elt ) ) ; return ; } break ; } } else if ( VECTOR_MEM_VSX_P ( mode ) && ! CONST_INT_P ( elt ) && TARGET_DIRECT_MOVE_64BIT ) { if ( GET_MODE ( elt ) != DImode ) { rtx tmp = gen_reg_rtx ( DImode ) ; convert_move ( tmp , elt , 0 ) ; elt = tmp ; } else if ( ! REG_P ( elt ) ) elt = force_reg ( DImode , elt ) ; switch ( mode ) { case V2DFmode : emit_insn ( gen_vsx_extract_v2df_var ( target , vec , elt ) ) ; return ; case V2DImode : emit_insn ( gen_vsx_extract_v2di_var ( target , vec , elt ) ) ; return ; case V4SFmode : emit_insn ( gen_vsx_extract_v4sf_var ( target , vec , elt ) ) ; return ; case V4SImode : emit_insn ( gen_vsx_extract_v4si_var ( target , vec , elt ) ) ; return ; case V8HImode : emit_insn ( gen_vsx_extract_v8hi_var ( target , vec , elt ) ) ; return ; case V16QImode : emit_insn ( gen_vsx_extract_v16qi_var ( target , vec , elt ) ) ; return ; default : gcc_unreachable ( ) ; } } gcc_assert ( CONST_INT_P ( elt ) ) ; mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( mem , vec ) ; mem = adjust_address_nv ( mem , inner_mode , INTVAL ( elt ) * GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( target , adjust_address_nv ( mem , inner_mode , 0 ) ) ; } </s>

Extract field ELT from VEC into TARGET .


<s> bool AMDGPUInstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { return false ; } </s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> BaseKind getKind ( ) const { return Kind ; } </s>


"The destination address is not aligned to a word"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void MSP430AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { MSP430MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & FS , bool isT ) : ARMArchVersion ( V4 ) , ARMFPUType ( None ) , UseNEONForSinglePrecisionFP ( UseNEONFP ) , IsThumb ( isT ) , ThumbMode ( Thumb1 ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( UseMOVT ) , HasFP16 ( false ) , stackAlignment ( 4 ) , CPUString ( "generic" ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; if ( CPUString == "generic" && ( FS . empty ( ) || FS == "generic" ) ) ARMArchVersion = V4T ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 5 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { ARMArchVersion = V7A ; } else if ( SubVer == '6' ) { ARMArchVersion = V6 ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == '2' ) ARMArchVersion = V6T2 ; } else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + 2 && TT [ Idx + 1 ] == 't' ) ARMArchVersion = V4T ; else ARMArchVersion = V4 ; } } if ( ARMArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) ARMArchVersion = V6T2 ; if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( ARMArchVersion < V6 ) ; if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( CPUString == "cortex-a8" ) { if ( UseNEONFP . getPosition ( ) == 0 ) UseNEONForSinglePrecisionFP = true ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s>
TargetTransformInfo
MipsTargetMachine
::
getTargetTransformInfo
(
const
Function
&
F
)
{
if
(
Subtarget
->
allowMixed16_32
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"No Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
F
.
getParent
(
)
->
getDataLayout
(
)
)
;
}
LLVM_DEBUG
(
errs
(
)
<<
"Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
BasicTTIImpl
(
this
,
F
)
)
;
}
</s>

Get a TargetTransformInfo implementation for the target .

Mips
Mips
"No Target Transform Info Pass Added\n"
"Target Transform Info Pass Added\n"


<s> void JVMFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> unsigned getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) , const Instruction * CxtI = nullptr ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: MUL : case ISD :: SDIV : case ISD :: UDIV : case ISD :: UREM : return 64 * BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

Lanai ISD::MUL ISD::SDIV ISD::UDIV ISD::UREM 64


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> const CallLowering * X86Subtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ; } </s>


<s>
bool
NVPTXAsmPrinter
::
doInitialization
(
Module
&
M
)
{
const
Triple
&
TT
=
TM
.
getTargetTriple
(
)
;
StringRef
CPU
=
TM
.
getTargetCPU
(
)
;
StringRef
FS
=
TM
.
getTargetFeatureString
(
)
;
const
NVPTXTargetMachine
&
NTM
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
TM
)
;
const
NVPTXSubtarget
STI
(
TT
,
CPU
,
FS
,
NTM
)
;
SmallString
<
128
>
Str1
;
raw_svector_ostream
OS1
(
Str1
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
const_cast
<
TargetLoweringObjectFile
&
>
(
getObjFileLowering
(
)
)
.
Initialize
(
OutContext
,
TM
)
;
Mang
=
new
Mangler
(
)
;
emitHeader
(
M
,
OS1
,
STI
)
;
OutStreamer
->
EmitRawText
(
OS1
.
str
(
)
)
;
if
(
!
M
.
getModuleInlineAsm
(
)
.
empty
(
)
)
{
OutStreamer
->
AddComment
(
"Start of file scope inline assembly"
)
;
OutStreamer
->
AddBlankLine
(
)
;
OutStreamer
->
EmitRawText
(
StringRef
(
M
.
getModuleInlineAsm
(
)
)
)
;
OutStreamer
->
AddBlankLine
(
)
;
OutStreamer
->
AddComment
(
"End of file scope inline assembly"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
if
(
TM
.
getTargetTriple
(
)
.
getOS
(
)
!=
Triple
::
NVCL
)
recordAndEmitFilenames
(
M
)
;
GlobalsEmitted
=
false
;
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

NVPTX
NVPTX
NVPTX
NVPTX
NVPTX
128
"Start of file scope inline assembly"
"End of file scope inline assembly"


<s> void update ( unsigned R , const LatticeCell & L ) { Map [ R ] = L ; } </s>


<s> void visium_split_cstore ( enum rtx_code op_code , rtx op0 , rtx op1 , enum rtx_code code , rtx op2 , rtx op3 ) { enum machine_mode cc_mode = visium_select_cc_mode ( code , op2 , op3 ) ; if ( cc_mode == CCFPEmode && ( op_code == NEG || op_code == MINUS ) ) cc_mode = CCFPmode ; rtx flags = gen_rtx_REG ( cc_mode , FLAGS_REGNUM ) ; rtx x = gen_rtx_COMPARE ( cc_mode , op2 , op3 ) ; x = gen_rtx_SET ( flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( code , SImode , flags , const0_rtx ) ; switch ( op_code ) { case SET : break ; case NEG : x = gen_rtx_NEG ( SImode , x ) ; break ; case PLUS : case MINUS : x = gen_rtx_fmt_ee ( op_code , SImode , op1 , x ) ; break ; default : gcc_unreachable ( ) ; } rtx pat = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( pat , 0 , 0 ) = gen_rtx_SET ( op0 , x ) ; flags = gen_rtx_REG ( CCmode , FLAGS_REGNUM ) ; XVECEXP ( pat , 0 , 1 ) = gen_rtx_CLOBBER ( VOIDmode , flags ) ; emit_insn ( pat ) ; visium_flags_exposed = true ; } </s>

Split a compare-and-store with CODE , operands OP2 and OP3 , combined with operation with OP_CODE , operands OP0 and OP1 .


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < SISubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool IsIEEEMode = ST -> enableIEEEBit ( MF ) || ! MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return false ; } </s>


<s> static int ix86_comp_type_attributes ( tree type1 , tree type2 ) { const char * const rtdstr = TARGET_RTD ? "cdecl" : "stdcall" ; if ( TREE_CODE ( type1 ) != FUNCTION_TYPE ) return 1 ; if ( ( ! lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( type2 ) ) ) || ( ix86_function_regparm ( type1 , NULL ) != ix86_function_regparm ( type2 , NULL ) ) ) return 0 ; if ( ! lookup_attribute ( "sseregparm" , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( "sseregparm" , TYPE_ATTRIBUTES ( type2 ) ) ) return 0 ; if ( ! lookup_attribute ( rtdstr , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( rtdstr , TYPE_ATTRIBUTES ( type2 ) ) ) return 0 ; return 1 ; } </s>

Return 0 if the attributes for two types are incompatible , 1 if they are compatible , and 2 if they are nearly compatible ( which causes a warning to be generated ) .


<s> bool aarch64_simd_check_vect_par_cnst_half ( rtx op , machine_mode mode , bool high ) { rtx ideal = aarch64_simd_vect_par_cnst_half ( mode , high ) ; HOST_WIDE_INT count_op = XVECLEN ( op , 0 ) ; HOST_WIDE_INT count_ideal = XVECLEN ( ideal , 0 ) ; int i = 0 ; if ( ! VECTOR_MODE_P ( mode ) ) return false ; if ( count_op != count_ideal ) return false ; for ( i = 0 ; i < count_ideal ; i ++ ) { rtx elt_op = XVECEXP ( op , 0 , i ) ; rtx elt_ideal = XVECEXP ( ideal , 0 , i ) ; if ( ! CONST_INT_P ( elt_op ) || INTVAL ( elt_ideal ) != INTVAL ( elt_op ) ) return false ; } return true ; } </s>

Check OP for validity as a PARALLEL RTX vector with elements numbering the lanes of either the high ( HIGH == TRUE ) or low lanes , from the perspective of the architecture . See the diagram above aarch64_simd_vect_par_cnst_half for more details .


<s> bool bfin_legitimate_address_p ( enum machine_mode mode , rtx x , int strict ) { switch ( GET_CODE ( x ) ) { case REG : if ( bfin_valid_reg_p ( REGNO ( x ) , strict ) ) return true ; break ; case PLUS : if ( REG_P ( XEXP ( x , 0 ) ) && bfin_valid_reg_p ( REGNO ( XEXP ( x , 0 ) ) , strict ) && ( GET_CODE ( XEXP ( x , 1 ) ) == UNSPEC || ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && bfin_valid_add ( mode , INTVAL ( XEXP ( x , 1 ) ) ) ) ) ) return true ; break ; case POST_INC : case POST_DEC : if ( LEGITIMATE_MODE_FOR_AUTOINC_P ( mode ) && REG_P ( XEXP ( x , 0 ) ) && bfin_valid_reg_p ( REGNO ( XEXP ( x , 0 ) ) , strict ) ) return true ; case PRE_DEC : if ( LEGITIMATE_MODE_FOR_AUTOINC_P ( mode ) && XEXP ( x , 0 ) == stack_pointer_rtx && REG_P ( XEXP ( x , 0 ) ) && bfin_valid_reg_p ( REGNO ( XEXP ( x , 0 ) ) , strict ) ) return true ; break ; default : break ; } return false ; } </s>

Recognize an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . Blackfin addressing modes are as follows : [ preg ] [ preg + imm16 ] B [ Preg + uimm15 ] W [ Preg + uimm16m2 ] [ Preg + uimm17m4 ] [ preg++ ] [ preg -- ] [ -- sp ]


<s> void SIInstrInfo :: reserveIndirectRegisters ( BitVector & Reserved , const MachineFunction & MF ) const { int End = getIndirectIndexEnd ( MF ) ; int Begin = getIndirectIndexBegin ( MF ) ; if ( End == - 1 ) return ; for ( int Index = Begin ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VGPR_32RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( 0 , Begin - 1 ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_64RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( 0 , Begin - 2 ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_96RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( 0 , Begin - 3 ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_128RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( 0 , Begin - 7 ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_256RegClass . getRegister ( Index ) ) ; for ( int Index = std :: max ( 0 , Begin - 15 ) ; Index <= End ; ++ Index ) Reserved . set ( AMDGPU :: VReg_512RegClass . getRegister ( Index ) ) ; } </s>

Reserve the registers that may be accessed using indirect addressing .


<s>
void
TPCHazardRecognizer
::
Reset
(
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"  *HR* Reset Hazard Recognizer\n"
)
;
clearResources
(
)
;
PacketNum
=
0
;
}
</s>

TPC
TPC
"  *HR* Reset Hazard Recognizer\n"
0


<s> int includes_lshift_p ( rtx shiftop , rtx andop ) { unsigned HOST_WIDE_INT shift_mask = ~ ( unsigned HOST_WIDE_INT ) 0 ; shift_mask <<= INTVAL ( shiftop ) ; return ( INTVAL ( andop ) & 0xffffffff & ~ shift_mask ) == 0 ; } </s>

Return 1 if ANDOP is a mask that has no bits on that are not in the mask required to convert the result of a rotate insn into a shift left insn of SHIFTOP bits . Both are known to be SImode CONST_INT .


<s> static rtx altivec_expand_vec_init_builtin ( tree type , tree arglist , rtx target ) { enum machine_mode tmode = TYPE_MODE ( type ) ; enum machine_mode inner_mode = GET_MODE_INNER ( tmode ) ; int i , n_elt = GET_MODE_NUNITS ( tmode ) ; rtvec v = rtvec_alloc ( n_elt ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; for ( i = 0 ; i < n_elt ; ++ i , arglist = TREE_CHAIN ( arglist ) ) { rtx x = expand_expr ( TREE_VALUE ( arglist ) , NULL_RTX , VOIDmode , 0 ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } gcc_assert ( arglist == NULL ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rs6000_expand_vector_init ( target , gen_rtx_PARALLEL ( tmode , v ) ) ; return target ; } </s>


<s> static bool is_leaf_function ( function * fn ) { basic_block bb ; gimple_stmt_iterator gsi ; if ( fn -> cfg == NULL ) return false ; FOR_EACH_BB_FN ( bb , fn ) for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) if ( is_gimple_call ( gsi_stmt ( gsi ) ) ) return false ; return true ; } </s>

Return true if it is certain that this is a leaf function . False if it is not a leaf function or if it is impossible to tell .


<s> uint64_t Mips64GOT :: emit ( MemoryRegion & pRegion ) { uint64_t * buffer = reinterpret_cast < uint64_t * > ( pRegion . begin ( ) ) ; uint64_t result = 0 ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { Mips64GOTEntry * got = & ( llvm :: cast < Mips64GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint64_t > ( got -> getValue ( ) ) ; result += got -> size ( ) ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s> unsigned getNumFixupKinds ( ) const override { return Mips :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> void emitBasicBlockEnd ( const MachineBasicBlock & MBB ) override { AsmPrinter :: emitBasicBlockEnd ( MBB ) ; SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; } </s>

Targets can override this to emit stuff at the end of a basic block .


<s> static enum rtx_code ix86_prepare_fp_compare_args ( enum rtx_code code , rtx * pop0 , rtx * pop1 ) { machine_mode fpcmp_mode = ix86_fp_compare_mode ( code ) ; rtx op0 = * pop0 , op1 = * pop1 ; machine_mode op_mode = GET_MODE ( op0 ) ; int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P ( op_mode ) ; if ( ! is_sse && ( fpcmp_mode == CCFPUmode || ( op_mode == XFmode && ! ( standard_80387_constant_p ( op0 ) == 1 || standard_80387_constant_p ( op1 ) == 1 ) && GET_CODE ( op1 ) != FLOAT ) || ix86_fp_comparison_strategy ( code ) == IX86_FPCMP_COMI ) ) { op0 = force_reg ( op_mode , op0 ) ; op1 = force_reg ( op_mode , op1 ) ; } else { if ( standard_80387_constant_p ( op0 ) == 0 || ( MEM_P ( op0 ) && ! ( standard_80387_constant_p ( op1 ) == 0 || MEM_P ( op1 ) ) ) ) { enum rtx_code new_code = ix86_fp_swap_condition ( code ) ; if ( new_code != UNKNOWN ) { std :: swap ( op0 , op1 ) ; code = new_code ; } } if ( ! REG_P ( op0 ) ) op0 = force_reg ( op_mode , op0 ) ; if ( CONSTANT_P ( op1 ) ) { int tmp = standard_80387_constant_p ( op1 ) ; if ( tmp == 0 ) op1 = validize_mem ( force_const_mem ( op_mode , op1 ) ) ; else if ( tmp == 1 ) { if ( TARGET_CMOVE ) op1 = force_reg ( op_mode , op1 ) ; } else op1 = force_reg ( op_mode , op1 ) ; } } if ( ix86_fp_comparison_cost ( code ) > ix86_fp_comparison_cost ( swap_condition ( code ) ) && ( REG_P ( op1 ) || can_create_pseudo_p ( ) ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; if ( ! REG_P ( op0 ) ) op0 = force_reg ( op_mode , op0 ) ; } * pop0 = op0 ; * pop1 = op1 ; return code ; } </s>

Swap , force into registers , or otherwise massage the two operands to a fp comparison . The operands are updated in place ; the new comparsion code is returned .


<s> void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_fmt_ee ( code , GET_MODE ( target ) , op0 , op1 ) ) ) ; } </s>

Emit an instruction of the form ( set TARGET ( CODE OP0 OP1 ) ) .


<s> int avr_vdump ( FILE * stream , const char * caller , ... ) { va_list ap ; if ( NULL == stream && dump_file ) stream = dump_file ; va_start ( ap , caller ) ; if ( stream ) avr_log_vadump ( stream , caller , ap ) ; va_end ( ap ) ; return 1 ; } </s>

Wrapper for avr_log_vadump . If STREAM is NULL we are called by avr_dump , i.e . output to dump_file if available . The 2nd argument is __FUNCTION__ . The 3rd argument is the format string .


<s> void HexagonAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB = HexagonMCInstrInfo :: createBundle ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; unsigned IgnoreCount = 0 ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else { HexagonLowerToMC ( & * MII , MCB , * this ) ; } } } else { HexagonLowerToMC ( MI , MCB , * this ) ; HexagonMCInstrInfo :: padEndloop ( OutStreamer -> getContext ( ) , MCB ) ; } HexagonMCInstrInfo :: tryCompound ( * Subtarget -> getInstrInfo ( ) , OutStreamer -> getContext ( ) , MCB ) ; SmallVector < DuplexCandidate , 8 > possibleDuplexes ; possibleDuplexes = HexagonMCInstrInfo :: getDuplexPossibilties ( * Subtarget -> getInstrInfo ( ) , MCB ) ; HexagonMCShuffle ( * Subtarget -> getInstrInfo ( ) , * Subtarget , OutStreamer -> getContext ( ) , MCB , possibleDuplexes ) ; EmitToStreamer ( * OutStreamer , MCB ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon 0 Hexagon Hexagon Hexagon Hexagon 8 Hexagon Hexagon


<s> bool WebAssemblyFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; unsigned i = 0 ; for ( auto const & Arg : F -> args ( ) ) { const AttributeSet & Attrs = F -> getAttributes ( ) ; if ( Attrs . hasAttribute ( i + 1 , Attribute :: ByVal ) || Attrs . hasAttribute ( i + 1 , Attribute :: SwiftSelf ) || Attrs . hasAttribute ( i + 1 , Attribute :: SwiftError ) || Attrs . hasAttribute ( i + 1 , Attribute :: InAlloca ) || Attrs . hasAttribute ( i + 1 , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( getSimpleType ( ArgTy ) ) { case MVT :: i1 : case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : Opc = WebAssembly :: ARGUMENT_I32 ; RC = & WebAssembly :: I32RegClass ; break ; case MVT :: i64 : Opc = WebAssembly :: ARGUMENT_I64 ; RC = & WebAssembly :: I64RegClass ; break ; case MVT :: f32 : Opc = WebAssembly :: ARGUMENT_F32 ; RC = & WebAssembly :: F32RegClass ; break ; case MVT :: f64 : Opc = WebAssembly :: ARGUMENT_F64 ; RC = & WebAssembly :: F64RegClass ; break ; default : return false ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( i ) ; updateValueMap ( & Arg , ResultReg ) ; ++ i ; } MRI . addLiveIn ( WebAssembly :: ARGUMENTS ) ; auto * MFI = MF -> getInfo < WebAssemblyFunctionInfo > ( ) ; for ( auto const & Arg : F -> args ( ) ) MFI -> addParam ( getLegalType ( getSimpleType ( Arg . getType ( ) ) ) ) ; return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> void AArch64TargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasStackProtectorIndex ( ) ) { for ( unsigned int i = 0 , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI . getStackID ( i ) == TargetStackID :: ScalableVector && MFI . getObjectSSPLayout ( i ) != MachineFrameInfo :: SSPLK_None ) { MFI . setStackID ( MFI . getStackProtectorIndex ( ) , TargetStackID :: ScalableVector ) ; MFI . setObjectAlignment ( MFI . getStackProtectorIndex ( ) , Align ( 16 ) ) ; break ; } } } MFI . computeMaxCallFrameSize ( MF ) ; TargetLoweringBase :: finalizeLowering ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> LaneBitmask HexagonExpandCondsets :: getLaneMask ( unsigned Reg , unsigned Sub ) { assert ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; return Sub != 0 ? TRI -> getSubRegIndexLaneMask ( Sub ) : MRI -> getMaxLaneMaskForVReg ( Reg ) ; } </s>

Returns the combination of all lane masks of register in this class .


<s> int m68hc11_auto_inc_p ( rtx x ) { return GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == PRE_INC ; } </s>

Returns true if X is a PRE/POST increment decrement ( same as auto_inc_p ( ) in rtlanal.c but do not take into account the stack ) .


<s> bool SystemZInstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Pred , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! STI . hasLoadStoreOnCond ( ) ) return false ; if ( Pred . size ( ) != 2 ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ( STI . hasLoadStoreOnCond2 ( ) && SystemZ :: GRX32BitRegClass . hasSubClassEq ( RC ) ) || SystemZ :: GR32BitRegClass . hasSubClassEq ( RC ) || SystemZ :: GR64BitRegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> static pad_direction mips_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! BYTES_BIG_ENDIAN ) return PAD_UPWARD ; if ( type != 0 ? ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || FIXED_POINT_TYPE_P ( type ) ) : ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) ) return PAD_DOWNWARD ; if ( mips_abi == ABI_O64 ) if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return PAD_DOWNWARD ; if ( mips_abi != ABI_EABI ) return PAD_UPWARD ; if ( mode != BLKmode ? GET_MODE_BITSIZE ( mode ) >= PARM_BOUNDARY : int_size_in_bytes ( type ) >= ( PARM_BOUNDARY / BITS_PER_UNIT ) ) return PAD_UPWARD ; return PAD_DOWNWARD ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING ; return PAD_UPWARD if the first byte of the stack slot has useful data , PAD_DOWNWARD if the last byte does .


<s>
SDValue
HSAILTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
HSAILMachineFunctionInfo
*
FuncInfo
=
MF
.
getInfo
<
HSAILMachineFunctionInfo
>
(
)
;
HSAILParamManager
&
PM
=
FuncInfo
->
getParamManager
(
)
;
unsigned
AS
=
HSAIL
::
isKernelFunc
(
MF
.
getFunction
(
)
)
HSAILAS
::
KERNARG_ADDRESS
:
HSAILAS
::
ARG_ADDRESS
;
const
DataLayout
&
DL
=
MF
.
getFunction
(
)
->
getParent
(
)
->
getDataLayout
(
)
;
MVT
PtrTy
=
getPointerTy
(
DL
,
AS
)
;
Mangler
Mang
;
Function
::
const_arg_iterator
AI
=
MF
.
getFunction
(
)
->
arg_begin
(
)
;
Function
::
const_arg_iterator
AE
=
MF
.
getFunction
(
)
->
arg_end
(
)
;
for
(
unsigned
ArgNo
=
0
;
AI
!=
AE
;
++
AI
)
{
unsigned
Param
=
PM
.
addArgumentParam
(
AS
,
*
AI
,
HSAILParamManager
::
mangleArg
(
&
Mang
,
AI
->
getName
(
)
,
DL
)
)
;
const
char
*
ParamName
=
PM
.
getParamName
(
Param
)
;
std
::
string
md
=
(
AI
->
getName
(
)
+
":"
+
ParamName
+
" "
)
.
str
(
)
;
FuncInfo
->
addMetadata
(
"argmap:"
+
md
,
true
)
;
SDValue
ParamPtr
=
DAG
.
getTargetExternalSymbol
(
ParamName
,
PtrTy
)
;
LowerArgument
(
Chain
,
SDValue
(
)
,
false
,
&
Ins
,
nullptr
,
dl
,
DAG
,
&
InVals
,
ArgNo
,
AI
->
getType
(
)
,
AS
,
ParamName
,
ParamPtr
,
nullptr
)
;
}
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

HSAIL
HSAIL
ISD::InputArg
HSAIL
HSAIL
HSAIL
HSAIL::isKernelFunc
HSAILAS::KERNARG_ADDRESS
HSAILAS::ARG_ADDRESS
0
HSAIL
":"
" "
"argmap:"


<s> static void riscv_extend_comparands ( rtx_code code , rtx * op0 , rtx * op1 ) { if ( GET_MODE_SIZE ( word_mode ) > GET_MODE_SIZE ( GET_MODE ( * op0 ) ) ) { if ( unsigned_condition ( code ) == code && GET_MODE ( * op0 ) == QImode ) { * op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ; if ( CONST_INT_P ( * op1 ) ) * op1 = GEN_INT ( ( uint8_t ) INTVAL ( * op1 ) ) ; else * op1 = gen_rtx_ZERO_EXTEND ( word_mode , * op1 ) ; } else { * op0 = gen_rtx_SIGN_EXTEND ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = gen_rtx_SIGN_EXTEND ( word_mode , * op1 ) ; } } } </s>

Sign- or zero-extend OP0 and OP1 for integer comparisons .


<s> static bool aarch64_mode_valid_for_sched_fusion_p ( machine_mode mode ) { return mode == SImode || mode == DImode || mode == SFmode || mode == DFmode || ( aarch64_vector_mode_supported_p ( mode ) && GET_MODE_SIZE ( mode ) == 8 ) ; } </s>

Return true if MODE is one of the modes for which we support LDP/STP operations .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > 1 ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) , Idx ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; X86OutgoingValueAssigner Assigner ( CC_X86 ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static void epiphany_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum = ROUND_ADVANCE_CUM ( * cum , mode , type ) + ROUND_ADVANCE_ARG ( mode , type ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s>
static
std
::
unique_ptr
<
X86Operand
>
CreateMem
(
unsigned
ModeSize
,
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
auto
Res
=
llvm
::
make_unique
<
X86Operand
>
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
ModeSize
=
ModeSize
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> bool rs6000_fndecl_pcrel_p ( const_tree fndecl ) { if ( DEFAULT_ABI != ABI_ELFv2 ) return false ; struct cl_target_option * opts = target_opts_for_fn ( fndecl ) ; return ( ( opts -> x_rs6000_isa_flags & OPTION_MASK_PCREL ) != 0 && TARGET_CMODEL == CMODEL_MEDIUM ) ; } </s>

Return whether we should generate PC-relative code for FNDECL .


<s>
ScheduleHazardRecognizer
::
HazardType
HexagonHazardRecognizer
::
getHazardType
(
SUnit
*
SU
,
int
stalls
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
if
(
!
MI
||
TII
->
isZeroCost
(
MI
->
getOpcode
(
)
)
)
return
NoHazard
;
if
(
!
Resources
->
canReserveResources
(
*
MI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"*** Hazard in cycle "
<<
PacketNum
<<
", "
<<
*
MI
)
;
HazardType
RetVal
=
Hazard
;
if
(
isNewStore
(
*
MI
)
)
{
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
MachineInstr
*
NewMI
=
MF
->
CreateMachineInstr
(
TII
->
get
(
TII
->
getDotNewOp
(
*
MI
)
)
,
MI
->
getDebugLoc
(
)
)
;
if
(
Resources
->
canReserveResources
(
*
NewMI
)
)
RetVal
=
NoHazard
;
LLVM_DEBUG
(
dbgs
(
)
<<
"*** Try .new version? "
<<
(
RetVal
==
NoHazard
)
<<
"\n"
)
;
MF
->
deleteMachineInstr
(
NewMI
)
;
}
return
RetVal
;
}
if
(
SU
==
UsesDotCur
&&
DotCurPNum
!=
(
int
)
PacketNum
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"*** .cur Hazard in cycle "
<<
PacketNum
<<
", "
<<
*
MI
)
;
return
Hazard
;
}
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .

Hexagon
Hexagon
"*** Hazard in cycle "
", "
"*** Try .new version? "
"\n"
"*** .cur Hazard in cycle "
", "


<s> MVT RISCVTargetLowering :: getPointerTy ( const DataLayout & DL , uint32_t AS ) const { if ( AS == UINT32_MAX ) { AS = 0 ; } return MVT :: getIntegerVT ( DL . getPointerSizeInBits ( AS ) ) ; } </s>

Return the pointer type for the given address space , defaults to the pointer type from the data layout .


<s>
bool
arc_legitimate_constant_p
(
machine_mode
mode
,
rtx
x
)
{
switch
(
GET_CODE
(
x
)
)
{
case
CONST
:
if
(
flag_pic
)
{
if
(
arc_legitimate_pic_addr_p
(
x
)
)
return
true
;
}
return
arc_legitimate_constant_p
(
mode
,
XEXP
(
x
,
0
)
)
;
case
SYMBOL_REF
:
if
(
SYMBOL_REF_TLS_MODEL
(
x
)
)
return
false
;
case
LABEL_REF
:
if
(
flag_pic
)
return
false
;
case
CONST_INT
:
case
CONST_DOUBLE
:
return
true
;
case
NEG
:
return
arc_legitimate_constant_p
(
mode
,
XEXP
(
x
,
0
)
)
;
case
PLUS
:
case
MINUS
:
{
bool
t1
=
arc_legitimate_constant_p
(
mode
,
XEXP
(
x
,
0
)
)
;
bool
t2
=
arc_legitimate_constant_p
(
mode
,
XEXP
(
x
,
1
)
)
;
return
(
t1
&&
t2
)
;
}
case
CONST_VECTOR
:
switch
(
mode
)
{
case
E_V2HImode
:
return
TARGET_PLUS_DMPY
;
case
E_V2SImode
:
case
E_V4HImode
:
return
TARGET_PLUS_QMACW
;
default
:
return
false
;
}
case
UNSPEC
:
switch
(
XINT
(
x
,
1
)
)
{
case
UNSPEC_TLS_GD
:
case
UNSPEC_TLS_OFF
:
case
UNSPEC_TLS_IE
:
return
true
;
default
:
return
false
;
}
default
:
fatal_insn
(
"unrecognized supposed constant"
,
x
)
;
}
gcc_unreachable
(
)
;
}
</s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


"Don't know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool shouldInsertFencesForAtomic ( const Instruction * I ) const override { return true ; } </s>

Helper functions for atomic operations .


<s> bool cris_return_address_on_stack ( void ) { return df_regs_ever_live_p ( CRIS_SRP_REGNUM ) || cfun -> machine -> needs_return_address_on_stack ; } </s>

Accessor used in cris.md : return because cfun- > machine is n't available there .


<s> bool X86TTIImpl :: isLSRCostLess ( const TargetTransformInfo :: LSRCost & C1 , const TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s> bool PPCQPXLoadSplat :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; bool MadeChange = false ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( auto MFI = MF . begin ( ) , MFIE = MF . end ( ) ; MFI != MFIE ; ++ MFI ) { MachineBasicBlock * MBB = & * MFI ; SmallVector < MachineInstr * , 4 > Splats ; for ( auto MBBI = MBB -> rbegin ( ) ; MBBI != MBB -> rend ( ) ; ++ MBBI ) { MachineInstr * MI = & * MBBI ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isCall ( ) ) { Splats . clear ( ) ; continue ; } for ( auto SI = Splats . begin ( ) ; SI != Splats . end ( ) ; ) { MachineInstr * SMI = * SI ; Register SplatReg = SMI -> getOperand ( 0 ) . getReg ( ) ; Register SrcReg = SMI -> getOperand ( 1 ) . getReg ( ) ; if ( MI -> modifiesRegister ( SrcReg , TRI ) ) { switch ( MI -> getOpcode ( ) ) { default : SI = Splats . erase ( SI ) ; continue ; case PPC :: LFS : case PPC :: LFD : case PPC :: LFSU : case PPC :: LFDU : case PPC :: LFSUX : case PPC :: LFDUX : case PPC :: LFSX : case PPC :: LFDX : case PPC :: LFIWAX : case PPC :: LFIWZX : if ( SplatReg != SrcReg ) { unsigned SubRegIndex = TRI -> getSubRegIndex ( SrcReg , MI -> getOperand ( 0 ) . getReg ( ) ) ; Register SplatSubReg = TRI -> getSubReg ( SplatReg , SubRegIndex ) ; MI -> getOperand ( 0 ) . setReg ( SplatSubReg ) ; MI -> substituteRegister ( SrcReg , SplatReg , 0 , * TRI ) ; } SI = Splats . erase ( SI ) ; ++ MBBI ; SMI -> eraseFromParent ( ) ; -- MBBI ; ++ NumSimplified ; MadeChange = true ; continue ; } } if ( MI -> modifiesRegister ( SplatReg , TRI ) || ( SrcReg != SplatReg && MI -> readsRegister ( SplatReg , TRI ) ) ) { SI = Splats . erase ( SI ) ; continue ; } ++ SI ; } if ( MI -> getOpcode ( ) != PPC :: QVESPLATI && MI -> getOpcode ( ) != PPC :: QVESPLATIs && MI -> getOpcode ( ) != PPC :: QVESPLATIb ) continue ; if ( MI -> getOperand ( 2 ) . getImm ( ) != 0 ) continue ; if ( ! MI -> getOperand ( 1 ) . isKill ( ) ) continue ; Splats . push_back ( MI ) ; } } return MadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool visium_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { return ! visium_interrupt_function_p ( ) ; } </s>

Return true if it is ok to do sibling call optimization for the specified call expression EXP . DECL will be the called function , or NULL if this is an indirect call .


<s> void AArch64O0PreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool X86TargetLowering :: isZExtFree ( MVT VT1 , MVT VT2 ) const { return VT1 == MVT :: i32 && VT2 == MVT :: i64 && Subtarget -> is64Bit ( ) ; } </s>

Return true if zero-extending the specific node Val to type VT2 is free ( either because it 's implicitly zero-extended such as ARM ldrb / ldrh or because it 's folded such as X86 zero-extending loads ) .


<s> unsigned int ix86_regmode_natural_size ( machine_mode mode ) { if ( mode == P2HImode || mode == P2QImode ) return GET_MODE_SIZE ( mode ) / 2 ; return UNITS_PER_WORD ; } </s>

Implement REGMODE_NATURAL_SIZE ( MODE ) .


"No expandLargeImm(SP, StackSize, false, TII, MBB, MBBI, dl);"


<s>
void
PPCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
;
if
(
PPC
::
GPRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR
;
else
if
(
PPC
::
G8RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
OR8
;
else
if
(
PPC
::
F4RCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
FMR
;
else
if
(
PPC
::
CRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
MCRF
;
else
if
(
PPC
::
VRRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
VOR
;
else
if
(
PPC
::
CRBITRCRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
PPC
::
CROR
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
const
MCInstrDesc
&
MCID
=
get
(
Opc
)
;
if
(
MCID
.
getNumOperands
(
)
==
3
)
BuildMI
(
MBB
,
I
,
DL
,
MCID
,
DestReg
)
.
addReg
(
SrcReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
BuildMI
(
MBB
,
I
,
DL
,
MCID
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>

PowerPC
PPC
PPC::GPRCRegClass
PPC::OR
PPC::G8RCRegClass
PPC::OR8
PPC::F4RCRegClass
PPC::FMR
PPC::CRRCRegClass
PPC::MCRF
PPC::VRRCRegClass
PPC::VOR
PPC::CRBITRCRegClass
PPC::CROR
"Impossible reg-to-reg copy"
3


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetPostRAHazardRecognizer
(
const
InstrItineraryData
*
II
,
const
ScheduleDAG
*
DAG
)
const
{
unsigned
Directive
=
TM
.
getSubtarget
<
PPCSubtarget
>
(
)
.
getDarwinDirective
(
)
;
if
(
Directive
!=
PPC
::
DIR_440
)
{
const
TargetInstrInfo
*
TII
=
TM
.
getInstrInfo
(
)
;
assert
(
TII
&&
"No InstrInfo?"
)
;
return
new
PPCHazardRecognizer970
(
*
TII
)
;
}
return
TargetInstrInfoImpl
::
CreateTargetPostRAHazardRecognizer
(
II
,
DAG
)
;
}
</s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .

PowerPC
PPC
PPC
PPC::DIR_440
"No InstrInfo?"
PPC


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; addPass ( createMipsLongBranchPass ( TM ) ) ; addPass ( createMipsConstantIslandPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
ZExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
SExt
:
Arg
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static inline void atomic_free ( unsigned int * mask , int bit ) { __sync_xor_and_fetch ( mask , 1 << bit ) ; } </s>


<s> void h8300_expand_store ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 2 ] ; rtx op1 = operands [ 3 ] ; rtx tmp ; tmp = gen_rtx_COMPARE ( VOIDmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( cc0_rtx , tmp ) ) ; tmp = gen_rtx_fmt_ee ( code , GET_MODE ( dest ) , cc0_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( dest , tmp ) ) ; } </s>


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( EVT VT ) const { if ( Subtarget -> hasNEON ( ) ) { if ( VT == MVT :: v4i64 ) return ARM :: QQPRRegisterClass ; else if ( VT == MVT :: v8i64 ) return ARM :: QQQQPRRegisterClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .

ARM ARM MVT::v4i64 ARM::QQPRRegisterClass MVT::v8i64 ARM::QQQQPRRegisterClass


<s>
void
print
(
)
{
if
(
numSymbols
==
0
)
{
for
(
unsigned
i
=
0
;
i
<
size
;
i
++
)
{
if
(
i
)
O
<<
", "
;
O
<<
(
unsigned
int
)
buffer
[
i
]
;
}
}
else
{
unsigned
int
pos
=
0
;
unsigned
int
nSym
=
0
;
unsigned
int
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
unsigned
int
nBytes
=
4
;
if
(
static_cast
<
const
NVPTXTargetMachine
&
>
(
AP
.
TM
)
.
is64Bit
(
)
)
nBytes
=
8
;
for
(
pos
=
0
;
pos
<
size
;
pos
+=
nBytes
)
{
if
(
pos
)
O
<<
", "
;
if
(
pos
==
nextSymbolPos
)
{
const
Value
*
v
=
Symbols
[
nSym
]
;
if
(
const
GlobalValue
*
GVar
=
dyn_cast
<
GlobalValue
>
(
v
)
)
{
MCSymbol
*
Name
=
AP
.
getSymbol
(
GVar
)
;
PointerType
*
PTy
=
dyn_cast
<
PointerType
>
(
GVar
->
getType
(
)
)
;
bool
IsNonGenericPointer
=
false
;
if
(
PTy
&&
PTy
->
getAddressSpace
(
)
!=
0
)
{
IsNonGenericPointer
=
true
;
}
if
(
EmitGeneric
&&
!
isa
<
Function
>
(
v
)
&&
!
IsNonGenericPointer
)
{
O
<<
"generic("
;
O
<<
*
Name
;
O
<<
")"
;
}
else
{
O
<<
*
Name
;
}
}
else
if
(
const
ConstantExpr
*
Cexpr
=
dyn_cast
<
ConstantExpr
>
(
v
)
)
{
O
<<
*
AP
.
lowerConstant
(
Cexpr
)
;
}
else
llvm_unreachable
(
"symbol type unknown"
)
;
nSym
++
;
if
(
nSym
>=
numSymbols
)
nextSymbolPos
=
size
+
1
;
else
nextSymbolPos
=
symbolPosInBuffer
[
nSym
]
;
}
else
if
(
nBytes
==
4
)
O
<<
*
(
unsigned
int
*
)
(
&
buffer
[
pos
]
)
;
else
O
<<
*
(
unsigned
long
long
*
)
(
&
buffer
[
pos
]
)
;
}
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> int iq2000_reg_mode_ok_for_base_p ( rtx reg , enum machine_mode mode ATTRIBUTE_UNUSED , int strict ) { return ( strict ? REGNO_MODE_OK_FOR_BASE_P ( REGNO ( reg ) , mode ) : GP_REG_OR_PSEUDO_NONSTRICT_P ( REGNO ( reg ) , mode ) ) ; } </s>

Return nonzero if REG is valid for MODE .