<s> bool M68kFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; M68kMachineFunctionInfo * M68kFI = MF . getInfo < M68kMachineFunctionInfo > ( ) ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + M68kFI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i < e ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> rtx legitimize_pic_address ( rtx orig , rtx reg , rtx picreg ) { rtx addr = orig ; rtx new = orig ; if ( GET_CODE ( addr ) == SYMBOL_REF || GET_CODE ( addr ) == LABEL_REF ) { if ( GET_CODE ( addr ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( addr ) ) reg = new = orig ; else { if ( reg == 0 ) { gcc_assert ( ! no_new_pseudos ) ; reg = gen_reg_rtx ( Pmode ) ; } if ( flag_pic == 2 ) { emit_insn ( gen_movsi_high_pic ( reg , addr ) ) ; emit_insn ( gen_movsi_low_pic ( reg , reg , addr ) ) ; emit_insn ( gen_addsi3 ( reg , reg , picreg ) ) ; new = gen_const_mem ( Pmode , reg ) ; } else { rtx tmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , addr ) , UNSPEC_MOVE_PIC ) ; new = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , picreg , tmp ) ) ; } emit_move_insn ( reg , new ) ; } if ( picreg == pic_offset_table_rtx ) current_function_uses_pic_offset_table = 1 ; return reg ; } else if ( GET_CODE ( addr ) == CONST || GET_CODE ( addr ) == PLUS ) { rtx base ; if ( GET_CODE ( addr ) == CONST ) { addr = XEXP ( addr , 0 ) ; gcc_assert ( GET_CODE ( addr ) == PLUS ) ; } if ( XEXP ( addr , 0 ) == picreg ) return orig ; if ( reg == 0 ) { gcc_assert ( ! no_new_pseudos ) ; reg = gen_reg_rtx ( Pmode ) ; } base = legitimize_pic_address ( XEXP ( addr , 0 ) , reg , picreg ) ; addr = legitimize_pic_address ( XEXP ( addr , 1 ) , base == reg ? NULL_RTX : reg , picreg ) ; if ( GET_CODE ( addr ) == CONST_INT ) { gcc_assert ( ! reload_in_progress && ! reload_completed ) ; addr = force_reg ( Pmode , addr ) ; } if ( GET_CODE ( addr ) == PLUS && CONSTANT_P ( XEXP ( addr , 1 ) ) ) { base = gen_rtx_PLUS ( Pmode , base , XEXP ( addr , 0 ) ) ; addr = XEXP ( addr , 1 ) ; } return gen_rtx_PLUS ( Pmode , base , addr ) ; } return new ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s>
void
SIScheduleBlock
::
releaseSucc
(
SUnit
*
SU
,
SDep
*
SuccEdge
)
{
SUnit
*
SuccSU
=
SuccEdge
->
getSUnit
(
)
;
if
(
SuccEdge
->
isWeak
(
)
)
{
SuccSU
->
WeakPredsLeft
;
return
;
}
if
(
SuccSU
->
NumPredsLeft
==
0
)
{
dbgs
(
)
<<
"*** Scheduling failed! ***\n"
;
DAG
->
dumpNode
(
*
SuccSU
)
;
dbgs
(
)
<<
" has been released too many times!\n"
;
llvm_unreachable
(
nullptr
)
;
}
SuccSU
->
NumPredsLeft
;
}
</s>

ReleaseSucc - Decrement the NumPredsLeft count of a successor .

AMDGPU
SI
0
"*** Scheduling failed! ***\n"
" has been released too many times!\n"


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
Size
,
Align
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
DestReg
!=
AMDGPU
::
M0
&&
"m0 should not be reloaded into"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
Register
::
isVirtualRegister
(
DestReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillRestoreOpcode
(
SpillSize
)
:
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
auto
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
;
if
(
RI
.
hasAGPRs
(
RC
)
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
Register
Tmp
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
VGPR_32RegClass
)
;
MIB
.
addReg
(
Tmp
,
RegState
::
Define
)
;
}
MIB
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> static int getMinValue ( uint64_t TSFlags ) { unsigned isSigned = ( TSFlags >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( TSFlags >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return - 1U << ( bits - 1 ) ; return 0 ; } </s>

Return the minimal unsigned value possible given these KnownBits .


<s> unsigned PatmosRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = TM . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? Patmos :: RFP : Patmos :: RSP ; } </s>


<s> static bool r10k_safe_mem_expr_p ( tree expr , unsigned HOST_WIDE_INT offset ) { HOST_WIDE_INT bitoffset , bitsize ; tree inner , var_offset ; machine_mode mode ; int unsigned_p , reverse_p , volatile_p ; inner = get_inner_reference ( expr , & bitsize , & bitoffset , & var_offset , & mode , & unsigned_p , & reverse_p , & volatile_p ) ; if ( ! DECL_P ( inner ) || ! DECL_SIZE_UNIT ( inner ) || var_offset ) return false ; offset += bitoffset / BITS_PER_UNIT ; return offset < tree_to_uhwi ( DECL_SIZE_UNIT ( inner ) ) ; } </s>

Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is an in-range access to an automatic variable , or to an object with a link-time-constant address .


<s> bool LEGInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case LEG :: MOVi32 : { DebugLoc DL = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; const bool DstIsDead = MI . getOperand ( 0 ) . isDead ( ) ; const MachineOperand & MO = MI . getOperand ( 1 ) ; auto LO16 = BuildMI ( MBB , MI , DL , get ( LEG :: MOVLOi16 ) , DstReg ) ; auto HI16 = BuildMI ( MBB , MI , DL , get ( LEG :: MOVHIi16 ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const unsigned Imm = MO . getImm ( ) ; const unsigned Lo16 = Imm & 0xffff ; const unsigned Hi16 = ( Imm >> 16 ) & 0xffff ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; const unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | LEGII :: MO_LO16 ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | LEGII :: MO_HI16 ) ; } MBB . erase ( MI ) ; return true ; } } } </s>

This function is called for all pseudo instructions that remain after register allocation .


Helper function of mt_legitimate_address_p . Return true if XINSN is a simple address , otherwise false .


<s> bool MOSTargetLowering :: isTruncateFree ( Type * SrcTy , Type * DstTy ) const { if ( ! SrcTy -> isIntegerTy ( ) || ! DstTy -> isIntegerTy ( ) ) return false ; return SrcTy -> getPrimitiveSizeInBits ( ) > DstTy -> getPrimitiveSizeInBits ( ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> static void emit_save_or_restore_local_in_regs ( rtx base , int offset , sorr_act_t action ) { if ( offset < - 4096 || offset + 16 * UNITS_PER_WORD > 4095 ) { base = emit_adjust_base_to_offset ( base , offset ) ; offset = 0 ; } emit_save_or_restore_regs ( 16 , 32 , base , offset , sparc_leaf_function_p , save_local_or_in_reg_p , action , SORR_ADVANCE ) ; } </s>

Emit code to save/restore call-saved local and in registers .


<s> SDNode * SparcDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return nullptr ; } switch ( N -> getOpcode ( ) ) { default : break ; case SPISD :: GLOBAL_BASE_REG : return getGlobalBaseReg ( ) ; case ISD :: SDIV : case ISD :: UDIV : { if ( N -> getValueType ( 0 ) == MVT :: i64 ) break ; SDValue DivLHS = N -> getOperand ( 0 ) ; SDValue DivRHS = N -> getOperand ( 1 ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == ISD :: SDIV ) { TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: SRAri , dl , MVT :: i32 , DivLHS , CurDAG -> getTargetConstant ( 31 , MVT :: i32 ) ) , 0 ) ; } else { TopPart = CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ; } TopPart = SDValue ( CurDAG -> getMachineNode ( SP :: WRYrr , dl , MVT :: Glue , TopPart , CurDAG -> getRegister ( SP :: G0 , MVT :: i32 ) ) , 0 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: SDIV ? SP :: SDIVrr : SP :: UDIVrr ; return CurDAG -> SelectNodeTo ( N , Opcode , MVT :: i32 , DivLHS , DivRHS , TopPart ) ; } case ISD :: MULHU : case ISD :: MULHS : { SDValue MulLHS = N -> getOperand ( 0 ) ; SDValue MulRHS = N -> getOperand ( 1 ) ; unsigned Opcode = N -> getOpcode ( ) == ISD :: MULHU ? SP :: UMULrr : SP :: SMULrr ; SDNode * Mul = CurDAG -> getMachineNode ( Opcode , dl , MVT :: i32 , MVT :: Glue , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , SP :: RDY , MVT :: i32 , SDValue ( Mul , 1 ) ) ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static bool is_store_insn1 ( rtx pat , rtx * str_mem ) { if ( ! pat || pat == NULL_RTX ) return false ; if ( GET_CODE ( pat ) == SET ) return find_mem_ref ( SET_DEST ( pat ) , str_mem ) ; if ( GET_CODE ( pat ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( is_store_insn1 ( XVECEXP ( pat , 0 , i ) , str_mem ) ) return true ; } return false ; } </s>

Determine if PAT is a PATTERN of a store insn .


<s> bool AMDGPUTargetLowering :: isFAbsFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return VT == MVT :: f32 || VT == MVT :: f64 || ( Subtarget -> has16BitInsts ( ) && VT == MVT :: f16 ) ; } </s>

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation .


<s> bool isVolatile ( const Instruction * Inst ) { if ( auto * LI = dyn_cast < LoadInst > ( Inst ) ) return LI -> isVolatile ( ) ; else if ( auto * SI = dyn_cast < StoreInst > ( Inst ) ) return SI -> isVolatile ( ) ; else if ( auto * AI = dyn_cast < AtomicCmpXchgInst > ( Inst ) ) return AI -> isVolatile ( ) ; return false ; } </s>

Return true if this is a store to a volatile memory location .


" - nope, %%lo(sym)[reg] not splittable\n"

Be careful not to use macros that need to be compiled one way for strict , and another way for not-strict , like REG_OK_FOR_BASE_P .


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : case 'z' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; case 'z' : RC = & AArch64 :: ZPRRegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; bool hasAltName ; const TargetRegisterClass * RegClass ; if ( AArch64 :: ZPRRegClass . contains ( Reg ) ) { RegClass = & AArch64 :: ZPRRegClass ; hasAltName = false ; } else if ( AArch64 :: PPRRegClass . contains ( Reg ) ) { RegClass = & AArch64 :: PPRRegClass ; hasAltName = false ; } else { RegClass = & AArch64 :: FPR128RegClass ; hasAltName = true ; } return printAsmRegInClass ( MO , RegClass , hasAltName , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool RISCVFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const MachineFunction * MF = MBB . getParent ( ) ; const auto * RVFI = MF -> getInfo < RISCVMachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( * MF ) ) return true ; RegScavenger RS ; RS . enterBasicBlock ( * TmpMBB ) ; return ! RS . isRegUsed ( RISCV :: X5 ) ; } </s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> static bool ix86_function_value_regno_p ( const unsigned int regno ) { switch ( regno ) { case AX_REG : return true ; case DX_REG : return ( ! TARGET_64BIT || ix86_cfun_abi ( ) != MS_ABI ) ; case DI_REG : case SI_REG : return TARGET_64BIT && ix86_cfun_abi ( ) != MS_ABI ; case BND0_REG : case BND1_REG : return chkp_function_instrumented_p ( current_function_decl ) ; case ST0_REG : case ST1_REG : if ( TARGET_64BIT && ix86_cfun_abi ( ) == MS_ABI ) return false ; return TARGET_FLOAT_RETURNS_IN_80387 ; case XMM0_REG : case XMM1_REG : return TARGET_SSE ; case MM0_REG : if ( TARGET_MACHO || TARGET_64BIT ) return false ; return TARGET_MMX ; } return false ; } </s>

Return true if N is a possible register number of function value .


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
dbgs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
NumEmitted
++
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> int arc_delay_slots_for_epilogue ( ) { if ( arc_compute_function_type ( current_function_decl ) != ARC_FUNCTION_NORMAL ) return 0 ; if ( ! current_frame_info . initialized ) ( void ) arc_compute_frame_size ( get_frame_size ( ) ) ; if ( current_frame_info . total_size == 0 ) return 1 ; return 0 ; } </s>

Define the number of delay slots needed for the function epilogue . Interrupt handlers ca n't have any epilogue delay slots ( it 's always needed for something else , I think ) . For normal functions , we have to worry about using call-saved regs as they 'll be restored before the delay slot insn . Functions with non-empty frames already have enough choices for the epilogue delay slot so for now we only consider functions with empty frames .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> unsigned ARMTargetLowering :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : return TFI -> hasFP ( MF ) ? 4 : 5 ; case ARM :: GPRRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 10 - FP - ( Subtarget -> isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool cris_base_p ( const_rtx x , bool strict ) { return ( REG_P ( x ) && reg_ok_for_base_p ( x , strict ) ) ; } </s>


<s> unsigned bfin_local_alignment ( tree type , unsigned align ) { if ( TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: gtu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , 8 ) && align < 32 ) return 32 ; return align ; } </s>

Compute the alignment for a local variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this macro is used instead of that alignment to align the object .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static unsigned int rx_function_arg_size ( machine_mode mode , const_tree type ) { unsigned int num_bytes ; num_bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; return rx_round_up ( num_bytes , UNITS_PER_WORD ) ; } </s>

Return the number of bytes in the argument registers occupied by an argument of type TYPE and mode MODE .


<s> static hashval_t mips_hash_base ( rtx base ) { int do_not_record_p ; return hash_rtx ( base , GET_MODE ( base ) , & do_not_record_p , NULL , false ) ; } </s>

Return a hash value for SYMBOL_REF or LABEL_REF BASE .


<s> static void write_fn_proto ( std :: stringstream & s , bool is_defn , const char * name , const_tree decl ) { const char * replacement = nvptx_name_replacement ( name ) ; char * replaced_dots = NULL ; if ( replacement != name ) name = replacement ; else { replaced_dots = nvptx_replace_dot ( name ) ; if ( replaced_dots ) name = replaced_dots ; } if ( name [ 0 ] == '*' ) name ++ ; if ( is_defn ) write_fn_proto_1 ( s , false , name , decl ) ; write_fn_proto_1 ( s , is_defn , name , decl ) ; if ( replaced_dots ) XDELETE ( replaced_dots ) ; } </s>

Write a .func or .kernel declaration or definition along with a helper comment for use by ld . S is the stream to write to , DECL the decl for the function with name NAME . For definitions , emit a declaration too .


<s> void RISCVAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerRISCVMachineInstrToMCInst ( MI , TmpInst , * this ) ; auto * MBB = MI -> getParent ( ) ; auto * RVFI = MI -> getMF ( ) -> getInfo < RISCVMachineFunctionInfo > ( ) ; if ( RVFI -> isHwlpBasicBlock ( MBB ) ) AsmPrinter :: EmitToStreamer ( * OutStreamer , TmpInst ) ; else EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


<s> static rtx aarch64_gen_load_pair ( machine_mode mode , rtx reg1 , rtx mem1 , rtx reg2 , rtx mem2 ) { switch ( mode ) { case E_DImode : return gen_load_pair_dw_didi ( reg1 , mem1 , reg2 , mem2 ) ; case E_DFmode : return gen_load_pair_dw_dfdf ( reg1 , mem1 , reg2 , mem2 ) ; case E_TFmode : return gen_load_pair_dw_tftf ( reg1 , mem1 , reg2 , mem2 ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and regurn a load pair isntruction of mode MODE to load register REG1 from MEM1 and register REG2 from MEM2 .


This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"-mshared-library-id= specified without -mid-shared-library"

Set global variables as needed for the options enabled .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"

This constructor initializes the data members to match that of the specified triple .


<s> static rtx sh_allocate_initial_value ( rtx hard_reg ) { if ( REGNO ( hard_reg ) == PR_REG ) { if ( crtl -> is_leaf && ! sh_pr_n_sets ( ) ) return hard_reg ; else return gen_frame_mem ( Pmode , return_address_pointer_rtx ) ; } return NULL_RTX ; } </s>

Return where to allocate pseudo for a given hard register initial value .


<s> bool i386_pe_valid_dllimport_attribute_p ( const_tree decl ) { if ( TARGET_NOP_FUN_DLLIMPORT && TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; return true ; } </s>

Handle the -mno-fun-dllimport target switch .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static int rid_int128 ( void ) { int i ; for ( i = 0 ; i < NUM_INT_N_ENTS ; i ++ ) if ( int_n_enabled_p [ i ] && int_n_data [ i ] . bitsize == 128 ) return RID_INT_N_0 + i ; return RID_MAX + 1 ; } </s>

Helper function to find out which RID_INT_N_ * code is the one for __int128 , if any . Returns RID_MAX+1 if none apply , which is safe ( for our purposes , since we always expect to have __int128 ) to compare against .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 || ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != X86ISD :: RET_FLAG && UI -> getOpcode ( ) != X86ISD :: CPS_RET ) return false ; if ( UI -> getNumOperands ( ) > 4 ) return false ; if ( UI -> getNumOperands ( ) == 4 && UI -> getOperand ( UI -> getNumOperands ( ) - 1 ) . getValueType ( ) != MVT :: Glue ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


print - Print a debug representation of the operand to the given stream .


<s> const MCExpr * MCS51AsmPrinter :: lowerConstant ( const Constant * CV ) { MCContext & Ctx = OutContext ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { bool IsProgMem = GV -> getAddressSpace ( ) == MCS51 :: ProgramMemory ; if ( IsProgMem ) { const MCExpr * Expr = MCSymbolRefExpr :: create ( getSymbol ( GV ) , Ctx ) ; return MCS51MCExpr :: create ( MCS51MCExpr :: VK_MCS51_PM , Expr , false , Ctx ) ; } } return AsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> static void pa_extra_live_on_entry ( bitmap regs ) { if ( TARGET_64BIT ) bitmap_set_bit ( regs , ARG_POINTER_REGNUM ) ; } </s>

Implement TARGET_EXTRA_LIVE_ON_ENTRY . The argument pointer is only marked as live on entry by df-scan when it is a fixed register . It is n't a fixed register in the 64-bit runtime , so we need to mark it here .


"MIa must load from or modify a memory location"

"MIb must load from or modify a memory location"

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


The label list for the current page freed by linking the list onto the free label element chain .


<s> SDValue NVPTXTargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & ExtraSteps , bool & UseOneConst , bool Reciprocal ) const { if ( ! ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && ! usePrecSqrtF32 ( ) ) ) ) return SDValue ( ) ; if ( ExtraSteps == ReciprocalEstimate :: Unspecified ) ExtraSteps = 0 ; SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; bool Ftz = useF32FTZ ( DAG . getMachineFunction ( ) ) ; auto MakeIntrinsicCall = [ & ] ( Intrinsic :: ID IID ) { return DAG . getNode ( ISD :: INTRINSIC_WO_CHAIN , DL , VT , DAG . getConstant ( IID , DL , MVT :: i32 ) , Operand ) ; } ; if ( Reciprocal || ExtraSteps > 0 ) { if ( VT == MVT :: f32 ) return MakeIntrinsicCall ( Ftz ? Intrinsic :: nvvm_rsqrt_approx_ftz_f : Intrinsic :: nvvm_rsqrt_approx_f ) ; else if ( VT == MVT :: f64 ) return MakeIntrinsicCall ( Intrinsic :: nvvm_rsqrt_approx_d ) ; else return SDValue ( ) ; } else { if ( VT == MVT :: f32 ) return MakeIntrinsicCall ( Ftz ? Intrinsic :: nvvm_sqrt_approx_ftz_f : Intrinsic :: nvvm_sqrt_approx_f ) ; else { return DAG . getNode ( ISD :: INTRINSIC_WO_CHAIN , DL , VT , DAG . getConstant ( Intrinsic :: nvvm_rcp_approx_ftz_d , DL , MVT :: i32 ) , MakeIntrinsicCall ( Intrinsic :: nvvm_rsqrt_approx_d ) ) ; } } } </s>

Hooks for building estimates in place of slower divisions and square roots .


<s> const CAHPMCExpr * CAHPMCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) CAHPMCExpr ( Expr , Kind ) ; } </s>


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Um
:
case
InlineAsm
::
Constraint_Un
:
case
InlineAsm
::
Constraint_Uq
:
case
InlineAsm
::
Constraint_Us
:
case
InlineAsm
::
Constraint_Ut
:
case
InlineAsm
::
Constraint_Uv
:
case
InlineAsm
::
Constraint_Uy
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

ARM
ARM
"Unexpected asm memory constraint"


<s> int fldi_ok ( ) { return ! TARGET_SH4 || TARGET_FMOVD || reload_completed ; } </s>

For -m4 and -m4-single-only , mode switching is used . If we are compiling without -mfmovd , movsf_ie is n't taken into account for mode switching . We could check in machine_dependent_reorg for cases where we know we are in single precision mode , but there is interface to find that out during reload , so we must avoid choosing an fldi alternative during reload and thus failing to allocate a scratch register for the constant loading .


<s> TargetPassConfig * X86TargetMachine :: createPassConfig ( PassManagerBase & PM ) { X86PassConfig * PC = new X86PassConfig ( this , PM ) ; if ( Subtarget . hasCMov ( ) ) PC -> enablePass ( & EarlyIfConverterID ) ; return PC ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> const AMDGPUCommonSubtarget & AMDGPUCommonSubtarget :: get ( const TargetMachine & TM , const Function & F ) { if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) return static_cast < const AMDGPUCommonSubtarget & > ( TM . getSubtarget < AMDGPUSubtarget > ( F ) ) ; else return static_cast < const AMDGPUCommonSubtarget & > ( TM . getSubtarget < R600Subtarget > ( F ) ) ; } </s>

Get the generated Value for a given VPValue and given Part and Lane .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU R600


<s> void AlphaRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( TFI -> hasFP ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; MachineInstr * New ; if ( Old -> getOpcode ( ) == Alpha :: ADJUSTSTACKDOWN ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Alpha :: LDA ) , Alpha :: R30 ) . addImm ( - Amount ) . addReg ( Alpha :: R30 ) ; } else { assert ( Old -> getOpcode ( ) == Alpha :: ADJUSTSTACKUP ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Alpha :: LDA ) , Alpha :: R30 ) . addImm ( Amount ) . addReg ( Alpha :: R30 ) ; } MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : if ( VT == MVT :: i32 ) return std :: make_pair ( 0U , SystemZ :: GR32RegisterClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , SystemZ :: GR128RegisterClass ) ; return std :: make_pair ( 0U , SystemZ :: GR64RegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static void aarch64_emit_atomic_swap ( machine_mode mode , rtx dst , rtx value , rtx mem , rtx model ) { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case E_QImode : gen = gen_aarch64_atomic_swpqi ; break ; case E_HImode : gen = gen_aarch64_atomic_swphi ; break ; case E_SImode : gen = gen_aarch64_atomic_swpsi ; break ; case E_DImode : gen = gen_aarch64_atomic_swpdi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , mem , value , model ) ) ; } </s>


<s> bool hasFP ( const MachineFunction & ) const override { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


"VIDEOCORE DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . addRequired < LiveIntervals > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


Implement TARGET_BUILD_BUILTIN_VA_LIST . Return the type to use as __builtin_va_list . AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as : struct __va_list { void * __stack ; void * __gr_top ; void * __vr_top ; int __gr_offs ; int __vr_offs ; } ;


<s> bool SNESTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; const SDNode * Op ; SDLoc DL ( N ) ; if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Op = LD -> getBasePtr ( ) . getNode ( ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; if ( SNES :: isProgramMemoryAccess ( LD ) ) { return false ; } } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Op = ST -> getBasePtr ( ) . getNode ( ) ; if ( SNES :: isProgramMemoryAccess ( ST ) ) { return false ; } } else { return false ; } if ( VT != MVT :: i8 && VT != MVT :: i16 ) { return false ; } if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == ISD :: SUB ) RHSC = - RHSC ; if ( ( VT == MVT :: i16 && RHSC != - 2 ) || ( VT == MVT :: i8 && RHSC != - 1 ) ) { return false ; } Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , DL , MVT :: i8 ) ; AM = ISD :: PRE_DEC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < SlotIndexes > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; dup = gen_rtx_VEC_DUPLICATE ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( target , dup ) ) ; if ( recog_memoized ( insn ) < 0 ) { rtx_insn * seq ; start_sequence ( ) ; XEXP ( dup , 0 ) = force_reg ( GET_MODE_INNER ( mode ) , val ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >= 0 ; gcc_assert ( ok ) ; } return true ; } </s>

A subroutine of ix86_expand_vector_init_duplicate . Tries to fill target with val via vec_duplicate .


<s> std :: pair < unsigned , unsigned > AMDGPUSubtarget :: getWavesPerEU ( const Function & F ) const { std :: pair < unsigned , unsigned > Default ( 1 , getMaxWavesPerEU ( ) ) ; std :: pair < unsigned , unsigned > FlatWorkGroupSizes = getFlatWorkGroupSizes ( F ) ; unsigned MinImpliedByFlatWorkGroupSize = getMaxWavesPerEU ( FlatWorkGroupSizes . second ) ; bool RequestedFlatWorkGroupSize = false ; if ( F . hasFnAttribute ( "amdgpu-max-work-group-size" ) || F . hasFnAttribute ( "amdgpu-flat-work-group-size" ) ) { Default . first = MinImpliedByFlatWorkGroupSize ; RequestedFlatWorkGroupSize = true ; } std :: pair < unsigned , unsigned > Requested = AMDGPU :: getIntegerPairAttribute ( F , "amdgpu-waves-per-eu" , Default , true ) ; if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . first > getMaxWavesPerEU ( ) ) return Default ; if ( Requested . second > getMaxWavesPerEU ( ) ) return Default ; if ( RequestedFlatWorkGroupSize && Requested . first > MinImpliedByFlatWorkGroupSize ) return Default ; return Requested ; } </s>

Overload which uses the specified values for the flat work group sizes , rather than querying the function itself .

AMDGPU AMDGPU 1 "amdgpu-max-work-group-size" "amdgpu-flat-work-group-size" AMDGPU::getIntegerPairAttribute "amdgpu-waves-per-eu"


<s>
bool
ARMTargetLowering
::
canCombineStoreAndExtract
(
Type
*
VectorTy
,
Value
*
Idx
,
unsigned
&
Cost
)
const
{
if
(
!
Subtarget
->
hasNEON
(
)
)
return
false
;
if
(
VectorTy
->
isFPOrFPVectorTy
(
)
)
return
false
;
if
(
!
isa
<
ConstantInt
>
(
Idx
)
)
return
false
;
assert
(
VectorTy
->
isVectorTy
(
)
&&
"VectorTy is not a vector type"
)
;
unsigned
BitWidth
=
VectorTy
->
getPrimitiveSizeInBits
(
)
.
getFixedSize
(
)
;
if
(
BitWidth
==
64
||
BitWidth
==
128
)
{
Cost
=
0
;
return
true
;
}
return
false
;
}
</s>

Return true if the target can combine store ( extractelement VectorTy , Idx ) .


<s> int ix86_data_alignment ( tree type , int align , bool opt ) { int max_align_compat = MIN ( 256 , MAX_OFILE_ALIGNMENT ) ; int max_align = MIN ( ( unsigned ) ix86_tune_cost -> prefetch_block * 8 , MAX_OFILE_ALIGNMENT ) ; if ( max_align < BITS_PER_WORD ) max_align = BITS_PER_WORD ; switch ( ix86_align_data_type ) { case ix86_align_data_type_abi : opt = false ; break ; case ix86_align_data_type_compat : max_align = BITS_PER_WORD ; break ; case ix86_align_data_type_cacheline : break ; } if ( TARGET_IAMCU ) align = iamcu_alignment ( type , align ) ; if ( opt && AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) { if ( wi :: geu_p ( TYPE_SIZE ( type ) , max_align_compat ) && align < max_align_compat ) align = max_align_compat ; if ( wi :: geu_p ( TYPE_SIZE ( type ) , max_align ) && align < max_align ) align = max_align ; } if ( TARGET_64BIT ) { if ( ( opt ? AGGREGATE_TYPE_P ( type ) : TREE_CODE ( type ) == ARRAY_TYPE ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , 128 ) && align < 128 ) return 128 ; } if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a static variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { bool Vector = ( ClassID == 1 ) ; if ( Vector ) { if ( ST -> hasNEON ( ) ) return 16 ; if ( ST -> hasMVEIntegerOps ( ) ) return 8 ; return 0 ; } if ( ST -> isThumb1Only ( ) ) return 8 ; return 13 ; } </s>


<s> static void nios2_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type , int * pretend_size , int second_time ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; cumulative_args_t local_cum_v = pack_cumulative_args ( & local_cum ) ; int regs_to_push ; int pret_size ; cfun -> machine -> uses_anonymous_args = 1 ; local_cum = * cum ; nios2_function_arg_advance ( local_cum_v , mode , type , true ) ; regs_to_push = NUM_ARG_REGS - local_cum . regs_used ; if ( ! TARGET_HAS_CDX && ! second_time && regs_to_push > 0 ) { rtx ptr = virtual_incoming_args_rtx ; rtx mem = gen_rtx_MEM ( BLKmode , ptr ) ; emit_insn ( gen_blockage ( ) ) ; move_block_from_reg ( local_cum . regs_used + FIRST_ARG_REGNO , mem , regs_to_push ) ; emit_insn ( gen_blockage ( ) ) ; } pret_size = regs_to_push * UNITS_PER_WORD ; if ( pret_size ) * pretend_size = pret_size ; } </s>

TODO : It may be possible to eliminate the copyback and implement own va_arg type .


<s> TargetPassConfig * TeakTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TeakPassConfig ( * this , PM ) ; } </s>


<s>
static
void
AnalyzeArguments
(
CCState
&
State
,
SmallVectorImpl
<
CCValAssign
>
&
ArgLocs
,
const
SmallVectorImpl
<
ArgT
>
&
Args
)
{
static
const
MCPhysReg
RegList
[
]
=
{
CJG
::
R24
,
CJG
::
R25
,
CJG
::
R26
,
CJG
::
R27
,
CJG
::
R28
,
CJG
::
R29
,
CJG
::
R30
,
CJG
::
R31
}
;
static
const
unsigned
NbRegs
=
array_lengthof
(
RegList
)
;
if
(
State
.
isVarArg
(
)
)
{
llvm_unreachable
(
"Cannot support var args"
)
;
}
SmallVector
<
unsigned
,
4
>
ArgsParts
;
ParseFunctionArgs
(
Args
,
ArgsParts
)
;
unsigned
RegsLeft
=
NbRegs
;
bool
UseStack
=
false
;
unsigned
ValNo
=
0
;
for
(
unsigned
i
=
0
,
e
=
ArgsParts
.
size
(
)
;
i
!=
e
;
i
++
)
{
MVT
ArgVT
=
Args
[
ValNo
]
.
VT
;
ISD
::
ArgFlagsTy
ArgFlags
=
Args
[
ValNo
]
.
Flags
;
MVT
LocVT
=
ArgVT
;
CCValAssign
::
LocInfo
LocInfo
=
CCValAssign
::
Full
;
if
(
ArgFlags
.
isByVal
(
)
)
{
State
.
HandleByVal
(
ValNo
++
,
ArgVT
,
LocVT
,
LocInfo
,
4
,
4
,
ArgFlags
)
;
continue
;
}
unsigned
Parts
=
ArgsParts
[
i
]
;
if
(
!
UseStack
&&
Parts
<=
RegsLeft
)
{
unsigned
FirstVal
=
ValNo
;
for
(
unsigned
j
=
0
;
j
<
Parts
;
j
++
)
{
unsigned
Reg
=
State
.
AllocateReg
(
RegList
)
;
State
.
addLoc
(
CCValAssign
::
getReg
(
ValNo
++
,
ArgVT
,
Reg
,
LocVT
,
LocInfo
)
)
;
RegsLeft
;
}
SmallVectorImpl
<
CCValAssign
>
::
iterator
B
=
ArgLocs
.
begin
(
)
+
FirstVal
;
std
::
reverse
(
B
,
B
+
Parts
)
;
}
else
{
UseStack
=
true
;
for
(
unsigned
j
=
0
;
j
<
Parts
;
j
++
)
CC_CJG
(
ValNo
++
,
ArgVT
,
LocVT
,
LocInfo
,
ArgFlags
,
State
)
;
}
}
}
</s>

The function will invoke AnalyzeCallOperands .


<s> int HexagonInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { auto & RI = getRegisterInfo ( ) ; MachineOperand DefMO = DefMI . getOperand ( DefIdx ) ; if ( RI . isPhysicalRegister ( DefMO . getReg ( ) ) ) { if ( DefMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( DefMO . getReg ( ) , & RI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & RI ) ; if ( Idx != - 1 ) { DefIdx = Idx ; break ; } } } MachineOperand UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & RI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & RI ) ; if ( Idx != - 1 ) { UseIdx = Idx ; break ; } } } } return TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; } </s>

Compute and return the use operand latency of a given pair of def and use .


"Unrecognized Hexagon processor version"

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static void or1k_output_mi_thunk ( FILE * file , tree thunk_fndecl , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; rtx this_rtx , funexp ; rtx_insn * insn ; reload_completed = 1 ; epilogue_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , 4 ) ; else this_rtx = gen_rtx_REG ( Pmode , 3 ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; if ( ! satisfies_constraint_I ( delta_rtx ) ) { rtx scratch = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; emit_move_insn ( scratch , delta_rtx ) ; delta_rtx = scratch ; } emit_insn ( gen_add2_insn ( this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx scratch = gen_rtx_REG ( Pmode , PE_TMP_REGNUM ) ; HOST_WIDE_INT lo = sext_hwi ( vcall_offset , 16 ) ; HOST_WIDE_INT hi = vcall_offset - lo ; rtx tmp ; tmp = gen_rtx_MEM ( Pmode , this_rtx ) ; emit_move_insn ( scratch , tmp ) ; if ( hi != 0 ) { rtx scratch2 = gen_rtx_REG ( Pmode , RV_REGNUM ) ; emit_move_insn ( scratch2 , GEN_INT ( hi ) ) ; emit_insn ( gen_add2_insn ( scratch , scratch2 ) ) ; } tmp = plus_constant ( Pmode , scratch , lo ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; emit_move_insn ( scratch , tmp ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; gcc_assert ( SYMBOL_REF_LOCAL_P ( funexp ) ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; emit_barrier ( ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk_fndecl , fnname ) ; reload_completed = 0 ; epilogue_completed = 0 ; } </s>

Worker for TARGET_ASM_OUTPUT_MI_THUNK . Output the assembler code for a thunk function . THUNK_DECL is the declaration for the thunk function itself , FUNCTION is the decl for the target function . DELTA is an immediate constant offset to be added to THIS . If VCALL_OFFSET is nonzero , the word at address ( * THIS + VCALL_OFFSET ) should be additionally added to THIS .


<s> static bool spu_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V4SFmode : case E_V2DFmode : return true ; default : return false ; } } </s>

Similarly for vector modes . `` Supported '' here is less strict . At least some operations are supported ; need to check optabs or builtins for further details .


<s> static bool mn10300_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == MODE_FLOAT && GET_MODE_CLASS ( mode2 ) != MODE_FLOAT ) return false ; if ( GET_MODE_CLASS ( mode2 ) == MODE_FLOAT && GET_MODE_CLASS ( mode1 ) != MODE_FLOAT ) return false ; if ( TARGET_AM33 || mode1 == mode2 || ( GET_MODE_SIZE ( mode1 ) <= 4 && GET_MODE_SIZE ( mode2 ) <= 4 ) ) return true ; return false ; } </s>


<s> bool SystemZTTIImpl :: isLSRCostLess ( const TargetTransformInfo :: LSRCost & C1 , const TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . SetupCost ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s>
bool
PPCTargetLowering
::
enableAggressiveFMAFusion
(
EVT
VT
)
const
{
assert
(
VT
.
isFloatingPoint
(
)
&&
"Non-floating-point FMA?"
)
;
return
true
;
}
</s>

Return true if target always benefits from combining into FMA for a given value type .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > 128 ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: LLSC ; if ( Subtarget -> hasLSE ( ) && Size < 128 ) return AtomicExpansionKind :: None ; if ( Subtarget -> outlineAtomics ( ) && Size < 128 ) { if ( AI -> getOperation ( ) != AtomicRMWInst :: Min && AI -> getOperation ( ) != AtomicRMWInst :: Max && AI -> getOperation ( ) != AtomicRMWInst :: UMin && AI -> getOperation ( ) != AtomicRMWInst :: UMax ) { return AtomicExpansionKind :: None ; } } return AtomicExpansionKind :: LLSC ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> bool RISCVAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool ARM64RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static const char * m68k_get_reloc_decoration ( enum m68k_reloc reloc ) { gcc_assert ( MOTOROLA || reloc == RELOC_GOT ) ; switch ( reloc ) { case RELOC_GOT : if ( MOTOROLA ) { if ( flag_pic == 1 && TARGET_68020 ) return "@GOT.w" ; else return "@GOT" ; } else { if ( TARGET_68020 ) { switch ( flag_pic ) { case 1 : return ":w" ; case 2 : return ":l" ; default : return "" ; } } } case RELOC_TLSGD : return "@TLSGD" ; case RELOC_TLSLDM : return "@TLSLDM" ; case RELOC_TLSLDO : return "@TLSLDO" ; case RELOC_TLSIE : return "@TLSIE" ; case RELOC_TLSLE : return "@TLSLE" ; default : gcc_unreachable ( ) ; } } </s>

Return string for TLS relocation RELOC .


<s> bool MSP430FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MSP430MachineFunctionInfo * MFI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( const CalleeSavedInfo & I : llvm :: reverse ( CSI ) ) { Register Reg = I . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( MSP430 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> AArch64Subtarget :: AArch64Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , IsLittleEndian ( LittleEndian ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; ParseSubtargetFeatures ( CPUString , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static bool s390_function_ok_for_sibcall ( tree decl , tree exp ) { if ( TARGET_TPF_PROFILING ) return false ; if ( ! TARGET_64BIT && flag_pic && decl && TREE_PUBLIC ( decl ) ) return false ; if ( TREE_OPERAND ( exp , 1 ) && s390_call_saved_register_used ( TREE_OPERAND ( exp , 1 ) ) ) return false ; return true ; } </s>

Return true if the given call expression can be turned into a sibling call . DECL holds the declaration of the function to be called whereas EXP is the call expression itself .


<s>
const
char
*
output_call
(
rtx
*
operands
)
{
gcc_assert
(
!
arm_arch5t
)
;
if
(
REGNO
(
operands
[
0
]
)
==
LR_REGNUM
)
{
operands
[
0
]
=
gen_rtx_REG
(
SImode
,
IP_REGNUM
)
;
output_asm_insn
(
"mov%?\t%0, %|lr"
,
operands
)
;
}
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
if
(
TARGET_INTERWORK
||
arm_arch4t
)
output_asm_insn
(
"bx%?\t%0"
,
operands
)
;
else
output_asm_insn
(
"mov%?\t%|pc, %0"
,
operands
)
;
return
""
;
}
</s>

INSN is either a function call or a millicode call . It may have an unconditional jump in its delay slot . CALL_DEST is the routine we are calling .


<s> static void riscv_disqualify_components ( sbitmap , edge , sbitmap , bool ) { } </s>


<s> void AArch64CondBrTuning :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool ARMTargetLowering :: isLegalInterleavedAccessType ( VectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( VecTy -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 ) return false ; return VecSize == 64 || VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s>
void
avr_final_prescan_insn
(
rtx_insn
*
insn
,
rtx
*
operand
ATTRIBUTE_UNUSED
,
int
num_operands
ATTRIBUTE_UNUSED
)
{
if
(
avr_log
.
rtx_costs
)
{
rtx
set
=
single_set
(
insn
)
;
if
(
set
)
fprintf
(
asm_out_file
,
"/* DEBUG: cost = %d.  */\n"
,
set_src_cost
(
SET_SRC
(
set
)
,
GET_MODE
(
SET_DEST
(
set
)
)
,
optimize_insn_for_speed_p
(
)
)
)
;
else
fprintf
(
asm_out_file
,
"/* DEBUG: pattern-cost = %d.  */\n"
,
rtx_cost
(
PATTERN
(
insn
)
,
VOIDmode
,
INSN
,
0
,
optimize_insn_for_speed_p
(
)
)
)
;
}
if
(
avr_log
.
insn_addresses
)
fprintf
(
asm_out_file
,
";; ADDR = %d\n"
,
(
int
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
}
</s>

avr
"/* DEBUG: cost = %d.  */\n"
"/* DEBUG: pattern-cost = %d.  */\n"
0
";; ADDR = %d\n"


<s>
bool
Z80old
::
splitReg
(
unsigned
ByteSize
,
unsigned
Opc8
,
unsigned
&
RC
,
unsigned
&
LoOpc
,
unsigned
&
LoIdx
,
unsigned
&
HiOpc
,
unsigned
&
HiIdx
,
unsigned
&
HiOff
)
{
switch
(
ByteSize
)
{
default
:
llvm_unreachable
(
"Unexpected Size!"
)
;
case
1
:
RC
=
Z80old
::
RR8RegClassID
;
LoOpc
=
HiOpc
=
Opc8
;
LoIdx
=
HiIdx
=
Z80old
::
NoSubRegister
;
HiOff
=
0
;
return
false
;
case
2
:
RC
=
Z80old
::
R16RegClassID
;
LoOpc
=
HiOpc
=
Opc8
;
LoIdx
=
Z80old
::
sub_low
;
HiIdx
=
Z80old
::
sub_high
;
HiOff
=
1
;
return
true
;
}
}
</s>

Splits a 16-bit DREGS register into the lo/hi register pair .


<s>
bool
AArch64InstrInfo
::
isGPRZero
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
MOVZWi
:
case
AArch64
::
MOVZXi
:
if
(
MI
.
getOperand
(
1
)
.
isImm
(
)
&&
MI
.
getOperand
(
1
)
.
getImm
(
)
==
0
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
.
getOperand
(
2
)
.
getImm
(
)
==
0
&&
"invalid MOVZi operands"
)
;
return
true
;
}
break
;
case
AArch64
::
ANDWri
:
return
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
;
case
AArch64
::
ANDXri
:
return
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
XZR
;
case
TargetOpcode
::
COPY
:
return
MI
.
getOperand
(
1
)
.
getReg
(
)
==
AArch64
::
WZR
;
}
return
false
;
}
</s>

Does this instruction set its full destination register to zero ?


<s> bool NVPTXLowerAlloca :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; bool Changed = false ; for ( auto & BB : F ) for ( auto & I : BB ) { if ( auto allocaInst = dyn_cast < AllocaInst > ( & I ) ) { Changed = true ; auto ETy = allocaInst -> getAllocatedType ( ) ; auto LocalAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_LOCAL ) ; auto NewASCToLocal = new AddrSpaceCastInst ( allocaInst , LocalAddrTy , "" ) ; auto GenericAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_GENERIC ) ; auto NewASCToGeneric = new AddrSpaceCastInst ( NewASCToLocal , GenericAddrTy , "" ) ; NewASCToLocal -> insertAfter ( allocaInst ) ; NewASCToGeneric -> insertAfter ( NewASCToLocal ) ; for ( Use & AllocaUse : llvm :: make_early_inc_range ( allocaInst -> uses ( ) ) ) { auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto GI = dyn_cast < GetElementPtrInst > ( AllocaUse . getUser ( ) ) ; if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto BI = dyn_cast < BitCastInst > ( AllocaUse . getUser ( ) ) ; if ( BI && BI -> getOperand ( 0 ) == allocaInst ) { BI -> setOperand ( 0 , NewASCToGeneric ) ; continue ; } } } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
Win64
)
return
CSR_AArch64_AAPCS_X18_SaveList
;
if
(
hasSVEArgsOrReturn
(
MF
)
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Parsed as: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
return
true
;
}
{
bool
wasInITBlock
=
inITBlock
(
)
;
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
LLVM_DEBUG
(
dbgs
(
)
<<
"Changed to: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
wasInITBlock
&&
hasV8Ops
(
)
&&
isThumb
(
)
&&
!
isV8EligibleForIT
(
&
Inst
)
&&
!
getTargetOptions
(
)
.
MCNoDeprecatedWarn
)
{
Warning
(
IDLoc
,
"deprecated instruction in IT block"
)
;
}
}
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
emitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

ARM
ARM
4
"Parsed as: "
"\n"
"Changed to: "
"\n"
"deprecated instruction in IT block"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s> bool arc_store_addr_hazard_p ( rtx_insn * producer , rtx_insn * consumer ) { if ( TARGET_ARC700 && ( arc_tune != ARC_TUNE_ARC7XX ) ) return true ; return arc_store_addr_hazard_internal_p ( producer , consumer ) ; } </s>

Return true if a load instruction ( CONSUMER ) uses the same address as a store instruction ( PRODUCER ) . This function is used to avoid st/ld address hazard in ARC700 cores .


<s> static bool legitimate_small_data_address_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : return legitimate_small_data_address_p ( XEXP ( x , 0 ) ) ; case SYMBOL_REF : return SYMBOL_REF_SMALL_P ( x ) ; case PLUS : { bool p0 = ( GET_CODE ( XEXP ( x , 0 ) ) == SYMBOL_REF ) && SYMBOL_REF_SMALL_P ( XEXP ( x , 0 ) ) ; bool p1 = CONST_INT_P ( XEXP ( x , 1 ) ) && ( INTVAL ( XEXP ( x , 1 ) ) <= g_switch_value ) ; return p0 && p1 ; } default : return false ; } } </s>

Return true if x is ok to be used as a small data address .


<s>
bool
scalar_chain
::
build
(
bitmap
candidates
,
unsigned
insn_uid
,
bitmap
disallowed
)
{
queue
=
BITMAP_ALLOC
(
)
;
bitmap_set_bit
(
queue
,
insn_uid
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Building chain #%d...\n"
,
chain_id
)
;
while
(
!
bitmap_empty_p
(
queue
)
)
{
insn_uid
=
bitmap_first_set_bit
(
queue
)
;
bitmap_clear_bit
(
queue
,
insn_uid
)
;
bitmap_clear_bit
(
candidates
,
insn_uid
)
;
if
(
!
add_insn
(
candidates
,
insn_uid
,
disallowed
)
)
{
bitmap_ior_into
(
disallowed
,
insns
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Aborted chain #%d discovery\n"
,
chain_id
)
;
BITMAP_FREE
(
queue
)
;
return
false
;
}
}
if
(
dump_file
)
{
fprintf
(
dump_file
,
"Collected chain #%d...\n"
,
chain_id
)
;
fprintf
(
dump_file
,
"  insns: "
)
;
dump_bitmap
(
dump_file
,
insns
)
;
if
(
!
bitmap_empty_p
(
defs_conv
)
)
{
bitmap_iterator
bi
;
unsigned
id
;
const
char
*
comma
=
""
;
fprintf
(
dump_file
,
"  defs to convert: "
)
;
EXECUTE_IF_SET_IN_BITMAP
(
defs_conv
,
0
,
id
,
bi
)
{
fprintf
(
dump_file
,
"%sr%d"
,
comma
,
id
)
;
comma
=
", "
;
}
fprintf
(
dump_file
,
"\n"
)
;
}
}
BITMAP_FREE
(
queue
)
;
return
true
;
}
</s>

Build new chain starting from insn INSN_UID recursively adding all dependent uses and definitions . Return true if OK , false if the chain discovery was aborted .

i386
"Building chain #%d...\n"
"Aborted chain #%d discovery\n"
"Collected chain #%d...\n"
"  insns: "
""
"  defs to convert: "
0
"%sr%d"
", "
"\n"


<s> static bool m32r_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { if ( GET_CODE ( addr ) == LO_SUM ) return true ; return false ; } </s>

Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P .


<s> static void ix86_pad_short_function ( void ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) { rtx_insn * ret = BB_END ( e -> src ) ; if ( JUMP_P ( ret ) && ANY_RETURN_P ( PATTERN ( ret ) ) ) { int insn_count = ix86_count_insn ( e -> src ) ; if ( insn_count < 4 ) { rtx_insn * insn = ret ; while ( insn && ( ! NOTE_P ( insn ) || NOTE_KIND ( insn ) != NOTE_INSN_EPILOGUE_BEG ) ) insn = PREV_INSN ( insn ) ; if ( ! insn ) insn = ret ; insn_count = 2 * ( 4 - insn_count ) ; emit_insn_before ( gen_nops ( GEN_INT ( insn_count ) ) , insn ) ; } } } } </s>


<s> void SparcAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case TargetOpcode :: DBG_VALUE : return ; case SP :: GETPCX : LowerGETPCXAndEmitMCInsts ( MI , getSubtargetInfo ( ) ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ; LowerSparcMachineInstrToMCInst ( I , TmpInst , * this ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
bool
PatmosInstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
assert
(
AllowModify
||
(
TBB
==
0
&&
FBB
==
0
&&
Cond
.
size
(
)
==
0
)
)
;
auto
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
||
I
->
isPseudo
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
||
I
->
isIndirectBranch
(
)
)
return
true
;
if
(
!
isPredicated
(
*
I
)
)
{
if
(
!
I
->
isUnconditionalBranch
(
)
)
fixOpcodeForGuard
(
*
I
)
;
TBB
=
getBranchTarget
(
&
*
I
)
;
if
(
AllowModify
)
{
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
}
continue
;
}
if
(
isPredicated
(
*
I
)
)
{
if
(
!
I
->
isConditionalBranch
(
)
)
fixOpcodeForGuard
(
*
I
)
;
if
(
Cond
.
size
(
)
>
0
)
return
true
;
int
i
=
I
->
findFirstPredOperandIdx
(
)
;
assert
(
i
!=
1
)
;
Cond
.
push_back
(
I
->
getOperand
(
i
)
)
;
Cond
.
push_back
(
I
->
getOperand
(
i
+
1
)
)
;
if
(
TBB
)
FBB
=
TBB
;
TBB
=
getBranchTarget
(
&
*
I
)
;
continue
;
}
llvm_unreachable
(
"AnalyzeBranch error."
)
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static void frame_related_constant_load ( rtx reg , HOST_WIDE_INT constant , bool related ) { rtx insn ; rtx cst = GEN_INT ( constant ) ; if ( constant >= - 32768 && constant < 65536 ) insn = emit_move_insn ( reg , cst ) ; else { insn = emit_insn ( gen_movsi_high ( reg , cst ) ) ; if ( related ) RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_movsi_low ( reg , reg , cst ) ) ; } if ( related ) RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Emit code to load a constant CONSTANT into register REG ; setting RTX_FRAME_RELATED_P on all insns we generate if RELATED is true . Make sure that the insns we generate need not be split .


"function_arg_pass_by_reference: V4 long double\n"

"non-standard ABI extension with no compatibility guarantee"

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s> tree resolve_overloaded_builtin ( location_t location , unsigned int code , vec < tree , va_gc > * arglist ) { if ( code >= vec_safe_length ( registered_functions ) ) return NULL_TREE ; registered_function & rfn = * ( * registered_functions ) [ code ] ; if ( rfn . overloaded_p ) return function_resolver ( location , rfn . instance , rfn . decl , * arglist ) . resolve ( ) ; return NULL_TREE ; } </s>

If we 're implementing manual overloading , check whether the SVE function with subcode CODE is overloaded , and if so attempt to determine the corresponding non-overloaded function . The call occurs at location LOCATION and has the arguments given by ARGLIST . If the call is erroneous , report an appropriate error and return error_mark_node . Otherwise , if the function is overloaded , return the decl of the non-overloaded function . Return NULL_TREE otherwise , indicating that the call should be processed in the normal way .


<s> const SystemZSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static void rs6000_emit_dot_insn ( rtx dst , rtx src , int dot , rtx ccreg ) { if ( dot == 0 ) { emit_move_insn ( dst , src ) ; return ; } if ( cc_reg_not_cr0_operand ( ccreg , CCmode ) ) { emit_move_insn ( dst , src ) ; emit_move_insn ( ccreg , gen_rtx_COMPARE ( CCmode , dst , const0_rtx ) ) ; return ; } rtx ccset = gen_rtx_SET ( ccreg , gen_rtx_COMPARE ( CCmode , src , const0_rtx ) ) ; if ( dot == 1 ) { rtx clobber = gen_rtx_CLOBBER ( VOIDmode , dst ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , ccset , clobber ) ) ) ; } else { rtx set = gen_rtx_SET ( dst , src ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , ccset , set ) ) ) ; } } </s>

Emit a potentially record-form instruction , setting DST from SRC . If DOT is 0 , that is all ; otherwise , set CCREG to the result of the signed comparison of DST with zero . If DOT is 1 , the generated RTL does n't care about the DST result ; if DOT is 2 , it does . If CCREG is CR0 do a single dot insn ( as a PARALLEL ) ; otherwise , do a SET and a separate COMPARE .


<s>
void
NVPTXAsmPrinter
::
emitHeader
(
Module
&
M
,
raw_ostream
&
O
,
const
NVPTXSubtarget
&
STI
)
{
O
<<
"//\n"
;
O
<<
"// Generated by LLVM NVPTX Back-End\n"
;
O
<<
"//\n"
;
O
<<
"\n"
;
unsigned
PTXVersion
=
STI
.
getPTXVersion
(
)
;
O
<<
".version "
<<
(
PTXVersion
/
10
)
<<
"."
<<
(
PTXVersion
%
10
)
<<
"\n"
;
O
<<
".target "
;
O
<<
STI
.
getTargetName
(
)
;
const
NVPTXTargetMachine
&
NTM
=
static_cast
<
const
NVPTXTargetMachine
&
>
(
TM
)
;
if
(
NTM
.
getDrvInterface
(
)
==
NVPTX
::
NVCL
)
O
<<
", texmode_independent"
;
bool
HasFullDebugInfo
=
false
;
for
(
DICompileUnit
*
CU
:
M
.
debug_compile_units
(
)
)
{
switch
(
CU
->
getEmissionKind
(
)
)
{
case
DICompileUnit
::
NoDebug
:
case
DICompileUnit
::
DebugDirectivesOnly
:
break
;
case
DICompileUnit
::
LineTablesOnly
:
case
DICompileUnit
::
FullDebug
:
HasFullDebugInfo
=
true
;
break
;
}
if
(
HasFullDebugInfo
)
break
;
}
if
(
MMI
&&
MMI
->
hasDebugInfo
(
)
&&
HasFullDebugInfo
)
O
<<
", debug"
;
O
<<
"\n"
;
O
<<
".address_size "
;
if
(
NTM
.
is64Bit
(
)
)
O
<<
"64"
;
else
O
<<
"32"
;
O
<<
"\n"
;
O
<<
"\n"
;
}
</s>

Emit the header for this unit , not including the initial length field .

NVPTX
NVPTX
NVPTX
"//\n"
"// Generated by LLVM NVPTX Back-End\n"
"//\n"
"\n"
".version "
10
"."
10
"\n"
".target "
NVPTX
NVPTX
NVPTX::NVCL
", texmode_independent"
", debug"
"\n"
".address_size "
"64"
"32"
"\n"
"\n"


"Unable to create a unique discriminator "

"for instruction with memory operand in: "

". This is likely due to a large macro expansion. \n"

"New discriminator shouldn't be present in set"

runOnMachineFunction - Emit the function body .


<s> void aarch64_expand_call ( rtx result , rtx mem , bool sibcall ) { rtx call , callee , tmp ; rtvec vec ; machine_mode mode ; gcc_assert ( MEM_P ( mem ) ) ; callee = XEXP ( mem , 0 ) ; mode = GET_MODE ( callee ) ; gcc_assert ( mode == Pmode ) ; if ( SYMBOL_REF_P ( callee ) ? ( aarch64_is_long_call_p ( callee ) || aarch64_is_noplt_call_p ( callee ) ) : ! REG_P ( callee ) ) XEXP ( mem , 0 ) = force_reg ( mode , callee ) ; call = gen_rtx_CALL ( VOIDmode , mem , const0_rtx ) ; if ( result != NULL_RTX ) call = gen_rtx_SET ( result , call ) ; if ( sibcall ) tmp = ret_rtx ; else tmp = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNUM ) ) ; vec = gen_rtvec ( 2 , call , tmp ) ; call = gen_rtx_PARALLEL ( VOIDmode , vec ) ; aarch64_emit_call_insn ( call ) ; } </s>

This function is used by the call expanders of the machine description . RESULT is the register in which the result is returned . It 's NULL for `` call '' and `` sibcall '' . MEM is the location of the function call . SIBCALL indicates whether this function call is normal call or sibling call . It will generate different pattern accordingly .


<s> int ARMBaseInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode * UseNode , unsigned UseIdx ) const { if ( ! DefNode -> isMachineOpcode ( ) ) return 1 ; const TargetInstrDesc & DefTID = get ( DefNode -> getMachineOpcode ( ) ) ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return DefTID . mayLoad ( ) ? 3 : 1 ; if ( ! UseNode -> isMachineOpcode ( ) ) { int Latency = ItinData -> getOperandCycle ( DefTID . getSchedClass ( ) , DefIdx ) ; if ( Subtarget . isCortexA9 ( ) ) return Latency <= 2 ? 1 : Latency - 1 ; else return Latency <= 3 ? 1 : Latency - 2 ; } const TargetInstrDesc & UseTID = get ( UseNode -> getMachineOpcode ( ) ) ; const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; int Latency = getOperandLatency ( ItinData , DefTID , DefIdx , DefAlign , UseTID , UseIdx , UseAlign ) ; if ( Latency > 1 && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefTID . getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: LDRBrs : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( 2 ) ) -> getZExtValue ( ) ; unsigned ShImm = ARM_AM :: getAM2Offset ( ShOpVal ) ; if ( ShImm == 0 || ( ShImm == 2 && ARM_AM :: getAM2ShiftOpc ( ShOpVal ) == ARM_AM :: lsl ) ) -- Latency ; break ; } case ARM :: t2LDRs : case ARM :: t2LDRBs : case ARM :: t2LDRHs : case ARM :: t2LDRSHs : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( 2 ) ) -> getZExtValue ( ) ; if ( ShAmt == 0 || ShAmt == 2 ) -- Latency ; break ; } } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> void MipsAsmPrinter :: emitFunctionEntryLabel ( ) { MipsTargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) emitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicroMipsMode ( ) ) { TS . emitDirectiveSetMicroMips ( ) ; TS . setUsesMicroMips ( ) ; TS . updateABIInfo ( * Subtarget ) ; } else TS . emitDirectiveSetNoMicroMips ( ) ; if ( Subtarget -> inMips16Mode ( ) ) TS . emitDirectiveSetMips16 ( ) ; else TS . emitDirectiveSetNoMips16 ( ) ; TS . emitDirectiveEnt ( * CurrentFnSym ) ; OutStreamer -> emitLabel ( CurrentFnSym ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> bool isFPVectorizationPotentiallyUnsafe ( ) { return ! ST -> isTargetDarwin ( ) ; } </s>

Indicate that it is potentially unsafe to automatically vectorize floating-point operations because the semantics of vector and scalar floating-point semantics may differ .


<s> unsigned rvexFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; if ( rvexFixGlobalBaseReg ) return GlobalBaseReg = rvex :: R0 ; const TargetRegisterClass * RC ; RC = ( const TargetRegisterClass * ) & rvex :: CPURegsRegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

rvex rvex rvex rvex::R0 rvex::CPURegsRegClass


<s> bool aarch64_sve_sqadd_sqsub_immediate_p ( machine_mode mode , rtx x , bool negate_p ) { if ( ! aarch64_sve_arith_immediate_p ( mode , x , negate_p ) ) return false ; rtx elt = unwrap_const_vec_duplicate ( x ) ; return negate_p == ( INTVAL ( elt ) < 0 ) ; } </s>

Return true if X is a valid immediate for the SVE SQADD and SQSUB instructions when applied to mode MODE . Negate X first if NEGATE_P is true .


<s> bool MSP430InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MSP430MachineFunctionInfo * MFI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , get ( MSP430 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool MBlazePassConfig :: addPreEmitPass ( ) { PM . add ( createMBlazeDelaySlotFillerPass ( getMBlazeTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void ix86_store_bounds ( rtx ptr , rtx slot , rtx bounds , rtx slot_no ) { rtx addr ; addr = ix86_get_arg_address_for_bt ( slot , slot_no , stack_pointer_rtx ) ; if ( ! ptr ) { gcc_assert ( MEM_P ( slot ) ) ; ptr = copy_addr_to_reg ( slot ) ; } gcc_assert ( POINTER_BOUNDS_MODE_P ( GET_MODE ( bounds ) ) ) ; if ( ! register_operand ( bounds , BNDmode ) ) bounds = copy_to_mode_reg ( BNDmode , bounds ) ; emit_insn ( BNDmode == BND64mode ? gen_bnd64_stx ( addr , ptr , bounds ) : gen_bnd32_stx ( addr , ptr , bounds ) ) ; } </s>

Expand pass uses this hook to store BOUNDS for call argument PTR passed in SLOT in case BOUNDS are not passed in a register . If SLOT is a memory , then BOUNDS are stored as for regular pointer stored in memory . PTR may be NULL in case SLOT is a memory . In such case value of PTR ( if required ) may be loaded from SLOT . If SLOT is NULL or a register then SLOT_NO is an integer constant holding number of the target dependent special slot which should be used to store BOUNDS .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s>
SDValue
LC2200TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeOutputArgs
(
DAG
.
getMachineFunction
(
)
,
CCInfo
,
Outs
,
true
,
nullptr
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
SDValue
Val
=
OutVals
[
i
]
;
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocVT
(
)
==
MVT
::
i32
&&
VA
.
getValVT
(
)
==
MVT
::
f64
)
{
llvm_unreachable
(
"not supported"
)
;
}
else
{
Val
=
convertValVTToLocVT
(
DAG
,
Val
,
VA
,
DL
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
Val
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
{
RetOps
.
push_back
(
Glue
)
;
}
const
Function
&
Func
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
;
if
(
Func
.
hasFnAttribute
(
"interrupt"
)
)
{
llvm_unreachable
(
"interrupts not supported"
)
;
}
return
DAG
.
getNode
(
LC2200ISD
::
RET
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


" Delete insn %d because it is redundant\n"

Redundant move elimination pass . Must be run after the basic block reordering pass for the best effect .


<s>
void
AArch64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
,
Mnemonic
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
AArch64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
STI
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
AArch64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
int
OpNum
=
LdStDesc
->
ListOperand
;
printVectorList
(
MI
,
OpNum
++
,
STI
,
O
,
""
)
;
if
(
LdStDesc
->
HasLane
)
O
<<
'['
<<
MI
->
getOperand
(
OpNum
++
)
.
getImm
(
)
<<
']'
;
unsigned
AddrReg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
if
(
Reg
!=
AArch64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
AArch64InstPrinter
::
printInst
(
MI
,
O
,
Annot
,
STI
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> void PPCInstrInfo :: genAlternativeCodeSequence ( MachineInstr & Root , MachineCombinerPattern Pattern , SmallVectorImpl < MachineInstr * > & InsInstrs , SmallVectorImpl < MachineInstr * > & DelInstrs , DenseMap < unsigned , unsigned > & InstrIdxForVirtReg ) const { switch ( Pattern ) { case MachineCombinerPattern :: REASSOC_XY_AMM_BMM : case MachineCombinerPattern :: REASSOC_XMM_AMM_BMM : reassociateFMA ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ; break ; default : TargetInstrInfo :: genAlternativeCodeSequence ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ; break ; } } </s>

When getMachineCombinerPatterns ( ) finds potential patterns , this function generates the instructions that could replace the original code sequence .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static machine_mode aarch64_c_mode_for_suffix ( char suffix ) { if ( suffix == 'q' ) return TFmode ; return VOIDmode ; } </s>


<s> void X86ATTInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << markup ( "<reg:" ) << '%' << getRegisterName ( RegNo ) << markup ( ">" ) ; } </s>


<s> unsigned getExplicitKernelArgOffset ( const Function & F ) const { return isAmdHsaOrMesa ( F ) ? 0 : 36 ; } </s>

Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument .


<s> void SparcInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { if ( ! printAliasInstr ( MI , O ) && ! printSparcAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>


"getJumpTargetOpValue expects only expressions"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> static HOST_WIDE_INT mmix_static_rtx_alignment ( machine_mode mode ) { return MAX ( GET_MODE_ALIGNMENT ( mode ) , 32 ) ; } </s>


<s> const R600RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static void arm_init_builtin ( unsigned int fcode , arm_builtin_datum * d , const char * prefix ) { bool print_type_signature_p = false ; char type_signature [ SIMD_MAX_BUILTIN_ARGS ] = { 0 } ; char namebuf [ 60 ] ; tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - 1 ; int arg_num = d -> qualifiers [ 0 ] & qualifier_void ? op_num + 1 : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= 0 ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum arm_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ; if ( qualifiers & qualifier_unsigned ) { type_signature [ arg_num ] = 'u' ; print_type_signature_p = true ; } else if ( qualifiers & qualifier_poly ) { type_signature [ arg_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ arg_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; eltype = arm_simd_builtin_type ( op_mode , ( qualifiers & qualifier_unsigned ) != 0 , ( qualifiers & qualifier_poly ) != 0 ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; if ( arg_num == 0 ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } ftype = build_function_type ( return_type , args ) ; gcc_assert ( ftype != NULL ) ; if ( print_type_signature_p && IN_RANGE ( fcode , ARM_BUILTIN_VFP_BASE , ARM_BUILTIN_ACLE_BASE - 1 ) ) snprintf ( namebuf , sizeof ( namebuf ) , "%s_%s_%s" , prefix , d -> name , type_signature ) ; else snprintf ( namebuf , sizeof ( namebuf ) , "%s_%s" , prefix , d -> name ) ; fndecl = add_builtin_function ( namebuf , ftype , fcode , BUILT_IN_MD , NULL , NULL_TREE ) ; arm_builtin_decls [ fcode ] = fndecl ; } </s>

Set up a builtin . It will use information stored in the argument struct D to derive the builtin 's type signature and name . It will append the name in D to the PREFIX passed and use these to create a builtin declaration that is then stored in 'arm_builtin_decls ' under index FCODE . This FCODE is also written back to D for future use .


<s> std :: unique_ptr < CSEConfigBase > MOSPassConfig :: getCSEConfig ( ) const { if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) return std :: make_unique < CSEConfigConstantOnly > ( ) ; return std :: make_unique < MOSCSEConfigFull > ( ) ; } </s>

Returns the CSEConfig object to use for the current optimization level .


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static bool expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt , bool testing_p ) { unsigned int i ; rtx x , save_vconcat ; int icode ; if ( vselect_insn == NULL_RTX ) init_vselect_insn ( ) ; x = XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , 1 ) ; PUT_NUM_ELEM ( XVEC ( x , 0 ) , nelt ) ; for ( i = 0 ; i < nelt ; ++ i ) XVECEXP ( x , 0 , i ) = GEN_INT ( perm [ i ] ) ; save_vconcat = XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , 0 ) ; XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , 0 ) = op0 ; PUT_MODE ( SET_SRC ( PATTERN ( vselect_insn ) ) , GET_MODE ( target ) ) ; SET_DEST ( PATTERN ( vselect_insn ) ) = target ; icode = recog_memoized ( vselect_insn ) ; if ( icode >= 0 && ! testing_p ) emit_insn ( copy_rtx ( PATTERN ( vselect_insn ) ) ) ; SET_DEST ( PATTERN ( vselect_insn ) ) = const0_rtx ; XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , 0 ) = save_vconcat ; INSN_CODE ( vselect_insn ) = - 1 ; return icode >= 0 ; } </s>

Construct ( set target ( vec_select op0 ( parallel perm ) ) ) and return true if that 's a valid instruction in the active ISA .


<s>
void
BPFDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
SDIV
:
{
DebugLoc
Empty
;
const
DebugLoc
&
DL
=
Node
->
getDebugLoc
(
)
;
if
(
DL
!=
Empty
)
errs
(
)
<<
"Error at line "
<<
DL
.
getLine
(
)
<<
": "
;
else
errs
(
)
<<
"Error: "
;
errs
(
)
<<
"Unsupport signed division for DAG: "
;
Node
->
print
(
errs
(
)
,
CurDAG
)
;
errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Node
->
getOperand
(
1
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
case
Intrinsic
::
bpf_load_byte
:
case
Intrinsic
::
bpf_load_half
:
case
Intrinsic
::
bpf_load_word
:
{
SDLoc
DL
(
Node
)
;
SDValue
Chain
=
Node
->
getOperand
(
0
)
;
SDValue
N1
=
Node
->
getOperand
(
1
)
;
SDValue
Skb
=
Node
->
getOperand
(
2
)
;
SDValue
N3
=
Node
->
getOperand
(
3
)
;
SDValue
R6Reg
=
CurDAG
->
getRegister
(
BPF
::
R6
,
MVT
::
i64
)
;
Chain
=
CurDAG
->
getCopyToReg
(
Chain
,
DL
,
R6Reg
,
Skb
,
SDValue
(
)
)
;
Node
=
CurDAG
->
UpdateNodeOperands
(
Node
,
Chain
,
N1
,
R6Reg
,
N3
)
;
break
;
}
}
break
;
}
case
ISD
::
FrameIndex
:
{
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
BPF
::
MOV_rr
;
if
(
Node
->
hasOneUse
(
)
)
{
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
)
;
return
;
}
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
Opc
,
SDLoc
(
Node
)
,
VT
,
TFI
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> enum direction function_arg_padding ( machine_mode mode , const_tree type ) { if ( TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P ( type ) ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ; } </s>

Handle the FUNCTION_ARG_PADDING macro . For the 64 bit ABI structs are always stored left shifted in their argument slot .


"PPC hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: NumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ArgGPRs [ I ] ) ; if ( ! MF . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( SystemZ :: R6D ) ; SavedRegs . set ( SystemZ :: R7D ) ; } if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS ) { printInstruction ( MI , OS ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>


<s> int c4x_R_constraint ( rtx op ) { enum machine_mode mode = GET_MODE ( op ) ; if ( TARGET_C3X ) return 0 ; if ( GET_CODE ( op ) != MEM ) return 0 ; op = XEXP ( op , 0 ) ; switch ( GET_CODE ( op ) ) { case REG : return 1 ; case PLUS : { rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; if ( ! REG_P ( op0 ) ) return 0 ; if ( GET_CODE ( op1 ) != CONST_INT ) return 0 ; if ( mode == HImode || mode == HFmode ) return IS_UINT5_CONST ( INTVAL ( op1 ) + 1 ) ; return IS_UINT5_CONST ( INTVAL ( op1 ) ) ; } break ; default : break ; } return 0 ; } </s>

ARx + 5-bit unsigned const * ARx , * +ARx ( n ) for n < 32 .


<s> Register LC2200RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const LC2200Subtarget & Subtarget = MF . getSubtarget < LC2200Subtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? LC2200 :: fp : LC2200 :: sp ; } </s>


<s> int ARMBaseInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { if ( ! ItinData || ItinData -> isEmpty ( ) ) return - 1 ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; const MCInstrDesc * DefMCID = & DefMI -> getDesc ( ) ; const MCInstrDesc * UseMCID = & UseMI -> getDesc ( ) ; unsigned DefAdj = 0 ; if ( DefMI -> isBundle ( ) ) { DefMI = getBundledDefMI ( & getRegisterInfo ( ) , DefMI , Reg , DefIdx , DefAdj ) ; DefMCID = & DefMI -> getDesc ( ) ; } if ( DefMI -> isCopyLike ( ) || DefMI -> isInsertSubreg ( ) || DefMI -> isRegSequence ( ) || DefMI -> isImplicitDef ( ) ) { return 1 ; } unsigned UseAdj = 0 ; if ( UseMI -> isBundle ( ) ) { unsigned NewUseIdx ; const MachineInstr * NewUseMI = getBundledUseMI ( & getRegisterInfo ( ) , UseMI , Reg , NewUseIdx , UseAdj ) ; if ( ! NewUseMI ) return - 1 ; UseMI = NewUseMI ; UseIdx = NewUseIdx ; UseMCID = & UseMI -> getDesc ( ) ; } if ( Reg == ARM :: CPSR ) { if ( DefMI -> getOpcode ( ) == ARM :: FMSTAT ) { return Subtarget . isLikeA9 ( ) ? 1 : 20 ; } if ( UseMI -> isBranch ( ) ) return 0 ; unsigned Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency > 0 && Subtarget . isThumb2 ( ) ) { const MachineFunction * MF = DefMI -> getParent ( ) -> getParent ( ) ; if ( MF -> getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: OptimizeForSize ) ) -- Latency ; } return Latency ; } if ( DefMO . isImplicit ( ) || UseMI -> getOperand ( UseIdx ) . isImplicit ( ) ) return - 1 ; unsigned DefAlign = DefMI -> hasOneMemOperand ( ) ? ( * DefMI -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; unsigned UseAlign = UseMI -> hasOneMemOperand ( ) ? ( * UseMI -> memoperands_begin ( ) ) -> getAlignment ( ) : 0 ; int Latency = getOperandLatency ( ItinData , * DefMCID , DefIdx , DefAlign , * UseMCID , UseIdx , UseAlign ) ; if ( Latency < 0 ) return Latency ; int Adj = DefAdj + UseAdj ; Adj += adjustDefLatency ( Subtarget , DefMI , DefMCID , DefAlign ) ; if ( Adj >= 0 || ( int ) Latency > - Adj ) { return Latency + Adj ; } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> BlackfinTargetLowering :: ConstraintType BlackfinTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) != 1 ) return TargetLowering :: getConstraintType ( Constraint ) ; switch ( Constraint [ 0 ] ) { case 'r' : return C_RegisterClass ; case 'a' : case 'd' : case 'z' : case 'D' : case 'W' : case 'e' : case 'b' : case 'v' : case 'f' : case 'c' : case 't' : case 'u' : case 'k' : case 'x' : case 'y' : case 'w' : return C_RegisterClass ; case 'A' : case 'B' : case 'C' : case 'Z' : case 'Y' : return C_Register ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool ix86_legitimate_constant_p ( machine_mode , rtx x ) { if ( POINTER_BOUNDS_MODE_P ( GET_MODE ( x ) ) ) return false ; switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; break ; case CONST_DOUBLE : if ( GET_MODE ( x ) == TImode && x != CONST0_RTX ( TImode ) && ! TARGET_64BIT ) return false ; break ; case CONST_VECTOR : if ( ! standard_sse_constant_p ( x ) ) return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count % 4 != 0 ) return false ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0x60000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .