<s> static bool is_cracked_insn ( rtx insn ) { if ( ! insn || ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_LOAD_U || type == TYPE_STORE_U || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE || type == TYPE_IDIV || type == TYPE_LDIV || type == TYPE_INSERT_WORD ) return true ; } return false ; } </s>

The function returns true if INSN is cracked into 2 instructions by the processor ( and therefore occupies 2 issue slots ) .


<s> unsigned AAPInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { unsigned Count = 0 ; auto I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) break ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; ++ Count ; } return Count ; } </s>

Remove the branching code at the end of the specific MBB .


<s> static reg_class_t sh_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( rclass == NO_REGS && TARGET_SHMEDIA && ( CONST_DOUBLE_P ( x ) || GET_CODE ( x ) == SYMBOL_REF || PIC_ADDR_P ( x ) ) ) return GENERAL_REGS ; return rclass ; } </s>


<s> void MBlazeTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> static void visium_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx addr = XEXP ( m_tramp , 0 ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 0 ) ) , plus_constant ( SImode , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , 16 , NULL_RTX , 1 ) , 0x04a90000 ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 4 ) ) , plus_constant ( SImode , expand_and ( SImode , fnaddr , GEN_INT ( 0xffff ) , NULL_RTX ) , 0x04890000 ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 8 ) ) , plus_constant ( SImode , expand_shift ( RSHIFT_EXPR , SImode , static_chain , 16 , NULL_RTX , 1 ) , 0x04b40000 ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 12 ) ) , gen_int_mode ( 0xff892404 , SImode ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 16 ) ) , plus_constant ( SImode , expand_and ( SImode , static_chain , GEN_INT ( 0xffff ) , NULL_RTX ) , 0x04940000 ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__set_trampoline_parity" ) , LCT_NORMAL , VOIDmode , 1 , addr , SImode ) ; } </s>

Initialize a trampoline . M_TRAMP is an RTX for the memory block for the trampoline , FNDECL is the FUNCTION_DECL for the nested function and STATIC_CHAIN is an RTX for the static chain value that should be passed to the function when it is called .


"sret virtual register not created in entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> Register ARMTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return Subtarget -> useSjLjEH ( ) ? Register ( ) : ARM :: R0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> const TargetRegisterClass * MSP430RegisterInfo :: getPointerRegClass ( ) const { return & MSP430 :: GR16RegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
unsigned
SparcCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
TM
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Sparc
Sparc
"Unable to encode MachineOperand!"
0


<s> SDNode * MandarinDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return NULL ; } switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: FrameIndex : if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) { return CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ; } } return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static void riscv_emit_float_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 ) { rtx tmp0 , tmp1 , cmp_op0 = * op0 , cmp_op1 = * op1 ; enum rtx_code fp_code = * code ; * code = NE ; switch ( fp_code ) { case UNORDERED : * code = EQ ; case ORDERED : tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; case UNEQ : case LTGT : * code = fp_code == LTGT ? GTU : EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; break ; default : gcc_unreachable ( ) ; } } </s>

Like riscv_emit_int_compare , but for floating-point comparisons .


<s> static struct constant_pool * s390_alloc_pool ( void ) { struct constant_pool * pool ; int i ; pool = ( struct constant_pool * ) xmalloc ( sizeof * pool ) ; pool -> next = NULL ; for ( i = 0 ; i < NR_C_MODES ; i ++ ) pool -> constants [ i ] = NULL ; pool -> execute = NULL ; pool -> label = gen_label_rtx ( ) ; pool -> first_insn = NULL_RTX ; pool -> pool_insn = NULL_RTX ; pool -> insns = BITMAP_ALLOC ( NULL ) ; pool -> size = 0 ; return pool ; } </s>


<s> void m32r_expand_prologue ( ) { int regno ; int frame_size ; unsigned int gmask ; if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; gmask = current_frame_info . gmask ; if ( current_frame_info . total_size == 0 && gmask ) abort ( ) ; if ( current_frame_info . pretend_size != 0 ) { HOST_WIDE_INT pretend_size = current_frame_info . pretend_size ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - pretend_size ) ) ) ; } if ( current_frame_info . save_fp ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , frame_pointer_rtx ) ) ; gmask &= ~ ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) ; for ( regno = 0 ; regno <= M32R_MAX_INT_REGS ; ++ regno ) { if ( ( gmask & ( 1 << regno ) ) != 0 ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , regno ) ) ) ; } if ( current_frame_info . save_lr ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ) ; frame_size = ( current_frame_info . total_size - ( current_frame_info . pretend_size + current_frame_info . reg_size ) ) ; if ( frame_size == 0 ) ; else if ( frame_size <= 32768 ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - frame_size ) ) ) ; else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( frame_size ) ) ) ; emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; } if ( frame_pointer_needed ) emit_insn ( gen_movsi ( frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( current_function_profile ) emit_insn ( gen_blockage ( ) ) ; } </s>

Expand the m32r prologue as a series of insns .


<s> static bool msp430_no_hwmult ( void ) { static const char * cached_match = NULL ; static bool cached_result ; int i ; if ( msp430_hwmult_type == NONE ) return true ; if ( msp430_hwmult_type != AUTO ) return false ; if ( target_mcu == NULL ) return true ; if ( target_mcu == cached_match ) return cached_result ; cached_match = target_mcu ; for ( i = ARRAY_SIZE ( msp430_mcu_data ) ; i -- ; ) if ( strcasecmp ( target_mcu , msp430_mcu_data [ i ] . name ) == 0 ) return cached_result = msp430_mcu_data [ i ] . hwmpy == 0 ; return cached_result = true ; } </s>

Returns true if the current MCU does not have a hardware multiplier of any kind .


"Instruction should be in a basic block!"

"Generic instr has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> int NVPTXRegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return 0 ; } </s>

Map a target register to an equivalent dwarf register number .


<s> void finish ( ) override { for ( auto * Sym : UpdateOther ) copyLocalEntry ( Sym , Sym -> getVariableValue ( ) ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> static rtx rs6000_complex_function_value ( machine_mode mode ) { unsigned int regno ; rtx r1 , r2 ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int inner_bytes = GET_MODE_UNIT_SIZE ( mode ) ; if ( FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else { regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= 4 ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= 8 ) return gen_rtx_REG ( mode , regno ) ; r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno ) , const0_rtx ) ; r2 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno + 1 ) , GEN_INT ( inner_bytes ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } </s>

Return an RTX representing where to find the function value of a function returning MODE .


<s> void gen_shifty_op ( int code , rtx * operands ) { int value = INTVAL ( operands [ 2 ] ) ; int max , i ; value = value & 0x1f ; if ( value == 31 ) { if ( code == LSHIFTRT ) { emit_insn ( gen_rotlsi3_1 ( operands [ 0 ] , operands [ 0 ] ) ) ; emit_insn ( gen_movt ( operands [ 0 ] ) ) ; return ; } else if ( code == ASHIFT ) { if ( GET_CODE ( operands [ 0 ] ) == REG && REGNO ( operands [ 0 ] ) == 0 ) { emit_insn ( gen_andsi3 ( operands [ 0 ] , operands [ 0 ] , const1_rtx ) ) ; emit_insn ( gen_rotlsi3_31 ( operands [ 0 ] , operands [ 0 ] ) ) ; return ; } } } else if ( value == 0 ) { emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , operands [ 0 ] ) ) ; return ; } max = shift_insns [ value ] ; for ( i = 0 ; i < max ; i ++ ) gen_ashift ( code , shift_amounts [ value ] [ i ] , operands [ 0 ] ) ; } </s>

Output RTL to split a constant shift into its component SH constant shift instructions .


<s>
bool
AMDGPUAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Name
=
parseMnemonicSuffix
(
Name
)
;
Operands
.
push_back
(
AMDGPUOperand
::
CreateToken
(
this
,
Name
,
NameLoc
)
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
OperandMatchResultTy
Res
=
parseOperand
(
Operands
,
Name
)
;
if
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
Parser
.
Lex
(
)
;
switch
(
Res
)
{
case
MatchOperand_Success
:
break
;
case
MatchOperand_ParseFail
:
Error
(
getLexer
(
)
.
getLoc
(
)
,
"failed parsing operand."
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
case
MatchOperand_NoMatch
:
Error
(
getLexer
(
)
.
getLoc
(
)
,
"not a valid operand."
)
;
while
(
!
getLexer
(
)
.
is
(
AsmToken
::
EndOfStatement
)
)
{
Parser
.
Lex
(
)
;
}
return
true
;
}
}
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

AMDGPU
AMDGPU
AMDGPU
"failed parsing operand."
"not a valid operand."


<s> bool GCNTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const GCNSubtarget * CallerST = static_cast < const GCNSubtarget * > ( TM . getSubtargetImpl ( * Caller ) ) ; const GCNSubtarget * CalleeST = static_cast < const GCNSubtarget * > ( TM . getSubtargetImpl ( * Callee ) ) ; const FeatureBitset & CallerBits = CallerST -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = CalleeST -> getFeatureBits ( ) ; FeatureBitset RealCallerBits = CallerBits & ~ InlineFeatureIgnoreList ; FeatureBitset RealCalleeBits = CalleeBits & ~ InlineFeatureIgnoreList ; if ( ( RealCallerBits & RealCalleeBits ) != RealCalleeBits ) return false ; AMDGPU :: SIModeRegisterDefaults CallerMode ( * Caller ) ; AMDGPU :: SIModeRegisterDefaults CalleeMode ( * Callee ) ; if ( ! CallerMode . isInlineCompatible ( CalleeMode ) ) return false ; if ( Callee -> hasFnAttribute ( Attribute :: AlwaysInline ) || Callee -> hasFnAttribute ( Attribute :: InlineHint ) ) return true ; if ( InlineMaxBB ) { if ( Callee -> size ( ) == 1 ) return true ; size_t BBSize = Caller -> size ( ) + Callee -> size ( ) - 1 ; return BBSize <= InlineMaxBB ; } return true ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> static rtx gen_rx_popm_vector ( unsigned int low , unsigned int high ) { unsigned int i ; unsigned int count = ( high - low ) + 2 ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , 0 , 0 ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , ( count - 1 ) * UNITS_PER_WORD ) ) ; for ( i = 0 ; i < count - 1 ; i ++ ) XVECEXP ( vector , 0 , i + 1 ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , low + i ) , gen_rtx_MEM ( SImode , i == 0 ? stack_pointer_rtx : plus_constant ( Pmode , stack_pointer_rtx , i * UNITS_PER_WORD ) ) ) ; return vector ; } </s>

Generate a PARALLEL which will satisfy the rx_load_multiple_vector predicate .


<s> virtual void scheduleTree ( unsigned SubtreeID ) { } </s>

Scheduler callback to update SubtreeConnectLevels when a tree is initially scheduled .


<s> bool RISCVTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { SDValue BaseFromLDST ; EVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { BaseFromLDST = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { BaseFromLDST = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else { return false ; } if ( Op -> getOpcode ( ) == ISD :: ADD ) { AM = ISD :: POST_INC ; Base = Op -> getOperand ( 0 ) ; Offset = Op -> getOperand ( 1 ) ; if ( BaseFromLDST != Base && BaseFromLDST == Offset ) { std :: swap ( Base , Offset ) ; } if ( ! ( VT == MVT :: i8 || VT == MVT :: i16 || VT == MVT :: i32 ) ) { return false ; } if ( ConstantSDNode * ConstOffset = dyn_cast < ConstantSDNode > ( Offset ) ) { uint64_t imm = ConstOffset -> getZExtValue ( ) ; if ( ! isInt < 12 > ( imm ) ) { return false ; } } return BaseFromLDST == Base ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> bool ARM64TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode * Node : Copy -> uses ( ) ) { if ( Node -> getOpcode ( ) != ARM64ISD :: RET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s> static int spu_sched_issue_rate ( void ) { return 2 ; } </s>

Insn scheduling routines , primarily for dual issue .


<s>
void
applyFixup
(
const
MCFixup
&
Fixup
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
static
rtx
bpf_expand_builtin
(
tree
exp
,
rtx
target
ATTRIBUTE_UNUSED
,
rtx
subtarget
ATTRIBUTE_UNUSED
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
ignore
ATTRIBUTE_UNUSED
)
{
tree
fndecl
=
TREE_OPERAND
(
CALL_EXPR_FN
(
exp
)
,
0
)
;
int
code
=
DECL_MD_FUNCTION_CODE
(
fndecl
)
;
if
(
code
==
BPF_BUILTIN_LOAD_BYTE
||
code
==
BPF_BUILTIN_LOAD_HALF
||
code
==
BPF_BUILTIN_LOAD_WORD
)
{
enum
insn_code
abs_icode
=
(
code
==
BPF_BUILTIN_LOAD_BYTE
CODE_FOR_ldabsb
:
code
==
BPF_BUILTIN_LOAD_HALF
CODE_FOR_ldabsh
:
CODE_FOR_ldabsw
)
;
enum
insn_code
ind_icode
=
(
code
==
BPF_BUILTIN_LOAD_BYTE
CODE_FOR_ldindb
:
code
==
BPF_BUILTIN_LOAD_HALF
CODE_FOR_ldindh
:
CODE_FOR_ldindw
)
;
tree
offset_arg
=
CALL_EXPR_ARG
(
exp
,
0
)
;
struct
expand_operand
ops
[
2
]
;
create_input_operand
(
&
ops
[
0
]
,
expand_normal
(
offset_arg
)
,
TYPE_MODE
(
TREE_TYPE
(
offset_arg
)
)
)
;
create_input_operand
(
&
ops
[
1
]
,
const0_rtx
,
SImode
)
;
if
(
!
maybe_expand_insn
(
abs_icode
,
2
,
ops
)
&&
!
maybe_expand_insn
(
ind_icode
,
2
,
ops
)
)
{
error
(
"invalid argument to built-in function"
)
;
return
gen_rtx_REG
(
ops
[
0
]
.
mode
,
BPF_R0
)
;
}
return
gen_rtx_REG
(
ops
[
0
]
.
mode
,
BPF_R0
)
;
}
else
if
(
code
==
1
)
{
tree
arg
=
CALL_EXPR_ARG
(
exp
,
0
)
;
if
(
arg
==
NULL_TREE
)
return
NULL_RTX
;
auto_vec
<
unsigned
int
,
16
>
accessors
;
tree
container
;
if
(
TREE_CODE
(
arg
)
==
SSA_NAME
)
{
gimple
*
def_stmt
=
SSA_NAME_DEF_STMT
(
arg
)
;
if
(
is_gimple_assign
(
def_stmt
)
)
arg
=
gimple_assign_rhs1
(
def_stmt
)
;
else
return
expand_normal
(
arg
)
;
}
if
(
is_attr_preserve_access
(
arg
)
)
return
expand_normal
(
arg
)
;
container
=
bpf_core_compute
(
arg
,
&
accessors
)
;
if
(
accessors
.
length
(
)
<
1
)
return
expand_normal
(
arg
)
;
accessors
.
reverse
(
)
;
container
=
TREE_TYPE
(
container
)
;
rtx_code_label
*
label
=
gen_label_rtx
(
)
;
LABEL_PRESERVE_P
(
label
)
=
1
;
emit_label
(
label
)
;
const
char
*
section_name
;
if
(
current_function_decl
&&
DECL_SECTION_NAME
(
current_function_decl
)
)
section_name
=
DECL_SECTION_NAME
(
current_function_decl
)
;
else
section_name
=
".text"
;
bpf_core_reloc_add
(
container
,
section_name
,
&
accessors
,
label
)
;
return
expand_normal
(
arg
)
;
}
gcc_unreachable
(
)
;
}
</s>

Expand a call to a BPF-specific built-in function that was set up with bpf_init_builtins .


<s> inline static int thumb_index_register_rtx_p ( rtx x , int strict_p ) { return thumb_base_register_rtx_p ( x , QImode , strict_p ) ; } </s>

Return nonzero if x is a legitimate index register . This is the case for any base register that can access a QImode object .


<s> void HexagonPassConfig :: addPreEmitPass ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( createHexagonNewValueJump ( ) , false ) ; addPass ( createHexagonExpandPredSpillCode ( ) , false ) ; addPass ( createHexagonSplitTFRCondSets ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( createHexagonFixupHwLoops ( ) , false ) ; addPass ( createHexagonPacketizer ( ) , false ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const { unsigned LblOperand = Inst . getOpcode ( ) == AArch64 :: Bcc ? 1 : 0 ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( LblOperand ) . getImm ( ) ; Target = Addr + Imm ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


"Cannot find register class for value type"

Return the 'representative ' register class for the specified value type .


"Can't move the target block as it would "

"introduce a new backwards WLS branch\n"

runOnMachineFunction - Emit the function body .


<s> static bool expand_vec_perm_vpermil ( struct expand_vec_perm_d * d ) { rtx rperm [ 8 ] , vperm ; unsigned i ; if ( ! TARGET_AVX || d -> vmode != V8SFmode || ! d -> one_operand_p ) return false ; for ( i = 0 ; i < 8 ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( i < 4 ? e >= 4 : e < 4 ) return false ; } if ( d -> testing_p ) return true ; for ( i = 0 ; i < 8 ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e >= 8 + 4 ) e -= 8 ; else if ( e >= 4 ) e -= 4 ; rperm [ i ] = GEN_INT ( e ) ; } vperm = gen_rtx_CONST_VECTOR ( V8SImode , gen_rtvec_v ( 8 , rperm ) ) ; vperm = force_reg ( V8SImode , vperm ) ; emit_insn ( gen_avx_vpermilvarv8sf3 ( d -> target , d -> op0 , vperm ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to implement D in terms of the variable form of vpermilps . Note that we will have already failed the immediate input vpermilps , which requires that the high and low part shuffle be identical ; the variable form does n't require that .


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
false
;
for
(
const
MachineOperand
&
MO
:
Orig
.
operands
(
)
)
{
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
MO
.
getReg
(
)
==
X86
::
EFLAGS
)
{
ClobbersEFLAGS
=
true
;
break
;
}
}
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
addOperand
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
*
NewMI
=
std
::
prev
(
I
)
;
NewMI
->
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


Maybe decorate and get a new identifier for the DECL of a stdcall or fastcall function . The original identifier is supplied in ID .


<s>
SDValue
ARMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
assert
(
0
&&
"Don't know how to custom lower this!"
)
;
abort
(
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
Subtarget
->
isTargetDarwin
(
)
LowerGlobalAddressDarwin
(
Op
,
DAG
)
:
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
CALL
:
return
LowerCALL
(
Op
,
DAG
)
;
case
ISD
::
RET
:
return
LowerRET
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
VarArgsFrameIndex
)
;
case
ISD
::
SINT_TO_FP
:
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
FCOPYSIGN
:
return
LowerFCOPYSIGN
(
Op
,
DAG
)
;
case
ISD
::
FORMAL_ARGUMENTS
:
return
LowerFORMAL_ARGUMENTS
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
break
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
LowerGLOBAL_OFFSET_TABLE
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
BIT_CONVERT
:
return
ExpandBIT_CONVERT
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
ExpandSRx
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> unsigned ARMBaseInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; switch ( MI . getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case ARM :: MOVi16_ga_pcrel : case ARM :: MOVTi16_ga_pcrel : case ARM :: t2MOVi16_ga_pcrel : case ARM :: t2MOVTi16_ga_pcrel : return 4 ; case ARM :: MOVi32imm : case ARM :: t2MOVi32imm : return 8 ; case ARM :: CONSTPOOL_ENTRY : case ARM :: JUMPTABLE_INSTS : case ARM :: JUMPTABLE_ADDRS : case ARM :: JUMPTABLE_TBB : case ARM :: JUMPTABLE_TBH : return MI . getOperand ( 2 ) . getImm ( ) ; case ARM :: Int_eh_sjlj_longjmp : return 16 ; case ARM :: tInt_eh_sjlj_longjmp : return 10 ; case ARM :: tInt_WIN_eh_sjlj_longjmp : return 12 ; case ARM :: Int_eh_sjlj_setjmp : case ARM :: Int_eh_sjlj_setjmp_nofp : return 20 ; case ARM :: tInt_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp_nofp : return 12 ; case ARM :: SPACE : return MI . getOperand ( 1 ) . getImm ( ) ; case ARM :: INLINEASM : case ARM :: INLINEASM_BR : { unsigned Size = getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ; if ( ! MF -> getInfo < ARMFunctionInfo > ( ) -> isThumbFunction ( ) ) Size = alignTo ( Size , 4 ) ; return Size ; } case ARM :: SpeculationBarrierISBDSBEndBB : case ARM :: t2SpeculationBarrierISBDSBEndBB : return 8 ; case ARM :: SpeculationBarrierSBEndBB : case ARM :: t2SpeculationBarrierSBEndBB : return 4 ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s>
bool
AArch64A53Fix835769
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"***** AArch64A53Fix835769 *****\n"
)
;
bool
Changed
=
false
;
TII
=
F
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
auto
&
MBB
:
F
)
{
Changed
|=
runOnBasicBlock
(
MBB
)
;
}
return
Changed
;
}
</s>


<s>
void
nvptx_declare_object_name
(
FILE
*
file
,
const
char
*
name
,
const_tree
decl
)
{
write_var_marker
(
file
,
true
,
TREE_PUBLIC
(
decl
)
,
name
)
;
fprintf
(
file
,
"\t%s"
,
(
!
TREE_PUBLIC
(
decl
)
""
:
DECL_WEAK
(
decl
)
".weak "
:
".visible "
)
)
;
tree
type
=
TREE_TYPE
(
decl
)
;
HOST_WIDE_INT
obj_size
=
tree_to_shwi
(
DECL_SIZE_UNIT
(
decl
)
)
;
nvptx_assemble_decl_begin
(
file
,
name
,
section_for_decl
(
decl
)
,
type
,
obj_size
,
DECL_ALIGN
(
decl
)
)
;
}
</s>

Implement the ASM_DECLARE_OBJECT_NAME macro . Used to start writing a variable DECL with NAME to FILE .


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'h' : case 'r' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == MVT :: Other ) return false ; if ( AddrSpace == AMDGPUAS :: LOCAL_ADDRESS ) { return Align % 4 == 0 ; } if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool AMDGPUAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { const AMDGPUSubtarget & STM = TM . getSubtarget < AMDGPUSubtarget > ( ) ; if ( STM . dumpCode ( ) ) { MF . dump ( ) ; } SetupMachineFunction ( MF ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { OutStreamer . EmitRawText ( "@" + MF . getName ( ) + ":" ) ; } OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( STM . device ( ) -> getGeneration ( ) > AMDGPUDeviceInfo :: HD6XXX ) { EmitProgramInfo ( MF ) ; } EmitFunctionBody ( ) ; return false ; } </s>


<s> WebAssemblySubtarget :: WebAssemblySubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : WebAssemblyGenSubtargetInfo ( TT , CPU , FS ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> void HexagonShuffler :: append ( MCInst const * ID , MCInst const * Extender , unsigned S , bool X ) { HexagonInstr PI ( MCII , ID , Extender , S , X ) ; Packet . push_back ( PI ) ; } </s>


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createZ80OMFObjectWriter ( OS ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> unsigned PIC16RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , int * Value , RegScavenger * RS ) const { return 0 ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"\t# pre-label NOPs for hotpatch (%d halfwords)\n"

"\t# post-label NOPs for hotpatch (%d halfwords)\n"

Write the extra assembler code needed to declare a function properly .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
Mono
:
if
(
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_Mono_DarwinPCS
;
else
if
(
Subtarget
->
isTargetWindows
(
)
)
report_fatal_error
(
"Unsupported calling convention."
)
;
else
return
CC_AArch64_Mono_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static int compare_constants ( const void * key , const void * t ) { return ( * ( int * ) key ) - * ( ( int * ) t ) ; } </s>


<s> unsigned get213Opcode ( ) const { return Opcodes [ Form213 ] ; } </s>


<s>
SUnit
*
R600SchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
SUnit
*
SU
=
0
;
NextInstKind
=
IDOther
;
IsTopNode
=
false
;
bool
AllowSwitchToAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
||
(
Available
[
CurInstKind
]
.
empty
(
)
)
;
bool
AllowSwitchFromAlu
=
(
CurEmitted
>=
InstKindLimit
[
CurInstKind
]
)
&&
(
!
Available
[
IDFetch
]
.
empty
(
)
||
!
Available
[
IDOther
]
.
empty
(
)
)
;
if
(
CurInstKind
==
IDAlu
&&
!
Available
[
IDFetch
]
.
empty
(
)
)
{
float
ALUFetchRationEstimate
=
(
AluInstCount
+
AvailablesAluCount
(
)
+
Pending
[
IDAlu
]
.
size
(
)
)
/
(
FetchInstCount
+
Available
[
IDFetch
]
.
size
(
)
)
;
unsigned
NeededWF
=
62.5f
/
ALUFetchRationEstimate
;
DEBUG
(
dbgs
(
)
<<
NeededWF
<<
" approx. Wavefronts Required\n"
)
;
unsigned
NearRegisterRequirement
=
2
*
Available
[
IDFetch
]
.
size
(
)
;
if
(
NeededWF
>
getWFCountLimitedByGPR
(
NearRegisterRequirement
)
)
AllowSwitchFromAlu
=
true
;
}
if
(
!
SU
&&
(
(
AllowSwitchToAlu
&&
CurInstKind
!=
IDAlu
)
||
(
!
AllowSwitchFromAlu
&&
CurInstKind
==
IDAlu
)
)
)
{
SU
=
pickAlu
(
)
;
if
(
!
SU
&&
!
PhysicalRegCopy
.
empty
(
)
)
{
SU
=
PhysicalRegCopy
.
front
(
)
;
PhysicalRegCopy
.
erase
(
PhysicalRegCopy
.
begin
(
)
)
;
}
if
(
SU
)
{
if
(
CurEmitted
>=
InstKindLimit
[
IDAlu
]
)
CurEmitted
=
0
;
NextInstKind
=
IDAlu
;
}
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDFetch
)
;
if
(
SU
)
NextInstKind
=
IDFetch
;
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDOther
)
;
if
(
SU
)
NextInstKind
=
IDOther
;
}
DEBUG
(
if
(
SU
)
{
dbgs
(
)
<<
" ** Pick node **\n"
;
SU
->
dump
(
DAG
)
;
}
else
{
dbgs
(
)
<<
"NO NODE \n"
;
for
(
unsigned
i
=
0
;
i
<
DAG
->
SUnits
.
size
(
)
;
i
++
)
{
const
SUnit
&
S
=
DAG
->
SUnits
[
i
]
;
if
(
!
S
.
isScheduled
)
S
.
dump
(
DAG
)
;
}
}
</s>

Pick the next node to schedule , or return NULL .


<s>
bool
MipsSEDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Base
,
Offset
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_m
:
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_R
:
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_ZC
:
if
(
Subtarget
->
inMicroMipsMode
(
)
)
{
if
(
selectAddrRegImm12
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
Subtarget
->
hasMips32r6
(
)
)
{
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static void emit_unspec2 ( rtx target , int code , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( target , gen_rtx_UNSPEC ( GET_MODE ( target ) , gen_rtvec ( 2 , op0 , op1 ) , code ) ) ) ; } </s>

Generate ( set TARGET ( unspec [ OP0 OP1 ] CODE ) ) .


<s>
void
bb_sese
::
remove
(
const
pseudo_node_t
&
pseudo
)
{
unsigned
removed
=
0
;
int
len
=
brackets
.
length
(
)
;
for
(
int
ix
=
0
;
ix
<
len
;
ix
++
)
{
if
(
brackets
[
ix
]
.
back
==
pseudo
)
{
if
(
dump_file
)
fprintf
(
dump_file
,
"Removing backedge %d:%+d\n"
,
pseudo
.
first
pseudo
.
first
->
index
:
0
,
pseudo
.
second
)
;
removed
++
;
}
else
if
(
removed
)
brackets
[
ix
removed
]
=
brackets
[
ix
]
;
}
while
(
removed
)
brackets
.
pop
(
)
;
}
</s>

Remove brackets that terminate at PSEUDO .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Sparc Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: X86_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; else return CSR_64_AllRegs_RegMask ; } else { if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; else return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void BTFTypeDeclTag :: completeType ( BTFDebug & BDebug ) { if ( IsCompleted ) return ; IsCompleted = true ; BTFType . NameOff = BDebug . addString ( Tag ) ; } </s>

Complete BTF type generation after all related DebugInfo types have been visited so their BTF type id 's are available for cross referece .


<s> bool SIInsertSkips :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; SkipThreshold = SkipThresholdFlag ; SmallVector < MachineInstr * , 4 > KillInstrs ; SmallVector < MachineInstr * , 4 > EarlyTermInstrs ; bool MadeChange = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_MASK_BRANCH : MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case AMDGPU :: S_BRANCH : if ( MBB . isLayoutSuccessor ( MI . getOperand ( 0 ) . getMBB ( ) ) ) { assert ( & MI == & MBB . back ( ) ) ; MI . eraseFromParent ( ) ; MadeChange = true ; } break ; case AMDGPU :: SI_KILL_F32_COND_IMM_TERMINATOR : case AMDGPU :: SI_KILL_I1_TERMINATOR : { MadeChange = true ; bool CanKill = kill ( MI ) ; if ( CanKill && MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: AMDGPU_PS && dominatesAllReachable ( MBB ) ) { KillInstrs . push_back ( & MI ) ; } else { MI . eraseFromParent ( ) ; } break ; } case AMDGPU :: SI_KILL_CLEANUP : if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: AMDGPU_PS && dominatesAllReachable ( MBB ) ) { KillInstrs . push_back ( & MI ) ; } else { MI . eraseFromParent ( ) ; } break ; case AMDGPU :: SI_EARLY_TERMINATE_SCC0 : EarlyTermInstrs . push_back ( & MI ) ; break ; default : break ; } } } for ( MachineInstr * Instr : EarlyTermInstrs ) { if ( MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: AMDGPU_GS ) earlyTerm ( * Instr ) ; Instr -> eraseFromParent ( ) ; } for ( MachineInstr * Kill : KillInstrs ) { skipIfDead ( * Kill -> getParent ( ) , std :: next ( Kill -> getIterator ( ) ) , Kill -> getDebugLoc ( ) ) ; Kill -> eraseFromParent ( ) ; } KillInstrs . clear ( ) ; EarlyTermInstrs . clear ( ) ; EarlyExitBlock = nullptr ; return MadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDValue PIC16TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , DebugLoc dl , SelectionDAG & DAG ) { unsigned NumRet = Outs . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getFrameLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , MVT :: i8 ) ; SDValue BS = DAG . getConstant ( 1 , MVT :: i8 ) ; SDValue RetVal ; for ( unsigned i = 0 ; i < NumRet ; ++ i ) { RetVal = Outs [ i ] . Val ; Chain = DAG . getNode ( PIC16ISD :: PIC16Store , dl , MVT :: Other , Chain , RetVal , ES , BS , DAG . getConstant ( i , MVT :: i8 ) ) ; } return DAG . getNode ( PIC16ISD :: RET , dl , MVT :: Other , Chain ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void MipsRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; adjustMipsStackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> hasCalls ( ) ) return ; int FPOffset = MipsFI -> getFPStackOffset ( ) ; int RAOffset = MipsFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOREORDER ) ) ; if ( isPIC && Subtarget . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPLOAD ) ) . addReg ( getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: NOMACRO ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDiu ) , Mips :: SP ) . addReg ( Mips :: SP ) . addImm ( - StackSize ) ; if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: RA ) . addImm ( RAOffset ) . addReg ( Mips :: SP ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SW ) ) . addReg ( Mips :: FP ) . addImm ( FPOffset ) . addReg ( Mips :: SP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ADDu ) , Mips :: FP ) . addReg ( Mips :: SP ) . addReg ( Mips :: ZERO ) ; } if ( MipsFI -> needGPSaveRestore ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: CPRESTORE ) ) . addImm ( MipsFI -> getGPStackOffset ( ) ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Mips Mips Mips Mips Mips Mips 0 Mips Mips Mips::NOREORDER Mips::CPLOAD Mips::NOMACRO Mips::ADDiu Mips::SP Mips::SP Mips::SW Mips::RA Mips::SP Mips::SW Mips::FP Mips::SP Mips::ADDu Mips::FP Mips::SP Mips::ZERO Mips Mips::CPRESTORE Mips


<s>
StackOffset
X86FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
&&
TRI
->
hasStackRealignment
(
MF
)
&&
!
STI
.
isTargetWin64
(
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
if
(
!
IgnoreSPUpdates
&&
!
hasReservedCallFrame
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
->
getTCReturnAddrDelta
(
)
>=
0
&&
"we don't handle this case!"
)
;
return
getFrameIndexReferenceSP
(
MF
,
FI
,
FrameReg
,
StackSize
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s>
static
void
rx_print_operand_address
(
FILE
*
file
,
rtx
addr
)
{
switch
(
GET_CODE
(
addr
)
)
{
case
REG
:
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
addr
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
case
PRE_DEC
:
fprintf
(
file
,
"[-"
)
;
rx_print_operand
(
file
,
XEXP
(
addr
,
0
)
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
case
POST_INC
:
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
XEXP
(
addr
,
0
)
,
0
)
;
fprintf
(
file
,
"+]"
)
;
break
;
case
PLUS
:
{
rtx
arg1
=
XEXP
(
addr
,
0
)
;
rtx
arg2
=
XEXP
(
addr
,
1
)
;
rtx
base
,
index
;
if
(
REG_P
(
arg1
)
&&
RTX_OK_FOR_BASE
(
arg1
,
true
)
)
base
=
arg1
,
index
=
arg2
;
else
if
(
REG_P
(
arg2
)
&&
RTX_OK_FOR_BASE
(
arg2
,
true
)
)
base
=
arg2
,
index
=
arg1
;
else
{
rx_print_operand
(
file
,
arg1
,
0
)
;
fprintf
(
file
,
" + "
)
;
rx_print_operand
(
file
,
arg2
,
0
)
;
break
;
}
if
(
REG_P
(
index
)
||
GET_CODE
(
index
)
==
MULT
)
{
fprintf
(
file
,
"["
)
;
rx_print_operand
(
file
,
index
,
'A'
)
;
fprintf
(
file
,
","
)
;
}
else
{
rx_print_operand
(
file
,
index
,
'A'
)
;
fprintf
(
file
,
"["
)
;
}
rx_print_operand
(
file
,
base
,
0
)
;
fprintf
(
file
,
"]"
)
;
break
;
}
case
CONST
:
if
(
GET_CODE
(
XEXP
(
addr
,
0
)
)
==
UNSPEC
)
{
addr
=
XEXP
(
addr
,
0
)
;
gcc_assert
(
XINT
(
addr
,
1
)
==
UNSPEC_CONST
)
;
case
UNSPEC
:
addr
=
XVECEXP
(
addr
,
0
,
0
)
;
gcc_assert
(
CONST_INT_P
(
addr
)
)
;
}
case
LABEL_REF
:
case
SYMBOL_REF
:
fprintf
(
file
,
"#"
)
;
default
:
output_addr_const
(
file
,
addr
)
;
break
;
}
}
</s>

A C compound statement to output to stdio stream FILE the assembler syntax for an instruction operand that is a memory reference whose address is ADDR .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> void MBlazeFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MBlazeInstrInfo & TII = * static_cast < const MBlazeInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; int Amount = Old -> getOperand ( 0 ) . getImm ( ) + 4 ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; MachineInstr * New ; if ( Old -> getOpcode ( ) == MBlaze :: ADJCALLSTACKDOWN ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MBlaze :: ADDIK ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( - Amount ) ; } else { assert ( Old -> getOpcode ( ) == MBlaze :: ADJCALLSTACKUP ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MBlaze :: ADDIK ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( Amount ) ; } MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> HOST_WIDE_INT mips_initial_elimination_offset ( int from , int to ) { HOST_WIDE_INT offset ; mips_compute_frame_info ( ) ; switch ( from ) { case FRAME_POINTER_REGNUM : if ( FRAME_GROWS_DOWNWARD ) offset = ( cfun -> machine -> frame . args_size + cfun -> machine -> frame . cprestore_size + cfun -> machine -> frame . var_size ) ; else offset = 0 ; break ; case ARG_POINTER_REGNUM : offset = cfun -> machine -> frame . arg_pointer_offset ; break ; default : gcc_unreachable ( ) ; } if ( to == HARD_FRAME_POINTER_REGNUM ) offset -= cfun -> machine -> frame . hard_frame_pointer_offset ; return offset ; } </s>

Implement INITIAL_ELIMINATION_OFFSET . FROM is either the frame pointer or argument pointer . TO is either the stack pointer or hard frame pointer .


<s>
void
NVPTXTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"Unhandled custom legalization"
)
;
case
ISD
::
LOAD
:
ReplaceLoadVector
(
N
,
DAG
,
Results
)
;
return
;
case
ISD
::
INTRINSIC_W_CHAIN
:
ReplaceINTRINSIC_W_CHAIN
(
N
,
DAG
,
Results
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

NVPTX
NVPTX
"Unhandled custom legalization"
ISD::LOAD
ISD::INTRINSIC_W_CHAIN


<s> static void msp430_print_operand_raw ( FILE * file , rtx op ) { HOST_WIDE_INT i ; switch ( GET_CODE ( op ) ) { case REG : fprintf ( file , "%s" , reg_names [ REGNO ( op ) ] ) ; break ; case CONST_INT : i = INTVAL ( op ) ; if ( TARGET_ASM_HEX ) fprintf ( file , "%#" HOST_WIDE_INT_PRINT "x" , i ) ; else fprintf ( file , "%" HOST_WIDE_INT_PRINT "d" , i ) ; break ; case CONST : case PLUS : case MINUS : case SYMBOL_REF : case LABEL_REF : output_addr_const ( file , op ) ; break ; default : print_rtl ( file , op ) ; break ; } } </s>

Common code for msp430_print_operand ...


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; unsigned LR = RegInfo -> getRARegister ( ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) , Subtarget . isELFv2ABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s>
bool
AMDGPUAsmParser
::
isInlineConstant
(
const
MCInst
&
Inst
,
unsigned
OpIdx
)
const
{
const
MCInstrDesc
&
Desc
=
MII
.
get
(
Inst
.
getOpcode
(
)
)
;
if
(
!
AMDGPU
::
isSISrcOperand
(
Desc
,
OpIdx
)
)
{
return
false
;
}
const
MCOperand
&
MO
=
Inst
.
getOperand
(
OpIdx
)
;
int64_t
Val
=
MO
.
getImm
(
)
;
auto
OpSize
=
AMDGPU
::
getOperandSize
(
Desc
,
OpIdx
)
;
switch
(
OpSize
)
{
case
8
:
return
AMDGPU
::
isInlinableLiteral64
(
Val
,
hasInv2PiInlineImm
(
)
)
;
case
4
:
return
AMDGPU
::
isInlinableLiteral32
(
Val
,
hasInv2PiInlineImm
(
)
)
;
case
2
:
{
const
unsigned
OperandType
=
Desc
.
OpInfo
[
OpIdx
]
.
OperandType
;
if
(
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
||
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
)
{
return
AMDGPU
::
isInlinableLiteralV216
(
Val
,
hasInv2PiInlineImm
(
)
)
;
}
else
{
return
AMDGPU
::
isInlinableLiteral16
(
Val
,
hasInv2PiInlineImm
(
)
)
;
}
}
default
:
llvm_unreachable
(
"invalid operand size"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> static bool alpha_vms_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { switch ( alpha_procedure_type ) { case PT_NULL : return to == STACK_POINTER_REGNUM ; case PT_REGISTER : case PT_STACK : return ( to != STACK_POINTER_REGNUM || vms_unwind_regno != HARD_FRAME_POINTER_REGNUM ) ; } gcc_unreachable ( ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget . ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> HexagonGOTEntry * HexagonGOT :: create ( ) { return new HexagonGOTEntry ( 0 , m_SectionData ) ; } </s>

Hexagon Hexagon HexagonGOT::create Hexagon 0


<s> unsigned AArch64TargetLowering :: getByValTypeAlignment ( Type * Ty ) const { return 4 ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s>
MachineBasicBlock
::
iterator
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
if
(
!
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
getStackAlign
(
)
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
StackOffset
::
getFixed
(
Amount
)
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
StackOffset
::
getFixed
(
(
int64_t
)
CalleePopAmount
)
,
TII
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>


<s> const WebAssemblySubtarget * WebAssemblyTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = make_unique < WebAssemblySubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

WebAssembly WebAssembly WebAssembly "target-cpu" "target-features" WebAssembly


<s> bool MipsRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool X86InstrInfo :: analyzeBranchPredicate ( MachineBasicBlock & MBB , MachineBranchPredicate & MBP , bool AllowModify ) const { using namespace std :: placeholders ; SmallVector < MachineOperand , 4 > Cond ; SmallVector < MachineInstr * , 4 > CondBranches ; if ( AnalyzeBranchImpl ( MBB , MBP . TrueDest , MBP . FalseDest , Cond , CondBranches , AllowModify ) ) return true ; if ( Cond . size ( ) != 1 ) return true ; assert ( MBP . TrueDest && "expected!" ) ; if ( ! MBP . FalseDest ) MBP . FalseDest = MBB . getNextNode ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstr * ConditionDef = nullptr ; bool SingleUseCondition = true ; for ( auto I = std :: next ( MBB . rbegin ( ) ) , E = MBB . rend ( ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( X86 :: EFLAGS , TRI ) ) { ConditionDef = & * I ; break ; } if ( I -> readsRegister ( X86 :: EFLAGS , TRI ) ) SingleUseCondition = false ; } if ( ! ConditionDef ) return true ; if ( SingleUseCondition ) { for ( auto * Succ : MBB . successors ( ) ) if ( Succ -> isLiveIn ( X86 :: EFLAGS ) ) SingleUseCondition = false ; } MBP . ConditionDef = ConditionDef ; MBP . SingleUseCondition = SingleUseCondition ; const unsigned TestOpcode = Subtarget . is64Bit ( ) ? X86 :: TEST64rr : X86 :: TEST32rr ; if ( ConditionDef -> getOpcode ( ) == TestOpcode && ConditionDef -> getNumOperands ( ) == 3 && ConditionDef -> getOperand ( 0 ) . isIdenticalTo ( ConditionDef -> getOperand ( 1 ) ) && ( Cond [ 0 ] . getImm ( ) == X86 :: COND_NE || Cond [ 0 ] . getImm ( ) == X86 :: COND_E ) ) { MBP . LHS = ConditionDef -> getOperand ( 0 ) ; MBP . RHS = MachineOperand :: CreateImm ( 0 ) ; MBP . Predicate = Cond [ 0 ] . getImm ( ) == X86 :: COND_NE ? MachineBranchPredicate :: PRED_NE : MachineBranchPredicate :: PRED_EQ ; return false ; } return true ; } </s>

Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible .


<s> bool RISCVTargetLowering :: shouldExtendTypeInLibCall ( EVT Type ) const { RISCVABI :: ABI ABI = Subtarget . getTargetABI ( ) ; if ( ABI == RISCVABI :: ABI_LP64 && ( Type == MVT :: f32 ) ) return false ; return true ; } </s>

Returns true if arguments should be extended in lib calls .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , Align ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> TargetPassConfig * Cpu0TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Cpu0PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void AMDGPUAsmPrinter :: emitFunctionEntryLabel ( ) { if ( IsaInfo :: hasCodeObjectV3 ( getGlobalSTI ( ) ) && TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) { AsmPrinter :: emitFunctionEntryLabel ( ) ; return ; } const SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; const GCNSubtarget & STM = MF -> getSubtarget < GCNSubtarget > ( ) ; if ( MFI -> isEntryFunction ( ) && STM . isAmdHsaOrMesa ( MF -> getFunction ( ) ) ) { SmallString < 128 > SymbolName ; getNameWithPrefix ( SymbolName , & MF -> getFunction ( ) ) , getTargetStreamer ( ) -> EmitAMDGPUSymbolType ( SymbolName , ELF :: STT_AMDGPU_HSA_KERNEL ) ; } if ( DumpCodeInstEmitter ) { DisasmLines . push_back ( MF -> getName ( ) . str ( ) + ":" ) ; DisasmLineMaxLen = std :: max ( DisasmLineMaxLen , DisasmLines . back ( ) . size ( ) ) ; HexLines . push_back ( "" ) ; } AsmPrinter :: emitFunctionEntryLabel ( ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .

AMDGPU AMDGPU SI SI 128 AMDGPU AMDGPU ":" ""


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getInstrInfo ( ) ) ; const MipsSubtarget & STI = TM . getSubtarget < MipsSubtarget > ( ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = TM . getSubtarget < MipsSubtarget > ( ) . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( TM . getSubtarget < MipsSubtarget > ( ) . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 2 4 Mips 2 16 4 0


<s> bool X86FrameLowering :: canUseLEAForSPInEpilogue ( const MachineFunction & MF ) const { return ! MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) || hasFP ( MF ) ; } </s>

Check that LEA can be used on SP in an epilogue sequence for MF .


<s> void NyuziInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( MI -> getOpcode ( ) == Nyuzi :: ORSSI && MI -> getOperand ( 0 ) . isReg ( ) && MI -> getOperand ( 0 ) . getReg ( ) == Nyuzi :: S0 && MI -> getOperand ( 1 ) . isReg ( ) && MI -> getOperand ( 1 ) . getReg ( ) == Nyuzi :: S0 && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { O << "\tnop" ; return ; } printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> const char * HexagonRelocator :: getName ( Relocation :: Type pType ) const { return ApplyFunctions [ pType ] . name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> unsigned getNumFixupKinds ( ) const { return 5 ; } </s>

Get the number of target specific fixup kinds .


<s> unsigned AMDGPUAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { AMDGPUOperand & Operand = ( AMDGPUOperand & ) Op ; switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_lds : return Operand . isLDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_glc : return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcB32 : return Operand . isSSrcB32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcF32 : return Operand . isSSrcF32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; case MCK_VReg32OrOff : return Operand . isVReg32OrOff ( ) ? Match_Success : Match_InvalidOperand ; case MCK_InterpSlot : return Operand . isInterpSlot ( ) ? Match_Success : Match_InvalidOperand ; case MCK_Attr : return Operand . isInterpAttr ( ) ? Match_Success : Match_InvalidOperand ; case MCK_AttrChan : return Operand . isAttrChan ( ) ? Match_Success : Match_InvalidOperand ; default : return Match_InvalidOperand ; } } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> void AMDGPUTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ; APInt KnownZero2 ; APInt KnownOne2 ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { case AMDGPUIntrinsic :: AMDGPU_imax : case AMDGPUIntrinsic :: AMDGPU_umax : case AMDGPUIntrinsic :: AMDGPU_imin : case AMDGPUIntrinsic :: AMDGPU_umin : computeKnownBitsForMinMax ( Op . getOperand ( 1 ) , Op . getOperand ( 2 ) , KnownZero , KnownOne , DAG , Depth ) ; break ; default : break ; } break ; } case AMDGPUISD :: SMAX : case AMDGPUISD :: UMAX : case AMDGPUISD :: SMIN : case AMDGPUISD :: UMIN : computeKnownBitsForMinMax ( Op . getOperand ( 0 ) , Op . getOperand ( 1 ) , KnownZero , KnownOne , DAG , Depth ) ; break ; case AMDGPUISD :: BFE_I32 : case AMDGPUISD :: BFE_U32 : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! CWidth ) return ; unsigned BitWidth = 32 ; uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ; if ( Opc == AMDGPUISD :: BFE_U32 ) KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ; break ; } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { HST = & MF . getSubtarget < HexagonSubtarget > ( ) ; HII = HST -> getInstrInfo ( ) ; HRI = HST -> getRegisterInfo ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>


<s>
SDValue
SparcTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
assert
(
0
&&
"Should not custom lower this!"
)
;
case
ISD
::
RETURNADDR
:
return
SDValue
(
)
;
case
ISD
::
FRAMEADDR
:
return
SDValue
(
)
;
case
ISD
::
GlobalTLSAddress
:
assert
(
0
&&
"TLS not implemented for Sparc."
)
;
case
ISD
::
GlobalAddress
:
return
LowerGLOBALADDRESS
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerCONSTANTPOOL
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_SINT
(
Op
,
DAG
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerSINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
*
this
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
CALL
:
return
LowerCALL
(
Op
,
DAG
)
;
case
ISD
::
RET
:
return
LowerRET
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


"emitEpilogue doesn't support framepointer-less functions"


"unexpected index-type in cris_print_index"

Print an index part of an address to file .


<s> static bool aarch64_pac_insn_p ( rtx x ) { if ( ! INSN_P ( x ) ) return false ; subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , PATTERN ( x ) , ALL ) { rtx sub = * iter ; if ( sub && GET_CODE ( sub ) == UNSPEC ) { int unspec_val = XINT ( sub , 1 ) ; switch ( unspec_val ) { case UNSPEC_PACIASP : case UNSPEC_PACIBSP : return true ; default : return false ; } iter . skip_subrtxes ( ) ; } } return false ; } </s>

Check if X ( or any sub-rtx of X ) is a PACIASP/PACIBSP instruction .


"AMDGPU Control Flow Graph structurizer Pass"

getPassName - Return a nice clean name for a pass .


<s> static int s390_issue_rate ( void ) { switch ( s390_tune ) { case PROCESSOR_2084_Z990 : case PROCESSOR_2094_Z9_109 : case PROCESSOR_2094_Z9_EC : case PROCESSOR_2817_Z196 : return 3 ; case PROCESSOR_2097_Z10 : return 2 ; case PROCESSOR_2064_Z900 : case PROCESSOR_2827_ZEC12 : case PROCESSOR_2964_Z13 : case PROCESSOR_3906_Z14 : case PROCESSOR_3931_Z16 : default : return 1 ; } } </s>

The number of instructions that can be issued per cycle .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = getDataLayout ( ) -> getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( Offset >= - ( 1LL << 9 ) && Offset <= ( 1LL << 9 ) - 1 ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } if ( ! AM . Scale || AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ) return true ; return false ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static rtx sparc_function_incoming_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { return sparc_function_arg_1 ( cum , mode , type , named , true ) ; } </s>

Handle the TARGET_FUNCTION_INCOMING_ARG target hook .


<s> void X86FrameLowering :: BuildCFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , const MCCFIInstruction & CFIInst , MachineInstr :: MIFlag Flag ) const { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFIIndex = MF . addFrameInst ( CFIInst ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( Flag ) ; } </s>

Wraps up getting a CFI index and building a MachineInstr for it .


<s> static unsigned HOST_WIDE_INT compute_current_alignment ( unsigned HOST_WIDE_INT base_align , unsigned HOST_WIDE_INT offset ) { if ( offset == 0 ) return base_align ; return min ( base_align , offset & - offset ) ; } </s>

Compute the alignment of pointer+OFFSET where the original alignment of pointer was BASE_ALIGN .


<s> bool PPCTTIImpl :: isHardwareLoopProfitable ( Loop * L , ScalarEvolution & SE , AssumptionCache & AC , TargetLibraryInfo * LibInfo , HardwareLoopInfo & HWLoopInfo ) { const PPCTargetMachine & TM = ST -> getTargetMachine ( ) ; TargetSchedModel SchedModel ; SchedModel . init ( ST ) ; unsigned ConstTripCount = SE . getSmallConstantTripCount ( L ) ; if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , 32 > EphValues ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( 6 * SchedModel . getIssueWidth ( ) ) ) return false ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo ) ) return false ; SmallVector < BasicBlock * , 4 > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { uint64_t TrueWeight = 0 , FalseWeight = 0 ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( 0 ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return false ; } } LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CountType = TM . isPPC64 ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType , 1 ) ; return true ; } </s>

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s>
static
uint8_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_XMM512
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_XMM256
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM128
:
\
case
TYPE_XMM64
:
\
case
TYPE_XMM32
:
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK1
:
\
case
TYPE_VK8
:
\
case
TYPE_VK16
:
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
case
TYPE_MM32
:
\
case
TYPE_MM
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_MM0
+
index
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
if
(
index
>
8
)
\
*
valid
=
0
;
\
return
prefix
##
_CR0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> const MCExpr * PPCTargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( ! Subtarget . isPPC64 ( ) || Subtarget . isAIXABI ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; default : return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s> void loongarch_expand_prologue ( void ) { struct loongarch_frame_info * frame = & cfun -> machine -> frame ; HOST_WIDE_INT size = frame -> total_size ; rtx insn ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( ( frame -> mask | frame -> fmask ) != 0 ) { HOST_WIDE_INT step1 = MIN ( size , loongarch_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; size -= step1 ; loongarch_for_each_saved_reg ( size , loongarch_save_reg ) ; } if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; loongarch_emit_stack_tie ( ) ; } if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { HOST_WIDE_INT first = get_stack_check_protect ( ) ; if ( frame -> total_size == 0 ) { dump_stack_clash_frame_info ( NO_PROBE_NO_FRAME , false ) ; return ; } if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { HOST_WIDE_INT interval ; if ( flag_stack_clash_protection ) interval = STACK_CLASH_PROTECTION_GUARD_SIZE ; else interval = PROBE_INTERVAL ; if ( size > interval && size > first ) loongarch_emit_probe_stack_range ( first , size - first ) ; else loongarch_emit_probe_stack_range ( first , size ) ; } else loongarch_emit_probe_stack_range ( first , size ) ; if ( size > 0 ) { insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ; insn = gen_rtx_SET ( stack_pointer_rtx , insn ) ; loongarch_set_frame_expr ( insn ) ; } return ; } if ( size > 0 ) { if ( IMM12_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = 1 ; } else { loongarch_emit_move ( LARCH_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , LARCH_PROLOGUE_TEMP ( Pmode ) ) ) ; insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ; insn = gen_rtx_SET ( stack_pointer_rtx , insn ) ; loongarch_set_frame_expr ( insn ) ; } } } </s>


"Alignment not a multiple of the instruction size:"

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned ShaderType = MF . getInfo < R600MachineFunctionInfo > ( ) -> ShaderType ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , DAG . getMachineFunction ( ) . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; EVT VT = Ins [ i ] . VT ; EVT MemVT = LocalIns [ i ] . VT ; if ( ShaderType != ShaderType :: COMPUTE ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; SDValue Arg = DAG . getExtLoad ( ISD :: SEXTLOAD , DL , VT , Chain , DAG . getConstant ( 36 + VA . getLocMemOffset ( ) , MVT :: i32 ) , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , MemVT , false , false , 4 ) ; InVals . push_back ( Arg ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static bool ix86_macro_fusion_pair_p ( rtx_insn * condgen , rtx_insn * condjmp ) { rtx src , dest ; enum rtx_code ccode ; rtx compare_set = NULL_RTX , test_if , cond ; rtx alu_set = NULL_RTX , addr = NULL_RTX ; if ( ! any_condjump_p ( condjmp ) ) return false ; if ( get_attr_type ( condgen ) != TYPE_TEST && get_attr_type ( condgen ) != TYPE_ICMP && get_attr_type ( condgen ) != TYPE_INCDEC && get_attr_type ( condgen ) != TYPE_ALU ) return false ; compare_set = single_set ( condgen ) ; if ( compare_set == NULL_RTX && ! TARGET_FUSE_ALU_AND_BRANCH ) return false ; if ( compare_set == NULL_RTX ) { int i ; rtx pat = PATTERN ( condgen ) ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set_src = SET_SRC ( XVECEXP ( pat , 0 , i ) ) ; if ( GET_CODE ( set_src ) == COMPARE ) compare_set = XVECEXP ( pat , 0 , i ) ; else alu_set = XVECEXP ( pat , 0 , i ) ; } } if ( compare_set == NULL_RTX ) return false ; src = SET_SRC ( compare_set ) ; if ( GET_CODE ( src ) != COMPARE ) return false ; if ( ( MEM_P ( XEXP ( src , 0 ) ) && CONST_INT_P ( XEXP ( src , 1 ) ) ) || ( MEM_P ( XEXP ( src , 1 ) ) && CONST_INT_P ( XEXP ( src , 0 ) ) ) ) return false ; if ( MEM_P ( XEXP ( src , 0 ) ) ) addr = XEXP ( XEXP ( src , 0 ) , 0 ) ; else if ( MEM_P ( XEXP ( src , 1 ) ) ) addr = XEXP ( XEXP ( src , 1 ) , 0 ) ; if ( addr ) { ix86_address parts ; int ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; if ( rip_relative_addr_p ( & parts ) ) return false ; } test_if = SET_SRC ( pc_set ( condjmp ) ) ; cond = XEXP ( test_if , 0 ) ; ccode = GET_CODE ( cond ) ; if ( ! TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS && ( ccode == GE || ccode == GT || ccode == LE || ccode == LT ) ) return false ; if ( get_attr_type ( condgen ) == TYPE_TEST || get_attr_type ( condgen ) == TYPE_ICMP ) return true ; if ( ! TARGET_FUSE_ALU_AND_BRANCH || ! alu_set ) return false ; dest = SET_DEST ( alu_set ) ; if ( MEM_P ( dest ) ) return false ; if ( get_attr_type ( condgen ) == TYPE_INCDEC && ( ccode == GEU || ccode == GTU || ccode == LEU || ccode == LTU ) ) return false ; return true ; } </s>

Check whether current microarchitecture support macro fusion for insn pair `` CONDGEN + CONDJMP '' . Refer to `` Intel Architectures Optimization Reference Manual '' .


"RISCV DAG->DAG Pattern Instruction Selection"


<s> static rtx s390_legitimize_cs_operand ( rtx mem ) { rtx tmp ; if ( ! contains_symbol_ref_p ( mem ) ) return mem ; tmp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tmp , copy_rtx ( XEXP ( mem , 0 ) ) ) ; return change_address ( mem , VOIDmode , tmp ) ; } </s>

If MEM is not a legitimate compare-and-swap memory operand , return a new MEM , whose address is a pseudo containing the original MEM 's address .


<s> static void ia64_clear_sched_context ( void * _sc ) { ia64_sched_context_t sc = ( ia64_sched_context_t ) _sc ; free ( sc -> prev_cycle_state ) ; sc -> prev_cycle_state = NULL ; } </s>

Clears the data in the _SC scheduling context .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


"MIa must load from or modify a memory location"

"MIb must load from or modify a memory location"

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) ) FJ ++ ; if ( FJ == F . end ( ) ) return Changed ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FJ != FE ; ++ FI , ++ FJ ) { Changed |= runOnMachineBasicBlock ( * FI , * FJ ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AMDGPUTargetLowering :: ShouldShrinkFPConstant ( EVT VT ) const { EVT ScalarVT = VT . getScalarType ( ) ; return ( ScalarVT != MVT :: f32 && ScalarVT != MVT :: f64 ) ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


<s> StringRef getData ( ) const { return StringRef ( Data . data ( ) , Data . size ( ) ) ; } </s>

Get the data pointed to by this extractor .


<s> void RISCVFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


Initialize the table of extra 80387 mathematical constants .


<s> rtx mep_libcall_value ( machine_mode mode ) { return gen_rtx_REG ( mode , RETURN_VALUE_REGNUM ) ; } </s>

Implement LIBCALL_VALUE , using the same rules as mep_function_value .


<s> int riscv_address_insns ( rtx x , machine_mode mode , bool might_split_p ) { struct riscv_address_info addr = { } ; int n = 1 ; if ( ! riscv_classify_address ( & addr , x , mode , false ) ) { return 3 ; } if ( ! riscv_v_ext_vector_mode_p ( mode ) && mode != BLKmode && might_split_p ) n += ( GET_MODE_SIZE ( mode ) . to_constant ( ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( addr . type == ADDRESS_LO_SUM ) n += riscv_symbol_insns ( addr . symbol_type ) - 1 ; return n ; } </s>

Return the number of instructions needed to load or store a value of mode MODE at address X . Return 0 if X is n't valid for MODE . Assume that multiword moves may need to be split into word moves if MIGHT_SPLIT_P , otherwise assume that a single load or store is enough .


<s> static SDValue buildRSRC ( SelectionDAG * DAG , SDLoc DL , SDValue Ptr , uint32_t RsrcDword1 , uint64_t RsrcDword2And3 ) { SDValue PtrLo = DAG -> getTargetExtractSubreg ( AMDGPU :: sub0 , DL , MVT :: i32 , Ptr ) ; SDValue PtrHi = DAG -> getTargetExtractSubreg ( AMDGPU :: sub1 , DL , MVT :: i32 , Ptr ) ; if ( RsrcDword1 ) PtrHi = SDValue ( DAG -> getMachineNode ( AMDGPU :: S_OR_B32 , DL , MVT :: i32 , PtrHi , DAG -> getConstant ( RsrcDword1 , MVT :: i32 ) ) , 0 ) ; SDValue DataLo = DAG -> getTargetConstant ( RsrcDword2And3 & APInt :: getAllOnesValue ( 32 ) . getZExtValue ( ) , MVT :: i32 ) ; SDValue DataHi = DAG -> getTargetConstant ( RsrcDword2And3 >> 32 , MVT :: i32 ) ; const SDValue Ops [ ] = { PtrLo , PtrHi , DataLo , DataHi } ; return SDValue ( DAG -> getMachineNode ( AMDGPU :: SI_BUFFER_RSRC , DL , MVT :: v4i32 , Ops ) , 0 ) ; } </s>

Return a resource descriptor with the 'Add TID ' bit enabled The TID ( Thread ID ) is multiplied by the stride value ( bits [ 61:48 ] of the resource descriptor ) to create an offset , which is added to the resource pointer .


"%qE attribute not available to functions with arguments "

"%qE attribute not available to functions with variable number "

"%qE attribute not available to functions that return value on "

This function returns true if a function with declaration FNDECL and type FNTYPE uses the stack to pass arguments or return variables and false otherwise . This is used for functions with the attributes 'cmse_nonsecure_call ' or 'cmse_nonsecure_entry ' and this function will issue diagnostic messages if the stack is used . NAME is the name of the attribute used .


<s> bool PatmosFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * STC . getInstrInfo ( ) ; PatmosMachineFunctionInfo & PMFI = * MF . getInfo < PatmosMachineFunctionInfo > ( ) ; if ( hasFP ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Patmos :: MOV ) , Patmos :: RSP ) ) . addReg ( Patmos :: RFP ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; unsigned tmpReg = Reg ; if ( Patmos :: PRegsRegClass . contains ( Reg ) ) continue ; if ( Reg == Patmos :: S0 && PMFI . getS0SpillReg ( ) ) { TII . copyPhysReg ( MBB , MI , DL , Reg , PMFI . getS0SpillReg ( ) , true ) ; std :: prev ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; continue ; } if ( Patmos :: SRegsRegClass . contains ( Reg ) ) tmpReg = Patmos :: R9 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( tmpReg ) ; TII . loadRegFromStackSlot ( MBB , MI , tmpReg , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; std :: prev ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; if ( tmpReg != Reg ) { TII . copyPhysReg ( MBB , MI , DL , Reg , tmpReg , true ) ; std :: prev ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static rtx nvptx_function_incoming_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( mode == VOIDmode || ! named ) return NULL_RTX ; return gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , GEN_INT ( cum -> count ) ) , UNSPEC_ARG_REG ) ; } </s>


<s> bool MBlazeRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool function_instance :: could_trap_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( CP_READ_MEMORY | CP_WRITE_MEMORY ) ) return true ; return false ; } </s>

Return true if calls to the function could raise a signal .


<s> int reg_unused_after ( rtx_insn * insn , rtx reg ) { return ( dead_or_set_p ( insn , reg ) || ( REG_P ( reg ) && _reg_unused_after ( insn , reg ) ) ) ; } </s>

Return nonzero if REG is not used after INSN . We assume REG is a reload reg , and therefore does not live past labels or calls or jumps .


<s> static int first_altivec_reg_to_save ( void ) { int i ; if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + 1 ; if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) return FIRST_ALTIVEC_REGNO + 20 ; for ( i = FIRST_ALTIVEC_REGNO + 20 ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( save_reg_p ( i ) ) break ; return i ; } </s>


<s> rtx function_expander :: use_scalar_move_insn ( insn_code icode ) { machine_mode mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; int arg_offset = 0 ; add_scalar_move_mask_operand ( mask_mode ( ) ) ; if ( use_real_merge_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_vundef_operand ( mode ) ; for ( int argno = arg_offset ; argno < call_expr_nargs ( exp ) ; argno ++ ) add_input_operand ( argno ) ; add_input_operand ( Pmode , get_tail_policy_for_pred ( pred ) ) ; add_input_operand ( Pmode , get_mask_policy_for_pred ( pred ) ) ; add_input_operand ( Pmode , get_avl_type_rtx ( avl_type :: NONVLMAX ) ) ; return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , with a 1:1 mapping between arguments and input operands .


<s> virtual bool addPreEmitPass ( ) { if ( ! getPatmosSubtarget ( ) . usePatmosPostRAScheduler ( getOptLevel ( ) ) ) { addPass ( createPatmosDelaySlotFillerPass ( getPatmosTargetMachine ( ) , getOptLevel ( ) == CodeGenOpt :: None ) ) ; } if ( getPatmosSubtarget ( ) . hasMethodCache ( ) ) { addPass ( createPatmosFunctionSplitterPass ( getPatmosTargetMachine ( ) ) ) ; } addPass ( createPatmosDelaySlotKillerPass ( getPatmosTargetMachine ( ) ) ) ; addPass ( createPatmosEnsureAlignmentPass ( getPatmosTargetMachine ( ) ) ) ; addPass ( createPatmosBypassFromPMLPass ( getPatmosTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips Machine Code Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void OutgoingValueHandler :: assignValueToReg ( unsigned ValVReg , unsigned PhysReg ) { MIRBuilder . buildCopy ( PhysReg , ValVReg ) ; MIB . addUse ( PhysReg , RegState :: Implicit ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> bool SystemZFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static void ultrasparc_sched_init ( ) { memset ( ( char * ) ultra_pipe_hist , 0 , sizeof ultra_pipe_hist ) ; ultra_cur_hist = 0 ; ultra_cycles_elapsed = 0 ; ultra_pipe . free_slot_mask = 0xf ; } </s>

Init our data structures for this current block .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s>
static
void
ix86_avoid_jump_mispredicts
(
void
)
{
rtx_insn
*
insn
,
*
start
=
get_insns
(
)
;
int
nbytes
=
0
,
njumps
=
0
;
bool
isjump
=
false
;
for
(
insn
=
start
;
insn
;
insn
=
NEXT_INSN
(
insn
)
)
{
int
min_size
;
if
(
LABEL_P
(
insn
)
)
{
int
align
=
label_to_alignment
(
insn
)
;
int
max_skip
=
label_to_max_skip
(
insn
)
;
if
(
max_skip
>
15
)
max_skip
=
15
;
if
(
align
<=
0
||
(
align
<=
3
&&
max_skip
!=
(
1
<<
align
)
1
)
)
max_skip
=
0
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Label %i with max_skip %i\n"
,
INSN_UID
(
insn
)
,
max_skip
)
;
if
(
max_skip
)
{
while
(
nbytes
+
max_skip
>=
16
)
{
start
=
NEXT_INSN
(
start
)
;
if
(
(
JUMP_P
(
start
)
&&
asm_noperands
(
PATTERN
(
start
)
)
<
0
)
||
CALL_P
(
start
)
)
njumps
,
isjump
=
true
;
else
isjump
=
false
;
nbytes
-=
ix86_min_insn_size
(
start
)
;
}
}
continue
;
}
min_size
=
ix86_min_insn_size
(
insn
)
;
nbytes
+=
min_size
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Insn %i estimated to %i bytes\n"
,
INSN_UID
(
insn
)
,
min_size
)
;
if
(
(
JUMP_P
(
insn
)
&&
asm_noperands
(
PATTERN
(
insn
)
)
<
0
)
||
CALL_P
(
insn
)
)
njumps
++
;
else
continue
;
while
(
njumps
>
3
)
{
start
=
NEXT_INSN
(
start
)
;
if
(
(
JUMP_P
(
start
)
&&
asm_noperands
(
PATTERN
(
start
)
)
<
0
)
||
CALL_P
(
start
)
)
njumps
,
isjump
=
true
;
else
isjump
=
false
;
nbytes
-=
ix86_min_insn_size
(
start
)
;
}
gcc_assert
(
njumps
>=
0
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Interval %i to %i has %i bytes\n"
,
INSN_UID
(
start
)
,
INSN_UID
(
insn
)
,
nbytes
)
;
if
(
njumps
==
3
&&
isjump
&&
nbytes
<
16
)
{
int
padsize
=
15
nbytes
+
ix86_min_insn_size
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Padding insn %i by %i bytes!\n"
,
INSN_UID
(
insn
)
,
padsize
)
;
emit_insn_before
(
gen_pad
(
GEN_INT
(
padsize
)
)
,
insn
)
;
}
}
}
</s>

AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte window .