<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
MLI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
if
(
Packetizer
.
getResourceTracker
(
)
->
getInstrItins
(
)
->
isEmpty
(
)
)
return
false
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
||
MI
->
getOpcode
(
)
==
AMDGPU
::
IMPLICIT_DEF
||
(
MI
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU
&&
!
MI
->
getOperand
(
8
)
.
getImm
(
)
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
&
*
std
::
prev
(
I
)
,
&
*
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
&
*
MBB
,
&
*
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool SIAnnotateControlFlow :: runOnFunction ( Function & F ) { DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; for ( df_iterator < BasicBlock * > I = df_begin ( & F . getEntryBlock ( ) ) , E = df_end ( & F . getEntryBlock ( ) ) ; I != E ; ++ I ) { BranchInst * Term = dyn_cast < BranchInst > ( ( * I ) -> getTerminator ( ) ) ; if ( ! Term || Term -> isUnconditional ( ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; continue ; } if ( I . nodeVisited ( Term -> getSuccessor ( 1 ) ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; handleLoop ( Term ) ; continue ; } if ( isTopOfStack ( * I ) ) { PHINode * Phi = dyn_cast < PHINode > ( Term -> getCondition ( ) ) ; if ( Phi && Phi -> getParent ( ) == * I && isElse ( Phi ) ) { insertElse ( Term ) ; eraseIfUnused ( Phi ) ; continue ; } closeControlFlow ( * I ) ; } openIf ( Term ) ; } assert ( Stack . empty ( ) ) ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && ! Subtarget -> isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new ARMFastISel ( funcInfo , libInfo ) ; } return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s>
bool
BPFAsmPrinter
::
doInitialization
(
Module
&
M
)
{
AsmPrinter
::
doInitialization
(
M
)
;
if
(
MAI
->
doesSupportDebugInformation
(
)
&&
!
M
.
debug_compile_units
(
)
.
empty
(
)
)
{
BTF
=
new
BTFDebug
(
this
)
;
Handlers
.
push_back
(
HandlerInfo
(
std
::
unique_ptr
<
BTFDebug
>
(
BTF
)
,
"emit"
,
"Debug Info Emission"
,
"BTF"
,
"BTF Emission"
)
)
;
}
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

BPF
BPF
"emit"
"Debug Info Emission"
"BTF"
"BTF Emission"


<s> void MOSInstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & NewDestBB , MachineBasicBlock & RestoreBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { MachineIRBuilder Builder ( MBB , MBB . end ( ) ) ; Builder . setDebugLoc ( DL ) ; Builder . buildInstr ( MOS :: JMP ) . addMBB ( & NewDestBB ) ; } </s>

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> static bool pa_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( from == to ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return true ; if ( ! GET_MODE_SIZE ( from ) || ! GET_MODE_SIZE ( to ) ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return TARGET_64BIT && from == DImode && to == SImode ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return false ; return true ; } </s>


<s> virtual const WDC65816Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> hasFnAttr ( Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && N -> getOpcode ( ) == X86ISD :: CALL ) { SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain ) ) continue ; MoveBelowCallSeqStart ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , NULL , 0 , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , NULL , 0 , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s>
void
MipsInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
Mips
::
CPURegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Mips
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
ADDu
,
ZeroReg
=
Mips
::
ZERO
;
else
if
(
Mips
::
CCRRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
CFC1
;
else
if
(
Mips
::
FGR32RegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
MFC1
;
else
if
(
SrcReg
==
Mips
::
HI
)
Opc
=
Mips
::
MFHI
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Mips
::
LO
)
Opc
=
Mips
::
MFLO
,
SrcReg
=
0
;
}
else
if
(
Mips
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
Mips
::
CCRRegClass
.
contains
(
DestReg
)
)
Opc
=
Mips
::
CTC1
;
else
if
(
Mips
::
FGR32RegClass
.
contains
(
DestReg
)
)
Opc
=
Mips
::
MTC1
;
else
if
(
DestReg
==
Mips
::
HI
)
Opc
=
Mips
::
MTHI
,
DestReg
=
0
;
else
if
(
DestReg
==
Mips
::
LO
)
Opc
=
Mips
::
MTLO
,
DestReg
=
0
;
}
else
if
(
Mips
::
FGR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
Mips
::
FMOV_S
;
else
if
(
Mips
::
AFGR64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
Mips
::
FMOV_D32
;
else
if
(
Mips
::
CCRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
Mips
::
MOVCCRToCCR
;
else
if
(
Mips
::
CPU64RegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Mips
::
CPU64RegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
DADDu
,
ZeroReg
=
Mips
::
ZERO_64
;
else
if
(
SrcReg
==
Mips
::
HI64
)
Opc
=
Mips
::
MFHI64
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Mips
::
LO64
)
Opc
=
Mips
::
MFLO64
,
SrcReg
=
0
;
}
else
if
(
Mips
::
CPU64RegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
Mips
::
HI64
)
Opc
=
Mips
::
MTHI64
,
DestReg
=
0
;
else
if
(
DestReg
==
Mips
::
LO64
)
Opc
=
Mips
::
MTLO64
,
DestReg
=
0
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : if ( MI -> getOperand ( 1 ) . isImm ( ) && ! MI -> getOperand ( 1 ) . getImm ( ) && MI -> getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> const R600InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> void moxie_print_operand_address ( FILE * file , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : fprintf ( file , "(%s)" , reg_names [ REGNO ( x ) ] ) ; break ; case PLUS : switch ( GET_CODE ( XEXP ( x , 1 ) ) ) { case CONST_INT : fprintf ( file , "%ld(%s)" , INTVAL ( XEXP ( x , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; break ; case SYMBOL_REF : output_addr_const ( file , XEXP ( x , 1 ) ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; break ; case CONST : { rtx plus = XEXP ( XEXP ( x , 1 ) , 0 ) ; if ( GET_CODE ( XEXP ( plus , 0 ) ) == SYMBOL_REF && CONST_INT_P ( XEXP ( plus , 1 ) ) ) { output_addr_const ( file , XEXP ( plus , 0 ) ) ; fprintf ( file , "+%ld(%s)" , INTVAL ( XEXP ( plus , 1 ) ) , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; } else abort ( ) ; } break ; default : abort ( ) ; } break ; default : output_addr_const ( file , x ) ; break ; } } </s>


<s> Value * AArch64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxp : Intrinsic :: aarch64_ldxp ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: aarch64_ldaxr : Intrinsic :: aarch64_ldxr ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldxr , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> InstructionCost ARMTTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * ValTy , bool IsPairwiseForm , TTI :: TargetCostKind CostKind ) { EVT ValVT = TLI -> getValueType ( DL , ValTy ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ValVT . isSimple ( ) || ISD != ISD :: ADD ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; static const CostTblEntry CostTblAdd [ ] { { ISD :: ADD , MVT :: v16i8 , 1 } , { ISD :: ADD , MVT :: v8i16 , 1 } , { ISD :: ADD , MVT :: v4i32 , 1 } , } ; if ( const auto * Entry = CostTableLookup ( CostTblAdd , ISD , LT . second ) ) return Entry -> Cost * ST -> getMVEVectorCostFactor ( CostKind ) * LT . first ; return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; } </s>

Calculate the cost of vector reduction intrinsics .


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


<s> static void ix86_emit_restore_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return ) ) { rtx reg = gen_rtx_REG ( V4SFmode , regno ) ; rtx mem ; unsigned int align ; mem = choose_baseaddr ( cfa_offset ) ; mem = gen_rtx_MEM ( V4SFmode , mem ) ; align = MIN ( GET_MODE_ALIGNMENT ( V4SFmode ) , INCOMING_STACK_BOUNDARY ) ; set_mem_align ( mem , align ) ; emit_insn ( gen_rtx_SET ( reg , mem ) ) ; ix86_add_cfa_restore_note ( NULL , reg , cfa_offset ) ; cfa_offset -= GET_MODE_SIZE ( V4SFmode ) ; } } </s>

Emit code to restore saved registers using MOV insns . First register is restored from CFA - CFA_OFFSET .


<s> void sparc_emit_fixunsdi ( rtx * operands , machine_mode mode ) { rtx i0 , i1 , f0 , in , out , limit ; out = operands [ 0 ] ; in = force_reg ( mode , operands [ 1 ] ) ; rtx_code_label * neglab = gen_label_rtx ( ) ; rtx_code_label * donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; limit = gen_reg_rtx ( mode ) ; f0 = gen_reg_rtx ( mode ) ; emit_move_insn ( limit , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( "9223372036854775808.0" , mode ) , mode ) ) ; emit_cmp_and_jump_insns ( in , limit , GE , NULL_RTX , mode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , in ) ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , f0 , gen_rtx_MINUS ( mode , in , limit ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , i0 , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , f0 ) ) ) ) ; emit_insn ( gen_movdi ( i1 , const1_rtx ) ) ; emit_insn ( gen_ashldi3 ( i1 , i1 , GEN_INT ( 63 ) ) ) ; emit_insn ( gen_xordi3 ( out , i0 , i1 ) ) ; emit_label ( donelab ) ; } </s>

Generate an FP to unsigned DImode conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> static inline HOST_WIDE_INT htm_spr_num ( enum rs6000_gen_builtins code ) { if ( code == RS6000_BIF_GET_TFHAR || code == RS6000_BIF_SET_TFHAR ) return TFHAR_SPR ; else if ( code == RS6000_BIF_GET_TFIAR || code == RS6000_BIF_SET_TFIAR ) return TFIAR_SPR ; else if ( code == RS6000_BIF_GET_TEXASR || code == RS6000_BIF_SET_TEXASR ) return TEXASR_SPR ; gcc_assert ( code == RS6000_BIF_GET_TEXASRU || code == RS6000_BIF_SET_TEXASRU ) ; return TEXASRU_SPR ; } </s>

Return the appropriate SPR number associated with the given builtin .


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
val
=
;
char
buf
[
128
]
;
FILE
*
f
=
;
bool
arch
;
const
struct
vendor_cpu
*
cpu_table
=
;
if
(
argc
<
1
)
goto
not_found
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"cpu"
)
!=
0
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
goto
not_found
;
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
goto
not_found
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
{
if
(
strncmp
(
buf
,
"CPU implementer"
,
sizeof
(
"CPU implementer"
)
1
)
==
0
)
{
int
i
;
for
(
i
=
0
;
vendors
[
i
]
.
vendor_no
!=
;
i
++
)
if
(
strstr
(
buf
,
vendors
[
i
]
.
vendor_no
)
!=
)
{
cpu_table
=
vendors
[
i
]
.
vendor_parts
;
break
;
}
}
if
(
strncmp
(
buf
,
"CPU part"
,
sizeof
(
"CPU part"
)
1
)
==
0
)
{
int
i
;
if
(
cpu_table
==
)
goto
not_found
;
for
(
i
=
0
;
cpu_table
[
i
]
.
part_no
!=
;
i
++
)
if
(
strstr
(
buf
,
cpu_table
[
i
]
.
part_no
)
!=
)
{
val
=
arch
cpu_table
[
i
]
.
arch_name
:
cpu_table
[
i
]
.
cpu_name
;
break
;
}
break
;
}
}
fclose
(
f
)
;
if
(
val
==
)
goto
not_found
;
return
concat
(
"-m"
,
argv
[
0
]
,
"="
,
val
,
)
;
not_found
:
{
unsigned
int
i
;
unsigned
int
opt
;
const
char
*
search
[
]
=
{
,
"arch"
}
;
if
(
f
)
fclose
(
f
)
;
search
[
0
]
=
argv
[
0
]
;
for
(
opt
=
0
;
opt
<
ARRAY_SIZE
(
search
)
;
opt
++
)
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
configure_default_options
)
;
i
++
)
if
(
strcmp
(
configure_default_options
[
i
]
.
name
,
search
[
opt
]
)
==
0
)
return
concat
(
"-m"
,
search
[
opt
]
,
"="
,
configure_default_options
[
i
]
.
value
,
)
;
return
;
}
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


"Cannot store this register to stack slot!"


<s> void ix86_split_convert_uns_si_sse ( rtx operands [ ] ) { machine_mode vecmode ; rtx value , large , zero_or_two31 , input , two31 , x ; large = operands [ 1 ] ; zero_or_two31 = operands [ 2 ] ; input = operands [ 3 ] ; two31 = operands [ 4 ] ; vecmode = GET_MODE ( large ) ; value = gen_rtx_REG ( vecmode , REGNO ( operands [ 0 ] ) ) ; if ( MEM_P ( input ) ) { if ( vecmode == V4SFmode ) emit_insn ( gen_vec_setv4sf_0 ( value , CONST0_RTX ( V4SFmode ) , input ) ) ; else emit_insn ( gen_sse2_loadlpd ( value , CONST0_RTX ( V2DFmode ) , input ) ) ; } else { input = gen_rtx_REG ( vecmode , REGNO ( input ) ) ; emit_move_insn ( value , CONST0_RTX ( vecmode ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_sse_movss ( value , value , input ) ) ; else emit_insn ( gen_sse2_movsd ( value , value , input ) ) ; } emit_move_insn ( large , two31 ) ; emit_move_insn ( zero_or_two31 , MEM_P ( two31 ) ? large : two31 ) ; x = gen_rtx_fmt_ee ( LE , vecmode , large , value ) ; emit_insn ( gen_rtx_SET ( large , x ) ) ; x = gen_rtx_AND ( vecmode , zero_or_two31 , large ) ; emit_insn ( gen_rtx_SET ( zero_or_two31 , x ) ) ; x = gen_rtx_MINUS ( vecmode , value , zero_or_two31 ) ; emit_insn ( gen_rtx_SET ( value , x ) ) ; large = gen_rtx_REG ( V4SImode , REGNO ( large ) ) ; emit_insn ( gen_ashlv4si3 ( large , large , GEN_INT ( 31 ) ) ) ; x = gen_rtx_REG ( V4SImode , REGNO ( value ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_fix_truncv4sfv4si2 ( x , value ) ) ; else emit_insn ( gen_sse2_cvttpd2dq ( x , value ) ) ; value = x ; emit_insn ( gen_xorv4si3 ( value , value , large ) ) ; } </s>

Post-reload splitter for converting an SF or DFmode value in an SSE register into an unsigned SImode .


<s> void WebAssemblyFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const auto * TII = static_cast < const WebAssemblyInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc DL = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; unsigned Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( Amount ) adjustStackPointer ( Amount , IsDestroy , MF , MBB , TII , I , DL ) ; MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"%qE attribute only applies to interrupt functions"

Generate 'handle_interrupt ' attribute for decls


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> getFnAttributes ( ) . hasNoImplicitFloatAttr ( ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> getStackAlignment ( ) >= 32 ) { if ( Subtarget -> hasAVX2 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasAVX ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { Register Reg = I . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , I . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) override { const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF , 1 ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , MVT :: i32 ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op , RC ) , 0 ) ; OutOps . push_back ( NewOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


"There must be a free register after frame setup"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , * Subtarget -> getRegisterInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData = false ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s>
StringRef
getPassName
(
)
const
override
{
return
"XCore Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
LM32InstPrinter
::
printSymbol
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
,
bool
hi
)
const
{
assert
(
(
MI
->
getOperand
(
OpNo
)
.
isImm
(
)
||
MI
->
getOperand
(
OpNo
)
.
isExpr
(
)
)
&&
"Unknown symbol operand"
)
;
O
<<
(
hi
"hi"
:
"lo"
)
<<
"("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
')'
;
}
</s>

LM32
LM32
"Unknown symbol operand"
"hi"
"lo"
"("


"without AVX512F enabled changes the ABI"

Return the `` natural '' mode for TYPE . In most cases , this is just TYPE_MODE . But in the case of vector types , it is some vector mode . When we have only some of our vector isa extensions enabled , then there are some modes for which vector_mode_supported_p is false . For these modes , the generic vector support in gcc will choose some non-vector mode in order to implement the type . By computing the natural mode , we 'll select the proper ABI location for the operand and not depend on whatever the middle-end decides to do with these vector types .


<s> const Cpu0FrameLowering * Cpu0FrameLowering :: create ( const Cpu0Subtarget & ST ) { return llvm :: createCpu0SEFrameLowering ( ST ) ; } </s>


<s> static unsigned riscv_pass_aggregate_in_fpr_pair_p ( const_tree type , riscv_aggregate_field fields [ 2 ] ) { int n = riscv_flatten_aggregate_argument ( type , fields ) ; for ( int i = 0 ; i < n ; i ++ ) if ( ! SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ) return 0 ; return n > 0 ? n : 0 ; } </s>

See whether TYPE is a record whose fields should be returned in one or two floating-point registers . If so , populate FIELDS accordingly .


<s> static void preprocess_args ( int * p_argc , char * argv [ ] ) { int i ; for ( i = 1 ; i < * p_argc ; i ++ ) { if ( strcmp ( argv [ i ] , "-o" ) == 0 ) { char * buff , * ptr ; i ++ ; ptr = to_host_file_spec ( argv [ i ] ) ; objfilename = xstrdup ( ptr ) ; buff = concat ( "/obj=" , ptr , NULL ) ; addarg ( buff ) ; } } } </s>

Preprocess the number of args P_ARGC in ARGV . Look for special flags , etc . that must be handled first .


<s> unsigned SIRegisterInfo :: getRegPressureSetLimit ( const MachineFunction & MF , unsigned Idx ) const { const AMDGPUSubtarget & STI = MF . getSubtarget < AMDGPUSubtarget > ( ) ; unsigned SGPRLimit = getNumSGPRsAllowed ( STI . getGeneration ( ) , STI . getMaxWavesPerCU ( ) ) ; unsigned VGPRLimit = getNumVGPRsAllowed ( STI . getMaxWavesPerCU ( ) ) ; for ( regclass_iterator I = regclass_begin ( ) , E = regclass_end ( ) ; I != E ; ++ I ) { unsigned NumSubRegs = std :: max ( ( int ) ( * I ) -> getSize ( ) / 4 , 1 ) ; unsigned Limit ; if ( isSGPRClass ( * I ) ) { Limit = SGPRLimit / NumSubRegs ; } else { Limit = VGPRLimit / NumSubRegs ; } const int * Sets = getRegClassPressureSets ( * I ) ; assert ( Sets ) ; for ( unsigned i = 0 ; Sets [ i ] != - 1 ; ++ i ) { if ( Sets [ i ] == ( int ) Idx ) return Limit ; } } return 256 ; } </s>

Get the register unit pressure limit for this dimension .


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { SectionKind Kind = CPE . getSectionKind ( TM . getDataLayout ( ) ) ; const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> void WDC65816TargetAsmStreamer :: EmitInstruction ( StringRef instruction ) { instruction = instruction . ltrim ( ) ; OS << indent ; OS << instruction ; OS << '\n' ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void push ( struct unw_state_record * sr ) { struct unw_reg_state * rs = alloc_reg_state ( ) ; memcpy ( rs , & sr -> curr , sizeof ( * rs ) ) ; sr -> curr . next = rs ; } </s>

Output RTL to push register RN onto the stack .


<s> void ix86_emit_i387_atanh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx half = const_double_from_real_value ( dconsthalf , XFmode ) ; rtx cst1 , tmp ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx_insn * insn ; emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_absxf2 ( e2 , op1 ) ) ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( e1 , e2 , cst1 ) ) ; emit_insn ( gen_addxf3 ( e2 , e2 , e2 ) ) ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_insn ( gen_divxf3 ( e1 , e2 , e1 ) ) ; ix86_emit_i387_log1p ( e2 , e1 ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( 0x02 ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = 1 ; half = force_reg ( XFmode , half ) ; emit_insn ( gen_mulxf3 ( op0 , e2 , half ) ) ; } </s>

Output code to perform an atanh XFmode calculation .


<s> static void h8300_print_operand_address ( FILE * file , rtx addr ) { rtx index ; int size ; switch ( GET_CODE ( addr ) ) { case REG : fprintf ( file , "%s" , h8_reg_names [ REGNO ( addr ) ] ) ; break ; case PRE_DEC : fprintf ( file , "-%s" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( file , "%s+" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case PRE_INC : fprintf ( file , "+%s" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case POST_DEC : fprintf ( file , "%s-" , h8_reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case PLUS : fprintf ( file , "(" ) ; index = h8300_get_index ( XEXP ( addr , 0 ) , VOIDmode , & size ) ; if ( GET_CODE ( index ) == REG ) { h8300_print_operand_address ( file , XEXP ( addr , 1 ) ) ; fprintf ( file , "," ) ; switch ( size ) { case 0 : h8300_print_operand_address ( file , index ) ; break ; case 1 : h8300_print_operand ( file , index , 'X' ) ; fputs ( ".b" , file ) ; break ; case 2 : h8300_print_operand ( file , index , 'T' ) ; fputs ( ".w" , file ) ; break ; case 4 : h8300_print_operand ( file , index , 'S' ) ; fputs ( ".l" , file ) ; break ; } } else { h8300_print_operand_address ( file , XEXP ( addr , 0 ) ) ; fprintf ( file , "+" ) ; h8300_print_operand_address ( file , XEXP ( addr , 1 ) ) ; } fprintf ( file , ")" ) ; break ; case CONST_INT : { int n = INTVAL ( addr ) ; if ( TARGET_H8300 ) n = ( int ) ( short ) n ; fprintf ( file , "%d" , n ) ; break ; } default : output_addr_const ( file , addr ) ; break ; } } </s>

Output assembly language output for the address ADDR to FILE .


<s> int cr16_operand_bit_pos ( int val , int bitval ) { int i ; if ( bitval == 0 ) val = ~ val ; for ( i = 0 ; i < 16 ; i ++ ) if ( val & ( 1 << i ) ) break ; return i ; } </s>

Returns bit position of first 0 or 1 bit . It is safe to assume val as 16-bit wide .


<s>
SDValue
CAHPTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
if
(
IsVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_CAHP
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
CAHPISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> rtx aarch64_eh_return_handler_rtx ( void ) { rtx tmp = gen_frame_mem ( Pmode , plus_constant ( Pmode , hard_frame_pointer_rtx , UNITS_PER_WORD ) ) ; MEM_VOLATILE_P ( tmp ) = true ; return tmp ; } </s>

Implement EH_RETURN_HANDLER_RTX . EH returns need to either return normally or return to a previous frame after unwinding . An EH return uses a single shared return sequence . The epilogue is exactly like a normal epilogue except that it has an extra input register ( EH_RETURN_STACKADJ_RTX ) which contains the stack adjustment that must be applied after the frame has been destroyed . An extra label is inserted before the epilogue which initializes this register to zero , and this is the entry point for a normal return . An actual EH return updates the return address , initializes the stack adjustment and jumps directly into the epilogue ( bypassing the zeroing of the adjustment ) . Since the return address is typically saved on the stack when a function makes a call , the saved LR must be updated outside the epilogue . This poses problems as the store is generated well before the epilogue , so the offset of LR is not known yet . Also optimizations will remove the store as it appears dead , even after the epilogue is generated ( as the base or offset for loading LR is different in many cases ) . To avoid these problems this implementation forces the frame pointer in eh_return functions so that the location of LR is fixed and known early . It also marks the store volatile , so no optimization is permitted to remove the store .


<s>
SDValue
PatmosTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Patmos
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
unsigned
Opc
=
PatmosISD
::
RET_FLAG
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>


<s> static void gen_ashift ( int type , int n , rtx reg ) { rtx n_rtx ; if ( n < 0 ) { if ( type == ASHIFT ) type = LSHIFTRT ; else type = ASHIFT ; n = - n ; } n_rtx = GEN_INT ( n ) ; gcc_assert ( satisfies_constraint_P27 ( n_rtx ) ) ; switch ( type ) { case ASHIFTRT : emit_insn ( gen_ashrsi3_k ( reg , reg , n_rtx ) ) ; break ; case LSHIFTRT : if ( n == 1 ) emit_insn ( gen_shlr ( reg , reg ) ) ; else emit_insn ( gen_lshrsi3_k ( reg , reg , n_rtx ) ) ; break ; case ASHIFT : emit_insn ( gen_ashlsi3_k ( reg , reg , n_rtx ) ) ; break ; default : gcc_unreachable ( ) ; } } </s>


<s> void i386_pe_record_external_function ( tree decl , const char * name ) { struct extern_list * p ; p = ggc_alloc < extern_list > ( ) ; p -> next = extern_head ; p -> decl = decl ; p -> name = name ; extern_head = p ; } </s>

Assemble an external function reference . We need to keep a list of these , so that we can output the function types at the end of the assembly . We ca n't output the types now , because we might see a definition of the function later on and emit debugging information for it then .


<s> static rtx aarch64_strip_extend ( rtx x , bool strip_shift ) { scalar_int_mode mode ; rtx op = x ; if ( ! is_a < scalar_int_mode > ( GET_MODE ( op ) , & mode ) ) return op ; if ( ( GET_CODE ( op ) == ZERO_EXTRACT || GET_CODE ( op ) == SIGN_EXTRACT ) && XEXP ( op , 2 ) == const0_rtx && GET_CODE ( XEXP ( op , 0 ) ) == MULT && aarch64_is_extend_from_extract ( mode , XEXP ( XEXP ( op , 0 ) , 1 ) , XEXP ( op , 1 ) ) ) return XEXP ( XEXP ( op , 0 ) , 0 ) ; if ( GET_CODE ( op ) == AND && GET_CODE ( XEXP ( op , 0 ) ) == MULT && CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) && CONST_INT_P ( XEXP ( op , 1 ) ) && aarch64_uxt_size ( exact_log2 ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) , INTVAL ( XEXP ( op , 1 ) ) ) != 0 ) return XEXP ( XEXP ( op , 0 ) , 0 ) ; if ( strip_shift && GET_CODE ( op ) == ASHIFT && CONST_INT_P ( XEXP ( op , 1 ) ) && ( ( unsigned HOST_WIDE_INT ) INTVAL ( XEXP ( op , 1 ) ) ) <= 4 ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == ZERO_EXTEND || GET_CODE ( op ) == SIGN_EXTEND ) op = XEXP ( op , 0 ) ; if ( op != x ) return op ; return x ; } </s>

Helper function for rtx cost calculation . Strip an extend expression from X . Returns the inner operand if successful , or the original expression on failure . We deal with a number of possible canonicalization variations here .


<s> bool nds32_n9_3r2w_mm_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_LOAD : case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( divmod_p ( producer ) ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , 0 ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , 1 ) ) ; return ( n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg1 ) || n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg2 ) ) ; } def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; default : gcc_unreachable ( ) ; } return n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg ) ; } </s>


<s> Register OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( Mips :: SP ) ) ; unsigned Offset = VA . getLocMemOffset ( ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; Align Alignment = commonAlignment ( TFL -> getStackAlign ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Alignment ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> void MOSFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; MachineIRBuilder Builder ( MBB , MBB . getFirstTerminator ( ) ) ; if ( hasFP ( MF ) ) { auto MBBI = find_if_not ( mbb_reverse ( MBB . begin ( ) , Builder . getInsertPt ( ) ) , [ ] ( const MachineInstr & MI ) { return MI . getFlag ( MachineInstr :: FrameDestroy ) ; } ) ; Builder . setInsertPt ( MBB , MachineBasicBlock :: iterator ( MBBI ) ) ; Builder . buildCopy ( MOS :: RS0 , TRI . getFrameRegister ( MF ) ) ; Builder . setInsertPt ( MBB , MBB . getFirstTerminator ( ) ) ; } int64_t StackSize = MFI . getStackSize ( ) ; if ( isISR ( MF ) ) StackSize += 256 ; if ( StackSize ) offsetSP ( Builder , StackSize ) ; } </s>


<s>
unsigned
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
}
else
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> bool NVVMIntrRange :: runOnFunction ( Function & F ) { bool Changed = false ; for ( Instruction & I : instructions ( F ) ) { CallInst * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; if ( Function * Callee = Call -> getCalledFunction ( ) ) { switch ( Callee -> getIntrinsicID ( ) ) { case Intrinsic :: nvvm_read_ptx_sreg_tid_x : Changed |= addRangeMetadata ( 0 , MaxBlockSize . x , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_tid_y : Changed |= addRangeMetadata ( 0 , MaxBlockSize . y , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_tid_z : Changed |= addRangeMetadata ( 0 , MaxBlockSize . z , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_ntid_x : Changed |= addRangeMetadata ( 1 , MaxBlockSize . x + 1 , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_ntid_y : Changed |= addRangeMetadata ( 1 , MaxBlockSize . y + 1 , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_ntid_z : Changed |= addRangeMetadata ( 1 , MaxBlockSize . z + 1 , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_ctaid_x : Changed |= addRangeMetadata ( 0 , MaxGridSize . x , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_ctaid_y : Changed |= addRangeMetadata ( 0 , MaxGridSize . y , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_ctaid_z : Changed |= addRangeMetadata ( 0 , MaxGridSize . z , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_nctaid_x : Changed |= addRangeMetadata ( 1 , MaxGridSize . x + 1 , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_nctaid_y : Changed |= addRangeMetadata ( 1 , MaxGridSize . y + 1 , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_nctaid_z : Changed |= addRangeMetadata ( 1 , MaxGridSize . z + 1 , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_warpsize : Changed |= addRangeMetadata ( 32 , 32 + 1 , Call ) ; break ; case Intrinsic :: nvvm_read_ptx_sreg_laneid : Changed |= addRangeMetadata ( 0 , 32 , Call ) ; break ; default : break ; } } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static rtx aarch64_gen_unspec_cond ( rtx_code code , machine_mode pred_mode , rtx pred , rtx op0 , rtx op1 ) { rtvec vec = gen_rtvec ( 3 , pred , op0 , op1 ) ; return gen_rtx_UNSPEC ( pred_mode , vec , aarch64_unspec_cond_code ( code ) ) ; } </s>

Return an ( unspec : PRED_MODE [ PRED OP0 OP1 ] UNSPEC_COND_ < X > ) expression , where < X > is the operation associated with comparison CODE .


<s> void aarch64_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; enum memmodel model ; rtx model_rtx ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; model_rtx = operands [ 5 ] ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; bool strong_zero_p = ! is_weak && oldval == const0_rtx ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; if ( is_mm_sync ( model ) ) aarch64_emit_load_exclusive ( mode , rval , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; if ( strong_zero_p ) { x = gen_rtx_NE ( VOIDmode , rval , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = aarch64_gen_compare_reg ( NE , rval , oldval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } emit_label ( label2 ) ; if ( strong_zero_p ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , rval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } if ( is_mm_sync ( model ) ) aarch64_emit_post_barrier ( model ) ; } </s>


<s> std :: unique_ptr < MCObjectWriter > MipsAsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return createMipsELFObjectWriter ( OS , TheTriple , IsN32 ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
if
(
!
Value
)
return
;
unsigned
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Kind
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
Value
=
adjustFixupValue
(
Fixup
,
Target
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
AArch64MCExpr
::
VariantKind
RefKind
=
static_cast
<
AArch64MCExpr
::
VariantKind
>
(
Target
.
getRefKind
(
)
)
;
if
(
AArch64MCExpr
::
getSymbolLoc
(
RefKind
)
==
AArch64MCExpr
::
VK_SABS
)
{
if
(
SignedValue
<
0
)
Data
[
Offset
+
3
]
&=
~
(
1
<<
6
)
;
else
Data
[
Offset
+
3
]
|=
(
1
<<
6
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> const char * LanaiTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case LanaiISD :: ADJDYNALLOC : return "LanaiISD::ADJDYNALLOC" ; case LanaiISD :: RET_FLAG : return "LanaiISD::RET_FLAG" ; case LanaiISD :: CALL : return "LanaiISD::CALL" ; case LanaiISD :: SELECT_CC : return "LanaiISD::SELECT_CC" ; case LanaiISD :: SETCC : return "LanaiISD::SETCC" ; case LanaiISD :: SUBBF : return "LanaiISD::SUBBF" ; case LanaiISD :: SET_FLAG : return "LanaiISD::SET_FLAG" ; case LanaiISD :: BR_CC : return "LanaiISD::BR_CC" ; case LanaiISD :: Wrapper : return "LanaiISD::Wrapper" ; case LanaiISD :: HI : return "LanaiISD::HI" ; case LanaiISD :: LO : return "LanaiISD::LO" ; case LanaiISD :: SMALL : return "LanaiISD::SMALL" ; default : return nullptr ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Lanai Lanai LanaiISD::ADJDYNALLOC "LanaiISD::ADJDYNALLOC" LanaiISD::RET_FLAG "LanaiISD::RET_FLAG" LanaiISD::CALL "LanaiISD::CALL" LanaiISD::SELECT_CC "LanaiISD::SELECT_CC" LanaiISD::SETCC "LanaiISD::SETCC" LanaiISD::SUBBF "LanaiISD::SUBBF" LanaiISD::SET_FLAG "LanaiISD::SET_FLAG" LanaiISD::BR_CC "LanaiISD::BR_CC" LanaiISD::Wrapper "LanaiISD::Wrapper" LanaiISD::HI "LanaiISD::HI" LanaiISD::LO "LanaiISD::LO" LanaiISD::SMALL "LanaiISD::SMALL"


<s> TargetLoweringBase :: LegalizeTypeAction SITargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( VT . getVectorNumElements ( ) != 1 && VT . getScalarType ( ) . bitsLE ( MVT :: i16 ) ) return TypeSplitVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s>
bool
ARMAsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
assert
(
MMI
)
;
DW
=
getAnalysisIfAvailable
<
DwarfWriter
>
(
)
;
assert
(
DW
&&
"Dwarf Writer is not available"
)
;
DW
->
BeginModule
(
&
M
,
MMI
,
O
,
this
,
TAI
)
;
if
(
Subtarget
->
isTargetDarwin
(
)
)
Mang
->
setUseQuotes
(
true
)
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> bool Z80RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { return false ; const Z80Subtarget & STI = MBB . getParent ( ) -> getSubtarget < Z80Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; DebugLoc DL ; if ( Reg == Z80 :: AF ) BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: PUSH24AF : Z80 :: PUSH16AF ) ) ; else BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? Z80 :: PUSH24r : Z80 :: PUSH16r ) ) . addReg ( Reg ) ; for ( MachineBasicBlock :: iterator II = MI ; II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; if ( II -> modifiesRegister ( Reg , TRI ) ) UseMI = II ; } if ( Reg == Z80 :: AF ) BuildMI ( MBB , UseMI , DL , TII . get ( Is24Bit ? Z80 :: POP24AF : Z80 :: POP16AF ) ) ; else BuildMI ( MBB , UseMI , DL , TII . get ( Is24Bit ? Z80 :: POP24r : Z80 :: POP16r ) , Reg ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> void PPCDispatchGroupSBHazardRecognizer :: EmitNoop ( ) { unsigned Directive = DAG -> MF . getSubtarget < PPCSubtarget > ( ) . getCPUDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 || Directive == PPC :: DIR_PWR8 || Directive == PPC :: DIR_PWR9 || CurSlots == 6 ) { CurGroup . clear ( ) ; CurSlots = CurBranches = 0 ; } else { CurGroup . push_back ( nullptr ) ; ++ CurSlots ; } } </s>

EmitNoop - This callback is invoked when a noop was added to the instruction stream .


<s> static inline hashval_t hash ( tree_map * m ) { return m -> hash ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM A15 S->D optimizer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> int ARMRegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return ARMGenRegisterInfo :: getDwarfRegNumFull ( RegNum , 0 ) ; } </s>

Map a target register to an equivalent dwarf register number .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool aarch64_uimm12_shift ( HOST_WIDE_INT val ) { return ( ( val & ( ( ( HOST_WIDE_INT ) 0xfff ) << 0 ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) 0xfff ) << 12 ) ) == val ) ; } </s>

Return true if val can be encoded as a 12-bit unsigned immediate with a left shift of 0 or 12 bits .


<s> bool FalkorMarkStridedAccessesLegacy :: runOnFunction ( Function & F ) { TargetPassConfig & TPC = getAnalysis < TargetPassConfig > ( ) ; const AArch64Subtarget * ST = TPC . getTM < AArch64TargetMachine > ( ) . getSubtargetImpl ( F ) ; if ( ST -> getProcFamily ( ) != AArch64Subtarget :: Falkor ) return false ; if ( skipFunction ( F ) ) return false ; LoopInfo & LI = getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; ScalarEvolution & SE = getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; FalkorMarkStridedAccesses LDP ( LI , SE ) ; return LDP . run ( ) ; } </s>


<s> int compute_a_shift_cc ( rtx insn ATTRIBUTE_UNUSED , rtx * operands ) { rtx shift = operands [ 3 ] ; machine_mode mode = GET_MODE ( shift ) ; enum rtx_code code = GET_CODE ( shift ) ; enum shift_type shift_type ; enum shift_mode shift_mode ; struct shift_info info ; int n ; switch ( mode ) { case E_QImode : shift_mode = QIshift ; break ; case E_HImode : shift_mode = HIshift ; break ; case E_SImode : shift_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFTRT : shift_type = SHIFT_ASHIFTRT ; break ; case LSHIFTRT : shift_type = SHIFT_LSHIFTRT ; break ; case ASHIFT : shift_type = SHIFT_ASHIFT ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( operands [ 2 ] ) == CONST_INT ) ; n = INTVAL ( operands [ 2 ] ) ; if ( n < 0 ) n = 0 ; else if ( ( unsigned int ) n > GET_MODE_BITSIZE ( mode ) ) n = GET_MODE_BITSIZE ( mode ) ; get_shift_alg ( shift_type , shift_mode , n , & info ) ; switch ( info . alg ) { case SHIFT_SPECIAL : if ( info . remainder == 0 ) return info . cc_special ; case SHIFT_INLINE : return info . cc_inline ; case SHIFT_ROT_AND : return OLD_CC_SET_ZNV ; case SHIFT_LOOP : if ( info . shift2 != NULL ) { if ( n % 2 ) return info . cc_inline ; } return OLD_CC_CLOBBER ; default : gcc_unreachable ( ) ; } } </s>

Compute which flag bits are valid after a shift insn .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_SaveList : CSR_SVR464_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ; } </s>


<s>
static
void
adjust_extract
(
rtx_insn
*
insn
)
{
rtx
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
)
pattern
=
XVECEXP
(
pattern
,
0
,
0
)
;
rtx
src
=
SET_SRC
(
pattern
)
;
rtx
sel
=
GET_CODE
(
src
)
==
VEC_DUPLICATE
XEXP
(
src
,
0
)
:
src
;
rtx
par
=
XEXP
(
sel
,
1
)
;
int
half_elts
=
GET_MODE_NUNITS
(
GET_MODE
(
XEXP
(
sel
,
0
)
)
)
>>
1
;
int
lane
=
INTVAL
(
XVECEXP
(
par
,
0
,
0
)
)
;
lane
=
lane
>=
half_elts
lane
half_elts
:
lane
+
half_elts
;
XVECEXP
(
par
,
0
,
0
)
=
GEN_INT
(
lane
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lane for extract %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains a vector extract operation , adjust the index of the extracted lane to account for the doubleword swap .


<s> bool RISCVAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { switch ( Fixup . getTargetKind ( ) ) { default : break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : if ( Target . isAbsolute ( ) ) return false ; break ; case RISCV :: fixup_riscv_got_hi20 : case RISCV :: fixup_riscv_tls_got_hi20 : case RISCV :: fixup_riscv_tls_gd_hi20 : return true ; } return STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] || ForceRelocs ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> virtual bool isVerboseAsm ( ) const { return IsVerboseAsm ; } </s>

Return true if this streamer supports verbose assembly and if it is enabled .


<s> void AlphaRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( hasFP ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; MachineInstr * New ; if ( Old -> getOpcode ( ) == Alpha :: ADJUSTSTACKDOWN ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Alpha :: LDA ) , Alpha :: R30 ) . addImm ( - Amount ) . addReg ( Alpha :: R30 ) ; } else { assert ( Old -> getOpcode ( ) == Alpha :: ADJUSTSTACKUP ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Alpha :: LDA ) , Alpha :: R30 ) . addImm ( Amount ) . addReg ( Alpha :: R30 ) ; } MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> int mmix_legitimate_constant_p ( rtx x ) { RTX_CODE code = GET_CODE ( x ) ; if ( code == CONST_INT || code == CONST_DOUBLE ) return 1 ; return CONSTANT_ADDRESS_P ( x ) ; } </s>


<s> bool X86TargetLowering :: hasStackProbeSymbol ( MachineFunction & MF ) const { return ! getStackProbeSymbolName ( MF ) . empty ( ) ; } </s>

Returns true if stack probing through a function call is requested .


<s> unsigned getReg ( ) const override { assert ( isRegKind ( ) ) ; return Reg . RegNo ; } </s>

Returns the register associated with this edge .


<s> bool AMDGPUSetWavePriority :: runOnMachineFunction ( MachineFunction & MF ) { const unsigned HighPriority = 3 ; const unsigned LowPriority = 0 ; Function & F = MF . getFunction ( ) ; if ( skipFunction ( F ) || ! AMDGPU :: isEntryFunctionCC ( F . getCallingConv ( ) ) ) return false ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; MBBInfoSet MBBInfos ; SmallVector < const MachineBasicBlock * , 16 > Worklist ; for ( MachineBasicBlock & MBB : MF ) { if ( any_of ( MBB , isVMEMLoad ) ) Worklist . push_back ( & MBB ) ; } while ( ! Worklist . empty ( ) ) { const MachineBasicBlock * MBB = Worklist . pop_back_val ( ) ; MBBInfo & Info = MBBInfos [ MBB ] ; if ( ! Info . MayReachVMEMLoad ) { Info . MayReachVMEMLoad = true ; Worklist . append ( MBB -> pred_begin ( ) , MBB -> pred_end ( ) ) ; } } MachineBasicBlock & Entry = MF . front ( ) ; if ( ! MBBInfos [ & Entry ] . MayReachVMEMLoad ) return false ; MachineBasicBlock :: iterator I = Entry . begin ( ) , E = Entry . end ( ) ; while ( I != E && ! SIInstrInfo :: isVALU ( * I ) && ! I -> isTerminator ( ) ) ++ I ; Entry . insert ( I , BuildSetprioMI ( MF , HighPriority ) ) ; SmallSet < MachineBasicBlock * , 16 > PriorityLoweringBlocks ; for ( MachineBasicBlock & MBB : MF ) { if ( MBBInfos [ & MBB ] . MayReachVMEMLoad ) { if ( MBB . succ_empty ( ) ) PriorityLoweringBlocks . insert ( & MBB ) ; continue ; } if ( CanLowerPriorityDirectlyInPredecessors ( MBB , MBBInfos ) ) { for ( MachineBasicBlock * Pred : MBB . predecessors ( ) ) { if ( MBBInfos [ Pred ] . MayReachVMEMLoad ) PriorityLoweringBlocks . insert ( Pred ) ; } continue ; } PriorityLoweringBlocks . insert ( & MBB ) ; } for ( MachineBasicBlock * MBB : PriorityLoweringBlocks ) { MachineBasicBlock :: iterator I = MBB -> end ( ) , B = MBB -> begin ( ) ; while ( I != B ) { if ( isVMEMLoad ( * -- I ) ) { ++ I ; break ; } } MBB -> insert ( I , BuildSetprioMI ( MF , LowPriority ) ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int sparc_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & arg ) { int slotno , regno , padding ; slotno = function_arg_slotno ( get_cumulative_args ( cum ) , arg . mode , arg . type , arg . named , false , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( TARGET_ARCH32 ) { const int size = GET_MODE_SIZE ( arg . mode ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else { if ( arg . aggregate_type_p ( ) ) { const int size = int_size_in_bytes ( arg . type ) ; if ( size > UNITS_PER_WORD && ( slotno == SPARC_INT_ARG_MAX - 1 || slotno == SPARC_FP_ARG_MAX - 1 ) ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_INT || ( ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT || ( arg . type && VECTOR_TYPE_P ( arg . type ) ) ) && ! ( TARGET_FPU && arg . named ) ) ) { const int size = ( arg . type && VECTOR_FLOAT_TYPE_P ( arg . type ) ) ? int_size_in_bytes ( arg . type ) : GET_MODE_SIZE ( arg . mode ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT || ( arg . type && VECTOR_TYPE_P ( arg . type ) ) ) { const int size = ( arg . type && VECTOR_FLOAT_TYPE_P ( arg . type ) ) ? int_size_in_bytes ( arg . type ) : GET_MODE_SIZE ( arg . mode ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_FP_ARG_MAX - 1 ) return UNITS_PER_WORD ; } } return 0 ; } </s>

For an arg passed partly in registers and partly in memory , this is the number of bytes of registers used . For args passed entirely in registers or entirely in memory , zero . Any arg that starts in the first 6 regs but wo n't entirely fit in them needs partial registers on v8 . On v9 , structures with integer values in arg slots 5,6 will be passed in % o5 and SP+176 , and complex fp values that begin in the last fp reg [ where `` last fp reg '' varies with the mode ] will be split between that reg and memory .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - ( STI -> isTargetDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void SIRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const SISubtarget & Subtarget = MF -> getSubtarget < SISubtarget > ( ) ; const SIInstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == 0 ) { BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned UnusedCarry = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & AMDGPU :: SReg_32RegClass ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: S_MOV_B32 ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_ADD_I32_e64 ) , BaseReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) . addReg ( OffsetReg , RegState :: Kill ) . addFrameIndex ( FrameIdx ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , AArch64 :: WSP ) ; markSuperRegs ( Reserved , AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , AArch64 :: W29 ) ; for ( size_t i = 0 ; i < AArch64 :: GPR32commonRegClass . getNumRegs ( ) ; ++ i ) { if ( MF . getSubtarget < AArch64Subtarget > ( ) . isXRegisterReserved ( i ) ) markSuperRegs ( Reserved , AArch64 :: GPR32commonRegClass . getRegister ( i ) ) ; } if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , AArch64 :: W19 ) ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ) markSuperRegs ( Reserved , AArch64 :: W16 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool GCNHazardRecognizer :: ShouldPreferAnother ( SUnit * SU ) { if ( ! SU -> isInstr ( ) ) return false ; MachineInstr * MAI = nullptr ; auto IsMFMAFn = [ & MAI ] ( MachineInstr * MI ) { MAI = nullptr ; if ( SIInstrInfo :: isMAI ( * MI ) && MI -> getOpcode ( ) != AMDGPU :: V_ACCVGPR_WRITE_B32 && MI -> getOpcode ( ) != AMDGPU :: V_ACCVGPR_READ_B32 ) MAI = MI ; return MAI != nullptr ; } ; MachineInstr * MI = SU -> getInstr ( ) ; if ( IsMFMAFn ( MI ) ) { int W = getWaitStatesSince ( IsMFMAFn , 16 ) ; if ( MAI ) return W < ( int ) TSchedModel . computeInstrLatency ( MAI ) ; } return false ; } </s>

ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard .


<s> void add_output_operand ( rtx x , machine_mode mode ) { create_output_operand ( & m_ops [ m_opno ++ ] , x , mode ) ; gcc_assert ( m_opno <= MAX_OPERANDS ) ; } </s>

Create output and add it into M_OPS and increase OPNO .


<s> unsigned M68kTargetLowering :: getJumpTableEncoding ( ) const { return Subtarget . getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_lo16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_ha16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_lo14"
,
16
,
14
,
0
}
,
{
"fixup_ppc_toc"
,
0
,
64
,
0
}
,
{
"fixup_ppc_toc16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_toc16_ds"
,
16
,
14
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( Subtarget . enableLongBranchPass ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; if ( Subtarget . inMips16Mode ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( createMipsConstantIslandPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


"instruction requires a WASM feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static int cg_magic_constant ( HOST_WIDE_INT c ) { switch ( c ) { case 0xffff : case - 1 : case 0 : case 1 : case 2 : case 4 : case 8 : return 1 ; default : return 0 ; } } </s>

These constants are really register reads , which are faster than regular constants .


<s> unsigned getMask ( ) const { assert ( ! Items . empty ( ) ) ; assert ( Mask != 0 ) ; return Mask ; } </s>


<s> bool PTXTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createPTXISelDag ( * this , OptLevel ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static machine_mode rs6000_preferred_simd_mode ( machine_mode mode ) { if ( TARGET_VSX ) switch ( mode ) { case DFmode : return V2DFmode ; default : ; } if ( TARGET_ALTIVEC || TARGET_VSX ) switch ( mode ) { case SFmode : return V4SFmode ; case TImode : return V1TImode ; case DImode : return V2DImode ; case SImode : return V4SImode ; case HImode : return V8HImode ; case QImode : return V16QImode ; default : ; } if ( TARGET_SPE ) switch ( mode ) { case SFmode : return V2SFmode ; case SImode : return V2SImode ; default : ; } if ( TARGET_PAIRED_FLOAT && mode == SFmode ) return V2SFmode ; return word_mode ; } </s>


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> inline bool sgpr_2reg_mode_p ( machine_mode mode ) { return mode == DImode || mode == DFmode ; } </s>

Return true if MODE is valid for pair of SGPR registers .


<s> SDValue Cpu0TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; Cpu0CC Cpu0CCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo ) ; Cpu0CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void ix86_expand_rint ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx res , xa , TWO52 , mask ; rtx_code_label * label ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; TWO52 = ix86_gen_TWO52 ( mode ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa , res , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand rint ( IEEE round to nearest ) rounding OPERAND1 and storing the result in OPERAND0 .


<s> static void tilepro_conditional_register_usage ( void ) { global_regs [ TILEPRO_NETORDER_REGNUM ] = 1 ; if ( TILEPRO_PIC_TEXT_LABEL_REGNUM != INVALID_REGNUM ) fixed_regs [ TILEPRO_PIC_TEXT_LABEL_REGNUM ] = 1 ; if ( PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM ) fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; } </s>


<s> static void loongarch_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; bits = MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ; mode = int_mode_for_size ( bits , 0 ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; loongarch_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) loongarch_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , ( enum memop_ret ) 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s>
static
void
nvptx_assemble_decl_begin
(
FILE
*
file
,
const
char
*
name
,
const
char
*
section
,
const_tree
type
,
HOST_WIDE_INT
size
,
unsigned
align
,
bool
undefined
=
false
)
{
bool
atype
=
(
TREE_CODE
(
type
)
==
ARRAY_TYPE
)
&&
(
TYPE_DOMAIN
(
type
)
==
NULL_TREE
)
;
if
(
undefined
&&
flexible_array_member_type_p
(
type
)
)
{
size
=
0
;
atype
=
true
;
}
while
(
TREE_CODE
(
type
)
==
ARRAY_TYPE
)
type
=
TREE_TYPE
(
type
)
;
if
(
TREE_CODE
(
type
)
==
VECTOR_TYPE
||
TREE_CODE
(
type
)
==
COMPLEX_TYPE
)
type
=
TREE_TYPE
(
type
)
;
unsigned
HOST_WIDE_INT
elt_size
=
int_size_in_bytes
(
type
)
;
machine_mode
elt_mode
=
TYPE_MODE
(
type
)
==
BLKmode
Pmode
:
DImode
;
elt_size
|=
GET_MODE_SIZE
(
elt_mode
)
;
elt_size
&=
elt_size
;
init_frag
.
size
=
elt_size
;
init_frag
.
mask
=
(
(
unsigned
HOST_WIDE_INT
)
2
<<
(
elt_size
*
BITS_PER_UNIT
1
)
)
1
;
init_frag
.
val
=
0
;
init_frag
.
offset
=
0
;
init_frag
.
started
=
false
;
init_frag
.
remaining
=
(
size
+
elt_size
1
)
/
elt_size
;
fprintf
(
file
,
"%s .align %d .u"
HOST_WIDE_INT_PRINT_UNSIGNED
" "
,
section
,
align
/
BITS_PER_UNIT
,
elt_size
*
BITS_PER_UNIT
)
;
assemble_name
(
file
,
name
)
;
if
(
size
)
fprintf
(
file
,
"["
HOST_WIDE_INT_PRINT_UNSIGNED
"]"
,
init_frag
.
remaining
)
;
else
if
(
atype
)
fprintf
(
file
,
"[]"
)
;
}
</s>

Emit a PTX variable decl and prepare for emission of its initializer . NAME is the symbol name and SETION the PTX data area . The type is TYPE , object size SIZE and alignment is ALIGN . The caller has already emitted any indentation and linkage specifier . It is responsible for any initializer , terminating ; and newline . SIZE is in bytes , ALIGN is in bits -- confusingly this is the opposite way round that PTX wants them !


<s> static HOST_WIDE_INT epiphany_starting_frame_offset ( void ) { return epiphany_stack_offset ; } </s>


<s> EVT MandarinTargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * PSI , BlockFrequencyInfo * BFI ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo , PSI , BFI ) ; MIB . setMF ( MF ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register ( ) ; processPHIs ( MF ) ; } </s>


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> bool X86TargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createX86MaxStackAlignmentHeuristicPass ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static rtx F ( rtx x ) { if ( GET_CODE ( x ) != CLOBBER ) RTX_FRAME_RELATED_P ( x ) = 1 ; return x ; } </s>

We use this to wrap all emitted insns in the prologue , so they get the `` frame-related '' ( /f ) flag set .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> static void pdp11_asm_print_operand ( FILE * file , rtx x , int code ) { long sval [ 2 ] ; if ( code == '#' ) { if ( TARGET_DEC_ASM ) putc ( '#' , file ) ; else putc ( '$' , file ) ; } else if ( code == '@' ) { if ( TARGET_UNIX_ASM ) fprintf ( file , "*" ) ; else fprintf ( file , "@" ) ; } else if ( GET_CODE ( x ) == REG ) fprintf ( file , "%s" , reg_names [ REGNO ( x ) ] ) ; else if ( GET_CODE ( x ) == MEM ) output_address ( GET_MODE ( x ) , XEXP ( x , 0 ) ) ; else if ( GET_CODE ( x ) == CONST_DOUBLE && FLOAT_MODE_P ( GET_MODE ( x ) ) ) { REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( x ) , sval ) ; if ( TARGET_DEC_ASM ) fprintf ( file , "#%lo" , ( sval [ 0 ] >> 16 ) & 0xffff ) ; else fprintf ( file , "$%#lo" , ( sval [ 0 ] >> 16 ) & 0xffff ) ; } else { if ( code != 'o' ) { if ( TARGET_DEC_ASM ) putc ( '#' , file ) ; else putc ( '$' , file ) ; } output_addr_const_pdp11 ( file , x ) ; } } </s>

Special format operators handled here : # -- output the correct immediate operand marker for the assembler dialect . @ -- output the correct indirect marker for the assembler dialect . o -- emit a constant value as a number ( not an immediate operand ) in octal .


<s> static void sh_output_function_epilogue ( FILE * ) { } </s>


<s> void AArch64TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { AArch64FunctionInfo * AFI = Entry -> getParent ( ) -> getInfo < AArch64FunctionInfo > ( ) ; AFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s> static Expected < std :: unique_ptr < HSACodeObject >> create ( MemoryBufferRef Wrapper ) { auto Obj = object :: ELF64LEObjectFile :: create ( Wrapper ) ; if ( auto E = Obj . takeError ( ) ) return std :: move ( E ) ; std :: unique_ptr < HSACodeObject > Ret ( new HSACodeObject ( std :: move ( * Obj ) ) ) ; return std :: move ( Ret ) ; } </s>


<s> static rtx frv_expand_binop_builtin ( enum insn_code icode , tree call , rtx target ) { rtx pat ; rtx op0 = frv_read_argument ( call , 0 ) ; rtx op1 = frv_read_argument ( call , 1 ) ; target = frv_legitimize_target ( icode , target ) ; op0 = frv_legitimize_argument ( icode , 1 , op0 ) ; op1 = frv_legitimize_argument ( icode , 2 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take two operands .


<s> bool MipsDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; processFunctionAfterISel ( MF ) ; return Ret ; } </s>

runOnMachineFunction - Emit the function body .


<s> void arm_output_fn_unwind ( FILE * f , bool prologue ) { if ( ! ARM_EABI_UNWIND_TABLES ) return ; if ( prologue ) fputs ( "\t.fnstart\n" , f ) ; else fputs ( "\t.fnend\n" , f ) ; } </s>

Output unwind directives for the start/end of a function .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"WebAssembly can only return up to one value"

"WebAssembly doesn't support non-C calling conventions"

"WebAssembly doesn't support varargs yet"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool X86TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_X86 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> static void s390_register_info_stdarg_gpr ( ) { int i ; int min_gpr ; int max_gpr ; if ( ! cfun -> stdarg || ! cfun -> va_list_gpr_size || crtl -> args . info . gprs >= GP_ARG_NUM_REG ) return ; min_gpr = crtl -> args . info . gprs ; max_gpr = min_gpr + cfun -> va_list_gpr_size - 1 ; if ( max_gpr >= GP_ARG_NUM_REG ) max_gpr = GP_ARG_NUM_REG - 1 ; min_gpr += GPR2_REGNUM ; max_gpr += GPR2_REGNUM ; if ( FP_REGNO_P ( cfun_gpr_save_slot ( GPR6_REGNUM ) ) && min_gpr <= GPR6_REGNUM && max_gpr >= GPR6_REGNUM ) { if ( cfun_frame_layout . first_restore_gpr == - 1 || cfun_frame_layout . first_restore_gpr > GPR6_REGNUM ) cfun_frame_layout . first_restore_gpr = GPR6_REGNUM ; if ( cfun_frame_layout . last_restore_gpr == - 1 || cfun_frame_layout . last_restore_gpr < GPR6_REGNUM ) cfun_frame_layout . last_restore_gpr = GPR6_REGNUM ; } if ( cfun_frame_layout . first_save_gpr == - 1 || cfun_frame_layout . first_save_gpr > min_gpr ) cfun_frame_layout . first_save_gpr = min_gpr ; if ( cfun_frame_layout . last_save_gpr == - 1 || cfun_frame_layout . last_save_gpr < max_gpr ) cfun_frame_layout . last_save_gpr = max_gpr ; for ( i = min_gpr ; i <= max_gpr ; i ++ ) cfun_gpr_save_slot ( i ) = SAVE_SLOT_STACK ; } </s>

Reserve the GPR save slots for GPRs which need to be saved due to stdarg . This is a helper routine for s390_register_info .


<s> unsigned X86FrameLowering :: getWinEHFuncletFrameSize ( const MachineFunction & MF ) const { unsigned CSSize = MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; unsigned MaxCallSize = MF . getFrameInfo ( ) -> getMaxCallFrameSize ( ) ; unsigned FrameSizeMinusRBP = RoundUpToAlignment ( CSSize + MaxCallSize , getStackAlignment ( ) ) ; return FrameSizeMinusRBP - CSSize ; } </s>

Funclets only need to account for space for the callee saved registers , as the locals are accounted for in the parent 's stack frame .


<s> unsigned int rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; if ( TYPE_PACKED ( type ) || align >= 64 ) return align ; do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node && ( TYPE_MODE ( type ) == DFmode || TYPE_MODE ( type ) == DCmode ) ) align = MAX ( align , 64 ) ; return align ; } </s>

Darwin , AIX increases natural record alignment to doubleword if the first field is an FP double while the FP fields remain word aligned .


<s>
void
XCoreFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
assert
(
RS
&&
"requiresRegisterScavenging failed"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
TargetRegisterClass
&
RC
=
XCore
::
GRRegsRegClass
;
const
TargetRegisterInfo
&
TRI
=
*
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
XCoreFunctionInfo
*
XFI
=
MF
.
getInfo
<
XCoreFunctionInfo
>
(
)
;
unsigned
Size
=
TRI
.
getSpillSize
(
RC
)
;
Align
Alignment
=
TRI
.
getSpillAlign
(
RC
)
;
if
(
XFI
->
isLargeFrame
(
MF
)
||
hasFP
(
MF
)
)
RS
->
addScavengingFrameIndex
(
MFI
.
CreateStackObject
(
Size
,
Alignment
,
false
)
)
;
if
(
XFI
->
isLargeFrame
(
MF
)
&&
!
hasFP
(
MF
)
)
RS
->
addScavengingFrameIndex
(
MFI
.
CreateStackObject
(
Size
,
Alignment
,
false
)
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .

XCore
XCore
"requiresRegisterScavenging failed"
XCore::GRRegsRegClass
XCore
XCore


<s> InstructionCost RISCVTTIImpl :: getRegUsageForType ( Type * Ty ) { TypeSize Size = Ty -> getPrimitiveSizeInBits ( ) ; if ( Ty -> isVectorTy ( ) ) { if ( Size . isScalable ( ) && ST -> hasVInstructions ( ) ) return divideCeil ( Size . getKnownMinValue ( ) , RISCV :: RVVBitsPerBlock ) ; if ( ST -> useRVVForFixedLengthVectors ( ) ) return divideCeil ( Size , ST -> getMinRVVVectorSizeInBits ( ) ) ; } return BaseT :: getRegUsageForType ( Ty ) ; } </s>

Returns the estimated number of registers required to represent Ty .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , SP :: IntRegsRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> unsigned PatmosInstrInfo :: getIssueWidth ( const MachineInstr * MI ) const { if ( MI -> isInlineAsm ( ) ) return PST . getSchedModel ( ) -> IssueWidth ; return PST . getIssueWidth ( MI -> getDesc ( ) . SchedClass ) ; } </s>

Maximum number of micro-ops that may be scheduled per cycle .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> BitVector Z80RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { auto vec = BitVector ( getNumRegs ( ) ) ; vec . set ( Z80 :: SP ) ; vec . set ( Z80 :: flags ) ; return vec ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode :: G_INTRINSIC : return selectG_INTRINSIC ( I , CoverageInfo ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : return selectG_INTRINSIC_W_SIDE_EFFECTS ( I , CoverageInfo ) ; case TargetOpcode :: G_ICMP : return selectG_ICMP ( I ) ; case TargetOpcode :: G_LOAD : if ( selectImpl ( I , CoverageInfo ) ) return true ; return selectG_LOAD ( I ) ; case TargetOpcode :: G_SELECT : return selectG_SELECT ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; case TargetOpcode :: G_TRUNC : return selectG_TRUNC ( I ) ; case TargetOpcode :: G_SEXT : case TargetOpcode :: G_ZEXT : case TargetOpcode :: G_ANYEXT : if ( selectG_SZA_EXT ( I ) ) { I . eraseFromParent ( ) ; return true ; } return false ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> static bool mips_use_debug_exception_return_p ( tree type ) { return lookup_attribute ( "use_debug_exception_return" , TYPE_ATTRIBUTES ( type ) ) != NULL ; } </s>

Check if the attribute to use debug exception return is set for a function .


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const override { return MVT :: i8 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> const MINA32RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static inline MemOpKey getEmptyKey ( ) { return MemOpKey ( PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) , PtrInfo :: getEmptyKey ( ) ) ; } </s>

Empty key : no key should be generated that has no DILocalVariable .


<s> void avr_log_set_avr_log ( void ) { bool all = TARGET_ALL_DEBUG != 0 ; if ( all ) avr_log_details = "all" ; if ( all || avr_log_details ) { char * str = ( char * ) alloca ( 3 + strlen ( avr_log_details ) ) ; bool info ; str [ 0 ] = ',' ; strcat ( stpcpy ( str + 1 , avr_log_details ) , "," ) ; all |= NULL != strstr ( str , ",all," ) ; info = NULL != strstr ( str , ",?," ) ; if ( info ) fprintf ( stderr , "\n-mlog=" ) ; do { \ avr_log . S = ( all || NULL != strstr ( str , "," # S "," ) ) ; \ if ( info ) \ fprintf ( stderr , # S "," ) ; \ } while ( 0 ) SET_DUMP_DETAIL ( address_cost ) ; SET_DUMP_DETAIL ( builtin ) ; SET_DUMP_DETAIL ( constraints ) ; SET_DUMP_DETAIL ( legitimate_address_p ) ; SET_DUMP_DETAIL ( legitimize_address ) ; SET_DUMP_DETAIL ( legitimize_reload_address ) ; SET_DUMP_DETAIL ( progmem ) ; SET_DUMP_DETAIL ( rtx_costs ) ; if ( info ) fprintf ( stderr , "?\n\n" ) ; } } </s>

Called from avr.cc : avr_option_override ( ) . Parse argument of -mlog= and set respective fields in avr_log .


<s> static tree resolve_vec_mul ( resolution * res , tree * args , tree * types , location_t loc ) { if ( TREE_CODE ( types [ 0 ] ) != VECTOR_TYPE || ! lang_hooks . types_compatible_p ( types [ 0 ] , types [ 1 ] ) ) { * res = resolved_bad ; return error_mark_node ; } switch ( TYPE_MODE ( TREE_TYPE ( types [ 0 ] ) ) ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_TImode : * res = resolved ; return fold_build2_loc ( loc , MULT_EXPR , types [ 0 ] , args [ 0 ] , fold_convert ( types [ 0 ] , args [ 1 ] ) ) ; case E_SFmode : { * res = resolved ; tree call = rs6000_builtin_decls [ RS6000_BIF_XVMULSP ] ; return build_call_expr ( call , 2 , args [ 0 ] , args [ 1 ] ) ; } case E_DFmode : { * res = resolved ; tree call = rs6000_builtin_decls [ RS6000_BIF_XVMULDP ] ; return build_call_expr ( call , 2 , args [ 0 ] , args [ 1 ] ) ; } default : * res = resolved_bad ; return error_mark_node ; } } </s>

Resolve an overloaded vec_mul call and return a tree expression for the resolved call if successful . ARGS contains the arguments to the call . TYPES contains their types . RES must be set to indicate the status of the resolution attempt . LOC contains statement location information .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DataLayoutPass > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved < StackProtector > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> getDesc ( ) . mayStore ( ) && hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


runOnMachineFunction - Emit the function body .


<s> unsigned size ( ) const { return AllValues . size ( ) ; } </s>

The number of name/type pairs is returned .


<s> void HexagonTargetLowering :: LowerOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { if ( N -> getOpcode ( ) != ISD :: STORE ) return TargetLowering :: LowerOperationWrapper ( N , Results , DAG ) ; } </s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> bool AArch64PromoteConstant :: runOnFunction ( Function & F ) { bool LocalChange = false ; SmallPtrSet < Constant * , 8 > AlreadyChecked ; for ( Instruction & I : instructions ( & F ) ) { for ( Value * Op : I . operand_values ( ) ) { Constant * Cst = dyn_cast < Constant > ( Op ) ; if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) . second ) LocalChange |= promoteConstant ( Cst ) ; } } return LocalChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool csky_label_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( GET_CODE ( x ) == LABEL_REF ) return true ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( csky_label_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; } else if ( fmt [ i ] == 'e' && csky_label_mentioned_p ( XEXP ( x , i ) ) ) return true ; } return false ; } </s>

Return TRUE if X references a LABEL_REF .


<s> MipsSubtarget :: MipsSubtarget ( const TargetMachine & TM , const Module & M , const std :: string & FS , bool little ) : MipsArchVersion ( Mips1 ) , MipsABI ( O32 ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , HasABICall ( true ) , HasAbsoluteCall ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasMulDivAdd ( false ) , HasMinMax ( false ) , HasSwap ( false ) , HasBitCount ( false ) { std :: string CPU = "mips1" ; MipsArchVersion = Mips1 ; ParseSubtargetFeatures ( FS , CPU ) ; const std :: string & TT = M . getTargetTriple ( ) ; SSectionThreshold = SSThreshold ; if ( TT . find ( "linux" ) == std :: string :: npos ) IsLinux = false ; if ( TT . find ( "mipsallegrex" ) != std :: string :: npos || TT . find ( "psp" ) != std :: string :: npos ) { MipsABI = EABI ; IsSingleFloat = true ; MipsArchVersion = Mips2 ; HasVFPU = true ; HasSEInReg = true ; HasBitCount = true ; HasSwap = true ; HasCondMov = true ; } if ( NotABICall || isABI_EABI ( ) || ( TM . getRelocationModel ( ) == Reloc :: Static ) ) HasABICall = false ; if ( HasABICall && AbsoluteCall ) HasAbsoluteCall = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

Mips Mips Mips Mips Mips Mips "mips1" Mips Mips "linux" "mipsallegrex" "psp" Mips Mips Mips


<s> bool isUnknown ( ) const { return State == Unknown ; } </s>

Tests if this MemDepResult represents a query which can not and/or will not be computed .