<s> if ( TableEntry -> IsLoad ) { DstIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; DstReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ;

MachineOperand MO = MI . getOperand ( OpIdx ++ ) ;


<s> for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( ! I -> pred_empty ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printMachineInstruction ( II ) ;


<s> if ( Def -> getOpcode ( ) == <STR_LIT> ) continue ; bool SameBlock = Def -> getParent ( ) == & MBB ; bool CanMove = SameBlock && isSafeToMove ( Def , Insert , AA , MRI ) && ! TreeWalker . isOnStack ( Reg ) ; if ( CanMove && hasOneUse ( Reg , Def , MRI , MDT , LIS ) ) { Insert = moveForSingleUse ( Reg , Op , Def , MBB , Insert , LIS , MFI , MRI ) ; } else if ( shouldRematerialize ( * Def , AA , TII ) ) { Insert = rematerializeCheapDef ( Reg , Op , * Def , MBB , Insert -> getIterator ( ) , LIS , MFI , MRI , TII , TRI ) ; } else if ( CanMove && oneUseDominatesOtherUses ( Reg , Op , MBB , MRI , MDT , LIS , MFI ) ) { Insert = moveAndTeeForMultiUse ( Reg , Op , Def , MBB , Insert , LIS , MFI , MRI , TII ) ; } else { if ( ! CanMove && SameBlock ) Commuting . maybeCommute ( Insert , TreeWalker , TII ) ; continue ; } if ( Insert -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) convertImplicitDefToConstZero ( Insert , MRI , TII , MF , LIS ) ; Commuting . reset ( ) ; TreeWalker . pushOperands ( Insert ) ; } if ( Insert != & * MII ) { imposeStackOrdering ( & * MII ) ; MII = MachineBasicBlock :: iterator ( Insert ) . getReverse ( ) ; Changed = true ; } } } if ( Changed ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ;

for ( MachineBasicBlock & MBB : MF ) MBB . addLiveIn ( <STR_LIT> ) ;


<s> ~ <ISA_LIT>ELFObjectWriter ( ) override {


<s> MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes = false ; HasNoDeadStrip = true ; SupportsDebugInformation = true ; UsesCFIForDebug = true ; DwarfRegNumForCFI = true ;


<s> bool PHILinearize :: findDest ( unsigned SourceReg , MachineBasicBlock * SourceMBB , unsigned & DestReg ) { PHIInfoElementT * InfoElement = findPHIInfoElementFromSource ( SourceReg , SourceMBB ) ; if ( InfoElement != nullptr ) { DestReg = phiInfoElementGetDest ( InfoElement ) ; return true ; }


<s> machine_mode cc_mode = visium_select_cc_mode ( code , op2 , op3 ) ; if ( cc_mode == CCFPEmode && ( op_code == NEG || op_code == MINUS ) ) cc_mode = CCFPmode ; rtx flags = gen_rtx_REG ( cc_mode , FLAGS_REGNUM ) ; rtx x = gen_rtx_COMPARE ( cc_mode , op2 , op3 ) ; x = gen_rtx_SET ( flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( code , SImode , flags , const0_rtx ) ; switch ( op_code ) { case SET : break ; case NEG : x = gen_rtx_NEG ( SImode , x ) ;


<s> output_addr_const ( file , addr ) ; if ( SYMBOL_REF_SMALL_P ( addr ) ) fprintf ( file , <STR_LIT> ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == MULT ) index = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , base = XEXP ( addr , <NUM_LIT> ) ; else if ( CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) index = XEXP ( addr , <NUM_LIT> ) , base = XEXP ( addr , <NUM_LIT> ) ;

else base = XEXP ( addr , <NUM_LIT> ) , index = XEXP ( addr , <NUM_LIT> ) ;


<s> if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> || ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( ! Memory . OffsetImm ) return true ;

int64_t Val = Memory . OffsetImm -> getValue ( ) ;


<s> constexpr UnmangledFuncInfo ( const char * _Name , unsigned _NumArgs ) : Name ( _Name ) , NumArgs ( _NumArgs ) {


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( create<ISA_LIT>DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && usingDefaultRegAlloc ( ) ) addPass ( create<ISA_LIT>A57FPLoadBalancing ( ) ) ;


<s> static const char * aarch64_mangle_builtin_scalar_type ( const_tree type ) { int i = <NUM_LIT> ; while ( aarch64_scalar_builtin_types [ i ] != NULL ) { const char * name = aarch64_scalar_builtin_types [ i ] ; if ( TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL && DECL_NAME ( TYPE_NAME ( type ) ) && ! strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( TYPE_NAME ( type ) ) ) , name ) ) return aarch64_scalar_builtin_types [ i ] ; i ++ ;


<s> static DecodeStatus DecodeDTripleRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) {

return DecodeRegisterClassByID ( Inst , RegNo , <STR_LIT> , Decoder ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) {


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DL ( <STR_LIT> ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> return ( uint64x1_t ) { __builtin_aarch64_uqrshldi_uus ( __a [ <NUM_LIT> ] , __b [ <NUM_LIT> ] ) } ;


<s> if ( Kind == LongRegisterKind :: ZRF && MRI -> getRegClass ( <STR_LIT> ) . contains ( OldReg ) ) return true ; if ( Kind == LongRegisterKind :: ARF || Kind == LongRegisterKind :: DRF ) if ( MRI -> getRegClass ( <STR_LIT> ) . contains ( OldReg ) ) return true ; unsigned NewReg = convertToLongReg ( OldReg , Kind ) ; static const int RegClass [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( NewReg == <NUM_LIT> ) { static const StringRef RegName [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const StringRef RegAlign [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Error ( LongRegOp -> getStartLoc ( ) , <STR_LIT> + StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( OldReg ) ) + <STR_LIT> + RegName [ static_cast < unsigned > ( Kind ) ] + <STR_LIT> + RegAlign [ static_cast < unsigned > ( Kind ) ] , LongRegOp -> getLocRange ( ) ) ; return false ; }

auto NewRegOp = <STR_LIT> ( NewReg , RegClass [ static_cast < unsigned > ( Kind ) ] , LongRegOp -> getStartLoc ( ) , LongRegOp -> getEndLoc ( ) ) ;


<s> assert ( ! VT . isVector ( ) ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( SrcVT ) ; if ( ! IsSigned && UseSSEReg ) { if ( Subtarget . hasAVX512 ( ) ) return Op ; if ( VT == <STR_LIT> ) return SDValue ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; if ( Subtarget . is64Bit ( ) ) { SDValue Res , Chain ; if ( IsStrict ) { Res = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , Src } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; } else Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , dl ) ; return Res ; } if ( ! Subtarget . hasSSE3 ( ) ) return SDValue ( ) ; } if ( VT == <STR_LIT> && ( UseSSEReg || SrcVT == <STR_LIT> ) ) { assert ( IsSigned && <STR_LIT> ) ; SDValue Res , Chain ; if ( IsStrict ) { Res = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Op . getOperand ( <NUM_LIT> ) , Src } ) ; Chain = Res . getValue ( <NUM_LIT> ) ; } else Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , dl ) ; return Res ; } if ( UseSSEReg && IsSigned ) return Op ; if ( SrcVT == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( IsSigned ) LC = RTLIB :: getFPTOSINT ( SrcVT , VT ) ; else LC = RTLIB :: getFPTOUINT ( SrcVT , VT ) ; SDValue Chain = IsStrict ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ; MakeLibCallOptions CallOptions ; std :: pair < SDValue , SDValue > Tmp = makeLibCall ( DAG , LC , VT , Src , CallOptions , SDLoc ( Op ) , Chain ) ;

if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ;


<s> const InstructionSelector * <ISA_LIT>Subtarget :: getInstructionSelector ( ) const { return InstSelector . get ( ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return ( new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerEH_SJLJ_SETJMP ( SDValue Op , SelectionDAG & DAG ) const {


<s> bool isMemImm ( ) const { return Kind == MEMORY_IMM ;


<s> is_simple_branch = true ; if ( INSN_ADDRESSES_SET_P ( ) ) { int from_addr = INSN_ADDRESSES ( INSN_UID ( insn ) ) ; int to_addr = INSN_ADDRESSES ( INSN_UID ( operands [ <NUM_LIT> ] ) ) ; int delta = to_addr - from_addr ; is_simple_branch = IN_RANGE ( delta , - <NUM_LIT> , <NUM_LIT> ) ; }


<s> union { vec_uint4 v ; unsigned long long ll [ <NUM_LIT> ] ; } shmask ;

shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> for ( MCRegAliasIterator AI ( Reg , & HRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( MRI . isPhysRegUsed ( * AI ) ) return true ;


<s> <ISA_LIT>GOTEntry ( uint64_t pContent , SectionData * pParent ) : GOT :: Entry < <NUM_LIT> > ( pContent , pParent ) {


<s> if ( IdxVal >= NumElems / <NUM_LIT> ) IdxVal -= NumElems / <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } MVT VT = Op . getValueType ( ) . getSimpleVT ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ;


<s> unsigned regCode = getRegBinaryCode ( MI . getOperand ( OpNo ) . getReg ( ) ) ; return regCode >> shift ;


<s> if ( NumElems != <NUM_LIT> ) return false ; return isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> auto LDC = Builder . buildInstr ( <STR_LIT> ) . add ( CDef ) . addImm ( <NUM_LIT> ) ; if ( LDC -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ) LDC -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; if ( ! Offset ) Builder . buildInstr ( <STR_LIT> ) . add ( Dst ) . addUse ( Src ) ; else { Register A = Builder . buildCopy ( & <STR_LIT> , Src ) . getReg ( <NUM_LIT> ) ; auto Instr = Builder . buildInstr ( <STR_LIT> ) . addDef ( A ) . add ( CDef ) . add ( VDef ) . addUse ( A ) . addImm ( Offset ) . addUse ( CDef . getReg ( ) , <NUM_LIT> , CDef . getSubReg ( ) ) ; Instr -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; Builder . buildInstr ( <STR_LIT> ) . add ( Dst ) . addUse ( A ) ;


<s> bool Modified = false ; MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; for ( ; I != E ; ++ I ) Modified |= ReduceMBB ( * I ) ; return Modified ;


<s> return __builtin_ia32_sqrtph512_mask_round ( __A , _mm512_setzero_ph ( ) , ( __mmask32 ) - <NUM_LIT> , __B ) ;


<s> for ( MachineInstr :: mmo_iterator I = MI . memoperands_begin ( ) , E = MI . memoperands_end ( ) ; I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ;


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> isEntryFunction ( ) ) return ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ;

SavedRegs . reset ( MFI -> getStackPtrOffsetReg ( ) ) ;


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Equal ) ) return reportParseError ( <STR_LIT> ) ; Parser . Lex ( ) ; StringRef Arch ; if ( Parser . parseIdentifier ( Arch ) ) return reportParseError ( <STR_LIT> ) ;

StringRef ArchFeatureName = StringSwitch < StringRef > ( Arch ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> } ) ; if ( GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = * ( uint32_t * ) CI -> getValue ( ) . getRawData ( ) ; emitWordLE ( Val ) ; } else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CV ) ) { if ( CFP -> getType ( ) -> isFloatTy ( ) ) emitWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else if ( CFP -> getType ( ) -> isDoubleTy ( ) ) emitDWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else { llvm_unreachable ( <STR_LIT> ) ; } } else { llvm_unreachable ( <STR_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: setExecutionDomain ( MachineInstr * MI , unsigned Domain ) const { assert ( Domain > <NUM_LIT> && Domain < <NUM_LIT> && <STR_LIT> ) ;

uint16_t dom = ( MI -> getDesc ( ) . TSFlags >> <STR_LIT> ) & <NUM_LIT> ;


<s> const MachineOperand & Op1 = MI1 . getOperand ( N1 + <STR_LIT> ) ; const MachineOperand & Op2 = MI2 . getOperand ( N2 + <STR_LIT> ) ; assert ( isSimilarDispOp ( Op1 , Op2 ) && <STR_LIT> ) ;

if ( Op1 . isJTI ( ) ) return <NUM_LIT> ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , HasDistinctOps ( false ) , HasLoadStoreOnCond ( false ) , HasHighWord ( false ) , HasFPExtension ( false ) , HasPopulationCount ( false ) , HasMessageSecurityAssist3 ( false ) , HasMessageSecurityAssist4 ( false ) , HasResetReferenceBitsMultiple ( false ) , HasFastSerialization ( false ) , HasInterlockedAccess1 ( false ) , HasMiscellaneousExtensions ( false ) , HasExecutionHint ( false ) , HasLoadAndTrap ( false ) , HasTransactionalExecution ( false ) , HasProcessorAssist ( false ) , HasDFPZonedConversion ( false ) , HasEnhancedDAT2 ( false ) , HasVector ( false ) , HasLoadStoreOnCond2 ( false ) , HasLoadAndZeroRightmostByte ( false ) , HasMessageSecurityAssist5 ( false ) , HasDFPPackedConversion ( false ) , HasMiscellaneousExtensions2 ( false ) , HasGuardedStorage ( false ) , HasMessageSecurityAssist7 ( false ) , HasMessageSecurityAssist8 ( false ) , HasVectorEnhancements1 ( false ) , HasVectorPackedDecimal ( false ) , HasInsertReferenceBitsMultiple ( false ) , HasMiscellaneousExtensions3 ( false ) , HasMessageSecurityAssist9 ( false ) , HasVectorEnhancements2 ( false ) , HasVectorPackedDecimalEnhancement ( false ) , HasEnhancedSort ( false ) , HasDeflateConversion ( false ) , HasSoftFloat ( false ) , TargetTriple ( TT ) , SpecialRegisters ( initializeSpecialRegisters ( ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {


<s> bool isFloatOrDoubleReg ( ) const { return ( Kind == k_Register && ( Reg . Kind == rk_FloatReg || Reg . Kind == rk_DoubleReg ) ) ;


<s> MachineBasicBlock :: iterator <ISA_LIT>LoadStoreOptimizer :: mergeTBufferStorePair ( CombineInfo & CI , CombineInfo & Paired , const SmallVectorImpl < MachineInstr * > & InstsToMove ) { MachineBasicBlock * MBB = CI . I -> getParent ( ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; const unsigned Opcode = getNewOpcode ( CI , Paired ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI , Paired ) ; Register SrcReg = MRI -> createVirtualRegister ( SuperRC ) ; const auto * Src0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Src1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , Paired . I , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; const unsigned Regs = getRegs ( Opcode , * TII ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; unsigned JoinedFormat = getBufferFormatWithCompCount ( CI . Format , CI . Width + Paired . Width , * STM ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ;

const MachineMemOperand * MMOb = * Paired . I -> memoperands_begin ( ) ;


<s> return ( GET_CODE ( x ) == SYMBOL_REF && startswith ( XSTR ( x , <NUM_LIT> ) , <STR_LIT> ) ) ;


<s> MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_Register : MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( StringRef ( GV -> getName ( ) ) ) ; MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( Sym , Ctx ) ) ;


<s> int c4x_I_constant ( rtx op ) { return c4x_immed_int_constant ( op ) && IS_INT16_CONST ( INTVAL ( op ) ) ;


<s> int short_memory_operand ( rtx x , enum machine_mode mode ) {

if ( ! memory_operand ( x , mode ) ) return <NUM_LIT> ;


<s> return BA . Addr -> getType ( ) == NodeAttrs :: Ref && BA . Addr -> getKind ( ) == NodeAttrs :: Use ;


<s> } SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128Shuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue Op = lowerShuffleWithSHUFPD ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Op ; if ( SDValue V = lowerShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ;

return lowerShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , mode , type , named , false ) ;

return arg . stack_p ? arg . num_gprs * UNITS_PER_WORD : <NUM_LIT> ;


<s> switch ( Strategy ) { case SCHEDULE_MINREGONLY : scheduleMinReg ( ) ; break ;

case SCHEDULE_MINREGFORCED : scheduleMinReg ( true ) ; break ;


<s> inline SDValue XformUToUM1Imm ( unsigned Imm , const SDLoc & DL ) { assert ( ( Imm >= <NUM_LIT> ) && <STR_LIT> ) ;

return CurDAG -> getTargetConstant ( Imm - <NUM_LIT> , DL , <STR_LIT> ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { const Triple & TT = STI . getTargetTriple ( ) ;

if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , TT ) ;


<s> bool isMem ( RegisterKind RegKind , MemoryKind MemKind ) const {

return ( Kind == KindMem && Mem . RegKind == RegKind && ( MemKind == BDXMem || ! Mem . Index ) && ( MemKind == BDLMem ) == ( Mem . Length != <NUM_LIT> ) ) ;


<s> return PredOpIdx != - <NUM_LIT> && MI . getOperand ( PredOpIdx ) . getImm ( ) != <STR_LIT> ;


<s> FunctionType * ResumeFTy = FunctionType :: get ( IRB . getVoidTy ( ) , IRB . getInt8PtrTy ( ) , false ) ; ResumeF = getEmscriptenFunction ( ResumeFTy , <STR_LIT> , & M ) ; FunctionType * EHTypeIDTy = FunctionType :: get ( IRB . getInt32Ty ( ) , IRB . getInt8PtrTy ( ) , false ) ; EHTypeIDF = getEmscriptenFunction ( EHTypeIDTy , <STR_LIT> , & M ) ; for ( Function & F : M ) { if ( F . isDeclaration ( ) ) continue ; Changed |= runEHOnFunction ( F ) ; } } if ( DoSjLj ) { Changed = true ; if ( LongjmpF ) { EmLongjmpJmpbufF = getEmscriptenFunction ( LongjmpF -> getFunctionType ( ) , <STR_LIT> , & M ) ; LongjmpF -> replaceAllUsesWith ( EmLongjmpJmpbufF ) ; } if ( SetjmpF ) { FunctionType * SetjmpFTy = SetjmpF -> getFunctionType ( ) ; FunctionType * FTy = FunctionType :: get ( Type :: getInt32PtrTy ( C ) , { SetjmpFTy -> getParamType ( <NUM_LIT> ) , IRB . getInt32Ty ( ) , Type :: getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } , false ) ; SaveSetjmpF = getEmscriptenFunction ( FTy , <STR_LIT> , & M ) ; FTy = FunctionType :: get ( IRB . getInt32Ty ( ) , { IRB . getInt32Ty ( ) , Type :: getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } , false ) ;

TestSetjmpF = getEmscriptenFunction ( FTy , <STR_LIT> , & M ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectVectorAshrLshr ( MachineInstr & I , MachineRegisterInfo & MRI ) { assert ( I . getOpcode ( ) == TargetOpcode :: G_ASHR || I . getOpcode ( ) == TargetOpcode :: G_LSHR ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; bool IsASHR = I . getOpcode ( ) == TargetOpcode :: G_ASHR ; unsigned Opc = <NUM_LIT> ; unsigned NegOpc = <NUM_LIT> ; const TargetRegisterClass * RC = getRegClassForTypeOnBank ( Ty , RBI . getRegBank ( <STR_LIT> ) , RBI ) ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ;


<s> DecodeStatus Result = decodeSImmOperand < <NUM_LIT> > ( Inst , SImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler :: Success && <STR_LIT> ) ;


<s> FunctionPass * create<ISA_LIT>CostModelEmitter ( ) { return new <ISA_LIT>CostModelEmitter ( ) ;


<s> if ( ! RM . hasValue ( ) ) { return Reloc :: Static ; } return * RM ;


<s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : SRetReturnReg ( <NUM_LIT> ) , StackAlignBaseReg ( <NUM_LIT> ) , HasClobberLR ( <NUM_LIT> ) , HasEHReturn ( false ) {


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; SmallVector < Type * , <NUM_LIT> > ArgTypes ; for ( const Argument & Arg : MF . getFunction ( ) . args ( ) ) ArgTypes . emplace_back ( Arg . getType ( ) ) ; <ISA_LIT>CCState CCInfo ( ArgTypes , CCID , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; unsigned LastVal = ~ <NUM_LIT> ; SDValue ArgValue ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . getValNo ( ) != LastVal && <STR_LIT> ) ; LastVal = VA . getValNo ( ) ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) { ArgValue = DAG . getBitcast ( VA . getValVT ( ) , ArgValue ) ; } if ( VA . isExtInLoc ( ) ) { ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; } } else {


<s> StringRef getPassName ( ) const override {


<s> for ( unsigned i = <NUM_LIT> , e = getNumRegUnits ( ) ; i != e ; ++ i ) { const int * PSets = getRegUnitPressureSets ( i ) ; for ( unsigned j = <NUM_LIT> ; PSets [ j ] != - <NUM_LIT> ; ++ j ) { ++ PressureSetRegUnits [ PSets [ j ] ] ; } } unsigned VGPRMax = <NUM_LIT> , SGPRMax = <NUM_LIT> , AGPRMax = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) { if ( isVGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > VGPRMax ) {


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ;


<s> case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ;

case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ;


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) { if ( isa < ConstantSDNode > ( LHS ) ) { std :: swap ( LHS , RHS ) ; } } if ( N -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * ShlRHS = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! ShlRHS ) { return SDValue ( ) ; } APInt ShiftAmt = ShlRHS -> getAPIntValue ( ) ; unsigned BitWidth = MulType . getSizeInBits ( ) ; if ( ShiftAmt . sge ( <NUM_LIT> ) && ShiftAmt . slt ( BitWidth ) ) { APInt MulVal = APInt ( BitWidth , <NUM_LIT> ) << ShiftAmt ; RHS = DCI . DAG . getConstant ( MulVal , DL , MulType ) ; } else { return SDValue ( ) ; } } bool Signed ; if ( ! AreMulWideOperandsDemotable ( LHS , RHS , OptSize , Signed ) ) { return SDValue ( ) ; } EVT DemotedVT ; if ( MulType == <STR_LIT> ) {


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ;

Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ;


<s> } if ( ! GV -> isThreadLocal ( ) ) return false ; if ( ! TM ) return true ; TLSModel :: Model Model = TM -> getTLSModel ( GV ) ;

return Model == TLSModel :: GeneralDynamic || Model == TLSModel :: LocalDynamic ;


<s> StringRef <ISA_LIT>MCExpr :: getVariantKindName ( VariantKind Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : return <STR_LIT> ; case VK_<ISA_LIT>_HI : return <STR_LIT> ;


<s> Value * HandlerI8 = Builder . CreateBitCast ( Handler , Builder . getInt8PtrTy ( ) ) ; Builder . CreateStore ( HandlerI8 , Builder . CreateStructGEP ( LinkTy , Link , <NUM_LIT> ) ) ; Constant * FSZero = Constant :: getNullValue ( LinkTy -> getPointerTo ( ) -> getPointerTo ( <NUM_LIT> ) ) ; Value * Next = Builder . CreateLoad ( LinkTy -> getPointerTo ( ) , FSZero ) ;

Builder . CreateStore ( Next , Builder . CreateStructGEP ( LinkTy , Link , <NUM_LIT> ) ) ;


<s> aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { if ( const ConstantInt * constInt = dyn_cast < ConstantInt > ( ConstantFoldConstantExpression ( Cexpr , DL ) ) ) { int int32 = ( int ) ( constInt -> getZExtValue ( ) ) ; ConvertIntToBytes < > ( ptr , int32 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } if ( Cexpr -> getOpcode ( ) == Instruction :: PtrToInt ) { Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr -> getOperand ( <NUM_LIT> ) ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else if ( ETy == Type :: getInt64Ty ( CPV -> getContext ( ) ) ) { if ( const ConstantInt * constInt = dyn_cast < ConstantInt > ( CPV ) ) { long long int64 = ( long long ) ( constInt -> getZExtValue ( ) ) ; ConvertIntToBytes < > ( ptr , int64 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { if ( const ConstantInt * constInt = dyn_cast < ConstantInt > ( ConstantFoldConstantExpression ( Cexpr , DL ) ) ) { long long int64 = ( long long ) ( constInt -> getZExtValue ( ) ) ; ConvertIntToBytes < > ( ptr , int64 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; break ; } if ( Cexpr -> getOpcode ( ) == Instruction :: PtrToInt ) { Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr -> getOperand ( <NUM_LIT> ) ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; } case Type :: FloatTyID : case Type :: DoubleTyID : { const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ; Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ConvertFloatToBytes ( ptr , float32 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ;

ConvertDoubleToBytes ( ptr , float64 ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes = false ; HasDotTypeDotSizeDirective = false ; HasNoDeadStrip = true ; WeakRefDirective = <STR_LIT> ;


<s> if ( TARGET_UNIFORM_SIMT ) cpp_define ( parse_in , <STR_LIT> ) ; const char * ptx_sm = NULL ; { \ if ( TARGET_SM ## XX ) \ ptx_sm = <STR_LIT> # XX <STR_LIT> ; \ } cpp_define ( parse_in , ptx_sm ) ; { unsigned major = ptx_version_to_number ( ( ptx_version ) ptx_version_option , true ) ; unsigned minor = ptx_version_to_number ( ( ptx_version ) ptx_version_option , false ) ;

cpp_define_formatted ( parse_in , <STR_LIT> , major ) ;


<s> return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> bool isVALU ( const SUnit * SU ) const { const MachineInstr * MI = SU -> getInstr ( ) ; return MI && TII -> isVALU ( * MI ) ;


<s> for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned NewVR = MRI -> createVirtualRegister ( RC ) ; assert ( Entry -> getParent ( ) -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) && <STR_LIT> ) ; Entry -> addLiveIn ( * I ) ; BuildMI ( * Entry , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVR ) . addReg ( * I ) ; for ( auto * Exit : Exits ) BuildMI ( * Exit , Exit -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * I ) . addReg ( NewVR ) ; }


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return false ;

int64_t Imm = Inst . getOperand ( LblOperand ) . getImm ( ) ;


<s> MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ;

BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ;


<s> static unsigned getBitExtrOpcode ( MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; bool IsTailCallReturn = false ; if ( MBB . end ( ) != MBBI ) { unsigned RetOpcode = MBBI -> getOpcode ( ) ; IsTailCallReturn = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; IsTailCallReturn |= RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; }

<ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> static bool s390_short_displacement ( rtx disp ) { if ( ! disp ) return true ; if ( GET_CODE ( disp ) == CONST_INT ) return INTVAL ( disp ) >= <NUM_LIT> && INTVAL ( disp ) < <NUM_LIT> ; if ( GET_CODE ( disp ) == CONST && GET_CODE ( XEXP ( disp , <NUM_LIT> ) ) == UNSPEC && ( XINT ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_GOT || XINT ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_GOTNTPOFF ) ) return false ;

if ( GET_CODE ( disp ) == CONST ) return true ;


<s> toexit ( nentry ) ; nentry . connect ( getNodeFor ( header ) , std :: make_pair ( ( const PredicatedBlock * ) NULL , header ) ) ;


<s> Stmt * prev = <NUM_LIT> ; Stmt * next ; while ( stmt ) { next = stmt -> next ; stmt -> next = prev ; prev = stmt ; stmt = next ; }


<s> if ( NumElts < <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > ConcatMask ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) ConcatMask [ i ] = i ; for ( unsigned i = NumElts ; i != <NUM_LIT> ; ++ i ) ConcatMask [ i ] = ( i % NumElts ) + NumElts ; Value * Zero = Constant :: getNullValue ( Op0 -> getType ( ) ) ; Op0 = Builder . CreateShuffleVector ( Op0 , Zero , ConcatMask ) ; Op1 = Builder . CreateShuffleVector ( Op1 , Zero , ConcatMask ) ; NumElts = <NUM_LIT> ; } Type * I32Ty = VectorType :: get ( Builder . getInt32Ty ( ) , IntrinsicNumElts / <NUM_LIT> ) ; assert ( NumElts % IntrinsicNumElts == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSplits = NumElts / IntrinsicNumElts ; SmallVector < Value * , <NUM_LIT> > Ops ( NumSplits ) ; for ( unsigned i = <NUM_LIT> ; i != NumSplits ; ++ i ) { SmallVector < int , <NUM_LIT> > ExtractMask ( IntrinsicNumElts ) ; std :: iota ( ExtractMask . begin ( ) , ExtractMask . end ( ) , i * IntrinsicNumElts ) ; Value * ExtractOp0 = Builder . CreateShuffleVector ( Op0 , Op0 , ExtractMask ) ; Value * ExtractOp1 = Builder . CreateShuffleVector ( Op1 , Op0 , ExtractMask ) ; Ops [ i ] = Builder . CreateCall ( PSADBWFn , { ExtractOp0 , ExtractOp1 } ) ; Ops [ i ] = Builder . CreateBitCast ( Ops [ i ] , I32Ty ) ; } assert ( isPowerOf2_32 ( NumSplits ) && <STR_LIT> ) ; unsigned Stages = Log2_32 ( NumSplits ) ; for ( unsigned s = Stages ; s > <NUM_LIT> ; -- s ) { unsigned NumConcatElts = cast < VectorType > ( Ops [ <NUM_LIT> ] -> getType ( ) ) -> getNumElements ( ) * <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> << ( s - <NUM_LIT> ) ; ++ i ) { SmallVector < int , <NUM_LIT> > ConcatMask ( NumConcatElts ) ; std :: iota ( ConcatMask . begin ( ) , ConcatMask . end ( ) , <NUM_LIT> ) ; Ops [ i ] = Builder . CreateShuffleVector ( Ops [ i * <NUM_LIT> ] , Ops [ i * <NUM_LIT> + <NUM_LIT> ] , ConcatMask ) ; } } NumElts = cast < VectorType > ( OpTy ) -> getNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { Ops [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , ArrayRef < int > { <NUM_LIT> , <NUM_LIT> } ) ; } else if ( NumElts >= <NUM_LIT> ) {

SmallVector < int , <NUM_LIT> > ConcatMask ( NumElts ) ;


<s> TRI -> eliminateFrameIndex ( MI , <NUM_LIT> , <NUM_LIT> ) ; } if ( MI -> mayLoad ( ) && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { TRI -> eliminateFrameIndex ( MI , <NUM_LIT> , <NUM_LIT> ) ; } }


<s> if ( ! FB . test ( F ) ) continue ; CpuArch = F ; break ; } bool UseHvx = false ; for ( unsigned F : { ExtensionHVX , ExtensionHVX64B , ExtensionHVX128B } ) { if ( ! FB . test ( F ) ) continue ; UseHvx = true ; break ; } bool HasHvxVer = false ; for ( unsigned F : { ExtensionHVXV60 , ExtensionHVXV62 , ExtensionHVXV65 } ) { if ( ! FB . test ( F ) ) continue ; HasHvxVer = true ; UseHvx = true ; break ; } if ( ! UseHvx || HasHvxVer ) return FB ;


<s> if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ;

if ( Subtarget -> isTargetDarwin ( ) ) return LowerDarwinGlobalTLSAddress ( Op , DAG ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . padShortFunctions ( ) ) { addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . LEAusesAG ( ) ) { addPass ( create<ISA_LIT>FixupLEAs ( ) ) ;


<s> TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getTarget ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; LIs = LI ; DEBUG ( MF -> dump ( ) ; ) ; for ( MachineFunction :: const_iterator mbbItr = MF -> begin ( ) , mbbEnd = MF -> end ( ) ; mbbItr != mbbEnd ; ++ mbbItr ) { const MachineBasicBlock * MBB = & * mbbItr ; Chains . clear ( ) ; for ( MachineBasicBlock :: const_iterator miItr = MBB -> begin ( ) , miEnd = MBB -> end ( ) ; miItr != miEnd ; ++ miItr ) { const MachineInstr * MI = & * miItr ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> :


<s> if ( ! SN -> isTruncatingStore ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && ( Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> ) ) { SDValue BSwapOp = Op1 . getOperand ( <NUM_LIT> ) ; if ( BSwapOp . getValueType ( ) == <STR_LIT> ) BSwapOp = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSwapOp ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , BSwapOp , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( Op1 . getValueType ( ) ) } ;

return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> ) , Ops , MemVT , SN -> getMemOperand ( ) ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> if ( RegOp0 . isUse ( ) ) { if ( ! MergeForward ) { RegOp0 . setIsKill ( false ) ; RegOp1 . setIsKill ( false ) ; } else { Register Reg = getLdStRegOp ( * I ) . getReg ( ) ; for ( MachineInstr & MI : make_range ( std :: next ( I ) , Paired ) ) MI . clearRegisterKills ( Reg , TRI ) ; } } MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingPairOpcode ( Opc ) ) ) . add ( RegOp0 ) . add ( RegOp1 ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . cloneMergedMemRefs ( { & * I , & * Paired } ) . setMIFlags ( I -> mergeFlagsWith ( * Paired ) ) ; ( void ) MIB ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( I -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Paired -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SExtIdx != - <NUM_LIT> ) { MachineOperand & DstMO = MIB -> getOperand ( SExtIdx ) ; Register DstRegX = DstMO . getReg ( ) ; Register DstRegW = TRI -> getSubReg ( DstRegX , <STR_LIT> ) ; DstMO . setReg ( DstRegW ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIBKill = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( TargetOpcode :: KILL ) , DstRegW ) . addReg ( DstRegW ) . addReg ( DstRegX , RegState :: Define ) ; MIBKill -> getOperand ( <NUM_LIT> ) . setImplicit ( ) ; MachineInstrBuilder MIBSXTW = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( <STR_LIT> ) , DstRegX ) . addReg ( DstRegX ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MIBSXTW ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( ( MachineInstr * ) MIBSXTW ) -> print ( dbgs ( ) ) ) ; } else { LLVM_DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; }


<s> if ( isToken ( AsmToken :: Identifier ) && ( HwReg . Id = getHwregId ( getTokenStr ( ) , getSTI ( ) ) ) != OPR_ID_UNKNOWN ) { HwReg . IsSymbolic = true ; lex ( ) ; } else if ( ! parseExpr ( HwReg . Id , <STR_LIT> ) ) {


<s> case <NUM_LIT> : return <STR_LIT> ( Val , hasInv2PiInlineImm ( ) ) ; case <NUM_LIT> : return <STR_LIT> ( Val , hasInv2PiInlineImm ( ) ) ; case <NUM_LIT> : { const unsigned OperandType = Desc . OpInfo [ OpIdx ] . OperandType ; if ( OperandType == <STR_LIT> || OperandType == <STR_LIT> || OperandType == <STR_LIT> ) return <STR_LIT> ( Val ) ; if ( OperandType == <STR_LIT> || OperandType == <STR_LIT> || OperandType == <STR_LIT> ) return <STR_LIT> ( Val ) ; if ( OperandType == <STR_LIT> || OperandType == <STR_LIT> || OperandType == <STR_LIT> ) return <STR_LIT> ( Val , hasInv2PiInlineImm ( ) ) ; return <STR_LIT> ( Val , hasInv2PiInlineImm ( ) ) ; } default : llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( ! active_insn_p ( use_insn ) ) return ; if ( ! nds32_float_reg_load_store_p ( use_insn ) || find_post_update_rtx ( use_insn ) != - <NUM_LIT> ) return ; } group_id = GEN_INT ( nds32_alloc_relax_group_id ( ) ) ; emit_insn_before ( gen_relax_group ( group_id ) , insn ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ;


<s> unsigned getDarwinVers ( ) const { if ( isTargetDarwin ( ) ) return TargetTriple . getDarwinMajorNumber ( ) ;


<s> if ( ReportErrors ) Context . reportError ( Loc , Msg ) ;


<s> if ( ( Ty . isScalar ( ) && ! isFP ) || Ty . isPointer ( ) ) { switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : return PMI_GPR8 ; case <NUM_LIT> : return PMI_GPR16 ; case <NUM_LIT> : return PMI_GPR32 ; case <NUM_LIT> : return PMI_GPR64 ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Ty . isScalar ( ) ) { switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : return PMI_FP32 ; case <NUM_LIT> : return PMI_FP64 ; default : llvm_unreachable ( <STR_LIT> ) ; } } else {


<s> bool isMemIndexReg ( unsigned LowR , unsigned HighR ) const { assert ( Kind == Memory && <STR_LIT> ) ; return Mem . IndexReg >= LowR && Mem . IndexReg <= HighR ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT , const MCTargetOptions & Options ) : MCAsmInfoELF ( ) { CodePointerSize = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; StackGrowsUp = true ; HasSingleParameterDotFile = false ; MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) , <STR_LIT> ( t1 ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> if ( s390_function_arg_size ( mode , type ) > <NUM_LIT> ) return false ; if ( TARGET_SOFT_FLOAT ) return false ; if ( ! type ) return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode ; while ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field , single = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( single == NULL_TREE ) single = TREE_TYPE ( field ) ; else return false ;


<s> static void EmitLoad ( bool Is64Bit , unsigned DestReg , unsigned BaseReg , unsigned Scale , unsigned IndexReg , unsigned Offset , unsigned SegmentReg , MCStreamer & Out ) { MCInst Load ; Load . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; Load . addOperand ( MCOperand :: CreateReg ( DestReg ) ) ; Load . addOperand ( MCOperand :: CreateReg ( BaseReg ) ) ; Load . addOperand ( MCOperand :: CreateImm ( Scale ) ) ; Load . addOperand ( MCOperand :: CreateReg ( IndexReg ) ) ;

Load . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> InsnType Imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> void <ISA_LIT>ElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isAAPCS_ABI ( ) ;

TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ;


<s> if ( ca -> start_reg >= CA_FIRST_REG ) for ( i = <NUM_LIT> ; i < ca -> reg_count ; i ++ ) ca -> reg_used [ i + ca -> start_reg - CA_FIRST_REG ] = <NUM_LIT> ;


<s> const RegisterBank * Bank = getRegBank ( Reg , * MRI , * TRI ) ; MRI -> setRegBank ( LoLHS , * Bank ) ; MRI -> setRegBank ( HiLHS , * Bank ) ; Regs . push_back ( LoLHS ) ; Regs . push_back ( HiLHS ) ;

B . buildInstr ( <STR_LIT> ) . addDef ( LoLHS ) . addDef ( HiLHS ) . addUse ( Reg ) ;


<s> bool shouldPreserveUseListOrder ( ) const {


<s> SmallVector < int , <NUM_LIT> > Mask ; createUnpackShuffleMask ( VT , Mask , false , false ) ;

return DAG . getVectorShuffle ( VT , dl , V1 , V2 , Mask ) ;


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> return convReg ( BusyRegs [ REG_OFFSET_SHADOW ] , VT ) ;


<s> if ( MBB . getNumber ( ) > <NUM_LIT> ) { auto & BS = BlockSizes [ MBB . getNumber ( ) - <NUM_LIT> ] ;


<s> const std :: string TypeName = STy && ! STy -> isLiteral ( ) ? STy -> getName ( ) : <STR_LIT> ;

for ( int i = <NUM_LIT> , e = array_lengthof ( specialTypes ) ; i != e ; ++ i ) if ( TypeName == specialTypes [ i ] ) return true ;


<s> static unsigned extractDLC ( unsigned CachePolicy ) { return ( CachePolicy >> <NUM_LIT> ) & <NUM_LIT> ;


<s> return ; } if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) && ! AM . IndexReg . getNode ( ) ) { AM . IndexReg = AM . Base_Reg ; AM . setBaseReg ( SDValue ( ) ) ; } if ( ! AM . IndexReg . getNode ( ) ) return ; bool HasSymbolic = AM . hasSymbolicDisplacement ( ) ; bool NeedsFixing1 = HasSymbolic || ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase && AM . Disp > <NUM_LIT> ) ; bool NeedsFixing2 = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) && AM . Base_Reg . getNode ( ) ; if ( ! NeedsFixing1 && ! NeedsFixing2 ) return ; static const unsigned LogTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; assert ( AM . Scale < sizeof ( LogTable ) / sizeof ( LogTable [ <NUM_LIT> ] ) ) ; unsigned ScaleLog = LogTable [ AM . Scale ] ; assert ( ScaleLog <= <NUM_LIT> ) ; SmallVector < SDNode * , <NUM_LIT> > NewNodes ; SDValue NewIndex = AM . IndexReg ; if ( ScaleLog > <NUM_LIT> ) { SDValue ShlCount = CurDAG -> getConstant ( ScaleLog , <STR_LIT> ) ; NewNodes . push_back ( ShlCount . getNode ( ) ) ; SDValue ShlNode = CurDAG -> getNode ( <STR_LIT> , dl , N . getValueType ( ) , NewIndex , ShlCount ) ; NewNodes . push_back ( ShlNode . getNode ( ) ) ; NewIndex = ShlNode ; } if ( AM . Disp > <NUM_LIT> || HasSymbolic ) { SDValue Base , Scale , Index , Disp , Segment ; getAddressOperands ( AM , Base , Scale , Index , Disp , Segment ) ;


<s> static bool cheap<ISA_LIT>FSETCC_SSE ( <STR_LIT> SetCCOpcode ) { return ( SetCCOpcode != <STR_LIT> ) && ( SetCCOpcode != <STR_LIT> ) ;


<s> vpmaxq_u32 ( uint32x4_t a , uint32x4_t b ) { return ( uint32x4_t ) __builtin_aarch64_umaxpv4si ( ( int32x4_t ) a , ( int32x4_t ) b ) ;


<s> void <ISA_LIT>InstrInfo :: expandRetLR ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ;


<s> if ( Literal >= - <NUM_LIT> && Literal <= <NUM_LIT> ) return true ;

uint16_t Val = static_cast < uint16_t > ( Literal ) ;


<s> MCAsmParserExtension :: Initialize ( Parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> SimplifyAction ( <STR_LIT> IID , FtzRequirementTy FtzReq ) : IID ( IID ) , FtzRequirement ( FtzReq ) {


<s> if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( Subtarget . hasSSSE3 ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ;


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectAddrRegImm11 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { if ( selectAddrFrameIndex ( Addr , Base , Offset ) ) return true ;

if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> ) ) return true ;


<s> break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ) return false ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { E = MI -> getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) return false ; Register SrcReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) ) return false ; const MachineInstr * SrcMI = MRI . getVRegDef ( SrcReg ) ; if ( ! SrcMI ) return false ; Worklist . push_back ( SrcMI ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __rorq ( unsigned long long __X , int __C ) {


return __builtin_ia32_pmovmskb ( ( __v8qi ) __A ) ;


<s> if ( regno == CC_REGNUM || regno == VFPCC_REGNUM ) return TARGET_THUMB2 ? CC_REG : NO_REGS ; if ( IS_VFP_REGNUM ( regno ) ) { if ( regno <= D7_VFP_REGNUM ) return VFP_D0_D7_REGS ; else if ( regno <= LAST_LO_VFP_REGNUM ) return VFP_LO_REGS ; else return VFP_HI_REGS ; } if ( IS_IWMMXT_REGNUM ( regno ) ) return IWMMXT_REGS ;

if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return IWMMXT_GR_REGS ;


<s> void <ISA_LIT>Pipeliner :: createPrologCounters ( int Counter , MachineBasicBlock * PrologBlock ) { unsigned StartReg ; MachineBasicBlock :: iterator InsertPos = PrologInserter ; assert ( isLoop ( & ( * ( -- Prolog -> end ( ) ) ) ) && <STR_LIT> ) ; if ( LoopInst -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { StartReg = LoopInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { unsigned v_reg = MRI -> createVirtualRegister ( PrologBlock -> getParent ( ) -> getSubtarget ( ) . getTargetLowering ( ) -> getRegClassFor ( <STR_LIT> ) ) ; BuildMI ( * PrologBlock , InsertPos , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , v_reg ) . addImm ( LoopInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addImm ( <ISA_LIT>II :: OpType :: INT32 ) . addImm ( <NUM_LIT> ) . addReg ( v_reg , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; StartReg = v_reg ; } InitialCounters . push_back ( StartReg ) ; unsigned PrevReg = StartReg ; for ( int i = <NUM_LIT> ; i < Counter ; ++ i ) { unsigned v_reg = MRI -> createVirtualRegister ( PrologBlock -> getParent ( ) -> getSubtarget ( ) . getTargetLowering ( ) -> getRegClassFor ( <STR_LIT> ) ) ; if ( LoopInst -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { MachineInstr * MI = BuildMI ( * PrologBlock , InsertPos , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , v_reg ) . addReg ( PrevReg ) . addReg ( LoopInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <ISA_LIT>II :: OpType :: INT32 ) . addImm ( <NUM_LIT> ) . addReg ( PrevReg , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; ( void ) MI ; PrevReg = v_reg ; LLVM_DEBUG ( ExecThreads [ i ] . Dprolog . push_back ( MI ) ) ; } else { MachineInstr * MI = BuildMI ( * PrologBlock , InsertPos , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , v_reg ) . addReg ( StartReg ) . addImm ( LoopInst -> getOperand ( <NUM_LIT> ) . getImm ( ) * i ) . addImm ( <ISA_LIT>II :: OpType :: INT32 ) . addImm ( <NUM_LIT> ) . addReg ( StartReg , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ;

return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ;


<s> return false ; } Tag = Ret . getValue ( ) ; Parser . Lex ( ) ; } else { const MCExpr * AttrExpr ; TagLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( AttrExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( AttrExpr ) ; if ( check ( ! CE , TagLoc , <STR_LIT> ) ) return true ; Tag = CE -> getValue ( ) ; } if ( Parser . parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; StringRef StringValue ; int64_t IntegerValue = <NUM_LIT> ; bool IsIntegerValue = ( ( Tag != <STR_LIT> ) && ( Tag != <STR_LIT> ) && ( Tag != <STR_LIT> ) ) ; SMLoc ValueExprLoc = Parser . getTok ( ) . getLoc ( ) ; if ( IsIntegerValue ) { const MCExpr * ValueExpr ; if ( Parser . parseExpression ( ValueExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ValueExpr ) ; if ( ! CE ) return Error ( ValueExprLoc , <STR_LIT> ) ; IntegerValue = CE -> getValue ( ) ; } else { if ( Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; StringValue = Parser . getTok ( ) . getStringContents ( ) ; Parser . Lex ( ) ; } if ( Parser . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( IsIntegerValue ) getTargetStreamer ( ) . emitAttribute ( Tag , IntegerValue ) ; else if ( Tag != <STR_LIT> && Tag != <STR_LIT> ) getTargetStreamer ( ) . emitTextAttribute ( Tag , StringValue ) ; else { <STR_LIT> ID = ( Tag == <STR_LIT> ) ? <STR_LIT> ( StringValue ) : <STR_LIT> ( StringValue ) ; if ( ID == <STR_LIT> :: INVALID ) return Error ( ValueExprLoc , ( Tag == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ;


<s> uint64_t Value = CE -> getValue ( ) ;

if ( Value % Angle == Remainder && Value <= <NUM_LIT> ) return DiagnosticPredicateTy :: Match ;


<s> int i ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_regs [ i ] ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ;

for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ;


<s> SMLoc BracLoc = Tok . getLoc ( ) , End = Tok . getEndLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return ErrorOperand ( BracLoc , <STR_LIT> ) ; Parser . Lex ( ) ; SMLoc StartInBrac = Tok . getLoc ( ) ; IntelExprStateMachine SM ( ImmDisp , false , true ) ; if ( ParseIntelExpression ( SM , End ) ) return <NUM_LIT> ; const MCExpr * Disp = <NUM_LIT> ; if ( const MCExpr * Sym = SM . getSym ( ) ) { Disp = Sym ; if ( isParsingInlineAsm ( ) ) RewriteIntelBracExpression ( InstInfo -> AsmRewrites , SM . getSymName ( ) , ImmDisp , SM . getImm ( ) , BracLoc , StartInBrac , End ) ; } if ( SM . getImm ( ) || ! Disp ) { const MCExpr * Imm = MCConstantExpr :: Create ( SM . getImm ( ) , getContext ( ) ) ; if ( Disp ) Disp = MCBinaryExpr :: CreateAdd ( Disp , Imm , getContext ( ) ) ; else Disp = Imm ; } if ( Tok . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return <NUM_LIT> ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( Disp , Start , End , Size ) ;

else return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size ) ;


<s> Allocas [ AI ] . DbgVariableIntrinsics . push_back ( DVI ) ; } continue ; } auto * II = dyn_cast < IntrinsicInst > ( I ) ; if ( II && ( II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> ) ) { AllocaInst * AI = findAllocaForValue ( II -> getArgOperand ( <NUM_LIT> ) ) ; if ( ! AI ) { UnrecognizedLifetimes . push_back ( I ) ; continue ; } if ( II -> getIntrinsicID ( ) == <STR_LIT> ) Allocas [ AI ] . LifetimeStart . push_back ( II ) ; else Allocas [ AI ] . LifetimeEnd . push_back ( II ) ; } if ( isa < ReturnInst > ( I ) || isa < ResumeInst > ( I ) || isa < CleanupReturnInst > ( I ) ) RetVec . push_back ( I ) ; } } if ( Allocas . empty ( ) ) return false ; int NextTag = <NUM_LIT> ; int NumInterestingAllocas = <NUM_LIT> ; for ( auto & I : Allocas ) { AllocaInfo & Info = I . second ; assert ( Info . AI ) ; if ( ! isInterestingAlloca ( * Info . AI ) ) { Info . Tag = - <NUM_LIT> ; continue ; } alignAndPadAlloca ( Info ) ; NumInterestingAllocas ++ ; Info . Tag = NextTag ; NextTag = ( NextTag + <NUM_LIT> ) % <NUM_LIT> ; } if ( NumInterestingAllocas == <NUM_LIT> ) return true ; std :: unique_ptr < DominatorTree > DeleteDT ; DominatorTree * DT = nullptr ; if ( auto * P = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ) DT = & P -> getDomTree ( ) ; if ( DT == nullptr && ( NumInterestingAllocas > <NUM_LIT> || ! F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) ) { DeleteDT = std :: make_unique < DominatorTree > ( * F ) ; DT = DeleteDT . get ( ) ; } std :: unique_ptr < PostDominatorTree > DeletePDT ; PostDominatorTree * PDT = nullptr ; if ( auto * P = getAnalysisIfAvailable < PostDominatorTreeWrapperPass > ( ) ) PDT = & P -> getPostDomTree ( ) ; if ( PDT == nullptr && ! F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) { DeletePDT = std :: make_unique < PostDominatorTree > ( * F ) ; PDT = DeletePDT . get ( ) ; } SetTagFunc = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; Instruction * Base = insertBaseTaggedPointer ( Allocas , DT ) ;


<s> printIfSet ( MI , OpNo , O , <STR_LIT> ) ;


<s> using namespace llvm :: <STR_LIT> ; unsigned <ISA_LIT>mm16 = MI -> getOperand ( OpNo ) . getImm ( ) ; const unsigned Id = ( <ISA_LIT>mm16 & ID_MASK_ ) >> ID_SHIFT_ ; const unsigned Offset = ( <ISA_LIT>mm16 & OFFSET_MASK_ ) >> OFFSET_SHIFT_ ; const unsigned Width = ( ( <ISA_LIT>mm16 & WIDTH_M1_MASK_ ) >> WIDTH_M1_SHIFT_ ) + <NUM_LIT> ; O << <STR_LIT> ; if ( ID_SYMBOLIC_FIRST_ <= Id && Id < ID_SYMBOLIC_LAST_ ) { O << IdSymbolic [ Id ] ; } else { O << Id ; } if ( Width != WIDTH_M1_DEFAULT_ + <NUM_LIT> || Offset != OFFSET_DEFAULT_ ) { O << <STR_LIT> << Offset << <STR_LIT> << Width ;


<s> __ev64_opaque__ v ; int32_t i [ <NUM_LIT> ] ; } u ;


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; }

Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;

* cum = ( * cum < FT32_R6 ? * cum + ( ( <NUM_LIT> + FT32_FUNCTION_ARG_SIZE ( mode , type ) ) / <NUM_LIT> ) : * cum ) ;


<s> Move = <STR_LIT> ; } else { Move = <STR_LIT> ; } unsigned Dst = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Dst != Src && <STR_LIT> ) ; auto TRI = getRegisterInfo ( ) ; auto RCDst = TRI . getMaximalPhysRegClass ( Dst , MVTDst ) ; auto RCSrc = TRI . getMaximalPhysRegClass ( Src , MVTSrc ) ; assert ( RCDst && RCSrc && <STR_LIT> ) ; assert ( RCDst != RCSrc && <STR_LIT> ) ; unsigned SSrc = RI . getMatchingMegaReg ( Src , RCDst ) ; assert ( SSrc && <STR_LIT> ) ; MachineBasicBlock & MBB = * MIB -> getParent ( ) ; DebugLoc DL = MIB -> getDebugLoc ( ) ;


<s> bool <ISA_LIT>InstrInfo :: StoreRegToStackSlot ( MachineFunction & MF , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * > & NewMIs , bool & NonRI , bool & SpillsVRS ) const { DebugLoc DL ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) {


<s> void <ISA_LIT>RegisterSema :: onRegisterGet ( unsigned RegNo ) {


<s> virtual void EmitARM64WinCFISaveNext ( ) {


<s> Function * F = Function :: Create ( FTy , GlobalValue :: ExternalLinkage , <STR_LIT> + Twine ( NumClauses + <NUM_LIT> ) , & M ) ;

FindMatchingCatches [ NumClauses ] = F ;


<s> SmallVector < int , <NUM_LIT> > LaneMask ( NumElts , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; int SrcLane = M / NumEltsPerLane ; int DstLane = i / NumEltsPerLane ; if ( ! isUndefOrEqual ( SrcLaneMask [ DstLane ] , SrcLane ) ) return SDValue ( ) ; SrcLaneMask [ DstLane ] = SrcLane ;

LaneMask [ i ] = ( SrcLane * NumEltsPerLane ) + ( i % NumEltsPerLane ) ;


<s> int byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; int word_size = ( byte_size + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; bool doubleword_aligned_p ; doubleword_aligned_p = tilegx_function_arg_boundary ( mode , type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) * cum += * cum & <NUM_LIT> ; if ( * cum < TILEGX_NUM_ARG_REGS && * cum + word_size > TILEGX_NUM_ARG_REGS ) * cum = TILEGX_NUM_ARG_REGS ;


<s> bool <ISA_LIT>InstrInfo :: isSetBoundsInstr ( const MachineInstr & I , const MachineOperand * & Base , const MachineOperand * & Size ) const { switch ( I . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Base = & I . getOperand ( <NUM_LIT> ) ; Size = & I . getOperand ( <NUM_LIT> ) ; return true ;


<s> static unsigned isRegUsedOnlyInSetIndx ( MachineRegisterInfo * MRI , unsigned RegNo ) { unsigned NumUses = <NUM_LIT> ; for ( MachineInstr & U : MRI -> use_nodbg_instructions ( RegNo ) ) { if ( U . definesRegister ( RegNo ) ) continue ; if ( ! isSET_INDX ( U . getOpcode ( ) ) ) return <NUM_LIT> ; ++ NumUses ; }


<s> ival = ival & <NUM_LIT> ; if ( SIGNED_INT12 ( ival ) ) return false ; if ( ( ival & ~ <NUM_LIT> ) == <NUM_LIT> ) return true ; if ( IS_POWEROF2_P ( ival + <NUM_LIT> ) ) return true ; if ( ! TARGET_BARREL_SHIFTER ) return false ; if ( ( ( ival >> ( __builtin_ffs ( ival ) - <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return true ; if ( ( ival & ~ <NUM_LIT> ) == <NUM_LIT> ) return true ;


<s> void <ISA_LIT>AsmPrinter :: LowerHWASAN_CHECK_MEMACCESS ( const MachineInstr & MI ) { unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint32_t AccessInfo = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCSymbol * & Sym = HwasanMemaccessSymbols [ { Reg , AccessInfo } ] ; if ( ! Sym ) { if ( ! TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) report_fatal_error ( <STR_LIT> ) ; std :: string SymName = <STR_LIT> + utostr ( Reg - <STR_LIT> ) + <STR_LIT> + utostr ( AccessInfo ) ; Sym = OutContext . getOrCreateSymbol ( SymName ) ;


<s> NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; const SDLoc & dl ( Op ) ; switch ( Op1 . getOpcode ( ) ) { case <STR_LIT> : if ( SDValue S = cast < BuildVectorSDNode > ( Op1 ) -> getSplatValue ( ) ) return DAG . getNode ( NewOpc , dl , ty ( Op ) , Op0 , S ) ;


<s> Offset = CurDAG -> getIntPtrConstant ( <NUM_LIT> , SDLoc ( Addr ) , true ) ; return true ; } return false ;


<s> for ( MachineOperand & MODef : Def -> operands ( ) ) { if ( ( ! MODef . isReg ( ) ) || ( ! MODef . isDef ( ) ) ) continue ; unsigned DefReg = MODef . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( DefReg ) ) { IsDead = false ; break ; } for ( MachineInstr & Use : MRI -> use_instructions ( Reg ) ) { if ( & Use == Def ) continue ; if ( DeadInstr . find ( & Use ) == DeadInstr . end ( ) ) { IsDead = false ;


<s> Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; MinSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; bool Changed = false ; CmpConv . runOnMachineFunction ( MF ) ;

for ( auto * I : depth_first ( DomTree ) ) if ( tryConvert ( I -> getBlock ( ) ) ) Changed = true ;


<s> for ( MachineInstr * MI : EmittedInstrs ) { if ( ! MI || ! <ISA_LIT>InstrInfo :: isSMRD ( * MI ) ) break ; addRegsToSet ( MI -> defs ( ) , ClauseDefs ) ; addRegsToSet ( MI -> uses ( ) , ClauseUses ) ; } if ( ClauseDefs . empty ( ) ) return <NUM_LIT> ; if ( SMEM -> mayStore ( ) ) return <NUM_LIT> ; addRegsToSet ( SMEM -> defs ( ) , ClauseDefs ) ; addRegsToSet ( SMEM -> uses ( ) , ClauseUses ) ; std :: vector < unsigned > Result ( std :: max ( ClauseDefs . size ( ) , ClauseUses . size ( ) ) ) ; std :: vector < unsigned > :: iterator End ; End = std :: set_intersection ( ClauseDefs . begin ( ) , ClauseDefs . end ( ) , ClauseUses . begin ( ) , ClauseUses . end ( ) , Result . begin ( ) ) ; if ( End != Result . begin ( ) ) return <NUM_LIT> ;


<s> BlockT * curBlk = * iter ; InstrT * curInstr = CFGTraits :: getReturnInstr ( curBlk ) ; if ( curInstr ) { curInstr -> eraseFromParent ( ) ; } curBlk -> addSuccessor ( dummyExitBlk ) ; if ( DEBUGME ) { errs ( ) << <STR_LIT> << curBlk -> getNumber ( ) << <STR_LIT> ;


<s> return ( current_function_calls_alloca || current_function_args_info . nregs == <NUM_LIT> || current_function_varargs || get_frame_size ( ) > <NUM_LIT> ) ;


<s> return llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( CPUType , CPUSubtype ) ;


<s> if ( <ISA_LIT>FI -> hasPreallocatedCall ( ) ) return true ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnableBasePointer ) return false ;

bool CantUseFP = hasStackRealignment ( MF ) ;


<s> UseInlineJumpTables = ! NoInlineJumpTables ; UseConstIslands = true ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ;


<s> if ( MSA_SUPPORTED_MODE_P ( GET_MODE ( dest ) ) ) mips_split_128bit_move ( dest , src ) ; else if ( FP_REG_RTX_P ( dest ) || FP_REG_RTX_P ( src ) ) { if ( ! TARGET_64BIT && GET_MODE ( dest ) == DImode ) emit_insn ( gen_move_doubleword_fprdi ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == DFmode ) emit_insn ( gen_move_doubleword_fprdf ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V2SFmode ) emit_insn ( gen_move_doubleword_fprv2sf ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V2SImode ) emit_insn ( gen_move_doubleword_fprv2si ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V4HImode ) emit_insn ( gen_move_doubleword_fprv4hi ( dest , src ) ) ; else if ( ! TARGET_64BIT && GET_MODE ( dest ) == V8QImode ) emit_insn ( gen_move_doubleword_fprv8qi ( dest , src ) ) ; else if ( TARGET_64BIT && GET_MODE ( dest ) == TFmode ) emit_insn ( gen_move_doubleword_fprtf ( dest , src ) ) ; else gcc_unreachable ( ) ; } else if ( REG_P ( dest ) && REGNO ( dest ) == MD_REG_FIRST ) { low_dest = mips_subword ( dest , false ) ; mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthidi_ti ( dest , mips_subword ( src , true ) , low_dest ) ) ; else emit_insn ( gen_mthisi_di ( dest , mips_subword ( src , true ) , low_dest ) ) ;


<s> addPass ( new RegBankSelect ( ) ) ; return false ;


<s> int Off = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Reg ; computeIndirectRegAndOffset ( Vec , Reg , Off ) ;

MachineInstr * MovRel = BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Reg ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( Vec , RegState :: Implicit ) ;


<s> static bool removeTerminatorBit ( const <ISA_LIT>InstrInfo & TII , MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { bool RegSrc = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ; MI . setDesc ( TII . get ( RegSrc ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { bool RegSrc = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ; MI . setDesc ( TII . get ( RegSrc ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : {


<s> while ( ! MI . getOperand ( i ) . isFI ( ) ) ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; frame_index = MI . getOperand ( i ) . getIndex ( ) ; offs = MF . getFrameInfo ( ) -> getObjectOffset ( frame_index ) ; const TargetInstrDesc tid = MI . getDesc ( ) ; access_alignment = ( tid . TSFlags & <STR_LIT> ) >> <STR_LIT> ; if ( ! ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) ) { if ( <ISA_LIT>InstrInfo :: check_sconst_fits ( offs , <NUM_LIT> ) ) { MI . getOperand ( i ) . ChangeToImmediate ( offs ) ; return ; } access_alignment = <NUM_LIT> ; } else if ( <ISA_LIT>InstrInfo :: check_uconst_fits ( abs ( offs ) , <NUM_LIT> + access_alignment ) ) { MI . getOperand ( i ) . ChangeToImmediate ( offs >> access_alignment ) ; return ; } if ( offs & ( ( <NUM_LIT> << access_alignment ) - <NUM_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; offs >>= access_alignment ; const TargetRegisterClass * c ; if ( tid . TSFlags & <STR_LIT> ) c = <STR_LIT> ; else c = <STR_LIT> ; reg = r -> FindUnusedReg ( c ) ; if ( reg == <NUM_LIT> ) { reg = r -> scavengeRegister ( c , MBBI , <NUM_LIT> ) ; } unsigned side_a = ( c == <STR_LIT> ) ; if ( <ISA_LIT>InstrInfo :: check_sconst_fits ( offs , <NUM_LIT> ) ) { <ISA_LIT>InstrInfo :: addFormOp ( <ISA_LIT>InstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( side_a ? mvk_1 : mvk_2 ) ) . addReg ( reg , RegState :: Define ) . addImm ( offs ) ) , <STR_LIT> , false ) ; } else { <ISA_LIT>InstrInfo :: addFormOp ( <ISA_LIT>InstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( side_a ? mvkl_1 : mvkl_2 ) ) . addReg ( reg , RegState :: Define ) . addImm ( offs ) ) , <STR_LIT> , false ) ; <ISA_LIT>InstrInfo :: addFormOp ( <ISA_LIT>InstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( side_a ? mvkh_1 : mvkh_2 ) ) . addReg ( reg , RegState :: Define ) . addImm ( offs ) . addReg ( reg ) ) , <STR_LIT> , false ) ; }

MI . getOperand ( i ) . ChangeToRegister ( reg , false , false , true ) ;


<s> SMLoc getLoc ( ) const { return Parser . getTok ( ) . getLoc ( ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDFormAddr ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Index ) { return DFormAddressPredicate ( Op , N , Base , Index , <ISA_LIT>FrameInfo :: minFrameOffset ( ) , <ISA_LIT>FrameInfo :: maxFrameOffset ( ) ) ;


<s> BasicBlock * Target = Term -> getSuccessor ( <NUM_LIT> ) ; PHINode * Broken = PHINode :: Create ( Int64 , <NUM_LIT> , <STR_LIT> , & Target -> front ( ) ) ; Value * Cond = Term -> getCondition ( ) ; Term -> setCondition ( BoolTrue ) ; Value * Arg = handleLoopCondition ( Cond , Broken , L , Term ) ; for ( pred_iterator PI = pred_begin ( Target ) , PE = pred_end ( Target ) ;


<s> uint32_t Imm = C -> getZExtValue ( ) ; uint32_t SOffset , ImmOffset ; if ( <STR_LIT> ( Imm , SOffset , ImmOffset , Subtarget , Alignment ) ) { Offsets [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( SOffset , DL , <STR_LIT> ) ; Offsets [ <NUM_LIT> ] = DAG . getTargetConstant ( ImmOffset , DL , <STR_LIT> ) ; return SOffset + ImmOffset ; } } if ( DAG . isBaseWithConstantOffset ( CombinedOffset ) ) { SDValue N0 = CombinedOffset . getOperand ( <NUM_LIT> ) ; SDValue N1 = CombinedOffset . getOperand ( <NUM_LIT> ) ; uint32_t SOffset , ImmOffset ; int Offset = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; if ( Offset >= <NUM_LIT> && <STR_LIT> ( Offset , SOffset , ImmOffset , Subtarget , Alignment ) ) { Offsets [ <NUM_LIT> ] = N0 ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( SOffset , DL , <STR_LIT> ) ; Offsets [ <NUM_LIT> ] = DAG . getTargetConstant ( ImmOffset , DL , <STR_LIT> ) ; return <NUM_LIT> ; } } Offsets [ <NUM_LIT> ] = CombinedOffset ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;

Offsets [ <NUM_LIT> ] = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; if ( TS ) TS -> emitAbiVersion ( <NUM_LIT> ) ; } if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is<ISA_LIT>64 ( ) || TM . getRelocationModel ( ) != Reloc :: PIC_ ) return AsmPrinter :: EmitStartOfAsmFile ( M ) ; if ( M . getPICLevel ( ) == PICLevel :: SmallPIC ) return AsmPrinter :: EmitStartOfAsmFile ( M ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ) ; MCSymbol * TOCSym = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; MCSymbol * CurrentPos = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( CurrentPos ) ; const MCExpr * tocExpr = MCBinaryExpr :: createAdd ( MCSymbolRefExpr :: create ( CurrentPos , OutContext ) , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; OutStreamer -> EmitAssignment ( TOCSym , tocExpr ) ;

OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ;


<s> fn_type = EPIPHANY_FUNCTION_NORMAL ; for ( a = DECL_ATTRIBUTES ( decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) ; if ( name == get_identifier ( <STR_LIT> ) ) fn_type = EPIPHANY_FUNCTION_INTERRUPT ; } last_fn = decl ; return fn_type ;


return Subtarget -> isTargetKnownWindowsMSVC ( ) && ! Subtarget -> is64Bit ( ) ;


<s> Register ApertureReg = getSegmentAperture ( AddrSpace , MRI , B ) ; auto Unmerge = B . buildUnmerge ( LLT :: scalar ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register Hi32 = Unmerge . getReg ( <NUM_LIT> ) ; B . buildICmp ( ICmpInst :: ICMP_EQ , MI . getOperand ( <NUM_LIT> ) , Hi32 , ApertureReg ) ;


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_ARM , false ) {


<s> uint32_t Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Kind ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; char * InstAddr = Data . data ( ) + Offset ; Value = adjustFixupValue ( Kind , FixupValue ) ; if ( ! Value ) return ; int sValue = ( int ) Value ; switch ( ( unsigned ) Kind ) { default : return ; case fixup_<ISA_LIT>_B7_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B7_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B9_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B9_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B13_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B13_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B15_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ;


<s> unsigned Op1 = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; bool KillsOp1 = MI -> killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI -> RemoveOperand ( <NUM_LIT> ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCT ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> if ( MBB . getParent ( ) -> getFrameInfo ( ) -> isReturnAddressTaken ( ) && MBB . getParent ( ) -> getRegInfo ( ) . isLiveIn ( Reg ) ) return false ; }


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedFrameMoves ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) {

int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ;


<s> SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Index , Table ) ; if ( Subtarget -> isThumb2 ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI , UId ) ; } if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , NULL , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI , UId ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , NULL , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI , UId ) ; }


<s> rtx in_pat = PATTERN ( in_insn ) ; if ( GET_CODE ( in_pat ) != PARALLEL ) return false ; for ( int i = <NUM_LIT> ; i < XVECLEN ( in_pat , <NUM_LIT> ) ; i ++ ) { rtx in_exp = XVECEXP ( in_pat , <NUM_LIT> , i ) ; if ( GET_CODE ( in_exp ) == CLOBBER || GET_CODE ( in_exp ) == USE || GET_CODE ( in_exp ) == TRAP_IF ) continue ; gcc_assert ( GET_CODE ( in_exp ) == SET ) ; if ( ! alpha_store_data_bypass_p_1 ( out_insn , in_exp ) ) return false ; } return true ;


case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ; if ( NewSetCC . getNode ( ) ) return NewSetCC ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && ( cast < ConstantSDNode > ( Op1 ) -> getZExtValue ( ) == <NUM_LIT> || cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ cast < ConstantSDNode > ( Op1 ) -> isNullValue ( ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } } bool isFP = Op1 . getValueType ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , isFP , Op0 , Op1 , DAG ) ;

if ( <ISA_LIT>CC == <STR_LIT> ) return SDValue ( ) ;


<s> Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; SupportsDebugInformation = true ; MaxInstLength = <NUM_LIT> ; switch ( TheTriple . getOS ( ) ) { case Triple :: NetBSD : ExceptionsType = ExceptionHandling :: DwarfCFI ; break ;


<s> bool <ISA_LIT>AsmTypeCheck :: popRefType ( SMLoc ErrorLoc ) { if ( Stack . empty ( ) ) { return typeError ( ErrorLoc , StringRef ( <STR_LIT> ) ) ; } auto PVT = Stack . pop_back_val ( ) ;


<s> reset ( * Begin , LiveRegsCopy ) ; return advance ( End ) ;


<s> static __inline __m64 _mm_setzero_si64 ( void ) {


<s> SMLoc Loc = getLexer ( ) . getLoc ( ) ;

getParser ( ) . eatToEndOfStatement ( ) ;


<s> if ( Alignment < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Alignment , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { return scalarizeVectorStore ( StoreNode , DAG ) ; } if ( StoreNode -> isTruncatingStore ( ) ) { return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; } ElementCount EC = MemVT . getVectorElementCount ( ) ; if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && EC . isKnownEven ( ) && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( EC . getKnownMinValue ( ) / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { assert ( StoreNode -> getValue ( ) -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } return SDValue ( ) ;


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; if ( Op -> getOpcode ( ) == <STR_LIT> && isNullConstant ( LHS ) && isNullConstant ( RHS ) ) { Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; return ; } } break ; case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) return ; KnownBits KnownRHS = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known = KnownBits :: commonBits ( Known , KnownRHS ) ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Lowering ( * TM . getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ;

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveNaN2008 ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_NAN2008 ;


<s> static DecodeStatus decodeOperand_AReg_64 ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { auto DAsm = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; return addOperand ( Inst , DAsm -> decodeSrcOp ( <ISA_LIT>Disassembler :: OPW64 , Imm | <NUM_LIT> ) ) ;


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> int size ; CUMULATIVE_ARGS * ca = get_cumulative_args ( pcum_v ) ; size = ( GET_MODE_SIZE ( arg . mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( arg . end_marker_p ( ) ) return GEN_INT ( <NUM_LIT> ) ; if ( TARGET_FPU && ( ( GET_MODE_CLASS ( arg . mode ) == MODE_FLOAT && GET_MODE_SIZE ( arg . mode ) <= UNITS_PER_HWFPVALUE ) || ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( arg . mode ) <= UNITS_PER_HWFPVALUE * <NUM_LIT> ) ) ) { if ( ca -> frcount + size <= MAX_ARGS_IN_FP_REGISTERS ) return gen_rtx_REG ( arg . mode , FP_ARG_FIRST + ca -> frcount ) ; else return NULL_RTX ; }

if ( ca -> grcount + size <= MAX_ARGS_IN_GP_REGISTERS ) return gen_rtx_REG ( arg . mode , ca -> grcount + GP_ARG_FIRST ) ;


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) return true ; if ( Mnemonic == <STR_LIT> ) return true ; return false ;


<s> machine_mode mode ; gcc_assert ( MEM_P ( mem ) ) ; callee = XEXP ( mem , <NUM_LIT> ) ; mode = GET_MODE ( callee ) ; gcc_assert ( mode == Pmode ) ;

if ( SYMBOL_REF_P ( callee ) ? ( aarch64_is_long_call_p ( callee ) || aarch64_is_noplt_call_p ( callee ) ) : ! REG_P ( callee ) ) XEXP ( mem , <NUM_LIT> ) = force_reg ( mode , callee ) ;


<s> uint64_t Val ; if ( ! isa < ConstantSDNode > ( N ) ) return SDValue ( ) ; Val = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; if ( ST -> isThumb1Only ( ) ) {

if ( Val <= <NUM_LIT> || ~ Val <= <NUM_LIT> ) return DAG . getConstant ( Val , dl , <STR_LIT> ) ;


<s> case ARC_TUNE_ARCHS4X : case ARC_TUNE_ARCHS4XD : return <NUM_LIT> ; default : break ;


<s> REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return ! HONOR_SIGNED_ZEROS ( GET_MODE ( x ) ) ; return REAL_VALUES_EQUAL ( r , dconst0 ) ;


<s> void initialize ( unsigned LHS , unsigned RHS ) { MachineRegisterInfo & MRI = True -> getParent ( ) -> getRegInfo ( ) ; LHSReg = LHS ; RHSReg = RHS ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( LHS ) ) { MachineInstr * DefI = MRI . getVRegDef ( LHS ) ; if ( DefI -> getOpcode ( ) == <STR_LIT> ) { LHSReg = <NUM_LIT> ; LHSImm = DefI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } } if ( ! TargetRegisterInfo :: isPhysicalRegister ( RHSReg ) ) { MachineInstr * DefI = MRI . getVRegDef ( RHSReg ) ; if ( DefI -> getOpcode ( ) == <STR_LIT> ) { RHSReg = <NUM_LIT> ; RHSImm = DefI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } }


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget -> isABI_N64 ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG , Subtarget -> isABI_N32 ( ) || Subtarget -> isABI_N64 ( ) ) ;


<s> ; } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ! CurDAG -> haveNoCommonBitsSet ( Addr . getOperand ( <NUM_LIT> ) , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; } else { return false ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ;

Base = Addr . getOperand ( <NUM_LIT> ) ;


<s> VLIWResourceModel ( const TargetSubtargetInfo & STI , const TargetSchedModel * SM ) : SchedModel ( SM ) , TotalPackets ( <NUM_LIT> ) { ResourcesModel = STI . getInstrInfo ( ) -> CreateTargetScheduleState ( STI ) ; assert ( ResourcesModel && <STR_LIT> ) ; Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ; ResourcesModel -> clearResources ( ) ;


<s> case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; }


<s> if ( ! CONST_INT_P ( x ) ) return false ; return IN_RANGE ( INTVAL ( x ) , - <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isPhysicalRegister ( DstReg ) ) return true ; const TargetRegisterClass * RC = guessRegClass ( DstReg , MRI , TRI , RBI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ;


<s> auto SysReg = <STR_LIT> ( Imm ) ; if ( SysReg && SysReg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) O << SysReg -> Name ; else O << Imm ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftExpr ) ; if ( ! CE ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } Imm = CE -> getValue ( ) ; if ( Imm < <NUM_LIT> || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) || ( ( ShiftTy == <STR_LIT> || ShiftTy == <STR_LIT> ) && Imm > <NUM_LIT> ) ) { Error ( ImmLoc , <STR_LIT> ) ; return - <NUM_LIT> ; } if ( Imm == <NUM_LIT> ) ShiftTy = <STR_LIT> ; } else if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) ) { SMLoc L = Parser . getTok ( ) . getLoc ( ) ; EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; ShiftReg = tryParseRegister ( ) ; if ( ShiftReg == - <NUM_LIT> ) { Error ( L , <STR_LIT> ) ; return - <NUM_LIT> ; } } else {

Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ;