<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( ( MCID . TSFlags & Flag ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) {


<s> uint64_t <ISA_LIT>BranchExpansion :: computeOffsetFromTheBeginning ( int MBB ) { uint64_t Offset = <NUM_LIT> ;

for ( int N = <NUM_LIT> ; N < MBB ; ++ N ) Offset += MBBInfos [ N ] . Size ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & ST , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( ST ) , TII ( tii ) {


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> && MI . getNumOperands ( ) > <NUM_LIT> ) { MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { StringRef FuncName = MO . getGlobal ( ) -> getName ( ) ;

if ( FuncName . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) {


<s> bool nonpipelinedVFP ( ) const { return NonpipelinedVFP ;


<s> addr = force_reg ( Pmode , XEXP ( src , <NUM_LIT> ) ) ; scratch1 = gen_reg_rtx ( Pmode ) ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > <NUM_LIT> && ! optimize_size ) { emit_move_insn ( out , addr ) ; ix86_expand_strlensi_unroll_1 ( out , src , align ) ; if ( TARGET_64BIT ) emit_insn ( gen_subdi3 ( out , out , addr ) ) ; else emit_insn ( gen_subsi3 ( out , out , addr ) ) ; } else { rtx unspec ; scratch2 = gen_reg_rtx ( Pmode ) ; scratch3 = gen_reg_rtx ( Pmode ) ; scratch4 = force_reg ( Pmode , constm1_rtx ) ; emit_move_insn ( scratch3 , addr ) ; eoschar = force_reg ( QImode , eoschar ) ; emit_insn ( gen_cld ( ) ) ; src = replace_equiv_address_nv ( src , scratch3 ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , src , eoschar , align , scratch4 ) , UNSPEC_SCAS ) ; emit_insn ( gen_strlenqi_1 ( scratch1 , scratch3 , unspec ) ) ; if ( TARGET_64BIT ) { emit_insn ( gen_one_cmpldi2 ( scratch2 , scratch1 ) ) ; emit_insn ( gen_adddi3 ( out , scratch2 , constm1_rtx ) ) ; } else { emit_insn ( gen_one_cmplsi2 ( scratch2 , scratch1 ) ) ; emit_insn ( gen_addsi3 ( out , scratch2 , constm1_rtx ) ) ; } } return <NUM_LIT> ;


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ; N0 = LowerCONCAT_VECTORS ( N0 , DAG , ST ) ;


<s> gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ;

rs6000_emit_le_vsx_store ( dest , source , mode ) ;


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI ) : MCELFStreamer ( Context , MAB , OS , Emitter ) {


<s> return __builtin_mve_vaddvq_p_sv16qi ( __a , __p ) ;


<s> unsigned Reg = Op . getReg ( ) ; if ( ! ShowVSRNumsAsVR ) Reg = <ISA_LIT>InstrInfo :: getRegNumForOperand ( MII . get ( MI -> getOpcode ( ) ) , Reg , OpNo ) ; const char * RegName ; RegName = getVerboseConditionRegName ( Reg , MRI . getEncodingValue ( Reg ) ) ; if ( RegName == nullptr ) RegName = getRegisterName ( Reg ) ;

if ( showRegistersWithPercentPrefix ( RegName ) ) O << <STR_LIT> ;


<s> return __builtin_mve_vcaddq_rot270_m_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a , __b , __p ) ;


<s> if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned BrOpc = BBUtils -> isBBInRange ( MI , DestBB , <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; llvm :: RevertLoopEnd ( MI , TII , BrOpc , SkipCmp ) ;


<s> local_fast_math = <NUM_LIT> ; } if ( cmp_mode == DImode ) { if ( ! reg_or_0_operand ( op0 , DImode ) ) op0 = force_reg ( DImode , op0 ) ; if ( ! reg_or_8bit_operand ( op1 , DImode ) ) op1 = force_reg ( DImode , op1 ) ; } if ( signed_comparison_operator ( cmp , VOIDmode ) && ( cmp_mode == DImode || local_fast_math ) && ( op0 == CONST0_RTX ( cmp_mode ) || op1 == CONST0_RTX ( cmp_mode ) ) ) return gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ; if ( ! can_create_pseudo_p ( ) ) return NULL_RTX ; switch ( code ) { case EQ : case LE : case LT : case LEU : case LTU : case UNORDERED : break ; case NE : case ORDERED : code = reverse_condition ( code ) ; cmov_code = EQ ; break ; case GE : case GT : case GEU : case GTU : if ( cmp_mode == DImode && op1 == const0_rtx ) break ; code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; break ; default : gcc_unreachable ( ) ; } if ( cmp_mode == DImode ) { if ( ! reg_or_0_operand ( op0 , DImode ) ) op0 = force_reg ( DImode , op0 ) ; if ( ! reg_or_8bit_operand ( op1 , DImode ) ) op1 = force_reg ( DImode , op1 ) ; } if ( cmp_mode == DFmode && ! local_fast_math ) cmov_mode = CCmode ; tem = gen_reg_rtx ( cmp_mode ) ; emit_move_insn ( tem , gen_rtx_fmt_ee ( code , cmp_mode , op0 , op1 ) ) ;

return gen_rtx_fmt_ee ( cmov_code , cmov_mode , tem , CONST0_RTX ( cmp_mode ) ) ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) {


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , RepeatedMask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ;

if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ;

InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> MVT eVT = VT . getVectorElementType ( ) ; if ( isTypeLegal ( eVT ) ) return true ;


<s> ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getBitcast ( ResVT , ResHi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } } else { unsigned ReducedSizeInBits = ReducedVT . getSizeInBits ( ) ; if ( ( RegSize % ReducedSizeInBits ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( RegSize / ReducedSizeInBits , DAG . getUNDEF ( ReducedVT ) ) ; Ops [ <NUM_LIT> ] = NewN0 ; NewN0 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; Ops [ <NUM_LIT> ] = NewN1 ; NewN1 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; if ( Mode == MULU8 || Mode == MULS8 ) { SDValue Mul = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue Res = DAG . getNode ( Mode == MULU8 ? <STR_LIT> : <STR_LIT> , DL , ResVT , Mul ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } else { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue Res = getUnpackl ( DAG , DL , OpsVT , MulLo , MulHi ) ; Res = DAG . getBitcast ( ResVT , Res ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; }


<s> static bool isSRL16 ( const SDValue & Op ) { if ( Op . getOpcode ( ) != <STR_LIT> ) return false ;

if ( auto Const = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return Const -> getZExtValue ( ) == <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSRA_PARTS ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; MVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && VT == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; MVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Tmp1 ) ;

SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ;


<s> int Base = ( int ) fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( FGR64RegsTable [ Reg ] ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ Base ] ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> return makeArrayRef ( <STR_LIT> . begin ( ) , <STR_LIT> . getNumRegs ( ) ) ;


<s> void <ISA_LIT>LowerControlFlow :: emitElse ( MachineInstr & MI ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) ; bool ExecModified = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; MachineBasicBlock :: iterator Start = MBB . begin ( ) ; unsigned CopyReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , Start , DL , TII -> get ( <STR_LIT> ) , CopyReg ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; unsigned SaveReg = ExecModified ? MRI -> createVirtualRegister ( & <STR_LIT> ) : DstReg ; MachineInstr * OrSaveExec = BuildMI ( MBB , Start , DL , TII -> get ( <STR_LIT> ) , SaveReg ) . addReg ( CopyReg ) ; MachineBasicBlock * DestBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: iterator ElsePt ( MI ) ; if ( ExecModified ) { MachineInstr * And = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( <STR_LIT> ) . addReg ( SaveReg ) ; if ( LIS ) LIS -> InsertMachineInstrInMaps ( * And ) ; } MachineInstr * Xor = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( DstReg ) ; MachineInstr * Branch = BuildMI ( MBB , ElsePt , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) ;


<s> virtual bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const {


<s> SDLoc dl ( NewResChain ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewResChain , DAG . getUNDEF ( <STR_LIT> ) ) ; assert ( TF . getNode ( ) != NewResChain . getNode ( ) && <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( ResChain , TF ) ; DAG . UpdateNodeOperands ( TF . getNode ( ) , ResChain , NewResChain ) ;


<s> bool isIdxen ( ) const { return isImmTy ( ImmTyIdxen ) ;


<s> if ( I -> isBranch ( ) || I -> isReturn ( ) ) { RemovedSize += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; ++ Count ; } I = Next ;


<s> EVT IntPtr = getPointerTy ( ) ; EVT SPTy = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;

Chain = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>StackPtr , SPTy ) . getValue ( <NUM_LIT> ) ;


<s> APInt MaskInt64 ( <NUM_LIT> , finalMask , <NUM_LIT> ) ; SDValue MaskNode64 = DAG -> getConstant ( MaskInt64 , <STR_LIT> ) ; if ( RegisterWidth == <NUM_LIT> ) { return MaskNode64 ; } else if ( RegisterWidth == <NUM_LIT> ) { SDValue Pool [ ] = { MaskNode64 , MaskNode64 } ; return BUILD_VECTOR ( <STR_LIT> , Pool ) ; } else if ( RegisterWidth == <NUM_LIT> ) { SDValue Pool [ ] = { MaskNode64 , MaskNode64 , MaskNode64 , MaskNode64 } ; return BUILD_VECTOR ( <STR_LIT> , Pool ) ;


<s> const MCExpr * Value ; MCAsmParser & Parser = getParser ( ) ; if ( Parser . parseIdentifier ( Name ) ) reportParseError ( <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return reportParseError ( <STR_LIT> ) ; Lex ( ) ; if ( Parser . parseExpression ( Value ) ) return reportParseError ( <STR_LIT> ) ;

MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Name ) ;


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const {


<s> getAddrMode2OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; unsigned Rn = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; uint32_t Binary = getAddrMode2OffsetOpValue ( MI , OpIdx + <NUM_LIT> , Fixups ) ; Binary |= Rn << <NUM_LIT> ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ;


<s> void MetadataStreamerV2 :: verify ( StringRef HSAMetadataString ) const { errs ( ) << <STR_LIT> ; HSAMD :: Metadata FromHSAMetadataString ; if ( fromString ( std :: string ( HSAMetadataString ) , FromHSAMetadataString ) ) { errs ( ) << <STR_LIT> ; return ; } std :: string ToHSAMetadataString ; if ( toString ( FromHSAMetadataString , ToHSAMetadataString ) ) {


<s> unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; }


<s> Inst . addOperand ( MCOperand :: createImm ( Add - Imm ) ) ; return Success ;


<s> for ( unsigned i = StartIdx ; i < MI -> getNumOperands ( ) ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( std :: find ( Ops . begin ( ) , Ops . end ( ) , i ) != Ops . end ( ) ) { MIB . addOperand ( MachineOperand :: CreateImm ( StackMaps :: IndirectMemRefOp ) ) ;

MIB . addOperand ( MachineOperand :: CreateFI ( FrameIndex ) ) ;


<s> bool LowOverheadLoop :: AddVCTP ( MachineInstr * MI ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; if ( VCTPs . empty ( ) ) { VCTPs . push_back ( MI ) ; return true ; } MachineInstr * Prev = VCTPs . back ( ) ; if ( ! Prev -> getOperand ( <NUM_LIT> ) . isIdenticalTo ( MI -> getOperand ( <NUM_LIT> ) ) || ! RDA . hasSameReachingDef ( Prev , MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) . asMCReg ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ;


<s> ReversePostOrderTraversal < MachineFunction * > RPO ( & MF ) ; for ( MachineBasicBlock * MBB : RPO ) { int64_t Offset = - <NUM_LIT> ; for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) Offset = std :: max ( Offset , OutOffset [ Pred ] ) ; if ( Offset == - <NUM_LIT> ) Offset = INT32_MAX ; for ( MachineInstr & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { int64_t Amount = getWinAllocaAmount ( & MI , MRI ) ; Lowering L = getLowering ( Offset , Amount ) ; Lowerings [ & MI ] = L ; switch ( L ) { case Sub : Offset += Amount ; break ; case TouchAndSub : Offset = Amount ; break ; case Probe : Offset = <NUM_LIT> ; break ; } } else if ( MI . isCall ( ) || isPushPop ( MI ) ) { Offset = <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { Offset -= MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( info -> first_gp_reg_save == <NUM_LIT> && info -> first_fp_reg_save == <NUM_LIT> && info -> first_altivec_reg_save == LAST_ALTIVEC_REGNO + <NUM_LIT> && ! info -> lr_save_p && ! info -> cr_save_p && info -> vrsave_size == <NUM_LIT> && ! info -> push_p ) return <NUM_LIT> ; } return <NUM_LIT> ;


<s> if ( CFn . hasFnAttribute ( <STR_LIT> ) ) F . addFnAttr ( CFn . getFnAttribute ( <STR_LIT> ) ) ;

<ISA_LIT>GenInstrInfo :: mergeOutliningCandidateAttributes ( F , Candidates ) ;


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small :


<s> enum riscv_privilege_levels new_interrupt_type = riscv_get_interrupt_type ( newdecl ) ; if ( ( old_interrupt_type != UNKNOWN_MODE ) && ( new_interrupt_type != UNKNOWN_MODE ) && ( old_interrupt_type != new_interrupt_type ) ) error ( <STR_LIT> , <STR_LIT> ) ; combined_attrs = merge_attributes ( DECL_ATTRIBUTES ( olddecl ) , DECL_ATTRIBUTES ( newdecl ) ) ; return combined_attrs ;


<s> O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; unsigned PTXVersion = nvptxSubtarget . getPTXVersion ( ) ; O << <STR_LIT> << ( PTXVersion / <NUM_LIT> ) << <STR_LIT> << ( PTXVersion % <NUM_LIT> ) << <STR_LIT> ; O << <STR_LIT> ; O << nvptxSubtarget . getTargetName ( ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( ! nvptxSubtarget . hasDouble ( ) ) O << <STR_LIT> ; } if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ;


<s> EVT PTy = getPointerTy ( ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( * getDataLayout ( ) ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , MemVT , false , false , <NUM_LIT> ) ;


<s> if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm / <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ NumNarrows ; return true ; } if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; if ( MI -> mayLoadOrStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( * MI , PredReg ) != <STR_LIT> ) break ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ;


<s> unsigned getMinimumNopSize ( ) const override { return <NUM_LIT> ;


<s> const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP ) continue ; unsigned AS = GEP -> getAddressSpace ( ) ; unsigned Threshold = <NUM_LIT> ; if ( AS == ASST . PRIVATE_ADDRESS ) Threshold = ThresholdPrivate ; else if ( AS == ASST . LOCAL_ADDRESS ) Threshold = ThresholdLocal ; else continue ; if ( UP . Threshold >= Threshold ) continue ; if ( AS == ASST . PRIVATE_ADDRESS ) { const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr , DL ) ) ; if ( ! Alloca || ! Alloca -> isStaticAlloca ( ) ) continue ; Type * Ty = Alloca -> getAllocatedType ( ) ; unsigned AllocaSize = Ty -> isSized ( ) ? DL . getTypeAllocSize ( Ty ) : <NUM_LIT> ; if ( AllocaSize > MaxAlloca ) continue ; } else if ( AS == ASST . LOCAL_ADDRESS ) { LocalGEPsSeen ++ ; if ( LocalGEPsSeen > <NUM_LIT> || L -> getLoopDepth ( ) > <NUM_LIT> || ( ! isa < GlobalVariable > ( GEP -> getPointerOperand ( ) ) && ! isa < Argument > ( GEP -> getPointerOperand ( ) ) ) ) continue ; } bool HasLoopDef = false ; for ( const Value * Op : GEP -> operands ( ) ) {

const Instruction * Inst = dyn_cast < Instruction > ( Op ) ;


<s> if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = FixedVectorType :: get ( SubVecTy -> getElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } auto Mask = SVI -> getShuffleMask ( ) ; Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { SmallVector < Value * , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { unsigned IdxI = StoreCount * LaneLen * Factor + i ; if ( Mask [ IdxI ] >= <NUM_LIT> ) { Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Mask [ IdxI ] , LaneLen , <NUM_LIT> ) ) ) ;


if ( ! Register :: isVirtualRegister ( Reg ) ) return nullptr ;


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; if ( ExtraCode [ <NUM_LIT> ] >= 'A' && ExtraCode [ <NUM_LIT> ] <= 'Z' ) { const MachineOperand & RegOp = MI -> getOperand ( OpNum ) ; assert ( RegOp . isReg ( ) && <STR_LIT> <STR_LIT> ) ; Register Reg = RegOp . getReg ( ) ; unsigned ByteNumber = ExtraCode [ <NUM_LIT> ] - 'A' ; unsigned OpFlags = MI -> getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ; unsigned NumOpRegs = InlineAsm :: getNumOperandRegisters ( OpFlags ) ; ( void ) NumOpRegs ; const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ;


<s> break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' :

if ( type -> isFloatTy ( ) ) weight = CW_Register ;


<s> auto CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;

Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchCondition ( CC ) ) ;


<s> EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N0 ) ; EVT SrcVT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT , ResVT . getSizeInBits ( ) / SrcVT . getSizeInBits ( ) ) ; EVT CCVT = SrcVT . changeVectorElementTypeToInteger ( ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ;

SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , CCVT , LHS , RHS , N0 . getOperand ( <NUM_LIT> ) ) ;


<s> return new <ISA_LIT>TargetELFStreamer ( S ) ;


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ;

MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ;


<s> SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * Disp ; if ( getParser ( ) . parseExpression ( Disp ) ) return MatchOperand_NoMatch ; unsigned Index = <NUM_LIT> ; unsigned Base = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Parser . Lex ( ) ; Register Reg ; OperandMatchResultTy Result = parseRegister ( Reg , 'x' , GR32Regs , true ) ; if ( Result != MatchOperand_Success ) return Result ; if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ! HasIndex ) { Error ( Reg . StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Index = Reg . Number ; Result = parseRegister ( Reg , 'x' , GR32Regs , true ) ; if ( Result != MatchOperand_Success ) return Result ;


<s> modify = build2 ( MODIFY_EXPR , TREE_TYPE ( lhs ) , lhs , lb ) ; append_to_statement_list ( modify , stmts ) ; lhs = build1 ( INDIRECT_REF , pointer_sized_int_node , build2 ( POINTER_PLUS_EXPR , bnd_ptr , var_p , TYPE_SIZE_UNIT ( pointer_sized_int_node ) ) ) ;

modify = build2 ( MODIFY_EXPR , TREE_TYPE ( lhs ) , lhs , ub ) ;


<s> <ISA_LIT>ISelAddressMode ( ) : BaseType ( RegBase ) , isRIPRel ( false ) , Scale ( <NUM_LIT> ) , IndexReg ( ) , Disp ( <NUM_LIT> ) , GV ( <NUM_LIT> ) , CP ( <NUM_LIT> ) , ES ( <NUM_LIT> ) , JT ( - <NUM_LIT> ) , Align ( <NUM_LIT> ) {


<s> MaxKernArgAlign = assumeAligned ( YamlMFI . MaxKernArgAlign ) ; LDSSize = YamlMFI . LDSSize ; DynLDSAlign = YamlMFI . DynLDSAlign ; HighBitsOf32BitAddress = YamlMFI . HighBitsOf32BitAddress ; Occupancy = YamlMFI . Occupancy ; IsEntryFunction = YamlMFI . IsEntryFunction ; NoSignedZerosFPMath = YamlMFI . NoSignedZerosFPMath ; MemoryBound = YamlMFI . MemoryBound ;


<s> static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const BitMode32CalleeSavedRC [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; if ( Subtarget . isSingleFloat ( ) ) return SingleFloatOnlyCalleeSavedRC ;


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , bool IsLittleEndian , uint8_t OSABI ) { auto MOTW = llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( Is64Bit , OSABI ) ;

return createELFObjectWriter ( std :: move ( MOTW ) , OS , IsLittleEndian ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ST ) , Subtarget ( ST ) {


<s> if ( ! TARGET_PCREL || GET_MODE ( dest ) != Pmode ) return false ; if ( ! SYMBOL_REF_P ( src ) && ! LABEL_REF_P ( src ) && GET_CODE ( src ) != CONST ) return false ; enum insn_form iform = address_to_insn_form ( src , Pmode , NON_PREFIXED_DEFAULT ) ;

return ( iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL ) ;


<s> assert ( T == <NUM_LIT> || T == <NUM_LIT> ) ; return T == <NUM_LIT> ? Type == Zero : ( T == <NUM_LIT> ? Type == One : false ) ;


<s> const MCExpr * OffsetExpr = MCConstantExpr :: create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: createAdd ( Expr , OffsetExpr , Ctx ) ; } } Fixups . push_back ( MCFixup :: create ( Offset , Expr , ( MCFixupKind ) Kind , Loc ) ) ; if ( AllowTLS && OpNum + <NUM_LIT> < MI . getNumOperands ( ) ) { const MCOperand & MOTLS = MI . getOperand ( OpNum + <NUM_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MOTLS . getExpr ( ) , ( MCFixupKind ) <STR_LIT> , Loc ) ) ; }


<s> unsigned getSmallDataThreshold ( ) const {


<s> case <STR_LIT> : { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; const unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const bool DstIsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; auto Q1 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) ; auto Q2 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; auto Q3 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; auto Q4 = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { const uint64_t Imm = MO . getImm ( ) ; Q1 = Q1 . addImm ( Imm & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Q2 = Q2 . addImm ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Q3 = Q3 . addImm ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Q4 = Q4 . addImm ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> if ( MemVT != VT . getVectorElementType ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) continue ; if ( * UI != N ) return SDValue ( ) ; } SDValue Addr = LD -> getOperand ( <NUM_LIT> ) ; SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) ) continue ; if ( User -> isPredecessorOf ( LD ) || LD -> isPredecessorOf ( User ) ) continue ; if ( User -> isPredecessorOf ( Vector . getNode ( ) ) ) continue ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; unsigned NumBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LD -> getOperand ( <NUM_LIT> ) ) ; if ( IsLaneOp ) { Ops . push_back ( Vector ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( Addr ) ; Ops . push_back ( Inc ) ;

EVT Tys [ <NUM_LIT> ] = { VT , <STR_LIT> , <STR_LIT> } ;


<s> unsigned Opc = I . getOpcode ( ) ; assert ( ( Opc == TargetOpcode :: G_STORE || Opc == TargetOpcode :: G_LOAD ) && <STR_LIT> ) ; const Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; const RegisterBank & RB = * RBI . getRegBank ( DefReg , MRI , TRI ) ; assert ( I . hasOneMemOperand ( ) ) ; auto & MemOp = * * I . memoperands_begin ( ) ; if ( MemOp . isAtomic ( ) ) { if ( ! MemOp . isUnordered ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( MemOp . getAlignment ( ) < Ty . getSizeInBits ( ) / <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned NewOpc = getLoadStoreOp ( Ty , RB , Opc , MemOp . getAlignment ( ) ) ; if ( NewOpc == Opc ) return false ; <ISA_LIT>AddressMode AM ; <ISA_LIT>SelectAddress ( * MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) , MRI , AM ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ; if ( Opc == TargetOpcode :: G_LOAD ) { I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) ; } else { I . RemoveOperand ( <NUM_LIT> ) ; I . RemoveOperand ( <NUM_LIT> ) ; addFullAddress ( MIB , AM ) . addUse ( DefReg ) ; }

return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ;


<s> for ( BasicBlock * PredBB : predecessors ( BB ) ) { auto PredEndState = FinalStates . find ( PredBB ) ; if ( PredEndState == FinalStates . end ( ) ) return OverdefinedState ; if ( isa < CatchReturnInst > ( PredBB -> getTerminator ( ) ) ) return OverdefinedState ; int PredState = PredEndState -> second ; assert ( PredState != OverdefinedState && <STR_LIT> ) ;

if ( CommonState == OverdefinedState ) CommonState = PredState ;


<s> rtx elt ; REAL_VALUE_TYPE r ; if ( ! const_vec_duplicate_p ( x , & elt ) || GET_CODE ( elt ) != CONST_DOUBLE ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate_p ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst1 ) ) return true ; if ( real_equal ( & r , & dconsthalf ) ) return true ; return false ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) , <ISA_LIT>Lowering ( * tm . getTargetLowering ( ) ) , Subtarget ( & tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , OptForSize ( false ) {


<s> cc_status . value1 = recog_data . operand [ <NUM_LIT> ] ; break ; case CC_SET_ZNV : CC_STATUS_INIT ; cc_status . flags |= CC_NO_CARRY ; cc_status . value1 = recog_data . operand [ <NUM_LIT> ] ; break ; case CC_COMPARE : CC_STATUS_INIT ; cc_status . value1 = SET_SRC ( body ) ; if ( GET_CODE ( cc_status . value1 ) == COMPARE && GET_MODE ( XEXP ( cc_status . value1 , <NUM_LIT> ) ) == SFmode ) cc_status . mdep . fpCC = <NUM_LIT> ; break ; case CC_CLOBBER : CC_STATUS_INIT ; break ; default : gcc_unreachable ( ) ;


<s> if ( ! getCell ( R1 , Inputs , LS1 ) || ! getCell ( R2 , Inputs , LS2 ) ) return false ; bool IsProp1 = LS1 . isProperty ( ) ; bool IsProp2 = LS2 . isProperty ( ) ; if ( IsProp1 ) { uint32_t Prop1 = LS1 . properties ( ) ; if ( IsProp2 ) return evaluateCMPpp ( Cmp , Prop1 , LS2 . properties ( ) , Result ) ; uint32_t NegCmp = Comparison :: negate ( Cmp ) ;

return evaluateCMPrp ( NegCmp , R2 , Prop1 , Inputs , Result ) ;


<s> bool ComplexPatternFuncMutatesDAG ( ) const override {


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ) return false ;

if ( CCInfo . getNextStackOffset ( ) != <NUM_LIT> && isVarArg ) return false ;


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = GPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return Success ;


<s> struct ix86_address parts ; rtx base , index , disp ; int len ; int ok ; if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) return <NUM_LIT> ; ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; len = ( parts . seg == ADDR_SPACE_GENERIC ) ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_64BIT && ! lea && ( SImode_address_operand ( addr , VOIDmode ) || ( parts . base && GET_MODE ( parts . base ) == SImode ) || ( parts . index && GET_MODE ( parts . index ) == SImode ) ) ) len ++ ; base = parts . base ; index = parts . index ; disp = parts . disp ;

if ( base && SUBREG_P ( base ) ) base = SUBREG_REG ( base ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createTargetAsmStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>V9Target , create<ISA_LIT>V9MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ;


<s> fprintf ( asm_out_file , <STR_LIT> ) ; ASM_OUTPUT_ALIGN ( asm_out_file , <NUM_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , buf ) ; fprintf ( asm_out_file , <STR_LIT> ) ; recurse = <NUM_LIT> ; return true ; } else if ( GET_CODE ( x ) == SYMBOL_REF && XSTR ( x , <NUM_LIT> ) [ <NUM_LIT> ] == '.' && DEFAULT_ABI == ABI_AIX ) { const char * name = XSTR ( x , <NUM_LIT> ) ; while ( * name == '.' ) name ++ ;

fprintf ( asm_out_file , <STR_LIT> , name ) ;


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return expandLoadImm ( Inst , IDLoc , Instructions ) ;


<s> return MIB . addReg ( Reg1 , getKillRegState ( isKill1 ) ) . addImm ( <NUM_LIT> ) . addReg ( Reg2 , getKillRegState ( isKill2 ) ) . addImm ( <NUM_LIT> ) ;


<s> if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( auto * DataVTy = dyn_cast < FixedVectorType > ( DataTy ) ) { unsigned NumElts = DataVTy -> getNumElements ( ) ; if ( NumElts == <NUM_LIT> ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ;

return IntWidth == <NUM_LIT> || IntWidth == <NUM_LIT> ;


<s> } unsigned NumVRegs = MF . getRegInfo ( ) . getNumVirtRegs ( ) ; unsigned NumStackRegs = <NUM_LIT> ; unsigned CurReg = MFI . getParams ( ) . size ( ) ; for ( unsigned VRegIdx = <NUM_LIT> ; VRegIdx < NumVRegs ; ++ VRegIdx ) { unsigned VReg = Register :: index2VirtReg ( VRegIdx ) ; if ( MRI . use_empty ( VReg ) ) continue ; if ( MFI . isVRegStackified ( VReg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VReg << <STR_LIT> << ( INT32_MIN | NumStackRegs ) << <STR_LIT> ) ; MFI . setWAReg ( VReg , INT32_MIN | NumStackRegs ++ ) ; continue ; } if ( MFI . getWAReg ( VReg ) == <ISA_LIT>FunctionInfo :: UnusedReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VReg << <STR_LIT> << CurReg << <STR_LIT> ) ; MFI . setWAReg ( VReg , CurReg ++ ) ; }


<s> bool frv_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p ) { return frv_legitimate_address_p_1 ( mode , x , strict_p , FALSE , FALSE ) ;


<s> static bool isShuffleFoldableLoad ( SDValue V ) { while ( V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ;


<s> if ( foldBinOpIntoSelect ( I ) ) return true ; if ( ST -> has16BitInsts ( ) && needsPromotionToI32 ( I . getType ( ) ) && DA -> isUniform ( & I ) && promoteUniformOpToI32 ( I ) ) return true ; if ( UseMul24Intrin && replaceMulWithMul24 ( I ) ) return true ; bool Changed = false ; Instruction :: BinaryOps Opc = I . getOpcode ( ) ; Type * Ty = I . getType ( ) ; Value * NewDiv = nullptr ; unsigned ScalarSize = Ty -> getScalarSizeInBits ( ) ; SmallVector < BinaryOperator * , <NUM_LIT> > Div64ToExpand ; if ( ( Opc == Instruction :: URem || Opc == Instruction :: UDiv || Opc == Instruction :: SRem || Opc == Instruction :: SDiv ) && ScalarSize <= <NUM_LIT> && ! DisableIDivExpand ) { Value * Num = I . getOperand ( <NUM_LIT> ) ; Value * Den = I . getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( & I ) ; Builder . SetCurrentDebugLocation ( I . getDebugLoc ( ) ) ; if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { NewDiv = UndefValue :: get ( VT ) ; for ( unsigned N = <NUM_LIT> , E = VT -> getNumElements ( ) ; N != E ; ++ N ) { Value * NumEltN = Builder . CreateExtractElement ( Num , N ) ;

Value * DenEltN = Builder . CreateExtractElement ( Den , N ) ;


<s> int <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy , TTI :: TargetCostKind CostKind , const Instruction * I ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( CostKind == TTI :: TCK_CodeSize && ISD == <STR_LIT> && ST -> isThumb ( ) && ! ValTy -> isVectorTy ( ) ) { if ( TLI -> getValueType ( DL , ValTy , true ) == <STR_LIT> ) return TTI :: TCC_Expensive ; int Cost = TLI -> getTypeLegalizationCost ( DL , ValTy ) . first ; ++ Cost ; if ( ValTy -> isIntegerTy ( <NUM_LIT> ) ) ++ Cost ;


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const ScheduleDAG * DAG ) : ScoreboardHazardRecognizer ( ItinData , DAG , <STR_LIT> ) , LastMI ( <NUM_LIT> ) {


<s> void printi8mem ( const MCInst * MI , unsigned OpNo ) {


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += <NUM_LIT> ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; else Offset += <NUM_LIT> ; Offset += MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == <NUM_LIT> ) return ;

unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> for ( MachineInstr * MI : LoweredEndCf ) { MachineBasicBlock & MBB = * MI -> getParent ( ) ; auto Next = skipIgnoreExecInstsTrivialSucc ( MBB , std :: next ( MI -> getIterator ( ) ) ) ;

if ( Next == MBB . end ( ) || ! LoweredEndCf . count ( & * Next ) ) continue ;


<s> return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) { return Error ( IDLoc , <STR_LIT> ) ; } ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_PreferE32 : return Error ( IDLoc , <STR_LIT> <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ;


<s> PM . add ( create<ISA_LIT>PrepareModulePass ( ) ) ; switch ( FileType ) { case CGFT_AssemblyFile :

PM . add ( createPrintModulePass ( Out , <STR_LIT> , true ) ) ;


<s> else if ( Lo ) { unsigned TmpReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , TmpReg ) . addImm ( Hi ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , ResultReg ) . addReg ( TmpReg ) . addImm ( Lo ) ;

} else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( IsGPRC ? <STR_LIT> : <STR_LIT> ) , ResultReg ) . addImm ( Hi ) ;


<s> static bool canDemoteGlobalVar ( const GlobalVariable * gv , Function const * & f ) { if ( gv -> hasInternalLinkage ( ) == false ) return false ; const PointerType * Pty = gv -> getType ( ) ; if ( Pty -> getAddressSpace ( ) != llvm :: ADDRESS_SPACE_SHARED ) return false ; const Function * oneFunc = nullptr ; bool flag = usedInOneFunc ( gv , oneFunc ) ; if ( flag == false ) return false ; if ( ! oneFunc ) return false ; f = oneFunc ; return true ;


<s> State = IES_ERROR ; break ; case IES_PLUS : case IES_NOT :


<s> const GlobalValue * GV = N -> getGlobal ( ) ; SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Load ; Entry . Ty = CallTy ; Args . push_back ( Entry ) ;

TargetLowering :: CallLoweringInfo CLI ( DAG ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> MachineBasicBlock & JmpMBB = * JmpI . getParent ( ) ; insertTest ( JmpMBB , JmpI . getIterator ( ) , JmpI . getDebugLoc ( ) , CondReg ) ; JmpI . getOperand ( <NUM_LIT> ) . setImm ( Inverted ? <STR_LIT> : <STR_LIT> ) ; JmpI . findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( true ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; JmpI . dump ( ) ) ;


<s> return LowerToBSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && AsmPieces . size ( ) == <NUM_LIT> && ( AsmPieces [ <NUM_LIT> ] == <STR_LIT> || AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { AsmPieces . clear ( ) ; SplitString ( IA -> getConstraintString ( ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; std :: sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) { return LowerToBSwap ( CI ) ; } } break ; case <NUM_LIT> : if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && Constraints . size ( ) >= <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> ) { SmallVector < StringRef , <NUM_LIT> > Words ;

SplitString ( AsmPieces [ <NUM_LIT> ] , Words , <STR_LIT> ) ;


<s> unsigned Imm = MI . getOperand ( ShiftAmtOperandIdx ) . getImm ( ) ; return Imm & ShiftCountMask ;


<s> const DataLayout * TD = TM . getDataLayout ( ) ; const PointerType * PTy = GVar -> getType ( ) ; Type * ETy = PTy -> getElementType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isPrimitiveType ( ) || ETy -> isIntegerTy ( ) || isa < PointerType > ( ETy ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * Mang -> getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ;


<s> MVT F32VT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; SrcVal = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , F32VT , SrcVal ) ; SrcVT = F32VT ; SrcElementVT = <STR_LIT> ; SrcElementWidth = <NUM_LIT> ; } else if ( SrcElementVT != <STR_LIT> && SrcElementVT != <STR_LIT> && SrcElementVT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; if ( SrcElementWidth == DstElementWidth && SrcElementWidth == SatWidth ) return DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT . getScalarType ( ) ) ) ; if ( SrcElementWidth < SatWidth || SrcElementVT == <STR_LIT> ) return SDValue ( ) ; EVT IntVT = SrcVT . changeVectorElementTypeToInteger ( ) ; SDValue NativeCvt = DAG . getNode ( Op . getOpcode ( ) , DL , IntVT , SrcVal , DAG . getValueType ( IntVT . getScalarType ( ) ) ) ; SDValue Sat ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue MinC = DAG . getConstant ( APInt :: getSignedMaxValue ( SatWidth ) . sextOrSelf ( SrcElementWidth ) , DL , IntVT ) ; SDValue Min = DAG . getNode ( <STR_LIT> , DL , IntVT , NativeCvt , MinC ) ; SDValue MaxC = DAG . getConstant ( APInt :: getSignedMinValue ( SatWidth ) . sextOrSelf ( SrcElementWidth ) , DL , IntVT ) ; Sat = DAG . getNode ( <STR_LIT> , DL , IntVT , Min , MaxC ) ; } else {

SDValue MinC = DAG . getConstant ( APInt :: getAllOnesValue ( SatWidth ) . zextOrSelf ( SrcElementWidth ) , DL , IntVT ) ;


<s> MVT NewDUPVT = <STR_LIT> ( ElementTy , NumElems * <NUM_LIT> ) ; SDValue NewDUP ; if ( IsDUPLANE ) NewDUP = DAG . getNode ( N . getOpcode ( ) , SDLoc ( N ) , NewDUPVT , N . getOperand ( <NUM_LIT> ) , N . getOperand ( <NUM_LIT> ) ) ;

else NewDUP = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , NewDUPVT , N . getOperand ( <NUM_LIT> ) ) ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override {


<s> void LLVMInitializeMandarinAsmPrinter ( ) { RegisterAsmPrinter < MandarinAsmPrinter > X ( TheMandarinTarget ) ;


<s> static bool isCommutedMOVL ( ShuffleVectorSDNode * N , bool V2IsSplat = false , bool V2IsUndef = false ) { return isCommutedMOVLMask ( N -> getMask ( ) , N -> getValueType ( <NUM_LIT> ) , V2IsSplat , V2IsUndef ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; Register FrameReg = RI . getFrameRegister ( MF ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ;

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ;


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && C ) return Op ; if ( Subtarget . hasP9Vector ( ) ) { if ( ( VT == <STR_LIT> ) && ( V2 . getValueType ( ) == <STR_LIT> ) && ( isa < LoadSDNode > ( V2 ) ) ) { SDValue BitcastVector = DAG . getBitcast ( <STR_LIT> , V1 ) ;

SDValue BitcastLoad = DAG . getBitcast ( <STR_LIT> , V2 ) ;


<s> if ( trySkipToken ( AsmToken :: Colon ) ) { SecondIdxLoc = getLoc ( ) ; if ( ! parseExpr ( RegHi ) ) return false ; } else { RegHi = RegLo ; } if ( ! skipToken ( AsmToken :: RBrac , <STR_LIT> ) ) return false ;

if ( ! isUInt < <NUM_LIT> > ( RegLo ) ) {


<s> unsigned Shift = <STR_LIT> ( Val ) ;

return <STR_LIT> ( Val ) == <STR_LIT> && ( Shift == <NUM_LIT> || Shift == <NUM_LIT> ) ;


<s> MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , HRI . getFrameRegister ( ) , VT ) ;


<s> { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; op src [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , } ; int i , j ; for ( i = <NUM_LIT> ; i < sizeof dest / sizeof dest [ <NUM_LIT> ] ; i ++ ) for ( j = <NUM_LIT> ; j < sizeof src / sizeof src [ <NUM_LIT> ] ; j ++ ) define_insn ( & dest [ i ] , & src [ j ] , <STR_LIT> ) ; exit ( <NUM_LIT> ) ;


<s> rtx temp_reg = create_temp_reg_if_possible ( Pmode , reg ) ; tilegx_compute_pcrel_address ( temp_reg , orig ) ; crtl -> uses_pic_offset_table = <NUM_LIT> ; address = temp_reg ; emit_move_insn ( reg , address ) ; return reg ; } else { rtx temp_reg = create_temp_reg_if_possible ( Pmode , reg ) ; gcc_assert ( flag_pic ) ; if ( flag_pic == <NUM_LIT> ) { if ( TARGET_32BIT ) { emit_insn ( gen_add_got16_32bit ( temp_reg , tilegx_got_rtx ( ) , orig ) ) ; } else { emit_insn ( gen_add_got16 ( temp_reg , tilegx_got_rtx ( ) , orig ) ) ; } } else { rtx temp_reg2 = create_temp_reg_if_possible ( Pmode , reg ) ; rtx temp_reg3 = create_temp_reg_if_possible ( Pmode , reg ) ; if ( TARGET_32BIT ) { emit_insn ( gen_mov_got32_step1_32bit ( temp_reg3 , orig ) ) ; emit_insn ( gen_mov_got32_step2_32bit ( temp_reg2 , temp_reg3 , orig ) ) ; } else { emit_insn ( gen_mov_got32_step1 ( temp_reg3 , orig ) ) ; emit_insn ( gen_mov_got32_step2 ( temp_reg2 , temp_reg3 , orig ) ) ; } emit_move_insn ( temp_reg , gen_rtx_PLUS ( Pmode , tilegx_got_rtx ( ) , temp_reg2 ) ) ; } address = temp_reg ; pic_ref = gen_const_mem ( Pmode , address ) ; crtl -> uses_pic_offset_table = <NUM_LIT> ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> pass_visium_reorg ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_visium_reorg , ctxt ) {


<s> const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned OffImm = Opc . getImm ( ) ; bool isAdd = <STR_LIT> ( OffImm ) == <STR_LIT> ; unsigned Amt = <STR_LIT> ( OffImm ) ; <STR_LIT> ShiftOpc = <STR_LIT> ( OffImm ) ;

if ( ShiftOpc == <STR_LIT> ) return false ;


<s> if ( ! lookup_attribute ( <STR_LIT> , attrs ) && ! lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( node ) ) ) { if ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE ) attrs = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , attrs ) ; else if ( lookup_attribute ( <STR_LIT> , attrs ) || lookup_attribute ( <STR_LIT> , attrs ) || lookup_attribute ( <STR_LIT> , attrs ) ) { tree * tail ; for ( tail = attributes ; attrs ; attrs = TREE_CHAIN ( attrs ) ) { if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) ) warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( TREE_PURPOSE ( attrs ) ) ) ; else {

* tail = tree_cons ( TREE_PURPOSE ( attrs ) , NULL_TREE , NULL_TREE ) ;


<s> static bool isTruncWithZeroHighBitsInput ( SDValue V , SelectionDAG & DAG ) {

if ( V . getOpcode ( ) != <STR_LIT> ) return false ;


<s> void <ISA_LIT>RegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , Register BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ;

Register OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> HARD_REG_SET x ; if ( ! TARGET_HARD_FLOAT ) { x = reg_class_contents [ FP_REGS ] ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( x , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; } if ( flag_pic ) fixed_regs [ PIC_REG ] = call_used_regs [ PIC_REG ] = <NUM_LIT> ;


<s> unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ;


<s> if ( findPrevDelaySlotEnd ( MBB , I , <NUM_LIT> ) < <NUM_LIT> ) return false ; I = prevNonPseudo ( MBB , II ) ; if ( I -> mayLoad ( ) ) return false ;

if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) return false ;


<s> SDValue Lo = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , In ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ;


<s> REAL_VALUE_TYPE r ; int i ; if ( ! fp_consts_inited ) init_fp_table ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return <NUM_LIT> ; for ( i = <NUM_LIT> ; i < fp_consts_inited ; i ++ ) if ( REAL_VALUES_EQUAL ( r , values_fp [ i ] ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; unsigned MaskValue = <NUM_LIT> ; unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) { int SndLaneEltIdx = ( NumLanes == <NUM_LIT> ) ? SVOp -> getMaskElt ( i + NumElemsInLane ) : - <NUM_LIT> ; int EltIdx = SVOp -> getMaskElt ( i ) ; if ( ( EltIdx == - <NUM_LIT> || EltIdx == ( int ) i ) && ( SndLaneEltIdx == - <NUM_LIT> || SndLaneEltIdx == ( int ) ( i + NumElemsInLane ) ) ) continue ; if ( ( ( unsigned ) EltIdx == ( i + NumElems ) ) && ( SndLaneEltIdx == - <NUM_LIT> || ( unsigned ) SndLaneEltIdx == i + NumElems + NumElemsInLane ) ) MaskValue |= ( <NUM_LIT> << i ) ; else return SDValue ( ) ; }


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ;


<s> return __arm_vldrdq_gather_shifted_offset_u64 ( __base , __offset ) ;


<s> unsigned SABIAlignment = DL . getABITypeAlignment ( S -> getValueOperand ( ) -> getType ( ) ) ; bool Aligned = S -> getAlignment ( ) == <NUM_LIT> || S -> getAlignment ( ) >= SABIAlignment ; MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ;

if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM ) ) return false ;


<s> Inst . addOperand ( MCOperand :: createReg ( SRegsTable [ RegNo ] ) ) ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : MF ( MF ) , SRetReturnReg ( <NUM_LIT> ) , VarArgsFrameOffset ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , IncomingArgSize ( <NUM_LIT> ) , EmitNOAT ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) , MaxCallFrameSize ( <NUM_LIT> ) {


<s> if ( Tensor1Info . Order == INVALID_SCEV || Tensor2Info . Order == INVALID_SCEV ) continue ; for ( int i = <NUM_LIT> ; i < Tensor1Info . IndexFactor . size ( ) ; i ++ ) { if ( Tensor1Info . IndexFactor [ i ] > Tensor2Info . IndexFactor [ i ] ) Tensor2Info . IndexFactor [ i ] = Tensor1Info . IndexFactor [ i ] ; else Tensor1Info . IndexFactor [ i ] = Tensor2Info . IndexFactor [ i ] ; } Tensor1Info . Name = <STR_LIT> + std :: to_string ( Iter -> first ) + <STR_LIT> ; std :: string IndexStr = <STR_LIT> ; auto Formula = Tensor1Info . umap . find ( <NUM_LIT> ) ; if ( Formula != Tensor1Info . umap . end ( ) ) { IndexStr = <STR_LIT> + Formula -> second + <STR_LIT> ; IndexStr += std :: to_string ( Tensor1Info . IndexFactor [ <NUM_LIT> ] ) ; } else IndexStr = <STR_LIT> + std :: to_string ( Tensor1Info . IndexFactor [ <NUM_LIT> ] ) ; for ( unsigned i = <NUM_LIT> ; i < Tensor1Info . IndexFactor . size ( ) ; i ++ ) {

Formula = Tensor1Info . umap . find ( i ) ;


<s> <ISA_LIT>IREmitter :: ~ <ISA_LIT>IREmitter ( ) {


<s> Opcode = <STR_LIT> ; break ; default : return NULL ; } SDValue Ops [ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode , dl , TargetVT , <STR_LIT> , Ops ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRri64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRri ( N1 . getNode ( ) , N1 , Base , Offset ) ) { if ( Subtarget . is64Bit ( ) ) { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } } else { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } } SDValue Ops [ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode , dl , TargetVT , <STR_LIT> , Ops ) ; } else { if ( Subtarget . is64Bit ( ) ) { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; } } else { switch ( TargetVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;


<s> return hasV6Ops ( ) && has<ISA_LIT>Ops ( ) && ! isTargetWindows ( ) ;


<s> assert ( Kind == k_Imm && <STR_LIT> ) ;

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; unsigned Opc ; bool ExtraOp = false ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;

case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;

return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ;


<s> if ( Subtarget -> isTargetDarwin ( ) && ! Subtarget -> isThumb1Only ( ) && ! Disable<ISA_LIT>FastISel ) return new <ISA_LIT>FastISel ( funcInfo ) ; return <NUM_LIT> ;


<s> Value * PreTrunc = Trunc -> getOperand ( <NUM_LIT> ) ; Type * PreTruncTy = PreTrunc -> getType ( ) ; if ( PreTruncTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { Input = PreTrunc ; InputTy = PreTruncTy ; } } if ( InputTy -> getPrimitiveSizeInBits ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; Value * Offsets ; Value * BasePtr = checkGEP ( Offsets , InputTy , GEP , Builder ) ; if ( ! BasePtr ) return nullptr ; Value * Store = tryCreateIncrementingGatScat ( I , BasePtr , Offsets , GEP , Builder ) ; if ( Store ) return Store ; int Scale = computeScale ( BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) , MemoryTy -> getScalarSizeInBits ( ) ) ;

if ( Scale == - <NUM_LIT> ) return nullptr ;


<s> inline vector unsigned int vec_lvewx ( int a1 , unsigned int * a2 ) { return ( vector unsigned int ) __builtin_altivec_lvewx ( a1 , ( void * ) a2 ) ;


<s> if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC ) switch ( XINT ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) { case UNSPEC_MOVE_PIC : case UNSPEC_TLSLE : x = XVECEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; break ; default : break ;


<s> MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( SpillLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn ( CS . getReg ( ) ) ;


<s> if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; }


<s> NextI = std :: next ( I ) ; if ( isSafeToSpeculate ( & * I ) ) ToB -> splice ( At , FromB , I ) ; else predicateInstr ( ToB , At , & * I , PredR , IfTrue ) ;


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ;

return ( Cnt >= <NUM_LIT> && Cnt <= ElementBits ) ;


<s> LoopWaitcntData ( ) : LfWaitcnt ( NULL ) , IterCnt ( <NUM_LIT> ) {


<s> if ( ! isUnary ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ;


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> * <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel , } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> * <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel , } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> * <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> * <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> * <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;

assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;


<s> LE . write < uint8_t > ( Value >> <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint8_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; else LE . write < uint8_t > ( SwapBits ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ) ; LE . write < uint16_t > ( <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint32_t > ( Value & <NUM_LIT> ) ; else BE . write < uint32_t > ( Value & <NUM_LIT> ) ; const MCOperand & MO = MI . getOperand ( <NUM_LIT> ) ; uint64_t Imm = MO . isImm ( ) ? MO . getImm ( ) : <NUM_LIT> ; LE . write < uint8_t > ( <NUM_LIT> ) ; LE . write < uint8_t > ( <NUM_LIT> ) ; LE . write < uint16_t > ( <NUM_LIT> ) ; if ( IsLittleEndian ) LE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; else BE . write < uint32_t > ( Imm >> <NUM_LIT> ) ; } else { uint64_t Value = getBinaryCodeForInstr ( MI , Fixups , STI ) ; LE . write < uint8_t > ( Value >> <NUM_LIT> ) ; if ( IsLittleEndian ) { LE . write < uint8_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ;

LE . write < uint16_t > ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; bool IsILP32 = STI . getTargetTriple ( ) . getEnvironment ( ) == Triple :: GNUILP32 ; return new ELF<ISA_LIT>AsmBackend ( T , TheTriple , OSABI , true , IsILP32 ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ;


<s> if ( Size == <NUM_LIT> ) return & <STR_LIT> [ <STR_LIT> ] ; MappingID = CustomMappingID ;


<s> if ( HII -> isLoopN ( I ) && isBadForLoopN ( J ) ) return true ; if ( HII -> isLoopN ( J ) && isBadForLoopN ( I ) ) return true ;

return HII -> isDeallocRet ( I ) && ( J -> isBranch ( ) || J -> isCall ( ) || J -> isBarrier ( ) ) ;


<s> getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( L , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; }


<s> ( ArePtrs64bit ( ) ? <STR_LIT> : <STR_LIT> ) ;


<s> ( * vax_d_format . encode ) ( fmt , buf , r ) ; buf [ <NUM_LIT> ] = ( ( buf [ <NUM_LIT> ] >> <NUM_LIT> ) & <NUM_LIT> ) | ( ( buf [ <NUM_LIT> ] & <NUM_LIT> ) << <NUM_LIT> ) ; buf [ <NUM_LIT> ] = ( ( buf [ <NUM_LIT> ] >> <NUM_LIT> ) & <NUM_LIT> ) | ( ( buf [ <NUM_LIT> ] & <NUM_LIT> ) << <NUM_LIT> ) ;


<s> sbitmap protected_bbs ; rtx_insn * insn , * end ; rtx unprotected_region ; if ( TARGET_MIPS16 ) { sorry ( <STR_LIT> , <STR_LIT> ) ; return ; } calculate_dominance_info ( CDI_DOMINATORS ) ; protected_bbs = sbitmap_alloc ( last_basic_block_for_fn ( cfun ) ) ; bitmap_clear ( protected_bbs ) ; rev_post_order = XNEWVEC ( int , last_basic_block_for_fn ( cfun ) ) ; n = pre_and_rev_post_order_compute ( NULL , rev_post_order , false ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) { bb = BASIC_BLOCK_FOR_FN ( cfun , rev_post_order [ i ] ) ; if ( r10k_protected_bb_p ( bb , protected_bbs ) ) unprotected_region = NULL_RTX ; else unprotected_region = pc_rtx ; end = NEXT_INSN ( BB_END ( bb ) ) ; for ( insn = BB_HEAD ( bb ) ; insn != end ; insn = NEXT_INSN ( insn ) ) { if ( unprotected_region && USEFUL_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_mips_cache ) unprotected_region = NULL_RTX ; else { if ( unprotected_region == pc_rtx ) unprotected_region = insn ; if ( r10k_needs_protection_p ( insn ) ) { emit_insn_before ( gen_r10k_cache_barrier ( ) , as_a < rtx_insn * > ( unprotected_region ) ) ;


<s> return __builtin_mve_vcmpltq_fv4sf ( __a , __b ) ;


<s> __o = __builtin_aarch64_set_qregoiv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv2df ( __o , ( float64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = <NUM_LIT> ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != <NUM_LIT> ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode , p ) ;

if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) {


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + <NUM_LIT> ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ <NUM_LIT> ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( <NUM_LIT> , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( <NUM_LIT> , reg ) , <NUM_LIT> ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ;

for ( i = <NUM_LIT> ; i < nclobs ; ++ i ) XVECEXP ( insn , <NUM_LIT> , i ) = clobs [ i ] ;


return ( __m128i ) vec_mergeh ( ( __vector long ) __A , ( __vector long ) __B ) ;


<s> SDNode * In128 = DAG . getMachineNode ( Extend , DL , <STR_LIT> , Op0 ) ; SDValue Result = DAG . getNode ( Opcode , DL , <STR_LIT> , SDValue ( In128 , <NUM_LIT> ) , Op1 ) ; bool Is32Bit = is32Bit ( VT ) ;

SDValue SubReg0 = DAG . getTargetConstant ( <STR_LIT> ( Is32Bit ) , VT ) ;


<s> MMI = & getAnalysis < MachineModuleInfo > ( ) ; Module & M = const_cast < Module & > ( * MMI -> getModule ( ) ) ; if ( ! MF . getName ( ) . startswith ( ThunkNamePrefix ) ) { if ( InsertedThunks ) return false ; if ( ! STI -> useRetpoline ( ) || STI -> useRetpolineExternalThunk ( ) ) return false ; if ( Is64Bit ) createThunkFunction ( M , R11ThunkName ) ; else for ( StringRef Name : { EAXThunkName , ECXThunkName , EDXThunkName , EDIThunkName } ) createThunkFunction ( M , Name ) ;


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitterEL ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx , true ) ;


<s> const MCSection * <ISA_LIT>MCAsmInfo ::

getNonexecutableStackSection ( MCContext & Ctx ) const {


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) return true ; const RegisterBank * RegBank = RBI . getRegBank ( DstReg , MRI , TRI ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( RegBank -> getID ( ) == <STR_LIT> ) {

if ( DstSize == <NUM_LIT> ) RC = & <STR_LIT> ;


<s> <ISA_LIT>MemOpInfo ( SyncScope :: ID S<ISA_LIT>D , AtomicOrdering Ordering , AtomicOrdering FailureOrdering , bool IsNonTemporal = false ) : S<ISA_LIT>D ( S<ISA_LIT>D ) , Ordering ( Ordering ) , FailureOrdering ( FailureOrdering ) , IsNonTemporal ( IsNonTemporal ) {


<s> enum attr_size m68k_sched_attr_size ( rtx_insn * insn ) { switch ( sched_get_attr_size_int ( insn ) ) { case <NUM_LIT> : return SIZE_1 ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseStringWithPrefix ( const char * Prefix , StringRef & Value ) { if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { return MatchOperand_NoMatch ; } StringRef Tok = Parser . getTok ( ) . getString ( ) ; if ( Tok != Prefix ) { return MatchOperand_NoMatch ; }


<s> MIB . addReg ( Regs [ <NUM_LIT> ] . first , RegState :: Define ) . addReg ( Regs [ <NUM_LIT> ] . first , RegState :: Define ) ; } else { MIB . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) ; } MIB . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; return MIB . getInstr ( ) ;


<s> storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , <NUM_LIT> ) ;


<s> switch ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) ) { case REG : case POST_INC : break ; case POST_DEC : return <NUM_LIT> ; case POST_MODIFY : { rtx adjust = XEXP ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( adjust ) != CONST_INT || INTVAL ( adjust ) != GET_MODE_SIZE ( GET_MODE ( src ) ) ) return <NUM_LIT> ; } break ; default :


<s> return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : <NUM_LIT> ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : <NUM_LIT> ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : <NUM_LIT> ) | ( ( TARGET_SPE ) ? RS6000_BTM_SPE : <NUM_LIT> ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : <NUM_LIT> ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : <NUM_LIT> ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : <NUM_LIT> ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : <NUM_LIT> ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : <NUM_LIT> ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : <NUM_LIT> ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : <NUM_LIT> ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : <NUM_LIT> ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : <NUM_LIT> ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : <NUM_LIT> ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : <NUM_LIT> ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : <NUM_LIT> ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : <NUM_LIT> ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : <NUM_LIT> ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : <NUM_LIT> ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : <NUM_LIT> ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : <NUM_LIT> ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : <NUM_LIT> ) ) ;


<s> static bool aarch64_evpc_ext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location = d -> perm [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { unsigned int required = location + i ; if ( d -> one_vector_p ) { required &= ( nelt - <NUM_LIT> ) ; } if ( d -> perm [ i ] != required ) return false ; } switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_extv16qi ; break ; case V8QImode : gen = gen_aarch64_extv8qi ; break ; case V4HImode : gen = gen_aarch64_extv4hi ; break ; case V8HImode : gen = gen_aarch64_extv8hi ; break ; case V2SImode : gen = gen_aarch64_extv2si ; break ; case V4SImode : gen = gen_aarch64_extv4si ; break ; case V2SFmode : gen = gen_aarch64_extv2sf ; break ; case V4SFmode : gen = gen_aarch64_extv4sf ; break ; case V2DImode : gen = gen_aarch64_extv2di ; break ; case V2DFmode : gen = gen_aarch64_extv2df ; break ; default : return false ;


<s> int sh_loop_align ( rtx label ) { rtx next = label ; do next = next_nonnote_insn ( next ) ; while ( next && GET_CODE ( next ) == CODE_LABEL ) ; if ( ! next || ! INSN_P ( next ) || GET_CODE ( PATTERN ( next ) ) == ADDR_DIFF_VEC || recog_memoized ( next ) == CODE_FOR_consttable_2 ) return <NUM_LIT> ; return align_loops_log ;


<s> void RecordRelocation ( MachObjectWriter * Writer , MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , uint64_t & FixedValue ) override { if ( Writer -> is64Bit ( ) ) Record<ISA_LIT>_64Relocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ; else Record<ISA_LIT>Relocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ;


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> void addPrefetchOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( getPrefetch ( ) ) ) ;


<s> const <ISA_LIT>TargetMachine & TM = ( const <ISA_LIT>TargetMachine & ) getTargetMachine ( ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineBasicBlock :: iterator I ( MI ) ;


<s> unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( MovInst ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = createResultReg ( & <STR_LIT> ) ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( Result32 ) . addImm ( <STR_LIT> ) ;


<s> if ( ! MCE ) return false ; int64_t Shift = Bits - <NUM_LIT> ; int64_t MinVal = ( int64_t ( <NUM_LIT> ) << Shift ) * - Scale ; int64_t MaxVal = ( ( int64_t ( <NUM_LIT> ) << Shift ) - <NUM_LIT> ) * Scale ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ;


<s> <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ; else return getParser ( ) . Error ( IDLoc , MemNoShuffMsg ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) {

} else return getParser ( ) . Error ( IDLoc , llvm :: Twine ( <STR_LIT> ) + Option + <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < WideNumElts ; ++ i ) ShuffV . push_back ( i + WideNumElts ) ; int Stride = FourEltRes ? WideNumElts / <NUM_LIT> : WideNumElts / <NUM_LIT> ; int SaveElts = FourEltRes ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . isLittleEndian ( ) ) for ( int i = <NUM_LIT> ; i < SaveElts ; i ++ ) ShuffV [ i * Stride ] = i ; else for ( int i = <NUM_LIT> ; i <= SaveElts ; i ++ ) ShuffV [ i * Stride - <NUM_LIT> ] = i - <NUM_LIT> ; SDValue ShuffleSrc2 = SignedConv ? DAG . getUNDEF ( WideVT ) : DAG . getConstant ( <NUM_LIT> , dl , WideVT ) ; SDValue Arrange = DAG . getVectorShuffle ( WideVT , dl , Wide , ShuffleSrc2 , ShuffV ) ; SDValue Extend ; if ( SignedConv ) { Arrange = DAG . getBitcast ( IntermediateVT , Arrange ) ; EVT ExtVT = Src . getValueType ( ) ; if ( Subtarget . hasP9Altivec ( ) ) ExtVT = EVT :: getVectorVT ( * DAG . getContext ( ) , WideVT . getVectorElementType ( ) , IntermediateVT . getVectorNumElements ( ) ) ;

Extend = DAG . getNode ( <STR_LIT> , dl , IntermediateVT , Arrange , DAG . getValueType ( ExtVT ) ) ;


<s> if ( MBBI == MBB . begin ( ) ) return false ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; MachineBasicBlock :: iterator PrevInst = MBBI ; -- PrevInst ;

if ( isDelayFiller ( MBB , PrevInst ) ) return false ;


<s> <ISA_LIT>CCState ( ArrayRef < Type * > ArgTypes , CallingConv :: ID CC , bool IsVarArg , MachineFunction & MF , SmallVectorImpl < CCValAssign > & Locs , LLVMContext & C ) : CCState ( CC , IsVarArg , MF , Locs , C ) , ArgTypeList ( ArgTypes ) {


<s> static void alpha_align_insns ( void ) { if ( alpha_tune == PROCESSOR_EV4 ) alpha_align_insns_1 ( <NUM_LIT> , alphaev4_next_group , alphaev4_next_nop ) ;


<s> SDLoc dl ( Op ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; EVT InVT = In . getValueType ( ) ; if ( VT . isScalableVector ( ) ) { unsigned Opcode = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return LowerToPredicatedOp ( Op , DAG , Opcode ) ; } uint64_t VTSize = VT . getFixedSizeInBits ( ) ; uint64_t InVTSize = InVT . getFixedSizeInBits ( ) ; if ( VTSize < InVTSize ) { MVT CastVT = <STR_LIT> ( <STR_LIT> ( InVT . getScalarSizeInBits ( ) ) , InVT . getVectorNumElements ( ) ) ; In = DAG . getNode ( Op . getOpcode ( ) , dl , CastVT , In ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; }


<s> if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ; if ( GP_REGNUM_P ( regno ) && ! aarch64_vect_struct_mode_p ( mode ) ) return <NUM_LIT> ; if ( FP_REGNUM_P ( regno ) ) { if ( aarch64_vect_struct_mode_p ( mode ) ) return ( regno + aarch64_hard_regno_nregs ( regno , mode ) - <NUM_LIT> ) <= V31_REGNUM ; else return <NUM_LIT> ; }


<s> I != E ; ++ I ) gv_array [ i ++ ] = & * I ; while ( ! global_list . empty ( ) ) global_list . remove ( global_list . begin ( ) ) ; bool ret = AsmPrinter :: doFinalization ( M ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ;


<s> static MCInst lowerRIEfLow ( const MachineInstr * MI , unsigned Opcode ) { return MCInstBuilder ( Opcode ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> return isImm ( ) && ( ( Imm . Val <= <NUM_LIT> && Imm . Val >= - <NUM_LIT> ) || ( F == <NUM_LIT> || F == <NUM_LIT> || F == - <NUM_LIT> || F == <NUM_LIT> || F == - <NUM_LIT> || F == <NUM_LIT> || F == - <NUM_LIT> || F == <NUM_LIT> || F == - <NUM_LIT> ) ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ;

if ( ! ST -> hasV6T2Ops ( ) ) return SDValue ( ) ;


<s> It . convertToMem ( State . AllocateStack ( Size , std :: max ( Align , SlotAlign ) ) ) ; State . addLoc ( It ) ; SlotAlign = <NUM_LIT> ; }


<s> StringRef Chan = Str . take_back ( <NUM_LIT> ) ; int AttrChan = StringSwitch < int > ( Chan ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; if ( AttrChan == - <NUM_LIT> ) return MatchOperand_ParseFail ; Str = Str . drop_back ( <NUM_LIT> ) . drop_front ( <NUM_LIT> ) ; uint8_t Attr ; if ( Str . getAsInteger ( <NUM_LIT> , Attr ) ) return MatchOperand_ParseFail ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Attr > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const {


<s> case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( ScratchBase , RegState :: Kill ) . addReg ( ScratchOffset , RegState :: Kill ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( ScratchBase , RegState :: Kill ) . addReg ( ScratchOffset , RegState :: Kill ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( ScratchBase , RegState :: Kill ) . addReg ( ScratchOffset , RegState :: Kill ) ;


<s> if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { NumSubs = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( ( VT . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } } else if ( Subtarget . hasAVX2 ( ) ) { if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { NumSubs = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( ( VT . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } } else { if ( VT . getSizeInBits ( ) > <NUM_LIT> ) { NumSubs = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( ( VT . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; } } if ( NumSubs == <NUM_LIT> ) return Builder ( DAG , DL , Op0 , Op1 ) ; SmallVector < SDValue , <NUM_LIT> > Subs ; EVT InVT = Op0 . getValueType ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT . getScalarType ( ) , InVT . getVectorNumElements ( ) / NumSubs ) ; for ( unsigned i = <NUM_LIT> ; i != NumSubs ; ++ i ) { unsigned Idx = i * SubVT . getVectorNumElements ( ) ;

SDValue LHS = extractSubVector ( Op0 , Idx , DAG , DL , SubVT . getSizeInBits ( ) ) ;


<s> bool isIfCvtEnabled ( ) const { return EnableIfCvt ;


<s> vcgtz_f64 ( float64x1_t __a ) { return ( uint64x1_t ) ( __a > ( float64x1_t ) { <NUM_LIT> } ) ;


<s> Ops . push_back ( & cast < Instruction > ( Op ) -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Op ) ; } else if ( Subtarget . hasSSE2 ( ) && match ( Op . get ( ) , m_And ( m_Value ( ) , m_SpecificInt ( UINT64_C ( <NUM_LIT> ) ) ) ) ) { Ops . push_back ( & Op ) ; } } return ! Ops . empty ( ) ; } int ShiftAmountOpNum = - <NUM_LIT> ; if ( I -> isShift ( ) ) ShiftAmountOpNum = <NUM_LIT> ; else if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { if ( II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> ) ShiftAmountOpNum = <NUM_LIT> ; } if ( ShiftAmountOpNum == - <NUM_LIT> ) return false ; auto * Shuf = dyn_cast < ShuffleVectorInst > ( I -> getOperand ( ShiftAmountOpNum ) ) ; if ( Shuf && getSplatIndex ( Shuf -> getShuffleMask ( ) ) >= <NUM_LIT> && isVectorShiftByScalarCheap ( I -> getType ( ) ) ) { Ops . push_back ( & I -> getOperandUse ( ShiftAmountOpNum ) ) ; return true ; } return false ;


<s> } assert ( VTList . NumVTs == <NUM_LIT> ) ; SDVTList WidenedVTList = DAG . getVTList ( WidenedVT , VTList . VTs [ <NUM_LIT> ] ) ; auto NewOp = DAG . getMemIntrinsicNode ( Opcode , DL , WidenedVTList , Ops , WidenedMemVT , MMO ) ; if ( WidenedVT != VT ) {

auto Extract = DAG . getNode ( <STR_LIT> , DL , VT , NewOp , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ;


<s> static SDValue lowerV2X128Shuffle ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { if ( Subtarget . hasAVX2 ( ) && V2 . isUndef ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( ! canWidenShuffleElements ( Mask , Zeroable , WidenedMask ) ) return SDValue ( ) ; bool IsLowZero = ( Zeroable & <NUM_LIT> ) == <NUM_LIT> ; bool IsHighZero = ( Zeroable & <NUM_LIT> ) == <NUM_LIT> ; if ( WidenedMask [ <NUM_LIT> ] == <NUM_LIT> && IsHighZero ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , getZeroVector ( VT , Subtarget , DAG , DL ) , LoV , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( SDValue Blend = lowerShuffleAsBlend ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( ! IsLowZero && ! IsHighZero ) { bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } }


<s> O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << <STR_LIT> ; assert ( MO2 . isImm ( ) && <STR_LIT> ) ;

O << <STR_LIT> << <STR_LIT> ( MO2 . getImm ( ) ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; if ( DestReg != <STR_LIT> ) { unsigned Reg1 = Reg ;


<s> if ( Opr . isExpr ( ) && ! Opr . isSymbolRefExpr ( ) ) { Error ( Loc , <STR_LIT> ) ; } else if ( Opr . isImm ( ) && ! Opr . isS16Imm ( ) ) { Error ( Loc , <STR_LIT> ) ; }


<s> return CreateReg ( Index , RegKind_MSA128 , RegInfo , S , E , Parser ) ;


<s> return all_of ( C -> operands ( ) , [ ] ( const Use & U ) {

return containsOnlyConstantData ( cast < Constant > ( & U ) ) ;


<s> APFloat Zero = APFloat :: getZero ( F . getSemantics ( ) ) ; APFloat :: cmpResult Cmp0 = F . compare ( Zero ) ; if ( Cmp0 == APFloat :: cmpLessThan || ( Cmp0 == APFloat :: cmpUnordered && Subtarget -> enableDX10Clamp ( ) ) ) { return DCI . DAG . getConstantFP ( Zero , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } APFloat One ( F . getSemantics ( ) , <STR_LIT> ) ; APFloat :: cmpResult Cmp1 = F . compare ( One ) ;

if ( Cmp1 == APFloat :: cmpGreaterThan ) return DCI . DAG . getConstantFP ( One , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;


<s> const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S ) ;

return new <ISA_LIT>TargetWasmStreamer ( S ) ;


<s> unsigned Reg = IntRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> break ; } case TargetOpcode :: PATCHABLE_RET : { unsigned RetOpcode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst RetInst ; RetInst . setOpcode ( RetOpcode ) ; for ( const auto & MO : make_range ( std :: next ( MI -> operands_begin ( ) ) , MI -> operands_end ( ) ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , * this ) ) RetInst . addOperand ( MCOp ) ; } bool IsConditional ; if ( RetOpcode == <STR_LIT> ) { IsConditional = true ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { break ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { IsConditional = false ; } else { EmitToStreamer ( * OutStreamer , RetInst ) ; break ; } MCSymbol * FallthroughLabel ; if ( IsConditional ) { FallthroughLabel = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ( static_cast < <STR_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addExpr ( MCSymbolRefExpr :: create ( FallthroughLabel , OutContext ) ) ) ; RetInst = MCInst ( ) ; RetInst . setOpcode ( <STR_LIT> ) ; } OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; MCSymbol * BeginOfSled = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( BeginOfSled ) ; EmitToStreamer ( * OutStreamer , RetInst ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( <STR_LIT> ) , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , RetInst ) ; if ( IsConditional ) OutStreamer -> emitLabel ( FallthroughLabel ) ; recordSled ( BeginOfSled , * MI , SledKind :: FUNCTION_EXIT ) ; break ; } case TargetOpcode :: PATCHABLE_FUNCTION_EXIT : llvm_unreachable ( <STR_LIT> ) ; case TargetOpcode :: PATCHABLE_TAIL_CALL : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ;


<s> SelectionDAG & DAG = CLI . DAG ; const char * <ISA_LIT>16HelperFunction = <NUM_LIT> ; bool Need<ISA_LIT>16Helper = false ; if ( getTargetMachine ( ) . Options . UseSoftFloat && Subtarget -> in<ISA_LIT>16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( HardFloatLibCalls , array_endof ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ;


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) {

return createMachObjectWriter ( llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit , CPUType , CPUSubtype ) , OS , true ) ;


<s> __v4si result ; if ( __B < <NUM_LIT> ) { if ( __builtin_constant_p ( __B ) ) { if ( __B < <NUM_LIT> ) rshift = ( __v4su ) vec_splat_s32 ( __B ) ; else rshift = ( __v4su ) vec_splats ( ( unsigned int ) __B ) ; } else rshift = vec_splats ( ( unsigned int ) __B ) ; }

result = vec_sra ( ( __v4si ) __A , rshift ) ;