<s> GCNSubtarget & GCNSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef GPU , StringRef FS ) { SmallString < <NUM_LIT> > FullFS ( <STR_LIT> ) ; if ( isAmdHsaOS ( ) ) FullFS += <STR_LIT> ; FullFS += <STR_LIT> ; if ( FS . find_lower ( <STR_LIT> ) != StringRef :: npos ) { if ( FS . find_lower ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; if ( FS . find_lower ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; if ( FS . find_lower ( <STR_LIT> ) == StringRef :: npos ) FullFS += <STR_LIT> ; } FullFS += FS ; ParseSubtargetFeatures ( GPU , GPU , FullFS ) ; assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) {


<s> Register Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = <STR_LIT> ; if ( ! Reg ) return false ; if ( ! State . AllocateReg ( ArgGPRs ) ) return false ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ;


<s> static bool isUseMIInFoldList ( const std :: vector < FoldCandidate > & FoldList , const MachineInstr * MI ) { for ( auto Candidate : FoldList ) { if ( Candidate . UseMI == MI ) return true ; }


<s> return ( __m128d ) _mm_setr_pd ( __c [ <NUM_LIT> ] , __A [ <NUM_LIT> ] ) ;


<s>
UnspilledCSGPR
=
Reg
;
UnspilledCSGPRPaired
=
PairedReg
;
}
continue
;
}
if
(
produceCompactUnwindFrame
(
MF
)
&&
PairedReg
!=
<STR_LIT>
&&
!
SavedRegs
.
test
(
PairedReg
)
)
{
SavedRegs
.
set
(
PairedReg
)
;
if
(
<STR_LIT>
.
contains
(
PairedReg
)
&&
!
RegInfo
->
isReservedReg
(
MF
,
PairedReg
)
)
ExtraCSSpill
=
PairedReg
;
}
}
unsigned
CSStackSize
=
<NUM_LIT>
;
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
CSStackSize
+=
TRI
->
getRegSizeInBits
(
Reg
,
MRI
)
/
<NUM_LIT>
;
unsigned
NumSavedRegs
=
SavedRegs
.
count
(
)
;
unsigned
EstimatedStackSize
=
MFI
.
estimateStackSize
(
MF
)
;
if
(
hasFP
(
MF
)
||
windowsRequiresStackProbe
(
MF
,
EstimatedStackSize
+
CSStackSize
+
<NUM_LIT>
)
)
{
SavedRegs
.
set
(
<STR_LIT>
)
;
SavedRegs
.
set
(
<STR_LIT>
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
SavedRegs
.
set_bits
(
)
)
dbgs
(
)
<<
' '
<<
printReg
(
Reg
,
RegInfo
)
;
dbgs
(
)
<<
<STR_LIT>
;
)
;
bool
CanEliminateFrame
=
SavedRegs
.
count
(
)
==
<NUM_LIT>
;
unsigned
EstimatedStackSizeLimit
=
estimateRSStackSizeLimit
(
MF
)
;
bool
BigStack
=
(
EstimatedStackSize
+
CSStackSize
)
>
EstimatedStackSizeLimit
;
if
(
BigStack
||
!
CanEliminateFrame
||
RegInfo
->
cannotEliminateFrame
(
MF
)
)
AFI
->
setHasStackFrame
(
true
)
;
if
(
BigStack
)
{
if
(
!
ExtraCSSpill
&&
UnspilledCSGPR
!=
<STR_LIT>
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printReg
(
UnspilledCSGPR
,
RegInfo
)
<<
<STR_LIT>
)
;
SavedRegs
.
set
(
UnspilledCSGPR
)
;
if
(
produceCompactUnwindFrame
(
MF
)
)
SavedRegs
.
set
(
UnspilledCSGPRPaired
)
;
ExtraCSSpill
=
UnspilledCSGPRPaired
;
}
if
(
!
ExtraCSSpill
||
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
ExtraCSSpill
)
)
{
const
TargetRegisterInfo
*
TRI
=
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
TargetRegisterClass
&
RC
=
<STR_LIT>
;
unsigned
Size
=
TRI
->
getSpillSize
(
RC
)
;
unsigned
Align
=
TRI
->
getSpillAlignment
(
RC
)
;

int FI = MFI . CreateStackObject ( Size , Align , false ) ;


<s> JTI = ( ( <ISA_LIT>BaseTargetMachine & ) MF . getTarget ( ) ) . getJITInfo ( ) ; II = ( const <ISA_LIT>BaseInstrInfo * ) MF . getTarget ( ) . getInstrInfo ( ) ; TD = MF . getTarget ( ) . getTargetData ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ;

if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , leaInReg , true , - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , leaInReg , true , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned Src2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill2 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned leaInReg2 = <NUM_LIT> ; MachineInstr * InsMI2 = <NUM_LIT> ; if ( Src == Src2 ) { addRegReg ( MIB , leaInReg , true , leaInReg , false ) ; } else { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; else leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , & * MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) ; InsMI2 = BuildMI ( * MFI , & * MIB , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( leaInReg2 , RegState :: Define , <STR_LIT> ) . addReg ( Src2 , getKillRegState ( isKill2 ) ) ; addRegReg ( MIB , leaInReg , true , leaInReg2 , true ) ; } if ( LV && isKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , InsMI2 ) ;


<s> case POST_MODIFY : gcc_unreachable ( ) ; case REG : if ( nregs > <NUM_LIT> ) { if ( nregs > <NUM_LIT> || ( TARGET_HAVE_MVE && nregs >= <NUM_LIT> ) ) templ = <STR_LIT> ; else templ = <STR_LIT> ; ops [ <NUM_LIT> ] = mem ; ops [ <NUM_LIT> ] = reg ; break ; } case PLUS : if ( GET_CODE ( addr ) == PLUS ) addr = XEXP ( addr , <NUM_LIT> ) ; case LABEL_REF : { int i ; int overlap = - <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( reg ) + <NUM_LIT> * i ) ; ops [ <NUM_LIT> ] = adjust_address ( mem , DImode , <NUM_LIT> * i ) ; if ( reg_overlap_mentioned_p ( ops [ <NUM_LIT> ] , mem ) ) { gcc_assert ( overlap == - <NUM_LIT> ) ; overlap = i ; } else { if ( TARGET_HAVE_MVE && LABEL_REF_P ( addr ) ) sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; else sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ; } } if ( overlap != - <NUM_LIT> ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( reg ) + <NUM_LIT> * overlap ) ; ops [ <NUM_LIT> ] = adjust_address ( mem , SImode , <NUM_LIT> * overlap ) ; if ( TARGET_HAVE_MVE && LABEL_REF_P ( addr ) ) sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; else sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ; } return <STR_LIT> ; } default : gcc_unreachable ( ) ; } sprintf ( buff , templ , load ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ;


<s> SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; APInt ShlConst = ( cast < ConstantSDNode > ( N01 ) ) -> getAPIntValue ( ) ; APInt SarConst = ( cast < ConstantSDNode > ( N1 ) ) -> getAPIntValue ( ) ; EVT CVT = N1 . getValueType ( ) ; if ( SarConst . isNegative ( ) ) return SDValue ( ) ; for ( MVT SVT : <STR_LIT> ( ) ) { unsigned ShiftSize = SVT . getSizeInBits ( ) ; if ( ShiftSize < <NUM_LIT> || ShiftSize > <NUM_LIT> || ShlConst != Size - ShiftSize ) continue ; SDLoc DL ( N ) ; SDValue NN = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getValueType ( SVT ) ) ; SarConst = SarConst - ( Size - ShiftSize ) ; if ( SarConst == <NUM_LIT> ) return NN ;

else if ( SarConst . isNegative ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , NN , DAG . getConstant ( - SarConst , DL , CVT ) ) ;


<s> const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; Function :: const_arg_iterator FuncArg = Func . arg_begin ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) && ! Func . arg_empty ( ) ) report_fatal_error ( <STR_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_FixedArg ) ; <ISA_LIT>FI -> setFormalArgInfo ( CCInfo . getNextStackOffset ( ) , CCInfo . getInRegsParamsCount ( ) > <NUM_LIT> ) ; unsigned CurArgIdx = <NUM_LIT> ; CCInfo . rewindByValRegsInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ i ] . isOrigArg ( ) ) { std :: advance ( FuncArg , Ins [ i ] . getOrigArgIndex ( ) - CurArgIdx ) ; CurArgIdx = Ins [ i ] . getOrigArgIndex ( ) ; } EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Ins [ i ] . isOrigArg ( ) && <STR_LIT> ) ; unsigned FirstByValReg , LastByValReg ; unsigned ByValIdx = CCInfo . getInRegsParamsProcessed ( ) ; CCInfo . getInRegsParamInfo ( ByValIdx , FirstByValReg , LastByValReg ) ; assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValIdx < CCInfo . getInRegsParamsCount ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , FirstByValReg , LastByValReg , VA , CCInfo ) ; CCInfo . nextInRegsParam ( ) ; continue ; } if ( IsRegLoc ) { MVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ;

SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ;


<s> case V8QImode : gen = gen_aarch64_simd_combinev8qi ; break ; case V4HImode : gen = gen_aarch64_simd_combinev4hi ; break ; case V2SImode : gen = gen_aarch64_simd_combinev2si ; break ; case V4HFmode : gen = gen_aarch64_simd_combinev4hf ; break ; case V2SFmode : gen = gen_aarch64_simd_combinev2sf ; break ; case DImode : gen = gen_aarch64_simd_combinedi ; break ;


<s> case <STR_LIT> : return expandSelectCC ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return expandSelectCC ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> llvm_unreachable ( <STR_LIT> ) ; } } case <STR_LIT> : { const auto * GA = cast < GlobalAddressSDNode > ( Node ) ; if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasBulkMemory ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( GA -> getGlobal ( ) -> getThreadLocalMode ( ) != GlobalValue :: LocalExecTLSModel && ! Subtarget -> getTargetTriple ( ) . isOSEmscripten ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> + GA -> getGlobal ( ) -> getName ( ) , false ) ; } MVT PtrVT = TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ; assert ( PtrVT == <STR_LIT> && <STR_LIT> ) ; SDValue TLSBaseSym = CurDAG -> getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ; SDValue TLSOffsetSym = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , PtrVT , GA -> getOffset ( ) , <NUM_LIT> ) ; MachineSDNode * TLSBase = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , TLSBaseSym ) ; MachineSDNode * TLSOffset = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , TLSOffsetSym ) ; MachineSDNode * TLSAddress = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( TLSBase , <NUM_LIT> ) , SDValue ( TLSOffset , <NUM_LIT> ) ) ; ReplaceNode ( Node , TLSAddress ) ; return ; } case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { case <STR_LIT> : { MVT PtrVT = TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ; assert ( PtrVT == <STR_LIT> && <STR_LIT> ) ; MachineSDNode * TLSSize = CurDAG -> getMachineNode ( <STR_LIT> , DL , PtrVT , CurDAG -> getTargetExternalSymbol ( <STR_LIT> , <STR_LIT> ) ) ; ReplaceNode ( Node , TLSSize ) ; return ; } case <STR_LIT> : { MVT PtrVT = TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ; assert ( PtrVT == <STR_LIT> && <STR_LIT> ) ; MachineSDNode * TLSAlign = CurDAG -> getMachineNode ( <STR_LIT> , DL , PtrVT , CurDAG -> getTargetExternalSymbol ( <STR_LIT> , <STR_LIT> ) ) ; ReplaceNode ( Node , TLSAlign ) ; return ; } } break ; }


<s> insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vexXopType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vexXopType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vexXopPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A : insn -> opcodeType = XOPA_MAP ; return consumeByte ( insn , & insn -> opcode ) ; } } if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_38 ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_3A ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ;


<s> static __inline __m128d __attribute__ ( ( __always_inline__ ) ) _mm_load_sd ( double const * __P ) {


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ;


<s> bool isFP32 ( ) const { return isReg ( FP32Reg ) ;


<s> return ( int64x2_t ) __builtin_neon_vrshlsv2di ( __a , __b ) ;


<s> return removePassThroughBuiltin ( M ) ;


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ;


<s> inline <STR_LIT> getVPTInstrPredicate ( const MachineInstr & MI ) { Register PredReg ; return getVPTInstrPredicate ( MI , PredReg ) ;


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef FS ) { if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ;

ParseSubtargetFeatures ( CPUString , FS ) ;


<s> return parseOperand ( Operands , false , false ) ; } case AsmToken :: LCurly : return parseNeonVectorList ( Operands ) ; case AsmToken :: Identifier : { if ( isCondCode ) return parseCondCode ( Operands , invertCondCode ) ; if ( ! parseRegister ( Operands ) ) return false ; if ( ! parseOptionalMulOperand ( Operands ) ) return false ; OperandMatchResultTy GotShift = tryParseOptionalShiftExtend ( Operands ) ; if ( GotShift != MatchOperand_NoMatch ) return GotShift ; if ( Mnemonic == <STR_LIT> ) return parseKeywordOperand ( Operands ) ; const MCExpr * IdVal ; S = getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Integer : case AsmToken :: Real : case AsmToken :: Hash : { S = getLoc ( ) ; parseOptionalToken ( AsmToken :: Hash ) ; bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; if ( Parser . getLexer ( ) . peekTok ( ) . is ( AsmToken :: Real ) ) Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble ( ) , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) return TokError ( <STR_LIT> ) ; else if ( IntVal != <NUM_LIT> || isNegative ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; return false ; } const MCExpr * ImmVal ; if ( parseSymbolicImmVal ( ImmVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Equal : {


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseAFGR64Regs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( isFP64 ( ) ) return MatchOperand_NoMatch ; return parseRegs ( Operands , ( int ) <STR_LIT> ) ;


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ;

if ( ( TSFlags & <STR_LIT> ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ;


<s> for ( auto & MBB : MF ) for ( auto & MI : MBB ) switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : {

MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ;


<s> if ( AttributeItem * Item = getAttributeItem ( Attribute ) ) { if ( ! OverwriteExisting ) return ; Item -> Type = AttributeType :: Text ; Item -> StringValue = std :: string ( Value ) ;


<s> args . quick_push ( GEN_INT ( ( ( prfop >> <NUM_LIT> ) & <NUM_LIT> ) + <NUM_LIT> ) ) ;


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return InstrItins ;


<s> <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( C , AM ) ) return <NUM_LIT> ; unsigned Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; TargetRegisterClass * RC = TLI . getRegClassFor ( TLI . getPointerTy ( ) ) ; unsigned ResultReg = createResultReg ( RC ) ;

addLeaAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) , ResultReg ) , AM ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( ) {


<s> case AMDGPU :: JUMP_COND : case AMDGPU :: JUMP : return AMDGPU :: CONTINUE_LOGICALNZ_i32 ;

default : llvm_unreachable ( <STR_LIT> ) ;


<s> size_t DashPosition = <NUM_LIT> ; StringRef TheTriple ; DashPosition = TT . find ( '-' ) ; if ( DashPosition == StringRef :: npos ) { TheTriple = TT . substr ( <NUM_LIT> ) ; } else { TheTriple = TT . substr ( <NUM_LIT> , DashPosition ) ; } if ( TheTriple == <STR_LIT> ) { if ( CPU . empty ( ) || CPU == <STR_LIT> ) { <ISA_LIT>ArchFeature = <STR_LIT> ;


<s> unsigned <ISA_LIT>ELFObjectWriter :: GetRelocType ( const MCValue & Target , const MCFixup & Fixup , bool IsPCRel , bool IsRelocWithSymbol , int64_t Addend ) const {

return GetRelocTypeInner ( Target , Fixup , IsPCRel ) ;


<s> if ( LT . second == <STR_LIT> ) return LT . first * <NUM_LIT> ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : { static const auto ValidMinMaxTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } default :


<s> * no_add_attrs = true ; } else if ( TARGET_SHCOMPACT ) { error ( <STR_LIT> ) ; * no_add_attrs = true ; } return NULL_TREE ;


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> MCAsmBackend * llvm :: create<ISA_LIT>leAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) {


<s> unsigned at = CountLeadingZeros_64 ( x ) ; uint64_t complow = <NUM_LIT> << ( <NUM_LIT> - at ) ; uint64_t comphigh = <NUM_LIT> << ( <NUM_LIT> - at ) ; if ( abs64 ( complow - x ) <= abs64 ( comphigh - x ) ) return complow ;


<s> if ( dump_file ) fprintf ( dump_file , <STR_LIT> , i ) ; break ; case SH_NOSWAP_LD : permute_load ( insn ) ; break ; case SH_NOSWAP_ST : permute_store ( insn ) ; break ; case SH_EXTRACT : adjust_extract ( insn ) ; break ; case SH_SPLAT : adjust_splat ( insn ) ; break ; case SH_XXPERMDI : adjust_xxpermdi ( insn ) ; break ; case SH_CONCAT : adjust_concat ( insn ) ; break ; case SH_VPERM :


<s> bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ;

return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ;


<s> auto PredOp = PredIntr -> getOperand ( <NUM_LIT> ) ; auto PredOpTy = cast < VectorType > ( PredOp -> getType ( ) ) ; if ( PredOpTy != II . getType ( ) ) return None ; IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ; SmallVector < Value * > NarrowedBinOpArgs = { PredOp } ; auto NarrowBinOpOp1 = Builder . CreateIntrinsic ( <STR_LIT> , { PredOpTy } , { BinOpOp1 } ) ; NarrowedBinOpArgs . push_back ( NarrowBinOpOp1 ) ; if ( BinOpOp1 == BinOpOp2 ) NarrowedBinOpArgs . push_back ( NarrowBinOpOp1 ) ; else NarrowedBinOpArgs . push_back ( Builder . CreateIntrinsic ( <STR_LIT> , { PredOpTy } , { BinOpOp2 } ) ) ; auto NarrowedBinOp = Builder . CreateIntrinsic ( IntrinsicID , { PredOpTy } , NarrowedBinOpArgs ) ; return IC . replaceInstUsesWith ( II , NarrowedBinOp ) ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getThe<ISA_LIT>elTarget ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , createMCStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitterEB ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackendEB32 ) ;

TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>AsmBackendEL32 ) ;


<s> if ( val >= - <NUM_LIT> && val <= <NUM_LIT> ) { operands [ <NUM_LIT> ] = gen_rtx_NEG ( SImode , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } else if ( val >= <NUM_LIT> && val < <NUM_LIT> ) { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_MINUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DL ( Subtarget . getDataLayoutString ( ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> auto * MINode = cast < MemIntrinsicSDNode > ( N ) ; return DAG . getMaskedStore ( MINode -> getChain ( ) , DL , Data , MINode -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( PtrTy ) , MINode -> getOperand ( <NUM_LIT> ) , MINode -> getMemoryVT ( ) , MINode -> getMemOperand ( ) , <STR_LIT> , false , false ) ;


<s> void VectorElementize :: createVecInsert ( MachineFunction & F , MachineInstr * Instr , std :: vector < MachineInstr * > & copies ) { unsigned numcopies = numCopiesNeeded ( Instr ) ; unsigned destregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned srcregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > dest = getScalarRegisters ( destregnum ) ; SmallVector < unsigned , <NUM_LIT> > src = getScalarRegisters ( srcregnum ) ; MachineOperand which = Instr -> getOperand ( <NUM_LIT> ) ; assert ( which . isImm ( ) && <STR_LIT> ) ; unsigned int elem = which . getImm ( ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; if ( i != elem ) copy -> addOperand ( MachineOperand :: CreateReg ( src [ i ] , false ) ) ; else copy -> addOperand ( Instr -> getOperand ( <NUM_LIT> ) ) ;


<s> pcrel = insn . startLocation + insn . displacementOffset + insn . displacementSize ; tryAddingPcLoadReferenceComment ( insn . startLocation + insn . displacementOffset , insn . displacement + pcrel , Dis ) ; baseReg = MCOperand :: createReg ( <STR_LIT> ) ; } else baseReg = MCOperand :: createReg ( <NUM_LIT> ) ; indexReg = MCOperand :: createReg ( <NUM_LIT> ) ; break ; case EA_BASE_BX_SI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BX_DI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BP_SI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; case EA_BASE_BP_DI : baseReg = MCOperand :: createReg ( <STR_LIT> ) ; indexReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; default : indexReg = MCOperand :: createReg ( <NUM_LIT> ) ; switch ( insn . eaBase ) { default : debug ( <STR_LIT> ) ; return true ; case EA_BASE_ ## x : \ baseReg = MCOperand :: createReg ( <STR_LIT> ) ; break ; ALL_EA_BASES ALL_REGS debug ( <STR_LIT> <STR_LIT> ) ; return true ; } } scaleAmount = MCOperand :: createImm ( <NUM_LIT> ) ; } displacement = MCOperand :: createImm ( insn . displacement ) ; segmentReg = MCOperand :: createReg ( segmentRegnums [ insn . segmentOverride ] ) ; mcInst . addOperand ( baseReg ) ; mcInst . addOperand ( scaleAmount ) ; mcInst . addOperand ( indexReg ) ; if ( ! tryAddingSymbolicOperand ( insn . displacement + pcrel , false , insn . startLocation , insn . displacementOffset , insn . displacementSize , mcInst , Dis ) ) mcInst . addOperand ( displacement ) ; mcInst . addOperand ( segmentReg ) ; return false ;


<s> tag_map . traverse < tag_map_t * , avoid_collisions_1 > ( & tag_map ) ; }


<s> SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue CPol = CurDAG -> getTargetConstant ( <STR_LIT> :: GLC , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , CPol , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue CPol = CurDAG -> getTargetConstant ( <STR_LIT> :: GLC , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , CPol , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineMemOperand * MMO = Mem -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( CmpSwap , { MMO } ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ;

SDValue Extract = CurDAG -> getTargetExtractSubreg ( SubReg , SL , VT , SDValue ( CmpSwap , <NUM_LIT> ) ) ;


<s> assert ( Width == <NUM_LIT> && <STR_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register IncrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW32 ( Ordering ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( IncrReg ) ; break ; case AtomicRMWInst :: Add : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ;


<s> if ( RegWidth == <NUM_LIT> ) Value &= <NUM_LIT> ; if ( Value == <NUM_LIT> && Shift != <NUM_LIT> ) return false ; return ( Value & ~ ( <NUM_LIT> << Shift ) ) == <NUM_LIT> ;


<s> void <ISA_LIT>TargetStreamer :: emitArchExtension ( unsigned ArchExt ) {


<s> return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> bool <ISA_LIT>ConstantIslands :: isLongFormOffsetInRange ( unsigned UserOffset , unsigned TrialOffset , const CPUser & U ) {

return isOffsetInRange ( UserOffset , TrialOffset , U . getLongFormMaxDisp ( ) , U . NegOk ) ;


<s> AMDGPUTargetMachine :: AMDGPUTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , TargetOptions Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OptLevel ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , RM , CM , OptLevel ) , TLOF ( new TargetLoweringObjectFileELF ( ) ) , Subtarget ( TT , CPU , FS , * this ) , IntrinsicInfo ( ) { setRequiresStructuredCFG ( true ) ;


<s> static DecodeStatus DecodeSystemPStateInstruction ( llvm :: MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { uint64_t op1 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t op2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t crm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t pstate_field = ( op1 << <NUM_LIT> ) | op2 ; Inst . addOperand ( MCOperand :: createImm ( pstate_field ) ) ; Inst . addOperand ( MCOperand :: createImm ( crm ) ) ;


<s> virtual void EmitARM64WinCFISaveR19R20X ( int Offset ) {


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOA ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ;


<s> format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; return false ; } uint32_t other_half = <NUM_LIT> ; switch ( Type ) { case MachO :: <ISA_LIT>_RELOC_LO16_SECTDIFF : other_half = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; FixedValue &= <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_RELOC_HA16_SECTDIFF : other_half = FixedValue & <NUM_LIT> ; FixedValue = ( ( FixedValue >> <NUM_LIT> ) + ( ( FixedValue & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) & <NUM_LIT> ; break ; case MachO :: <ISA_LIT>_RELOC_HI16_SECTDIFF : other_half = FixedValue & <NUM_LIT> ; FixedValue = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MachO :: any_relocation_info MRE ; makeScatteredRelocationInfo ( MRE , other_half , MachO :: GENERIC_RELOC_PAIR , Log2Size , IsPCRel , Value2 ) ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) return false ;


<s> rtx rs6000_emit_eqne ( machine_mode mode , rtx op1 , rtx op2 , rtx scratch ) { if ( op2 == const0_rtx ) return op1 ; if ( GET_CODE ( scratch ) == SCRATCH ) scratch = gen_reg_rtx ( mode ) ; if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ;

else emit_insn ( gen_rtx_SET ( scratch , gen_rtx_PLUS ( mode , op1 , negate_rtx ( mode , op2 ) ) ) ) ;


<s> <ISA_LIT>MCCodeEmitter ( MCContext & ctx , const MCInstrInfo & MCII ) : Ctx ( ctx ) , MCII ( MCII ) {


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectBRCOND ( SDNode * N ) { assert ( N -> getNumOperands ( ) >= <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Pred = N -> getOperand ( <NUM_LIT> ) ; SDValue Target = N -> getOperand ( <NUM_LIT> ) ; SDValue PredInvFlag = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDLoc dl ( N ) ; assert ( Target . getOpcode ( ) == <STR_LIT> ) ; assert ( Pred . getValueType ( ) == <STR_LIT> ) ;

SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> static machine_mode ix86_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp , const_tree fntype , int for_return ) { if ( cfun -> machine -> func_type == TYPE_NORMAL && type != NULL_TREE && POINTER_TYPE_P ( type ) ) { * punsignedp = POINTERS_EXTEND_UNSIGNED ; return word_mode ; } return default_promote_function_mode ( type , mode , punsignedp , fntype , for_return ) ;


<s> for ( MachineInstr :: const_mop_iterator IO = MI . operands_begin ( ) , IOEnd = MI . operands_end ( ) ; IO != IOEnd ; ++ IO ) { if ( ! IO -> isReg ( ) || ! IO -> isDef ( ) ) continue ; unsigned CurReg = IO -> getReg ( ) ; for ( MCRegAliasIterator AI ( CurReg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegToId . find ( * AI ) == RegToId . end ( ) ) { DEBUG ( IdToReg . push_back ( * AI ) ; assert ( IdToReg [ CurRegId ] == * AI && <STR_LIT> ) ) ; RegToId [ * AI ] = CurRegId ++ ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( * AI , TRI ) << '\n' ) ; } } }


<s> first = SEQ_BEGIN ( insn ) ; second = SEQ_END ( insn ) ; if ( JUMP_P ( first ) && NONJUMP_INSN_P ( second ) && GET_CODE ( PATTERN ( first ) ) == SET && GET_CODE ( SET_DEST ( PATTERN ( first ) ) ) == PC && GET_CODE ( SET_SRC ( PATTERN ( first ) ) ) == IF_THEN_ELSE ) { rtx cond = XEXP ( SET_SRC ( PATTERN ( first ) ) , <NUM_LIT> ) ; if ( ( GET_CODE ( cond ) == EQ || GET_CODE ( cond ) == NE ) && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && REG_P ( XEXP ( cond , <NUM_LIT> ) ) && reg_referenced_p ( XEXP ( cond , <NUM_LIT> ) , PATTERN ( second ) ) && ! reg_referenced_p ( XEXP ( cond , <NUM_LIT> ) , PATTERN ( second ) ) ) { rtx tmp = XEXP ( cond , <NUM_LIT> ) ; XEXP ( cond , <NUM_LIT> ) = XEXP ( cond , <NUM_LIT> ) ; XEXP ( cond , <NUM_LIT> ) = tmp ;


<s> for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const auto & TLOF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream OS ( Flags ) ; for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function , * Mang ) ; for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Global , * Mang ) ;

for ( const auto & Alias : M . aliases ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Alias , * Mang ) ;


<s> static bool indirect_call_p ( rtx pat ) { if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( pat ) == SET ) pat = SET_SRC ( pat ) ;

gcc_assert ( GET_CODE ( pat ) == CALL ) ;


<s> vmlal_n_u16 ( uint32x4_t a , uint16x4_t b , uint16_t c ) { uint32x4_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> return MFI -> getShaderType ( ) == ShaderType :: COMPUTE ;


<s> assert ( VT == <STR_LIT> && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == Vec . getValueSizeInBits ( ) ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } if ( VT . getSizeInBits ( ) < Vec . getValueSizeInBits ( ) ) { assert ( Vec . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> && <STR_LIT> ) ; Vec = DAG . getNode ( Opc , dl , <STR_LIT> , Vec ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( VT . getSizeInBits ( ) > Vec . getValueSizeInBits ( ) ) { unsigned CastOpc = IsSigned ? <STR_LIT> : <STR_LIT> ; EVT CastVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) . getSizeInBits ( ) ) ; CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , CastVT , VT . getVectorNumElements ( ) ) ; Vec = DAG . getNode ( CastOpc , dl , CastVT , Vec ) ;


<s> static __inline vec_double2 spu_shuffle ( vec_double2 a , vec_double2 b , vec_uchar16 pattern ) { return ( ( vec_double2 ) ( si_shufb ( ( qword ) ( a ) , ( qword ) ( b ) , ( qword ) ( pattern ) ) ) ) ;


<s> std :: pair < SDValue , SDValue > <ISA_LIT>TargetLowering :: FP_TO_SINTHelper ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; assert ( Op . getValueType ( ) . getSimpleVT ( ) <= <STR_LIT> && Op . getValueType ( ) . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget -> is64Bit ( ) && Op . getValueType ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = Op . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned Opc ; switch ( Op . getValueType ( ) . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , dl , Value , StackSlot , PseudoSourceValue :: getFixedStack ( SSFI ) , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) } ; Value = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ;

Chain = Value . getValue ( <NUM_LIT> ) ;


<s> SDValue MaskedShamt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftLeft1Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeft1Hi , Not ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftRightHi = DAG . getNode ( IsSRA ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , Hi , MaskedShamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Shift31 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftRightHi , Or ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , IsSRA ? Shift31 : DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftRightHi ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ;

return DAG . getMergeValues ( Ops , DL ) ;


<s> if ( ! Disable<ISA_LIT>DropOpt ) Changed |= runBlkDropCombine ( MBB , TII ) ; if ( ! Disable<ISA_LIT>BlkPushOpt ) Changed |= runBlkPushCombine ( MBB , TII ) ; if ( ! Disable<ISA_LIT>ShorterFormOpt ) Changed |= runReplaceWithShorterForm ( MBB , TII ) ;


<s> dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; assert ( ( ! NeedsWinCFI || ! ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned FrameIdxReg1 = RPI . FrameIdx ; unsigned FrameIdxReg2 = RPI . FrameIdx + <NUM_LIT> ; if ( NeedsWinCFI && RPI . isPaired ( ) ) { std :: swap ( Reg1 , Reg2 ) ; std :: swap ( FrameIdxReg1 , FrameIdxReg2 ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) ) ; if ( ! MRI . isReserved ( Reg1 ) ) MBB . addLiveIn ( Reg1 ) ; if ( RPI . isPaired ( ) ) { if ( ! MRI . isReserved ( Reg2 ) ) MBB . addLiveIn ( Reg2 ) ; MIB . addReg ( Reg2 , getPrologueDeath ( MF , Reg2 ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg2 ) , MachineMemOperand :: MOStore , Size , Alignment ) ) ; } MIB . addReg ( Reg1 , getPrologueDeath ( MF , Reg1 ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg1 ) , MachineMemOperand :: MOStore , Size , Alignment ) ) ; if ( NeedsWinCFI ) InsertSEH ( MIB , TII , MachineInstr :: FrameSetup ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( RPI . Type == RegPairInfo :: ZPR || RPI . Type == RegPairInfo :: PPR ) MFI . setStackID ( RPI . FrameIdx , TargetStackID :: ScalableVector ) ; } return true ;


<s> void addMEMziOperands ( MCInst & Inst , unsigned N ) const {


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( CurDAG -> getTargetConstant ( RegClassIDs [ Regs . size ( ) - <NUM_LIT> ] , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < Regs . size ( ) ; ++ i ) {


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const {

if ( Imm . isPosZero ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return true ;


<s> <ISA_LIT>PreEmitPeephole ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>PreEmitPeepholePass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> unsigned int regno , count ; gcc_assert ( TARGET_HARD_FLOAT && ISA_HAS_8CC ) ; if ( mode == CCmode ) count = <NUM_LIT> ; else if ( mode == CCV2mode ) count = <NUM_LIT> ; else if ( mode == CCV4mode ) count = <NUM_LIT> ; else gcc_unreachable ( ) ;

cfun -> machine -> next_fcc += - cfun -> machine -> next_fcc & ( count - <NUM_LIT> ) ;


<s> MachineInstr * LoHalf = BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . addReg ( Addr . Base . LoReg , <NUM_LIT> , Addr . Base . LoSubReg ) . add ( OffsetLo ) . addImm ( <NUM_LIT> ) ; ( void ) LoHalf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; LoHalf -> dump ( ) ; ) ; MachineInstr * HiHalf = BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . addReg ( Addr . Base . HiReg , <NUM_LIT> , Addr . Base . HiSubReg ) . add ( OffsetHi ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; ( void ) HiHalf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; HiHalf -> dump ( ) ; ) ;

Register FullDestReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ;


<s> return RM . hasValue ( ) ? * RM : Reloc :: Static ;


<s> CONSTEXPR binary_permute ( int unspec ) : m_unspec ( unspec ) {


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const Thumb1RegisterInfo * RegInfo = static_cast < const Thumb1RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HA : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ;

case VK_<ISA_LIT>_HIGHERA : OS << <STR_LIT> ; break ;


<s> static DecodeStatus DecodeGPR8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> explicit <ISA_LIT>GNUInfo ( const llvm :: Triple & pTriple ) : GNUInfo ( pTriple ) {


<s> bool aarch64_simd_imm_scalar_p ( rtx x , machine_mode mode ATTRIBUTE_UNUSED ) { HOST_WIDE_INT imm = INTVAL ( x ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned int byte = imm & <NUM_LIT> ; if ( byte != <NUM_LIT> && byte != <NUM_LIT> ) return false ; imm >>= <NUM_LIT> ; }


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> unsigned Mask = MaskMO . getImm ( ) ; assert ( OpIdx > <NUM_LIT> && <STR_LIT> ) ; const MCOperand CondMO = MI . getOperand ( OpIdx - <NUM_LIT> ) ; assert ( CondMO . isImm ( ) && <STR_LIT> ) ; if ( CondMO . getImm ( ) & <NUM_LIT> ) { unsigned LowBit = Mask & - Mask ; unsigned BitsAboveLowBit = <NUM_LIT> & ( - LowBit << <NUM_LIT> ) ; Mask ^= BitsAboveLowBit ; } return Mask ;


<s> const auto & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned SecondOpcode = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;

return expandAuipcInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , SecondOpcode ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue ( ) ; for ( int MOVZShift = <NUM_LIT> ; MOVZShift <= <NUM_LIT> ; MOVZShift += <NUM_LIT> ) if ( ( Value & ~ ( <NUM_LIT> << MOVZShift ) ) == <NUM_LIT> ) return false ; Value = ~ Value ; if ( RegWidth == <NUM_LIT> ) Value &= <NUM_LIT> ; return ( Value & ~ ( <NUM_LIT> << Shift ) ) == <NUM_LIT> ;


<s> char * secname , * stubname ; tree stubid , stubdecl ; int need_comma ; unsigned int f ; fnname = XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; secname = ( char * ) alloca ( strlen ( fnname ) + <NUM_LIT> ) ; sprintf ( secname , <STR_LIT> , fnname ) ; stubname = ( char * ) alloca ( strlen ( fnname ) + <NUM_LIT> ) ; sprintf ( stubname , <STR_LIT> , fnname ) ; stubid = get_identifier ( stubname ) ; stubdecl = build_decl ( FUNCTION_DECL , stubid , build_function_type ( void_type_node , NULL_TREE ) ) ; DECL_SECTION_NAME ( stubdecl ) = build_string ( strlen ( secname ) , secname ) ; fprintf ( file , <STR_LIT> , current_function_name ( ) ) ; need_comma = <NUM_LIT> ; for ( f = ( unsigned int ) current_function_args_info . fp_code ; f != <NUM_LIT> ; f >>= <NUM_LIT> ) { fprintf ( file , <STR_LIT> , need_comma ? <STR_LIT> : <STR_LIT> , ( f & <NUM_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; need_comma = <NUM_LIT> ; } fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; function_section ( stubdecl ) ; ASM_OUTPUT_ALIGN ( file , floor_log2 ( FUNCTION_BOUNDARY / BITS_PER_UNIT ) ) ; if ( ! FUNCTION_NAME_ALREADY_DECLARED ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , stubname ) ; fputs ( <STR_LIT> , file ) ; } assemble_name ( file , stubname ) ; fputs ( <STR_LIT> , file ) ; fprintf ( file , <STR_LIT> ) ; mips16_fp_args ( file , current_function_args_info . fp_code , <NUM_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; assemble_name ( file , fnname ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; if ( ! FUNCTION_NAME_ALREADY_DECLARED ) {


<s> enum reg_class preferred_reload_class ( rtx x ATTRIBUTE_UNUSED , enum reg_class class ) { return class ;


<s> TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCRelocationInfo ( The<ISA_LIT>Target , create<ISA_LIT>ElfRelocation ) ;

TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>Target , create<ISA_LIT>InstrAnalysis ) ;


<s> return parseIntWithPrefix ( <STR_LIT> , Operands , <ISA_LIT>Operand :: ImmTyDMask ) ;


<s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) ; else IsValid = isUInt < <NUM_LIT> > ( Imm ) ;

return IsValid && ( ( IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO ) ;


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ;


<s> break ; case GT : cond = <STR_LIT> ; break ; case LE : if ( cc_mode == CCFPmode || cc_mode == CCFPEmode ) cond = <STR_LIT> ; else cond = <STR_LIT> ; break ; case LT : if ( cc_mode == CCFPmode || cc_mode == CCFPEmode ) cond = <STR_LIT> ; else if ( cc_mode == CCNZmode ) cond = <STR_LIT> ; else cond = <STR_LIT> ; break ; case GEU : cond = <STR_LIT> ; break ; case GTU : cond = <STR_LIT> ; break ; case LEU : cond = <STR_LIT> ; break ; case LTU : cond = <STR_LIT> ;


<s> return __arm_vcaddq_rot90_f32 ( __a , __b ) ;


<s> paddd_s ( int64_t s , int64_t t ) { return __builtin_loongson_paddd_s ( s , t ) ;


<s> return <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , basereg , <NUM_LIT> , <NUM_LIT> , Loc , Loc , <NUM_LIT> ) ;


<s> InitialStates . insert ( { BB , PredState } ) ; FinalStates . insert ( { BB , PredState } ) ; for ( BasicBlock * SuccBB : successors ( BB ) ) Worklist . push_back ( SuccBB ) ; } for ( BasicBlock * BB : RPOT ) { int SuccState = getSuccState ( InitialStates , F , ParentBaseState , BB ) ; if ( SuccState == OverdefinedState ) continue ; FinalStates . insert ( { BB , SuccState } ) ; } for ( BasicBlock * BB : RPOT ) { auto & BBColors = BlockColors [ BB ] ; BasicBlock * FuncletEntryBB = BBColors . front ( ) ; if ( isa < CleanupPadInst > ( FuncletEntryBB -> getFirstNonPHI ( ) ) ) continue ; int PrevState = getPredState ( FinalStates , F , ParentBaseState , BB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << PrevState << '\n' ) ; for ( Instruction & I : * BB ) { auto * Call = dyn_cast < CallBase > ( & I ) ; if ( ! Call || ! isStateStoreNeeded ( Personality , * Call ) ) continue ; int State = getStateForCall ( BlockColors , FuncInfo , * Call ) ; if ( State != PrevState ) insertStateNumberStore ( & I , State ) ; PrevState = State ; } auto EndState = FinalStates . find ( BB ) ; if ( EndState != FinalStates . end ( ) ) if ( EndState -> second != PrevState ) insertStateNumberStore ( BB -> getTerminator ( ) , EndState -> second ) ; } SmallVector < CallBase * , <NUM_LIT> > SetJmp3Calls ; for ( BasicBlock * BB : RPOT ) { for ( Instruction & I : * BB ) { auto * Call = dyn_cast < CallBase > ( & I ) ; if ( ! Call ) continue ; if ( Call -> getCalledOperand ( ) -> stripPointerCasts ( ) != SetJmp3 . getCallee ( ) -> stripPointerCasts ( ) ) continue ; SetJmp3Calls . push_back ( Call ) ; } } for ( CallBase * Call : SetJmp3Calls ) { auto & BBColors = BlockColors [ Call -> getParent ( ) ] ; BasicBlock * FuncletEntryBB = BBColors . front ( ) ; bool InCleanup = isa < CleanupPadInst > ( FuncletEntryBB -> getFirstNonPHI ( ) ) ; IRBuilder < > Builder ( Call ) ; Value * State ; if ( InCleanup ) { Value * StateField = Builder . CreateStructGEP ( RegNode -> getAllocatedType ( ) , RegNode , StateFieldIndex ) ; State = Builder . CreateLoad ( Builder . getInt32Ty ( ) , StateField ) ; } else { State = Builder . getInt32 ( getStateForCall ( BlockColors , FuncInfo , * Call ) ) ;


<s> bool <ISA_LIT>PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ;


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_Cheri ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ;

assert ( RegIdx . RealRegister == <STR_LIT> || ( RegIdx . RealRegister >= <STR_LIT> && RegIdx . RealRegister <= <STR_LIT> ) ) ;


<s> return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) && RBI . constrainGenericRegister ( Src0 , <STR_LIT> , * MRI ) ; } Register ShiftSrc0 ; Register ShiftSrc1 ; bool Shift0 = mi_match ( Src0 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc0 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; bool Shift1 = mi_match ( Src1 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc1 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; unsigned Opc = <STR_LIT> ; if ( Shift0 && Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc0 ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift0 && ConstSrc1 && ConstSrc1 -> Value == <NUM_LIT> ) { auto MIB = BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( ShiftSrc0 ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } MI . setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( MI , TII , TRI , RBI ) ;


<s> bool Modified = false ; for ( auto & MBB : MF ) { for ( auto MBBI = MBB . begin ( ) ; MBBI != MBB . end ( ) ; ++ MBBI ) { if ( MBBI -> getOpcode ( ) != <STR_LIT> ) continue ; unsigned ClobberReg = TRI -> findDeadCallerSavedReg ( MBB , MBBI ) ; if ( ClobberReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( ClobberReg , RegState :: Define ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( ClobberReg ) ; MBB . erase ( MBBI ) ; } else { MachineInstr * Fence = BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; addRegOffset ( BuildMI ( MBB , Fence , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) , <STR_LIT> , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) -> addRegisterDead ( <STR_LIT> , TRI ) ; } ++ NumFences ; Modified = true ;


<s> unsigned PhiDef = Phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int OutOfLoopUse = - <NUM_LIT> ; int LoopUse = - <NUM_LIT> ; int counter = <NUM_LIT> ; for ( MachineOperand & MO : Phi -> uses ( ) ) { if ( MO . isMBB ( ) && MO . getMBB ( ) == Prolog ) { OutOfLoopUse = counter ; } if ( MO . isMBB ( ) && MO . getMBB ( ) == Latch ) { LoopUse = counter ; } ++ counter ; } phiPath ( Phi , Path , Phi -> getOperand ( OutOfLoopUse ) ) ; std :: reverse ( Path . begin ( ) , Path . end ( ) ) ; unsigned FinalReg = Phi -> getOperand ( OutOfLoopUse ) . getReg ( ) ; unsigned FirstReg = FinalReg ; std :: vector < unsigned > UseVec ; std :: vector < unsigned > DefVec ; for ( int i = <NUM_LIT> ; i < UnrollCount ; ++ i ) { MachineInstr * ClonedPhi = MBB -> getParent ( ) -> CloneMachineInstr ( & ( * I ) ) ; ExecThreads [ i ] . Phis . push_back ( ClonedPhi ) ; replaceVregs ( ClonedPhi , i ) ; MBB -> insert ( I , ClonedPhi ) ; RegMap RM ; if ( ! Path . empty ( ) && <ISA_LIT>II :: isMac ( Path . back ( ) -> getDesc ( ) ) ) { MachineOperand & ReplaceMO = ClonedPhi -> getOperand ( OutOfLoopUse ) ;

replaceWithZero ( ReplaceMO , getOpType ( * Path . back ( ) ) ) ;


<s> bool Unpckl = true ; bool Unpckh = true ; bool UnpcklSwapped = true ; bool UnpckhSwapped = true ; int NumEltsInLane = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned LaneStart = ( i / NumEltsInLane ) * NumEltsInLane ; int LoPos = ( i % NumEltsInLane ) / <NUM_LIT> + LaneStart + NumElts * ( i % <NUM_LIT> ) ; int HiPos = LoPos + NumEltsInLane / <NUM_LIT> ; int LoPosSwapped = ( LoPos + NumElts ) % ( NumElts * <NUM_LIT> ) ; int HiPosSwapped = ( HiPos + NumElts ) % ( NumElts * <NUM_LIT> ) ;

if ( Mask [ i ] == - <NUM_LIT> ) continue ;


<s> if ( msp430_code_region == LOWER ) return lower_prefix ; if ( msp430_code_region == UPPER ) return upper_prefix ; if ( msp430_code_region == EITHER ) return either_prefix ; } else { if ( msp430_data_region == LOWER ) return lower_prefix ; if ( msp430_data_region == UPPER ) return upper_prefix ; if ( msp430_data_region == EITHER ) return either_prefix ; } return NULL ;


<s> if ( TARGET_64BIT ) return <NUM_LIT> ; ccvt = ix86_get_callcvt ( funtype ) ; if ( ( ccvt & ( IX86_CALLCVT_STDCALL | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL ) ) != <NUM_LIT> && ! stdarg_p ( funtype ) ) return size ; if ( aggregate_value_p ( TREE_TYPE ( funtype ) , fundecl ) && ! ix86_keep_aggregate_return_pointer ( funtype ) ) { int nregs = ix86_function_regparm ( funtype , fundecl ) ; if ( nregs == <NUM_LIT> ) return GET_MODE_SIZE ( Pmode ) ; } return <NUM_LIT> ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> assert ( VA . getValNo ( ) == NextVA . getValNo ( ) && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; assert ( NextVA . isRegLoc ( ) && <STR_LIT> ) ; Register NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ;

assignValueToReg ( NewRegs [ <NUM_LIT> ] , VA . getLocReg ( ) , VA ) ;


<s> bool <ISA_LIT>ElfSpecSet :: runOnMachineFunction ( MachineFunction & Func ) { if ( ! EnableElfSpec ) return false ; searchInstruction ( Func ) ; searchPrintF ( Func ) ; createElfSection ( Func ) ; return false ;


<s> int i , regno , hi_reg ; int num_saves = XVECLEN ( parallel_op , <NUM_LIT> ) ; if ( TARGET_ARM ) return <NUM_LIT> ; if ( TARGET_THUMB1 ) return <NUM_LIT> ; regno = REGNO ( first_op ) ; hi_reg = ( REGNO_REG_CLASS ( regno ) == HI_REGS ) && ( regno != LR_REGNUM ) ; for ( i = <NUM_LIT> ; i < num_saves && ! hi_reg ; i ++ ) { regno = REGNO ( XEXP ( XVECEXP ( parallel_op , <NUM_LIT> , i ) , <NUM_LIT> ) ) ; hi_reg |= ( REGNO_REG_CLASS ( regno ) == HI_REGS ) && ( regno != LR_REGNUM ) ;


<s> static DecodeStatus DecodeAddrRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;

unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ;


<s> bool <ISA_LIT>InstrInfo :: isJumpR ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> :


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; auto regSeq = getRegSeq ( ) ; Inst . addOperand ( MCOperand :: createReg ( regSeq . first ) ) ; Inst . addOperand ( MCOperand :: createReg ( regSeq . second ) ) ;


<s> void <ISA_LIT>InstPrinter :: printNOneImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { O << - <NUM_LIT> ;


<s> else addPass ( createAtomicExpandPass ( TM ) ) ;

if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeReturned ( ) ) ;


<s> if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] < MaskSize ) { if ( EltFromOp0 != - <NUM_LIT> ) return - <NUM_LIT> ; EltFromOp0 = i ;

} else if ( Mask [ i ] != i + MaskSize ) {


<s> MVT ReturnMVT ; if ( Subtarget -> is64Bit ( ) && VT == <STR_LIT> && ExtendKind == <STR_LIT> ) ReturnMVT = <STR_LIT> ; else ReturnMVT = <STR_LIT> ; EVT MinVT = getRegisterType ( Context , ReturnMVT ) ;

return VT . bitsLT ( MinVT ) ? MinVT : VT ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ;


<s> if ( GV -> hasDLLImportStorageClass ( ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( isOSWindows ( ) ) return <STR_LIT> ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? <STR_LIT> : <STR_LIT> ; return <STR_LIT> ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return <STR_LIT> ;


<s> if ( ! HII -> mayBeNewStore ( MI ) ) return false ; MachineInstr * PacketMI = PacketSU -> getInstr ( ) ; if ( canPromoteToNewValueStore ( MI , PacketMI , DepReg ) ) return true ;


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { return & TSInfo ;


<s> bool hasNOP ( const MCSubtargetInfo * STI ) const { return STI -> getFeatureBits ( ) [ <STR_LIT> ] ;


<s> if ( hasGoyaISA ( ) ) return <NUM_LIT> ; else if ( hasGaudiISA ( ) ) return <NUM_LIT> ;


<s> assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; assert ( Largest + <NUM_LIT> < <NUM_LIT> ) ; result . push_back ( { Largest + <NUM_LIT> , LegalizerInfo :: Unsupported } ) ;

result . push_back ( { <NUM_LIT> , LegalizerInfo :: NarrowScalar } ) ;


<s> CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_SaveList : CSR_Win32_CFGuard_Check_NoSSE_SaveList ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: SwiftTail : if ( ! Is64Bit ) return CSR_32_SaveList ; return IsWin64 ? CSR_Win64_SwiftTail_SaveList : CSR_64_SwiftTail_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ; return CSR_32_AllRegs_SaveList ; } default : break ; } if ( Is64Bit ) { bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ;

if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_SaveList : CSR_64_SwiftError_SaveList ;


if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Printer . MF -> getContext ( ) ) , Printer . MF -> getContext ( ) ) ;


<s> Op -> Imm . Val = Val ; Op -> Imm . IsFPImm = IsFPImm ; Op -> Imm . Kind = ImmKindTyNone ; Op -> Imm . Type = Type ; Op -> Imm . Mods = Modifiers ( ) ; Op -> StartLoc = Loc ; Op -> EndLoc = Loc ;


<s> if ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) { x = get_pool_constant ( x ) ; return for_each_rtx ( & x , get_some_local_dynamic_name_1 , <NUM_LIT> ) ; } if ( GET_CODE ( x ) == SYMBOL_REF && tls_symbolic_operand ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) { cfun -> machine -> some_ld_name = XSTR ( x , <NUM_LIT> ) ; return <NUM_LIT> ;


<s> return true ; } if ( I -> getOpcode ( ) != Instruction :: Add && I -> getOpcode ( ) != Instruction :: Sub ) return false ; if ( ! ST -> hasDSP ( ) || ! EnableDSP || ! isSupportedType ( I ) ) return false ; if ( ST -> isThumb ( ) && ! ST -> hasThumb2 ( ) ) return false ; for ( auto & Op : I -> operands ( ) ) { if ( isa < Constant > ( Op ) ) { if ( ! EnableDSPWithImms ) return false ;


<s> bool isSplitCSR ( ) const { return IsSplitCSR ;


<s> O << MO . getImm ( ) ; return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : printSymbolOperand ( * this , MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << <STR_LIT> ; return false ; case MachineOperand :: MO_Register : O << '(' ; printOperand ( * this , MI , OpNo , O ) ; O << ')' ; return false ; } case 'c' : switch ( MO . getType ( ) ) { default : printOperand ( * this , MI , OpNo , O ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : printSymbolOperand ( * this , MO , O ) ; break ; } return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( * this , MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' :


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Val ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : Val = performANDCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : Val = performORCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performMULCombine ( N , DAG , DCI , this , Subtarget ) ; case <STR_LIT> : Val = performSHLCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVSELECTCombine ( N , DAG ) ; case <STR_LIT> : Val = performXORCombine ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : Val = performSETCCCombine ( N , DAG ) ; break ; } if ( Val . getNode ( ) ) {


<s> <ISA_LIT>_64TargetMachine :: <ISA_LIT>_64TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>TargetMachine ( T , TT , FS , true ) , DataLayout ( <STR_LIT> ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this ) , JITInfo ( * this ) {


<s> bool <ISA_LIT>TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DstAS ) const {


<s> return RegSavedAreaStartFrameIndex ;


<s> LLVM_DEBUG ( MO . dump ( ) ) ; if ( MO . isExpr ( ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( errs ( ) << ( unsigned ) MO . getExpr ( ) -> getKind ( ) << <STR_LIT> ) ; MCFixupKind FixupKind ; const MCSymbolRefExpr * expr = static_cast < const MCSymbolRefExpr * > ( MO . getExpr ( ) ) ; LLVM_DEBUG ( expr -> dump ( ) ) ; if ( expr -> getSymbol ( ) . isExternal ( ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; FixupKind = static_cast < MCFixupKind > ( <STR_LIT> ) ; } else { LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; FixupKind = static_cast < MCFixupKind > ( <STR_LIT> ) ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } assert ( MO . isImm ( ) && <STR_LIT> ) ;


<s> unsigned HOST_WIDE_INT value = <NUM_LIT> ; int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE ( mode ) ; int part_bits = GET_MODE_BITSIZE ( mode ) ; unsigned HOST_WIDE_INT part_mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << part_bits ) - <NUM_LIT> ; int i ; for ( i = <NUM_LIT> ; i < max_parts ; i ++ ) { if ( i == <NUM_LIT> ) value = ( unsigned HOST_WIDE_INT ) INTVAL ( op ) ; else value >>= part_bits ; if ( ( value & part_mask ) != ( def & part_mask ) ) return value & part_mask ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( getSwitchSet ( ) ) ) ;


<s> if ( ! isInt < <NUM_LIT> > ( Imm ) ) { Shift = countTrailingZeros < uint64_t > ( Imm ) ; int64_t ImmSh = static_cast < uint64_t > ( Imm ) >> Shift ; if ( isInt < <NUM_LIT> > ( ImmSh ) ) { Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned Result = <NUM_LIT> ; unsigned Lo = Imm & <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) { ++ Result ; } else if ( Lo ) { Result += <NUM_LIT> ; } else { ++ Result ; }


<s> std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( ) : TS . emitDirectiveNaNLegacy ( ) ; TS . updateABIInfo ( STI ) ; if ( ( ABI . IsO32 ( ) && ( STI . isABI_FPXX ( ) || STI . isFP64bit ( ) ) ) || STI . useSoftFloat ( ) ) TS . emitDirectiveModuleFP ( ) ; if ( ABI . IsO32 ( ) && ( ! STI . useOddSPReg ( ) || STI . isABI_FPXX ( ) ) ) TS . emitDirectiveModuleOddSPReg ( ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ;


<s> static __inline__ float __fsels ( float x , float y , float z ) { float r ;

__asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ;


<s> if ( RegNum == <NUM_LIT> ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( RegNum == <NUM_LIT> ) return - <NUM_LIT> ; Parser . Lex ( ) ; return RegNum ;


<s> for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( pru_ctable ) ; i ++ ) {

if ( pru_ctable [ i ] . valid && IN_RANGE ( caddr , pru_ctable [ i ] . base , pru_ctable [ i ] . base + <NUM_LIT> ) ) return i ;


if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ;


<s> <STR_LIT> ; B . buildInstr ( Opc ) . addDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . cloneMemRefs ( MI ) ;


<s> return C_CPP_HASHNODE ( __vector_keyword ) ; } else if ( ident ) rid_code = ( enum rid ) ( ident -> rid_code ) ; } if ( rid_code == RID_UNSIGNED || rid_code == RID_LONG || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || ( rid_code == RID_FLOAT && TARGET_VXE ) || rid_code == RID_DOUBLE ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_p = true ; else { do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = s390_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_p = true ;


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; unsigned Opc = <NUM_LIT> ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else {


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> const ReturnInst * Ret = cast < ReturnInst > ( I ) ; const Function & F = * I -> getParent ( ) -> getParent ( ) ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , * Context ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64_ELF_FIS ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ValLocs . size ( ) > <NUM_LIT> ) return false ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( RV ) ) { CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; unsigned RetReg = VA . getLocReg ( ) ; unsigned SrcReg = <ISA_LIT>MaterializeInt ( CI , <STR_LIT> , VA . getLocInfo ( ) != CCValAssign :: ZExt ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( RetReg ) ; } else { unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default :


<s> Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ;


<s> } if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasV4TOps ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && ! DisableDeallocRet ) { MachineBasicBlock :: iterator BeforeJMPR = MBB . begin ( ) == MBBI ? MBBI : std :: prev ( MBBI ) ; if ( BeforeJMPR != MBBI && BeforeJMPR -> getOpcode ( ) == <STR_LIT> ) { MBB . erase ( MBBI ) ; return ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI_end , dl , TII . get ( <STR_LIT> ) ) ; MIB -> copyImplicitOps ( * MBB . getParent ( ) , & * MBBI ) ; MBB . erase ( MBBI ) ; } else { MachineBasicBlock :: iterator Term = MBB . getFirstTerminator ( ) ;

MachineBasicBlock :: iterator I = Term == MBB . begin ( ) ? MBB . end ( ) : std :: prev ( Term ) ;


<s> switch ( ConstraintID ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_m : if ( ! SelectMem ( Op , Op0 ) ) return true ; OutOps . push_back ( Op0 ) ; return false ; case InlineAsm :: Constraint_o : if ( ! SelectOff ( Op , Op0 , Op1 ) ) return true ;


<s> if ( Register MOReg = MO . getReg ( ) ) { if ( TRI -> regsOverlap ( MOReg , Reg ) ) { if ( MO . isUse ( ) ) Ref . Use = true ; else if ( MO . isDef ( ) ) Ref . Def = true ; } } } }


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OL ) : SelectionDAGISel ( TM , OL ) {


<s> PB . registerPipelineStartEPCallback ( [ = ] ( ModulePassManager & MPM , PassBuilder :: OptimizationLevel ) { FunctionPassManager FPM ( DebugPassManager ) ; FPM . addPass ( <ISA_LIT>AbstractMemberAccessPass ( this ) ) ; FPM . addPass ( <ISA_LIT>PreserveDITypePass ( ) ) ; MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; } ) ; PB . registerPeepholeEPCallback ( [ = ] ( FunctionPassManager & FPM , PassBuilder :: OptimizationLevel Level ) {

FPM . addPass ( SimplifyCFGPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true ) ) ) ;


emitFunctionEnd ( MachineFunction & MF ) {


<s> DigitalebTargetMachine :: DigitalebTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : DigitalTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> unsigned Out = MRI -> createVirtualRegister ( QPR ? & <STR_LIT> : & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , InsertBefore , DL , TII -> get ( QPR ? <STR_LIT> : <STR_LIT> ) , Out ) . addReg ( Reg ) . addImm ( Lane ) ) ;


<s> Entry -> addLiveIn ( * I ) ; BuildMI ( * Entry , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVR ) . addReg ( * I ) ; for ( auto * Exit : Exits ) BuildMI ( * Exit , Exit -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * I ) . addReg ( NewVR ) ;


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ;

SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ;


<s> reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveInsn ( ) ; getParser ( ) . Lex ( ) ;


<s> bool <ISA_LIT>BaseRegisterInfo :: canSimplifyCallFramePseudos ( MachineFunction & MF ) const {

return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> <ISA_LIT>LETargetMachine :: <ISA_LIT>LETargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> if ( ! Visited . insert ( * PB ) . second ) continue ; if ( * PB == BB ) continue ; for ( MachineBasicBlock :: reverse_instr_iterator I = ( * PB ) -> instr_rbegin ( ) , E = ( * PB ) -> instr_rend ( ) ; I != E ; ++ I ) { int Opc = I -> getOpcode ( ) ; if ( Opc == LOOPi || Opc == LOOPr ) return & * I ; if ( Opc == EndLoopOp ) return <NUM_LIT> ; } MachineInstr * loop = findLoopInstr ( * PB , EndLoopOp , Visited ) ; if ( loop ) return loop ; } return <NUM_LIT> ;


<s> void <ISA_LIT>AsmPrinter :: printAddrMode3OffsetOperand ( const MachineInstr * MI , int Op ) { const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( MO1 . getReg ( ) ) { O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << TRI -> getAsmName ( MO1 . getReg ( ) ) ; return ; }

unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ;


<s> if ( Start -> getOpcode ( ) == <STR_LIT> ) { TPNumElements = Start -> getOperand ( <NUM_LIT> ) ; StartInsertPt = Start ; StartInsertBB = Start -> getParent ( ) ; } else { TPNumElements = VCTP -> getOperand ( <NUM_LIT> ) ; MCRegister NumElements = TPNumElements . getReg ( ) . asMCReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StartInsertPt != StartInsertBB -> end ( ) && ! RDA . isReachingDefLiveOut ( & * StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( StartInsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , & * StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; StartInsertBB -> insert ( StartInsertPt , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( & * StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; StartInsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , & * StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { MachineOperand Operand = ElemDef -> getOperand ( <NUM_LIT> ) ; if ( isMovRegOpcode ( ElemDef -> getOpcode ( ) ) && RDA . getUniqueReachingMIDef ( ElemDef , Operand . getReg ( ) . asMCReg ( ) ) == RDA . getUniqueReachingMIDef ( & * StartInsertPt , Operand . getReg ( ) . asMCReg ( ) ) ) { TPNumElements = Operand ; NumElements = TPNumElements . getReg ( ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } } } } auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , MCRegister NumElements ) { if ( MBB -> empty ( ) ) return false ; if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = Preheader ; while ( MBB && MBB != StartInsertBB ) {

if ( CannotProvideElements ( MBB , NumElements ) ) {


<s> Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return false ; if ( ! isLaneMaskReg ( Reg ) ) return false ; } if ( MI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; int64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm == <NUM_LIT> ) { Val = false ; return true ;


<s> return ( __m512i ) __builtin_ia32_pabsq512_mask ( ( __v8di ) __A , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> static const unsigned CalleeSavedRegsIntr [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const unsigned CalleeSavedRegsIntrFP [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_INTR ? CalleeSavedRegsIntrFP : CalleeSavedRegsFP ) ;

else return ( F -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_INTR ? CalleeSavedRegsIntr : CalleeSavedRegs ) ;


<s> if ( isThumb1 ) return false ; const MachineOperand & BaseOP = MI -> getOperand ( <NUM_LIT> ) ; unsigned Base = BaseOP . getReg ( ) ; bool BaseKill = BaseOP . isKill ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; unsigned Opcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; int Bytes = getLSMultipleTransferSize ( MI ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) return false ; } MBB . erase ( MergeInstr ) ; unsigned NewOpc = getUpdatingLSMultipleOpcode ( Opcode , Mode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned OpNum = <NUM_LIT> , e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . addOperand ( MI -> getOperand ( OpNum ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; MBB . erase ( MBBI ) ; return true ;


<s> if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( DL ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC >> Scale , dl , <STR_LIT> ) ;


<s> } if ( NumMove <= <NUM_LIT> ) Ops . pop_back ( ) ; else { SmallPtrSet < MachineInstr * , <NUM_LIT> > MemOps ; SmallSet < unsigned , <NUM_LIT> > MemRegs ; for ( int i = NumMove - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { MemOps . insert ( Ops [ i ] ) ; MemRegs . insert ( Ops [ i ] -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } bool DoMove = ( LastLoc - FirstLoc ) <= NumMove * <NUM_LIT> ; if ( DoMove ) DoMove = IsSafeAndProfitableToMove ( isLd , Base , FirstOp , LastOp , MemOps , MemRegs , TRI ) ; if ( ! DoMove ) { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( InsertPos ) || InsertPos -> isDebugValue ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned EvenReg = <NUM_LIT> , OddReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , EvenReg , OddReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ;

const MCInstrDesc & MCID = TII -> get ( NewOpc ) ;


<s> int Splat = getT2SOImmValSplatVal ( Arg ) ; if ( Splat != - <NUM_LIT> ) return Splat ; int Rot = getT2SOImmValRotateVal ( Arg ) ;


<s> bool <ISA_LIT>TargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRIN<ISA_LIT>C_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> :

return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> if ( parseBranchModifiers ( Operands ) != MatchOperand_Success ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } if ( parseOperand ( Operands , Name ) != MatchOperand_Success ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) || getLexer ( ) . is ( AsmToken :: Plus ) ) { if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; } Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) != MatchOperand_Success ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ;


<s> unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT> , PtrVT ) , Size ) ; SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ;

SDValue Ops [ <NUM_LIT> ] = { Chain , NegSize , FPSIdx } ;


<s> const unsigned FixupKind = Fixup . getKind ( ) ; switch ( FixupKind ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> inline void gt_pch_nx ( function_instance * , gt_pointer_operator , void * ) {


<s> return ( unsigned ) ( imm & <NUM_LIT> ) ;


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ;


<s> <ISA_LIT>CCState ( CallingConv :: ID CC , bool isVarArg , MachineFunction & MF , SmallVectorImpl < CCValAssign > & locs , LLVMContext & C ) : CCState ( CC , isVarArg , MF , locs , C ) {


<s> loopMBB -> addSuccessor ( sinkMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> normalizeSuccProbs ( ) ; BuildMI ( loopMBB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( IsNand ) { BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( <STR_LIT> ) . addReg ( BinOpRes ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( BinOpRes ) . addReg ( Mask ) ; } else if ( ! IsSwap ) { BuildMI ( loopMBB , DL , TII -> get ( Opcode ) , BinOpRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( BinOpRes ) . addReg ( Mask ) ; } else { BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( Incr ) . addReg ( Mask ) ; } BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( OldVal ) . addReg ( Mask2 ) ; BuildMI ( loopMBB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( StoreVal ) . addReg ( BinOpRes ) ; BuildMI ( loopMBB , DL , TII -> get ( SC ) , StoreVal ) . addReg ( StoreVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loopMBB , DL , TII -> get ( BEQ ) ) . addReg ( StoreVal ) . addReg ( <STR_LIT> ) . addMBB ( loopMBB ) ; sinkMBB -> addSuccessor ( exitMBB , BranchProbability :: getOne ( ) ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldVal ) . addReg ( Mask ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest ) . addReg ( ShiftAmnt ) ; if ( STI -> has<ISA_LIT>32r2 ( ) ) { BuildMI ( sinkMBB , DL , TII -> get ( SEOp ) , Dest ) . addReg ( Dest ) ; } else { const unsigned ShiftImm = SEOp == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ;

BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addImm ( ShiftImm ) ;


<s> } else { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SQ_MESSAGE , Inst ) ; break ; case <STR_LIT> : case <STR_LIT> : { int Imm = TII -> getNamedOperand ( Inst , <STR_LIT> :: tgt ) -> getImm ( ) ; if ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_PARAM_ACCESS , Inst ) ; else if ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_POS_ACCESS , Inst ) ; else ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_GPR_LOCK , Inst ) ; break ; } case <STR_LIT> : case <STR_LIT> : ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ; break ; default : break ; } }


<s> Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> IsRV64 = IsRV64 ; return Op ;


<s> bool isNEONi16ByteReplicate ( ) const {

return isNEONByteReplicate ( <NUM_LIT> ) ;


<s> if ( cum -> nbytes > <NUM_LIT> * UNITS_PER_WORD ) return <NUM_LIT> ; if ( type == NULL_TREE && cum -> nbytes + size > <NUM_LIT> * UNITS_PER_WORD ) return <NUM_LIT> ; switch ( cum -> nbytes / UNITS_PER_WORD ) { case <NUM_LIT> : result = gen_rtx_REG ( mode , <NUM_LIT> ) ; break ; case <NUM_LIT> : result = gen_rtx_REG ( mode , <NUM_LIT> ) ; break ; case <NUM_LIT> : result = gen_rtx_REG ( mode , <NUM_LIT> ) ; break ; case <NUM_LIT> : result = gen_rtx_REG ( mode , <NUM_LIT> ) ;


<s> case TargetOpcode :: G_FDIV : case TargetOpcode :: G_FCONSTANT : case TargetOpcode :: G_FPEXT : case TargetOpcode :: G_FPTRUNC : return true ;


<s> case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB ) ;


<s> int64_t Value = CE -> getValue ( ) ;

return ( Value >= <NUM_LIT> && Value < <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) ;


<s> pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) pat = COND_EXEC_CODE ( pat ) ; if ( GET_CODE ( pat ) != SET ) return - <NUM_LIT> ; reg = SET_DEST ( pat ) ; if ( ! REG_P ( reg ) ) return - <NUM_LIT> ; mem = SET_SRC ( pat ) ;

if ( GET_CODE ( mem ) == ZERO_EXTEND ) mem = XEXP ( mem , <NUM_LIT> ) ;


return isImmediate < - <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> if ( TII -> hasModifiersSet ( Inst , <STR_LIT> :: gds ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , GDS_ACCESS , Inst ) ; ScoreBrackets -> updateByEvent ( TII , TRI , MRI , GDS_GPR_LOCK , Inst ) ; } else { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; } } else if ( TII -> isFLAT ( Inst ) ) { assert ( Inst . mayLoad ( ) || Inst . mayStore ( ) ) ; if ( TII -> usesVM_CNT ( Inst ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; if ( TII -> usesLGKM_CNT ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; if ( mayAccessLDSThroughFlat ( Inst ) ) ScoreBrackets -> setPendingFlat ( ) ; } } else if ( <ISA_LIT>InstrInfo :: isVMEM ( Inst ) && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; if ( ST -> vmemWriteNeedsExpWaitcnt ( ) && ( Inst . mayStore ( ) || <STR_LIT> ( Inst . getOpcode ( ) ) != - <NUM_LIT> ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMW_GPR_LOCK , Inst ) ; } } else if ( TII -> isSMRD ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ; } else { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SQ_MESSAGE , Inst ) ; break ; case <STR_LIT> : case <STR_LIT> : { int Imm = TII -> getNamedOperand ( Inst , <STR_LIT> :: tgt ) -> getImm ( ) ; if ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_PARAM_ACCESS , Inst ) ; else if ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_POS_ACCESS , Inst ) ; else ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_GPR_LOCK , Inst ) ; break ; } case <STR_LIT> : case <STR_LIT> : ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ; break ; default : break ;


<s> return <ISA_LIT>Insts [ Opcode ] . Name ;


<s> EVT SrcVT , DestVT ; SrcVT = TLI . getValueType ( DL , Op -> getType ( ) , true ) ; DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ;

if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ;


<s> case E_DImode : case E_SFmode : case E_DFmode : break ; default : warning_at ( DECL_SOURCE_LOCATION ( node -> decl ) , <NUM_LIT> , <STR_LIT> , ret_type ) ; return <NUM_LIT> ; } tree t ; int i ; for ( t = DECL_ARGUMENTS ( node -> decl ) , i = <NUM_LIT> ; t ; t = DECL_CHAIN ( t ) , i ++ ) switch ( TYPE_MODE ( TREE_TYPE ( t ) ) ) { case E_QImode : case E_HImode : case E_SImode : case E_DImode : case E_SFmode : case E_DFmode : break ; default : warning_at ( DECL_SOURCE_LOCATION ( node -> decl ) , <NUM_LIT> , <STR_LIT> , TREE_TYPE ( t ) ) ; return <NUM_LIT> ; } if ( ! TREE_PUBLIC ( node -> decl ) ) { if ( TARGET_AVX512F ) clonei -> vecsize_mangle = 'e' ; else if ( TARGET_AVX2 ) clonei -> vecsize_mangle = 'd' ; else if ( TARGET_AVX ) clonei -> vecsize_mangle = 'c' ; else clonei -> vecsize_mangle = 'b' ; ret = <NUM_LIT> ; } else { clonei -> vecsize_mangle = <STR_LIT> [ num ] ; ret = <NUM_LIT> ; }