<s> auto & Op1 = N -> getOperand ( <NUM_LIT> ) ; EVT MemVT = SN -> getMemoryVT ( ) ; if ( MemVT . isInteger ( ) ) { if ( SDValue Value = combineTruncateExtract ( SDLoc ( N ) , MemVT , SN -> getValue ( ) , DCI ) ) { DCI . AddToWorklist ( Value . getNode ( ) ) ; return DAG . getTruncStore ( SN -> getChain ( ) , SDLoc ( SN ) , Value , SN -> getBasePtr ( ) , SN -> getMemoryVT ( ) , SN -> getMemOperand ( ) ) ; } } if ( ! SN -> isVolatile ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && ( Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> ) ) { SDValue BSwapOp = Op1 . getOperand ( <NUM_LIT> ) ; if ( BSwapOp . getValueType ( ) == <STR_LIT> ) BSwapOp = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSwapOp ) ; SDValue Ops [ ] = {

N -> getOperand ( <NUM_LIT> ) , BSwapOp , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( Op1 . getValueType ( ) ) } ;


<s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : IsKernel ( false ) {


<s> void GCNScheduleDAGMILive :: collectRematerializableInstructions ( unsigned HighRPIdx ) { const <ISA_LIT>RegisterInfo * SRI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const GCNRPTracker :: LiveRegSet & HighRPLiveIns = LiveIns [ HighRPIdx ] ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I != E ; ++ I ) { Register Reg = Register :: index2VirtReg ( I ) ; if ( ! LIS -> hasInterval ( Reg ) ) continue ; if ( ! SRI -> isVGPRClass ( MRI . getRegClass ( Reg ) ) || ! MRI . hasOneDef ( Reg ) || ! MRI . hasOneUse ( Reg ) ) continue ; if ( HighRPLiveIns . find ( Reg ) == HighRPLiveIns . end ( ) ) continue ; MachineInstr * Def = MRI . getOneDef ( Reg ) -> getParent ( ) ; if ( ! Def || Def -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != <NUM_LIT> || ! isTriviallyReMaterializable ( * Def , AA ) ) continue ; MachineInstr * UseI = & * MRI . use_instr_begin ( Reg ) ; if ( Def -> getParent ( ) == UseI -> getParent ( ) ) continue ; RematerializableInsts . push_back ( std :: make_pair ( Def , UseI ) ) ; }


<s> case D11 : case D10 : case D9 : case D8 : return true ;


<s> bool <ISA_LIT>FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI . hasCalls ( ) || hasFP ( MF ) || NumBytes > <NUM_LIT> ) ;


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ;

if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ;


<s> FunctionPass * create<ISA_LIT>ExpandSSRPass ( ) { return new <ISA_LIT>ExpandSSR ( ) ;


<s> dest = SET_DEST ( pat ) ; src = SET_SRC ( pat ) ; } callee = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; if ( SIBLING_CALL_P ( insn ) ) { if ( REG_P ( callee ) ) newpat = gen_indirect_sibcall_shadow ( ) ; else newpat = gen_sibcall_shadow ( callee ) ; pat = gen_real_jump ( callee ) ; } else if ( dest != NULL_RTX ) { if ( REG_P ( callee ) ) newpat = gen_indirect_call_value_shadow ( dest ) ; else newpat = gen_call_value_shadow ( dest , callee ) ; pat = gen_real_call ( callee ) ; } else { if ( REG_P ( callee ) ) newpat = gen_indirect_call_shadow ( ) ; else newpat = gen_call_shadow ( callee ) ; pat = gen_real_call ( callee ) ; } pat = duplicate_cond ( pat , insn ) ; newpat = duplicate_cond ( newpat , insn ) ; } else {


<s> return ; } else { enum rtx_code code = GET_CODE ( operands [ <NUM_LIT> ] ) ; enum rtx_code new_code = code ; machine_mode cmp0_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; machine_mode cmp1_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx cmp_op0 = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; rtx cmp_op1 = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; rtx tmp ; int reverse = <NUM_LIT> ; switch ( code ) { case GT : case GE : tmp = cmp_op0 ; cmp_op0 = cmp_op1 ; cmp_op1 = tmp ; new_code = swap_condition ( new_code ) ;


<s> if ( ExtractedVecT == VecT ) return Op ; const SDNode * Index = Extract . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ! isa < ConstantSDNode > ( Index ) ) return SDValue ( ) ; unsigned IndexVal = cast < ConstantSDNode > ( Index ) -> getZExtValue ( ) ; unsigned Scale = ExtractedVecT . getVectorNumElements ( ) / VecT . getVectorNumElements ( ) ; assert ( Scale > <NUM_LIT> ) ; SDValue NewIndex = DAG . getConstant ( IndexVal * Scale , DL , Index -> getValueType ( <NUM_LIT> ) ) ; SDValue NewExtract = DAG . getNode ( <STR_LIT> , DL , Extract . getValueType ( ) , DAG . getBitcast ( ExtractedVecT , Extract . getOperand ( <NUM_LIT> ) ) , NewIndex ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , NewExtract , Op . getOperand ( <NUM_LIT> ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ;

MIB . addReg ( SrcReg , false , false , isKill ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerShifts ( SDValue Op , SelectionDAG & DAG ) const {


<s> inline static <STR_LIT> stringTo<ISA_LIT>ICondCode ( StringRef S ) {

return StringSwitch < <STR_LIT> > ( S ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> const auto * IVTy = cast < VectorType > ( II . getType ( ) ) ; while ( Cursor ) { const auto * CursorVTy = cast < VectorType > ( Cursor -> getType ( ) ) ; if ( CursorVTy -> getElementCount ( ) . getKnownMinValue ( ) < IVTy -> getElementCount ( ) . getKnownMinValue ( ) ) break ;

if ( Cursor -> getType ( ) == IVTy ) EarliestReplacement = Cursor ;


<s> SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , G ) ;

if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( llvm :: AsmToken DirectiveID ) { return true ;


<s> int ok = <NUM_LIT> ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) <= MAX_LD_OFFSET ( GET_MODE ( x ) ) ) ) {

rtx xx = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> return autopref_multipass_dfa_lookahead_guard ( insn , ready_index ) ;


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) {

PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ;


<s> MCAsmParser & Parser = getParser ( ) ; const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) { return matchCPURegisterName ( Parser . getLexer ( ) . peekTok ( ) . getString ( ) ) == - <NUM_LIT> ? MatchOperand_ParseFail : MatchOperand_NoMatch ; } if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ; if ( ! MCE ) return MatchOperand_NoMatch ; int64_t Val = MCE -> getValue ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;

Operands . push_back ( <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> - Val , getContext ( ) ) , S , E , * this ) ) ;


<s> } for ( i = R_LR ( <NUM_LIT> ) ; i >= R_LR ( <NUM_LIT> ) ; i -- ) if ( regs_ever_live [ i ] ) break ; a29k_regstack_size = i - ( R_LR ( <NUM_LIT> ) - <NUM_LIT> ) ; if ( a29k_makes_calls && a29k_regstack_size < <NUM_LIT> ) a29k_regstack_size = <NUM_LIT> ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = GPRDecoderTable [ RegNo + <NUM_LIT> ] ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> r0 = * CONST_DOUBLE_REAL_VALUE ( operand ) ; if ( exact_real_inverse ( DFmode , & r0 ) && ! REAL_VALUE_NEGATIVE ( r0 ) ) { if ( exact_real_truncate ( DFmode , & r0 ) ) { HOST_WIDE_INT value = real_to_integer ( & r0 ) ; value = value & <NUM_LIT> ; if ( ( value != <NUM_LIT> ) && ( ( value & ( value - <NUM_LIT> ) ) == <NUM_LIT> ) ) return int_log2 ( value ) ; } } return <NUM_LIT> ;


<s> mips_split_const ( src , & base , & offset ) ; if ( ! TARGET_MIPS16 && offset != <NUM_LIT> && ( ! no_new_pseudos || SMALL_OPERAND ( offset ) ) ) { base = mips_force_temporary ( dest , base ) ; emit_move_insn ( dest , mips_add_offset ( <NUM_LIT> , base , offset ) ) ; return ; } src = force_const_mem ( mode , src ) ; if ( ! memory_operand ( src , VOIDmode ) ) src = replace_equiv_address ( src , mips_split_symbol ( dest , XEXP ( src , <NUM_LIT> ) ) ) ; emit_move_insn ( dest , src ) ;


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const {


<s> static SDValue getTagSymNode ( int Tag , SelectionDAG * DAG ) { assert ( Tag == <STR_LIT> ) ; auto & MF = DAG -> getMachineFunction ( ) ; const auto & TLI = DAG -> getTargetLoweringInfo ( ) ; MVT PtrVT = TLI . getPointerTy ( DAG -> getDataLayout ( ) ) ;

const char * SymName = MF . createExternalSymbolName ( <STR_LIT> ) ;


<s> static enum riscv_symbol_type riscv_classify_symbol ( const_rtx x ) {

if ( riscv_tls_symbol_p ( x ) ) return SYMBOL_TLS ;


<s> int fp_reg_size = <NUM_LIT> ; if ( bitmap_bit_p ( components , <NUM_LIT> ) ) { rtx lr = gen_rtx_REG ( reg_mode , LR_REGNO ) ; rtx reg = gen_rtx_REG ( reg_mode , <NUM_LIT> ) ; rtx_insn * insn = emit_move_insn ( reg , lr ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( reg , lr ) ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ;


<s> if ( ! MemOpChains2 . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains2 ) ; Chain = EmitTailCallStoreFPAndRetAddr ( DAG , MF , Chain , LROp , FPOp , SPDiff , is<ISA_LIT>64 , isDarwinABI , dl ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag , dl ) ;

InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MI -> addRegisterKilled ( SrcRegS , TRI , true ) ; }

DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ;


<s> return ( int32x2_t ) __builtin_neon_vrshlsv2si ( __a , __b ) ;


<s> NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> emitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> emitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> emitLabel ( Target ) ; recordSled ( CurSled , MI , SledKind :: TAIL_CALL ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;

OpCode = convertTailJumpOpcode ( OpCode ) ;


<s> MachineIRBuilder B ( MI ) ; MachineFunction * MF = MI . getMF ( ) ; MachineRegisterInfo & MRI = OpdMapper . getMRI ( ) ; InstManager NewInstrObserver ( NewInstrs ) ; GISelObserverWrapper WrapperObserver ( & NewInstrObserver ) ; LegalizerHelper Helper ( * MF , WrapperObserver , B ) ; LegalizationArtifactCombiner ArtCombiner ( B , MF -> getRegInfo ( ) , * MF -> getSubtarget ( ) . getLegalizerInfo ( ) ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_PHI : case TargetOpcode :: G_SELECT : { Helper . narrowScalar ( MI , <NUM_LIT> , LLT :: scalar ( <NUM_LIT> ) ) ; while ( ! NewInstrs . empty ( ) ) { MachineInstr * NewMI = NewInstrs . pop_back_val ( ) ; if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_UNMERGE_VALUES ) { SmallVector < MachineInstr * , <NUM_LIT> > DeadInstrs ; ArtCombiner . tryCombineMerges ( * NewMI , DeadInstrs ) ; for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI -> eraseFromParent ( ) ; } else if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_MERGE_VALUES ) continue ; else for ( auto Op : NewMI -> operands ( ) ) { if ( Op . isReg ( ) ) { assert ( MRI . getType ( Op . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MRI . setRegBank ( Op . getReg ( ) , getRegBank ( <STR_LIT> ) ) ; } } } return ; } case TargetOpcode :: G_UNMERGE_VALUES : { SmallVector < MachineInstr * , <NUM_LIT> > DeadInstrs ; ArtCombiner . tryCombineMerges ( MI , DeadInstrs ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> if ( isInt < <NUM_LIT> > ( Offset ) ) { emitRRI ( Opcode , SrcReg , BaseReg , Offset , IDLoc , STI ) ; return ; } unsigned ATReg = GetATReg ( ) ; if ( ! ATReg ) return ;

unsigned LoOffset = Offset & <NUM_LIT> ;


<s> tree caller_opts = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; struct cl_target_option * callee_ptr , * caller_ptr ; unsigned int i ; if ( ! callee_opts ) callee_opts = target_option_default_node ; if ( ! caller_opts ) caller_opts = target_option_default_node ;

if ( callee_opts == caller_opts ) return true ;


<s> fcfg . printNode ( * ( * I ) -> ipdom ) << <STR_LIT> ; for ( Node :: child_iterator SI = ( * I ) -> succs_begin ( ) , SE = ( * I ) -> succs_end ( ) ; SI != SE ; ++ SI ) {

fcfg . printNode ( * * SI ) << <STR_LIT> ;


<s> <ISA_LIT>MachineFunctionInfo * MFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUInstrInfo :: expandPostRAPseudo ( MI ) ; case AMDGPU :: <ISA_LIT>_SPILL_S512_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_S256_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_S128_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_S64_SAVE : { unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; unsigned FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill ; unsigned SubReg = RI . getPhysRegSubReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , & AMDGPU :: SGPR_32RegClass , i ) ; Spill = MFI -> SpillTracker . getSpilledReg ( FrameIndex ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_WRITELANE_B32 ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SubReg ) . addImm ( Spill . Lane + i ) ; } MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: <ISA_LIT>_SPILL_S512_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_S256_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_S128_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_S64_RESTORE : { unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill ; unsigned FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SubReg = RI . getPhysRegSubReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , & AMDGPU :: SGPR_32RegClass , i ) ; Spill = MFI -> SpillTracker . getSpilledReg ( FrameIndex ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_READLANE_B32 ) , SubReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( Spill . Lane + i ) ; } MI -> eraseFromParent ( ) ; break ; }


<s> switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case COND_EQ : return <STR_LIT> ; case COND_NE : return <STR_LIT> ; case COND_GT : return <STR_LIT> ; case COND_GE : return <STR_LIT> ; case COND_LT : return <STR_LIT> ; case COND_LE : return <STR_LIT> ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDFormAddr ( SDValue Op , SDValue N , SDValue & Base , SDValue & Index ) {

return DFormAddressPredicate ( Op , N , Base , Index , <ISA_LIT>FrameInfo :: minFrameOffset ( ) , <ISA_LIT>FrameInfo :: maxFrameOffset ( ) ) ;


<s> } else { const fltSemantics & Sem = APFloat :: IEEEsingle ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask1 = DAG . getLoad ( SrcVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , SrcVT , Op1 , Mask1 ) ; if ( SrcVT . bitsGT ( VT ) ) { SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } CV . clear ( ) ; if ( VT == <STR_LIT> ) { const fltSemantics & Sem = APFloat :: IEEEdouble ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } else { const fltSemantics & Sem = APFloat :: IEEEsingle ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( Sem , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ;


<s> display_content_memory ( stderr ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , get_content_name ( get_content_index ( from ) , mode ) ) ; fprintf ( dump_file , <STR_LIT> , get_content_name ( get_content_index ( to ) , mode ) ) ; } } else { rtx move = mode == QImode ? gen_movqi ( to , from ) : gen_movhi ( to , from ) ; EM ( move ) ; if ( where == NULL_RTX ) emit_insn ( move ) ; else if ( before ) emit_insn_before ( move , where ) ; else { rtx note = find_reg_note ( where , REG_EH_REGION , NULL_RTX ) ; if ( note != NULL_RTX ) { add_reg_note ( move , REG_EH_REGION , XEXP ( note , <NUM_LIT> ) ) ; remove_note ( where , note ) ; } emit_insn_after ( move , where ) ; }

if ( before ) record_content ( to , from ) ;


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , JITCodeEmitter & JCE ) { PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ;


<s> NodePreLegalizer ( ) : FunctionPass ( ID ) , FDivFunc ( nullptr ) , FRemFunc ( nullptr ) , UDivFunc ( nullptr ) , URemFunc ( nullptr ) , SDivFunc ( nullptr ) , SRemFunc ( nullptr ) {


<s> case EXCESS_PRECISION_TYPE_FAST : case EXCESS_PRECISION_TYPE_STANDARD : return ( ( TARGET_ZFH || TARGET_ZHINX ) ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ) ; case EXCESS_PRECISION_TYPE_IMPLICIT : case EXCESS_PRECISION_TYPE_FLOAT16 : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 ;


<s> MaxAlign = Align ( <NUM_LIT> ) ; for ( const Argument & Arg : F . args ( ) ) { Type * ArgTy = Arg . getType ( ) ; const Align Alignment = DL . getABITypeAlign ( ArgTy ) ;

uint64_t AllocSize = DL . getTypeAllocSize ( ArgTy ) ;


<s> return SelectAdd ( N ) ; case <STR_LIT> : return SelectSHL ( N ) ; case <STR_LIT> : return SelectLoad ( N ) ; case <STR_LIT> : return SelectStore ( N ) ; case <STR_LIT> : return SelectSelect ( N ) ; case <STR_LIT> : return SelectTruncate ( N ) ;


<s> vld1_dup_f16 ( const float16_t * __a ) {


<s> AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> return aarch64_classify_vector_mode ( mode ) & VEC_ANY_SVE ;


<s> for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) { int j ; int n_this_op = this_rr -> op_info [ i ] . n_chains ; for ( j = <NUM_LIT> ; j < n_this_op ; j ++ ) { du_head_p other = this_rr -> op_info [ i ] . heads [ j ] ; if ( regrename_chain_from_id ( other -> id ) == this_head ) break ; } if ( j == n_this_op ) continue ; if ( n_this_op != <NUM_LIT> ) goto out_fail ; mask_changed |= <NUM_LIT> << i ; } gcc_assert ( mask_changed != <NUM_LIT> ) ; if ( mask_changed != mask1 && mask_changed != mask2 ) goto out_fail ; } COMPL_HARD_REG_SET ( unavailable , reg_class_contents [ ( int ) super_class ] ) ; old_reg = this_head -> regno ; best_reg = find_rename_reg ( this_head , super_class , & unavailable , old_reg , true ) ; ok = regrename_do_replace ( this_head , best_reg ) ; gcc_assert ( ok ) ; count_unit_reqs ( new_reqs , head , PREV_INSN ( tail ) ) ; merge_unit_reqs ( new_reqs ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) , op_mask , orig_side , best_reg ) ; fprintf ( dump_file , <STR_LIT> , unit_req_imbalance ( reqs ) , unit_req_imbalance ( new_reqs ) ) ; } if ( unit_req_imbalance ( new_reqs ) > unit_req_imbalance ( reqs ) ) { ok = regrename_do_replace ( this_head , old_reg ) ; gcc_assert ( ok ) ; } else memcpy ( reqs , new_reqs , sizeof ( unit_req_table ) ) ;


<s> <ISA_LIT>VSXCopyCleanup ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>VSXCopyCleanupPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> mask = vec_sra ( vec_sl ( neg_b , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ; return ( ( qword ) ( vec_sra ( ( vec_int4 ) ( a ) , ( vec_uint4 ) vec_or ( neg_b , mask ) ) ) ) ;


<s> if ( Value == <NUM_LIT> ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; auto NumBits = Info . TargetSize + Info . TargetOffset ; auto NumBytes = ( NumBits / <NUM_LIT> ) + ( ( NumBits % <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; ++ i ) { uint8_t mask = ( ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ) ; Data [ Offset + i ] |= mask ; }


<s> for ( unsigned i = <NUM_LIT> , e = MFI -> getLocalFrameObjectCount ( ) ; i != e ; ++ i ) { std :: pair < int , int64_t > Entry = MFI -> getLocalFrameObjectMap ( i ) ; int64_t FIOffset = ( StackGrowsDown ? - Offset : Offset ) + Entry . second ; DEBUG ( dbgs ( ) << <STR_LIT> << Entry . first << <STR_LIT> << FIOffset << <STR_LIT> ) ; MFI -> setObjectOffset ( Entry . first , FIOffset ) ; } Offset += MFI -> getLocalFrameSize ( ) ; MaxAlign = std :: max ( Align , MaxAlign ) ; } for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isObjectPreAllocated ( i ) && MFI -> getUseLocalStackAllocationBlock ( ) ) continue ; if ( MFI -> isDeadObjectIndex ( i ) ) continue ; AdjustStackOffset ( MFI , i , StackGrowsDown , Offset , MaxAlign ) ; } if ( ! TFI . targetHandlesStackFrameRounding ( ) ) { if ( MFI -> adjustsStack ( ) && TFI . hasReservedCallFrame ( Fn ) ) Offset += MFI -> getMaxCallFrameSize ( ) ; unsigned StackAlign ; if ( MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) || ( RegInfo -> needsStackRealignment ( Fn ) && MFI -> getObjectIndexEnd ( ) != <NUM_LIT> ) ) StackAlign = TFI . getStackAlignment ( ) ;

else StackAlign = TFI . getTransientStackAlignment ( ) ;


<s> case EQ : branch = <STR_LIT> ; break ; case GE : branch = <STR_LIT> ; break ; case GT : branch = <STR_LIT> ; break ; case LE : branch = <STR_LIT> ; break ; case LT : branch = <STR_LIT> ; break ; case UNORDERED : branch = <STR_LIT> ; break ; case ORDERED : branch = <STR_LIT> ; break ; case UNGT : branch = <STR_LIT> ; break ; case UNLT : branch = <STR_LIT> ; break ; case UNEQ : branch = <STR_LIT> ; break ; case UNGE : branch = <STR_LIT> ; break ; case UNLE : branch = <STR_LIT> ; break ; case LTGT : branch = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } string [ <NUM_LIT> ] = '\0' ; if ( ! TARGET_V9 ) strcpy ( string , <STR_LIT> ) ; strcat ( string , branch ) ; } else { switch ( code ) { case NE : branch = <STR_LIT> ; break ; case EQ : branch = <STR_LIT> ; break ; case GE : if ( mode == CC_NOOVmode || mode == CCX_NOOVmode ) branch = <STR_LIT> ; else branch = <STR_LIT> ; break ; case GT : branch = <STR_LIT> ; break ; case LE : branch = <STR_LIT> ; break ; case LT : if ( mode == CC_NOOVmode || mode == CCX_NOOVmode ) branch = <STR_LIT> ; else branch = <STR_LIT> ; break ; case GEU : branch = <STR_LIT> ; break ; case GTU : branch = <STR_LIT> ; break ; case LEU : branch = <STR_LIT> ; break ; case LTU : branch = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } strcpy ( string , branch ) ; } spaces -= strlen ( branch ) ; p = strchr ( string , '\0' ) ; if ( annul && ! far ) { strcpy ( p , <STR_LIT> ) ; p += <NUM_LIT> ; spaces -= <NUM_LIT> ; } if ( TARGET_V9 ) { rtx note ; int v8 = <NUM_LIT> ; if ( ! far && insn && INSN_ADDRESSES_SET_P ( ) ) { int delta = ( INSN_ADDRESSES ( INSN_UID ( dest ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) ) ; if ( delta < - <NUM_LIT> || delta >= <NUM_LIT> ) v8 = <NUM_LIT> ; } if ( mode == CCFPmode || mode == CCFPEmode ) { static char v9_fcc_labelno [ ] = <STR_LIT> ; v9_fcc_labelno [ <NUM_LIT> ] = REGNO ( cc_reg ) - SPARC_FIRST_V9_FCC_REG + '0' ; labelno = v9_fcc_labelno ; if ( v8 ) {

gcc_assert ( REGNO ( cc_reg ) == SPARC_FCC_REG ) ;


<s> nCI -> insertBefore ( CI ) ; CI -> replaceAllUsesWith ( nCI ) ; } else if ( LHS -> getName ( ) . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) { BinaryOperator * mulOp = BinaryOperator :: Create ( Instruction :: Mul , CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , <STR_LIT> , CI ) ; CI -> replaceAllUsesWith ( mulOp ) ; } else if ( LHS -> getName ( ) . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ) { Type * aType = CI -> getOperand ( <NUM_LIT> ) -> getType ( ) ; bool isVector = aType -> isVectorTy ( ) ; int numEle = isVector ? dyn_cast < VectorType > ( aType ) -> getNumElements ( ) : <NUM_LIT> ; std :: vector < Type * > callTypes ; callTypes . push_back ( CI -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; callTypes . push_back ( CI -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; FunctionType * funcType = FunctionType :: get ( CI -> getOperand ( <NUM_LIT> ) -> getType ( ) , callTypes , false ) ; std :: string name = <STR_LIT> ; if ( isVector ) { name += <STR_LIT> + itostr ( numEle ) + <STR_LIT> ; } else { name += <STR_LIT> ; } Function * Func = dyn_cast < Function > ( CI -> getParent ( ) -> getParent ( ) -> getParent ( ) -> getOrInsertFunction ( StringRef ( name ) , funcType ) ) ; Value * Operands [ <NUM_LIT> ] = { CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) } ; CallInst * nCI = CallInst :: Create ( Func , Operands , <STR_LIT> ) ; nCI -> insertBefore ( CI ) ; CI -> replaceAllUsesWith ( nCI ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; if ( HasDef ) return false ; HasDef = true ; } for ( auto & Mo : MI -> memoperands ( ) ) if ( Mo -> isVolatile ( ) || Mo -> isAtomic ( ) ) return false ;


<s> int ix86_compare_version_priority ( tree decl1 , tree decl2 ) { unsigned int priority1 = get_builtin_code_for_version ( decl1 , NULL ) ; unsigned int priority2 = get_builtin_code_for_version ( decl2 , NULL ) ; return ( int ) priority1 - ( int ) priority2 ;


<s> else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && mode == SFmode ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P ( mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ;


<s> MachineBasicBlock & NewMBB = * MF . CreateMachineBasicBlock ( ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( & MBB ) ) , & NewMBB ) ; NewMBB . splice ( NewMBB . end ( ) , & MBB , SplitI . getIterator ( ) , MBB . end ( ) ) ; for ( auto SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) if ( IsEdgeSplit || * SI != & UnsplitSucc ) NewMBB . copySuccessor ( & MBB , SI ) ; if ( ! IsEdgeSplit ) NewMBB . normalizeSuccProbs ( ) ; for ( MachineBasicBlock * Succ : NewMBB . successors ( ) ) if ( Succ != & UnsplitSucc ) MBB . replaceSuccessor ( Succ , & NewMBB ) ; assert ( MBB . isSuccessor ( & NewMBB ) && <STR_LIT> ) ; for ( MachineBasicBlock * Succ : NewMBB . successors ( ) ) { for ( MachineInstr & MI : * Succ ) { if ( ! MI . isPHI ( ) ) break ; for ( int OpIdx = <NUM_LIT> , NumOps = MI . getNumOperands ( ) ; OpIdx < NumOps ; OpIdx += <NUM_LIT> ) { MachineOperand & OpV = MI . getOperand ( OpIdx ) ; MachineOperand & OpMBB = MI . getOperand ( OpIdx + <NUM_LIT> ) ; assert ( OpMBB . isMBB ( ) && <STR_LIT> ) ; if ( OpMBB . getMBB ( ) != & MBB ) continue ; if ( ! IsEdgeSplit || Succ != & UnsplitSucc ) { OpMBB . setMBB ( & NewMBB ) ; continue ; } MI . addOperand ( MF , OpV ) ; MI . addOperand ( MF , MachineOperand :: CreateMBB ( & NewMBB ) ) ; break ; } }


<s> assert ( Exit && <STR_LIT> ) ; if ( ! Latch -> isLayoutSuccessor ( Exit ) ) { return false ; } int OnlyOneExit = <NUM_LIT> ; for ( auto B : L -> getBlocks ( ) ) { if ( L -> isLoopExiting ( B ) ) OnlyOneExit ++ ; if ( OnlyOneExit > <NUM_LIT> ) return false ;


<s> MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisDestReg ) . addReg ( StartDestReg ) . addMBB ( StartMBB ) . addReg ( NextDestReg ) . addMBB ( NextMBB ) ; if ( ! HaveSingleBase ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisSrcReg ) . addReg ( StartSrcReg ) . addMBB ( StartMBB ) . addReg ( NextSrcReg ) . addMBB ( NextMBB ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ThisCountReg ) . addReg ( StartCountReg ) . addMBB ( StartMBB ) . addReg ( NextCountReg ) . addMBB ( NextMBB ) ; if ( Opcode == <STR_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( ThisDestReg ) . addImm ( DestDisp + <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( ThisDestReg ) . addImm ( DestDisp ) . addImm ( <NUM_LIT> ) . addReg ( ThisSrcReg ) . addImm ( SrcDisp ) ; if ( EndMBB ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; MBB -> addSuccessor ( NextMBB ) ; } MBB = NextMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextDestReg ) . addReg ( ThisDestReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; if ( ! HaveSingleBase ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextSrcReg ) . addReg ( ThisSrcReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NextCountReg ) . addReg ( ThisCountReg ) . addImm ( - <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NextCountReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; DestBase = MachineOperand :: CreateReg ( NextDestReg , false ) ; SrcBase = MachineOperand :: CreateReg ( NextSrcReg , false ) ; Length &= <NUM_LIT> ;

if ( EndMBB && ! Length ) DoneMBB -> addLiveIn ( <STR_LIT> ) ;


<s> static unsigned createLaneMaskReg ( MachineFunction & MF ) {

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


<s> if ( MI . getNumOperands ( ) != <NUM_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; const TargetRegisterClass * RC = TII -> getOpRegClass ( MI , <NUM_LIT> ) ; unsigned Size = TRI -> getRegSizeInBits ( * RC ) ; Result . Named . LGKM = Size > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } else { Result . Named . LGKM = <NUM_LIT> ; } } else {


<s> bool isDSOffset0 ( ) const { assert ( isImm ( ) ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( Prev . getOpcode ( ) ) , Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addOperand ( Prev . getOperand ( <NUM_LIT> ) ) ; MBB . insert ( ( MachineBasicBlock :: iterator ) & Root , MIB ) ; if ( MRI . hasOneNonDBGUse ( Prev . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) {


<s> if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( <STR_LIT> ) , GlobalBaseReg ) ; SparcFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ;


<s> if ( VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> && NumElts % <NUM_LIT> == <NUM_LIT> ) { EltVT = <STR_LIT> ; NumElts /= <NUM_LIT> ; } for ( unsigned j = <NUM_LIT> ; j != NumElts ; ++ j ) {


<s> SDValue Callee = DAG . getTargetExternalFunctionSymbol ( <STR_LIT> , <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getWindowsStackProbePreservedMask ( ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( DAG . getMachineFunction ( ) , & Mask ) ; Size = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Size , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;

Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Size , SDValue ( ) ) ;


<s> addPass ( create<ISA_LIT>SEISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ;


<s> unsigned i = <NUM_LIT> ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned ElmIdx = <NUM_LIT> ; for ( ; i < STy -> getNumElements ( ) ; i ++ ) { ElmIdx = i ; unsigned ElmOffset = SL -> getElementOffset ( i ) ; if ( ElmOffset >= Offset ) { ElmIdx = ElmOffset > Offset ? i - <NUM_LIT> : i ; break ; } } unsigned ElmSz = DL . getTypeSizeInBits ( STy -> getTypeAtIndex ( ElmIdx ) ) / <NUM_LIT> ; if ( SL -> hasPadding ( ) && ( Offset - SL -> getElementOffset ( ElmIdx ) ) > ElmSz ) { unsigned Alignment = SL -> getAlignment ( ) ; PadOffset = Alignment - ( ( Offset - SL -> getElementOffset ( ElmIdx ) ) ) ; } return ElmIdx ;


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) {


<s> static rtx c4x_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , AR0_REGNO ) ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> , j = l + NumLaneElts / <NUM_LIT> ; i != NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ l + i ] ;

int BitI1 = Mask [ l + i + <NUM_LIT> ] ;


<s> if ( Segment . getReg ( ) ) { printOperand ( P , MI , Op + <STR_LIT> , O , Modifier ) ; O << ':' ; } printLeaMemReference ( P , MI , Op , O , Modifier ) ;


<s> bool isMem ( ) const { return Kind == k_Mem ;


<s> unsigned Register = ( Insn >> <NUM_LIT> ) & <NUM_LIT> ;

Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Register ] ) ) ;


<s> Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , MaskVT . getSizeInBits ( ) / <NUM_LIT> ) ; return true ; } } if ( AllowFloatDomain && EltSizeInBits == <NUM_LIT> && ( ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( isRepeatedTargetShuffleMask ( <NUM_LIT> , MaskVT , Mask , RepeatedMask ) ) { auto MatchHalf = [ & ] ( unsigned Offset , int & S0 , int & S1 ) { int M0 = RepeatedMask [ Offset ] ; int M1 = RepeatedMask [ Offset + <NUM_LIT> ] ; if ( isUndefInRange ( RepeatedMask , Offset , <NUM_LIT> ) ) { return DAG . getUNDEF ( MaskVT ) ; } else if ( isUndefOrZeroInRange ( RepeatedMask , Offset , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : <NUM_LIT> ) ; return getZeroVector ( MaskVT , Subtarget , DAG , DL ) ; } else if ( isUndefOrInRange ( M0 , <NUM_LIT> , <NUM_LIT> ) && isUndefOrInRange ( M1 , <NUM_LIT> , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : M0 & <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : M1 & <NUM_LIT> ) ; return V1 ; } else if ( isUndefOrInRange ( M0 , <NUM_LIT> , <NUM_LIT> ) && isUndefOrInRange ( M1 , <NUM_LIT> , <NUM_LIT> ) ) { S0 = ( SM_SentinelUndef == M0 ? - <NUM_LIT> : M0 & <NUM_LIT> ) ; S1 = ( SM_SentinelUndef == M1 ? - <NUM_LIT> : M1 & <NUM_LIT> ) ; return V2 ; } return SDValue ( ) ; } ; int ShufMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ;

SDValue Lo = MatchHalf ( <NUM_LIT> , ShufMask [ <NUM_LIT> ] , ShufMask [ <NUM_LIT> ] ) ;


<s> return <STR_LIT> + R ( reg ) + Dsm ( step ) + <STR_LIT> ;


return SelectMUBUFAddr64 ( Addr , SRsrc , VAddr , SOffset , Offset , GLC , SLC , TFE , DLC , SWZ ) ;


<s> SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; ++ Position ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) || ! ( N -> getMachineOpcode ( ) == <STR_LIT> ) ) continue ; SDValue F64Val = N -> getOperand ( <NUM_LIT> ) ; if ( F64Val . isMachineOpcode ( ) && F64Val . getMachineOpcode ( ) == <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( F64Val -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue From [ ] = { SDValue ( N , <NUM_LIT> ) , SDValue ( N , <NUM_LIT> ) } ; SDValue To [ ] = { F64Val . getOperand ( <NUM_LIT> ) , F64Val . getOperand ( <NUM_LIT> ) } ; CurDAG -> ReplaceAllUsesOfValuesWith ( From , To , <NUM_LIT> ) ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode5FP16 ( SDValue N , SDValue & Base , SDValue & Offset ) { int Lwb = - <NUM_LIT> + <NUM_LIT> ; int Upb = <NUM_LIT> ;

return IsAddressingMode5 ( N , Base , Offset , Lwb , Upb , true ) ;


<s> } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = isStackAligned ? <STR_LIT> : <STR_LIT> ;


<s> MVT LegalVT = ( TLI . getTypeToTransformTo ( * DAG . getContext ( ) , EltVT ) ) . getSimpleVT ( ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , LegalVT , In , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Res ) ; }

assert ( ( In . getSimpleValueType ( ) . is256BitVector ( ) || In . getSimpleValueType ( ) . is512BitVector ( ) ) && <STR_LIT> ) ;


<s> unsigned getCheriReg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_Cheri ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ;

assert ( RegIdx . RealRegister == <STR_LIT> || ( RegIdx . RealRegister >= <STR_LIT> && RegIdx . RealRegister <= <STR_LIT> ) ) ;


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t Value = CE -> getValue ( ) ; if ( RegWidth == <NUM_LIT> ) { Value &= <NUM_LIT> ; } bool Valid = isValidImm ( RegWidth , Value , UImm16 , Shift ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , STI ) ;


<s> switch ( MI -> getOpcode ( ) ) { case AMDGPU :: PRED_X : return AluPredX ; case AMDGPU :: INTERP_PAIR_XY : case AMDGPU :: INTERP_PAIR_ZW : case AMDGPU :: INTERP_VEC_LOAD : case AMDGPU :: DOT_4 : return AluT_XYZW ; case AMDGPU :: COPY : if ( MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) { return AluDiscarded ; } default : break ; } if ( TII -> isVector ( * MI ) || TII -> isCubeOp ( MI -> getOpcode ( ) ) || TII -> isReductionOp ( MI -> getOpcode ( ) ) || MI -> getOpcode ( ) == AMDGPU :: GROUP_BARRIER ) { return AluT_XYZW ; } if ( TII -> isLD<ISA_LIT>nstr ( MI -> getOpcode ( ) ) ) { return AluT_X ; } unsigned DestSubReg = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; switch ( DestSubReg ) { case AMDGPU :: sub0 : return AluT_X ; case AMDGPU :: sub1 : return AluT_Y ; case AMDGPU :: sub2 : return AluT_Z ; case AMDGPU :: sub3 : return AluT_W ; default : break ; } unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( regBelongsToClass ( DestReg , & AMDGPU :: R600_TReg32_XRegClass ) || regBelongsToClass ( DestReg , & AMDGPU :: R600_AddrRegClass ) ) return AluT_X ;


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; COMMDirectiveTakesAlignment = true ;


<s> <ISA_LIT>TTIImpl ( <ISA_LIT>TTIImpl && Arg ) : BaseT ( std :: move ( static_cast < BaseT & > ( Arg ) ) ) , TM ( std :: move ( Arg . TM ) ) , ST ( std :: move ( Arg . ST ) ) , TLI ( std :: move ( Arg . TLI ) ) {


<s> SelectMUBUF ( Addr , Ptr , VAddr , SOffset , Offset , Offen , Idxen , Addr64 , GLC , SLC , TFE ) ; ConstantSDNode * C = cast < ConstantSDNode > ( Addr64 ) ; if ( C -> getSExtValue ( ) ) {


<s> gcc_assert ( block -> preds -> length ( ) == <NUM_LIT> ) ;

basic_block pre_block = ( * block -> preds ) [ <NUM_LIT> ] -> src ;


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;

if ( Op1 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> bool arm_vector_mode_supported_p ( enum machine_mode mode ) { if ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) return true ;


<s> if ( GET_CODE ( op ) != MEM ) return FALSE ; addr = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == MEM ) addr = XEXP ( addr , <NUM_LIT> ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : case POST_INC : case PRE_MODIFY : case POST_MODIFY : return REGNO ( XEXP ( addr , <NUM_LIT> ) ) == ( unsigned ) regno ; default : return FALSE ; }


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ;

CriticalPathRCs . push_back ( has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ;


<s> <ISA_LIT>PrologEpilogPass ( ) : MachineFunctionPass ( ID ) {


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool NoExecStack ) { if ( Triple ( TT ) . isOSDarwin ( ) ) return createMachOStreamer ( Ctx , MAB , OS , Emitter , RelaxAll ) ; return createELFStreamer ( Ctx , MAB , OS , Emitter , RelaxAll , NoExecStack ) ;


<s> AM . GV = GV ; AM . GVOpFlags = STI . classifyGlobalReference ( GV ) ; if ( isGlobalStubReference ( AM . GVOpFlags ) ) return false ; if ( isGlobalRelativeToPICBase ( AM . GVOpFlags ) ) return false ; if ( STI . isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } const Register DefReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( DefReg ) ; unsigned NewOpc = getLeaOP ( Ty , STI ) ; I . setDesc ( TII . get ( NewOpc ) ) ;


<s> HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ( T . getOS ( ) == Triple :: OpenBSD || T . getOS ( ) == Triple :: Bitrig ) && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = nullptr ; UseIntegratedAssembler = true ;


<s> void <ISA_LIT>TargetWasmStreamer :: emitParam ( MCSymbol * Symbol , ArrayRef < MVT > Types ) {


<s> pat = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; pat = arc_unspec_offset ( pat , ARC_UNSPEC_GOT ) ; pat = gen_rtx_SET ( baseptr_rtx , pat ) ; emit_insn ( pat ) ;


<s> if ( TARGET_SIMD && ( mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V2DImode || mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == V2SFmode || mode == V4SFmode || mode == V2DFmode || mode == V4HFmode || mode == V8HFmode || mode == V1DFmode ) ) return true ;


<s> YamlIO . mapOptional ( <STR_LIT> , MFI . HasRedZone ) ;


<s> SmallVector < EVT , <NUM_LIT> > SplitVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , <NUM_LIT> ) ; if ( OrigArg . Ty -> isVoidTy ( ) ) return true ; EVT VT = SplitVTs [ <NUM_LIT> ] ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == <NUM_LIT> ) { SplitArgs . emplace_back ( OrigArg . Reg , VT . getTypeForEVT ( Context ) , OrigArg . Flags , OrigArg . IsFixed ) ; return true ; }

SmallVector < unsigned , <NUM_LIT> > SplitRegs ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ;


<s> const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( <ISA_LIT> :: fixup_MICROMIPS_PC16_S1 ) ) ) ; return <NUM_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeRI5S1 ( SDValue N , SDValue & Base , SDValue & Offset ) {

return SelectThumbAddrModeRI ( N , Base , Offset , <NUM_LIT> ) ;


<s> MachineInstr & MI = * MII ; if ( MI . getOpcode ( ) != <STR_LIT> ) { if ( TII -> get ( MI . getOpcode ( ) ) . TSFlags & <STR_LIT> ) { unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: def_instr_iterator It = MRI -> def_instr_begin ( Reg ) , E = MRI -> def_instr_end ( ) ; It != E ; ++ It ) { RemoveMI ( & ( * It ) ) ; } } continue ; } RegSeqInfo R<ISA_LIT> ( * MRI , & MI ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( ! areAllUsesSwizzeable ( Reg ) ) continue ;


<s> if ( MI . isBundle ( ) ) BundleIt = I ; if ( ! MI . isInsideBundle ( ) ) continue ; bool InsertBeforeBundle ; if ( MI . isInlineAsm ( ) ) InsertBeforeBundle = ! hasWriteToReadDep ( MI , * BundleIt , HRI ) ; else if ( MI . isDebugValue ( ) ) InsertBeforeBundle = true ;


<s> MCELFStreamer :: EmitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = <NUM_LIT> ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; RegInfoRecord -> SetPhysRegUsed ( Reg , MCRegInfo ) ; } createPendingLabelRelocs ( ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Start = Parser . getTok ( ) . getLoc ( ) , End ; unsigned SegReg = <NUM_LIT> ; unsigned Size = getIntelMemOperandSize ( Tok . getString ( ) ) ; if ( Size ) { Parser . Lex ( ) ; assert ( Tok . getString ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) { DAG . getContext ( ) -> emitError ( <STR_LIT> ) ; return SDValue ( ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned RA = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ;

MFI . setReturnAddressIsTaken ( true ) ;


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { EVT OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT == <STR_LIT> || OpVT == <STR_LIT> ) return Subtarget -> hasVLX ( ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static const struct mips_cpu_info * mips_default_arch ( void ) { unsigned int i ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mips_cpu_info_table ) ; i ++ ) if ( strcmp ( mips_cpu_info_table [ i ] . name , MIPS_CPU_STRING_DEFAULT ) == <NUM_LIT> ) return mips_cpu_info_table + i ;


<s> if ( Split . getNode ( ) ) return Split ; if ( Subtarget -> supportsAddressTopByteIgnored ( ) && performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue ( ) ;


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;

return IsConstantImm && isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> return LRs . at ( a ) . hasNextUseBefore ( pos , LRs . at ( b ) ) ; } ) ;


<s> void setCalleeSavedFrameSize ( unsigned bytes ) { CalleeSavedFrameSize = bytes ;


<s> FrameID = MachineOutlinerTailCall ; NumInstrsForCall = <NUM_LIT> ; NumInstrsToCreateFrame = <NUM_LIT> ; } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , DoesntNeedLRSave ) ) { CallID = MachineOutlinerNoLRSave ; FrameID = MachineOutlinerNoLRSave ; NumInstrsForCall = <NUM_LIT> ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> void makeReady ( ready_set & ready , ablock * block ) { ready_block rb ; rb . block = block ; if ( PML && block -> MBB ) { rb . criticality = PML -> getCriticality ( Criticalities , * block -> MBB ) ; } else if ( PML ) { double maxCrit = <NUM_LIT> ; for ( ablocks :: iterator i = block -> SCC . begin ( ) , ie = block -> SCC . end ( ) ; i != ie ; i ++ ) { if ( ! ( * i ) -> MBB ) continue ; maxCrit = std :: max ( maxCrit , PML -> getCriticality ( Criticalities , * ( * i ) -> MBB ) ) ; } rb . criticality = maxCrit ; } else { rb . criticality = <NUM_LIT> ;


<s> static int xstormy16_address_cost ( rtx x , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) {

return ( CONST_INT_P ( x ) ? <NUM_LIT> : GET_CODE ( x ) == PLUS ? <NUM_LIT> : <NUM_LIT> ) ;


<s> case Instruction :: GetElementPtr : return Builder . CreateGEP ( cast < GEPOperator > ( C ) -> getSourceElementType ( ) , NewOperands [ <NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) , <STR_LIT> , cast < GEPOperator > ( C ) -> isInBounds ( ) ) ; case Instruction :: Select : return Builder . CreateSelect ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; default : if ( Instruction :: isBinaryOp ( Opcode ) ) { return Builder . CreateBinOp ( Instruction :: BinaryOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; } if ( Instruction :: isCast ( Opcode ) ) { return Builder . CreateCast ( Instruction :: CastOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , C -> getType ( ) ) ;


<s> int sz ; sz = op -> getNumOperands ( ) ;

out = op -> getOperand ( sz - <NUM_LIT> ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . Scale ) return false ; if ( AM . BaseGV && AM . HasBaseReg ) return false ;

if ( AM . BaseGV ) return AM . BaseOffs == <NUM_LIT> ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasSIMD128 ( false ) , HasAtomics ( false ) , HasNontrappingFPToInt ( false ) , HasSignExt ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) {


<s> switch ( TexHandleDef . getOpcode ( ) ) { case <STR_LIT> : { const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; if ( TM . getDrvInterface ( ) == <STR_LIT> ) { return false ; } assert ( TexHandleDef . getOperand ( <NUM_LIT> ) . isSymbol ( ) && <STR_LIT> ) ; StringRef Sym = TexHandleDef . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; std :: string ParamBaseName = MF . getName ( ) ; ParamBaseName += <STR_LIT> ; assert ( Sym . startswith ( ParamBaseName ) && <STR_LIT> ) ;

unsigned Param = atoi ( Sym . data ( ) + ParamBaseName . size ( ) ) ;


<s> if ( * group_end ) can_issue_more = <NUM_LIT> ; if ( can_issue_more && ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; if ( rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 ) { nop = gen_group_ending_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more = <NUM_LIT> ; } else while ( can_issue_more > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more -- ; } * group_end = true ; return <NUM_LIT> ; } if ( rs6000_sched_insert_nops < sched_finish_regroup_exact ) { int n_nops = rs6000_sched_insert_nops ; if ( can_issue_more == <NUM_LIT> ) can_issue_more = issue_rate ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } while ( n_nops > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; if ( can_issue_more == issue_rate - <NUM_LIT> ) end = false ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } n_nops -- ; } can_issue_more ++ ; * group_end = ( end || ( can_issue_more == <NUM_LIT> && ! is_branch_slot_insn ( next_insn ) ) || ( can_issue_more <= <NUM_LIT> && is_cracked_insn ( next_insn ) ) || ( can_issue_more < issue_rate && insn_terminates_group_p ( next_insn , previous_group ) ) ) ; if ( * group_end && end ) ( * group_count ) -- ;

if ( sched_verbose > <NUM_LIT> ) fprintf ( dump , <STR_LIT> , * group_count , can_issue_more ) ;


<s> bool isSigned = N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = N -> getOperand ( i ) . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * Context ) ; Entry . Node = N -> getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } return Args ;


<s> static bool v850_reg_ok_for_base_p ( const_rtx reg , bool strict_p ) { if ( strict_p ) { return REGNO_OK_FOR_BASE_P ( REGNO ( reg ) ) ; } else { return true ;


<s> if ( combineCCMask ( CCReg , CCValidVal , CCMaskVal ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( CCValidVal , SDLoc ( N ) , <STR_LIT> ) , DAG . getTargetConstant ( CCMaskVal , SDLoc ( N ) , <STR_LIT> ) , CCReg ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; maxStoresPerMemset = maxStoresPerMemsetOptSize = <NUM_LIT> ; maxStoresPerMemmove = maxStoresPerMemmoveOptSize = maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = <NUM_LIT> ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ;


<s> <ISA_LIT>ELFObjectWriter ( Triple :: OSType OSType ) : MCELFObjectTargetWriter ( false , OSType , ELF :: EM_MBLAZE , true ) {


<s> if ( TM . getMCAsmInfo ( ) -> getExceptionHandlingType ( ) != ExceptionHandling :: <ISA_LIT> ) return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , TM , MMI , Streamer ) ; assert ( Encoding == DW_EH_PE_absptr && <STR_LIT> ) ;

return MCSymbolRefExpr :: create ( TM . getSymbol ( GV ) , MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 , getContext ( ) ) ;


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> SDLoc dl ( Op ) ; const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> pat = GEN_FCN ( icode ) ( target , op0 , addr_helper , target ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( <NUM_LIT> ) ) ; emit_move_insn ( target , op1 ) ;


<s> void setRoadEnd ( unsigned roadEnd ) {


<s> ~ <ISA_LIT>AddressSanitizer32 ( ) override {


<s> RegisterTargetMachine < <ISA_LIT>64TargetMachine > B ( getThe<ISA_LIT>64Target ( ) ) ;

RegisterTargetMachine < <ISA_LIT>64TargetMachine > C ( getThe<ISA_LIT>64LETarget ( ) ) ;


<s> if ( ! must_link ( ) && ( cfun -> machine -> callee_saved_reg_size == <NUM_LIT> ) ) { insn = emit_insn ( gen_link ( gen_rtx_REG ( Pmode , FT32_R13 ) , GEN_INT ( - cfun -> machine -> size_for_adjusting_sp ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; return ; } if ( optimize_size ) { for ( regno = FIRST_PSEUDO_REGISTER ; regno -- > <NUM_LIT> ; ) { if ( ! fixed_regs [ regno ] && ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) { rtx preg = gen_rtx_REG ( Pmode , regno ) ; emit_insn ( gen_call_prolog ( preg ) ) ; break ; } } } else { for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( ! fixed_regs [ regno ] && df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) { insn = emit_insn ( gen_movsi_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } } if ( cfun -> machine -> size_for_adjusting_sp >= <NUM_LIT> ) { error ( <STR_LIT> ) ; return ; } if ( must_link ( ) ) { insn = emit_insn ( gen_link ( gen_rtx_REG ( Pmode , FT32_FP ) , GEN_INT ( - cfun -> machine -> size_for_adjusting_sp ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else if ( cfun -> machine -> size_for_adjusting_sp > <NUM_LIT> ) {

int adj = cfun -> machine -> size_for_adjusting_sp ;


<s> if ( VT . isVector ( ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ;


<s> BlockPosition ( unsigned InitialLogAlignment ) : KnownBits ( InitialLogAlignment ) {


<s> void EmitARM64WinCFIAddFP ( unsigned Size ) override { OS << <STR_LIT> << Size << <STR_LIT> ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII ) ;


<s> const auto & Modifier = std :: find_if ( std :: begin ( ModifierNames ) , std :: end ( ModifierNames ) , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> Spelling ;


<s> return TM -> getSubtarget < <ISA_LIT>GenSubtargetInfo > ( ) . createDFAPacketizer ( II ) ;


<s> bool Valid ; StringRef Name ( SysReg . Data , SysReg . Length ) ;

uint32_t Bits = <STR_LIT> ( ) . fromString ( Name , Valid ) ;


<s> inline bool IsSampler ( const Type * T ) { return GetOpaqueType ( T ) == Sampler ;


<s> return gen_rtx_REG ( mode , NDS32_GPR_RET_FIRST_REGNUM ) ;


<s> HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasSGX = false ; HasPRFCHW = false ; HasRDSEED = false ; HasSMAP = false ;


<s> MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } unsigned FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = <STR_LIT> ; else { const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>16InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false , false , IsKill ) ; MI . getOperand ( OpNo + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; } } if ( ! TARGET_SVE ) for ( i = P0_REGNUM ; i <= P15_REGNUM ; i ++ ) { fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; }


<s> <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this ) , JITInfo ( * this ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> case TargetOpcode :: G_MEMCPY : case TargetOpcode :: G_MEMMOVE : case TargetOpcode :: G_MEMSET : { unsigned MaxLen = <NUM_LIT> ; if ( Helper . tryCombineMemCpyFamily ( MI , MaxLen ) ) return true ; if ( Opc == TargetOpcode :: G_MEMSET ) return llvm :: <ISA_LIT>GISelUtils :: tryEmitBZero ( MI , B , EnableMinSize ) ;


return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> int getRestoreBasePointerOffset ( ) const {


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_ShiftedImmediate ) ; Op -> RegShiftedImm . ShiftTy = ShTy ; Op -> RegShiftedImm . SrcReg = SrcReg ;

Op -> RegShiftedImm . ShiftImm = ShiftImm ;


<s> SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue MaskInReg = DAG . getConstant ( ~ <NUM_LIT> , MaskVT ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ;

SDValue Ops [ ] = { Base , Scale , Index , Disp , Segment , MaskInReg , Src , Chain } ;


<s> switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> Type * I8 = Type :: getInt8Ty ( Ctx ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { Type :: getInt8PtrTy ( Ctx ) , I8 , Arg . getType ( ) } , false ) ; Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( GetArgumentSymbolName ( Arg ) , FnType ) ; Value * ArgName = CreateStringPtr ( BB , Arg . getName ( ) ) ; Value * Args [ ] = { ArgName , ConstantInt :: get ( I8 , Arg . getArgNo ( ) ) , & Arg } ; CallInst :: Create ( Fn , Args , <STR_LIT> , & BB ) ;


<s> inline bool isPromotedToDotNew ( ) const { return PromotedToDotNew ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0_X , <STR_LIT> :: src0_sel_X } , { <STR_LIT> :: src0_Y , <STR_LIT> :: src0_sel_Y } , { <STR_LIT> :: src0_Z , <STR_LIT> :: src0_sel_Z } , { <STR_LIT> :: src0_W , <STR_LIT> :: src0_sel_W } , { <STR_LIT> :: src1_X , <STR_LIT> :: src1_sel_X } , { <STR_LIT> :: src1_Y , <STR_LIT> :: src1_sel_Y } , { <STR_LIT> :: src1_Z , <STR_LIT> :: src1_sel_Z } , { <STR_LIT> :: src1_W , <STR_LIT> :: src1_sel_W } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { MachineOperand & MO = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; unsigned Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } } return Result ; } static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0 , <STR_LIT> :: src0_sel } , { <STR_LIT> :: src1 , <STR_LIT> :: src1_sel } , { <STR_LIT> :: src2 , <STR_LIT> :: src2_sel } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { int SrcIdx = getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ; if ( SrcIdx < <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( SrcIdx ) ; unsigned Reg = MO . getReg ( ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , <STR_LIT> ) , DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , <STR_LIT> | MO_NC ) , DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , <STR_LIT> | MO_NC ) , DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , <STR_LIT> | MO_NC ) ) ; } else { SDValue Hi = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , <STR_LIT> ) ; SDValue Lo = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , <STR_LIT> | <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , Lo ) ;


<s> if ( GET_CODE ( operands [ i ] ) == MEM && ( t == 'b' || t == 't' ) ) { rtx sym , n , r ; int u ; sym = XEXP ( operands [ i ] , <NUM_LIT> ) ; if ( GET_CODE ( sym ) == CONST && GET_CODE ( XEXP ( sym , <NUM_LIT> ) ) == UNSPEC ) sym = XVECEXP ( XEXP ( sym , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; if ( t == 'b' ) { r = mep_tp_rtx ( ) ; u = UNS_TPREL ; } else { r = mep_gp_rtx ( ) ; u = UNS_GPREL ; } n = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , sym ) , u ) ; n = gen_rtx_CONST ( Pmode , n ) ; n = gen_rtx_PLUS ( Pmode , r , n ) ; operands [ i ] = replace_equiv_address ( operands [ i ] , n ) ; } } } if ( ( GET_CODE ( operands [ <NUM_LIT> ] ) != REG && MEP_CONTROL_REG ( operands [ <NUM_LIT> ] ) ) || ( GET_CODE ( operands [ <NUM_LIT> ] ) != REG && MEP_CONTROL_REG ( operands [ <NUM_LIT> ] ) ) ) { rtx temp ; fprintf ( stderr , <STR_LIT> ) ; temp = gen_reg_rtx ( mode ) ; emit_move_insn ( temp , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = temp ; } if ( symbolref_p ( operands [ <NUM_LIT> ] ) && ( mep_section_tag ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == 'f' || ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) ) ) { rtx temp ; gcc_assert ( ! reload_in_progress && ! reload_completed ) ; temp = force_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; operands [ <NUM_LIT> ] = replace_equiv_address ( operands [ <NUM_LIT> ] , temp ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; } if ( ! post_reload && ( tag [ <NUM_LIT> ] == 't' || tag [ <NUM_LIT> ] == 'b' ) ) tag [ <NUM_LIT> ] = <NUM_LIT> ; if ( symbol_p ( operands [ <NUM_LIT> ] ) && ( tag [ <NUM_LIT> ] == 'f' || tag [ <NUM_LIT> ] == 't' || tag [ <NUM_LIT> ] == 'b' ) ) { emit_insn ( gen_movsi_topsym_s ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_movsi_botsym_s ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return true ;


<s> return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) , false , false ) ;


<s> void <ISA_LIT>InstPrinter :: printThumbS4ImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( MI -> getOperand ( OpNum ) . getImm ( ) * <NUM_LIT> ) << markup ( <STR_LIT> ) ;


<s> for ( MachineInstr & BBI : MBB . instrs ( ) ) { unsigned Opc = BBI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { Register Acc = BBI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Acc ) && <STR_LIT> ) ; Candidates [ Acc - <STR_LIT> ] = & BBI ; } else if ( Opc == <STR_LIT> ) { Register Acc = BBI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> . contains ( Acc ) && <STR_LIT> ) ; if ( ! Candidates [ Acc - <STR_LIT> ] ) continue ; InstrsToErase . insert ( & BBI ) ; InstrsToErase . insert ( Candidates [ Acc - <STR_LIT> ] ) ; } else { for ( MachineOperand & Operand : BBI . operands ( ) ) { if ( ! Operand . isReg ( ) ) continue ; Register Reg = Operand . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) Candidates [ Reg - <STR_LIT> ] = nullptr ; } } }

for ( MachineInstr * MI : InstrsToErase ) MI -> eraseFromParent ( ) ;


<s> } SDValue C , D ; SmallVector < int , <NUM_LIT> > RMask ( NumElts ) ; if ( RHS . getOpcode ( ) == <STR_LIT> ) { if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) C = RHS . getOperand ( <NUM_LIT> ) ; if ( RHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) D = RHS . getOperand ( <NUM_LIT> ) ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( RHS . getNode ( ) ) -> getMask ( ) ; std :: copy ( Mask . begin ( ) , Mask . end ( ) , RMask . begin ( ) ) ; } else { if ( RHS . getOpcode ( ) != <STR_LIT> ) C = RHS ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) RMask [ i ] = i ; } if ( ! ( A == C && B == D ) && ! ( A == D && B == C ) ) return false ; if ( ! A . getNode ( ) && ! B . getNode ( ) ) return false ; if ( A != C ) CommuteVectorShuffleMask ( RMask , NumElts ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int LIdx = LMask [ i ] , RIdx = RMask [ i ] ; if ( LIdx < <NUM_LIT> || RIdx < <NUM_LIT> || ( ! A . getNode ( ) && ( LIdx < ( int ) NumElts || RIdx < ( int ) NumElts ) ) || ( ! B . getNode ( ) && ( LIdx >= ( int ) NumElts || RIdx >= ( int ) NumElts ) ) ) continue ; unsigned Src = ( i / HalfLaneElts ) % <NUM_LIT> ; unsigned LaneStart = ( i / NumLaneElts ) * NumLaneElts ; int Index = <NUM_LIT> * ( i % HalfLaneElts ) + NumElts * Src + LaneStart ; if ( ! ( LIdx == Index && RIdx == Index + <NUM_LIT> ) && ! ( IsCommutative && LIdx == Index + <NUM_LIT> && RIdx == Index ) ) return false ; } LHS = A . getNode ( ) ? A : B ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( class AsmPrinter & asmprinter ) : Printer ( asmprinter ) {


<s> void <ISA_LIT>InstPrinter :: printAM2PreOrOffsetIndexOp ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ;


<s> bool hasSRAMECC ( const MCSubtargetInfo & STI ) {

return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> void <ISA_LIT>TargetStreamer :: switchVendor ( StringRef Vendor ) {


<s> if ( Ops . size ( ) != <NUM_LIT> ) return ; unsigned UniqueOpndIdx ; if ( Ops [ <NUM_LIT> ] . isIdenticalTo ( Ops [ <NUM_LIT> ] ) ) UniqueOpndIdx = <NUM_LIT> ; else if ( Ops [ <NUM_LIT> ] . isIdenticalTo ( Ops [ <NUM_LIT> ] ) ) UniqueOpndIdx = <NUM_LIT> ; else if ( Ops [ <NUM_LIT> ] . isIdenticalTo ( Ops [ <NUM_LIT> ] ) ) UniqueOpndIdx = <NUM_LIT> ; else return ; Register Reg = MI . getOperand ( OpToReplace ) . getReg ( ) ; MI . removeOperand ( OpToReplace ) ; MI . addOperand ( Ops [ UniqueOpndIdx ] ) ;

if ( MRI -> use_empty ( Reg ) ) MRI -> getUniqueVRegDef ( Reg ) -> eraseFromParent ( ) ;


<s> std :: shared_ptr < msgpack :: ArrayNode > MetadataStreamerV3 :: getWorkGroupDimensions ( MDNode * Node ) const { auto Dims = std :: make_shared < msgpack :: ArrayNode > ( ) ;

if ( Node -> getNumOperands ( ) != <NUM_LIT> ) return Dims ;


<s> else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! ( TARGET_SSE && TARGET_SSE_MATH ) ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; } return ( type == EXCESS_PRECISION_TYPE_STANDARD ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT : FLT_EVAL_METHOD_UNPREDICTABLE ) ;


<s> static bool isFunctionGlobalAddress ( SDValue Callee ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> ) return false ;

return G -> getGlobal ( ) -> getValueType ( ) -> isFunctionTy ( ) ;


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , const MCSubtargetInfo & STI , raw_ostream & O , const char * Modifier ) { printOperand ( MI , opNum , STI , O ) ; if ( Modifier && ! strcmp ( Modifier , <STR_LIT> ) ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , STI , O ) ; return ; } const MCOperand & MO = MI -> getOperand ( opNum + <NUM_LIT> ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) return ; if ( MO . isImm ( ) && MO . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ;


<s> return ( wi :: ltu_p ( iterations_max , <NUM_LIT> ) ) ;


<s> if ( ! IsPCREL ) { InReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; OrigRegs . push_back ( InReg ) ; } DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Opc1 , Opc2 ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : assert ( IsPCREL && <STR_LIT> ) ; Opc1 = <STR_LIT> ; Opc2 = MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi ; if ( IsPCREL ) { Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addImm ( <NUM_LIT> ) ; } else {

assert ( InReg != <STR_LIT> && <STR_LIT> ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> bool shouldBuildLookupTablesForConstant ( Constant * C ) const {

if ( ST -> isROPI ( ) || ST -> isRWPI ( ) ) return ! C -> needsDynamicRelocation ( ) ;


<s> bool Changed = false ; const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; auto * EHInfo = MF . getWasmEHFuncInfo ( ) ; for ( auto & MBB : MF ) { auto Pos = MBB . getFirstTerminator ( ) ; if ( Pos == MBB . end ( ) ) continue ; MachineInstr * TI = & * Pos ; switch ( TI -> getOpcode ( ) ) { case <STR_LIT> : { MachineBasicBlock * TBB = TI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! MBB . isLayoutSuccessor ( TBB ) ) BuildMI ( MBB , TI , TI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( TBB ) ; TI -> eraseFromParent ( ) ; Changed = true ; break ; } case <STR_LIT> : { if ( EHInfo -> hasThrowUnwindDest ( & MBB ) ) BuildMI ( MBB , TI , TI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( EHInfo -> getThrowUnwindDest ( & MBB ) ) ; else BuildMI ( MBB , TI , TI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; TI -> eraseFromParent ( ) ; Changed = true ; break ;


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) { if ( is64Bit ) MAI = new <ISA_LIT>_64MCAsmInfoDarwin ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . isOSBinFormatELF ( ) ) { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } else if ( TheTriple . isWindowsMSVCEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . isOSCygMing ( ) ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; unsigned StackPtr = is64Bit ? <STR_LIT> : <STR_LIT> ;

MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( StackPtr , true ) , - stackGrowth ) ;


<s> bool isVSSRCRegister ( unsigned Register ) const {

return MRI . getRegClass ( Register ) -> getID ( ) == <STR_LIT> ;


<s> halfthree = rs6000_load_constant_and_splat ( mode , dconst3_2 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , src ) , UNSPEC_RSQRT ) ) ) ; rs6000_emit_msub ( y , src , halfthree , src ) ; for ( i = <NUM_LIT> ; i < passes ; i ++ ) { rtx x1 = gen_reg_rtx ( mode ) ; rtx u = gen_reg_rtx ( mode ) ; rtx v = gen_reg_rtx ( mode ) ; emit_insn ( gen_mul ( u , x0 , x0 ) ) ; rs6000_emit_nmsub ( v , y , u , halfthree ) ;


<s> res = parseSDWASel ( Operands , Op . Name , Op . Type ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTySdwaDstUnused ) { res = parseSDWADstUnused ( Operands ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyOpSel || Op . Type == <ISA_LIT>Operand :: ImmTyOpSelHi || Op . Type == <ISA_LIT>Operand :: ImmTyNegLo || Op . Type == <ISA_LIT>Operand :: ImmTyNegHi ) { res = parseOperandArrayWithPrefix ( Op . Name , Operands , Op . Type , Op . ConvertResult ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyDim ) { res = parseDim ( Operands ) ; } else { res = parseIntWithPrefix ( Op . Name , Operands , Op . Type , Op . ConvertResult ) ; } if ( res != MatchOperand_NoMatch ) {


<s> lab = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ;

fun = gen_rtx_SYMBOL_REF ( Pmode , MCOUNT_FUNCTION ) ;


<s> BRIG32_DwarfTargetObjectFile :: ~ BRIG32_DwarfTargetObjectFile ( ) {


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

AU . addRequired < TargetPassConfig > ( ) ;


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; assert ( Carry . getOpcode ( ) != <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;

SDValue <ISA_LIT>cc = DAG . getConstant ( IntCCTo<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) , DL , <STR_LIT> ) ;


<s> const char * getPassName ( ) const override {


<s> rtx last_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT> ) ; if ( last_def_reg == NULL_RTX ) return false ; gcc_assert ( REG_P ( last_def_reg ) || GET_CODE ( last_def_reg ) == SUBREG ) ; return n8_consumed_by_addr_in_p ( consumer , last_def_reg ) ;


<s> unsigned ResultReg ; RV = <ISA_LIT>EmitLoad ( VT , ResultReg , Src ) ; assert ( RV == true && <STR_LIT> ) ; RV = <ISA_LIT>EmitStore ( VT , ResultReg , Dest ) ; assert ( RV == true && <STR_LIT> ) ; ( void ) RV ; unsigned Size = VT . getSizeInBits ( ) / <NUM_LIT> ; Len -= Size ; Dest . Offset += Size ; Src . Offset += Size ;


<s> auto I = MBB . getLastNonDebugInstr ( ) ; if ( I != MBB . end ( ) ) { if ( ( Subtarget -> hardenSlsRet ( ) && isSimpleReturn ( * I ) ) || ( Subtarget -> hardenSlsIJmp ( ) && isIndirectBranchOrTailCall ( * I ) ) ) { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } } } AsmPrinter :: emitBasicBlockEnd ( MBB ) ; SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , X ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , X ) ; if ( VT == <STR_LIT> && X . getValueType ( ) == <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , X ) ; while ( X . getValueType ( ) != VT && X -> getOpcode ( ) == <STR_LIT> ) X = X -> getOperand ( <NUM_LIT> ) ; if ( X . getValueType ( ) == VT ) return X ; }

if ( Op0 -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && N -> getConstantOperandVal ( <NUM_LIT> ) < Op0 . getNumOperands ( ) ) {


<s> assert ( CE && <STR_LIT> ) ; int Imm = CE -> getValue ( ) ; bool isAdd = Imm >= <NUM_LIT> ; if ( Imm == INT32_MIN ) Imm = <NUM_LIT> ; Imm = ( ( Imm < <NUM_LIT> ? - Imm : Imm ) / <NUM_LIT> ) | ( int ) isAdd << <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> return __builtin_aarch64_rsqrtehf ( __a ) ;


<s> int i ; if ( req_mode == VOIDmode ) return false ; if ( GET_CODE ( PATTERN ( insn ) ) == SET ) return s390_match_ccmode_set ( PATTERN ( insn ) , req_mode ) ; if ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL ) for ( i = <NUM_LIT> ; i < XVECLEN ( PATTERN ( insn ) , <NUM_LIT> ) ; i ++ ) { rtx set = XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , i ) ;

if ( GET_CODE ( set ) == SET ) if ( ! s390_match_ccmode_set ( set , req_mode ) ) return false ;


<s> return new ix86_vector_costs ( vinfo , costing_for_scalar ) ;


<s> if ( AM . isDynAlloc ( ) && ! AM . IncludesDynAlloc ) { changeComponent ( AM , IsBase , Value ) ; AM . IncludesDynAlloc = true ; return true ;


<s> static inline int getMClassFlagsMask ( StringRef Flags , bool hasDSP ) {

if ( Flags . empty ( ) ) return <NUM_LIT> | ( int ) hasDSP ;


<s> <ISA_LIT>LatencyResolver ( ) : MachineFunctionPass ( ID ) { MLI = nullptr ; MF = nullptr ; ItinData = nullptr ; TII = nullptr ;


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Size == <NUM_LIT> ) O << <STR_LIT> << formatImm ( ( signed char ) Op . getImm ( ) ) ; else if ( Size == <NUM_LIT> ) O << <STR_LIT> << formatImm ( ( signed short ) Op . getImm ( ) ) ;

else O << <STR_LIT> << formatImm ( Op . getImm ( ) ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isVMOVModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ;

if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ;


<s> else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: Style :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: Style :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: Style :: GOT ) ; CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ;

InstSelector . reset ( create<ISA_LIT>InstructionSelector ( TM , * this , * RBI ) ) ;


<s> size_t <ISA_LIT>64GNULDBackend :: getRelEntrySize ( ) { return <NUM_LIT> ;


<s> int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT> && Value < <NUM_LIT> ;


<s> CUMULATIVE_ARGS xstormy16_function_arg_advance ( CUMULATIVE_ARGS cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { if ( cum < NUM_ARGUMENT_REGISTERS && cum + XSTORMY16_WORD_SIZE ( type , mode ) > NUM_ARGUMENT_REGISTERS ) cum = NUM_ARGUMENT_REGISTERS ;

cum += XSTORMY16_WORD_SIZE ( type , mode ) ;


<s> } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return <STR_LIT> ; if ( is64Bit ( ) ) return <STR_LIT> ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return <STR_LIT> ;


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const {

if ( isPositionIndependent ( ) && Subtarget . isPICStyleGOT ( ) ) return MachineJumpTableInfo :: EK_Custom32 ;


<s> Negative = false ; OffsetRegShifted = false ; OffsetIsReg = false ; OffsetRegNum = - <NUM_LIT> ; const AsmToken & NextTok = Parser . getTok ( ) ; if ( NextTok . is ( AsmToken :: Plus ) ) Parser . Lex ( ) ; else if ( NextTok . is ( AsmToken :: Minus ) ) { Negative = true ; Parser . Lex ( ) ; } const AsmToken & OffsetRegTok = Parser . getTok ( ) ; if ( OffsetRegTok . is ( AsmToken :: Identifier ) ) { OffsetIsReg = ! MaybeParseRegister ( Op , false ) ; if ( OffsetIsReg ) OffsetRegNum = Op . getReg ( ) ; } if ( OffsetRegNum != - <NUM_LIT> ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ParseShift ( ShiftType , ShiftAmount ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_<ISA_LIT>_AllRegs_Vector_RegMask : CSR_<ISA_LIT>_AllRegs_RegMask ;

if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_SwiftError_RegMask ;


<s> return __builtin_aarch64_fmulxhf ( __a , __b ) ;


<s> replaceWith ( & I , ConstantInt :: getTrue ( I . getContext ( ) ) ) ; return true ;

} else if ( isImageWriteOnly ( * TexHandle ) || isImageReadWrite ( * TexHandle ) || isSampler ( * TexHandle ) ) {


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue WideVec = WidenVector ( Op . getOperand ( <NUM_LIT> ) , DAG ) ; EVT WideTy = WideVec . getValueType ( ) ; SDValue Node = DAG . getNode ( <STR_LIT> , DL , WideTy , WideVec , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> if ( get_attr_length ( trial ) == <NUM_LIT> && current_frame_info . gmask == <NUM_LIT> && ! reg_mentioned_p ( stack_pointer_rtx , PATTERN ( trial ) ) && ! reg_mentioned_p ( frame_pointer_rtx , PATTERN ( trial ) ) ) return <NUM_LIT> ;


<s> auto Imm5 = Imm & <NUM_LIT> ; auto Ry = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( DecodesFPR64RegisterClass ( Inst , Ry , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( FPR64DecoderTable [ Ry + Imm5 ] ) ) ; return MCDisassembler :: Success ;


<s> const TargetRegisterClass * RCreg = MRI . getRegClass ( reg ) ; unsigned predReg = State . getXccVReg ( reg , <ISA_LIT>InstrInfo :: getSide ( MI ) ) ; if ( predReg && MRI . getRegClass ( reg ) == PredRegsRegisterClass ) { MO . setReg ( predReg ) ; continue ; } if ( RCreg -> hasSuperClass ( ARegsRegisterClass ) ) RCreg = ARegsRegisterClass ; else if ( RCreg -> hasSuperClass ( BRegsRegisterClass ) ) RCreg = BRegsRegisterClass ; assert ( RCreg == ARegsRegisterClass || RCreg == BRegsRegisterClass ) ; const TargetRegisterClass * RCinst = TOI . getRegClass ( TRI ) ; if ( RCinst != GPRegsRegisterClass && RCreg != RCinst ) { DEBUG ( dbgs ( ) << * MI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MO << <STR_LIT> << RCreg -> getName ( ) << <STR_LIT> << RCinst -> getName ( ) << <STR_LIT> ) ; unsigned newReg = State . getXccVReg ( MO . getReg ( ) , <ISA_LIT>InstrInfo :: getSide ( MI ) ) ; assert ( newReg && <STR_LIT> ) ; MO . setReg ( newReg ) ; } }


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & ) const { return EnableRegisterScavenging ;


<s> unsigned Opc = getCMovFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) , TRI . getRegSizeInBits ( RC ) / <NUM_LIT> , false ) ;

BuildMI ( MBB , I , DL , get ( Opc ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ;


<s> addPass ( createUnpackMachineBundles ( [ this ] ( const Function & F ) {

return this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . isThumb2 ( ) ;


<s> virtual ~ <ISA_LIT>DAGToDAGISel ( ) {


<s> SDValue <ISA_LIT>TargetLowering :: getAddrLarge ( NodeTy * N , SelectionDAG & DAG , unsigned Flags ) const { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ;


<s> auto NumBits = Info . TargetSize + Info . TargetOffset ; auto NumBytes = ( NumBits / <NUM_LIT> ) + ( ( NumBits % <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ;

assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ;


<s> void R600MCCodeEmitter :: EmitNullBytes ( unsigned int ByteCount , raw_ostream & OS ) const { for ( unsigned int i = <NUM_LIT> ; i < ByteCount ; i ++ ) {


<s> else return ( TYPE_MODE ( type ) == BLKmode && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ;


<s> extern __inline __m256i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_mask_i64gather_epi64 ( __m256i src , long long int const * base , __m256i index , __m256i mask , const int scale ) {

return ( __m256i ) __builtin_ia32_gatherdiv4di ( ( __v4di ) src , base , ( __v4di ) index , ( __v4di ) mask , scale ) ;


<s> return ( Mask >> ( <NUM_LIT> - Position ) & <NUM_LIT> ) ;


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ; unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups ) << <NUM_LIT> ;

unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups ) ;


<s> if ( SubReg . getReg ( ) . isPhysical ( ) ) return TRI . isSubRegister ( SuperVec . getReg ( ) , SubReg . getReg ( ) ) ; return SubReg . getSubReg ( ) != <STR_LIT> && SubReg . getReg ( ) == SuperVec . getReg ( ) ;


<s> bool enableGLCBit ( const MachineBasicBlock :: iterator & MI ) const { return enableNamedBit ( MI , <STR_LIT> :: GLC ) ;


<s> const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) {


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadInstrs ; ArtCombiner . tryCombineUnmergeValues ( MI , DeadInstrs , UpdatedDefs , Observer ) ; for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI -> eraseFromParent ( ) ;


<s> for ( unsigned i = Pos , e = Pos + Size ; i != e ; ++ i ) if ( <NUM_LIT> <= Mask [ i ] ) return false ;


<s> MCSection * <ISA_LIT>Z80TargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> void <ISA_LIT>CondBrFolding :: fixupModifiedCond ( MachineBasicBlock * MBB ) { TargetMBBInfo * MBBInfo = getMBBInfo ( MBB ) ; if ( ! MBBInfo -> Modified ) return ; MachineInstr * BrMI = MBBInfo -> BrInstr ; <STR_LIT> CC = MBBInfo -> BranchCode ; MachineInstrBuilder MIB = BuildMI ( * MBB , BrMI , MBB -> findDebugLoc ( BrMI ) , TII -> get ( <STR_LIT> ) ) . addMBB ( MBBInfo -> TBB ) . addImm ( CC ) ; BrMI -> eraseFromParent ( ) ;

MBBInfo -> BrInstr = MIB . getInstr ( ) ;


<s> IsaInfo :: streamIsaVersion ( getGlobalSTI ( ) , ISAVersionStream ) ; getTargetStreamer ( ) -> EmitISAVersion ( ISAVersionStream . str ( ) ) ; }

if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) {


<s> break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: AExt : case CCValAssign :: AExtUpper : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: ZExt : case CCValAssign :: ZExtUpper : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: SExt : case CCValAssign :: SExtUpper : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; } InVals . push_back ( Val ) ; }