<s> rtx x = XEXP ( dest , <NUM_LIT> ) ; if ( CONSTANT_ADDRESS_P ( x ) ) { int n_words = AVR_TINY ? <NUM_LIT> : <NUM_LIT> ; return optimize > <NUM_LIT> && io_address_operand ( x , QImode ) ? avr_asm_len ( <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> , op , plen , - n_words ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { int disp = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( AVR_TINY ) return avr_out_movqi_mr_r_reg_disp_tiny ( insn , op , plen ) ; if ( disp - GET_MODE_SIZE ( GET_MODE ( dest ) ) >= <NUM_LIT> ) { if ( REGNO ( XEXP ( x , <NUM_LIT> ) ) != REG_Y ) fatal_insn ( <STR_LIT> , insn ) ; if ( disp <= <NUM_LIT> + MAX_LD_OFFSET ( GET_MODE ( dest ) ) ) return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else if ( REGNO ( XEXP ( x , <NUM_LIT> ) ) == REG_X ) { if ( reg_overlap_mentioned_p ( src , XEXP ( x , <NUM_LIT> ) ) ) { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ;


<s> } if ( opts -> x_nopcrelative_literal_loads == <NUM_LIT> ) aarch64_nopcrelative_literal_loads = false ; if ( opts -> x_nopcrelative_literal_loads == <NUM_LIT> && ! TARGET_FIX_ERR_A53_843419 ) aarch64_nopcrelative_literal_loads = true ;

if ( opts -> x_nopcrelative_literal_loads && ( aarch64_cmodel == AARCH64_CMODEL_TINY || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC ) ) aarch64_nopcrelative_literal_loads = false ;


<s> } } return ; } case 'i' : { if ( ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ) { Result = DAG . getTargetConstant ( CST -> getSExtValue ( ) , <STR_LIT> ) ; break ; } if ( Subtarget -> isPICStyleGOT ( ) || Subtarget -> isPICStyleStubPIC ( ) ) return ; GlobalAddressSDNode * GA = nullptr ; int64_t Offset = <NUM_LIT> ; while ( <NUM_LIT> ) { if ( ( GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) ) { Offset += GA -> getOffset ( ) ; break ; } else if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Offset += C -> getZExtValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; continue ; } } else if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Offset += - C -> getZExtValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; continue ; } } return ; } const GlobalValue * GV = GA -> getGlobal ( ) ; if ( isGlobalStubReference ( Subtarget -> ClassifyGlobalReference ( GV , DAG . getTarget ( ) ) ) ) return ; Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , GA -> getValueType ( <NUM_LIT> ) , Offset ) ; break ; } } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } return TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ;


<s> RC = & <STR_LIT> ; } else if ( VT . getSimpleVT ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { return false ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; unsigned Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( Op0Reg ) . addReg ( Op0Reg ) ;

unsigned ResultReg = createResultReg ( RC ) ;


<s> getTargetStreamer ( ) -> emitFunctionType ( WasmSym ) ; if ( MDNode * Idx = F . getMetadata ( <STR_LIT> ) ) { assert ( Idx -> getNumOperands ( ) == <NUM_LIT> ) ; getTargetStreamer ( ) -> emitIndIdx ( AsmPrinter :: lowerConstant ( cast < ConstantAsMetadata > ( Idx -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ) ) ; } SmallVector < <STR_LIT> , <NUM_LIT> > Locals ;

valTypesFromMVTs ( MFI -> getLocals ( ) , Locals ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( GroupDesc . Val ) ) ;


<s> return __builtin_shuffle ( __a , __b , ( uint64x2_t ) { <NUM_LIT> , <NUM_LIT> } ) ;


<s> Type * Int32Ty = Type :: getInt32Ty ( * Ctx ) ; IdxList [ IdxC ++ ] = ConstantInt :: get ( Int32Ty , <NUM_LIT> ) ; } while ( ++ nax <= Num ) { GepNode * N = NA [ nax - <NUM_LIT> ] ; IdxList [ IdxC ++ ] = N -> Idx ; if ( nax < Num ) { Type * NextTy = next_type ( N -> PTy , N -> Idx ) ; if ( NextTy != NA [ nax ] -> PTy ) break ; } } ArrayRef < Value * > A ( IdxList , IdxC ) ; Type * InpTy = Input -> getType ( ) ; Type * ElTy = cast < PointerType > ( InpTy -> getScalarType ( ) ) -> getElementType ( ) ; NewInst = GetElementPtrInst :: Create ( ElTy , Input , A , <STR_LIT> , At ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * NewInst << '\n' ) ; Input = NewInst ;


<s> case <STR_LIT> : { const TargetRegisterClass * SrcRC = getOpRegClass ( Inst , <NUM_LIT> ) ; if ( RI . isAGPRClass ( SrcRC ) ) { if ( RI . isAGPRClass ( NewDstRC ) ) return nullptr ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NewDstRC = RI . getEquivalentAGPRClass ( NewDstRC ) ; break ; default : NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; } if ( ! NewDstRC ) return nullptr ; } else {

if ( RI . isVGPRClass ( NewDstRC ) || NewDstRC == & <STR_LIT> ) return nullptr ;


<s> rtx pat , addr ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = Pmode ; machine_mode mode1 = Pmode ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( icode == CODE_FOR_altivec_lvx_v1ti || icode == CODE_FOR_altivec_lvx_v2df || icode == CODE_FOR_altivec_lvx_v2di || icode == CODE_FOR_altivec_lvx_v4sf || icode == CODE_FOR_altivec_lvx_v4si || icode == CODE_FOR_altivec_lvx_v8hi || icode == CODE_FOR_altivec_lvx_v16qi ) { rtx rawaddr ; if ( op0 == const0_rtx ) rawaddr = op1 ;


<s> * offset_ptr = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; } else { * base_ptr = x ;


<s> rsym -> setReserved ( rsym -> reserved ( ) | ReserveRel ) ; getTarget ( ) . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } return ; } case llvm :: ELF :: R_<ISA_LIT>_ABS16 : case llvm :: ELF :: R_<ISA_LIT>_ABS12 : case llvm :: ELF :: R_<ISA_LIT>_THM_ABS5 : case llvm :: ELF :: R_<ISA_LIT>_ABS8 : case llvm :: ELF :: R_<ISA_LIT>_BASE_ABS : case llvm :: ELF :: R_<ISA_LIT>_MOVW_ABS_NC : case llvm :: ELF :: R_<ISA_LIT>_MOVT_ABS : case llvm :: ELF :: R_<ISA_LIT>_THM_MOVW_ABS_NC : case llvm :: ELF :: R_<ISA_LIT>_THM_MOVT_ABS : { if ( config ( ) . isCodeIndep ( ) ) { error ( diag :: non_pic_relocation ) << getName ( pReloc . type ( ) ) << pReloc . symInfo ( ) -> name ( ) ; } return ; } case llvm :: ELF :: R_<ISA_LIT>_GOTOFF32 : case llvm :: ELF :: R_<ISA_LIT>_GOTOFF12 : { return ; } case llvm :: ELF :: R_<ISA_LIT>_TARGET2 : pReloc . setType ( llvm :: ELF :: R_<ISA_LIT>_GOT_PREL ) ; case llvm :: ELF :: R_<ISA_LIT>_GOT_BREL : case llvm :: ELF :: R_<ISA_LIT>_GOT_PREL : {

if ( rsym -> reserved ( ) & ReserveGOT ) return ;


<s> void <ISA_LIT>InstPrinter :: printCallOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printOperand ( MI , OpNum , O ) ;


<s> if ( mask == <NUM_LIT> || ( mask & ix86_isa_flags ) != <NUM_LIT> || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; }


<s> } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else { Base = N ; } OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; }


<s> return D ( <STR_LIT> , MemARPSI ( xy , i ) , MemARPSJ ( xy , j ) , PA ( base , sub_p0 , p0_align , sub_p1 , p1_align ) , DsmReg ( a ) , Mul ( x0_sign , y0_sign ) , Mul ( x1_sign , y1_sign ) , dmodi ? <STR_LIT> : <STR_LIT> , dmodj ? <STR_LIT> : <STR_LIT> ) ;


<s> if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return SDValue ( ) ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return SDValue ( ) ; if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ;


return ( __m128i ) __builtin_ia32_vpconflictdi_128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_di ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FrameIdx ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue StoreChain = DAG . getEntryNode ( ) ; SDValue Ops [ ] = { StoreChain , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value , FIdx } ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; StoreChain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , Ops , <STR_LIT> , PtrInfo ) ; unsigned Offset = <NUM_LIT> * cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Idx = DAG . getConstant ( Offset , dl , FIdx . getValueType ( ) ) ; Idx = DAG . getNode ( <STR_LIT> , dl , FIdx . getValueType ( ) , FIdx , Idx ) ;

SDValue IntVal = DAG . getLoad ( <STR_LIT> , dl , StoreChain , Idx , PtrInfo . getWithOffset ( Offset ) ) ;


<s> BeginToEnd . clear ( ) ; EndToBegin . clear ( ) ;


<s> __builtin_mve_vstrbq_uv16qi ( ( __builtin_neon_qi * ) __addr , __value ) ;


<s> auto & ReadOnlySection = * ObjectFileInfo . getReadOnlySection ( ) ; Streamer . PushSection ( ) ; Streamer . SwitchSection ( & ReadOnlySection ) ; Streamer . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; if ( ReadOnlySection . getAlignment ( ) < <NUM_LIT> ) ReadOnlySection . setAlignment ( <NUM_LIT> ) ; SmallString < <NUM_LIT> > KernelName ; getNameWithPrefix ( KernelName , & MF -> getFunction ( ) ) ;

getTargetStreamer ( ) -> EmitAmdhsaKernelDescriptor ( * getSTI ( ) , KernelName , getAmdhsaKernelDescriptor ( * MF , CurrentProgramInfo ) , CurrentProgramInfo . NumVGPRsForWavesPerEU , CurrentProgramInfo . NumSGPRsForWavesPerEU - IsaInfo :: getNumExtraSGPRs ( getSTI ( ) -> getFeatureBits ( ) , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed ) , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed , hasXNACK ( * getSTI ( ) ) ) ;


<s> switch ( Type ) { case PPR : return <NUM_LIT> ; case GPR : case FPR64 :


<s> StringRef getSysReg ( ) const { assert ( Kind == SystemRegister && <STR_LIT> ) ; return StringRef ( SysReg . Data , SysReg . Length ) ;


<s> for ( MachineBasicBlock :: instr_iterator MI = MBB -> instr_begin ( ) ; MI != MBB -> instr_end ( ) ; ++ MI ) MBBInfos [ I ] . Size += TII -> getInstSizeInBytes ( * MI ) ;


<s> Register Reg ; if ( VT == LLT :: scalar ( <NUM_LIT> ) ) { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> :


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget ;


<s> const RegisterBank & <ISA_LIT>RegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC , LLT Ty ) const { return <STR_LIT> ;


<s> unsigned InBits = UnpackFromEltSize * <NUM_LIT> ; EVT InVT = <STR_LIT> ( <STR_LIT> ( InBits ) , <STR_LIT> / InBits ) ; SDValue PackedOp = DAG . getNode ( <STR_LIT> , DL , InVT , Op ) ; unsigned OutBits = InBits * <NUM_LIT> ;

EVT OutVT = <STR_LIT> ( <STR_LIT> ( OutBits ) , <STR_LIT> / OutBits ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo :: getFixedStack ( SSFI ) , false , false , <NUM_LIT> ) ; return BuildFILD ( Op , SrcVT , Chain , StackSlot , DAG ) ;


<s> if ( i >= FIRST_REX_INT_REG ) i -= ( FIRST_REX_INT_REG - LAST_INT_REG - <NUM_LIT> ) ; indirect_thunks_used |= <NUM_LIT> << i ; } indirect_thunk_name ( thunk_name_buf , regno , need_prefix , false ) ; thunk_name = thunk_name_buf ; } else thunk_name = NULL ; if ( sibcall_p ) { if ( thunk_name != NULL ) fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; else output_indirect_thunk ( regno ) ; } else { if ( thunk_name != NULL ) { fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; return ; } char indirectlabel1 [ <NUM_LIT> ] ; char indirectlabel2 [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel1 , INDIRECT_LABEL , indirectlabelno ++ ) ; ASM_GENERATE_INTERNAL_LABEL ( indirectlabel2 , INDIRECT_LABEL , indirectlabelno ++ ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel2 ) ; fputc ( '\n' , asm_out_file ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel1 ) ; if ( thunk_name != NULL ) fprintf ( asm_out_file , <STR_LIT> , thunk_name ) ; else output_indirect_thunk ( regno ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , indirectlabel2 ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , indirectlabel1 ) ; fputc ( '\n' , asm_out_file ) ; }


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; unsigned NewImm = Imm ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned s = <NUM_LIT> ; s != NumElts * <NUM_LIT> ; s += NumElts ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElts / <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( NewImm % NumLaneElts + s + l ) ; NewImm /= NumLaneElts ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGC_TRANSITION_END ( SDValue Op , SelectionDAG & DAG ) const { SmallVector < SDValue , <NUM_LIT> > Ops ;

Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> return gen_rtx_REG ( mode , regno ) ; } else if ( POINTER_TYPE_P ( valtype ) ) { mode = word_mode ; } ret = construct_container ( mode , orig_mode , valtype , <NUM_LIT> , X86_64_REGPARM_MAX , X86_64_SSE_REGPARM_MAX , x86_64_int_return_registers , <NUM_LIT> ) ; if ( ! ret ) ret = gen_rtx_REG ( orig_mode , AX_REG ) ; return ret ;


<s> return __builtin_shuffle ( __a , __b , ( uint64x2_t ) { <NUM_LIT> , <NUM_LIT> } ) ;


<s> int NumExpectedSteps = APInt ( <NUM_LIT> , NumVecElts ) . logBase2 ( ) ; SDValue PreOp = OpV ; for ( int CurStep = <NUM_LIT> ; CurStep != NumExpectedSteps ; ++ CurStep ) { SDValue CurOp = PreOp . getOperand ( <NUM_LIT> ) ; SDValue Shuffle = PreOp . getOperand ( <NUM_LIT> ) ; if ( Shuffle . getOpcode ( ) != <STR_LIT> ) { CurOp = PreOp . getOperand ( <NUM_LIT> ) ; Shuffle = PreOp . getOperand ( <NUM_LIT> ) ; if ( Shuffle . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; } if ( CurOp . getOpcode ( ) != Op && ( CurStep != ( NumExpectedSteps - <NUM_LIT> ) ) ) return SDValue ( ) ; if ( Shuffle . getOperand ( <NUM_LIT> ) != CurOp ) return SDValue ( ) ; int NumMaskElts = <NUM_LIT> << CurStep ; ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( Shuffle ) -> getMask ( ) ; for ( int i = <NUM_LIT> ; i < NumVecElts ; ++ i ) if ( ( i < NumMaskElts && Mask [ i ] != ( NumMaskElts + i ) ) || ( i >= NumMaskElts && ! ( Mask [ i ] < <NUM_LIT> ) ) ) return SDValue ( ) ; PreOp = CurOp ; } unsigned Opcode ; bool IsIntrinsic = false ; switch ( Op ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;


<s> Inst . addOperand ( MCOperand :: createImm ( Literal . lshr ( <NUM_LIT> ) . getZExtValue ( ) ) ) ; setImmKindLiteral ( ) ; return ; } llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool lost ; APFloat FPLiteral ( APFloat :: IEEEdouble ( ) , Literal ) ; FPLiteral . convert ( * getOpFltSemantics ( OpTy ) , APFloat :: rmNearestTiesToEven , & lost ) ; uint64_t ImmVal = FPLiteral . bitcastToAPInt ( ) . getZExtValue ( ) ; Inst . addOperand ( MCOperand :: createImm ( ImmVal ) ) ; setImmKindLiteral ( ) ; return ; } default : llvm_unreachable ( <STR_LIT> ) ; } return ; } switch ( OpTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isSafeTruncation ( Val , <NUM_LIT> ) && <STR_LIT> ( static_cast < int32_t > ( Val ) , AsmParser -> hasInv2PiInlineImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; setImmKindConst ( ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( Val & <NUM_LIT> ) ) ; setImmKindLiteral ( ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( <STR_LIT> ( Val , AsmParser -> hasInv2PiInlineImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; setImmKindConst ( ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( Lo_32 ( Val ) ) ) ; setImmKindLiteral ( ) ;


<s> if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createImmTLS ( const MCExpr * Imm , const MCExpr * Sym , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindImmTLS , StartLoc , EndLoc ) ; Op -> ImmTLS . Imm = Imm ; Op -> ImmTLS . Sym = Sym ; return Op ;


<s> static bool visium_legitimate_constant_p ( enum machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED ) { return true ;


<s> if ( ! isImmediate ( MO ) ) { CmpRegs . insert ( MO . getReg ( ) ) ; continue ; } if ( CmpImmOp ) return false ; CmpImmOp = & MO ; } } else if ( MO . isImm ( ) ) { if ( CmpImmOp ) return false ; CmpImmOp = & MO ; } } if ( CmpRegs . empty ( ) ) return false ; for ( RegisterInductionSet :: iterator I = IndRegs . begin ( ) , E = IndRegs . end ( ) ; I != E ; ++ I ) { if ( CmpRegs . count ( I -> first ) ) return true ; const RegisterBump & RB = I -> second ; if ( CmpRegs . count ( RB . first ) ) { if ( ! CmpImmOp ) { MachineInstr * IndI = nullptr ; MachineInstr * nonIndI = nullptr ; MachineOperand * IndMO = nullptr ; MachineOperand * nonIndMO = nullptr ; for ( unsigned i = <NUM_LIT> , n = PredDef -> getNumOperands ( ) ; i < n ; ++ i ) { MachineOperand & MO = PredDef -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == RB . first ) { DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << * ( MRI -> getVRegDef ( I -> first ) ) ) ; if ( IndI ) return false ; IndI = MRI -> getVRegDef ( I -> first ) ; IndMO = & MO ; } else if ( MO . isReg ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << * ( MRI -> getVRegDef ( MO . getReg ( ) ) ) ) ; if ( nonIndI ) return false ; nonIndI = MRI -> getVRegDef ( MO . getReg ( ) ) ; nonIndMO = & MO ; } } if ( IndI && nonIndI && nonIndI -> getOpcode ( ) == <STR_LIT> && nonIndI -> getOperand ( <NUM_LIT> ) . isImm ( ) && nonIndI -> getOperand ( <NUM_LIT> ) . getImm ( ) == - RB . second ) { bool Order = orderBumpCompare ( IndI , PredDef ) ; if ( Order ) { IndMO -> setReg ( I -> first ) ; nonIndMO -> setReg ( nonIndI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return true ; } } return false ; } Comparison :: Kind Cmp = getComparisonKind ( PredDef -> getOpcode ( ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ;

if ( ! Cmp || Comparison :: isUnsigned ( Cmp ) ) return false ;


<s> static DecodeStatus DecodePtrRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) {

if ( static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) -> isGP64Bit ( ) ) return DecodeGPR64RegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool DumpAsm , JITCodeEmitter & JCE ) { if ( DefRelocModel == Reloc :: Default && ( ! Subtarget . isTargetDarwin ( ) || ! Subtarget . is64Bit ( ) ) ) setRelocationModel ( Reloc :: Static ) ; if ( Subtarget . is64Bit ( ) ) { if ( Subtarget . isTargetDarwin ( ) ) setCodeModel ( CodeModel :: Small ) ; else setCodeModel ( CodeModel :: Large ) ; } PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; if ( DumpAsm ) { assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) , * this , OptLevel , true ) ) ; }


<s> MVT DstVT = Op . getSimpleValueType ( ) ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && DstVT . isScalarInteger ( ) ) { assert ( ! Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; MVT SExtVT = SrcVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( Op ) ; SDValue V = DAG . getSExtOrTrunc ( Src , DL , SExtVT ) ; V = getPMOVMSKB ( DL , V , DAG , Subtarget ) ; return DAG . getZExtOrTrunc ( V , DL , DstVT ) ; } assert ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; if ( ! ( DstVT == <STR_LIT> && SrcVT == <STR_LIT> ) && ! ( DstVT == <STR_LIT> && SrcVT . isVector ( ) ) ) return SDValue ( ) ;


<s> if ( GET_MODE ( x ) == SFmode ) return <NUM_LIT> ; if ( real_equal ( r , & values_68881 [ <NUM_LIT> ] ) ) return ( codes_68881 [ <NUM_LIT> ] ) ;


<s> PB . registerPipelineStartEPCallback ( [ this ] ( ModulePassManager & PM , OptimizationLevel Level ) { FunctionPassManager FPM ; FPM . addPass ( NVVMReflectPass ( Subtarget . getSmVersion ( ) ) ) ; PM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; } ) ;


<s> else if ( OpWidth == <NUM_LIT> ) return Subtarget . hasCmpxchg16b ( ) ; else return false ;


<s> if ( getSubtarget ( ) . hasV8Ops ( ) ) return isV8EligibleForIT ( MI ) ; } else {

if ( ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ;


<s> bool isCSRSystemRegister ( ) const {


<s> SDLoc DL ( Offset ) ; if ( ! isa < ConstantSDNode > ( Offset ) ) return false ; SelectMUBUFConstant ( Offset , SOffset , ImmOffset ) ; return true ;


<s> void printAS8Mem ( const MCInst * MI , int opNum , raw_ostream & O ) { printAbsMem ( MI , opNum , O ) ;


<s> bool Is32Bit = Size == <NUM_LIT> ; if ( auto Fns = selectArithImmed ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; if ( auto Fns = selectNegArithImmed ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; if ( auto Fns = selectArithExtendedRegister ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; if ( auto Fns = selectShiftedRegister ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ;

return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS , RHS } , MIRBuilder ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > defaultRhuOperands ( ) {

return <STR_LIT> ( <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ;


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> break ; case <STR_LIT> : ShiftAmt = <NUM_LIT> ; break ; } unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( SrcReg ) . addImm ( ShiftAmt ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) . addImm ( ShiftAmt ) ;


<s> static bool nvptx_welformed_vector_length_p ( int l ) { gcc_assert ( l > <NUM_LIT> ) ;


<s> void addMemOffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Mem . Base ) ) ;

if ( Mem . Index ) Inst . addOperand ( MCOperand :: CreateReg ( Mem . Index ) ) ;


<s> if ( isPredicateSetter ( MI . getOpcode ( ) ) ) return & MI ; } return nullptr ;


<s> const MachineBasicBlock * MBB = MBBI -> getParent ( ) ; while ( MBBI == MBB -> begin ( ) ) {

if ( MBB == & MBB -> getParent ( ) -> front ( ) ) return MachineBasicBlock :: const_iterator ( ) ;


<s> ELFSymbol -> setExternal ( true ) ; } ELFSymbol -> setType ( ELF :: STT_OBJECT ) ; if ( ELFSymbol -> getBinding ( ) == ELF :: STB_LOCAL ) { StringRef SectionName = ( ( AccessSize == <NUM_LIT> ) || ( Size == <NUM_LIT> ) || ( Size > GPSize ) ) ? <STR_LIT> : sbss [ ( Log2_64 ( AccessSize ) ) ] ; MCSection & Section = * getAssembler ( ) . getContext ( ) . getELFSection ( SectionName , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; MCSectionSubPair P = getCurrentSection ( ) ; SwitchSection ( & Section ) ; EmitValueToAlignment ( ByteAlignment , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; EmitLabel ( Symbol ) ; EmitZeros ( Size ) ; if ( ByteAlignment > Section . getAlignment ( ) ) Section . setAlignment ( ByteAlignment ) ; SwitchSection ( P . first , P . second ) ; } else { if ( ELFSymbol -> declareCommon ( Size , ByteAlignment ) ) report_fatal_error ( <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> ) ; if ( ( AccessSize ) && ( Size <= GPSize ) ) { uint64_t SectionIndex = ( AccessSize <= GPSize ) ? ELF :: SHN_HEXAGON_SCOMMON + ( Log2_64 ( AccessSize ) + <NUM_LIT> ) : ( unsigned ) ELF :: SHN_HEXAGON_SCOMMON ; ELFSymbol -> setIndex ( SectionIndex ) ;


<s> Op -> Mem . Base = <NUM_LIT> ; Op -> Mem . IndexReg = Index ; Op -> Mem . Index = nullptr ;


<s> bool <ISA_LIT>LowerMemoryIntrinsics :: ProcessFunction ( ) { LLVMContext & Cxt = Func -> getContext ( ) ; SmallVector < MemIntrinsic * , <NUM_LIT> > WorkList ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; TargetIdxTy = GetTargetIndexType ( DL , Cxt ) ;

for ( auto & BB : * Func ) for ( auto & I : BB ) if ( isa < MemIntrinsic > ( & I ) ) {


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , bool IsELF64 , uint8_t OSABI , uint16_t EMachine ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( IsELF64 , OSABI , EMachine ) ; return createELFObjectWriter ( MOTW , OS , true ) ;


<s> if ( worker_red_size ) write_worker_buffer ( asm_out_file , worker_red_sym , worker_red_align , worker_red_size ) ; if ( need_softstack_decl ) { write_var_marker ( asm_out_file , false , true , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , POINTER_SIZE ) ; } if ( need_unisimt_decl ) { write_var_marker ( asm_out_file , false , true , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ;


<s> for ( SDNode :: use_iterator I = LoadVal -> use_begin ( ) ; ! I . atEnd ( ) ; ++ I ) {

if ( ! <STR_LIT> ( * I ) ) return false ;


<s> emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , loc ) ) ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; if ( MACHOPIC_INDIRECT ) funexp = machopic_indirect_call_target ( funexp ) ; insn = emit_call_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_CALL ( VOIDmode , funexp , const0_rtx ) , gen_rtx_USE ( VOIDmode , const0_rtx ) , simple_return_rtx ) ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; emit_barrier ( ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , XEXP ( op , <NUM_LIT> ) , GET_MODE ( op ) , false ) ) return false ;

if ( addr . type == ADDRESS_REG_IMM ) return known_eq ( addr . const_offset , <NUM_LIT> ) ;


<s> Info . vol = false ; Info . offset = <NUM_LIT> ; switch ( IntrData -> Type ) { case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getType ( ) ) ; Info . align = <NUM_LIT> ; Info . readMem = true ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . align = <NUM_LIT> ; Info . writeMem = true ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; MVT VT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT ScalarVT = <STR_LIT> ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = <STR_LIT> ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = <STR_LIT> ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = <STR_LIT> ; Info . memVT = <STR_LIT> ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = <NUM_LIT> ; Info . writeMem = true ; break ; } default : return false ;


<s> <ISA_LIT>MergeBaseOffsetOpt ( ) : MachineFunctionPass ( ID ) {


<s> bool msp430_do_not_relax_short_jumps ( void ) { return msp430_code_region == EITHER || msp430_code_region == LOWER || has_attr ( ATTR_EITHER , current_function_decl ) || has_attr ( ATTR_LOWER , current_function_decl ) ;


<s> setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_GEP , <NUM_LIT> , Ty } , WidenScalar ) ; setAction ( { G_BRCOND , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , NarrowScalar ) ; for ( auto Ty : { s8 , s16 , s32 } ) { setAction ( { G_ZEXT , Ty } , Legal ) ; setAction ( { G_SEXT , Ty } , Legal ) ; setAction ( { G_ANYEXT , Ty } , Legal ) ; } for ( auto Ty : { s1 , s8 , s16 } ) { setAction ( { G_ZEXT , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_SEXT , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_ANYEXT , <NUM_LIT> , Ty } , Legal ) ; } setAction ( { G_ICMP , s1 } , Legal ) ;

for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { G_ICMP , <NUM_LIT> , Ty } , Legal ) ;


<s> <ISA_LIT>ISelAddressMode ( ) : BaseType ( RegBase ) , Base_FrameIndex ( <NUM_LIT> ) , Scale ( <NUM_LIT> ) , IndexReg ( ) , Disp ( <NUM_LIT> ) , Segment ( ) , GV ( nullptr ) , CP ( nullptr ) , BlockAddr ( nullptr ) , ES ( nullptr ) , JT ( - <NUM_LIT> ) , Align ( <NUM_LIT> ) , SymbolFlags ( <STR_LIT> ) {


<s> return __builtin_mve_vqmovuntq_sv4si ( __a , __b ) ;


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override {

return create<ISA_LIT>ELFObjectWriter ( Is64Bit , HasRelocationAddend , OS ) ;


<s> bool hasTransactionalExecution ( ) const {


<s> assert ( Inputs . has ( CR . Reg ) ) ; LatticeCell LS ; if ( ! getCell ( CR , Inputs , LS ) ) return false ; uint32_t Ps = LS . properties ( ) ; unsigned TakeOp ; if ( Ps & ConstantProperties :: Zero ) TakeOp = <NUM_LIT> ; else if ( Ps & ConstantProperties :: NonZero ) TakeOp = <NUM_LIT> ; else return false ; const MachineOperand & ValOp = MI . getOperand ( TakeOp ) ; Register DefR ( MI . getOperand ( <NUM_LIT> ) ) ; LatticeCell RC = Outputs . get ( DefR . Reg ) ; if ( ValOp . isImm ( ) ) { int64_t V = ValOp . getImm ( ) ; unsigned W = getRegBitWidth ( DefR . Reg ) ; APInt A ( W , V , true ) ; const Constant * C = intToConst ( A ) ; RC . add ( C ) ; Outputs . update ( DefR . Reg , RC ) ; return true ; } if ( ValOp . isReg ( ) ) { Register R ( ValOp ) ;

const LatticeCell & LR = Inputs . get ( R . Reg ) ;


<s> assert ( PI != TopMBB -> pred_end ( ) && <STR_LIT> ) ; MachineBasicBlock * Backedge = * PI ++ ; if ( PI == TopMBB -> pred_end ( ) ) return ; MachineBasicBlock * Incoming = * PI ++ ; if ( PI != TopMBB -> pred_end ( ) ) return ; if ( L -> contains ( Incoming ) ) { if ( L -> contains ( Backedge ) ) return ; std :: swap ( Incoming , Backedge ) ; } else if ( ! L -> contains ( Backedge ) ) return ; for ( MachineBasicBlock :: iterator I = TopMBB -> begin ( ) , E = TopMBB -> end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * MPhi = & * I ; unsigned DefReg = MPhi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = <NUM_LIT> ; i != MPhi -> getNumOperands ( ) ; i += <NUM_LIT> ) { MachineBasicBlock * MBB = MPhi -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; if ( L -> contains ( MBB ) ) { MachineInstr * DI = MRI -> getVRegDef ( MPhi -> getOperand ( i ) . getReg ( ) ) ; if ( isInductionOperation ( DI , DefReg ) ) { IOps . push_back ( DI ) ; IVars . push_back ( MPhi ) ; } }


<s> assert ( OPW_FIRST_ <= Width && Width < OPW_LAST_ ) ; switch ( Width ) { default : case OPW32 : return SGPR_32RegClassID ; case OPW64 : return SGPR_64RegClassID ;

case OPW128 : return SGPR_128RegClassID ;


<s> bool <ISA_LIT>ExpandPseudo :: ExpandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool isMem = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( isMem ? <NUM_LIT> : <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; if ( StackAdj ) { StackAdj += <ISA_LIT>FL -> mergeSPUpdates ( MBB , MBBI , true ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , StackAdj , true ) ; } bool IsWin64 = STI -> isTargetWin64 ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) MIB . addOperand ( MBBI -> getOperand ( i ) ) ; } else if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; NewMI -> copyImplicitOps ( * MBBI -> getParent ( ) -> getParent ( ) , MBBI ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ;

const bool Uses64BitFramePtr = STI -> isTarget64BitLP64 ( ) || STI -> isTargetNaCl64 ( ) ;


<s> if ( HSAMD :: fromString ( HSAMetadataString , HSAMetadata ) ) return false ;

return EmitHSAMetadata ( HSAMetadata ) ;


<s> static unsigned int rs6000_elf_section_type_flags ( tree decl , const char * name , int reloc ) { return default_section_type_flags_1 ( decl , name , reloc , flag_pic || DEFAULT_ABI == ABI_AIX ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectPostLoadLane ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) transform ( Regs , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , RegSeq -> getValueType ( <NUM_LIT> ) , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Narrow ? NarrowVector ( SuperReg , * CurDAG ) : SuperReg ) ; } else { EVT WideVT = RegSeq . getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; static const unsigned QSubs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) { SDValue NV = CurDAG -> getTargetExtractSubreg ( QSubs [ i ] , dl , WideVT , SuperReg ) ; if ( Narrow ) NV = NarrowVector ( NV , * CurDAG ) ; ReplaceUses ( SDValue ( N , i ) , NV ) ; } } ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( Ld , <NUM_LIT> ) ) ;


<s> * total = COSTS_N_INSNS ( INTVAL ( XEXP ( ( x ) , <NUM_LIT> ) ) ) ; if ( * total < <NUM_LIT> ) * total = <NUM_LIT> ; } return false ; case DIV : case UDIV : if ( speed ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case MULT : if ( ( TARGET_DPFP && GET_MODE ( x ) == DFmode ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( speed ) * total = arc_multcost ; else if ( TARGET_MUL64_SET || ( TARGET_ARC700 && ! TARGET_NOMPY_SET ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && _2_4_8_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) { * total += ( rtx_cost ( XEXP ( x , <NUM_LIT> ) , PLUS , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , PLUS , <NUM_LIT> , speed ) ) ; return true ; } return false ; case MINUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && _2_4_8_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) { * total += ( rtx_cost ( XEXP ( x , <NUM_LIT> ) , PLUS , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , PLUS , <NUM_LIT> , speed ) ) ; return true ; } return false ; case COMPARE : { rtx op0 = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == ZERO_EXTRACT && op1 == const0_rtx && XEXP ( op0 , <NUM_LIT> ) == const1_rtx ) { * total = ( rtx_cost ( XEXP ( op0 , <NUM_LIT> ) , SET , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( op0 , <NUM_LIT> ) , SET , <NUM_LIT> , speed ) ) ;


<s> rtx insn , clobs [ TOTAL_ALTIVEC_REGS + <NUM_LIT> ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ <NUM_LIT> ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( <NUM_LIT> , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_or_fixed_reg_p ( i ) ) clobs [ nclobs ++ ] = gen_hard_reg_clobber ( V4SImode , i ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( <NUM_LIT> , reg ) , <NUM_LIT> ) ) ; }


<s> assert ( ( Value == <NUM_LIT> || Value == <NUM_LIT> ) && <STR_LIT> ) ;


<s> if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ;


<s> return ! cfun -> machine -> lr_save_eliminated && ( ! leaf_function_p ( ) || thumb_far_jump_used_p ( ) || df_regs_ever_live_p ( LR_REGNUM ) ) ;


<s> unsigned HalfMask = Imm >> ( l * <NUM_LIT> ) ; unsigned HalfBegin = ( HalfMask & <NUM_LIT> ) * HalfSize ; for ( unsigned i = HalfBegin , e = HalfBegin + HalfSize ; i != e ; ++ i ) ShuffleMask . push_back ( HalfMask & <NUM_LIT> ? SM_SentinelZero : ( int ) i ) ; }


<s> if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsl ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Asr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Ror ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Rrx ; else return true ; Parser . Lex ( ) ; if ( St == Rrx ) return false ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getParser ( ) . ParseExpression ( ShiftAmount ) ) return true ; return false ;


if ( GET_CODE ( op ) != PLUS || GET_MODE ( op ) != Pmode || ! register_operand ( XEXP ( op , <NUM_LIT> ) , Pmode ) || ! nonmemory_operand ( XEXP ( op , <NUM_LIT> ) , Pmode ) ) return <NUM_LIT> ;


<s> assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= - <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ;


<s> for ( auto & Str : MAI -> SrcExt ) { MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; addStringImm ( Str . first ( ) , Inst ) ;


<s> const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ;

const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> return ( __m128d ) __builtin_ia32_andnpd128_mask ( ( __v2df ) __A , ( __v2df ) __B , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> } if ( MI ) { for ( auto & MO : BI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } } if ( ! MI ) return ; MI -> setDesc ( HII -> get ( HII -> getNonDotCurOp ( * MI ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI -> dump ( ) ; ) ;


<s> switch ( SD -> getMemoryVT ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : AliasReg = TM . getFrameLowering ( ) -> hasFP ( * MF ) ? AliasFPReg : get<ISA_LIT>16SPAliasReg ( ) ; return ; } break ; } case <STR_LIT> : { StoreSDNode * SD = dyn_cast < StoreSDNode > ( Parent ) ; switch ( SD -> getMemoryVT ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : AliasReg = TM . getFrameLowering ( ) -> hasFP ( * MF ) ? AliasFPReg : get<ISA_LIT>16SPAliasReg ( ) ; return ; } break ; } } }

AliasReg = CurDAG -> getRegister ( <STR_LIT> , TLI . getPointerTy ( ) ) ;


<s> static void demoteInst ( MCInst & Inst , const MCInstrInfo & InstInfo ) { unsigned NewOpc = demoteOpcode ( Inst . getOpcode ( ) ) ; Inst . setOpcode ( NewOpc ) ;

const MCOperandInfo * OpInfo = InstInfo . get ( Inst . getOpcode ( ) ) . OpInfo ;


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < LiveIntervals > ( ) ;

AU . addPreserved < LiveIntervals > ( ) ;


return S . schedule ( BotRoots , DAG ) ;


<s> if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) ) ) return <STR_LIT> ;

if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT ( ) ) ) && is64Bit ( ) ) return <STR_LIT> ;


<s> __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> void printJT2BlockOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {


<s> StringRef TokStr = Tok . getString ( ) ; if ( TokStr . equals ( <STR_LIT> ) ) Start = Tok . getLoc ( ) ; else if ( TokStr . equals ( <STR_LIT> ) ) { End = Tok . getEndLoc ( ) ; break ; } if ( Tok . getKind ( ) == AsmToken :: Eof ) return false ; Lexer . Lex ( ) ; } IndexMap = std :: string ( Start . getPointer ( ) , End . getPointer ( ) ) ; Lexer . setSkipSpace ( true ) ;


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override {


<s> static DecodeStatus DecodeSMLAInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Ra = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> Target & T = The<ISA_LIT>Target ; RegisterMCAsmInfoFn X ( T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( T , create<ISA_LIT>MCRegisterInfo ) ;

TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfo ) ;


<s> if ( Modifier && strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT> ) ) == <NUM_LIT> ) { EVT VT = ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , VT ) ; }


<s> bool isCCallSymbol ( ) const { int64_t Imm ;

<ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> return ! <STR_LIT> ( F . getCallingConv ( ) ) || EnableVGPRSpilling ;


<s> } const MCInstrDesc * MCID = & MI -> getDesc ( ) ; unsigned NewOpc = convertAddSubFlagsOpcode ( MI -> getOpcode ( ) ) ; if ( NewOpc ) { const <ISA_LIT>BaseInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> && <STR_LIT> ) ; MI -> setDesc ( * MCID ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; } unsigned ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; if ( ! MI -> hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; }


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ;


<s> static const int INSTR_DISTANCE_THRESHOLD = <NUM_LIT> ; CurInst = I ; bool Found ; Found = getPreviousInstr ( CurInst , MFI ) ; while ( Found && I != CurInst ) { if ( CurInst -> isCall ( ) || CurInst -> isInlineAsm ( ) ) break ; if ( InstrDistance > INSTR_DISTANCE_THRESHOLD ) break ; if ( usesRegister ( p , CurInst ) == RU_Write ) { return CurInst ; }

InstrDistance += TII -> getInstrLatency ( MF -> getSubtarget ( ) . getInstrItineraryData ( ) , * CurInst ) ;


<s> SDValue <ISA_LIT>TargetLowering :: legalizeInternalLoadStoreOp ( SDValue Op , <ISA_LIT>CustomDAG & CDAG ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; MVT DataVT = getIdiomaticVectorType ( Op . getNode ( ) ) -> getSimpleVT ( ) ; if ( isPackedVectorType ( DataVT ) ) return splitPackedLoadStore ( Op , CDAG ) ; return legalizePackedAVL ( Op , CDAG ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) return <STR_LIT> ; return <STR_LIT> ;


return ( int ) __builtin_loongarch_crcc_w_b_w ( ( char ) _1 , ( int ) _2 ) ;


<s> AddDefaultPred ( MIB ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ NumNarrows ; return true ; } if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; if ( MI -> mayLoad ( ) || MI -> mayStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ; } case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; }


<s> assert ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) ; const Register Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SubReg = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; if ( TRI -> isVGPR ( * MRI , Reg ) ) { const TargetRegisterClass * regClass = Reg . isVirtual ( ) ? MRI -> getRegClass ( Reg ) : TRI -> getPhysRegClass ( Reg ) ; if ( SubReg ) regClass = TRI -> getSubRegClass ( regClass , SubReg ) ; const unsigned MovOp = TII -> getMovOpcode ( regClass ) ; MI -> setDesc ( TII -> get ( MovOp ) ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } else if ( ! MRI -> isSSA ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isEarlyClobber ( ) ) { LIS -> removeInterval ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsEarlyClobber ( false ) ; LIS -> createAndComputeVirtRegInterval ( Reg ) ; } int Index = MI -> findRegisterUseOperandIdx ( <STR_LIT> ) ; while ( Index >= <NUM_LIT> ) { MI -> RemoveOperand ( Index ) ; Index = MI -> findRegisterUseOperandIdx ( <STR_LIT> ) ; } MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; } } for ( MachineInstr * MI : LowerToCopyInstrs ) { if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> untieRegOperand ( <NUM_LIT> ) ; } else { assert ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) ;


<s> MVT InVT = In . getSimpleValueType ( ) ; if ( VT . getVectorNumElements ( ) < InVT . getVectorNumElements ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { assert ( InVT . is128BitVector ( ) && <STR_LIT> ) ; LoadSDNode * LN = cast < LoadSDNode > ( In ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; if ( SDValue VZLoad = narrowLoadToVZLoad ( LN , MemVT , LoadVT , DAG ) ) { SDLoc dl ( N ) ; if ( IsStrict ) { SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , DAG . getBitcast ( InVT , VZLoad ) } ) ; DCI . CombineTo ( N , Convert , Convert . getValue ( <NUM_LIT> ) ) ; } else { SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , VT , DAG . getBitcast ( InVT , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; } DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT> ) ) ; DCI . recursivelyDeleteUnusedNodes ( LN ) ; return SDValue ( N , <NUM_LIT> ) ; } }


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getEHExceptionRegister ( ) const {


<s> if ( GET_CODE ( addr ) == CONST ) { if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> MachineBasicBlock * JoinMBB = splitBlockAfter ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; BuildMI ( * MBB , MBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg ) . addMBB ( StartMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & <STR_LIT> ; unsigned UDomain = UseMI -> getDesc ( ) . TSFlags & <STR_LIT> ;

if ( Subtarget . isCortexA8 ( ) && ( DDomain == <STR_LIT> || UDomain == <STR_LIT> ) ) return true ;


<s> if ( popType ( ErrorLoc , RVT ) ) return true ; } if ( ! Stack . empty ( ) ) { return typeError ( ErrorLoc , std :: to_string ( Stack . size ( ) ) + <STR_LIT> ) ; } Unreachable = true ;


<s> if ( <STR_LIT> ( GO ) && ! GO -> hasSection ( ) ) return ProgmemDataSection ; return Base :: SelectSectionForGlobal ( GO , Kind , TM ) ;


<s> else return false ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return false ; if ( CCUsers . size ( ) != <NUM_LIT> ) return false ; MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; while ( Branch -> getNumOperands ( ) ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( BRCT ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; MIB . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( Target ) ;

if ( BRCT != <STR_LIT> ) MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ;


<s> Bits = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; break ; default : return SelectCode ( N ) ; } SDValue const & V = N -> getOperand ( <NUM_LIT> ) ; SDValue U ; if ( isValueExtension ( V , Bits , U ) ) { SDValue R = CurDAG -> getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , U ) ;


<s> bool <ISA_LIT>AsmPrinter :: doInitialization ( Module & M ) { SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; } if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; GlobalsEmitted = false ; return false ;


<s> Optional < <ISA_LIT>MemOpInfo > <ISA_LIT>MemOpInfo :: getAtomicCmpxchgOrRmwInfo ( const MachineBasicBlock :: iterator & MI ) {

assert ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) ;


<s> if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; }


<s> for ( MachineBasicBlock & MBB : MF ) OutOffset [ & MBB ] = INT32_MAX ; ReversePostOrderTraversal < MachineFunction * > RPO ( & MF ) ; for ( MachineBasicBlock * MBB : RPO ) { int64_t Offset = - <NUM_LIT> ; for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) Offset = std :: max ( Offset , OutOffset [ Pred ] ) ; if ( Offset == - <NUM_LIT> ) Offset = INT32_MAX ; for ( MachineInstr & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { int64_t Amount = getWinAllocaAmount ( & MI , MRI ) ; Lowering L = getLowering ( Offset , Amount ) ; Lowerings [ & MI ] = L ; switch ( L ) { case Sub : Offset += Amount ; break ; case TouchAndSub : Offset = Amount ; break ; case Probe : Offset = <NUM_LIT> ; break ; } } else if ( MI . isCall ( ) || isPushPop ( MI ) ) {


<s> static const Constant * getTargetConstantFromNode ( LoadSDNode * Load ) { if ( ! Load ) return nullptr ; SDValue Ptr = Load -> getBasePtr ( ) ; if ( Ptr -> getOpcode ( ) == <STR_LIT> || Ptr -> getOpcode ( ) == <STR_LIT> ) Ptr = Ptr -> getOperand ( <NUM_LIT> ) ; auto * CNode = dyn_cast < ConstantPoolSDNode > ( Ptr ) ;

if ( ! CNode || CNode -> isMachineConstantPoolEntry ( ) || CNode -> getOffset ( ) != <NUM_LIT> ) return nullptr ;


<s> <ISA_LIT>AAResult ( <ISA_LIT>AAResult && Arg ) : AAResultBase ( std :: move ( Arg ) ) {


<s> } switch ( code ) { case EQ : pos = <STR_LIT> , neg = <STR_LIT> ; break ; case NE : pos = <STR_LIT> , neg = <STR_LIT> ; break ; case GT : pos = <STR_LIT> , neg = <STR_LIT> ; break ; case GTU : pos = <STR_LIT> , neg = <STR_LIT> ; break ; case LT : pos = <STR_LIT> , neg = <STR_LIT> ; break ; case LTU : pos = <STR_LIT> , neg = <STR_LIT> ; break ; case GE : pos = <STR_LIT> , neg = <STR_LIT> ; break ; case GEU : pos = <STR_LIT> , neg = <STR_LIT> ; break ; case LE : pos = <STR_LIT> , neg = <STR_LIT> ; break ; case LEU : pos = <STR_LIT> , neg = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( cc_status . flags & CC_IN_FPU ) output_asm_insn ( <STR_LIT> , NULL ) ; switch ( length ) { case <NUM_LIT> : sprintf ( buf , <STR_LIT> , inv ? neg : pos ) ;


<s> StringRef getPassName ( ) const override {


<s> unsigned AddrBase = IsStore ; unsigned RegOp = IsStore ? <NUM_LIT> : <NUM_LIT> ; unsigned AddrOp = AddrBase + <NUM_LIT> ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( RegOp ) . isReg ( ) && Inst . getOperand ( AddrBase + <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( AddrBase + <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( AddrBase + <NUM_LIT> ) . isReg ( ) && ( Inst . getOperand ( AddrOp ) . isExpr ( ) || Inst . getOperand ( AddrOp ) . isImm ( ) ) && Inst . getOperand ( AddrBase + <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned Reg = Inst . getOperand ( RegOp ) . getReg ( ) ; if ( Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> ) return ; bool Absolute = true ; if ( Inst . getOperand ( AddrOp ) . isExpr ( ) ) { const MCExpr * MCE = Inst . getOperand ( AddrOp ) . getExpr ( ) ; if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( MCE ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_TLVP ) Absolute = false ; } if ( Absolute && ( Inst . getOperand ( AddrBase + <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || Inst . getOperand ( AddrBase + <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || Inst . getOperand ( AddrBase + <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || Inst . getOperand ( AddrBase + <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ) return ;

MCOperand Saved = Inst . getOperand ( AddrOp ) ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & F ) const override {


<s> } SDValue LHS = DAG . getSExtOrTrunc ( Op . getOperand ( <NUM_LIT> ) , DL , INTTY ) ; SDValue RHS = DAG . getSExtOrTrunc ( Op . getOperand ( <NUM_LIT> ) , DL , INTTY ) ; LHS = DAG . getNode ( <STR_LIT> , DL , INTTY , LHS , RHS ) ; LHS = DAG . getSExtOrTrunc ( LHS , DL , OVT ) ; return LHS ;


<s> SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; bool Upper = IdxVal >= NumElems / <NUM_LIT> ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( Upper ? IdxVal - NumElems / <NUM_LIT> : IdxVal , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } if ( Subtarget -> hasSSE41 ( ) ) return LowerINSERT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( EltVT == <STR_LIT> ) return SDValue ( ) ; if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ;

if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ;


<s> const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ( Size * <NUM_LIT> ) ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const bool ArePtrs64bit = ABI . ArePtrs64bit ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned LL , SC , ZERO , BNE , BEQ ; if ( Size == <NUM_LIT> ) { if ( isMicro<ISA_LIT> ) { LL = <STR_LIT> ; SC = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; SC = Subtarget . has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; } ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( BNE ) ) . addReg ( Dest ) . addReg ( OldVal ) . addMBB ( exitMBB ) ;


<s> static bool selectCopy ( MachineInstr & I , const TargetInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) return true ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; }


<s> Register ResultReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ResultReg == <NUM_LIT> ) return false ; MVT SrcVT = TLI . getSimpleValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( SrcVT == <STR_LIT> ) { ResultReg = fastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; SrcVT = <STR_LIT> ; if ( ResultReg == <NUM_LIT> ) return false ; } if ( DstVT == <STR_LIT> ) { unsigned MovInst ; switch ( SrcVT . SimpleTy ) { case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; case <STR_LIT> : MovInst = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Register Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovInst ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( Result32 ) . addImm ( <STR_LIT> ) ; } else if ( DstVT == <STR_LIT> ) { Register Result32 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result32 ) . addReg ( ResultReg ) ; ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , Result32 , true , <STR_LIT> ) ;


<s> EVT MemVT = Splits [ i ] . VT ; const unsigned Offset = <NUM_LIT> + VA . getLocMemOffset ( ) ; SDValue Arg = LowerParameter ( DAG , VT , MemVT , DL , DAG . getRoot ( ) , Offset , Ins [ i ] . Flags . isSExt ( ) ) ; const PointerType * ParamTy = dyn_cast < PointerType > ( FType -> getParamType ( Ins [ i ] . OrigArgIndex ) ) ; if ( Subtarget -> getGeneration ( ) == AMDGPUSubtarget :: SOUTHERN_ISLANDS && ParamTy && ParamTy -> getAddressSpace ( ) == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , Arg . getValueType ( ) , Arg , DAG . getValueType ( <STR_LIT> ) ) ; } InVals . push_back ( Arg ) ; Info -> ABIArgOffset = Offset + MemVT . getStoreSize ( ) ; continue ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; unsigned Reg = VA . getLocReg ( ) ; if ( VT == <STR_LIT> ) { Reg = TRI -> getMatchingSuperReg ( Reg , AMDGPU :: sub0 , & AMDGPU :: SReg_64RegClass ) ; Reg = MF . addLiveIn ( Reg , & AMDGPU :: SReg_64RegClass ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ) ; continue ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; Reg = MF . addLiveIn ( Reg , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; if ( Arg . VT . isVector ( ) ) { Type * ParamType = FType -> getParamType ( Arg . OrigArgIndex ) ; unsigned NumElements = ParamType -> getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Regs ; Regs . push_back ( Val ) ; for ( unsigned j = <NUM_LIT> ; j != NumElements ; ++ j ) { Reg = ArgLocs [ ArgIdx ++ ] . getLocReg ( ) ; Reg = MF . addLiveIn ( Reg , RC ) ; Regs . push_back ( DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ) ; } NumElements = Arg . VT . getVectorNumElements ( ) - NumElements ; for ( unsigned j = <NUM_LIT> ; j != NumElements ; ++ j ) Regs . push_back ( DAG . getUNDEF ( VT ) ) ; InVals . push_back ( DAG . getNode ( <STR_LIT> , DL , Arg . VT , Regs ) ) ;


<s> int ptr_mode_size = GET_MODE_SIZE ( ptr_mode ) ; fnaddr = copy_to_reg ( XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ) ; chaddr = copy_to_reg ( static_chain ) ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ;


<s> return ( int16_t ) __builtin_aarch64_sqshrun_nsi ( __a , __b ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getMaxInterleaveFactor ( ) { unsigned Directive = ST -> getDarwinDirective ( ) ; if ( Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> ) return <NUM_LIT> ;

if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : if ( Val <= <NUM_LIT> ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( Val , DL , <STR_LIT> ) ; return true ; } if ( Val <= <NUM_LIT> && Val % <NUM_LIT> == <NUM_LIT> ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( Val >> <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } break ; default :


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ;

case <STR_LIT> : return LowerVAARG ( Op , DAG ) ;


<s> return <ISA_LIT>CompilationCallback_SSE ; if ( useSSE ) return <ISA_LIT>CompilationCallback_SSE ; return <ISA_LIT>CompilationCallback ;


<s> MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register LoReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register HiReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register ConstReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Register OpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addReg ( Src , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addReg ( Src , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , ConstReg ) . addImm ( <NUM_LIT> ) ; unsigned Opc = Fabs ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , OpReg ) . addReg ( HiReg ) . addReg ( ConstReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( OpReg ) . addImm ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ;


<s> unsigned SysM = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ;

if ( ! <STR_LIT> ( ( R << <NUM_LIT> ) | SysM ) ) return MCDisassembler :: Fail ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; }


<s> if ( VT == <STR_LIT> ) return Subtarget -> hasDSP ( ) ? & <STR_LIT> : & <STR_LIT> ; return TargetLowering :: getRepRegClassFor ( VT ) ;


<s> machine_mode mode = GET_MODE ( op1 ) ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx adj ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - <NUM_LIT> , mode ) ; REAL_ARITHMETIC ( pred_half , MINUS_EXPR , dconsthalf , half_minus_pred_half ) ;

adj = force_reg ( mode , const_double_from_real_value ( pred_half , mode ) ) ;


<s> MVT XLenVT = Subtarget -> getXLenVT ( ) ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } break ; } case <STR_LIT> : {

SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( DAG . getConstant ( <NUM_LIT> , dl , ElementType ) ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . shl ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( DAG . getConstant ( <NUM_LIT> , dl , ElementType ) ) ; continue ; } auto * ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ;

Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt ) , dl , ElementType ) ) ;


<s> SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget -> isTargetWindows ( ) || Subtarget -> isTargetMingw ( ) ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : ( Subtarget -> isTargetMingw ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ) ; SDValue ThreadPointer = DAG . getLoad ( getPointerTy ( ) , dl , Chain , TlsArray , MachinePointerInfo ( Ptr ) , false , false , false , <NUM_LIT> ) ; SDValue IDX = DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ; if ( Subtarget -> is64Bit ( ) ) IDX = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( ) , Chain , IDX , MachinePointerInfo ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; else IDX = DAG . getLoad ( getPointerTy ( ) , dl , Chain , IDX , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Scale = DAG . getConstant ( Log2_64_Ceil ( TD -> getPointerSize ( ) ) , getPointerTy ( ) ) ; IDX = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , IDX , Scale ) ;

SDValue res = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , ThreadPointer , IDX ) ;


<s> if ( SrcSize > DestSize ) { assert ( SrcSize == <NUM_LIT> && DestSize == <NUM_LIT> ) ; return CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , DestVT , Src , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ; } if ( DestSize > SrcSize ) { assert ( SrcSize == <NUM_LIT> && DestSize == <NUM_LIT> ) ; SDValue RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; const SDValue Ops [ ] = { RC , Src , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ; } assert ( SrcSize == <NUM_LIT> && DestSize == <NUM_LIT> ) ; return CurDAG -> getNode ( <STR_LIT> , DL , DestVT , Src ) . getNode ( ) ;


<s> BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( J -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( J -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . copyImplicitOps ( I ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> isBranch ( ) ) { if ( J -> isIndirectBranch ( ) ) { if ( ReturnMBB . hasAddressTaken ( ) ) OtherReference = true ; } else for ( unsigned i = <NUM_LIT> ; i < J -> getNumOperands ( ) ; ++ i ) if ( J -> getOperand ( i ) . isMBB ( ) && J -> getOperand ( i ) . getMBB ( ) == & ReturnMBB ) OtherReference = true ; } else if ( ! J -> isTerminator ( ) && ! J -> isDebugValue ( ) ) break ; if ( J == ( * PI ) -> begin ( ) ) break ; -- J ; } if ( ( * PI ) -> canFallThrough ( ) && ( * PI ) -> isLayoutSuccessor ( & ReturnMBB ) ) OtherReference = true ; if ( ! OtherReference && BlockChanged ) { PredToRemove . push_back ( * PI ) ; } if ( BlockChanged ) Changed = true ; } for ( unsigned i = <NUM_LIT> , ie = PredToRemove . size ( ) ; i != ie ; ++ i ) PredToRemove [ i ] -> removeSuccessor ( & ReturnMBB , true ) ; if ( Changed && ! ReturnMBB . hasAddressTaken ( ) ) { if ( ReturnMBB . pred_size ( ) == <NUM_LIT> ) { MachineBasicBlock & PrevMBB = * * ReturnMBB . pred_begin ( ) ; if ( PrevMBB . isLayoutSuccessor ( & ReturnMBB ) && PrevMBB . canFallThrough ( ) ) {

PrevMBB . splice ( PrevMBB . end ( ) , & ReturnMBB , I ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc DL ; bool isTailCall = false ; bool isInterrupt = false ; bool isTrap = false ; if ( MBB . end ( ) != MI ) { DL = MI -> getDebugLoc ( ) ; unsigned RetOpcode = MI -> getOpcode ( ) ; isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; isTrap = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { CalleeSavedInfo & Info = CSI [ i - <NUM_LIT> ] ; unsigned Reg = Info . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && ! isTrap && STI . hasV5TOps ( ) ) { if ( MBB . succ_empty ( ) ) { Reg = <STR_LIT> ; DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } else LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; llvm :: sort ( Regs . begin ( ) , Regs . end ( ) , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ;

if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) {


<s> <ISA_LIT>MCExpr :: VariantKind LHSVariant , RHSVariant ; const MCExpr * LHS = ExtractModifierFromExpr ( BE -> getLHS ( ) , LHSVariant ) ; const MCExpr * RHS = ExtractModifierFromExpr ( BE -> getRHS ( ) , RHSVariant ) ; if ( ! LHS && ! RHS ) return nullptr ; if ( ! LHS ) LHS = BE -> getLHS ( ) ; if ( ! RHS ) RHS = BE -> getRHS ( ) ; if ( LHSVariant == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) Variant = RHSVariant ; else if ( RHSVariant == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) Variant = LHSVariant ; else if ( LHSVariant == RHSVariant ) Variant = LHSVariant ; else return nullptr ;

return MCBinaryExpr :: Create ( BE -> getOpcode ( ) , LHS , RHS , Context ) ;


<s> return <STR_LIT> ; case <NUM_LIT> : return Opc == TargetOpcode :: G_SEXTLOAD ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> :


<s> void <ISA_LIT>InstPrinter :: print<ISA_LIT>SymbolOperand ( const MCInst * MI , uint64_t Address , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNo ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ;


<s> unsigned CC = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

unsigned regY = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( isa < FrameIndexSDNode > ( Src . getNode ( ) ) ) { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned Reg = cast < RegisterSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; EVT VT = Src . getValueType ( ) ; SDValue Copy ( DAG . getMachineNode ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , VT , Src ) , <NUM_LIT> ) ; return Op . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ? DAG . getCopyToReg ( Chain , DL , Reg , Copy ) : DAG . getCopyToReg ( Chain , DL , Reg , Copy , Op . getNumOperands ( ) == <NUM_LIT> ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ) ;


<s> if ( ! TARGET_EXPLICIT_RELOCS && mips_must_initialize_gp_p ( ) && cfun -> machine -> global_pointer != GLOBAL_POINTER_REGNUM ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ;


<s> case TYPE_FSTORESF : priority = priority << <NUM_LIT> ; break ; case TYPE_STORE : case TYPE_STM : priority = priority << <NUM_LIT> ; break ; default : break ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( BC0 . hasOneUse ( ) && SVT . isVector ( ) && SVT . getVectorNumElements ( ) * <NUM_LIT> == NumElts && TLI . isOperationLegal ( Opcode , VT ) ) { bool CanFold = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true ) ; if ( LD . getNode ( ) ) return LD ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Shuffle = PerformTargetShuffleCombine ( SDValue ( N , <NUM_LIT> ) , DAG , DCI , Subtarget ) ; if ( Shuffle . getNode ( ) ) return Shuffle ; SmallVector < int , <NUM_LIT> > NonceMask ;


<s> if ( current_frame_info . save_fp ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , frame_pointer_rtx ) ) ; gmask &= ~ ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) ; for ( regno = <NUM_LIT> ; regno <= M32R_MAX_INT_REGS ; ++ regno ) { if ( ( gmask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , regno ) ) ) ; } if ( current_frame_info . save_lr ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ) ; frame_size = ( current_frame_info . total_size - ( current_frame_info . pretend_size + current_frame_info . reg_size ) ) ; if ( frame_size == <NUM_LIT> ) ; else if ( frame_size <= <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - frame_size ) ) ) ; else { rtx tmp = gen_rtx_REG ( Pmode , PROLOGUE_TMP_REGNUM ) ; emit_insn ( gen_movsi ( tmp , GEN_INT ( frame_size ) ) ) ; emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; }


<s> bool <ISA_LIT>InstrInfo :: transformToNewImmFormFedByAdd ( MachineInstr & MI , MachineInstr & DefMI , unsigned OpNoForForwarding ) const { MachineRegisterInfo * MRI = & MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; bool PostRA = ! MRI -> isSSA ( ) ; if ( PostRA ) return false ; if ( ! MI . mayLoadOrStore ( ) ) return false ; unsigned XFormOpcode = RI . getMappedIdxOpcForImmOpc ( MI . getOpcode ( ) ) ; assert ( ( XFormOpcode != <STR_LIT> ) && <STR_LIT> ) ; ImmInstrInfo III ; bool IsVFReg = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; if ( ! instrHasImmForm ( XFormOpcode , IsVFReg , III , PostRA ) ) return false ; if ( ! III . IsSummingOperands ) return false ; if ( OpNoForForwarding != III . OpNoForForwarding ) return false ; MachineOperand ImmOperandMI = MI . getOperand ( III . ImmOpNo ) ; if ( ! ImmOperandMI . isImm ( ) ) return false ; MachineOperand * ImmMO = nullptr ; MachineOperand * RegMO = nullptr ; if ( ! isDefMIElgibleForForwarding ( DefMI , III , ImmMO , RegMO ) ) return false ; assert ( ImmMO && RegMO && <STR_LIT> ) ; int64_t ImmBase = ImmOperandMI . getImm ( ) ; int64_t Imm = <NUM_LIT> ; if ( ! isImmElgibleForForwarding ( * ImmMO , DefMI , III , Imm , ImmBase ) ) return false ; unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; if ( MI . getOperand ( III . OpNoForForwarding ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( III . OpNoForForwarding ) . getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> SDValue MultLo = ADDCNode -> getOperand ( <NUM_LIT> ) ; SDNode * MultNode = MultHi . getNode ( ) ; unsigned MultOpc = MultHi . getOpcode ( ) ; if ( MultLo . getNode ( ) != MultNode ) return false ; if ( MultOpc != <STR_LIT> && MultOpc != <STR_LIT> ) return false ; if ( MultHi . getResNo ( ) != <NUM_LIT> || MultLo . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! MultHi . hasOneUse ( ) || ! MultLo . hasOneUse ( ) ) return false ; SDLoc DL ( ADDENode ) ; SDValue ACCIn = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , ADDCNode -> getOperand ( <NUM_LIT> ) , ADDENode -> getOperand ( <NUM_LIT> ) ) ; MultOpc = MultOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MAdd = CurDAG -> getNode ( MultOpc , DL , <STR_LIT> , MultNode -> getOperand ( <NUM_LIT> ) , MultNode -> getOperand ( <NUM_LIT> ) , ACCIn ) ; if ( ! SDValue ( ADDCNode , <NUM_LIT> ) . use_empty ( ) ) { SDValue LoOut = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , MAdd ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( ADDCNode , <NUM_LIT> ) , LoOut ) ; }

if ( ! SDValue ( ADDENode , <NUM_LIT> ) . use_empty ( ) ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> break ; case <STR_LIT> : DecodeMOVLHPSMask ( NumElems , Mask ) ; IsUnary = IsFakeUnary = N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePALIGNRMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; break ; case <STR_LIT> : case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFHWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : ImmN = N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) ; DecodePSHUFLWMask ( VT , cast < ConstantSDNode > ( ImmN ) -> getZExtValue ( ) , Mask ) ; IsUnary = true ; break ; case <STR_LIT> : { IsUnary = true ; SDValue MaskNode = N -> getOperand ( <NUM_LIT> ) ; while ( MaskNode -> getOpcode ( ) == <STR_LIT> ) MaskNode = MaskNode -> getOperand ( <NUM_LIT> ) ; if ( MaskNode -> getOpcode ( ) == <STR_LIT> ) { EVT VT = MaskNode . getValueType ( ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; if ( ! VT . isInteger ( ) ) return false ; int NumBytesPerElement = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < uint64_t , <NUM_LIT> > RawMask ; for ( int i = <NUM_LIT> , e = MaskNode -> getNumOperands ( ) ; i < e ; ++ i ) { SDValue Op = MaskNode -> getOperand ( i ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { RawMask . push_back ( ( uint64_t ) SM_SentinelUndef ) ; continue ; } auto * CN = dyn_cast < ConstantSDNode > ( Op . getNode ( ) ) ; if ( ! CN ) return false ; APInt MaskElement = CN -> getAPIntValue ( ) ; for ( int j = <NUM_LIT> ; j < NumBytesPerElement ; ++ j ) { RawMask . push_back ( MaskElement . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ) ; MaskElement = MaskElement . lshr ( <NUM_LIT> ) ; } } DecodePSHUFBMask ( RawMask , Mask ) ; break ; }

auto * MaskLoad = dyn_cast < LoadSDNode > ( MaskNode ) ;


<s> if ( ! SVOp -> getSimpleValueType ( <NUM_LIT> ) . is128BitVector ( ) ) return false ; if ( isVectorShiftLeft ( SVOp , DAG , isLeft , ShVal , ShAmt ) || isVectorShiftRight ( SVOp , DAG , isLeft , ShVal , ShAmt ) ) return true ; return false ;


<s> static bool IsKernelFunction ( const Function & F ) { return F . getCallingConv ( ) == CallingConv :: SPIR_KERNEL ;


<s> void setCalleeSavedFrameSize ( unsigned bytes ) { CalleeSavedFrameSize = bytes ;


<s> SDLoc DL ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset , OpFlags ) ; if ( <STR_LIT> ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue ( ) ; return Value == <NUM_LIT> || Value == <NUM_LIT> ;


<s> explicit SlotWithTag ( const MachineInstr & MI ) : FI ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ) , Tag ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) {


<s> builtin_define ( <STR_LIT> ) ; def_or_undef_macro ( pfile , NAME , CONDITION ) ; builtin_define_with_int_value ( <STR_LIT> , arc_tp_regno ) ;


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> if ( BoundCtrl == <NUM_LIT> ) { BoundCtrl = <NUM_LIT> ;


<s> Tmp3 = DAG . getStore ( VAList . getValue ( <NUM_LIT> ) , dl , Tmp3 , Node -> getOperand ( <NUM_LIT> ) , MachinePointerInfo ( V ) , false , false , <NUM_LIT> ) ; return DAG . getLoad ( VT , dl , Tmp3 , VAList , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> const DataLayout & DL = M . getDataLayout ( ) ; bool Changed = false ; if ( ! SuperAlignLDSGlobals ) { return Changed ; } for ( auto & GV : M . globals ( ) ) { if ( GV . getType ( ) -> getPointerAddressSpace ( ) != <ISA_LIT>AS :: LOCAL_ADDRESS ) { continue ; } if ( ! GV . hasInitializer ( ) ) { continue ; } Align Alignment = <STR_LIT> ( DL , & GV ) ; TypeSize GVSize = DL . getTypeAllocSize ( GV . getValueType ( ) ) ; if ( GVSize > <NUM_LIT> ) { Alignment = std :: max ( Alignment , Align ( <NUM_LIT> ) ) ; } else if ( GVSize > <NUM_LIT> ) { Alignment = std :: max ( Alignment , Align ( <NUM_LIT> ) ) ; } else if ( GVSize > <NUM_LIT> ) { Alignment = std :: max ( Alignment , Align ( <NUM_LIT> ) ) ; } else if ( GVSize > <NUM_LIT> ) { Alignment = std :: max ( Alignment , Align ( <NUM_LIT> ) ) ; } if ( Alignment != <STR_LIT> ( DL , & GV ) ) { Changed = true ; GV . setAlignment ( Alignment ) ; } } return Changed ;


<s> } else if ( B == & <STR_LIT> || B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } break ; case <STR_LIT> : if ( B == & <STR_LIT> ) { if ( A -> getSize ( ) == <NUM_LIT> || A -> getSize ( ) == <NUM_LIT> ) return A ; } else if ( B == & <STR_LIT> ) { if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; else if ( A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> || A == & <STR_LIT> ) return & <STR_LIT> ; } else if ( B == & <STR_LIT> ) {