<s> if ( CByte ) { uint64_t ByteVal = CByte -> getZExtValue ( ) ; if ( ByteVal == <NUM_LIT> || ByteVal == <NUM_LIT> ? Bytes <= <NUM_LIT> && countPopulation ( Bytes ) <= <NUM_LIT> : Bytes <= <NUM_LIT> ) { unsigned Size1 = Bytes == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << findLastSet ( Bytes ) ; unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Alignment . value ( ) , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( ( unsigned ) Alignment . value ( ) , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , Alignment ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue Chain2 = DAG . getStore ( Chain , DL , Byte , Dst2 , DstPtrInfo . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } }

assert ( Bytes >= <NUM_LIT> && <STR_LIT> ) ;


<s> uint64_t SplatUndefZ = SplatUndef . getZExtValue ( ) ; uint64_t Lower = ( SplatUndefZ & ( ( uint64_t ( <NUM_LIT> ) << findFirstSet ( SplatBitsZ ) ) - <NUM_LIT> ) ) ; uint64_t Upper = ( SplatUndefZ & ~ ( ( uint64_t ( <NUM_LIT> ) << findLastSet ( SplatBitsZ ) ) - <NUM_LIT> ) ) ; uint64_t Value = SplatBitsZ | Upper | Lower ; SDValue Op = tryBuildVectorReplicate ( DAG , TII , DL , VT , Value , SplatBitSize ) ; if ( Op . getNode ( ) ) return Op ; uint64_t Middle = SplatUndefZ & ~ Upper & ~ Lower ; Value = SplatBitsZ | Middle ; Op = tryBuildVectorReplicate ( DAG , TII , DL , VT , Value , SplatBitSize ) ;


<s> return __builtin_aarch64_frint32xsf ( __a ) ;


<s> if ( <STR_LIT> ( * getGlobalSTI ( ) ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ;

getTargetStreamer ( ) -> EmitCodeEnd ( ) ;


<s> getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { s32 , p0 } , { s1 } ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s1 } ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalForCartesianProduct ( { s1 } , { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; auto & PhiBuilder = getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FCONSTANT , G_FNEG } ) . legalFor ( { s32 , s64 } ) ; LoadStoreBuilder . legalFor ( { { s64 , p0 } } ) ; PhiBuilder . legalFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s1 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_MERGE_VALUES ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_UNMERGE_VALUES ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( { G_FPTOSI , G_FPTOUI } ) . legalForCartesianProduct ( { s32 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_SITOFP , G_UITOFP } ) . legalForCartesianProduct ( { s32 , s64 } , { s32 } ) ; } else { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) . libcallFor ( { s32 , s64 } ) ; LoadStoreBuilder . maxScalar ( <NUM_LIT> , s32 ) ; for ( auto Ty : { s32 , s64 } ) setAction ( { G_FNEG , Ty } , Lower ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . customFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . customForCartesianProduct ( { s1 } , { s32 , s64 } ) ; if ( AEABI ( ST ) ) setFCmpLibcallsAEABI ( ) ; else setFCmpLibcallsGNU ( ) ; getActionDefinitionsBuilder ( G_FPEXT ) . libcallFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . libcallFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( { G_FPTOSI , G_FPTOUI } ) . libcallForCartesianProduct ( { s32 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_SITOFP , G_UITOFP } ) . libcallForCartesianProduct ( { s32 , s64 } , { s32 } ) ;


<s> if ( found ) { if ( base != <STR_LIT> && Inst -> definesRegister ( base , RI ) ) { found = false ; } if ( index != <STR_LIT> && Inst -> definesRegister ( index , RI ) ) { found = false ; }


<s> int vec_pos = <NUM_LIT> ; rtx call = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; rtx tmp_retval = retval ; if ( retval ) { if ( ! nvptx_register_operand ( retval , GET_MODE ( retval ) ) ) tmp_retval = gen_reg_rtx ( GET_MODE ( retval ) ) ; call = gen_rtx_SET ( tmp_retval , call ) ; } XVECEXP ( pat , <NUM_LIT> , vec_pos ++ ) = call ; for ( rtx arg = cfun -> machine -> call_args ; arg ; arg = XEXP ( arg , <NUM_LIT> ) ) XVECEXP ( pat , <NUM_LIT> , vec_pos ++ ) = gen_rtx_USE ( VOIDmode , XEXP ( arg , <NUM_LIT> ) ) ; if ( varargs ) XVECEXP ( pat , <NUM_LIT> , vec_pos ++ ) = gen_rtx_USE ( VOIDmode , varargs ) ; gcc_assert ( vec_pos = XVECLEN ( pat , <NUM_LIT> ) ) ; nvptx_emit_forking ( parallel , true ) ; emit_call_insn ( pat ) ;

nvptx_emit_joining ( parallel , true ) ;


<s> NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; if ( ! isThumb ) BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; else BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) . add ( predOps ( <STR_LIT> ) ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; for ( MCPhysReg L : LRs ) if ( ! MRI . isReserved ( L ) ) NewBB -> addLiveIn ( L ) ; MF -> RenumberBlocks ( NewBB ) ; BBUtils -> insert ( NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = llvm :: lower_bound ( WaterList , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ;

if ( WaterBB == OrigBB ) WaterList . insert ( std :: next ( IP ) , NewBB ) ;


<s> SDValue Val = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ;


<s> SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( UseGPRForF64 && XLen == <NUM_LIT> && ValVT == <STR_LIT> ) { assert ( ! ArgFlags . isSplit ( ) && PendingLocs . empty ( ) && <STR_LIT> ) ; Register Reg = State . AllocateReg ( ArgGPRs ) ; LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } Register Reg ; if ( ValVT == <STR_LIT> && ! UseGPRForF32 ) Reg = State . AllocateReg ( ArgFPR32s , ArgFPR64s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF16 ) Reg = State . AllocateReg ( ArgFPR16s , ArgFPR64s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s , ArgFPR32s ) ; else if ( ValVT . isScalableVector ( ) ) { switch ( ValVT . getSizeInBits ( ) . getKnownMinSize ( ) ) { case <NUM_LIT> :


return ( uint64x1_t ) { __builtin_aarch64_usqadddi_uus ( __a [ <NUM_LIT> ] , __b [ <NUM_LIT> ] ) } ;


res . as_int [ <NUM_LIT> ] = m . as_int [ <NUM_LIT> ] >> __count ;


<s> if ( GET_CODE ( op ) == REG ) op = op2 ; gcc_assert ( GET_CODE ( op ) != REG ) ; size = GET_MODE_SIZE ( GET_MODE ( op ) ) ; operand_length = h8300_classify_operand ( op , size , & opclass ) ; switch ( opclass ) { case H8OP_MEM_BASE : case H8OP_MEM_ABSOLUTE : case H8OP_MEM_COMPLEX :


<s> ExtReg = RootDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Ext == <STR_LIT> && MRI . getType ( ExtReg ) . getSizeInBits ( ) == <NUM_LIT> ) { MachineInstr * ExtInst = MRI . getVRegDef ( ExtReg ) ; if ( ExtInst && isDef32 ( * ExtInst ) ) return None ; } } MachineIRBuilder MIB ( * RootDef ) ; ExtReg = moveScalarRegClass ( ExtReg , <STR_LIT> , MIB ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( ExtReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( getArithExtendImm ( Ext , ShiftVal ) ) ; } } } ;


<s> void <ISA_LIT>AssemblerImpl :: freeClassObjectBuffer ( ) { if ( classObjectBuffer ) free ( classObjectBuffer ) ; classObjectBuffer = nullptr ;


<s> Char = DAG . getZExtOrTrunc ( Char , DL , <STR_LIT> ) ; Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , Char ) ;

SDValue CCReg = End . getValue ( <NUM_LIT> ) ;


<s> static int mcore_ior_cost ( rtx x ) { int val ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ;

val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ;


<s> struct spu_builtin_description * desc ; tree match = NULL_TREE ; gcc_assert ( ! flag_preprocess_only ) ; desc = & spu_builtins [ fcode ] ; if ( desc -> type != B_OVERLOAD ) return NULL_TREE ; for ( new_fcode = fcode + <NUM_LIT> ; spu_builtins [ new_fcode ] . type == B_INTERNAL ; new_fcode ++ ) { tree decl = targetm . builtin_decl ( new_fcode , true ) ; tree params = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; tree param ; bool all_scalar ; unsigned int p ; all_scalar = true ; for ( param = params ; param != void_list_node ; param = TREE_CHAIN ( param ) ) if ( ! SCALAR_TYPE_P ( TREE_VALUE ( param ) ) ) all_scalar = false ; for ( param = params , p = <NUM_LIT> ;


<s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ;

SDValue OutOps [ ] = { OutLo , OutHi } ;


<s> return Impl -> parseFuncName ( MangledName ) ;


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> Register getQueuePtrUserSGPR ( ) const {

return ArgInfo . QueuePtr . getRegister ( ) ;


<s> for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) >= <NUM_LIT> ) NonLibcallCSI . push_back ( CS ) ; return NonLibcallCSI ;


<s> bool isMTBUF ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ;


<s> return gen_rtx_REG ( ( ( GET_MODE_CLASS ( TYPE_MODE ( valtype ) ) == MODE_INT && GET_MODE_SIZE ( TYPE_MODE ( valtype ) ) < <NUM_LIT> && ( TREE_CODE ( valtype ) == INTEGER_TYPE || TREE_CODE ( valtype ) == ENUMERAL_TYPE || TREE_CODE ( valtype ) == BOOLEAN_TYPE || TREE_CODE ( valtype ) == REAL_TYPE || TREE_CODE ( valtype ) == OFFSET_TYPE ) ) && sh_promote_prototypes ( fn_decl_or_type ) ? SImode : TYPE_MODE ( valtype ) ) , BASE_RETURN_VALUE_REG ( TYPE_MODE ( valtype ) ) ) ;


<s> unsigned <ISA_LIT>BranchFixup :: getOffsetOf ( MachineInstr * MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned Offset = BBInfo [ MBB -> getNumber ( ) ] . Offset ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) ; & * I != MI ; ++ I ) { assert ( I != MBB -> end ( ) && <STR_LIT> ) ;

Offset += TII -> getInstSizeInBytes ( * I ) ;


<s> } if ( expand_set_cint32_one_inst ( temp , val << leading_zeroes , three_wide_only ) ) { emit_move_insn ( dest_reg , gen_rtx_LSHIFTRT ( SImode , temp , GEN_INT ( leading_zeroes ) ) ) ; return ; } for ( count = <NUM_LIT> ; count < <NUM_LIT> ; count ++ ) { HOST_WIDE_INT r = rotate_right ( val , count ) ; if ( expand_set_cint32_one_inst ( temp , r , three_wide_only ) ) { emit_move_insn ( dest_reg , gen_rtx_ROTATE ( SImode , temp , GEN_INT ( count ) ) ) ; return ; } } if ( lower == trunc_int_for_mode ( lower , QImode ) ) {


<s> static const <ISA_LIT>MCExpr * CreateHi ( const MCExpr * Expr , MCContext & Ctx ) {

return Create ( VK_<ISA_LIT>_HI , Expr , Ctx ) ;


<s> for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( AInfo , ArgInfos , DL , MF . getRegInfo ( ) ) ; Idx ++ ; } FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ;

return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ;


<s> if ( LoopFixer ( MF , MLI , nullptr ) . run ( ) ) { return true ; } SmallVector < MachineLoop * , <NUM_LIT> > Worklist ( MLI . begin ( ) , MLI . end ( ) ) ; while ( ! Worklist . empty ( ) ) { MachineLoop * Loop = Worklist . pop_back_val ( ) ; Worklist . append ( Loop -> begin ( ) , Loop -> end ( ) ) ; if ( LoopFixer ( MF , MLI , Loop ) . run ( ) ) {


return Kind == Memory && getMemBaseReg ( ) == <STR_LIT> && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> ;


<s> bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getFnAttributes ( ) . hasAttribute ( Attributes :: StackAlignment ) ) ; if ( ForceStackAlign ) return canRealignStack ( MF ) ;

return requiresRealignment && canRealignStack ( MF ) ;


<s> for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] != i ) return false ; return true ;


<s> unsigned NumUsedVgprsKey = getScratchSizeKey ( CC ) + PALMD :: Key :: VS_NUM_USED_VGPRS - PALMD :: Key :: VS_SCRATCH_<ISA_LIT>ZE ; setRegister ( NumUsedVgprsKey , Val ) ; return ; }

getHwStage ( CC ) [ <STR_LIT> ] = MsgPackDoc . getNode ( Val ) ;


<s> if ( SDValue V = lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; if ( V2 . isUndef ( ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; }

if ( Subtarget . hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ;


<s> unsigned TIDIGXReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGYReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGZReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned InputPtrReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; getAddNoCarry ( Entry , Insert , DL , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = i / NumElts ; else WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != j + WhichResult ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != j + WhichResult ) ) return false ; }


<s> SDValue T = DAG . getNode ( <STR_LIT> , dl , RegVT , Copy , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) ) ; Copy = DAG . getSetCC ( dl , <STR_LIT> , T , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) , <STR_LIT> ) ; } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> uint32x4_t result = vcombine_u32 ( a , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) : ) ;


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , OpNum , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; assert ( ( ( OffImm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( OffImm != <NUM_LIT> ) O << <STR_LIT> ;

if ( OffImm != <NUM_LIT> && UseMarkup ) O << <STR_LIT> ;


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ;


<s> Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ; OldPacket . resize ( SchedModel -> getIssueWidth ( ) ) ; OldPacket . clear ( ) ; ResourcesModel -> clearResources ( ) ;


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; bool NeedsStackRealignment = RegInfo . needsStackRealignment ( MF ) ; if ( ! NeedsStackRealignment && MFI . getMaxAlignment ( ) > getStackAlignment ( ) ) report_fatal_error ( <STR_LIT> + Twine ( MF . getName ( ) ) + <STR_LIT> <STR_LIT> <STR_LIT> ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) NumBytes += MFI . getMaxCallFrameSize ( ) ; NumBytes = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; if ( MFI . getMaxAlignment ( ) > <NUM_LIT> ) { NumBytes = alignTo ( NumBytes , MFI . getMaxAlignment ( ) ) ; } MFI . setStackSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ;

unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ;


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; return DAG . getLoad ( <STR_LIT> , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Register LoVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , LoVReg ) ; SDValue Lo = DAG . getCopyFromReg ( Chain , DL , LoVReg , <STR_LIT> ) ; SDValue Hi ; if ( VA . getLocReg ( ) == <STR_LIT> ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; Hi = DAG . getLoad ( <STR_LIT> , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } else { Register HiVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) + <NUM_LIT> , HiVReg ) ; Hi = DAG . getCopyFromReg ( Chain , DL , HiVReg , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT , FS , Options ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) {


<s>
CellMap
Outputs
;
bool
Eval
=
MCE
.
evaluate
(
MI
,
Cells
,
Outputs
)
;
LLVM_DEBUG
(
{
if
(
Eval
)
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
&
I
:
Outputs
)
dbgs
(
)
<<
' '
<<
I
.
second
;
dbgs
(
)
<<
'\n'
;
}
}
)
;
for
(
const
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
!
MO
.
isReg
(
)
||
!
MO
.
isDef
(
)
)
continue
;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const {


<s> assert ( ( I == nullptr || I -> getOpcode ( ) == Opcode ) && <STR_LIT> ) ; const bool SCost = ( CostKind == TTI :: TCK_CodeSize || CostKind == TTI :: TCK_SizeAndLatency ) ; const int CBrCost = SCost ? <NUM_LIT> : <NUM_LIT> ; switch ( Opcode ) { case Instruction :: Br : { auto BI = dyn_cast_or_null < BranchInst > ( I ) ; if ( BI && BI -> isUnconditional ( ) ) return SCost ? <NUM_LIT> : <NUM_LIT> ; return CBrCost ; } case Instruction :: Switch : { auto <ISA_LIT> = dyn_cast_or_null < SwitchInst > ( I ) ; return ( <ISA_LIT> ? ( <ISA_LIT> -> getNumCases ( ) + <NUM_LIT> ) : <NUM_LIT> ) * ( CBrCost + <NUM_LIT> ) ; } case Instruction :: Ret : return SCost ? <NUM_LIT> : <NUM_LIT> ; case Instruction :: PHI : return <NUM_LIT> ;


<s> CV . push_back ( C ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; if ( VT . isVector ( ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ) ) ; } else {

return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , Mask ) ;


<s> unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPEMI -> eraseFromParent ( ) ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; BBUtils -> adjustBBSize ( CPEBB , - Size ) ; if ( CPEBB -> empty ( ) ) { BBInfo [ CPEBB -> getNumber ( ) ] . Size = <NUM_LIT> ;

CPEBB -> setAlignment ( Align :: None ( ) ) ;


<s> BranchInst * Term = cast < BranchInst > ( ( * PI ) -> getTerminator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Term -> getNumSuccessors ( ) ; i != e ; ++ i ) {

BasicBlock * Succ = Term -> getSuccessor ( i ) ;


<s> if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) SRE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; else SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; assert ( Kind == MCSymbolRefExpr :: VK_None ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getParamSymbol ( SelectionDAG & DAG , int idx , EVT v ) const { std :: string ParamSym ; raw_string_ostream ParamStr ( ParamSym ) ; ParamStr << DAG . getMachineFunction ( ) . getName ( ) << <STR_LIT> << idx ; ParamStr . flush ( ) ;

std :: string * SavedStr = nvTM -> getManagedStrPool ( ) -> getManagedString ( ParamSym . c_str ( ) ) ;


<s> if ( OverrideBalance != <NUM_LIT> ) return OverrideBalance == <NUM_LIT> ? Color :: Even : Color :: Odd ; return LastColor ;


<s> nVT <= <STR_LIT> ; ++ nVT ) { EVT SVT = ( <STR_LIT> ) nVT ; if ( isTypeLegal ( SVT ) && SVT . getVectorElementType ( ) == EltVT && SVT . getVectorNumElements ( ) > NElts ) return SVT ; }


<s> bool <ISA_LIT>16RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ;


<s> const LDSymbol * getGOTSymbol ( ) const {


<s> fprintf ( file , <STR_LIT> , h8_reg_names [ REGNO ( XEXP ( addr , <NUM_LIT> ) ) ] ) ; break ; case PLUS : fprintf ( file , <STR_LIT> ) ; index = h8300_get_index ( XEXP ( addr , <NUM_LIT> ) , VOIDmode , & size ) ; if ( GET_CODE ( index ) == REG ) { h8300_print_operand_address ( file , XEXP ( addr , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ; switch ( size ) { case <NUM_LIT> : h8300_print_operand_address ( file , index ) ; break ; case <NUM_LIT> : h8300_print_operand ( file , index , 'X' ) ; fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : h8300_print_operand ( file , index , 'T' ) ; fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : h8300_print_operand ( file , index , 'S' ) ; fputs ( <STR_LIT> , file ) ; break ; } } else { h8300_print_operand_address ( file , XEXP ( addr , <NUM_LIT> ) ) ;


<s> bool noOddSPReg ( ) const { return ! UseOddSPReg ;


<s> if ( get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER7 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_CR_LOGICAL : case TYPE_MFCR : case TYPE_MFCRF : case TYPE_MTCR : case TYPE_DIV : case TYPE_ISYNC : case TYPE_LOAD_L : case TYPE_STORE_C : case TYPE_MFJMPR : case TYPE_MTJMPR : return true ; case TYPE_MUL : case TYPE_SHIFT : case TYPE_EXTS : if ( get_attr_dot ( insn ) == DOT_YES ) return true ; else break ; case TYPE_LOAD : if ( get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES || get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; case TYPE_STORE : case TYPE_FPLOAD : case TYPE_FPSTORE : if ( get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER8 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_CR_LOGICAL : case TYPE_MFCR : case TYPE_MFCRF : case TYPE_MTCR : case TYPE_SYNC : case TYPE_ISYNC : case TYPE_LOAD_L : case TYPE_STORE_C : case TYPE_VECSTORE : case TYPE_MFJMPR : case TYPE_MTJMPR : return true ; case TYPE_SHIFT : case TYPE_EXTS : case TYPE_MUL : if ( get_attr_dot ( insn ) == DOT_YES ) return true ; else break ; case TYPE_LOAD : if ( get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES || get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; case TYPE_STORE : if ( get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) return true ; else break ; default : break ; } break ; default : break ;


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; auto InsertPt = MI . getIterator ( ) ; DebugLoc Loc = MI . getDebugLoc ( ) ; if ( FenceCallAndRet ) { if ( MI . isReturn ( ) ) return ; BuildMI ( MBB , std :: next ( InsertPt ) , Loc , TII -> get ( <STR_LIT> ) ) ; ++ NumInstsInserted ; ++ NumLFENCEsInserted ; return ; } unsigned StateReg = PS -> SSA . GetValueAtEndOfBlock ( & MBB ) ; mergePredStateIntoSP ( MBB , InsertPt , Loc , StateReg ) ; if ( MI . isReturn ( ) || ( std :: next ( InsertPt ) == MBB . end ( ) && MBB . succ_empty ( ) ) ) return ; MCSymbol * RetSymbol = MF . getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; MI . setPostInstrSymbol ( MF , RetSymbol ) ; const TargetRegisterClass * AddrRC = & <STR_LIT> ; unsigned ExpectedRetAddrReg = <NUM_LIT> ; if ( ! Subtarget -> getFrameLowering ( ) -> has128ByteRedZone ( MF ) || MF . exposesReturnsTwice ( ) ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addSym ( RetSymbol ) ; } else { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; } } ++ InsertPt ; if ( ! ExpectedRetAddrReg ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } unsigned NewStateReg = extractPredStateFromSP ( MBB , InsertPt , Loc ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addSym ( RetSymbol ) ; } else { unsigned ActualRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ActualRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ;

BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addReg ( ActualRetAddrReg , RegState :: Kill ) ;


<s> func_ptr * p ; for ( p = __CTOR_END__ - <NUM_LIT> ; * p != ( func_ptr ) - <NUM_LIT> ; p -- ) ( * p ) ( ) ;


<s> bool <ISA_LIT>AsmPrinter :: UseReadOnlyJumpTables ( ) const { return Subtarget -> isTargetNaCl ( ) ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * <NUM_LIT> ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ;


<s> if ( N . getOpcode ( ) != <STR_LIT> ) return false ; const SDValue LHS = N . getOperand ( <NUM_LIT> ) ; const SDValue RHS = N . getOperand ( <NUM_LIT> ) ; if ( Scale == <NUM_LIT> ) { Base = LHS ; Offset = RHS ; return true ; } if ( auto C = dyn_cast < ConstantSDNode > ( RHS ) ) { int64_t ImmOff = C -> getSExtValue ( ) ; unsigned Size = <NUM_LIT> << Scale ; if ( ImmOff % Size ) return false ; SDLoc DL ( N ) ; Base = LHS ; Offset = CurDAG -> getTargetConstant ( ImmOff >> Scale , DL , <STR_LIT> ) ; SDValue Ops [ ] = { Offset } ;

SDNode * MI = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ;


<s> assert ( NOps == <NUM_LIT> ) ; O << '\t' << MAI -> getCommentString ( ) << <STR_LIT> ; DIVariable V ( const_cast < MDNode * > ( MI -> getOperand ( NOps - <NUM_LIT> ) . getMetadata ( ) ) ) ; O << V . getName ( ) ; O << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; O << '[' ; printOperand ( MI , <NUM_LIT> , O ) ; O << '+' ; printOperand ( MI , <NUM_LIT> , O ) ; O << ']' ; O << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> , O ) ; OutStreamer . EmitRawText ( O . str ( ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : {

Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this , Subtarget . isDarwin ( ) ) ;


<s> return ( __m256 ) __builtin_ia32_cvtdq2ps256_mask ( ( __v8si ) __A , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT> ) ) return false ; } return true ;


<s> VisitedBBInfo ( bool HasReturn , unsigned int Cycles ) : HasReturn ( HasReturn ) , Cycles ( Cycles ) {


<s> return __builtin_neon_vaddv8hf ( __a , __b ) ;


<s> } if ( ! AlwaysInline && ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; const unsigned ClobberSet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget . is64Bit ( ) ? <STR_LIT> :


<s> Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB -> copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) { MIB . addReg ( <NUM_LIT> ) ;

MIB . addImm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; bool IsLittleEndian = TT . getArch ( ) == Triple :: ppc64le ;

return new ELF<ISA_LIT>AsmBackend ( T , IsLittleEndian , OSABI ) ;


<s> rtx sh_gen_truncate ( machine_mode mode , rtx x , int need_sign_ext ) { enum rtx_code code = TRUNCATE ; if ( GET_CODE ( x ) == ZERO_EXTEND || GET_CODE ( x ) == SIGN_EXTEND ) { rtx inner = XEXP ( x , <NUM_LIT> ) ; machine_mode inner_mode = GET_MODE ( inner ) ; if ( inner_mode == mode ) return inner ;

else if ( GET_MODE_SIZE ( inner_mode ) >= GET_MODE_SIZE ( mode ) ) x = inner ;


<s> MVT VT = Op -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; SDLoc dl ( Op ) ; if ( ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask1 [ <NUM_LIT> ] ) ;

SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ;


<s> return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) && getMemIndexReg ( ) >= <STR_LIT> && getMemIndexReg ( ) <= <STR_LIT> ;


<s> if ( ! CInfo . Metadata ) report_fatal_error ( <STR_LIT> ) ; CInfo . AccessIndex = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ; CInfo . Base = Call -> getArgOperand ( <NUM_LIT> ) ; CInfo . RecordAlignment = DL -> getABITypeAlign ( getBaseElementType ( Call ) ) ; return true ; } if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { CInfo . Kind = <ISA_LIT>PreserveFieldInfoAI ; CInfo . Metadata = nullptr ; uint64_t InfoKind = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ; if ( InfoKind >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; CInfo . AccessIndex = InfoKind ; return true ; } if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { CInfo . Kind = <ISA_LIT>PreserveFieldInfoAI ; CInfo . Metadata = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; if ( ! CInfo . Metadata ) report_fatal_error ( <STR_LIT> ) ; uint64_t Flag = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ; if ( Flag >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Flag == <STR_LIT> ) CInfo . AccessIndex = <STR_LIT> ; else CInfo . AccessIndex = <STR_LIT> ; return true ; }


<s> if ( mode == SImode ) fn = gen_store_conditional_si ; else if ( mode == DImode ) fn = gen_store_conditional_di ; emit_insn ( fn ( res , mem , val ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < PrevPacket . size ( ) ; i ++ ) { SUnit * SU1 = PrevPacket [ i ] ; MachineInstr * PMI = SU1 -> getInstr ( ) ; if ( <ISA_LIT>II :: isLookupC ( PMI -> getDesc ( ) ) ) { LookupPrev = true ; break ; } } for ( unsigned i = <NUM_LIT> ; i < CurrentPacket . size ( ) ; i ++ ) { SUnit * SU1 = CurrentPacket [ i ] ; MachineInstr * PMI = SU1 -> getInstr ( ) ; if ( <ISA_LIT>II :: isLookupC ( PMI -> getDesc ( ) ) ) { LookupPrev = true ; break ; } } if ( LookupPrev && ( ! <ISA_LIT>II :: isVPUInst ( MI -> getDesc ( ) ) || isUsingSrcD ( MI ) || <ISA_LIT>II :: isLookupC ( MI -> getDesc ( ) ) ) ) { res = Hazard ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return res ;


<s> inline vector unsigned char vec_andc ( vector unsigned char a1 , vector unsigned char a2 ) {

return ( vector unsigned char ) __builtin_altivec_vandc ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI64Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; } } Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else { short SImm ;

if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( SImm & <NUM_LIT> , dl ) ) , <NUM_LIT> ) ;


<s> case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : return Helper . tryCombineExtendingLoads ( MI ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned MaxLen = EnableOpt ? <NUM_LIT> : <NUM_LIT> ; return ( ! EnableOptSize ) ? Helper . tryCombineMemCpyFamily ( MI , MaxLen ) : false ; } default : break ;


<s> enum reg_class class_likely_spilled_p ( int c ) { return ( c != ALL_REGS && c != ADDW_REGS ) ;


<s> using RegisterInductionSet = std :: set < RegisterInduction > ; RegisterInductionSet IndRegs ; using instr_iterator = MachineBasicBlock :: instr_iterator ; for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * Phi = & * I ; for ( unsigned i = <NUM_LIT> , n = Phi -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { if ( Phi -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) != Latch ) continue ; unsigned PhiReg = Phi -> getOperand ( i ) . getReg ( ) ; MachineInstr * DI = MRI -> getVRegDef ( PhiReg ) ; if ( DI -> getDesc ( ) . isAdd ( ) ) { unsigned IndReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Opnd2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V ; if ( MRI -> getVRegDef ( IndReg ) == Phi && checkForImmediate ( Opnd2 , V ) ) { unsigned UpdReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; IndRegs . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; } } } } if ( IndRegs . empty ( ) ) return false ; MachineBasicBlock * TB = nullptr , * FB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; if ( NotAnalyzed || Cond . empty ( ) ) return false ; if ( ExitingBlock != Latch && ( TB == Latch || FB == Latch ) ) { MachineBasicBlock * LTB = nullptr , * LFB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > LCond ; bool NotAnalyzed = TII -> analyzeBranch ( * Latch , LTB , LFB , LCond , false ) ; if ( NotAnalyzed ) return false ; if ( TB == Latch ) TB = ( LTB == Header ) ? LTB : LFB ; else FB = ( LTB == Header ) ? LTB : LFB ; } if ( TB != Header ) { if ( FB != Header ) { return false ; } if ( MDT -> dominates ( TB , FB ) ) return false ; } unsigned CSz = Cond . size ( ) ; if ( CSz != <NUM_LIT> && CSz != <NUM_LIT> ) return false ; if ( ! Cond [ CSz - <NUM_LIT> ] . isReg ( ) ) return false ; unsigned P = Cond [ CSz - <NUM_LIT> ] . getReg ( ) ; MachineInstr * PredDef = MRI -> getVRegDef ( P ) ; if ( ! PredDef -> isCompare ( ) ) return false ; SmallSet < unsigned , <NUM_LIT> > CmpRegs ;


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { if ( ST -> getCPUDirective ( ) == <STR_LIT> ) {


<s> } } else if ( ST . isMesaGfxShader ( Fn ) || ! PreloadedScratchRsrcReg ) { assert ( ! ST . isAmdHsaOrMesa ( Fn ) ) ; const MCInstrDesc & SMovB32 = TII -> get ( <STR_LIT> ) ; Register Rsrc2 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; Register Rsrc3 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; uint64_t Rsrc23 = TII -> getScratchRsrcWords23 ( ) ; if ( MFI -> hasImplicitBufferPtr ( ) ) { Register Rsrc01 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; if ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) { const MCInstrDesc & Mov64 = TII -> get ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , Mov64 , Rsrc01 ) . addReg ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } else { const MCInstrDesc & LoadDwordX2 = TII -> get ( <STR_LIT> ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; auto MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , LoadDwordX2 , Rsrc01 ) . addReg ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; MF . getRegInfo ( ) . addLiveIn ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) ; MBB . addLiveIn ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) ; } } else { Register Rsrc0 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; Register Rsrc1 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc0 ) . addExternalSymbol ( <STR_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc1 ) . addExternalSymbol ( <STR_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } BuildMI ( MBB , I , DL , SMovB32 , Rsrc2 ) . addImm ( Rsrc23 & <NUM_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc3 ) . addImm ( Rsrc23 >> <NUM_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } else if ( ST . isAmdHsaOrMesa ( Fn ) ) { assert ( PreloadedScratchRsrcReg ) ; if ( ScratchRsrcReg != PreloadedScratchRsrcReg ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchRsrcReg ) . addReg ( PreloadedScratchRsrcReg , RegState :: Kill ) ; } }

Register ScratchRsrcSub0 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const uint16_t * CURegs = is64Bit ? CU64BitRegs : CU32BitRegs ; for ( int Idx = <NUM_LIT> ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs == Reg ) return Idx ;


<s> assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI -> getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI -> setObjectAlignment ( RPI . FrameIdx , <NUM_LIT> ) ; AFI -> setCalleeSaveStackHasFreeSpace ( true ) ; } else Offset -= RPI . isPaired ( ) ? <NUM_LIT> : <NUM_LIT> ; assert ( Offset % <NUM_LIT> == <NUM_LIT> ) ; RPI . Offset = Offset / <NUM_LIT> ; assert ( ( RPI . Offset >= - <NUM_LIT> && RPI . Offset <= <NUM_LIT> ) && <STR_LIT> ) ; RegPairs . push_back ( RPI ) ; if ( RPI . isPaired ( ) ) ++ i ;


<s> switch ( Src . getOpcode ( ) ) { default : MaxNumUsers = <NUM_LIT> ; break ; case <STR_LIT> : MaxNumUsers = <NUM_LIT> ; } if ( NumUsers > MaxNumUsers ) return false ; for ( const MachineInstr & I : make_range ( std :: next ( MachineBasicBlock :: const_iterator ( Src ) ) , MachineBasicBlock :: const_iterator ( Dst ) ) ) { if ( I . isCall ( ) || I . hasUnmodeledSideEffects ( ) ) return false ; if ( I . mayLoadOrStore ( ) ) { if ( Src . hasOrderedMemoryRef ( ) || I . hasOrderedMemoryRef ( ) ) return false ; if ( I . mayAlias ( AA , Src , true ) ) return false ; if ( I . mayAlias ( AA , Dst , true ) ) return false ;


<s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ;

else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ;


<s> return ( Opc == <STR_LIT> && ( Val == <NUM_LIT> || Val == <NUM_LIT> ) ) || ( Opc == <STR_LIT> && ( Val == <NUM_LIT> || Val == <NUM_LIT> ) ) || ( Opc == <STR_LIT> && Val == <NUM_LIT> ) ;


<s> SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask2 [ <NUM_LIT> ] ) ; MVT HalfVT = <STR_LIT> ( VT . getScalarType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpHi ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpHi ) ;


<s> if ( Subtarget . hasStdExtZba ( ) && ! Imm . isSignedIntN ( <NUM_LIT> ) && ( ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( <NUM_LIT> ) && Imm . countTrailingZeros ( ) < <NUM_LIT> ) { APInt ImmS = Imm . ashr ( Imm . countTrailingZeros ( ) ) ; if ( ( ImmS + <NUM_LIT> ) . isPowerOf2 ( ) || ( ImmS - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - ImmS ) . isPowerOf2 ( ) ) return true ; } }


<s> while ( AvailablesAluCount ( ) || ! Pending [ IDAlu ] . empty ( ) ) { if ( ! OccupiedSlotsMask ) { if ( ! AvailableAlus [ AluPredX ] . empty ( ) ) { OccupiedSlotsMask |= <NUM_LIT> ; return PopInst ( AvailableAlus [ AluPredX ] , false ) ; } if ( ! AvailableAlus [ AluDiscarded ] . empty ( ) ) { OccupiedSlotsMask |= <NUM_LIT> ; return PopInst ( AvailableAlus [ AluDiscarded ] , false ) ; } if ( ! AvailableAlus [ AluT_XYZW ] . empty ( ) ) { OccupiedSlotsMask |= <NUM_LIT> ; return PopInst ( AvailableAlus [ AluT_XYZW ] , false ) ; } } bool TransSlotOccupied = OccupiedSlotsMask & <NUM_LIT> ; if ( ! TransSlotOccupied && VLIW5 ) { if ( ! AvailableAlus [ AluTrans ] . empty ( ) ) { OccupiedSlotsMask |= <NUM_LIT> ; return PopInst ( AvailableAlus [ AluTrans ] , false ) ; } SUnit * SU = AttemptFillSlot ( <NUM_LIT> , true ) ; if ( SU ) { OccupiedSlotsMask |= <NUM_LIT> ; return SU ; } } for ( int Chan = <NUM_LIT> ; Chan > - <NUM_LIT> ; -- Chan ) { bool isOccupied = OccupiedSlotsMask & ( <NUM_LIT> << Chan ) ; if ( ! isOccupied ) {

SUnit * SU = AttemptFillSlot ( Chan , false ) ;


<s> unsigned R = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( R ) ) { MCSuperRegIterator S ( R , HRI , false ) ; MI . addOperand ( MachineOperand :: CreateReg ( * S , true , true ) ) ; } return MII ; } assert ( ResourceTracker -> canReserveResources ( MI ) ) ; bool ExtMI = HII -> isExtended ( & MI ) || HII -> isConstExtended ( & MI ) ; bool Good = true ; if ( GlueToNewValueJump ) { MachineInstr & NvjMI = * ++ MII ; ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI ) Good = tryAllocateResourcesForConstExt ( true ) ; bool ExtNvjMI = HII -> isExtended ( & NvjMI ) || HII -> isConstExtended ( & NvjMI ) ; if ( Good ) { if ( ResourceTracker -> canReserveResources ( NvjMI ) ) ResourceTracker -> reserveResources ( NvjMI ) ; else Good = false ; } if ( Good && ExtNvjMI ) Good = tryAllocateResourcesForConstExt ( true ) ; if ( ! Good ) { endPacket ( MBB , MI ) ; assert ( ResourceTracker -> canReserveResources ( MI ) ) ; ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI ) { assert ( canReserveResourcesForConstExt ( ) ) ; tryAllocateResourcesForConstExt ( true ) ; } assert ( ResourceTracker -> canReserveResources ( NvjMI ) ) ; ResourceTracker -> reserveResources ( NvjMI ) ; if ( ExtNvjMI ) { assert ( canReserveResourcesForConstExt ( ) ) ; reserveResourcesForConstExt ( ) ;


<s> if ( MI -> mayStore ( ) || MI -> isBranch ( ) || MI -> isCall ( ) || MI -> isReturn ( ) ) return true ; if ( MI -> hasOrderedMemoryRef ( ) || MI -> hasUnmodeledSideEffects ( ) ) return true ; if ( MI -> isPHI ( ) ) return false ; for ( auto & Op : MI -> operands ( ) ) if ( Op . isReg ( ) && MRI . isReserved ( Op . getReg ( ) ) ) return true ;


<s> if ( shouldPromote ( I ) ) { I -> mutateType ( ExtTy ) ; Promoted . insert ( I ) ; } } for ( auto * V : * Visited ) { auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) continue ; if ( Sources -> count ( I ) || Sinks -> count ( I ) ) continue ; if ( ! shouldPromote ( I ) || SafeToPromote -> count ( I ) || NewInsts . count ( I ) ) continue ; assert ( EnableDSP && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; Function * DSPInst = <STR_LIT> ( M , getNarrowIntrinsic ( I ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ;

Value * Args [ ] = { I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) } ;


<s> static unsigned getRelaxedOpcodeBranch ( const MCInst & Inst , bool Is16BitMode ) { unsigned Op = Inst . getOpcode ( ) ; switch ( Op ) { default : return Op ; case <STR_LIT> : return ( Is16BitMode ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ( Is16BitMode ) ? <STR_LIT> : <STR_LIT> ;


<s> tree fntype , new_fndecl , args ; unsigned arity ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_EXP : CASE_CFN_LOG : CASE_CFN_LOG10 : CASE_CFN_POW : CASE_CFN_TANH : CASE_CFN_TAN : CASE_CFN_ATAN : CASE_CFN_ATAN2 : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_SINH : CASE_CFN_SIN : CASE_CFN_ASINH : CASE_CFN_ASIN : CASE_CFN_COSH : CASE_CFN_COS : CASE_CFN_ACOSH : CASE_CFN_ACOS : if ( ( el_mode != DFmode || n != <NUM_LIT> ) && ( el_mode != SFmode || n != <NUM_LIT> ) ) return NULL_TREE ; break ; default : return NULL_TREE ; } tree fndecl = mathfn_built_in ( el_mode == DFmode ? double_type_node : float_type_node , fn ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( fndecl ) ) ; if ( DECL_FUNCTION_CODE ( fndecl ) == BUILT_IN_LOGF ) strcpy ( name , <STR_LIT> ) ; else if ( DECL_FUNCTION_CODE ( fndecl ) == BUILT_IN_LOG ) strcpy ( name , <STR_LIT> ) ; else if ( n == <NUM_LIT> ) { sprintf ( name , <STR_LIT> , bname + <NUM_LIT> ) ; name [ strlen ( name ) - <NUM_LIT> ] = '4' ; } else sprintf ( name , <STR_LIT> , bname + <NUM_LIT> ) ; name [ <NUM_LIT> ] &= ~ <NUM_LIT> ; arity = <NUM_LIT> ; for ( args = DECL_ARGUMENTS ( fndecl ) ; args ; args = TREE_CHAIN ( args ) ) arity ++ ; if ( arity == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = <NUM_LIT> ; DECL_EXTERNAL ( new_fndecl ) = <NUM_LIT> ;


<s> bool <ISA_LIT>InstructionSelector :: selectCmp ( Register ResVReg , const <ISA_LIT>Type * ResType , unsigned CmpOpc , MachineInstr & I ) const { Register Cmp0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Cmp1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( GR . get<ISA_LIT>TypeForVReg ( Cmp0 ) -> getOpcode ( ) == GR . get<ISA_LIT>TypeForVReg ( Cmp1 ) -> getOpcode ( ) && <STR_LIT> ) ; return BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( CmpOpc ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) . addUse ( Cmp0 ) . addUse ( Cmp1 ) . constrainAllUses ( TII , TRI , RBI ) ;


<s> SmallString < <NUM_LIT> > epilogueString ; raw_svector_ostream OS ( epilogueString ) ; OS << <STR_LIT> ; OS << <STR_LIT> ; OS << <STR_LIT> ; OS << <STR_LIT> ; OS << <STR_LIT> ; OS << <STR_LIT> ; OS << <STR_LIT> ; OutStreamer . EmitRawText ( OS . str ( ) ) ;


assert ( MBB -> succ_size ( ) == <NUM_LIT> && MBB -> pred_size ( ) == <NUM_LIT> && <STR_LIT> ) ;


if ( skipFunction ( Func . getFunction ( ) ) ) return false ;


<s> __inline__ static unsigned long long sh_media_MSUBS_UB ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ;

__asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ;


<s> MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( ImmOp ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; OpStart = <NUM_LIT> ; } else if ( HII -> getAddrMode ( * OldMI ) == <STR_LIT> ) { short NewOpCode = HII -> changeAddrMode_io_abs ( * OldMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; const GlobalValue * GV = ImmOp . getGlobal ( ) ; int64_t Offset = ImmOp . getOffset ( ) + OldMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addGlobalAddress ( GV , Offset , ImmOp . getTargetFlags ( ) ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; OpStart = <NUM_LIT> ; } Changed = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * OldMI << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; } else if ( ImmOpNum == <NUM_LIT> && OldMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { short NewOpCode = HII -> changeAddrMode_rr_io ( * OldMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( ImmOp ) ; OpStart = <NUM_LIT> ;


<s> if ( isMAI ( MI ) && ST . hasMFMAInlineLiteralBug ( ) && OpNo == ( unsigned ) <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: src2 ) ) return false ; return RI . opCanUseInlineConstant ( OpInfo . OperandType ) ; } if ( ! RI . opCanUseLiteralConstant ( OpInfo . OperandType ) ) return false ; if ( ! isVOP3 ( MI ) || ! <STR_LIT> ( InstDesc , OpNo ) ) return true ;


<s> return ( ( vec_int4 ) ( si_xori ( ( qword ) ( a ) , ( unsigned int ) ( b ) ) ) ) ;


<s> unsigned MinOffset = std :: min ( A -> getOffset ( ) , B -> getOffset ( ) ) ; unsigned Size = A -> getSize ( ) + B -> getSize ( ) ; return MF . getMachineMemOperand ( A , MinOffset , Size ) ;


<s> Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;


return aarch64_classify_address ( & addr , x , mode , strict_p , type ) ;


<s> <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; } return Op0 . getOperand ( <NUM_LIT> ) ; } } if ( isAllOnesConstant ( Op1 ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) == Op1 && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isProfitableToUseFlagOp ( Op0 ) ) { SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Op0 . getNode ( ) , <NUM_LIT> ) , New ) ; <STR_LIT> CCode = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>CC = DAG . getTargetConstant ( CCode , dl , <STR_LIT> ) ; return SDValue ( New . getNode ( ) , <NUM_LIT> ) ; } } <STR_LIT> CondCode = Translate<ISA_LIT>CC ( CC , dl , false , Op0 , Op1 , DAG ) ;

assert ( CondCode != <STR_LIT> && <STR_LIT> ) ;


<s> O << '(' ; if ( MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ;

else printOperand ( MI , OpNo + <NUM_LIT> , O ) ;


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; } if ( I -> getOpcode ( ) != <STR_LIT> && GetCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : <ISA_LIT>InstPrinter ( MAI , MII , MRI ) {


<s> return parseRegister ( Operands , VR32Reg ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCExpr * Expr = getImm ( ) ; addExpr ( Inst , Expr ) ;


<s> while ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || ( Carry . getOpcode ( ) == <STR_LIT> && isOneConstant ( Carry . getOperand ( <NUM_LIT> ) ) ) ) Carry = Carry . getOperand ( <NUM_LIT> ) ; if ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> ) { uint64_t CarryCC = Carry . getConstantOperandVal ( <NUM_LIT> ) ; SDValue CarryOp1 = Carry . getOperand ( <NUM_LIT> ) ; if ( CarryCC == <STR_LIT> ) return CarryOp1 ; if ( CarryCC == <STR_LIT> ) { if ( CarryOp1 . getOpcode ( ) == <STR_LIT> && CarryOp1 . getNode ( ) -> hasOneUse ( ) && CarryOp1 . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( CarryOp1 . getOperand ( <NUM_LIT> ) ) ) { SDValue SubCommute = DAG . getNode ( <STR_LIT> , SDLoc ( CarryOp1 ) , CarryOp1 -> getVTList ( ) , CarryOp1 . getOperand ( <NUM_LIT> ) , CarryOp1 . getOperand ( <NUM_LIT> ) ) ; return SDValue ( SubCommute . getNode ( ) , CarryOp1 . getResNo ( ) ) ; } } } } } return SDValue ( ) ;


<s> if ( ! FullRegNamesWithPercent || TT . isOSDarwin ( ) || TT . getOS ( ) == Triple :: AIX ) return false ; switch ( RegName [ <NUM_LIT> ] ) { default : return false ;


<s> llvm_unreachable ( <STR_LIT> ) ; return false ;


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) {


<s> Inst . addOperand ( MCOperand :: createReg ( XRegsNoX0 [ getReg ( ) ] ) ) ;


<s> const MCExpr * getSubExpr ( ) const {


<s> if ( OptLEA ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . slowLEA ( ) ) processInstructionForSlowLEA ( I , MFI ) ; else { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . slow3OpsLEA ( ) ) { if ( auto * NewMI = processInstrForSlow3OpLEA ( * I , MFI ) ) { MFI -> erase ( I ) ; I = NewMI ; } } else processInstruction ( I , MFI ) ; } }


<s> if ( AbsMod && getLexer ( ) . peekTok ( ) . is ( AsmToken :: Pipe ) && ( getLexer ( ) . getKind ( ) == AsmToken :: Integer || getLexer ( ) . getKind ( ) == AsmToken :: Real ) ) { SMLoc EndLoc ; const MCExpr * Expr ; if ( getParser ( ) . parsePrimaryExpr ( Expr , EndLoc ) ) { return true ;


<s> <ISA_LIT>AAWrapperPass ( ) : ImmutablePass ( ID ) { initialize<ISA_LIT>AAWrapperPassPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( ST . enable<ISA_LIT>Scheduler ( ) ) return create<ISA_LIT>MachineScheduler ( C ) ;


<s> const TargetRegisterClass * <ISA_LIT>Z80RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & <STR_LIT> ;


<s> bool hasVBMI2 ( ) const { return HasVBMI2 ;


<s> Register dim_off_reg = ( int ) MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int rw_off = isRead ? <NUM_LIT> : <NUM_LIT> ; Register dim_off0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , dim_off0 ) . addReg ( dim_off_reg ) . addImm ( rw_off ) ; Register dim_off1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , dim_off1 ) . addReg ( dim_off0 ) . addImm ( <NUM_LIT> ) ; Register dim_off2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , dim_off2 ) . addReg ( dim_off1 ) . addReg ( dm_off_reg ) ;

Register PtrReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> vpminq_u8 ( uint8x16_t a , uint8x16_t b ) {

return ( uint8x16_t ) __builtin_aarch64_uminpv16qi ( ( int8x16_t ) a , ( int8x16_t ) b ) ;


<s> bool <ISA_LIT>TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { EVT ExtT = ExtVal . getValueType ( ) ; EVT MemT = cast < LoadSDNode > ( ExtVal -> getOperand ( <NUM_LIT> ) ) -> getValueType ( <NUM_LIT> ) ;

return ( ExtT == <STR_LIT> && MemT == <STR_LIT> ) || ( ExtT == <STR_LIT> && MemT == <STR_LIT> ) || ( ExtT == <STR_LIT> && MemT == <STR_LIT> ) ;


<s> if ( ElemWidth == <NUM_LIT> ) { assert ( VecWidth == VecTy . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; if ( IdxN ) { if ( IdxN -> isNullValue ( ) && ValTy . getSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , IdxV ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; }

return DAG . getNode ( <STR_LIT> , dl , ResTy , T1 ) ;


<s> <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; if ( ! Op . isReg ( ) ) return Match_InvalidOperand ; Register Reg = Op . getReg ( ) ; bool IsRegFPR64 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ;

if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) {


<s> Op -> Mem . OffReg = Off ; Op -> Mem . Off = <NUM_LIT> ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ; return ( unsigned long long ) __builtin_sssubv2si3 ( ( v2si ) mm , ( v2si ) mn ) ;


<s> Type * LLVMTy = IntegerType :: get ( CurMF -> getFunction ( ) . getContext ( ) , BitWidth ) ; Register Reg ; if ( DT . find ( LLVMTy , CurMF , Reg ) ) { return get<ISA_LIT>TypeForVReg ( Reg ) ; } MachineBasicBlock & BB = * I . getParent ( ) ;

auto MIB = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( createTypeVReg ( CurMF -> getRegInfo ( ) ) ) . addImm ( BitWidth ) . addImm ( <NUM_LIT> ) ;


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O << <STR_LIT> ;


<s> switch ( mode ) { case E_CCFmode : case E_SFmode : return TARGET_HARD_FLOAT ; case E_DFmode : return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ; case E_V2SFmode : return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT ;


<s> if ( NumNonZero > <NUM_LIT> && ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; return LowerBuildVectorAsInsert ( Op , NonZeroMask , NumNonZero , NumZero , DAG , Subtarget ) ;


<s> ShiftVal = NumBitsPerElt - <NUM_LIT> ; } if ( ! ShiftVal ) return N0 ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( ! LogicalShift && <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( - <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( Opcode == N0 . getOpcode ( ) ) { unsigned ShiftVal2 = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NewShiftVal = ShiftVal + ShiftVal2 ; if ( NewShiftVal >= NumBitsPerElt ) { if ( LogicalShift ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; NewShiftVal = NumBitsPerElt - <NUM_LIT> ; } return DAG . getNode ( Opcode , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( NewShiftVal , SDLoc ( N ) , <STR_LIT> ) ) ; } if ( LogicalShift && ( ShiftVal % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ;

if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ;


<s> return ( __a + ( __b * __aarch64_vget_lane_any ( __c , __lane ) ) ) ;


<s> if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ;

Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ;


<s> bool Filler :: IsRegInSet ( SmallSet < unsigned , <NUM_LIT> > & RegSet , unsigned Reg ) { for ( MCRegAliasIterator AI ( Reg , TM . getRegisterInfo ( ) , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ; return false ;


<s> SDValue <ISA_LIT>Z80TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerZExt ( Op , DAG ) ; case <STR_LIT> : return LowerSExt ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSUB ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> :


<s> it != <ISA_LIT>FI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: <STR_LIT> * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; emitXRayTable ( ) ; return true ;


<s> BI -> unbundleFromPred ( ) ; for ( MachineOperand & MO : BI -> operands ( ) ) { if ( MO . isReg ( ) && MO . isInternalRead ( ) ) MO . setIsInternalRead ( false ) ; } getLiteral ( * BI , Literals ) ; ClauseContent . push_back ( & * BI ) ; } I = BI ; DeleteMI . eraseFromParent ( ) ; } else { getLiteral ( * I , Literals ) ; ClauseContent . push_back ( & * I ) ; I ++ ; } for ( unsigned i = <NUM_LIT> , e = Literals . size ( ) ; i < e ; i += <NUM_LIT> ) { MachineInstrBuilder MILit = BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; if ( Literals [ i ] -> isImm ( ) ) { MILit . addImm ( Literals [ i ] -> getImm ( ) ) ; } else { MILit . addGlobalAddress ( Literals [ i ] -> getGlobal ( ) , Literals [ i ] -> getOffset ( ) ) ; } if ( i + <NUM_LIT> < e ) { if ( Literals [ i + <NUM_LIT> ] -> isImm ( ) ) { MILit . addImm ( Literals [ i + <NUM_LIT> ] -> getImm ( ) ) ; } else { MILit . addGlobalAddress ( Literals [ i + <NUM_LIT> ] -> getGlobal ( ) , Literals [ i + <NUM_LIT> ] -> getOffset ( ) ) ; } } else MILit . addImm ( <NUM_LIT> ) ; ClauseContent . push_back ( MILit ) ; } }

assert ( ClauseContent . size ( ) < <NUM_LIT> && <STR_LIT> ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) : ) ; return result ;


<s> Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasNVJump && ( LastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( MBB ) << <STR_LIT> ; ) ; return true ; } bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNVJump = isNewValueJump ( * SecondLastInst ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcodeHasNVJump && ( SecondLastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst -> getIterator ( ) ; if ( AllowModify ) I -> eraseFromParent ( ) ;


<s> bool IsO32 ( ) const { return ThisABI == <STR_LIT> ;


<s> bool ix86_target_stack_probe ( void ) { if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) return false ;


<s> void h8300_swap_into_er6 ( rtx addr ) { rtx insn = push ( HARD_FRAME_POINTER_REGNUM , false ) ;

if ( frame_pointer_needed ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , gen_rtx_MEM ( Pmode , stack_pointer_rtx ) , <NUM_LIT> * UNITS_PER_WORD ) ) ;


<s> Offsets [ <NUM_LIT> ] = DAG . getTargetConstant ( ImmOffset , DL , <STR_LIT> ) ; return SOffset + ImmOffset ; } } if ( DAG . isBaseWithConstantOffset ( CombinedOffset ) ) { SDValue N0 = CombinedOffset . getOperand ( <NUM_LIT> ) ; SDValue N1 = CombinedOffset . getOperand ( <NUM_LIT> ) ; uint32_t SOffset , ImmOffset ; int Offset = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; if ( Offset >= <NUM_LIT> && <STR_LIT> ( Offset , SOffset , ImmOffset , Subtarget , Align ) ) { Offsets [ <NUM_LIT> ] = N0 ; Offsets [ <NUM_LIT> ] = DAG . getConstant ( SOffset , DL , <STR_LIT> ) ; Offsets [ <NUM_LIT> ] = DAG . getTargetConstant ( ImmOffset , DL , <STR_LIT> ) ; return <NUM_LIT> ; } }

Offsets [ <NUM_LIT> ] = CombinedOffset ;


<s> MCContext & Context = getParser ( ) . getContext ( ) ; Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; switch ( E -> getKind ( ) ) { case MCExpr :: Target : case MCExpr :: Constant : return <NUM_LIT> ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( E ) ; switch ( SRE -> getKind ( ) ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_LO : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HI : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA : Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHESTA ; break ; default : return <NUM_LIT> ; } return MCSymbolRefExpr :: Create ( & SRE -> getSymbol ( ) , Context ) ; } case MCExpr :: Unary : { const MCUnaryExpr * UE = cast < MCUnaryExpr > ( E ) ; const MCExpr * Sub = ExtractModifierFromExpr ( UE -> getSubExpr ( ) , Variant ) ; if ( ! Sub ) return <NUM_LIT> ; return MCUnaryExpr :: Create ( UE -> getOpcode ( ) , Sub , Context ) ; } case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( E ) ;

<ISA_LIT>MCExpr :: VariantKind LHSVariant , RHSVariant ;


<s> int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ;

if ( ! Decoder -> tryAddingSymbolicOperand ( Inst , imm , Addr , Fail , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> __asm__ volatile ( <STR_LIT> : [ val ] <STR_LIT> ( __rdtime . value ) , [ tid ] <STR_LIT> ( __rdtime . timeid ) : ) ; return __rdtime ;


<s> bool <ISA_LIT>OptAddrMode :: xformUseMI ( MachineInstr * TfrMI , MachineInstr * UseMI , NodeAddr < UseNode * > UseN , unsigned UseMOnum ) { const MachineOperand ImmOp = TfrMI -> getOperand ( <NUM_LIT> ) ; const MCInstrDesc & MID = UseMI -> getDesc ( ) ; unsigned Changed = false ; if ( MID . mayLoad ( ) ) Changed = changeLoad ( UseMI , ImmOp , UseMOnum ) ; else if ( MID . mayStore ( ) ) Changed = changeStore ( UseMI , ImmOp , UseMOnum ) ;

else if ( UseMI -> getOpcode ( ) == <STR_LIT> ) Changed = changeAddAsl ( UseN , UseMI , ImmOp , UseMOnum ) ;


<s> case AMDGPU :: S_SUB_I32 : case AMDGPU :: S_SUB_U32 : return AMDGPU :: V_SUB_I32_e32 ; case AMDGPU :: S_SUBB_U32 : return AMDGPU :: V_SUBB_U32_e32 ; case AMDGPU :: S_MUL_I32 : return AMDGPU :: V_MUL_LO_I32 ; case AMDGPU :: S_AND_B32 : return AMDGPU :: V_AND_B32_e32 ; case AMDGPU :: S_OR_B32 : return AMDGPU :: V_OR_B32_e32 ; case AMDGPU :: S_XOR_B32 : return AMDGPU :: V_XOR_B32_e32 ; case AMDGPU :: S_MIN_I32 : return AMDGPU :: V_MIN_I32_e32 ; case AMDGPU :: S_MIN_U32 : return AMDGPU :: V_MIN_U32_e32 ; case AMDGPU :: S_MAX_I32 : return AMDGPU :: V_MAX_I32_e32 ; case AMDGPU :: S_MAX_U32 : return AMDGPU :: V_MAX_U32_e32 ; case AMDGPU :: S_ASHR_I32 : return AMDGPU :: V_ASHR_I32_e32 ; case AMDGPU :: S_ASHR_I64 : return AMDGPU :: V_ASHR_I64 ; case AMDGPU :: S_LSHL_B32 : return AMDGPU :: V_LSHL_B32_e32 ; case AMDGPU :: S_LSHL_B64 : return AMDGPU :: V_LSHL_B64 ; case AMDGPU :: S_LSHR_B32 : return AMDGPU :: V_LSHR_B32_e32 ; case AMDGPU :: S_LSHR_B64 : return AMDGPU :: V_LSHR_B64 ; case AMDGPU :: S_SEXT_I32_I8 : return AMDGPU :: V_BFE_I32 ; case AMDGPU :: S_SEXT_I32_I16 : return AMDGPU :: V_BFE_I32 ; case AMDGPU :: S_BFE_U32 : return AMDGPU :: V_BFE_U32 ; case AMDGPU :: S_BFE_I32 : return AMDGPU :: V_BFE_I32 ;

case AMDGPU :: S_BREV_B32 : return AMDGPU :: V_BFREV_B32_e32 ;


<s> static_assert ( <STR_LIT> > <NUM_LIT> , <STR_LIT> ) ; if ( CSI . empty ( ) ) return <NUM_LIT> ;

unsigned Max = getMax32BitSubRegister ( CSI [ <NUM_LIT> ] . getReg ( ) , TRI ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI . getShiftAmountTy ( SrcOp . getValueType ( ) ) ) ) ) ;


<s> static rtx v850_libcall_value ( machine_mode mode , const_rtx func ATTRIBUTE_UNUSED ) {

return gen_rtx_REG ( mode , RV_REGNUM ) ;


<s> Keyword = StringSwitch < StringRef > ( Keyword . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Keyword ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Keyword , Tok . getLoc ( ) , getContext ( ) ) ) ;


<s> if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsl ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Asr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Ror ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Rrx ; else return true ; Parser . Lex ( ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blsfill_u64 ( unsigned long long __X ) {


<s> if ( flag_pic && regno == PIC_OFFSET_TABLE_REGNUM && ( ! saving || cfun -> machine -> pic_reg == pic_offset_table_rtx ) ) return <NUM_LIT> ; return <NUM_LIT> ;


return Kind == Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ;


<s> unsigned int flags = default_section_type_flags ( decl , name , reloc ) ;

if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL && target_pure_code ) flags |= SECTION_ARM_PURECODE ;


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && LHS . getOpcode ( ) == <STR_LIT> ) if ( isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) && LHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , RHS , LHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , DL , addV . getValueType ( ) ) , CC ) ; } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && RHS . getOpcode ( ) == <STR_LIT> ) if ( isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , DL , addV . getValueType ( ) ) , CC ) ; } if ( VT . getScalarType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! IsSEXT0 || ! IsVZero1 ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: expandLoadStackGuard ( MachineBasicBlock :: iterator MI ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; if ( ! Subtarget . useMovt ( MF ) ) { if ( TM . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } if ( ! TM . isPositionIndependent ( ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . isGVIndirectSymbol ( GV ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ;

auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ;


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; GlobalDirective = <STR_LIT> ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ;


<s> } if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || isNullConstant ( Op . getOperand ( <NUM_LIT> ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( <STR_LIT> , Extract ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return Op ;


<s> switch ( MOFlags ) { default : return MCSymbolRefExpr :: VK_None ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL : return MCSymbolRefExpr :: VK_GOTPCREL ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL32_LO : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_LO ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL32_HI : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_HI ; case <ISA_LIT>InstrInfo :: MO_REL32_LO : return MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_LO ; case <ISA_LIT>InstrInfo :: MO_REL32_HI : return MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_HI ; case <ISA_LIT>InstrInfo :: MO_ABS32_LO : return MCSymbolRefExpr :: VK_<ISA_LIT>_ABS32_LO ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( IdToReg [ CurReg ] , TRI ) << <STR_LIT> ) ; for ( const auto & DefsIt : ColorOpToReachedUses [ CurReg ] ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( DefsIt . first -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( const MachineInstr * MI : DefsIt . second ) { DEBUG ( MI -> print ( dbgs ( ) ) ) ; } } }


<s> unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isSigned ) return ~ ( - <NUM_LIT> << ( bits - <NUM_LIT> ) ) ; else return ~ ( - <NUM_LIT> << bits ) ;


<s> SDValue PtrOffset = DAG . getUNDEF ( getPointerTy ( <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned Align = DL -> getABITypeAlignment ( Ty ) ; if ( VT != MemVT && VT . isFloatingPoint ( ) ) { assert ( VT . getScalarType ( ) == <STR_LIT> && MemVT . getScalarType ( ) == <STR_LIT> ) ; EVT IVT = toIntegerVT ( VT ) ; EVT MemIVT = toIntegerVT ( MemVT ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , <STR_LIT> , IVT , SL , Chain , Ptr , PtrOffset , PtrInfo , MemIVT , false , true , true , Align ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , Load ) ;


<s> if ( IsNonEntryFunc && ( Access & DS_GLOBAL ) ) return true ; return ! HasAperture && ( Access & ADDR_SPACE_CAST ) ;


<s> if ( NextRegWidth != <NUM_LIT> ) return <STR_LIT> ; if ( NextRegKind != RegKind ) return <STR_LIT> ; if ( ! AddNextRegisterToList ( Reg , RegWidth , RegKind , NextReg ) ) return <STR_LIT> ; } if ( ! trySkipToken ( AsmToken :: RBrac ) ) return <STR_LIT> ; if ( isRegularReg ( RegKind ) ) Reg = getRegularReg ( RegKind , RegNum , RegWidth ) ; return Reg ;


<s> static DecodeStatus DecodeSSRInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned s2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , s2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s1 , Address , Decoder ) ;


<s> rtx def_reg = SET_DEST ( PATTERN ( insn ) ) ; machine_mode mode ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; switch ( GET_MODE ( def_reg ) ) { case E_DImode : mode = SImode ;


<s> if ( IN_NAMED_SECTION ( decl ) ) return get_named_section ( decl , NULL , reloc ) ; } if ( decl_readonly_section ( decl , reloc ) ) { if ( TREE_PUBLIC ( decl ) ) return read_only_data_section ; else return read_only_private_data_section ; } else { if ( TREE_CODE ( decl ) == VAR_DECL && DECL_THREAD_LOCAL_P ( decl ) ) { if ( TREE_PUBLIC ( decl ) ) return tls_data_section ; else if ( bss_initializer_p ( decl ) ) {


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ;


<s> if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; } Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , M0Base ) . addReg ( BaseOffset ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Base ) ; } auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( gwsIntrinToOpcode ( IID ) ) ) ; if ( HasVSrc ) { Register VSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( STI . needsAlignedVGPRs ( ) ) { Register Undef = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & * MIB , DL , TII . get ( <STR_LIT> ) , Undef ) ; Register NewVR = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & * MIB , DL , TII . get ( <STR_LIT> ) , NewVR ) . addReg ( VSrc , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) . addImm ( <STR_LIT> ) . addReg ( Undef ) . addImm ( <STR_LIT> ) ; MIB . addReg ( NewVR , <NUM_LIT> , <STR_LIT> ) ; MIB . addReg ( NewVR , RegState :: Implicit ) ; } else {


<s> std :: vector < SDValue > Ops ; Ops . resize ( outSize + Ins . size ( ) + <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = Chain ; Callee = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) ) ; Ops [ Ins . size ( ) + <NUM_LIT> ] = Callee ; Ops [ Ins . size ( ) + <NUM_LIT> ] = DAG . getTargetConstant ( outSize , <STR_LIT> ) ; if ( isPrintf ) { unsigned Param0 = PM . addLocalParam ( getPointerTy ( ) . getSizeInBits ( ) ) ; SDValue ParamValue0 = DAG . getTargetExternalSymbol ( PM . getParamName ( Param0 ) . c_str ( ) , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , ParamValue0 , OutVals [ <NUM_LIT> ] ) ; Ops [ Ins . size ( ) + <NUM_LIT> ] = ParamValue0 ; unsigned alignment = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < OutVals . size ( ) ; ++ i ) { alignment = std :: max ( alignment , OutVals [ i ] . getValueType ( ) . getSizeInBits ( ) ) ; } unsigned size = alignment * ( OutVals . size ( ) - <NUM_LIT> ) ; unsigned Param1 = PM . addLocalParam ( getPointerTy ( ) . getSizeInBits ( ) ) ; SDValue ParamValue1 = DAG . getTargetExternalSymbol ( PM . getParamName ( Param1 ) . c_str ( ) , <STR_LIT> ) ; Ops [ Ins . size ( ) + <NUM_LIT> ] = ParamValue1 ; if ( size > <NUM_LIT> ) { unsigned StackObject = MFI -> CreateStackObject ( size / <NUM_LIT> , alignment / <NUM_LIT> , false ) ; SDValue FrameIndex = DAG . getFrameIndex ( StackObject , getPointerTy ( ) ) ; for ( unsigned int i = <NUM_LIT> ; i != OutVals . size ( ) ; i ++ ) { SDValue FrameAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameIndex , DAG . getTargetConstant ( ( i - <NUM_LIT> ) * <NUM_LIT> , getPointerTy ( ) ) ) ; Chain = DAG . getStore ( Chain , dl , OutVals [ i ] , FrameAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; } SDValue genericAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameIndex ) ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , ParamValue1 , genericAddr ) ; }


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT PtrTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; auto * MINode = cast < MemIntrinsicSDNode > ( N ) ; SDValue PassThru = DAG . getConstant ( <NUM_LIT> , DL , LoadVT ) ; SDValue L = DAG . getMaskedLoad ( LoadVT , DL , MINode -> getChain ( ) , MINode -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( PtrTy ) , MINode -> getOperand ( <NUM_LIT> ) , PassThru , MINode -> getMemoryVT ( ) , MINode -> getMemOperand ( ) , <STR_LIT> , <STR_LIT> , false ) ; if ( VT . isFloatingPoint ( ) ) { SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , VT , L ) , L . getValue ( <NUM_LIT> ) } ;

return DAG . getMergeValues ( Ops , DL ) ;


<s> unsigned Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; return SegmentOffset ( IRB , Offset , getAddressSpace ( ) ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerATOMIC_LOAD ( SDValue Op , SelectionDAG & DAG ) const { AtomicSDNode * N = cast < AtomicSDNode > ( Op ) ; assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( N -> getOrdering ( ) <= Monotonic && <STR_LIT> ) ; if ( N -> getMemoryVT ( ) == <STR_LIT> ) { if ( N -> getAlignment ( ) < <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( DAG . getDataLayout ( ) ) , SDLoc ( Op ) , N -> getChain ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , N -> isVolatile ( ) , N -> isNonTemporal ( ) , N -> isInvariant ( ) , N -> getAlignment ( ) , N -> getAAInfo ( ) , N -> getRanges ( ) ) ; } if ( N -> getMemoryVT ( ) == <STR_LIT> ) { if ( N -> getAlignment ( ) < <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return DAG . getExtLoad ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , N -> getChain ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> isVolatile ( ) , N -> isNonTemporal ( ) , N -> isInvariant ( ) , N -> getAlignment ( ) , N -> getAAInfo ( ) ) ; } if ( N -> getMemoryVT ( ) == <STR_LIT> ) return DAG . getExtLoad ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , N -> getChain ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> isVolatile ( ) , N -> isNonTemporal ( ) , N -> isInvariant ( ) , N -> getAlignment ( ) , N -> getAAInfo ( ) ) ; return SDValue ( ) ;


<s> uint64_t MulFactor = <NUM_LIT> << N -> getConstantOperandVal ( <NUM_LIT> ) ;

return CurDAG -> getConstant ( MulFactor , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ) ;


<s> while ( <NUM_LIT> ) { insn = NEXT_INSN ( insn ) ; if ( insn == NULL_RTX || insn == tail ) return NULL_RTX ; if ( CALL_P ( insn ) || JUMP_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER && INSN_CODE ( insn ) != CODE_FOR_stack_tie ) ) break ;


<s> Value * entity = elem -> getOperand ( <NUM_LIT> ) ; if ( ! entity ) continue ; if ( entity != gv ) continue ; cacheAnnotationFromMD ( elem , tmp ) ; } if ( tmp . empty ( ) ) return ; if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) . end ( ) ) ( * annotationCache ) [ m ] [ gv ] = std :: move ( tmp ) ; else { global_val_annot_t tmp1 ;


<s> SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( DL ) ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result ) ;


<s> BuildMI ( BB , dl , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; } else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator i = BB -> succ_begin ( ) , e = BB -> succ_end ( ) ; i != e ; ++ i ) sinkMBB -> addSuccessor ( * i ) ; while ( ! BB -> succ_empty ( ) ) BB -> removeSuccessor ( BB -> succ_begin ( ) ) ;


<s> break ; } if ( consumeByte ( insn , & insn -> sib ) ) return - <NUM_LIT> ; index = indexFromSIB ( insn -> sib ) | ( xFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; if ( insn -> vectorExtensionType == TYPE_EVEX ) index |= v2FromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ; switch ( index ) { case <NUM_LIT> : insn -> sibIndex = SIB_INDEX_NONE ; break ; default : insn -> sibIndex = ( SIBIndex ) ( sibIndexBase + index ) ; if ( insn -> sibIndex == SIB_INDEX_sib || insn -> sibIndex == SIB_INDEX_sib64 ) insn -> sibIndex = SIB_INDEX_NONE ; break ; } switch ( scaleFromSIB ( insn -> sib ) ) { case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; case <NUM_LIT> : insn -> sibScale = <NUM_LIT> ; break ; } base = baseFromSIB ( insn -> sib ) | ( bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ) ; switch ( base ) { case <NUM_LIT> : case <NUM_LIT> : switch ( modFromModRM ( insn -> modRM ) ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_32 ; insn -> sibBase = SIB_BASE_NONE ; break ; case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_8 ; insn -> sibBase = ( SIBBase ) ( sibBaseBase + base ) ; break ; case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_32 ; insn -> sibBase = ( SIBBase ) ( sibBaseBase + base ) ; break ; case <NUM_LIT> : debug ( <STR_LIT> ) ; return - <NUM_LIT> ; }


<s> if ( ! isInt < <NUM_LIT> > ( ShiftedImm ) ) return ; Seq [ <NUM_LIT> ] . Opc = LUi ; Seq [ <NUM_LIT> ] . ImmOpnd = ( unsigned ) ( ShiftedImm & <NUM_LIT> ) ;

Seq . erase ( Seq . begin ( ) + <NUM_LIT> ) ;


<s> virtual void emitIndirectFunctionType ( StringRef name , SmallVectorImpl < MVT > & SignatureVTs , size_t NumResults ) { llvm_unreachable ( <STR_LIT> ) ;


<s> static void mips_prepare_pch_save ( void ) { mips_set_compression_mode ( <NUM_LIT> ) ;


<s> static bool provablyDisjointOr ( SelectionDAG & DAG , const SDValue & N ) { if ( N . getOpcode ( ) != <STR_LIT> ) return false ;

KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) ) ;


<s> const std :: pair < int , unsigned > & Src = TransOps [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < <NUM_LIT> ) continue ; if ( ConstCount > <NUM_LIT> && Cycle == <NUM_LIT> ) return false ; if ( ConstCount > <NUM_LIT> && Cycle == <NUM_LIT> ) return false ; } return true ;


<s> unsigned JTI = MI -> getOperand ( opNum ) . getIndex ( ) ; const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; O << <STR_LIT> << directive << <STR_LIT> ;

for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) {


<s> switch ( getKind ( ) ) { case CEK_None : case CEK_Special : llvm_unreachable ( <STR_LIT> ) ; break ; case CEK_CALL_HI16 :


<s> enablePass ( & MachineSchedulerID ) ; } if ( TM -> getSubtargetImpl ( ) -> use<ISA_LIT>PostRAScheduler ( getOptLevel ( ) ) ) { initialize<ISA_LIT>PostRASchedulerPass ( * PassRegistry :: getPassRegistry ( ) ) ; substitutePass ( & PostRASchedulerID , & <ISA_LIT>PostRASchedulerID ) ; }


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) , MRI ( * Ctx . getRegisterInfo ( ) ) {


return ( __m256i ) __builtin_ia32_vcvttph2dq256_mask ( __B , ( __v8si ) _mm256_setzero_si256 ( ) , __A ) ;


<s> MachineInstrBuilder MIM = BuildMI ( * BB , MI , DL , TII -> get ( MOp ) ) . addReg ( MSrc ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;

MachineInstr * MIO = BuildMI ( * BB , ( MachineInstr * ) MIM , DL , TII -> get ( FOp ) , MRI . createVirtualRegister ( MRI . getRegClass ( VSrc ) ) ) . addReg ( VSrc ) . addReg ( MSrc ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> NamedMDNode * NMD = m -> getNamedMetadata ( llvm :: NamedMDForAnnotations ) ; if ( ! NMD ) return ; key_val_pair_t tmp ; for ( unsigned i = <NUM_LIT> , e = NMD -> getNumOperands ( ) ; i != e ; ++ i ) { const MDNode * elem = NMD -> getOperand ( i ) ; Value * entity = elem -> getOperand ( <NUM_LIT> ) ;