<s> StringRef ArchName = TargetTriple . getArchName ( ) ; <STR_LIT> AK = <STR_LIT> ( ArchName ) ; if ( AK == <STR_LIT> :: <ISA_LIT>V7S ) CPUString = <STR_LIT> ; else if ( AK == <STR_LIT> :: <ISA_LIT>V7K ) CPUString = <STR_LIT> ; } } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) { NoMovt = false ; assert ( hasV8MBaselineOps ( ) && <STR_LIT> ) ; } SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ;


<s> Parser . Lex ( ) ; return MatchOperand_Success ; } const MCExpr * LaneIndex ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( LaneIndex ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( LaneIndex ) ; if ( ! CE ) {


<s> if ( ! out_obj_filename ) fatal_error ( input_location , <STR_LIT> ) ; if ( ! dumppfx ) dumppfx = out_obj_filename ; const char * target_so_filename = prepare_target_image ( target_compiler , argc , argv ) ; const char * host_descr_filename = generate_host_descr_file ( host_compiler ) ; struct obstack argv_obstack ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , host_descr_filename ) ; obstack_ptr_grow ( & argv_obstack , target_so_filename ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , out_obj_filename ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; char * * new_argv = XOBFINISH ( & argv_obstack , char * * ) ; fork_execute ( new_argv [ <NUM_LIT> ] , new_argv , false , NULL ) ; obstack_free ( & argv_obstack , NULL ) ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ;


<s> if ( cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getZExtValue ( ) != <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getZExtValue ( ) != <NUM_LIT> ) return false ; break ; default : return false ; } return true ;


<s> ExtType ( char t , uint16_t w ) : Type ( t ) , Width ( w ) {


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> bool allFP64FP16Denormals ( ) const {


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ;


<s> unsigned getBytesToPopOnReturn ( ) const {


<s> const auto * Src1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , Paired . I , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; AddressRegs Regs = getRegs ( Opcode , * TII ) ; if ( Regs . VAddr ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ;

assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ;


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; uint64_t Value = SignExtend64 < N > ( Imm ) * <NUM_LIT> + Address ; if ( ! tryAddingSymbolicOperand ( Value , isBranch , Address , <NUM_LIT> , N / <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( Value ) ) ; return MCDisassembler :: Success ;


<s> if ( tryLess ( Top . getLatencyStallCycles ( TryCand . SU ) , Top . getLatencyStallCycles ( Cand . SU ) , TryCand , Cand , Stall ) ) return ; if ( tryGreater ( TryCand . SU == DAG -> getNextClusterSucc ( ) , Cand . SU == DAG -> getNextClusterSucc ( ) , TryCand , Cand , Cluster ) ) return ; if ( tryLess ( TryCand . ResDelta . CritResources , Cand . ResDelta . CritResources , TryCand , Cand , ResourceReduce ) ) return ; if ( tryGreater ( TryCand . ResDelta . DemandedResources , Cand . ResDelta . DemandedResources , TryCand , Cand , ResourceDemand ) ) return ; if ( Cand . Policy . ReduceLatency && tryLatency ( TryCand , Cand , Top ) ) { return ; } if ( TryCand . SU -> NodeNum < Cand . SU -> NodeNum ) TryCand . Reason = NodeOrder ; if ( TryCand . Reason != NodeOrder && TryCand . Reason != NoCand ) return ; if ( biasAddiCandidate ( Cand , TryCand ) ) return ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> return Attr . getValueAsString ( ) == <STR_LIT> ;


<s> unsigned calcLiveInMask ( MachineBasicBlock * MBB ) { unsigned Mask = <NUM_LIT> ; for ( MachineBasicBlock :: livein_iterator I = MBB -> livein_begin ( ) , E = MBB -> livein_end ( ) ; I != E ; ++ I ) { unsigned Reg = * I - <STR_LIT> ;

if ( Reg < <NUM_LIT> ) Mask |= <NUM_LIT> << Reg ;


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const {

if ( Constraint . size ( ) == <NUM_LIT> ) {


<s> int BytesCalleePops = ( CallConv == CallingConv :: Fast && PerformTailCallOpt ) ? NumBytes : <NUM_LIT> ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;

InFlag = Chain . getValue ( <NUM_LIT> ) ;


if ( MI && ( isCondBranch ( MI ) || isUncondBranch ( MI ) ) ) return MI ;


<s> if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } for ( Module :: named_metadata_iterator I = M . named_metadata_begin ( ) , E = M . named_metadata_end ( ) ; I != E ; I ++ ) { remapNamedMDNode ( & M , I ) ; } for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; ++ I ; Constant * BitCastNewGV = ConstantExpr :: getPointerCast ( NewGV , GV -> getType ( ) ) ; for ( Value :: use_iterator UI = GV -> use_begin ( ) , UE = GV -> use_end ( ) ; UI != UE ; ) ( UI ++ ) -> set ( BitCastNewGV ) ; std :: string Name = GV -> getName ( ) ; GV -> removeDeadConstantUsers ( ) ;


<s> static bool riscv_compressed_lw_offset_p ( rtx x ) { return ( CONST_INT_P ( x ) && ( INTVAL ( x ) & <NUM_LIT> ) == <NUM_LIT> && IN_RANGE ( INTVAL ( x ) , <NUM_LIT> , CSW_MAX_OFFSET ) ) ;


<s> unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , dl , <STR_LIT> ) ) , SrcPtrInfo . getWithOffset ( SrcOff ) , false , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , makeArrayRef ( TFOps , i ) ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ;


<s> unsigned char TF = <NUM_LIT> ; if ( Subtarget -> isTargetMachO ( ) ) TF = <STR_LIT> ; switch ( RelocM ) { case Reloc :: PIC_ : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; default : Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , TF ) ) ; } else { unsigned Align = DL . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; return NewDestReg ; } } } if ( IsIndirect ) { MachineInstrBuilder MIB ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; if ( isThumb2 ) MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , NewDestReg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ;

else MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , NewDestReg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ;


<s> static StringRef computeDataLayout ( const Triple & TT ) { if ( TT . getArch ( ) == Triple :: r600 ) { return <STR_LIT> <STR_LIT> ;


<s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> void <ISA_LIT>MachineFunctionInfo :: anchor ( ) {


<s> else CurrentSubEntries -= getSubEntrySize ( Top ) ; BranchStack . pop_back ( ) ;


<s> for ( i = <NUM_LIT> ; i < len ; i ++ ) { int c = p [ i ] ; if ( len_so_far >= MAX_ASCII_LEN ) { fputs ( <STR_LIT> , stream ) ; len_so_far = <NUM_LIT> ; } if ( ISPRINT ( c ) ) { if ( c == '\\' || c == '\"' ) { putc ( '\\' , stream ) ; len_so_far ++ ; }


<s> <ISA_LIT>Operand ( KindTy K , <ISA_LIT>AsmParser & Parser ) : MCParsedAsmOperand ( ) , Kind ( K ) , AsmParser ( Parser ) {


<s> static DecodeStatus DecodeBlezlGroupBranch ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ;

else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ;


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) {


if ( getOptLevel ( ) != CodeGenOpt :: None ) {


<s> short <ISA_LIT>InstrInfo :: getBaseWithLongOffset ( const MachineInstr & MI ) const {

return <STR_LIT> ( MI . getOpcode ( ) ) ;


<s> auto BlockIter = MBB . begin ( ) ; while ( BlockIter != MBB . end ( ) ) { auto & MI = * BlockIter ++ ; if ( isCVTAToLocalCombinationCandidate ( MI ) ) {


<s> if ( getMatchingLoType ( Asm , <ISA_LIT>Relocs [ I ] . R ) == ELF :: R_MIPS_NONE || ( I > <NUM_LIT> && isPrecededByMatchingHi ( Asm , I - <NUM_LIT> , <ISA_LIT>Relocs ) ) ) continue ; int32_t MatchedLoIndex = - <NUM_LIT> ; for ( int32_t J = <ISA_LIT>Relocs . size ( ) - <NUM_LIT> , N = - <NUM_LIT> ; J != N ; -- J ) { if ( areMatchingHiAndLo ( Asm , <ISA_LIT>Relocs [ I ] . R , <ISA_LIT>Relocs [ J ] . R ) && ( MatchedLoIndex == - <NUM_LIT> || ( MatchedLoIndex > J && isFreeLo ( Asm , J , <ISA_LIT>Relocs ) ) ) ) MatchedLoIndex = J ; } if ( MatchedLoIndex != - <NUM_LIT> ) setMatch ( <ISA_LIT>Relocs [ I ] , <ISA_LIT>Relocs [ MatchedLoIndex ] ) ;


<s> if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ;


<s> OptionalImmIndexMap OptionalIdx ; unsigned I = <NUM_LIT> ; const MCInstrDesc & Desc = MII . get ( Inst . getOpcode ( ) ) ; for ( unsigned J = <NUM_LIT> ; J < Desc . getNumDefs ( ) ; ++ J ) { ( ( <ISA_LIT>Operand & ) * Operands [ I ++ ] ) . addRegOperands ( Inst , <NUM_LIT> ) ; } for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( ( BasicInstType == <STR_LIT> || BasicInstType == <STR_LIT> ) && Op . isReg ( ) && Op . Reg . RegNo == <STR_LIT> ) { continue ; } else if ( isRegOrImmWithInputMods ( Desc , Inst . getNumOperands ( ) ) ) { Op . addRegWithInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { llvm_unreachable ( <STR_LIT> ) ; } } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> , <NUM_LIT> ) ; if ( Inst . getOpcode ( ) != <STR_LIT> ) { switch ( BasicInstType ) { case <STR_LIT> : addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstSel , SdwaSel :: DWORD ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstUnused , DstUnused :: UNUSED_PRESERVE ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc0Sel , SdwaSel :: DWORD ) ;


<s> if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ; part = gen_lowpart ( SImode , val ) ; gcc_assert ( GET_CODE ( part ) == CONST_INT ) ; if ( const_ok_for_arm ( INTVAL ( part ) ) || const_ok_for_arm ( ~ INTVAL ( part ) ) ) return true ;


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ;


<s> bool Vector = ( ClassID == <NUM_LIT> ) ; if ( Vector ) Result = std :: max ( Result , <NUM_LIT> ) ; return Result ;


<s> break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Printer . MF -> getContext ( ) ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ;

case MachineOperand :: MO_JumpTableIndex :


<s> pass_tiabi_check ( gcc :: context * ctxt ) : gimple_opt_pass ( pass_data_tiabi_check , ctxt ) {


<s> addPass ( createCheriAddressingModeFolder ( ) ) ;

if ( getOptLevel ( ) != CodeGenOpt :: Level :: None ) addPass ( & DeadMachineInstructionElimID ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0 ) || isa < JumpTableSDNode > ( Opnd0 ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Opnd0 ; return true ; } } const LSBaseSDNode * LS = dyn_cast < LSBaseSDNode > ( Parent ) ; if ( LS && ( LS -> getMemoryVT ( ) == <STR_LIT> || LS -> getMemoryVT ( ) == <STR_LIT> ) && Subtarget . has<ISA_LIT>32r2Or64 ( ) ) return false ; } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , ValTy ) ;


<s> operands [ <NUM_LIT> ] = force_reg ( GET_MODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = force_reg ( GET_MODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] ) ; op = gen_rtx_fmt_ee ( code , GET_MODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } if ( register_operand ( operands [ <NUM_LIT> ] , VOIDmode ) ) dest = operands [ <NUM_LIT> ] ; else dest = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , op ) ) ; if ( dest != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [ <NUM_LIT> ] , dest ) ;


<s> while ( CurrentReg != OrderEnd && ! EnabledRegs [ * CurrentReg ] ) ++ CurrentReg ; return CurrentReg ;


<s> SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , X , Op1 ) ; } } if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Z = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , ResVT , Op0 , Z ) ;


<s> unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> -> contains ( RegD ) ; RegD = get<ISA_LIT>RegisterNumbering ( RegD ) ; if ( ! isSPVFP ) { Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; } else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ;


<s> if ( RegNo == <NUM_LIT> ) Check ( S , MCDisassembler :: SoftFail ) ; Check ( S , DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ) ;


<s> static bool isSystemInstr ( const MachineInstr & MI ) { unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


if ( SysReg && SysReg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) O << SysReg -> Name ;


<s> void insert ( MachineInstr * MI ) { Insts . push_back ( MI ) ;

assert ( Insts . size ( ) <= <NUM_LIT> && <STR_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ;


<s> return true ; } Begin = <NUM_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = RC -> getSize ( ) * <NUM_LIT> / <NUM_LIT> ; if ( RR . Sub == <STR_LIT> || RR . Sub == <STR_LIT> ) Begin = Width ; break ; default : return false ; } return true ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerANDOR ( SDValue Op , SelectionDAG & DAG ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> || RHS . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;

SDValue False = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> const <ISA_LIT>InstrInfo * TII = TM . getInstrInfo ( ) ; MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned In128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , In128 ) ; if ( ClearEven ) { unsigned NewIn128 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Zero64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Zero64 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , NewIn128 ) . addReg ( In128 ) . addReg ( Zero64 ) . addImm ( <STR_LIT> ) ; In128 = NewIn128 ; } BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: INSERT_SUBREG ) , Dest ) . addReg ( In128 ) . addReg ( Src ) . addImm ( SubReg ) ; MI -> eraseFromParent ( ) ;


<s> OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; }


<s> SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ; bool MadeChange = false ;

for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> if ( candidate -> mayStore ( ) ) { if ( sawStore ) return true ; sawStore = true ; if ( sawLoad ) return true ; } assert ( ( ! candidate -> isCall ( ) && ! candidate -> isReturn ( ) ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = candidate -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = candidate -> getOperand ( i ) ; unsigned Reg ;

if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ;


<s> return ( Imm & <NUM_LIT> ) >> <NUM_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) addExpr ( Inst , getImm ( ) ) ;

else Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) >> <NUM_LIT> ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;

return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , VT , MulResult , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( isSigned ) { SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , BottomHalf , ShiftAmt ) ; TopHalf = DAG . getSetCC ( dl , <STR_LIT> , TopHalf , Tmp1 , <STR_LIT> ) ; } else { TopHalf = DAG . getSetCC ( dl , <STR_LIT> , TopHalf , DAG . getConstant ( <NUM_LIT> , VT ) , <STR_LIT> ) ; } assert ( MulResult -> use_empty ( ) && <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { BottomHalf , TopHalf } ; return DAG . getMergeValues ( Ops , dl ) ;


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const {


<s> O << <STR_LIT> ; printSDWASel ( MI , OpNo , O ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; Offset /= <NUM_LIT> ; bool FP = TFI -> hasFP ( MF ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; assert ( <STR_LIT> -> contains ( Reg ) && <STR_LIT> ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( FP ) { bool isUs = isImmUs ( Offset ) ; unsigned FramePtr = <STR_LIT> ; if ( ! isUs ) { if ( ! RS ) report_fatal_error ( <STR_LIT> + Twine ( Offset ) ) ; unsigned ScratchReg = RS -> scavengeRegister ( <STR_LIT> , II , SPAdj ) ; loadConstant ( MBB , II , ScratchReg , Offset , dl ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ; break ; case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ; break ; case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addImm ( Offset ) ; break ; case <STR_LIT> :

BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . addReg ( FramePtr ) . addImm ( Offset ) ;


<s> MBBInfo :: MBBInfo ( MachineDomTreeNode * N ) : Node ( N ) , HTScope ( <NUM_LIT> ) {


<s> ConstantSDNode * ConstOpOrElement = isConstOrConstSplat ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! ConstOpOrElement ) return SDValue ( ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) && isOperationLegal ( <STR_LIT> , N -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; auto IsProfitable = [ this ] ( bool IsNeg , bool IsAddOne , EVT VT ) -> bool { switch ( this -> Subtarget . getCPUDirective ( ) ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return IsAddOne && IsNeg ? VT . isVector ( ) : true ; } } ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; const APInt & MulAmt = ConstOpOrElement -> getAPIntValue ( ) ; bool IsNeg = MulAmt . isNegative ( ) ; APInt MulAmtAbs = MulAmt . abs ( ) ; if ( ( MulAmtAbs - <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , true , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs - <NUM_LIT> ) . logBase2 ( ) , DL , VT ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 ) ; if ( ! IsNeg ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Res ) ; } else if ( ( MulAmtAbs + <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , false , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ;

SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs + <NUM_LIT> ) . logBase2 ( ) , DL , VT ) ) ;


<s> CCValAssign & VA = RVLocs [ i ] ; if ( VA . isRegLoc ( ) ) continue ; assert ( VA . isMemLoc ( ) ) ; if ( IsVarArg ) { report_fatal_error ( <STR_LIT> ) ; } int Offset = VA . getLocMemOffset ( ) ; unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , OutVals [ i ] , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; }

if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ;


<s> if ( AI -> use_empty ( ) ) return AtomicExpansionKind :: None ; auto * C1 = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ; Instruction * I = AI -> user_back ( ) ; if ( ! C1 || ! AI -> hasOneUse ( ) || I -> getOpcode ( ) != Instruction :: And || AI -> getParent ( ) != I -> getParent ( ) ) return AtomicExpansionKind :: CmpXChg ; auto * C2 = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Bits = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ;

if ( ! C2 || Bits == <NUM_LIT> || ! isPowerOf2_64 ( C2 -> getZExtValue ( ) ) ) return AtomicExpansionKind :: CmpXChg ;


<s> unsigned Opcode = ( ! IsSigned || ! Subtarget -> hasSSE41 ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Mul1 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget -> hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ; SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op1 , ShAmt ) , Op0 ) ; SDValue Fixup = DAG . getNode ( <STR_LIT> , dl , VT , T1 , T2 ) ;

Highs = DAG . getNode ( <STR_LIT> , dl , VT , Highs , Fixup ) ;


<s> void emitTCEntry ( const MCSymbol & S ) override {


<s> uint16_t DestEncoding = TRI -> getEncodingValue ( DestReg ) ; uint16_t SrcEncoding = TRI -> getEncodingValue ( SrcReg ) ; unsigned NumRegs = Indices . size ( ) ; int SubReg = <NUM_LIT> , End = NumRegs , Incr = <NUM_LIT> ; if ( forwardCopyWillClobberTuple ( DestEncoding , SrcEncoding , NumRegs ) ) { SubReg = NumRegs - <NUM_LIT> ; End = - <NUM_LIT> ; Incr = - <NUM_LIT> ; } for ( ; SubReg != End ; SubReg += Incr ) {

const MachineInstrBuilder & MIB = BuildMI ( MBB , I , DL , get ( Opcode ) ) ;


<s> O << <STR_LIT> << LabelId << <STR_LIT> << ( unsigned ) PCAdjust ; if ( AddCurrentAddress ) O << <STR_LIT> ;


<s> static DecodeStatus decodeU16ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> split_const ( * x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( base ) ) { label = mips16_add_constant ( pool , copy_rtx ( get_pool_constant ( base ) ) , get_pool_mode ( base ) ) ;

base = gen_rtx_LABEL_REF ( Pmode , label ) ;


<s> assert ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; static const TargetRegisterClass * const BaseClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ;

for ( const TargetRegisterClass * BaseClass : BaseClasses ) {


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { unsigned Idx = IsLittleEndian ? i : <NUM_LIT> - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> if ( ST -> getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( AddrSpace == AS . FLAT_ADDRESS || AddrSpace == AS . LOCAL_ADDRESS || AddrSpace == AS . REGION_ADDRESS ) return <NUM_LIT> ; if ( AddrSpace == AS . PRIVATE_ADDRESS ) return <NUM_LIT> * ST -> getMaxPrivateElementSize ( ) ; if ( ST -> getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS && ( AddrSpace == AS . PARAM_D_ADDRESS || AddrSpace == AS . PARAM_I_ADDRESS || ( AddrSpace >= AS . CONSTANT_BUFFER_0 && AddrSpace <= AS . CONSTANT_BUFFER_15 ) ) ) return <NUM_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> int FIOffset ; if ( AfterFPPop ) { const TargetFrameInfo & TFI = * MF . getTarget ( ) . getFrameInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI . getOffsetOfLocalArea ( ) ; } else FIOffset = getFrameIndexOffset ( MF , FrameIndex ) ; if ( MI . getOperand ( i + <NUM_LIT> ) . isImm ( ) ) { int Offset = FIOffset + ( int ) ( MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> SDValue Ins = N -> getOperand ( <NUM_LIT> ) ; EVT IdxVT = Idx . getValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> , E = VecVT . getVectorNumElements ( ) ; I < E ; ++ I ) { SDValue IC = DAG . getConstant ( I , SL , IdxVT ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec , IC ) ; SDValue V = DAG . getSelectCC ( SL , Idx , IC , Ins , Elt , <STR_LIT> ) ; Ops . push_back ( V ) ; }

return DAG . getBuildVector ( VecVT , SL , Ops ) ;


<s> <ISA_LIT>Z80FrameAnalyzer ( ) : MachineFunctionPass ( ID ) {


<s> SDLoc SL ( N ) ; SDValue Cvt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cvt ) ) ; return ; } default : break ; } } case <STR_LIT> : { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ; EVT SelectVT = NewVT ; if ( NewVT . bitsLT ( <STR_LIT> ) ) { LHS = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS ) ; SelectVT = <STR_LIT> ; } SDValue NewSelect = DAG . getNode ( <STR_LIT> , SL , SelectVT , N -> getOperand ( <NUM_LIT> ) , LHS , RHS ) ; if ( NewVT != SelectVT ) NewSelect = DAG . getNode ( <STR_LIT> , SL , NewVT , NewSelect ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , VT , NewSelect ) ) ;


<s> Value * Arg = II . getArgOperand ( <NUM_LIT> ) ; Value * ArgArg ; if ( match ( Arg , PatternMatch :: m_Intrinsic < <STR_LIT> > ( PatternMatch :: m_Value ( ArgArg ) ) ) ) { return IC . replaceInstUsesWith ( II , ArgArg ) ; } if ( ! II . getMetadata ( LLVMContext :: MD_range ) ) { Type * IntTy32 = Type :: getInt32Ty ( II . getContext ( ) ) ; Metadata * M [ ] = { ConstantAsMetadata :: get ( ConstantInt :: get ( IntTy32 , <NUM_LIT> ) ) , ConstantAsMetadata :: get ( ConstantInt :: get ( IntTy32 , <NUM_LIT> ) ) } ; II . setMetadata ( LLVMContext :: MD_range , MDNode :: get ( II . getContext ( ) , M ) ) ; return & II ; } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned CarryOp = ( II . getIntrinsicID ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; assert ( II . getArgOperand ( CarryOp ) -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; KnownBits CarryKnown ( <NUM_LIT> ) ; if ( IC . SimplifyDemandedBits ( & II , CarryOp , APInt :: getOneBitSet ( <NUM_LIT> , <NUM_LIT> ) , CarryKnown ) ) { return & II ; } break ; } case <STR_LIT> : { Instruction * I = cast < Instruction > ( & II ) ; if ( I -> hasOneUse ( ) ) { auto * User = cast < Instruction > ( * I -> user_begin ( ) ) ; Value * OpZ ; if ( match ( User , m_c_Add ( m_Specific ( I ) , m_Value ( OpZ ) ) ) && match ( I -> getOperand ( <NUM_LIT> ) , m_Zero ( ) ) ) { Value * OpX = I -> getOperand ( <NUM_LIT> ) ; Value * OpY = I -> getOperand ( <NUM_LIT> ) ; Type * OpTy = OpX -> getType ( ) ; IC . Builder . SetInsertPoint ( User ) ; Value * V = IC . Builder . CreateIntrinsic ( <STR_LIT> , { OpTy } , { I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) , OpZ , OpX , OpY } ) ;

IC . replaceInstUsesWith ( * User , V ) ;


<s> rtx base_address = gen_rtx_MEM ( Pmode , pointer ) ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ix86_save_reg ( regno , maybe_eh_return ) ) { if ( TARGET_64BIT && offset != trunc_int_for_mode ( offset , SImode ) ) {


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) {

return createELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) , RelaxAll ) ;


<s> StoredVal = DAG . getBitcast ( <STR_LIT> , StoredVal ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; assert ( StoredVal . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoredVal , DAG . getUNDEF ( <STR_LIT> ) ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;

return DecodeDPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> static void ix86_emit_restore_regs_using_pop ( void ) { unsigned int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , false ) ) ix86_emit_restore_reg_using_pop ( gen_rtx_REG ( word_mode , regno ) ) ;


<s> bool HasAligna = ( MFI -> getMaxAlignment ( ) > getStackAlignment ( ) ) ; if ( ! HasAlloca || ! HasAligna ) return ; unsigned LFS = MFI -> getLocalFrameSize ( ) ; int Offset = - LFS ; for ( int i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( ! MFI -> isSpillSlotObjectIndex ( i ) || MFI -> isDeadObjectIndex ( i ) ) continue ; int S = MFI -> getObjectSize ( i ) ; LFS += S ; Offset -= S ; MFI -> mapLocalFrameObject ( i , Offset ) ; } MFI -> setLocalFrameSize ( LFS ) ; unsigned A = MFI -> getLocalFrameMaxAlign ( ) ; assert ( A <= <NUM_LIT> && <STR_LIT> ) ; if ( A == <NUM_LIT> ) MFI -> setLocalFrameMaxAlign ( <NUM_LIT> ) ; MFI -> setUseLocalStackAllocationBlock ( true ) ;


<s> MCContext & Ctx = getContext ( ) ; MCSymbol * TmpLabel = Ctx . createTempSymbol ( <STR_LIT> , true , false ) ; Out . EmitLabel ( TmpLabel ) ; MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const <ISA_LIT>MCExpr * Symbol = <ISA_LIT>MCExpr :: create ( Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( DestReg ) . addExpr ( Symbol ) ) ; const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( DestReg ) . addOperand ( DestReg ) . addExpr ( RefToLinkTmpLabel ) ) ;


<s> static void mips_autovectorize_vector_sizes ( vector_sizes * sizes ) { if ( ISA_HAS_MSA ) sizes -> safe_push ( <NUM_LIT> ) ;


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> default : return false ; } if ( ( AlignMask & Offset ) != <NUM_LIT> ) return false ;

return HII -> isValidOffset ( MI -> getOpcode ( ) , Offset , HRI , false ) ;


<s> MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( ST . getInstrInfo ( ) ) ; MachineOperand & FIOp = MI -> getOperand ( FIOperandNum ) ;

int Index = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ;


<s> AlignBranchType . addKind ( <STR_LIT> ) ; } if ( <ISA_LIT>AlignBranchBoundary . getNumOccurrences ( ) ) AlignBoundary = assumeAligned ( <ISA_LIT>AlignBranchBoundary ) ; if ( <ISA_LIT>AlignBranch . getNumOccurrences ( ) ) AlignBranchType = <ISA_LIT>AlignBranchKindLoc ; if ( <ISA_LIT>PadMaxPrefixSize . getNumOccurrences ( ) ) TargetPrefixMax = <ISA_LIT>PadMaxPrefixSize ;


<s> AMDGPUSubtarget :: AMDGPUSubtarget ( StringRef TT , StringRef GPU , StringRef FS ) : AMDGPUGenSubtargetInfo ( TT , GPU , FS ) , DevName ( GPU ) , Is64bit ( false ) , DumpCode ( false ) , R600ALUInst ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , Gen ( AMDGPUSubtarget :: R600 ) , FP64 ( false ) , CaymanISA ( false ) , EnableIRStructurizer ( true ) , EnableIfCvt ( true ) , WavefrontSize ( <NUM_LIT> ) , CFALUBug ( false ) , LocalMemorySize ( <NUM_LIT> ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) {


<s> uint32_t upper = uint32_t ( SplatVal >> <NUM_LIT> ) ; uint32_t lower = uint32_t ( SplatVal ) ; if ( upper == lower ) { SDValue Val = DAG . getTargetConstant ( upper , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , Val , Val , Val ) ) ; } else { bool upper_special , lower_special ; upper_special = ( upper == <NUM_LIT> || upper == <NUM_LIT> || upper == <NUM_LIT> ) ; lower_special = ( lower == <NUM_LIT> || lower == <NUM_LIT> || lower == <NUM_LIT> ) ; if ( lower_special && upper_special ) { SDValue UpperVal = DAG . getConstant ( upper , <STR_LIT> ) ; SDValue LowerVal = DAG . getConstant ( lower , <STR_LIT> ) ; SDValue BV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , UpperVal , LowerVal , UpperVal , LowerVal ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , BV ) ; } SDValue LO32 ; SDValue HI32 ; SmallVector < SDValue , <NUM_LIT> > ShufBytes ; SDValue Result ; if ( ! lower_special ) { SDValue LO32C = DAG . getConstant ( lower , <STR_LIT> ) ; LO32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LO32C , LO32C , LO32C , LO32C ) ) ; } if ( ! upper_special ) { SDValue HI32C = DAG . getConstant ( upper , <STR_LIT> ) ; HI32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HI32C , HI32C , HI32C , HI32C ) ) ; } if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t val = <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { SDValue V ; bool process_upper , process_lower ; val <<= <NUM_LIT> ; process_upper = ( upper_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ; process_lower = ( lower_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ; if ( process_upper || process_lower ) { if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= <NUM_LIT> ; else if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= <NUM_LIT> ; else if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= ( j == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } else val |= i * <NUM_LIT> + j + ( ( i & <NUM_LIT> ) * <NUM_LIT> ) ; } ShufBytes . push_back ( DAG . getConstant ( val , <STR_LIT> ) ) ;


<s> int c4x_O_constant ( rtx op ) { return c4x_immed_int_constant ( op ) && IS_HIGH_CONST ( INTVAL ( op ) ) ;


<s> MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( MachineFunction :: iterator I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } else NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; }


<s> return get<ISA_LIT>ArchVersion ( ) >= <STR_LIT> :: V5 ;


<s> SCEVLess ( ScalarEvolution * SE ) : SE ( SE ) {


<s> StringRef Head = Name . slice ( Start , Next ) ; unsigned RegNum = matchSVEVectorNameAlias ( Head ) ; if ( RegNum ) { if ( Next != StringRef :: npos ) { Kind = Name . slice ( Next , StringRef :: npos ) ; if ( ! isValidSVEKind ( Kind ) ) { if ( Expected ) TokError ( <STR_LIT> ) ; return - <NUM_LIT> ; } } return RegNum ;


<s> if ( SDValue Result = PerformADDCombineWithOperands ( N , N0 , N1 , DCI , Subtarget ) ) return Result ;

return PerformADDCombineWithOperands ( N , N1 , N0 , DCI , Subtarget ) ;


<s> bool <ISA_LIT>TargetLowering :: useLoadStackGuardNode ( ) const {


<s> return ( int8x16_t ) __builtin_neon_vmaxsv16qi ( __a , __b ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) {


<s> bool <ISA_LIT>MachineCFGStructurizer :: isCondBranch ( MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) {


<s> if ( TT . isOSBinFormatCOFF ( ) ) return std :: make_unique < <ISA_LIT>_COFFTargetObjectFile > ( ) ; return std :: make_unique < <ISA_LIT>_ELFTargetObjectFile > ( ) ;


<s> static bool sh_cannot_substitute_mem_equiv_p ( rtx ) { if ( TARGET_SHMEDIA ) return false ;


<s> static bool isUnalignedLoadStore ( unsigned Opc ) {

return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> LF . initialize ( MBB ) ; for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( DstReg ) || MRI -> getRegClass ( DstReg ) != & <STR_LIT> ) continue ; if ( MRI -> use_empty ( DstReg ) ) { DeadCopies . push_back ( & MI ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MRI -> setRegClass ( DstReg , & <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) continue ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) || ! isLaneMaskReg ( SrcReg ) ) { assert ( TII -> getRegisterInfo ( ) . getRegSizeInBits ( SrcReg , * MRI ) == <NUM_LIT> ) ; unsigned TmpReg = createLaneMaskReg ( * MF ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( TmpReg ) ; SrcReg = TmpReg ; } MachineBasicBlock * PostDomBound = & MBB ; for ( MachineInstr & Use : MRI -> use_instructions ( DstReg ) ) { PostDomBound = PDT -> findNearestCommonDominator ( PostDomBound , Use . getParent ( ) ) ; }

unsigned FoundLoopLevel = LF . findLoop ( PostDomBound ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) { AMDGPUA<ISA_LIT> = <STR_LIT> ( TM ) ;


<s> case ALL_REGS : case FP_REGS : case FP_LO_REGS : return aarch64_vector_mode_p ( mode ) ? ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> : ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ; case STACK_REG : return <NUM_LIT> ; case NO_REGS :


<s> SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) ) ;

const auto * GA = cast < GlobalAddressSDNode > ( Op ) ;


<s> bool llvm :: isImageReadOnly ( const llvm :: Value & val ) { if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ;


<s> return new TargetLoweringObjectFileELF ( ) ; case <ISA_LIT>Subtarget :: isMingw : case <ISA_LIT>Subtarget :: isCygwin : case <ISA_LIT>Subtarget :: isWindows : return new TargetLoweringObjectFileCOFF ( ) ; }


<s> void Emit<ISA_LIT>MappingSymbol ( ) {

if ( LastEMS == EMS_<ISA_LIT> ) return ;


<s> void addVectorPred ( MCInst & Inst , unsigned N ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> void setSavedGPRFrameSize ( unsigned bytes ) {


<s> break ; case Function :: ExternalLinkage : O << <STR_LIT> << CurrentFnName << '\n' ; break ; case Function :: WeakAnyLinkage : case Function :: WeakODRLinkage : case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage : O << <STR_LIT> << CurrentFnName << '\n' ; O << <STR_LIT> << CurrentFnName << '\n' ; break ; } printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; EmitAlignment ( F -> hasFnAttr ( Attribute :: OptimizeForSize ) ? <NUM_LIT> : <NUM_LIT> , F ) ; O << CurrentFnName << <STR_LIT> ; DW -> BeginFunction ( & MF ) ; MachineFunction :: iterator I = MF . begin ( ) ; if ( ++ I == MF . end ( ) && MF . front ( ) . empty ( ) ) O << <STR_LIT> ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true , VerboseAsm ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , IE = I -> end ( ) ;


<s> SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) && Vec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) {

unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ;


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( const MachineInstr & Use : MRI . use_nodbg_instructions ( Dst ) ) { if ( ! hasSourceMods ( Use ) ) return false ; if ( ! opMustUseVOP3Encoding ( Use , MRI ) ) { if ( ++ NumMayIncreaseSize > CostThreshold ) return false ; } } return true ;


<s> int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == <NUM_LIT> && Offs == <NUM_LIT> ) { return true ; } if ( isa < PointerType > ( Ty ) && AS == <STR_LIT> ) { return false ; }


<s> if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy ) ) {

DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ;


<s> SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) { RetOps . push_back ( Glue ) ; } const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { llvm_unreachable ( <STR_LIT> ) ; }

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Insn ) << <NUM_LIT> ) ) ;


<s> getParser ( ) . eatToEndOfStatement ( ) ; return false ; } if ( IdVal == <STR_LIT> ) { if ( has<ISA_LIT>64r6 ( ) ) { Error ( Loc , <STR_LIT> ) ; return false ; } return parseSetFeature ( <STR_LIT> ) ; } if ( IdVal == <STR_LIT> ) return parseSet<ISA_LIT>0Directive ( ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) { if ( inMicro<ISA_LIT>Mode ( ) ) { Error ( Loc , <STR_LIT> ) ; return false ; } return parseSetFeature ( <STR_LIT> ) ; } if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetNoDspDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetNo<ISA_LIT>3DDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetMsaDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNoMsaDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetMtDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNoMtDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetSoftFloatDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetHardFloatDirective ( ) ; if ( IdVal == <STR_LIT> || IdVal == <STR_LIT> ) { MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; AreCheriSysRegsAccessible = IdVal == <STR_LIT> ; return false ; }


<s> bool isSwitchAll ( ) const { return Kind == OpKind :: SwitchAll ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { auto DL = DAG . getDataLayout ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , getPointerTy ( DL ) , Offset ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result ) ;


<s> switch ( SrcVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return lowerUINT_TO_FP_v2i32 ( Op , DAG , Subtarget , dl ) ; case <STR_LIT> : case <STR_LIT> : assert ( ! Subtarget . hasAVX512 ( ) ) ; return lowerUINT_TO_FP_vXi32 ( Op , DAG , Subtarget ) ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> static const MCPhysReg CSGPCRs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; ArrayRef < MCPhysReg > CSRegs ; if ( <STR_LIT> ( STI . getTargetABI ( ) ) ) CSRegs = CSGPCRs ; else CSRegs = CSGPRs ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; Regs [ i ] ; ++ i ) if ( <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; } }


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( GV -> isDeclaration ( ) ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; Offset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } else { SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi ) ;


<s> OutStreamer . EmitLabel ( GlobalEntryLabel ) ; const MCSymbolRefExpr * GlobalEntryLabelExp = MCSymbolRefExpr :: Create ( GlobalEntryLabel , OutContext ) ; MCSymbol * TOCSymbol = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( TOCSymbol , OutContext ) , GlobalEntryLabelExp , OutContext ) ; const MCExpr * TOCDeltaHi = <ISA_LIT>MCExpr :: CreateHa ( TOCDeltaExpr , false , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = <ISA_LIT>MCExpr :: CreateLo ( TOCDeltaExpr , false , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaLo ) ) ; MCSymbol * LocalEntryLabel = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( LocalEntryLabel ) ; const MCSymbolRefExpr * LocalEntryLabelExp = MCSymbolRefExpr :: Create ( LocalEntryLabel , OutContext ) ; const MCExpr * LocalOffsetExp = MCBinaryExpr :: CreateSub ( LocalEntryLabelExp , GlobalEntryLabelExp , OutContext ) ; <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer . getTargetStreamer ( ) ) ;

if ( TS ) TS -> emitLocalEntry ( CurrentFnSym , LocalOffsetExp ) ;


<s> } if ( Disp . isImm ( ) && isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , FK_Data_1 , CurByte , OS , Fixups ) ; return ; } EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , CurByte , OS ) ; EmitImmediate ( Disp , <NUM_LIT> , MCFixupKind ( <STR_LIT> ) , CurByte , OS , Fixups ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( ! Disp . isImm ( ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp32 = true ; } else if ( Disp . getImm ( ) == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } else if ( isDisp8 ( Disp . getImm ( ) ) ) { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; ForceDisp8 = true ; } else { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , CurByte , OS ) ; } static const unsigned SSTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; unsigned SS = SSTable [ Scale . getImm ( ) ] ; if ( BaseReg == <NUM_LIT> ) { unsigned IndexRegNo ; if ( IndexReg . getReg ( ) ) IndexRegNo = Get<ISA_LIT>RegNum ( IndexReg ) ; else IndexRegNo = <NUM_LIT> ; EmitSIBByte ( SS , IndexRegNo , <NUM_LIT> , CurByte , OS ) ; } else { unsigned IndexRegNo ; if ( IndexReg . getReg ( ) ) IndexRegNo = Get<ISA_LIT>RegNum ( IndexReg ) ; else IndexRegNo = <NUM_LIT> ; EmitSIBByte ( SS , IndexRegNo , Get<ISA_LIT>RegNum ( Base ) , CurByte , OS ) ; }

if ( ForceDisp8 ) EmitImmediate ( Disp , <NUM_LIT> , FK_Data_1 , CurByte , OS , Fixups ) ;


<s> addPass ( createAMDGPUPromoteAlloca ( ST ) ) ; addPass ( createSROAPass ( ) ) ; }

TargetPassConfig :: addCodeGenPrepare ( ) ;


<s> const uint32_t * Mask ; if ( ! OutArgs . empty ( ) && OutArgs [ <NUM_LIT> ] . Flags [ <NUM_LIT> ] . isReturned ( ) ) { Mask = TRI . getThisReturnPreservedMask ( MF , Info . CallConv ) ; if ( ! Mask ) { OutArgs [ <NUM_LIT> ] . Flags [ <NUM_LIT> ] . setReturned ( false ) ;

Mask = TRI . getCallPreservedMask ( MF , Info . CallConv ) ;


<s> unsigned DivOpc = IsSigned ? <STR_LIT> : <STR_LIT> ; const SDValue & Num = N -> getOperand ( <NUM_LIT> ) ; const SDValue & Den = N -> getOperand ( <NUM_LIT> ) ; for ( const SDNode * U : Num -> uses ( ) ) {

if ( U -> getOpcode ( ) == DivOpc && U -> getOperand ( <NUM_LIT> ) == Num && U -> getOperand ( <NUM_LIT> ) == Den ) {


<s> for ( User * U : GV . users ( ) ) Stack . push_back ( U ) ; while ( ! Stack . empty ( ) ) { User * U = Stack . pop_back_val ( ) ; if ( ! Visited . insert ( U ) . second ) continue ;

if ( Instruction * I = dyn_cast < Instruction > ( U ) ) {


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ;


<s> <ISA_LIT>AIXAsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : <ISA_LIT>AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> bool emitSymbolAttribute ( MCSymbol * Symbol , MCSymbolAttr Attribute ) override {


<s> MCCodeEmitter * llvm :: create<ISA_LIT>beMCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MRI , false ) ;


<s> bool KillsOp0 = MI -> killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI -> killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ;

if ( KillsOp0 ) freeStackSlotAfter ( I , Op0 ) ;


<s> virtual llvm :: StringRef getPassName ( ) const { return <STR_LIT> ;


if ( Subtarget -> isTargetWindows ( ) ) name = <STR_LIT> ;


return ( float64x1_t ) { __builtin_fma ( __b [ <NUM_LIT> ] , __c [ <NUM_LIT> ] , __a [ <NUM_LIT> ] ) } ;


<s> return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;


<s> unsigned LoadOpcode , StoreOpcode ; getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( StoreOpcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ;


<s> assert ( Align && ( ( Align - <NUM_LIT> ) & Align ) == <NUM_LIT> ) ; StackOffset = ( ( StackOffset + Align - <NUM_LIT> ) & ~ ( Align - <NUM_LIT> ) ) ; unsigned Result = StackOffset ;


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; bool IsFSHR = Op . getOpcode ( ) == <STR_LIT> ; if ( VT . isVector ( ) ) { assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( isConstantSplat ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( VT . getScalarSizeInBits ( ) ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; if ( VT == <STR_LIT> ) Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ;

unsigned SHDOp = ( IsFSHR ? <STR_LIT> : <STR_LIT> ) ;


<s> static CodeModel :: Model getEffective<ISA_LIT>CodeModel ( Optional < CodeModel :: Model > CM , bool JIT , bool Is64Bit ) { if ( CM ) { if ( * CM == CodeModel :: Tiny ) report_fatal_error ( <STR_LIT> ) ; return * CM ;


<s> std :: vector < std :: string > load_ps ( Imm2 a ) { return D ( <STR_LIT> , a , <STR_LIT> ) ;


<s> MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr ::

Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; return current_frame_info . total_size == <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const { return true ;


<s> attr_type dep_type = get_attr_type ( dep_insn ) ; attr_type type ; if ( dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD ) cost -- ; else if ( ( dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI ) && ( type = get_attr_type ( insn ) ) != TYPE_CALL && type != TYPE_SFUNC ) cost -- ; if ( get_attr_type ( insn ) == TYPE_DYN_SHIFT && get_attr_any_int_load ( dep_insn ) == ANY_INT_LOAD_YES && reg_overlap_mentioned_p ( SET_DEST ( dep_set ) , XEXP ( SET_SRC ( single_set ( insn ) ) , <NUM_LIT> ) ) ) cost ++ ; else if ( cost < <NUM_LIT> && get_attr_insn_class ( dep_insn ) == INSN_CLASS_LS_GROUP && get_attr_dfp_comp ( insn ) == DFP_COMP_YES ) cost = <NUM_LIT> ; else if ( reload_completed && get_attr_dfp_comp ( dep_insn ) == DFP_COMP_YES && ( use_pat = single_set ( insn ) ) && ! regno_use_in ( REGNO ( SET_DEST ( single_set ( dep_insn ) ) ) , SET_SRC ( use_pat ) ) ) cost -= <NUM_LIT> ; if ( get_attr_any_fp_comp ( dep_insn ) == ANY_FP_COMP_YES && get_attr_late_fp_use ( insn ) == LATE_FP_USE_YES ) cost -= <NUM_LIT> ; } else if ( TARGET_SH4_300 ) { attr_type type ; if ( dep_set && cost >= <NUM_LIT> && ( ( type = get_attr_type ( insn ) ) == TYPE_STORE || type == TYPE_PSTORE || type == TYPE_FSTORE || type == TYPE_MAC_MEM ) ) { rtx set = single_set ( insn ) ; if ( ! reg_mentioned_p ( SET_SRC ( set ) , XEXP ( SET_DEST ( set ) , <NUM_LIT> ) ) && rtx_equal_p ( SET_SRC ( set ) , SET_DEST ( dep_set ) ) ) { cost -= <NUM_LIT> ; if ( cost < <NUM_LIT> && modified_in_p ( XEXP ( SET_DEST ( set ) , <NUM_LIT> ) , dep_insn ) ) cost = <NUM_LIT> ; } } }


<s> preserveCondRegFlags ( CondBr -> getOperand ( <NUM_LIT> ) , Cond [ <NUM_LIT> ] ) ; if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; return <NUM_LIT> ; } assert ( TBB && FBB ) ; MachineInstr * CondBr = BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; MachineOperand & CondReg = CondBr -> getOperand ( <NUM_LIT> ) ;

CondReg . setIsUndef ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; <ISA_LIT>MCExpr * Expr = const_cast < <ISA_LIT>MCExpr * > ( cast < <ISA_LIT>MCExpr > ( getImm ( ) ) ) ; int64_t Value ; if ( ! Expr -> evaluateAsAbsolute ( Value ) ) { Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; return ; }

int64_t Extended = SignExtend64 ( Value , <NUM_LIT> ) ;


<s> SDValue LenAdj = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getZExtOrTrunc ( Size , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> - Adj , DL , <STR_LIT> ) ) ; return createMemMemNode ( DAG , DL , Op , Chain , Dst , Src , LenAdj , Byte ) ;


<s> HOST_WIDE_INT offset ; unsigned int regno , i , num_x_saved = <NUM_LIT> , num_f_saved = <NUM_LIT> ; frame = & cfun -> machine -> frame ; memset ( frame , <NUM_LIT> , sizeof ( * frame ) ) ; for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( loongarch_save_reg_p ( regno ) ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( crtl -> calls_eh_return ) for ( i = <NUM_LIT> ; ( regno = EH_RETURN_DATA_REGNO ( i ) ) != INVALID_REGNUM ; i ++ ) frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ; if ( TARGET_HARD_FLOAT ) for ( regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( loongarch_save_reg_p ( regno ) ) frame -> fmask |= <NUM_LIT> << ( regno - FP_REG_FIRST ) , num_f_saved ++ ;

offset = LARCH_STACK_ALIGN ( crtl -> outgoing_args_size ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> unsigned <STR_LIT> ( SDNode * N ) { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; unsigned Mask = <NUM_LIT> ;

for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) {


<s> InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; SDValue ArgValue ; <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) { fi = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , true ) ; ArgValue = DAG . getFrameIndex ( fi , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else { unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) ; assert ( ( ObjSize <= <NUM_LIT> ) && <STR_LIT> ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << VA . getLocMemOffset ( ) << <STR_LIT> ) ; last_formal_arg_offset = stack_size - VA . getLocMemOffset ( ) - <NUM_LIT> ; fi = MFI -> CreateFixedObject ( ObjSize , last_formal_arg_offset , true ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << fi << <STR_LIT> ) ; SDValue FIN = DAG . getFrameIndex ( fi , <STR_LIT> ) ; ArgValue = DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , fi ) ) ; } InVals . push_back ( ArgValue ) ; OutChains . push_back ( ArgValue . getValue ( <NUM_LIT> ) ) ; } } if ( IsVarArg ) { <ISA_LIT>FI -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , last_formal_arg_offset - <NUM_LIT> , true ) ) ; } for ( unsigned i = <NUM_LIT> ; i < ArgLocs . size ( ) ; i ++ ) { if ( Ins [ i ] . Flags . isSRet ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( <STR_LIT> ) ) ; <ISA_LIT>FI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ i ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; } } if ( ! OutChains . empty ( ) ) { OutChains . push_back ( Chain ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutChains ) ; } return Chain ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; APFloat RealVal ( FPImm . Val ) ; uint32_t ImmVal ; A64Imms :: isFPImm ( RealVal , ImmVal ) ;

Inst . addOperand ( MCOperand :: CreateImm ( ImmVal ) ) ;


<s> getTargetStreamer ( ) . emitARM64WinCFIPrologEnd ( ) ; return false ;


<s> if ( isInlinableIntLiteral ( <ISA_LIT>mm ) ) O << <ISA_LIT>mm ;

else O << formatHex ( static_cast < uint64_t > ( Imm ) ) ;


<s> if ( GET_CODE ( length ) == CONST_INT ) { unsigned HOST_WIDE_INT bytes = UINTVAL ( length ) ; unsigned int align = UINTVAL ( align_rtx ) ; if ( align > UNITS_PER_WORD ) { align = UNITS_PER_WORD ; } else if ( align < UNITS_PER_WORD ) { if ( UINTVAL ( length ) <= MAX_MOVE_BYTES ) { move_by_pieces ( dest , src , bytes , align , RETURN_BEGIN ) ; return true ; } else return false ; } if ( UINTVAL ( length ) <= <NUM_LIT> * MAX_MOVE_BYTES ) { microblaze_block_move_straight ( dest , src , UINTVAL ( length ) ) ; return true ; } else if ( optimize ) { microblaze_block_move_loop ( dest , src , UINTVAL ( length ) ) ; return true ; }


<s> DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; const uint64_t MaxSubImm = <NUM_LIT> ; if ( Offset <= MaxSubImm ) { return <NUM_LIT> ; } else { unsigned OffsetReg = <STR_LIT> ; unsigned OffsetQ1 = ( unsigned ) ( Offset & <NUM_LIT> ) ; unsigned OffsetQ2 = ( unsigned ) ( ( Offset & <NUM_LIT> ) >> <NUM_LIT> ) ; unsigned OffsetQ3 = ( unsigned ) ( ( Offset & <NUM_LIT> ) >> <NUM_LIT> ) ;

unsigned OffsetQ4 = ( unsigned ) ( ( Offset & <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> MVT <ISA_LIT>TargetLowering :: getVecBoolVT ( ) const { return <STR_LIT> ( <STR_LIT> , <NUM_LIT> * Subtarget . getVectorLength ( ) ) ;


<s> bool enableNTBit ( const MachineBasicBlock :: iterator & MI ) const { return enableNamedBit ( MI , <STR_LIT> :: NT ) ;


<s> default : if ( Base . isReg ( ) ) O << <STR_LIT> << StringRef ( getRegisterName ( Base . getReg ( ) ) ) . lower ( ) << <STR_LIT> ; if ( Offset . isExpr ( ) ) Offset . getExpr ( ) -> print ( O , & MAI ) ; else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; O << <STR_LIT> << Offset . getImm ( ) ;


<s> rtx offset ; split_const ( x , & x , & offset ) ; return aarch64_classify_symbol ( x , INTVAL ( offset ) ) ;


<s> unsigned ArgSize = ArgVT . getSizeInBits ( ) / <NUM_LIT> ;

if ( Flags . isByVal ( ) ) ArgSize = Flags . getByValSize ( ) ;


<s> Ops . push_back ( V ) ; continue ; } MVT OpVT = V . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( OpVT ) ; assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; }

if ( ! VT . isFixedLengthVector ( ) ) return DAG . getNode ( <ISA_LIT>ISDOpc , DL , VT , Ops , Op -> getFlags ( ) ) ;


<s> EmitSled ( MI , SledKind :: FUNCTION_EXIT ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerVectorMaskTrunc ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT MaskVT = Op . getValueType ( ) ; assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Src . getValueType ( ) ; bool IsRV32E64 = ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == <STR_LIT> ; SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ; if ( ! IsRV32E64 ) { SplatOne = DAG . getSplatVector ( VecVT , DL , SplatOne ) ; SplatZero = DAG . getSplatVector ( VecVT , DL , SplatZero ) ; } else {

SplatOne = DAG . getNode ( <STR_LIT> , DL , VecVT , SplatOne ) ;


<s> } else if ( EnableTCLatencySched ) {

if ( QII . isTC1 ( SrcInst ) || QII . isTC2 ( SrcInst ) ) if ( ! QII . isTC1 ( DstInst ) && ! QII . isTC2 ( DstInst ) ) Dep . setLatency ( Dep . getLatency ( ) + <NUM_LIT> ) ;


<s> void addRegVRRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateReg ( VRegs [ getReg ( ) ] ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) { unsigned val = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( val != <NUM_LIT> ) ; }


<s> getParser ( ) . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; const AsmToken & Reg = Parser . getTok ( ) ; if ( Reg . is ( AsmToken :: Identifier ) ) { AtRegNo = matchCPURegisterName ( Reg . getIdentifier ( ) ) ; } else if ( Reg . is ( AsmToken :: Integer ) ) { AtRegNo = Reg . getIntVal ( ) ; } else { reportParseError ( <STR_LIT> ) ; return false ; } if ( AtRegNo < <NUM_LIT> || AtRegNo > <NUM_LIT> ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! Options . setATReg ( AtRegNo ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; }


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) {


<s> switch ( MI -> getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> auto I = S2 . find ( P . first ) ; if ( I == S2 . end ( ) || I -> second != P . second ) return false ;


<s> } ; auto IsReassociable = [ & ] ( const MachineInstr & Instr , int16_t & AddOpIdx , bool IsLeaf , bool IsAdd ) { int16_t Idx = - <NUM_LIT> ; if ( ! IsAdd ) { Idx = getFMAOpIdxInfo ( Instr . getOpcode ( ) ) ; if ( Idx < <NUM_LIT> ) return false ; } else if ( Instr . getOpcode ( ) != FMAOpIdxInfo [ getFMAOpIdxInfo ( Root . getOpcode ( ) ) ] [ InfoArrayIdxFAddInst ] ) return false ; if ( ! ( Instr . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Instr . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ) ) return false ; if ( ! IsAllOpsVirtualReg ( Instr ) ) return false ; if ( IsAdd && IsLeaf ) return true ; AddOpIdx = FMAOpIdxInfo [ Idx ] [ InfoArrayIdxAddOpIdx ] ; const MachineOperand & OpAdd = Instr . getOperand ( AddOpIdx ) ; MachineInstr * MIAdd = MRI . getUniqueVRegDef ( OpAdd . getReg ( ) ) ; if ( ! MIAdd || MIAdd -> getParent ( ) != MBB ) return false ; return IsLeaf ? true : MRI . hasOneNonDBGUse ( OpAdd . getReg ( ) ) ; } ; int16_t AddOpIdx = - <NUM_LIT> ; if ( ! IsReassociable ( Root , AddOpIdx , false , false ) ) return false ; assert ( ( AddOpIdx >= <NUM_LIT> ) && <STR_LIT> ) ; Register RegB = Root . getOperand ( AddOpIdx ) . getReg ( ) ; MachineInstr * Prev = MRI . getUniqueVRegDef ( RegB ) ; AddOpIdx = - <NUM_LIT> ; if ( ! IsReassociable ( * Prev , AddOpIdx , false , false ) ) return false ; assert ( ( AddOpIdx >= <NUM_LIT> ) && <STR_LIT> ) ; Register RegA = Prev -> getOperand ( AddOpIdx ) . getReg ( ) ; MachineInstr * Leaf = MRI . getUniqueVRegDef ( RegA ) ; AddOpIdx = - <NUM_LIT> ; if ( IsReassociable ( * Leaf , AddOpIdx , true , false ) ) { Patterns . push_back ( MachineCombinerPattern :: REASSOC_XMM_AMM_BMM ) ; return true ; } if ( IsReassociable ( * Leaf , AddOpIdx , true , true ) ) { Patterns . push_back ( MachineCombinerPattern :: REASSOC_XY_AMM_BMM ) ; return true ;


<s> <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT VT = Op . getValueType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; if ( ExtType == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Chain = Load -> getChain ( ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; MachineMemOperand * MMO = Load -> getMemOperand ( ) ; SDValue NewLD = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , BasePtr , <STR_LIT> , MMO ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , VT , NewLD ) , NewLD . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } if ( Subtarget -> getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS || Load -> getAddressSpace ( ) != <STR_LIT> || ExtType == <STR_LIT> || Load -> getMemoryVT ( ) . bitsGE ( <STR_LIT> ) ) return SDValue ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ; if ( ExtType == <STR_LIT> ) { SDValue MemEltVTNode = DAG . getValueType ( MemEltVT ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , MemEltVTNode ) , Load -> getChain ( ) } ;


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ;


<s> if ( ( hasQPX ( ) || isBGQ ( ) ) && ! isQPXStackUnaligned ( ) ) return <NUM_LIT> ;


<s> const MCDwarfFrameInfo & Frame = Out . getDwarfFrameInfos ( ) . back ( ) ; if ( Frame . End ) return <STR_LIT> ; const MCRegisterInfo * MRI = Ctx . getRegisterInfo ( ) ; if ( ! MRI ) return <STR_LIT> ; if ( InitialFrameReg ) { return InitialFrameReg ; }

return MRI -> getLLVMRegNum ( Frame . CurrentCfaRegister , true ) ;


<s> if ( orig [ i ] == '\0' || equiv [ i ] == '\0' ) return false ; if ( orig [ i ] != equiv [ i ] ) { if ( ( orig [ i ] == 'Q' || orig [ i ] == 'L' ) && equiv [ i ] == 'W' ) continue ; if ( ( orig [ i ] == '6' || orig [ i ] == '3' ) && equiv [ i ] == '1' ) continue ; if ( ( orig [ i ] == '4' || orig [ i ] == '2' ) && equiv [ i ] == '6' ) continue ; return false ; }


<s> if ( TT . getObjectFormat ( ) == Triple :: ELF ) return new <ISA_LIT>TargetELFStreamer ( S ) ; return new <ISA_LIT>TargetMachOStreamer ( S ) ;


<s> static bool nds32_symbol_binds_local_p ( const_rtx x ) {

return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ;


<s> } else if ( TheTriple . getOS ( ) == Triple :: MinGW32 || TheTriple . getOS ( ) == Triple :: Cygwin ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( is64Bit ? <STR_LIT> : <STR_LIT> , stackGrowth ) ; MAI -> addInitialFrameState ( <NUM_LIT> , Dst , Src ) ; MachineLocation CSDst ( is64Bit ? <STR_LIT> : <STR_LIT> , stackGrowth ) ; MachineLocation CSSrc ( is64Bit ? <STR_LIT> : <STR_LIT> ) ; MAI -> addInitialFrameState ( <NUM_LIT> , CSDst , CSSrc ) ; return MAI ;


<s> else append_name ( instance . mode_suffix ( ) . string ) ; for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( ! overloaded_p || instance . shape -> explicit_type_suffix_p ( i ) ) append_name ( instance . type_suffix ( i ) . string ) ; append_name ( pred_suffixes [ instance . pred ] ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : if ( ! MI -> isCall ( ) ) { Write = true ; Effects = true ; } break ; } } if ( MI -> hasUnmodeledSideEffects ( ) ) { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : Effects = true ; break ; } } if ( MI -> isCall ( ) ) { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> :

QueryCallee ( MI , <NUM_LIT> , Read , Write , Effects , StackPointer ) ;


<s> Imm = CurDAG -> getTargetConstant ( Val & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && Val % <NUM_LIT> == <NUM_LIT> ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ( Val >> <NUM_LIT> ) & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } break ; default : break ; } return false ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> for ( auto & MI : MBB ) { InstrPos [ & MI ] = Pos += <NUM_LIT> ;

if ( isLEA ( MI ) ) LEAs [ getMemOpKey ( MI , <NUM_LIT> ) ] . push_back ( const_cast < MachineInstr * > ( & MI ) ) ;


<s> static __inline qword si_clgth ( qword a , qword b ) {

return ( ( qword ) ( vec_cmpgt ( ( vec_ushort8 ) ( a ) , ( vec_ushort8 ) ( b ) ) ) ) ;


<s> bool <ISA_LIT>ShrinkInstructions :: runOnMachineFunction ( MachineFunction & MF ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & TRI = TII -> getRegisterInfo ( ) ; std :: vector < unsigned > I1Defs ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( MI . getOpcode ( ) == AMDGPU :: S_MOV_B32 ) { const MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( Src . isImm ( ) ) { if ( isInt < <NUM_LIT> > ( Src . getImm ( ) ) && ! TII -> isInlineConstant ( Src , <NUM_LIT> ) ) MI . setDesc ( TII -> get ( AMDGPU :: S_MOVK_I32 ) ) ; } continue ; } if ( ! TII -> hasVALU32BitEncoding ( MI . getOpcode ( ) ) ) continue ; if ( ! canShrink ( MI , TII , TRI , MRI ) ) { if ( ! MI . isCommutable ( ) || ! TII -> commuteInstruction ( & MI ) || ! canShrink ( MI , TII , TRI , MRI ) ) continue ; } if ( ! TII -> hasVALU32BitEncoding ( MI . getOpcode ( ) ) ) continue ;

int Op32 = AMDGPU :: getVOPe32 ( MI . getOpcode ( ) ) ;


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const {


<s> return ( int32x2_t ) __builtin_neon_vrsubhnv2di ( __a , __b ) ;


<s> BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) , DestReg ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sbase ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC0 ) . addImm ( CI . DLC0 ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sdst ) ;

const auto * Dest1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: sdst ) ;


<s> EVT PtrVT = getPointerTy ( ) ; TLSModel :: Model model = DAG . getTarget ( ) . getTLSModel ( GV ) ; if ( model != TLSModel :: LocalExec ) llvm_unreachable ( <STR_LIT> ) ; SDValue TPHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ;

SDValue TP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted , TPLo ) ;


<s> InstrumentMemOperand ( * Op , AccessSize , false , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , DstReg , <NUM_LIT> , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , true , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: Create ( - <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , DstReg , CntReg , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ;