<s> } else if ( Opc == <STR_LIT> ) { const SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; const SDValue Op1 = N . getOperand ( <NUM_LIT> ) ; if ( ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> ) || ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) ) { Base = CurDAG -> getTargetConstant ( <NUM_LIT> , PtrTy ) ; Index = N ; return true ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> || Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op1 ) ; int32_t offset = int32_t ( CN -> getSExtValue ( ) ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op0 ) ; int FI = int ( FIN -> getIndex ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << offset << <STR_LIT> << FI << <STR_LIT> ) ; if ( <ISA_LIT>FrameLowering :: FItoStackOffset ( FI ) < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return true ; } } else if ( offset > minOffset && offset < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = Op0 ; return true ; } } else if ( Op0 . getOpcode ( ) == <STR_LIT> || Op0 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op0 ) ; int32_t offset = int32_t ( CN -> getSExtValue ( ) ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) { FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op1 ) ; int FI = int ( FIN -> getIndex ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << offset << <STR_LIT> << FI << <STR_LIT> ) ; if ( <ISA_LIT>FrameLowering :: FItoStackOffset ( FI ) < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = CurDAG -> getTargetFrameIndex ( FI , PtrTy ) ; return true ; } } else if ( offset > minOffset && offset < maxOffset ) { Base = CurDAG -> getTargetConstant ( offset , PtrTy ) ; Index = Op1 ; return true ; } } } else if ( Opc == <STR_LIT> ) { const SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; const SDValue Op1 = N . getOperand ( <NUM_LIT> ) ;

if ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> ) {


<s> while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; while ( AGGREGATE_TYPE_P ( type ) ) { tree field = TYPE_FIELDS ( type ) ;

while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ;


<s> error_at ( location , <STR_LIT> <STR_LIT> , get_argument_type ( argno ) , argno + <NUM_LIT> , fndecl , expected ) ; return false ; }


<s> MIB . addUse ( PhysReg , RegState :: Implicit ) ; Register ExtReg = extendRegisterMin32 ( * this , ValVReg , VA ) ;

MIRBuilder . buildCopy ( PhysReg , ExtReg ) ;


<s> in_set ( const NodeSet & S ) : NS ( S ) {


<s> int64_t getConstantMemOff ( ) const {

return static_cast < const MCConstantExpr * > ( getMemOff ( ) ) -> getValue ( ) ;


<s> hi_half [ num ] = adjust_address ( op , SImode , <NUM_LIT> ) ; } else {

lo_half [ num ] = simplify_gen_subreg ( SImode , op , GET_MODE ( op ) == VOIDmode ? DImode : GET_MODE ( op ) , <NUM_LIT> ) ;


<s> case <STR_LIT> : NonKernelOnly = true ; return WORKITEM_ID_X ; case <STR_LIT> : NonKernelOnly = true ; return WORKGROUP_ID_X ; case <STR_LIT> : case <STR_LIT> : return WORKITEM_ID_Y ; case <STR_LIT> : case <STR_LIT> : return WORKITEM_ID_Z ; case <STR_LIT> : case <STR_LIT> : return WORKGROUP_ID_Y ; case <STR_LIT> : case <STR_LIT> : return WORKGROUP_ID_Z ; case <STR_LIT> : return DISPATCH_PTR ; case <STR_LIT> : return DISPATCH_ID ; case <STR_LIT> : return IMPLICIT_ARG_PTR ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void unicosmk_add_extern ( const char * name ) { struct unicosmk_extern_list * p ; p = ( struct unicosmk_extern_list * ) xmalloc ( sizeof ( struct unicosmk_extern_list ) ) ; p -> next = unicosmk_extern_head ; p -> name = name ; unicosmk_extern_head = p ;


<s> auto Node = Kernel . getMetadata ( <STR_LIT> ) ; if ( Node && Node -> getNumOperands ( ) == <NUM_LIT> ) return mdconst :: extract < ConstantInt > ( Node -> getOperand ( Dim ) ) -> getZExtValue ( ) ; return std :: numeric_limits < unsigned > :: max ( ) ;


<s> Arg . mPointeeAlign = PointeeAlign ; if ( auto PtrTy = dyn_cast < PointerType > ( Ty ) ) Arg . mAddrSpaceQual = getAddressSpaceQualifier ( PtrTy -> getAddressSpace ( ) ) ; Arg . mAccQual = getAccessQualifier ( AccQual ) ; SmallVector < StringRef , <NUM_LIT> > SplitTypeQuals ; TypeQual . split ( SplitTypeQuals , <STR_LIT> , - <NUM_LIT> , false ) ; for ( StringRef Key : SplitTypeQuals ) { auto P = StringSwitch < bool * > ( Key ) . Case ( <STR_LIT> , & Arg . mIsConst ) . Case ( <STR_LIT> , & Arg . mIsRestrict ) . Case ( <STR_LIT> , & Arg . mIsVolatile ) . Case ( <STR_LIT> , & Arg . mIsPipe ) . Default ( nullptr ) ; if ( P ) * P = true ;


<s> std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } else if ( CTVal && CFVal && CTVal -> isOne ( ) && CFVal -> isNullValue ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } else if ( TVal . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( TVal . getOperand ( <NUM_LIT> ) ) ; if ( CVal && CVal -> isAllOnesValue ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } } else if ( TVal . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( TVal . getOperand ( <NUM_LIT> ) ) ; if ( CVal && CVal -> isNullValue ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } } else if ( CTVal && CFVal ) { const int64_t TrueVal = CTVal -> getSExtValue ( ) ; const int64_t FalseVal = CFVal -> getSExtValue ( ) ; bool Swap = false ; if ( TrueVal == ~ FalseVal ) { Opcode = <STR_LIT> ; } else if ( TrueVal == - FalseVal ) { Opcode = <STR_LIT> ; } else if ( TVal . getValueType ( ) == <STR_LIT> ) { const uint32_t TrueVal32 = CTVal -> getZExtValue ( ) ; const uint32_t FalseVal32 = CFVal -> getZExtValue ( ) ; if ( ( TrueVal32 == FalseVal32 + <NUM_LIT> ) || ( TrueVal32 + <NUM_LIT> == FalseVal32 ) ) { Opcode = <STR_LIT> ; if ( TrueVal32 > FalseVal32 ) { Swap = true ; }


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; void EmitBasicBlockEnd ( const MachineBasicBlock & MBB ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier = nullptr ) ; void printRegisterList ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void EmitStartOfAsmFile ( Module & M ) override ; void EmitEndOfAsmFile ( Module & M ) override ;

void PrintDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) ;


<s> static void addSavedGPR ( MachineBasicBlock & MBB , MachineInstrBuilder & MIB , unsigned GPR64 , bool IsImplicit ) {

const TargetRegisterInfo * RI = MBB . getParent ( ) -> getTarget ( ) . getRegisterInfo ( ) ;


<s> } ; bool PrecUp = RAI . covers ( QR , RR ) ; if ( any_of ( Defs , AliasQR ) ) { if ( PrecUp ) break ; continue ; } NodeAddr < DefNode * > RDA = * I ; if ( TAP . Id == <NUM_LIT> ) { TAP = TA ; } else { TAP . Addr -> setFlags ( TAP . Addr -> getFlags ( ) | NodeAttrs :: Shadow ) ; TAP = getNextShadow ( IA , TAP , true ) ; } TAP . Addr -> linkToDef ( TAP . Id , RDA ) ; if ( PrecUp ) break ; Defs . insert ( QR ) ; }


<s> static bool alg_usable_p ( enum stringop_alg alg , bool memset , bool have_as ) { if ( alg == no_stringop ) return false ; if ( alg == vector_loop ) return TARGET_SSE || TARGET_AVX ;

if ( alg == rep_prefix_1_byte || alg == rep_prefix_4_byte || alg == rep_prefix_8_byte ) {


<s> <ISA_LIT>TTIImpl ( <ISA_LIT>TTIImpl && Arg ) : BaseT ( std :: move ( static_cast < BaseT & > ( Arg ) ) ) , TM ( std :: move ( Arg . TM ) ) , ST ( std :: move ( Arg . ST ) ) , TLI ( std :: move ( Arg . TLI ) ) {


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) { unsigned Val = ( MO . getImm ( ) & <NUM_LIT> ) ; assert ( Val == MO . getImm ( ) && <STR_LIT> ) ; unsigned Shift = <STR_LIT> ( MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ) ;


<s> M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: <ISA_LIT>_FastCall ) ; F -> addAttribute ( <NUM_LIT> , Attribute :: AttrKind :: InReg ) ; }


<s> assert ( AddcNode -> getNumValues ( ) == <NUM_LIT> && AddcNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( AddcNode -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( AddcOp0 -> getOpcode ( ) != <STR_LIT> && AddcOp0 -> getOpcode ( ) != <STR_LIT> && AddcOp1 -> getOpcode ( ) != <STR_LIT> && AddcOp1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDNode * AddeNode = AddcNode -> getGluedUser ( ) ; if ( AddeNode == NULL ) return SDValue ( ) ; if ( AddeNode -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( AddeNode -> getNumOperands ( ) == <NUM_LIT> && AddeNode -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue AddeOp0 = AddeNode -> getOperand ( <NUM_LIT> ) ; SDValue AddeOp1 = AddeNode -> getOperand ( <NUM_LIT> ) ; if ( AddeOp0 . getNode ( ) == AddeOp1 . getNode ( ) ) return SDValue ( ) ; bool IsLeftOperandMUL = false ; SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiMul = & MULOp ; SDValue * HiAdd = NULL ; SDValue * LoMul = NULL ; SDValue * LowAdd = NULL ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 -> getOpcode ( ) == Opc ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; }

if ( AddcOp1 -> getOpcode ( ) == Opc ) {


<s> if ( MCID . isReturn ( ) || MCID . isCall ( ) ) return false ;


<s> const DISubprogram * SP = F -> getSubprogram ( ) ; if ( ! SP || SP -> isDefinition ( ) ) return ;

if ( ProtoFunctions . find ( F ) != ProtoFunctions . end ( ) ) return ;


<s> <ISA_LIT>LoadStoreOpt ( ) : MachineFunctionPass ( ID ) {


<s> return __builtin_mve_vcmpeqq_v4si ( ( int32x4_t ) __a , ( int32x4_t ) __b ) ;


<s> const auto & Tok = Parser . getTok ( ) ; SMLoc StartLoc = Tok . getLoc ( ) ; SMLoc EndLoc = Tok . getEndLoc ( ) ; RegisterKind RegKind ; unsigned Reg , RegNum , RegWidth ; if ( ! Parse<ISA_LIT>Register ( RegKind , Reg , RegNum , RegWidth ) ) { Error ( StartLoc , <STR_LIT> ) ; return nullptr ; } if ( <STR_LIT> :: hasCodeObjectV3 ( & getSTI ( ) ) ) {

if ( ! updateGprCountSymbols ( RegKind , RegNum , RegWidth ) ) return nullptr ;


<s> ArrayRef < MCPhysReg > <ISA_LIT>ABIInfo :: GetByValArgRegs ( ) const { if ( IsCheriPureCap ( ) ) return { } ; if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ;

if ( IsN32 ( ) || IsN64 ( ) ) return makeArrayRef ( <ISA_LIT>64IntRegs ) ;


<s> CONSTEXPR svprf_bhwd_impl ( machine_mode mode ) : m_mode ( mode ) {


<s> <ISA_LIT>ModeRegisterDefaults ( ) : IEEE ( true ) , DX10Clamp ( true ) , FP32Denormals ( true ) , FP64FP16Denormals ( true ) {


<s> AddDefaultPred ( BuildMI ( * fallthrough , fallthrough -> instr_end ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) ) . addMBB ( target -> MBB ) ; AddDefaultPred ( BuildMI ( * fallthrough , fallthrough -> instr_end ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } MachineBasicBlock :: iterator II = fallthrough -> end ( ) ; -- II ; unsigned cycles = PTM . getSubtargetImpl ( ) -> getDelaySlotCycles ( & * II ) ; if ( PTM . getSubtargetImpl ( ) -> getCFLType ( ) != <ISA_LIT>Subtarget :: CFL_NON_DELAYED && ! PII . hasRegUse ( & * II ) ) { cycles = PII . moveUp ( * fallthrough , II ) ;


<s> if ( Op . isReg ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else if ( Op . isFPImm ( ) ) { assert ( OpNo < Desc . getNumOperands ( ) && <STR_LIT> ) ; assert ( Desc . TSFlags == <NUM_LIT> && <STR_LIT> ) ; if ( Info . OperandType == <STR_LIT> ) { O << Op . getFPImm ( ) ; } else { assert ( Info . OperandType == <STR_LIT> ) ;


<s> case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ;

CmpMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> static bool zero_call_used_regno_p ( const unsigned int regno , bool all_sse_zeroed , bool need_zero_mmx ) { return GENERAL_REGNO_P ( regno ) || ( ! all_sse_zeroed && SSE_REGNO_P ( regno ) ) || MASK_REGNO_P ( regno ) || ( need_zero_mmx && MMX_REGNO_P ( regno ) ) ;


PrefAlign = ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> MBBInfo & Block = MBBs [ I ] ; Block . Alignment = MBB -> getAlignment ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; MachineBasicBlock :: iterator End = MBB -> end ( ) ; while ( MI != End && ! MI -> isTerminator ( ) ) { Block . Size += TII -> getInstSizeInBytes ( * MI ) ;


<s> return __builtin_arm_crypto_sha1su1 ( __tw0_3 , __w12_15 ) ;


<s> static bool isHardwareLoopOne ( const MachineInstr & MI ) {

return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> int leading_ones = clz_hwi ( ~ value ) ; int trailing_ones = ctz_hwi ( ~ value ) ; if ( leading_ones < <NUM_LIT> && ( ( <NUM_LIT> - leading_ones - trailing_ones ) < <NUM_LIT> ) ) { codes [ <NUM_LIT> ] . code = UNKNOWN ; codes [ <NUM_LIT> ] . value = ( ( ( unsigned HOST_WIDE_INT ) value >> trailing_ones ) | ( value << ( <NUM_LIT> - trailing_ones ) ) ) ; codes [ <NUM_LIT> ] . code = ROTATERT ; codes [ <NUM_LIT> ] . value = <NUM_LIT> - trailing_ones ; cost = <NUM_LIT> ; } else { int upper_trailing_ones = ctz_hwi ( ~ value >> <NUM_LIT> ) ; int lower_leading_ones = clz_hwi ( ~ value << <NUM_LIT> ) ; if ( upper_trailing_ones < <NUM_LIT> && lower_leading_ones < <NUM_LIT> && ( ( <NUM_LIT> - upper_trailing_ones - lower_leading_ones ) < <NUM_LIT> ) ) { codes [ <NUM_LIT> ] . code = UNKNOWN ; codes [ <NUM_LIT> ] . value = ( ( value << ( <NUM_LIT> - upper_trailing_ones ) ) | ( ( unsigned HOST_WIDE_INT ) value >> ( <NUM_LIT> + upper_trailing_ones ) ) ) ; codes [ <NUM_LIT> ] . code = ROTATERT ; codes [ <NUM_LIT> ] . value = <NUM_LIT> - upper_trailing_ones ; cost = <NUM_LIT> ; }


<s> static inline bool getMemDoShift ( unsigned Imm ) { return ( Imm & <NUM_LIT> ) != <NUM_LIT> ;


<s> unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; LLT SrcTy = MRI . getType ( Src ) ; unsigned DestAS = DstTy . getAddressSpace ( ) ; unsigned SrcAS = SrcTy . getAddressSpace ( ) ; assert ( ! DstTy . isVector ( ) ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ST . getTargetLowering ( ) -> isNoopAddrSpaceCast ( SrcAS , DestAS ) ) { MI . setDesc ( MIRBuilder . getTII ( ) . get ( TargetOpcode :: G_BITCAST ) ) ; return true ; } if ( SrcAS == <ISA_LIT>AS :: FLAT_ADDRESS ) { assert ( DestAS == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; unsigned NullVal = TM . getNullPointerValue ( DestAS ) ; auto SegmentNull = MIRBuilder . buildConstant ( DstTy , NullVal ) ; auto FlatNull = MIRBuilder . buildConstant ( SrcTy , <NUM_LIT> ) ; unsigned PtrLo32 = MRI . createGenericVirtualRegister ( DstTy ) ; MIRBuilder . buildExtract ( PtrLo32 , Src , <NUM_LIT> ) ; unsigned CmpRes = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildICmp ( CmpInst :: ICMP_NE , CmpRes , Src , FlatNull . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildSelect ( Dst , CmpRes , PtrLo32 , SegmentNull . getReg ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ; } assert ( SrcAS == <ISA_LIT>AS :: LOCAL_ADDRESS || SrcAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; auto SegmentNull = MIRBuilder . buildConstant ( SrcTy , TM . getNullPointerValue ( SrcAS ) ) ; auto FlatNull = MIRBuilder . buildConstant ( DstTy , TM . getNullPointerValue ( DestAS ) ) ; unsigned ApertureReg = getSegmentAperture ( DestAS , MRI , MIRBuilder ) ; unsigned CmpRes = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildICmp ( CmpInst :: ICMP_NE , CmpRes , Src , SegmentNull . getReg ( <NUM_LIT> ) ) ; unsigned BuildPtr = MRI . createGenericVirtualRegister ( DstTy ) ; unsigned SrcAsInt = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildInstr ( TargetOpcode :: G_PTRTOINT ) . addDef ( SrcAsInt ) . addUse ( Src ) ; MIRBuilder . buildMerge ( BuildPtr , { SrcAsInt , ApertureReg } ) ; MIRBuilder . buildSelect ( Dst , CmpRes , BuildPtr , FlatNull . getReg ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return true ;


<s> ELF<ISA_LIT>_32AsmBackend ( const Target & T , Triple :: OSType OSType ) : ELF<ISA_LIT>AsmBackend ( T , OSType ) {


<s> case <STR_LIT> : if ( ! Subtarget . hasSSE2 ( ) || FromVT != <STR_LIT> ) return false ; return ToVT == <STR_LIT> || ( Subtarget . hasAVX ( ) && ToVT == <STR_LIT> ) ; case <STR_LIT> :

if ( ! Subtarget . hasAVX512 ( ) || FromVT != <STR_LIT> ) return false ;


<s> if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Integer ) ) return TokError ( <STR_LIT> ) ; int64_t Id = getParser ( ) . getTok ( ) . getIntVal ( ) ; if ( Id <= - <NUM_LIT> && ! isValidMCLOHType ( Id ) ) return TokError ( <STR_LIT> ) ; Kind = ( MCLOHType ) Id ; } else { StringRef Name = getTok ( ) . getIdentifier ( ) ; int Id = MCLOHNameToId ( Name ) ; if ( Id == - <NUM_LIT> ) return TokError ( <STR_LIT> ) ; Kind = ( MCLOHType ) Id ; } Lex ( ) ; int NbArgs = MCLOHIdToNbArgs ( Kind ) ; assert ( NbArgs != - <NUM_LIT> && <STR_LIT> ) ; SmallVector < MCSymbol * , <NUM_LIT> > Args ; for ( int Idx = <NUM_LIT> ; Idx < NbArgs ; ++ Idx ) { StringRef Name ; if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; Args . push_back ( getContext ( ) . getOrCreateSymbol ( Name ) ) ;

if ( Idx + <NUM_LIT> == NbArgs ) break ;


<s> explicit <ISA_LIT>ScalarTargetTransformImpl ( const TargetLowering * TL ) :

ScalarTargetTransformImpl ( TL ) , Subtarget ( & TL -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ) { }


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; LLVMContext * Context = DAG . getContext ( ) ; assert ( Subtarget -> hasSSE41 ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> ) { Op = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; ConstantInt * CI = ConstantInt :: get ( * Context , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; std :: vector < Constant * > CV ( <NUM_LIT> , CI ) ; Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Addend = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT , Op , Addend ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Op , R ) ; }


<s> static opt_scalar_float_mode arm_floatn_mode ( int n , bool extended ) { if ( ! extended && n == <NUM_LIT> ) {

if ( arm_fp16_format == ARM_FP16_FORMAT_IEEE ) return HFmode ;


<s> static SDValue lowerFABS32 ( SDValue Op , SelectionDAG & DAG , bool HasExtractInsert ) { SDLoc DL ( Op ) ; SDValue Res , Const1 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue X = ( Op . getValueType ( ) == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ;

if ( HasExtractInsert ) Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Const1 , X ) ;


<s> hi_chain = riscv_force_binary ( SImode , AND , hi_chain , uimm_mask ) ; lui_hi_chain_code = OPCODE_LUI | ( STATIC_CHAIN_REGNUM << SHIFT_RD ) ; rtx lui_hi_chain = riscv_force_binary ( SImode , IOR , hi_chain , gen_int_mode ( lui_hi_chain_code , SImode ) ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ; riscv_emit_move ( mem , riscv_swap_instruction ( lui_hi_chain ) ) ; rtx hi_func = riscv_force_binary ( SImode , PLUS , target_function , fixup_value ) ; hi_func = riscv_force_binary ( SImode , AND , hi_func , uimm_mask ) ; lui_hi_func_code = OPCODE_LUI | ( RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD ) ; rtx lui_hi_func = riscv_force_binary ( SImode , IOR , hi_func , gen_int_mode ( lui_hi_func_code , SImode ) ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> * GET_MODE_SIZE ( SImode ) ) ; riscv_emit_move ( mem , riscv_swap_instruction ( lui_hi_func ) ) ; rtx lo_chain = riscv_force_binary ( SImode , AND , chain_value , imm12_mask ) ; lo_chain = riscv_force_binary ( SImode , ASHIFT , lo_chain , GEN_INT ( <NUM_LIT> ) ) ; lo_chain_code = OPCODE_ADDI | ( STATIC_CHAIN_REGNUM << SHIFT_RD ) | ( STATIC_CHAIN_REGNUM << SHIFT_RS1 ) ; rtx addi_lo_chain = riscv_force_binary ( SImode , IOR , lo_chain , force_reg ( SImode , GEN_INT ( lo_chain_code ) ) ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> * GET_MODE_SIZE ( SImode ) ) ; riscv_emit_move ( mem , riscv_swap_instruction ( addi_lo_chain ) ) ; rtx lo_func = riscv_force_binary ( SImode , AND , target_function , imm12_mask ) ; lo_func = riscv_force_binary ( SImode , ASHIFT , lo_func , GEN_INT ( <NUM_LIT> ) ) ; lo_func_code = OPCODE_JALR | ( RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1 ) ; rtx jr_lo_func = riscv_force_binary ( SImode , IOR , lo_func , force_reg ( SImode , GEN_INT ( lo_func_code ) ) ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateTokenWithStringCopy ( StringRef Str , SMLoc S , bool Is<ISA_LIT>64 ) { void * Mem = :: operator new ( sizeof ( <ISA_LIT>Operand ) + Str . size ( ) ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( new ( Mem ) <ISA_LIT>Operand ( Token ) ) ; Op -> Tok . Data = reinterpret_cast < const char * > ( Op . get ( ) + <NUM_LIT> ) ; Op -> Tok . Length = Str . size ( ) ; std :: memcpy ( const_cast < char * > ( Op -> Tok . Data ) , Str . data ( ) , Str . size ( ) ) ;


<s> void <ISA_LIT>InstrInfo :: insertOutlinerPrologue ( MachineBasicBlock & MBB , MachineFunction & MF , bool IsTailCall ) const {


<s> HII = HST . getInstrInfo ( ) ; HRI = HST . getRegisterInfo ( ) ; bool Changed = false ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return nullptr ;


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr & MI ) const { if ( MI . mayStore ( ) && ! Subtarget . useNewValueStores ( ) ) return false ; const uint64_t F = MI . getDesc ( ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> void LLVMInitializeDcpu16TargetInfo ( ) { RegisterTarget < Triple :: dcpu16 > X ( TheDcpu16Target , <STR_LIT> , <STR_LIT> ) ;


<s> std :: vector < std :: string > getCallMagicLabels ( ) { std :: vector < std :: string > labels ;

for ( int i = <NUM_LIT> ; i < sgx_call_magic_labels_index ; i ++ ) labels . push_back ( <STR_LIT> + std :: to_string ( i ) ) ;


<s> SDValue Mul1 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget . hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT , DAG . getDataLayout ( ) ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ;

SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op1 , ShAmt ) , Op0 ) ;


<s> if ( Modifier && strncmp ( Modifier , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { if ( strncmp ( Modifier + <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; else if ( strncmp ( Modifier + <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; else assert ( <NUM_LIT> && <STR_LIT> ) ; } O << '%' << TRI -> getAsmName ( Reg ) ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; return ; case MachineOperand :: MO_JumpTableIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; printOffset ( MO . getOffset ( ) ) ; break ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; std :: string Name = Mang -> getMangledName ( GV ) ; O << Name ; break ;


<s> BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) , LimitReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( ThreadEnvironmentStackLimit ) . addReg ( <STR_LIT> ) ; BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( FinalReg ) . addReg ( LimitReg ) ; BuildMI ( & MBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( ContinueMBB ) ; BuildMI ( RoundMBB , DL , TII . get ( <STR_LIT> ) , RoundedReg ) . addReg ( FinalReg ) . addImm ( PageMask ) ; BuildMI ( RoundMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( LoopMBB ) ; if ( ! InProlog ) { BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) , JoinReg ) . addReg ( LimitReg ) . addMBB ( RoundMBB ) . addReg ( ProbeReg ) . addMBB ( LoopMBB ) ; } addRegOffset ( BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) , ProbeReg ) , JoinReg , false , - PageSize ) ; BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ProbeReg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( RoundedReg ) . addReg ( ProbeReg ) ; BuildMI ( LoopMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( LoopMBB ) ; MachineBasicBlock :: iterator ContinueMBBI = ContinueMBB -> getFirstNonPHI ( ) ; if ( InProlog ) { addRegOffset ( BuildMI ( * ContinueMBB , ContinueMBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , false , RCXShadowSlot ) ; addRegOffset ( BuildMI ( * ContinueMBB , ContinueMBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , false , RDXShadowSlot ) ; } BuildMI ( * ContinueMBB , ContinueMBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( SizeReg ) ; MBB . addSuccessor ( ContinueMBB ) ;


<s> const MCTargetOptions & getTargetOptions ( ) const {


<s> if ( compare_diff_p ( insn ) ) { rtx_insn * next = next_real_insn ( insn ) ; rtx pat = PATTERN ( next ) ; pattern = SET_SRC ( pattern ) ; if ( true_regnum ( XEXP ( pattern , <NUM_LIT> ) ) >= <NUM_LIT> && true_regnum ( XEXP ( pattern , <NUM_LIT> ) ) >= <NUM_LIT> ) { rtx x = XEXP ( pattern , <NUM_LIT> ) ; rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , <NUM_LIT> ) ; PUT_CODE ( t , swap_condition ( GET_CODE ( t ) ) ) ; XEXP ( pattern , <NUM_LIT> ) = XEXP ( pattern , <NUM_LIT> ) ; XEXP ( pattern , <NUM_LIT> ) = x ; INSN_CODE ( next ) = - <NUM_LIT> ; } else if ( true_regnum ( XEXP ( pattern , <NUM_LIT> ) ) >= <NUM_LIT> && XEXP ( pattern , <NUM_LIT> ) == const0_rtx ) { rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , <NUM_LIT> ) ; PUT_CODE ( t , swap_condition ( GET_CODE ( t ) ) ) ; XEXP ( pattern , <NUM_LIT> ) = XEXP ( pattern , <NUM_LIT> ) ; XEXP ( pattern , <NUM_LIT> ) = const0_rtx ; INSN_CODE ( next ) = - <NUM_LIT> ; INSN_CODE ( insn ) = - <NUM_LIT> ; } else if ( true_regnum ( XEXP ( pattern , <NUM_LIT> ) ) >= <NUM_LIT> && CONST_INT_P ( XEXP ( pattern , <NUM_LIT> ) ) ) { rtx x = XEXP ( pattern , <NUM_LIT> ) ;


<s> bool enableMultipleCopyHints ( ) const override {


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const Triple & TT ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) , TT ( TT ) {


<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { Changes |= insertWait ( MBB , I , handleOperands ( * I ) ) ; pushInstruction ( * I ) ; } Changes |= insertWait ( MBB , MBB . getFirstTerminator ( ) , LastIssued ) ;


<s> for ( size_t i = <NUM_LIT> ; i < <ISA_LIT>GOTPLT0Num ; ++ i ) { create ( ) ; }


<s> static unsigned calculateSetFPREG ( uint64_t SPAdjust ) { const uint64_t Win64MaxSEHOffset = <NUM_LIT> ; uint64_t SEHFrameOffset = std :: min ( SPAdjust , Win64MaxSEHOffset ) ; return SEHFrameOffset & - <NUM_LIT> ;


<s> unsigned getCommonDomains ( unsigned mask ) const {


<s> static MachineBasicBlock :: iterator FindLastAluClause ( MachineBasicBlock & MBB ) { for ( MachineBasicBlock :: reverse_iterator It = MBB . rbegin ( ) , E = MBB . rend ( ) ; It != E ; ++ It ) { if ( It -> getOpcode ( ) == <STR_LIT> || It -> getOpcode ( ) == <STR_LIT> ) return It . getReverse ( ) ; } return MBB . end ( ) ;


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ExpandPseudoPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>InstrInfo :: getRegisterInfo ( ) const {


<s> int regno = REGNO ( dest ) ; rtx dest1 = gen_highpart ( SImode , dest ) ; rtx dest2 = gen_lowpart ( SImode , dest ) ; rtx address = XEXP ( source , <NUM_LIT> ) ; if ( GET_CODE ( address ) == PRE_MODIFY || ! refers_to_regno_p ( regno , regno + <NUM_LIT> , address , NULL ) ) { emit_move_insn ( dest1 , change_address ( source , SImode , NULL ) ) ; emit_move_insn ( dest2 , frv_index_memory ( source , SImode , <NUM_LIT> ) ) ; }


<s> MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : break ; case AMDGPU :: <ISA_LIT>_IF : ++ Depth ; If ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_ELSE : Else ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_BREAK : Break ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_IF_BREAK : IfBreak ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_ELSE_BREAK : ElseBreak ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_LOOP : ++ Depth ; Loop ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_END_CF : if ( -- Depth == <NUM_LIT> && HaveKill ) { SkipIfDead ( MI ) ; HaveKill = false ; } EndCf ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_KILL : if ( Depth == <NUM_LIT> ) SkipIfDead ( MI ) ; else HaveKill = true ; Kill ( MI ) ; break ; case AMDGPU :: S_BRANCH : Branch ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_INDIRECT_SRC : IndirectSrc ( MI ) ; break ;

case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V2 :


<s> Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; SplatBits |= <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; SplatBits |= <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ; Imm = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) { Val |= BitMask ; Imm |= ImmMask ; } else if ( ( SplatBits & BitMask ) != <NUM_LIT> ) { return SDValue ( ) ; } BitMask <<= <NUM_LIT> ;


<s> SDValue BasePtr = Load -> getBasePtr ( ) ; MachineMemOperand * MMO = Load -> getMemOperand ( ) ; SDValue NewLD = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , BasePtr , <STR_LIT> , MMO ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , MemVT , NewLD ) , NewLD . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } if ( ! MemVT . isVector ( ) ) return SDValue ( ) ; assert ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned AS = Load -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , AS , Load -> getAlignment ( ) ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , DL ) ; } unsigned NumElements = MemVT . getVectorNumElements ( ) ; switch ( AS ) { case <ISA_LIT>AS :: CONSTANT_ADDRESS : if ( isMemOpUniform ( Load ) ) return SDValue ( ) ; LLVM_FALLTHROUGH ; case <ISA_LIT>AS :: GLOBAL_ADDRESS : case <ISA_LIT>AS :: FLAT_ADDRESS : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; case <ISA_LIT>AS :: PRIVATE_ADDRESS : { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorLoad ( Load , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } case <ISA_LIT>AS :: LOCAL_ADDRESS : { if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; if ( NumElements == <NUM_LIT> ) return SDValue ( ) ; return SplitVectorLoad ( Op , DAG ) ; } default :


<s> static nodes_iterator nodes_begin ( const GraphType & G ) { return G . Blocks . begin ( ) ;


<s> static void EmitDefCfaRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc dl , const TargetInstrInfo & TII , MachineModuleInfo * MMI , unsigned DRegNum ) {

unsigned CFIIndex = MMI -> addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , DRegNum ) ) ;


<s> case <STR_LIT> : LowerDextDins ( TmpInst ) ; } unsigned long N = Fixups . size ( ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; if ( STI . getFeatureBits ( ) & <STR_LIT> ) { int NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back ( ) ; Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; } } const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ;

if ( ! Size ) llvm_unreachable ( <STR_LIT> ) ;


<s> const char * getDataLayoutString ( ) const { return <STR_LIT> <STR_LIT> <STR_LIT> ;


<s> if ( ! FrameSize || FrameSize > Subtarget . getRedZoneSize ( ) ) return false ; if ( hasFP ( MF ) || RegInfo -> hasBasePointer ( MF ) ) return false ;

if ( FI -> hasFastCall ( ) || FI -> usesPICBase ( ) ) return false ;


<s> static SDValue LowerScalarVariableShift ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opcode = Op . getOpcode ( ) ; unsigned <ISA_LIT>OpcI = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned <ISA_LIT>OpcV = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Amt = peekThroughEXTRACT_SUBVECTORs ( Amt ) ; if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Opcode ) ) { if ( SDValue BaseShAmt = IsSplatValue ( VT , Amt , dl , DAG , Subtarget , Opcode ) ) { MVT EltVT = VT . getVectorElementType ( ) ; assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; return getTargetVShiftNode ( <ISA_LIT>OpcI , dl , VT , R , BaseShAmt , Subtarget , DAG ) ; } } if ( VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getSimpleValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ;

std :: vector < SDValue > Vals ( Ratio ) ;


<s> return _semctl ( semid , semnum , cmd , arg << SHIFT_BITS ) ;


<s> if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; else Offset += <NUM_LIT> ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == <NUM_LIT> ) return ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Offset < <NUM_LIT> ) BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ;

MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> if ( code == BPF_BUILTIN_LOAD_BYTE || code == BPF_BUILTIN_LOAD_HALF || code == BPF_BUILTIN_LOAD_WORD ) { enum insn_code abs_icode = ( code == BPF_BUILTIN_LOAD_BYTE ? CODE_FOR_ldabsb : code == BPF_BUILTIN_LOAD_HALF ? CODE_FOR_ldabsh : CODE_FOR_ldabsw ) ; enum insn_code ind_icode = ( code == BPF_BUILTIN_LOAD_BYTE ? CODE_FOR_ldindb : code == BPF_BUILTIN_LOAD_HALF ? CODE_FOR_ldindh : CODE_FOR_ldindw ) ; tree offset_arg = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; struct expand_operand ops [ <NUM_LIT> ] ; create_input_operand ( & ops [ <NUM_LIT> ] , expand_normal ( offset_arg ) , TYPE_MODE ( TREE_TYPE ( offset_arg ) ) ) ; create_input_operand ( & ops [ <NUM_LIT> ] , const0_rtx , SImode ) ; if ( ! maybe_expand_insn ( abs_icode , <NUM_LIT> , ops ) && ! maybe_expand_insn ( ind_icode , <NUM_LIT> , ops ) ) { error ( <STR_LIT> ) ; return gen_rtx_REG ( ops [ <NUM_LIT> ] . mode , BPF_R0 ) ; } return gen_rtx_REG ( ops [ <NUM_LIT> ] . mode , BPF_R0 ) ; } else if ( code == - BPF_BUILTIN_PRESERVE_ACCESS_INDEX ) {

tree arg = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ;


<s> StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & CTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , CPU , FS , CTM ) ;


<s> Value = adjustFixupValue ( Fixup , Value , IsPCRel , Ctx , IsLittleEndian , true ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; unsigned FullSizeBytes ; if ( ! IsLittleEndian ) {

FullSizeBytes = getFixupKindContainerSizeBytes ( Fixup . getKind ( ) ) ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) {


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MCB . dump_pretty ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MCB . setLoc ( IDLoc ) ; const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; <ISA_LIT>MCChecker Check ( getContext ( ) , MCII , getSTI ( ) , MCB , * RI ) ; bool CheckOk = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , getSTI ( ) , getContext ( ) , MCB , & Check ) ; if ( CheckOk ) { if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) == <NUM_LIT> ) { assert ( ! <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCB ) ) ; assert ( ! <ISA_LIT>MCInstrInfo :: isOuterLoop ( MCB ) ) ; return false ; } Out . EmitInstruction ( MCB , getSTI ( ) ) ; } else { if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) > HEXAGON_PACKET_SIZE ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } } return false ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FramePointerSaveIndex ( <NUM_LIT> ) , ReturnAddrSaveIndex ( <NUM_LIT> ) , HasSpills ( false ) , HasNonRISpills ( false ) , SpillsCR ( false ) , SpillsVRSAVE ( false ) , LRStoreRequired ( false ) , MinReservedArea ( <NUM_LIT> ) , TailCallSPDelta ( <NUM_LIT> ) , HasFastCall ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgsStackOffset ( <NUM_LIT> ) , VarArgsNumGPR ( <NUM_LIT> ) , VarArgsNumFPR ( <NUM_LIT> ) , CRSpillFrameIndex ( <NUM_LIT> ) {


<s> llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ;


<s> static <ISA_LIT>Operand :: Ptr CreateReg ( const <ISA_LIT>AsmParser * AsmParser , unsigned RegNo , SMLoc S , SMLoc E ) {

auto Op = llvm :: make_unique < <ISA_LIT>Operand > ( Register , AsmParser ) ;


<s> void changeSection ( const MCSection * CurSection , MCSection * Section , const MCExpr * SubSection , raw_ostream & OS ) override {


<s> SupportsDebugInformation = true ; CommentString = <STR_LIT> ;


<s> if ( count != <NUM_LIT> ) return NULL_RTX ;

return get_hard_reg_initial_val ( Pmode , CSKY_LR_REGNUM ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned & OpNum , const TargetRegisterInfo * TRI ) const {

if ( ! hasUndefRegUpdate ( MI . getOpcode ( ) , OpNum ) ) return <NUM_LIT> ;


<s> emitLEAzii ( * OutStreamer , cim24 , loImm , RegS0 , STI ) ; MCOperand M032 = MCOperand :: createImm ( M0 ( <NUM_LIT> ) ) ; emitANDrm ( * OutStreamer , RegS0 , M032 , RegS0 , STI ) ; emitSIC ( * OutStreamer , RegLR , STI ) ; MCOperand hiImm = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI32 , AddrSym , OutContext ) ; emitLEASLrri ( * OutStreamer , RegS0 , RegLR , hiImm , RegS0 , STI ) ; MCOperand ci8 = MCOperand :: createImm ( <NUM_LIT> ) ; MCOperand loImm2 = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_LO32 , GetTLSLabel , OutContext ) ; emitLEAzii ( * OutStreamer , ci8 , loImm2 , RegS12 , STI ) ; emitANDrm ( * OutStreamer , RegS12 , M032 , RegS12 , STI ) ; MCOperand hiImm2 = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_HI32 , GetTLSLabel , OutContext ) ;

emitLEASLrri ( * OutStreamer , RegS12 , RegLR , hiImm2 , RegS12 , STI ) ;


<s> static __inline void __attribute__ ( ( __always_inline__ ) ) _MM_SET_ROUNDING_MODE ( unsigned int __mode ) {

_mm_setcsr ( ( _mm_getcsr ( ) & ~ _MM_ROUND_MASK ) | __mode ) ;


return ( __m128d ) __builtin_ia32_sqrtpd ( ( __v2df ) __A ) ;


<s> if ( TARGET_64BIT && ! TARGET_POWERPC64 ) { rs6000_isa_flags |= OPTION_MASK_POWERPC64 ; warning ( <NUM_LIT> , <STR_LIT> ) ; } if ( flag_mkernel ) { rs6000_default_long_calls = <NUM_LIT> ; rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT ; } if ( ! flag_mkernel && ! flag_apple_kext && TARGET_64BIT && ! ( rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC ) ) rs6000_isa_flags |= OPTION_MASK_ALTIVEC ; if ( ! flag_mkernel && ! flag_apple_kext && strverscmp ( darwin_macosx_version_min , <STR_LIT> ) >= <NUM_LIT> && ! ( rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC ) && ! global_options_set . x_rs6000_cpu_index ) { rs6000_isa_flags |= OPTION_MASK_ALTIVEC ; }


<s> bool isMemOffs16_8 ( ) const { return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> <ISA_LIT>MachObjectWriter ( uint32_t CPUType , uint32_t CPUSubtype , bool IsILP32 ) : MCMachObjectTargetWriter ( ! IsILP32 , CPUType , CPUSubtype ) {


<s> bool hasPredRes ( ) const { return HasPredRes ;


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( ) ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) {

if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) {


<s> pushReg ( AsReg ) ; BuildMI ( * MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addReg ( STReg ) ;


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = TFI -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> hasFnAttribute ( Attribute :: StackAlignment ) ) ; return requiresRealignment && canRealignStack ( MF ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> static bool microblaze_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ;


<s> Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ;


<s> static int fr30_num_arg_regs ( machine_mode mode , const_tree type ) { int size ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return <NUM_LIT> ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ( size + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> bool isPICBase = false ; for ( MachineRegisterInfo :: def_iterator I = MRI . def_begin ( BaseReg ) , E = MRI . def_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = I . getOperand ( ) . getParent ( ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase && <STR_LIT> ) ; isPICBase = true ; } return isPICBase ;


<s> static __inline qword si_ila ( unsigned int imm ) {

return ( ( qword ) ( vec_splat ( ( vec_uint4 ) ( si_from_uint ( imm ) ) , <NUM_LIT> ) ) ) ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ;


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'q' : switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } case 'v' : switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && UseHVX && UseHVXDbl ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) return Opc ;

if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? Opcodes . SEXT8 : Opcodes . SEXT16 ;


<s> SDValue Chain2 = N2 -> getOperand ( <NUM_LIT> ) ; if ( Chain1 == Chain2 ) return Chain1 ; return SDValue ( ) ;


<s> int <ISA_LIT>RegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { llvm_unreachable ( <STR_LIT> ) ; return - <NUM_LIT> ;


<s> if ( N . getOpcode ( ) != <STR_LIT> ) return false ; FrameIndexSDNode * FX = cast < FrameIndexSDNode > ( N ) ;

R = CurDAG -> getTargetFrameIndex ( FX -> getIndex ( ) , <STR_LIT> ) ;


<s> for ( MachineBasicBlock * MBB : CurLoop -> getBlocks ( ) ) { for ( const MachineInstr & MI : MBB -> instrs ( ) ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { return true ; } if ( <ISA_LIT>InstrInfo :: isMMIOAccess ( MI ) ) { return true ; } for ( const MachineOperand & MO : MI . defs ( ) ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; if ( MO . getReg ( ) . isPhysical ( ) ) continue ; const TargetRegisterClass * RC = MRI -> getRegClass ( MO . getReg ( ) ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { return true ; } } } } return false ;


<s> OutMI . addOperand ( OutMI . getOperand ( <NUM_LIT> ) ) ; OutMI . addOperand ( OutMI . getOperand ( <NUM_LIT> ) ) ;


<s> return D ( <STR_LIT> , MemR ( a , as ) ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T ) : MCAsmBackend ( ) {


<s> struct ix86_address parts ; int ok ; if ( ! TARGET_AVOID_LEA_FOR_ADDR || optimize_function_for_size_p ( cfun ) ) return false ; if ( REG_P ( operands [ <NUM_LIT> ] ) || ( SImode_address_operand ( operands [ <NUM_LIT> ] , VOIDmode ) && REG_P ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ) return false ; if ( ! ix86_ok_to_clobber_flags ( insn ) ) return false ; ok = ix86_decompose_address ( operands [ <NUM_LIT> ] , & parts ) ; gcc_assert ( ok ) ; if ( ( parts . base != NULL_RTX ) + ( parts . index != NULL_RTX ) + ( parts . disp != NULL_RTX ) + ( parts . scale > <NUM_LIT> ) < <NUM_LIT> ) return false ; if ( parts . disp && flag_pic && ! LEGITIMATE_PIC_OPERAND_P ( parts . disp ) ) return false ; regno0 = true_regnum ( operands [ <NUM_LIT> ] ) ; regno1 = INVALID_REGNUM ; regno2 = INVALID_REGNUM ; if ( parts . base ) regno1 = true_regnum ( parts . base ) ; if ( parts . index ) regno2 = true_regnum ( parts . index ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> ; i < numArgs ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i + <NUM_LIT> ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ; return BB ;


<s> return false ; } if ( eatTerm ( FuncName , <STR_LIT> ) ) F . Impl = std :: make_unique < <ISA_LIT>MangledLibFunc > ( ) ;

else F . Impl = std :: make_unique < <ISA_LIT>UnmangledLibFunc > ( ) ;


<s> Arg1 = Builder . CreateSelect ( Builder . CreateICmpSLT ( Arg1 , MinC ) , MinC , Arg1 ) ; Arg0 = Builder . CreateSelect ( Builder . CreateICmpSGT ( Arg0 , MaxC ) , MaxC , Arg0 ) ; Arg1 = Builder . CreateSelect ( Builder . CreateICmpSGT ( Arg1 , MaxC ) , MaxC , Arg1 ) ; SmallVector < int , <NUM_LIT> > PackMask ; for ( unsigned Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { for ( unsigned Elt = <NUM_LIT> ; Elt != NumSrcEltsPerLane ; ++ Elt ) PackMask . push_back ( Elt + ( Lane * NumSrcEltsPerLane ) ) ; for ( unsigned Elt = <NUM_LIT> ; Elt != NumSrcEltsPerLane ; ++ Elt ) PackMask . push_back ( Elt + ( Lane * NumSrcEltsPerLane ) + NumSrcElts ) ; }

auto * Shuffle = Builder . CreateShuffleVector ( Arg0 , Arg1 , PackMask ) ;


<s> fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ;


<s> else emit_insn ( gen_load_gotsi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp1 = mips_get_tp ( ) ; offset = mips_unspec_address ( loc , SYMBOL_TPREL ) ; if ( mips_split_p [ SYMBOL_TPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_TPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , <NUM_LIT> , <NUM_LIT> , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } return dest ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> int offset ; addr_space_t as = DEFAULT_TLS_SEG_REG ; rtx r ; gcc_assert ( flag_split_stack ) ; offset = TARGET_THREAD_SPLIT_STACK_OFFSET ; gcc_unreachable ( ) ; r = GEN_INT ( offset ) ; r = gen_const_mem ( Pmode , r ) ; set_mem_addr_space ( r , as ) ;


<s> return emitAddSub_rr ( false , RetVT , LHSReg , RHSReg , true , WantResult ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ;


<s> switch ( l ) { default : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : case GlobalValue :: LinkerPrivateLinkage : break ; case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << <STR_LIT> ; break ; case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : O << TAI -> getGlobalDirective ( ) << name << <STR_LIT> ; O << TAI -> getWeakDefDirective ( ) << name << <STR_LIT> ; break ; }


<s> if ( SrcReg == <NUM_LIT> ) return false ; Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ;

if ( ! <ISA_LIT>EmitStore ( VT , SrcReg , Addr , cast < StoreInst > ( I ) -> getAlignment ( ) ) ) return false ;


else if ( AARCH64_CHECK_BUILTIN_MODE ( <NUM_LIT> , S ) ) builtin = AARCH64_SIMD_BUILTIN_UNOP_lceilv2sfv2si ;


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; bool IsValid ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> int64_t Enabled = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t Done = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t VM = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) , VM , false , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { const DebugLoc & DL = I . getDebugLoc ( ) ; int64_t Tgt = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ;


<s> static void EmitDefCfaRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & dl , const TargetInstrInfo & TII , MachineFunction & MF , unsigned DRegNum ) {

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , DRegNum ) ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine * TM , CodeGenOpt :: Level OptLevel ) :

<ISA_LIT>DAGToDAGISel ( TM , OptLevel ) {


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWinEHHandlerData ( SMLoc Loc ) {

MCStreamer :: EmitWinEHHandlerData ( Loc ) ;


<s> static inline bool isSingleUnscheduledSucc ( SUnit * SU , SUnit * SU2 ) { if ( SU -> NumSuccsLeft == <NUM_LIT> ) return false ;


<s> setAttributeItem ( Virtualization_use , AllowTZ , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6M : setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7A : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7R : setAttributeItem ( CPU_arch_profile , RealTimeProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V7M : setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V8A : case <STR_LIT> :: <ISA_LIT>V8_1A : case <STR_LIT> :: <ISA_LIT>V8_2A : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; setAttributeItem ( MPextension_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZVirtualization , false ) ; break ;


<s> rbt_inorder_callback ( t , subtree -> left , fn ) ; ( * fn ) ( subtree -> str ) ; rbt_inorder_callback ( t , subtree -> right , fn ) ;


<s> unsigned Size = ScalarVT . getSizeInBits ( ) ; if ( Size == <NUM_LIT> ) return ScalarVT . getSimpleVT ( ) ; if ( Size == <NUM_LIT> ) return <STR_LIT> ;

if ( Size == <NUM_LIT> && Subtarget -> has16BitInsts ( ) ) return VT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ;


<s> static SDVTList getMemMemVTs ( unsigned Op , SelectionDAG & DAG ) { return Op == <STR_LIT> ? DAG . getVTList ( <STR_LIT> , <STR_LIT> ) : DAG . getVTList ( <STR_LIT> ) ;


<s> Offset += getOffsetOfLocalArea ( ) ; } if ( IsWin64Prologue ) { assert ( ! MFI . hasCalls ( ) || ( StackSize % <NUM_LIT> ) == <NUM_LIT> ) ; uint64_t FrameSize = StackSize - SlotSize ; if ( <ISA_LIT>FI -> getRestoreBasePointer ( ) ) FrameSize += SlotSize ; uint64_t NumBytes = FrameSize - CSSize ; uint64_t SEHFrameOffset = calculateSetFPREG ( NumBytes ) ; if ( FI && FI == <ISA_LIT>FI -> getFAIndex ( ) ) return StackOffset :: getFixed ( - SEHFrameOffset ) ; FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI . hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return StackOffset :: getFixed ( Offset + SlotSize + FPDelta ) ; } else { assert ( isAligned ( MFI . getObjectAlign ( FI ) , - ( Offset + StackSize ) ) ) ; return StackOffset :: getFixed ( Offset + StackSize ) ; } } else if ( TRI -> hasStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return StackOffset :: getFixed ( Offset + SlotSize + FPDelta ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoCapMode ( ) {


<s> return D ( <STR_LIT> , a , R ( b ) ) ;


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCSymbol * Symbol , <ISA_LIT>MCExpr :: <ISA_LIT>ExprKind Kind , MCContext & Ctx ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ;

return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , MCSym ) ;


<s> SmallVector < <STR_LIT> , <NUM_LIT> > Params ; const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; for ( const MachineOperand & MO : MI -> defs ( ) ) Returns . push_back ( getType ( MRI . getRegClass ( MO . getReg ( ) ) ) ) ; for ( const MachineOperand & MO : MI -> explicit_uses ( ) ) if ( MO . isReg ( ) ) Params . push_back ( getType ( MRI . getRegClass ( MO . getReg ( ) ) ) ) ; if ( <STR_LIT> ( * MI ) ) Params . pop_back ( ) ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Sym ) ; WasmSym -> setReturns ( std :: move ( Returns ) ) ; WasmSym -> setParams ( std :: move ( Params ) ) ; WasmSym -> setIsFunction ( true ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( WasmSym , MCSymbolRefExpr :: VK_<ISA_LIT>_TYPEINDEX , Ctx ) ; MCOp = MCOperand :: createExpr ( Expr ) ; break ; } } } MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_FPImmediate : { const ConstantFP * Imm = MO . getFPImm ( ) ; if ( Imm -> getType ( ) -> isFloatTy ( ) ) MCOp = MCOperand :: createFPImm ( Imm -> getValueAPF ( ) . convertToFloat ( ) ) ; else if ( Imm -> getType ( ) -> isDoubleTy ( ) ) MCOp = MCOperand :: createFPImm ( Imm -> getValueAPF ( ) . convertToDouble ( ) ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; } case MachineOperand :: MO_GlobalAddress : assert ( MO . getTargetFlags ( ) == <NUM_LIT> && <STR_LIT> ) ;

MCOp = LowerSymbolOperand ( GetGlobalAddressSymbol ( MO ) , MO . getOffset ( ) , MO . getGlobal ( ) -> getValueType ( ) -> isFunctionTy ( ) ) ;


<s> return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ) ;


<s> TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;


<s> bool loongarch_global_symbol_noweak_p ( const_rtx x ) { if ( LABEL_REF_P ( x ) ) return false ; const_tree decl = SYMBOL_REF_DECL ( x ) ; if ( ! decl ) return ! SYMBOL_REF_LOCAL_P ( x ) || SYMBOL_REF_EXTERNAL_P ( x ) ;

return DECL_P ( decl ) && TREE_PUBLIC ( decl ) ;


<s> ModulePass * create<ISA_LIT>ClonerPass ( ) { return new <ISA_LIT>Cloner ( ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) {

if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override { return & Subtarget ;


<s> Filler ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , TII ( tm . getInstrInfo ( ) ) {


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , uint8_t _OSABI , StringRef CPU ) : <ISA_LIT>AsmBackend ( T , CPU ) , OSABI ( _OSABI ) {


<s> unsigned getMinNumVGPRs ( unsigned WavesPerEU ) const {

return <STR_LIT> :: getMinNumVGPRs ( MCSubtargetInfo :: getFeatureBits ( ) , WavesPerEU ) ;


<s> break ; case <STR_LIT> : if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Val = cast < ConstantSDNode > ( Node ) -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Val ) && ! <STR_LIT> ( Val ) && ! isInt < <NUM_LIT> > ( Val ) ) { splitLargeImmediate ( <STR_LIT> , Node , SDValue ( ) , Val - uint32_t ( Val ) , uint32_t ( Val ) ) ; return ; } } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) || ( Subtarget -> hasLoadStoreOnCond2 ( ) && Node -> getValueType ( <NUM_LIT> ) . isInteger ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op1 ) -> getSExtValue ( ) ) && ! ( Op0 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op0 ) -> getSExtValue ( ) ) ) ) ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode ( ) ) -> getZExtValue ( ) ; uint64_t ConstCCMask = cast < ConstantSDNode > ( CCMask . getNode ( ) ) -> getZExtValue ( ) ; CCMask = CurDAG -> getConstant ( ConstCCValid ^ ConstCCMask , SDLoc ( Node ) , CCMask . getValueType ( ) ) ; SDValue Op4 = Node -> getOperand ( <NUM_LIT> ) ; SDNode * UpdatedNode = CurDAG -> UpdateNodeOperands ( Node , Op1 , Op0 , CCValid , CCMask , Op4 ) ; if ( UpdatedNode != Node ) { ReplaceNode ( Node , UpdatedNode ) ; Node = UpdatedNode ; } } break ; } case <STR_LIT> : { EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ElemBitSize = VT . getScalarSizeInBits ( ) ; if ( ElemBitSize == <NUM_LIT> ) { if ( tryGather ( Node , <STR_LIT> ) ) return ; } else if ( ElemBitSize == <NUM_LIT> ) { if ( tryGather ( Node , <STR_LIT> ) ) return ; } break ; } case <STR_LIT> : { auto * BVN = cast < BuildVectorSDNode > ( Node ) ; <ISA_LIT>VectorConstantInfo VCI ( BVN ) ; if ( VCI . isVectorConstantLegal ( * Subtarget ) ) { loadVectorConstant ( VCI , Node ) ; return ; } break ; } case <STR_LIT> : { APFloat Imm = cast < ConstantFPSDNode > ( Node ) -> getValueAPF ( ) ; if ( Imm . isZero ( ) || Imm . isNegZero ( ) ) break ;

<ISA_LIT>VectorConstantInfo VCI ( Imm ) ;


<s> SDLoc dl ( Op ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; assert ( C && <STR_LIT> ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ;

EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getValueType ( ) . getVectorNumElements ( ) ) ;


<s> bool use<ISA_LIT>PostRASchedStrategy ( ) const { return Use<ISA_LIT>PostRASchedStrategy ;


<s> rtx reg = gen_rtx_REG ( Pmode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , <NUM_LIT> ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ;


<s> if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ;


<s> SDValue ES = DAG . getTargetExternalSymbol ( tmpName , <STR_LIT> ) ; SDValue BS = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue RetVal ; for ( unsigned i = <NUM_LIT> ; i < NumRet ; ++ i ) { RetVal = Outs [ i ] . Val ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , RetVal , ES , BS , DAG . getConstant ( i , <STR_LIT> ) ) ; }

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> AsmPrinter :: runOnMachineFunction ( MF ) ;


<s> assert ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ; unsigned AmountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Def = MRI -> getUniqueVRegDef ( AmountReg ) ;

while ( Def && Def -> isCopy ( ) && Def -> getOperand ( <NUM_LIT> ) . isReg ( ) ) Def = MRI -> getUniqueVRegDef ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , CODE_LABEL_NUMBER ( lab ) ) ; for ( idx = <NUM_LIT> ; idx < vlen ; idx ++ ) { ASM_OUTPUT_ADDR_VEC_ELT ( file , CODE_LABEL_NUMBER ( XEXP ( XVECEXP ( body , <NUM_LIT> , idx ) , <NUM_LIT> ) ) ) ; }


<s> void <ISA_LIT>InstrInfo :: insertOutlinerEpilogue ( MachineBasicBlock & MBB , MachineFunction & MF , bool IsTailCall ) const { if ( IsTailCall ) return ;

MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; SDValue Elt1 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; DCI . AddToWorklist ( Elt0 . getNode ( ) ) ; DCI . AddToWorklist ( Elt1 . getNode ( ) ) ; return DAG . getNode ( Opc , SL , EltVT , Elt0 , Elt1 , Vec -> getFlags ( ) ) ; } } } if ( ! DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; unsigned VecSize = VecVT . getSizeInBits ( ) ; unsigned EltSize = EltVT . getSizeInBits ( ) ; auto * Idx = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( isa < MemSDNode > ( Vec ) && EltSize <= <NUM_LIT> && EltVT . isByteSized ( ) && VecSize > <NUM_LIT> && VecSize % <NUM_LIT> == <NUM_LIT> && Idx ) { EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VecVT ) ; unsigned BitIndex = Idx -> getZExtValue ( ) * EltSize ; unsigned EltIdx = BitIndex / <NUM_LIT> ;

unsigned LeftoverBitIdx = BitIndex % <NUM_LIT> ;


<s> if ( N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) != <NUM_LIT> ) return false ; return isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) ;


<s> MCDisassembler ( STI ) , fMode ( mode ) {


<s> unsigned DstReg = LEA . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AddrDispOp = <NUM_LIT> + <STR_LIT> ;

return SrcReg == DstReg && LEA . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && LEA . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && LEA . getOperand ( AddrDispOp ) . isImm ( ) && ( LEA . getOperand ( AddrDispOp ) . getImm ( ) == <NUM_LIT> || LEA . getOperand ( AddrDispOp ) . getImm ( ) == - <NUM_LIT> ) ;


<s> static SDValue ParseBFI ( SDNode * N , APInt & ToMask , APInt & FromMask ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; SDValue From = N -> getOperand ( <NUM_LIT> ) ; ToMask = ~ cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; FromMask = APInt :: getLowBitsSet ( ToMask . getBitWidth ( ) , ToMask . countPopulation ( ) ) ; if ( From -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( From -> getOperand ( <NUM_LIT> ) ) ) { APInt Shift = cast < ConstantSDNode > ( From -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; assert ( Shift . getLimitedValue ( ) < <NUM_LIT> && <STR_LIT> ) ; FromMask <<= Shift . getLimitedValue ( <NUM_LIT> ) ; From = From -> getOperand ( <NUM_LIT> ) ; } return From ;


<s> for ( i = <NUM_LIT> ; i < nunits / <NUM_LIT> ; i ++ ) RTVEC_ELT ( v , i ) = GEN_INT ( base + i ) ; t1 = gen_rtx_PARALLEL ( mode , v ) ;


<s> SDValue Res ; if ( CP -> isMachineConstantPoolEntry ( ) ) { Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; } else { Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) ) ;


<s> unsigned CondReg ; bool Inverted ; std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & MBB = * CMovI . getParent ( ) ; insertTest ( MBB , CMovI . getIterator ( ) , CMovI . getDebugLoc ( ) , CondReg ) ;

auto & CMovRC = * MRI -> getRegClass ( CMovI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> if ( ! TARGET_LINK_STACK ) return ; get_ppc476_thunk_name ( name ) ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; TREE_STATIC ( decl ) = <NUM_LIT> ; if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; ASM_WEAKEN_DECL ( asm_out_file , decl , name , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else {


<s> if ( VT == <STR_LIT> ) return false ; } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) {

if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ;


<s> OperandMatchResultTy parseFP64 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegister ( Operands , RegFP , <STR_LIT> , FP64Reg ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerHvxBuildVector ( SDValue Op , SelectionDAG & DAG ) const { const SDLoc & dl ( Op ) ; MVT VecTy = ty ( Op ) ; unsigned Size = Op . getNumOperands ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; if ( VecTy . getSizeInBits ( ) == <NUM_LIT> * Subtarget . getVectorLength ( ) ) { ArrayRef < SDValue > A ( Ops ) ; MVT SingleTy = typeSplit ( VecTy ) . first ; SDValue V0 = buildHvxVectorReg ( A . take_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; SDValue V1 = buildHvxVectorReg ( A . drop_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , V0 , V1 ) ; } if ( VecTy . getVectorElementType ( ) == <STR_LIT> ) return buildHvxVectorPred ( Ops , dl , VecTy , DAG ) ; if ( VecTy . getVectorElementType ( ) == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ; for ( unsigned i = <NUM_LIT> ; i != Size ; i ++ ) NewOps . push_back ( DAG . getBitcast ( <STR_LIT> , Ops [ i ] ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , tyVector ( VecTy , <STR_LIT> ) , NewOps ) ; return DAG . getBitcast ( tyVector ( VecTy , <STR_LIT> ) , T0 ) ; }

return buildHvxVectorReg ( Ops , dl , VecTy , DAG ) ;


<s> DEBUG ( DBGSCHED ( dbgs ( ) , MI ) << <STR_LIT> << <ISA_LIT>InstrInfo :: getUnitStrings ( ) [ unit ] << <STR_LIT> ) ; udx = getUnitIndex ( side , unit ) ; break ; } } if ( desc . TSFlags & <STR_LIT> ) { xuse = ( side == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { std :: set < const TargetRegisterClass * > RCs = getOperandRCs ( MI ) ; if ( RCs . size ( ) > <NUM_LIT> ) xuse = ( side == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; } DEBUG ( DBGSCHED ( dbgs ( ) , MI ) << <STR_LIT> << ( xuse ? getExtraStr ( xuse ) : <STR_LIT> ) << <STR_LIT> ) ; } else { udx = getUnitIndex ( SU ) ; xuse = getExtraUse ( SU ) ; } assert ( udx >= <NUM_LIT> && <STR_LIT> ) ;


<s> Shape ( ShapeKind KindInit ) : Id ( - <NUM_LIT> ) , Next ( nullptr ) , Kind ( KindInit ) {


<s> return ( N -> getOpcode ( ) == <STR_LIT> && isIntS16Immediate ( cast < ConstantSDNode > ( N ) , Imm ) ) ;


<s> if ( LRSavedOnEntry ) { MachineLocation CSDst ( MachineLocation :: VirtualFP , <NUM_LIT> ) ; MachineLocation CSSrc ( <STR_LIT> ) ; Moves . push_back ( MachineMove ( FrameLabel , CSDst , CSSrc ) ) ; } } if ( saveLR ) { int LRSpillOffset = MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , LRSpillOffset + FrameSize * <NUM_LIT> , dl ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveLRLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveLRLabel ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , LRSpillOffset ) ; MachineLocation CSSrc ( <STR_LIT> ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( SaveLRLabel , CSDst , CSSrc ) ) ; } } } if ( FP ) { int FPSpillOffset = MFI -> getObjectOffset ( XFI -> getFPSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , FPSpillOffset + FrameSize * <NUM_LIT> , dl ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveR10Label = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveR10Label ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , FPSpillOffset ) ; MachineLocation CSSrc ( <STR_LIT> ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( SaveR10Label , CSDst , CSSrc ) ) ; } unsigned FramePtr = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addImm ( <NUM_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * FrameLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; MachineLocation SPDst ( FramePtr ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; } } if ( emitFrameMoves ) { std :: vector < MachineMove > & Moves = MMI -> getFrameMoves ( ) ;

std :: vector < std :: pair < MCSymbol * , CalleeSavedInfo > > & SpillLabels = XFI -> getSpillLabels ( ) ;


<s> if ( isFrameLoadOpcode ( MI -> getOpcode ( ) ) ) if ( isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ) ;

Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> + getReg ( ) - <STR_LIT> ) ) ;


<s> int words = ( bytes + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; int arg_num = * cum ; int ret ; arg_num = ROUND_ADVANCE_CUM ( arg_num , mode , type ) ;


<s> void addu32MustExtOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N ) ;


<s> if ( ! mips_get_unaligned_mem ( & src , width , bitpos , & left , & right ) ) return false ; temp = gen_reg_rtx ( GET_MODE ( dest ) ) ; if ( GET_MODE ( dest ) == DImode ) { emit_insn ( gen_mov_ldl ( temp , src , left ) ) ; emit_insn ( gen_mov_ldr ( dest , copy_rtx ( src ) , right , temp ) ) ; } else { emit_insn ( gen_mov_lwl ( temp , src , left ) ) ; emit_insn ( gen_mov_lwr ( dest , copy_rtx ( src ) , right , temp ) ) ; } return true ;


<s> } if ( UC . cantUnwind ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitCantUnwindLocNotes ( ) ; return false ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitHandlerDataLocNotes ( ) ; return false ; } if ( HasExistingPersonality ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ; UC . emitPersonalityLocNotes ( ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerShifts ( SDValue Op , SelectionDAG & DAG ) const { unsigned Opc = Op . getOpcode ( ) ; SDNode * N = Op . getNode ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( N ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return Op ; uint64_t ShiftAmount = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Victim = N -> getOperand ( <NUM_LIT> ) ; if ( ShiftAmount >= <NUM_LIT> ) { assert ( VT == <STR_LIT> && <STR_LIT> ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Victim = DAG . getZeroExtendInReg ( Victim , dl , <STR_LIT> ) ; Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; break ; case <STR_LIT> : case <STR_LIT> : Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; Victim = ( Opc == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , dl , VT , Victim , DAG . getValueType ( <STR_LIT> ) ) : DAG . getZeroExtendInReg ( Victim , dl , <STR_LIT> ) ; break ; } ShiftAmount -= <NUM_LIT> ; } if ( Opc == <STR_LIT> && ShiftAmount ) { Victim = DAG . getNode ( <STR_LIT> , dl , VT , Victim ) ; ShiftAmount -= <NUM_LIT> ; } while ( ShiftAmount -- ) Victim = DAG . getNode ( ( Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) , dl , VT , Victim ) ;


<s> const InstrItineraryData & II = * Subtarget . getInstrItineraryData ( ) ; const InstrStage & IS = * II . beginStage ( MI . getDesc ( ) . getSchedClass ( ) ) ; return IS . getUnits ( ) ;


return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = <NUM_LIT> ) const override {


<s> EDInstInfo * <ISA_LIT>GenericDisassembler :: getEDInfo ( ) const {


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> if ( Val == <NUM_LIT> ) { assert ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) && <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code16 ) ; } else { assert ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) && <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code32 ) ; } return false ;


<s> ImmutablePass * llvm :: create<ISA_LIT>ExternalAAWrapperPass ( ) {

return new <ISA_LIT>ExternalAAWrapper ( ) ;


<s> return false ; } bool Gatscat = true ; for ( User * U : I -> users ( ) ) { if ( ! isa < Instruction > ( U ) ) return false ; if ( isa < GetElementPtrInst > ( U ) || isGatherScatter ( dyn_cast < IntrinsicInst > ( U ) ) ) { return Gatscat ; } else {

unsigned OpCode = cast < Instruction > ( U ) -> getOpcode ( ) ;


<s> SectionData * sectData = IRBuilder :: CreateSectionData ( * m_pEXIDX ) ; const size_t alignExIdx = <NUM_LIT> ; m_pEXIDX -> setAlign ( alignExIdx ) ; AlignFragment * frag = new AlignFragment ( alignExIdx , <NUM_LIT> , <NUM_LIT> , alignExIdx - <NUM_LIT> ) ; frag -> setOffset ( <NUM_LIT> ) ; frag -> setParent ( sectData ) ; sectData -> getFragmentList ( ) . push_back ( frag ) ; m_pEXIDX -> setSize ( frag -> size ( ) ) ; } uint64_t offset = m_pEXIDX -> size ( ) ; SectionData :: FragmentListType & src = pSection . getSectionData ( ) -> getFragmentList ( ) ; SectionData :: FragmentListType & dst = m_pEXIDX -> getSectionData ( ) -> getFragmentList ( ) ; SectionData :: FragmentListType :: iterator frag = src . begin ( ) ; SectionData :: FragmentListType :: iterator fragEnd = src . end ( ) ; while ( frag != fragEnd ) {

if ( frag -> getKind ( ) != Fragment :: Region ) {


<s> StackOffset Offset ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FrameReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = { MFI . getObjectOffset ( FrameIndex ) + AFI -> getTaggedBasePointerOffset ( ) , <STR_LIT> } ; } else if ( Tagged ) { StackOffset SPOffset = { MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) , <STR_LIT> } ; if ( MFI . hasVarSizedObjects ( ) || is<ISA_LIT>FrameOffsetLegal ( MI , SPOffset , nullptr , nullptr , nullptr ) != ( <ISA_LIT>FrameOffsetCanUpdate | <ISA_LIT>FrameOffsetIsLegal ) ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; return ; } FrameReg = <STR_LIT> ; Offset = { MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) , <STR_LIT> } ; } else { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; } if ( rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ;

assert ( ( ! RS || ! RS -> isScavengingFrameIndex ( FrameIndex ) ) && <STR_LIT> ) ;


<s> if ( ! ( ac . aligned && code == SET && MEM_P ( val ) ) ) val = s390_expand_mask_and_shift ( val , mode , ac . shift ) ; if ( code == PLUS || code == MINUS ) emit_move_insn ( orig , val ) ; else if ( code == MULT || code == AND ) val = expand_simple_binop ( SImode , XOR , val , ac . modemaski , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; cmp = force_reg ( SImode , ac . memsi ) ; emit_label ( csloop ) ; emit_move_insn ( new_rtx , cmp ) ; switch ( code ) { case PLUS : case MINUS : val = expand_simple_binop ( SImode , code , new_rtx , orig , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; val = expand_simple_binop ( SImode , AND , val , ac . modemask , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; case SET : if ( ac . aligned && MEM_P ( val ) ) store_bit_field ( new_rtx , GET_MODE_BITSIZE ( mode ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , SImode , val , false , false ) ;


<s> Mutations . push_back ( make_unique < <ISA_LIT>Subtarget :: <ISA_LIT>DAGMutation > ( ) ) ;


<s> if ( GET_MODE ( op ) == V4SFmode || GET_MODE ( op ) == V2SFmode ) tmp = gen_lowpart ( SImode , tmp ) ;


<s> return TM . Options . EnableFastISel && ( ( isTargetMachO ( ) && ! isThumb1Only ( ) ) || ( isTargetLinux ( ) && ! isThumb ( ) ) || ( isTargetNaCl ( ) && ! isThumb ( ) ) ) ;


<s> InChain = FprIndex . getValue ( <NUM_LIT> ) ; SDValue RegSaveAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OverflowAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OverflowArea = DAG . getLoad ( <STR_LIT> , dl , InChain , OverflowAreaPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; InChain = OverflowArea . getValue ( <NUM_LIT> ) ; SDValue RegSaveArea = DAG . getLoad ( <STR_LIT> , dl , InChain , RegSaveAreaPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; InChain = RegSaveArea . getValue ( <NUM_LIT> ) ; SDValue CC = DAG . getSetCC ( dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue RegConstant = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( VT . isInteger ( ) ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue OurReg = DAG . getNode ( <STR_LIT> , dl , PtrVT , RegSaveArea , RegConstant ) ; if ( VT . isFloatingPoint ( ) ) OurReg = DAG . getNode ( <STR_LIT> , dl , PtrVT , OurReg , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;

SDValue IndexPlus1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VT . isInteger ( ) ? GprIndex : FprIndex , DAG . getConstant ( VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> if ( ! IsTailPredicationLegal ( ) ) return IsDo ? <STR_LIT> : <STR_LIT> ;

return VCTPOpcodeToLSTP ( VCTPs . back ( ) -> getOpcode ( ) , IsDo ) ;


<s> BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent ( ) ; return BB ;


<s> void setCFGStackified ( bool Value = true ) { CFGStackified = Value ;


<s> break ; default : break ; } if ( GET_CODE ( x ) == MINUS && ( XEXP ( x , <NUM_LIT> ) == got_register_rtx || sparc_pic_register_p ( XEXP ( x , <NUM_LIT> ) ) ) ) { rtx y = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , <NUM_LIT> ) ; if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_MOVE_PIC_LABEL ) { x = XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) ; } }


<s> Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> if ( CC == <STR_LIT> ) { std :: string Msg = <STR_LIT> ; if ( ! Suggestion . empty ( ) ) Msg += <STR_LIT> + Suggestion + <STR_LIT> ; return TokError ( Msg ) ; } Lex ( ) ; if ( invertCondCode ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return TokError ( <STR_LIT> ) ; CC = <STR_LIT> ( <STR_LIT> ( CC ) ) ; }

Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , S , getLoc ( ) , getContext ( ) ) ) ;


<s> int num_insns_constant_wide ( HOST_WIDE_INT value ) { if ( ( ( unsigned HOST_WIDE_INT ) value + <NUM_LIT> ) < <NUM_LIT> ) return <NUM_LIT> ; else if ( ( value & <NUM_LIT> ) == <NUM_LIT> && ( value >> <NUM_LIT> == - <NUM_LIT> || value >> <NUM_LIT> == <NUM_LIT> ) ) return <NUM_LIT> ;


<s> return pru_regno_ok_for_base_p ( regno , strict_p ) ;


<s> high = riscv_force_temporary ( temp , high ) ; reg = riscv_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ;

assert ( VA . isRegLoc ( ) && <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( ! FI ) { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; int Offset = getBackchainOffset ( MF ) - <STR_LIT> ; FI = MFFrame . CreateFixedObject ( <NUM_LIT> , Offset , false ) ; ZFI -> setFramePointerSaveIndex ( FI ) ; } return FI ;


<s> int num_saves = XVECLEN ( parallel_op , <NUM_LIT> ) ; if ( TARGET_ARM ) return <NUM_LIT> ; if ( TARGET_THUMB1 ) return <NUM_LIT> ; regno = REGNO ( first_op ) ; hi_reg = ( REGNO_REG_CLASS ( regno ) == HI_REGS ) && ( regno != LR_REGNUM ) ;

for ( i = <NUM_LIT> ; i < num_saves && ! hi_reg ; i ++ ) {


<s> int _U_Qfge ( long double a , long double b ) {

return ( _U_Qfcmp ( a , b , <NUM_LIT> ) != <NUM_LIT> ) ;


<s> d . perm [ <NUM_LIT> ] = which + <NUM_LIT> ; emit_insn ( gen_fpack ( d . op1 , operands [ <NUM_LIT> ] , CONST0_RTX ( SFmode ) ) ) ; ok = ia64_expand_vec_perm_const_1 ( & d ) ;


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; return RegBits ;


<s> } StringRef ModifierName = Parser . getTok ( ) . getString ( ) ; ModifierKind = <ISA_LIT>MCExpr :: getKindByName ( ModifierName ) ; if ( ModifierKind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Parser . Lex ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . getString ( ) == GENERATE_STUBS && Parser . getTok ( ) . getKind ( ) == AsmToken :: Identifier ) { std :: string GSModName = ModifierName . str ( ) + <STR_LIT> + GENERATE_STUBS ; ModifierKind = <ISA_LIT>MCExpr :: getKindByName ( GSModName ) ; if ( ModifierKind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) Parser . Lex ( ) ; } } else { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } if ( tokens [ <NUM_LIT> ] . getKind ( ) == AsmToken :: Minus || tokens [ <NUM_LIT> ] . getKind ( ) == AsmToken :: Plus ) { Parser . Lex ( ) ; assert ( Parser . getTok ( ) . getKind ( ) == AsmToken :: LParen ) ; Parser . Lex ( ) ; } MCExpr const * InnerExpression ; if ( getParser ( ) . parseExpression ( InnerExpression ) ) return true ; if ( tokens [ <NUM_LIT> ] . getKind ( ) == AsmToken :: Minus || tokens [ <NUM_LIT> ] . getKind ( ) == AsmToken :: Plus ) { assert ( Parser . getTok ( ) . getKind ( ) == AsmToken :: RParen ) ; Parser . Lex ( ) ; } assert ( Parser . getTok ( ) . getKind ( ) == AsmToken :: RParen ) ; Parser . Lex ( ) ; MCExpr const * Expression = <ISA_LIT>MCExpr :: create ( ModifierKind , InnerExpression , isNegated , getContext ( ) ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( Expression , S , E ) ) ;


<s> Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC , DL ) ) ; SDValue Glue = emitCmp ( DAG , DL , C ) ;

return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( C . CCValid , DL , <STR_LIT> ) , DAG . getConstant ( C . CCMask , DL , <STR_LIT> ) , Dest , Glue ) ;


<s> static rtx mips_unspec_offset_high ( rtx temp , rtx base , rtx addr , enum mips_symbol_type symbol_type ) { if ( mips_split_p [ symbol_type ] ) { addr = gen_rtx_HIGH ( Pmode , mips_unspec_address ( addr , symbol_type ) ) ; addr = mips_force_temporary ( temp , addr ) ; base = mips_force_temporary ( temp , gen_rtx_PLUS ( Pmode , addr , base ) ) ; } return base ;


<s> snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_section_head_template ( section_name , symbol_name , <NUM_LIT> , true ) ; fprintf ( asm_out_file , <STR_LIT> , ( strlen ( nds32_isr_vectors [ <NUM_LIT> ] . nmi_name ) == <NUM_LIT> ) ? <STR_LIT> : nds32_isr_vectors [ <NUM_LIT> ] . nmi_name ) ; nds32_emit_section_tail_template ( symbol_name ) ; snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_section_head_template ( section_name , symbol_name , <NUM_LIT> , true ) ; fprintf ( asm_out_file , <STR_LIT> , ( strlen ( nds32_isr_vectors [ <NUM_LIT> ] . warm_name ) == <NUM_LIT> ) ? <STR_LIT> : nds32_isr_vectors [ <NUM_LIT> ] . warm_name ) ;


<s> for ( unsigned VR : NewRegs ) SpillRCs . insert ( MRI . getRegClass ( VR ) ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; const TargetRegisterClass & IntRC = <STR_LIT> ; if ( SpillRCs . count ( & IntRC ) ) { for ( int i = <NUM_LIT> ; i < NumberScavengerSlots ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( IntRC . getSize ( ) , IntRC . getAlignment ( ) ) ; RS -> addScavengingFrameIndex ( NewFI ) ; } } for ( auto * RC : SpillRCs ) { if ( RC == & IntRC ) continue ; int NewFI = MFI . CreateSpillStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) ) ; RS -> addScavengingFrameIndex ( NewFI ) ; } } TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;