<s> bool IsDecreasing = ( ( Opc == Instruction :: Sub ) && ! NegImm ) || ( ( Opc == Instruction :: Add ) && NegImm ) ; if ( ! IsDecreasing ) return false ; auto * CI = cast < ICmpInst > ( * I -> user_begin ( ) ) ; if ( CI -> isSigned ( ) || CI -> isEquality ( ) ) return false ; ConstantInt * ICmpConst = nullptr ; if ( auto * Const = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ) ICmpConst = Const ; else if ( auto * Const = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ) ICmpConst = Const ; else return false ; APInt Total = ICmpConst -> getValue ( ) . getBitWidth ( ) < <NUM_LIT> ? ICmpConst -> getValue ( ) . zext ( <NUM_LIT> ) : ICmpConst -> getValue ( ) ; Total += OverflowConst -> getValue ( ) . getBitWidth ( ) < <NUM_LIT> ? OverflowConst -> getValue ( ) . abs ( ) . zext ( <NUM_LIT> ) : OverflowConst -> getValue ( ) . abs ( ) ; APInt Max = APInt :: getAllOnesValue ( <ISA_LIT>CodeGenPrepare :: TypeSize ) ; if ( Total . getBitWidth ( ) > Max . getBitWidth ( ) ) { if ( Total . ugt ( Max . zext ( Total . getBitWidth ( ) ) ) ) return false ; } else if ( Max . getBitWidth ( ) > Total . getBitWidth ( ) ) {

if ( Total . zext ( Max . getBitWidth ( ) ) . ugt ( Max ) ) return false ;


<s> return __builtin_mve_vmvnq_sv4si ( __a ) ;


<s> AVAIL ( hard_float , TARGET_HARD_FLOAT ) { CODE_FOR_riscv_ ## INSN , <STR_LIT> NAME , \ BUILTIN_TYPE , FUNCTION_TYPE , riscv_builtin_avail_ ## AVAIL } RISCV_BUILTIN ( INSN , # INSN , RISCV_BUILTIN_DIRECT , FUNCTION_TYPE , AVAIL ) RISCV_BUILTIN ( INSN , # INSN , RISCV_BUILTIN_DIRECT_NO_TARGET , \ FUNCTION_TYPE , AVAIL ) RISCV_ATYPE_ ## A RISCV_ATYPE_ ## A , RISCV_ATYPE_ ## B static const struct riscv_builtin_description riscv_builtins [ ] = { DIRECT_BUILTIN ( frflags , RISCV_USI_FTYPE , hard_float ) , DIRECT_NO_TARGET_BUILTIN ( fsflags , RISCV_VOID_FTYPE_USI , hard_float ) } ; static GTY ( ( ) ) tree riscv_builtin_decls [ ARRAY_SIZE ( riscv_builtins ) ] ; static GTY ( ( ) ) int riscv_builtin_decl_index [ NUM_INSN_CODES ] ; riscv_builtin_decls [ riscv_builtin_decl_index [ ( CODE ) ] ] static tree riscv_build_function_type ( enum riscv_function_type type ) { static tree types [ ( int ) RISCV_MAX_FTYPE_MAX ] ; if ( types [ ( int ) type ] == NULL_TREE ) switch ( type ) { case RISCV_FTYPE_NAME ## NUM ARGS : \ types [ ( int ) type ] \ = build_function_type_list ( RISCV_FTYPE_ATYPES ## NUM ARGS , \ NULL_TREE ) ; \ break ; default : gcc_unreachable ( ) ; } return types [ ( int ) type ] ; } void riscv_init_builtins ( void ) { for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) { const struct riscv_builtin_description * d = & riscv_builtins [ i ] ; if ( d -> avail ( ) ) { tree type = riscv_build_function_type ( d -> prototype ) ; riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode ] = i ; } } } tree riscv_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ; return riscv_builtin_decls [ code ] ; } static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned argno ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( op , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } static rtx riscv_expand_builtin_insn ( enum insn_code icode , unsigned int n_ops , struct expand_operand * ops , bool has_target_p ) { if ( ! maybe_expand_insn ( icode , n_ops , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; }

return has_target_p ? ops [ <NUM_LIT> ] . value : const0_rtx ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ;

TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ;


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const {


<s> case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( ! Info -> isEntryFunction ( ) ) { const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } } }


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue CvtHi = DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , Hi ) ;

SDValue CvtLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ;


<s> int sh_dynamicalize_shift_p ( rtx count ) {

return shift_insns [ INTVAL ( count ) ] > <NUM_LIT> + SH_DYNAMIC_SHIFT_COST ;


<s> -- I ; } if ( ! isUnpredicatedTerminator ( I ) ) return false ; MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; }


<s> for ( MachineRegisterInfo :: def_instr_iterator It = MRI -> def_instr_begin ( Reg ) , E = MRI -> def_instr_end ( ) ; It != E ; ++ It ) { RemoveMI ( & ( * It ) ) ; } } continue ; } RegSeqInfo R<ISA_LIT> ( * MRI , & MI ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! areAllUsesSwizzeable ( Reg ) ) continue ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; } ) ; RegSeqInfo CandidateR<ISA_LIT> ; std :: vector < std :: pair < unsigned , unsigned >> RemapChan ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ;

if ( tryMergeUsingCommonSlot ( R<ISA_LIT> , CandidateR<ISA_LIT> , RemapChan ) ) {


<s> <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return ! invertPredicate ? <STR_LIT> :


<s> wide = expand_simple_binop ( SImode , LSHIFTRT , wide , shift , wide , <NUM_LIT> , OPTAB_LIB_WIDEN ) ;

emit_move_insn ( narrow , gen_lowpart ( GET_MODE ( narrow ) , wide ) ) ;


<s> StringRef getPassName ( ) const override { return AARCH64_CONDBR_TUNING_NAME ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti , uint64_t Alignment ) : TargetFrameLowering ( StackDirection :: StackGrowsDown , Align ( Alignment ) , <NUM_LIT> , Align ( Alignment ) ) , STI ( sti ) {


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCantUnwind ( SMLoc L ) { CantUnwindLoc = L ; if ( ! FnStartLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( HandlerDataLoc . isValid ( ) ) { Error ( L , <STR_LIT> ) ; Error ( HandlerDataLoc , <STR_LIT> ) ; return true ; } if ( PersonalityLoc . isValid ( ) ) { Error ( L , <STR_LIT> ) ;


<s> if ( CC == <STR_LIT> ) return <STR_LIT> ; return <STR_LIT> ( CC , true ) ;


<s> auto Largest = result . back ( ) . first ; result . push_back ( { Largest + <NUM_LIT> , LegalizerInfo :: Unsupported } ) ; return result ;


<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) {

Base = Addr . getOperand ( <NUM_LIT> ) ;


<s> if ( MaybeCFI == End || MaybeCFI -> getOpcode ( ) != TargetOpcode :: CFI_INSTRUCTION || ! ( MI . getFlag ( MachineInstr :: FrameSetup ) || MI . getFlag ( MachineInstr :: FrameDestroy ) ) || getLdStBaseOp ( MI ) . getReg ( ) != <STR_LIT> ) return End ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; unsigned CFIIndex = MaybeCFI -> getOperand ( <NUM_LIT> ) . getCFIIndex ( ) ; const MCCFIInstruction & CFI = MF . getFrameInstructions ( ) [ CFIIndex ] ; switch ( CFI . getOperation ( ) ) { case MCCFIInstruction :: OpDefCfa : case MCCFIInstruction :: OpDefCfaOffset : return MaybeCFI ; default : return End ; }


<s> int i ; if ( ! TARGET_V9 ) return <NUM_LIT> ; for ( i = XVECLEN ( pat , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { rtx expr = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( GET_CODE ( expr ) != SET ) return <NUM_LIT> ; if ( GET_CODE ( SET_DEST ( expr ) ) != REG ) return <NUM_LIT> ; regno = REGNO ( SET_DEST ( expr ) ) ; if ( regno >= <NUM_LIT> && regno < <NUM_LIT> ) return <NUM_LIT> ; } return ! epilogue_renumber ( & pat , <NUM_LIT> ) ; } if ( GET_CODE ( pat ) != SET ) return <NUM_LIT> ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG ) return <NUM_LIT> ; regno = REGNO ( SET_DEST ( pat ) ) ; if ( regno >= <NUM_LIT> && regno < <NUM_LIT> ) return <NUM_LIT> ; if ( ! SPARC_INT_REG_P ( regno ) ) return TARGET_V9 && ! epilogue_renumber ( & pat , <NUM_LIT> ) ;

return eligible_for_restore_insn ( trial , true ) ;


return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( addIntraChainConstraint ( G , Rd , Ra ) ) addInterChainConstraint ( G , Rd , Ra ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned Rd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; addInterChainConstraint ( G , Rd , Rd ) ; break ; } default : break ; }


<s> return ; } const bool HasVSrc = N -> getNumOperands ( ) == <NUM_LIT> ; assert ( HasVSrc || N -> getNumOperands ( ) == <NUM_LIT> ) ; SDLoc SL ( N ) ; SDValue BaseOffset = N -> getOperand ( HasVSrc ? <NUM_LIT> : <NUM_LIT> ) ; int ImmOffset = <NUM_LIT> ; MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; MachineMemOperand * MMO = M -> getMemOperand ( ) ; if ( ConstantSDNode * ConstOffset = dyn_cast < ConstantSDNode > ( BaseOffset ) ) { glueCopyToM0 ( N , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; ImmOffset = ConstOffset -> getZExtValue ( ) ; } else { if ( CurDAG -> isBaseWithConstantOffset ( BaseOffset ) ) { ImmOffset = BaseOffset . getConstantOperandVal ( <NUM_LIT> ) ; BaseOffset = BaseOffset . getOperand ( <NUM_LIT> ) ; } SDNode * SGPROffset = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , BaseOffset ) ; SDNode * M0Base = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , SDValue ( SGPROffset , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ;

glueCopyToM0 ( N , SDValue ( M0Base , <NUM_LIT> ) ) ;


<s> static bool r10k_simplified_address_p ( rtx x ) {

if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) x = XEXP ( x , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSPONENTRY ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; EVT VT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( Op ) ; int FI = MFI . CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , false ) ; return DAG . getFrameIndex ( FI , VT ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getRegister ( IsN64 ? <STR_LIT> : <STR_LIT> , Ty ) , DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( Ty ) , GPRel ) ) ;


<s> static bool isGPR ( const TargetRegisterClass * RC ) { return <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ;


<s> if ( ! FI ) return None ; auto & MF = DAG . getMachineFunction ( ) ; return <ISA_LIT>FrameLowering :: getLocalForStackObject ( MF , FI -> getIndex ( ) ) ;


<s> TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; }

TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_32Target , create<ISA_LIT>_32AsmBackend ) ;


<s> if ( ! Load || ! <STR_LIT> ( Load ) ) return nullptr ; SDValue Ptr = Load -> getBasePtr ( ) ; if ( Ptr -> getOpcode ( ) == <STR_LIT> || Ptr -> getOpcode ( ) == <STR_LIT> ) Ptr = Ptr -> getOperand ( <NUM_LIT> ) ; auto * CNode = dyn_cast < ConstantPoolSDNode > ( Ptr ) ; if ( ! CNode || CNode -> isMachineConstantPoolEntry ( ) || CNode -> getOffset ( ) != <NUM_LIT> ) return nullptr ;


<s> <ISA_LIT>HazardRecognizer440 ( const InstrItineraryData * ItinData , const ScheduleDAG * DAG_ ) : ScoreboardHazardRecognizer ( ItinData , DAG_ ) , DAG ( DAG_ ) {


<s> if ( <STR_LIT> ( Imm ) ) { Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return Success ; }


<s> return ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isMemOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; uint64_t Offset = MO . getOffset ( ) ; if ( ! Modifier || strcmp ( Modifier , <STR_LIT> ) ) O << ( isMemOp ? '&' : '#' ) ; if ( Offset ) O << '(' << Offset << '+' ; O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; if ( Offset ) O << ')' ; return ; } case MachineOperand :: MO_ExternalSymbol : { bool isMemOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ;


<s> void setShouldRestoreSPFromFP ( bool s ) {


<s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) {


<s> return create<ISA_LIT>ELFObjectWriter ( reinterpret_cast < <ISA_LIT>Subtarget const * > ( & STI ) -> getFamily ( ) ) ;


<s> ELF<ISA_LIT>_64AsmBackend ( const Target & T , uint8_t OSABI , const MCSubtargetInfo & STI ) : ELF<ISA_LIT>AsmBackend ( T , OSABI , STI ) {


<s> __result = ( ( __vector unsigned long long ) vec_vbpermq ( ( __vector unsigned char ) __A , ( __vector unsigned char ) __perm_mask ) ) ; return __result [ <NUM_LIT> ] ; return __result [ <NUM_LIT> ] ;


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT> ) ;


<s> <ISA_LIT>LibcallNames [ Call ] = Name ;


<s> bool isMaybeDirectBranchDest ( ) const { assert ( Kind == Memory && <STR_LIT> ) ;


<s> inline unsigned even128 ( bool Is32bit ) { return Is32bit ? subreg_32bit : subreg_high ;


<s> DebugLoc dl = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ;


<s> MCInstLowering . Lower ( MI , TmpInst ) ;

OutStreamer . EmitInstruction ( TmpInst ) ;


<s> SDValue C = DAG . getConstant ( InvalidOnQNaN , dl , <STR_LIT> ) ;

if ( ! isFloatingPointZero ( RHS ) ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , C ) ;


<s> O << ( int64_t ) MI -> getOperand ( OpNo ) . getImm ( ) ; } else { printOp ( MI -> getOperand ( OpNo ) ) ;


<s> if ( ! isa < ConstantSDNode > ( K1 ) || ! isa < ConstantSDNode > ( K2 ) ) return false ; int64_t Val1 = cast < ConstantSDNode > ( K1 ) -> getSExtValue ( ) ; int64_t Val2 = cast < ConstantSDNode > ( K2 ) -> getSExtValue ( ) ; int64_t PosVal = std :: max ( Val1 , Val2 ) ; int64_t NegVal = std :: min ( Val1 , Val2 ) ; if ( ! ( ( Val1 > Val2 && isLTorLE ( CC1 ) ) || ( Val1 < Val2 && isLTorLE ( CC2 ) ) ) || ! isPowerOf2_64 ( PosVal + <NUM_LIT> ) ) return false ; if ( Val1 == ~ Val2 ) Usat = false ; else if ( NegVal == <NUM_LIT> ) Usat = true ; else return false ; V = V2Tmp ;


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = <NUM_LIT> ) const override {


<s> bool arm_small_register_classes_for_mode_p ( machine_mode mode ATTRIBUTE_UNUSED ) {


<s> return ( bit_count ( ARM_FSET_CPU1 ( * set ) ) + bit_count ( ARM_FSET_CPU2 ( * set ) ) ) ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , FMA ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , <ISA_LIT>ALUInst ( false ) , FP64 ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , Gen ( <ISA_LIT> ) , TLInfo ( TM , initializeSubtargetDependencies ( TT , GPU , FS ) ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) {


<s> } } if ( slot && get_attr_in_delay_slot ( prev ) == IN_DELAY_SLOT_YES ) slot = <NUM_LIT> ; credit -= get_attr_length ( prev ) ; } if ( prev && GET_CODE ( prev ) == JUMP_INSN && JUMP_LABEL ( prev ) ) { rtx x ; if ( jump_to_next || next_real_insn ( JUMP_LABEL ( prev ) ) == next || JUMP_LABEL ( prev ) == next_nonnote_insn ( next ) || ( x = ( NEXT_INSN ( NEXT_INSN ( PREV_INSN ( prev ) ) ) ) , ( INSN_P ( x ) && ( INSN_CODE ( x ) == CODE_FOR_block_branch_redirect || INSN_CODE ( x ) == CODE_FOR_indirect_jump_scratch || INSN_CODE ( x ) == CODE_FOR_stuff_delay_slot ) ) ) ) { rtx pat = PATTERN ( prev ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ;

if ( credit - slot >= ( GET_CODE ( SET_SRC ( pat ) ) == PC ? <NUM_LIT> : <NUM_LIT> ) ) return <NUM_LIT> ;


<s> ConstantSDNode * ConstVal = cast < ConstantSDNode > ( N ) ; uint64_t ImmVal = ConstVal -> getZExtValue ( ) ; uint64_t SupportedMask = <NUM_LIT> ; if ( ( ImmVal & SupportedMask ) != ImmVal ) { SelectCode ( N ) ; } uint64_t LoMask = <NUM_LIT> ; uint64_t HiMask = <NUM_LIT> ; uint64_t ImmLo = ( ImmVal & LoMask ) ; uint64_t ImmHi = ( ImmVal & HiMask ) ; return ;


<s> void setCalleeSavedFrameSize ( unsigned bytes ) { CalleeSavedFrameSize = bytes ;


<s> MIB . addDef ( PhysReg , RegState :: Implicit ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & <STR_LIT> ;


<s> int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TII . adjustStackPtr ( <STR_LIT> , Amount , MBB , I ) ; } MBB . erase ( I ) ;


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>LegalizerInfo * LI = static_cast < const <ISA_LIT>LegalizerInfo * > ( ST . getLegalizerInfo ( ) ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = IsOptNone ? nullptr : & getAnalysis < MachineDominatorTree > ( ) ; <ISA_LIT>PostLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , LI , KB , MDT ) ; Combiner C ( PCInfo , TPC ) ;

return C . combineMachineInstrs ( MF , nullptr ) ;


<s> MachineFunction & MF = * B . getParent ( ) ; auto * HRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; HII . loadRegFromStackSlot ( B , It , TmpR1 , FI , RC , HRI ) ; expandLoadVec ( B , std :: prev ( It ) , MRI , HII , NewRegs ) ; BuildMI ( B , It , DL , HII . get ( <STR_LIT> ) , DstR ) . addReg ( TmpR1 , RegState :: Kill ) . addReg ( TmpR0 , RegState :: Kill ) ; NewRegs . push_back ( TmpR0 ) ; NewRegs . push_back ( TmpR1 ) ; B . erase ( It ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> SMLoc getStartLoc ( ) const override {


<s> if ( cfun -> machine -> naked_p ) return false ; if ( cfun -> machine -> interrupt_handler_p ) return false ;


<s> return getNumExtraSGPRs ( Features , VCCUsed , FlatScrUsed , Features [ <STR_LIT> ] ) ;


<s> return static_cast < signed char > ( Letter - '0' ) ; } if ( Letter >= 'a' && Letter <= 'f' ) { return static_cast < signed char > ( Letter - 'a' + <NUM_LIT> ) ; } return - <NUM_LIT> ;


<s> const Value * V1 = Load -> getMemOperand ( ) -> getValue ( ) ; const Value * V2 = Store -> getMemOperand ( ) -> getValue ( ) ; if ( ! V1 || ! V2 ) return false ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; int64_t End1 = Load -> getSrcValueOffset ( ) + Size ; int64_t End2 = Store -> getSrcValueOffset ( ) + Size ; if ( V1 == V2 && End1 == End2 ) return false ;

return ! AA -> alias ( AliasAnalysis :: Location ( V1 , End1 , Load -> getTBAAInfo ( ) ) , AliasAnalysis :: Location ( V2 , End2 , Store -> getTBAAInfo ( ) ) ) ;


<s> initializeR600EmitClauseMarkersPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( term ) == PLUS && CONST_INT_P ( XEXP ( term , <NUM_LIT> ) ) ) term = XEXP ( term , <NUM_LIT> ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , <NUM_LIT> ) != UNSPEC_GOTPCREL && XINT ( term , <NUM_LIT> ) != UNSPEC_PCREL ) ) return x ;

return XVECEXP ( term , <NUM_LIT> , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerFrameIndex ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ;

const <ISA_LIT>FrameLowering * TFL = getSubtarget ( ) -> getFrameLowering ( ) ;


<s> gcc_assert ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl ) == FUNCTION_DECL ) ; if ( TREE_CODE ( TREE_TYPE ( decl ) ) == METHOD_TYPE && DECL_ARTIFICIAL ( decl ) && ! DECL_THUNK_P ( decl ) ) return false ; if ( TREE_CODE ( decl ) == FUNCTION_DECL && DECL_DECLARED_INLINE_P ( decl ) ) { if ( DECL_REALLY_EXTERN ( decl ) || ! flag_keep_inline_dllexport ) return false ; }


<s> auto & HRI = static_cast < const <ISA_LIT>RegisterInfo & > ( * MRI . getTargetRegisterInfo ( ) ) ; unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( DstRC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( DstRC , <STR_LIT> ) ; assert ( ( Sub1 == SubLo && Sub2 == SubHi ) || ( Sub1 == SubHi && Sub2 == SubLo ) ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T ) : MCAsmBackend ( ) {


<s> for ( int ix = <NUM_LIT> ; ix < len ; ix ++ ) { if ( brackets [ ix ] . back == pseudo ) {

if ( dump_file ) fprintf ( dump_file , <STR_LIT> , pseudo . first ? pseudo . first -> index : <NUM_LIT> , pseudo . second ) ;


<s> assert ( isBundle ( MCI ) ) ; auto Flags = MCI . getOperand ( <NUM_LIT> ) . getImm ( ) ;

return ( Flags & memReorderDisabledMask ) != <NUM_LIT> ;


<s> return true ; } unsigned Opc = Offset >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , <STR_LIT> ) . addUse ( BaseReg ) . addImm ( abs ( Offset ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addUse ( <STR_LIT> ) . addUse ( CtxReg ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addUse ( <STR_LIT> ) . addUse ( BaseReg ) . addImm ( Offset / <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MBBI -> eraseFromParent ( ) ; return true ;


<s> bool tilegx_can_use_return_insn_p ( void ) { return ( reload_completed && ! cfun -> static_chain_decl && ! compute_total_frame_size ( ) && tilegx_current_function_is_leaf ( ) && ! crtl -> profile && ! df_regs_ever_live_p ( TILEGX_LINK_REGNUM ) ) ;


<s> if ( OutStreamer -> hasRawTextSupport ( ) ) OutStreamer -> EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ;

OutStreamer -> EmitLabel ( CurrentFnSym ) ;


<s> if ( EltTy != <STR_LIT> && EltTy != <STR_LIT> && EltTy != <STR_LIT> ) return SDValue ( ) ; } if ( ! ( VectorOp == IfTrue -> getOperand ( <NUM_LIT> ) && VectorOp == IfFalse -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( SetCC -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) || ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) || ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) || ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) || ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) || ( Op == <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> && CC != <STR_LIT> ) ) return SDValue ( ) ;

if ( ! isa < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) || cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ;


<s> push2 ( unsigned i , unsigned j ) : doubleChange ( true , true , i , j ) {


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> void addu32_0ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> MCRegister DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Src2Reg == DstReg ) return true ; const MCRegisterInfo * TRI = getContext ( ) . getRegisterInfo ( ) ; if ( TRI -> getRegClass ( Desc . OpInfo [ <NUM_LIT> ] . RegClass ) . getSizeInBits ( ) <= <NUM_LIT> ) return true ; if ( isRegIntersect ( Src2Reg , DstReg , TRI ) ) { Error ( getRegLoc ( mc2PseudoReg ( Src2Reg ) , Operands ) , <STR_LIT> ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = VMRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> switch ( NewOpc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm ( <NUM_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> unsigned getGlobalRetAddr ( ) const { return GlobalRetAddr ;


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;

Reg = getReg ( Decoder , <STR_LIT> , Reg ) ;


<s> if ( ! NewVT . isVector ( ) || NewVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( V . getOpcode ( ) == <STR_LIT> || ( Idx == <NUM_LIT> && V . getOpcode ( ) == <STR_LIT> ) ) {


<s> SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRight1Lo , RegisterSizeMinus1Shamt ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue HiTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue HiFalse = DAG . getNode ( <STR_LIT> , DL , VT , Lo , ShamtMinusRegisterSize ) ; SDValue CC = DAG . getSetCC ( DL , <STR_LIT> , ShamtMinusRegisterSize , Zero , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , CC , LoTrue , Zero ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , CC , HiTrue , HiFalse ) ;

return DAG . getMergeValues ( { Lo , Hi } , DL ) ;


return ( __m512d ) __builtin_ia32_loadupd512_mask ( ( const __v8df * ) __P , ( __v8df ) _mm512_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> return false ; case 'y' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { Register Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; for ( MCSuperRegIterator SR ( Reg , TRI ) ; SR . isValid ( ) ; ++ SR ) { if ( ! <STR_LIT> . contains ( * SR ) ) continue ; bool Lane0 = TRI -> getSubReg ( * SR , <STR_LIT> ) == Reg ; O << <ISA_LIT>InstPrinter :: getRegisterName ( * SR ) << ( Lane0 ? <STR_LIT> : <STR_LIT> ) ; return false ; } } return true ; case 'B' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << ~ ( MI -> getOperand ( OpNum ) . getImm ( ) ) ; return false ; case 'L' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; O << ( MI -> getOperand ( OpNum ) . getImm ( ) & <NUM_LIT> ) ; return false ; case 'M' : { if ( ! MI -> getOperand ( OpNum ) . isReg ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; Register RegBegin = MO . getReg ( ) ; O << <STR_LIT> ; if ( <STR_LIT> . contains ( RegBegin ) ) { const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; Register Reg0 = TRI -> getSubReg ( RegBegin , <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg0 ) << <STR_LIT> ; RegBegin = TRI -> getSubReg ( RegBegin , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( RegBegin ) ; unsigned RegOps = OpNum + <NUM_LIT> ; while ( MI -> getOperand ( RegOps ) . isReg ( ) ) { O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( RegOps ) . getReg ( ) ) ; RegOps ++ ; }


<s> if ( ! CE ) return true ; uint64_t Value = CE -> getValue ( ) ;

return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) ) ;


<s> static unsigned encodeVFPRn ( const MachineInstr & MI , unsigned OpIdx ) { unsigned RegN = MI . getOperand ( OpIdx ) . getReg ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; unsigned FrameReg ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ;


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; }


<s> __builtin_aarch64_simd_xi __o ; int64x2x4_t temp ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st4di ( ( __builtin_aarch64_simd_di * ) __a , __o ) ;


<s> auto & OldSrc = MI -> getOperand ( <NUM_LIT> ) ; unsigned NewDestReg ; if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; unsigned NewSrcReg = get<ISA_LIT>SubSuperRegister ( OldSrc . getReg ( ) , <NUM_LIT> ) ; auto * TRI = & TII -> getRegisterInfo ( ) ; if ( TRI -> getSubRegIndex ( NewSrcReg , OldSrc . getReg ( ) ) != TRI -> getSubRegIndex ( NewDestReg , OldDest . getReg ( ) ) ) return nullptr ;

MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , NewDestReg ) . addReg ( NewSrcReg , RegState :: Undef ) . addReg ( OldSrc . getReg ( ) , RegState :: Implicit ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << <ISA_LIT>MCInstrInfo :: getName ( MCII , MI ) << <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } Binary |= Parse ; if ( MI . getOpcode ( ) >= <STR_LIT> && MI . getOpcode ( ) <= <STR_LIT> ) { assert ( Parse == <STR_LIT> && <STR_LIT> ) ; unsigned dupIClass = MI . getOpcode ( ) - <STR_LIT> ; Binary = ( ( dupIClass & <NUM_LIT> ) << ( <NUM_LIT> - <NUM_LIT> ) ) | ( ( dupIClass & <NUM_LIT> ) << <NUM_LIT> ) ; const MCInst * subInst0 = MI . getOperand ( <NUM_LIT> ) . getInst ( ) ; const MCInst * subInst1 = MI . getOperand ( <NUM_LIT> ) . getInst ( ) ; unsigned subInstSlot0Bits = getBinaryCodeForInstr ( * subInst0 , Fixups , STI ) ;

unsigned subInstSlot1Bits = getBinaryCodeForInstr ( * subInst1 , Fixups , STI ) ;


<s> bool LinearizedRegion :: contains ( MachineBasicBlock * MBB ) { return MBBs . contains ( MBB ) ;


<s> for ( MachineInstr & MI : llvm :: reverse ( llvm :: make_range ( MBB . begin ( ) , TestPos ) ) ) { <STR_LIT> Cond = <STR_LIT> ( MI ) ; if ( Cond != <STR_LIT> && ! MI . mayStore ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && TRI -> isVirtualRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { assert ( MI . getOperand ( <NUM_LIT> ) . isDef ( ) && <STR_LIT> ) ; CondRegs [ Cond ] = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI . findRegisterDefOperand ( <STR_LIT> ) ) break ;


<s> void ApplyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const {


<s> if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) return false ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Align ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ; if ( CM == CodeModel :: Large ) { unsigned AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ;


<s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const {

if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfh ( ) ) return <STR_LIT> ;


<s> SubRegStores . push_back ( NewChain ) ; SDValue NewPtr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( SRF_REGISTER_LENGTH_IN_BYTES , DL , Ptr . getValueType ( ) ) ) ; SubReg = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; Node = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , EltTy , Value , SubReg ) ; SDValue V2 ( Node , <NUM_LIT> ) ; NewChain = DAG . getStore ( Chain , DL , V2 , NewPtr , PtrInfo . getWithOffset ( SRF_REGISTER_LENGTH_IN_BYTES ) , Alignment , StoreNode -> getMemOperand ( ) -> getFlags ( ) ) ; SubRegStores . push_back ( NewChain ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SubRegStores ) ; return Chain ;


<s> case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , false , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , false , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , false , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , true , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; } return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG ) ;


<s> MachineInstr * Inst = NULL ; if ( stackFrameSize ) { assert ( isUInt < <NUM_LIT> > ( stackFrameSize ) && <STR_LIT> ) ; DebugLoc DL = ( MI != MBB . end ( ) ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; const TargetInstrInfo & TII = * STC . getInstrInfo ( ) ;

Inst = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opcode ) ) ) . addImm ( stackFrameSize ) ;


<s> const uint32_t * getRegMaskBits ( RegisterId R ) const {

return RegMasks . get ( TargetRegisterInfo :: stackSlot2Index ( R ) ) ;


<s> Negate = ! Negate ; return SearchLoopIntrinsic ( N . getOperand ( <NUM_LIT> ) , CC , Imm , Negate ) ; } case <STR_LIT> : { auto * Const = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! Const ) return SDValue ( ) ; if ( Const -> isNullValue ( ) ) Imm = <NUM_LIT> ; else if ( Const -> isOne ( ) ) Imm = <NUM_LIT> ; else return SDValue ( ) ; CC = cast < CondCodeSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return SearchLoopIntrinsic ( N -> getOperand ( <NUM_LIT> ) , CC , Imm , Negate ) ; } case <STR_LIT> : { unsigned IntOp = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntOp != <STR_LIT> && IntOp != <STR_LIT> ) return SDValue ( ) ; return N ; }


<s> if ( DefRelocModel == Reloc :: Default ) setRelocationModel ( Reloc :: Static ) ; PM . add ( create<ISA_LIT>ObjectCodeEmitterPass ( * this , OCE ) ) ; return false ;


<s> assert ( OpIdx >= <NUM_LIT> && <STR_LIT> ) ; MIB . addImm ( ( MI . getOperand ( OpIdx ) . getImm ( ) >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> if ( ! SI . isUnordered ( ) ) return false ;


<s> if ( ! TARGET_HPUX && TYPE_MODE ( type ) == TFmode ) return <STR_LIT> ; if ( TYPE_MODE ( type ) == XFmode ) return TARGET_HPUX ? <STR_LIT> : <STR_LIT> ; if ( TYPE_MODE ( type ) == RFmode ) return <STR_LIT> ; return NULL ;


<s> bool isImm ( ) const { return ! OpToFold ;


<s> set_optab_libfunc ( smod_optab , SImode , <STR_LIT> ) ; set_optab_libfunc ( smod_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( umod_optab , SImode , <STR_LIT> ) ; set_optab_libfunc ( umod_optab , DImode , <STR_LIT> ) ;


<s> Impl ( PredicateDefinition * pub ) : Pub ( * pub ) , type ( DefinitionType :: Simple ) {


<s> bool Micro<ISA_LIT>SizeReduce :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; if ( ! Subtarget -> inMicro<ISA_LIT>Mode ( ) || ! Subtarget -> has<ISA_LIT>32r2 ( ) ) return false ; <ISA_LIT>II = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) {


<s> if ( mode == VOIDmode ) return <NUM_LIT> ;

return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ;


<s> void GCNPassConfig :: addFastRegAlloc ( FunctionPass * RegAllocPass ) { insertPass ( & TwoAddressInstructionPassID , & <ISA_LIT>LowerControlFlowID , false ) ; TargetPassConfig :: addFastRegAlloc ( RegAllocPass ) ;


<s> MCInst LabelInst ; LabelInst . setOpcode ( <STR_LIT> ) ;

LabelInst . addOperand ( MCOperand :: createReg ( MAI -> getOrCreateMBBRegister ( MBB ) ) ) ;


<s> unsigned Size = getSizeInBits ( MI . getOperand ( I ) . getReg ( ) , MRI , * TRI ) ; OpdsMapping [ I ] = <STR_LIT> ( <STR_LIT> , Size ) ; }

return getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( OpdsMapping ) , MI . getNumOperands ( ) ) ;


<s> unsigned int align = INTVAL ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) ; unsigned long n_bytes = INTVAL ( XEXP ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) ; unsigned int n_insns = <NUM_LIT> ; if ( align > ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) align = ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; n_insns = <NUM_LIT> ; if ( n_bytes % ( <NUM_LIT> * align ) != <NUM_LIT> ) { if ( ( n_bytes % ( <NUM_LIT> * align ) ) >= align ) n_insns += <NUM_LIT> ; if ( ( n_bytes % align ) != <NUM_LIT> ) n_insns += <NUM_LIT> ;


<s> } else { OutStreamer . EmitSymbolValue ( DyldStubBindingHelper , <NUM_LIT> ) ; } } OutStreamer . AddBlankLine ( ) ; return ; } const MCSection * StubSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; const MCExpr * LazyPtrExpr = MCSymbolRefExpr :: Create ( LazyPtr , OutContext ) ; OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; OutStreamer . EmitLabel ( Stub ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; const MCExpr * LazyPtrHa16 = <ISA_LIT>MCExpr :: CreateHa ( LazyPtrExpr , isDarwin , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( LazyPtrHa16 ) ) ; const MCExpr * LazyPtrLo16 = <ISA_LIT>MCExpr :: CreateLo ( LazyPtrExpr , isDarwin , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( LazyPtrLo16 ) . addExpr ( LazyPtrLo16 ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ;

OutStreamer . SwitchSection ( LSPSection ) ;


<s> unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register DestLo = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; Register DestHi = TRI -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ;

BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ;


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> static rtx sparc_builtin_setjmp_frame_value ( void ) {


<s> <ISA_LIT>TargetStreamer :: emitDirectiveCpRestore ( StoreInsts , Offset ) ;

if ( ! Pic || ( getABI ( ) . IsN32 ( ) || getABI ( ) . IsN64 ( ) ) ) return ;


<s> for ( size_t I = <NUM_LIT> , E = SortedIntervals . size ( ) ; I < E ; ++ I ) { LiveInterval * LI = SortedIntervals [ I ] ; unsigned Old = LI -> reg ; size_t Color = I ; const TargetRegisterClass * RC = MRI -> getRegClass ( Old ) ; if ( ! MRI -> isLiveIn ( Old ) ) for ( unsigned C : UsedColors . set_bits ( ) ) { if ( MRI -> getRegClass ( SortedIntervals [ C ] -> reg ) != RC ) continue ; for ( LiveInterval * OtherLI : Assignments [ C ] ) if ( ! OtherLI -> empty ( ) && OtherLI -> overlaps ( * LI ) ) goto continue_outer ; Color = C ; break ; continue_outer : ; } unsigned New = SortedIntervals [ Color ] -> reg ; SlotMapping [ I ] = New ; Changed |= Old != New ; UsedColors . set ( Color ) ; Assignments [ Color ] . push_back ( LI ) ; if ( Old != New && MFI . isFrameBaseVirtual ( ) && MFI . getFrameBaseVreg ( ) == Old ) MFI . setFrameBaseVreg ( New ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Register :: virtReg2Index ( LI -> reg ) << <STR_LIT> << Register :: virtReg2Index ( New ) << <STR_LIT> ) ;


<s> continue ; } if ( Op . isImm ( ) && Op . getImmTy ( ) == <ISA_LIT>Operand :: ImmTyNone ) { Op . addImmOperands ( Inst , <NUM_LIT> ) ; continue ; } HasLdsModifier = Op . isLDS ( ) ; if ( Op . isToken ( ) ) { continue ; } assert ( Op . isImm ( ) ) ; OptionalIdx [ Op . getImmTy ( ) ] = i ; } if ( IsLdsOpcode && ! HasLdsModifier ) { int NoLdsOpcode = <STR_LIT> ( Inst . getOpcode ( ) ) ; if ( NoLdsOpcode != - <NUM_LIT> ) { Inst . setOpcode ( NoLdsOpcode ) ; IsLdsOpcode = false ; } } if ( IsAtomicReturn ) { MCInst :: iterator I = Inst . begin ( ) ; Inst . insert ( I , * I ) ; } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOffset ) ; if ( ! IsAtomic ) {

addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyGLC ) ;


<s> ErrorLoc = IdLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IdLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IdLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } default : break ; }


<s> DebugLoc dl = Op . getNode ( ) -> getDebugLoc ( ) ; SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ;

if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) && Vec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) {


<s> <ISA_LIT>GenSubtargetInfo STI ( TM . getTargetTriple ( ) , TM . getTargetCPU ( ) , TM . getTargetFeatureString ( ) ) ; if ( STI . hasFeature ( <STR_LIT> ) ) substitutePass ( & PostRASchedulerID , & PostMachineSchedulerID ) ; }


<s> return SPAdj ; } if ( MI . isCall ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; auto I = ++ MachineBasicBlock :: const_iterator ( MI ) ; for ( auto E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) || I -> isCall ( ) ) break ; } if ( I -> getOpcode ( ) != getCallFrameDestroyOpcode ( ) ) return <NUM_LIT> ; return - ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> Count -= HEXAGON_INSTR_SIZE ; uint32_t ParseBits = ( Count % ( MaxPacketSize * HEXAGON_INSTR_SIZE ) ) ? ParseIn : ParseEnd ; <STR_LIT> :: write < uint32_t > ( OS , Nopcode | ParseBits , Endian ) ; }


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( TM . getRelocationModel ( ) != Reloc :: Static ) { if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) { GlobalValue * GV = MO . getGlobal ( ) ; if ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) { FnStubInfo & FnInfo = FnStubs [ Mang -> getMangledName ( GV ) ] ; FnInfo . Init ( GV , Mang ) ; O << FnInfo . Stub ; return ; } } if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) {

FnStubInfo & FnInfo = FnStubs [ Mang -> makeNameProper ( MO . getSymbolName ( ) ) ] ;


<s> MachineInstr * MI = & * MII ; LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; unsigned Opcode = MI -> getOpcode ( ) ; DenseMap < unsigned , unsigned > :: iterator OPI = ReduceOpcodeMap . find ( Opcode ) ; if ( OPI != ReduceOpcodeMap . end ( ) ) { const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) { if ( ReduceSpecial ( MBB , MI , Entry , LiveCPSR ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ;


<s> CCState :: AnalyzeCallResult ( Ins , Fn ) ;


<s> LoReg = getSubReg ( Reg , <STR_LIT> ) ;


<s> } } if ( parseOperand ( Operands , Name ) != MatchOperand_Success ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) || getLexer ( ) . is ( AsmToken :: Plus ) ) { if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; } Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) != MatchOperand_Success ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ;


<s> SDValue LoadInp = LoadOperand ( DAG , DL , <STR_LIT> , CondNode ) ; SDValue CondCode = DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , CondCode , LoadInp , BBlock } ; SDValue BrConstcc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ; TransferNodeFlagsWithGlue ( CondNode , BrConstcc ) ;


<s> } SDValue NewOp = lowerVectorIntExtend ( Op , DAG ) ; if ( NewOp . getNode ( ) ) return NewOp ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG , dl ) ; if ( NewOp . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , NewOp ) ; } else if ( ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasSSE2 ( ) ) ) ) { if ( <STR_LIT> ( V2 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG , dl ) ; if ( NewOp . getNode ( ) ) { EVT NewVT = NewOp . getValueType ( ) ; if ( isCommutedMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT , true , false ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } else if ( <STR_LIT> ( V1 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG , dl ) ; if ( NewOp . getNode ( ) ) { EVT NewVT = NewOp . getValueType ( ) ; if ( isMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; }


<s> if ( imask & ( <NUM_LIT> << REG_RA ) ) { emit_frame_store ( REG_RA , sa_reg , sa_bias , reg_offset ) ; imask &= ~ ( <NUM_LIT> << REG_RA ) ; reg_offset += <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( imask & ( <NUM_LIT> << i ) ) { emit_frame_store ( i , sa_reg , sa_bias , reg_offset ) ; reg_offset += <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( fmask & ( <NUM_LIT> << i ) ) { emit_frame_store ( i + <NUM_LIT> , sa_reg , sa_bias , reg_offset ) ; reg_offset += <NUM_LIT> ; } if ( TARGET_ABI_OPEN_VMS ) { if ( alpha_procedure_type == PT_REGISTER ) { rtx_insn * insn = emit_move_insn ( gen_rtx_REG ( DImode , vms_save_fp_regno ) , hard_frame_pointer_rtx ) ; add_reg_note ( insn , REG_CFA_REGISTER , NULL ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV ) emit_insn ( gen_force_movdi ( gen_rtx_REG ( DImode , vms_base_regno ) , gen_rtx_REG ( DImode , REG_PV ) ) ) ; if ( alpha_procedure_type != PT_NULL && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM ) FRP ( emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( crtl -> outgoing_args_size != <NUM_LIT> ) { rtx_insn * seq = emit_move_insn ( stack_pointer_rtx , plus_constant ( Pmode , hard_frame_pointer_rtx , - ( ALPHA_ROUND ( crtl -> outgoing_args_size ) ) ) ) ; RTX_FRAME_RELATED_P ( seq ) = ! frame_pointer_needed ; } } else { if ( frame_pointer_needed ) { if ( TARGET_CAN_FAULT_IN_PROLOGUE ) FRP ( emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; else FRP ( emit_insn ( gen_init_fp ( hard_frame_pointer_rtx , stack_pointer_rtx , sa_reg ) ) ) ; }


<s> unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ;


<s> else for ( i = <NUM_LIT> ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( mode , rdest + count - i - <NUM_LIT> ) , gen_rtx_REG ( mode , rsrc + count - i - <NUM_LIT> ) ) ;


<s> assert ( LoVT . getVectorNumElements ( ) + ( HiVT . isVector ( ) ? HiVT . getVectorNumElements ( ) : <NUM_LIT> ) <= N . getValueType ( ) . getVectorNumElements ( ) && <STR_LIT> ) ; auto IdxTy = getVectorIdxTy ( DAG . getDataLayout ( ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , LoVT , N , DAG . getConstant ( <NUM_LIT> , DL , IdxTy ) ) ; SDValue Hi = DAG . getNode ( HiVT . isVector ( ) ? <STR_LIT> : <STR_LIT> , DL , HiVT , N , DAG . getConstant ( LoVT . getVectorNumElements ( ) , DL , IdxTy ) ) ;


<s> llvm :: StringRef fde_region = createFDERegionForPLT ( ) ; EhFrame :: CIE * cie = new EhFrame :: GeneratedCIE ( cie_region ) ; EhFrame :: FDE * fde = new EhFrame :: GeneratedFDE ( fde_region , * cie ) ; uint8_t aug_data = ( uint8_t ) ( llvm :: dwarf :: DW_EH_PE_pcrel | llvm :: dwarf :: DW_EH_PE_sdata4 ) ; cie -> setFDEEncode ( aug_data ) ; cie -> setAugmentationData ( std :: string ( <NUM_LIT> , aug_data ) ) ; EhFrame :: cie_iterator i = eh_frame -> cie_begin ( ) ; for ( EhFrame :: cie_iterator e = eh_frame -> cie_end ( ) ; i != e ; ++ i ) { EhFrame :: CIE & exist_cie = * * i ; if ( exist_cie == * cie ) { SectionData :: iterator cur_iter ( exist_cie ) ; frag_list . insertAfter ( cur_iter , fde ) ;


<s> op [ arity ] = expand_expr ( arg , NULL_RTX , insn_op -> mode , EXPAND_NORMAL ) ; if ( CONST_INT_P ( op [ arity ] ) && SCALAR_INT_MODE_P ( insn_op -> mode ) && GET_MODE ( op [ arity ] ) != insn_op -> mode ) op [ arity ] = GEN_INT ( trunc_int_for_mode ( INTVAL ( op [ arity ] ) , insn_op -> mode ) ) ; if ( POINTER_TYPE_P ( TREE_TYPE ( arg ) ) && insn_op -> predicate != address_operand ) op [ arity ] = gen_rtx_MEM ( insn_op -> mode , op [ arity ] ) ; if ( op_flags == O_ELEM ) { gcc_assert ( last_vec_mode != VOIDmode ) ; op [ arity ] = simplify_expand_binop ( SImode , code_to_optab ( AND ) , op [ arity ] , GEN_INT ( GET_MODE_NUNITS ( last_vec_mode ) - <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; } if ( VECTOR_MODE_P ( insn_op -> mode ) ) last_vec_mode = insn_op -> mode ; if ( insn_op -> predicate ( op [ arity ] , insn_op -> mode ) ) {


<s> <ISA_LIT>AddressingMode ( AddrForm form , DispRange dr ) : Form ( form ) , DR ( dr ) , Disp ( <NUM_LIT> ) , IncludesDynAlloc ( false ) {


<s> return ArgDescriptor ( Reg , Mask , true , true ) ;


<s> case <STR_LIT> : { assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } } return false ;


<s> if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( siReg ) ) return <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( diReg ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( siReg ) ) return <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( diReg ) ;


<s> } adjustLiveRegs ( LiveMask , MI ) ; if ( ! LiveMask ) return ; if ( SecondFPRegOp == ~ <NUM_LIT> ) { assert ( StackTop == <NUM_LIT> && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; StackTop = <NUM_LIT> ; return ; } if ( StackTop == <NUM_LIT> ) { assert ( FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; unsigned NewReg = ScratchFPReg ; duplicateToTop ( FirstFPRegOp , NewReg , MI ) ; FirstFPRegOp = NewReg ; } assert ( StackTop == <NUM_LIT> && <STR_LIT> ) ; if ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp ) { assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ; moveToTop ( FirstFPRegOp , MI ) ; } assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ;

assert ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp && <STR_LIT> ) ;


<s> <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( osABI ) {


<s> if ( riscv_symbol_insns ( sym_type ) == <NUM_LIT> ) return false ;

if ( ! riscv_split_symbol_type ( sym_type ) ) return false ;


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) {

return new <ISA_LIT>DAGToDAGISel ( TM ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerTLSDescCall ( SDValue SymAddr , SDValue DescAddr , SDLoc DL , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( ) ; SDValue Func , Chain ; Func = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getEntryNode ( ) , DescAddr ) ; SDValue Glue ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , DescAddr , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const <ISA_LIT>RegisterInfo * A64RI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = A64RI -> getTLSDescCallPreservedMask ( ) ; std :: vector < SDValue > Ops ;


<s> fprintf ( stderr , <STR_LIT> , prefix , flags ) ; dump_target_flag_bits ( flags ) ;


<s> for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { rp [ i ] = i ; age [ i ] = <NUM_LIT> ;


<s> ~ <ISA_LIT>AsmBackend ( ) override {


<s> const <ISA_LIT>BaseRegisterInfo * getRegisterInfo ( ) const override {

return & InstrInfo -> getRegisterInfo ( ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmTargetStreamer ) ;

TargetRegistry :: RegisterObjectTargetStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>ObjectTargetStreamer ) ;


<s> return new <ISA_LIT>MCCodeEmitter ( MRI , true ) ;


<s> unsigned Reg = ScopedHT . lookup ( Entry ) . second ; assert ( Reg ) ; return Reg ;


<s> bool <ISA_LIT>InstructionSelector :: validOpRegPair ( MachineRegisterInfo & MRI , unsigned LHSReg , unsigned RHSReg , unsigned ExpectedSize , unsigned ExpectedRegBankID ) const { return MRI . getType ( LHSReg ) == MRI . getType ( RHSReg ) && validReg ( MRI , LHSReg , ExpectedSize , ExpectedRegBankID ) && validReg ( MRI , RHSReg , ExpectedSize , ExpectedRegBankID ) ;


<s> static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse ( MachineRegisterInfo * MRI ) {

for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) if ( MRI -> isPhysRegUsed ( reg ) ) return false ;


<s> const <ISA_LIT>RegisterInfo & TRI = TII -> getRegisterInfo ( ) ; if ( ! Op -> isMachineOpcode ( ) ) { switch ( Op -> getOpcode ( ) ) { case <STR_LIT> : { MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; unsigned Reg = cast < RegisterSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { return MRI . getRegClass ( Reg ) ; } return TRI . getPhysRegClass ( Reg ) ; } default : return nullptr ; } } const MCInstrDesc & Desc = TII -> get ( Op -> getMachineOpcode ( ) ) ; int OpClassID = Desc . OpInfo [ Op . getResNo ( ) ] . RegClass ; if ( OpClassID != - <NUM_LIT> ) { return TRI . getRegClass ( OpClassID ) ; } switch ( Op . getMachineOpcode ( ) ) { case AMDGPU :: COPY_TO_REGCLASS : OpClassID = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( OpClassID == AMDGPU :: VSrc_32RegClassID || OpClassID == AMDGPU :: VSrc_64RegClassID ) { return getRegClassForNode ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; } return TRI . getRegClass ( OpClassID ) ; case AMDGPU :: EXTRACT_SUBREG : {

int SubIdx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> rtx fusion_wrap_memory_address ( rtx old_mem ) { rtx old_addr = XEXP ( old_mem , <NUM_LIT> ) ; rtvec v = gen_rtvec ( <NUM_LIT> , old_addr ) ; rtx new_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_FUSION_ADDIS ) ;

return replace_equiv_address_nv ( old_mem , new_addr , false ) ;


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> } } if ( ! SN -> isTruncatingStore ( ) && ! SN -> isVolatile ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && ( Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> ) ) { SDValue BSwapOp = Op1 . getOperand ( <NUM_LIT> ) ; if ( BSwapOp . getValueType ( ) == <STR_LIT> ) BSwapOp = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSwapOp ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , BSwapOp , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( Op1 . getValueType ( ) ) } ;

return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> ) , Ops , MemVT , SN -> getMemOperand ( ) ) ;


<s> virtual raw_ostream & GetCommentOS ( ) {

if ( ! IsVerboseAsm ) return nulls ( ) ;


<s> static SDValue emitMemMemImm ( SelectionDAG & DAG , const SDLoc & DL , unsigned Op , SDValue Chain , SDValue Dst , SDValue Src , uint64_t Size ) {

return DAG . getNode ( Op , DL , getMemMemVTs ( Op , DAG ) , Chain , Dst , Src , DAG . getConstant ( Size - <NUM_LIT> , DL , Src . getValueType ( ) ) ) ;


<s> AsmStr = std :: string ( AsmPieces [ <NUM_LIT> ] ) ; AsmPieces . clear ( ) ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { IntegerType * Ty = dyn_cast < IntegerType > ( CI -> getType ( ) ) ; if ( Ty && Ty -> getBitWidth ( ) == <NUM_LIT> ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } break ; }


<s> static int m32c_pushm_popm ( Push_Pop_Type ppt ) { int reg_mask = <NUM_LIT> ; int byte_count = <NUM_LIT> , bytes ; int i ; rtx dwarf_set [ PUSHM_N ] ; int n_dwarfs = <NUM_LIT> ; int nosave_mask = <NUM_LIT> ; if ( crtl -> return_rtx && GET_CODE ( crtl -> return_rtx ) == PARALLEL && ! ( crtl -> calls_eh_return || cfun -> machine -> is_interrupt ) ) { rtx exp = XVECEXP ( crtl -> return_rtx , <NUM_LIT> , <NUM_LIT> ) ; rtx rv = XEXP ( exp , <NUM_LIT> ) ; int rv_bytes = GET_MODE_SIZE ( GET_MODE ( rv ) ) ; if ( rv_bytes > <NUM_LIT> ) nosave_mask |= <NUM_LIT> ; else nosave_mask |= <NUM_LIT> ; if ( rv_bytes > <NUM_LIT> ) nosave_mask |= <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < ( int ) PUSHM_N ; i ++ ) { if ( ! need_to_save ( pushm_info [ i ] . reg1 ) ) continue ; if ( pushm_info [ i ] . bit & nosave_mask ) continue ; reg_mask |= pushm_info [ i ] . bit ; bytes = TARGET_A16 ? pushm_info [ i ] . a16_bytes : pushm_info [ i ] . a24_bytes ; if ( ppt == PP_pushm ) { machine_mode mode = ( bytes == <NUM_LIT> ) ? HImode : SImode ; rtx addr ; addr = stack_pointer_rtx ; if ( byte_count != <NUM_LIT> ) addr = gen_rtx_PLUS ( GET_MODE ( addr ) , addr , GEN_INT ( byte_count ) ) ; dwarf_set [ n_dwarfs ++ ] = gen_rtx_SET ( gen_rtx_MEM ( mode , addr ) , gen_rtx_REG ( mode , pushm_info [ i ] . reg1 ) ) ; F ( dwarf_set [ n_dwarfs - <NUM_LIT> ] ) ; } byte_count += bytes ; } if ( cfun -> machine -> is_interrupt ) { cfun -> machine -> intr_pushm = reg_mask & <NUM_LIT> ; reg_mask = <NUM_LIT> ; byte_count = <NUM_LIT> ; } if ( cfun -> machine -> is_interrupt ) for ( i = MEM0_REGNO ; i <= MEM7_REGNO ; i ++ ) if ( need_to_save ( i ) ) { byte_count += <NUM_LIT> ; cfun -> machine -> intr_pushmem [ i - MEM0_REGNO ] = <NUM_LIT> ; } if ( ppt == PP_pushm && byte_count ) { rtx note = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( n_dwarfs + <NUM_LIT> ) ) ; rtx pushm ; if ( reg_mask ) { XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( GET_MODE ( stack_pointer_rtx ) , stack_pointer_rtx , GEN_INT ( - byte_count ) ) ) ; F ( XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < n_dwarfs ; i ++ ) XVECEXP ( note , <NUM_LIT> , i + <NUM_LIT> ) = dwarf_set [ i ] ;

pushm = F ( emit_insn ( gen_pushm ( GEN_INT ( reg_mask ) ) ) ) ;


<s> SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , PtrVT ) ) ; MachinePointerInfo SrcValue ( Store -> getMemOperand ( ) -> getValue ( ) ) ;

SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , Store -> getAlignment ( ) ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> return performSetCCCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performMinMaxCombine ( N , DCI ) ; case <STR_LIT> : return performFMACombine ( N , DCI ) ; case <STR_LIT> : { if ( SDValue Widended = widenLoad ( cast < LoadSDNode > ( N ) , DCI ) ) return Widended ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performZeroExtendCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : return performRcpCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

return performCvtF32UByteNCombine ( N , DCI ) ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseSWaitCntOps ( OperandVector & Operands ) { <STR_LIT> :: IsaVersion ISA = <STR_LIT> :: getIsaVersion ( getSTI ( ) . getFeatureBits ( ) ) ; int64_t Waitcnt = getWaitcntBitMask ( ISA ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_ParseFail ; case AsmToken :: Integer : if ( getParser ( ) . parseAbsoluteExpression ( Waitcnt ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Identifier : do { if ( parseCnt ( Waitcnt ) ) return MatchOperand_ParseFail ; } while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) ;


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( hasBP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> switch ( <STR_LIT> ( Imm ) ) { case <STR_LIT> :: Void : break ; case <STR_LIT> :: I32 : O << <STR_LIT> ; break ; case <STR_LIT> :: I64 : O << <STR_LIT> ; break ; case <STR_LIT> :: F32 : O << <STR_LIT> ; break ; case <STR_LIT> :: F64 : O << <STR_LIT> ; break ; case <STR_LIT> :: I8x16 : O << <STR_LIT> ; break ; case <STR_LIT> :: I16x8 : O << <STR_LIT> ; break ; case <STR_LIT> :: I32x4 : O << <STR_LIT> ; break ;

case <STR_LIT> :: F32x4 : O << <STR_LIT> ; break ;


<s> } switch ( N -> getOpcode ( ) ) { case <STR_LIT> : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; }


<s> if ( config ( ) . options ( ) . hasNow ( ) ) { if ( pFormat . hasGOT ( ) ) reserveOne ( llvm :: ELF :: DT_PLTGOT ) ;


<s> ElemDef -> removeFromParent ( ) ; StartInsertBB -> insert ( StartInsertPt , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( & * StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; StartInsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , & * StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { MachineOperand Operand = ElemDef -> getOperand ( <NUM_LIT> ) ; if ( isMovRegOpcode ( ElemDef -> getOpcode ( ) ) && RDA . getUniqueReachingMIDef ( ElemDef , Operand . getReg ( ) . asMCReg ( ) ) == RDA . getUniqueReachingMIDef ( & * StartInsertPt , Operand . getReg ( ) . asMCReg ( ) ) ) { TPNumElements = Operand ; NumElements = TPNumElements . getReg ( ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } } } } auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , MCRegister NumElements ) { if ( MBB -> empty ( ) ) return false ; if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = Preheader ; while ( MBB && MBB != StartInsertBB ) { if ( CannotProvideElements ( MBB , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MBB = * MBB -> pred_begin ( ) ; } } if ( std :: any_of ( StartInsertPt , StartInsertBB -> end ( ) , shouldInspect ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto IsValidSub = [ ] ( MachineInstr * MI , int ExpectedVecWidth ) { return - getAddSubImmediate ( * MI ) == ExpectedVecWidth ; } ; MachineBasicBlock * MBB = VCTP -> getParent ( ) ; if ( auto * Def = RDA . getUniqueReachingMIDef ( & MBB -> back ( ) , VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) . asMCReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > ElementChain ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ;

unsigned ExpectedVectorWidth = getTailPredVectorWidth ( VCTP -> getOpcode ( ) ) ;


<s> return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> return BT_Cond ; } if ( ++ I != REnd && isUnpredicatedTerminator ( & * I ) ) return BT_None ; BranchInstrs . insert ( BranchInstrs . begin ( ) , SecondLastInst ) ; if ( SecondLastOpc == UncondBrOpc ) { if ( ! AllowModify ) return BT_None ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastInst -> eraseFromParent ( ) ; BranchInstrs . pop_back ( ) ; return BT_Uncond ; } if ( LastOpc != UncondBrOpc ) return BT_None ; AnalyzeCondBr ( SecondLastInst , SecondLastOpc , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) == <STR_LIT> ) return LowerLOADi1 ( Op , DAG ) ;


<s> if ( op . isReg ( ) ) { unsigned reg = op . getReg ( ) ; int regside ; if ( TargetRegisterInfo :: isVirtualRegister ( reg ) ) { const TargetRegisterClass * RC = MRI . getRegClass ( reg ) ; if ( RC == ARegsRegisterClass ) regside = <NUM_LIT> ; else if ( RC == BRegsRegisterClass ) regside = <NUM_LIT> ; else continue ; } else { regside = <STR_LIT> . contains ( reg ) ? <NUM_LIT> : <NUM_LIT> ; } if ( result . second < <NUM_LIT> ) result . second = regside ; else if ( result . second != regside ) { DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandCondsets ( ) { return new <ISA_LIT>ExpandCondsets ( ) ;


<s> } else { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; emit_insn ( aarch64_gen_loadwb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; }


<s> static inline unsigned decodeRotate ( uint32_t insn ) {

unsigned rotate = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST ; break ; } switch ( MOTy ) { case MachineOperand :: MO_MachineBasicBlock :

Symbol = MO . getMBB ( ) -> getSymbol ( ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _addcarry_u64 ( unsigned char __CF , unsigned long long __X , unsigned long long __Y , unsigned long long * __P ) {


<s> case <STR_LIT> : case <STR_LIT> : assert ( hasReservedCallFrame ( MF ) && <STR_LIT> ) ; return MBB . erase ( MI ) ; break ; default :


<s> static SDValue PerformVZEXT_MOVLCombine ( SDNode * N , SelectionDAG & DAG ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ;

if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ;


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ;


<s> ArtCombiner . tryCombineMerges ( MI , DeadInstrs , UpdatedDefs ) ;

for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI -> eraseFromParent ( ) ;


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; Triple TT ( STI . getTargetTriple ( ) ) ;

bool is<ISA_LIT>64 = TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ;


<s> TargetRegistry :: RegisterMCDisassembler ( TheARM64leTarget , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( TheARM64beTarget , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( TheARM64leTarget , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCSymbolizer ( TheARM64beTarget , create<ISA_LIT>ExternalSymbolizer ) ;


<s> BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( BranchOp ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TBB ) ; unsigned RD1 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD1 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ; unsigned RD2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * TBB , TBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , RD2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;

BuildMI ( * Sink , Sink -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( RD1 ) . addMBB ( FBB ) . addReg ( RD2 ) . addMBB ( TBB ) ;


<s> case LABEL_REF : return flag_pic ? cris_rel_symbol : cris_offsettable_symbol ; case CONST : return cris_symbol_type_of ( XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : { enum cris_symbol_type t1 = cris_symbol_type_of ( XEXP ( x , <NUM_LIT> ) ) ; enum cris_symbol_type t2 = cris_symbol_type_of ( XEXP ( x , <NUM_LIT> ) ) ; gcc_assert ( t1 == cris_no_symbol || t2 == cris_no_symbol ) ;


<s> if ( riscv_v_ext_vector_mode_p ( mode ) ) return riscv_vector_chunks * scale ;


<s> subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , <NUM_LIT> ) == UNSPEC_TLS_LABEL || XINT ( x , <NUM_LIT> ) == UNSPEC_PIC_SYMBOL_GOTPC_GRS ) ) return true ; } return false ;


<s> case V4HImode : pattern = <STR_LIT> ; break ; case V8QImode : pattern = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } fprintf ( file , <STR_LIT> ) ; for ( i = CONST_VECTOR_NUNITS ( x ) ; i -- ; ) { rtx element ;


<s> RegisterTargetMachine < <ISA_LIT>LETargetMachine > A ( getTheThumbLETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > B ( getTheThumbBETarget ( ) ) ;

PassRegistry & Registry = * PassRegistry :: getPassRegistry ( ) ;


<s> case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; break ;

case MachineOperand :: MO_GlobalAddress :


<s> tree symbol_decl = SYMBOL_REF_DECL ( call_op ) ; if ( ! flag_plt || ( symbol_decl != NULL_TREE && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( symbol_decl ) ) ) ) return true ; return false ;


<s> unsigned FI1 = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned FI2 = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( MFI . getObjectSize ( FI1 ) != Length || MFI . getObjectSize ( FI2 ) != Length ) return false ; DestFrameIndex = FI1 ;


<s> AU . addRequiredID ( MachineLoopInfoID ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ;

AU . addPreservedID ( LiveVariablesID ) ;


<s> unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DL , TII -> get ( AMDGPU :: S_OR_SAVEEXEC_B64 ) , Dst ) . addReg ( Src ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_XOR_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) . addReg ( Dst ) ;

Skip ( MI , MI . getOperand ( <NUM_LIT> ) ) ;


<s> MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineModuleInfo > ( ) ;

AU . addPreserved < MachineModuleInfo > ( ) ;


<s> MachineBasicBlock :: iterator MI = MBB . getFirstTerminator ( ) ; DebugLoc DL ( MI -> getDebugLoc ( ) ) ; MachineInstr * DefMI ; if ( usePmov ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; DefMI = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , predReg ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) ;


<s> RHS = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( - <NUM_LIT> , dl , VT ) , RHS ) ;

return DAG . getAtomic ( <STR_LIT> , dl , AN -> getMemoryVT ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , RHS , AN -> getMemOperand ( ) ) ;


<s> SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ;

SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ;


<s> static bool isCandidateStore ( const MachineInstr * Instr ) { switch ( Instr -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , RHS1 , CC ) , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , RHS2 , CC ) ) ;


<s> virtual void EmitInstruction ( const MCInst & Inst ) { const MCInstrDesc & MID = MII . get ( Inst . getOpcode ( ) ) ; count ++ ;


<s> for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getThe<ISA_LIT>elTarget ( ) , & getThe<ISA_LIT>64Target ( ) , & getThe<ISA_LIT>64elTarget ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , createMCStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; } for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitterEB ) ; for ( Target * T : { & getThe<ISA_LIT>elTarget ( ) , & getThe<ISA_LIT>64elTarget ( ) } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackendEB32 ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>AsmBackendEL32 ) ;

TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>AsmBackendEB64 ) ;


<s> return ! arm_no_early_store_addr_dep ( producer , consumer ) ;


<s> insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ;


<s> for ( int I = <NUM_LIT> ; I != static_cast < int > ( SegLen ) ; ++ I ) { int M = SM . Mask [ S * SegLen + I ] ; if ( M < <NUM_LIT> ) continue ; unsigned G = M / SegLen ; if ( Idx == ~ <NUM_LIT> ) { Idx = G ; } else if ( Idx != G ) { Idx = ~ <NUM_LIT> ; break ;


<s> } else { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getTarget ( ) . getRegisterInfo ( ) ; const unsigned * SubSet = TRI -> getSubRegisters ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SubSet [ <NUM_LIT> ] , getKillRegState ( isKill ) ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SubSet [ <NUM_LIT> ] , getKillRegState ( isKill ) ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } } else llvm_unreachable ( <STR_LIT> ) ;


<s> const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createAMDGPUStructurizeCFGPass ( ) ) ; addPass ( create<ISA_LIT>AnnotateControlFlowPass ( ) ) ; } else {

addPass ( createR600TextureIntrinsicsReplacer ( ) ) ;


<s> explicit <ISA_LIT>16DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OL ) : <ISA_LIT>DAGToDAGISel ( TM , OL ) {


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ;


<s> const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , getRegisterName ) ; if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { OS << <STR_LIT> ; printPCRelImm ( MI , <NUM_LIT> , OS ) ; }

else if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) {


<s> { MO_LO16 , <STR_LIT> } , { MO_HI16 , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ;


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;

MCAsmParserExtension :: Initialize ( Parser ) ;


<s> unsigned getCalleeSavedFrameSize ( ) const {


<s> if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && & MBB != MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; return false ;


<s> if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; } else llvm_unreachable ( <STR_LIT> ) ;

if ( AM . Scale == <NUM_LIT> ) return true ;


<s> inline static bool isPCRelBlockReference ( unsigned char Flag ) { switch ( Flag ) { default : return false ; case <STR_LIT> : return true ; }


<s> if ( SMALL_INT_UNSIGNED ( op1 ) ) ret = <STR_LIT> ; else if ( SMALL_INT ( op1 ) ) ret = <STR_LIT> ; else ret = <STR_LIT> ; } } else if ( code1 == CONST_DOUBLE && mode == SFmode ) { if ( op1 == CONST0_RTX ( SFmode ) ) { if ( GP_REG_P ( regno0 ) ) ret = <STR_LIT> ; } else { delay = DELAY_LOAD ; ret = <STR_LIT> ; } } else if ( code1 == LABEL_REF ) { if ( TARGET_STATS ) iq2000_count_memory_refs ( op1 , <NUM_LIT> ) ; ret = <STR_LIT> ; } else if ( code1 == SYMBOL_REF || code1 == CONST ) { if ( TARGET_STATS ) iq2000_count_memory_refs ( op1 , <NUM_LIT> ) ; ret = <STR_LIT> ; } else if ( code1 == PLUS ) { rtx add_op0 = XEXP ( op1 , <NUM_LIT> ) ; rtx add_op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == CONST_INT ) add_op0 = XEXP ( op1 , <NUM_LIT> ) , add_op1 = XEXP ( op1 , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = add_op0 ; operands [ <NUM_LIT> ] = add_op1 ; ret = <STR_LIT> ; } else if ( code1 == HIGH ) { operands [ <NUM_LIT> ] = XEXP ( op1 , <NUM_LIT> ) ; ret = <STR_LIT> ; } } else if ( code0 == MEM ) { if ( TARGET_STATS ) iq2000_count_memory_refs ( op0 , <NUM_LIT> ) ; if ( code1 == REG ) { int regno1 = REGNO ( op1 ) + subreg_offset1 ; if ( GP_REG_P ( regno1 ) ) { switch ( mode ) { case SFmode : ret = <STR_LIT> ; break ; case SImode : ret = <STR_LIT> ; break ; case HImode : ret = <STR_LIT> ; break ; case QImode : ret = <STR_LIT> ; break ; default : break ; } } } else if ( code1 == CONST_INT && INTVAL ( op1 ) == <NUM_LIT> ) { switch ( mode ) { case SFmode : ret = <STR_LIT> ; break ; case SImode : ret = <STR_LIT> ; break ; case HImode : ret = <STR_LIT> ; break ; case QImode : ret = <STR_LIT> ; break ; default : break ; } } else if ( code1 == CONST_DOUBLE && op1 == CONST0_RTX ( mode ) ) { switch ( mode ) { case SFmode : ret = <STR_LIT> ; break ;


<s> if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI ) ;


<s> if ( isThumb ( ) ) return <STR_LIT> ; if ( hasV4TOps ( ) ) return <STR_LIT> ;


<s> } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return <NUM_LIT> ; if ( invert_move ) { tmp = op_true ; op_true = op_false ; op_false = tmp ; } cond2 = gen_rtx_fmt_ee ( NE , cc_mode , gen_lowpart ( dest_mode , mask ) , CONST0_RTX ( dest_mode ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( dest_mode , cond2 , op_true , op_false ) ) ) ;


<s> bool <ISA_LIT>FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = <NUM_LIT> ; unsigned XMMCalleeSavedFrameSize = <NUM_LIT> ; auto & WinEHXMMSlotInfo = <ISA_LIT>FI -> getWinEHXMMSlotInfo ( ) ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; int64_t TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( this -> TRI -> hasBasePointer ( MF ) ) { if ( MF . hasEHFunclets ( ) ) { int FI = MFI . CreateSpillStackObject ( SlotSize , Align ( SlotSize ) ) ; <ISA_LIT>FI -> setHasSEHFramePtrSave ( true ) ; <ISA_LIT>FI -> setSEHFramePtrSaveIndex ( FI ) ; } } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; Register FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; MFI . setCVBytesOfCalleeSavedRegisters ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ;

if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ;


<s> const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = PointerType :: get ( ParamTy , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned TypeSize = DL . getTypeStoreSize ( ParamTy ) ;

Register PtrReg = lowerParameterPtr ( MIRBuilder , ParamTy , Offset ) ;


<s> case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } } case <STR_LIT> : switch ( MI -> getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; }


<s> if ( isVOP2 ( MI -> getOpcode ( ) ) && ( ! isOperandLegal ( MI , Src0Idx , & Src1 ) || ! isOperandLegal ( MI , Src1Idx , & Src0 ) ) ) { return nullptr ; } if ( ! Src1 . isReg ( ) ) { if ( NewMI || ! Src1 . isImm ( ) || ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) ) { return nullptr ; } if ( MachineOperand * Src0Mods = getNamedOperand ( * MI , <STR_LIT> :: src0_modifiers ) ) { MachineOperand * Src1Mods = getNamedOperand ( * MI , <STR_LIT> :: src1_modifiers ) ;

int Src0ModsVal = Src0Mods -> getImm ( ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;