<s> if ( len == <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( speed ) { int n = ( len + <NUM_LIT> ) / <NUM_LIT> ; if ( xtensa_is_insn_L32R_p ( insn ) ) return COSTS_N_INSNS ( <NUM_LIT> + xtensa_extra_l32r_costs ) ; switch ( get_attr_type ( insn ) ) { case TYPE_STORE : case TYPE_MOVE : case TYPE_ARITH : case TYPE_MULTI : case TYPE_NOP : case TYPE_FSTORE : return COSTS_N_INSNS ( n ) ; case TYPE_LOAD : return COSTS_N_INSNS ( n - <NUM_LIT> + <NUM_LIT> ) ; case TYPE_JUMP : case TYPE_CALL : return COSTS_N_INSNS ( n - <NUM_LIT> + <NUM_LIT> ) ; case TYPE_FCONV : case TYPE_FLOAD : case TYPE_MUL16 : case TYPE_MUL32 : case TYPE_RSR : return COSTS_N_INSNS ( n * <NUM_LIT> ) ; case TYPE_FMADD : return COSTS_N_INSNS ( n * <NUM_LIT> ) ; case TYPE_DIV32 : return COSTS_N_INSNS ( n * <NUM_LIT> ) ; default : break ;


<s> SDValue Data = Op . getOperand ( <NUM_LIT> ) ; VTSDNode * BaseType = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; DebugLoc DL = Op . getDebugLoc ( ) ; EVT DVT = Data . getValueType ( ) ; EVT BVT = BaseType -> getVT ( ) ; unsigned baseBits = BVT . getScalarType ( ) . getSizeInBits ( ) ; unsigned srcBits = DVT . isSimple ( ) ? DVT . getScalarType ( ) . getSizeInBits ( ) : <NUM_LIT> ; unsigned shiftBits = srcBits - baseBits ; if ( srcBits < <NUM_LIT> ) { EVT IVT = genIntType ( <NUM_LIT> , DVT . isVector ( ) ? DVT . getVectorNumElements ( ) : <NUM_LIT> ) ; Data = DAG . getNode ( <STR_LIT> , DL , IVT , Data ) ; shiftBits = <NUM_LIT> - baseBits ;


return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> } else if ( ( GET_CODE ( SET_DEST ( exp ) ) == REG || GET_CODE ( SET_DEST ( exp ) ) == MEM ) && GET_CODE ( SET_SRC ( exp ) ) != PC && ( GET_MODE ( SET_DEST ( exp ) ) == HImode || GET_MODE ( SET_DEST ( exp ) ) == QImode ) && ( GET_CODE ( SET_SRC ( exp ) ) == PLUS || GET_CODE ( SET_SRC ( exp ) ) == MINUS || GET_CODE ( SET_SRC ( exp ) ) == AND || GET_CODE ( SET_SRC ( exp ) ) == IOR || GET_CODE ( SET_SRC ( exp ) ) == XOR || GET_CODE ( SET_SRC ( exp ) ) == NOT || GET_CODE ( SET_SRC ( exp ) ) == NEG || GET_CODE ( SET_SRC ( exp ) ) == REG || GET_CODE ( SET_SRC ( exp ) ) == MEM ) ) { cc_status . flags = <NUM_LIT> ; cc_status . value1 = SET_SRC ( exp ) ; cc_status . value2 = SET_DEST ( exp ) ; if ( cc_status . value1 && GET_CODE ( cc_status . value1 ) == REG && cc_status . value2 && reg_overlap_mentioned_p ( cc_status . value1 , cc_status . value2 ) ) cc_status . value2 = <NUM_LIT> ; if ( cc_status . value1 && GET_CODE ( cc_status . value1 ) == MEM && cc_status . value2 && GET_CODE ( cc_status . value2 ) == MEM ) cc_status . value2 = <NUM_LIT> ; } else if ( GET_CODE ( SET_SRC ( exp ) ) == CALL ) {


<s> } else if ( ! MRI -> hasOneDef ( Reg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; } assert ( MRI -> hasOneDef ( Reg ) && <STR_LIT> ) ; MachineOperand * Def = & ( * ( MRI -> def_begin ( Reg ) ) ) ; MachineOperand * UseOperand = & ( RI ) ; bool UseIsOutsideDefMBB = Def -> getParent ( ) -> getParent ( ) != MBB ;

if ( UseIsOutsideDefMBB && UseOperand -> isKill ( ) ) {


<s> if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue Bits = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bits ) ; if ( Op . getValueType ( ) == <STR_LIT> ) FP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FP , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return FP ; } assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ;

SDValue Ext64 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> cast < MCSymbolELF > ( Symbol ) -> setOther ( ELF :: STO_AARCH64_VARIANT_PCS ) ;


<s> if ( read_vl_insn_p ( i -> rtl ( ) ) ) continue ; if ( find_access ( i -> defs ( ) , REGNO ( dem . get_avl ( ) ) ) ) return false ; if ( dest && find_access ( i -> defs ( ) , REGNO ( dest ) ) ) return false ;


<s> EmitIMM ( const MCInst & MI , unsigned & CurByte , raw_ostream & OS ) const { switch ( MI . getOpcode ( ) ) {


<s> if ( abs ( complow - x ) <= abs ( comphigh - x ) ) return complow ;


<s> for ( unsigned i = NumElems / <NUM_LIT> , e = NumElems ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; return true ;


<s> break ; default : llvm_unreachable ( <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Ptr ) , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( SRLPad , <STR_LIT> ) ) ;


<s> if ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) ) { Function * MCR = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Value * args [ <NUM_LIT> ] = { Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) , Builder . getInt32 ( <NUM_LIT> ) } ; return Builder . CreateCall ( MCR , args ) ;


<s> const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( D ) ; const MCRegisterInfo * RegInfo = Dis -> getContext ( ) . getRegisterInfo ( ) ;

return RegInfo -> getRegClass ( RC ) . getRegister ( RegNo ) ;


<s> rtx temp_reg = NULL ; if ( rl78_far_p ( operands [ <NUM_LIT> ] ) ) { temp_reg = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; did = <NUM_LIT> ; } if ( ! did ) return <NUM_LIT> ;

emit_insn ( gen ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ;


<s> bool hasResetReferenceBitsMultiple ( ) const {


<s> unsigned PFetchInstrID = PrefInfo . InstructionID ; int64_t Delta = PrefInfo . Delta ; const MCInstrDesc & Desc = TII -> get ( PFetchInstrID ) ; MachineInstr * PFetch = MF . CreateMachineInstr ( Desc , Current -> getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , PFetch ) ; static_assert ( <STR_LIT> == <NUM_LIT> && <STR_LIT> == <NUM_LIT> && <STR_LIT> == <NUM_LIT> && <STR_LIT> == <NUM_LIT> && <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; MIB . addReg ( Current -> getOperand ( MemOpOffset + <STR_LIT> ) . getReg ( ) ) . addImm ( Current -> getOperand ( MemOpOffset + <STR_LIT> ) . getImm ( ) ) . addReg ( Current -> getOperand ( MemOpOffset + <STR_LIT> ) . getReg ( ) ) . addImm ( Current -> getOperand ( MemOpOffset + <STR_LIT> ) . getImm ( ) + Delta ) . addReg ( Current -> getOperand ( MemOpOffset + <STR_LIT> ) . getReg ( ) ) ; if ( ! Current -> memoperands_empty ( ) ) { MachineMemOperand * CurrentOp = * ( Current -> memoperands_begin ( ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( CurrentOp , CurrentOp -> getOffset ( ) + Delta , CurrentOp -> getSize ( ) ) ) ;


<s> if ( MI -> getOperand ( i ) . isImplicit ( ) ) continue ; if ( ( int ) i != OpNum + <NUM_LIT> ) O << <STR_LIT> ; printOperand ( MI , i ) ; }


<s> return ( ( DstReg - SrcReg ) & <NUM_LIT> ) < NumRegs ;


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( STM . getInstrInfo ( ) ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; assert ( ! MRI -> isSSA ( ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) { std :: string CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return Success ;


auto Val = Signed ? decodeSLEB128 ( Bytes . data ( ) + Size , & N , Bytes . data ( ) + Bytes . size ( ) , & Error ) : static_cast < int64_t > ( decodeULEB128 ( Bytes . data ( ) + Size , & N , Bytes . data ( ) + Bytes . size ( ) , & Error ) ) ;


<s> return OriginalArgWasFloatVector [ ValNo ] ;


<s> const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return TM -> getSubtarget < <ISA_LIT>GenSubtargetInfo > ( ) . createDFAPacketizer ( II ) ;


<s> TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>leTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>beTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>leTarget , create<ISA_LIT>leAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>beTarget , create<ISA_LIT>beAsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>leTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>beTarget , createMCStreamer ) ;

TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>leTarget , create<ISA_LIT>MCInstPrinter ) ;


<s> int Offset = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) ; int RegisterIndex = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned BaseReg = getReg ( Decoder , RC , RegisterIndex ) ; Inst . addOperand ( MCOperand :: createReg ( BaseReg ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ;


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( ! tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) return true ; Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , is<ISA_LIT>64 ( ) ) ) return true ; if ( ! getLexer ( ) . is ( AsmToken :: RParen ) ) return true ; S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : if ( searchSymbolAlias ( Operands , <STR_LIT> ) ) return false ; case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;


<s> vpadalq_u8 ( uint16x8_t a , uint8x16_t b ) {


<s> static DecodeStatus DecodeAVLdSt_96RegisterClass ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return decodeOperand_AVLdSt_Any ( Inst , Imm , <ISA_LIT>Disassembler :: OPW96 , Decoder ) ;


<s> const auto & MFI = MF . getFrameInfo ( ) ;

return MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) ;


<s> if ( isa < BitCastInst > ( Inst ) ) { for ( Use & U : Inst -> uses ( ) ) Uses . push_back ( & U ) ; continue ; } if ( auto * GEP = dyn_cast < GetElementPtrInst > ( Inst ) ) { Value * Index = GEPToVectorIndex ( GEP , Alloca , VecEltTy , DL ) ; if ( ! Index ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * GEP << '\n' ) ; return false ; } GEPVectorIdx [ GEP ] = Index ; for ( Use & U : Inst -> uses ( ) ) Uses . push_back ( & U ) ; continue ; } if ( isAssumeLikeIntrinsic ( Inst ) ) continue ; if ( isa < ICmpInst > ( Inst ) && all_of ( Inst -> users ( ) , [ ] ( User * U ) { return isAssumeLikeIntrinsic ( cast < Instruction > ( U ) ) ; } ) ) continue ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * AllocaTy << <STR_LIT> << * VectorTy << '\n' ) ; for ( Instruction * Inst : WorkList ) { IRBuilder < > Builder ( Inst ) ; switch ( Inst -> getOpcode ( ) ) { case Instruction :: Load : { Value * Ptr = cast < LoadInst > ( Inst ) -> getPointerOperand ( ) ; Value * Index = calculateVectorIndex ( Ptr , GEPVectorIdx ) ; Type * VecPtrTy = VectorTy -> getPointerTo ( Alloca -> getAddressSpace ( ) ) ; Value * BitCast = Builder . CreateBitCast ( Alloca , VecPtrTy ) ; Value * VecValue = Builder . CreateLoad ( VectorTy , BitCast ) ; Value * ExtractElement = Builder . CreateExtractElement ( VecValue , Index ) ; if ( Inst -> getType ( ) != VecEltTy ) ExtractElement = Builder . CreateBitOrPointerCast ( ExtractElement , Inst -> getType ( ) ) ; Inst -> replaceAllUsesWith ( ExtractElement ) ; Inst -> eraseFromParent ( ) ; break ; } case Instruction :: Store : { StoreInst * <ISA_LIT> = cast < StoreInst > ( Inst ) ; Value * Ptr = <ISA_LIT> -> getPointerOperand ( ) ; Value * Index = calculateVectorIndex ( Ptr , GEPVectorIdx ) ; Type * VecPtrTy = VectorTy -> getPointerTo ( Alloca -> getAddressSpace ( ) ) ; Value * BitCast = Builder . CreateBitCast ( Alloca , VecPtrTy ) ; Value * VecValue = Builder . CreateLoad ( VectorTy , BitCast ) ; Value * Elt = <ISA_LIT> -> getValueOperand ( ) ; if ( Elt -> getType ( ) != VecEltTy ) Elt = Builder . CreateBitOrPointerCast ( Elt , VecEltTy ) ; Value * NewVecValue = Builder . CreateInsertElement ( VecValue , Elt , Index ) ; Builder . CreateStore ( NewVecValue , BitCast ) ; Inst -> eraseFromParent ( ) ; break ;


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * FixupExpression = MCBinaryExpr :: createAdd ( MO . getExpr ( ) , MCConstantExpr :: create ( - <NUM_LIT> , Ctx ) , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , FixupExpression , MCFixupKind ( <STR_LIT> ) ) ) ; return <NUM_LIT> ;


<s> assert ( SpillList [ i ] . Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( SpillList [ i ] . Offset <= <NUM_LIT> && <STR_LIT> ) ; int OffsetFromTop = - SpillList [ i ] . Offset / <NUM_LIT> ; IfNeededExtSP ( MBB , MBBI , dl , TII , MMI , OffsetFromTop , Adjusted , FrameSize , emitFrameMoves ) ; int Offset = Adjusted - OffsetFromTop ; int Opcode = isImmU6 ( Offset ) ? <STR_LIT> : <STR_LIT> ; MBB . addLiveIn ( SpillList [ i ] . Reg ) ; BuildMI ( MBB , MBBI , dl , TII . get ( Opcode ) ) . addReg ( SpillList [ i ] . Reg , RegState :: Kill ) . addImm ( Offset ) . addMemOperand ( getFrameIndexMMO ( MBB , SpillList [ i ] . FI , MachineMemOperand :: MOStore ) ) ; if ( emitFrameMoves ) { unsigned DRegNum = MRI -> getDwarfRegNum ( SpillList [ i ] . Reg , true ) ; EmitCfiOffset ( MBB , MBBI , dl , TII , MMI , DRegNum , SpillList [ i ] . Offset ) ; } } IfNeededExtSP ( MBB , MBBI , dl , TII , MMI , FrameSize , Adjusted , FrameSize , emitFrameMoves ) ; assert ( Adjusted == FrameSize && <STR_LIT> ) ; if ( FP ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addImm ( <NUM_LIT> ) ; if ( emitFrameMoves ) EmitDefCfaRegister ( MBB , MBBI , dl , TII , MMI , MRI -> getDwarfRegNum ( FramePtr , true ) ) ; } if ( emitFrameMoves ) { for ( const auto & SpillLabel : XFI -> getSpillLabels ( ) ) { MachineBasicBlock :: iterator Pos = SpillLabel . first ; ++ Pos ; const CalleeSavedInfo & CSI = SpillLabel . second ; int Offset = MFI -> getObjectOffset ( CSI . getFrameIdx ( ) ) ;

unsigned DRegNum = MRI -> getDwarfRegNum ( CSI . getReg ( ) , true ) ;


<s> register UDItype_x l ; dl1 . d = a1 ; if ( ! EXPD ( dl1 ) || SIGND ( dl1 ) ) return <NUM_LIT> ; exp = EXPD ( dl1 ) - EXPONENT_BIAS - MANTISSA_BITS ; if ( exp <= - PRECISION ) return <NUM_LIT> ; if ( ( EXPD ( dl1 ) == <NUM_LIT> ) && ! FRACD_ZERO_P ( dl1 ) ) return <NUM_LIT> ; if ( exp >= - HIGH_LL_FRAC_BITS ) return <NUM_LIT> ;


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc SL ( N ) ; if ( ! Subtarget -> hasDLInsts ( ) || VT != <STR_LIT> ) return SDValue ( ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = N -> getOperand ( <NUM_LIT> ) ; SDValue FMA = N -> getOperand ( <NUM_LIT> ) ; if ( FMA . getOpcode ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const TargetOptions & Options = DAG . getTarget ( ) . Options ; if ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath || ( N -> getFlags ( ) . hasAllowContract ( ) && FMA -> getFlags ( ) . hasAllowContract ( ) ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; Op2 = Op2 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || Op2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Idx1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Vec2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FMAOp1 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAOp2 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAAcc = FMA . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; FMAOp1 = FMAOp1 . getOperand ( <NUM_LIT> ) ; FMAOp2 = FMAOp2 . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec3 = FMAOp1 . getOperand ( <NUM_LIT> ) ;

SDValue Vec4 = FMAOp2 . getOperand ( <NUM_LIT> ) ;


<s> const LiveInterval & LI = LIS . getInterval ( Reg ) ; VNInfo * DefVNI = MO . isDef ( ) ? LI . getVNInfoAt ( LIS . getInstructionIndex ( Def ) . getRegSlot ( ) ) : LI . getVNInfoBefore ( LIS . getInstructionIndex ( Def ) ) ; assert ( DefVNI && <STR_LIT> ) ; VNInfo * InsVNI = LI . getVNInfoBefore ( LIS . getInstructionIndex ( Insert ) ) ; if ( InsVNI && DefVNI != InsVNI ) return false ; } for ( -- I ; I != D ; -- I ) SawSideEffects |= ! I -> isSafeToMove ( & AA , SawStore ) ;

return ! ( SawStore && Def -> mayLoad ( ) && ! Def -> isInvariantLoad ( & AA ) ) && ! ( SawSideEffects && ! Def -> isSafeToMove ( & AA , SawStore ) ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return subtarget . getInstrInfo ( ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ;

SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ;


<s> SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ; } if ( FSB ) { const MCInstrDesc & D = HasBranch ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , D ) ; if ( ! HasBranch ) MIB . addReg ( FP . PredR ) ; MIB . addMBB ( FSB ) ; FP . SplitB -> addSuccessor ( FSB ) ; } if ( SSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( SSB ) ; FP . SplitB -> addSuccessor ( SSB ) ; }


<s> bool isXNACKEnabled ( ) const { return EnableXNACK ;


<s> if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ; } case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , CPSRDef , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ;


<s> edge e ; edge_iterator ( ei ) ; FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( target -> flags & BB_VISITED ) n = nvptx_sese_number ( n , p , dir , target , list ) ; } dir = - dir ; } return n ;


<s> if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDZ = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDY = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDZ = true ; } bool HasStackObjects = FrameInfo . hasStackObjects ( ) ; if ( isEntryFunction ( ) ) { if ( WorkItemIDZ ) WorkItemIDY = true ; PrivateSegmentWaveByteOffset = true ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 && ( CC == CallingConv :: <ISA_LIT>_HS || CC == CallingConv :: <ISA_LIT>_GS ) ) ArgInfo . PrivateSegmentWaveByteOffset = ArgDescriptor :: createRegister ( <STR_LIT> ) ; } bool isAmdHsaOrMesa = ST . isAmdHsaOrMesa ( F ) ; if ( isAmdHsaOrMesa ) { PrivateSegmentBuffer = true ; if ( UseFixedABI ) { DispatchPtr = true ; QueuePtr = true ; DispatchID = true ; } else { if ( F . hasFnAttribute ( <STR_LIT> ) ) DispatchPtr = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) QueuePtr = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) DispatchID = true ; } } else if ( ST . isMesaGfxShader ( F ) ) { ImplicitBufferPtr = true ; } if ( UseFixedABI || F . hasFnAttribute ( <STR_LIT> ) ) KernargSegmentPtr = true ; if ( ST . hasFlatAddressSpace ( ) && isEntryFunction ( ) && isAmdHsaOrMesa ) { auto hasNonSpillStackObjects = [ & ] ( ) { if ( ! HasStackObjects ) return false ; for ( auto OI = FrameInfo . getObjectIndexBegin ( ) , OE = FrameInfo . getObjectIndexEnd ( ) ; OI != OE ; ++ OI ) if ( ! FrameInfo . isSpillSlotObjectIndex ( OI ) ) return true ; return false ; } ; if ( HasCalls || hasNonSpillStackObjects ( ) ) FlatScratchInit = true ; } Attribute A = F . getFnAttribute ( <STR_LIT> ) ; StringRef S = A . getValueAsString ( ) ; if ( ! S . empty ( ) ) S . consumeInteger ( <NUM_LIT> , GITPtrHigh ) ; A = F . getFnAttribute ( <STR_LIT> ) ; S = A . getValueAsString ( ) ; if ( ! S . empty ( ) ) S . consumeInteger ( <NUM_LIT> , HighBitsOf32BitAddress ) ;

S = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ;


<s> node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ; node_names [ ( unsigned ) <STR_LIT> ] = <STR_LIT> ;


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) {


<s> static bool isImplicitDependency ( const MachineInstr & I , unsigned DepReg ) { for ( auto & MO : I . operands ( ) ) if ( MO . isReg ( ) && MO . isDef ( ) && ( MO . getReg ( ) == DepReg ) && MO . isImplicit ( ) ) return true ;


<s> bool <ISA_LIT>DAGToDAGISel :: isRunOfOnes ( unsigned Val , unsigned & MB , unsigned & ME ) { if ( isShiftedMask_32 ( Val ) ) { MB = countLeadingZeros ( Val ) ;

ME = countLeadingZeros ( ( Val - <NUM_LIT> ) ^ Val ) ;


<s> MachineOperand & Dest = ( * MI ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = ( * MI ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = ( * MI ) -> getOperand ( <NUM_LIT> ) ; bool IsADDIInstRequired = ! useSameRegister ( Dest , TrueValue ) ; bool IsORIInstRequired = ! useSameRegister ( Dest , FalseValue ) ; if ( ! IsADDIInstRequired && ! IsORIInstRequired ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; NumRemoved ++ ; ( * MI ) -> eraseFromParent ( ) ; MI = BIL . erase ( MI ) ; continue ; } if ( useSameRegister ( TrueValue , FalseValue ) && ( BIL . size ( ) == <NUM_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; NumFolded ++ ; BuildMI ( * MBB , ( * MI ) , dl , TII -> get ( isISEL8 ( * * MI ) ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( TrueValue ) . add ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; ( * MI ) -> eraseFromParent ( ) ;


<s> MF -> RenumberBlocks ( FromBB ) ; MachineFunction :: iterator Begin ; if ( FromBB == nullptr ) { Begin = MF -> begin ( ) ; } else { Begin = FromBB -> getIterator ( ) ; }

BlockOffsets . resize ( MF -> getNumBlockIDs ( ) ) ;


<s> if ( EnableRDFOpt ) addPass ( create<ISA_LIT>RDFOpt ( ) ) ; if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( ) ) ; if ( ! DisableAModeOpt ) addPass ( create<ISA_LIT>OptAddrMode ( ) ) ;


<s> O << <STR_LIT> ; printSaveRestore ( MI , O ) ; O << <STR_LIT> ; return ; } if ( ! printAliasInstr ( MI , Address , O ) && ! printAlias ( * MI , O ) ) printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ;


<s> InOp = InOp . getOperand ( <NUM_LIT> ) ; InVT = InOp . getSimpleValueType ( ) ; InNumElts = InVT . getVectorNumElements ( ) ; } } if ( <STR_LIT> ( InOp . getNode ( ) ) || <STR_LIT> ( InOp . getNode ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < InNumElts ; ++ i ) Ops . push_back ( InOp . getOperand ( i ) ) ; SDValue FillVal = FillWithZeroes ? DAG . getConstant ( <NUM_LIT> , dl , EltVT ) : DAG . getUNDEF ( EltVT ) ; for ( unsigned i = <NUM_LIT> ; i < WidenNumElts - InNumElts ; ++ i ) Ops . push_back ( FillVal ) ;

return DAG . getNode ( <STR_LIT> , dl , NVT , Ops ) ;


<s> bool MadeChange = false ; for ( unsigned i = <NUM_LIT> , e = PushPopMIs . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = PushPopMIs [ i ] ; if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) {

BuildMI ( MI -> getParent ( ) , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( Mangler * mang , MCContext & ctx , <ISA_LIT>AsmPrinter & asmprinter ) : Mang ( mang ) , Ctx ( ctx ) , AsmPrinter ( asmprinter ) {


return __builtin_aarch64_ld1v2df ( ( const __builtin_aarch64_simd_df * ) a ) ;


<s> void addOptimizedRegAlloc ( ) override {


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , uint8_t _OSABI ) : <ISA_LIT>AsmBackend ( T , TT ) , OSABI ( _OSABI ) {


<s> static void fail ( SDLoc DL , SelectionDAG & DAG , const char * msg ) {

MachineFunction & MF = DAG . getMachineFunction ( ) ;


<s> MCSectionELF * ConfigSection = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; OutStreamer -> SwitchSection ( ConfigSection ) ; EmitProgramInfo<ISA_LIT> ( MF ) ; EmitFunctionBody ( ) ;


<s> bool <ISA_LIT>BitSimplify :: replaceSubWithSub ( unsigned OldR , unsigned OldSR , unsigned NewR , unsigned NewSR , MachineRegisterInfo & MRI ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( OldR ) || ! TargetRegisterInfo :: isVirtualRegister ( NewR ) ) return false ; auto Begin = MRI . use_begin ( OldR ) , End = MRI . use_end ( ) ; decltype ( End ) NextI ;

for ( auto I = Begin ; I != End ; I = NextI ) {


<s> OutStreamer -> SwitchSection ( Csect ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GV -> hasCommonLinkage ( ) || GVKind . isBSSLocal ( ) || GVKind . isThreadBSSLocal ( ) ) { Align Alignment = GV -> getAlign ( ) . getValueOr ( DL . getPreferredAlign ( GV ) ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getValueType ( ) ) ; GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; if ( GVKind . isBSSLocal ( ) || GVKind . isThreadBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( OutContext . getOrCreateSymbol ( GVSym -> getSymbolTableName ( ) ) , Size , GVSym , Alignment . value ( ) ) ;

else OutStreamer -> emitCommonSymbol ( GVSym , Size , Alignment . value ( ) , TailPaddingAmount :: None ) ;


<s> void <ISA_LIT>16DAGToDAGISel :: initGlobalBaseReg ( MachineFunction & MF ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! <ISA_LIT>FI -> globalBaseRegSet ( ) ) return ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned V0 , V1 , V2 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ;

const TargetRegisterClass * RC = ( const TargetRegisterClass * ) & <STR_LIT> ;


<s> break ; case MachO :: <ISA_LIT>_THUMB_RELOC_BR22 : Value -= <NUM_LIT> ; Range = <NUM_LIT> ; } Value += Writer -> getSectionAddress ( & S . getSection ( ) ) ; Value -= Writer -> getSectionAddress ( Fragment . getParent ( ) ) ; if ( Value > Range || Value < - ( Range + <NUM_LIT> ) ) return true ; return false ;


<s> case <STR_LIT> : if ( Use -> isMachineOpcode ( ) ) return <NUM_LIT> ; MaxTruncation = std :: max ( MaxTruncation , Use -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) ; continue ; case <STR_LIT> : { if ( Use -> isMachineOpcode ( ) ) return <NUM_LIT> ; StoreSDNode * STN = cast < StoreSDNode > ( * Use ) ; unsigned MemVTSize = STN -> getMemoryVT ( ) . getSizeInBits ( ) ; if ( MemVTSize == <NUM_LIT> || Use . getOperandNo ( ) != <NUM_LIT> ) return <NUM_LIT> ; MaxTruncation = std :: max ( MaxTruncation , MemVTSize ) ; continue ; } case <STR_LIT> : case <STR_LIT> :


<s> bool has3E3r1 ( ) const { return Has3E3r1 ;


<s> MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } break ; } case <NUM_LIT> : { switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; else BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; break ; } } unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; bool TryFold = false ; if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) {


<s> FunctionPass * llvm :: create<ISA_LIT>LDCleanupPass ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>LDCleanup ( ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } }

AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ;


<s> if ( YIn . error ( ) ) return false ; return EmitHSAMetadata ( HSAMetadataRoot , false ) ;


<s> return MCID . TSFlags & <STR_LIT> || MCID . TSFlags & <STR_LIT> || MCID . TSFlags & <STR_LIT> ;


<s> <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> void d30v_expand_epilogue ( ) { rtx sp = stack_pointer_rtx ; d30v_stack_t * info = d30v_stack_info ( ) ; int i ; rtx mem_di = NULL_RTX ; rtx mem_si = NULL_RTX ; rtx post_inc ; int extra_stack ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) emit_move_insn ( sp , frame_pointer_rtx ) ; if ( info -> save_offset ) emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( info -> save_offset ) ) ) ; post_inc = gen_rtx ( POST_INC , Pmode , sp ) ; mem_di = gen_rtx ( MEM , DImode , post_inc ) ; mem_si = gen_rtx ( MEM , SImode , post_inc ) ; for ( i = ACCUM_FIRST ; i <= ACCUM_LAST ; i ++ ) if ( info -> save_p [ i ] ) { rtx acc_tmp = gen_rtx ( REG , DImode , GPR_ATMP_FIRST ) ; emit_insn ( gen_movdi ( acc_tmp , mem_di ) ) ; emit_insn ( gen_movdi ( gen_rtx ( REG , DImode , i ) , acc_tmp ) ) ; } for ( i = GPR_FIRST ; i <= GPR_LAST ; i += <NUM_LIT> ) if ( info -> save_p [ i ] == <NUM_LIT> ) emit_insn ( gen_movdi ( gen_rtx ( REG , DImode , i ) , mem_di ) ) ; extra_stack = <NUM_LIT> ; for ( i = GPR_FIRST ; i <= GPR_LAST ; i ++ ) if ( info -> save_p [ i ] == <NUM_LIT> ) { if ( cfun -> machine -> eh_epilogue_sp_ofs && i == GPR_LINK ) extra_stack = <NUM_LIT> ; else { if ( extra_stack ) { emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( extra_stack ) ) ) ; extra_stack = <NUM_LIT> ; } emit_insn ( gen_movsi ( gen_rtx ( REG , SImode , i ) , mem_si ) ) ; } } if ( ( info -> memrefs_1word & <NUM_LIT> ) != <NUM_LIT> ) extra_stack += UNITS_PER_WORD ; extra_stack += current_function_pretend_args_size + info -> varargs_size ; if ( extra_stack ) { if ( cfun -> machine -> eh_epilogue_sp_ofs ) emit_insn ( gen_addsi3 ( cfun -> machine -> eh_epilogue_sp_ofs , cfun -> machine -> eh_epilogue_sp_ofs , GEN_INT ( extra_stack ) ) ) ; else emit_insn ( gen_addsi3 ( sp , sp , GEN_INT ( extra_stack ) ) ) ;


<s> <ISA_LIT>PreRegAlloc ( ) : MachineFunctionPass ( ID ) {


<s> case PRE_DEC : case POST_DEC : if ( mode != QImode && mode != QFmode ) return <NUM_LIT> ; case PRE_INC : case POST_INC : op = XEXP ( op , <NUM_LIT> ) ; case REG : return IS_ADDR_OR_PSEUDO_REG ( op ) ; case PRE_MODIFY : case POST_MODIFY : { rtx op0 = XEXP ( op , <NUM_LIT> ) ; rtx op1 = XEXP ( op , <NUM_LIT> ) ; if ( mode != QImode && mode != QFmode ) return <NUM_LIT> ; if ( ( GET_CODE ( op1 ) != PLUS && GET_CODE ( op1 ) != MINUS ) || ( op0 != XEXP ( op1 , <NUM_LIT> ) ) ) return <NUM_LIT> ; op0 = XEXP ( op1 , <NUM_LIT> ) ; op1 = XEXP ( op1 , <NUM_LIT> ) ; return REG_P ( op0 ) && IS_ADDR_OR_PSEUDO_REG ( op0 ) && REG_P ( op1 ) && IS_INDEX_OR_PSEUDO_REG ( op1 ) ;


<s> switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> if ( Op -> getSrcTy ( ) == i128 ) { I . replaceAllUsesWith ( Op -> getOperand ( <NUM_LIT> ) ) ; I . eraseFromParent ( ) ; } }


<s> unsigned SourcePhysReg = VA . getLocReg ( ) ; unsigned ResultReg = <NUM_LIT> ; if ( RetVT == CopyVT ) { const TargetRegisterClass * CpyRC = TLI . getRegClassFor ( CopyVT ) ; ResultReg = createResultReg ( CpyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SourcePhysReg ) ; } else if ( CopyVT == <STR_LIT> ) { ResultReg = createResultReg ( TLI . getRegClassFor ( RetVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( SourcePhysReg ) ; } else if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) { ResultReg = createResultReg ( & <STR_LIT> ) ; SourcePhysReg -= <STR_LIT> - <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SourcePhysReg ) ;


<s> unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ;

MIB . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( SrcIsKill ) ) ;


<s> if ( isFMAddSubOrFMSubAdd ( Subtarget , DAG , Opnd0 , Opnd1 , Opnd2 , <NUM_LIT> ) ) { unsigned Opc = IsSubAdd ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; } if ( IsSubAdd ) return SDValue ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0 , Opnd1 ) ;


<s> rtx_insn * tmp ; rtx load_mem , str_mem ; if ( is_store_insn ( last_scheduled_insn , & str_mem ) ) load_store_pendulum -- ; else if ( is_load_insn ( last_scheduled_insn , & load_mem ) ) load_store_pendulum ++ ; else return cached_can_issue_more ; if ( ( load_store_pendulum == <NUM_LIT> ) || ( * pn_ready <= <NUM_LIT> ) ) return cached_can_issue_more ; if ( load_store_pendulum == <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < * pn_ready - <NUM_LIT> ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ * pn_ready - <NUM_LIT> ] = tmp ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( tmp ) ) INSN_PRIORITY ( tmp ) ++ ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) && ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ pos ] ) ) { INSN_PRIORITY ( ready [ pos ] ) ++ ; load_store_pendulum -- ;


<s> fputs ( <STR_LIT> , asm_out_file ) ; fputs ( sm_version_to_string ( ( enum ptx_isa ) ptx_isa_option ) , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fprintf ( asm_out_file , <STR_LIT> , GET_MODE_BITSIZE ( Pmode ) ) ;


<s> return info1 . get_vlmul ( ) != info2 . get_vlmul ( ) ;


<s> if ( CanFail ) return false ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; }

if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ;


<s> if ( ( RegNo & <NUM_LIT> ) || RegNo == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; unsigned RegisterPair = GPRPairDecoderTable [ RegNo / <NUM_LIT> ] ;

Inst . addOperand ( MCOperand :: createReg ( RegisterPair ) ) ;


<s> MachineInstr * CPEMI = U . CPEMI ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEMI , U . getMaxDisp ( ) , U . NegOk , true ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == nullptr ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getMaxDisp ( ) , U . NegOk ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount ++ ; return decrementCPEReferenceCount ( CPI , CPEMI ) ? <NUM_LIT> : <NUM_LIT> ; } } return <NUM_LIT> ;


<s> if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } else if ( ! TARGET_SV_MODE ) { error ( <STR_LIT> ) ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> void <ISA_LIT>AsmParser :: emitCapLoadTLSIEAddress ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ;

MCOperand TmpReg = Inst . getOperand ( <NUM_LIT> ) ;


<s> CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; CommentString = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; Data16bitsDirective = <STR_LIT> ;


<s> return new <ISA_LIT>LowerControlFlowPass ( tm ) ;


<s> } else { if ( isDef ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( RelocM == Reloc :: PIC_ ) { if ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) return true ; } } return false ;


<s> CC_STATUS_INIT ; if ( operands [ <NUM_LIT> ] == const0_rtx ) return <STR_LIT> ; return <STR_LIT> ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( logval = exact_log2 ( ~ INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) ) >= <NUM_LIT> && ( DATA_REG_P ( operands [ <NUM_LIT> ] ) || offsettable_memref_p ( operands [ <NUM_LIT> ] ) ) ) { if ( DATA_REG_P ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( logval ) ; else { operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , SImode , <NUM_LIT> - ( logval / <NUM_LIT> ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( logval % <NUM_LIT> ) ;


<s> int getVarArgsFrameIndex ( ) const {


<s> assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = alignTo ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc ) { unsigned CopyImm = std :: min ( Bytes , CopyRange ) / CopyScale ; Bytes -= CopyImm * CopyScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( CopyOpc ) , DestReg ) ; if ( CopyNeedsCC ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; MIB . addReg ( BaseReg , RegState :: Kill ) ; if ( CopyOpc != <STR_LIT> ) { MIB . addImm ( CopyImm ) ; } MIB . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg = DestReg ; } while ( Bytes ) { unsigned ExtraImm = std :: min ( Bytes , ExtraRange ) / ExtraScale ; Bytes -= ExtraImm * ExtraScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ExtraOpc ) , DestReg ) ; if ( ExtraNeedsCC ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; MIB . addReg ( BaseReg ) . addImm ( ExtraImm ) . add ( predOps ( <STR_LIT> ) ) . setMIFlags ( MIFlags ) ; }


<s> return ( Ty1 -> getPrimitiveSizeInBits ( ) > Ty2 -> getPrimitiveSizeInBits ( ) ) ;


if ( ! TARGET_IEEEQUAD ) init_float128_ibm ( TFmode ) ;


<s> Value * RetVal = Ret -> getReturnValue ( ) ; assert ( RetVal && <STR_LIT> ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { RetVal -> getType ( ) } , false ) ; Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( GetReturnSymbolName ( * RetVal ) , FnType ) ;

CallInst :: Create ( Fn , { RetVal } , <STR_LIT> , & I ) ;


<s> case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . isSymbol ( ) && <STR_LIT> ) ; OS << <STR_LIT> << MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) << <STR_LIT> << MAI -> getCommentString ( ) << <STR_LIT> ; break ; default :


<s> for ( auto & MBB : MF ) Modified |= runOnMBB ( MBB ) ; return Modified ;


<s> SDValue Build = ST -> getValue ( ) ; if ( MemVT != <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> ; I < MemVT . getVectorNumElements ( ) ; I ++ ) { unsigned Elt = DAG . getDataLayout ( ) . isBigEndian ( ) ? MemVT . getVectorNumElements ( ) - I - <NUM_LIT> : I ; Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Build , DAG . getConstant ( Elt , dl , <STR_LIT> ) ) ) ; }

for ( unsigned I = MemVT . getVectorNumElements ( ) ; I < <NUM_LIT> ; I ++ ) Ops . push_back ( DAG . getUNDEF ( <STR_LIT> ) ) ;


<s> OutStreamer . SwitchSection ( ConfigSection ) ; if ( STM . getGeneration ( ) > AMDGPUSubtarget :: NORTHERN_ISLANDS ) { EmitProgramInfo<ISA_LIT> ( MF ) ; } else { EmitProgramInfoR600 ( MF ) ; } OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; EmitFunctionBody ( ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createVTypeImm ( APInt sew , APInt lmul , APInt ediv , SMLoc S , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: VTypeImm ) ; sew . ashrInPlace ( <NUM_LIT> ) ; Op -> Vtypei . Sew = static_cast < VSEW > ( sew . logBase2 ( ) ) ; Op -> Vtypei . Lmul = static_cast < VLMUL > ( lmul . logBase2 ( ) ) ; Op -> Vtypei . Ediv = static_cast < VEDIV > ( ediv . logBase2 ( ) ) ; Op -> Vtypei . Encoding = ( ediv . logBase2 ( ) << <NUM_LIT> ) | ( sew . logBase2 ( ) << <NUM_LIT> ) | ( lmul . logBase2 ( ) ) ; Op -> StartLoc = S ; Op -> IsRV64 = IsRV64 ; return Op ;


<s> } if ( numArgs > <NUM_LIT> ) { if ( ( copr2 = dyn_cast < Constant > ( aCI -> getArgOperand ( <NUM_LIT> ) ) ) == nullptr ) return false ; } double DVal0 [ <NUM_LIT> ] , DVal1 [ <NUM_LIT> ] ; bool hasTwoResults = ( FInfo . getId ( ) == <ISA_LIT>LibFunc :: EI_<ISA_LIT>NCOS ) ; if ( getVecSize ( FInfo ) == <NUM_LIT> ) { if ( ! evaluateScalarMathFunc ( FInfo , DVal0 [ <NUM_LIT> ] , DVal1 [ <NUM_LIT> ] , copr0 , copr1 , copr2 ) ) { return false ; } } else { ConstantDataVector * CDV0 = dyn_cast_or_null < ConstantDataVector > ( copr0 ) ; ConstantDataVector * CDV1 = dyn_cast_or_null < ConstantDataVector > ( copr1 ) ; ConstantDataVector * CDV2 = dyn_cast_or_null < ConstantDataVector > ( copr2 ) ; for ( int i = <NUM_LIT> ; i < getVecSize ( FInfo ) ; ++ i ) { Constant * celt0 = CDV0 ? CDV0 -> getElementAsConstant ( i ) : nullptr ; Constant * celt1 = CDV1 ? CDV1 -> getElementAsConstant ( i ) : nullptr ; Constant * celt2 = CDV2 ? CDV2 -> getElementAsConstant ( i ) : nullptr ; if ( ! evaluateScalarMathFunc ( FInfo , DVal0 [ i ] , DVal1 [ i ] , celt0 , celt1 , celt2 ) ) { return false ; } } } LLVMContext & context = CI -> getParent ( ) -> getParent ( ) -> getContext ( ) ; Constant * nval0 , * nval1 ; if ( getVecSize ( FInfo ) == <NUM_LIT> ) { nval0 = ConstantFP :: get ( CI -> getType ( ) , DVal0 [ <NUM_LIT> ] ) ; if ( hasTwoResults ) nval1 = ConstantFP :: get ( CI -> getType ( ) , DVal1 [ <NUM_LIT> ] ) ; } else { if ( getArgType ( FInfo ) == <ISA_LIT>LibFunc :: F32 ) { SmallVector < float , <NUM_LIT> > FVal0 , FVal1 ; for ( int i = <NUM_LIT> ; i < getVecSize ( FInfo ) ; ++ i ) FVal0 . push_back ( ( float ) DVal0 [ i ] ) ; ArrayRef < float > tmp0 ( FVal0 ) ; nval0 = ConstantDataVector :: get ( context , tmp0 ) ; if ( hasTwoResults ) { for ( int i = <NUM_LIT> ; i < getVecSize ( FInfo ) ; ++ i ) FVal1 . push_back ( ( float ) DVal1 [ i ] ) ; ArrayRef < float > tmp1 ( FVal1 ) ; nval1 = ConstantDataVector :: get ( context , tmp1 ) ; } } else { ArrayRef < double > tmp0 ( DVal0 ) ;


<s> switch ( insn . eaBase ) { case EA_BASE_NONE : llvm_unreachable ( <STR_LIT> ) ; break ; ALL_EA_BASES llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; break ; case EA_REG_ ## x : \ mcInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; break ;


<s> OutStreamer -> EmitIntValue ( R_00B84C_COMPUTE_PGM_RSRC2 , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( CurrentProgramInfo . ComputePGMRSrc2 , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( R_00B860_COMPUTE_TMPRING_<ISA_LIT>ZE , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_00B860_WAVE<ISA_LIT>ZE ( CurrentProgramInfo . ScratchBlocks ) , <NUM_LIT> ) ; } else { OutStreamer -> EmitIntValue ( RsrcReg , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_00B028_VGPRS ( CurrentProgramInfo . VGPRBlocks ) | S_00B028_SGPRS ( CurrentProgramInfo . SGPRBlocks ) , <NUM_LIT> ) ; unsigned Rsrc2Val = <NUM_LIT> ; if ( STM . isVGPRSpillingEnabled ( * MF . getFunction ( ) ) ) { OutStreamer -> EmitIntValue ( R_0286E8_SPI_TMPRING_<ISA_LIT>ZE , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( S_0286E8_WAVE<ISA_LIT>ZE ( CurrentProgramInfo . ScratchBlocks ) , <NUM_LIT> ) ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) Rsrc2Val = S_00B84C_SCRATCH_EN ( CurrentProgramInfo . ScratchBlocks > <NUM_LIT> ) ; } if ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS ) { OutStreamer -> EmitIntValue ( R_0286CC_SPI_PS_INPUT_ENA , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( MFI -> getP<ISA_LIT>nputEnable ( ) , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( R_0286D0_SPI_PS_INPUT_ADDR , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( MFI -> getP<ISA_LIT>nputAddr ( ) , <NUM_LIT> ) ; Rsrc2Val |= S_00B02C_EXTRA_LDS_<ISA_LIT>ZE ( CurrentProgramInfo . LDSBlocks ) ; } if ( Rsrc2Val ) { OutStreamer -> EmitIntValue ( RsrcReg + <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( Rsrc2Val , <NUM_LIT> ) ; } } OutStreamer -> EmitIntValue ( R_SPILLED_SGPRS , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( MFI -> getNumSpilledSGPRs ( ) , <NUM_LIT> ) ;

OutStreamer -> EmitIntValue ( R_SPILLED_VGPRS , <NUM_LIT> ) ;


<s> bool cz = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t simm32 = SignExtend64 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; DecodeStatus status ; if ( cz ) { status = DecodeI64RegisterClass ( MI , sz , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } else { MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; } if ( cy ) { status = DecodeI64RegisterClass ( MI , sy , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } else { MI . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( sy ) ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasDistinctOps ( false ) , HasLoadStoreOnCond ( false ) , HasHighWord ( false ) , HasFPExtension ( false ) , HasPopulationCount ( false ) , HasMessageSecurityAssist4 ( false ) , HasFastSerialization ( false ) , HasInterlockedAccess1 ( false ) , HasMiscellaneousExtensions ( false ) , HasExecutionHint ( false ) , HasLoadAndTrap ( false ) , HasTransactionalExecution ( false ) , HasProcessorAssist ( false ) , HasDFPZonedConversion ( false ) , HasVector ( false ) , HasLoadStoreOnCond2 ( false ) , HasLoadAndZeroRightmostByte ( false ) , HasMessageSecurityAssist5 ( false ) , HasDFPPackedConversion ( false ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {


<s> if ( II -> getOperand ( i ) . isReg ( ) && ( II -> getOperand ( i ) . isUse ( ) || II -> getOperand ( i ) . isDef ( ) ) ) { MachineBasicBlock :: iterator localII = II ; ++ localII ; unsigned Reg = II -> getOperand ( i ) . getReg ( ) ; for ( MachineBasicBlock :: iterator localBegin = localII ; localBegin != end ; ++ localBegin ) { if ( localBegin == skip ) continue ; if ( localBegin -> modifiesRegister ( Reg , TRI ) || localBegin -> readsRegister ( Reg , TRI ) ) return false ; } } }


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( TARGET_64BIT ) { if ( cfun_save_high_fprs_p ) { next_offset = cfun_frame_layout . f8_offset ; for ( i = FPR8_REGNUM ; i <= FPR15_REGNUM ; i ++ ) { if ( cfun_fpr_save_p ( i ) ) { restore_fpr ( frame_pointer , offset + next_offset , i ) ; cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( DFmode , i ) , cfa_restores ) ; next_offset += <NUM_LIT> ; } } } } else { next_offset = cfun_frame_layout . f4_offset ; for ( i = FPR4_REGNUM ; i <= FPR4_REGNUM + <NUM_LIT> ; i ++ ) { if ( cfun_fpr_save_p ( i ) ) { restore_fpr ( frame_pointer , offset + next_offset , i ) ; cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( DFmode , i ) , cfa_restores ) ; next_offset += <NUM_LIT> ; } else if ( ! TARGET_PACKED_STACK ) next_offset += <NUM_LIT> ; } } if ( cfun_frame_layout . first_restore_gpr != - <NUM_LIT> ) { rtx insn , addr ; int i ; for ( i = cfun_frame_layout . first_restore_gpr ; i <= cfun_frame_layout . last_restore_gpr ; i ++ ) { if ( global_not_special_regno_p ( i ) ) { addr = plus_constant ( Pmode , frame_pointer , offset + cfun_frame_layout . gprs_offset + ( i - cfun_frame_layout . first_save_gpr_slot ) * UNITS_PER_LONG ) ; addr = gen_rtx_MEM ( Pmode , addr ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; emit_move_insn ( addr , gen_rtx_REG ( Pmode , i ) ) ; } else cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( Pmode , i ) , cfa_restores ) ; } if ( ! sibcall && cfun_gpr_save_slot ( RETURN_REGNUM ) == SAVE_SLOT_STACK && s390_tune <= PROCESSOR_2097_Z10 ) { int return_regnum = find_unused_clobbered_reg ( ) ;

if ( ! return_regnum || ( TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION && ! TARGET_CPU_Z10 && return_regnum == INDIRECT_BRANCH_THUNK_REGNUM ) ) {


<s> } LLVMContext & Ctx = M . getContext ( ) ; auto Ty = F -> getFunctionType ( ) ; Function * Fn = Function :: Create ( Ty , GlobalValue :: WeakAnyLinkage , N , & M ) ; Fn -> setDoesNotReturn ( ) ; Fn -> setVisibility ( GlobalValue :: DefaultVisibility ) ; Fn -> setCallingConv ( CallingConv :: C ) ; Fn -> setSection ( <STR_LIT> ) ; Fn -> setIsMaterializable ( true ) ; AttrBuilder B ; B . addAttribute ( llvm :: Attribute :: NoUnwind ) ; B . addAttribute ( llvm :: Attribute :: Naked ) ;

Fn -> addAttributes ( llvm :: AttributeList :: FunctionIndex , B ) ;


<s> MachineFunction & MF = * B . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; LivePhysRegs LPR ( HRI ) ; LPR . addLiveIns ( B ) ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; for ( auto R = B . begin ( ) ; R != It ; ++ R ) { Clobbers . clear ( ) ; LPR . stepForward ( * R , Clobbers ) ; for ( auto & C : Clobbers ) if ( C . second -> isReg ( ) && C . second -> isDead ( ) ) LPR . removeReg ( C . first ) ; } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcLo = HRI . getSubReg ( SrcR , <STR_LIT> ) ; unsigned SrcHi = HRI . getSubReg ( SrcR , <STR_LIT> ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool Is128B = HST . useHVXDblOps ( ) ; const auto & RC = ! Is128B ? <STR_LIT> : <STR_LIT> ; unsigned Size = HRI . getSpillSize ( RC ) ; unsigned NeedAlign = HRI . getSpillAlignment ( RC ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc ; if ( LPR . contains ( SrcLo ) ) { if ( NeedAlign <= HasAlign ) StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcLo , getKillRegState ( IsKill ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; } if ( LPR . contains ( SrcHi ) ) { if ( NeedAlign <= MinAlign ( HasAlign , Size ) ) StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( Size ) . addReg ( SrcHi , getKillRegState ( IsKill ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> return create<ISA_LIT>ELFObjectWriter ( OSABI , Is64Bit ) ;


<s> auto F = DefM . find ( RR ) ; if ( F == DefM . end ( ) ) continue ; DefStack & DS = F -> second ; if ( Kind == NodeAttrs :: Use ) linkRefUp < UseNode * > ( SA , RA , DS ) ; else if ( Kind == NodeAttrs :: Def ) linkRefUp < DefNode * > ( SA , RA , DS ) ; else llvm_unreachable ( <STR_LIT> ) ;


<s>
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
LiveRegs
)
dbgs
(
)
<<
printVRegOrUnit
(
Reg
,
DAG
->
getTRI
(
)
)
<<
' '
;
dbgs
(
)
<<
'\n'
;
dbgs
(
)
<<
<STR_LIT>
<<
VregCurrentUsage
<<
'\n'
;
dbgs
(
)
<<
<STR_LIT>
<<
SregCurrentUsage
<<
'\n'
;
)
;
Cand
.
Block
=
nullptr
;
for
(
std
::
vector
<
<ISA_LIT>ScheduleBlock
*
>
::
iterator
I
=
ReadyBlocks
.
begin
(
)
,
E
=
ReadyBlocks
.
end
(
)
;
I
!=
E
;
++
I
)
{
<ISA_LIT>BlockSchedCandidate
TryCand
;
TryCand
.
Block
=
*
I
;
TryCand
.
IsHighLatency
=
TryCand
.
Block
->
isHighLatencyBlock
(
)
;
TryCand
.
VGPRUsageDiff
=
checkRegUsageImpact
(
TryCand
.
Block
->
getInRegs
(
)
,
TryCand
.
Block
->
getOutRegs
(
)
)
[
DAG
->
getVGPRSetID
(
)
]
;
TryCand
.
NumSuccessors
=
TryCand
.
Block
->
getSuccs
(
)
.
size
(
)
;
TryCand
.
NumHighLatencySuccessors
=
TryCand
.
Block
->
getNumHighLatencySuccessors
(
)
;
TryCand
.
LastPosHighLatParentScheduled
=
(
unsigned
int
)
std
::
max
<
int
>
(
<NUM_LIT>
,
LastPosHighLatencyParentScheduled
[
TryCand
.
Block
->
getID
(
)
]
LastPosWaitedHighLatency
)
;
TryCand
.
Height
=
TryCand
.
Block
->
Height
;
if
(
VregCurrentUsage
>
<NUM_LIT>
||
Variant
!=
<STR_LIT>
)
{
if
(
!
tryCandidateRegUsage
(
Cand
,
TryCand
)
&&
Variant
!=
<STR_LIT>
)
tryCandidateLatency
(
Cand
,
TryCand
)
;
}
else
{
if
(
!
tryCandidateLatency
(
Cand
,
TryCand
)
)
tryCandidateRegUsage
(
Cand
,
TryCand
)
;
}
if
(
TryCand
.
Reason
!=
NoCand
)
{
Cand
.
setBest
(
TryCand
)
;
Best
=
I
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
Cand
.
Block
->
getID
(
)
<<
' '
<<
getReasonStr
(
Cand
.
Reason
)
<<
'\n'
)
;
}
}

DEBUG ( dbgs ( ) << <STR_LIT> << Cand . Block -> getID ( ) << '\n' ;


<s> PerformSDIVReplace = false ; InsertNOPLoad = false ; FixFSMULD = false ; ReplaceFMULS = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ;


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) { CPUName = <STR_LIT> ; }

ParseSubtargetFeatures ( CPUName , FS ) ;


<s> std :: set < unsigned > SUColors ; if ( CurrentColoring [ SU -> NodeNum ] <= ( int ) DAGSize ) continue ; if ( SU -> Preds . size ( ) > <NUM_LIT> && ! DAG -> IsLowLatencySU [ SU -> NodeNum ] ) continue ; for ( SDep & SuccDep : SU -> Succs ) { SUnit * Succ = SuccDep . getSUnit ( ) ; if ( SuccDep . isWeak ( ) || Succ -> NodeNum >= DAGSize ) continue ; SUColors . insert ( CurrentColoring [ Succ -> NodeNum ] ) ;


<s> __b = ( __vector unsigned char ) vec_splats ( __m2 ) ; __c = vec_subs ( __a , __b ) ; return ( __m64 ) ( ( __vector long long ) __c ) [ <NUM_LIT> ] ;


<s> bool <ISA_LIT>InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx0 , unsigned & SrcOpIdx1 ) const { const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( ! MCID . isCommutable ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return false ; if ( ! MI . getOperand ( Src0Idx ) . isReg ( ) ) return false ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return false ; MachineOperand & Src1 = MI . getOperand ( Src1Idx ) ; if ( Src1 . isImm ( ) ) { if ( ! isVOP2 ( MI . getOpcode ( ) ) && ! isVOP3 ( MI . getOpcode ( ) ) ) return false ; } else if ( Src1 . isReg ( ) ) { if ( hasModifiersSet ( MI , <STR_LIT> :: src0_modifiers ) || hasModifiersSet ( MI , <STR_LIT> :: src1_modifiers ) ) return false ; } else return false ; return fixCommutedOpIndices ( SrcOpIdx0 , SrcOpIdx1 , Src0Idx , Src1Idx ) ;


<s> static const unsigned NEONDRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; MO . setReg ( NEONDRegs [ Offset + R * Stride ] ) ; if ( MO . isUse ( ) ) { TII -> copyRegToReg ( MBB , MBBI , MO . getReg ( ) , VirtReg , <STR_LIT> , <STR_LIT> ) ; if ( MO . isKill ( ) ) { MachineInstr * CopyMI = prior ( MBBI ) ; CopyMI -> findRegisterUseOperand ( VirtReg ) -> setIsKill ( ) ; } MO . setIsKill ( ) ; } else if ( MO . isDef ( ) && ! MO . isDead ( ) ) { TII -> copyRegToReg ( MBB , NextI , VirtReg , MO . getReg ( ) , <STR_LIT> , <STR_LIT> ) ; }


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return STI . hasTinyEncoding ( ) ? CSR_NormalTiny_RegMask : CSR_Normal_RegMask ;


<s> if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < <NUM_LIT> && INTVAL ( index ) > - <NUM_LIT> && ( INTVAL ( index ) & <NUM_LIT> ) == <NUM_LIT> ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) return <NUM_LIT> ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; return val > - <NUM_LIT> && val < <NUM_LIT> && ( val & <NUM_LIT> ) == <NUM_LIT> ; } else return <NUM_LIT> ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , <NUM_LIT> ) ; rtx xiop1 = XEXP ( index , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , <NUM_LIT> ) ;

return ( arm_address_register_rtx_p ( XEXP ( index , <NUM_LIT> ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > <NUM_LIT> && INTVAL ( op ) <= <NUM_LIT> ) ;


<s> static bool isEndChunk ( uint64_t Chunk ) {

if ( Chunk == <NUM_LIT> || Chunk == UINT64_MAX ) return false ;


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Form = TID . TSFlags & <STR_LIT> ; bool IsPrePost = ( TID . TSFlags & <STR_LIT> ) != <NUM_LIT> ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { emitWordLE ( Binary ) ; return ; } Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; bool Skipped = false ; if ( IsPrePost && Form == <STR_LIT> ) { ++ OpIdx ; Skipped = true ; } if ( ImplicitRd ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM2Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM2Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( AM2Opc ) ) Binary |= <STR_LIT> ( AM2Opc ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO2 . getReg ( ) ) ) ; Binary |= get<ISA_LIT>RegisterNumbering ( MO2 . getReg ( ) ) ; if ( unsigned ShImm = <STR_LIT> ( AM2Opc ) ) {

Binary |= getShiftOp ( AM2Opc ) << <STR_LIT> ;


<s> const MCExpr * <ISA_LIT>TargetLowering :: LowerCustomJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB , unsigned uid , MCContext & Ctx ) const { assert ( isPositionIndependent ( ) && Subtarget . isPICStyleGOT ( ) ) ;

return MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , MCSymbolRefExpr :: VK_GOTOFF , Ctx ) ;


<s> bool <ISA_LIT>MCInstrInfo :: isPrefix ( MCInstrInfo const & MCII , MCInst const & MCI ) {

return <STR_LIT> == <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI ) ;


<s> void addm6ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> void <ISA_LIT>AsmPrinter :: printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; O << <STR_LIT> ( ( <STR_LIT> ) MO . getImm ( ) ) ;


<s> machine_mode cmode ; int first_val_regnum = MMIX_OUTGOING_RETURN_VALUE_REGNUM ; rtx vec [ MMIX_MAX_REGS_FOR_VALUE ] ; int i ; int nregs ; if ( ! outgoing ) return gen_rtx_REG ( mode , MMIX_RETURN_VALUE_REGNUM ) ; if ( TARGET_ABI_GNU || GET_MODE_BITSIZE ( mode ) <= BITS_PER_WORD ) return gen_rtx_REG ( mode , MMIX_OUTGOING_RETURN_VALUE_REGNUM ) ; if ( COMPLEX_MODE_P ( mode ) ) cmode = TYPE_MODE ( TREE_TYPE ( valtype ) ) ;


<s> if ( ST -> isTgSplitEnabled ( ) ) return false ; if ( MI . memoperands_empty ( ) ) return true ;

for ( const MachineMemOperand * Memop : MI . memoperands ( ) ) {


<s> uint32_t Arg = DV -> getArg ( ) ; if ( Arg ) { visitTypeEntry ( DV -> getType ( ) ) ; FuncArgNames [ Arg ] = DV -> getName ( ) ; } } } uint32_t ProtoTypeId ; visitSubroutineType ( SP -> getType ( ) , true , FuncArgNames , ProtoTypeId ) ; auto FuncTypeEntry = std :: make_unique < BTFTypeFunc > ( SP -> getName ( ) , ProtoTypeId ) ; uint32_t FuncTypeId = addType ( std :: move ( FuncTypeEntry ) ) ; for ( const auto & TypeEntry : TypeEntries ) TypeEntry -> completeType ( * this ) ; MCSymbol * FuncLabel = Asm -> getFunctionBegin ( ) ; BTFFuncInfo FuncInfo ; FuncInfo . Label = FuncLabel ; FuncInfo . TypeId = FuncTypeId ; if ( FuncLabel -> isInSection ( ) ) { MCSection & Section = FuncLabel -> getSection ( ) ; const MCSectionELF * SectionELF = dyn_cast < MCSectionELF > ( & Section ) ; assert ( SectionELF && <STR_LIT> ) ;

SecNameOff = addString ( SectionELF -> getSectionName ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm ( ) ) { O << '#' << Op . getImm ( ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ;


<s> if ( VT . is256BitVector ( ) && ! Subtarget -> hasInt256 ( ) ) return Lower256IntArith ( Op , DAG ) ; SDValue A = Op . getOperand ( <NUM_LIT> ) ; SDValue B = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { assert ( Subtarget -> hasSSE2 ( ) && ! Subtarget -> hasSSE41 ( ) && <STR_LIT> ) ; static const int UnpackMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Aodds = DAG . getVectorShuffle ( VT , dl , A , A , UnpackMask ) ; SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A , B ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Aodds , Bodds ) ; Evens = DAG . getNode ( <STR_LIT> , dl , VT , Evens ) ; Odds = DAG . getNode ( <STR_LIT> , dl , VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Ahi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , A , <NUM_LIT> , DAG ) ; SDValue Bhi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , B , <NUM_LIT> , DAG ) ; EVT MulVT = ( VT == <STR_LIT> ) ? <STR_LIT> : ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; A = DAG . getNode ( <STR_LIT> , dl , MulVT , A ) ; B = DAG . getNode ( <STR_LIT> , dl , MulVT , B ) ; Ahi = DAG . getNode ( <STR_LIT> , dl , MulVT , Ahi ) ;

Bhi = DAG . getNode ( <STR_LIT> , dl , MulVT , Bhi ) ;


<s> } output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_INTERWORK || arm_arch4t ) output_asm_insn ( <STR_LIT> , operands ) ;

else output_asm_insn ( <STR_LIT> , operands ) ;


<s> static bool isPredicateSetter ( unsigned Opcode ) {


<s> <ISA_LIT>InsertWaitcnts ( ) : MachineFunctionPass ( ID ) { ( void ) ForceExpCounter ; ( void ) ForceLgkmCounter ;


<s> return ( __m512d ) __builtin_ia32_cvtuqq2pd512_mask ( ( __v8di ) __A , ( __v8df ) _mm512_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> break ; case CODE_FOR_doloop_end_internal : insn_extract ( insn ) ; loop = & loops [ INTVAL ( recog_data . operand [ <NUM_LIT> ] ) ] ; end = ( struct mep_doloop_end * ) alloca ( sizeof ( struct mep_doloop_end ) ) ; end -> insn = insn ; end -> fallthrough = next_real_insn ( insn ) ; end -> counter = recog_data . operand [ <NUM_LIT> ] ; end -> label = recog_data . operand [ <NUM_LIT> ] ; end -> scratch = recog_data . operand [ <NUM_LIT> ] ; if ( loop -> end != <NUM_LIT> && simplejump_p ( end -> fallthrough ) ) { end -> next = loop -> end -> next ; loop -> end -> next = end ; } else { end -> next = loop -> end ; loop -> end = end ; } break ; } for ( loop = loops ; loop < loops + cfun -> machine -> doloop_tags ; loop ++ ) if ( mep_repeat_loop_p ( loop ) ) { rtx_code_label * repeat_label ; rtx label_ref ; repeat_label = gen_label_rtx ( ) ; label_ref = gen_rtx_LABEL_REF ( VOIDmode , repeat_label ) ; emit_insn_before ( gen_repeat ( loop -> begin -> counter , label_ref ) , loop -> begin -> insn ) ; delete_insn ( loop -> begin -> insn ) ; mep_insert_repeat_label_last ( loop -> end -> insn , repeat_label , false , loop -> end -> next != <NUM_LIT> ) ; emit_insn_before ( gen_repeat_end ( ) , loop -> end -> insn ) ; delete_insn ( loop -> end -> insn ) ; for ( end = loop -> end -> next ; end != <NUM_LIT> ; end = end -> next ) { emit_jump_insn_before ( gen_jump ( repeat_label ) , end -> insn ) ; delete_insn ( end -> insn ) ;


<s> if ( VCCRValue && Iter -> getOpcode ( ) == <STR_LIT> && Iter -> findRegisterUseOperandIdx ( VCCRValue ) != - <NUM_LIT> ) { if ( ! MoveVPNOTBeforeFirstUser ( MBB , Iter , VCCRValue ) ) continue ; OppositeVCCRValue = Dst ; ++ Iter ; break ; } VCCRValue = Dst ; } if ( Iter == End ) break ; assert ( VCCRValue && OppositeVCCRValue && <STR_LIT> <STR_LIT> ) ; assert ( VCCRValue != OppositeVCCRValue && <STR_LIT> ) ; Register LastVPNOTResult = OppositeVCCRValue ; for ( ; Iter != End ; ++ Iter ) { bool IsInteresting = false ; if ( MachineOperand * MO = Iter -> findRegisterUseOperand ( VCCRValue ) ) { IsInteresting = true ; if ( Iter -> getOpcode ( ) == <STR_LIT> ) { Register Result = Iter -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MRI -> replaceRegWith ( Result , LastVPNOTResult ) ; DeadInstructions . push_back ( & * Iter ) ; Modified = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Result ) << <STR_LIT> << printReg ( LastVPNOTResult ) << <STR_LIT> ) ; } else { MachineInstr & VPNOT = ReplaceRegisterUseWithVPNOT ( MBB , * Iter , * MO , LastVPNOTResult ) ; Modified = true ; LastVPNOTResult = VPNOT . getOperand ( <NUM_LIT> ) . getReg ( ) ; std :: swap ( VCCRValue , OppositeVCCRValue ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( VCCRValue ) << <STR_LIT> << printReg ( LastVPNOTResult ) << <STR_LIT> << * Iter ) ; } } else { if ( MachineOperand * MO = Iter -> findRegisterUseOperand ( OppositeVCCRValue ) ) { IsInteresting = true ; if ( LastVPNOTResult != OppositeVCCRValue ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( OppositeVCCRValue ) << <STR_LIT> << printReg ( LastVPNOTResult ) << <STR_LIT> ; Iter -> dump ( ) ) ; MO -> setReg ( LastVPNOTResult ) ; Modified = true ; } MO -> setIsKill ( false ) ; } if ( Iter -> getOpcode ( ) == <STR_LIT> && getVPTInstrPredicate ( * Iter ) == <STR_LIT> ) { Register VPNOTOperand = Iter -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( VPNOTOperand == LastVPNOTResult || VPNOTOperand == OppositeVCCRValue ) { IsInteresting = true ; std :: swap ( VCCRValue , OppositeVCCRValue ) ; LastVPNOTResult = Iter -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } }


<s> return ( gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) || gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) ) ;


<s> CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; rtx rv = NULL_RTX ; fprintf ( stderr , <STR_LIT> , ca -> parm_num , mode_name [ arg . mode ] , arg . named ) ; debug_tree ( arg . type ) ; if ( arg . end_marker_p ( ) ) return GEN_INT ( <NUM_LIT> ) ; if ( ca -> force_mem || ! arg . named ) { fprintf ( stderr , <STR_LIT> , ca -> force_mem , arg . named ) ; return NULL_RTX ; } if ( arg . type && INTEGRAL_TYPE_P ( arg . type ) && POINTER_TYPE_P ( arg . type ) ) return NULL_RTX ; if ( arg . aggregate_type_p ( ) ) return NULL_RTX ; switch ( ca -> parm_num ) { case <NUM_LIT> : if ( GET_MODE_SIZE ( arg . mode ) == <NUM_LIT> || GET_MODE_SIZE ( arg . mode ) == <NUM_LIT> ) rv = gen_rtx_REG ( arg . mode , TARGET_A16 ? R1_REGNO : R0_REGNO ) ; break ; case <NUM_LIT> : if ( TARGET_A16 && GET_MODE_SIZE ( arg . mode ) == <NUM_LIT> ) rv = gen_rtx_REG ( arg . mode , R2_REGNO ) ; break ; }


<s> const unsigned MaxWorkGroupsPerCu = getMaxWorkGroupsPerCU ( MaxWorkGroupSize ) ; if ( ! MaxWorkGroupsPerCu ) return <NUM_LIT> ; const unsigned WaveSize = getWavefrontSize ( ) ; unsigned NumGroups = getLocalMemorySize ( ) / ( Bytes ? Bytes : <NUM_LIT> ) ; if ( NumGroups == <NUM_LIT> ) return <NUM_LIT> ; NumGroups = std :: min ( MaxWorkGroupsPerCu , NumGroups ) ; const unsigned MaxGroupNumWaves = ( MaxWorkGroupSize + WaveSize - <NUM_LIT> ) / WaveSize ; unsigned MaxWaves = NumGroups * MaxGroupNumWaves ; MaxWaves = std :: min ( MaxWaves , getMaxWavesPerEU ( ) ) ; assert ( MaxWaves > <NUM_LIT> && MaxWaves <= getMaxWavesPerEU ( ) && <STR_LIT> ) ; return MaxWaves ;


<s> if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & <NUM_LIT> ) != <NUM_LIT> ) return false ;

extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ;


<s> void addImm0_65535Operands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) {


<s> case 'r' : return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; }


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MachineFunction & MF , <ISA_LIT>AsmPrinter & AP ) : Ctx ( MF . getContext ( ) ) , MF ( MF ) , TM ( MF . getTarget ( ) ) , MAI ( * TM . getMCAsmInfo ( ) ) , AsmPrinter ( AP ) {


<s> Register <ISA_LIT>FunctionInfo :: getCapGlobalBaseReg ( MachineFunction & MF ) { if ( CapGlobalBaseReg ) return CapGlobalBaseReg ; const TargetRegisterClass * RC = & <STR_LIT> ;

return CapGlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> if ( GR . isScalarOfType ( CmpOperand , <STR_LIT> ) ) CmpOpc = getPtrCmpOpcode ( Pred ) ; else if ( GR . isScalarOrVectorOfType ( CmpOperand , <STR_LIT> ) ) CmpOpc = getBoolCmpOpcode ( Pred ) ;


<s> virtual const Dcpu16InstrInfo * getInstrInfo ( ) const { return & InstrInfo ;


<s> static inline std :: string createGlobalValueName ( const Module & M , const std :: string & Propose ) {


<s> SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { SDValue SrcReg ; if ( NumVecs == <NUM_LIT> ) { SrcReg = N -> getOperand ( Vec0Idx ) ; } else if ( is64BitVector ) { SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) SrcReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } } else { SDValue Q0 = N -> getOperand ( Vec0Idx ) ; SDValue Q1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SrcReg = SDValue ( createQRegPairNode ( <STR_LIT> , Q0 , Q1 ) , <NUM_LIT> ) ; } unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( NumVecs <= <NUM_LIT> && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( Inc ) ;

else if ( NumVecs > <NUM_LIT> && ! isVSTfixed ( Opc ) ) Ops . push_back ( Reg0 ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; allocateHSAUserSGPRs ( CCInfo , B , MF , * TRI , * Info ) ; unsigned i = <NUM_LIT> ; const Align KernArgBaseAlign ( <NUM_LIT> ) ; const unsigned BaseOffset = Subtarget -> getExplicitKernelArgOffset ( F ) ; uint64_t ExplicitArgOffset = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { Type * ArgTy = Arg . getType ( ) ; unsigned AllocSize = DL . getTypeAllocSize ( ArgTy ) ; if ( AllocSize == <NUM_LIT> ) continue ; Align ABIAlign = DL . getABITypeAlign ( ArgTy ) ; uint64_t ArgOffset = alignTo ( ExplicitArgOffset , ABIAlign ) + BaseOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , ABIAlign ) + AllocSize ; if ( Arg . use_empty ( ) ) { ++ i ;


<s> return ( __m128i ) __builtin_ia32_cvttpd2qq128_mask ( ( __v2df ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return X ; } ; assert ( VecLen > <NUM_LIT> ) ; for ( unsigned I = VecLen ; I >= <NUM_LIT> ; I >>= <NUM_LIT> ) { unsigned X = XorPow2 ( LocalMask , I ) ; if ( ! isPowerOf2_32 ( X ) ) return OpRef :: fail ( ) ; for ( int J = I ; J < VecLen ; J += I ) { if ( XorPow2 ( LocalMask . slice ( J , I ) , I ) != X ) return OpRef :: fail ( ) ; } Perm [ Log2_32 ( X ) ] = Log2_32 ( I ) - <NUM_LIT> ; } using CycleType = SmallVector < unsigned , <NUM_LIT> > ; std :: set < CycleType > Cycles ; std :: set < unsigned > All ; for ( unsigned I : Perm ) All . insert ( I ) ; auto canonicalize = [ LogLen ] ( const CycleType & C ) -> CycleType { unsigned LogPos , N = C . size ( ) ; for ( LogPos = <NUM_LIT> ; LogPos != N ; ++ LogPos ) if ( C [ LogPos ] == LogLen - <NUM_LIT> ) break ; if ( LogPos == N ) return C ; CycleType NewC ( C . begin ( ) + LogPos , C . end ( ) ) ; NewC . append ( C . begin ( ) , C . begin ( ) + LogPos ) ; return NewC ; } ; auto pfs = [ ] ( const std :: set < CycleType > & Cs , unsigned Len ) { if ( Cs . size ( ) != <NUM_LIT> ) return <NUM_LIT> ; const CycleType & C = * Cs . begin ( ) ; if ( C [ <NUM_LIT> ] != Len - <NUM_LIT> ) return <NUM_LIT> ; int D = Len - C . size ( ) ; if ( D != <NUM_LIT> && D != <NUM_LIT> ) return <NUM_LIT> ; bool IsDeal = true , IsShuff = true ; for ( unsigned I = <NUM_LIT> ; I != Len - D ; ++ I ) { if ( C [ I ] != Len - <NUM_LIT> - I ) IsDeal = false ; if ( C [ I ] != I - ( <NUM_LIT> - D ) ) IsShuff = false ; } assert ( ! ( IsDeal || IsShuff ) || IsDeal != IsShuff ) ; static unsigned Deals [ ] = { <STR_LIT> , <STR_LIT> } ; static unsigned Shufs [ ] = { <STR_LIT> , <STR_LIT> } ; return IsDeal ? Deals [ D ] : ( IsShuff ? Shufs [ D ] : <NUM_LIT> ) ; } ; while ( ! All . empty ( ) ) { unsigned A = * All . begin ( ) ; All . erase ( A ) ; CycleType C ; C . push_back ( A ) ;

for ( unsigned B = Perm [ A ] ; B != A ; B = Perm [ B ] ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI -> hasOrderedMemoryRef ( ) ) { ++ MBBI ; break ; } if ( ! getLdStOffsetOp ( MI ) . isImm ( ) ) { ++ MBBI ; break ; } if ( TII -> isLdStPairSuppressed ( MI ) ) { ++ MBBI ; break ; } LdStPairFlags Flags ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , Flags , ScanLimit ) ; if ( Paired != E ) { ++ NumPairCreated ; if ( isUnscaledLdSt ( MI ) ) ++ NumUnscaledPairCreated ; MBBI = mergePairedInsns ( MBBI , Paired , Flags ) ; Modified = true ; break ; } ++ MBBI ; break ; } } } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = MBBI ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : ++ MBBI ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return ( int16x4_t ) __builtin_neon_vaddhnv4si ( __a , __b ) ;


<s> const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_IMPLICIT_DEF : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ;

if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) break ;


<s> bool IsTarget = <ISA_LIT>MCInstrInfo :: isAccumulator ( MCII , I ) && I . getOperand ( <NUM_LIT> ) . isReg ( ) ; if ( ! IsTarget ) continue ; unsigned int R = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; TmpDefsIterator It = TmpDefs . find ( R ) ; if ( It != TmpDefs . end ( ) ) {

reportError ( <STR_LIT> + Twine ( RI . getName ( R ) ) + <STR_LIT> + <STR_LIT> ) ;


<s> const TargetRegisterClass * vecClass = MRI -> getRegClass ( regnum ) ; const TargetRegisterClass * scalarClass = getScalarRegClass ( vecClass ) ; SmallVector < unsigned , <NUM_LIT> > temp ; for ( unsigned i = <NUM_LIT> , e = get<ISA_LIT>VectorSize ( vecClass ) ; i != e ; ++ i ) temp . push_back ( MRI -> createVirtualRegister ( scalarClass ) ) ; VectorToScalarMap [ regnum ] = temp ; }


<s> uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) ) return false ; Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = <STR_LIT> ; return true ; }


<s> rtx cfa_relative_addr = gen_rtx_PLUS ( Pmode , cfa , gen_int_si ( cfa_offset ) ) ; rtx cfa_relative_mem = gen_frame_mem ( Pmode , cfa_relative_addr ) ; rtx real = gen_rtx_SET ( VOIDmode , cfa_relative_mem , reg_note ) ; add_reg_note ( mov , REG_CFA_OFFSET , real ) ; return emit_insn ( mov ) ;


<s> StringRef getPassName ( ) const override {


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> ) return InsertBitToMaskVector ( Op , DAG ) ; SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( N2 ) ) return SDValue ( ) ; auto * N2C = cast < ConstantSDNode > ( N2 ) ; unsigned IdxVal = N2C -> getZExtValue ( ) ; if ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) { if ( VT . is256BitVector ( ) && IdxVal == <NUM_LIT> ) { if ( ( Subtarget -> hasAVX ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) || ( Subtarget -> hasAVX2 ( ) && EltVT == <STR_LIT> ) ) { SDValue N1Vec = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; N2 = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , N2 ) ; } } SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; unsigned IdxIn128 = IdxVal - ( IdxVal / NumEltsIn128 ) * NumEltsIn128 ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , dl , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) { if ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Opc ; if ( VT == <STR_LIT> ) {


<s> drap_ok = drap_ok && drap_align >= align_reqested ; sp_ok = sp_ok && sp_align >= align_reqested ; } if ( m -> use_fast_prologue_epilogue ) { if ( hfp_ok ) { base_reg = hard_frame_pointer_rtx ; base_offset = m -> fs . fp_offset - cfa_offset ; } else if ( drap_ok ) { base_reg = crtl -> drap_reg ; base_offset = <NUM_LIT> - cfa_offset ; } else if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; } } else { HOST_WIDE_INT toffset ; int len = <NUM_LIT> , tlen ; if ( sp_ok ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( drap_ok ) { toffset = <NUM_LIT> - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( hfp_ok ) { toffset = m -> fs . fp_offset - cfa_offset ; tlen = choose_baseaddr_len ( HARD_FRAME_POINTER_REGNUM , toffset ) ; if ( tlen <= len ) { base_reg = hard_frame_pointer_rtx ; base_offset = toffset ;


return CallConv != CallingConv :: Fast ;


<s> EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; return LT . first ; }

return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , I ) ;


<s> static inline bool s390_preserve_gpr_arg_p ( int regno ) {

return s390_preserve_gpr_arg_in_range_p ( regno , regno ) ;


<s> unsigned Opcode1 = Op1 . getOpcode ( ) ; if ( ( Opcode1 == <STR_LIT> || Opcode1 == <STR_LIT> || Opcode1 == <STR_LIT> ) && Op1 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= TruncSizeInBits ) return true ; SDValue BC0 = peekThroughOneUseBitcasts ( Op0 ) ; SDValue BC1 = peekThroughOneUseBitcasts ( Op1 ) ; return <STR_LIT> ( BC0 . getNode ( ) ) || <STR_LIT> ( BC1 . getNode ( ) ) ; } ; auto TruncateArithmetic = [ & ] ( SDValue N0 , SDValue N1 ) { SDValue Trunc0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; SDValue Trunc1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; return DAG . getNode ( Opcode , DL , VT , Trunc0 , Trunc1 ) ; } ; if ( ! N -> isOnlyUserOf ( Src . getNode ( ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = Src . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Src . getOperand ( <NUM_LIT> ) ; if ( TLI . isOperationLegalOrPromote ( Opcode , VT ) && IsRepeatedOpOrFreeTruncation ( Op0 , Op1 ) ) return TruncateArithmetic ( Op0 , Op1 ) ; break ; } case <STR_LIT> : if ( SrcVT . getScalarType ( ) == <STR_LIT> && TLI . isOperationLegal ( Opcode , VT ) && ! Subtarget . hasDQI ( ) ) return TruncateArithmetic ( Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue Op0 = Src . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Src . getOperand ( <NUM_LIT> ) ; if ( TLI . isOperationLegal ( Opcode , VT ) && IsRepeatedOpOrFreeTruncation ( Op0 , Op1 ) ) return TruncateArithmetic ( Op0 , Op1 ) ; break ;


<s> Zero = TBB ; break ; case <STR_LIT> : Nonzero = TBB ; Zero = FBB ; break ; default : return Optional < BlockBRNZ > ( ) ; } MachineBasicBlock :: const_reverse_instr_iterator MI = MBB . instr_rbegin ( ) ; while ( MI != MBB . instr_rend ( ) && MI -> isUnconditionalBranch ( ) ) ++ MI ; if ( MI == MBB . instr_rend ( ) || ! MI -> isConditionalBranch ( ) ) return Optional < BlockBRNZ > ( ) ; BlockBRNZ Desc ; Desc . Zero = Zero ; Desc . Nonzero = Nonzero ; while ( ++ MI != MBB . instr_rend ( ) ) { if ( MI -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & op = MI -> getOperand ( <NUM_LIT> ) ; if ( op . getReg ( ) != MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return Optional < BlockBRNZ > ( ) ; Desc . IsKill = op . isKill ( ) ; Desc . Regs . push_back ( op . getReg ( ) ) ; break ; } if ( MI -> modifiesRegister ( <STR_LIT> , TRI ) ) return Optional < BlockBRNZ > ( ) ; } if ( Desc . Regs . size ( ) != <NUM_LIT> ) { return Optional < BlockBRNZ > ( ) ; } const Register & Reg0 = Desc . Regs [ <NUM_LIT> ] ; while ( ++ MI != MBB . instr_rend ( ) ) { if ( MI -> isPHI ( ) ) { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg0 ) { unsigned NumOperands = MI -> getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOperands ; I += <NUM_LIT> ) { Desc . Regs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ; } } return Desc ; } if ( MI -> modifiesRegister ( Reg0 , TRI ) ) return Optional < BlockBRNZ > ( ) ; if ( MI -> readsRegister ( Reg0 , TRI ) ) Desc . IsKill = false ; }


<s> BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ; } } } } if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return PerformORCombine_i1 ( N , DCI , Subtarget ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) ) { if ( SDValue Res = PerformORCombineToBFI ( N , DCI , Subtarget ) ) return Res ; }

if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ;


<s> unsigned getMaxWavesPerCU ( unsigned FlatWorkGroupSize ) const {

return <STR_LIT> :: getMaxWavesPerCU ( getFeatureBits ( ) , FlatWorkGroupSize ) ;


<s> const Align NewAlignment = max ( MaybeAlign ( Info . AI -> getAlign ( ) ) , kTagGranuleSize ) ; Info . AI -> setAlignment ( NewAlignment ) ; uint64_t Size = Info . AI -> getAllocationSizeInBits ( * DL ) . getValue ( ) / <NUM_LIT> ; uint64_t AlignedSize = alignTo ( Size , kTagGranuleSize ) ; if ( Size == AlignedSize ) return ; Type * AllocatedType = Info . AI -> isArrayAllocation ( ) ? ArrayType :: get ( Info . AI -> getAllocatedType ( ) , cast < ConstantInt > ( Info . AI -> getArraySize ( ) ) -> getZExtValue ( ) ) : Info . AI -> getAllocatedType ( ) ; Type * PaddingType = ArrayType :: get ( Type :: getInt8Ty ( F -> getContext ( ) ) , AlignedSize - Size ) ; Type * TypeWithPadding = StructType :: get ( AllocatedType , PaddingType ) ; auto * NewAI = new AllocaInst ( TypeWithPadding , Info . AI -> getType ( ) -> getAddressSpace ( ) , nullptr , <STR_LIT> , Info . AI ) ;


<s> int unsigned_p = TYPE_UNSIGNED ( type ) ; mode = TYPE_MODE ( type ) ; mode = promote_function_mode ( type , mode , & unsigned_p , func , <NUM_LIT> ) ; } memset ( & args , <NUM_LIT> , sizeof ( args ) ) ; return loongarch_get_arg_info ( & info , & args , mode , type , true , true ) ;


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const {

OutMI . setOpcode ( MI -> getOpcode ( ) ) ;


<s> static MCSymbol * GetLazyPtr ( MCSymbol * Sym , MCContext & Ctx ) {

SmallString < <NUM_LIT> > TmpStr ( Sym -> getName ( ) . begin ( ) , Sym -> getName ( ) . end ( ) - <NUM_LIT> ) ;


<s> MachineBasicBlock :: iterator MII = Inst ; const DebugLoc & DL = Inst . getDebugLoc ( ) ; MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( <STR_LIT> ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & <STR_LIT> ; Register MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ;

MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ;


<s> if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_I1 ) { I1Defs . push_back ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . setDesc ( TII -> get ( AMDGPU :: V_MOV_B32_e32 ) ) ; continue ; } if ( MI . getOpcode ( ) == AMDGPU :: V_AND_I1 ) { I1Defs . push_back ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . setDesc ( TII -> get ( AMDGPU :: V_AND_B32_e32 ) ) ; continue ; } if ( MI . getOpcode ( ) == AMDGPU :: V_OR_I1 ) { I1Defs . push_back ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . setDesc ( TII -> get ( AMDGPU :: V_OR_B32_e32 ) ) ; continue ; } if ( MI . getOpcode ( ) != AMDGPU :: COPY || ! TargetRegisterInfo :: isVirtualRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) || ! TargetRegisterInfo :: isVirtualRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; const TargetRegisterClass * DstRC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DstRC == & AMDGPU :: VReg_1RegClass && TRI -> getCommonSubClass ( SrcRC , & AMDGPU :: SGPR_64RegClass ) ) { I1Defs . push_back ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: V_CNDMASK_B32_e64 ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; } else if ( TRI -> getCommonSubClass ( DstRC , & AMDGPU :: SGPR_64RegClass ) && SrcRC == & AMDGPU :: VReg_1RegClass ) { BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: V_CMP_NE_I32_e64 ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; }


int64_t Flags = MCI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> bool <ISA_LIT>CombinerHelperState :: matchSBCEqual ( MachineInstr & MI , MachineRegisterInfo & MRI ) const { assert ( MI . getOpcode ( ) == <STR_LIT> ) ; Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

Register CarryIn = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DestReg ) ) { MI . setDesc ( Builder . getTII ( ) . get ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . contains ( DestReg ) ) { MI . setDesc ( Builder . getTII ( ) . get ( <STR_LIT> ) ) ; MI . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> rtx reg ; int i ; for ( i = <NUM_LIT> ; i <= ACC_MASK ; i ++ ) if ( ( i & ACC_MASK ) == i ) global_regs [ i + ACC_FIRST ] = global_regs [ i + ACCG_FIRST ] = <NUM_LIT> ; if ( GET_CODE ( opval ) != CONST_INT ) { error ( <STR_LIT> ) ; return NULL_RTX ; } if ( ( INTVAL ( opval ) & ~ ACC_MASK ) != <NUM_LIT> ) { error ( <STR_LIT> ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { OS << <STR_LIT> ; } else if ( ! printAliasInstr ( MI , Address , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ;

if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , MII ) ;


<s> unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MIB -> memoperands_begin ( ) ) -> getValue ( ) ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ;

BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> assert ( MI . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ;

MachineOperand & CCOp = MI . getOperand ( <NUM_LIT> ) ;


<s> <ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>5 ( ) ;


<s> static unsigned encodeNeonVMOVImmediate ( unsigned Value ) { if ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; else if ( Value > <NUM_LIT> && Value <= <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; else if ( Value > <NUM_LIT> ) Value = ( Value >> <NUM_LIT> ) | <NUM_LIT> ; return Value ;


<s> bool xtensa_match_CLAMPS_imms_p ( rtx cst_max , rtx cst_min ) { int max , min ;

return IN_RANGE ( max = exact_log2 ( - INTVAL ( cst_max ) ) , <NUM_LIT> , <NUM_LIT> ) && IN_RANGE ( min = exact_log2 ( INTVAL ( cst_min ) + <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) && max == min ;