<s> if ( ( m68k_cpu_flags & ( FL_68881 | FL_CF_FPU ) ) != <NUM_LIT> ) target_mask |= MASK_HARD_FLOAT ; target_flags |= target_mask & ~ target_flags_explicit ; m68k_cpu = entry -> device ; if ( m68k_tune_entry ) { m68k_tune = m68k_tune_entry -> microarch ; m68k_tune_flags = m68k_tune_entry -> flags ; } else if ( ! m68k_cpu_entry && ! m68k_arch_entry ) { enum target_device dev ; dev = all_microarchs [ M68K_DEFAULT_TUNE ] . device ; m68k_tune_flags = all_devices [ dev ] . flags ; } else { m68k_tune = entry -> microarch ; m68k_tune_flags = entry -> flags ; } m68k_fpu = ( ! TARGET_HARD_FLOAT ? FPUTYPE_NONE : ( m68k_cpu_flags & FL_COLDFIRE ) != <NUM_LIT> ? FPUTYPE_COLDFIRE : FPUTYPE_68881 ) ; if ( TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY ) error ( <STR_LIT> ) ; if ( TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY ) flag_pic = <NUM_LIT> ; if ( TARGET_PCREL && ! TARGET_68020 && flag_pic == <NUM_LIT> ) error ( <STR_LIT> ) ; if ( TARGET_PCREL && flag_pic == <NUM_LIT> ) flag_pic = <NUM_LIT> ; if ( ! flag_pic ) { m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR ; m68k_symbolic_jump = <STR_LIT> ; } else if ( TARGET_ID_SHARED_LIBRARY ) ; else if ( TARGET_68020 || TARGET_ISAB || TARGET_ISAC ) { if ( TARGET_PCREL ) m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C ; else m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P ; if ( TARGET_ISAC ) ; else if ( TARGET_PCREL ) m68k_symbolic_jump = <STR_LIT> ; else m68k_symbolic_jump = <STR_LIT> ; flag_no_function_cse = <NUM_LIT> ; } switch ( m68k_symbolic_call_var ) { case M68K_SYMBOLIC_CALL_JSR : m68k_symbolic_call = <STR_LIT> ; break ; case M68K_SYMBOLIC_CALL_BSR_C : m68k_symbolic_call = <STR_LIT> ;


<s> if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == <NUM_LIT> ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > <NUM_LIT> ) return false ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; return dalign >= dsize ; }


<s> return ( __m64 ) __builtin_ia32_punpckldq ( ( __v2si ) __m1 , ( __v2si ) __m2 ) ;


<s> if ( Reg2 == <STR_LIT> ) return true ; if ( ! NeedsWinCFI ) return false ; if ( Reg2 == Reg1 + <NUM_LIT> ) return false ;


<s> if ( NumOperands == <NUM_LIT> ) return false ; const TargetInstrDesc & TID = TII -> get ( MI -> getOpcode ( ) ) ; if ( ! ( TID . isCall ( ) || TID . mayLoad ( ) || TID . mayStore ( ) ) ) return false ; int MemOpPos = - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; i ++ ) { MachineOperand Op = MI -> getOperand ( i ) ; if ( Op . getType ( ) == MachineOperand :: MO_GlobalAddress || Op . getType ( ) == MachineOperand :: MO_ExternalSymbol ) { MemOpPos = i ; break ; } } if ( MemOpPos == - <NUM_LIT> ) return Changed ; MachineOperand & Op = MI -> getOperand ( MemOpPos ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { DebugLoc dl = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addOperand ( Op ) ; return true ; } std :: string NewBank = CurBank ; if ( Op . getType ( ) == MachineOperand :: MO_GlobalAddress && Op . getGlobal ( ) -> getType ( ) -> getAddressSpace ( ) == <STR_LIT> ) {

NewBank = Op . getGlobal ( ) -> getSection ( ) ;


<s> Size = <NUM_LIT> ; Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler :: Success ;


<s> bool isMemImm7s4Offset ( ) const { if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> || ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && ( Val & <NUM_LIT> ) == <NUM_LIT> ) || Val == INT32_MIN ;


<s> } return AM . Scale == <NUM_LIT> && AM . BaseOffs == <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT> : if ( AM . Scale == <NUM_LIT> ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == <NUM_LIT> && AM . BaseOffs == <NUM_LIT> ; default : if ( AM . Scale == <NUM_LIT> ) {


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( true , OSABI , ELF :: EM_AARCH64 , true ) {


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> __rv . __o = __builtin_neon_vld3_dupv4hi ( ( const __builtin_neon_hi * ) __a ) ;


if ( ( MEM_EXPR ( mem ) && MEM_OFFSET_KNOWN_P ( mem ) && r10k_safe_mem_expr_p ( MEM_EXPR ( mem ) , MEM_OFFSET ( mem ) ) ) || r10k_safe_address_p ( XEXP ( mem , <NUM_LIT> ) , insn ) ) iter . skip_subrtxes ( ) ;


<s> OutStreamer -> EmitRawText ( <STR_LIT> ) ; OutStreamer -> EmitRawText ( <STR_LIT> ) ;


assert ( ( Kind == k_Memory ) && <STR_LIT> ) ;


<s> int64_t Bit = <NUM_LIT> ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Identifier : { StringRef Tok = Parser . getTok ( ) . getString ( ) ; if ( Tok == Name ) { if ( Tok == <STR_LIT> && ! hasMIMG_R128 ( ) ) Error ( S , <STR_LIT> ) ; if ( Tok == <STR_LIT> && ! isGFX9 ( ) && ! hasGFX10A16 ( ) ) Error ( S , <STR_LIT> ) ; Bit = <NUM_LIT> ; Parser . Lex ( ) ; } else if ( Tok . startswith ( <STR_LIT> ) && Tok . endswith ( Name ) ) { Bit = <NUM_LIT> ; Parser . Lex ( ) ; } else { return MatchOperand_NoMatch ; } break ; }


<s> if ( isa < MCSymbolELF > ( Sym ) ) return Sym ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Sym ) ; if ( const auto * FuncTy = dyn_cast < FunctionType > ( Global -> getValueType ( ) ) ) { const MachineFunction & MF = * MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const Function & CurrentFunc = * MF . getFunction ( ) ; SmallVector < unsigned , <NUM_LIT> > Returns ; SmallVector < unsigned , <NUM_LIT> > Params ; <STR_LIT> iPTR = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAddr64 ( ) ? <STR_LIT> :: I64 : <STR_LIT> :: I32 ; SmallVector < MVT , <NUM_LIT> > ResultMVTs ; ComputeLegalValueVTs ( CurrentFunc , TM , FuncTy -> getReturnType ( ) , ResultMVTs ) ; if ( ResultMVTs . size ( ) <= <NUM_LIT> ) for ( MVT ResultMVT : ResultMVTs ) Returns . push_back ( unsigned ( <STR_LIT> ( ResultMVT ) ) ) ; else Params . push_back ( unsigned ( iPTR ) ) ; for ( Type * Ty : FuncTy -> params ( ) ) { SmallVector < MVT , <NUM_LIT> > ParamMVTs ; ComputeLegalValueVTs ( CurrentFunc , TM , Ty , ParamMVTs ) ; for ( MVT ParamMVT : ParamMVTs ) Params . push_back ( unsigned ( <STR_LIT> ( ParamMVT ) ) ) ; }

if ( FuncTy -> isVarArg ( ) ) Params . push_back ( unsigned ( iPTR ) ) ;


<s> int elmul_log2 ; if ( sew == eew ) elmul_log2 = lmul_log2 ; else if ( sew > eew ) elmul_log2 = lmul_log2 - std :: log2 ( sew / eew ) ; else elmul_log2 = lmul_log2 + std :: log2 ( eew / sew ) ;

if ( float_p ) return floattype ( eew , elmul_log2 ) ;


<s> unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( <NUM_LIT> - i - <NUM_LIT> ) * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> static unsigned getSetLocalOpcode ( const TargetRegisterClass * RC ) { if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;


<s> SDValue Val = isVMOVModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VbicVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; } if ( Subtarget -> isThumb1Only ( ) ) if ( SDValue Result = CombineANDShift ( N , DCI , Subtarget ) ) return Result ; return SDValue ( ) ;


<s> static inline bool cris_index_p ( const_rtx x , bool strict ) {

return ( REG_P ( x ) && reg_ok_for_index_p ( x , strict ) ) ;


<s> if ( Phi == nullptr || Phi -> getNumIncomingValues ( ) != <NUM_LIT> || Phi -> getParent ( ) != L -> getHeader ( ) || Phi -> getNumUses ( ) != <NUM_LIT> ) return nullptr ; unsigned IncrementIndex = Phi -> getIncomingBlock ( <NUM_LIT> ) == L -> getLoopLatch ( ) ? <NUM_LIT> : <NUM_LIT> ; Offsets = Phi -> getIncomingValue ( IncrementIndex ) ; std :: pair < Value * , int64_t > Add = getVarAndConst ( Offsets , TypeScale ) ; if ( Add . first == nullptr ) return nullptr ; Value * OffsetsIncoming = Add . first ; int64_t Immediate = Add . second ; if ( OffsetsIncoming != Phi ) return nullptr ; Builder . SetInsertPoint ( & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; unsigned NumElems = cast < FixedVectorType > ( OffsetsIncoming -> getType ( ) ) -> getNumElements ( ) ; Instruction * ScaledOffsets = BinaryOperator :: Create ( Instruction :: Shl , Phi -> getIncomingValue ( <NUM_LIT> - IncrementIndex ) , Builder . CreateVectorSplat ( NumElems , Builder . getInt32 ( TypeScale ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; OffsetsIncoming = BinaryOperator :: Create ( Instruction :: Add , ScaledOffsets , Builder . CreateVectorSplat ( NumElems , Builder . CreatePtrToInt ( BasePtr , cast < VectorType > ( ScaledOffsets -> getType ( ) ) -> getElementType ( ) ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; OffsetsIncoming = BinaryOperator :: Create ( Instruction :: Sub , OffsetsIncoming , Builder . CreateVectorSplat ( NumElems , Builder . getInt32 ( Immediate ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; Phi -> setIncomingValue ( <NUM_LIT> - IncrementIndex , OffsetsIncoming ) ; Builder . SetInsertPoint ( I ) ; Value * EndResult ; Value * NewInduction ; if ( I -> getIntrinsicID ( ) == <STR_LIT> ) { Value * Load = tryCreateMaskedGatherBaseWB ( I , Phi , Builder , Immediate ) ; EndResult = Builder . CreateExtractValue ( Load , <NUM_LIT> , <STR_LIT> ) ; NewInduction = Builder . CreateExtractValue ( Load , <NUM_LIT> , <STR_LIT> ) ; } else { NewInduction = tryCreateMaskedScatterBaseWB ( I , Phi , Builder , Immediate ) ;


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( TM -> getTargetLowering ( ) ) {

initialize<ISA_LIT>TTIPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printLabelOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! MO . isImm ( ) ) { printOperand ( MI , OpNum , O ) ; return ; } uint64_t UImm = MO . getImm ( ) ; uint64_t Sign = UImm & ( <NUM_LIT> << ( field_width - <NUM_LIT> ) ) ;

int64_t SImm = scale * ( ( UImm & ~ Sign ) - Sign ) ;


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false ) ;


<s> addPass ( createInferAddressSpacesPass ( ) ) ;

addPass ( create<ISA_LIT>AtomicLowerPass ( ) ) ;


<s> vmls_u32 ( uint32x2_t a , uint32x2_t b , uint32x2_t c ) { uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> if ( LABEL_REF_P ( orig ) ) { * is_readonly = true ; return true ; } if ( SYMBOL_REF_P ( orig ) ) { if ( CONSTANT_POOL_ADDRESS_P ( orig ) ) { * is_readonly = true ; return true ; } if ( SYMBOL_REF_LOCAL_P ( orig ) && ! SYMBOL_REF_EXTERNAL_P ( orig ) && SYMBOL_REF_DECL ( orig ) && ( ! DECL_P ( SYMBOL_REF_DECL ( orig ) ) || ! DECL_COMMON ( SYMBOL_REF_DECL ( orig ) ) ) ) { tree decl = SYMBOL_REF_DECL ( orig ) ; tree init = ( TREE_CODE ( decl ) == VAR_DECL ) ? DECL_INITIAL ( decl ) : ( TREE_CODE ( decl ) == CONSTRUCTOR ) ? decl : <NUM_LIT> ; int reloc = <NUM_LIT> ; bool named_section , readonly ; if ( init && init != error_mark_node ) reloc = compute_reloc_for_constant ( init ) ;

named_section = TREE_CODE ( decl ) == VAR_DECL && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ;


<s> unsigned Base = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned Bytes = getLSMultipleTransferSize ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; int Opcode = MI -> getOpcode ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; bool DoMerge = false ; <STR_LIT> Mode = <STR_LIT> ( Opcode ) ; MachineBasicBlock :: iterator BeginMBBI = MBB . begin ( ) ; if ( MBBI != BeginMBBI ) { MachineBasicBlock :: iterator PrevMBBI = std :: prev ( MBBI ) ; while ( PrevMBBI != BeginMBBI && PrevMBBI -> isDebugValue ( ) ) -- PrevMBBI ; if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode = <STR_LIT> ; DoMerge = true ; } else if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { Mode = <STR_LIT> ; DoMerge = true ; } if ( DoMerge ) MBB . erase ( PrevMBBI ) ; } MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; if ( ! DoMerge && MBBI != EndMBBI ) { MachineBasicBlock :: iterator NextMBBI = std :: next ( MBBI ) ; while ( NextMBBI != EndMBBI && NextMBBI -> isDebugValue ( ) ) ++ NextMBBI ; if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ;


<s> void <ISA_LIT>16InstrInfo :: ExpandFEXT_CCRX16_ins ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SltOpc ) const { unsigned CC = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( SltOpc ) ) . addReg ( regX ) . addReg ( regY ) ;


<s> return __builtin_mve_vcmpleq_n_v8hi ( __a , __b ) ;


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( IsPositionIndependent ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> static nodes_iterator nodes_end ( const SpillCostAnalysisGraph & G ) { return G . getNodes ( ) . end ( ) ;


<s> MachineOperand VdSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VdSrc ) ; } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; Register SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ;


<s> virtual bool enableMachineScheduler ( ) const { return getGeneration ( ) <= NORTHERN_ISLANDS ;


<s> } unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( SrcReg ) . addImm ( ShiftAmt ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) . addImm ( ShiftAmt ) ;


<s> static DecodeStatus decodeBDAddr12Operand ( MCInst & Inst , uint64_t Field , const unsigned * Regs ) { uint64_t Base = Field >> <NUM_LIT> ; uint64_t Disp = Field & <NUM_LIT> ; assert ( Base < <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ;


<s> } if ( op1 != const0_rtx ) { op0 = expand_binop ( SImode , sub_optab , op0 , op1 , <NUM_LIT> , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; op1 = const0_rtx ; } } else if ( branch_operator ( cmp , VOIDmode ) ) { if ( op0 == const0_rtx ) { op0 = op1 ; op1 = const0_rtx ; switch ( code ) { case LT : code = GE ; break ; case GE : code = LT ; break ; default : gcc_unreachable ( ) ; } } if ( op1 != const0_rtx ) return <NUM_LIT> ; } else return <NUM_LIT> ; return gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ; }

if ( TARGET_HARD_FLOAT && mode == SFmode ) return gen_float_relational ( code , op0 , op1 ) ;


<s> <ISA_LIT>CCState ( CallingConv :: ID CC , bool isVarArg , MachineFunction & MF , SmallVectorImpl < CCValAssign > & locs , LLVMContext & C , int NumNamedVarArgParams ) : CCState ( CC , isVarArg , MF , locs , C ) , NumNamedVarArgParams ( NumNamedVarArgParams ) {


<s> RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; int Ops [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Ops [ i ] = i + Amt ; SDValue T = DAG . getVectorShuffle ( <STR_LIT> , dl , LHS , RHS , Ops ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , T ) ;


<s> if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) return & <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> uint64_t <ISA_LIT>GNULDBackend :: emitSectionData ( const LDSection & pSection , MemoryRegion & pRegion ) const { assert ( pRegion . size ( ) && <STR_LIT> ) ; const ELFFileFormat * file_format = getOutputFormat ( ) ; if ( file_format -> hasPLT ( ) && ( & pSection == & ( file_format -> getPLT ( ) ) ) ) { uint64_t result = m_pPLT -> emit ( pRegion ) ; return result ; } if ( file_format -> hasGOT ( ) && ( & pSection == & ( file_format -> getGOT ( ) ) ) ) { uint64_t result = m_pGOT -> emit ( pRegion ) ;


<s> ( void ) RS ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; unsigned Reg = LP64 ? <STR_LIT> : <STR_LIT> ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; if ( DestReg != <STR_LIT> ) {

unsigned ShiftBits = get<ISA_LIT>RegisterNumbering ( DestReg ) * <NUM_LIT> ;


<s> unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WidePassThru = DAG . getBitcast ( WideVecVT , Mld -> getPassThru ( ) ) ; if ( ! Mld -> getPassThru ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WidePassThru = DAG . getVectorShuffle ( WideVecVT , dl , WidePassThru , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ;

for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ;


<s> if ( msp430_reversible_cmp_operator ( operands [ <NUM_LIT> ] , VOIDmode ) ) const_op_idx = <NUM_LIT> ;

if ( GET_CODE ( operands [ const_op_idx ] ) != REG && GET_CODE ( operands [ const_op_idx ] ) != MEM ) operands [ const_op_idx ] = copy_to_mode_reg ( my_mode , operands [ const_op_idx ] ) ;


<s> unsigned <ISA_LIT>FastISel :: FastEmit_i ( MVT Ty , MVT VT , unsigned Opc , uint64_t Imm ) { if ( Opc != <STR_LIT> ) return <NUM_LIT> ; if ( VT == <STR_LIT> && <ISA_LIT>SubTarget . useCRBits ( ) ) { unsigned ImmReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Imm == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ;


<s> reserveRegisterTuples ( Reserved , Reg ) ; } } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; }


<s> std :: string <ISA_LIT>AsmPrinter :: regToString ( const MachineOperand & MO ) { unsigned RegNo = MO . getReg ( ) ;

assert ( TargetRegisterInfo :: isVirtualRegister ( RegNo ) && <STR_LIT> ) ;


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {

return new <ISA_LIT>ELFStreamer ( S , STI ) ;


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override {

return getSubtargetImpl ( ) -> getRegisterInfo ( ) ;


<s> return ( uint32x2_t ) __builtin_aarch64_ld1v2si ( ( const __builtin_aarch64_simd_si * ) a ) ;


<s> if ( MI -> getOpcode ( ) == AMDGPU :: GROUP_BARRIER ) return true ; return false ;


<s> bool useSoftFloat ( ) const override {


<s> TargetTransformInfo :: PopcntSupportKind <ISA_LIT>TTIImpl :: getPopcntSupport ( unsigned IntTyWidthInBit ) const {

return TargetTransformInfo :: PSK_FastHardware ;


<s> <ISA_LIT>ConstantPoolConstant :: <ISA_LIT>ConstantPoolConstant ( const GlobalVariable * GV , const Constant * C ) : <ISA_LIT>ConstantPoolValue ( ( Type * ) C -> getType ( ) , <NUM_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> , false ) , CVal ( C ) , GVar ( GV ) {


<s> DEBUG ( errs ( ) << <STR_LIT> ) ; EmitBranchToAt ( CameFromStub , Target ) ; } else { DEBUG ( errs ( ) << <STR_LIT> << CameFromStub << <STR_LIT> << oldpv << <STR_LIT> << Target << <STR_LIT> ) ; }


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & FS ) {


<s> return ( vector signed int ) __builtin_altivec_vsum4sbs ( ( vector signed char ) a1 , ( vector signed int ) a2 ) ;


<s> return DecodeCAS ( MI , insn , Address , Decoder , false , false , DecodeI64RegisterClass ) ;


<s> IsaVersion Version = getIsaVersion ( STI -> getCPU ( ) ) ; if ( Version . Major >= <NUM_LIT> ) return <NUM_LIT> ; if ( Version . Major >= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> Base = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Idx , Size ) ) { Base = V2 ; } else { continue ; } for ( int Hi = Idx + <NUM_LIT> ; Hi <= HalfSize ; ++ Hi ) { SDValue Insert ; int Len = Hi - Idx ; if ( isSequentialOrUndefInRange ( Mask , Idx , Len , <NUM_LIT> ) ) { Insert = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , Idx , Len , Size ) ) { Insert = V2 ; } else { continue ; }

if ( isUndefInRange ( Mask , Hi , HalfSize - Hi ) ) {


<s> microblaze_elf_asm_cdtor ( symbol , priority , true ) ;


<s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> const SDValue Ops [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , PtrLo , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , PtrHi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DataLo , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DataHi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ;

return DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ;


<s> case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_FREM : return true ; default : return false ; }


<s> auto Best = AvailQueue . begin ( ) ; for ( auto I = std :: next ( AvailQueue . begin ( ) ) , E = AvailQueue . end ( ) ; I != E ; ++ I ) { auto NewBestSU = pickBest ( Best -> SU , I -> SU ) ; if ( NewBestSU != Best -> SU ) { assert ( NewBestSU == I -> SU ) ; Best = I ; } } return & * Best ;


<s> return createELFObjectWriter ( new <ISA_LIT>ELFObjectWriter ( true , OSType , ELF :: EM_<ISA_LIT>_64 , true ) , OS , true ) ;


<s> F -> insert ( MBBIter , newMBB ) ; F -> insert ( MBBIter , nextMBB ) ; nextMBB -> transferSuccessors ( thisMBB ) ; thisMBB -> addSuccessor ( newMBB ) ; newMBB -> addSuccessor ( nextMBB ) ; newMBB -> addSuccessor ( newMBB ) ; DebugLoc dl = bInstr -> getDebugLoc ( ) ; assert ( bInstr -> getNumOperands ( ) < <NUM_LIT> && <STR_LIT> ) ; MachineOperand & dest1Oper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand & dest2Oper = bInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand * argOpers [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) argOpers [ i ] = & bInstr -> getOperand ( i + <NUM_LIT> ) ; int lastAddrIndx = <NUM_LIT> ; unsigned t1 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( thisMBB , dl , TII -> get ( LoadOpc ) , t1 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; unsigned t2 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MIB = BuildMI ( thisMBB , dl , TII -> get ( LoadOpc ) , t2 ) ; for ( int i = <NUM_LIT> ; i <= lastAddrIndx - <NUM_LIT> ; ++ i ) ( * MIB ) . addOperand ( * argOpers [ i ] ) ; MachineOperand newOp3 = * ( argOpers [ <NUM_LIT> ] ) ; if ( newOp3 . isImm ( ) ) newOp3 . setImm ( newOp3 . getImm ( ) + <NUM_LIT> ) ; else newOp3 . setOffset ( newOp3 . getOffset ( ) + <NUM_LIT> ) ; ( * MIB ) . addOperand ( newOp3 ) ; unsigned t3 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; unsigned t4 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , dest1Oper . getReg ( ) ) . addReg ( t1 ) . addMBB ( thisMBB ) . addReg ( t3 ) . addMBB ( newMBB ) ; BuildMI ( newMBB , dl , TII -> get ( <STR_LIT> ) , dest2Oper . getReg ( ) ) . addReg ( t2 ) . addMBB ( thisMBB ) . addReg ( t4 ) . addMBB ( newMBB ) ; unsigned tt1 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ;

unsigned tt2 = F -> getRegInfo ( ) . createVirtualRegister ( RC ) ;


<s> else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ; if ( ( * annotationCache ) [ m ] [ gv ] . find ( prop ) == ( * annotationCache ) [ m ] [ gv ] . end ( ) ) return false ;

retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ <NUM_LIT> ] ;


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addReg ( SrcVec ) ; } } else if ( Mask [ <NUM_LIT> ] == <NUM_LIT> && Mask [ <NUM_LIT> ] == <NUM_LIT> ) { if ( IsVALU ) { MachineInstr * MovSDWA = BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> :: WORD_0 ) . addImm ( <STR_LIT> :: UNUSED_PRESERVE ) . addImm ( <STR_LIT> :: WORD_1 ) . addReg ( SrcVec , RegState :: Implicit ) ; MovSDWA -> tieOperands ( <NUM_LIT> , MovSDWA -> getNumOperands ( ) - <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addReg ( SrcVec ) ; } } else if ( Mask [ <NUM_LIT> ] == <NUM_LIT> && Mask [ <NUM_LIT> ] == <NUM_LIT> ) { if ( IsVALU ) { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcVec ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) ; } else { Register TmpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( SrcVec ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( TmpReg ) . addReg ( SrcVec ) ; } } else llvm_unreachable ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ;


<s> case NE : if ( ( GET_CODE ( op0 ) == NEG || GET_CODE ( op0 ) == ABS ) && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) return CCAPmode ; if ( GET_CODE ( op0 ) == PLUS && GET_CODE ( XEXP ( op0 , <NUM_LIT> ) ) == CONST_INT && CONST_OK_FOR_K ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ) ) return CCAPmode ; if ( ( GET_CODE ( op0 ) == PLUS || GET_CODE ( op0 ) == MINUS || GET_CODE ( op1 ) == NEG ) && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) return CCLmode ; if ( GET_CODE ( op0 ) == AND ) { machine_mode ccmode ; ccmode = s390_tm_ccmode ( XEXP ( op0 , <NUM_LIT> ) , op1 , <NUM_LIT> ) ; if ( ccmode != VOIDmode ) { return ccmode == CCTmode ? CCZmode : ccmode ; } } if ( register_operand ( op0 , HImode ) && GET_CODE ( op1 ) == CONST_INT && ( INTVAL ( op1 ) == - <NUM_LIT> || INTVAL ( op1 ) == <NUM_LIT> ) ) return CCT3mode ; if ( register_operand ( op0 , QImode ) && GET_CODE ( op1 ) == CONST_INT && ( INTVAL ( op1 ) == - <NUM_LIT> || INTVAL ( op1 ) == <NUM_LIT> ) ) return CCT3mode ; return CCZmode ; case LE : case LT : case GE : case GT : if ( ( GET_CODE ( op0 ) == NEG || GET_CODE ( op0 ) == ABS ) && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) return CCAPmode ; if ( GET_CODE ( op0 ) == PLUS && GET_CODE ( XEXP ( op0 , <NUM_LIT> ) ) == CONST_INT && ( CONST_OK_FOR_K ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ) || ( CONST_OK_FOR_CONSTRAINT_P ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) , 'O' , <STR_LIT> ) && ( ! TARGET_ZARCH || INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) != - <NUM_LIT> - <NUM_LIT> ) ) ) ) { if ( INTVAL ( XEXP ( ( op0 ) , <NUM_LIT> ) ) < <NUM_LIT> ) return CCANmode ; else return CCAPmode ; } case UNORDERED : case ORDERED : case UNEQ : case UNLE : case UNLT : case UNGE : case UNGT : case LTGT : if ( ( GET_CODE ( op0 ) == SIGN_EXTEND || GET_CODE ( op0 ) == ZERO_EXTEND ) && GET_CODE ( op1 ) != CONST_INT ) return CCSRmode ; return CCSmode ; case LTU : case GEU : if ( GET_CODE ( op0 ) == PLUS && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) return CCL1mode ; if ( ( GET_CODE ( op0 ) == SIGN_EXTEND || GET_CODE ( op0 ) == ZERO_EXTEND ) && GET_CODE ( op1 ) != CONST_INT ) return CCURmode ;


<s> void addImmTLSOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg ) ; auto MIBHI = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ;

if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> unsigned Opc = Op . getOpcode ( ) ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; bool SignedConv = Opc == <STR_LIT> ; if ( SignedConv && ! Subtarget . hasP9Altivec ( ) ) return SDValue ( ) ; SDValue Wide = widenVec ( DAG , Op . getOperand ( <NUM_LIT> ) , dl ) ; EVT WideVT = Wide . getValueType ( ) ; unsigned WideNumElts = WideVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffV ; for ( unsigned i = <NUM_LIT> ; i < WideNumElts ; ++ i ) ShuffV . push_back ( i + WideNumElts ) ; if ( Subtarget . isLittleEndian ( ) ) { ShuffV [ <NUM_LIT> ] = <NUM_LIT> ; ShuffV [ WideNumElts / <NUM_LIT> ] = <NUM_LIT> ; } else { ShuffV [ WideNumElts / <NUM_LIT> - <NUM_LIT> ] = <NUM_LIT> ; ShuffV [ WideNumElts - <NUM_LIT> ] = <NUM_LIT> ; } SDValue ShuffleSrc2 = SignedConv ? DAG . getUNDEF ( WideVT ) :

DAG . getConstant ( <NUM_LIT> , dl , WideVT ) ;


<s> auto * ZII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFFrame -> getCalleeSavedInfo ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int64_t SPOffsetFromCFA = - <STR_LIT> ; if ( ZFI -> getLowSavedGPR ( ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int64_t Offset = SPOffsetFromCFA + RegSpillOffsets [ Reg ] ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;

for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ;


<s> switch ( code ) { case UNSPEC_LDA : case UNSPEC_LDS : case UNSPEC_LDS_A : case UNSPEC_LDSA : return code ; default : return - <NUM_LIT> ; }


<s> virtual void EmitBytes ( StringRef Data ) {


<s> int eq_neq_comparison_operator ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) {

return ( GET_CODE ( op ) == EQ || GET_CODE ( op ) == NE ) ;


<s> if ( DoBothBroadcast ( ) ) return lowerShuffleAsDecomposedShuffleMerge ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ; int LaneCount = VT . getSizeInBits ( ) / <NUM_LIT> ; int LaneSize = Size / LaneCount ; SmallBitVector LaneInputs [ <NUM_LIT> ] ; LaneInputs [ <NUM_LIT> ] . resize ( LaneCount , false ) ; LaneInputs [ <NUM_LIT> ] . resize ( LaneCount , false ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneInputs [ Mask [ i ] / Size ] [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( LaneInputs [ <NUM_LIT> ] . count ( ) <= <NUM_LIT> && LaneInputs [ <NUM_LIT> ] . count ( ) <= <NUM_LIT> ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ;


<s> int xstormy16_mode_dependent_address_p ( rtx x ) { if ( LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) && ! LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == PLUS && LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) && ! LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) return <NUM_LIT> ; if ( GET_CODE ( x ) == PLUS ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return <NUM_LIT> ;


<s> if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || flag_signed_zeros ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( <NUM_LIT> , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ;

if ( MEM_P ( if_true ) && MEM_P ( if_false ) ) if_true = force_reg ( mode , if_true ) ;


<s> SDValue Vec2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FMAOp1 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAOp2 = FMA . getOperand ( <NUM_LIT> ) ; SDValue FMAAcc = FMA . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; FMAOp1 = FMAOp1 . getOperand ( <NUM_LIT> ) ; FMAOp2 = FMAOp2 . getOperand ( <NUM_LIT> ) ; if ( FMAOp1 . getOpcode ( ) != <STR_LIT> || FMAOp2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec3 = FMAOp1 . getOperand ( <NUM_LIT> ) ; SDValue Vec4 = FMAOp2 . getOperand ( <NUM_LIT> ) ; SDValue Idx2 = FMAOp1 . getOperand ( <NUM_LIT> ) ; if ( Idx1 != Op2 . getOperand ( <NUM_LIT> ) || Idx2 != FMAOp2 . getOperand ( <NUM_LIT> ) || Idx1 == Idx2 ) return SDValue ( ) ; if ( Vec1 == Vec2 || Vec3 == Vec4 ) return SDValue ( ) ; if ( Vec1 . getValueType ( ) != <STR_LIT> || Vec2 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ( Vec1 == Vec3 && Vec2 == Vec4 ) || ( Vec1 == Vec4 && Vec2 == Vec3 ) ) { return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec1 , Vec2 , FMAAcc , DAG . getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; }


<s> case AMDGPU :: IF_PREDICATE_SET : case AMDGPU :: ELSE : case AMDGPU :: ENDIF : case AMDGPU :: ENDLOOP : case AMDGPU :: WHILELOOP : return true ;


<s> auto IsALoadChain = [ & ] ( Value * Start ) { SmallVector < Value * , <NUM_LIT> > ValuesToCheck = { Start } ; auto IsALoadChainInstr = [ ] ( Value * V ) -> bool { if ( isa < GetElementPtrInst > ( V ) || isa < BitCastInst > ( V ) || isa < LoadInst > ( V ) ) return true ; if ( auto * ASC = dyn_cast < AddrSpaceCastInst > ( V ) ) { if ( ASC -> getDestAddressSpace ( ) == ADDRESS_SPACE_PARAM ) return true ; } return false ; } ; while ( ! ValuesToCheck . empty ( ) ) { Value * V = ValuesToCheck . pop_back_val ( ) ; if ( ! IsALoadChainInstr ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Arg << <STR_LIT> << * V << <STR_LIT> ) ; ( void ) Arg ;


<s> bool <ISA_LIT>InstrInfo :: ClobbersPredicate ( MachineInstr & MI , std :: vector < MachineOperand > & Pred , bool SkipDead ) const {

return isPredicateSetter ( MI . getOpcode ( ) ) ;


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const {


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>BaseTargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , TM ( TM ) , RBI ( RBI ) , STI ( STI ) , Opcodes ( STI ) , {


<s> bool <ISA_LIT>FastISel :: emitFCmp ( MVT RetVT , const Value * LHS , const Value * RHS ) { if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; bool UseImm = false ; if ( const auto * CFP = dyn_cast < ConstantFP > ( RHS ) ) if ( CFP -> isZero ( ) && ! CFP -> isNegative ( ) ) UseImm = true ; Register LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return false ; if ( UseImm ) { unsigned Opc = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( LHSReg ) ; return true ;


<s> <ISA_LIT>ExpandSpecialInstrsPass ( ) : MachineFunctionPass ( ID ) {


<s> return __builtin_mve_vcreateq_uv8hi ( __a , __b ) ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


OutStreamer . emitRawComment ( <STR_LIT> + Twine ( header . wavefront_sgpr_count ) , false ) ;


<s> MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind ) ) ; ++ MCNumCPRelocations ; } else isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm8 , Fixups ) ; uint32_t Binary = ( Imm8 >> <NUM_LIT> ) & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; Binary |= ( Reg << <NUM_LIT> ) ;


<s> unsigned TakenBranchCost = Subtarget . getMispredictionPenalty ( ) ; unsigned TUnpredCycles , FUnpredCycles ; if ( ! FCycles ) { TUnpredCycles = TCycles + NotTakenBranchCost ; FUnpredCycles = TakenBranchCost ; } else { TUnpredCycles = TCycles + TakenBranchCost ; FUnpredCycles = FCycles + NotTakenBranchCost ; PredCost -= <NUM_LIT> * ScalingUpFactor ; } unsigned TUnpredCost = Probability . scale ( TUnpredCycles * ScalingUpFactor ) ; unsigned FUnpredCost = Probability . getCompl ( ) . scale ( FUnpredCycles * ScalingUpFactor ) ; UnpredCost = TUnpredCost + FUnpredCost ; if ( Subtarget . isThumb2 ( ) && TCycles + FCycles > <NUM_LIT> ) { PredCost += ( ( TCycles + FCycles - <NUM_LIT> ) / <NUM_LIT> ) * ScalingUpFactor ;


<s> Op , DAG . getConstant ( NumBits , OpVT ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Ops , array_lengthof ( Ops ) ) ;

if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ;


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { assert ( Modifier && <STR_LIT> ) ; unsigned Code = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( StringRef ( Modifier ) == <STR_LIT> ) { switch ( ( <STR_LIT> ) Code ) { case <STR_LIT> : return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ;


return ( uint8x16_t ) __builtin_neon_vreinterpretv16qiv8hi ( ( int16x8_t ) __a ) ;


<s> MatchClassKind Expected = static_cast < MatchClassKind > ( ExpectedKind ) ; if ( Op . isImm ( ) ) { if ( MCConstantExpr const * Const = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) { int64_t RegNum = Const -> getValue ( ) ; std :: ostringstream RegName ; RegName << <STR_LIT> << RegNum ; RegNum = MatchRegisterName ( RegName . str ( ) . c_str ( ) ) ; if ( RegNum != <STR_LIT> ) { Op . makeReg ( RegNum ) ; if ( validateOperandClass ( Op , Expected ) == Match_Success ) { return Match_Success ; } } } } if ( Op . isReg ( ) ) { if ( isSubclass ( Expected , MCK_DREGS ) ) { unsigned correspondingDREG = toDREG ( Op . getReg ( ) ) ; if ( correspondingDREG != <STR_LIT> ) {


<s> assert ( AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> ) ; if ( AM . BaseType == <STR_LIT> ) MIB . addReg ( AM . Base . Reg ) ; else if ( AM . BaseType == <STR_LIT> ) MIB . addFrameIndex ( AM . Base . FrameIndex ) ; else assert ( <NUM_LIT> ) ; MIB . addImm ( AM . Scale ) . addReg ( AM . IndexReg ) ;

if ( AM . GV ) return MIB . addGlobalAddress ( AM . GV , AM . Disp , AM . GVOpFlags ) ;


<s> if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else return MCDisassembler :: Fail ; MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; return MCDisassembler :: Success ;


return ( int32x2_t ) __builtin_aarch64_sqabsv2si ( __a ) ;


<s> if ( Suffix == 's' || Suffix == 'd' ) O << '.' << Suffix ; else assert ( Suffix == <NUM_LIT> && <STR_LIT> ) ; bool DoShift = ExtWidth != <NUM_LIT> ; if ( SignExtend || DoShift || SrcRegKind == 'w' ) { O << <STR_LIT> ;

printMemExtendImpl ( SignExtend , DoShift , ExtWidth , SrcRegKind , O ) ;


<s> void setTCReturnAddrDelta ( int delta ) {


<s> } if ( is_sse ) { if ( TARGET_AVX ) { strcpy ( buf , ssep ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else { strcpy ( buf , ssep + <NUM_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SFmode ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } return buf ; } strcpy ( buf , p ) ; switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case MULT : case PLUS : if ( REG_P ( operands [ <NUM_LIT> ] ) && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) { if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; break ; } if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ; break ; case MINUS : case DIV : if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { p = <STR_LIT> ; break ; } if ( find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) { if ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) p = <STR_LIT> ; else p = <STR_LIT> ;


<s> FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; } return <NUM_LIT> ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> pass_nds32_relax_opt ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_nds32_relax_opt , ctxt ) {


<s> return HasLAHFSAHF64 || ! is64Bit ( ) ;


<s> LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ;


<s> <ISA_LIT>AsmPrinter ( raw_ostream & o , TargetMachine & tm , const TargetAsmInfo * T , bool F ) : AsmPrinter ( o , tm , T , F ) {


<s> OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( DotExpr ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ;


<s> if ( ! IsPush && ! IsPop ) return false ; bool IsVFPPushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; bool IsT1PushPop = MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ; assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned FirstReg = MI -> getOperand ( RegListIdx ) . getReg ( ) ; unsigned RD0Reg , RegsNeeded ; if ( IsVFPPushPop ) { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } else { RD0Reg = <STR_LIT> ; RegsNeeded = NumBytes / <NUM_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) RegList . push_back ( MI -> getOperand ( i ) ) ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned CurReg = FirstReg - <NUM_LIT> ; CurReg >= RD0Reg && RegsNeeded ; -- CurReg ) { if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded ; continue ; } if ( isCalleeSavedRegister ( CurReg , CSRegs ) || isAnySubRegLive ( CurReg , TRI , MI ) ) { if ( IsVFPPushPop ) return false ; else continue ; } RegList . push_back ( MachineOperand :: CreateReg ( CurReg , true , false , false , true ) ) ; -- RegsNeeded ; } if ( RegsNeeded > <NUM_LIT> ) return false ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) MI -> RemoveOperand ( i ) ;

MachineInstrBuilder MIB ( MF , & * MI ) ;


<s> return DisassembleLdStMiscFrm ( MI , Opcode , insn , NumOps , NumOpsAdded , true , B ) ;


<s> for ( const std :: string & S : DwarfFiles ) getStreamer ( ) . emitRawText ( S ) ;


<s> assert ( ( Kind == k_CCOp ) && <STR_LIT> ) ; return CC . CCVal ;


<s> V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ;

if ( ExtVT != VT ) V2 = DAG . getBitcast ( VT , V2 ) ;


<s> if ( Op . isAligned ( AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ; } ; if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: scalar ( <NUM_LIT> ) ;

if ( Op . size ( ) >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: scalar ( <NUM_LIT> ) ;


<s> void Thumb1InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { assert ( ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( Register :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) && <STR_LIT> ) ; if ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( Register :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> if ( i != ~ ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) && arm_const_double_by_immediates ( GEN_INT ( i + <NUM_LIT> ) ) ) { * op1 = GEN_INT ( i + <NUM_LIT> ) ; * code = * code == GTU ? GEU : LTU ; return ; } break ; default : gcc_unreachable ( ) ; } } if ( ! op0_preserve_value ) { std :: swap ( * op0 , * op1 ) ; * code = ( int ) swap_condition ( ( enum rtx_code ) * code ) ; } } return ; } if ( mode == SImode && GET_CODE ( * op0 ) == ZERO_EXTEND && GET_CODE ( XEXP ( * op0 , <NUM_LIT> ) ) == SUBREG && GET_MODE ( XEXP ( * op0 , <NUM_LIT> ) ) == QImode && GET_MODE ( SUBREG_REG ( XEXP ( * op0 , <NUM_LIT> ) ) ) == SImode && subreg_lowpart_p ( XEXP ( * op0 , <NUM_LIT> ) ) && * op1 == const0_rtx ) * op0 = gen_rtx_AND ( SImode , SUBREG_REG ( XEXP ( * op0 , <NUM_LIT> ) ) , GEN_INT ( <NUM_LIT> ) ) ; if ( ! CONST_INT_P ( * op1 ) || const_ok_for_arm ( INTVAL ( * op1 ) ) || const_ok_for_arm ( - INTVAL ( * op1 ) ) ) return ; i = INTVAL ( * op1 ) ; switch ( * code ) { case EQ : case NE : return ; case GT : case LE : if ( i != maxval && ( const_ok_for_arm ( i + <NUM_LIT> ) || const_ok_for_arm ( - ( i + <NUM_LIT> ) ) ) ) { * op1 = GEN_INT ( ARM_SIGN_EXTEND ( i + <NUM_LIT> ) ) ; * code = * code == GT ? GE : LT ; return ; } break ; case GE : case LT : if ( i != ~ maxval && ( const_ok_for_arm ( i - <NUM_LIT> ) || const_ok_for_arm ( - ( i - <NUM_LIT> ) ) ) ) { * op1 = GEN_INT ( i - <NUM_LIT> ) ; * code = * code == GE ? GT : LE ; return ; } break ; case GTU : case LEU : if ( i != ~ ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) && ( const_ok_for_arm ( i + <NUM_LIT> ) || const_ok_for_arm ( - ( i + <NUM_LIT> ) ) ) ) { * op1 = GEN_INT ( ARM_SIGN_EXTEND ( i + <NUM_LIT> ) ) ; * code = * code == GTU ? GEU : LTU ; return ; } break ; case GEU : case LTU : if ( i != <NUM_LIT> && ( const_ok_for_arm ( i - <NUM_LIT> ) || const_ok_for_arm ( - ( i - <NUM_LIT> ) ) ) ) { * op1 = GEN_INT ( i - <NUM_LIT> ) ; * code = * code == GEU ? GTU : LEU ; return ;


<s> unsigned SrcOpc1 = Src1 . getOpcode ( ) ; EVT SrcVT0 = Src0 . getValueType ( ) ; EVT SrcVT1 = Src1 . getValueType ( ) ; if ( ! Src1 . isUndef ( ) && ( SrcVT0 != SrcVT1 || SrcOpc0 != SrcOpc1 ) ) return SDValue ( ) ; switch ( SrcOpc0 ) { case <STR_LIT> : { SDValue LHS = DAG . getBitcast ( VT , Src0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getBitcast ( VT , Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , V . getOperand ( <NUM_LIT> ) ) ; Res = DAG . getNode ( SrcOpc0 , DL , SrcVT0 , DAG . getBitcast ( SrcVT0 , Res ) ) ; return DAG . getBitcast ( VT , Res ) ; } case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> std :: shared_ptr < msgpack :: Node > & getRootMetadata ( StringRef Key ) {

return ( * cast < msgpack :: MapNode > ( HSAMetadataRoot . get ( ) ) ) [ Key ] ;


<s> for ( j = XVECLEN ( op , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return <NUM_LIT> ; } else if ( fmt [ i ] == 'e' && symbolic_reference_mentioned_p ( XEXP ( op , i ) ) ) return <NUM_LIT> ; }


<s> bool enableMultipleCopyHints ( ) const override { return true ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( <ISA_LIT>MachineFunction * MFI , SDValue Op , SelectionDAG & DAG ) const { const DataLayout & DL = DAG . getDataLayout ( ) ; GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( G -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS || G -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ) { if ( ! MFI -> isModuleEntryFunction ( ) && ! GV -> getName ( ) . equals ( <STR_LIT> ) ) { SDLoc DL ( Op ) ;

const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ;


<s> static DecodeStatus s4_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) {

signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> if ( f & CC_FLAG_O ) { if ( f & CC_FLAG_C ) return CCmode ; else return CC_ZSOmode ; } else if ( f & CC_FLAG_C ) return CC_ZSCmode ;


<s> printOperand ( MI , OpNum , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; unsigned Op = <STR_LIT> ( MO2 . getImm ( ) ) ;

if ( AlwaysPrintImm0 || ImmOffs || Op == <STR_LIT> ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ;


<s> vld1_s8 ( const int8_t * a ) { return __builtin_aarch64_ld1v8qi ( ( const __builtin_aarch64_simd_qi * ) a ) ;


<s> return Opc != getTransformOpcode ( Opc ) ;


<s> } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ; if ( UseMovt ) { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; OffsetMIB . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; } else { OffsetMIB = BuildMI ( MBB , * MIB , MIB -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Offset ) ; addOpsForConstantPoolLoad ( OffsetMIB , GV , true ) ; } if ( ! constrainSelectedInstRegOperands ( * OffsetMIB , TII , TRI , RBI ) ) return false ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; MIB . addReg ( <STR_LIT> ) . addReg ( Offset ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isTargetELF ( ) ) { if ( UseMovt ) { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } else { MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> RemoveOperand ( <NUM_LIT> ) ; addOpsForConstantPoolLoad ( MIB , GV , false ) ; } } else if ( STI . isTargetMachO ( ) ) {

if ( UseMovt ) MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ;


<s> if ( P . useSoftFloat ( ) ) CPR1Size = <STR_LIT> ; else if ( P . hasMSA ( ) ) CPR1Size = <STR_LIT> ;

else CPR1Size = P . isFP64bit ( ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( Subtarget -> hasApertureRegs ( ) ) { unsigned Offset = AS == <ISA_LIT>AS :: LOCAL_ADDRESS ? <STR_LIT> :: OFFSET_SRC_SHARED_BASE : <STR_LIT> :: OFFSET_SRC_PRIVATE_BASE ; unsigned WidthM1 = AS == <ISA_LIT>AS :: LOCAL_ADDRESS ? <STR_LIT> :: WIDTH_M1_SRC_SHARED_BASE : <STR_LIT> :: WIDTH_M1_SRC_PRIVATE_BASE ; unsigned Encoding = <STR_LIT> :: ID_MEM_BASES << <STR_LIT> :: ID_SHIFT_ | Offset << <STR_LIT> :: OFFSET_SHIFT_ | WidthM1 << <STR_LIT> :: WIDTH_M1_SHIFT_ ; SDValue EncodingImm = DAG . getTargetConstant ( Encoding , DL , <STR_LIT> ) ; SDValue ApertureReg = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , EncodingImm ) , <NUM_LIT> ) ; SDValue ShiftAmount = DAG . getTargetConstant ( WidthM1 + <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ApertureReg , ShiftAmount ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

unsigned UserSGPR = Info -> getQueuePtrUserSGPR ( ) ;


<s> static bool rs6000_real_tls_symbol_ref_p ( rtx x ) {

return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) >= TLS_MODEL_REAL ) ;


<s> bool <ISA_LIT>InstructionSelector :: tryOptCompareBranchFedByICmp ( MachineInstr & I , MachineInstr & ICmp , MachineIRBuilder & MIB ) const { assert ( ICmp . getOpcode ( ) == TargetOpcode :: G_ICMP ) ; assert ( I . getOpcode ( ) == TargetOpcode :: G_BRCOND ) ; if ( ! ProduceNonFlagSettingCondBr ) return false ; MachineRegisterInfo & MRI = * MIB . getMRI ( ) ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; auto Pred = static_cast < CmpInst :: Predicate > ( ICmp . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; Register LHS = ICmp . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = ICmp . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; MachineInstr * AndInst = getOpcodeDef ( TargetOpcode :: G_AND , LHS , MRI ) ; if ( VRegAndVal && ! AndInst ) { int64_t C = VRegAndVal -> Value . getSExtValue ( ) ; if ( C == - <NUM_LIT> && Pred == CmpInst :: ICMP_SGT ) { uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , false , DestMBB , MIB ) ; I . eraseFromParent ( ) ; return true ; } if ( C == <NUM_LIT> && Pred == CmpInst :: ICMP_SLT ) { uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , true , DestMBB , MIB ) ; I . eraseFromParent ( ) ; return true ; } } if ( ICmpInst :: isEquality ( Pred ) ) { if ( ! VRegAndVal ) { std :: swap ( RHS , LHS ) ; VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; AndInst = getOpcodeDef ( TargetOpcode :: G_AND , LHS , MRI ) ; } if ( VRegAndVal && VRegAndVal -> Value == <NUM_LIT> ) { if ( AndInst && tryOptAndIntoCompareBranch ( * AndInst , Pred == CmpInst :: ICMP_NE , DestMBB , MIB ) ) { I . eraseFromParent ( ) ; return true ; }


<s> return ( __m128i ) __builtin_ia32_pbroadcastb128 ( ( __v16qi ) __X ) ;


<s> const MCExpr * <ISA_LIT>ELFMCAsmInfo :: getExprForPersonalitySymbol ( const MCSymbol * Sym , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { MCContext & Ctx = Streamer . getContext ( ) ; return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 , MCSymbolRefExpr :: create ( Sym , Ctx ) , Ctx ) ;


<s> SDValue Loads [ <NUM_LIT> ] ; uint64_t SrcOff = <NUM_LIT> , DstOff = <NUM_LIT> ; unsigned NumMEMCPYs = ( NumMemOps + MaxLoadsInLDM - <NUM_LIT> ) / MaxLoadsInLDM ; if ( NumMEMCPYs > <NUM_LIT> && DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) { return SDValue ( ) ; } SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I != NumMEMCPYs ; ++ I ) { unsigned NextEmittedNumMemOps = NumMemOps * ( I + <NUM_LIT> ) / NumMEMCPYs ; unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps ; Dst = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Dst , Src , DAG . getConstant ( NumRegs , dl , <STR_LIT> ) ) ; Src = Dst . getValue ( <NUM_LIT> ) ; Chain = Dst . getValue ( <NUM_LIT> ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( NumRegs * VTSize ) ; SrcPtrInfo = SrcPtrInfo . getWithOffset ( NumRegs * VTSize ) ; EmittedNumMemOps = NextEmittedNumMemOps ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; auto getRemainingValueType = [ ] ( unsigned BytesLeft ) { return ( BytesLeft >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; } ; auto getRemainingSize = [ ] ( unsigned BytesLeft ) { return ( BytesLeft >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;


<s> FunctionPass * llvm :: create<ISA_LIT>MachineInstrPrinter ( ) { return new <ISA_LIT>MachineInstrPrinter ( ) ;


<s> else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Lsr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Asr ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Ror ; else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = Rrx ; else return true ; Parser . Lex ( ) ; if ( St == Rrx ) return false ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ;


<s> <ISA_LIT>64TargetMachine :: <ISA_LIT>64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> bool <ISA_LIT>FunctionInfo :: isLiveInZExt ( unsigned VReg ) const { for ( const std :: pair < unsigned , <STR_LIT> > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isZExt ( ) ;


<s> switch ( Desc . TSFlags & <STR_LIT> ) { default : switch ( Desc . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } } case <STR_LIT> : switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( j == <NUM_LIT> ) { Rv ( StackFixup :: pushI ( i ) ) ; Rv ( StackFixup :: swap ( ) ) ; } else {


<s> return new <ISA_LIT>MCInstrAnalysis ( Info ) ;


<s> if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocNum ( Num , S ) ) ;


<s> unsigned Opc ; SDValue Offset , Base ; std :: tie ( Opc , Base , Offset ) = findAddrModeSVELoadStore ( N , Opc_rr , Opc_ri , N -> getOperand ( NumVecs + <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Scale ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , Base , Offset , N -> getOperand ( <NUM_LIT> ) } ;

SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType ( <NUM_LIT> ) , Ops ) ;


<s> if ( MI -> isCopy ( ) ) CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; else { assert ( MI -> isSubregToReg ( ) && <STR_LIT> ) ; CopySrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( ! TargetRegisterInfo :: isVirtualRegister ( CopySrcReg ) ) return CopySrcReg ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ;


<s> public : <ISA_LIT>MCInstLower ( <ISA_LIT>AsmPrinter & asmprinter ) ; void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; private : MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const ;

MCSymbol * GetBlockAddressSymbol ( const MachineOperand & MO ) const ;


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) {

Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> static bool isSGPRClass ( const TargetRegisterClass * RC ) { return ! hasVGPRs ( RC ) && ! hasAGPRs ( RC ) ;


<s> void <ISA_LIT>LowerControlFlowPass :: SkipIfDead ( MachineInstr & MI ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; if ( ! shouldSkip ( & MBB , & MBB . getParent ( ) -> back ( ) ) ) return ; MachineBasicBlock :: iterator Insert = & MI ; ++ Insert ;

BuildMI ( MBB , Insert , DL , TII -> get ( AMDGPU :: S_CBRANCH_EXECNZ ) ) . addImm ( <NUM_LIT> ) . addReg ( AMDGPU :: EXEC ) ;


<s> gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ;

rs6000_emit_le_vsx_store ( dest , source , mode ) ;


<s> return ( Imm . I >= - <NUM_LIT> && Imm . I <= <NUM_LIT> ) || Imm . F == <NUM_LIT> || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> ;


<s> BranchTarget = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; BranchTargetNoTraps = <NUM_LIT> ; TOut . emitRRI ( <STR_LIT> , RtReg , ZeroReg , BranchTargetNoTraps , IDLoc , STI ) ; } TOut . emitRR ( DivOp , RsReg , RtReg , IDLoc , STI ) ; if ( ! UseTraps ) TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; if ( ! Signed ) { TOut . emitR ( <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; TOut . emitRRI ( <STR_LIT> , ATReg , ZeroReg , - <NUM_LIT> , IDLoc , STI ) ; if ( Is<ISA_LIT>64 ) { TOut . emitRRI ( <STR_LIT> , RtReg , ATReg , BranchTarget , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; } else { TOut . emitRRI ( <STR_LIT> , RtReg , ATReg , BranchTarget , IDLoc , STI ) ; TOut . emitRI ( <STR_LIT> , ATReg , ( uint16_t ) <NUM_LIT> , IDLoc , STI ) ; } if ( UseTraps ) TOut . emitRRI ( <STR_LIT> , RsReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; else { TOut . emitRRI ( <STR_LIT> , RsReg , ATReg , BranchTargetNoTraps , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; }


<s> return getSTI ( ) . hasFeature ( <STR_LIT> ) ;


<s> <ISA_LIT>_CCState :: <ISA_LIT>_CCState ( CallingConv :: ID CC , bool isVarArg , const TargetMachine & tm , SmallVector < CCValAssign , <NUM_LIT> > & locs , LLVMContext & c ) : CallingConv ( CC ) , IsVarArg ( isVarArg ) , TM ( tm ) , TRI ( * TM . getRegisterInfo ( ) ) , Locs ( locs ) , Context ( c ) { StackOffset = <NUM_LIT> ; UsedRegs . resize ( ( TRI . getNumRegs ( ) + <NUM_LIT> ) / <NUM_LIT> ) ;


<s> if ( <ISA_LIT>ScalarSSEf64 && I -> getType ( ) -> isDoubleTy ( ) ) { const Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( V -> getType ( ) -> isFloatTy ( ) ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ;


<s> GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; <ISA_LIT>CombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; Combiner C ( PCInfo , TPC ) ;

return C . combineMachineInstrs ( MF , CSEInfo ) ;


<s> assert ( ( ElSize == <NUM_LIT> || ElSize == <NUM_LIT> || ElSize == <NUM_LIT> || ElSize == <NUM_LIT> ) && <STR_LIT> ) ; APInt UndefElts ; SmallVector < uint64_t , <NUM_LIT> > RawMask ; if ( ! extractConstantMask ( C , ElSize , UndefElts , RawMask ) ) return ; unsigned NumElts = Width / ElSize ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } int Index = RawMask [ i ] & ( NumElts - <NUM_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printZPRasFPR64 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) {

unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ;


<s> static SDValue LowerVACOPY ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ;

SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ;


<s> if ( Sub == <NUM_LIT> ) return MachineEvaluator :: mask ( Reg , <NUM_LIT> ) ; const TargetRegisterClass & RC = * MRI . getRegClass ( Reg ) ; unsigned ID = RC . getID ( ) ; uint16_t RW = getRegBitWidth ( RegisterRef ( Reg , Sub ) ) ; const auto & HRI = static_cast < const <ISA_LIT>RegisterInfo & > ( TRI ) ; bool IsSubLo = ( Sub == HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ) ; switch ( ID ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return IsSubLo ? BT :: BitMask ( <NUM_LIT> , RW - <NUM_LIT> ) : BT :: BitMask ( RW , <NUM_LIT> * RW - <NUM_LIT> ) ; default : break ;


<s> bool isMachineBasicBlock ( ) const {


<s> for ( unsigned i = <NUM_LIT> ; i < W ; ++ i ) { const BitTracker :: BitValue & V1 = OutC1 [ i ] , & V2 = OutC2 [ i ] ; if ( V1 . Type != V2 . Type || V1 . Type == BitTracker :: BitValue :: One ) return false ; if ( V1 . Type != BitTracker :: BitValue :: Ref ) continue ; if ( V1 . RefI . Pos != V2 . RefI . Pos ) return false ; if ( V1 . RefI . Reg != InpR1 ) return false ;

if ( V2 . RefI . Reg == <NUM_LIT> || V2 . RefI . Reg == OutR2 ) return false ;


<s> bool <ISA_LIT>AtomicExpandPass :: shouldExpand ( Instruction * Inst ) { if ( AtomicRMWInst * AI = dyn_cast < AtomicRMWInst > ( Inst ) ) return shouldExpandAtomicRMW ( AI ) ; if ( StoreInst * SI = dyn_cast < StoreInst > ( Inst ) ) return shouldExpandStore ( SI ) ;


<s> Base = Addr ; Index = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ;

Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ;


<s> SDValue Or = N . getOperand ( <NUM_LIT> ) ; if ( Or . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Or . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Shl = Or . getOperand ( <NUM_LIT> ) ; SDValue Srl = Or . getOperand ( <NUM_LIT> ) ; if ( Srl . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue And = Srl . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( And . getOperand ( <NUM_LIT> ) ) ) { uint32_t VC1 = Srl . getConstantOperandVal ( <NUM_LIT> ) ; uint32_t VC2 = Shl . getConstantOperandVal ( <NUM_LIT> ) ; uint32_t VC3 = And . getConstantOperandVal ( <NUM_LIT> ) ; if ( VC2 == ( <NUM_LIT> - VC1 ) && VC3 == maskLeadingOnes < uint32_t > ( VC2 ) ) { RS1 = Shl . getOperand ( <NUM_LIT> ) ; Shamt = CurDAG -> getTargetConstant ( VC1 , SDLoc ( N ) , Srl . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; return true ; } } }


<s> bool <ISA_LIT>InstrInfo :: isSaveCalleeSavedRegsCall ( const MachineInstr * MI ) const {

return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; SDValue M0 = DAG . getConstant ( <NUM_LIT> / VecWidth , dl , <STR_LIT> ) ; SDValue I0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , M0 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , I0 ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> * Scale , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , ResTy , T1 ) ; } assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ; SDValue ExtV ; if ( IdxN ) { unsigned Off = IdxN -> getZExtValue ( ) * ElemWidth ; if ( VecWidth == <NUM_LIT> && ValWidth == <NUM_LIT> ) {

assert ( Off == <NUM_LIT> || Off == <NUM_LIT> ) ;


<s> void printThumbAddrModeS4Operand ( const MCInst * MI , unsigned OpNum ) {


<s> <ISA_LIT>FavorNonGenericAddrSpaces ( ) : FunctionPass ( ID ) {


<s> gcc_assert ( REG_P ( op ) ) ; if ( ! strict || REGNO ( op ) < FIRST_PSEUDO_REGISTER || ! reg_renumber || reg_renumber [ REGNO ( op ) ] < <NUM_LIT> ) return REGNO ( op ) ;


<s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } return Ctx . GetOrCreateSymbol ( Name . str ( ) ) ;


<s> ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o , <NUM_LIT> ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> F -> insert ( I , TailMBB ) ; for ( MachineInstr * DebugInstr : SelectDebugValues ) { TailMBB -> push_back ( DebugInstr -> removeFromParent ( ) ) ; } TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; unsigned Opcode = getBranchOpcodeForIntCondCode ( CC ) ; BuildMI ( HeadMBB , DL , TII . get ( Opcode ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( TailMBB ) ; IfFalseMBB -> addSuccessor ( TailMBB ) ; auto SelectMBBI = MI . getIterator ( ) ; auto SelectEnd = std :: next ( LastSelectPseudo -> getIterator ( ) ) ; auto InsertionPoint = TailMBB -> begin ( ) ; while ( SelectMBBI != SelectEnd ) { auto Next = std :: next ( SelectMBBI ) ; if ( isSelectPseudo ( * SelectMBBI ) ) { BuildMI ( * TailMBB , InsertionPoint , SelectMBBI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( HeadMBB ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( IfFalseMBB ) ; SelectMBBI -> eraseFromParent ( ) ; } SelectMBBI = Next ;


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ;


<s> if ( ! NegVal ) return SDValue ( ) ; if ( NegVal . getValueType ( ) != VT ) return SDValue ( ) ; unsigned NewOpcode ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ;


<s> return __builtin_aarch64_sminv4si ( __a , __b ) ;


<s> else if ( CurrCycleInstr -> isDebugInstr ( ) ) return ; unsigned NumWaitStates = TII . getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = <NUM_LIT> , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) {

EmittedInstrs . push_front ( nullptr ) ;


<s> Relocation :: Type type = pRelocation . type ( ) ;

if ( type >= sizeof ( <ISA_LIT>_64ApplyFunctions ) / sizeof ( <ISA_LIT>_64ApplyFunctions [ <NUM_LIT> ] ) ) {


<s> bool <ISA_LIT>InstrInfo :: isLegalRegOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( ! MO . isReg ( ) ) return false ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = Reg . isVirtual ( ) ? MRI . getRegClass ( Reg ) : RI . getPhysRegClass ( Reg ) ; const TargetRegisterClass * DRC = RI . getRegClass ( OpInfo . RegClass ) ; if ( MO . getSubReg ( ) ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * SuperRC = RI . getLargestLegalSuperClass ( RC , * MF ) ;


<s> case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVAARG ( Op , DAG ) ;

case <STR_LIT> : return lowerVACOPY ( Op , DAG ) ;


<s> default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: <ISA_LIT>_RegisterStorePseudo : { MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ;

MachineInstrBuilder MIB = BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: <ISA_LIT>_RegisterStore ) , Reg ) ;


<s> HOST_WIDE_INT neon_element_bits ( machine_mode mode ) { return GET_MODE_UNIT_BITSIZE ( mode ) ;


<s> const char * getPassName ( ) const {


<s> TargetRegistry :: RegisterInstrPostProcess ( getThe<ISA_LIT>_32Target ( ) , create<ISA_LIT>InstrPostProcess ) ; TargetRegistry :: RegisterInstrPostProcess ( getThe<ISA_LIT>_64Target ( ) , create<ISA_LIT>InstrPostProcess ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , DAG . getConstant ( <NUM_LIT> , DL , InVT ) ) ; Ops [ <NUM_LIT> ] = Zext0 . getOperand ( <NUM_LIT> ) ; MVT ExtendedVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue SadOp0 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; Ops [ <NUM_LIT> ] = Zext1 . getOperand ( <NUM_LIT> ) ; SDValue SadOp1 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; auto PSADBWBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT VT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } ; MVT SadVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ;

return SplitOpsAndApply ( DAG , Subtarget , DL , SadVT , { SadOp0 , SadOp1 } , PSADBWBuilder ) ;


<s> } else if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { rtx src , dest ; src = SET_SRC ( PATTERN ( insn ) ) ; dest = SET_DEST ( PATTERN ( insn ) ) ; if ( ! REG_P ( dest ) || ! CC_REGNO_P ( REGNO ( dest ) ) || GET_CODE ( src ) != COMPARE ) return false ; cond = NULL_RTX ; op0 = & XEXP ( src , <NUM_LIT> ) ; op1 = & XEXP ( src , <NUM_LIT> ) ; } else return false ; if ( ! REG_P ( * op0 ) || ! REG_P ( * op1 ) ) return false ; if ( GET_MODE_CLASS ( GET_MODE ( * op0 ) ) != MODE_INT ) return false ; prev_insn = prev_active_insn ( insn ) ; if ( prev_insn != NULL_RTX && INSN_P ( prev_insn ) && reg_referenced_p ( * op1 , PATTERN ( prev_insn ) ) ) s390_swap_cmp ( cond , op0 , op1 , insn ) ; next_insn = next_active_insn ( insn ) ; if ( next_insn != NULL_RTX && INSN_P ( next_insn ) && s390_non_addr_reg_read_p ( * op1 , next_insn ) ) { if ( prev_insn != NULL_RTX && INSN_P ( prev_insn ) && s390_non_addr_reg_read_p ( * op0 , prev_insn ) ) { if ( REGNO ( * op1 ) == <NUM_LIT> ) emit_insn_after ( gen_nop1 ( ) , insn ) ; else emit_insn_after ( gen_nop ( ) , insn ) ; insn_added_p = true ; }

else s390_swap_cmp ( cond , op0 , op1 , insn ) ;


<s> Dependence = true ; return false ; } if ( ( QII -> isMemOp ( J ) && MCIDI . mayStore ( ) ) || ( MCIDJ . mayStore ( ) && QII -> isMemOp ( I ) ) || ( QII -> isMemOp ( J ) && QII -> isMemOp ( I ) ) ) { Dependence = true ; return false ; } if ( MCIDJ . mayStore ( ) && QII -> isDeallocRet ( I ) ) { Dependence = true ; return false ; } MachineBasicBlock :: iterator NextMII = I ; ++ NextMII ; MachineInstr * NextMI = NextMII ; if ( QII -> isNewValueJump ( NextMI ) ) { bool secondRegMatch = false ; bool maintainNewValueJump = false ; if ( NextMI -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . getReg ( ) == NextMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { secondRegMatch = true ; maintainNewValueJump = true ; } if ( ! secondRegMatch && I -> getOperand ( <NUM_LIT> ) . getReg ( ) == NextMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { maintainNewValueJump = true ; } for ( std :: vector < MachineInstr * > :: iterator VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE && maintainNewValueJump ) ; ++ VI ) { SUnit * PacketSU = MIToSUnit [ * VI ] ; if ( PacketSU -> getInstr ( ) -> getDesc ( ) . isCall ( ) ) { Dependence = true ; break ; } if ( PacketSU -> getInstr ( ) -> getDesc ( ) . mayStore ( ) || PacketSU -> getInstr ( ) -> getOpcode ( ) == <STR_LIT> || ( ! secondRegMatch && NextMI -> getOperand ( <NUM_LIT> ) . isReg ( ) && PacketSU -> getInstr ( ) -> modifiesRegister ( NextMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , QRI ) ) || ( secondRegMatch && PacketSU -> getInstr ( ) -> modifiesRegister ( NextMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , QRI ) ) ) { Dependence = true ; break ; } } if ( ! Dependence ) GlueToNewValueJump = true ; else return false ; } } if ( SUJ -> isSucc ( SUI ) ) { for ( unsigned i = <NUM_LIT> ; ( i < SUJ -> Succs . size ( ) ) && ! FoundSequentialDependence ;


<s> const MCInstrDesc & MC = MI . getDesc ( ) ; if ( ! <ISA_LIT>II :: isVPUInst ( MC ) ) return false ;

if ( <ISA_LIT>II :: getSrcCIsStoreSrcC ( MC ) ) return true ;


<s> SDLoc dl ( Op ) ; if ( Subtarget . isDarwinABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } SDValue ArgGPR = DAG . getConstant ( FuncInfo -> getVarArgsNumGPR ( ) , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( FuncInfo -> getVarArgsNumFPR ( ) , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackOffset ( ) , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; uint64_t nextOffset = FPROffset ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op . getOperand ( <NUM_LIT> ) , ConstFPROffset ) ; SDValue secondStore = DAG . getTruncStore ( firstStore , dl , ArgFPR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , <STR_LIT> , false , false , <NUM_LIT> ) ; nextOffset += StackOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr , ConstStackOffset ) ; SDValue thirdStore = DAG . getStore ( secondStore , dl , StackOffsetFI , nextPtr , MachinePointerInfo ( SV , nextOffset ) , false , false , <NUM_LIT> ) ;


<s> unsigned InitReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , InitReg ) ; if ( UseGPRIdxMode ) { MachineInstr * SetOn = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( VGPRIndexMode :: SRC0_ENABLE ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( <STR_LIT> ) ) ; } auto InsPt = loadM0FromVGPR ( TII , MBB , MI , InitReg , PhiReg , Offset , UseGPRIdxMode ) ; MachineBasicBlock * LoopBB = InsPt -> getParent ( ) ; if ( UseGPRIdxMode ) {

BuildMI ( * LoopBB , InsPt , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) ;


<s> getBDRAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ; uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ;

uint64_t Len = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ;


<s> getActionDefinitionsBuilder ( { G_UADDE , G_USUBO , G_USUBE } ) . lowerFor ( { { s32 , s1 } } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemSize ( { { s32 , p0 , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_ZEXTLOAD , G_SEXTLOAD } ) . legalForTypesWithMemSize ( { { s32 , p0 , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ;

getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ;


<s> void <ISA_LIT>CodeEmitter :: emitWordLE ( unsigned Word ) { DEBUG ( errs ( ) << <STR_LIT> ; errs ( ) . write_hex ( Word ) << <STR_LIT> ) ; MCE . emitWordLE ( Word ) ;


<s> DebugLoc dl = N -> getDebugLoc ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { StoreSDNode * ST = cast < StoreSDNode > ( N ) ; if ( ! DCI . isBeforeLegalize ( ) || allowsUnalignedMemoryAccesses ( ST -> getMemoryVT ( ) ) || ST -> isVolatile ( ) || ST -> isIndexed ( ) ) { break ; } SDValue Chain = ST -> getChain ( ) ; unsigned StoreBits = ST -> getMemoryVT ( ) . getStoreSizeInBits ( ) ;


<s> return ( float32x2_t ) __builtin_shuffle ( __a , ( uint32x2_t ) { <NUM_LIT> , <NUM_LIT> } ) ;


<s> void impl_pxp ( StackFixup & Rv , unsigned i , unsigned j , unsigned k ) { Rv ( StackFixup :: puxcpu ( i , j , k ) ) ;


<s> bool useCompound ( ) const { return UseCompound ;


<s> if ( Str == <STR_LIT> ) { Val = <NUM_LIT> ; return MatchOperand_Success ; } if ( Str . startswith ( <STR_LIT> ) ) { Str = Str . drop_front ( <NUM_LIT> ) ; if ( Str == <STR_LIT> ) { Val = <NUM_LIT> ; return MatchOperand_Success ; } if ( Str . getAsInteger ( <NUM_LIT> , Val ) ) return MatchOperand_ParseFail ; if ( Val > <NUM_LIT> ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } return MatchOperand_Success ; } if ( Str . startswith ( <STR_LIT> ) ) { Str = Str . drop_front ( <NUM_LIT> ) ; if ( Str . getAsInteger ( <NUM_LIT> , Val ) ) return MatchOperand_ParseFail ; if ( Val > <NUM_LIT> || ( Val == <NUM_LIT> && ! isGFX10 ( ) ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Val += <NUM_LIT> ; return MatchOperand_Success ; } if ( isGFX10 ( ) && Str == <STR_LIT> ) { Val = <NUM_LIT> ; return MatchOperand_Success ; } if ( Str . startswith ( <STR_LIT> ) ) { Str = Str . drop_front ( <NUM_LIT> ) ; if ( Str . getAsInteger ( <NUM_LIT> , Val ) ) return MatchOperand_ParseFail ; if ( Val >= <NUM_LIT> ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Val += <NUM_LIT> ; return MatchOperand_Success ; } if ( Str . startswith ( <STR_LIT> ) ) { Str = Str . drop_front ( <NUM_LIT> ) ;


<s> int <ISA_LIT>TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) {

assert ( Ty -> isIntegerTy ( ) && <STR_LIT> ) ;


<s> } Register PreloadedScratchRsrcReg ; if ( ST . isAmdHsaOrMesa ( F ) ) { PreloadedScratchRsrcReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; if ( ScratchRsrcReg && PreloadedScratchRsrcReg ) { MRI . addLiveIn ( PreloadedScratchRsrcReg ) ; MBB . addLiveIn ( PreloadedScratchRsrcReg ) ; } } DebugLoc DL ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; Register ScratchWaveOffsetReg ; if ( TRI -> isSubRegisterEq ( ScratchRsrcReg , PreloadedScratchWaveOffsetReg ) ) { ArrayRef < MCPhysReg > AllSGPRs = getAllSGPRs ( ST , MF ) ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) ; AllSGPRs = AllSGPRs . slice ( std :: min ( static_cast < unsigned > ( AllSGPRs . size ( ) ) , NumPreloaded ) ) ; Register GITPtrLoReg = MFI -> getGITPtrLoReg ( MF ) ; for ( MCPhysReg Reg : AllSGPRs ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) && ! TRI -> isSubRegisterEq ( ScratchRsrcReg , Reg ) && GITPtrLoReg != Reg ) { ScratchWaveOffsetReg = Reg ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchWaveOffsetReg ) . addReg ( PreloadedScratchWaveOffsetReg , RegState :: Kill ) ; break ; } } } else { ScratchWaveOffsetReg = PreloadedScratchWaveOffsetReg ; }


<s> if ( ! insn ) return <NUM_LIT> ; start = insn ; for ( insn = PREV_INSN ( start ) ; insn ; insn = PREV_INSN ( insn ) ) { if ( GET_CODE ( insn ) == CODE_LABEL ) { for ( tmp = NEXT_INSN ( start ) ; tmp != end ; tmp = NEXT_INSN ( tmp ) ) if ( GET_CODE ( tmp ) == JUMP_INSN && c4x_label_ref_used_p ( tmp , insn ) ) return <NUM_LIT> ; } } for ( insn = NEXT_INSN ( end ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) == CODE_LABEL ) { for ( tmp = NEXT_INSN ( start ) ; tmp != end ; tmp = NEXT_INSN ( tmp ) ) if ( GET_CODE ( tmp ) == JUMP_INSN && c4x_label_ref_used_p ( tmp , insn ) ) return <NUM_LIT> ; } } for ( insn = NEXT_INSN ( start ) ; insn != end ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) == CODE_LABEL ) { for ( tmp = NEXT_INSN ( end ) ; tmp ; tmp = NEXT_INSN ( tmp ) ) if ( GET_CODE ( tmp ) == JUMP_INSN && c4x_label_ref_used_p ( tmp , insn ) ) return <NUM_LIT> ; for ( tmp = PREV_INSN ( start ) ; tmp ; tmp = PREV_INSN ( tmp ) ) if ( GET_CODE ( tmp ) == JUMP_INSN && c4x_label_ref_used_p ( tmp , insn ) ) return <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI ) ;


<s> MIB -> getOperand ( <NUM_LIT> ) . setReg ( get<ISA_LIT>SubSuperRegister ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ) ; } else { assert ( MIB -> getOpcode ( ) == <STR_LIT> ) ; StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget . getFrameLowering ( ) ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ;

bool NeedsDwarfCFI = ! IsWin64Prologue && ( MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) . needsUnwindTableEntry ( ) ) ;


<s> if ( NoAliases || ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ;


<s> SDValue L1 = expandV4F32ToV2F64 ( DAG , <NUM_LIT> , DL , CmpOp1 ) ; SDValue HRes = DAG . getNode ( Opcode , DL , <STR_LIT> , H0 , H1 ) ; SDValue LRes = DAG . getNode ( Opcode , DL , <STR_LIT> , L0 , L1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , HRes , LRes ) ; }

return DAG . getNode ( Opcode , DL , VT , CmpOp0 , CmpOp1 ) ;


<s> __o = __builtin_aarch64_ld3v4sf ( ( const __builtin_aarch64_simd_sf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregciv4sf ( __o , <NUM_LIT> ) ;


<s> bool <ISA_LIT>ArgumentUsageInfo :: doInitialization ( Module & M ) {


<s> tree builtin_type ; builtin_type = rs6000_builtin_type ( id ) ;

if ( INTEGRAL_TYPE_P ( t ) && INTEGRAL_TYPE_P ( builtin_type ) ) return true ;


<s> if ( ! vector_block_infos . is_empty ( ) ) vector_block_infos . release ( ) ; if ( ! vector_exprs . is_empty ( ) ) vector_exprs . release ( ) ; gcc_assert ( to_refine_vsetvls . is_empty ( ) ) ; gcc_assert ( to_delete_vsetvls . is_empty ( ) ) ; if ( optimize > <NUM_LIT> ) free_bitmap_vectors ( ) ;


<s> } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && VT == XLenVT ) { auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } if ( Opcode == <STR_LIT> ) { SDLoc DL ( Node ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ;


<s> else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , ATReg ) . addReg ( ATReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ;

if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ;


<s> void <ISA_LIT>GNUInfo :: setABIVersion ( uint8_t ver ) {


<s> if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return true ; Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( RegLo ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return true ; Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( RegHi ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: RBrac ) ) return true ; Parser . Lex ( ) ; RegWidth = ( RegHi - RegLo ) + <NUM_LIT> ; if ( IsVgpr ) { RegIndexInClass = RegLo ; } else { unsigned Size = std :: min ( RegWidth , <NUM_LIT> ) ; if ( RegLo % Size != <NUM_LIT> ) return true ; RegIndexInClass = RegLo / Size ; } } const MCRegisterInfo * TRI = getContext ( ) . getRegisterInfo ( ) ; int RCID = getRegClass ( IsVgpr , RegWidth ) ; if ( RCID == - <NUM_LIT> ) return true ;

const MCRegisterClass RC = TRI -> getRegClass ( RCID ) ;


<s> return & InstrInfo . getRegisterInfo ( ) ;