<s> Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; default : return false ; } unsigned Reg ; if ( FuncInfo . Fn -> getAttributes ( ) . hasAttribute ( <NUM_LIT> , Attribute :: SExt ) ) Reg = getRegForSignedValue ( RV ) ; else if ( FuncInfo . Fn -> getAttributes ( ) . hasAttribute ( <NUM_LIT> , Attribute :: ZExt ) ) Reg = getRegForUnsignedValue ( RV ) ; else Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( Reg ) ;


<s> const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ( STI . hasLoadStoreOnCond2 ( ) && <STR_LIT> . hasSubClassEq ( RC ) ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> ; TrueCycles = <NUM_LIT> ; FalseCycles = <NUM_LIT> ; return true ;


<s> Base . Reg . getNode ( ) -> dump ( ) ; } else if ( BaseType == FrameIndexBase ) { errs ( ) << <STR_LIT> << Base . FrameIndex << '\n' ; } errs ( ) << <STR_LIT> << Disp << '\n' ; if ( GV ) { errs ( ) << <STR_LIT> ; GV -> dump ( ) ; } else if ( CP ) { errs ( ) << <STR_LIT> ; CP -> dump ( ) ; errs ( ) << <STR_LIT> << Align << '\n' ; } else if ( ES ) { errs ( ) << <STR_LIT> ;


<s> return StringSwitch < <STR_LIT> > ( LayoutStr ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> if ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) { Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , Val , <STR_LIT> ) , <STR_LIT> ) ; return true ; } } Offset = N ; <STR_LIT> ShOpcVal = <STR_LIT> ( N ) ; unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; Offset = N . getOperand ( <NUM_LIT> ) ; } else { ShOpcVal = <STR_LIT> ; } } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , ShOpcVal ) , <STR_LIT> ) ; return true ;


<s> MCRegAliasIterator R ( Reg , this , true ) ; for ( ; R . isValid ( ) ; ++ R ) Reserved . set ( * R ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseGPR64 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( ! is<ISA_LIT>64 ( ) ) return MatchOperand_NoMatch ;

return parseRegs ( Operands , ( int ) <STR_LIT> ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal / <NUM_LIT> ; if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( WordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; }


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) {

return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr ) ;


<s> for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( isa < AddOperator > ( Op ) && ( ! isa < Instruction > ( Op ) || FuncInfo . MBBMap [ cast < Instruction > ( Op ) -> getParent ( ) ] == FuncInfo . MBB ) && isa < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . Offset = TmpOffset ; if ( <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = SI -> second ; return true ; } break ; } }

if ( Addr . Base . Reg == <NUM_LIT> ) Addr . Base . Reg = getRegForValue ( Obj ) ;


<s> SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue HiSmallShift = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ;

SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ;


<s> auto ScaVT = Scalar . getValueType ( ) ; if ( isMaskType ( ResultVT ) ) return getMaskBroadcast ( ResultVT , Scalar , AVL ) ; if ( isPackedVectorType ( ResultVT ) ) {


<s> unsigned LastOp = TII -> getOperandIdx ( MI -> getOpcode ( ) , <STR_LIT> ) ;

MI -> getOperand ( LastOp ) . setImm ( Bit ) ;


<s> SDValue <ISA_LIT>TargetLowering :: combineSHIFTROT ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) { SDValue AndMaskOp = N1 -> getOperand ( <NUM_LIT> ) ; auto * AndMask = dyn_cast < ConstantSDNode > ( AndMaskOp ) ; if ( AndMask ) { auto AmtVal = AndMask -> getZExtValue ( ) ; if ( ( AmtVal & <NUM_LIT> ) == <NUM_LIT> ) { SDValue AndOp = N1 -> getOperand ( <NUM_LIT> ) ; if ( N1 . hasOneUse ( ) ) { DCI . CombineTo ( N1 . getNode ( ) , AndOp ) ; return SDValue ( N , <NUM_LIT> ) ; } else { SDValue Replace = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , AndOp ) ; DCI . AddToWorklist ( Replace . getNode ( ) ) ; return Replace ; } } else if ( AmtVal >> <NUM_LIT> != <NUM_LIT> ) { SDValue AndOp = N1 -> getOperand ( <NUM_LIT> ) ; auto NewMask = DAG . getConstant ( AndMask -> getZExtValue ( ) & <NUM_LIT> , SDLoc ( AndMaskOp ) , AndMaskOp . getValueType ( ) ) ; auto NewAnd = DAG . getNode ( N1 . getOpcode ( ) , SDLoc ( N1 ) , N1 . getValueType ( ) , AndOp , NewMask ) ; SDValue Replace = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NewAnd ) ; DCI . AddToWorklist ( Replace . getNode ( ) ) ; return Replace ;


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & C , MCAsmBackend & AB , raw_ostream & OS , MCCodeEmitter * CE , bool RelaxAll ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , AB , CE , OS ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; return S ;


<s> emit_push_byte ( AVR_ZERO_REGNO , true ) ; emit_push_byte ( AVR_TMP_REGNO , true ) ; emit_push_sfr ( sreg_rtx , false , false ) ; emit_move_insn ( zero_reg_rtx , const0_rtx ) ; emit_use ( zero_reg_rtx ) ; if ( AVR_HAVE_RAMPD ) emit_push_sfr ( rampd_rtx , false , true ) ; if ( AVR_HAVE_RAMPX && TEST_HARD_REG_BIT ( set , REG_X ) && TEST_HARD_REG_BIT ( set , REG_X + <NUM_LIT> ) ) {

emit_push_sfr ( rampx_rtx , false , true ) ;


<s> fail ( DL , DAG , <STR_LIT> ) ; } CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>64 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override {

return TargetLowering :: shouldFormOverflowOp ( Opcode , VT , true ) ;


<s> SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; } if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res ) ;

SDValue LowX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> addPass ( new RegBankSelect ( ) ) ; return false ;


<s> CurFPOData = std :: make_unique < FPOData > ( ) ; CurFPOData -> Function = ProcSym ; CurFPOData -> Begin = emitFPOLabel ( ) ; CurFPOData -> ParamsSize = ParamsSize ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { assert ( ! IsVarArg && <STR_LIT> ) ; assert ( Outs . empty ( ) && <STR_LIT> ) ; return true ;


<s> NewOut . VT = VT ; unsigned NumElements = Out . ArgVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j != NumElements ; ++ j ) { SDValue Elem = DAG . getNode ( <STR_LIT> , DL , VT , OutVals [ i ] , DAG . getConstant ( j , DL , <STR_LIT> ) ) ; SplitVals . push_back ( Elem ) ; Splits . push_back ( NewOut ) ; NewOut . PartOffset += NewOut . VT . getStoreSize ( ) ; } } else { SplitVals . push_back ( OutVals [ i ] ) ; Splits . push_back ( Out ) ; } } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Splits , CCAssignFnForReturn ( CallConv , isVarArg ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; if ( ! Info -> isEntryFunction ( ) ) { const <ISA_LIT>RegisterInfo * TRI = getSubtarget ( ) -> getRegisterInfo ( ) ; SDValue ReturnAddrReg = CreateLiveInRegister ( DAG , & <STR_LIT> , TRI -> getReturnAddressReg ( MF ) , <STR_LIT> ) ; SDValue PhysReturnAddrReg = DAG . getRegister ( TRI -> getReturnAddressReg ( MF ) , <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , PhysReturnAddrReg , ReturnAddrReg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( PhysReturnAddrReg ) ; } for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = SplitVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ;


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const {


<s> return ( int16x4_t ) __builtin_neon_vaddhnv4si ( __a , __b ) ;


<s> return __builtin_mve_vorrq_fv4sf ( __a , __b ) ;


<s> int words = ia64_function_arg_words ( type , mode ) ; int offset = ia64_function_arg_offset ( cum , type , words ) ; machine_mode hfa_mode = VOIDmode ; if ( cum -> words >= MAX_ARGUMENT_SLOTS ) { cum -> words += words + offset ; return ; } cum -> atypes [ cum -> words ] = ia64_arg_type ( mode ) ; cum -> words += words + offset ; if ( TARGET_ABI_OPEN_VMS ) { cum -> int_regs = cum -> words ; cum -> fp_regs = cum -> words ; return ; } if ( type ) hfa_mode = hfa_element_mode ( type , <NUM_LIT> ) ; if ( hfa_mode != VOIDmode && ( ! cum -> prototype || named ) ) { int fp_regs = cum -> fp_regs ; int int_regs = cum -> words - words ; int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; int byte_size ; int args_byte_size ; byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; args_byte_size = int_regs * UNITS_PER_WORD ; offset = <NUM_LIT> ; for ( ; ( offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS && args_byte_size < ( MAX_ARGUMENT_SLOTS * UNITS_PER_WORD ) ) ; ) { offset += hfa_size ; args_byte_size += hfa_size ; fp_regs ++ ; } cum -> fp_regs = fp_regs ; } else if ( mode == TFmode || mode == TCmode || ( ! FLOAT_MODE_P ( mode ) || cum -> fp_regs == MAX_ARGUMENT_SLOTS ) ) cum -> int_regs = cum -> words ; else if ( cum -> prototype ) { if ( ! named ) cum -> int_regs = cum -> words ; else cum -> fp_regs += ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ? <NUM_LIT> : <NUM_LIT> ) ; } else { cum -> fp_regs += ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ? <NUM_LIT> : <NUM_LIT> ) ; cum -> int_regs = cum -> words ; }


<s> std :: string <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( const Triple & TT , StringRef CPU ) { std :: string <ISA_LIT>ArchFeature ; <STR_LIT> ArchID = <STR_LIT> ( TT . getArchName ( ) ) ; if ( ArchID != <STR_LIT> :: INVALID && ( CPU . empty ( ) || CPU == <STR_LIT> ) ) <ISA_LIT>ArchFeature = ( <ISA_LIT>ArchFeature + <STR_LIT> + <STR_LIT> ( ArchID ) ) . str ( ) ; if ( TT . isThumb ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSNaCl ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; }


<s> if ( IsPICCall && ! InternalLinkage ) { unsigned GPReg = isN64 ( ) ? <STR_LIT> : <STR_LIT> ; EVT Ty = isN64 ( ) ? <STR_LIT> : <STR_LIT> ; RegsToPass . push_back ( std :: make_pair ( GPReg , getGlobalReg ( CLI . DAG , Ty ) ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ; if ( Subtarget -> in<ISA_LIT>16HardFloat ( ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { llvm :: StringRef Sym = G -> getGlobal ( ) -> getName ( ) ; Function * F = G -> getGlobal ( ) -> getParent ( ) -> getFunction ( Sym ) ; if ( F && F -> hasFnAttribute ( <STR_LIT> ) ) { Mask = <ISA_LIT>RegisterInfo :: get<ISA_LIT>16RetHelperMask ( ) ; } }


<s> O << '(' ; printF64 ( MI , OpNo + <NUM_LIT> , O ) ; O << <STR_LIT> ; printF64 ( MI , OpNo + <NUM_LIT> , O ) ;


<s> EVT MemVT = St -> getMemoryVT ( ) ; unsigned StElts = MemVT . getSizeInBits ( ) / VT . getScalarSizeInBits ( ) ; APInt DemandedElts = APInt :: getLowBitsSet ( VT . getVectorNumElements ( ) , StElts ) ; APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedVectorElts ( StoredVal , DemandedElts , KnownUndef , KnownZero , DCI ) ) { DCI . AddToWorklist ( N ) ;


<s> } case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; return Offset > <NUM_LIT> || Offset < <NUM_LIT> || Offset & <NUM_LIT> ; } case <STR_LIT> : int64_t Offset = ( Value & ~ <NUM_LIT> ) ; return Offset == <NUM_LIT> ; }


<s> BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( AMDGPU :: V_MOV_B32_e64 ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent ( ) ; break ; case AMDGPU :: FABS_<ISA_LIT> : BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( AMDGPU :: V_MOV_B32_e64 ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent ( ) ; break ; case AMDGPU :: FNEG_<ISA_LIT> : BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( AMDGPU :: V_MOV_B32_e64 ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent ( ) ; break ; case AMDGPU :: SHADER_TYPE : BB -> getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> ShaderType = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> bool NeedExpansion ( std :: uint16_t opcode ) {

auto decoder = Decode < Disassembler > ( opcode ) ;


<s> if ( optab_handler ( movmisalign_optab , mode ) == CODE_FOR_nothing ) return false ; if ( misalignment == - <NUM_LIT> ) {

if ( rs6000_vector_alignment_reachable ( type , is_packed ) ) {


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; f ( MI ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addImm ( P_ADDR ) . addReg ( SCRATCH_REGISTER ) ; MI . eraseFromParent ( ) ; return true ;


<s> if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , & IsFast ) ) return expandUnalignedStore ( SN , DAG ) ; if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue Val = SN -> getValue ( ) ; bool OtherUses = ! Val . hasOneUse ( ) ; SDValue CastVal = DAG . getNode ( <STR_LIT> , SL , NewVT , Val ) ; if ( OtherUses ) { SDValue CastBack = DAG . getNode ( <STR_LIT> , SL , VT , CastVal ) ;

DAG . ReplaceAllUsesOfValueWith ( Val , CastBack ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> cum -> words = <NUM_LIT> ; cum -> prototype_p = fntype && TYPE_ARG_TYPES ( fntype ) ;

cum -> libcall_p = fntype == <NUM_LIT> ;


<s> return aarch64_move_pointer ( pointer , GET_MODE_SIZE ( GET_MODE ( pointer ) ) ) ;


<s> } unsigned Opcode = decodeThumbSideEffect ( IsThumb2 , insn ) ; <ISA_LIT>Format Format = <ISA_LIT>Formats [ Opcode ] ; Size = IsThumb2 ? <NUM_LIT> : <NUM_LIT> ; DEBUG ( { errs ( ) << <STR_LIT> << Opcode << <STR_LIT> << <STR_LIT> ( Opcode ) << <STR_LIT> << stringFor<ISA_LIT>Format ( Format ) << '(' << ( int ) Format << <STR_LIT> ; showBitVector ( errs ( ) , insn ) ; } ) ; <ISA_LIT>BasicMCBuilder * Builder = CreateMCBuilder ( Opcode , Format ) ;


<s> case <STR_LIT> : return combineAnd ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineOr ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineXor ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineMaskedLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineMaskedStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : return combineVZextMovl ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ;

case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ;


<s> return ( ( ( insn ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> isFirst = isSingle = isCracked = isLoad = isStore = false ; return <STR_LIT> ; } Opcode = ~ Opcode ; const MCInstrDesc & MCID = TII . get ( Opcode ) ; isLoad = MCID . mayLoad ( ) ; isStore = MCID . mayStore ( ) ; uint64_t TSFlags = MCID . TSFlags ; isFirst = TSFlags & <STR_LIT> ; isSingle = TSFlags & <STR_LIT> ; isCracked = TSFlags & <STR_LIT> ;

return ( <STR_LIT> ) ( TSFlags & <STR_LIT> ) ;


<s> unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return S ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) SeenCatchAll = true ; if ( SeenCatchAll && MI . isCall ( ) ) { const MachineOperand & CalleeOp = MI . getOperand ( getCalleeOpNo ( MI ) ) ; if ( CalleeOp . isGlobal ( ) && CalleeOp . getGlobal ( ) -> getName ( ) == StdTerminateFn ) return true ;


<s> SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , DL ) ; SDValue Low = DAG . getNode ( <STR_LIT> , DL , VT , V , Zeros ) ; SDValue High = DAG . getNode ( <STR_LIT> , DL , VT , V , Zeros ) ; Zeros = getZeroVector ( ByteVecVT , Subtarget , DAG , DL ) ; MVT SadVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; Low = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , Low ) , Zeros ) ; High = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , High ) , Zeros ) ; MVT ShortVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , DAG . getBitcast ( ShortVecVT , Low ) , DAG . getBitcast ( ShortVecVT , High ) ) ; return DAG . getBitcast ( VT , V ) ; } assert ( EltVT == <STR_LIT> && <STR_LIT> ) ;

SmallVector < SDValue , <NUM_LIT> > Shifters ( NumElts , DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MFI . initWARegs ( ) ; MachineBasicBlock & EntryMBB = MF . front ( ) ; for ( MachineInstr & MI : EntryMBB ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MI . getOperand ( <NUM_LIT> ) . getReg ( ) << <STR_LIT> << Imm << <STR_LIT> ) ; MFI . setWAReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Imm ) ; break ; } default : break ;


<s> FunctionPass * llvm :: create<ISA_LIT>HardwareLoops ( ) {


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {

return new <ISA_LIT>TargetELFStreamer ( S , STI ) ;


<s> return isImm ( - <NUM_LIT> , <NUM_LIT> ) ;


<s> bool <ISA_LIT>ConstantIslands :: fixupConditionalBr ( ImmBranch & Br ) { MachineInstr * MI = Br . MI ; MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CC = <STR_LIT> ( CC ) ; unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ;


<s> AMDGPUTargetMachine :: AMDGPUTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , TargetOptions Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OptLevel ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OptLevel ) , Subtarget ( TT , CPU , FS , * this ) , IntrinsicInfo ( ) {


<s> static inline bool is_naked_func ( const_tree decl ) { return has_func_attr ( decl , <STR_LIT> ) ;


<s> ensureLocals ( Out ) ; auto Align = <STR_LIT> ( Inst . getOpcode ( ) ) ; if ( Align != - <NUM_LIT> ) { auto & Op0 = Inst . getOperand ( <NUM_LIT> ) ; if ( Op0 . getImm ( ) == - <NUM_LIT> ) Op0 . setImm ( Align ) ; } if ( getSTI ( ) . getTargetTriple ( ) . isArch64Bit ( ) ) { auto Opc64 = <STR_LIT> ( static_cast < uint16_t > ( Inst . getOpcode ( ) ) ) ; if ( Opc64 >= <NUM_LIT> ) { Inst . setOpcode ( Opc64 ) ; } } Out . emitInstruction ( Inst , getSTI ( ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: calculateIndirectAddress ( unsigned RegIndex , unsigned Channel ) const { assert ( Channel == <NUM_LIT> ) ;


<s> } Changed = true ; } } if ( ! UnreachableBlocks . empty ( ) ) { BasicBlock * UnreachableBlock = nullptr ; if ( UnreachableBlocks . size ( ) == <NUM_LIT> ) { UnreachableBlock = UnreachableBlocks . front ( ) ; } else { UnreachableBlock = BasicBlock :: Create ( F . getContext ( ) , <STR_LIT> , & F ) ; new UnreachableInst ( F . getContext ( ) , UnreachableBlock ) ; for ( BasicBlock * BB : UnreachableBlocks ) { BB -> getTerminator ( ) -> eraseFromParent ( ) ; BranchInst :: Create ( UnreachableBlock , BB ) ; } Changed = true ; } if ( ! ReturningBlocks . empty ( ) ) { Type * RetTy = F . getReturnType ( ) ; Value * RetVal = RetTy -> isVoidTy ( ) ? nullptr : UndefValue :: get ( RetTy ) ; UnreachableBlock -> getTerminator ( ) -> eraseFromParent ( ) ; Function * UnreachableIntrin = <STR_LIT> ( F . getParent ( ) , <STR_LIT> ) ; CallInst :: Create ( UnreachableIntrin , { } , <STR_LIT> , UnreachableBlock ) ; ReturnInst :: Create ( F . getContext ( ) , RetVal , UnreachableBlock ) ; ReturningBlocks . push_back ( UnreachableBlock ) ; Changed = true ; } } if ( ReturningBlocks . empty ( ) ) return Changed ; if ( ReturningBlocks . size ( ) == <NUM_LIT> && ! InsertExport ) return Changed ; const TargetTransformInfo & TTI = getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ;

auto BlocksToUnify = std :: move ( ReturningBlocks ) ;


<s> * unavailable |= ~ reg_class_contents [ tmp -> cl ] ; super_class = reg_class_superunion [ ( int ) super_class ] [ ( int ) tmp -> cl ] ; } for ( unsigned i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( fixed_regs [ i ] || global_regs [ i ] ) add_to_hard_reg_set ( unavailable , mode , i ) ; arg_pair_t arg = arg_pair_t ( insn_info , unavailable ) ; tag_map . traverse < arg_pair_t * , check_colliding_tags > ( & arg ) ; ignore_all_aliases ( unavailable , mode , dest & <NUM_LIT> ) ; return super_class ;


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ;

return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> virtual void emitARM64WinCFIAllocStack ( unsigned Size ) {


<s> case Instruction :: Xor : case Instruction :: LShr : case Instruction :: Shl : case Instruction :: Select :


<s> getFunctionAlignment ( const Function * ) const {


<s> CodeObjectMetadataStreamer . end ( ) ;

EmitCodeObjectMetadata ( CodeObjectMetadataStreamer . toYamlString ( ) . get ( ) ) ;


<s> if ( ! ConstSplatVal && ! Ld -> hasNUsesOfValue ( VT . getVectorNumElements ( ) , <NUM_LIT> ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( ! SVOp -> isSplat ( ) ) || SVOp -> getMaskElt ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Sc = Op . getOperand ( <NUM_LIT> ) ; if ( Sc . getOpcode ( ) != <STR_LIT> && Sc . getOpcode ( ) != <STR_LIT> ) { if ( ! Subtarget -> hasInt256 ( ) ) return SDValue ( ) ; if ( VT . is256BitVector ( ) ) Sc = Extract128BitVector ( Sc , <NUM_LIT> , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Sc ) ; } Ld = Sc . getOperand ( <NUM_LIT> ) ; ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; if ( ! ConstSplatVal && ( ! Sc . hasOneUse ( ) || ! Ld . hasOneUse ( ) ) ) return SDValue ( ) ; break ; } } bool Is256 = VT . is256BitVector ( ) ; if ( ConstSplatVal && Subtarget -> hasInt256 ( ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; unsigned ScalarSize = CVT . getSizeInBits ( ) ;

if ( ScalarSize == <NUM_LIT> || ( Is256 && ScalarSize == <NUM_LIT> ) ) {


<s> DataFlowGraph :: DataFlowGraph ( MachineFunction & mf , const TargetInstrInfo & tii , const TargetRegisterInfo & tri , const MachineDominatorTree & mdt , const MachineDominanceFrontier & mdf , const TargetOperandInfo & toi ) : MF ( mf ) , TII ( tii ) , TRI ( tri ) , PRI ( tri , mf ) , MDT ( mdt ) , MDF ( mdf ) , TOI ( toi ) , LiveIns ( PRI ) {


<s> unsigned <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy , const Instruction * I ) { if ( ValTy -> isVectorTy ( ) ) { auto * VecTy = dyn_cast < VectorType > ( ValTy ) ; std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , ValTy ) ; if ( Opcode == Instruction :: FCmp ) return LT . first + <NUM_LIT> * VecTy -> getNumElements ( ) ; } return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , I ) ;


<s> case VAR_DECL : if ( ! TREE_READONLY ( decl ) || TREE_SIDE_EFFECTS ( decl ) || ! DECL_INITIAL ( decl ) || ( DECL_INITIAL ( decl ) != error_mark_node && ! TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) readonly = <NUM_LIT> ; break ; case CONSTRUCTOR : if ( ! TREE_CONSTANT ( decl ) ) readonly = <NUM_LIT> ; break ; default : break ; } if ( TREE_CODE ( decl ) == VAR_DECL ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) switch ( name [ <NUM_LIT> ] ) { case 's' : return saddr_section ; } if ( TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) == ADDR_SPACE_FAR && readonly ) {


<s> StringRef DX10ClampAttr = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( ! DX10ClampAttr . empty ( ) ) DX10Clamp = DX10ClampAttr == <STR_LIT> ; FP32InputDenormals = ST . hasFP32Denormals ( F ) ;


<s> } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0 ) || isa < JumpTableSDNode > ( Opnd0 ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Opnd0 ; return true ; } } const LSBaseSDNode * LS = dyn_cast < LSBaseSDNode > ( Parent ) ;

if ( LS && ( LS -> getMemoryVT ( ) == <STR_LIT> || LS -> getMemoryVT ( ) == <STR_LIT> ) && Subtarget . hasFPIdx ( ) ) return false ;


<s> } else { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; }


<s> Size = <NUM_LIT> ; if ( Bytes . size ( ) < <NUM_LIT> ) return Fail ; Size = <NUM_LIT> ; uint32_t Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ;


<s> void <ISA_LIT>AsmParser :: eatComma ( ) {

if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) {


<s> Result = lowerVECTOR_SHUFFLE_ILVL ( Op , ResTy , Indices , DAG ) ; if ( Result . getNode ( ) ) return Result ; Result = lowerVECTOR_SHUFFLE_ILVR ( Op , ResTy , Indices , DAG ) ; if ( Result . getNode ( ) ) return Result ; Result = lowerVECTOR_SHUFFLE_PCKEV ( Op , ResTy , Indices , DAG ) ; if ( Result . getNode ( ) ) return Result ; Result = lowerVECTOR_SHUFFLE_PCKOD ( Op , ResTy , Indices , DAG ) ; if ( Result . getNode ( ) ) return Result ; return lowerVECTOR_SHUFFLE_VSHF ( Op , ResTy , Indices , DAG ) ;


<s> MVT WideEltVT = WideVT . getVectorElementType ( ) ; if ( ( Subtarget . hasDQI ( ) && WideEltVT . getSizeInBits ( ) >= <NUM_LIT> ) || ( Subtarget . hasBWI ( ) && WideEltVT . getSizeInBits ( ) <= <NUM_LIT> ) ) { V = DAG . getNode ( Op . getOpcode ( ) , dl , WideVT , In ) ; } else { SDValue NegOne = DAG . getConstant ( - <NUM_LIT> , dl , WideVT ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , WideVT ) ; V = DAG . getSelect ( dl , WideVT , In , NegOne , Zero ) ; } if ( VT != ExtVT ) { WideVT = <STR_LIT> ( VTElt , NumElts ) ; V = DAG . getNode ( <STR_LIT> , dl , WideVT , V ) ; } if ( WideVT != VT ) V = DAG . getNode ( <STR_LIT> , dl , VT , V , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return V ;


<s> MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; while ( Branch -> getNumOperands ( ) ) Branch -> removeOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( BRCT ) ) ;

MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ;


<s> void addPRFMOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE -> getValue ( ) >= <NUM_LIT> && CE -> getValue ( ) <= <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ;


<s> return DECL_MD_FUNCTION_CODE ( fndecl ) >= ARM_BUILTIN_vcx1q_p_v16qi ? <NUM_LIT> : <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl , VT , V1 , V2 ) ;


<s> MemIntrinsicSDNode * MIN = dyn_cast < MemIntrinsicSDNode > ( N ) ; SDValue AddrOp ; if ( LDN || ( MIN && MIN -> getOpcode ( ) == <STR_LIT> ) ) AddrOp = N -> getOperand ( <NUM_LIT> ) ; else if ( STN ) AddrOp = STN -> getOperand ( <NUM_LIT> ) ; short Imm = <NUM_LIT> ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( AddrOp . getOpcode ( ) == <STR_LIT> ? AddrOp . getOperand ( <NUM_LIT> ) : AddrOp ) ) { const MachineFrameInfo & MFI = CurDAG -> getMachineFunction ( ) . getFrameInfo ( ) ; unsigned SlotAlign = MFI . getObjectAlign ( FI -> getIndex ( ) ) . value ( ) ; if ( ( SlotAlign % Val ) != <NUM_LIT> ) return false ;

if ( AddrOp . getOpcode ( ) != <STR_LIT> ) return true ;


<s> SDLoc dl ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; DEBUG ( Node -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return nullptr ; } switch ( Node -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , <STR_LIT> ) ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedLoad ( Node ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> :


<s> rtx insn ; gcc_assert ( INTVAL ( cookie ) == <NUM_LIT> ) ; if ( global_tlsarg ) tlsarg = global_tlsarg ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( <NUM_LIT> , call ) ) ; insn = emit_call_insn ( insn ) ;

use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ;


<s> ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = <NUM_LIT> * Subtarget . getVectorLength ( ) ; unsigned VecWidth = VT . getSizeInBits ( ) ; if ( VecWidth >= HwWidth / <NUM_LIT> && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ;


<s> } bool DoXform = false ; bool InvCC = false ; assert ( ( Opc == <STR_LIT> || ( Opc == <STR_LIT> && Slct == N -> getOperand ( <NUM_LIT> ) ) ) && <STR_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( LHS ) -> isNullValue ( ) ) { DoXform = true ; } else if ( CC != <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( RHS ) -> isNullValue ( ) ) { std :: swap ( LHS , RHS ) ; SDValue Op0 = Slct . getOperand ( <NUM_LIT> ) ; EVT OpVT = isSlctCC ? Op0 . getValueType ( ) : Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; bool isInt = OpVT . isInteger ( ) ; CC = <STR_LIT> ( CC , isInt ) ; if ( ! TLI . isCondCodeLegal ( CC , OpVT ) ) return SDValue ( ) ; DoXform = true ; InvCC = true ; }


<s> } OffsetMap [ & B ] = InstOffset ; for ( auto & MI : B . instrs ( ) ) { InstOffset += HII -> getSize ( MI ) ; if ( MI . isBranch ( ) && HII -> isExtendable ( MI ) ) InstOffset += HEXAGON_INSTR_SIZE ; }


<s> enum tail_policy get_prefer_tail_policy ( ) { return TAIL_ANY ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - <NUM_LIT> ) && ( Val <= - <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } } return ; case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) ) { Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } } return ; case 'P' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = C -> getSExtValue ( ) ; if ( ( Val <= <NUM_LIT> ) && ( Val >= <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } } return ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ;


<s> bool hasDstSelForwardingHazard ( ) const { return GFX940Insts ;


<s> <ISA_LIT>PreserveDIType ( ) : FunctionPass ( ID ) {


<s> FPDelta = FrameSize - SEHFrameOffset ; assert ( ( ! MFI . hasCalls ( ) || ( FPDelta % <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; } if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( isAligned ( MFI . getObjectAlign ( FI ) , - ( Offset + StackSize ) ) ) ; return Offset + StackSize ; } } else if ( TRI -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + SlotSize + FPDelta ; } else { assert ( isAligned ( MFI . getObjectAlign ( FI ) , - ( Offset + StackSize ) ) ) ; return Offset + StackSize ; } } else { if ( ! HasFP ) return Offset + StackSize ; Offset += SlotSize ; int TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) Offset -= TailCallReturnAddrDelta ;


<s> MachineBasicBlock * PB = LIS -> getMBBFromIndex ( PE ) ; if ( PB != MB && ! LIS -> isLiveInToMBB ( LID , MB ) ) Undef = true ; } if ( ! Undef ) { makeUndead ( DefR , P -> valno -> def ) ; P -> end = MX ; } else { ImpUse . setIsUndef ( true ) ; } if ( ! MI -> readsRegister ( DefR ) ) MI -> addOperand ( ImpUse ) ; if ( N != LID . end ( ) ) makeDefined ( DefR , N -> start , true ) ; } LiveRange :: Segment NR = LiveRange :: Segment ( MX , EX , VN ) ; LID . addSegment ( NR ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NR << <STR_LIT> << LID << <STR_LIT> ) ; shrinkToUses ( DefR , LID ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; LID . verify ( ) ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || Op . isImplicit ( ) || Op . isUndef ( ) ) continue ; unsigned UseR = Op . getReg ( ) ; LiveInterval & LIU = LIS -> getInterval ( UseR ) ; LiveInterval :: iterator P = LIU . FindSegmentContaining ( MX ) ; if ( P == LIU . end ( ) ) P = prevSegment ( LIU , MX ) ; assert ( P != LIU . end ( ) && <STR_LIT> ) ; SlotIndex EX = P -> end ; if ( EX > MX ) {


<s> return <STR_LIT> ; case CmpInst :: ICMP_EQ : case CmpInst :: FCMP_OEQ : return <STR_LIT> ; case CmpInst :: ICMP_SGT : case CmpInst :: FCMP_OGT : return <STR_LIT> ; case CmpInst :: ICMP_SGE : case CmpInst :: FCMP_OGE : return <STR_LIT> ; case CmpInst :: ICMP_UGT : case CmpInst :: FCMP_UGT : return <STR_LIT> ; case CmpInst :: FCMP_OLT : return <STR_LIT> ; case CmpInst :: ICMP_ULE :


<s> else { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) {

MachineBasicBlock & MBB = * MI . getParent ( ) ;


<s> SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ;

SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ;


<s> if ( CPEs [ j ] . RefCount == <NUM_LIT> && CPEs [ j ] . CPEMI ) { removeDeadCPEMI ( CPEs [ j ] . CPEMI ) ; CPEs [ j ] . CPEMI = NULL ; MadeChange = true ; } } }


<s> Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . getAttributes ( ) . hasFnAttr ( Attribute :: Naked ) ) { return Chain ; } const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned RetOpc = AFI -> isInterruptOrSignalHandler ( ) ? <STR_LIT> : <STR_LIT> ; RetOps [ <NUM_LIT> ] = Chain ;


<s> return ( uint8x8_t ) ( __a > __b ) ;


<s> fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; }


<s> case RTLIB :: MEMSET : AEABILibcall = AEABI_MEMSET ; if ( ConstantSDNode * ConstantSrc = dyn_cast < ConstantSDNode > ( Src ) ) if ( ConstantSrc -> getZExtValue ( ) == <NUM_LIT> ) AEABILibcall = AEABI_MEMCLR ; break ; default : return SDValue ( ) ; } enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = TLI -> getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ;

else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ;


<s> MachineInstrBuilder DstPtr ; if ( Alignment > PtrAlign ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Alignment . value ( ) - <NUM_LIT> ) ; auto ListTmp = MIRBuilder . buildPtrAdd ( PtrTy , List , AlignMinus1 . getReg ( <NUM_LIT> ) ) ; DstPtr = MIRBuilder . buildMaskLowPtrBits ( PtrTy , ListTmp , Log2 ( Alignment ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Alignment , PtrAlign ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrAlign ) ) ; auto NewList = MIRBuilder . buildPtrAdd ( PtrTy , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , PtrSize , PtrAlign ) ) ; MI . eraseFromParent ( ) ;


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return <NUM_LIT> ;


<s> Inst . addOperand ( MCOperand :: createImm ( static_cast < int > ( getComparison ( ) ) ) ) ;


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> if ( Imm . bitwiseIsEqual ( LegalFPImmediates [ i ] ) ) return true ; }


<s> YamlIO . mapOptional ( <STR_LIT> , MFI . WaveLimiter , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . ScratchRSrcReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . ScratchWaveOffsetReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . FrameOffsetReg , StringValue ( <STR_LIT> ) ) ;

YamlIO . mapOptional ( <STR_LIT> , MFI . StackPtrOffsetReg , StringValue ( <STR_LIT> ) ) ;


<s> EmitBinary ( OutStreamer , <STR_LIT> , RS1 , RS2 , RD , STI ) ;


<s> extern __inline __m128d __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_i64gather_pd ( double const * base , __m128i index , const int scale ) { __v2df src = _mm_setzero_pd ( ) ;

__v2df mask = _mm_cmpeq_pd ( src , src ) ;


<s> ConstantSDNode * N = cast < ConstantSDNode > ( S ) ;

int64_t v = ( int64_t ) N -> getSExtValue ( ) ;


<s> bool isSImm14 ( ) const { return Kind == K_Immediate ;


<s> if ( Subtarget -> hasV8Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV7Ops ( ) ) { if ( Subtarget -> isMClass ( ) && Subtarget -> hasThumb2DSP ( ) ) return <STR_LIT> ; return <STR_LIT> ; } else if ( Subtarget -> hasV6T2Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6MOps ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV6Ops ( ) ) return <STR_LIT> ; else if ( Subtarget -> hasV5TEOps ( ) ) return <STR_LIT> ;

else if ( Subtarget -> hasV5TOps ( ) ) return <STR_LIT> ;


<s> return emitAddSub_ri ( false , RetVT , LHSReg , Imm , true , false ) != <NUM_LIT> ;


<s> FunctionPass * create<ISA_LIT>CommonGEP ( ) { return new <ISA_LIT>CommonGEP ( ) ;


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( TM . getSubtargetImpl ( ) -> isDarwin ( ) && <STR_LIT> ) ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; SpillsVRS = true ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> } else if ( OVT == <STR_LIT> ) { INTTY = <STR_LIT> ; } SDValue LHS = DAG . getSExtOrTrunc ( Op . getOperand ( <NUM_LIT> ) , DL , INTTY ) ; SDValue RHS = DAG . getSExtOrTrunc ( Op . getOperand ( <NUM_LIT> ) , DL , INTTY ) ; LHS = DAG . getNode ( <STR_LIT> , DL , INTTY , LHS , RHS ) ; LHS = DAG . getSExtOrTrunc ( LHS , DL , OVT ) ; return LHS ;


<s> const IntrinsicVector & getTrunc16_8 ( ) const {


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> mmix_output_shifted_value ( stream , ~ ( uint64_t ) value ) ; fprintf ( stream , <STR_LIT> , reg_names [ regno ] , reg_names [ regno ] ) ; } else { static const char * const higher_parts [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * op = <STR_LIT> ; const char * line_begin = <STR_LIT> ; int insns = <NUM_LIT> ; int i ; int64_t tmpvalue = value ; for ( i = <NUM_LIT> ; i < <NUM_LIT> && tmpvalue != <NUM_LIT> ; i ++ ) { if ( tmpvalue & <NUM_LIT> ) insns ++ ; tmpvalue >>= <NUM_LIT> ; } if ( TARGET_BASE_ADDRESSES && insns == <NUM_LIT> ) { fprintf ( stream , <STR_LIT> , reg_names [ regno ] ) ; mmix_output_octa ( stream , value , <NUM_LIT> ) ; } else { for ( i = <NUM_LIT> ; i < <NUM_LIT> && value != <NUM_LIT> ; i ++ ) { if ( value & <NUM_LIT> ) {

fprintf ( stream , <STR_LIT> , line_begin , op , higher_parts [ i ] , reg_names [ regno ] , ( int ) ( value & <NUM_LIT> ) ) ;


<s> _cmpccxadd_epi64 ( long long * __A , long long __B , long long __C , const _CMPCCX_ENUM __D ) { return __builtin_ia32_cmpccxadd64 ( __A , __B , __C , __D ) ;


<s> for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getThe<ISA_LIT>Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ;

TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ;


<s> if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_NONE ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_32 ) . Case ( <STR_LIT> , ELF :: R_<ISA_LIT>_64 ) . Default ( - <NUM_LIT> ) ;

if ( Type != - <NUM_LIT> ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ;


<s> void * RelocPos = ( char * ) Function + MR -> getMachineCodeOffset ( ) ; intptr_t ResultPtr = resolveRelocDestAddr ( MR ) ; switch ( ( <STR_LIT> ) MR -> getRelocationType ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> ; if ( ResultPtr >= <NUM_LIT> ) * ( ( intptr_t * ) RelocPos ) |= <NUM_LIT> << <STR_LIT> ; else { * ( ( intptr_t * ) RelocPos ) &= ~ ( <NUM_LIT> << <STR_LIT> ) ; ResultPtr = - ResultPtr ; } if ( MR -> getRelocationType ( ) == <STR_LIT> ) ResultPtr = ResultPtr >> <NUM_LIT> ; * ( ( intptr_t * ) RelocPos ) |= ResultPtr ; * ( ( intptr_t * ) RelocPos ) |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( <STR_LIT> ) << <STR_LIT> ; break ; } case <STR_LIT> :


<s> if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) && pdp11_small_shift ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) shift_size *= INTVAL ( operands [ <NUM_LIT> ] ) ;


<s> TmpInst . addOperand ( MCOperand :: createImm ( Imm1 ) ) ; TmpInst . addOperand ( MCOperand :: createImm ( Imm2 ) ) ; TmpInst . setLoc ( IDLoc ) ;

getStreamer ( ) . emitInstruction ( TmpInst , * STI ) ;


<s> FunctionPass * llvm :: createMachineInstPrint ( ) { return new MachineInstPrint ( ) ;


<s> asm_fprintf ( f , <STR_LIT> ) ; if ( TARGET_ILP32 ) { asm_fprintf ( f , <STR_LIT> , IP1_REGNUM - R0_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , STATIC_CHAIN_REGNUM - R0_REGNUM ) ; } else { asm_fprintf ( f , <STR_LIT> , reg_names [ IP1_REGNUM ] ) ; asm_fprintf ( f , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] ) ; } asm_fprintf ( f , <STR_LIT> , reg_names [ IP1_REGNUM ] ) ; asm_fprintf ( f , <STR_LIT> ) ; assemble_aligned_integer ( POINTER_BYTES , const0_rtx ) ;


<s> rtx insn , test ; emit_insn_before ( gen_addsi3 ( loop -> iter_reg , loop -> iter_reg , constm1_rtx ) , loop -> loop_end ) ; test = gen_rtx_NE ( VOIDmode , loop -> iter_reg , const0_rtx ) ; insn = emit_jump_insn_before ( gen_cbranchsi4 ( test , loop -> iter_reg , const0_rtx , loop -> start_label ) , loop -> loop_end ) ; JUMP_LABEL ( insn ) = loop -> start_label ; LABEL_NUSES ( loop -> start_label ) ++ ; delete_insn ( loop -> loop_end ) ; } else {


<s> <ISA_LIT>MachObjectWriter ( bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) : MCMachObjectTargetWriter ( Is64Bit , CPUType , CPUSubtype , Is64Bit ) {


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;


<s> I . getOperand ( <NUM_LIT> ) . setReg ( AndResult ) ; auto InsertBefore = std :: next ( I . getIterator ( ) ) ; auto SubI = BuildMI ( MBB , InsertBefore , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( SExtResult ) . addUse ( AndResult ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; if ( ! constrainSelectedInstRegOperands ( * SubI , TII , TRI , RBI ) ) return false ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpc = selectSimpleExtOpc ( I . getOpcode ( ) , SrcSize ) ; if ( NewOpc == I . getOpcode ( ) ) return false ; I . setDesc ( TII . get ( NewOpc ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } break ; } case G_ADD : case G_GEP : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_FADD : if ( ! selectFAdd ( MIB , TII , MRI ) ) return false ; break ; case G_FRAME_INDEX : I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; case G_CONSTANT : { unsigned Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . getType ( Reg ) . getSizeInBits ( ) != <NUM_LIT> ) return false ; assert ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; I . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; break ; } case G_STORE :


<s> label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_TLS_LABEL ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( reloc ) , label ) , UNSPEC_TLS ) ; tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( reg , unspec ) ; emit_move_insn ( tmp , label ) ; emit_insn ( gen_addsi3 ( reg , reg , tmp ) ) ; * valuep = emit_library_call_value ( get_tls_get_addr ( ) , NULL_RTX , LCT_PURE , Pmode , reg , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) {


<s> } else if ( TypeStr . startswith ( <STR_LIT> ) ) { Type = Type :: getHalfTy ( Ctx ) ; TypeStr = TypeStr . substr ( strlen ( <STR_LIT> ) ) ; } else if ( TypeStr . startswith ( <STR_LIT> ) ) { Type = StructType :: create ( Ctx , <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( TypeStr . startswith ( <STR_LIT> ) ) { TypeStr = TypeStr . substr ( strlen ( <STR_LIT> ) ) ; TypeStr = TypeStr . substr ( <NUM_LIT> , TypeStr . find ( ']' ) ) ; } TypeStr . getAsInteger ( <NUM_LIT> , VecElts ) ; auto SpirvTy = getOrCreate<ISA_LIT>Type ( Type , MIRBuilder ) ; if ( VecElts > <NUM_LIT> ) SpirvTy = getOrCreate<ISA_LIT>VectorType ( SpirvTy , VecElts , MIRBuilder ) ;


<s> if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ;

SrcReg = SDValue ( Result , <NUM_LIT> ) ;


<s> func -> push_back ( newBlk ) ; for ( MachineBasicBlock :: iterator iter = srcBlk -> begin ( ) , iterEnd = srcBlk -> end ( ) ; iter != iterEnd ; ++ iter ) {

MachineInstr * instr = func -> CloneMachineInstr ( iter ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>leAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU , const MCTargetOptions & Options ) { if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , MRI ) ;

if ( TheTriple . isOSBinFormatCOFF ( ) ) return new COFF<ISA_LIT>AsmBackend ( T , TheTriple ) ;


<s> bool FrameObjectCompare ( const FrameObject & A , const FrameObject & B ) { return std :: make_tuple ( ! A . IsValid , A . ObjectFirst , A . GroupFirst , A . GroupIndex , A . ObjectIndex ) < std :: make_tuple ( ! B . IsValid , B . ObjectFirst , B . GroupFirst , B . GroupIndex , B . ObjectIndex ) ;


<s> else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; assert ( Opc && <STR_LIT> ) ;

MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ;


<s> if ( ! Op ) continue ; return true ; } return false ; } ; auto IsExpiredFn = [ ] ( MachineInstr * MI , int ) { return MI && ( <ISA_LIT>InstrInfo :: isVALU ( * MI ) || ( MI -> getOpcode ( ) == <STR_LIT> && ! MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) || ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) ; } ;

if ( :: getWaitStatesSince ( IsHazardFn , MI , IsExpiredFn ) == std :: numeric_limits < int > :: max ( ) ) return false ;


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( MachineInstr * MI ) const {


<s> if ( A -> modifiesRegister ( ExecReg , TRI ) ) return false ; if ( A -> modifiesRegister ( CondReg , TRI ) ) { if ( ! A -> definesRegister ( CondReg , TRI ) || A -> getOpcode ( ) != And ) return false ; break ; } ReadsCond |= A -> readsRegister ( CondReg , TRI ) ; } if ( A == E ) return false ; MachineOperand & Op1 = A -> getOperand ( <NUM_LIT> ) ; MachineOperand & Op2 = A -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getReg ( ) != ExecReg && Op2 . isReg ( ) && Op2 . getReg ( ) == ExecReg ) { TII -> commuteInstruction ( * A ) ; Changed = true ; } if ( Op1 . getReg ( ) != ExecReg ) return Changed ; if ( Op2 . isImm ( ) && Op2 . getImm ( ) != - <NUM_LIT> ) return Changed ; Register SReg ; if ( Op2 . isReg ( ) ) { SReg = Op2 . getReg ( ) ; auto M = std :: next ( A ) ; bool ReadsSreg = false ; for ( ; M != E ; ++ M ) { if ( M -> definesRegister ( SReg , TRI ) ) break ; if ( M -> modifiesRegister ( SReg , TRI ) ) return Changed ; ReadsSreg |= M -> readsRegister ( SReg , TRI ) ; } if ( M == E || ! M -> isMoveImmediate ( ) || ! M -> getOperand ( <NUM_LIT> ) . isImm ( ) || M -> getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return Changed ; if ( ! ReadsSreg && Op2 . isKill ( ) ) { A -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( - <NUM_LIT> ) ; M -> eraseFromParent ( ) ; } } if ( ! ReadsCond && A -> registerDefIsDead ( <STR_LIT> ) && MI . killsRegister ( CondReg , TRI ) ) A -> eraseFromParent ( ) ; bool IsVCCZ = MI . getOpcode ( ) == <STR_LIT> ; if ( SReg == ExecReg ) { if ( IsVCCZ ) { MI . eraseFromParent ( ) ; return true ; } MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; } else { MI . setDesc ( TII -> get ( IsVCCZ ? <STR_LIT> : <STR_LIT> ) ) ; }

MI . RemoveOperand ( MI . findRegisterUseOperandIdx ( CondReg , false , TRI ) ) ;


<s> addPass ( & <ISA_LIT>PerfHintAnalysisID ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; if ( EnableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ;


<s> expand_float ( out , in , <NUM_LIT> ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( inmode , LSHIFTRT , in , const1_rtx , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; i1 = expand_simple_binop ( inmode , AND , in , const1_rtx , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; i0 = expand_simple_binop ( inmode , IOR , i0 , i1 , i0 , <NUM_LIT> , OPTAB_DIRECT ) ; expand_float ( f0 , i0 , <NUM_LIT> ) ;

emit_insn ( gen_rtx_SET ( out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ;


<s> const <ISA_LIT>GOTPLT & <ISA_LIT>LDBackend :: getGOTPLT ( ) const { assert ( m_pGOTPLT != NULL ) ; return * m_pGOTPLT ;


<s> case <STR_LIT> : if ( Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> Opc = Is32BitInt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsZExt ? ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) : ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) ) ; break ; case <STR_LIT> : Opc = ( IsZExt ? ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) : ( Is32BitInt ? <STR_LIT> : <STR_LIT> ) ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( ( Addr . Offset & <NUM_LIT> ) != <NUM_LIT> ) ) UseOffset = false ; break ; case <STR_LIT> : Opc = <STR_LIT> ; assert ( UseRC -> hasSuperClassEq ( & <STR_LIT> ) && <STR_LIT> ) ; UseOffset = ( ( Addr . Offset & <NUM_LIT> ) == <NUM_LIT> ) ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = FP64LoadOpc ; break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , VT , UseOffset , IndexReg ) ; if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ;


<s> void setKind ( BaseKind K ) { Kind = K ;


<s> Register ( llvm :: Register R , unsigned S ) : Reg ( R ) , Sub ( S ) {


<s> unsigned <ISA_LIT>SEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , DebugLoc DL , unsigned * NewImm ) const { <ISA_LIT>AnalyzeImmediate AnalyzeImm ; const <ISA_LIT>Subtarget & STI = Subtarget ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned LUi = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZEROReg = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; bool LastInstrIsADDiu = NewImm ; const <ISA_LIT>AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > <NUM_LIT> ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ;

else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ;


for ( auto & IPAndShapes : PosAndShapes ) addTileConfig ( IPAndShapes . first , IPAndShapes . second ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget . isAIXABI ( ) ) return LowerGlobalTLSAddressAIX ( Op , DAG ) ;

return LowerGlobalTLSAddressLinux ( Op , DAG ) ;


<s> } if ( VectorComponents > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = RI . getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else {

MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , <STR_LIT> , DestReg , SrcReg ) ;


<s> unsigned Opc = MI -> getOpcode ( ) ; unsigned PredOpc = HII -> getCondOpcode ( Opc , ! Cond ) ; MachineInstrBuilder MB = BuildMI ( B , Where , DL , HII -> get ( PredOpc ) ) ; unsigned Ox = <NUM_LIT> , NP = MI -> getNumOperands ( ) ; while ( Ox < NP ) { MachineOperand & MO = MI -> getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) break ; Ox ++ ; } MB . addReg ( DefOp . getReg ( ) , getRegState ( DefOp ) , DefOp . getSubReg ( ) ) ; MB . addReg ( PredOp . getReg ( ) , PredOp . isUndef ( ) ? RegState :: Undef : <NUM_LIT> , PredOp . getSubReg ( ) ) ; while ( Ox < NP ) { MachineOperand & MO = MI -> getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) MB . addOperand ( MO ) ; Ox ++ ; } MachineFunction & MF = * B . getParent ( ) ; MachineInstr :: mmo_iterator I = MI -> memoperands_begin ( ) ; unsigned NR = std :: distance ( I , MI -> memoperands_end ( ) ) ; MachineInstr :: mmo_iterator MemRefs = MF . allocateMemRefsArray ( NR ) ; for ( unsigned i = <NUM_LIT> ; i < NR ; ++ i ) MemRefs [ i ] = * I ++ ; MB . setMemRefs ( MemRefs , MemRefs + NR ) ; MachineInstr * NewI = MB ; NewI -> clearKillInfo ( ) ; LIS -> InsertMachineInstrInMaps ( * NewI ) ;

for ( auto & Op : NewI -> operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ;


<s> if ( ! IsTailCall ) return IsIndirect ? getBLRCallOpcode ( CallerF ) : ( unsigned ) <STR_LIT> ;


<s> ~ <ISA_LIT>FrameLowering ( ) override {


<s> static bool arm_evpc_neon_vtbl ( struct expand_vec_perm_d * d ) { rtx rperm [ MAX_VECT_LEN ] , sel ; machine_mode vmode = d -> vmode ; unsigned int i , nelt = d -> perm . length ( ) ;


<s> } else { ++ I ; } continue ; } else if ( Opc == AMDGPU :: DS_WRITE_B32 || Opc == AMDGPU :: DS_WRITE_B64 ) { unsigned Size = ( Opc == AMDGPU :: DS_WRITE_B64 ) ? <NUM_LIT> : <NUM_LIT> ; MachineBasicBlock :: iterator Match = findMatchingD<ISA_LIT>nst ( I , Size ) ; if ( Match != E ) { Modified = true ;

I = mergeWrite2Pair ( I , Match , Size ) ;


<s> MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ;


<s> Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; } Inst . addOperand ( MCOperand :: createImm ( Code ) ) ; return MCDisassembler :: Success ;


<s> void c6x_set_return_address ( rtx source , rtx scratch ) { struct c6x_frame frame ; rtx addr ; HOST_WIDE_INT offset ; c6x_compute_frame_layout ( & frame ) ; if ( ! c6x_save_reg ( RETURN_ADDR_REGNO ) ) emit_move_insn ( gen_rtx_REG ( Pmode , RETURN_ADDR_REGNO ) , source ) ; else { if ( frame_pointer_needed ) { addr = hard_frame_pointer_rtx ; offset = frame . b3_offset ; }


<s> if ( CostKind == TTI :: TCK_RecipThroughput && ( ST -> hasNEON ( ) || ST -> hasMVEIntegerOps ( ) ) ) { return <NUM_LIT> ; }

return BaseT :: getCFInstrCost ( Opcode , CostKind , I ) ;


<s> if ( isAllOnes ( Mask ) ) return Op ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ;

SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ;


<s> SDValue CondRes = Op . getOperand ( <NUM_LIT> ) ; SDValue CCNode = CondRes . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue ( ) ; SDValue BrCode = DAG . getConstant ( GetFPBranchCodeFromCond ( CC ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , BrCode , Dest , CondRes ) ;


<s> if ( PreferredWidth >= <NUM_LIT> && ST -> hasAVX512 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( PreferredWidth >= <NUM_LIT> && ST -> hasAVX2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( PreferredWidth >= <NUM_LIT> && ST -> hasSSE2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . AllowOverlappingLoads = true ; } if ( ST -> is64Bit ( ) ) { Options . LoadSizes . push_back ( <NUM_LIT> ) ; } Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . LoadSizes . push_back ( <NUM_LIT> ) ; Options . LoadSizes . push_back ( <NUM_LIT> ) ; return Options ;


<s> } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) > - <NUM_LIT> && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && push_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( unsigned ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( unsigned ) INTVAL ( operands [ <NUM_LIT> ] ) >= <NUM_LIT> && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && ( ( INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) > - <NUM_LIT> ) || REGNO ( operands [ <NUM_LIT> ] ) > <NUM_LIT> ) ) return <STR_LIT> ; return <STR_LIT> ; case HImode : if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( operands [ <NUM_LIT> ] == const1_rtx ) return <STR_LIT> ; if ( operands [ <NUM_LIT> ] == constm1_rtx ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( unsigned ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( unsigned ) ( - INTVAL ( operands [ <NUM_LIT> ] ) ) < <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ; case QImode : if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( operands [ <NUM_LIT> ] == const1_rtx ) return <STR_LIT> ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned RBegin , REnd ; if ( InRegsParamRecordIdx < CCInfo . getInRegsParamsCount ( ) ) { CCInfo . getInRegsParamInfo ( InRegsParamRecordIdx , RBegin , REnd ) ; } else { unsigned RBeginIdx = CCInfo . getFirstUnallocated ( GPRArgRegs ) ; RBegin = RBeginIdx == <NUM_LIT> ? ( unsigned ) <STR_LIT> : GPRArgRegs [ RBeginIdx ] ; REnd = <STR_LIT> ; } if ( REnd != RBegin ) ArgOffset = - <NUM_LIT> * ( <STR_LIT> - RBegin ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; int FrameIndex = MFI -> CreateFixedObject ( ArgSize , ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , PtrVT ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; const TargetRegisterClass * RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ;

for ( unsigned Reg = RBegin , i = <NUM_LIT> ; Reg < REnd ; ++ Reg , ++ i ) {


<s> AU . addRequired < TargetTransformInfoWrapperPass > ( ) ;


<s> switch ( MO . getTargetFlags ( ) & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: createLower16 ( Expr , OutContext ) ;


<s> rtx next = plus_constant ( Pmode , XEXP ( pointer , <NUM_LIT> ) , amount ) ;

return adjust_automodify_address ( pointer , GET_MODE ( pointer ) , next , amount ) ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( mode == VOIDmode ) return const0_rtx ;

if ( targetm . calls . must_pass_in_stack ( mode , type ) || * cum + XSTORMY16_WORD_SIZE ( type , mode ) > NUM_ARGUMENT_REGISTERS ) return NULL_RTX ;


<s> auto & MRI = * MIB . getMRI ( ) ; LLT OpTy = MRI . getType ( LHS ) ; assert ( OpTy . getSizeInBits ( ) == <NUM_LIT> || OpTy . getSizeInBits ( ) == <NUM_LIT> ) ; unsigned CCmpOpc ; if ( CmpInst :: isIntPredicate ( CC ) ) { CCmpOpc = OpTy . getSizeInBits ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else { switch ( OpTy . getSizeInBits ( ) ) { case <NUM_LIT> :


<s> if ( StackSize ) SPReg = MRI . createVirtualRegister ( PtrRC ) ; const char * ES = <STR_LIT> ; auto * SPSymbol = MF . createExternalSymbolName ( ES ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addExternalSymbol ( SPSymbol ) ; bool HasBP = hasBP ( MF ) ; if ( HasBP ) { auto FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned BasePtr = MRI . createVirtualRegister ( PtrRC ) ; FI -> setBasePointerVreg ( BasePtr ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , BasePtr ) . addReg ( SPReg ) ; } if ( StackSize ) { unsigned OffsetReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( StackSize ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SPReg ) . addReg ( OffsetReg ) ; } if ( HasBP ) { unsigned BitmaskReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned Alignment = MFI . getMaxAlignment ( ) ; assert ( ( <NUM_LIT> << countTrailingZeros ( Alignment ) ) == Alignment && <STR_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , BitmaskReg ) . addImm ( ( int ) ~ ( Alignment - <NUM_LIT> ) ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( BitmaskReg ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } if ( StackSize && needsSPWriteback ( MF ) ) { writeSPToGlobal ( <STR_LIT> , MF , MBB , InsertPt , DL ) ;


<s> unsigned Opc8 ; const SDNode * N = Op . getNode ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( N ) ; assert ( isPowerOf2_32 ( VT . getSizeInBits ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { SDValue Amt = N -> getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; Amt = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , dl , AmtVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , Amt ) ; } case <STR_LIT> : { SDValue Amt = N -> getOperand ( <NUM_LIT> ) ;


<s> MCAsmLexer & Lexer = getLexer ( ) ; SMLoc StartLoc = Lexer . getLoc ( ) ; bool flag = false ; if ( Lexer . is ( AsmToken :: Exclaim ) ) { flag = true ; Lexer . Lex ( ) ; } SMLoc RegLoc = Lexer . getLoc ( ) ; if ( ParseRegister ( Operands ) ) { return true ; } if ( checkClass ) { <ISA_LIT>Operand * Op = ( <ISA_LIT>Operand * ) Operands . back ( ) ; if ( ! Op -> isReg ( ) ) return Error ( Lexer . getLoc ( ) , <STR_LIT> ) ; if ( <ISA_LIT>InstPrinter :: getRegisterName ( Op -> getReg ( ) ) [ <NUM_LIT> ] != 'p' ) { if ( flag ) { Error ( StartLoc , <STR_LIT> ) ;


<s> assert ( MO2 . getReg ( ) && <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ; unsigned ShAmt = MO3 . getImm ( ) ; if ( ShAmt ) { assert ( ShAmt <= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << ShAmt << markup ( <STR_LIT> ) ; }

O << <STR_LIT> << markup ( <STR_LIT> ) ;


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned FrameReg = <STR_LIT> ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue FrameAddr ; if ( depth == <NUM_LIT> ) FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; else { SDValue Chain = getFLUSHW ( Op , DAG ) ;

FrameAddr = DAG . getCopyFromReg ( Chain , dl , FrameReg , VT ) ;


<s> else abi = <STR_LIT> ; return build_string_literal ( strlen ( abi ) + <NUM_LIT> , abi ) ;


<s> if ( auto * CI = dyn_cast < CallInst > ( & * U ) ) {

auto * Caller = CI -> getParent ( ) -> getParent ( ) ;


<s> TokOp -> Tok . Data = Token . data ( ) ; TokOp -> Tok . Length = Token . size ( ) ;


<s> Value * <ISA_LIT>IREmitter :: visitWrapper ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned RegNo = getRegPair ( ) ;

Inst . addOperand ( MCOperand :: CreateReg ( RegNo ++ ) ) ;


<s> const <ISA_LIT>FunctionInfo & MFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( needsSP ( MF ) && MFI . isFrameBaseVirtual ( ) ) { unsigned LocalNum = MFI . getFrameBaseLocal ( ) ; Loc . Location . WasmLoc = { <STR_LIT> , LocalNum } ; } else { Loc . Location . WasmLoc = { <STR_LIT> , <NUM_LIT> } ; } return Loc ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> unsigned TargetFlags = get ( Opcode ) . TSFlags ; return ( TargetFlags & <STR_LIT> ) ;


<s> return ! optimize || c4x_valid_operands ( code , operands , mode , <NUM_LIT> ) ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ;


<s> if ( SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> ) ) { SDLoc DL ( Op ) ;

SDValue FpToInt32 = DAG . getNode ( Op . getOpcode ( ) , DL , <STR_LIT> , Src ) ;


<s> DEBUG_WITH_TYPE ( <STR_LIT> , { dbgs ( ) << __func__ << '\n' ; } ) ; int VecLen = SM . Mask . size ( ) ; assert ( <NUM_LIT> * HwLen == unsigned ( VecLen ) && <STR_LIT> ) ; std :: pair < int , unsigned > Strip = findStrip ( SM . Mask , <NUM_LIT> , VecLen ) ; if ( Strip . first != <NUM_LIT> ) return OpRef :: fail ( ) ; if ( Strip . second != <NUM_LIT> && Strip . second != <NUM_LIT> ) return OpRef :: fail ( ) ; int N = VecLen ; int L = Strip . second ; for ( int I = <NUM_LIT> * L ; I < <NUM_LIT> * N ; I += <NUM_LIT> * L ) { auto S = findStrip ( SM . Mask . drop_front ( I ) , <NUM_LIT> , N - I ) ; if ( S . second != unsigned ( L ) ) return OpRef :: fail ( ) ; if ( <NUM_LIT> * S . first != I ) return OpRef :: fail ( ) ; } for ( int I = L ; I < <NUM_LIT> * N ; I += <NUM_LIT> * L ) { auto S = findStrip ( SM . Mask . drop_front ( I ) , <NUM_LIT> , N - I ) ; if ( S . first != - <NUM_LIT> || S . second != unsigned ( L ) ) return OpRef :: fail ( ) ; } unsigned Opc = Strip . second == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Results . push ( Opc , getPairVT ( <STR_LIT> ) , { Va } ) ; return OpRef :: res ( Results . top ( ) ) ;


<s> virtual const DataLayout * getDataLayout ( ) const {


<s> __ev64_opaque__ t ; t = __ev_mwhssf ( a , b ) ;

return __ev_mwsmian ( t , ( ( __ev64_s32__ ) { <NUM_LIT> , <NUM_LIT> } ) ) ;


<s> switch ( static_cast < uint32_t > ( getKind ( ) ) ) { case VK_CALL : return <STR_LIT> ; case VK_LO12 : return <STR_LIT> ; case VK_ABS_G3 : return <STR_LIT> ; case VK_ABS_G2 : return <STR_LIT> ; case VK_ABS_G2_S : return <STR_LIT> ; case VK_ABS_G2_NC : return <STR_LIT> ; case VK_ABS_G1 : return <STR_LIT> ; case VK_ABS_G1_S : return <STR_LIT> ; case VK_ABS_G1_NC : return <STR_LIT> ; case VK_ABS_G0 : return <STR_LIT> ; case VK_ABS_G0_S : return <STR_LIT> ; case VK_ABS_G0_NC : return <STR_LIT> ; case VK_DTPREL_G2 : return <STR_LIT> ; case VK_DTPREL_G1 : return <STR_LIT> ; case VK_DTPREL_G1_NC : return <STR_LIT> ; case VK_DTPREL_G0 : return <STR_LIT> ; case VK_DTPREL_G0_NC : return <STR_LIT> ;

case VK_DTPREL_HI12 : return <STR_LIT> ;


<s> if ( NumElts == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) { if ( InVT == <STR_LIT> ) { InVT = <STR_LIT> ; In = DAG . getNode ( <STR_LIT> , DL , InVT , In ) ; } SDValue Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ) ; } MVT EltVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ( <NUM_LIT> / NumElts ) ; MVT ExtVT = <STR_LIT> ( EltVT , NumElts ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , In ) ; InVT = ExtVT ; ShiftInx = InVT . getScalarSizeInBits ( ) - <NUM_LIT> ; } if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) { In = DAG . getNode ( <STR_LIT> , DL , InVT , In , DAG . getConstant ( ShiftInx , DL , InVT ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , In , In ) ;


<s> <ISA_LIT>32TargetMachine :: <ISA_LIT>32TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>TargetMachine ( T , TT , FS , false ) {


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : MF ( MF ) {


<s> SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; DebugLoc dl = SVOp -> getDebugLoc ( ) ; MVT VT = SVOp -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; unsigned MaskValue = <NUM_LIT> ; unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) {

int SndLaneEltIdx = ( NumLanes == <NUM_LIT> ) ? SVOp -> getMaskElt ( i + NumElemsInLane ) : - <NUM_LIT> ;


<s> if ( optimize_size ) { bool src_aligned = MEM_ALIGN ( operands [ <NUM_LIT> ] ) >= BITS_PER_WORD ; bool dst_aligned = MEM_ALIGN ( operands [ <NUM_LIT> ] ) >= BITS_PER_WORD ; unsigned int interleave_factor = ( src_aligned || dst_aligned ) ? <NUM_LIT> : <NUM_LIT> ; HOST_WIDE_INT bytes_per_iter = ( src_aligned || dst_aligned ) ? <NUM_LIT> : <NUM_LIT> ; if ( length > <NUM_LIT> ) arm_block_move_unaligned_loop ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , interleave_factor , bytes_per_iter ) ; else arm_block_move_unaligned_straight ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , interleave_factor ) ; } else { if ( length > <NUM_LIT> ) arm_block_move_unaligned_loop ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , <NUM_LIT> , <NUM_LIT> ) ;

else arm_block_move_unaligned_straight ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , <NUM_LIT> ) ;


<s> int32_t lo = Imm & <NUM_LIT> ; NewImm = lo ; int Reg = <NUM_LIT> ; int SpReg = <NUM_LIT> ; rs . enterBasicBlock ( & MBB ) ; rs . forward ( II ) ; BitVector Candidates = RI . getAllocatableSet ( * II -> getParent ( ) -> getParent ( ) , & <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; } int DefReg = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { DefReg = MO . getReg ( ) ; break ; } } BitVector Available = rs . getRegsAvailable ( & <STR_LIT> ) ; Available &= Candidates ; unsigned FirstRegSaved = <NUM_LIT> , SecondRegSaved = <NUM_LIT> ; unsigned FirstRegSavedTo = <NUM_LIT> , SecondRegSavedTo = <NUM_LIT> ; Reg = Available . find_first ( ) ; if ( Reg == - <NUM_LIT> ) { Reg = Candidates . find_first ( ) ; Candidates . reset ( Reg ) ; if ( DefReg != Reg ) { FirstRegSaved = Reg ; FirstRegSavedTo = <STR_LIT> ; copyPhysReg ( MBB , II , DL , FirstRegSavedTo , FirstRegSaved , true ) ; } } else Available . reset ( Reg ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Imm ) . addImm ( - <NUM_LIT> ) ; NewImm = <NUM_LIT> ; if ( FrameReg == <STR_LIT> ) { SpReg = Available . find_first ( ) ; if ( SpReg == - <NUM_LIT> ) { SpReg = Candidates . find_first ( ) ; if ( DefReg != SpReg ) { SecondRegSaved = SpReg ; SecondRegSavedTo = <STR_LIT> ; } if ( SecondRegSaved ) copyPhysReg ( MBB , II , DL , SecondRegSavedTo , SecondRegSaved , true ) ; } else Available . reset ( SpReg ) ; copyPhysReg ( MBB , II , DL , SpReg , <STR_LIT> , false ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addReg ( SpReg , RegState :: Kill ) . addReg ( Reg ) ; }

else BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addReg ( FrameReg ) . addReg ( Reg , RegState :: Kill ) ;


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { addPass ( create<ISA_LIT>FMAoptPass ( ) ) ; addPass ( create<ISA_LIT>UnbranchPass ( ) ) ; } addPass ( create<ISA_LIT>SelectorPreshaper ( ) ) ; addPass ( create<ISA_LIT>SingleUseScalarOptimizer ( ) ) ;

addPass ( createAggressiveDCEPass ( ) ) ;


<s> insn_op = & insn_data [ icode ] . operand [ nopnds ] ; op [ nopnds ] = expand_normal ( arg ) ; if ( ! ( * insn_op -> predicate ) ( op [ nopnds ] , insn_op -> mode ) ) { if ( ! strcmp ( insn_op -> constraint , <STR_LIT> ) ) { int arg_num = ( nonvoid ) ? nopnds : nopnds + <NUM_LIT> ; if ( ! CONST_INT_P ( op [ nopnds ] ) ) error ( <STR_LIT> , arg_num ) ; else error ( <STR_LIT> <STR_LIT> , arg_num ) ; return const0_rtx ; } op [ nopnds ] = copy_to_mode_reg ( insn_op -> mode , op [ nopnds ] ) ; } nopnds ++ ; } switch ( fcode ) { case HTM_BUILTIN_TENDALL : case HTM_BUILTIN_TRESUME : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; if ( flag_checking ) attr |= RS6000_BTC_UNARY ; break ; case HTM_BUILTIN_TSUSPEND : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; if ( flag_checking ) attr |= RS6000_BTC_UNARY ; break ; default : break ; } if ( uses_spr ) { machine_mode mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; op [ nopnds ++ ] = gen_rtx_CONST_INT ( mode , htm_spr_num ( fcode ) ) ; } else if ( attr & RS6000_BTC_CR ) { cr = gen_reg_rtx ( CCmode ) ; op [ nopnds ++ ] = cr ; } if ( flag_checking ) { int expected_nopnds = <NUM_LIT> ; if ( ( attr & RS6000_BTC_OPND_MASK ) == RS6000_BTC_UNARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_OPND_MASK ) == RS6000_BTC_BINARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_OPND_MASK ) == RS6000_BTC_TERNARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_QUATERNARY ) expected_nopnds = <NUM_LIT> ; if ( ! ( attr & RS6000_BTC_VOID ) ) expected_nopnds += <NUM_LIT> ; if ( uses_spr ) expected_nopnds += <NUM_LIT> ; gcc_assert ( nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS ) ; } switch ( nopnds ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ;


<s> if ( Subtarget . isRV64 ( ) ) return <STR_LIT> ;


<s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : MF ( MF ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) {


<s> getBitfieldInvertedMaskOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; uint32_t v = ~ MO . getImm ( ) ; uint32_t lsb = countTrailingZeros ( v ) ; uint32_t msb = ( <NUM_LIT> - countLeadingZeros ( v ) ) - <NUM_LIT> ; assert ( v != <NUM_LIT> && lsb < <NUM_LIT> && msb < <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned getMaxWavesPerCU ( unsigned FlatWorkGroupSize ) const { return <STR_LIT> :: getMaxWavesPerCU ( getFeatureBits ( ) , FlatWorkGroupSize ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) {

emit_insn ( gen_movsf_from_si ( dest , inner_source ) ) ;


<s> unsigned getReg ( ) const override { return Reg . RegNo ;


<s> Value * <ISA_LIT>IREmitter :: visitVCGEU ( const SDNode * N ) {


<s> break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; MachineInstrBuilder MIB ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ! IsF64 && ( ST . getConstantBusLimit ( Opc ) > <NUM_LIT> || ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB . getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { int64_t Imm ; if ( getFoldableImm ( Src2 , Imm ) ) { unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; updateLiveVariables ( LV , MI , * MIB ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ; return MIB ; } } unsigned NewOpc = IsFMA ? ( IsF16 ? <STR_LIT> : <STR_LIT> ) : ( IsF16 ? <STR_LIT> : <STR_LIT> ) ; if ( getFoldableImm ( Src1 , Imm ) ) { if ( pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) { MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; updateLiveVariables ( LV , MI , * MIB ) ; if ( LIS ) LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; switch ( Kind ) { case Immediate : Inst . addOperand ( MCOperand :: createImm ( getImm ( ) ) ) ; break ; case ContextImmediate :

Inst . addOperand ( MCOperand :: createImm ( getImmS16Context ( ) ) ) ;


<s> const GlobalValue * GV = G ? G -> getGlobal ( ) : nullptr ; return DAG . getTarget ( ) . shouldAssumeDSOLocal ( * Mod , GV ) && ! dyn_cast_or_null < GlobalIFunc > ( GV ) ; } ; bool UsePlt = Subtarget . is32BitELFABI ( ) && ! isLocalCallee ( ) && Subtarget . getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; const auto getAIXFuncEntryPointSymbolSDNode = [ & ] ( const GlobalValue * GV ) { const TargetMachine & TM = Subtarget . getTargetMachine ( ) ; const TargetLoweringObjectFile * TLOF = TM . getObjFileLowering ( ) ; MCSymbolXCOFF * S = cast < MCSymbolXCOFF > ( TLOF -> getFunctionEntryPointSymbol ( GV , TM ) ) ; if ( GV -> isDeclaration ( ) && ! S -> hasRepresentedCsectSet ( ) ) { const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ; auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ; MCSectionXCOFF * Sec = Context . getXCOFFSection ( S -> getSymbolTableName ( ) , XCOFF :: XMC_PR , XCOFF :: XTY_ER , SC , SectionKind :: getMetadata ( ) ) ; S -> setRepresentedCsect ( Sec ) ; } MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getMCSymbol ( S , PtrVT ) ; } ; if ( isFunctionGlobalAddress ( Callee ) ) { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Callee ) -> getGlobal ( ) ; if ( Subtarget . isAIXABI ( ) ) { assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; return getAIXFuncEntryPointSymbolSDNode ( GV ) ; } return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( Subtarget . isAIXABI ( ) ) { const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName ) ) ) return getAIXFuncEntryPointSymbolSDNode ( F ) ; const auto getFunctionEntryPointSymbol = [ & ] ( StringRef SymName ) { auto & Context = DAG . getMachineFunction ( ) . getMMI ( ) . getContext ( ) ;

return cast < MCSymbolXCOFF > ( Context . getOrCreateSymbol ( Twine ( <STR_LIT> ) + Twine ( SymName ) ) ) ;


<s> const unsigned UB = getScoreUB ( T ) ; if ( Count >= UB - LB ) Count = ~ <NUM_LIT> ;


<s> if ( ( NumElts % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue NewN0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N0 ) ; SDValue NewN1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N1 ) ; SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getBitcast ( ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ;

ResHi = DAG . getBitcast ( ResVT , ResHi ) ;


<s> } if ( ! Modified ) { return std :: make_tuple ( nullptr , nullptr ) ; } auto NewFT = FunctionType :: get ( FT -> getReturnType ( ) , ArgTypes , false ) ; auto NewF = Function :: Create ( NewFT , F -> getLinkage ( ) , F -> getName ( ) ) ; ValueToValueMapTy VMap ; auto NewFArgIt = NewF -> arg_begin ( ) ; for ( auto & Arg : F -> args ( ) ) { auto ArgName = Arg . getName ( ) ; NewFArgIt -> setName ( ArgName ) ; VMap [ & Arg ] = & ( * NewFArgIt ++ ) ; if ( IsImageType ( ArgTypeFromMD ( KernelMDNode , Arg . getArgNo ( ) ) ) ) { ( NewFArgIt ++ ) -> setName ( Twine ( <STR_LIT> ) + ArgName ) ; ( NewFArgIt ++ ) -> setName ( Twine ( <STR_LIT> ) + ArgName ) ; } } SmallVector < ReturnInst * , <NUM_LIT> > Returns ; CloneFunctionInto ( NewF , F , VMap , CloneFunctionChangeType :: LocalChangesOnly , Returns ) ; SmallVector < Metadata * , <NUM_LIT> > KernelMDArgs ; KernelMDArgs . push_back ( ConstantAsMetadata :: get ( NewF ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumKernelArgMDNodes ; ++ i ) KernelMDArgs . push_back ( MDNode :: get ( * Context , NewArgMDs . ArgVector [ i ] ) ) ;

MDNode * NewMDNode = MDNode :: get ( * Context , KernelMDArgs ) ;