<s> for ( SDNode * N : C . Op0 -> uses ( ) ) { if ( N -> getOpcode ( ) == <STR_LIT> ) { C . Op0 = SDValue ( N , <NUM_LIT> ) ; C . CCMask = <STR_LIT> ( C . CCMask ) ; return ; } } }


<s> UserOffset += ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; U . KnownAlignment = ( KnownBits >= <NUM_LIT> ) ; if ( isThumb && U . KnownAlignment ) UserOffset &= ~ <NUM_LIT> ; return UserOffset ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ) ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ;

else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ;


<s> return DAG . getTruncStore ( N -> getChain ( ) , SDLoc ( Op ) , N -> getVal ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> getAlignment ( ) , N -> getMemOperand ( ) -> getFlags ( ) , N -> getAAInfo ( ) ) ; } if ( N -> getMemoryVT ( ) == <STR_LIT> ) return DAG . getTruncStore ( N -> getChain ( ) , SDLoc ( Op ) , N -> getVal ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> getAlignment ( ) , N -> getMemOperand ( ) -> getFlags ( ) , N -> getAAInfo ( ) ) ;


<s> AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> paddw_s ( int32x2_t s , int32x2_t t ) {

return __builtin_loongson_paddw_s ( s , t ) ;


<s> virtual const char * getPassName ( ) const LLVM_OVERRIDE { return <STR_LIT> ;


<s> uint64_t RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; assert ( RegBits == <NUM_LIT> && <STR_LIT> ) ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( ! MO . isExpr ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups , STI ) ) & <NUM_LIT> ) | RegBits ; const MCExpr * Expr = MO . getExpr ( ) ; switch ( Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( Expr ) ; ( void ) SRE ; assert ( ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_PCREL || SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PCREL || SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_PCREL || SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_PCREL ) && <STR_LIT> <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , static_cast < MCFixupKind > ( <STR_LIT> ) ) ) ; return <NUM_LIT> ; } case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; assert ( BE -> getOpcode ( ) == MCBinaryExpr :: Add && <STR_LIT> ) ; const MCExpr * LHS = BE -> getLHS ( ) ; const MCExpr * RHS = BE -> getRHS ( ) ; if ( LHS -> getKind ( ) != MCExpr :: SymbolRef ) std :: swap ( LHS , RHS ) ; if ( LHS -> getKind ( ) != MCExpr :: SymbolRef || RHS -> getKind ( ) != MCExpr :: Constant ) llvm_unreachable ( <STR_LIT> ) ; const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( LHS ) ; ( void ) SRE ;

assert ( isInt < <NUM_LIT> > ( cast < MCConstantExpr > ( RHS ) -> getValue ( ) ) && <STR_LIT> ) ;


<s> exit ( FATAL_EXIT_CODE ) ; } } } if ( extract_mode ) { do { char * lname = argv [ nexti ] ; int lnamelen ; if ( is_regular_file ( lname ) ) { addarg ( xstrdup ( to_host_file_spec ( lname ) ) ) ; break ; } lnamelen = strlen ( lname ) ; if ( lnamelen > <NUM_LIT> && strcmp ( & lname [ lnamelen - <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ) { char * nlibname ; nlibname = ( char * ) alloca ( lnamelen + <NUM_LIT> ) ; strcpy ( nlibname , lname ) ; strcpy ( & nlibname [ lnamelen - <NUM_LIT> ] , <STR_LIT> ) ; if ( is_regular_file ( nlibname ) ) { addarg ( xstrdup ( to_host_file_spec ( nlibname ) ) ) ; break ; } } fprintf ( stderr , <STR_LIT> , lname ) ; exit ( FATAL_EXIT_CODE ) ; } while ( <NUM_LIT> ) ; } else strcpy ( libname , to_host_file_spec ( argv [ nexti ] ) ) ; nexti ++ ; if ( replace_mode ) { strcat ( modecmd , <STR_LIT> ) ; if ( ! is_regular_file ( libname ) || ! replace_mode ) { strcat ( modecmd , <STR_LIT> ) ; } } else if ( extract_mode ) { if ( nexti == argc ) { strcat ( modecmd , <STR_LIT> ) ; } else strcat ( modecmd , <STR_LIT> ) ; } for ( i = nexti ; i < argc ; i ++ ) { if ( extract_mode ) { char * module = argv [ i ] ; int module_len = strlen ( module ) ; char * newarg = ( char * ) xmalloc ( module_len + <NUM_LIT> ) ; int l ; newarg [ <NUM_LIT> ] = '"' ; memcpy ( newarg + <NUM_LIT> , module , module_len ) ; l = <NUM_LIT> + module_len ; if ( module_len > <NUM_LIT> && strcmp ( & module [ module_len - <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ) l -= <NUM_LIT> ; newarg [ l ] = '"' ; newarg [ l + <NUM_LIT> ] = <NUM_LIT> ; addarg ( newarg ) ; } else { addarg ( xstrdup ( to_host_file_spec ( argv [ i ] ) ) ) ; } } if ( extract_mode ) addarg ( <STR_LIT> ) ; strcpy ( temp_filename , TEMP_FILE SUFFIX ) ; comfd = mkstemps ( temp_filename , SUFFIX_LEN ) ; comfile = fdopen ( comfd , <STR_LIT> ) ; outlen = <NUM_LIT> ; for ( iarg = <NUM_LIT> ; iarg <= lib_arg_index ; iarg ++ ) { if ( outlen == <NUM_LIT> ) {

fprintf ( comfile , <STR_LIT> , modecmd , libname ) ;


<s> if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } } if ( I . getOpcode ( ) == TargetOpcode :: G_IMPLICIT_DEF ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else I . setDesc ( TII . get ( <STR_LIT> ) ) ; return true ;


<s> const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ; assert ( dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) && dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ;


<s> disablePass ( & MachineCopyPropagationID ) ; disablePass ( & BranchFolderPassID ) ; disablePass ( & TailDuplicateID ) ; TargetPassConfig :: addIRPasses ( ) ;

addPass ( createGenericToNVVMPass ( ) ) ;


<s> for ( MachineInstr & MI : MBB ) if ( MI . getOpcode ( ) == <STR_LIT> ) CFGs . push_back ( & MI ) ;

for ( auto * MI : CFGs ) materializeTileCfg ( MI ) ;


<s> void addFBits16Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - CE -> getValue ( ) ) ) ;


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ; return true ; } if ( restrict_addressing_modes_for_nacl ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; Name = StringSwitch < StringRef > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Name ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Identifier ) && Parser . getTok ( ) . getIdentifier ( ) == <STR_LIT> ) { parseDirectiveReq ( Name , NameLoc ) ; return true ; } size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Head = Name . slice ( Start , Next ) ; if ( Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> || Head == <STR_LIT> ) { bool IsError = parseSysAlias ( Head , NameLoc , Operands ) ; if ( IsError && getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) Parser . eatToEndOfStatement ( ) ; return IsError ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Head , false , NameLoc , getContext ( ) ) ) ; Mnemonic = Head ; if ( Head == <STR_LIT> && Next != StringRef :: npos ) { Start = Next ; Next = Name . find ( '.' , Start + <NUM_LIT> ) ; Head = Name . slice ( Start + <NUM_LIT> , Next ) ;

SMLoc SuffixLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + ( Head . data ( ) - Name . data ( ) ) ) ;


<s> BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , AddDestReg ) . addUse ( OpSizeReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register BicDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , BicDestReg ) . addUse ( AddDestReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register LsrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , LsrDestReg ) . addUse ( BicDestReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register TotalIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) , TotalIterationsReg ) . addUse ( LsrDestReg , RegState :: Kill ) ; BuildMI ( TpEntry , Dl , TII -> get ( <STR_LIT> ) ) . addUse ( TotalIterationsReg ) . addMBB ( TpExit ) ; return TotalIterationsReg ;


<s> unsigned Imm2 ; if ( Val . getOpcode ( ) != <STR_LIT> || ! isInt32Immediate ( Val . getOperand ( <NUM_LIT> ) , Imm2 ) ) return false ; unsigned MB , ME ; if ( isRunOfOnes ( ~ ( Imm ^ Imm2 ) , MB , ME ) && ! ( ~ Imm & Imm2 ) ) {


<s> } } else { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> * ( ArgNo - <NUM_LIT> ) , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; } InVals . push_back ( ArgVal ) ; } if ( isVarArg ) { VarArgsOffset = Ins . size ( ) * <NUM_LIT> ; std :: vector < SDValue > LS ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( TargetRegisterInfo :: isPhysicalRegister ( args_int [ i ] ) ) args_int [ i ] = AddLiveIn ( MF , args_int [ i ] , & <STR_LIT> ) ; SDValue argt = DAG . getCopyFromReg ( Chain , dl , args_int [ i ] , <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> * ( <NUM_LIT> - i ) , true , false ) ; if ( i == <NUM_LIT> ) VarArgsBase = FI ; SDValue SDFI = DAG . getFrameIndex ( FI , <STR_LIT> ) ; LS . push_back ( DAG . getStore ( Chain , dl , argt , SDFI , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( args_float [ i ] ) ) args_float [ i ] = AddLiveIn ( MF , args_float [ i ] , & <STR_LIT> ) ;

argt = DAG . getCopyFromReg ( Chain , dl , args_float [ i ] , <STR_LIT> ) ;


<s> Optional < MCFixupKind > <ISA_LIT>AsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , FK_Data_4 ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Case ( <STR_LIT> , ( MCFixupKind ) <STR_LIT> ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ;


<s> if ( DefinesOptionalPredicate ( MI , & CPSR ) ) { if ( CPSR ) AddDefaultT1CC ( MIB ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ;

MCInstLowering . Lower ( MI , TmpInst ) ;


<s> static void fail ( SDLoc DL , SelectionDAG & DAG , const char * Msg , SDValue Val ) { MachineFunction & MF = DAG . getMachineFunction ( ) ;


<s> if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; auto * ShiftC = dyn_cast < ConstantSDNode > ( N1 ) ; auto * AndC = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! ShiftC || ! AndC ) return SDValue ( ) ; APInt MaskVal = AndC -> getAPIntValue ( ) ; APInt NewMaskVal = MaskVal . lshr ( ShiftC -> getAPIntValue ( ) ) ; unsigned OldMaskSize = MaskVal . getMinSignedBits ( ) ; unsigned NewMaskSize = NewMaskVal . getMinSignedBits ( ) ; if ( ( OldMaskSize > <NUM_LIT> && NewMaskSize <= <NUM_LIT> ) || ( OldMaskSize > <NUM_LIT> && NewMaskSize <= <NUM_LIT> ) ) {


<s> EVT InSVT = InVT . getScalarType ( ) ; if ( InVT . isVector ( ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> || ( InSVT == <STR_LIT> && ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( InVT ) ) ) ) { SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( InVT . getScalarSizeInBits ( ) > <NUM_LIT> && ! Subtarget . hasDQI ( ) ) { unsigned BitWidth = InVT . getScalarSizeInBits ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( Op0 ) ; if ( NumSignBits >= ( BitWidth - <NUM_LIT> ) ) { EVT TruncVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , <NUM_LIT> ) ; if ( InVT . isVector ( ) ) TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , InVT . getVectorNumElements ( ) ) ; SDLoc dl ( N ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , dl , TruncVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Trunc ) ; } } if ( ! Subtarget . useSoftFloat ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT LdVT = Ld -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( ! Ld -> isVolatile ( ) && ! VT . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! Subtarget . is64Bit ( ) && LdVT == <STR_LIT> ) {

SDValue FILDChain = Subtarget . getTargetLowering ( ) -> BuildFILD ( SDValue ( N , <NUM_LIT> ) , LdVT , Ld -> getChain ( ) , Op0 , DAG ) ;


<s> const <ISA_LIT>Subtarget & STI = MI -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MMO -> getSize ( ) == <NUM_LIT> && ( ! STI . systemSupportsUnalignedAccess ( ) && MMO -> getAlign ( ) < MMO -> getSize ( ) ) ) return true ; }


<s> icode = ( fcode == AARCH64_BUILTIN_GET_FPSR ) ? CODE_FOR_get_fpsr : CODE_FOR_get_fpcr ; target = gen_reg_rtx ( SImode ) ; pat = GEN_FCN ( icode ) ( target ) ; } else { target = NULL_RTX ; icode = ( fcode == AARCH64_BUILTIN_SET_FPSR ) ? CODE_FOR_set_fpsr : CODE_FOR_set_fpcr ; arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = force_reg ( SImode , expand_normal ( arg0 ) ) ; pat = GEN_FCN ( icode ) ( op0 ) ; } emit_insn ( pat ) ; return target ; } if ( fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX ) return aarch64_simd_expand_builtin ( fcode , exp , target ) ; else if ( fcode >= AARCH64_CRC32_BUILTIN_BASE && fcode <= AARCH64_CRC32_BUILTIN_MAX ) return aarch64_crc32_expand_builtin ( fcode , exp , target ) ; if ( fcode == AARCH64_BUILTIN_RSQRT_DF || fcode == AARCH64_BUILTIN_RSQRT_SF || fcode == AARCH64_BUILTIN_RSQRT_V2DF || fcode == AARCH64_BUILTIN_RSQRT_V2SF || fcode == AARCH64_BUILTIN_RSQRT_V4SF ) return aarch64_expand_builtin_rsqrt ( fcode , exp , target ) ; gcc_unreachable ( ) ;


<s> MVT ResTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; if ( HST -> isHVXVectorType ( ResTy , true ) ) return SelectHvxVAlign ( N ) ; const SDLoc & dl ( N ) ; unsigned VecLen = ResTy . getSizeInBits ( ) ; if ( VecLen == <NUM_LIT> ) { SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ; SDNode * R = CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , Ops ) ; SDValue M0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue M1 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * C = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , M0 , N -> getOperand ( <NUM_LIT> ) , M1 ) ; SDNode * S = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( R , <NUM_LIT> ) , SDValue ( C , <NUM_LIT> ) ) ; SDValue E = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , ResTy , SDValue ( S , <NUM_LIT> ) ) ; ReplaceNode ( N , E . getNode ( ) ) ; } else { assert ( VecLen == <NUM_LIT> ) ;

SDNode * Pu = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>16RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ;


<s> getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ; if ( Result ) return MatchOperand_NoMatch ;


<s> FStub -> addFnAttr ( <STR_LIT> ) ; FStub -> setSection ( SectionName ) ; BasicBlock * BB = BasicBlock :: Create ( Context , <STR_LIT> , FStub ) ; InlineAsmHelper IAH ( Context , BB ) ; FPReturnVariant RV = whichFPReturnVariant ( FStub -> getReturnType ( ) ) ; FPParamVariant PV = whichFPParamVariantNeeded ( F ) ; swapFPIntParams ( PV , M , IAH , LE , true ) ; if ( RV != NoFPRet ) { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name ) ; } else { IAH . Out ( <STR_LIT> + Name + <STR_LIT> ) ; IAH . Out ( <STR_LIT> + Name + <STR_LIT> ) ; } switch ( RV ) { case FRet : IAH . Out ( <STR_LIT> ) ; break ; case DRet : if ( LE ) { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ; } else { IAH . Out ( <STR_LIT> ) ; IAH . Out ( <STR_LIT> ) ;


<s> if ( ! TT . isOSBinFormatELF ( ) ) llvm_unreachable ( <STR_LIT> ) ; return new <ISA_LIT>AsmBackend ( T , TT . getOS ( ) ) ;


<s> return ( __m128i ) __builtin_ia32_cvttpd2uqq128_mask ( ( __v2df ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( Log2IfPositive <= <NUM_LIT> ) return SDValue ( ) ; SDValue Op0Op2 = Op0 -> getOperand ( <NUM_LIT> ) ; EVT ExtendTy = cast < VTSDNode > ( Op0Op2 ) -> getVT ( ) ; unsigned ExtendTySize = ExtendTy . getSizeInBits ( ) ; unsigned Log2 = Log2IfPositive ; if ( ( Op0Opcode == <STR_LIT> && Log2 >= ExtendTySize ) || Log2 == ExtendTySize ) { SDValue Ops [ ] = { Op0 -> getOperand ( <NUM_LIT> ) , Op0 -> getOperand ( <NUM_LIT> ) , Op0Op2 } ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op0 ) , Op0 -> getVTList ( ) , makeArrayRef ( Ops , Op0 -> getNumOperands ( ) ) ) ; } } return SDValue ( ) ;


<s> VTSDNode * TypeNode = cast < VTSDNode > ( V . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) || ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) ) { ExtType = <STR_LIT> ; return true ; } return false ; } case <STR_LIT> : { VTSDNode * TypeNode = cast < VTSDNode > ( V . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) || ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) ) { ExtType = <STR_LIT> ; return true ; }


<s> if ( GET_CODE ( pattern ) != SET ) return false ; src = SET_SRC ( pattern ) ;

return ( GET_CODE ( src ) == CONST && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_HW1_LAST_PCREL ) ;


<s> } if ( IsAllOf && Subtarget . hasSSE41 ( ) ) { SDValue BC = peekThroughBitcasts ( Vec ) ; if ( BC . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( BC . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { MVT TestVT = VecVT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue V = DAG . getBitcast ( TestVT , BC . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , <STR_LIT> , V , V ) ; } } if ( Vec . getOpcode ( ) == <STR_LIT> && VecVT == <STR_LIT> ) { SDValue VecOp0 = Vec . getOperand ( <NUM_LIT> ) ; SDValue VecOp1 = Vec . getOperand ( <NUM_LIT> ) ; bool SignExt0 = DAG . ComputeNumSignBits ( VecOp0 ) > <NUM_LIT> ; bool SignExt1 = DAG . ComputeNumSignBits ( VecOp1 ) > <NUM_LIT> ; if ( IsAnyOf && CmpBits == <NUM_LIT> && VecOp1 . isUndef ( ) ) { SDLoc DL ( EFLAGS ) ; SDValue Result = DAG . getBitcast ( <STR_LIT> , VecOp0 ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result ) ; Result = DAG . getZExtOrTrunc ( Result , DL , <STR_LIT> ) ; if ( ! SignExt0 ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( CmpBits >= <NUM_LIT> && Subtarget . hasInt256 ( ) && VecOp0 . getOpcode ( ) == <STR_LIT> && VecOp1 . getOpcode ( ) == <STR_LIT> && VecOp0 . getOperand ( <NUM_LIT> ) == VecOp1 . getOperand ( <NUM_LIT> ) && VecOp0 . getConstantOperandAPInt ( <NUM_LIT> ) == <NUM_LIT> && VecOp1 . getConstantOperandAPInt ( <NUM_LIT> ) == <NUM_LIT> && ( IsAnyOf || ( SignExt0 && SignExt1 ) ) ) { SDLoc DL ( EFLAGS ) ; SDValue Result = DAG . getBitcast ( <STR_LIT> , VecOp0 . getOperand ( <NUM_LIT> ) ) ;


<s> for ( auto & MBB : Fn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; if ( MBB . empty ( ) ) { continue ; } if ( <ISA_LIT>NumDebugNops ) { insertDebugNops ( MBB , <ISA_LIT>NumDebugNops ) ; } else { resolveBlockLatency ( MBB ) ; fixSmallLoops ( MBB ) ; } } if ( <ISA_LIT>NumDebugNops ) { return true ; } else resolveFunctionLatency ( Fn ) ; for ( auto & MBB : Fn ) { if ( ! MBB . empty ( ) ) { resolveCrossBlockLatency ( MBB ) ; } } for ( auto & MBB : Fn ) { if ( ! MBB . empty ( ) ) { resolveCrossBlockLatency ( MBB , false , true ) ; } } for ( auto & MBB : Fn ) { if ( ! MBB . empty ( ) ) { fillLoopDelaySlot ( MBB ) ; } } for ( auto & MBB : Fn ) { if ( ! MBB . empty ( ) ) { ensureLoopEndAndJmpLatency ( MBB ) ; } } return true ;


<s> if ( cfun -> machine -> va_args_size != <NUM_LIT> ) { sp_adjust = cfun -> machine -> va_args_size + cfun -> machine -> va_args_area_padding_bytes ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; return ; } if ( frame_pointer_needed ) { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int gpr_padding = cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; nds32_emit_pop_fpr_callee_saved ( gpr_padding ) ; } else { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , hard_frame_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } else {


<s> if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false , false , false ) ; else { ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) emit<ISA_LIT>RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; emitT2RegPlusImmediate ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , Pred , PredReg , TII ) ; } MI . getOperand ( i ) . ChangeToRegister ( ScratchReg , false , false , true ) ; }


<s> const TargetRegisterClass * RC = TRI -> getPhysRegClass ( Reg ) ; return TRI -> getSubRegClass ( RC , SubReg ) ; } MachineInstr * Def = MRI . getVRegDef ( Reg ) ; if ( Def -> getOpcode ( ) != AMDGPU :: COPY ) {

return TRI -> getSubRegClass ( MRI . getRegClass ( Reg ) , SubReg ) ;


<s> } if ( Prefix == <STR_LIT> ) { Int = <NUM_LIT> ; } else if ( Prefix == <STR_LIT> ) { Int = <NUM_LIT> ; } else { if ( Prefix != <STR_LIT> && Prefix != <STR_LIT> && Prefix != <STR_LIT> && Prefix != <STR_LIT> && Prefix != <STR_LIT> && Prefix != <STR_LIT> && Prefix != <STR_LIT> && Prefix != <STR_LIT> && Prefix != <STR_LIT> ) { return MatchOperand_NoMatch ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return MatchOperand_ParseFail ; if ( Prefix == <STR_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Integer ) ) return MatchOperand_ParseFail ; Int = getLexer ( ) . getTok ( ) . getIntVal ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Integer ) ) return MatchOperand_ParseFail ; Int += ( getLexer ( ) . getTok ( ) . getIntVal ( ) << <NUM_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Integer ) ) return MatchOperand_ParseFail ; Int += ( getLexer ( ) . getTok ( ) . getIntVal ( ) << <NUM_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Integer ) ) return MatchOperand_ParseFail ; Int += ( getLexer ( ) . getTok ( ) . getIntVal ( ) << <NUM_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ;


<s> Type * RetType = F . getReturnType ( ) ; return whichFPReturnVariant ( RetType ) != NoFPRet ;


<s> setPICStyle ( PICStyles :: RIPRel ) ; } else if ( isTargetCOFF ( ) ) { setPICStyle ( PICStyles :: None ) ; } else if ( isTargetDarwin ( ) ) { if ( isPositionIndependent ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( isTargetELF ( ) ) {


<s> if ( ! Value . isAbsolute ( ) ) return false ;

Res = evaluateAsInt64 ( Value . getConstant ( ) ) ;


<s> unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState ( isKill ) ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd ) ; NewMIs . push_back ( MIB ) ;


<s> inline bool <ISA_LIT>DAGToDAGISel :: foldGlobalAddress ( SDValue & N , SDValue & R ) { return foldGlobalAddressImpl ( N , R , false ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> bool <ISA_LIT>AsmParser :: ParseLiteralValues ( unsigned Size , SMLoc L ) { auto parseOne = [ & ] ( ) -> bool { const MCExpr * Value ;

if ( getParser ( ) . parseExpression ( Value ) ) return true ;


<s> addPass ( create<ISA_LIT>LowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; }


<s> case MachineCombinerPattern :: REASSOC_XMM_AMM_BMM : case MachineCombinerPattern :: REASSOC_XY_BCA : case MachineCombinerPattern :: REASSOC_XY_BAC : reassociateFMA ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ; break ; default :

TargetInstrInfo :: genAlternativeCodeSequence ( Root , Pattern , InsInstrs , DelInstrs , InstrIdxForVirtReg ) ;


<s> initialize<ISA_LIT>TDCPassPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> static bool mips_find_gp_ref ( bool * cache , bool ( * pred ) ( rtx_insn * ) ) { rtx_insn * insn ; if ( ! * cache ) { push_topmost_sequence ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( USEFUL_INSN_P ( insn ) && pred ( insn ) ) { * cache = true ; break ; } pop_topmost_sequence ( ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isDarwinABI ( ) || ! Subtarget . hasAltivec ( ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } } if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) {

if ( Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) && MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) Reserved . set ( <STR_LIT> ) ;


<s> if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , loongarch_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; loongarch_for_each_saved_reg ( size , loongarch_save_reg ) ; } if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; loongarch_emit_stack_tie ( ) ; } if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { HOST_WIDE_INT first = get_stack_check_protect ( ) ; if ( frame -> total_size == <NUM_LIT> ) { dump_stack_clash_frame_info ( NO_PROBE_NO_FRAME , false ) ; return ; } if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { HOST_WIDE_INT interval ; if ( flag_stack_clash_protection ) interval = STACK_CLASH_PROTECTION_GUARD_SIZE ;


<s> assert ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned Opcode ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; const MCInstrDesc & Desc = TII -> get ( Opcode ) ;

assert ( Desc . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ) { CanAcceptCarrySet = true ; } else CanAcceptCarrySet = false ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && ! isThumb ( ) ) || ( Mnemonic == <STR_LIT> && isThumbOne ( ) ) || ( ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && ! isThumb ( ) ) || ( ( Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) ) && ! isThumb ( ) ) || Mnemonic . startswith ( <STR_LIT> ) || ( Mnemonic == <STR_LIT> && isThumbOne ( ) ) ) { CanAcceptPredicationCode = false ; } else CanAcceptPredicationCode = true ; if ( isThumb ( ) ) { if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) CanAcceptPredicationCode = false ;


<s> return new ELF<ISA_LIT>AsmBackend ( T , STI . getTargetTriple ( ) . getOS ( ) ) ;


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , unsigned UnitSize , unsigned ShuffleKind , SelectionDAG & DAG ) { if ( DAG . getSubtarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return false ; } else { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( create<ISA_LIT>SetSpillBase ( ) , false ) ;


<s> break ; case LEU : case GEU : code = reverse_condition ( code ) ; reverse = true ; case LTU : case GTU : if ( code == GTU ) { rtx tmp = op1 ; op1 = op2 ; op2 = tmp ; } break ; default : gcc_unreachable ( ) ; } sltu = gen_rtx_LTU ( SImode , op1 , op2 ) ; if ( reverse ) { rtx tmp = copy_to_mode_reg ( SImode , gen_rtx_NEG ( SImode , sltu ) ) ; emit_insn ( gen_add3_insn ( op0 , tmp , const1_rtx ) ) ; } else emit_insn ( gen_rtx_SET ( op0 , sltu ) ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > C ( getThe<ISA_LIT>64LETarget ( ) ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>BoolRetToIntPass ( PR ) ; initialize<ISA_LIT>ExpandISELPass ( PR ) ;


<s> BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CfCount ) ; for ( MachineInstr * MI : Clause . second ) BB -> splice ( InsertPos , BB , MI ) ;


<s> for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( ! isSafeToFold ( MI . getOpcode ( ) ) ) continue ; unsigned OpSize = TII -> getOpSize ( MI , <NUM_LIT> ) ; MachineOperand & OpToFold = MI . getOperand ( <NUM_LIT> ) ; bool FoldingImm = OpToFold . isImm ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( FoldingImm && ! TII -> isInlineConstant ( OpToFold , OpSize ) && ! MRI . hasOneUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; if ( Dst . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > CopiesToReplace ; std :: vector < FoldCandidate > FoldList ; for ( MachineRegisterInfo :: use_iterator Use = MRI . use_begin ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) , E = MRI . use_end ( ) ; Use != E ; ++ Use ) { MachineInstr * UseMI = Use -> getParent ( ) ; foldOperand ( OpToFold , UseMI , Use . getOperandNo ( ) , FoldList , CopiesToReplace , TII , TRI , MRI ) ; } for ( MachineInstr * Copy : CopiesToReplace ) Copy -> addImplicitDefUseOperands ( MF ) ; for ( FoldCandidate & Fold : FoldList ) { if ( updateOperand ( Fold , TRI ) ) { if ( ! Fold . isImm ( ) ) { assert ( Fold . OpToFold && Fold . OpToFold -> isReg ( ) ) ; MRI . clearKillFlags ( Fold . OpToFold -> getReg ( ) ) ; }

DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << Fold . UseOpNo << <STR_LIT> << * Fold . UseMI << '\n' ) ;


<s> return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( AMDGPUTTIImpl ( this ) ) ; } ) ;


<s> return & pass . getAnalysis < MachineLoopInfo > ( ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitArch ( unsigned Value ) {


<s> bool i386_pe_type_dllimport_p ( tree decl ATTRIBUTE_UNUSED ) { return false ;


<s> unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ; unsigned VSEWBits = static_cast < unsigned > ( VSEW ) ; unsigned VTypeI = ( VSEWBits << <NUM_LIT> ) | ( VLMULBits & <NUM_LIT> ) ; if ( TailAgnostic ) VTypeI |= <NUM_LIT> ; if ( MaskAgnostic ) VTypeI |= <NUM_LIT> ; return VTypeI ;


<s> if ( size == <NUM_LIT> ) { if ( mode == VOIDmode ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; else regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; } else if ( size <= <NUM_LIT> ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) | ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; else if ( size <= <NUM_LIT> ) regs_available_for_popping = ( <NUM_LIT> << ARG_REGISTER ( <NUM_LIT> ) ) ; } for ( available = regs_available_for_popping , required = regs_to_pop ; required != <NUM_LIT> && available != <NUM_LIT> ; available &= ~ ( available & - available ) , required &= ~ ( required & - required ) ) -- pops_needed ; if ( available > <NUM_LIT> ) regs_available_for_popping &= ~ available ; else if ( pops_needed ) { if ( regs_available_for_popping == <NUM_LIT> && reg_containing_return_addr == LAST_ARG_REGNUM ) { asm_fprintf ( f , <STR_LIT> , LR_REGNUM , LAST_ARG_REGNUM ) ; reg_containing_return_addr = LR_REGNUM ; } else if ( size > <NUM_LIT> ) { restore_a4 = TRUE ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM , LAST_ARG_REGNUM ) ; } if ( reg_containing_return_addr != LAST_ARG_REGNUM ) { regs_available_for_popping |= <NUM_LIT> << LAST_ARG_REGNUM ; -- pops_needed ; } } thumb_pop ( f , regs_available_for_popping ) ; if ( reg_containing_return_addr == - <NUM_LIT> ) { regs_to_pop &= ~ ( <NUM_LIT> << LR_REGNUM ) ; reg_containing_return_addr = number_of_first_bit_set ( regs_available_for_popping ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << reg_containing_return_addr ) ; } if ( regs_available_for_popping ) { int frame_pointer ; frame_pointer = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , ARM_HARD_FRAME_POINTER_REGNUM , frame_pointer ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << frame_pointer ) ; regs_to_pop &= ~ ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) ; if ( regs_available_for_popping ) {


<s> if ( call_cookie & CALL_SHORT ) return <NUM_LIT> ; if ( call_cookie & CALL_LONG ) return <NUM_LIT> ; if ( TARGET_LONG_CALLS ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> MVT TVT ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { Ops . assign ( <NUM_LIT> , Cst ) ; TVT = <STR_LIT> ; } else { Ops . assign ( <NUM_LIT> , Cst ) ; TVT = <STR_LIT> ; } Vec = DAG . getNode ( <STR_LIT> , dl , TVT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec ) ;


<s> void R600SchedStrategy :: releaseBottomNode ( SUnit * SU ) {


for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) {


<s> <ISA_LIT>ElimCompare ( const <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) , TII ( nullptr ) , TRI ( nullptr ) {


<s> bool UseGOT = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; Alignment = <NUM_LIT> ; } else { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; } SDValue GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , HiFixup ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , LoFixup ) , DAG . getConstant ( Alignment , <STR_LIT> ) ) ; if ( UseGOT ) { GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getEntryNode ( ) , GlobalRef ) ; } if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GlobalRef , DAG . getConstant ( GN -> getOffset ( ) , PtrVT ) ) ;


<s> assert ( Kind == k_Prefetch && <STR_LIT> ) ;


<s> explicit Entry ( const SortRegion * R ) : TheRegion ( R ) , NumBlocksLeft ( R -> getNumBlocks ( ) ) {


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) {

addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ;


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , create<ISA_LIT>MCStreamer ) ;

TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> void MVEGatherScatterLowering :: pushOutMul ( PHINode * & Phi , Value * IncrementPerRound , Value * OffsSecondOperand , unsigned LoopIncrement , IRBuilder < > & Builder ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Instruction * InsertionPoint = & cast < Instruction > ( Phi -> getIncomingBlock ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) -> back ( ) ) ; Value * StartIndex = BinaryOperator :: Create ( Instruction :: Mul , Phi -> getIncomingValue ( LoopIncrement == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ;

Instruction * Product = BinaryOperator :: Create ( Instruction :: Mul , IncrementPerRound , OffsSecondOperand , <STR_LIT> , InsertionPoint ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Word0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( LoIdx , <STR_LIT> ) ) ; SDValue Hi0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( HiIdx , <STR_LIT> ) ) ; SDValue Hi1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( HiIdx , <STR_LIT> ) ) ;

SDValue And0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> accessor . base = stack_pointer_rtx ; accessor . base_offset = <NUM_LIT> ; } { rtx asm_offset = frv_frame_offset_rtx ( - info -> total_size ) ; rtx dwarf_offset = GEN_INT ( - info -> total_size ) ; frv_frame_insn ( gen_stack_adjust ( sp , sp , asm_offset ) , gen_rtx_SET ( sp , gen_rtx_PLUS ( Pmode , sp , dwarf_offset ) ) ) ; } if ( frame_pointer_needed ) { int fp_offset = info -> reg_offset [ FRAME_POINTER_REGNUM ] ; rtx asm_src = plus_constant ( Pmode , accessor . base , fp_offset - accessor . base_offset ) ; rtx dwarf_src = plus_constant ( Pmode , sp , fp_offset ) ; frv_frame_access ( & accessor , fp , fp_offset ) ; frv_frame_insn ( gen_rtx_SET ( fp , asm_src ) , gen_rtx_SET ( fp , dwarf_src ) ) ; accessor . base = fp ;


<s> bool <ISA_LIT>PacketizerList :: isNewifiable ( const MachineInstr & MI , const TargetRegisterClass * NewRC ) { if ( NewRC == & <STR_LIT> ) if ( HII -> isV60VectorInstruction ( MI ) && MI . mayStore ( ) ) return false ; return HII -> isCondInst ( MI ) || HII -> isJumpR ( MI ) || MI . isReturn ( ) || HII -> mayBeNewStore ( MI ) ;


<s> rtx op1 , addr ; extract_insn_cached ( insn ) ; op1 = recog_data . operand [ <NUM_LIT> ] ; if ( CONSTANT_P ( op1 ) ) return true ; if ( GET_CODE ( op1 ) == ZERO_EXTEND || GET_CODE ( op1 ) == SIGN_EXTEND ) op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( GET_CODE ( op1 ) != MEM ) return false ; addr = XEXP ( op1 , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ;


<s> IRBuilder < > Builder ( & II ) ; Value * Pred = II . getOperand ( <NUM_LIT> ) ; Value * Vec = II . getOperand ( <NUM_LIT> ) ; Value * Shift = II . getOperand ( <NUM_LIT> ) ; Value * AbsPred , * MergedValue ; if ( ! match ( Vec , m_Intrinsic < <STR_LIT> > ( m_Value ( MergedValue ) , m_Value ( AbsPred ) , m_Value ( ) ) ) && ! match ( Vec , m_Intrinsic < <STR_LIT> > ( m_Value ( MergedValue ) , m_Value ( AbsPred ) , m_Value ( ) ) ) ) return None ; if ( ! isa < UndefValue > ( MergedValue ) && ! match ( MergedValue , m_NonNegative ( ) ) && AbsPred != Pred && ! isAllActivePredicate ( AbsPred ) ) return None ; if ( ! match ( Shift , m_NonNegative ( ) ) ) return None ; auto LSL = Builder . CreateIntrinsic ( <STR_LIT> , { II . getType ( ) } , { Pred , Vec , Shift } ) ; return IC . replaceInstUsesWith ( II , LSL ) ;


<s> if ( MI -> isRegSequence ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) return true ; return false ;


<s> void <ISA_LIT>SchedStrategy :: schedNode ( SUnit * SU , bool IsTopNode ) { if ( NextInstKind != CurInstKind ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( NextInstKind != IDAlu ) OccupedSlotsMask |= <NUM_LIT> ; CurEmitted = <NUM_LIT> ; CurInstKind = NextInstKind ; } if ( CurInstKind == IDAlu ) { AluInstCount ++ ; switch ( getAluKind ( SU ) ) { case AluT_XYZW : CurEmitted += <NUM_LIT> ; break ; case AluDiscarded : break ; default : { ++ CurEmitted ; for ( MachineInstr :: mop_iterator It = SU -> getInstr ( ) -> operands_begin ( ) , E = SU -> getInstr ( ) -> operands_end ( ) ; It != E ; ++ It ) { MachineOperand & MO = * It ;

if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) ++ CurEmitted ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSampleIntrinsic ( unsigned Opcode , const SDValue & Op , SelectionDAG & DAG ) const { return DAG . getNode ( Opcode , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 ) ;


<s> MachineOperand & brA = brInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand & brB = brInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand & andA = andInstr -> getOperand ( <NUM_LIT> ) ; MachineOperand & andB = andInstr -> getOperand ( <NUM_LIT> ) ; if ( andB . isReg ( ) ) { brA . ChangeToRegister ( andA . getReg ( ) , andA . isDef ( ) , andA . isImplicit ( ) , andA . isKill ( ) , andA . isDead ( ) , andA . isUndef ( ) , andA . isDebug ( ) ) ; brB . ChangeToRegister ( andB . getReg ( ) , andB . isDef ( ) , andB . isImplicit ( ) , andB . isKill ( ) , andB . isDead ( ) , andB . isUndef ( ) , andB . isDebug ( ) ) ; return true ;


<s> if ( ! C ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , Src . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; if ( Mask . getValueType ( ) != MaskVT ) Mask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ;

SDValue Ops [ ] = { Chain , Src , Mask , Base , Index , Scale } ;


<s> if ( Op . isReg ( ) ) { printRegName ( O , Op . getReg ( ) ) ; return ; } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ;


<s> MCDisassembler ( STI ) , MII ( T . createMCInstrInfo ( ) ) {


<s> if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ;

case MachineOperand :: MO_GlobalAddress :


<s> if ( Hzd -> isXResBusy ( xuse ) ) { static std :: string estr [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; DEBUG ( dbgs ( ) << <STR_LIT> << estr [ xuse ] << <STR_LIT> ) ; return NoopHazard ; } if ( ! Hzd -> moveUnitsAvailable ( side ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return NoopHazard ; } return NoHazard ;


<s> } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } if ( N . getOpcode ( ) != <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } } if ( ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) ) && ! N . hasOneUse ( ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return AM2_BASE ; } <STR_LIT> AddSub = N . getOpcode ( ) != <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseNumericFormat ( int64_t & Format ) { using namespace llvm :: <STR_LIT> ; SMLoc Loc = getLoc ( ) ; if ( ! parseExpr ( Format ) ) return MatchOperand_ParseFail ;

if ( ! isValidFormatEncoding ( Format , getSTI ( ) ) ) {


<s> auto * Memcpy = cast < MemCpyInst > ( Inst ) ; if ( shouldExpandOperationWithSize ( Memcpy -> getLength ( ) ) ) { expandMemCpyAsLoop ( Memcpy ) ; Changed = true ; Memcpy -> eraseFromParent ( ) ; } break ; } case <STR_LIT> : { auto * Memmove = cast < MemMoveInst > ( Inst ) ; if ( shouldExpandOperationWithSize ( Memmove -> getLength ( ) ) ) { expandMemMoveAsLoop ( Memmove ) ; Changed = true ; Memmove -> eraseFromParent ( ) ;


<s> static unsigned getPostIndexedOpcode ( unsigned Opc ) { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : nullptr ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , RC , ! IsSigned ) ) return <NUM_LIT> ; return ResultReg ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _bzhi_u64 ( unsigned long long __X , unsigned long long __Y ) {


<s> const <ISA_LIT>MCExpr * RVExpr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( RVExpr -> getKind ( ) ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : FixupKind = MIFrm == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO : FixupKind = MIFrm == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI : FixupKind = <STR_LIT> ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ;

Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ;


<s> if ( auto * Aliasee = dyn_cast < GlobalValue > ( GA -> getAliasee ( ) ) ) F = dyn_cast < Function > ( Aliasee ) ; } bool pagerandoBinTarget = F && F -> isPagerando ( ) ; if ( MF . getFunction ( ) . isPagerando ( ) || pagerandoBinTarget ) { return getPOT ( GN , DAG ) ; } if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { return getGOT ( GN , DAG , OpFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , OpFlags ) ; } else if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Tiny ) { Result = getAddrTiny ( GN , DAG , OpFlags ) ; } else { Result = getAddr ( GN , DAG , OpFlags ) ; }

EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;


<s> if ( Op . isReg ( ) ) { Op . addRegOperands ( Inst , <NUM_LIT> ) ; continue ; } if ( Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ) { IsGdsHardcoded = true ; continue ; } OptionalIdx [ Op . getImmTy ( ) ] = i ; } <ISA_LIT>Operand :: ImmTy OffsetType = ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) ? <ISA_LIT>Operand :: ImmTySwizzle : <ISA_LIT>Operand :: ImmTyOffset ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , OffsetType ) ; if ( ! IsGdsHardcoded ) { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyGDS ) ; }

Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> if ( ! TT . isArch32Bit ( ) && ! TT . isArch64Bit ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; int WordSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; EmitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( FeatureFlagsAnd , <NUM_LIT> ) ; EmitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> endSection ( Nt ) ; OutStreamer -> SwitchSection ( Cur ) ; } } if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: x86 ) {


<s> static SDValue PerformShiftCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * ST ) { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) return PerformSRACombine ( N , DCI ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; int64_t Cnt ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , Cnt ) ) { SDValue RHS = DAG . getNode ( <STR_LIT> , SDLoc ( N -> getOperand ( <NUM_LIT> ) ) , VT , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , RHS ) ; } break ; case <STR_LIT> : case <STR_LIT> :

if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , Cnt ) ) {


<s> void msp430_output_aligned_decl_common ( FILE * stream , const tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align , int local ) { if ( ( msp430_data_region == MSP430_REGION_ANY || ( ( msp430_data_region == MSP430_REGION_LOWER ) && ! TARGET_USE_LOWER_REGION_PREFIX ) ) && ! ( decl != NULL_TREE && DECL_SECTION_NAME ( decl ) ) && ! has_attr ( ATTR_EITHER , decl ) && ! has_attr ( ATTR_LOWER , decl ) && ! has_attr ( ATTR_UPPER , decl ) && ! has_attr ( ATTR_PERSIST , decl ) && ! has_attr ( ATTR_NOINIT , decl ) ) { if ( local ) { fprintf ( stream , LOCAL_ASM_OP ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> ) ; } fprintf ( stream , COMMON_ASM_OP ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> , size , align / BITS_PER_UNIT ) ; } else {


<s> unsigned R600SchedStrategy :: AvailablesAluCount ( ) const { return AvailableAlus [ AluAny ] . size ( ) + AvailableAlus [ AluT_XYZW ] . size ( ) + AvailableAlus [ AluT_X ] . size ( ) + AvailableAlus [ AluT_Y ] . size ( ) + AvailableAlus [ AluT_Z ] . size ( ) + AvailableAlus [ AluT_W ] . size ( ) + AvailableAlus [ AluDiscarded ] . size ( ) + AvailableAlus [ AluPredX ] . size ( ) ;


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( GV -> hasLocalLinkage ( ) ) return false ; if ( ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV -> hasCommonLinkage ( ) ) ) return false ;

Type * Ty = GV -> getType ( ) -> getElementType ( ) ;


<s> if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; if ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( SVT == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) {


<s> AM . BaseOffs = Offset . getSExtValue ( ) ; if ( ! isLegalAddressingMode ( DCI . DAG . getDataLayout ( ) , AM , Ty , AddrSpace ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue ShlX = DAG . getNode ( <STR_LIT> , SL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; SDValue COffset = DAG . getConstant ( Offset , SL , VT ) ; SDNodeFlags Flags ; Flags . setNoUnsignedWrap ( N -> getFlags ( ) . hasNoUnsignedWrap ( ) && ( N0 . getOpcode ( ) == <STR_LIT> || N0 -> getFlags ( ) . hasNoUnsignedWrap ( ) ) ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , ShlX , COffset , Flags ) ;


<s> MCSym = OutContext . GetOrCreateSymbol ( OS . str ( ) ) ; } else if ( ACPV -> isBlockAddress ( ) ) { const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; const char * Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ;

PCRelExpr = MCBinaryExpr :: CreateSub ( PCRelExpr , DotExpr , OutContext ) ;


<s> if ( skipFunction ( * MF . getFunction ( ) ) ) return false ;


<s> if ( ud2 != <NUM_LIT> ) emit_move_insn ( copy_rtx ( temp ) , gen_rtx_IOR ( DImode , copy_rtx ( temp ) , GEN_INT ( ud2 ) ) ) ; emit_move_insn ( ud1 != <NUM_LIT> ? copy_rtx ( temp ) : dest , gen_rtx_ASHIFT ( DImode , copy_rtx ( temp ) , GEN_INT ( <NUM_LIT> ) ) ) ; if ( ud1 != <NUM_LIT> ) emit_move_insn ( dest , gen_rtx_IOR ( DImode , copy_rtx ( temp ) , GEN_INT ( ud1 ) ) ) ; } else { temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( DImode ) ; emit_move_insn ( copy_rtx ( temp ) , GEN_INT ( ( ( ud4 << <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ) ) ; if ( ud3 != <NUM_LIT> ) emit_move_insn ( copy_rtx ( temp ) , gen_rtx_IOR ( DImode , copy_rtx ( temp ) , GEN_INT ( ud3 ) ) ) ; emit_move_insn ( ud2 != <NUM_LIT> || ud1 != <NUM_LIT> ? copy_rtx ( temp ) : dest , gen_rtx_ASHIFT ( DImode , copy_rtx ( temp ) , GEN_INT ( <NUM_LIT> ) ) ) ;

if ( ud2 != <NUM_LIT> ) emit_move_insn ( ud1 != <NUM_LIT> ? copy_rtx ( temp ) : dest , gen_rtx_IOR ( DImode , copy_rtx ( temp ) , GEN_INT ( ud2 << <NUM_LIT> ) ) ) ;


<s> switch ( Opcode ) { default : return Instruction :: isShift ( Opcode ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ExtractElement : case Instruction :: ExtractValue : case Instruction :: InsertElement : case Instruction :: InsertValue : return true ; }


<s> <ISA_LIT>PacketizerList ( MachineFunction & MF , MachineLoopInfo & MLI ) : VLIWPacketizerList ( MF , MLI , nullptr ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ) , TRI ( TII -> getRegisterInfo ( ) ) { VLIW5 = ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCaymanISA ( ) ;


<s> void addLiveInstr ( MachineInstr * MI ) { liveInstrs . insert ( MI ) ;


<s> assert ( ! Store -> isIndexed ( ) ) ; if ( ! SelectAddr ( Addr , Base , Reg , Offset ) ) return false ; unsigned AS = Store -> getAddressSpace ( ) ; MVT MemVT = Store -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned BrigType = getBrigTypeFromStoreType ( MemVT . SimpleTy ) ; SDLoc SL ( ParentStore ) ; Segment = CurDAG -> getTargetConstant ( AS , SL , <STR_LIT> ) ; Align = CurDAG -> getTargetConstant ( Store -> getAlignment ( ) , SL , <STR_LIT> ) ; Type = CurDAG -> getTargetConstant ( BrigType , SL , <STR_LIT> ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) return expandTLSLA ( MI ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return emitCustomConstantPool ( MI ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ;

EmitToStreamer ( * OutStreamer , TmpInst ) ;


<s> if ( MaskAfter ) { unsigned SPReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ( <STR_LIT> == SPReg ) && <STR_LIT> ) ; emitMask ( SPReg , LoadStoreStackMaskReg , STI ) ; } EmitBundleUnlock ( ) ;


<s> static Optional < Instruction * > instCombineSVEZip ( InstCombiner & IC , IntrinsicInst & II ) { Value * A , * B ; if ( match ( II . getArgOperand ( <NUM_LIT> ) , m_Intrinsic < <STR_LIT> > ( m_Value ( A ) , m_Value ( B ) ) ) && match ( II . getArgOperand ( <NUM_LIT> ) , m_Intrinsic < <STR_LIT> > ( m_Specific ( A ) , m_Specific ( B ) ) ) ) return IC . replaceInstUsesWith ( II , ( II . getIntrinsicID ( ) == <STR_LIT> ? A : B ) ) ;


<s> unsigned Reg = fastEmit_ISD_BITCAST_r ( VT . getSimpleVT ( ) , RetVT . getSimpleVT ( ) , In , I -> getOperand ( <NUM_LIT> ) -> hasOneUse ( ) ) ; if ( ! Reg ) return false ; MachineBasicBlock :: iterator Iter = FuncInfo . InsertPt ; -- Iter ; assert ( Iter -> isBitcast ( ) ) ;

Iter -> setPhysRegsDeadExcept ( ArrayRef < unsigned > ( ) , TRI ) ;


<s> static void riscv_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned argno ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( op , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } static rtx riscv_expand_builtin_insn ( enum insn_code icode , unsigned int n_ops , struct expand_operand * ops , bool has_target_p ) { if ( ! maybe_expand_insn ( icode , n_ops , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; } return has_target_p ? ops [ <NUM_LIT> ] . value : const0_rtx ; } static rtx riscv_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno = <NUM_LIT> ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( int argno = <NUM_LIT> ; argno < call_expr_nargs ( exp ) ; argno ++ ) riscv_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return riscv_expand_builtin_insn ( icode , opno , ops , has_target_p ) ; } rtx riscv_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; const struct riscv_builtin_description * d = & riscv_builtins [ fcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ; case RISCV_BUILTIN_DIRECT_NO_TARGET : return riscv_expand_builtin_direct ( d -> icode , target , exp , false ) ; } gcc_unreachable ( ) ; } void riscv_atomic_assign_expand_fenv ( tree * hold , tree * clear , tree * update ) { if ( ! TARGET_HARD_FLOAT ) return ;

tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ;


<s> return __builtin_shuffle ( a , ( uint16x4_t ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> struct cpp_dir * dir ; if ( ! stdinc ) return ; for ( dir = get_added_cpp_dirs ( INC_SYSTEM ) ; dir != NULL ; dir = dir -> next ) { const char * const * lib ; for ( lib = vms_std_modules ; * lib != NULL ; lib ++ ) { char * path ; struct stat st ; if ( sysroot != NULL ) path = concat ( sysroot , dir -> name , dir_separator_str , * lib , NULL ) ; else path = concat ( dir -> name , dir_separator_str , * lib , NULL ) ; if ( stat ( path , & st ) == <NUM_LIT> && S_ISDIR ( st . st_mode ) ) { cpp_dir * p ; p = XNEW ( cpp_dir ) ; p -> next = NULL ; p -> name = path ; p -> sysp = <NUM_LIT> ; p -> construct = vms_construct_include_filename ;


<s> const MachineInstr * PI = PacketSU -> getInstr ( ) ; if ( PI -> isInlineAsm ( ) ) return false ; if ( PI -> isImplicitDef ( ) ) return false ; if ( isImplicitDependency ( PI , DepReg ) ) return false ; const MCInstrDesc & MCID = PI -> getDesc ( ) ; const TargetRegisterClass * VecRC = HII -> getRegClass ( MCID , <NUM_LIT> , HRI , MF ) ; if ( DisableVecDblNVStores && VecRC == & <STR_LIT> ) return false ; if ( RC == & <STR_LIT> ) if ( HII -> isCondInst ( MI ) || MI -> isReturn ( ) ) return HII -> predCanBeUsedAsDotNew ( PI , DepReg ) ; if ( RC != & <STR_LIT> && ! HII -> mayBeNewStore ( MI ) ) return false ; int NewOpcode = HII -> getDotNewOp ( MI ) ; const MCInstrDesc & D = HII -> get ( NewOpcode ) ; MachineInstr * NewMI = MF . CreateMachineInstr ( D , DebugLoc ( ) ) ; bool ResourcesAvailable = ResourceTracker -> canReserveResources ( * NewMI ) ; MF . DeleteMachineInstr ( NewMI ) ; if ( ! ResourcesAvailable ) return false ; if ( ! canPromoteToNewValue ( MI , PacketSU , DepReg , MII ) ) return false ; return true ;


<s> return ( __m64 ) __builtin_ia32_pfrcp ( ( __v2sf ) __A ) ;


<s> BaseOpIdx = <NUM_LIT> ; OffsetOpIdx = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( OffsetOpIdx ) ) ) continue ; SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset2 = N -> getConstantOperandVal ( OffsetOpIdx ) ; if ( auto Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { int64_t Offset1 = Const -> getSExtValue ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; if ( ! isInt < <NUM_LIT> > ( CombinedOffset ) ) continue ; ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { const DataLayout & DL = CurDAG -> getDataLayout ( ) ; Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = GA -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , CombinedOffset , GA -> getTargetFlags ( ) ) ; } else if ( auto CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { Align Alignment = CP -> getAlign ( ) ;


<s> unsigned TypeSize = DL . getTypeStoreSize ( ParamTy ) ; Register PtrReg = lowerParameterPtr ( B , ParamTy , Offset ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , TypeSize , Align ) ;

B . buildLoad ( DstReg , PtrReg , * MMO ) ;


<s> for ( const ExpTgt & Val : ExpTgtInfo ) { if ( Val . Tgt <= Id && Id <= Val . Tgt + Val . MaxIndex ) {

Index = ( Val . MaxIndex == <NUM_LIT> ) ? - <NUM_LIT> : ( Id - Val . Tgt ) ;


<s> if ( ! TT . isOSEmscripten ( ) ) { return Reloc :: Static ; } return * RM ;


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetLowering :: getSubtarget ( ) const { return static_cast < const <ISA_LIT>Subtarget * > ( Subtarget ) ;


<s> if ( ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) || ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) ) return false ; if ( STI . hasUsableDSOffset ( ) || STI . unsafeDSOffsetFoldingEnabled ( ) ) return true ;

return KnownBits -> signBitIsZero ( Base . getReg ( ) ) ;


<s> if ( has_attr ( ATTR_UPPER , decl ) || has_attr ( ATTR_EITHER , decl ) || has_attr ( ATTR_PERSIST , decl ) || ( ! has_attr ( ATTR_LOWER , decl ) && ! has_attr ( ATTR_NOINIT , decl ) && ( has_attr ( <STR_LIT> , decl ) || msp430_data_region == MSP430_REGION_UPPER || msp430_data_region == MSP430_REGION_EITHER || msp430_data_region == MSP430_REGION_ANY ) ) ) return false ; return true ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isAIXABI ( ) ) return LowerFormalArguments_AIX ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ;

if ( Subtarget . is64BitELFABI ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ;


<s> if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>LongBranchPass ( <ISA_LIT>TargetMachine & tm ) {


<s> rtx x = find_reg_note ( insn , REG_BR_PROB , <NUM_LIT> ) ; if ( x ) { int pred_val = XINT ( x , <NUM_LIT> ) ; return pred_val >= REG_BR_PROB_BASE / <NUM_LIT> ; } return <NUM_LIT> ;


<s> uint64_t Disp = Field & <NUM_LIT> ; assert ( Length < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Disp ) ) ;

Inst . addOperand ( MCOperand :: createImm ( Length + <NUM_LIT> ) ) ;


<s> void relaxInstruction ( MCInst & Inst , const MCSubtargetInfo & STI ) const override { llvm_unreachable ( <STR_LIT> ) ;


<s> bool isDelimiter ( const StorageType :: value_type & P , NodeId N = <NUM_LIT> ) const { return ( P . Addr == nullptr ) && ( N == <NUM_LIT> || P . Id == N ) ;


<s> unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / vectorWidth ) * ElemsPerChunk ) ;

if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResultVT , makeArrayRef ( Vec -> op_begin ( ) + NormalizedIdxVal , ElemsPerChunk ) ) ;


<s> ShAmt = ShAmt . getOperand ( <NUM_LIT> ) ; MVT AmtTy = ShAmt . getSimpleValueType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , AmtTy , ShAmt ) ; if ( Subtarget . hasSSE41 ( ) ) ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; else { SDValue ByteShift = DAG . getTargetConstant ( ( <NUM_LIT> - AmtTy . getScalarSizeInBits ( ) ) / <NUM_LIT> , SDLoc ( ShAmt ) , <STR_LIT> ) ; ShAmt = DAG . getBitcast ( <STR_LIT> , ShAmt ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt , ByteShift ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt , ByteShift ) ; } } else if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> ) { ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; } else { SDValue ShOps [ <NUM_LIT> ] = { ShAmt , DAG . getConstant ( <NUM_LIT> , dl , SVT ) , DAG . getUNDEF ( SVT ) , DAG . getUNDEF ( SVT ) } ;

ShAmt = DAG . getBuildVector ( <STR_LIT> , dl , ShOps ) ;


<s> if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = InVec . getValueType ( ) . getVectorNumElements ( ) ; unsigned i = <NUM_LIT> ; for ( ; i != NumElts ; ++ i ) { SDValue Arg = InVec . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; BaseShAmt = Arg ; break ; } } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { unsigned SplatIdx = cast < ShuffleVectorSDNode > ( ShAmtOp ) -> getSplatIndex ( ) ; if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( BaseShAmt . getNode ( ) == <NUM_LIT> ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , EltVT , ShAmtOp , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else return SDValue ( ) ; if ( EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; SDValue ValOp = N -> getOperand ( <NUM_LIT> ) ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

return getTargetVShiftNode ( <STR_LIT> , DL , VT , ValOp , BaseShAmt , DAG ) ;


<s> int ValueSplitCost = getScalarizationOverhead ( SrcVTy , DemandedElts , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ; else if ( LT . second . getVectorNumElements ( ) > NumElem ) {

VectorType * NewMaskTy = VectorType :: get ( MaskTy -> getElementType ( ) , LT . second . getVectorNumElements ( ) ) ;


<s> MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( AbsOffset ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; return MI ;


<s> const InlineAsmIdentifierInfo & Info = SM . getIdentifierInfo ( ) ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { Operands . push_back ( <STR_LIT> ( Disp , Start , End , SM . getSymName ( ) , Info . Var . Decl , Info . Var . IsGlobalLV ) ) ; return false ; } } Operands . push_back ( <STR_LIT> ( Disp , Start , End ) ) ; return false ; } StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ; unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( ! PtrInOperand ) Size = SM . getElementSize ( ) << <NUM_LIT> ; if ( Scale == <NUM_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale == <NUM_LIT> && ! ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) return Error ( Start , <STR_LIT> ) ; if ( Scale == <NUM_LIT> ) Scale = <NUM_LIT> ; if ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( ( BaseReg || IndexReg ) && CheckBaseRegAndIndexRegAndScale ( BaseReg , IndexReg , Scale , is64BitMode ( ) , ErrMsg ) ) return Error ( Start , ErrMsg ) ; if ( isParsingMSInlineAsm ( ) ) return CreateMemForMSInlineAsm ( RegNo , Disp , BaseReg , IndexReg , Scale , Start , End , Size , SM . getSymName ( ) , SM . getIdentifierInfo ( ) , Operands ) ;

if ( Parser . isParsingMasm ( ) && is64BitMode ( ) ) {


<s> SmallSet < MachineBasicBlock * , <NUM_LIT> > RestoreBlocks ; if ( MFI . getSavePoint ( ) ) { SaveBlocks . insert ( MFI . getSavePoint ( ) ) ; RestoreBlocks . insert ( MFI . getRestorePoint ( ) ) ; } else { SaveBlocks . insert ( & MF . front ( ) ) ; for ( MachineBasicBlock & MBB : MF ) if ( MBB . isReturnBlock ( ) ) RestoreBlocks . insert ( & MBB ) ; } SmallVector < MachineBasicBlock * , <NUM_LIT> > WorkList ; SmallSet < MachineBasicBlock * , <NUM_LIT> > VisitedBlocks ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . front ( ) . getName ( ) << <STR_LIT> ) ; WorkList . push_back ( & MF . front ( ) ) ; for ( MachineBasicBlock & MBB : MF ) { if ( MBB . isReturnBlock ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; WorkList . push_back ( & MBB ) ; } } auto CheckOutsideInst = [ & UnsaveableRegs , TRI ] ( MachineInstr & MI ) { for ( Register Reg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { if ( MI . modifiesRegister ( Reg , TRI ) ) { UnsaveableRegs . set ( Reg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg ) << <STR_LIT> << MI << <STR_LIT> ) ; } } } ; while ( ! WorkList . empty ( ) ) { MachineBasicBlock * MBB = WorkList . pop_back_val ( ) ; if ( VisitedBlocks . count ( MBB ) ) continue ; VisitedBlocks . insert ( MBB ) ; bool IsSave = SaveBlocks . count ( MBB ) ; bool IsRestore = RestoreBlocks . count ( MBB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> << IsSave << <STR_LIT> << IsRestore << <STR_LIT> ) ; if ( IsRestore ) { LivePhysRegs LPR ( * TRI ) ; LPR . addLiveOuts ( * MBB ) ; for ( auto & Term : reverse ( MBB -> terminators ( ) ) ) { LPR . stepBackward ( Term ) ;


<s> BeginToEnd . clear ( ) ; EndToBegin . clear ( ) ; TryToEHPad . clear ( ) ;


<s> unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Rn == <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; StackPtr = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) ;

<ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( ) ;


<s> const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI , Paired ) ; Register SrcReg = MRI -> createVirtualRegister ( SuperRC ) ; const auto * Src0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Src1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , InsertBefore , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; AddressRegs Regs = getRegs ( Opcode , * TII ) ; if ( Regs . VAddr ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; unsigned JoinedFormat = getBufferFormatWithCompCount ( CI . Format , CI . Width + Paired . Width , * STM ) ;

assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ;


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; }


<s> bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; isTailCall = false ; bool needsRegArgSlots = isVarArg ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering & TFI = * MF . getTarget ( ) . getFrameLowering ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; if ( isVarArg && NumBytes < <NUM_LIT> ) NumBytes = <NUM_LIT> ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , dl ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; MVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , RegVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , RegVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , RegVT , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; needsRegArgSlots = false ; unsigned ArgSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned StackLoc = VA . getLocMemOffset ( ) + <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , StackLoc , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ;

MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ;


<s> void override_options ( void ) { if ( TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY ) error ( <STR_LIT> ) ; if ( TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY ) flag_pic = <NUM_LIT> ;

if ( ! TARGET_68020 && ! TARGET_COLDFIRE && ( flag_pic == <NUM_LIT> ) ) error ( <STR_LIT> ) ;


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;


<s> for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { int SrcIdx = getOperandIdx ( MI -> getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ; if ( SrcIdx < <NUM_LIT> ) break ; if ( MI -> getOperand ( SrcIdx ) . getReg ( ) == AMDGPU :: ALU_CONST ) { unsigned Const = MI -> getOperand ( getOperandIdx ( MI -> getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) . getImm ( ) ; Consts . push_back ( Const ) ; } } }

return fitsConstReadLimitations ( Consts ) ;


<s> const TargetInstrInfo * TII = TM -> getInstrInfo ( ) ;


<s> aarch64_layout_frame ( ) ; if ( to == HARD_FRAME_POINTER_REGNUM ) { if ( from == ARG_POINTER_REGNUM ) return cfun -> machine -> frame . hard_fp_offset ; if ( from == FRAME_POINTER_REGNUM ) return cfun -> machine -> frame . hard_fp_offset - cfun -> machine -> frame . locals_offset ; } if ( to == STACK_POINTER_REGNUM ) { if ( from == FRAME_POINTER_REGNUM ) return cfun -> machine -> frame . frame_size - cfun -> machine -> frame . locals_offset ; }

return cfun -> machine -> frame . frame_size ;


<s> AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> return ( __m128i ) __builtin_ia32_pmovusdb256_mask ( ( __v8si ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> raw_string_ostream OS ( TmpStr ) ; PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; case <STR_LIT> : { MCInst TmpInst ; MCSymbol * PICBase = MCInstLowering . GetPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ;

const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ;


<s> virtual AMDGPUTargetLowering * getTargetLowering ( ) const {


<s> void addMemTBBOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ;

return lower<ISA_LIT>FPLogicOp ( N , DAG , Subtarget ) ;


<s> HOST_WIDE_INT size = int_size_in_bytes ( type ) ;

if ( TREE_CODE ( type ) == COMPLEX_TYPE ) if ( size < <NUM_LIT> || size > <NUM_LIT> * UNITS_PER_WORD ) return true ;


<s> static StringRef computeDataLayout ( const Triple & TT ) { if ( TT . getArch ( ) == Triple :: r600 ) { return <STR_LIT> <STR_LIT> ; } return <STR_LIT> <STR_LIT> <STR_LIT> ;


<s> auto NumUnmerge = B . buildUnmerge ( S32 , LHS ) ; auto DenUnmerge = B . buildUnmerge ( S32 , RHS ) ; auto Scale0Unmerge = B . buildUnmerge ( S32 , DivScale0 ) ; auto Scale1Unmerge = B . buildUnmerge ( S32 , DivScale1 ) ; auto CmpNum = B . buildICmp ( ICmpInst :: ICMP_EQ , S1 , NumUnmerge . getReg ( <NUM_LIT> ) , Scale1Unmerge . getReg ( <NUM_LIT> ) ) ; auto CmpDen = B . buildICmp ( ICmpInst :: ICMP_EQ , S1 , DenUnmerge . getReg ( <NUM_LIT> ) , Scale0Unmerge . getReg ( <NUM_LIT> ) ) ; Scale = B . buildXor ( S1 , CmpNum , CmpDen ) . getReg ( <NUM_LIT> ) ; } else { Scale = DivScale1 . getReg ( <NUM_LIT> ) ; }

auto Fmas = B . buildIntrinsic ( <STR_LIT> , { S64 } , false ) . addUse ( Fma4 . getReg ( <NUM_LIT> ) ) . addUse ( Fma3 . getReg ( <NUM_LIT> ) ) . addUse ( Mul . getReg ( <NUM_LIT> ) ) . addUse ( Scale ) . setMIFlags ( Flags ) ;


<s> if ( ! ST -> hasMVEFloatOps ( ) ) break ; Type * VT = ICA . getReturnType ( ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VT ) ; if ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) return LT . first * ST -> getMVEVectorCostFactor ( CostKind ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( ICA . getArgTypes ( ) . empty ( ) ) break ; bool IsSigned = ICA . getID ( ) == <STR_LIT> ; auto LT = TLI -> getTypeLegalizationCost ( DL , ICA . getArgTypes ( ) [ <NUM_LIT> ] ) ; EVT MTy = TLI -> getValueType ( DL , ICA . getReturnType ( ) ) ; if ( ( ST -> hasVFP2Base ( ) && LT . second == <STR_LIT> && MTy == <STR_LIT> ) || ( ST -> hasFP64 ( ) && LT . second == <STR_LIT> && MTy == <STR_LIT> ) || ( ST -> hasFullFP16 ( ) && LT . second == <STR_LIT> && MTy == <STR_LIT> ) ) return LT . first ; if ( ST -> hasMVEFloatOps ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) && LT . second . getScalarSizeInBits ( ) == MTy . getScalarSizeInBits ( ) ) return LT . first * ST -> getMVEVectorCostFactor ( CostKind ) ; if ( ( ( ST -> hasVFP2Base ( ) && LT . second == <STR_LIT> ) || ( ST -> hasFP64 ( ) && LT . second == <STR_LIT> ) || ( ST -> hasFullFP16 ( ) && LT . second == <STR_LIT> ) || ( ST -> hasMVEFloatOps ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ) ) && LT . second . getScalarSizeInBits ( ) >= MTy . getScalarSizeInBits ( ) ) { Type * LegalTy = Type :: getIntNTy ( ICA . getReturnType ( ) -> getContext ( ) , LT . second . getScalarSizeInBits ( ) ) ; InstructionCost Cost = LT . second . isVector ( ) ? ST -> getMVEVectorCostFactor ( CostKind ) : <NUM_LIT> ; IntrinsicCostAttributes Attrs1 ( IsSigned ? <STR_LIT> : <STR_LIT> , LegalTy , { LegalTy , LegalTy } ) ; Cost += getIntrinsicInstrCost ( Attrs1 , CostKind ) ; IntrinsicCostAttributes Attrs2 ( IsSigned ? <STR_LIT> : <STR_LIT> , LegalTy , { LegalTy , LegalTy } ) ; Cost += getIntrinsicInstrCost ( Attrs2 , CostKind ) ; return LT . first * Cost ; } break ;


<s> std :: string sep = <STR_LIT> ; if ( e == static_cast < uint32_t > ( MemorySemantics :: None ) ) return <STR_LIT> ; if ( e == static_cast < uint32_t > ( MemorySemantics :: Acquire ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( MemorySemantics :: Acquire ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( MemorySemantics :: Release ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( MemorySemantics :: Release ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( MemorySemantics :: AcquireRelease ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( MemorySemantics :: AcquireRelease ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( MemorySemantics :: SequentiallyConsistent ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( MemorySemantics :: SequentiallyConsistent ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( MemorySemantics :: UniformMemory ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( MemorySemantics :: UniformMemory ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( MemorySemantics :: SubgroupMemory ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( MemorySemantics :: SubgroupMemory ) ) {


<s> static TargetLoweringObjectFile * createTLOF ( <ISA_LIT>TargetMachine & TM ) { const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isTargetLinux ( ) ) return new <ISA_LIT>LinuxTargetObjectFile ( ) ;

if ( Subtarget -> isTargetELF ( ) ) return new TargetLoweringObjectFileELF ( ) ;


<s> void addu5ImmOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N ) ;


<s> unsigned LoOpc = LowRegInst -> getOpcode ( ) ; ( void ) HiOpc ; ( void ) LoOpc ; assert ( ( HiOpc == <STR_LIT> || HiOpc == <STR_LIT> ) && ( LoOpc == <STR_LIT> || LoOpc == <STR_LIT> ) && <STR_LIT> ) ; if ( isGreaterThanNBitTFRI < <NUM_LIT> > ( HighRegInst ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( LowRegInst ) ) return false ; return true ;