<s> if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) getTargetStreamer ( ) -> getPALMetadata ( ) -> readFromIR ( M ) ; if ( IsaInfo :: hasCodeObjectV3 ( getGlobalSTI ( ) ) ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectVersion ( <NUM_LIT> , <NUM_LIT> ) ;

IsaVersion Version = getIsaVersion ( getGlobalSTI ( ) -> getCPU ( ) ) ;


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target , create<ISA_LIT>Disassembler ) ;


<s> replaceb = int_rtx ; } else { offset_rtx = int_rtx ; replacea = NULL_RTX ; replaceb = NULL_RTX ; } reg = gen_rtx_REG ( mode , regno ) ; addr = gen_rtx_PLUS ( Pmode , frame_reg , offset_rtx ) ; mem = gen_rtx_MEM ( mode , addr ) ; set_mem_alias_set ( mem , rs6000_sr_alias_set ) ;


<s> TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createAsmTargetStreamer ) ; } TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getTheE<ISA_LIT>Target ( ) , createE<ISA_LIT>AsmBackend ) ;


<s> assert ( JTI < JT . size ( ) ) ; bool ByteOk = true ; bool HalfWordOk = true ; unsigned JTOffset = getOffsetOf ( MI ) + <NUM_LIT> ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; unsigned DstOffset = BBInfo [ MBB -> getNumber ( ) ] . Offset ; if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { if ( ! printAliasInstr ( MI , STI , OS ) ) printInstruction ( MI , Address , STI , OS ) ; printAnnotation ( OS , Annot ) ;


<s> switch ( MI . getOpcode ( ) ) { default : if ( MI . isMetaInstruction ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ;


<s> return isMem ( ) && ! Mem . Index && ! Mem . Disp && Mem . Update == PreDecrement ;


<s> int getMCOpcode ( uint16_t Opcode , unsigned Gen ) {

return getMCOpcodeGen ( Opcode , ( enum Subtarget ) Gen ) ;


<s> if ( TARGET_GENERAL_REGS_ONLY ) if ( FLOAT_MODE_P ( mode ) ) error ( <STR_LIT> , <STR_LIT> ) ; else error ( <STR_LIT> , <STR_LIT> ) ; else if ( FLOAT_MODE_P ( mode ) ) error ( <STR_LIT> <STR_LIT> , <STR_LIT> ) ; else error ( <STR_LIT> <STR_LIT> , <STR_LIT> ) ;


<s> else { * sh_deferred_function_attributes_tail = tree_cons ( id , NULL_TREE , * sh_deferred_function_attributes_tail ) ; sh_deferred_function_attributes_tail = & TREE_CHAIN ( * sh_deferred_function_attributes_tail ) ;


<s> if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Indices [ i ] , SubVecTy -> getNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ; if ( VecLength == <NUM_LIT> || VecLength == <NUM_LIT> ) { VecBaseTy = FixedVectorType :: get ( Type :: getInt8Ty ( LI -> getContext ( ) ) , <NUM_LIT> ) ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; NumLoads = NumSubVectors * ( VecLength / <NUM_LIT> ) ; } else { VecBaseTy = SubVecTy ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;

* cum += ( type && TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ? <NUM_LIT> : mode == BLKmode ? ( ( int_size_in_bytes ( type ) + <NUM_LIT> ) / <NUM_LIT> ) : mode == VOIDmode ? <NUM_LIT> : spu_hard_regno_nregs ( FIRST_ARG_REGNUM , mode ) ) ;


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , CSI [ i ] . getReg ( ) ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI , UId ) ; } if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI , UId ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI , UId ) ;


<s> virtual void EmitARM64WinCFIEpilogEnd ( ) {


<s> BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; } BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> void printqwordmem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


<s> AMDGPUPromoteAlloca ( const AMDGPUSubtarget & st ) : FunctionPass ( ID ) , ST ( st ) , LocalMemAvailable ( <NUM_LIT> ) {


<s> bool <ISA_LIT>InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const {


<s> if ( DstRC != SrcRC ) return false ; if ( DstRC == InsRC ) return true ; if ( DstRC == & <STR_LIT> ) return false ;

if ( S < <NUM_LIT> && S + L > <NUM_LIT> ) return false ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectSETCC ( SDNode * N ) { SDLoc dl ( N ) ; unsigned Imm ; <STR_LIT> CC = cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; EVT PtrVT = CurDAG -> getTargetLoweringInfo ( ) . getPointerTy ( CurDAG -> getDataLayout ( ) ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; if ( ! <ISA_LIT>SubTarget -> useCRBits ( ) && isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Imm ) ) { if ( Imm == <NUM_LIT> ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; switch ( CC ) { default : break ; case <STR_LIT> : { Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { Op , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { if ( is<ISA_LIT>64 ) break ; SDValue AD = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( ~ <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , AD , Op , AD . getValue ( <NUM_LIT> ) ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Op , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } case <STR_LIT> : { SDValue T = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op ) , <NUM_LIT> ) ; T = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , T , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { T , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; } } } else if ( Imm == ~ <NUM_LIT> ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; switch ( CC ) { default : break ; case <STR_LIT> : if ( is<ISA_LIT>64 ) break ; Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) , Op . getValue ( <NUM_LIT> ) ) ; case <STR_LIT> : { if ( is<ISA_LIT>64 ) break ;

Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op , Op ) , <NUM_LIT> ) ;


<s> SDNode * <ISA_LIT>SEDAGToDAGISel :: selectAddESubE ( unsigned MOp , SDValue InFlag , SDValue CmpLHS , DebugLoc DL , SDNode * Node ) const { unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ;

SDValue LHS = Node -> getOperand ( <NUM_LIT> ) , RHS = Node -> getOperand ( <NUM_LIT> ) ;


<s> int FI = PFI -> getFramePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } if ( PFI -> usesPICBase ( ) ) { HasGPSaveArea = true ; int FI = PFI -> getPICBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) { HasGPSaveArea = true ; int FI = PFI -> getBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } unsigned MinReg = std :: min < unsigned > ( TRI -> getEncodingValue ( MinGPR ) , TRI -> getEncodingValue ( MinG8R ) ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } else { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } } if ( spillsCR ( MF ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ( Subtarget . isSVR4ABI ( ) && Reg == <STR_LIT> ) || ( ! Subtarget . isSVR4ABI ( ) && ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } }


<s> } if ( bytes > <NUM_LIT> ) return ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; ++ i ) { if ( ! isSrcOperand ( Desc , i ) ) continue ; const MCOperand & Op = MI . getOperand ( i ) ; if ( getLitEncoding ( Op ) != <NUM_LIT> ) continue ; IntFloatUnion Imm ; if ( Op . isImm ( ) ) Imm . I = Op . getImm ( ) ; else Imm . F = Op . getFPImm ( ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { OS . write ( ( uint8_t ) ( ( Imm . I >> ( <NUM_LIT> * j ) ) & <NUM_LIT> ) ) ; } break ;


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFINop ( ) {


<s> static void arm_elf_asm_constructor ( rtx symbol , int priority ) {

arm_elf_asm_cdtor ( symbol , priority , true ) ;


<s> INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan ( insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn ) ) ;


<s> L = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) return Error ( L , <STR_LIT> ) ; int64_t Value = Parser . getTok ( ) . getIntVal ( ) ; Parser . Lex ( ) ; getTargetStreamer ( ) . emitAttribute ( Tag , Value ) ;


<s> unsigned getLabelId ( ) const { return LabelId ;


<s> case <STR_LIT> : MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( BitSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addImm ( I -> Op2 ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ;

MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && LastItem ) ) . addImm ( I -> Op1 ) . addImm ( I -> Op2 ) ) ;


<s> tree fntype = TREE_TYPE ( current_function_decl ) ; int argadj = ( ( ! stdarg_p ( fntype ) ) ? UNITS_PER_WORD : <NUM_LIT> ) ; alias_set_type set = get_varargs_alias_set ( ) ; if ( argadj ) offset = plus_constant ( Pmode , crtl -> args . arg_offset_rtx , argadj ) ; else offset = crtl -> args . arg_offset_rtx ; mem = gen_rtx_MEM ( SImode , crtl -> args . internal_arg_pointer ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , crtl -> args . internal_arg_pointer , <NUM_LIT> ) ) ; set_mem_alias_set ( mem , set ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; return copy_to_reg ( expand_binop ( Pmode , add_optab , crtl -> args . internal_arg_pointer , offset , <NUM_LIT> , <NUM_LIT> , OPTAB_LIB_WIDEN ) ) ;


<s> tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_frflags ) ; tree fsflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_fsflags ) ; tree old_flags = create_tmp_var_raw ( RISCV_ATYPE_USI ) ; * hold = build4 ( TARGET_EXPR , RISCV_ATYPE_USI , old_flags , build_call_expr ( frflags , <NUM_LIT> ) , NULL_TREE , NULL_TREE ) ; * clear = build_call_expr ( fsflags , <NUM_LIT> , old_flags ) ;


<s> <ISA_LIT>OptAddrMode ( ) : MachineFunctionPass ( ID ) {


<s> } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & <NUM_LIT> ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; }


<s> memcpy ( have_regs_of_mode , m_old_have_regs_of_mode , sizeof ( have_regs_of_mode ) ) ;


<s> void PadShortFunc :: addPadding ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator & MBBI , unsigned int NOOPsToAdd ) { DebugLoc DL = MBBI -> getDebugLoc ( ) ; while ( NOOPsToAdd -- > <NUM_LIT> ) { BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ;


<s> if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler :: Success ;


<s> register union double_long dl1 ; register long exp ; register long l ; dl1 . d = a1 ; if ( ! dl1 . l . upper && ! dl1 . l . lower ) return <NUM_LIT> ; exp = EXPD ( dl1 ) - EXCESSD - <NUM_LIT> ; l = MANTD ( dl1 ) ; if ( exp > <NUM_LIT> ) {

return SIGND ( dl1 ) ? <NUM_LIT> : <NUM_LIT> ;


<s> unsigned Opc = LdSt . getOpcode ( ) ; if ( isDS ( LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; if ( OffsetImm ) { BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: addr ) ; Offset = OffsetImm -> getImm ( ) ; assert ( BaseOp -> isReg ( ) && <STR_LIT> <STR_LIT> ) ; return true ; } const MachineOperand * Offset0Imm = getNamedOperand ( LdSt , <STR_LIT> :: offset0 ) ; const MachineOperand * Offset1Imm = getNamedOperand ( LdSt , <STR_LIT> :: offset1 ) ; uint8_t Offset0 = Offset0Imm -> getImm ( ) ; uint8_t Offset1 = Offset1Imm -> getImm ( ) ; if ( Offset1 > Offset0 && Offset1 - Offset0 == <NUM_LIT> ) { unsigned EltSize ; if ( LdSt . mayLoad ( ) ) EltSize = TRI -> getRegSizeInBits ( * getOpRegClass ( LdSt , <NUM_LIT> ) ) / <NUM_LIT> ; else { assert ( LdSt . mayStore ( ) ) ; int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = TRI -> getRegSizeInBits ( * getOpRegClass ( LdSt , Data0Idx ) ) / <NUM_LIT> ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: addr ) ; Offset = EltSize * Offset0 ; assert ( BaseOp -> isReg ( ) && <STR_LIT> <STR_LIT> ) ; return true ; } return false ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { const MachineOperand * SOffset = getNamedOperand ( LdSt , <STR_LIT> :: soffset ) ; if ( SOffset && SOffset -> isReg ( ) ) return false ; MachineOperand * AddrReg = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ;


<s> switch ( CallConv ) { case CallingConv :: C : case CallingConv :: Fast :

return LowerCCCArguments ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ;


<s> if ( ! File -> getFilename ( ) . startswith ( <STR_LIT> ) && File -> getDirectory ( ) . size ( ) ) FileName = File -> getDirectory ( ) . str ( ) + <STR_LIT> + File -> getFilename ( ) . str ( ) ; else FileName = File -> getFilename ( ) ; if ( FileContent . find ( FileName ) != FileContent . end ( ) ) return FileName ; std :: vector < std :: string > Content ; std :: string Line ; Content . push_back ( Line ) ; std :: unique_ptr < MemoryBuffer > Buf ; auto Source = File -> getSource ( ) ;

if ( Source ) Buf = MemoryBuffer :: getMemBufferCopy ( * Source ) ;


<s> case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint32_t Trunc = static_cast < uint32_t > ( Imm ) ; return <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; }


<s> size_t <ISA_LIT>ToTHMStub :: size ( ) const { return m_Size ;


<s> } ; setBitVector ( <STR_LIT> ) ; setBitVector ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { setBitVector ( FramePtr ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> <STR_LIT> ) ; setBitVector ( getBaseRegister ( ) ) ; }


<s> return ( reload_completed && ! frame_pointer_needed && get_frame_size ( ) == <NUM_LIT> && compute_saved_regs ( ) == <NUM_LIT> ) ;


<s> switch ( e ) { CASE ( ImageFormat , Unknown ) CASE ( ImageFormat , Rgba32f ) CASE ( ImageFormat , Rgba16f ) CASE ( ImageFormat , R32f ) CASE ( ImageFormat , Rgba8 ) CASE ( ImageFormat , Rgba8Snorm ) CASE ( ImageFormat , Rg32f ) CASE ( ImageFormat , Rg16f ) CASE ( ImageFormat , R11fG11fB10f ) CASE ( ImageFormat , R16f ) CASE ( ImageFormat , Rgba16 ) CASE ( ImageFormat , Rgb10A2 ) CASE ( ImageFormat , Rg16 ) CASE ( ImageFormat , Rg8 ) CASE ( ImageFormat , R16 ) CASE ( ImageFormat , R8 ) CASE ( ImageFormat , Rgba16Snorm ) CASE ( ImageFormat , Rg16Snorm ) CASE ( ImageFormat , Rg8Snorm ) CASE ( ImageFormat , R16Snorm ) CASE ( ImageFormat , R8Snorm ) CASE ( ImageFormat , Rgba32i ) CASE ( ImageFormat , Rgba16i ) CASE ( ImageFormat , Rgba8i ) CASE ( ImageFormat , R32i ) CASE ( ImageFormat , Rg32i ) CASE ( ImageFormat , Rg16i ) CASE ( ImageFormat , Rg8i ) CASE ( ImageFormat , R16i ) CASE ( ImageFormat , R8i ) CASE ( ImageFormat , Rgba32ui ) CASE ( ImageFormat , Rgba16ui ) CASE ( ImageFormat , Rgba8ui ) CASE ( ImageFormat , R32ui ) CASE ( ImageFormat , Rgb10a2ui ) CASE ( ImageFormat , Rg32ui ) CASE ( ImageFormat , Rg16ui ) CASE ( ImageFormat , Rg8ui ) CASE ( ImageFormat , R16ui ) CASE ( ImageFormat , R8ui ) break ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ;

MCRegister SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;

SDValue Addr = DAG . getFrameIndex ( XFI -> getVarArgsFrameIndex ( ) , <STR_LIT> ) ;


<s> if ( ( preg1 == <STR_LIT> || preg1 == <STR_LIT> ) && ! flag1 ) return true ;

if ( preg1 == Pred2 [ <NUM_LIT> ] . getReg ( ) && flag1 == Pred2 [ <NUM_LIT> ] . getImm ( ) ) return true ;


<s> static __inline vec_double2 spu_rlqwbytebc ( vec_double2 a , int count ) { return ( ( vec_double2 ) ( si_rotqbybi ( ( qword ) ( a ) , si_from_int ( count ) ) ) ) ;


<s> unsigned Register = DPairSpacedDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> MachineFunction * MF = MBB . getParent ( ) ; MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; int Opcode = - <NUM_LIT> ; if ( RI . isSGPRClass ( RC ) ) { switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S32_RESTORE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S64_RESTORE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S128_RESTORE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S256_RESTORE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S512_RESTORE ; break ;


<s> if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES ) { if ( GET_CODE ( addr ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( addr ) ) return legitimize_dllimport_symbol ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ) { rtx t = legitimize_dllimport_symbol ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ; } } if ( ix86_cmodel != CM_LARGE_PIC && ix86_cmodel != CM_MEDIUM_PIC ) return NULL_RTX ; if ( GET_CODE ( addr ) == SYMBOL_REF && ! is_imported_p ( addr ) && SYMBOL_REF_EXTERNAL_P ( addr ) && SYMBOL_REF_DECL ( addr ) ) return legitimize_pe_coff_extern_decl ( addr , inreg ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && ! is_imported_p ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) && SYMBOL_REF_EXTERNAL_P ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) && SYMBOL_REF_DECL ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ) { rtx t = legitimize_pe_coff_extern_decl ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , inreg ) ; return gen_rtx_PLUS ( Pmode , t , XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ; } return NULL_RTX ;


<s> Streamer . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; if ( ReadOnlySection . getAlignment ( ) < <NUM_LIT> ) ReadOnlySection . setAlignment ( Align ( <NUM_LIT> ) ) ; const GCNSubtarget & STM = MF -> getSubtarget < GCNSubtarget > ( ) ; SmallString < <NUM_LIT> > KernelName ; getNameWithPrefix ( KernelName , & MF -> getFunction ( ) ) ; getTargetStreamer ( ) -> EmitAmdhsaKernelDescriptor ( STM , KernelName , getAmdhsaKernelDescriptor ( * MF , CurrentProgramInfo ) , CurrentProgramInfo . NumVGPRsForWavesPerEU , CurrentProgramInfo . NumSGPRsForWavesPerEU - IsaInfo :: getNumExtraSGPRs ( & STM , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed ) , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed ) ;


<s> <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; MatchClassKind Expected = static_cast < MatchClassKind > ( ExpectedKind ) ; if ( Op . isImm ( ) ) { if ( MCConstantExpr const * Const = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) { int64_t RegNum = Const -> getValue ( ) ; std :: ostringstream RegName ; RegName << <STR_LIT> << RegNum ; RegNum = MatchRegisterName ( RegName . str ( ) . c_str ( ) ) ; if ( RegNum != <STR_LIT> ) { Op . makeReg ( RegNum ) ; if ( validateOperandClass ( Op , Expected ) == Match_Success ) { return Match_Success ; } } }


<s> return ( __m512 ) __builtin_ia32_cvtdq2ps512_mask ( ( __v16si ) __A , ( __v16sf ) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , false ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ; return false ; case <STR_LIT> : if ( checkPseudoAddTPRel ( Inst , Operands ) ) return true ; }


<s> void <ISA_LIT>InstPrinter :: printHigh ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {

if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O << <STR_LIT> ;


<s> expr = mep_frame_expr ( insn2 ) ; if ( RTX_FRAME_RELATED_P ( insn1 ) ) expr = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec ( <NUM_LIT> , mep_frame_expr ( insn1 ) , expr ) ) ; set_unique_reg_note ( insn1 , REG_FRAME_RELATED_EXPR , expr ) ; RTX_FRAME_RELATED_P ( insn1 ) = <NUM_LIT> ; }

PATTERN ( insn1 ) = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , PATTERN ( insn1 ) , PATTERN ( insn2 ) ) ) ;


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . getBrCond ( CC ) ) . addMBB ( copy1MBB ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ;

BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ;


<s> for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] = Mask ; for ( unsigned i = <NUM_LIT> ; i != NumConcat ; ++ i ) Ops [ i ] = ZeroVal ; NewMask = DAG . getNode ( <STR_LIT> , dl , NewMaskVT , Ops ) ; } return DAG . getMaskedStore ( Mst -> getChain ( ) , dl , TruncatedVal , Mst -> getBasePtr ( ) , NewMask , StVT , Mst -> getMemOperand ( ) , false ) ;


<s> <STR_LIT> ArgFlags = Outs [ i ] . Flags ; if ( IsRet ) { if ( RetCC_<ISA_LIT> ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << NumArgs << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr ) ; } } else { if ( CC_<ISA_LIT> ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << NumArgs << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ;


<s> if ( PAN :: isLocalToFunc ( FnName , VarName ) ) { const GlobalVariable * GV = I ; const Type * InitTy = GV -> getInitializer ( ) -> getType ( ) ; GlobalVariable * ClonedGV = new GlobalVariable ( InitTy , false , GV -> getLinkage ( ) , GV -> getInitializer ( ) ) ; ClonedGV -> setName ( PAN :: getCloneVarName ( FnName , VarName ) ) ;


<s> if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) ) BccOpc = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( Term != MBB . end ( ) && isPredicated ( * Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = & * ++ MBB . getIterator ( ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ;


<s> unsigned StackPtr = Context . SPCopy -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MaxAdjust > <NUM_LIT> ) Context . MovVector . resize ( MaxAdjust , nullptr ) ; InstClassification Classification ; DenseSet < unsigned int > UsedRegs ; while ( ( Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ) != Exit ) { if ( Classification == Skip ) { ++ I ; continue ; } if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ;

int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz ( ) const {


<s> return ; } * dash = '-' ; if ( first > last ) { warning ( <NUM_LIT> , <STR_LIT> , str , dash + <NUM_LIT> ) ; return ; } for ( i = first ; i <= last ; ++ i ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; if ( ! comma ) break ; * comma = ',' ; str = comma + <NUM_LIT> ; }


<s> } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( RoundAfterCopy ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( VA . isExtInLoc ( ) && ( VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ) ) { if ( VA . getValVT ( ) . isVector ( ) && ( ( VA . getLocVT ( ) == <STR_LIT> ) || ( VA . getLocVT ( ) == <STR_LIT> ) || ( VA . getLocVT ( ) == <STR_LIT> ) || ( VA . getLocVT ( ) == <STR_LIT> ) ) ) { Val = lowerRegToMasks ( Val , VA . getValVT ( ) , VA . getLocVT ( ) , dl , DAG ) ; } else Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; } InVals . push_back ( Val ) ;


<s> SDValue Hi64 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg128 ) ; SDValue Lo64 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg128 ) ; if ( isV9 ) Hi64 = DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , Hi64 ) ; else Hi64 = LowerF64Op ( Op , DAG ) ;

SDValue DstReg128 = SDValue ( DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) , <NUM_LIT> ) ;


<s> TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = N -> getOperand ( i ) . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * Context ) ; Entry . Node = N -> getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ;


<s> static inline bool isVPTOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; MIB . addOperand ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . addOperand ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . addOperand ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . addOperand ( ImmOp ) ; OpStart = <NUM_LIT> ; Changed = true ; } else if ( HII -> getAddrMode ( OldMI ) == <STR_LIT> ) { short NewOpCode = HII -> getAbsoluteForm ( OldMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) . addOperand ( OldMI -> getOperand ( <NUM_LIT> ) ) ; const GlobalValue * GV = ImmOp . getGlobal ( ) ; int64_t Offset = ImmOp . getOffset ( ) + OldMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addGlobalAddress ( GV , Offset , ImmOp . getTargetFlags ( ) ) ; OpStart = <NUM_LIT> ; Changed = true ; } else Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> << * OldMI << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MIB << <STR_LIT> ) ; } else if ( ImmOpNum == <NUM_LIT> && OldMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { short NewOpCode = HII -> xformRegToImmOffset ( OldMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; MIB . addOperand ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . addOperand ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . addOperand ( ImmOp ) ; OpStart = <NUM_LIT> ; Changed = true ; DEBUG ( dbgs ( ) << <STR_LIT> << * OldMI << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MIB << <STR_LIT> ) ; }

if ( Changed ) for ( unsigned i = OpStart ; i < OpEnd ; ++ i ) MIB . addOperand ( OldMI -> getOperand ( i ) ) ;


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) && ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains ( DstReg ) ) ) return false ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) return false ;


<s> Register LastVReg = Last . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( auto UI = MRI -> use_begin ( LastVReg ) , UE = MRI -> use_end ( ) ; UI != UE ; ) { MachineOperand & MO = * UI ++ ; MachineInstr & MI = * MO . getParent ( ) ; if ( MI . isDebugValue ( ) ) { replaceDebugValue ( MI , FirstVReg , AddrDispShift ) ; continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) + <STR_LIT> ( Desc ) ; MO . setReg ( FirstVReg ) ; MachineOperand & Op = MI . getOperand ( MemOpNo + <STR_LIT> ) ; if ( Op . isImm ( ) ) Op . setImm ( Op . getImm ( ) + AddrDispShift ) ; else if ( ! Op . isJTI ( ) ) Op . setOffset ( Op . getOffset ( ) + AddrDispShift ) ; } MRI -> clearKillFlags ( FirstVReg ) ; ++ NumRedundantLEAs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Last . dump ( ) ; ) ; assert ( MRI -> use_empty ( LastVReg ) && <STR_LIT> ) ; Last . eraseFromParent ( ) ; I2 = List . erase ( I2 ) ; Changed = true ; } ++ I1 ; }


<s> const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr & BMI = * MII ; if ( ! isNopInstr ( & BMI ) ) { return false ; } } return true ; } else { if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { return true ; } } return false ;


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ;

if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ;


<s> do { LaneBitmask M = TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ; if ( ( M & I . LaneMask ) . any ( ) ) LV . set ( S . getSubReg ( ) ) ; ++ S ; } while ( S . isValid ( ) ) ; } } ; BitVector LiveIn ( TRI . getNumRegs ( ) ) , Live ( TRI . getNumRegs ( ) ) ; CopyLiveIns ( B , LiveIn ) ; for ( auto SI : B -> successors ( ) ) CopyLiveIns ( SI , Live ) ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> isDebugValue ( ) ) continue ; MI -> clearKillInfo ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; for ( MCSubRegIterator SR ( R , & TRI , true ) ; SR . isValid ( ) ; ++ SR ) Live . reset ( * SR ) ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || Op . isUndef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; bool IsLive = false ;

for ( MCRegAliasIterator AR ( R , & TRI , true ) ; AR . isValid ( ) ; ++ AR ) {


<s> return ( __A [ <NUM_LIT> ] == __B [ <NUM_LIT> ] ) ;


<s> Value * ArgInGeneric = new AddrSpaceCastInst ( ArgInGlobal , Arg -> getType ( ) , Arg -> getName ( ) , FirstInst ) ; Arg -> replaceAllUsesWith ( ArgInGeneric ) ; ArgInGlobal -> setOperand ( <NUM_LIT> , Arg ) ;


<s> bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( psbhintop , STI . getFeatureBits ( ) , Valid ) ; if ( Valid ) O << Name ;


<s> if ( IK == IDOther ) Available [ IDOther ] . push_back ( SU ) ;

else Pending [ IK ] . push_back ( SU ) ;


<s> rtx op00 = XEXP ( op0 , <NUM_LIT> ) ; rtx op000 = XEXP ( op00 , <NUM_LIT> ) ; rtx * op000p = & XEXP ( op00 , <NUM_LIT> ) ; if ( ( GET_MODE ( op00 ) == HImode || GET_MODE ( op00 ) == QImode ) && ( REG_P ( op000 ) || ( GET_CODE ( op000 ) == POST_INC && REG_P ( XEXP ( op000 , <NUM_LIT> ) ) ) ) ) { bool something_reloaded = false ; if ( GET_CODE ( op000 ) == POST_INC && REG_P ( XEXP ( op000 , <NUM_LIT> ) ) && REGNO ( XEXP ( op000 , <NUM_LIT> ) ) > CRIS_LAST_GENERAL_REGISTER ) return false ; if ( ( REG_P ( op000 ) && REGNO ( op000 ) > CRIS_LAST_GENERAL_REGISTER ) ) { push_reload ( op000 , NULL_RTX , op000p , NULL , GENERAL_REGS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , type ) ; something_reloaded = true ; } if ( REGNO ( op1 ) > CRIS_LAST_GENERAL_REGISTER ) { push_reload ( op1 , NULL_RTX , op1p , NULL , GENERAL_REGS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , type ) ; something_reloaded = true ; }


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT N0VT = N0 . getValueType ( ) ; unsigned Off = TRI -> getSubRegIdxOffset ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDLoc DL ( N ) ; if ( N0 -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , N0VT , N0 , DAG . getConstant ( Off , DL , N0VT ) ) ) ; if ( ! N0 . hasOneUse ( ) ) return SDValue ( ) ;

if ( auto Load = dyn_cast < LoadSDNode > ( N0 ) ) return DAG . getLoad ( VT , DL , Load -> getChain ( ) , DAG . getMemBasePlusOffset ( Load -> getBasePtr ( ) , Off , DL ) , Load -> getPointerInfo ( ) . getWithOffset ( Off ) , Load -> getAlignment ( ) , Load -> getMemOperand ( ) -> getFlags ( ) , Load -> getAAInfo ( ) ) ;


<s> bool <ISA_LIT>ExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , false , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Add , true , <NUM_LIT> , NextMBBI ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSet<ISA_LIT>64R2 ( ) {


<s> bool isPIC = ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; adjust<ISA_LIT>StackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> hasCalls ( ) ) return ; int FPOffset = <ISA_LIT>FI -> getFPStackOffset ( ) ; int RAOffset = <ISA_LIT>FI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; if ( isPIC && Subtarget . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - StackSize ) ; if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( RAOffset ) . addReg ( <STR_LIT> ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( FPOffset ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } if ( <ISA_LIT>FI -> needGPSaveRestore ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>FI -> getGPStackOffset ( ) ) ;


<s> bool hasExtXfauxvecalthalf ( ) const { return HasExtXfauxvecalthalf ;


<s> return llvm :: create<ISA_LIT>SEISelDag ( TM ) ;


<s> bool <ISA_LIT>RegisterInfo :: isAGPR ( const MachineRegisterInfo & MRI , Register Reg ) const { const TargetRegisterClass * RC = getRegClassForReg ( MRI , Reg ) ; return RC && isAGPRClass ( RC ) ;


<s> MCPhysReg Reg = MFI -> getVGPRToAGPRSpill ( Index , Lane ) ; if ( Reg == <STR_LIT> ) return MachineInstrBuilder ( ) ; bool IsStore = MI -> mayStore ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; auto * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned Dst = IsStore ? Reg : ValueReg ;

unsigned Src = IsStore ? ValueReg : Reg ;


<s> if ( Size == <NUM_LIT> ) { const MachineInstr * L2 = * Entry . second . begin ( ) ; const MachineInstr * L1 = Entry . first ; if ( ! MDT -> dominates ( L2 , L1 ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * L2 << '\n' << * L1 << '\n' ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> << * L2 << '\n' << * L1 << '\n' ) ; SmallVector < const MachineInstr * , <NUM_LIT> > Args ; Args . push_back ( L2 ) ; Args . push_back ( L1 ) ; <ISA_LIT>FI . addLOHDirective ( MCLOH_AdrpAdrp , Args ) ; ++ NumADRPSimpleCandidate ; } else if ( Size == <NUM_LIT> ) ++ NumADRPComplexCandidate2 ; else if ( Size == <NUM_LIT> ) ++ NumADRPComplexCandidate3 ; else ++ NumADRPComplexCandidateOther ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ;


<s> std :: vector < std :: string > modr_d2_dmod ( Rn a ) { return D ( <STR_LIT> , R ( a ) , <STR_LIT> , <STR_LIT> ) ;


<s> if ( <ISA_LIT>FastEmitLoad ( VT , AM , ResultReg ) ) { UpdateValueMap ( I , ResultReg ) ; return true ; } return false ;


<s> } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FrameOffset ; } else { FrameReg = <STR_LIT> ; return FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ;


<s> Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ;


<s> OutStreamer . SwitchSection ( S ) ; unsigned Offset = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = CP . size ( ) ; i != e ; ++ i ) { const MachineConstantPoolEntry & CPE = CP [ i ] ; unsigned Align = CPE . getAlignment ( ) ; unsigned AlignMask = CPE . getAlignment ( ) - <NUM_LIT> ; unsigned NewOffset = ( Offset + AlignMask ) & ~ AlignMask ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; if ( NewOffset - Offset ) OS << <STR_LIT> << ( NewOffset - Offset ) << <STR_LIT> ; Type * Ty = CPE . getType ( ) ; Offset = NewOffset + TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ; MCSymbol * Symbol = GetCPISymbol ( i ) ; OS << <STR_LIT> << * Symbol ; HackStreamer ( OutStreamer ) << OS . str ( ) ; if ( CPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( CPE . Val . MachineCPVal ) ;

else EmitGlobalConstant ( CPE . Val . ConstVal ) ;


<s> return ( __m512 ) __builtin_ia32_broadcastf32x2_512_mask ( ( __v4sf ) __A , ( __v16sf ) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ;

getTargetStreamer ( ) . emitCurrentConstantPool ( ) ;


<s> int offset = GET_MODE_SIZE ( mode ) ; gcc_assert ( mode != VOIDmode ) ; if ( output_memory_autoinc_first ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( addr , <NUM_LIT> ) ) ] ) ; else fprintf ( file , <STR_LIT> , GET_CODE ( addr ) == POST_DEC ? - offset : offset ) ; } else if ( GET_CODE ( addr ) == POST_MODIFY ) {


<s> name = XSTR ( addr , <NUM_LIT> ) ; if ( name [ strlen ( name ) - <NUM_LIT> ] != ']' && ( TREE_PUBLIC ( SYMBOL_REF_DECL ( addr ) ) || bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ) ) { tlsname = XALLOCAVEC ( char , strlen ( name ) + <NUM_LIT> ) ; strcpy ( tlsname , name ) ; strcat ( tlsname , bss_initializer_p ( SYMBOL_REF_DECL ( addr ) ) ? <STR_LIT> : <STR_LIT> ) ; tlsaddr = copy_rtx ( addr ) ; XSTR ( tlsaddr , <NUM_LIT> ) = ggc_strdup ( tlsname ) ; } else tlsaddr = addr ; sym = force_const_mem ( GET_MODE ( tlsaddr ) , tlsaddr ) ; if ( constant_pool_expr_p ( XEXP ( sym , <NUM_LIT> ) ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( XEXP ( sym , <NUM_LIT> ) ) , Pmode ) ) { tocref = create_TOC_reference ( XEXP ( sym , <NUM_LIT> ) , NULL_RTX ) ; mem = gen_const_mem ( Pmode , tocref ) ; set_mem_alias_set ( mem , get_TOC_alias_set ( ) ) ; }


<s> bool <ISA_LIT>ReduceCRLogicals :: handleCROp ( CRLogicalOpInfo & CRI ) { bool Changed = false ; if ( CRI . IsBinary && CRI . ContainedInBlock && CRI . SingleUse && CRI . FeedsBR && CRI . DefsSingleUse ) { Changed = splitBlockOnBinaryCROp ( CRI ) ; if ( Changed ) NumBlocksSplitOnBinaryCROp ++ ; } return Changed ;


<s> RCW . RegWeight = <NUM_LIT> ; RCW . WeightLimit = <NUM_LIT> ;


<s> } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ;


<s> assert ( Slot < Data . size ( ) && <STR_LIT> ) ;


<s> SmallVector < SDNode * , <NUM_LIT> > Queue ( <NUM_LIT> , Chain . getNode ( ) ) ; SmallSet < SDNode * , <NUM_LIT> > Visited ; while ( ! Queue . empty ( ) ) { SDNode * ChainNext = Queue . pop_back_val ( ) ; if ( ! Visited . insert ( ChainNext ) ) continue ; if ( LoadSDNode * ChainLD = dyn_cast < LoadSDNode > ( ChainNext ) ) { if ( isConsecutiveLS ( ChainLD , LD , VT . getStoreSize ( ) , <NUM_LIT> , DAG ) ) return true ; if ( ! Visited . count ( ChainLD -> getChain ( ) . getNode ( ) ) ) Queue . push_back ( ChainLD -> getChain ( ) . getNode ( ) ) ; } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( const SDUse & O : ChainNext -> ops ( ) ) if ( ! Visited . count ( O . getNode ( ) ) ) Queue . push_back ( O . getNode ( ) ) ; } else LoadRoots . insert ( ChainNext ) ; } Visited . clear ( ) ; Queue . clear ( ) ; for ( SmallSet < SDNode * , <NUM_LIT> > :: iterator I = LoadRoots . begin ( ) , IE = LoadRoots . end ( ) ; I != IE ; ++ I ) { Queue . push_back ( * I ) ; while ( ! Queue . empty ( ) ) {

SDNode * LoadRoot = Queue . pop_back_val ( ) ;


<s> Register AmountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Def = MRI -> getUniqueVRegDef ( AmountReg ) ; if ( ! Def || ( Def -> getOpcode ( ) != <STR_LIT> && Def -> getOpcode ( ) != <STR_LIT> ) || ! Def -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return - <NUM_LIT> ;

return Def -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> break ; } MCOperand RegLR = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand RegS0 = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand RegS12 = MCOperand :: createReg ( <STR_LIT> ) ; MCSymbol * GetTLSLabel = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; MCOperand cim24 = MCOperand :: createImm ( - <NUM_LIT> ) ; MCOperand loImm = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO32 , AddrSym , OutContext ) ; emitLEAzii ( * OutStreamer , cim24 , loImm , RegS0 , STI ) ; MCOperand ci32 = MCOperand :: createImm ( <NUM_LIT> ) ; emitANDrm0 ( * OutStreamer , RegS0 , ci32 , RegS0 , STI ) ; emitSIC ( * OutStreamer , RegLR , STI ) ; MCOperand hiImm = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI32 , AddrSym , OutContext ) ; emitLEASLrri ( * OutStreamer , RegS0 , RegLR , hiImm , RegS0 , STI ) ; MCOperand ci8 = MCOperand :: createImm ( <NUM_LIT> ) ; MCOperand loImm2 = createGOTRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PLT_LO32 , GetTLSLabel , OutContext ) ; emitLEAzii ( * OutStreamer , ci8 , loImm2 , RegS12 , STI ) ;

emitANDrm0 ( * OutStreamer , RegS12 , ci32 , RegS12 , STI ) ;


<s> case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ;


<s> assert ( Addr . isRegBase ( ) && <STR_LIT> ) ; const MCInstrDesc & II = MIB -> getDesc ( ) ; unsigned Idx = ( Flags & MachineMemOperand :: MOStore ) ? <NUM_LIT> : <NUM_LIT> ; Addr . setReg ( constrainOperandRegClass ( II , Addr . getReg ( ) , II . getNumDefs ( ) + Idx ) ) ; Addr . setOffsetReg ( constrainOperandRegClass ( II , Addr . getOffsetReg ( ) , II . getNumDefs ( ) + Idx + <NUM_LIT> ) ) ; if ( Addr . getOffsetReg ( ) ) { assert ( Addr . getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; bool IsSigned = Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ; MIB . addReg ( Addr . getReg ( ) ) ; MIB . addReg ( Addr . getOffsetReg ( ) ) ; MIB . addImm ( IsSigned ) ; MIB . addImm ( Addr . getShift ( ) != <NUM_LIT> ) ; } else MIB . addReg ( Addr . getReg ( ) ) . addImm ( Offset ) ; }

if ( MMO ) MIB . addMemOperand ( MMO ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ; } recordExtender ( MI , HII -> getCExtOpNum ( MI ) ) ;


<s> union { const rtx_insn * c ; rtx_insn * r ; } u ; u . c = follower ; if ( CROSSING_JUMP_P ( followee ) ) switch ( get_attr_type ( u . r ) ) { case TYPE_BRCC : case TYPE_BRCC_NO_DELAY_SLOT : return false ; default : return true ; } return true ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( ) { SupportsDebugInformation = true ;


<s> void printASROperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

printShiftOperand ( <STR_LIT> , MI , OpNum , O ) ;


<s> if ( MO . isImplicit ( ) ) { return MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> ; } else { return <STR_LIT> . contains ( MO . getReg ( ) ) || <STR_LIT> . contains ( MO . getReg ( ) ) ;


<s> InputIt find_best ( InputIt First , InputIt Last , UnaryPredicate Predicate , Comparator BetterThan ) { InputIt Best = Last ; for ( InputIt I = First ; I != Last ; ++ I ) { unsigned Matched = Predicate ( * I ) ; if ( Matched != FindBest_NoMatch ) { DEBUG ( dbgs ( ) << std :: distance ( First , I ) << <STR_LIT> ; I -> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ) ; if ( Best == Last || BetterThan ( * I , * Best ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Best = I ;


<s> static void predict_jump ( int prob ) { rtx_insn * insn = get_last_insn ( ) ; gcc_assert ( JUMP_P ( insn ) ) ; add_int_reg_note ( insn , REG_BR_PROB , prob ) ;


<s> else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; } default : { if ( ( LoadMI -> getOpcode ( ) == <STR_LIT> || LoadMI -> getOpcode ( ) == <STR_LIT> ) && MF . getRegInfo ( ) . getRegClass ( LoadMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getSize ( ) > <NUM_LIT> ) return nullptr ; if ( ( LoadMI -> getOpcode ( ) == <STR_LIT> || LoadMI -> getOpcode ( ) == <STR_LIT> ) && MF . getRegInfo ( ) . getRegClass ( LoadMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) -> getSize ( ) > <NUM_LIT> ) return nullptr ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) MOs . push_back ( LoadMI -> getOperand ( i ) ) ;


<s> Function * Handler = const_cast < Function * > ( P . first ) ; int BaseState = P . second ; IRBuilder < > Builder ( & Handler -> getEntryBlock ( ) , Handler -> getEntryBlock ( ) . begin ( ) ) ; Value * ParentFP = Builder . CreateCall ( FrameAddress , { Builder . getInt32 ( <NUM_LIT> ) } ) ;

Value * RecoveredRegNode = Builder . CreateCall ( FrameRecover , { FI8 , ParentFP , Builder . getInt32 ( RegNodeEscapeIndex ) } ) ;


<s> unsigned int bytes_so_far = * get_cumulative_args ( cum ) ; unsigned int size ; unsigned int rounded_size ; size = arg . promoted_size_in_bytes ( ) ; if ( size < <NUM_LIT> ) return NULL_RTX ; rounded_size = rx_round_up ( size , UNITS_PER_WORD ) ;


<s> if ( ! TM . Options . GuaranteedTailCallOpt && DisableSCO ) return false ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee || Callee -> isVarArg ( ) ) return false ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller -> getCallingConv ( ) , CI -> getCallingConv ( ) ) ) return false ; return getTargetMachine ( ) . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , Callee ) ;


<s> else if ( GET_CODE ( x ) == POST_MODIFY && ia64_legitimate_address_reg ( XEXP ( x , <NUM_LIT> ) , strict ) && XEXP ( x , <NUM_LIT> ) != arg_pointer_rtx && ia64_legitimate_address_disp ( XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) , strict ) ) return true ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned ObjSizeScaled = ObjSize / <NUM_LIT> ; SDValue TagSrc = Ptr ; if ( Ptr . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Ptr ) -> getIndex ( ) ; Ptr = DAG . getTargetFrameIndex ( FI , <STR_LIT> ) ; TagSrc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } const unsigned OpCode1 = ZeroData ? <STR_LIT> : <STR_LIT> ; const unsigned OpCode2 = ZeroData ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > OutChains ; unsigned OffsetScaled = <NUM_LIT> ; while ( OffsetScaled < ObjSizeScaled ) { if ( ObjSizeScaled - OffsetScaled >= <NUM_LIT> ) {

SDValue AddrNode = DAG . getMemBasePlusOffset ( Ptr , OffsetScaled * <NUM_LIT> , dl ) ;


return ( __m128 ) __builtin_ia32_cvtpd2ps ( ( __v2df ) __A ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;

addPass ( create<ISA_LIT>ArgumentMove ( ) ) ;


<s> if ( NeedAlign <= HasAlign ) StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcLo , getKillRegState ( IsKill ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; if ( NeedAlign <= MinAlign ( HasAlign , Size ) ) StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( Size ) . addReg ( SrcHi , getKillRegState ( IsKill ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; B . erase ( It ) ; return true ;


<s> else if ( asm_noperands ( body ) >= <NUM_LIT> ) templ = decode_asm_operands ( body , NULL , NULL , NULL , NULL , NULL ) ; else templ = NULL ;

return ( templ && templ [ <NUM_LIT> ] == '\0' ) ;


<s> ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregxidi_pss ( __o , <NUM_LIT> ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs ) ) { <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setSpillsCR ( ) ; } for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ;


<s> bool <ISA_LIT>PerfHint :: needLimitWave ( const <ISA_LIT>PerfHintAnalysis :: FuncInfo & FI ) {

return ( ( FI . MemInstCost + FI . IAMInstCost * IAWeight + FI . LSMInstCost * LSWeight ) * <NUM_LIT> / FI . InstCost ) > LimitWaveThresh ;


<s> bool isGFX9Plus ( const MCSubtargetInfo & STI ) { return isGFX9 ( STI ) || isGFX10Plus ( STI ) ;


<s> if ( SCALAR_FLOAT_MODE_P ( mode1 ) ) return SCALAR_FLOAT_MODE_P ( mode2 ) ; if ( SCALAR_FLOAT_MODE_P ( mode2 ) ) return false ; if ( GET_MODE_CLASS ( mode1 ) == MODE_CC ) return GET_MODE_CLASS ( mode2 ) == MODE_CC ; if ( GET_MODE_CLASS ( mode2 ) == MODE_CC ) return false ; if ( SPE_VECTOR_MODE ( mode1 ) ) return SPE_VECTOR_MODE ( mode2 ) ; if ( SPE_VECTOR_MODE ( mode2 ) ) return false ;


<s> if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ;

if ( ! V1 . getNode ( ) ) V1 = SrcVector ;


<s> <ISA_LIT>ELFStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > Emitter ) : MCELFStreamer ( Context , std :: move ( MAB ) , OS , std :: move ( Emitter ) ) {


<s> SDValue NeededSpace = Size ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue Backchain ; if ( StoreBackchain ) Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , OldSP , MachinePointerInfo ( ) ) ; if ( ExtraAlignSpace ) NeededSpace = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NeededSpace , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; SDValue NewSP ; if ( hasInlineStackProbe ( MF ) ) { NewSP = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , OldSP , NeededSpace ) ; Chain = NewSP . getValue ( <NUM_LIT> ) ; } else { NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , NeededSpace ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; } SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP , ArgAdjust ) ; if ( RequiredAlign > StackAlign ) {

Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ;


<s> case <ISA_LIT>_PARAM_TYPE_CALL_PARAM : ParamList = & CallArgParams ; DefName = <STR_LIT> ; break ; case <ISA_LIT>_PARAM_TYPE_CALL_RET : ParamList = & CallRetParams ; DefName = <STR_LIT> ; break ; } if ( ParamName . empty ( ) ) { Name = DefName ; Name += utostr ( ParamList -> size ( ) ) ; } else { Name = ParamName ; } unsigned prev_offset = <NUM_LIT> ; unsigned prev_size = <NUM_LIT> ; if ( ParamList -> size ( ) > <NUM_LIT> ) { unsigned prev_param = ( * ParamList ) [ ParamList -> size ( ) - <NUM_LIT> ] ; prev_offset = getParamOffset ( prev_param ) ; prev_size = getParamSize ( prev_param ) ; } if ( prev_offset == UINT_MAX || GetOpaqueType ( Ty ) ) { Param . Offset = UINT_MAX ; } else { unsigned alignment = DL -> getABITypeAlignment ( Ty ) ; if ( ParamType == <ISA_LIT>_PARAM_TYPE_KERNARG && Ty -> isVectorTy ( ) ) alignment = DL -> getABITypeAlignment ( Ty -> getVectorElementType ( ) ) ; assert ( alignment != <NUM_LIT> ) ; Param . Offset = ( prev_offset + prev_size + alignment - <NUM_LIT> ) & ~ ( alignment - <NUM_LIT> ) ; } unsigned Index = AllParams . size ( ) ;


<s> const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; unsigned Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount ) adjustStackPointer ( Amount , IsDestroy , MF , MBB , TII , I , DL ) ;


<s> if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) || ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( N -> getMaskElt ( i + <NUM_LIT> ) , i ) ) return false ;


<s> Queue . pop ( ) ; Set . erase ( V ) ; return V ;


<s> rewriteFrameIndex ( MachineInstr & MI , unsigned FrameRegIdx , unsigned FrameReg , int Offset , unsigned MOVOpc , unsigned ADDriOpc , unsigned SUBriOpc ) const {


<s> if ( ( TSFlags & ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) == <NUM_LIT> ) return true ; uint16_t DataNameIdx = ( TSFlags & <STR_LIT> ) ? <STR_LIT> :: data0 : <STR_LIT> :: vdata ; const MCRegisterInfo * MRI = getMRI ( ) ; int DstAreg = IsAGPROperand ( Inst , <STR_LIT> :: vdst , MRI ) ; int DataAreg = IsAGPROperand ( Inst , DataNameIdx , MRI ) ; if ( ( TSFlags & <STR_LIT> ) && DataAreg >= <NUM_LIT> ) { int Data2Areg = IsAGPROperand ( Inst , <STR_LIT> :: data1 , MRI ) ; if ( Data2Areg >= <NUM_LIT> && Data2Areg != DataAreg ) return false ; } auto FB = getFeatureBits ( ) ; if ( FB [ <STR_LIT> ] ) { if ( DataAreg < <NUM_LIT> || DstAreg < <NUM_LIT> ) return true ; return DstAreg == DataAreg ; } return DstAreg < <NUM_LIT> && DataAreg < <NUM_LIT> ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CC_Save_RegMask ;


<s> if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_PRECISION ( t ) == <NUM_LIT> ) return N_ ( <STR_LIT> ) ; return NULL ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <ISA_LIT>DataLayout , TT , getCPU ( CPU ) , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , SubTarget ( TT , getCPU ( CPU ) . str ( ) , FS . str ( ) , * this ) { this -> TLOF = std :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ;


<s> llvm :: Triple :: ArchType arch = pConfig . targets ( ) . triple ( ) . getArch ( ) ; assert ( arch == llvm :: Triple :: x86 || arch == llvm :: Triple :: x86_64 ) ; if ( arch == llvm :: Triple :: x86 || pConfig . targets ( ) . triple ( ) . getEnvironment ( ) == llvm :: Triple :: GNUX32 ) { m_RelEntrySize = <NUM_LIT> ; m_RelaEntrySize = <NUM_LIT> ; if ( arch == llvm :: Triple :: x86 ) m_PointerRel = llvm :: ELF :: R_386_32 ; else m_PointerRel = llvm :: ELF :: R_<ISA_LIT>_64_32 ; } else {


<s> for ( auto * MBB : ML -> getBlocks ( ) ) dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> ; ) ; std :: function < MachineInstr * ( MachineBasicBlock * ) > SearchForStart = [ & SearchForStart ] ( MachineBasicBlock * MBB ) -> MachineInstr * { for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( ML ) ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } if ( ! LoLoop . Dec || LoLoop . End || LoLoop . Revert ) continue ; for ( auto & MO : MI . operands ( ) ) { if ( MI . getOpcode ( ) != <STR_LIT> && MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ;


<s> EVT SrcEVT = TLI . getValueType ( DL , Ty , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>SubTarget -> useCRBits ( ) ) return false ; long Imm = <NUM_LIT> ; bool UseImm = false ; if ( const ConstantInt * ConstInt = dyn_cast < ConstantInt > ( SrcValue2 ) ) { if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { const APInt & CIVal = ConstInt -> getValue ( ) ; Imm = ( IsZExt ) ? ( long ) CIVal . getZExtValue ( ) : ( long ) CIVal . getSExtValue ( ) ; if ( ( IsZExt && isUInt < <NUM_LIT> > ( Imm ) ) || ( ! IsZExt && isInt < <NUM_LIT> > ( Imm ) ) ) UseImm = true ; } } unsigned CmpOpc ; bool NeedsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : CmpOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsExt = true ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( ! UseImm ) CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; else CmpOpc = IsZExt ? <STR_LIT> : <STR_LIT> ; break ; } unsigned SrcReg1 = getRegForValue ( SrcValue1 ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( SrcValue2 ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( NeedsExt ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , ExtReg , IsZExt ) ) return false ; SrcReg1 = ExtReg ; if ( ! UseImm ) { unsigned ExtReg = createResultReg ( & <STR_LIT> ) ;

if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , ExtReg , IsZExt ) ) return false ;


<s> TargetJITInfo :: LazyResolverFn <ISA_LIT>JITInfo :: getLazyResolverFunction ( JITCompilerFn F ) { JITCompilerFunction = F ; return <ISA_LIT>CompilationCallback ;


return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false ) ;


<s> int len = strlen ( str ) ; char * newstr = alloca ( len + <NUM_LIT> ) ; newstr [ <NUM_LIT> ] = '@' ; strcpy ( & newstr [ <NUM_LIT> ] , str ) ; XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) = ggc_alloc_string ( newstr , len + <NUM_LIT> ) ;


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ) . addReg ( AddrReg ) ) ;

const IndirectBrInst * IB = cast < IndirectBrInst > ( I ) ;


<s> assert ( PHI . isPHI ( ) ) ; return PHI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> bool ShouldShrinkFPConstant ( EVT VT ) const override { return VT != <STR_LIT> ;


<s> for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> ) Gathers . push_back ( II ) ; } } if ( Gathers . empty ( ) ) return false ; for ( IntrinsicInst * I : Gathers ) lowerGather ( I ) ;


<s> OutgoingArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder MIB , CCAssignFn * AssignFn , CCAssignFn * AssignFnVarArg ) : ValueHandler ( MIRBuilder , MRI , AssignFn ) , MIB ( MIB ) , AssignFnVarArg ( AssignFnVarArg ) , StackSize ( <NUM_LIT> ) {


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( ! Reg ) return ; unsigned Excess = <NUM_LIT> * ( <STR_LIT> - Reg ) ; const unsigned NSAAOffset = State -> getNextStackOffset ( ) ; if ( NSAAOffset != <NUM_LIT> && Size > Excess ) { while ( State -> AllocateReg ( GPRArgRegs ) ) ; return ; } unsigned ByValRegBegin = Reg ; unsigned ByValRegEnd = std :: min < unsigned > ( Reg + Size / <NUM_LIT> , <STR_LIT> ) ; State -> addInRegsParamInfo ( ByValRegBegin , ByValRegEnd ) ;

for ( unsigned i = Reg + <NUM_LIT> ; i != ByValRegEnd ; ++ i ) State -> AllocateReg ( GPRArgRegs ) ;


<s> SDLoc DL ( N ) ; if ( SDValue DivRem8 = getDivRem8 ( N , DAG ) ) return DivRem8 ; if ( ! DCI . isBeforeLegalizeOps ( ) ) { if ( InVT == <STR_LIT> ) { SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue AllOnes = DAG . getAllOnesConstant ( DL , VT ) ; return DAG . getSelect ( DL , VT , N0 , AllOnes , Zero ) ; } return SDValue ( ) ; } if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) {

SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ;


bool IsLegal = ( ( Immed >> <NUM_LIT> ) == <NUM_LIT> || ( ( Immed & <NUM_LIT> ) == <NUM_LIT> && Immed >> <NUM_LIT> == <NUM_LIT> ) ) ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) return Op0 ;

Op0 = LoadOperand ( DAG , DL , Op0 . getValueType ( ) , Op0 ) ;


<s> size_t THMToTHMStub :: alignment ( ) const {


<s> uint32_t c = CountPopulation_64 ( v ) ; return c == <NUM_LIT> ;


<s> return ( ( qword ) ( vec_perm ( vec_perm ( a , b , pattern ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , pat ) ) ) ;


<s> unsigned EncodedOffset = <STR_LIT> ( Subtarget , Offset ) ; BuildMI ( MBB , I , DL , LoadDwordX2 , FlatScrInit ) . addReg ( FlatScrInit ) . addImm ( EncodedOffset ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; const MCInstrDesc & SAndB32 = TII -> get ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , SAndB32 , FlatScrInitHi ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; } else { Register FlatScratchInitReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; assert ( FlatScratchInitReg ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . addLiveIn ( FlatScratchInitReg ) ; MBB . addLiveIn ( FlatScratchInitReg ) ; FlatScrInitLo = TRI -> getSubReg ( FlatScratchInitReg , <STR_LIT> ) ; FlatScrInitHi = TRI -> getSubReg ( FlatScratchInitReg , <STR_LIT> ) ; } if ( ST . flatScratchIsPointer ( ) ) { if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitLo ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitHi ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FlatScrInitLo ) . addImm ( int16_t ( <STR_LIT> :: ID_FLAT_SCR_LO | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FlatScrInitHi ) . addImm ( int16_t ( <STR_LIT> :: ID_FLAT_SCR_HI | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ) ) ; return ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; return ; } assert ( ST . getGeneration ( ) < <ISA_LIT>Subtarget :: GFX9 ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitHi , RegState :: Kill ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitLo ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ;

BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitLo , RegState :: Kill ) . addImm ( <NUM_LIT> ) ;


<s> bool is64bit = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; if ( model != TLSModel :: LocalExec ) llvm_unreachable ( <STR_LIT> ) ; SDValue TLSReg = DAG . getRegister ( is64bit ? <STR_LIT> : <STR_LIT> , is64bit ? <STR_LIT> : <STR_LIT> ) ;

SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGAHi , TLSReg ) ;


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsPCRel ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) {

unsigned Idx = IsLittleEndian ? i : ( NumBytes - <NUM_LIT> - i ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> } bool PreferAVX512 = ( ( Subtarget . hasAVX512 ( ) && InSVT == <STR_LIT> ) || ( Subtarget . hasBWI ( ) && InSVT == <STR_LIT> ) ) && ( InVT . getSizeInBits ( ) > <NUM_LIT> ) && ( Subtarget . hasVLX ( ) || InVT . getSizeInBits ( ) > <NUM_LIT> ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . getSizeInBits ( ) >= <NUM_LIT> ) ; if ( isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ! PreferAVX512 && VT . getSizeInBits ( ) >= <NUM_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = VT . changeVectorElementType ( <STR_LIT> ) ; SDValue Mid = truncateVectorWithPACK ( <STR_LIT> , MidVT , USatVal , DL , DAG , Subtarget ) ; assert ( Mid && <STR_LIT> ) ; SDValue V = truncateVectorWithPACK ( <STR_LIT> , VT , Mid , DL , DAG , Subtarget ) ; assert ( V && <STR_LIT> ) ; return V ; } else if ( SVT == <STR_LIT> || Subtarget . hasSSE41 ( ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , USatVal , DL , DAG , Subtarget ) ; } if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTypeLegal ( InVT ) && InVT . isVector ( ) && SVT != <STR_LIT> && Subtarget . hasAVX512 ( ) && ( InSVT != <STR_LIT> || Subtarget . hasBWI ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) ) { unsigned TruncOpc = <NUM_LIT> ; SDValue SatVal ; if ( auto SSatVal = detectSSatPattern ( In , VT ) ) { SatVal = SSatVal ;


<s> unsigned <ISA_LIT>TTI :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; unsigned Cost = LT . first * <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( SrcBytes && Alignment && Alignment < SrcBytes ) Cost *= ( SrcBytes / Alignment ) ;


<s> ArrayRef < MVT > ElemTypes = getHVXElementTypes ( ) ;

return llvm :: find ( ElemTypes , Ty ) != ElemTypes . end ( ) ;


<s> if ( InputZExtConst || Opc == <STR_LIT> || Opc == <STR_LIT> ) return Input ; SDLoc dl ( Input ) ; ZeroExtensionsAdded ++ ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Input , getI64Imm ( <NUM_LIT> , dl ) , getI64Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ;


<s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> write32 ( <NUM_LIT> ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ;


<s> gimple_call_set_lhs ( g , tmp_var ) ; tree indirect = fold_build2 ( MEM_REF , size_type_node , gimple_call_arg ( f . call , gimple_call_num_args ( f . call ) - <NUM_LIT> ) , build_int_cst ( build_pointer_type ( size_type_node ) , <NUM_LIT> ) ) ; gassign * assign = gimple_build_assign ( indirect , tmp_var ) ; gsi_insert_after ( f . gsi , assign , GSI_SAME_STMT ) ; gsi_insert_after ( f . gsi , g , GSI_SAME_STMT ) ;


<s> if ( VT . isVector ( ) ) return LowerVSETCC ( Op , Subtarget , DAG ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerAndToBT ( Op0 , CC , dl , DAG ) ) return NewSetCC ; } if ( SDValue NewSetCC = EmitKTEST ( Op0 , Op1 , CC , dl , DAG , Subtarget ) ) return NewSetCC ; if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ;

bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ;


<s> Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> , Call ) ; break ; default : break ; } } } return Changed ;


<s> if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ; Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( ExtraLoadRequired ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ;

if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result , DAG . getConstant ( Offset , getPointerTy ( ) ) ) ;


<s> void markP<ISA_LIT>nputAllocated ( unsigned Index ) { P<ISA_LIT>nputAddr |= <NUM_LIT> << Index ;


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) { if ( Op1 == N -> getOperand ( <NUM_LIT> ) ) return Op1 ; EVT VT = Op1 . getValueType ( ) ; unsigned ElemBytes = VT . getVectorElementType ( ) . getStoreSize ( ) ; if ( ElemBytes <= <NUM_LIT> ) { Opcode = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EVT InVT = VT . changeVectorElementTypeToInteger ( ) ; EVT OutVT = <STR_LIT> ( <STR_LIT> ( ElemBytes * <NUM_LIT> ) , <STR_LIT> / ElemBytes / <NUM_LIT> ) ; if ( VT != InVT ) { Op1 = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , InVT , Op1 ) ; DCI . AddToWorklist ( Op1 . getNode ( ) ) ; } SDValue Op = DAG . getNode ( Opcode , SDLoc ( N ) , OutVT , Op1 ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op ) ; } } } if ( Opcode == <STR_LIT> ) { auto * SN = cast < StoreSDNode > ( N ) ; EVT MemVT = SN -> getMemoryVT ( ) ; if ( MemVT . isInteger ( ) ) { if ( SDValue Value = combineTruncateExtract ( SDLoc ( N ) , MemVT , SN -> getValue ( ) , DCI ) ) { DCI . AddToWorklist ( Value . getNode ( ) ) ; return DAG . getTruncStore ( SN -> getChain ( ) , SDLoc ( SN ) , Value , SN -> getBasePtr ( ) , SN -> getMemoryVT ( ) , SN -> getMemOperand ( ) ) ; } } } if ( Opcode == <STR_LIT> ) { if ( auto * IndexN = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) {


<s> MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) { if ( ! MRI . getRegClassOrNull ( Reg ) ) MRI . setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; } return true ; } default : return selectImpl ( I , CoverageInfo ) ;


<s> return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> vmull_n_s32 ( int32x2_t a , int32_t b ) { int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result ;


<s> if ( Op . getImm ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ;


<s> Register R = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , R ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) . addImm ( <NUM_LIT> << <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) . addReg ( R , RegState :: Kill ) ;


<s> static int getLoadStoreMultipleOpcode ( int Opcode ) { switch ( Opcode ) { case <STR_LIT> : NumLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumSTMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFLDMGened ++ ; return <STR_LIT> ; case <STR_LIT> : NumFSTMGened ++ ; return <STR_LIT> ;


<s> return InlineAsm :: Constraint_R ; case 'S' : return InlineAsm :: Constraint_S ; case 'T' : return InlineAsm :: Constraint_T ; } } return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ;


<s> ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) { Value * Op = I -> getOperand ( i ) ; unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; unsigned CalleeReg = <NUM_LIT> ; if ( Enable<ISA_LIT>LongCalls ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Enable<ISA_LIT>LongCalls ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) AddDefaultPred ( MIB ) ; if ( Enable<ISA_LIT>LongCalls ) MIB . addReg ( CalleeReg ) ; else MIB . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ;

for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] , RegState :: Implicit ) ;


<s> unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) && Subtarget -> hasFP64 ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( DstVT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( FP ) ) ; updateValueMap ( I , ResultReg ) ;


<s> void rs6000_fatal_bad_address ( rtx op ) { fatal_insn ( <STR_LIT> , op ) ;


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> ) ; } Register LinkReg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ;

return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , LinkReg , PtrVT ) ;


return :: isPSHUFHWMask ( M , N -> getValueType ( <NUM_LIT> ) ) ;


<s> MachineBasicBlock :: iterator J = I ; if ( ! MBDisableDelaySlotFiller ) D = findDelayInstr ( MBB , I ) ; ++ FilledSlots ; Changed = true ; if ( D == MBB . end ( ) ) BuildMI ( MBB , ++ J , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; else MBB . splice ( ++ J , & MBB , D ) ;


<s> static const uint16_t F64Regs [ ] = { <STR_LIT> , <STR_LIT> } ; return CC_<ISA_LIT>O32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , F64Regs ) ;


<s> for ( ; regno > ereg ; regno -- ) if ( reg_mask & ( <NUM_LIT> << regno ) ) { rtx dst = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; rtx insn = emit_insn ( gen_movsi ( dst , gen_rtx_REG ( SImode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( offset == stm_size ) break ; offset -= <NUM_LIT> ; } } if ( stm_p ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( stm_regs ) ) ; int regno , slot ; for ( regno = sreg , slot = <NUM_LIT> ; regno <= ereg ; regno ++ , slot ++ ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , slot * <NUM_LIT> ) ; rtx set = gen_rtx_SET ( gen_frame_mem ( SImode , addr ) , reg ) ; RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , slot ) = set ; } insn = emit_insn ( par ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } if ( frame_pointer_needed ) { insn = emit_insn ( gen_movsi ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } expand_csky_stack_adjust ( - cfun -> machine -> reg_offset ) ; if ( flag_pic && ( reg_mask & ( <NUM_LIT> << PIC_OFFSET_TABLE_REGNUM ) ) ) { rtx l1 = gen_label_rtx ( ) ; rtx grs_label = gen_rtx_LABEL_REF ( SImode , l1 ) ; rtx reg_gb = gen_rtx_REG ( SImode , PIC_OFFSET_TABLE_REGNUM ) ; rtx reg_temp = gen_rtx_REG ( SImode , <NUM_LIT> ) ; rtx tmp0_unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , grs_label ) , UNSPEC_PIC_SYMBOL_GOTPC_GRS ) ; rtx tmp1_unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , grs_label ) , UNSPEC_PIC_SYMBOL_GOTPC ) ; emit_insn ( gen_prologue_get_pc ( tmp0_unspec ) ) ; emit_move_insn ( reg_temp , tmp1_unspec ) ; emit_insn ( gen_addsi3 ( reg_gb , reg_gb , reg_temp ) ) ;


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> const <ISA_LIT>Subtarget & ST = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; uint32_t FP32Denormals = ST . hasFP32Denormals ( ) ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT ; uint32_t FP64Denormals = ST . hasFP64Denormals ( ) ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT ;


<s> switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ;

if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ;


<s> static bool tilegx_frame_pointer_required ( void ) { return crtl -> calls_eh_return || cfun -> calls_alloca ;


<s> } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == <NUM_LIT> && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) {

parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ;


<s> if ( Sext && ! skipToken ( AsmToken :: LParen , <STR_LIT> ) ) return MatchOperand_ParseFail ; OperandMatchResultTy Res ; if ( AllowImm ) { Res = parseRegOrImm ( Operands ) ; } else { Res = parseReg ( Operands ) ; } if ( Res != MatchOperand_Success ) { return Sext ? MatchOperand_ParseFail : Res ; } if ( Sext && ! skipToken ( AsmToken :: RParen , <STR_LIT> ) ) return MatchOperand_ParseFail ; <ISA_LIT>Operand :: Modifiers Mods ; Mods . Sext = Sext ; if ( Mods . hasIntModifiers ( ) ) { <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( * Operands . back ( ) ) ; if ( Op . isExpr ( ) ) { Error ( Op . getStartLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , BB_E = MF . end ( ) ; BB != BB_E ; ++ BB ) { MachineBasicBlock & MBB = * BB ;

MachineBasicBlock :: iterator I = MBB . begin ( ) ;


<s> int orderNo = N -> getIROrder ( ) ; int orderNo2 = N0 . getNode ( ) -> getIROrder ( ) ; if ( orderNo - orderNo2 < <NUM_LIT> ) return SDValue ( ) ; bool opIsLive = false ; const SDNode * left = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; const SDNode * right = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( dyn_cast < ConstantSDNode > ( left ) || dyn_cast < ConstantSDNode > ( right ) ) opIsLive = true ; if ( ! opIsLive ) for ( SDNode :: use_iterator UI = left -> use_begin ( ) , UE = left -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) { opIsLive = true ; break ; } } if ( ! opIsLive ) for ( SDNode :: use_iterator UI = right -> use_begin ( ) , UE = right -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) {


<s> if ( ! EnablePreLink ) Changed |= setFastFlags ( F , Options ) ; for ( auto & BB : F ) { for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; ) { CallInst * CI = dyn_cast < CallInst > ( I ) ; ++ I ;