<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; uint64_t FrameSize = MFI . getStackSize ( ) ; uint64_t StackAlign = RI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ;

FrameSize = alignTo ( FrameSize , StackAlign ) ;


<s> void <ISA_LIT>ATTInstPrinter :: printMemOffset ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & DispSpec = MI -> getOperand ( Op ) ; const MCOperand & SegReg = MI -> getOperand ( Op + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { O << formatImm ( DispSpec . getImm ( ) ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx , bool isLittle ) : MCII ( mcii ) , CTX ( ctx ) , IsLittleEndian ( isLittle ) {


<s> switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( Subtarget -> isThumb1Only ( ) ) return false ; LLVM_FALLTHROUGH ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Scale < <NUM_LIT> ) Scale = - Scale ; if ( Scale == <NUM_LIT> ) return true ; return isPowerOf2_32 ( Scale & ~ <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= <NUM_LIT> ) return true ; return false ; case <STR_LIT> : if ( Scale & <NUM_LIT> ) return false ; return isPowerOf2_32 ( Scale ) ; } } return true ;


<s> static rtx aarch64_simd_dup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ;

if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ;


<s> void fr30_setup_incoming_varargs ( cumulative_args_t arg_regs_used_so_far_v , const function_arg_info & arg , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * arg_regs_used_so_far = get_cumulative_args ( arg_regs_used_so_far_v ) ; int size ; gcc_assert ( arg . mode != BLKmode ) ; if ( targetm . calls . strict_argument_naming ( arg_regs_used_so_far_v ) ) arg_regs_used_so_far += fr30_num_arg_regs ( arg ) ; size = FR30_NUM_ARG_REGS - ( * arg_regs_used_so_far ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ;

if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isV9 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;


<s> if ( OffsetRegNum != - <NUM_LIT> ) { OffsetIsReg = true ; E = CurLoc ; } } if ( OffsetRegNum != - <NUM_LIT> ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ParseShift ( ShiftType , ShiftAmount , E ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; OffsetRegShifted = true ; } } else { const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getParser ( ) . ParseExpression ( Offset ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;


<s> while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned EltSize = Op . getScalarValueSizeInBits ( ) ; unsigned Imm = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> SmallVectorImpl < MachineInstr * > & Insts = Block . getInsts ( ) ;

return isPredicatedOnVCTP ( Insts . front ( ) , Exclusive ) ;


<s> <ISA_LIT>ConstantIslands ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , ABI ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ) , STI ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , MF ( <NUM_LIT> ) , MCP ( <NUM_LIT> ) {


<s> int fp_size = frame_pointer_needed * UNITS_PER_WORD ; int saved_regs_size = <NUM_LIT> ; int frame_size = round_frame_size ( get_frame_size ( ) ) ; int regno ; for ( regno = <NUM_LIT> ; regno <= HARD_FRAME_POINTER_REGNUM ; regno ++ ) if ( WORD_REG_USED ( regno ) ) saved_regs_size += UNITS_PER_WORD ; saved_regs_size -= fp_size ; switch ( to ) { case HARD_FRAME_POINTER_REGNUM : switch ( from ) { case ARG_POINTER_REGNUM : return pc_size + fp_size ; case RETURN_ADDRESS_POINTER_REGNUM : return fp_size ; case FRAME_POINTER_REGNUM : return - saved_regs_size ; default : gcc_unreachable ( ) ; } break ; case STACK_POINTER_REGNUM :


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ;

O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg ( ) ) ;


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ;


<s> FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CAPTAB_PCREL_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_CINCOFFSET : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CCALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) FixupKind = <STR_LIT> ; else FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; }


<s> SDValue Carry = CCR . getOperand ( <NUM_LIT> ) ; while ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || ( Carry . getOpcode ( ) == <STR_LIT> && isOneConstant ( Carry . getOperand ( <NUM_LIT> ) ) ) ) Carry = Carry . getOperand ( <NUM_LIT> ) ; if ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> ) {

if ( Carry . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) return Carry . getOperand ( <NUM_LIT> ) ;


<s> AU . addPreservedID ( MachineLoopInfoID ) ;

AU . addPreservedID ( MachineDominatorsID ) ;


<s> static bool rx_small_data_operand ( rtx op ) {

if ( rx_small_data_limit == <NUM_LIT> ) return false ;


<s> parm = TREE_CHAIN ( parm ) ) { if ( DECL_RTL ( parm ) == <NUM_LIT> || GET_CODE ( DECL_RTL ( parm ) ) == MEM ) return <NUM_LIT> ;

if ( DECL_INCOMING_RTL ( parm ) == <NUM_LIT> || GET_CODE ( DECL_INCOMING_RTL ( parm ) ) == MEM ) return <NUM_LIT> ;


<s> MachineBasicBlock * MBB = Preheader ; while ( MBB && MBB != StartInsertBB ) { if ( CannotProvideElements ( MBB , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MBB = * MBB -> pred_begin ( ) ; } auto IsValidSub = [ ] ( MachineInstr * MI , int ExpectedVecWidth ) { return - getAddSubImmediate ( * MI ) == ExpectedVecWidth ; } ; MBB = VCTP -> getParent ( ) ; if ( auto * Def = RDA . getUniqueReachingMIDef ( & MBB -> back ( ) , VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > ElementChain ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; unsigned ExpectedVectorWidth = getTailPredVectorWidth ( VCTP -> getOpcode ( ) ) ; Ignore . insert ( VCTPs . begin ( ) , VCTPs . end ( ) ) ; if ( TryRemove ( Def , RDA , ElementChain , Ignore ) ) { bool FoundSub = false ; for ( auto * MI : ElementChain ) { if ( isMovRegOpcode ( MI -> getOpcode ( ) ) ) continue ; if ( isSubImmOpcode ( MI -> getOpcode ( ) ) ) { if ( FoundSub || ! IsValidSub ( MI , ExpectedVectorWidth ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << * MI ) ; return false ; } FoundSub = true ;


<s> assert ( Success ) ; ( void ) Success ; assert ( ( ( Imm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; O << formatImm ( Imm / <NUM_LIT> ) ;


<s> case MachineOperand :: MO_Immediate : if ( Src . isImm ( ) ) { Dst . setImm ( Src . getImm ( ) ) ; } else if ( Src . isReg ( ) ) { Dst . ChangeToRegister ( Src . getReg ( ) , Src . isDef ( ) , Src . isImplicit ( ) , Src . isKill ( ) , Src . isDead ( ) , Src . isUndef ( ) , Src . isDebug ( ) ) ;


<s> bool has<ISA_LIT>32I ( ) const { return <ISA_LIT>ArchVersion >= <ISA_LIT>32I ;


<s> return __builtin_mve_vcvtq_n_to_f_uv8hf ( __a , __imm6 ) ;


<s> else { int j ; const char * fmt = GET_RTX_FORMAT ( code ) ; for ( i = <NUM_LIT> ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) swap_const_vector_halves ( & XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = <NUM_LIT> ; j < XVECLEN ( op , i ) ; ++ j ) swap_const_vector_halves ( & XVECEXP ( op , i , j ) ) ;


<s> unsigned SegReg = getRegOp ( MIOperandNo + <NUM_LIT> ) ; if ( SegReg ) report_fatal_error ( <STR_LIT> ) ; if ( VT != <STR_LIT> ) { Type * PtrTy = EVT ( VT ) . getTypeForEVT ( getContext ( ) ) -> getPointerTo ( ) ; Offset = Builder . CreateIntToPtr ( Offset , PtrTy ) ; } return Offset ;


<s> } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ; } assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print ( O , & MAI , true ) ;


<s> case VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; } OS << '(' ; Expr -> print ( OS ) ; OS << ')' ;


<s> for ( auto & MBB : MF ) { AllBlocks . insert ( & MBB ) ; }

if ( LLVM_UNLIKELY ( processRegion ( & * MF . begin ( ) , AllBlocks , MF ) ) ) {


<s> return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , OS ) ; case <STR_LIT> : case <STR_LIT> : return isReg < <STR_LIT> > ( MI , <NUM_LIT> ) && printAlias ( <STR_LIT> , MI , <NUM_LIT> , <NUM_LIT> , OS ) ; case <STR_LIT> :


<s> if ( I . nodeVisited ( Term -> getSuccessor ( <NUM_LIT> ) ) ) { if ( isTopOfStack ( BB ) ) closeControlFlow ( BB ) ; handleLoop ( Term ) ; continue ; } if ( isTopOfStack ( BB ) ) { PHINode * Phi = dyn_cast < PHINode > ( Term -> getCondition ( ) ) ; if ( Phi && Phi -> getParent ( ) == BB && isElse ( Phi ) ) { insertElse ( Term ) ; eraseIfUnused ( Phi ) ; continue ;


<s> MDNode * Operand = N -> getOperand ( i ) ; MDNode * NewOperand = MapMetadata ( Operand , VM ) ; OperandChanged |= Operand != NewOperand ; NewOperands . push_back ( NewOperand ) ; } if ( ! OperandChanged ) {


<s> inline Predicate getPredicate ( unsigned Condition , unsigned Hint ) {

return ( Predicate ) ( ( Condition & ~ BR_HINT_MASK ) | ( Hint & BR_HINT_MASK ) ) ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_clflush ( void const * __A ) { __builtin_ia32_clflush ( __A ) ;


<s> for ( auto Read : Loads ) { MemoryLocation ReadLoc = MemoryLocation ( Read -> getPointerOperand ( ) , Size ) ; if ( ! isModOrRefSet ( intersectModRef ( AA -> getModRefInfo ( Write , ReadLoc ) , ModRefInfo :: ModRef ) ) ) continue ; if ( Write -> comesBefore ( Read ) ) RAWDeps [ Read ] . insert ( Write ) ; } } auto SafeToPair = [ & ] ( LoadInst * Base , LoadInst * Offset ) { bool BaseFirst = Base -> comesBefore ( Offset ) ; LoadInst * Dominator = BaseFirst ? Base : Offset ; LoadInst * Dominated = BaseFirst ? Offset : Base ; if ( RAWDeps . count ( Dominated ) ) { InstSet & WritesBefore = RAWDeps [ Dominated ] ; for ( auto Before : WritesBefore ) {

if ( Dominator -> comesBefore ( Before ) ) return false ;


<s> pass_shorten_memrefs ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_shorten_memrefs , ctxt ) {


<s> if ( Load -> getExtensionType ( ) == <STR_LIT> ) { int64_t SignedValue = ConstOp1 -> getSExtValue ( ) ; if ( uint64_t ( SignedValue ) + ( uint64_t ( <NUM_LIT> ) << ( NumBits - <NUM_LIT> ) ) > Mask ) return ; if ( C . ICmpType != <STR_LIT> ) { Value &= Mask ; } else if ( NumBits == <NUM_LIT> ) { if ( Value == <NUM_LIT> && C . CCMask == <STR_LIT> ) Value = <NUM_LIT> , C . CCMask = <STR_LIT> ; else if ( Value == <NUM_LIT> && C . CCMask == <STR_LIT> ) Value = <NUM_LIT> , C . CCMask = <STR_LIT> ; else return ; C . ICmpType = <STR_LIT> ; } } else if ( Load -> getExtensionType ( ) == <STR_LIT> ) { if ( Value > Mask ) return ; C . ICmpType = <STR_LIT> ; } else return ; <STR_LIT> ExtType = ( C . ICmpType == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( C . Op0 . getValueType ( ) != <STR_LIT> || Load -> getExtensionType ( ) != ExtType ) C . Op0 = DAG . getExtLoad ( ExtType , SDLoc ( Load ) , <STR_LIT> , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getPointerInfo ( ) , Load -> getMemoryVT ( ) , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ;

if ( C . Op1 . getValueType ( ) != <STR_LIT> || Value != ConstOp1 -> getZExtValue ( ) ) C . Op1 = DAG . getConstant ( Value , DL , <STR_LIT> ) ;


<s> } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) return false ; } MBB . erase ( MergeInstr ) ; unsigned NewOpc = getUpdatingLSMultipleOpcode ( Opcode , Mode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned OpNum = <NUM_LIT> , e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . addOperand ( MI -> getOperand ( OpNum ) ) ;

MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> assert ( ES -> getTargetFlags ( ) == <NUM_LIT> && <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , VT , <NUM_LIT> ) ) ;


<s> LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; TM = & MF . getTarget ( ) ; ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; Is64Bit = TM -> getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; Module & M = const_cast < Module & > ( * MMI -> getModule ( ) ) ; if ( ! MF . getName ( ) . startswith ( ThunkNamePrefix ) ) {


<s> LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || ( LocVT == <STR_LIT> && HST . useHVX128BOps ( ) ) ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; LocInfo = CCValAssign :: Full ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! RetCC_<ISA_LIT>Vector ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } return true ;


<s> uint32_t S = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t J1 = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; uint32_t J2 = ( offset & <NUM_LIT> ) >> <NUM_LIT> ; J1 = ( ~ J1 & <NUM_LIT> ) ; J2 = ( ~ J2 & <NUM_LIT> ) ; J1 ^= S ; J2 ^= S ;


<s> ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ;


<s> bool AMDGPUInstrInfo :: canFoldMemoryOperand ( const MachineInstr * MI , ArrayRef < unsigned > Ops ) const {


<s> <ISA_LIT>Operand :: Ptr <ISA_LIT>AsmParser :: defaultHwreg ( ) const {

return <ISA_LIT>Operand :: CreateImm ( <NUM_LIT> , SMLoc ( ) , <ISA_LIT>Operand :: ImmTyHwreg ) ;


<s> return __builtin_mve_vabdq_uv16qi ( __a , __b ) ;


<s> SDValue Ops [ ] = { Node -> getChain ( ) , SclToVec , Node -> getBasePtr ( ) } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , Node -> getMemOperand ( ) ) ; } else if ( Subtarget . hasX87 ( ) ) { SDValue StackPtr = DAG . CreateStackTemporary ( <STR_LIT> ) ; int SPFI = cast < FrameIndexSDNode > ( StackPtr . getNode ( ) ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SPFI ) ; Chain = DAG . getStore ( Node -> getChain ( ) , dl , Node -> getOperand ( <NUM_LIT> ) , StackPtr , MPI , <NUM_LIT> , MachineMemOperand :: MOStore ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LdOps [ ] = { Chain , StackPtr } ; SDValue Value = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , LdOps , <STR_LIT> , MPI , None , MachineMemOperand :: MOLoad ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SDValue StoreOps [ ] = { Chain , Value , Node -> getBasePtr ( ) } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , StoreOps , <STR_LIT> , Node -> getMemOperand ( ) ) ; } if ( Chain ) { if ( IsSeqCst ) Chain = emitLockedStackOp ( DAG , Subtarget , Chain , dl ) ; return Chain ; } }


<s> if ( isAAPCS_ABI && ! Triple ( TM . getTargetTriple ( ) ) . isOSNaCl ( ) ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> ) ;


<s> if ( FoundScan ) break ; } assert ( FoundScan ) ; DEBUG ( { StringRef PP = ( PV . M ? <STR_LIT> : <STR_LIT> ) ; if ( ! PV . Inv ) dbgs ( ) << <STR_LIT> << PP << <STR_LIT> ; else dbgs ( ) << <STR_LIT> << PP << <STR_LIT> << PP << <STR_LIT> ; dbgs ( ) << <STR_LIT> << * PV . Res << <STR_LIT> << * PV . P << <STR_LIT> ; if ( PV . M ) dbgs ( ) << <STR_LIT> << * PV . M << <STR_LIT> ; dbgs ( ) << <STR_LIT> << * PV . Q << <STR_LIT> ; dbgs ( ) << <STR_LIT> << PV . IterCount << <STR_LIT> ; } ) ; BasicBlock :: iterator At ( EntryB -> getTerminator ( ) ) ; Value * PM = generate ( At , PV ) ; if ( PM == nullptr ) return false ; if ( PM -> getType ( ) != PV . Res -> getType ( ) ) PM = IRBuilder < > ( & * At ) . CreateIntCast ( PM , PV . Res -> getType ( ) , false ) ; PV . Res -> replaceAllUsesWith ( PM ) ; PV . Res -> eraseFromParent ( ) ;


<s> fprintf ( dump_file , <STR_LIT> , ( unsigned ) mp -> offset , ( unsigned long ) mp -> min_address , ( unsigned long ) mp -> max_address ) ; arm_print_value ( dump_file , mp -> value ) ; fputc ( '\n' , dump_file ) ; } switch ( GET_MODE_SIZE ( mp -> mode ) ) { case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_1 ( mp -> value ) , scan ) ; break ; case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_2 ( mp -> value ) , scan ) ; break ; case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_4 ( mp -> value ) , scan ) ; break ; case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_8 ( mp -> value ) , scan ) ; break ; case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_16 ( mp -> value ) , scan ) ; break ; default : gcc_unreachable ( ) ; } } nmp = mp -> next ; free ( mp ) ; }


<s> return MCDisassembler :: Fail ; } Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler :: Success ;


<s> if ( MI -> isCopyLike ( ) || MI -> isInsertSubreg ( ) || MI -> isRegSequence ( ) || MI -> isImplicitDef ( ) ) return <NUM_LIT> ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return <NUM_LIT> ; if ( MI -> isBundle ( ) ) { int Latency = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ;


<s> } switch ( <ISA_LIT>II :: getSlotOpCode ( MI . getDesc ( ) ) ) { case <ISA_LIT>II :: spuLOOP : return <ISA_LIT>II :: getInstrType ( MI . getDesc ( ) ) == <ISA_LIT>II :: TypeLOOP ; default : return false ; }


<s> return __builtin_mve_vbrsrq_m_n_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a , __b , __p ) ;


<s> SDValue ByteShift = DAG . getTargetConstant ( ( <NUM_LIT> - AmtTy . getScalarSizeInBits ( ) ) / <NUM_LIT> , SDLoc ( ShAmt ) , <STR_LIT> ) ; ShAmt = DAG . getBitcast ( <STR_LIT> , ShAmt ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt , ByteShift ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt , ByteShift ) ; } } else if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> ) { ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; } else { SDValue ShOps [ <NUM_LIT> ] = { ShAmt , DAG . getConstant ( <NUM_LIT> , dl , SVT ) , DAG . getUNDEF ( SVT ) , DAG . getUNDEF ( SVT ) } ; ShAmt = DAG . getBuildVector ( <STR_LIT> , dl , ShOps ) ; } MVT EltVT = VT . getVectorElementType ( ) ; MVT ShVT = <STR_LIT> ( EltVT , <NUM_LIT> / EltVT . getSizeInBits ( ) ) ; ShAmt = DAG . getBitcast ( ShVT , ShAmt ) ; return DAG . getNode ( Opc , dl , VT , SrcOp , ShAmt ) ;


<s> return false ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , <NUM_LIT> ) ) { if ( MO . isImplicit ( ) || ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( Reg < <STR_LIT> || Reg > <STR_LIT> ) { if ( ! ( MI . getOpcode ( ) == <STR_LIT> && Reg == <STR_LIT> ) && ! ( MI . getOpcode ( ) == <STR_LIT> && Reg == <STR_LIT> ) ) { ErrInfo = <STR_LIT> ; return false ; } } } } if ( MI . getOpcode ( ) == <STR_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; if ( ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } <STR_LIT> AddrMode = ( <STR_LIT> ) ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) ; switch ( AddrMode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint32_t Imm = <NUM_LIT> ; for ( auto Op : MI . operands ( ) ) { if ( Op . isImm ( ) ) {


<s> OriginalArgWasF128 . push_back ( originalTypeIsF128 ( CLI . RetTy , CLI . Callee . getNode ( ) ) ) ; OriginalArgWasFloat . push_back ( CLI . RetTy -> isFloatingPointTy ( ) ) ; }


<s> Inserter ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , TII ( tm . getInstrInfo ( ) ) {


<s> return true ; } if ( isZeroOrAllOnes ( N2 , AllOnes ) ) { Invert = true ; OtherOp = N1 ; return true ; } return false ; } case <STR_LIT> : if ( AllOnes ) return false ; case <STR_LIT> : { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC . getValueType ( ) != <STR_LIT> ) return false ; Invert = ! AllOnes ; if ( AllOnes ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else if ( N -> getOpcode ( ) == <STR_LIT> ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ;

else OtherOp = DAG . getConstant ( APInt :: getAllOnesValue ( VT . getSizeInBits ( ) ) , dl , VT ) ;


<s> inline SDValue getI8Imm ( unsigned Imm ) {

return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


<s> MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , RHS1 , CC ) , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , RHS2 , CC ) ) ;


<s> void PreAnalyzeCallOperandsForF128_ ( const SmallVectorImpl < <STR_LIT> > & Outs , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , SDNode * CallNode ) { PreAnalyzeCallOperandsForF128 ( Outs , FuncArgs , CallNode ) ;


<s> return & * <ISA_LIT>InstrFMA3InfoObj ;


<s> } unsigned DoubleRegDest = TRI -> getMatchingSuperReg ( LoRegDef , <STR_LIT> , SuperRC ) ; assert ( DoubleRegDest != <NUM_LIT> && <STR_LIT> ) ; MachineOperand & LoOperand = IsI1Loreg ? I1 . getOperand ( <NUM_LIT> ) : I2 . getOperand ( <NUM_LIT> ) ; MachineOperand & HiOperand = IsI1Loreg ? I2 . getOperand ( <NUM_LIT> ) : I1 . getOperand ( <NUM_LIT> ) ; bool IsHiReg = HiOperand . isReg ( ) ; bool IsLoReg = LoOperand . isReg ( ) ; bool IsC64 = OptForSize && LoOperand . isImm ( ) && HiOperand . isImm ( ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I1 ) && isGreaterThanNBitTFRI < <NUM_LIT> > ( I2 ) ; MachineBasicBlock :: iterator InsertPt ( DoInsertAtI1 ? I1 : I2 ) ; if ( IsHiReg && IsLoReg ) emitCombineRR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsHiReg ) emitCombineRI ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsLoReg ) emitCombineIR ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else if ( IsC64 && ! IsConst64Disabled ) emitConst64 ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; else emitCombineII ( InsertPt , DoubleRegDest , HiOperand , LoOperand ) ; if ( ! DoInsertAtI1 && DbgMItoMove . size ( ) != <NUM_LIT> ) { MachineBasicBlock * BB = InsertPt -> getParent ( ) ;


<s> Code32Directive = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; switch ( TheTriple . getOS ( ) ) { case Triple :: NetBSD : case Triple :: NaCl : ExceptionsType = ExceptionHandling :: DwarfCFI ; break ; default : ExceptionsType = ExceptionHandling :: <ISA_LIT> ; break ;


<s> if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; MachineInstrBuilder MIB ; unsigned CallOpc = <ISA_LIT>SelectCallOp ( NULL ) ; if ( isThumb2 ) MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; else MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes ) ) return false ;

static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept ( UsedRegs , TRI ) ;


<s> DebugLoc DL = EntryMBB . findDebugLoc ( MBBI ) ; Register SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( EntryMBB , MBBI , DL , TII . get ( <STR_LIT> ) , SPCopy ) . addReg ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) { if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ;

BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SPCopy , RegState :: Kill ) ;


<s> { int offset = <NUM_LIT> ; if ( GET_CODE ( reg ) == SUBREG ) { offset = SUBREG_BYTE ( reg ) ; reg = SUBREG_REG ( reg ) ; } gen_ashift ( type , n , gen_rtx_SUBREG ( SImode , reg , offset ) ) ; break ; } case ASHIFT : emit_insn ( gen_ashlhi3_k ( reg , reg , GEN_INT ( n ) ) ) ; break ;


<s> CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RCW , RCW . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ;


<s> std :: string name = mSTM -> getDeviceName ( ) ; if ( name == <STR_LIT> ) { DeviceFlag = OCL_DEVICE_RV710 ; } else if ( name == <STR_LIT> ) { DeviceFlag = OCL_DEVICE_RV730 ; } else { DeviceFlag = OCL_DEVICE_RV770 ;


<s> if ( type == NULL ) return false ; if ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return true ;

if ( TREE_ADDRESSABLE ( type ) ) return true ;


<s> OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ;


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & C , MCAsmBackend & AB , raw_pwrite_stream & OS , MCCodeEmitter * CE , bool RelaxAll , bool IncrementalLinkerCompatible ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , AB , CE , OS ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; S -> getAssembler ( ) . setIncrementalLinkerCompatible ( IncrementalLinkerCompatible ) ; return S ;


<s> if ( ( GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS && shouldUseLDSConstAddress ( GV ) ) || GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS || GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ) return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op , DAG ) ; SDLoc DL ( GSD ) ; EVT PtrVT = Op . getValueType ( ) ; if ( GSD -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , GSD -> getOffset ( ) , <ISA_LIT>InstrInfo :: MO_ABS32_LO ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GA ) ; } if ( shouldEmitFixup ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT ) ; else if ( shouldEmitPCReloc ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT , <ISA_LIT>InstrInfo :: MO_REL32 ) ; SDValue GOTAddr = buildPCRelGlobalAddress ( DAG , GV , DL , <NUM_LIT> , PtrVT , <ISA_LIT>InstrInfo :: MO_GOTPCREL32 ) ; Type * Ty = PtrVT . getTypeForEVT ( * DAG . getContext ( ) ) ;

PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ;


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { O << <STR_LIT> << MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ; } else {

printOp ( MI -> getOperand ( OpNo ) , O ) ;


<s> || defined ( __x86_64__ ) || defined ( _M_AMD64 ) || defined ( _M_X64 ) int rEAX , rEDX ; __asm__ ( <STR_LIT> : <STR_LIT> ( rEAX ) , <STR_LIT> ( rEDX ) : <STR_LIT> ( <NUM_LIT> ) ) ; unsigned long long rEAX = _xgetbv ( _XCR_XFEATURE_ENABLED_MASK ) ; int rEAX = <NUM_LIT> ; return ( rEAX & <NUM_LIT> ) == <NUM_LIT> ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i + NumElems / <NUM_LIT> ) , i + NumElems ) ) return false ;


<s> ForceLongBranchFirstPass = ForceLongBranch ; bool longBranchChanged = handlePossibleLongBranch ( ) ; bool forbiddenSlotChanged = handleForbiddenSlot ( ) ; bool Changed = longBranchChanged || forbiddenSlotChanged ; while ( forbiddenSlotChanged ) { longBranchChanged = handlePossibleLongBranch ( ) ; if ( ! longBranchChanged ) break ; forbiddenSlotChanged = handleForbiddenSlot ( ) ; } return Changed ;


<s> float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ; return r ;


<s> Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'q' : <STR_LIT> Ty = P . getSubtarget ( ) . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , Ty ) ; break ; } O << '%' << <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rn == <NUM_LIT> || Rd == Rn || Rd == Rt || Rd == Rt + <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRPairRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S ;


<s> Value * Incoming = PN . getIncomingValue ( i ) ; if ( Incoming == UndefValue :: get ( Incoming -> getType ( ) ) ) return true ; } return false ;


<s> if ( const MCSymbolRefExpr * MSRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { StringRef Symbol = MSRE -> getSymbol ( ) . getName ( ) ; return MCSymbolRefExpr :: create ( Symbol , VK , getContext ( ) ) ; } if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { const MCExpr * LExp = evaluateRelocExpr ( BE -> getLHS ( ) , VK ) ; const MCExpr * RExp = evaluateRelocExpr ( BE -> getRHS ( ) , VK ) ; return MCBinaryExpr :: create ( BE -> getOpcode ( ) , LExp , RExp , getContext ( ) ) ;


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) {


<s> bool hasExceptionHandling ( ) const {


<s> rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; rtx addr , addr_reg , tramp , eight = GEN_INT ( <NUM_LIT> ) ; if ( ! TARGET_GNU_AS ) { static bool declared_ia64_trampoline = false ; if ( ! declared_ia64_trampoline ) { declared_ia64_trampoline = true ; ( * targetm . asm_out . globalize_label ) ( asm_out_file , <STR_LIT> ) ; } } addr = convert_memory_address ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ; fnaddr = convert_memory_address ( Pmode , fnaddr ) ; static_chain = convert_memory_address ( Pmode , static_chain ) ;


<s> LowGPR = Reg ; StartOffset = Offset ; } } } ZFI -> setLowSavedGPR ( LowGPR ) ; ZFI -> setHighSavedGPR ( HighGPR ) ; if ( IsVarArg ) { unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; unsigned Offset = RegSpillOffsets [ Reg ] ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ;


<s> static DecodeStatus decodeU3ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) {

return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> static sbitmap rs6000_components_for_bb ( basic_block bb ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ;

sbitmap components = sbitmap_alloc ( <NUM_LIT> ) ;


<s> } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opcode = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ;


<s> BBInfo ( MachineBasicBlock * argMBB = <NUM_LIT> ) : MBB ( argMBB ) , conditional ( true ) , analyzable ( true ) , duplicable ( true ) , predicable ( true ) , predicated ( false ) , size ( <NUM_LIT> ) , cycles ( <NUM_LIT> ) , branchTBB ( <NUM_LIT> ) , branchFBB ( <NUM_LIT> ) {


<s> break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; } } else { switch ( N -> getOpcode ( ) ) { default : return NULL ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } break ; case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ;


<s> const InstrItineraryData * II = STI . getInstrItineraryData ( ) ; return static_cast < const <ISA_LIT>Subtarget & > ( STI ) . createDFAPacketizer ( II ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( <STR_LIT> ) ; return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? ( SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ) : ( SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ) ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_SaveList : CSR_SVR432_SaveList ) ;


<s> int avr_progmem_p ( tree decl , tree attributes ) { tree a ; if ( TREE_CODE ( decl ) != VAR_DECL ) return <NUM_LIT> ; if ( avr_decl_memx_p ( decl ) ) return <NUM_LIT> ; if ( avr_decl_flash_p ( decl ) ) return <NUM_LIT> ; if ( NULL_TREE != lookup_attribute ( <STR_LIT> , attributes ) ) return - <NUM_LIT> ; a = decl ;


<s> if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ;

} else return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX512 ) return CSR_64_RT_AllRegs_512_RegMask ; if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_RegMask : CSR_Win32_CFGuard_Check_NoSSE_RegMask ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: SwiftTail : if ( ! Is64Bit ) return CSR_32_RegMask ; return IsWin64 ? CSR_Win64_SwiftTail_RegMask : CSR_64_SwiftTail_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else {

if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ;


<s> const MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; if ( ! <STR_LIT> ( F -> getCallingConv ( ) ) ) { KernargSegmentPtr = true ; WorkGroupIDX = true ; WorkItemIDX = true ; } if ( F -> hasFnAttribute ( <STR_LIT> ) || ST . debuggerEmitPrologue ( ) ) WorkGroupIDY = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) || ST . debuggerEmitPrologue ( ) ) WorkGroupIDZ = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) || ST . debuggerEmitPrologue ( ) ) WorkItemIDY = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) || ST . debuggerEmitPrologue ( ) ) WorkItemIDZ = true ; if ( WorkItemIDZ ) WorkItemIDY = true ; bool MaySpill = ST . isVGPRSpillingEnabled ( * F ) ; bool HasStackObjects = FrameInfo . hasStackObjects ( ) ; if ( HasStackObjects || MaySpill ) PrivateSegmentWaveByteOffset = true ; if ( ST . isAmdHsaOS ( ) ) { if ( HasStackObjects || MaySpill ) PrivateSegmentBuffer = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) DispatchPtr = true ;

if ( F -> hasFnAttribute ( <STR_LIT> ) ) QueuePtr = true ;


<s> void setFPSpillSlot ( int off ) { FPSpillSlot = off ;


<s> } DEBUG ( dbgs ( ) << <STR_LIT> << DstMBB -> size ( ) << <STR_LIT> << SrcMBB -> size ( ) << <STR_LIT> ; ) ; DstMBB -> splice ( I , SrcMBB , SrcMBB -> begin ( ) , SpliceEnd ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << DstMBB -> size ( ) << <STR_LIT> << SrcMBB -> size ( ) << '\n' ;


<s> this_head = involved_chains [ <NUM_LIT> ] ; if ( this_head -> cannot_rename ) goto out_fail ; for ( chain = this_head -> first ; chain ; chain = chain -> next_use ) { unsigned int mask1 , mask2 , mask_changed ; int count , side1 , side2 , req1 , req2 ; insn_rr_info * this_rr = & insn_rr [ INSN_UID ( chain -> insn ) ] ; count = get_unit_reqs ( chain -> insn , & req1 , & side1 , & req2 , & side2 ) ; if ( count == <NUM_LIT> ) goto out_fail ; if ( ! get_unit_operand_masks ( chain -> insn , & mask1 , & mask2 ) ) goto out_fail ; extract_insn ( chain -> insn ) ; mask_changed = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) { int j ; int n_this_op = this_rr -> op_info [ i ] . n_chains ; for ( j = <NUM_LIT> ; j < n_this_op ; j ++ ) { du_head_p other = this_rr -> op_info [ i ] . heads [ j ] ; if ( regrename_chain_from_id ( other -> id ) == this_head ) break ; } if ( j == n_this_op ) continue ; if ( n_this_op != <NUM_LIT> ) goto out_fail ; mask_changed |= <NUM_LIT> << i ; } gcc_assert ( mask_changed != <NUM_LIT> ) ; if ( mask_changed != mask1 && mask_changed != mask2 ) goto out_fail ; } unavailable = ~ reg_class_contents [ super_class ] ;


<s> if ( ! VT . isScalableVector ( ) && VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getScalarSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;


<s> f_gpr = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_fpr = DECL_CHAIN ( f_gpr ) ; f_res = DECL_CHAIN ( f_fpr ) ; f_ovf = DECL_CHAIN ( f_res ) ; f_sav = DECL_CHAIN ( f_ovf ) ; valist = build_simple_mem_ref ( valist ) ; gpr = build3 ( COMPONENT_REF , TREE_TYPE ( f_gpr ) , valist , f_gpr , NULL_TREE ) ; fpr = build3 ( COMPONENT_REF , TREE_TYPE ( f_fpr ) , unshare_expr ( valist ) , f_fpr , NULL_TREE ) ; ovf = build3 ( COMPONENT_REF , TREE_TYPE ( f_ovf ) , unshare_expr ( valist ) , f_ovf , NULL_TREE ) ; sav = build3 ( COMPONENT_REF , TREE_TYPE ( f_sav ) , unshare_expr ( valist ) , f_sav , NULL_TREE ) ; words = crtl -> args . info . words ; n_gpr = MIN ( crtl -> args . info . sysv_gregno - GP_ARG_MIN_REG , GP_ARG_NUM_REG ) ; n_fpr = MIN ( crtl -> args . info . fregno - FP_ARG_MIN_REG , FP_ARG_NUM_REG ) ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , words , n_gpr , n_fpr ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>BaseRegisterInfo ( ) {


<s> auto found = std :: find_if ( Priv -> Blocks . begin ( ) , Priv -> Blocks . end ( ) , [ & ] ( auto block ) { return block -> getMBB ( ) == edge . first ; } ) ; assert ( found != Priv -> Blocks . end ( ) ) ;

( * found ) -> addExitTarget ( Priv -> getPredicatedParent ( edge . second ) ) ;


<s> if ( regno < <NUM_LIT> ) return LO_REGS ; return HI_REGS ; } if ( regno <= LAST_ARM_REGNUM || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GENERAL_REGS ;

if ( regno == CC_REGNUM || regno == VFPCC_REGNUM ) return NO_REGS ;


<s> bool SeenUse = false ; MachineBasicBlock :: reverse_iterator It = Br , Er = MBB . rend ( ) ; for ( It ++ ; It != Er ; It ++ ) { if ( It -> modifiesRegister ( CRBit , TRI ) ) { if ( ( It -> getOpcode ( ) == <STR_LIT> || It -> getOpcode ( ) == <STR_LIT> ) && It -> getOperand ( <NUM_LIT> ) . getReg ( ) == CRBit ) CRSetMI = & * It ; break ; } if ( It -> readsRegister ( CRBit , TRI ) ) SeenUse = true ; } if ( ! CRSetMI ) continue ; unsigned CRSetOp = CRSetMI -> getOpcode ( ) ; if ( ( Br -> getOpcode ( ) == <STR_LIT> && CRSetOp == <STR_LIT> ) || ( Br -> getOpcode ( ) == <STR_LIT> && CRSetOp == <STR_LIT> ) ) { InstrsToErase . push_back ( Br ) ; MBB . removeSuccessor ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; } else { MachineBasicBlock :: iterator It = Br , Er = MBB . end ( ) ; for ( ; It != Er ; It ++ ) { if ( It -> isDebugInstr ( ) ) continue ; assert ( It -> isTerminator ( ) && <STR_LIT> ) ; InstrsToErase . push_back ( & * It ) ; } if ( ! MBB . isLayoutSuccessor ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { ArrayRef < MachineOperand > NoCond ; TII -> insertBranch ( MBB , Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) , nullptr , NoCond , Br -> getDebugLoc ( ) ) ; } for ( auto & Succ : MBB . successors ( ) ) if ( Succ != Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) { MBB . removeSuccessor ( Succ ) ; break ; }


AU . addRequired < TargetPassConfig > ( ) ;


<s> MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( Result == <NUM_LIT> ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ;


<s> bool <ISA_LIT>TargetLowering :: findOptimalMemOpLowering ( std :: vector < EVT > & MemOps , unsigned Limit , const MemOp & Op , unsigned DstAS , unsigned SrcAS , const AttributeList & FuncAttributes ) const { const int MVCFastLen = <NUM_LIT> ; if ( Op . isMemcpy ( ) && Op . allowOverlap ( ) && Op . size ( ) <= MVCFastLen ) return false ;

if ( Op . isMemset ( ) && Op . size ( ) - <NUM_LIT> <= MVCFastLen ) return false ;


<s> if ( auto ShiftedVal = getShiftedVal < Shift > ( ) ) { Inst . addOperand ( MCOperand :: createImm ( - ShiftedVal -> first ) ) ;

Inst . addOperand ( MCOperand :: createImm ( ShiftedVal -> second ) ) ;


<s> const TargetSubtargetInfo & STI = DAG -> MF . getSubtarget ( ) ; const TargetInstrInfo * TII = STI . getInstrInfo ( ) ; delete Top . HazardRec ; delete Bot . HazardRec ; Top . HazardRec = TII -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; Bot . HazardRec = TII -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; delete Top . ResourceModel ; delete Bot . ResourceModel ; Top . ResourceModel = new VLIWResourceModel ( STI , DAG -> getSchedModel ( ) ) ;

Bot . ResourceModel = new VLIWResourceModel ( STI , DAG -> getSchedModel ( ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasV8_2aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasPerfMon ( false ) , HasFullFP16 ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , StrictAlign ( false ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) {


<s> FunctionPass * llvm :: create<ISA_LIT>RegisterAllocator ( ) {

return new <ISA_LIT>RegisterAllocator ( ) ;


<s> default : cpu = <STR_LIT> ; break ; } } if ( has_features == <NUM_LIT> && strncmp ( buf , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { const char * p ; p = strchr ( buf , ':' ) ; if ( p == NULL ) continue ; p ++ ; while ( * p != <NUM_LIT> ) { int i ; while ( ISSPACE ( * p ) ) p ++ ; for ( i = <NUM_LIT> ; ! ISSPACE ( p [ i ] ) && p [ i ] != <NUM_LIT> ; i ++ ) ; if ( i == <NUM_LIT> && strncmp ( p , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) has_dfp = <NUM_LIT> ; else if ( i == <NUM_LIT> && strncmp ( p , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) has_te = <NUM_LIT> ; else if ( i == <NUM_LIT> && strncmp ( p , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) has_vx = <NUM_LIT> ; else if ( i == <NUM_LIT> && strncmp ( p , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) has_highgprs = <NUM_LIT> ; p += i ; } has_features = <NUM_LIT> ; } } fclose ( f ) ; if ( cpu == NULL ) return NULL ; if ( arch ) { const char * opt_htm = <STR_LIT> ; const char * opt_vx = <STR_LIT> ; const char * opt_esa_zarch = <STR_LIT> ; if ( ! has_te ) opt_htm = <STR_LIT> ; if ( ! has_vx ) opt_vx = <STR_LIT> ; if ( ! has_opt_esa_zarch && has_highgprs ) opt_esa_zarch = <STR_LIT> ; options = concat ( options , opt_htm , opt_vx , opt_esa_zarch , NULL ) ; } if ( has_dfp && is_cpu_z9_109 ) cpu = <STR_LIT> ; return concat ( <STR_LIT> , argv [ <NUM_LIT> ] , <STR_LIT> , cpu , options , NULL ) ;


<s> return __builtin_neon_vrndxhf ( __a ) ;


<s> SDValue AMDGPUTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ;


<s> if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;

TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


<s> MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; Register HighBits = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , HighBits ) . addImm ( RemainderOffset ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrBase ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( HighBits ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( SplitImmOffset ) ; } , } } ; } } unsigned NumLiterals = ! TII . isInlineConstant ( APInt ( <NUM_LIT> , ConstOffset & <NUM_LIT> ) ) + ! TII . isInlineConstant ( APInt ( <NUM_LIT> , ConstOffset >> <NUM_LIT> ) ) ; if ( STI . getConstantBusLimit ( <STR_LIT> ) > NumLiterals ) return None ; } } } auto AddrDef = getDefSrcRegIgnoringCopies ( Addr , * MRI ) ; if ( ! AddrDef ) return None ; if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register SAddr = getSrcRegIgnoringCopies ( AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( SAddr && isSGPR ( SAddr ) ) { Register PtrBaseOffset = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register VOffset = matchZeroExtendFromS32 ( * MRI , PtrBaseOffset ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( SAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( VOffset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } } } if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> || AddrDef -> MI -> getOpcode ( ) == <STR_LIT> || ! isSGPR ( AddrDef -> Reg ) ) return None ; MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; Register VOffset = MRI -> createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , VOffset ) . addImm ( <NUM_LIT> ) ;


<s> unsigned CFSize = MFI . getMaxCallFrameSize ( ) ;

if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ;


<s> static bool MorphToQuadReg ( <ISA_LIT>Operand & Op ) { unsigned Reg = Op . getReg ( ) ; unsigned regIdx = <NUM_LIT> ; switch ( Op . Reg . Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case rk_FloatReg : regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return false ; Reg = QuadFPRegs [ regIdx / <NUM_LIT> ] ; break ; case rk_DoubleReg : regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return false ; Reg = QuadFPRegs [ regIdx / <NUM_LIT> ] ; break ; } Op . Reg . RegNum = Reg ;


<s> gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( CCmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat ) ; switch ( form_int ) { case <NUM_LIT> : emit_insn ( gen_move_from_CR_ov_bit ( target , scratch ) ) ; return target ; case <NUM_LIT> : code = EQ ; break ; case <NUM_LIT> : code = LT ; break ; case <NUM_LIT> : code = GT ; break ; default : error ( <STR_LIT> ) ; return const0_rtx ; } tmp = gen_rtx_fmt_ee ( code , SImode , scratch , const0_rtx ) ; emit_move_insn ( target , tmp ) ; return target ;


<s> if ( isAssociativeAndCommutative ( Inst . getOpcode ( ) ) && hasVirtualRegDefsInBasicBlock ( Inst , Inst . getParent ( ) ) && hasReassocSibling ( Inst , Commuted ) ) return true ; return false ;


<s> RegisterTarget < Triple :: ppc64 , true > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: ppc64le , true > Z ( getThe<ISA_LIT>64LETarget ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> else if ( DestVT == <STR_LIT> ) { unsigned Src64 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Src64 ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; SrcReg = Src64 ; } unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( DestVT ) ) ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( Imm ) ;


<s> MVT ExtVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ( ExtVT != <STR_LIT> || Subtarget -> is64Bit ( ) ) && SrcOp . getOpcode ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && SrcOp . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == ExtVT ) { OpVT = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , SrcOp . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) ) ;


<s> TRI -> getPhysRegClass ( Reg ) ; RC = TRI -> getSubRegClass ( RC , SubReg ) ;

for ( MachineRegisterInfo :: use_instr_iterator I = MRI . use_instr_begin ( Reg ) , E = MRI . use_instr_end ( ) ; I != E ; ++ I ) {


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FPStackOffset ( <NUM_LIT> ) , RAStackOffset ( <NUM_LIT> ) , CPUTopSavedRegOff ( <NUM_LIT> ) , FPUTopSavedRegOff ( <NUM_LIT> ) , GPHolder ( - <NUM_LIT> , - <NUM_LIT> ) , HasLoadArgs ( false ) , HasStoreVarArgs ( false ) , SRetReturnReg ( <NUM_LIT> ) {


<s> unsigned Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned RegNum = RegLst & <NUM_LIT> ;

for ( unsigned i = <NUM_LIT> ; i <= RegNum ; i ++ ) Inst . addOperand ( MCOperand :: createReg ( Regs [ i ] ) ) ;


<s> addPass ( create<ISA_LIT>IfConversionTerm ( ) ) ;


<s> if ( F -> hasFnAttribute ( <STR_LIT> ) || F -> hasFnAttribute ( <STR_LIT> ) ) { MachineFunction * MF = MMI -> getMachineFunction ( F ) ; assert ( MF ) ; <ISA_LIT>MachineFunctionInfo * PMFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; PMFI -> setSinglePath ( ) ; NumSPTotal ++ ; W . push_back ( MF ) ; } } while ( ! W . empty ( ) ) { MachineFunction * MF = W . front ( ) ;


<s> bool <ISA_LIT>MCChecker :: checkShuffle ( ) { <ISA_LIT>MCShuffler MCSDX ( Context , ReportErrors , MCII , STI , MCB ) ; return MCSDX . check ( ) ;


<s> calculate_dominance_info ( CDI_DOMINATORS ) ; insn = get_insns ( ) ; gcc_assert ( NOTE_P ( insn ) ) ; for ( insn = next_active_insn ( insn ) ; insn ; insn = next_active_insn ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_sethi && nds32_symbolic_operand ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) , SImode ) ) nds32_group_insns ( insn ) ; } } df_insn_rescan_all ( ) ; df_finish_pass ( false ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ;


<s> return true ; case ELF :: R_CPU0_HI16 : case ELF :: R_CPU0_LO16 : case ELF :: R_CPU0_32 : return true ; case ELF :: R_CPU0_GPREL16 : return false ; }


<s> if ( TM . getDrvInterface ( ) == <STR_LIT> ) return ( SmVersion >= <NUM_LIT> ) ;


<s> const_tree decl = SYMBOL_REF_DECL ( sym ) ; bool is_weak = ( decl && DECL_P ( decl ) && DECL_WEAK ( decl ) ) ;

if ( ! is_weak && SYMBOL_REF_LOCAL_P ( sym ) ) emit_insn ( gen_sym_label2reg ( reg , sym , lab ) ) ;


<s> ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; DAG -> addMutation ( create<ISA_LIT>MacroFusionDAGMutation ( ) ) ;


<s> Register Reg = MO . getReg ( ) ; if ( MO . isTied ( ) ) return false ; RegUse & Map = MO . isDef ( ) ? Uses : Defs ; auto Conflict = Map . find ( Reg ) ; if ( Conflict == Map . end ( ) ) continue ;

if ( Register :: isPhysicalRegister ( Reg ) ) return false ;


<s> static tree fold_build_vec_cmp ( tree_code code , tree type , tree arg0 , tree arg1 ) { tree cmp_type = truth_type_for ( type ) ; tree zero_vec = build_zero_cst ( type ) ; tree minus_one_vec = build_minus_one_cst ( type ) ; tree cmp = fold_build2 ( code , cmp_type , arg0 , arg1 ) ; return fold_build3 ( VEC_COND_EXPR , type , cmp , minus_one_vec , zero_vec ) ;


<s> MVT VT = LD -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned Opc = ( VT == <STR_LIT> ? Opc32 : VT == <STR_LIT> ? Opc16 : Opc8 ) ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N1 ) -> getMemOperand ( ) ; SDValue Ops0 [ ] = { N2 , LD -> getBasePtr ( ) , LD -> getChain ( ) } ; SDNode * ResNode = CurDAG -> SelectNodeTo ( Op , Opc , VT , <STR_LIT> , <STR_LIT> , Ops0 , <NUM_LIT> ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; ReplaceUses ( SDValue ( N1 . getNode ( ) , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N1 . getNode ( ) , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; return ResNode ; } return NULL ;


<s> void setScratchRSrcReg ( Register Reg ) {

assert ( Reg != <NUM_LIT> && <STR_LIT> ) ;


<s> return new <ISA_LIT>TileConfig ( ) ;


<s> auto Default = std :: make_pair ( Root . getReg ( ) , <NUM_LIT> ) ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI -> getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ; if ( ! TII . isLegalFLATOffset ( Offset . getValue ( ) , AddrSpace , Signed ) ) return Default ; Register BasePtr = OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

return std :: make_pair ( BasePtr , Offset . getValue ( ) ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , DL , TII -> get ( AddOpcode ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( - <NUM_LIT> ) ; MachineInstr * BRCL = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BRCL -> addRegisterKilled ( <STR_LIT> , & TII -> getRegisterInfo ( ) ) ;


<s> return ( rtx_equal_p ( XEXP ( cond1 , <NUM_LIT> ) , XEXP ( cond2 , <NUM_LIT> ) ) && rtx_equal_p ( XEXP ( cond1 , <NUM_LIT> ) , XEXP ( cond2 , <NUM_LIT> ) ) && GET_CODE ( cond1 ) == reverse_condition ( GET_CODE ( cond2 ) ) ) ;


<s> if ( TREE_CODE ( exp ) == STRING_CST ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = TREE_STRING_POINTER ( DECL_SECTION_NAME ( exp ) ) ; if ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) return true ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp ) ) ;

if ( size > <NUM_LIT> && ( unsigned HOST_WIDE_INT ) size <= g_switch_value ) return true ;


<s> <ISA_LIT>RRIAddressMode ( bool RI = false ) : BaseType ( RegBase ) , IndexReg ( ) , Disp ( <NUM_LIT> ) , isRI ( RI ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( ) const { const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( Subtarget -> is64Bit ( ) ) return & <STR_LIT> ;


<s> NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; if ( isSigned && Offset < <NUM_LIT> ) Offset = - Offset ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ;

if ( ( unsigned ) Offset <= Mask * Scale ) return true ;


<s> DetectRoundChange :: DetectRoundChange ( ) : LEONMachineFunctionPass ( ID ) {


<s> assert ( dstBlk ) ; if ( srcBlk == dstBlk ) { return SinglePath_InPath ; } while ( srcBlk && srcBlk -> succ_size ( ) == <NUM_LIT> ) { srcBlk = * srcBlk -> succ_begin ( ) ; if ( srcBlk == dstBlk ) { return SinglePath_InPath ; } if ( ! allowSideEntry && srcBlk -> pred_size ( ) > <NUM_LIT> ) { return Not_SinglePath ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & DefaultSubtarget ;


<s> MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * MF -> getSubtarget ( ) . getInstrInfo ( ) , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , MF -> getSubtarget ( ) ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ;

MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ;


<s> SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( SVOp ) ; MVT VT = SVOp -> getSimpleValueType ( <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; unsigned MaskValue = <NUM_LIT> ; unsigned NumLanes = ( NumElems - <NUM_LIT> ) / <NUM_LIT> + <NUM_LIT> ; unsigned NumElemsInLane = NumElems / NumLanes ; for ( unsigned i = <NUM_LIT> ; i < NumElemsInLane ; ++ i ) {

int SndLaneEltIdx = ( NumLanes == <NUM_LIT> ) ? SVOp -> getMaskElt ( i + NumElemsInLane ) : - <NUM_LIT> ;


<s> if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : return true ; case <NUM_LIT> : return true ; case <NUM_LIT> : if ( AM . HasBaseReg ) { return false ; } return true ; default : return false ; } } case <STR_LIT> : case <STR_LIT> : { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ;

if ( AM . Scale == <NUM_LIT> ) return true ;


<s> return getNamedSection ( Name . c_str ( ) , SectionFlags :: setEntitySize ( SectionFlags :: Mergeable | SectionFlags :: Small , Size ) ) ; } return getReadOnlySection ( ) ;


<s> SeenPointer = Tag == dwarf :: DW_TAG_pointer_type ; } if ( CheckPointer && SeenPointer ) { const DIType * Base = DTy -> getBaseType ( ) ; if ( Base ) { if ( const auto * CTy = dyn_cast < DICompositeType > ( Base ) ) { auto CTag = CTy -> getTag ( ) ; if ( ( CTag == dwarf :: DW_TAG_structure_type || CTag == dwarf :: DW_TAG_union_type ) && ! CTy -> isForwardDecl ( ) ) { auto TypeEntry = std :: make_unique < BTFTypeDerived > ( DTy , Tag , true ) ; auto & Fixup = FixupDerivedTypes [ CTy -> getName ( ) ] ;

Fixup . first = CTag == dwarf :: DW_TAG_union_type ;


<s> unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IID ) { default : return nullptr ; case <STR_LIT> :


<s> SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setHasSpills ( ) ; bool NonRI = false , SpillsVRS = false ; if ( StoreRegToStackSlot ( MF , SrcReg , isKill , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( NonRI ) FuncInfo -> setHasNonRISpills ( ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ;

NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ;


<s> <ISA_LIT>RDFOpt ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>RDFOptPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> unsigned SRsrcSub3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub0 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub1 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub2 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrcSub3 ) . addReg ( VRsrc , VRsrcUndef , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrc ) . addReg ( SRsrcSub0 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub1 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub2 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcSub3 ) . addImm ( <STR_LIT> ) ; Rsrc . setReg ( SRsrc ) ; Rsrc . setIsKill ( true ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CondReg0 ) . addReg ( SRsrc , <NUM_LIT> , <STR_LIT> ) . addReg ( VRsrc , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CondReg1 ) . addReg ( SRsrc , <NUM_LIT> , <STR_LIT> ) . addReg ( VRsrc , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , AndCond ) . addReg ( CondReg0 ) . addReg ( CondReg1 ) ; MRI . setSimpleHint ( SaveExec , AndCond ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SaveExec ) . addReg ( AndCond , RegState :: Kill ) ; I = LoopBB . end ( ) ;

BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( SaveExec ) ;


<s> else gcc_unreachable ( ) ; } if ( symbolic_operand ( src , VOIDmode ) ) { if ( ( TARGET_CMODEL_TINY && ( ! loongarch_global_symbol_p ( src ) || loongarch_symbol_binds_local_p ( src ) ) ) || ( TARGET_CMODEL_TINY_STATIC && ! loongarch_weak_symbol_p ( src ) ) ) { unsigned int align ; if ( LABEL_REF_P ( src ) ) align = <NUM_LIT> ; else if ( CONSTANT_POOL_ADDRESS_P ( src ) ) align = GET_MODE_ALIGNMENT ( get_pool_mode ( src ) ) ; else if ( TREE_CONSTANT_POOL_ADDRESS_P ( src ) ) { tree exp = SYMBOL_REF_DECL ( src ) ; align = TYPE_ALIGN ( TREE_TYPE ( exp ) ) ; align = loongarch_constant_alignment ( exp , align ) ; } else if ( SYMBOL_REF_DECL ( src ) ) align = DECL_ALIGN ( SYMBOL_REF_DECL ( src ) ) ; else if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( src ) && SYMBOL_REF_BLOCK ( src ) != NULL ) align = SYMBOL_REF_BLOCK ( src ) -> alignment ; else align = BITS_PER_UNIT ; if ( align % ( <NUM_LIT> * <NUM_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; } if ( TARGET_CMODEL_TINY || TARGET_CMODEL_TINY_STATIC || TARGET_CMODEL_NORMAL || TARGET_CMODEL_LARGE ) { if ( ! loongarch_global_symbol_p ( src ) || loongarch_symbol_binds_local_p ( src ) ) return <STR_LIT> ; else return <STR_LIT> ; } if ( TARGET_CMODEL_EXTREME ) { sorry ( <STR_LIT> ) ; gcc_unreachable ( ) ; } } } if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) { if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) return dbl_p ? <STR_LIT> : <STR_LIT> ; if ( dest_code == MEM ) { const char * insn = NULL ; insn = loongarch_output_move_index_float ( XEXP ( dest , <NUM_LIT> ) , GET_MODE ( dest ) , false ) ; if ( insn ) return insn ; return dbl_p ? <STR_LIT> : <STR_LIT> ; } } if ( dest_code == REG && FP_REG_P ( REGNO ( dest ) ) ) { if ( src_code == MEM ) { const char * insn = NULL ; insn = loongarch_output_move_index_float ( XEXP ( src , <NUM_LIT> ) , GET_MODE ( src ) , true ) ; if ( insn ) return insn ;


<s> const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT> ) ; O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << ImmOffs ;


<s> void <ISA_LIT>IRDecorator :: ReplaceConstantGlobsRefs ( GlobalVariable * GV , GlobalVariable * GCStruct , GlobFieldOffsetMap & GlobOffsetMap ) { LLVMContext & Cxt = Func -> getContext ( ) ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; Type * TargetIdxTy = GetTargetIndexType ( DL , Cxt ) ; SmallVector < Instruction * , <NUM_LIT> > RemoveList ; SmallVector < std :: pair < Instruction * , Value * > , <NUM_LIT> > UserGEPClonePairVec ; for ( auto Use = GV -> use_begin ( ) ; Use != GV -> use_end ( ) ; Use ++ ) { SmallVector < Value * , <NUM_LIT> > Indices ; unsigned FldIndex = GlobOffsetMap [ GV ] ; Indices . push_back ( ConstantInt :: get ( TargetIdxTy , <NUM_LIT> ) ) ;

Indices . push_back ( ConstantInt :: get ( TargetIdxTy , FldIndex ) ) ;


<s> bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> hasFnAttr ( Attribute :: StackAlignment ) ) ;

if ( ForceStackAlign ) return canRealignStack ( MF ) ;


<s> void <ISA_LIT>InstPrinter :: printTFE ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printNamedBit ( MI , OpNo , O , <STR_LIT> ) ;


<s> SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ;

if ( Kind . isDataNoRel ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ;


<s> if ( Inst -> getOperand ( ImmOpPosition ) . getImm ( ) == <NUM_LIT> && Inst -> getOperand ( BaseOpPosition ) . getReg ( ) == <NUM_LIT> ) { Inst -> getOperand ( BaseOpPosition ) . setReg ( IndexReg ) ;

Inst -> getOperand ( IndexOpPosition ) . setReg ( <NUM_LIT> ) ;


<s> if ( ValVT . getSizeInBits ( ) <= <NUM_LIT> && ( ( LT . second == <STR_LIT> && RevVTSize <= <NUM_LIT> ) || ( LT . second == <STR_LIT> && RevVTSize <= ( IsMLA ? <NUM_LIT> : <NUM_LIT> ) ) || ( LT . second == <STR_LIT> && RevVTSize <= <NUM_LIT> ) ) ) return ST -> getMVEVectorCostFactor ( CostKind ) * LT . first ;


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; if ( MFI -> hasVarSizedObjects ( ) ) llvm_unreachable ( <STR_LIT> ) ; if ( MBBI -> getOpcode ( ) != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; const <ISA_LIT>InstrInfo & TII = * TM . getInstrInfo ( ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . enablePostRAScheduler ( ) ) { <ISA_LIT>InstrInfo :: addFormOp ( <ISA_LIT>InstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ) , <STR_LIT> , true ) ; MBBI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; <ISA_LIT>InstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ) ; <ISA_LIT>InstrInfo :: addFormOp ( <ISA_LIT>InstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) , <STR_LIT> , false ) ; } else { <ISA_LIT>InstrInfo :: addDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ) ; }


<s> unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Copy = BuildMI ( * MI -> getParent ( ) , MI , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( LiveMaskReg ) ; LIS -> ReplaceMachineInstrInMaps ( * MI , * Copy ) ; MI -> eraseFromParent ( ) ;


<s> Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ;


<s> <ISA_LIT>ImmToReg ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ImmToRegPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> int <ISA_LIT>InstrInfo :: getMinValue ( const MachineInstr * MI ) const {

const uint64_t F = MI -> getDesc ( ) . TSFlags ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> static SDValue splitVectorIntUnary ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; assert ( ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) || Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . is512BitVector ( ) ) && ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && <STR_LIT> ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ;


<s> return AFI -> getTailCallReservedStack ( ) ; } else { if ( AFI -> getTailCallReservedStack ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; const unsigned VarArgsArea = AFI -> getVarArgsGPRSize ( ) ; const unsigned UnwindHelpObject = ( MF . hasEHFunclets ( ) ? <NUM_LIT> : <NUM_LIT> ) ; return alignTo ( VarArgsArea + UnwindHelpObject , <NUM_LIT> ) ; }


<s> for ( i = <NUM_LIT> ; i < n ; ++ i ) current_frame_info . gr_used_mask |= <NUM_LIT> << ( regno + i ) ; }


<s> Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = B . getMRI ( ) -> getType ( Dst ) ; unsigned Flags = MI . getFlags ( ) ; B . setInstr ( MI ) ; auto Log2Operand = B . buildFLog2 ( Ty , Src , Flags ) ; auto Log2BaseInvertedOperand = B . buildFConstant ( Ty , Log2BaseInverted ) ;

B . buildFMul ( Dst , Log2Operand , Log2BaseInvertedOperand , Flags ) ;


<s> case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> , Call ) ;


<s> MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; LoadCmpBB -> addLiveIn ( Addr . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DestLo . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DestHi . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DesiredLo . getReg ( ) ) ; LoadCmpBB -> addLiveIn ( DesiredHi . getReg ( ) ) ; addPostLoopLiveIns ( LoadCmpBB , LiveRegs ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestLo . getReg ( ) , RegState :: Define ) . addReg ( DestHi . getReg ( ) , RegState :: Define ) . addReg ( Addr . getReg ( ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestLo . getReg ( ) , getKillRegState ( DestLo . isDead ( ) ) ) . addOperand ( DesiredLo ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DestHi . getReg ( ) , getKillRegState ( DestHi . isDead ( ) ) ) . addOperand ( DesiredHi ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( DoneBB ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( NewLo . getReg ( ) ) ; StoreBB -> addLiveIn ( NewHi . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addOperand ( NewLo ) . addOperand ( NewHi ) . addOperand ( Addr ) ;

BuildMI ( StoreBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StatusReg , RegState :: Kill ) . addMBB ( LoadCmpBB ) ;


<s> MachineBasicBlock :: iterator <ISA_LIT>LoadStoreOptimizer :: mergeBufferStorePair ( CombineInfo & CI ) { MachineBasicBlock * MBB = CI . I -> getParent ( ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; const unsigned Opcode = getNewOpcode ( CI ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI ) ; Register SrcReg = MRI -> createVirtualRegister ( SuperRC ) ; const auto * Src0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ;

const auto * Src1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: vdata ) ;


<s> static bool c6x_scalar_mode_supported_p ( scalar_mode mode ) { if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= <NUM_LIT> * BITS_PER_WORD ) return true ; return default_scalar_mode_supported_p ( mode ) ;


<s> if ( crtl -> calls_eh_return ) { unsigned i ; for ( i = <NUM_LIT> ; EH_RETURN_DATA_REGNO ( i ) != INVALID_REGNUM ; i ++ ) { if ( regno == EH_RETURN_DATA_REGNO ( i ) ) return true ; } } return false ;


<s> void printS22ImmOperand ( const MachineInstr * MI , unsigned OpNo ) { int val = ( unsigned int ) MI -> getOperand ( OpNo ) . getImm ( ) ;

if ( val >= <NUM_LIT> ) val = val - <NUM_LIT> ;


<s> while ( true ) { End = Tok . getEndLoc ( ) ; getLexer ( ) . Lex ( ) ; assert ( End . getPointer ( ) <= EndPtr && <STR_LIT> ) ; if ( End . getPointer ( ) == EndPtr ) break ; } Identifier = LineBuf ; if ( ! Result ) { StringRef InternalName = SemaCallback -> LookupInlineAsmLabel ( Identifier , getSourceManager ( ) , Loc , false ) ; assert ( InternalName . size ( ) && <STR_LIT> ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Label , Loc , Identifier . size ( ) , InternalName ) ) ; } MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Identifier ) ; MCSymbolRefExpr :: VariantKind Variant = MCSymbolRefExpr :: VK_None ;

Val = MCSymbolRefExpr :: Create ( Sym , Variant , getParser ( ) . getContext ( ) ) ;


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitterEB ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitterEB ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCCodeEmitterEL ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>elTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>64elTarget , createMCStreamer ) ; TargetRegistry :: RegisterAsmStreamer ( The<ISA_LIT>Target , createMCAsmStreamer ) ; TargetRegistry :: RegisterAsmStreamer ( The<ISA_LIT>elTarget , createMCAsmStreamer ) ; TargetRegistry :: RegisterAsmStreamer ( The<ISA_LIT>64Target , createMCAsmStreamer ) ; TargetRegistry :: RegisterAsmStreamer ( The<ISA_LIT>64elTarget , createMCAsmStreamer ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackendEB32 ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>elTarget , create<ISA_LIT>AsmBackendEL32 ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>64Target , create<ISA_LIT>AsmBackendEB64 ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>64elTarget , create<ISA_LIT>AsmBackendEL64 ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>64elTarget , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;

TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstPrinter ) ;


<s> if ( FoldOp -> isImm ( ) ) { ImmToFold = FoldOp -> getImm ( ) ; } else if ( FoldOp -> isFI ( ) ) { FrameIndexToFold = FoldOp -> getIndex ( ) ;


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const {

const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ;


<s> split_const ( x , & base , & offset ) ; if ( riscv_symbolic_constant_p ( base , & type ) ) { if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > <NUM_LIT> ) return true ; if ( flag_pic ) return true ; }

if ( tls_referenced_p ( x ) ) return true ;


<s> return __builtin_aarch64_smaxv2sf ( __a , __b ) ;


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target , create<ISA_LIT>Disassembler ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetNo<ISA_LIT>16 ( ) {


<s> for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ;


<s> const LegalizerInfo * <ISA_LIT>Subtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ;


<s> if ( oneFunc && ( curFunc != oneFunc ) ) return false ; oneFunc = curFunc ; return true ; } else return false ; } if ( const MDNode * md = dyn_cast < MDNode > ( U ) ) if ( md -> hasName ( ) && ( ( md -> getName ( ) . str ( ) == <STR_LIT> ) || ( md -> getName ( ) . str ( ) == <STR_LIT> ) ) ) return true ; for ( User :: const_use_iterator ui = U -> use_begin ( ) , ue = U -> use_end ( ) ; ui != ue ; ++ ui ) { if ( usedInOneFunc ( * ui , oneFunc ) == false ) return false ;


<s> } if ( TII -> usesLGKM_CNT ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; if ( mayAccessLDSThroughFlat ( Inst ) ) ScoreBrackets -> setPendingFlat ( ) ; } } else if ( <ISA_LIT>InstrInfo :: isVMEM ( Inst ) && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) { if ( ! ST -> hasVscnt ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; else if ( ( Inst . mayLoad ( ) && <STR_LIT> ( Inst . getOpcode ( ) ) == - <NUM_LIT> ) || ( TII -> isMIMG ( Inst ) && ! Inst . mayLoad ( ) && ! Inst . mayStore ( ) ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_READ_ACCESS , Inst ) ; else if ( Inst . mayStore ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_WRITE_ACCESS , Inst ) ; if ( ST -> vmemWriteNeedsExpWaitcnt ( ) && ( Inst . mayStore ( ) || <STR_LIT> ( Inst . getOpcode ( ) ) != - <NUM_LIT> ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMW_GPR_LOCK , Inst ) ; } } else if ( TII -> isSMRD ( Inst ) ) {

ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ;


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ;


<s> if ( ! ( recog_memoized ( use_insn ) == CODE_FOR_lo_sum || nds32_symbol_load_store_p ( use_insn ) || ( nds32_reg_base_load_store_p ( use_insn ) && ! nds32_sp_base_or_plus_load_store_p ( use_insn ) ) ) ) return ; } group_id = GEN_INT ( relax_group_id ) ; emit_insn_before ( gen_relax_group ( group_id ) , sethi ) ; for ( link = DF_REF_CHAIN ( def_record ) ; link ; link = link -> next ) { if ( ! DF_REF_INSN_INFO ( link -> ref ) ) continue ; use_insn = DF_REF_INSN ( link -> ref ) ;


<s> static bool UpdateOperandRegClass ( MachineInstr * Instr ) { MachineBasicBlock * MBB = Instr -> getParent ( ) ; assert ( MBB && <STR_LIT> ) ; MachineFunction * MF = MBB -> getParent ( ) ; assert ( MF && <STR_LIT> ) ; const TargetMachine * TM = & MF -> getTarget ( ) ; const TargetInstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; const TargetRegisterInfo * TRI = TM -> getSubtargetImpl ( ) -> getRegisterInfo ( ) ; MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; for ( unsigned OpIdx = <NUM_LIT> , EndIdx = Instr -> getNumOperands ( ) ; OpIdx < EndIdx ;


<s> if ( tryParseRegister ( RegNo , S , E ) == MatchOperand_Success ) { Operands . push_back ( <STR_LIT> ( RegNo , S , E ) ) ;


<s> CodePointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; UseIntegratedAssembler = true ; SupportsDebugInformation = true ;


<s> AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ;


<s> const <ISA_LIT>MachineFunctionInfo & PMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

if ( Reg == <STR_LIT> && PMFI . getS0SpillReg ( ) ) return true ;