<s> for ( unsigned i = <NUM_LIT> ; i < size ; i ++ ) { if ( i ) O << <STR_LIT> ; O << ( unsigned int ) buffer [ i ] ; } } else { unsigned int pos = <NUM_LIT> ; unsigned int nSym = <NUM_LIT> ; unsigned int nextSymbolPos = symbolPosInBuffer [ nSym ] ; unsigned int nBytes = <NUM_LIT> ; if ( AP . nvptxSubtarget . is64Bit ( ) ) nBytes = <NUM_LIT> ; for ( pos = <NUM_LIT> ; pos < size ; pos += nBytes ) { if ( pos ) O << <STR_LIT> ; if ( pos == nextSymbolPos ) { const Value * v = Symbols [ nSym ] ; if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { MCSymbol * Name = AP . Mang -> getSymbol ( GVar ) ; O << * Name ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) { O << * <STR_LIT> ( Cexpr , AP ) ; } else llvm_unreachable ( <STR_LIT> ) ; nSym ++ ;

if ( nSym >= numSymbols ) nextSymbolPos = size + <NUM_LIT> ;


<s> if ( checkPrivateAddress ( N -> getMemOperand ( ) ) ) { if ( isCPLoad ( N ) || isConstantLoad ( N , - <NUM_LIT> ) ) { return false ; } } const Value * MemVal = N -> getMemOperand ( ) -> getValue ( ) ; if ( ! checkType ( MemVal , <STR_LIT> ) && ! checkType ( MemVal , <STR_LIT> ) && ! checkType ( MemVal , <STR_LIT> ) && ! checkType ( MemVal , <STR_LIT> ) && ! checkType ( MemVal , <STR_LIT> ) && ! checkType ( MemVal , <STR_LIT> ) && ! checkType ( MemVal , <STR_LIT> ) ) { return true ; } return false ;


<s> bool has16BitE<ISA_LIT>Ops ( ) const { return false ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDLoc SL ( N ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SL , VT , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ; } if ( const ConstantSDNode * Arg = dyn_cast < ConstantSDNode > ( Src ) ) { if ( Arg -> isZero ( ) ) return DAG . getConstant ( <NUM_LIT> , SL , VT ) ; if ( Arg -> isOne ( ) ) {


<s> if ( <ISA_LIT>MCInstrInfo :: isImmext ( * JumpInst ) ) { JExtended = true ; continue ; } if ( <ISA_LIT>MCInstrInfo :: getType ( MCII , * JumpInst ) == <STR_LIT> ) { bool BExtended = false ; for ( MCInst :: iterator B = MCI . begin ( ) + <ISA_LIT>MCInstrInfo :: bundleInstructionsOffset ; B != MCI . end ( ) ; ++ B ) { MCInst const * Inst = B -> getInst ( ) ; if ( JumpInst == Inst ) { BExtended = false ; continue ; } if ( <ISA_LIT>MCInstrInfo :: isImmext ( * Inst ) ) { BExtended = true ; continue ;


<s> <ISA_LIT>V9TargetMachine :: <ISA_LIT>V9TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override {


<s> <ISA_LIT>ConstantIslands ( ) : MachineFunctionPass ( ID ) {


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : ForceFramePointer ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) , BytesToPopOnReturn ( <NUM_LIT> ) , DecorationStyle ( None ) , ReturnAddrIndex ( <NUM_LIT> ) , TailCallReturnAddrDelta ( <NUM_LIT> ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned StackAlign = TRI -> needsStackRealignment ( MF ) ? MFI -> getMaxAlignment ( ) : MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = RoundUpToAlignment ( maxCallFrameSize , StackAlign ) ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI -> adjustsStack ( ) ) ) FrameSize += maxCallFrameSize ; FrameSize = RoundUpToAlignment ( FrameSize , StackAlign ) ; MFI -> setStackSize ( FrameSize ) ;


<s> void fixup_call ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) {

adjustBranch ( Size , Fixup , Value , Ctx ) ;


<s> AddrReg = constrainOperandRegClass ( II , AddrReg , II . getNumDefs ( ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( AddrReg ) ;

for ( unsigned i = <NUM_LIT> , e = BI -> getNumSuccessors ( ) ; i != e ; ++ i ) FuncInfo . MBB -> addSuccessor ( FuncInfo . MBBMap [ BI -> getSuccessor ( i ) ] ) ;


<s> Base = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , CurDAG -> getEntryNode ( ) . getDebugLoc ( ) , AMDGPU :: ZERO , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( IMMOffset -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } Base = Addr ;

Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> case R17 : case X17 : case F17 : case V17 : case CR4GT : return <NUM_LIT> ; case R18 : case X18 : case F18 : case V18 : case CR4EQ : return <NUM_LIT> ; case R19 : case X19 : case F19 : case V19 : case CR4UN : return <NUM_LIT> ; case R20 : case X20 : case F20 : case V20 : case CR5LT : return <NUM_LIT> ; case R21 : case X21 : case F21 : case V21 : case CR5GT : return <NUM_LIT> ; case R22 : case X22 : case F22 : case V22 : case CR5EQ : return <NUM_LIT> ; case R23 : case X23 : case F23 : case V23 : case CR5UN : return <NUM_LIT> ; case R24 : case X24 : case F24 : case V24 : case CR6LT : return <NUM_LIT> ; case R25 : case X25 : case F25 : case V25 : case CR6GT : return <NUM_LIT> ; case R26 : case X26 : case F26 : case V26 : case CR6EQ : return <NUM_LIT> ; case R27 : case X27 : case F27 : case V27 : case CR6UN : return <NUM_LIT> ; case R28 : case X28 : case F28 : case V28 : case CR7LT : return <NUM_LIT> ;

case R29 : case X29 : case F29 : case V29 : case CR7GT : return <NUM_LIT> ;


<s> fprintf ( f , <STR_LIT> ) ; } fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ;


<s> for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( <NUM_LIT> , reg ) , <NUM_LIT> ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = <NUM_LIT> ; i < nclobs ; ++ i ) XVECEXP ( insn , <NUM_LIT> , i ) = clobs [ i ] ;


<s> <ISA_LIT>MangledLibFunc :: <ISA_LIT>MangledLibFunc ( EFuncId id , const <ISA_LIT>MangledLibFunc & copyFrom ) { FuncId = id ; FKind = copyFrom . FKind ; Leads [ <NUM_LIT> ] = copyFrom . Leads [ <NUM_LIT> ] ; Leads [ <NUM_LIT> ] = copyFrom . Leads [ <NUM_LIT> ] ;


<s> if ( AlwaysBasePointer ) return true ;


<s> if ( i + <NUM_LIT> == e ) { SOffsetRegState |= getKillRegState ( Scavenged ) ; SrcDstRegState |= getKillRegState ( IsKill ) ; } const bool NeedSuperRegDef = NumSubRegs > <NUM_LIT> && IsStore && i == <NUM_LIT> ; auto MIB = spillVGPRtoAGPR ( ST , MI , Index , i , SubReg , IsKill ) ; if ( ! MIB . getInstr ( ) ) { unsigned FinalReg = SubReg ; const bool IsAGPR = hasAGPRs ( RC ) ; if ( IsAGPR ) { if ( ! TmpReg ) { assert ( RS && <STR_LIT> ) ; TmpReg = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; RS -> setRegUsed ( TmpReg ) ; } if ( IsStore ) { auto AccRead = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SubReg , getKillRegState ( IsKill ) ) ; if ( NeedSuperRegDef ) AccRead . addReg ( ValueReg , RegState :: ImplicitDefine ) ; } SubReg = TmpReg ; } MachinePointerInfo PInfo = BasePtrInfo . getWithOffset ( EltSize * i ) ; MachineMemOperand * NewMMO = MF -> getMachineMemOperand ( PInfo , MMO -> getFlags ( ) , EltSize , commonAlignment ( Alignment , EltSize * i ) ) ; MIB = BuildMI ( * MBB , MI , DL , * Desc ) . addReg ( SubReg , getDefRegState ( ! IsStore ) | getKillRegState ( IsKill ) ) ; if ( ! IsFlat ) MIB . addReg ( ScratchRsrcReg ) ; if ( SOffset == <STR_LIT> ) { if ( ! IsFlat ) MIB . addImm ( <NUM_LIT> ) ; } else { MIB . addReg ( SOffset , SOffsetRegState ) ; } MIB . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; if ( ! IsFlat ) MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MIB . addMemOperand ( NewMMO ) ; if ( ! IsAGPR && NeedSuperRegDef ) MIB . addReg ( ValueReg , RegState :: ImplicitDefine ) ; if ( ! IsStore && TmpReg != <STR_LIT> ) MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , FinalReg ) . addReg ( TmpReg , RegState :: Kill ) ;


<s> return Parser . Error ( L , Msg , Ranges ) ;


<s> return __builtin_mve_vrshrq_n_uv4si ( __a , __imm ) ;


[ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


return ( __m512i ) __builtin_ia32_pmovsxdq512_mask ( ( __v8si ) __X , ( __v8di ) _mm512_setzero_si512 ( ) , ( __mmask8 ) __U ) ;


<s> const MCOperand & Disp = MI . getOperand ( Op + <STR_LIT> ) ; if ( is16BitMode ( STI ) && BaseReg . getReg ( ) == <NUM_LIT> && Disp . isImm ( ) && Disp . getImm ( ) < <NUM_LIT> ) return true ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; return false ;


<s> return true ; } IndexReg = TmpReg ; Scale = TmpInt ; if ( checkScale ( Scale , ErrMsg ) ) return true ; IC . popOperator ( ) ; } else { IC . pushOperand ( IC_IMM , TmpInt ) ; } break ; }


<s> if ( RC == & <STR_LIT> ) { return <ISA_LIT>Reg32PressureLimit ; } if ( RC == & <STR_LIT> ) { return <ISA_LIT>Reg64PressureLimit ;


<s> return static_cast < const MCConstantExpr * > ( getMemOff ( ) ) -> getValue ( ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) : ) ; return result ;


<s> verifyInstructionPredicates ( MI , Features ) ; EndianWriter OSE ( OS , <STR_LIT> ) ; const uint64_t OpCode = getBinaryCodeForInstr ( MI , Fixups , STI ) ;

const uint32_t NumWords = MI . getNumOperands ( ) + <NUM_LIT> ;


<s> } MI -> setDesc ( TII -> get ( Opc ) ) ; } if ( Opc == <STR_LIT> && OpToFold -> isImm ( ) ) { MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; appendFoldCandidate ( FoldList , MI , OpNo , OpToFold ) ; return true ; } if ( isUseMIInFoldList ( FoldList , MI ) ) return false ; unsigned CommuteOpNo = OpNo ; unsigned CommuteIdx0 = TargetInstrInfo :: CommuteAnyOperandIndex ; unsigned CommuteIdx1 = TargetInstrInfo :: CommuteAnyOperandIndex ; bool CanCommute = TII -> findCommutedOpIndices ( * MI , CommuteIdx0 , CommuteIdx1 ) ; if ( CanCommute ) { if ( CommuteIdx0 == OpNo ) CommuteOpNo = CommuteIdx1 ; else if ( CommuteIdx1 == OpNo ) CommuteOpNo = CommuteIdx0 ; } if ( CanCommute && ( ! MI -> getOperand ( CommuteIdx0 ) . isReg ( ) || ! MI -> getOperand ( CommuteIdx1 ) . isReg ( ) ) ) return false ; if ( ! CanCommute || ! TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ) return false ; if ( ! TII -> isOperandLegal ( * MI , CommuteOpNo , OpToFold ) ) { if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( OpToFold -> isImm ( ) || OpToFold -> isFI ( ) || OpToFold -> isGlobal ( ) ) ) { MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0 ; MachineOperand & OtherOp = MI -> getOperand ( OtherIdx ) ; if ( ! OtherOp . isReg ( ) || ! TII -> getRegisterInfo ( ) . isVGPR ( MRI , OtherOp . getReg ( ) ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isDef ( ) ) ; unsigned MaybeCommutedOpc = MI -> getOpcode ( ) ; int Op32 = <STR_LIT> ( MaybeCommutedOpc ) ; appendFoldCandidate ( FoldList , MI , CommuteOpNo , OpToFold , true , Op32 ) ; return true ; } TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ; return false ; }

appendFoldCandidate ( FoldList , MI , CommuteOpNo , OpToFold , true ) ;


<s> if ( s390_function_arg_float ( mode , type ) ) { if ( cum -> fprs + <NUM_LIT> > FP_ARG_NUM_REG ) return <NUM_LIT> ; else return gen_rtx_REG ( mode , cum -> fprs + <NUM_LIT> ) ; } else if ( s390_function_arg_integer ( mode , type ) ) { int size = s390_function_arg_size ( mode , type ) ; int n_gprs = ( size + UNITS_PER_LONG - <NUM_LIT> ) / UNITS_PER_LONG ; if ( cum -> gprs + n_gprs > GP_ARG_NUM_REG ) return <NUM_LIT> ; else if ( n_gprs == <NUM_LIT> || UNITS_PER_WORD == UNITS_PER_LONG ) return gen_rtx_REG ( mode , cum -> gprs + <NUM_LIT> ) ; else if ( n_gprs == <NUM_LIT> ) { rtvec p = rtvec_alloc ( <NUM_LIT> ) ; RTVEC_ELT ( p , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , cum -> gprs + <NUM_LIT> ) , const0_rtx ) ; RTVEC_ELT ( p , <NUM_LIT> ) = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , cum -> gprs + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; return gen_rtx_PARALLEL ( mode , p ) ; }


<s> if ( is64Bit ) setRelocationModel ( Reloc :: PIC_ ) ; else if ( ! Subtarget . isTargetDarwin ( ) ) setRelocationModel ( Reloc :: Static ) ; } if ( getRelocationModel ( ) == Reloc :: Static && Subtarget . isTargetDarwin ( ) && is64Bit ) setRelocationModel ( Reloc :: PIC_ ) ; if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ;


<s> unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; return S ;


<s> if ( ! C ) return false ; ScaledConstant = ( int ) C -> getZExtValue ( ) ; if ( ( ScaledConstant % Scale ) != <NUM_LIT> ) return false ;


<s> void addRegShiftedImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isRegShiftedImm ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegShiftedImm . SrcReg ) ) ; unsigned Imm = ( RegShiftedImm . ShiftImm == <NUM_LIT> ? <NUM_LIT> : RegShiftedImm . ShiftImm ) ;

Inst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( RegShiftedImm . ShiftTy , Imm ) ) ) ;


<s> machine_mode mode , cmp_mode ; bval = operands [ <NUM_LIT> ] ; rval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = operands [ <NUM_LIT> ] ; mod_s = operands [ <NUM_LIT> ] ; mod_f = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case E_DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_THUMB1 ) cmp_mode = E_SImode ;


<s> if ( Res >= <NUM_LIT> ) return ( ( uint64_t ) Res < ( uint64_t ) ( <NUM_LIT> << bits ) ) ? true : false ; else { const int64_t high_bit_set = <NUM_LIT> << <NUM_LIT> ; const uint64_t mask = ( high_bit_set >> ( <NUM_LIT> - bits ) ) ; return ( ( ( uint64_t ) Res & mask ) == mask ) ? true : false ; } } } else if ( myMCExpr -> getKind ( ) == MCExpr :: SymbolRef && isRelocatable ) return true ; else if ( myMCExpr -> getKind ( ) == MCExpr :: Binary || myMCExpr -> getKind ( ) == MCExpr :: Unary ) return true ; }


<s> bool <ISA_LIT>MCExpr :: EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout ) const {

return getSubExpr ( ) -> EvaluateAsRelocatable ( Res , Layout ) ;


<s> continue ; } if ( std :: none_of ( GV . user_begin ( ) , GV . user_end ( ) , [ & ] ( User * U ) { return userRequiresLowering ( UsedList , U ) ; } ) ) { continue ; } LocalVars . push_back ( & GV ) ; }


<s> static bool TableChecked = false ; if ( ! TableChecked ) { for ( unsigned i = <NUM_LIT> ; i != NumEntries - <NUM_LIT> ; ++ i ) assert ( NEONLdStTable [ i ] < NEONLdStTable [ i + <NUM_LIT> ] && <STR_LIT> ) ; TableChecked = true ;


<s> F = MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( llvm :: isKernelFunction ( * F ) ) O << <STR_LIT> ; else { O << <STR_LIT> ; printReturnValStr ( * MF , O ) ; }


<s> for ( i = <NUM_LIT> ; ; ++ i ) { if ( name [ i ] == '\0' ) return false ; if ( name [ i ] == '6' && name [ i + <NUM_LIT> ] == '4' ) return true ;


<s> if ( Vector ) return useHVX ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( Def . isReg ( ) && Def . isDef ( ) ) Defs . insert ( Def . getReg ( ) ) ; }


<s> if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; Binary |= encodeNEONRn ( MI , OpIdx ++ ) ; if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; Binary |= encodeNEONRm ( MI , OpIdx ) ; if ( IsThumb ) Binary = convertNEONDataProcToThumb ( Binary ) ;


<s> const MCOperand & RegOp = MI -> getOperand ( OpNo ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand & AluOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; const unsigned AluCode = AluOp . getImm ( ) ; assert ( OffsetOp . isReg ( ) && RegOp . isReg ( ) && <STR_LIT> ) ; OS << <STR_LIT> ; if ( LPAC :: isPreOp ( AluCode ) ) OS << <STR_LIT> ; OS << <STR_LIT> << getRegisterName ( RegOp . getReg ( ) ) ;

if ( LPAC :: isPostOp ( AluCode ) ) OS << <STR_LIT> ;


<s> <ISA_LIT>VLIWPacketizer ( ) : MachineFunctionPass ( ID ) {


<s> auto & Map = LibcallNameMap -> Map ; auto val = Map . find ( Name ) ;

assert ( val != Map . end ( ) && <STR_LIT> ) ;


<s> auto Predicate = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; auto Libcalls = getFCmpLibcalls ( Predicate , OpSize ) ; if ( Libcalls . empty ( ) ) { assert ( ( Predicate == CmpInst :: FCMP_TRUE || Predicate == CmpInst :: FCMP_FALSE ) && <STR_LIT> ) ; MIRBuilder . buildConstant ( OriginalResult , Predicate == CmpInst :: FCMP_TRUE ? <NUM_LIT> : <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < unsigned , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildConstant ( Zero , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred , ProcessedResult , LibcallResult , Zero ) ; } Results . push_back ( ProcessedResult ) ; } if ( Results . size ( ) != <NUM_LIT> ) { assert ( Results . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MIRBuilder . buildOr ( OriginalResult , Results [ <NUM_LIT> ] , Results [ <NUM_LIT> ] ) ; } break ; } case G_FCONSTANT : { auto AsInteger = MI . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) . bitcastToAPInt ( ) ; MIRBuilder . buildConstant ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , * ConstantInt :: get ( Ctx , AsInteger ) ) ;


<s> if ( isCondCodeLegal ( SwapInvCC , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( False , True ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( SwapInvCC ) ; } } } if ( isHWTrueValue ( True ) && isHWFalseValue ( False ) && ( CompareVT == VT || VT == <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , True , False , CC ) ; } if ( isZero ( LHS ) ) { <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; <STR_LIT> CCSwapped = <STR_LIT> ( CCOpcode ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } else { <STR_LIT> CCInv = <STR_LIT> ( CCOpcode , CompareVT . isInteger ( ) ) ; CCSwapped = <STR_LIT> ( CCInv ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ; } switch ( CCOpcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CCOpcode = <STR_LIT> ( CCOpcode , CompareVT == <STR_LIT> ) ; Temp = True ; True = False ; False = Temp ; break ;


<s> MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; unsigned IgnoreCount = <NUM_LIT> ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else { <ISA_LIT>LowerToMC ( & * MII , MCB , * this ) ; } } }


<s> SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : { if ( auto * ConstOp = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ) { if ( ! ( ConstOp -> hasOneUse ( ) ) ) break ; int64_t Imm = ConstOp -> getSExtValue ( ) ; if ( ! ( - <NUM_LIT> <= Imm && Imm <= - <NUM_LIT> ) && ! ( <NUM_LIT> <= Imm && Imm <= <NUM_LIT> ) ) break ; SDLoc DL ( Node ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; const SDValue ImmOp0 = CurDAG -> getTargetConstant ( Imm - Imm / <NUM_LIT> , DL , VT ) ; const SDValue ImmOp1 = CurDAG -> getTargetConstant ( Imm / <NUM_LIT> , DL , VT ) ; auto * NodeAddi0 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Node -> getOperand ( <NUM_LIT> ) , ImmOp0 ) ; auto * NodeAddi1 = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( NodeAddi0 , <NUM_LIT> ) , ImmOp1 ) ; ReplaceNode ( Node , NodeAddi1 ) ; return ; } break ; } case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) {

SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ;


<s> if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } } return MBB . erase ( MI ) ;


<s> slot = SLOT_CW_TRUNC ; break ; case I387_CW_FLOOR : emit_insn ( gen_andhi3 ( reg , reg , GEN_INT ( ~ <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_FLOOR ; break ; case I387_CW_CEIL : emit_insn ( gen_andhi3 ( reg , reg , GEN_INT ( ~ <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_CEIL ; break ; case I387_CW_MASK_PM : emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_MASK_PM ; break ; default : gcc_unreachable ( ) ;


<s> bool useLoadStackGuardNode ( ) const override {


<s> unsigned R = ( Insn & ( <NUM_LIT> & ~ <NUM_LIT> ) ) >> <NUM_LIT> ; DecodeGPR32RegisterClass ( Inst , R , Address , Dec ) ;

Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( S9 ) ) ) ;


<s> if ( a != NULL_RTX ) emit_move_insn ( cr , gen_rtx_COMPARE ( cmpmode , a , b ) ) ; rtx cmp_rtx = gen_rtx_fmt_ee ( comparison , VOIDmode , cr , const0_rtx ) ; rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , label_ref , pc_rtx ) ; rtx j = emit_jump_insn ( gen_rtx_SET ( pc_rtx , ifelse ) ) ; JUMP_LABEL ( j ) = true_label ;


<s> unsigned LWEVal = ( LWEIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( LWEIdx ) . getImm ( ) ; int ToUntie = - <NUM_LIT> ; if ( TFEVal || LWEVal ) { for ( unsigned i = LWEIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( MI . getOperand ( i ) . isReg ( ) && MI . getOperand ( i ) . isTied ( ) && MI . getOperand ( i ) . isImplicit ( ) ) { assert ( ToUntie == - <NUM_LIT> && <STR_LIT> ) ; ToUntie = i ; MI . untieRegOperand ( ToUntie ) ; } } } unsigned NewOpcode = <STR_LIT> ( Info -> BaseOpcode , <STR_LIT> , Info -> VDataDwords , NewAddrDwords ) ; MI . setDesc ( TII -> get ( NewOpcode ) ) ; MI . getOperand ( VAddr0Idx ) . setReg ( RC -> getRegister ( VgprBase ) ) ; MI . getOperand ( VAddr0Idx ) . setIsUndef ( IsUndef ) ; MI . getOperand ( VAddr0Idx ) . setIsKill ( IsKill ) ; for ( unsigned i = <NUM_LIT> ; i < Info -> VAddrDwords ; ++ i ) MI . RemoveOperand ( VAddr0Idx + <NUM_LIT> ) ; if ( ToUntie >= <NUM_LIT> ) { MI . tieOperands ( <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vdata ) , ToUntie - ( Info -> VAddrDwords - <NUM_LIT> ) ) ;


<s> EVT MemVT = St -> getMemoryVT ( ) ; assert ( St -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( MemVT . isVector ( ) && MemVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Op = St -> getValue ( ) ; MVT OpVT = Op . getValueType ( ) . getSimpleVT ( ) ; unsigned NumElts = OpVT . getVectorNumElements ( ) ; if ( ( Subtarget . hasVLX ( ) && Subtarget . hasBWI ( ) && Subtarget . hasDQI ( ) ) || NumElts == <NUM_LIT> ) { Op = DAG . getNode ( <STR_LIT> , dl , MemVT , Op ) ; if ( MemVT . getSizeInBits ( ) < <NUM_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Op , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , Op , St -> getBasePtr ( ) , St -> getMemOperand ( ) ) ; } if ( NumElts <= <NUM_LIT> ) { if ( NumElts < <NUM_LIT> ) { MVT ExtVT = <STR_LIT> ( OpVT . getScalarType ( ) , <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , ExtVT , DAG . getUNDEF ( ExtVT ) , Op , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; return DAG . getStore ( St -> getChain ( ) , dl , Op , St -> getBasePtr ( ) , St -> getMemOperand ( ) ) ; } assert ( OpVT == <STR_LIT> && <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; SDValue BasePtr = St -> getBasePtr ( ) ; SDValue StLo = DAG . getStore ( St -> getChain ( ) , dl , Lo , BasePtr , St -> getMemOperand ( ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; SDValue BasePtrHi = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( <NUM_LIT> , dl , BasePtr . getValueType ( ) ) ) ; SDValue StHi = DAG . getStore ( St -> getChain ( ) , dl , Hi , BasePtrHi , St -> getMemOperand ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StLo , StHi ) ;


<s> bool OptimizeLEAPass :: chooseBestLEA ( const SmallVectorImpl < MachineInstr * > & List , const MachineInstr & MI , MachineInstr * & LEA , int64_t & AddrDispShift , int & Dist ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags , MI . getOpcode ( ) ) + <STR_LIT> ( Desc ) ; LEA = nullptr ; for ( auto DefMI : List ) { int64_t AddrDispShiftTemp = <NUM_LIT> ; if ( ! isSimilarMemOp ( MI , MemOpNo , * DefMI , <NUM_LIT> , AddrDispShiftTemp ) ) continue ; if ( ! isInt < <NUM_LIT> > ( AddrDispShiftTemp ) ) continue ; if ( TII -> getRegClass ( Desc , MemOpNo + <STR_LIT> , TRI , * MF ) != MRI -> getRegClass ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; int DistTemp = calcInstrDist ( * DefMI , MI ) ; assert ( DistTemp != <NUM_LIT> && <STR_LIT> ) ; if ( DistTemp > <NUM_LIT> || LEA == nullptr ) { if ( LEA != nullptr && ! isInt < <NUM_LIT> > ( AddrDispShiftTemp ) && isInt < <NUM_LIT> > ( AddrDispShift ) ) continue ; LEA = DefMI ; AddrDispShift = AddrDispShiftTemp ; Dist = DistTemp ; } if ( DistTemp < <NUM_LIT> ) break ; }


const static MCFixupKindInfo InfosBE [ <STR_LIT> ] = {


<s> int j ; for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( csky_label_mentioned_p ( XVECEXP ( x , i , j ) ) ) return true ; }

else if ( fmt [ i ] == 'e' && csky_label_mentioned_p ( XEXP ( x , i ) ) ) return true ;


<s> if ( GET_CODE ( high ) != HIGH || GET_CODE ( XEXP ( high , <NUM_LIT> ) ) != CONST ) return false ; unspec = XEXP ( XEXP ( high , <NUM_LIT> ) , <NUM_LIT> ) ; return ( GET_CODE ( unspec ) == UNSPEC && XINT ( unspec , <NUM_LIT> ) == UNSPEC_PCREL_SYM ) ;


<s> MachineBasicBlock :: iterator <ISA_LIT>LoadStoreOptimizer :: mergeBufferLoadPair ( CombineInfo & CI ) { MachineBasicBlock * MBB = CI . I -> getParent ( ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; const unsigned Opcode = getNewOpcode ( CI ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI ) ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; unsigned MergedOffset = std :: min ( CI . Offset0 , CI . Offset1 ) ; auto MIB = BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) , DestReg ) ; const unsigned Regs = getRegs ( Opcode ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC0 ) . addImm ( CI . SLC0 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ;

const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ;


<s> if ( const ICmpInst * ICmp = dyn_cast < ICmpInst > ( V ) ) if ( const ConstantInt * C = dyn_cast < ConstantInt > ( ICmp -> getOperand ( <NUM_LIT> ) ) ) if ( ICmp -> isEquality ( ) && C -> isZero ( ) && C -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { Not = ICmp -> isTrueWhenEqual ( ) ; return getRegForValue ( ICmp -> getOperand ( <NUM_LIT> ) ) ; } if ( BinaryOperator :: isNot ( V ) ) { Not = true ; return getRegForValue ( BinaryOperator :: getNotArgument ( V ) ) ; } Not = false ; unsigned Reg = getRegForValue ( V ) ; if ( Reg == <NUM_LIT> ) return <NUM_LIT> ; return maskI1Value ( Reg , V ) ;


<s> tree field ; if ( ! packed_p ) for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && DECL_PACKED ( field ) ) { packed_p = true ; break ; } } for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; if ( DECL_SIZE ( field ) != <NUM_LIT> ) { if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( tree_fits_uhwi_p ( bit_position ( field ) ) ) bitpos += int_bit_position ( field ) ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) function_arg_record_value_2 ( TREE_TYPE ( field ) , bitpos , parms , packed_p ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU && parms -> named && ! packed_p ) { int this_slotno = parms -> slotno + bitpos / BITS_PER_WORD ; int regno , nregs , pos ;

machine_mode mode = DECL_MODE ( field ) ;


<s> RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ;


<s> unsigned LoopSize = <NUM_LIT> ; for ( const MachineBasicBlock * MBB : ML -> blocks ( ) ) { if ( MBB != Header ) LoopSize += ( <NUM_LIT> << MBB -> getAlignment ( ) ) / <NUM_LIT> ; for ( const MachineInstr & MI : * MBB ) { LoopSize += TII -> getInstSizeInBytes ( MI ) ; if ( LoopSize > <NUM_LIT> ) return PrefAlign ; } } if ( LoopSize <= <NUM_LIT> ) return PrefAlign ; if ( LoopSize <= <NUM_LIT> ) return CacheLineAlign ; for ( MachineLoop * P = ML -> getParentLoop ( ) ; P ; P = P -> getParentLoop ( ) ) { if ( MachineBasicBlock * Exit = P -> getExitBlock ( ) ) { auto I = Exit -> getFirstNonDebugInstr ( ) ; if ( I != Exit -> end ( ) && I -> getOpcode ( ) == <STR_LIT> ) return CacheLineAlign ; } } MachineBasicBlock * Pre = ML -> getLoopPreheader ( ) ; MachineBasicBlock * Exit = ML -> getExitBlock ( ) ; if ( Pre && Exit ) { BuildMI ( * Pre , Pre -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( * Exit , Exit -> getFirstNonDebugInstr ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> static __inline vec_int4 spu_xor ( vec_int4 a , signed int b ) { return ( ( vec_int4 ) ( si_xori ( ( qword ) ( a ) , ( unsigned int ) ( b ) ) ) ) ;


<s> CrashPseudoSourceValue ( const TargetMachine & TM ) : PseudoSourceValue ( TargetCustom , TM ) {


<s> else { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; operands [ <NUM_LIT> ] = GEN_INT ( sp_adjust ) ; } else { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> ) ; } } snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; } else { int pop_en4_only_p = <NUM_LIT> ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , rb_callee_saved ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_callee_saved ) ; if ( ! cfun -> machine -> fp_size && ! cfun -> machine -> gp_size && ! cfun -> machine -> lp_size && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM ) { return <STR_LIT> ; } else { if ( REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM ) pop_en4_only_p = <NUM_LIT> ; snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , pop_en4_only_p ? <STR_LIT> : <STR_LIT> , cfun -> machine -> fp_size ? <STR_LIT> : <STR_LIT> , cfun -> machine -> gp_size ? <STR_LIT> : <STR_LIT> , cfun -> machine -> lp_size ? <STR_LIT> : <STR_LIT> ) ; } }

output_asm_insn ( pattern , operands ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const {

return create<ISA_LIT>ELFObjectWriter ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ;


<s> } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } return false ; case IS_VGPR : case IS_SGPR : case IS_AGPR : case IS_TTMP : if ( Reg1 != Reg + RegWidth ) {


<s> bool isMM16AsmReg ( ) const { if ( ! ( isRegIdx ( ) && RegIdx . Kind ) ) return false ;

return ( ( RegIdx . Index >= <NUM_LIT> && RegIdx . Index <= <NUM_LIT> ) || RegIdx . Index == <NUM_LIT> || RegIdx . Index == <NUM_LIT> ) ;


<s> SDValue InHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InLo , InHi ) ;


<s> assert ( isIntN ( Size * <NUM_LIT> + <NUM_LIT> , Value ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Data [ Fixup . getOffset ( ) + i ] = uint8_t ( Value >> ( i * <NUM_LIT> ) ) ;


<s> static inline bool isZeroLengthArray ( const Type * Ty ) { const ArrayType * AT = dyn_cast_or_null < ArrayType > ( Ty ) ; return AT && ( AT -> getNumElements ( ) == <NUM_LIT> ) ;


<s> case PROCESSOR_700 : return <NUM_LIT> ; case PROCESSOR_7100 : return <NUM_LIT> ; case PROCESSOR_7100LC : return <NUM_LIT> ; case PROCESSOR_7200 : return <NUM_LIT> ; case PROCESSOR_7300 : return <NUM_LIT> ; case PROCESSOR_8000 : return <NUM_LIT> ; default : gcc_unreachable ( ) ;


<s> if ( GET_CODE ( disp ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( disp , <NUM_LIT> ) ) ) return false ; disp = XEXP ( disp , <NUM_LIT> ) ; saw_plus = true ; } if ( TARGET_MACHO && darwin_local_data_pic ( disp ) ) return true ; if ( GET_CODE ( disp ) != UNSPEC ) return false ; switch ( XINT ( disp , <NUM_LIT> ) ) { case UNSPEC_GOT : if ( saw_plus ) return false ; return ( GET_CODE ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF || GET_CODE ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ) == LABEL_REF ) ; case UNSPEC_GOTOFF : if ( ( GET_CODE ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF || GET_CODE ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ) == LABEL_REF ) && ! TARGET_64BIT ) return ! TARGET_PECOFF && gotoff_operand ( XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) , Pmode ) ; return false ; case UNSPEC_GOTTPOFF : case UNSPEC_GOTNTPOFF : case UNSPEC_INDNTPOFF : if ( saw_plus ) return false ; disp = XVECEXP ( disp , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( disp ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( disp ) == TLS_MODEL_INITIAL_EXEC ) ; case UNSPEC_NTPOFF :


<s> for ( auto * B : L -> blocks ( ) ) for ( auto & I : * B ) if ( Ignored . count ( & I ) == <NUM_LIT> && isModOrRefSet ( intersectModRef ( AA . getModRefInfo ( & I , StoreLoc ) , Access ) ) ) return true ; return false ;


<s> ASM_OUTPUT_LABEL ( asm_out_file , label ) ; } if ( ! TARGET_ZARCH ) fputs ( <STR_LIT> , asm_out_file ) ; if ( REG_P ( execute_target ) ) fprintf ( asm_out_file , <STR_LIT> , REGNO ( execute_target ) ) ; else output_asm_insn ( <STR_LIT> , & execute_target ) ; if ( ! TARGET_ZARCH ) fputs ( <STR_LIT> , asm_out_file ) ;


<s> bool IsNaCl = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( IsNaCl ) { if ( CallsEHReturn ) return CSR_NaCl64EHRet_SaveList ; return CSR_NaCl64_SaveList ; } if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; }

if ( CallsEHReturn ) return CSR_32EHRet_SaveList ;


<s> OPCODE ( CALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( CMP ) ; OPCODE ( UCMP ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ;


<s> } else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) { ArgValue = DAG . getBitcast ( VA . getValVT ( ) , ArgValue ) ; } if ( VA . isExtInLoc ( ) ) { ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; ArgValue = LowerMemArgument ( Chain , CCID , Ins , DL , DAG , VA , MFI , i ) ; } if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) ArgValue = DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ; InVals . push_back ( ArgValue ) ; } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { if ( CCID == CallingConv :: Swift ) continue ; if ( Ins [ i ] . Flags . isSRet ( ) ) { unsigned Reg = MMFI -> getSRetReturnReg ( ) ; if ( ! Reg ) { MVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( PtrTy ) ) ; MMFI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ i ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; break ;


<s> rtx_insn * jump = find_cond_jump ( NEXT_INSN ( insn ) ) ; rtx set = jump ? single_set ( jump ) : NULL_RTX ; if ( set == NULL_RTX ) return ; cond = XEXP ( SET_SRC ( set ) , <NUM_LIT> ) ; } * op0 = * op1 ; * op1 = tmp ;

PUT_CODE ( cond , swap_condition ( GET_CODE ( cond ) ) ) ;


return ( ( SmVersion >= <NUM_LIT> ) && ( SmVersion < <NUM_LIT> ) ) ;


<s> static inline bool s390_preserve_gpr_arg_in_range_p ( int first , int last ) {

int num_arg_regs = MIN ( crtl -> args . info . gprs + cfun -> va_list_gpr_size , GP_ARG_NUM_REG ) ;


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;

else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> return __builtin_mve_vhaddq_m_n_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a , __b , __p ) ;


<s> int64_t RHSC = ( int64_t ) RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { if ( LHSDef -> getOpcode ( ) == TargetOpcode :: G_FRAME_INDEX ) return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHSDef -> getOperand ( <NUM_LIT> ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( RHSC >> Scale ) ; } , } } ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( RHSC >> Scale ) ; } , } } ; } } } if ( selectAddrModeUnscaled ( Root , Size ) . hasValue ( ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( Root ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , } } ;


<s> return __builtin_mve_vminavq_sv8hi ( __a , __b ) ;


<s> AAPointerInfo :: OffsetAndSize OAS ( Pos , <NUM_LIT> ) ; return funcRetrievesImplicitKernelArg ( A , OAS ) ;


<s> int64_t FullValue = fullValue ( Disassembler , MI , tmp ) ; assert ( FullValue >= <NUM_LIT> && <STR_LIT> ) ; <ISA_LIT>MCInstrInfo :: addConstant ( MI , FullValue , Disassembler . getContext ( ) ) ; return MCDisassembler :: Success ;


<s> if ( ! ST . hasMAIInsts ( ) ) return <NUM_LIT> ; int WaitStatesNeeded = <NUM_LIT> ; auto IsAccVgprReadFn = [ ] ( MachineInstr * MI ) { return MI -> getOpcode ( ) == <STR_LIT> ; } ; for ( const MachineOperand & Op : MI -> explicit_uses ( ) ) { if ( ! Op . isReg ( ) || ! TRI . isVGPR ( MF . getRegInfo ( ) , Op . getReg ( ) ) ) continue ; Register Reg = Op . getReg ( ) ; const int AccVgprReadLdStWaitStates = <NUM_LIT> ;


<s> if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; if ( SDValue R = combinePTESTCC ( EFLAGS , CC , DAG , Subtarget ) ) return R ;

return combineSetCCAtomicArith ( EFLAGS , CC , DAG , Subtarget ) ;


<s> return Ref . size ( ) >= sizeof ( Item ) && Ref . size ( ) >= getItemPadSize ( ) ;


<s> const Triple & getTargetTriple ( ) const {


<s> if ( VT . getVectorNumElements ( ) == <NUM_LIT> ) return ScalarizeVectorStore ( Op , DAG ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ;

const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ;


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; const TargetMachine & TM = DAG . getTarget ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) {

return DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ;


<s> if ( parseImmExpr ( Offset ) ) return true ;

getTargetStreamer ( ) . emitARM64WinCFISaveFPLRX ( Offset ) ;


<s> assert ( Fixup . getKind ( ) == FK_PCRel_4 ) ;

* Dst = ( Value - <NUM_LIT> ) / <NUM_LIT> ;


<s> case TLS_MODEL_LOCAL_DYNAMIC : insns = csky_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , addend ) ; return gen_rtx_PLUS ( Pmode , dest , addend ) ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( tls_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_TLS_LABEL ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32 ) , label ) , UNSPEC_TLS ) ; tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( reg , unspec ) ;


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; return false ; } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << Reg << <STR_LIT> << CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) << <STR_LIT> ) ;


<s> switch ( Alignment ) { case <NUM_LIT> : LdOpc = <STR_LIT> ; StOpc = <STR_LIT> ; break ; case <NUM_LIT> : LdOpc = <STR_LIT> ; StOpc = <STR_LIT> ; break ; case <NUM_LIT> : LdOpc = <STR_LIT> ; StOpc = <STR_LIT> ; break ; case <NUM_LIT> : LdOpc = <STR_LIT> ; StOpc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned IterationNum = CopyLen >> Log2_64 ( Alignment ) ; for ( unsigned I = <NUM_LIT> ; I < IterationNum ; ++ I ) { BuildMI ( * BB , MI , dl , get ( LdOpc ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( SrcReg ) . addImm ( I * Alignment ) ; BuildMI ( * BB , MI , dl , get ( StOpc ) ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( DstReg ) . addImm ( I * Alignment ) ; } unsigned BytesLeft = CopyLen & ( Alignment - <NUM_LIT> ) ; unsigned Offset = IterationNum * Alignment ; bool Hanging4Byte = BytesLeft & <NUM_LIT> ; bool Hanging2Byte = BytesLeft & <NUM_LIT> ; bool Hanging1Byte = BytesLeft & <NUM_LIT> ; if ( Hanging4Byte ) { BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( SrcReg ) . addImm ( Offset ) ; BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( DstReg ) . addImm ( Offset ) ; Offset += <NUM_LIT> ; } if ( Hanging2Byte ) { BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( SrcReg ) . addImm ( Offset ) ; BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( DstReg ) . addImm ( Offset ) ; Offset += <NUM_LIT> ; } if ( Hanging1Byte ) { BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( SrcReg ) . addImm ( Offset ) ;


<s> if ( Cost != - <NUM_LIT> ) return Cost ;

return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ;


<s> void <ISA_LIT>AsmPrinter :: emitFunctionBodyEnd ( ) {


<s> static unsigned HOST_WIDE_INT compute_current_alignment ( unsigned HOST_WIDE_INT base_align , unsigned HOST_WIDE_INT offset ) { if ( offset == <NUM_LIT> ) return base_align ; return min ( base_align , offset & - offset ) ;


<s> machine_mode memory_vector_mode ( const function_instance & fi ) const override { poly_uint64 nunits = GET_MODE_NUNITS ( fi . vector_mode ( <NUM_LIT> ) ) ;

return aarch64_sve_data_mode ( m_to_mode , nunits ) . require ( ) ;


<s> static bool DisassembleThumb1AddSPi ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO B ) { assert ( Opcode == <STR_LIT> && <STR_LIT> ) ; const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && ( OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && ! OpInfo [ <NUM_LIT> ] . isPredicate ( ) && ! OpInfo [ <NUM_LIT> ] . isOptionalDef ( ) ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRt ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ;

MI . addOperand ( MCOperand :: CreateImm ( getT1Imm8 ( insn ) ) ) ;


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override {


<s> inline SDValue getI32Imm ( unsigned Imm ) {

return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveOptionNoPIC ( ) { OS << <STR_LIT> ;


<s> const MCSymbolRefExpr * SymRef ; if ( getSymRef ( ErrorLoc , Inst , SymRef ) ) return true ; const auto * WasmSym = cast < MCSymbolWasm > ( & SymRef -> getSymbol ( ) ) ; const auto * Sig = WasmSym -> getSignature ( ) ; if ( ! Sig || WasmSym -> getType ( ) != <STR_LIT> ) return typeError ( ErrorLoc , StringRef ( <STR_LIT> ) + WasmSym -> getName ( ) + <STR_LIT> ) ; Stack . insert ( Stack . end ( ) , Sig -> Params . begin ( ) , Sig -> Params . end ( ) ) ; } else if ( Name == <STR_LIT> ) { auto VT = static_cast < <STR_LIT> > ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; Stack . push_back ( VT ) ; } else { auto RegOpc = <STR_LIT> ( Opc ) ; assert ( RegOpc != - <NUM_LIT> && <STR_LIT> ) ; const auto & II = MII . get ( RegOpc ) ; for ( unsigned I = II . getNumOperands ( ) ; I > II . getNumDefs ( ) ; I -- ) { const auto & Op = II . OpInfo [ I - <NUM_LIT> ] ; if ( Op . OperandType == MCOI :: OPERAND_REGISTER ) { auto VT = <STR_LIT> ( Op . RegClass ) ; if ( popType ( ErrorLoc , VT ) ) return true ; } } for ( unsigned I = <NUM_LIT> ; I < II . getNumDefs ( ) ; I ++ ) { const auto & Op = II . OpInfo [ I ] ; assert ( Op . OperandType == MCOI :: OPERAND_REGISTER && <STR_LIT> ) ; auto VT = <STR_LIT> ( Op . RegClass ) ;


<s> else if ( GET_CODE ( src ) == PLUS || GET_CODE ( src ) == MINUS || GET_CODE ( src ) == IOR || GET_CODE ( src ) == XOR || GET_CODE ( src ) == AND ) { gain += ix86_cost -> add ; if ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == NOT && ! TARGET_BMI ) gain += <NUM_LIT> * ix86_cost -> add ; if ( CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) gain -= vector_const_cost ( XEXP ( src , <NUM_LIT> ) ) ; if ( CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) gain -= vector_const_cost ( XEXP ( src , <NUM_LIT> ) ) ; } else if ( GET_CODE ( src ) == NEG || GET_CODE ( src ) == NOT ) gain += ix86_cost -> add - COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( GET_CODE ( src ) == COMPARE ) { } else if ( CONST_INT_P ( src ) ) { if ( REG_P ( dst ) ) gain += COSTS_N_INSNS ( <NUM_LIT> ) ;

else if ( MEM_P ( dst ) ) gain += <NUM_LIT> * ix86_cost -> int_store [ <NUM_LIT> ] - ix86_cost -> sse_store [ <NUM_LIT> ] ;


<s> LLVM_DUMP_METHOD void GCNIterativeScheduler :: printSchedRP ( raw_ostream & OS , const GCNRegPressure & Before , const GCNRegPressure & After ) const { const auto & ST = MF . getSubtarget < GCNSubtarget > ( ) ;


<s> if ( is<ISA_LIT> ( STI ) || isCI ( STI ) || isVI ( STI ) ) return ID_SYMBOLIC_FIRST_GFX9_ ; else if ( isGFX9 ( STI ) ) return ID_SYMBOLIC_FIRST_GFX10_ ;


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , PRI ( g . getPRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , LiveMap ( g . getPRI ( ) ) , Empty ( ) , NoRegs ( g . getPRI ( ) ) , Trace ( false ) {


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Val ) ) return C -> isAllOnesValue ( ) ;


<s> if ( ! CalleeFn ) return <NUM_LIT> ; assert ( CalleeFn -> hasStructRetAttr ( ) && <STR_LIT> ) ; PointerType * Ty = cast < PointerType > ( CalleeFn -> arg_begin ( ) -> getType ( ) ) ; Type * ElementTy = Ty -> getElementType ( ) ; return getDataLayout ( ) -> getTypeAllocSize ( ElementTy ) ;


<s> Emitter ( TargetMachine & tm , CodeEmitter & mce , const <ISA_LIT>InstrInfo & ii , const TargetData & td ) : MachineFunctionPass ( & ID ) , JTI ( <NUM_LIT> ) , II ( & ii ) , TD ( & td ) , TM ( tm ) , MCE ( mce ) , MCPEs ( <NUM_LIT> ) , MJTEs ( <NUM_LIT> ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> static void iq2000_setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { unsigned int iq2000_off = ! cum -> last_arg_fp ; unsigned int iq2000_fp_off = cum -> last_arg_fp ; if ( ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) ) { int iq2000_save_gp_regs = MAX_ARGS_IN_REGISTERS - cum -> arg_words - iq2000_off ; int iq2000_save_fp_regs = ( MAX_ARGS_IN_REGISTERS - cum -> fp_arg_words - iq2000_fp_off ) ; if ( iq2000_save_gp_regs < <NUM_LIT> ) iq2000_save_gp_regs = <NUM_LIT> ; if ( iq2000_save_fp_regs < <NUM_LIT> ) iq2000_save_fp_regs = <NUM_LIT> ; * pretend_size = ( ( iq2000_save_gp_regs * UNITS_PER_WORD ) + ( iq2000_save_fp_regs * UNITS_PER_FPREG ) ) ; if ( ! ( no_rtl ) ) { if ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) { rtx ptr , mem ; ptr = plus_constant ( virtual_incoming_args_rtx , - ( iq2000_save_gp_regs * UNITS_PER_WORD ) ) ;


<s> static SDValue emitMemMem ( SelectionDAG & DAG , SDLoc DL , unsigned Sequence , unsigned Loop , SDValue Chain , SDValue Dst , SDValue Src , uint64_t Size ) { EVT PtrVT = Src . getValueType ( ) ; if ( Size > <NUM_LIT> * <NUM_LIT> ) return DAG . getNode ( Loop , DL , <STR_LIT> , Chain , Dst , Src , DAG . getConstant ( Size , PtrVT ) , DAG . getConstant ( Size / <NUM_LIT> , PtrVT ) ) ;

return DAG . getNode ( Sequence , DL , <STR_LIT> , Chain , Dst , Src , DAG . getConstant ( Size , PtrVT ) ) ;


<s> if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = InVec . getValueType ( ) . getVectorNumElements ( ) ; unsigned i = <NUM_LIT> ; for ( ; i != NumElts ; ++ i ) { SDValue Arg = InVec . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ; BaseShAmt = Arg ; break ; } } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { unsigned SplatIdx = cast < ShuffleVectorSDNode > ( ShAmtOp ) -> getSplatIndex ( ) ; if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( BaseShAmt . getNode ( ) == <NUM_LIT> ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( EltVT ) && ! DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; BaseShAmt = DAG . getNode ( <STR_LIT> , DL , EltVT , ShAmtOp , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } } else return SDValue ( ) ; if ( EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BaseShAmt ) ;

SDValue ValOp = N -> getOperand ( <NUM_LIT> ) ;


<s> bool LoadFirstElt = ! isNullConstant ( MaskBV -> getOperand ( <NUM_LIT> ) ) ; bool LoadLastElt = ! isNullConstant ( MaskBV -> getOperand ( NumElts - <NUM_LIT> ) ) ; if ( LoadFirstElt && LoadLastElt ) { SDValue VecLd = DAG . getLoad ( VT , DL , ML -> getChain ( ) , ML -> getBasePtr ( ) , ML -> getMemOperand ( ) ) ; SDValue Blend = DAG . getSelect ( DL , VT , ML -> getMask ( ) , VecLd , ML -> getPassThru ( ) ) ; return DCI . CombineTo ( ML , Blend , VecLd . getValue ( <NUM_LIT> ) , true ) ; } if ( ML -> getPassThru ( ) . isUndef ( ) ) return SDValue ( ) ; SDValue NewML = DAG . getMaskedLoad ( VT , DL , ML -> getChain ( ) , ML -> getBasePtr ( ) , ML -> getMask ( ) , DAG . getUNDEF ( VT ) , ML -> getMemoryVT ( ) , ML -> getMemOperand ( ) , ML -> getExtensionType ( ) ) ; SDValue Blend = DAG . getSelect ( DL , VT , ML -> getMask ( ) , NewML , ML -> getPassThru ( ) ) ;

return DCI . CombineTo ( ML , Blend , NewML . getValue ( <NUM_LIT> ) , true ) ;


<s> if ( precision == FLOAT_TYPE_SIZE ) return true ; if ( precision == DOUBLE_TYPE_SIZE ) return true ; if ( precision == LONG_DOUBLE_TYPE_SIZE ) return true ; return false ; default : gcc_unreachable ( ) ; }


<s> EVT ValVT = VA . getValVT ( ) ; SDValue Val ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , ValVT , Val ) ; break ; }


<s> static inline const MachineInstrBuilder & addOffset ( const MachineInstrBuilder & MIB , int Offset ) { return MIB . addImm ( Offset ) ;


<s> OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleRIPRel ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) { PICBase = <STR_LIT> ; } unsigned CPI = MCP . getConstantPoolIndex ( CFP , Align ) ; unsigned ResultReg = createResultReg ( RC ) ; if ( CM == CodeModel :: Large ) { unsigned AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ;


<s> vst1_s32 ( int32_t * a , int32x2_t b ) { __builtin_aarch64_st1v2si ( ( __builtin_aarch64_simd_si * ) a , b ) ;


<s> SDValue SplatValCN = DAG . getConstant ( SplatVal , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatValCN , SplatValCN ) ; } SDValue LO32 ; SDValue HI32 ; SmallVector < SDValue , <NUM_LIT> > ShufBytes ; SDValue Result ; if ( ! lower_special ) { SDValue LO32C = DAG . getConstant ( lower , <STR_LIT> ) ; LO32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LO32C , LO32C , LO32C , LO32C ) ) ; } if ( ! upper_special ) { SDValue HI32C = DAG . getConstant ( upper , <STR_LIT> ) ; HI32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HI32C , HI32C , HI32C , HI32C ) ) ; } if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t val = <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { SDValue V ; bool process_upper , process_lower ; val <<= <NUM_LIT> ; process_upper = ( upper_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ; process_lower = ( lower_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ; if ( process_upper || process_lower ) { if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= <NUM_LIT> ; else if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= <NUM_LIT> ; else if ( ( process_upper && upper == <NUM_LIT> ) || ( process_lower && lower == <NUM_LIT> ) ) val |= ( j == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } else val |= i * <NUM_LIT> + j + ( ( i & <NUM_LIT> ) * <NUM_LIT> ) ; } ShufBytes . push_back ( DAG . getConstant ( val , <STR_LIT> ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isSExtCheaperThanZExt ( EVT SrcVT , EVT DstVT ) const {

return Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ;


<s> if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ;

MachineFunction & MF = DAG . getMachineFunction ( ) ;


initialize<ISA_LIT>SExtWRemovalPass ( * PR ) ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_SecRel_4 ) ) ; else if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_SecRel_8 ) ) ; else Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , FK_PCRel_2 ) ) ; return <NUM_LIT> ;


<s> if ( TheTriple . getArch ( ) == Triple :: mips || TheTriple . getArch ( ) == Triple :: mipsel ) CPU = <STR_LIT> ; else CPU = <STR_LIT> ;


<s> if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; return S ;


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>WinCOFFObjectWriter ( bool Is64Bit ) { return llvm :: make_unique < <ISA_LIT>WinCOFFObjectWriter > ( Is64Bit ) ;


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) ) return true ;

if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;


<s> return true ; } if ( BaseReg == <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( BaseReg != <NUM_LIT> && IndexReg != <NUM_LIT> ) { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || IndexReg == <STR_LIT> ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || IndexReg == <STR_LIT> ) ) { ErrMsg = <STR_LIT> ; return true ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) { ErrMsg = <STR_LIT> ;


<s> } Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: Address P = pReloc . place ( ) ; if ( pReloc . symInfo ( ) -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) S = helper_get_PLT_address ( * pReloc . symInfo ( ) , pParent ) ;


<s> assert ( cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { SDValue GotAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , OpFlags ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , GotAddr ) ; } if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { assert ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small && <STR_LIT> ) ; SDValue Hi = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi ) ; unsigned char LoFlags = <STR_LIT> | <STR_LIT> ; SDValue Lo = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , LoFlags ) ; SDValue PoolAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , ADRP , Lo ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , DL , PtrVT ) ) ; return GlobalAddr ; } if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { const unsigned char MO_NC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | MO_NC ) ) ; } else { SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , OpFlags | <STR_LIT> ) ;

unsigned char LoFlags = OpFlags | <STR_LIT> | <STR_LIT> ;


<s> LLVMContext & Ctx = F . getContext ( ) ; Type * I8 = Type :: getInt8Ty ( Ctx ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { Type :: getInt8PtrTy ( Ctx ) , I8 , Arg . getType ( ) } , false ) ; Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( GetArgumentSymbolName ( Arg ) , FnType ) ; Value * ArgName = CreateStringPtr ( BB , Arg . getName ( ) ) ;

Value * Args [ ] = { ArgName , ConstantInt :: get ( I8 , Arg . getArgNo ( ) ) , & Arg } ;


<s> MachineInstr & Tail = * MRI -> use_begin ( DestReg ) -> getParent ( ) ; switch ( Tail . getOpcode ( ) ) { default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; return false ; case <STR_LIT> : { int64_t Offset = Tail . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } case <STR_LIT> : { int64_t Offset ; if ( ! matchLargeOffset ( Tail , DestReg , Offset ) ) return false ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstructionSelector :: selectInsertVal ( Register ResVReg , const <ISA_LIT>Type * ResType , MachineInstr & I ) const { MachineBasicBlock & BB = * I . getParent ( ) ;

auto MIB = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> return makeArrayRef ( VarInitAddresses ) ;


<s> <ISA_LIT>Subtarget ( TT , GPU , FS , TM ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , TLInfo ( TM , * this ) , GISel ( ) {


<s> MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ;

return findScratchRegister ( TmpMBB , true , nullptr ) ;


aarch64_override_options_after_change_1 ( opts ) ;


<s> static std :: pair < bool , unsigned > getReversedCmp ( unsigned Op ) { switch ( Op ) { case <STR_LIT> : return std :: pair < bool , unsigned > ( true , <STR_LIT> ) ; case <STR_LIT> : return std :: pair < bool , unsigned > ( true , <STR_LIT> ) ; default : return std :: pair < bool , unsigned > ( false , <NUM_LIT> ) ; }


return ( __m512i ) __builtin_ia32_loaddqusi512_mask ( ( const __v16si * ) __P , ( __v16si ) _mm512_setzero_si512 ( ) , ( __mmask16 ) __U ) ;


<s> setArgFlags ( CurArgInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( CurArgInfo , <NUM_LIT> , RetInfos , OrigArgIndices ) ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , RetInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ;


<s> else return false ; } if ( GET_CODE ( pat ) == PARALLEL ) { int i ;

for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) if ( is_load_insn1 ( XVECEXP ( pat , <NUM_LIT> , i ) , load_mem ) ) return true ;


<s> assert ( ( size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> ) && <STR_LIT> ) ;

unsigned index_align = insn >> <NUM_LIT> & <NUM_LIT> ;


<s> bool isRegPair ( ) const { return Kind == k_RegPair && RegIdx . Index <= <NUM_LIT> ;


<s> assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ; if ( ! UseMaskForCond && ! UseMaskForGaps && Factor <= TLI -> getMaxSupportedInterleaveFactor ( ) ) { unsigned NumElts = VecTy -> getVectorNumElements ( ) ; auto * SubVecTy = VectorType :: get ( VecTy -> getScalarType ( ) , NumElts / Factor ) ; if ( NumElts % Factor == <NUM_LIT> && TLI -> isLegalInterleavedAccessType ( SubVecTy , DL ) ) return Factor * TLI -> getNumInterleavedAccesses ( SubVecTy , DL ) ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ;


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ;

if ( MO . isImm ( ) ) return <ISA_LIT>CondCodeToVal ( static_cast < <STR_LIT> > ( getMachineOpValue ( MI , MO , Fixups , STI ) ) ) ;


<s> continue ; } for ( auto UI = MRI -> use_begin ( Last . getOperand ( <NUM_LIT> ) . getReg ( ) ) , UE = MRI -> use_end ( ) ; UI != UE ; ) { MachineOperand & MO = * UI ++ ; MachineInstr & MI = * MO . getParent ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) + <STR_LIT> ( Desc ) ; MO . setReg ( First . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineOperand & Op = MI . getOperand ( MemOpNo + <STR_LIT> ) ; if ( Op . isImm ( ) ) Op . setImm ( Op . getImm ( ) + AddrDispShift ) ; else if ( ! Op . isJTI ( ) ) Op . setOffset ( Op . getOffset ( ) + AddrDispShift ) ; } MRI -> clearKillFlags ( First . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ++ NumRedundantLEAs ; DEBUG ( dbgs ( ) << <STR_LIT> ; Last . dump ( ) ; ) ; assert ( MRI -> use_empty ( Last . getOperand ( <NUM_LIT> ) . getReg ( ) ) && <STR_LIT> ) ; Last . eraseFromParent ( ) ; I2 = List . erase ( I2 ) ; Changed = true ; } ++ I1 ; } } return Changed ;


<s> case <STR_LIT> : { if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; int Shift = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( ( Shift == <NUM_LIT> || Shift == <NUM_LIT> ) && <STR_LIT> ) ; Offset = Sign * ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) << Shift ) ; } } return RegImmPair { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Offset } ;


<s> for ( const ArgT & Arg : Args ) { TotalBytes += Arg . VT . getStoreSize ( ) ; } return TotalBytes ;


<s> if ( Size == <NUM_LIT> && Dst . getID ( ) == <STR_LIT> && Src . getID ( ) == <STR_LIT> ) return std :: numeric_limits < unsigned > :: max ( ) ; return RegisterBankInfo :: copyCost ( Dst , Src , Size ) ;


<s> void <ISA_LIT>OffsetAllocator :: EnterScope ( MachineBasicBlock * MBB ) {

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << '\n' ) ;


<s> CCAssignFn * <ISA_LIT>CallLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool IsVarArg ) const {


<s> if ( GET_CODE ( addr ) != UNSPEC || XVECLEN ( addr , <NUM_LIT> ) != <NUM_LIT> ) return false ;

if ( XINT ( addr , <NUM_LIT> ) != ARC_UNSPEC_GOT && XINT ( addr , <NUM_LIT> ) != ARC_UNSPEC_GOTOFF && XINT ( addr , <NUM_LIT> ) != ARC_UNSPEC_GOTOFFPC && XINT ( addr , <NUM_LIT> ) != UNSPEC_TLS_GD && XINT ( addr , <NUM_LIT> ) != UNSPEC_TLS_IE ) return false ;


<s> if ( crtl -> is_leaf && ! sh_pr_n_sets ( ) && ! ( TARGET_SHCOMPACT && ( ( crtl -> args . info . call_cookie & ~ CALL_COOKIE_RET_TRAMP ( <NUM_LIT> ) ) || crtl -> saves_all_registers ) ) ) x = hard_reg ; else x = gen_frame_mem ( Pmode , return_address_pointer_rtx ) ; } else x = NULL_RTX ;


<s> if ( simplejump_p ( insn ) || ( ( JUMP_P ( insn ) || CALL_P ( insn ) ) ) ) length += <NUM_LIT> ; return length ;


<s> if ( ! isPositionIndependent ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ;


<s> SDValue VAListFI = Op . getOperand ( <NUM_LIT> ) ; const Value * VAListS = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; int argOffset = FuncInfo -> getVarArgsOffset ( ) ;

SDValue VAList = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getIntPtrConstant ( argOffset ) ) ;


<s> half_mode = HImode ; break ; case E_P2QImode : half_mode = QImode ; break ; default : gcc_unreachable ( ) ; } byte = GET_MODE_SIZE ( half_mode ) ; while ( num -- ) { rtx op = operands [ num ] ; if ( MEM_P ( op ) ) { if ( mem_op && rtx_equal_p ( op , mem_op ) ) { lo_half [ num ] = lo_half [ mem_num ] ; hi_half [ num ] = hi_half [ mem_num ] ; } else { mem_op = op ; mem_num = num ; lo_half [ num ] = adjust_address ( op , half_mode , <NUM_LIT> ) ; hi_half [ num ] = adjust_address ( op , half_mode , byte ) ; }


<s> MVT InnerEltVT = InnerVT . getVectorElementType ( ) ; if ( OpEltVT == InnerEltVT ) { assert ( OpVT == InnerVT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V . getOperand ( <NUM_LIT> ) ) ; } if ( InnerEltVT . getSizeInBits ( ) < InputBits ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , OpVT , V ) ) ; } if ( V . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) == InputBits ) { SDValue ExtractedV = V . getOperand ( <NUM_LIT> ) ; SDValue OrigV = ExtractedV . getOperand ( <NUM_LIT> ) ; if ( auto * ExtractIdx = dyn_cast < ConstantSDNode > ( ExtractedV . getOperand ( <NUM_LIT> ) ) ) if ( ExtractIdx -> getZExtValue ( ) == <NUM_LIT> ) { MVT OrigVT = OrigV . getSimpleValueType ( ) ; if ( OrigVT . getSizeInBits ( ) > OpVT . getSizeInBits ( ) ) { int Ratio = OrigVT . getSizeInBits ( ) / OpVT . getSizeInBits ( ) ; OrigVT = <STR_LIT> ( OrigVT . getVectorElementType ( ) , OrigVT . getVectorNumElements ( ) / Ratio ) ; OrigV = DAG . getNode ( <STR_LIT> , DL , OrigVT , OrigV , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } Op = DAG . getNode ( <STR_LIT> , DL , OpVT , OrigV ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; }


<s> void <ISA_LIT>TargetWinCOFFStreamer :: EmitARM64WinCFISaveRegPX ( unsigned Reg , int Offset ) { EmitARM64WinUnwindCode ( Win64EH :: UOP_SaveRegPX , Reg , Offset ) ;


<s> } else if ( imm == <NUM_LIT> ) { Opcode = <STR_LIT> ; } Inst . setOpcode ( Opcode ) ; if ( Opcode == <STR_LIT> ) {

Inst . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) if ( ! ( isUndefOrEqual ( Mask [ i ] , i + NumOps ) || ( V2IsUndef && isUndefOrInRange ( Mask [ i ] , NumOps , NumOps * <NUM_LIT> ) ) || ( V2IsSplat && isUndefOrEqual ( Mask [ i ] , NumOps ) ) ) ) return false ;


<s> if ( LinkerConfig :: DynObj == config ( ) . codeGenType ( ) || m_pGOT -> hasGOT1 ( ) || m_pGOTSymbol != NULL ) { m_pGOT -> finalizeSectionSize ( ) ; defineGOTSymbol ( pBuilder ) ; } if ( m_pPLT -> hasPLT1 ( ) ) m_pPLT -> finalizeSectionSize ( ) ; ELFFileFormat * file_format = getOutputFormat ( ) ; if ( ! m_pRelDyn -> empty ( ) ) { assert ( ! config ( ) . isCodeStatic ( ) && <STR_LIT> ) ; file_format -> getRelDyn ( ) . setSize ( m_pRelDyn -> numOfRelocs ( ) * getRelEntrySize ( ) ) ;


<s> bool hasRCPC_IMMO ( ) const { return HasRCPC_IMMO ;


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const {

return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> void <ISA_LIT>InstPrinter :: printNeg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {

static_cast < <ISA_LIT>InstPrinter * > ( this ) -> printNeg ( MI , OpNo , O ) ;


<s> assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ; bool EltIs64Bits = DL . getTypeSizeInBits ( VecTy -> getScalarType ( ) ) == <NUM_LIT> ; if ( Factor <= TLI -> getMaxSupportedInterleaveFactor ( ) && ! EltIs64Bits ) { unsigned NumElts = VecTy -> getVectorNumElements ( ) ; Type * SubVecTy = VectorType :: get ( VecTy -> getScalarType ( ) , NumElts / Factor ) ; unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; if ( NumElts % Factor == <NUM_LIT> && ( SubVecSize == <NUM_LIT> || SubVecSize % <NUM_LIT> == <NUM_LIT> ) && ! VecTy -> getScalarType ( ) -> isHalfTy ( ) ) return Factor * ( ( SubVecSize + <NUM_LIT> ) / <NUM_LIT> ) ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ;


<s> if ( TII -> isPredicated ( & * BI ) ) continue ; int OperandIdx = TII -> getOperandIdx ( BI -> getOpcode ( ) , <STR_LIT> :: write ) ; if ( OperandIdx > - <NUM_LIT> && BI -> getOperand ( OperandIdx ) . getImm ( ) == <NUM_LIT> ) continue ; int DstIdx = TII -> getOperandIdx ( BI -> getOpcode ( ) , <STR_LIT> :: dst ) ; if ( DstIdx == - <NUM_LIT> ) { continue ; } unsigned Dst = BI -> getOperand ( DstIdx ) . getReg ( ) ; if ( isTrans || TII -> isTransOnly ( & * BI ) ) { Result [ Dst ] = <STR_LIT> ; continue ; } if ( BI -> getOpcode ( ) == <STR_LIT> || BI -> getOpcode ( ) == <STR_LIT> ) { Result [ Dst ] = <STR_LIT> ; continue ; } if ( Dst == <STR_LIT> ) { continue ; } unsigned PVReg = <NUM_LIT> ; switch ( TRI . getHWRegChan ( Dst ) ) { case <NUM_LIT> : PVReg = <STR_LIT> ; break ; case <NUM_LIT> :


<s> static bool isPerfectIncrement ( SDValue Inc , EVT VecTy , unsigned NumVecs ) { auto C = dyn_cast < ConstantSDNode > ( Inc ) ; return C && C -> getZExtValue ( ) == VecTy . getSizeInBits ( ) / <NUM_LIT> * NumVecs ;


<s> if ( units == UNITS_D_ADDR ) return ( get_attr_addr_regfile ( insn ) == ADDR_REGFILE_A ? <NUM_LIT> : <NUM_LIT> ) ; else { enum attr_dest_regfile rf = get_attr_dest_regfile ( insn ) ; if ( rf == DEST_REGFILE_ANY ) return get_attr_type ( insn ) == TYPE_BRANCH ? <NUM_LIT> : <NUM_LIT> ;

else return rf == DEST_REGFILE_A ? <NUM_LIT> : <NUM_LIT> ;


<s> void <ISA_LIT>DAGToDAGISel :: getAddressOperands ( const <ISA_LIT>AddressingMode & AM , EVT VT , SDValue & Base , SDValue & Disp ) { Base = AM . Base ; if ( ! Base . getNode ( ) ) Base = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( Base . getOpcode ( ) == <STR_LIT> ) { int64_t FrameIndex = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FrameIndex , VT ) ;

} else if ( Base . getValueType ( ) != VT ) {


<s> return ( SU -> getInstr ( ) -> getOpcode ( ) == <STR_LIT> ) ;


<s> static SDValue LowerSUB ( SDValue Op , SelectionDAG & DAG ) {

assert ( Op . getValueType ( ) . is256BitVector ( ) && Op . getValueType ( ) . isInteger ( ) && <STR_LIT> ) ;


<s> addr = mips_got_load ( dest , addr , SYMBOL_GOTOFF_CALL ) ; emit_insn ( gen_rtx_SET ( dest , addr ) ) ; return true ; } else { mips_emit_move ( dest , addr ) ; return false ; }


<s> void addHWRegsAsmRegOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSize == Offset ) return ; if ( LeftoverBytes ) { assert ( ( ByValSize > Offset ) && ( ByValSize < Offset + RegSize ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSize = RegSize / <NUM_LIT> , TotalSizeLoaded = <NUM_LIT> ; Offset < ByValSize ; LoadSize /= <NUM_LIT> ) { unsigned RemSize = ByValSize - Offset ; if ( RemSize < LoadSize ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ;

if ( isLittle ) Shamt = TotalSizeLoaded ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ST ) , ST ( ST ) {


<s> PLTEntryBase * plt0 = & ( llvm :: cast < PLTEntryBase > ( * first ) ) ; return plt0 ;


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> BuildMI ( MBB , I , DL , AddiuSpImm ( Imm ) ) . addImm ( Imm ) ;


<s> bool <ISA_LIT>TTIImpl :: isLegalNTLoad ( Type * DataType , llvm :: Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ;

if ( Alignment >= DataSize && ( DataSize == <NUM_LIT> || DataSize == <NUM_LIT> ) ) return DataSize == <NUM_LIT> ? ST -> hasSSE1 ( ) : ST -> hasAVX2 ( ) ;


<s> unsigned IFlags = <NUM_LIT> ; if ( IFlagsStr != <STR_LIT> ) { for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Flag == ~ <NUM_LIT> || ( IFlags & Flag ) ) return MatchOperand_NoMatch ; IFlags |= Flag ; } } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateProcIFlags ( ( <STR_LIT> ) IFlags , S ) ) ; return MatchOperand_Success ;


<s> } return UsedConst . XYPair == ReadConstIndex ; } else { if ( ! UsedConst . ZWPair ) { UsedConst . ZWPair = ReadConstIndex ; } return UsedConst . ZWPair == ReadConstIndex ;


<s> return STUB_INDEX_OFFSET + m_stack_align_off_in ;


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getMemEncodingMMSPImm5Lsl2 ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) && MI . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) >> <NUM_LIT> ; return OffBits & <NUM_LIT> ;


<s> Opc = ( EltSize == <NUM_LIT> ) ? AMDGPU :: DS_WRITE2ST64_B32 : AMDGPU :: DS_WRITE2ST64_B64 ; } assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Write2Desc = TII -> get ( Opc ) ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineInstrBuilder Write2 = BuildMI ( * MBB , I , DL , Write2Desc ) . addImm ( <NUM_LIT> ) . addOperand ( * Addr ) . addOperand ( * Data0 ) . addOperand ( * Data1 ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addOperand ( * M0Reg ) . addMemOperand ( * I -> memoperands_begin ( ) ) . addMemOperand ( * Paired -> memoperands_begin ( ) ) ; unsigned OrigRegs [ ] = { Data0 -> getReg ( ) , Data1 -> getReg ( ) , Addr -> getReg ( ) , M0Reg -> getReg ( ) } ; LIS -> RemoveMachineInstrFromMaps ( I ) ; LIS -> RemoveMachineInstrFromMaps ( Paired ) ; I -> eraseFromParent ( ) ; Paired -> eraseFromParent ( ) ;

LIS -> repairIntervalsInRange ( MBB , Write2 , Write2 , OrigRegs ) ;


<s> long long __result = ( ( __v2df ) __rounded ) [ <NUM_LIT> ] ; return __result ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , Subtarget -> isABI_O32 ( ) , Subtarget -> isFP64bit ( ) , CCInfo ) ; <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget -> mipsSEUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ;

if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getValVT ( ) , Val ) ;


<s> case EXTRACT_LAST_REDUCTION : return sve_costs -> clast_cost ; case FOLD_LEFT_REDUCTION : switch ( GET_MODE_INNER ( TYPE_MODE ( vectype ) ) ) { case E_HFmode : case E_BFmode :


<s> void <ISA_LIT>ATTInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '%' << getRegisterName ( RegNo ) ;


<s> } } else if ( Reg0 != Reg1 ) { unsigned CommOpIdx1 , CommOpIdx2 ; if ( ! TII -> findCommutedOpIndices ( MI , CommOpIdx1 , CommOpIdx2 ) || CommOpIdx1 != <NUM_LIT> || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( MI ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ;

MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ;


<s> DEBUG ( { dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ; } ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineDominatorTree & MDT = getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; assert ( MRI . isSSA ( ) && <STR_LIT> ) ; for ( auto & MBB : MF ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << '\n' ) ; for ( auto & MI : MBB ) switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned ToReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FromReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( auto I = MRI . use_begin ( FromReg ) , E = MRI . use_end ( ) ; I != E ; ) { MachineOperand & O = * I ++ ; MachineInstr * Where = O . getParent ( ) ; if ( Where -> getOpcode ( ) == TargetOpcode :: PHI ) { MachineBasicBlock * Pred = Where -> getOperand ( & O - & Where -> getOperand ( <NUM_LIT> ) + <NUM_LIT> ) . getMBB ( ) ; if ( ! MDT . dominates ( & MBB , Pred ) ) continue ; } else { if ( & MI == Where || ! MDT . dominates ( & MI , Where ) ) continue ; } Changed = true ; DEBUG ( dbgs ( ) << <STR_LIT> << O << <STR_LIT> << * Where << <STR_LIT> << MI << <STR_LIT> ) ; O . setReg ( ToReg ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) && <STR_LIT> ) ; } }


<s> bool hasMT ( ) const { return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> case AMDGPU :: JUMP : return AMDGPU :: CONTINUE_LOGICALZ_i32 ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } return - <NUM_LIT> ;


<s> rtx mem = gen_frame_mem ( GET_MODE ( reg ) , plus_constant ( Pmode , base , offset ) ) ;

add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , reg ) ) ;


<s> return DAG . getTargetConstant ( countPopulation ( V ) , dl , <STR_LIT> ) ; } SDValue PopOut = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InpVal ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , PopOut ) ;


<s> const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( ! TID . isTerminator ( ) ) return false ; if ( TID . isBranch ( ) && ! TID . isBarrier ( ) ) return true ; if ( ! TID . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ;


<s> bool <ISA_LIT>RegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const {

return PhysReg != <STR_LIT> && PhysReg != <STR_LIT> ;


<s> for ( auto Type : Types ) { if ( Grouped . empty ( ) || Grouped . back ( ) . first != Type ) Grouped . push_back ( std :: make_pair ( Type , <NUM_LIT> ) ) ;


<s> if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( create<ISA_LIT>PostRewritePass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> if ( IsFirst ) { IsFirst = false ; } else { OS << <STR_LIT> ; } OS << MBB -> getNumber ( ) ; } OS << <STR_LIT> << Entry -> getNumber ( ) << <STR_LIT> << ( Exit == nullptr ? - <NUM_LIT> : Exit -> getNumber ( ) ) << <STR_LIT> << printReg ( getBBSelectRegIn ( ) , TRI ) << <STR_LIT> << printReg ( getBBSelectRegOut ( ) , TRI ) << <STR_LIT> ; for ( auto & LI : LiveOuts ) { OS << printReg ( LI , TRI ) << <STR_LIT> ; }


<s> auto I = llvm :: find_if ( Res , [ Reg ] ( const RegisterMaskPair & RM ) { return RM . RegUnit == Reg ; } ) ; if ( I != Res . end ( ) ) I -> LaneMask |= UsedMask ;

else Res . push_back ( RegisterMaskPair ( Reg , UsedMask ) ) ;


<s> <ISA_LIT>PMLProfileImport ( const <ISA_LIT>TargetMachine & TM ) : MachineFunctionPass ( ID ) {


<s> if ( ! Subtarget . isDarwin ( ) ) RegName = stripRegisterPrefix ( RegName ) ; O << RegName ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl ::

StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ;


<s> if ( ( flags & OPTION_MASK_MFCRF ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_POPCNTB ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_FPRND ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_CMPB ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_MFPGPR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_SOFT_FLOAT ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_RECIP_PRECISION ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_ALTIVEC ) != <NUM_LIT> ) { const char * vec_str = ( define_p ) ? <STR_LIT> : <STR_LIT> ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , vec_str ) ; if ( ! flag_iso ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_VSX ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_HTM ) != <NUM_LIT> ) { rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; } if ( ( flags & OPTION_MASK_P8_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_P9_VECTOR ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_QUAD_MEMORY_ATOMIC ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_CRYPTO ) != <NUM_LIT> ) rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( ( flags & OPTION_MASK_FLOAT128_KEYWORD ) != <NUM_LIT> ) { rs6000_define_or_undefine_macro ( define_p , <STR_LIT> ) ; if ( define_p ) rs6000_define_or_undefine_macro ( true , <STR_LIT> ) ;

else rs6000_define_or_undefine_macro ( false , <STR_LIT> ) ;


<s> virtual ~ <ISA_LIT>Disassembler ( ) {


<s> MCSection * findAssociatedSection ( ) const override { return getSubExpr ( ) -> findAssociatedSection ( ) ;


<s> return createELFObjectWriter ( MOTW , OS , false ) ;


<s> EVT VecVT = N0 . getValueType ( ) ; if ( ! VT . isScalarInteger ( ) || ! VecVT . isSimple ( ) ) return SDValue ( ) ; bool IsTruncated = N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && ( N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; if ( ! Subtarget . hasSSE2 ( ) || ( Subtarget . hasAVX512 ( ) && ! IsTruncated ) ) return SDValue ( ) ; MVT SExtVT ; switch ( VecVT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; if ( N0 . getOpcode ( ) == <STR_LIT> && Subtarget . hasAVX ( ) && N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) ) { SExtVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; if ( N0 . getOpcode ( ) == <STR_LIT> && Subtarget . hasAVX ( ) && ( N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) || N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . is512BitVector ( ) ) ) { SExtVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : MF ( MF ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , InArgFIRange ( std :: make_pair ( - <NUM_LIT> , <NUM_LIT> ) ) , OutArgFIRange ( std :: make_pair ( - <NUM_LIT> , <NUM_LIT> ) ) , GlobalRegFI ( <NUM_LIT> ) , DynAllocFI ( <NUM_LIT> ) , MaxCallFrameSize ( <NUM_LIT> ) , EmitNOAT ( false ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { unsigned NumRet = Outs . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getFrameLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , <STR_LIT> ) ; SDValue BS = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue RetVal ; for ( unsigned i = <NUM_LIT> ; i < NumRet ; ++ i ) { RetVal = OutVals [ i ] ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , RetVal , ES , BS , DAG . getConstant ( i , <STR_LIT> ) ) ; }

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> computeRegisterProperties ( Subtarget . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: Source ) ;

setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ;


<s> unsigned exitDelay = PST -> getCFLDelaySlotCycles ( false ) ; unsigned alignSize = ( defaultAlign . value ( ) < <NUM_LIT> ) ? <NUM_LIT> : defaultAlign . value ( ) - <NUM_LIT> ; unsigned branch_fixups = numBranchesToFix * ( exitDelay - localDelay ) * <NUM_LIT> ; if ( PTM . getCodeModel ( ) == CodeModel :: Large ) { branch_fixups += numBranchesToFix * <NUM_LIT> ; } if ( mightFallthrough ) { unsigned brcfCost = PTM . getCodeModel ( ) == CodeModel :: Large ? <NUM_LIT> : <NUM_LIT> ; branch_fixups += brcfCost + ( mightExitRegion ? exitDelay : localDelay ) * <NUM_LIT> ; } return alignSize + branch_fixups ;


<s> static inline unsigned getImm4 ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectVOP3OpSelMods0 ( MachineOperand & Root ) const { return { {

[ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Root . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> rtx sp = NULL_RTX ; rtx fp = NULL_RTX ; framesize = ( frame_info . valid ? frame_info . total_size : compute_frame_size ( get_frame_size ( ) ) ) ; if ( framesize > <NUM_LIT> || frame_pointer_needed ) sp = gen_rtx_REG ( SImode , SP_REGNUM ) ; if ( frame_pointer_needed ) fp = gen_rtx_REG ( SImode , FP_REGNUM ) ; if ( SHOULD_COMBINE_STORE_RESTORE ) { emit_insn ( gen_store_regs ( gen_rtx_REG ( SImode , frame_info . first_reg ) , gen_rtx_REG ( SImode , frame_info . last_reg ) ) ) ; } else {


<s> switch ( Bits ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : Imm = - <NUM_LIT> ; break ; }

MI . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> static enum loongarch_symbol_type loongarch_classify_symbol ( const_rtx x ) { if ( LABEL_REF_P ( x ) ) return SYMBOL_GOT_DISP ; gcc_assert ( SYMBOL_REF_P ( x ) ) ; if ( SYMBOL_REF_TLS_MODEL ( x ) ) return SYMBOL_TLS ;

if ( SYMBOL_REF_P ( x ) ) return SYMBOL_GOT_DISP ;