<s> bool <ISA_LIT>FrameLowering :: expandLoadVec2 ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const { MachineFunction & MF = * B . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MachineInstr * MI = & * It ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstHi = HRI . getSubReg ( DstR , <STR_LIT> ) ; unsigned DstLo = HRI . getSubReg ( DstR , <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && <STR_LIT> ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool Is128B = HST . useHVXDblOps ( ) ; auto * RC = ! Is128B ? & <STR_LIT> : & <STR_LIT> ; unsigned Size = RC -> getSize ( ) ; unsigned NeedAlign = RC -> getAlignment ( ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned LoadOpc ; if ( NeedAlign <= HasAlign ) LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstLo ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; if ( NeedAlign <= MinAlign ( HasAlign , Size ) ) LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstHi ) . addFrameIndex ( FI ) . addImm ( Size ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return <STR_LIT> ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && Subtarget . hasBWI ( ) ) ) ) return <STR_LIT> ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return <STR_LIT> ;

return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ;


<s> case TargetOpcode :: G_INTTOPTR : return selectCopy ( I , MRI ) ; case TargetOpcode :: G_ZEXT : return selectZext ( I , MRI , MF ) ; case TargetOpcode :: G_ANYEXT : return selectAnyext ( I , MRI , MF ) ; case TargetOpcode :: G_ICMP : return selectCmp ( I , MRI , MF ) ; case TargetOpcode :: G_FCMP : return selectFCmp ( I , MRI , MF ) ; case TargetOpcode :: G_UADDE : return selectUadde ( I , MRI , MF ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectUnmergeValues ( I , MRI , MF ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_CONCAT_VECTORS : return selectMergeValues ( I , MRI , MF ) ; case TargetOpcode :: G_EXTRACT : return selectExtract ( I , MRI , MF ) ; case TargetOpcode :: G_INSERT : return selectInsert ( I , MRI , MF ) ; case TargetOpcode :: G_BRCOND : return selectCondBranch ( I , MRI , MF ) ; case TargetOpcode :: G_IMPLICIT_DEF : case TargetOpcode :: G_PHI : return selectImplicitDefOrPHI ( I , MRI ) ; case TargetOpcode :: G_SDIV : case TargetOpcode :: G_UDIV : case TargetOpcode :: G_SREM : case TargetOpcode :: G_UREM :


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; int Cost = getMemoryOpCost ( Opcode , VecTy , Alignment , AddressSpace ) ;

Cost += Factor * ( LT . first - <NUM_LIT> ) ;


<s> <ISA_LIT>16InstrInfo :: <ISA_LIT>16InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>InstrInfo ( tm , <STR_LIT> ) , RI ( * tm . getSubtargetImpl ( ) ) {


<s> if ( ! C ) return false ; SDLoc SL ( ByteOffsetNode ) ; GCNSubtarget :: Generation Gen = Subtarget -> getGeneration ( ) ; uint64_t ByteOffset = C -> getZExtValue ( ) ; Optional < int64_t > EncodedOffset = <STR_LIT> ( * Subtarget , ByteOffset ) ; if ( EncodedOffset ) { Offset = CurDAG -> getTargetConstant ( * EncodedOffset , SL , <STR_LIT> ) ; Imm = true ; return true ; } if ( Gen == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { EncodedOffset = <STR_LIT> ( * Subtarget , ByteOffset ) ; if ( EncodedOffset ) { Offset = CurDAG -> getTargetConstant ( * EncodedOffset , SL , <STR_LIT> ) ; return true ; }


<s> if ( Reg == <STR_LIT> ) return MCDisassembler :: Fail ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> LiveInterval & LI = LIS -> getInterval ( Reg ) ; for ( LiveInterval :: iterator I = LI . begin ( ) , E = LI . end ( ) ; I != E ; ++ I ) { if ( ! I -> start . isRegister ( ) || ! I -> end . isBlock ( ) ) continue ; MachineInstr * MI = LIS -> getInstructionFromIndex ( I -> start ) ; Defs . push_back ( MI ) ; } } else if ( S . isRegister ( ) ) { MachineInstr * MI = LIS -> getInstructionFromIndex ( S ) ; Defs . push_back ( MI ) ; } for ( unsigned i = <NUM_LIT> , n = Defs . size ( ) ; i < n ; ++ i ) { MachineInstr * MI = Defs [ i ] ; for ( auto & Op : MI -> operands ( ) ) {

if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . getReg ( ) != Reg ) continue ;


<s> unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ;


<s> break ; case CM_EMBMEDANY : if ( data_segment_operand ( op1 , GET_MODE ( op1 ) ) ) { if ( temp ) { temp1 = temp ; temp2 = op0 ; } else { temp1 = gen_reg_rtx ( DImode ) ; temp2 = gen_reg_rtx ( DImode ) ; } emit_insn ( gen_embmedany_sethi ( temp1 , op1 ) ) ; emit_insn ( gen_embmedany_brsum ( temp2 , temp1 ) ) ; emit_insn ( gen_embmedany_losum ( op0 , temp2 , op1 ) ) ; } else { if ( temp ) { if ( rtx_equal_p ( temp , op0 ) ) { gcc_assert ( ti_temp ) ; temp = gen_rtx_REG ( DImode , REGNO ( temp ) + <NUM_LIT> ) ; } temp1 = op0 ; temp2 = temp ; temp3 = op0 ; temp4 = op0 ; temp5 = op0 ; } else { temp1 = gen_reg_rtx ( DImode ) ; temp2 = gen_reg_rtx ( DImode ) ; temp3 = gen_reg_rtx ( DImode ) ; temp4 = gen_reg_rtx ( DImode ) ; temp5 = gen_reg_rtx ( DImode ) ; } emit_insn ( gen_embmedany_textuhi ( temp1 , op1 ) ) ; emit_insn ( gen_embmedany_texthi ( temp2 , op1 ) ) ; emit_insn ( gen_embmedany_textulo ( temp3 , temp1 , op1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp4 , gen_rtx_ASHIFT ( DImode , temp3 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp5 , gen_rtx_PLUS ( DImode , temp4 , temp2 ) ) ) ; emit_insn ( gen_embmedany_textlo ( op0 , temp5 , op1 ) ) ;


<s> LiveRegs . addLiveOuts ( MBB ) ; OptForSize = MF . getFunction ( ) . hasOptSize ( ) || llvm :: shouldOptimizeForSize ( & MBB , PSI , MBFI ) ; for ( MachineInstr & MI : llvm :: reverse ( MBB ) ) { if ( MachineInstr * NewMI = tryReplaceInstr ( & MI , MBB ) ) MIReplacements . push_back ( std :: make_pair ( & MI , NewMI ) ) ; LiveRegs . stepBackward ( MI ) ;


<s> bool CustomExpandInst ( const MCInst & Inst , MCStreamer & Out ) const { return CustomExpandInstNaCl<ISA_LIT> ( Inst , Out ) ;


<s> TargetIRAnalysis <ISA_LIT>TargetMachine :: getTargetIRAnalysis ( ) {

return TargetIRAnalysis ( [ this ] ( Function & ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ) ) ; } ) ;


<s> OperandMatchResultTy parseGR32 ( OperandVector & Operands ) { return parseRegister ( Operands , 'x' , GR32Regs , <ISA_LIT>Operand :: GR32Reg ) ;


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; if ( MI . getOpcode ( ) == AMDGPU :: COPY && isVGPRToSGPRCopy ( MI , TRI , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . print ( dbgs ( ) ) ) ; TII -> moveToVALU ( MI ) ; } switch ( MI . getOpcode ( ) ) { default : continue ; case AMDGPU :: PHI : { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . print ( dbgs ( ) ) ) ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i += <NUM_LIT> ) { unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; const TargetRegisterClass * RC = inferRegClassFromDef ( TRI , MRI , Reg , MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; MRI . constrainRegClass ( Reg , RC ) ; } unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

const TargetRegisterClass * RC = inferRegClassFromUses ( TRI , MRI , Reg , MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ;


<s> unsigned PackCost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) PackCost = getVectorBitmaskConversionCost ( CmpOpTy , ValTy ) ; return getNumberOfParts ( ValTy ) + PackCost ; } } else { switch ( Opcode ) { case Instruction :: ICmp : { unsigned Cost = <NUM_LIT> ; if ( ValTy -> isIntegerTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) Cost += <NUM_LIT> ; return Cost ; } case Instruction :: Select : if ( ValTy -> isFloatingPointTy ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } }

return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , nullptr ) ;


<s> MVT VecVT = N -> getSimpleValueType ( <NUM_LIT> ) ; MVT ElVT = VecVT . getVectorElementType ( ) ; unsigned NumElemsPerChunk = vecWidth / ElVT . getSizeInBits ( ) ; return Index / NumElemsPerChunk ;


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count ; } return Count ;


<s> static unsigned calcLiveInMask ( MachineBasicBlock * MBB ) { unsigned Mask = <NUM_LIT> ;

for ( const auto & LI : MBB -> liveins ( ) ) {


<s> bool need_mem ; if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) != PLUS || GET_MODE ( x ) != Pmode ) return orig_x ; if ( XEXP ( x , <NUM_LIT> ) == pic_offset_table_rtx ) ; else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) { rtx x0 = XEXP ( x , <NUM_LIT> ) ; rtx x00 = XEXP ( x0 , <NUM_LIT> ) ; rtx x01 = XEXP ( x0 , <NUM_LIT> ) ; if ( x00 == pic_offset_table_rtx ) addend = x01 ; else if ( x01 == pic_offset_table_rtx ) addend = x00 ; else return orig_x ; } else return orig_x ; x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) != CONST ) return orig_x ; x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) != UNSPEC ) return orig_x ; ret = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; if ( XINT ( x , <NUM_LIT> ) == UNSPEC_GOTOFF ) need_mem = false ; else if ( XINT ( x , <NUM_LIT> ) == UNSPEC_GOT ) need_mem = true ; else return orig_x ; gcc_assert ( GET_CODE ( ret ) == SYMBOL_REF ) ;

if ( need_mem != MEM_P ( orig_x ) ) return orig_x ;


<s> if ( ! isALUInstr ( MI . getOpcode ( ) ) ) { return false ; } for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( ! I -> isReg ( ) || ! I -> isUse ( ) || I -> getReg ( ) . isVirtual ( ) ) continue ; if ( <STR_LIT> . contains ( I -> getReg ( ) ) ) return true ; } return false ;


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = STI . getFrameLowering ( ) -> getStackAlignment ( ) ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; }

if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) {


<s> unsigned <ISA_LIT>LoadStoreOptimizer :: write2ST64Opcode ( unsigned EltSize ) const { if ( STM -> ldsRequiresM0Init ( ) ) return ( EltSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( Register :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) { if ( IndirectRC -> getRegister ( RegIndex ) == Reg ) break ; }

Offset = std :: max ( Offset , ( int ) RegIndex ) ;


<s> void <ISA_LIT>MachineFunctionInfo :: anchor ( ) {


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ^ Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> gcc_assert ( ( GET_MODE ( dest ) == V2DImode && ( GET_MODE ( src ) == DImode || src == const0_rtx ) ) || ( GET_MODE ( dest ) == V2DFmode && GET_MODE ( src ) == DFmode ) ) ; rtx low , high ; if ( src == const0_rtx ) { low = src ; high = src ; } else { low = mips_subword ( src , false ) ; high = mips_subword ( src , true ) ; } rtx new_dest = simplify_gen_subreg ( V4SImode , dest , GET_MODE ( dest ) , <NUM_LIT> ) ; emit_insn ( gen_msa_fill_w ( new_dest , low ) ) ; emit_insn ( gen_msa_insert_w ( new_dest , high , new_dest , GEN_INT ( <NUM_LIT> << <NUM_LIT> ) ) ) ; emit_insn ( gen_msa_insert_w ( new_dest , high , new_dest , GEN_INT ( <NUM_LIT> << <NUM_LIT> ) ) ) ;


<s> auto I = Reachable . find ( From ) ; if ( I == Reachable . end ( ) ) return false ; return I -> second . count ( To ) ;


<s> cum -> fpr_offset = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG ( cum -> fpr_offset , mode , type ) - NDS32_FPR_ARG_FIRST_REGNUM + NDS32_NEED_N_REGS_FOR_ARG ( mode , type ) ; } else { cum -> gpr_offset = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , mode , type ) - NDS32_GPR_ARG_FIRST_REGNUM + NDS32_NEED_N_REGS_FOR_ARG ( mode , type ) ; } }


<s> case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : { bool Changed = false ; Changed |= Helper . tryCombineExtendingLoads ( MI ) ; Changed |= Helper . tryCombineIndexedLoadStore ( MI ) ; return Changed ; } case TargetOpcode :: G_STORE : return Helper . tryCombineIndexedLoadStore ( MI ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS :


<s> ArrayRef < int > GoodInputs = MoveToLo ? LoInputs : HiInputs ; ArrayRef < int > BadInputs = MoveToLo ? HiInputs : LoInputs ; if ( BadInputs . empty ( ) ) return V ; int MoveMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int MoveOffset = MoveToLo ? <NUM_LIT> : <NUM_LIT> ; if ( GoodInputs . empty ( ) ) { for ( int BadInput : BadInputs ) { MoveMask [ Mask [ BadInput ] % <NUM_LIT> + MoveOffset ] = Mask [ BadInput ] - MaskOffset ; Mask [ BadInput ] = Mask [ BadInput ] % <NUM_LIT> + MoveOffset + MaskOffset ; } } else { if ( GoodInputs . size ( ) == <NUM_LIT> ) { MoveMask [ Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset ] = Mask [ GoodInputs [ <NUM_LIT> ] ] - MaskOffset ; MoveMask [ Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset ] = Mask [ GoodInputs [ <NUM_LIT> ] ] - MaskOffset ; Mask [ GoodInputs [ <NUM_LIT> ] ] = Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset + MaskOffset ; Mask [ GoodInputs [ <NUM_LIT> ] ] = Mask [ GoodInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MoveOffset + MaskOffset ; } else { for ( int GoodInput : GoodInputs ) MoveMask [ Mask [ GoodInput ] - MaskOffset ] = Mask [ GoodInput ] - MaskOffset ; } int MoveMaskIdx = std :: find ( std :: begin ( MoveMask ) + MoveOffset , std :: end ( MoveMask ) , - <NUM_LIT> ) - std :: begin ( MoveMask ) ; assert ( MoveMaskIdx >= MoveOffset && <STR_LIT> ) ; if ( BadInputs . size ( ) == <NUM_LIT> ) { assert ( MoveMask [ MoveMaskIdx ] == - <NUM_LIT> && <STR_LIT> ) ; assert ( MoveMask [ MoveMaskIdx + <NUM_LIT> ] == - <NUM_LIT> && <STR_LIT> ) ; MoveMask [ MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> ] = Mask [ BadInputs [ <NUM_LIT> ] ] - MaskOffset ; MoveMask [ MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> ] = Mask [ BadInputs [ <NUM_LIT> ] ] - MaskOffset ; Mask [ BadInputs [ <NUM_LIT> ] ] = MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MaskOffset ; Mask [ BadInputs [ <NUM_LIT> ] ] = MoveMaskIdx + Mask [ BadInputs [ <NUM_LIT> ] ] % <NUM_LIT> + MaskOffset ; } else { assert ( BadInputs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MoveMask [ MoveMaskIdx ] = Mask [ BadInputs [ <NUM_LIT> ] ] - MaskOffset ; Mask [ BadInputs [ <NUM_LIT> ] ] = MoveMaskIdx + MaskOffset ; } }

return DAG . getVectorShuffle ( <STR_LIT> , DL , V , DAG . getUNDEF ( <STR_LIT> ) , MoveMask ) ;


<s> explicit <ISA_LIT>FrameInfo ( const <ISA_LIT>Subtarget & ST ) : TargetFrameInfo ( StackGrowsDown , ST . getStackAlignment ( ) , <NUM_LIT> ) {


<s> if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) assert ( <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = <STR_LIT> ( I -> getOpcode ( ) ) ; assert ( BranchCond . size ( ) == <NUM_LIT> ) ; if ( CC != BranchCond [ <NUM_LIT> ] . getImm ( ) ) continue ; break ; } unsigned Opc = TailCall . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opc ) ) ; MIB -> addOperand ( TailCall . getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB -> addOperand ( BranchCond [ <NUM_LIT> ] ) ; MIB . copyImplicitOps ( TailCall ) ; LivePhysRegs LiveRegs ( getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; LiveRegs . stepForward ( * MIB , Clobbers ) ; for ( const auto & C : Clobbers ) { MIB . addReg ( C . first , RegState :: Implicit ) ; MIB . addReg ( C . first , RegState :: Implicit | RegState :: Define ) ;


<s> return new <ISA_LIT>CFGOptimizer ( TM ) ;


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { llvm :: StringRef Sym = G -> getGlobal ( ) -> getName ( ) ; Function * F = G -> getGlobal ( ) -> getParent ( ) -> getFunction ( Sym ) ; if ( F && F -> hasFnAttribute ( <STR_LIT> ) ) { SpecialCallingConv = <STR_LIT> ; }


<s> SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , VT , Remainder_GE_Den , Remainder_GE_Zero ) ; SDValue Quotient_A_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Quotient_S_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Quotient , Quotient_A_One , <STR_LIT> ) ; Div = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Quotient_S_One , Div , <STR_LIT> ) ; SDValue Remainder_S_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Remainder_A_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Rem = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Remainder , Remainder_S_Den , <STR_LIT> ) ; Rem = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Remainder_A_Den , Rem , <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) / <NUM_LIT> : <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ;


<s> static DecodeStatus DecodePowerTwoOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) {

DecodeStatus S = MCDisassembler :: Success ;


<s> std :: vector < std :: string > rets ( Imm8 a ) { return D ( <STR_LIT> , a ) ;


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { disablePass ( & PrologEpilogCodeInserterID ) ; disablePass ( & MachineCopyPropagationID ) ; addPass ( create<ISA_LIT>RegStackify ( ) ) ; addPass ( create<ISA_LIT>RegColoring ( ) ) ; TargetPassConfig :: addPostRegAlloc ( ) ;


<s> CombinerHelper Helper ( Observer , B , KB , MDT , LInfo ) ; <ISA_LIT>PostLegalizerCombinerHelper PostLegalizerHelper ( B , Helper ) ; <ISA_LIT>GenPostLegalizerCombinerHelper Generated ( GeneratedRuleCfg , Helper , PostLegalizerHelper ) ; if ( Generated . tryCombineAll ( Observer , MI , B ) ) return true ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_SHL : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_ASHR : return Helper . tryCombineShiftToUnmerge ( MI , <NUM_LIT> ) ;


<s> MCWinCOFFStreamer :: FinishImpl ( ) ;


<s> MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const <ISA_LIT>FrameLowering * HFI = HST -> getFrameLowering ( ) ; int FX = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; unsigned StkA = HFI -> getStackAlignment ( ) ; unsigned MaxA = MFI -> getMaxAlignment ( ) ; SDValue FI = CurDAG -> getTargetFrameIndex ( FX , <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDNode * R = <NUM_LIT> ; if ( FX < <NUM_LIT> || MaxA <= StkA || ! MFI -> hasVarSizedObjects ( ) ) { R = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , FI , Zero ) ; } else { auto & HMFI = * MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned AR = HMFI . getStackAlignBaseVReg ( ) ; SDValue CH = CurDAG -> getEntryNode ( ) ; SDValue Ops [ ] = { CurDAG -> getCopyFromReg ( CH , DL , AR , <STR_LIT> ) , FI , Zero } ;

R = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ;


<s> static bool use_toc_relative_ref ( rtx sym , machine_mode mode ) { return ( ( constant_pool_expr_p ( sym ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( sym ) , get_pool_mode ( sym ) ) ) || ( TARGET_CMODEL == CMODEL_MEDIUM && SYMBOL_REF_LOCAL_P ( sym ) && GET_MODE_SIZE ( mode ) <= POWERPC64_TOC_POINTER_ALIGNMENT ) ) ;


<s> getPostIdxRegOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; bool isAdd = MO1 . getImm ( ) != <NUM_LIT> ; return CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) | ( isAdd << <NUM_LIT> ) ;


<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( TT . getOS ( ) == Triple :: AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , DoesNotSupportXNACK ( false ) , EnableCuMode ( false ) , TrapHandler ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , EnablePRTStrictNull ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX8Insts ( false ) , GFX9Insts ( false ) , GFX10Insts ( false ) , GFX7GFX8GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDPP8 ( false ) , HasR128A16 ( false ) , HasNSAEncoding ( false ) , HasDLInsts ( false ) , HasDot1Insts ( false ) , HasDot2Insts ( false ) , HasDot5Insts ( false ) , HasDot6Insts ( false ) , EnableSRAMECC ( false ) , DoesNotSupportSRAMECC ( false ) , HasNoSdstCMPX ( false ) , HasVscnt ( false ) , HasRegisterBanking ( false ) , HasVOP3Literal ( false ) , HasNoDataDepHazard ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , ScalarFlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , LDSMisalignedBug ( false ) , ScalarizeGlobal ( false ) , HasVcmpxPermlaneHazard ( false ) , HasVMEMtoScalarWriteHazard ( false ) , HasSMEMtoVectorWriteHazard ( false ) , HasInstFwdPrefetchBug ( false ) , HasVcmpxExecWARHazard ( false ) , HasLdsBranchVmemWARHazard ( false ) , HasNSAtoVMEMBug ( false ) , HasOffset3fBug ( false ) , HasFlatSegmentOffsetBug ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ;

RegBankInfo . reset ( new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned i = <NUM_LIT> ; for ( auto & Arg : Args ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + <NUM_LIT> , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ i ] , Regs , Offsets ) ; } ) ; ++ i ; }

if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ;


<s> default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> * BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; }


<s> unsigned int <ISA_LIT>RegisterInfo :: getSubReg ( unsigned int , unsigned int ) const {


<s> return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> return ( __m64 ) __builtin_arm_waddwus ( ( __v2si ) __m1 , ( __v2si ) __m2 ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitInst ( uint32_t Inst ) { getStreamer ( ) . emitInst ( Inst ) ;


<s> void CounterPropagateAddr ( const std :: set < MachineInstr * > & MIs , unsigned Addr ) const {


<s> if ( ! MI . isTransient ( ) ) ++ Count ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI . mayLoadOrStore ( ) && <STR_LIT> ) ; Register MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) {


<s> void setVariadicGPRSize ( unsigned Size ) { VariadicGPRSize = Size ;


<s> case 'y' : O << <STR_LIT> ; printOperand ( MI , OpNo , O ) ; return false ; case 'U' : case 'X' : assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; return false ; } }


<s> FullFS += <STR_LIT> ; } FullFS += <STR_LIT> ; FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) { FlatForGlobal = true ; } if ( MaxPrivateElementSize == <NUM_LIT> ) MaxPrivateElementSize = <NUM_LIT> ; if ( LDSBankCount == <NUM_LIT> ) LDSBankCount = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: amdgcn ) { if ( LocalMemorySize == <NUM_LIT> ) LocalMemorySize = <NUM_LIT> ; if ( ! HasMovrel && ! HasVGPRIndexMode ) HasMovrel = true ; }

if ( WavefrontSize == <NUM_LIT> ) WavefrontSize = <NUM_LIT> ;


<s> int i , n = ( int ) ( sizeof ( prefixes ) / sizeof ( * prefixes ) ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) if ( str_prefix_p ( str , prefixes [ i ] ) ) return i ; return n ;


<s> assert ( ValMapping . NumBreakDowns == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . Length == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . StartIdx == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . Length == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . StartIdx == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . RegBank == ValMapping . BreakDown [ <NUM_LIT> ] . RegBank ) ; return <NUM_LIT> ;


<s> void <ISA_LIT>LegalizerInfo :: setLegalizerInfoSSE41 ( ) { if ( ! Subtarget . hasSSE41 ( ) ) return ; const LLT v4s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ; auto & LegacyInfo = getLegacyLegalizerInfo ( ) ;

LegacyInfo . setAction ( { G_MUL , v4s32 } , LegacyLegalizeActions :: Legal ) ;


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : MachineFunctionInfo ( ) , KernArgSize ( <NUM_LIT> ) , MaxKernArgAlign ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , ScratchSize ( <NUM_LIT> ) , IsKernel ( true ) {


<s> SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; } if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 ) ;


<s> if ( getEMachine ( ) == ELF :: EM_<ISA_LIT>_64 ) return getRelocType64 ( Ctx , Fixup . getLoc ( ) , Modifier , Type , IsPCRel ) ; assert ( ( getEMachine ( ) == ELF :: EM_386 || getEMachine ( ) == ELF :: EM_IAMCU ) && <STR_LIT> ) ;

return getRelocType32 ( Modifier , getType32 ( Type ) , IsPCRel ) ;


<s> if ( getParser ( ) . parseExpression ( ShiftAmount , EndLoc ) ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Val = CE -> getValue ( ) ; if ( Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> ) { Error ( ExLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateRotImm ( Val , S , EndLoc ) ) ;


<s> if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( * MI ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;

if ( checkAnyInstHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;


<s> MVT MaskVecVT = <STR_LIT> ( MaskEltVT , VT . getVectorNumElements ( ) ) ; SDValue MaskNode = getConstVector ( Mask , MaskVecVT , DAG , DL , true ) ;

if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , MaskNode , V1 ) ;


<s> Parser . Lex ( ) ; unsigned regKind = <STR_LIT> ; if ( matchRegisterName ( Tok , RegNo , regKind ) ) { Parser . Lex ( ) ; return false ; } return Error ( StartLoc , <STR_LIT> ) ;


<s> return BuildMI ( * InsertPt -> getParent ( ) , InsertPt , MI . getDebugLoc ( ) , get ( StoreOpcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } if ( OpNum == <NUM_LIT> ) { unsigned LoadOpcode = Op0IsGPR ? <STR_LIT> : <STR_LIT> ; return BuildMI ( * InsertPt -> getParent ( ) , InsertPt , MI . getDebugLoc ( ) , get ( LoadOpcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } } if ( OpNum == <NUM_LIT> && MI . hasOneMemOperand ( ) ) { MachineMemOperand * MMO = * MI . memoperands_begin ( ) ; if ( MMO -> getSize ( ) == Size && ! MMO -> isVolatile ( ) ) { if ( isSimpleBD12Move ( & MI , <STR_LIT> ) ) { return BuildMI ( * InsertPt -> getParent ( ) , InsertPt , MI . getDebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addImm ( Size ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addMemOperand ( MMO ) ; } if ( isSimpleBD12Move ( & MI , <STR_LIT> ) ) { return BuildMI ( * InsertPt -> getParent ( ) , InsertPt , MI . getDebugLoc ( ) , get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addImm ( Size ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; }


<s> const char * getPassName ( ) const override {


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const {

const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ;


<s> unsigned GetRelocType ( const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const override {


<s> switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : DivOpc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : DivOpc = <STR_LIT> ; break ; } Register Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; Register Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg || ! Src1Reg ) return false ; emitInst ( DivOpc ) . addReg ( Src0Reg ) . addReg ( Src1Reg ) ; emitInst ( <STR_LIT> ) . addReg ( Src1Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Register ResultReg = createResultReg ( & <STR_LIT> ) ;


<s> return MI -> getOperand ( TII -> getOperandIdx ( MI -> getOpcode ( ) , <STR_LIT> :: COUNT ) ) . getImm ( ) ;


<s> MFI -> addToSpilledVGPRs ( getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ) ; MI -> eraseFromParent ( ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand * VData = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ; buildSpillLoadStore ( MI , <STR_LIT> , Index , VData -> getReg ( ) , VData -> isKill ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) -> getReg ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) -> getReg ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: offset ) -> getImm ( ) , * MI -> memoperands_begin ( ) , RS ) ; MI -> eraseFromParent ( ) ; break ; } default : { const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsMUBUF = TII -> isMUBUF ( * MI ) ; if ( ! IsMUBUF && MFI -> getFrameOffsetReg ( ) != MFI -> getScratchWaveOffsetReg ( ) ) { unsigned DiffReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; bool IsCopy = MI -> getOpcode ( ) == <STR_LIT> ; unsigned ResultReg = IsCopy ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , DiffReg ) . addReg ( MFI -> getFrameOffsetReg ( ) ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) ) ; int64_t Offset = FrameInfo . getObjectOffset ( Index ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , ResultReg ) . addImm ( Log2_32 ( ST . getWavefrontSize ( ) ) ) . addReg ( DiffReg ) ; } else { unsigned CarryOut = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ScaledReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , ScaledReg ) . addReg ( DiffReg , RegState :: Kill ) . addImm ( Log2_32 ( ST . getWavefrontSize ( ) ) ) ;

BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , ResultReg ) . addReg ( CarryOut , RegState :: Define | RegState :: Dead ) . addImm ( Offset ) . addReg ( ScaledReg , RegState :: Kill ) ;


<s> return regno == FIRST_RETVAL_REGNUM ;


<s> if ( Subtarget . hasAVX512 ( ) && MaskVT . is512BitVector ( ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( AllowFloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( RepeatedMask ) ; return true ; } } } else if ( AllowFloatDomain && Subtarget . hasAVX ( ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , Mask . size ( ) ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) {

ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ;


<s> void addImm0_7Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr , bool IsDarwin ) : Kind ( Kind ) , Expr ( Expr ) , IsDarwin ( IsDarwin ) {


<s> MIB . addReg ( AddrIn ) . addImm ( StSize ) ; AddDefaultPred ( MIB ) ; } else if ( IsThumb2 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( StSize ) ) ; } else {

AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( Data ) . addReg ( AddrIn ) . addReg ( <NUM_LIT> ) . addImm ( StSize ) ) ;


<s> return __aarch64_vset_lane_any ( * __src , __vec , __lane ) ;


<s> void <ISA_LIT>TargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known = KnownBits :: commonBits ( Known , Known2 ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Subtarget -> isTargetILP32 ( ) ) break ; Known . Zero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; break ; } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . Zero |= APInt ( Known . getBitWidth ( ) , <NUM_LIT> ) ; break ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) ;


<s> static void packImageA16AddressToDwords ( MachineIRBuilder & B , MachineInstr & MI , SmallVectorImpl < Register > & PackedAddrs , int AddrIdx , int DimIdx , int NumVAddrs , int NumGradients ) { const LLT S16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT V2S16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( int I = AddrIdx ; I < AddrIdx + NumVAddrs ; ++ I ) { Register AddrReg = MI . getOperand ( I ) . getReg ( ) ; if ( I < DimIdx ) { AddrReg = B . buildBitcast ( V2S16 , AddrReg ) . getReg ( <NUM_LIT> ) ; PackedAddrs . push_back ( AddrReg ) ; } else { if ( ( ( I + <NUM_LIT> ) >= ( AddrIdx + NumVAddrs ) ) || ( ( NumGradients / <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> && ( I == DimIdx + ( NumGradients / <NUM_LIT> ) - <NUM_LIT> || I == DimIdx + NumGradients - <NUM_LIT> ) ) ) { PackedAddrs . push_back ( B . buildBuildVector ( V2S16 , { AddrReg , B . buildUndef ( S16 ) . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ;

const MCExpr * Expr = MO . getExpr ( ) ;


<s> const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ;

bool IsThreadLocal = GVar && GVar -> isThreadLocal ( ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; maxStoresPerMemset = maxStoresPerMemsetOptSize = <NUM_LIT> ; maxStoresPerMemmove = maxStoresPerMemmoveOptSize = maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = <NUM_LIT> ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setMinFunctionAlignment ( <NUM_LIT> ) ;


<s> if ( ! isMemory ( ) || ! Memory . OffsetRegNum || Memory . isNegative || Memory . ShiftType != <STR_LIT> || Memory . ShiftImm != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; return true ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & F ) const override {


<s> static int pa_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; unsigned int max_arg_words = <NUM_LIT> ; unsigned int offset = <NUM_LIT> ; if ( ! TARGET_64BIT ) return <NUM_LIT> ;

if ( pa_function_arg_size ( arg . mode , arg . type ) > <NUM_LIT> && ( cum -> words & <NUM_LIT> ) ) offset = <NUM_LIT> ;


<s> ArgVRegs . push_back ( Arg . Regs [ <NUM_LIT> ] ) ; auto <ISA_LIT>Ty = GR -> getOrCreate<ISA_LIT>Type ( Arg . Ty , MIRBuilder ) ; GR -> assign<ISA_LIT>TypeToVReg ( <ISA_LIT>Ty , Arg . Regs [ <NUM_LIT> ] , MIRBuilder . getMF ( ) ) ; } bool Result = generateOpenCLBuiltinCall ( DoubleUnderscore ? FuncName : DemangledName , MIRBuilder , ResVReg , Info . OrigRet . Ty , ArgVRegs , GR ) ; free ( DemangledName ) ; return Result ; } llvm_unreachable ( <STR_LIT> ) ; } else { free ( DemangledName ) ; if ( Info . Callee . isGlobal ( ) ) { const Function * CF = cast < const Function > ( Info . Callee . getGlobal ( ) ) ; Register FuncVReg ; if ( CF -> isDeclaration ( ) && ( GR -> find ( CF , & MIRBuilder . getMF ( ) , FuncVReg ) == false ) ) { MachineIRBuilder FirstBlockBuilder ; FirstBlockBuilder . setMF ( MF ) ; FirstBlockBuilder . setMBB ( * MF . getBlockNumbered ( <NUM_LIT> ) ) ; SmallVector < ArrayRef < Register > , <NUM_LIT> > VRegArgs ; SmallVector < SmallVector < Register , <NUM_LIT> > , <NUM_LIT> > ToInsert ; for ( const Argument & Arg : CF -> args ( ) ) { if ( MIRBuilder . getDataLayout ( ) . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ToInsert . push_back ( { MIRBuilder . getMRI ( ) -> createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ) ; VRegArgs . push_back ( ToInsert . back ( ) ) ; } FunctionLoweringInfo FuncInfo ; lowerFormalArguments ( FirstBlockBuilder , * CF , VRegArgs , FuncInfo ) ; } FTy = getOriginalFunctionType ( * CF ) ; } if ( ! ResVReg . isValid ( ) ) { ResVReg = MIRBuilder . getMRI ( ) -> createVirtualRegister ( & <STR_LIT> ) ; } <ISA_LIT>Type * RetType = GR -> assignTypeToVReg ( FTy -> getReturnType ( ) , ResVReg , MIRBuilder ) ; auto MIB = MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( ResVReg ) . addUse ( GR -> get<ISA_LIT>TypeID ( RetType ) ) . add ( Info . Callee ) ; for ( const auto & arg : Info . OrigArgs ) { assert ( arg . Regs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MIB . addUse ( arg . Regs [ <NUM_LIT> ] ) ; } const auto & STI = MF . getSubtarget ( ) ; return MIB . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ;


<s> static int insn_uid_get_clock ( int uid ) { return INSN_INFO_ENTRY ( uid ) . clock ;


<s> JCE . startGVStub ( GV , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitWordLE ( ( unsigned ) ( intptr_t ) ptr ) ; JCE . emitWordLE ( ( unsigned ) ( ( ( intptr_t ) ptr ) >> <NUM_LIT> ) ) ; JCE . startGVStub ( GV , <NUM_LIT> , <NUM_LIT> ) ; JCE . emitWordLE ( ( intptr_t ) ptr ) ;


<s> void <ISA_LIT>DebugValueManager :: move ( MachineInstr * Insert ) { MachineBasicBlock * MBB = Insert -> getParent ( ) ;

for ( MachineInstr * DBI : reverse ( DbgValues ) ) MBB -> splice ( Insert , DBI -> getParent ( ) , DBI ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;

return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> return new <ISA_LIT>InstructionSelector ( TM , Subtarget , RBI ) ;


<s> if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> if ( old_tree != target_option_current_node ) new_tree = target_option_current_node ; else new_tree = NULL_TREE ; } else { new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; } if ( TARGET_DEBUG_TARGET ) { if ( new_tree ) { fprintf ( stderr , <STR_LIT> ) ; debug_tree ( new_tree ) ; } if ( old_tree ) { fprintf ( stderr , <STR_LIT> ) ; debug_tree ( old_tree ) ; }

if ( old_tree != NULL_TREE || new_tree != NULL_TREE ) fprintf ( stderr , <STR_LIT> ) ;


<s> addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ;

if ( EnableCommGEP ) addPass ( create<ISA_LIT>CommonGEP ( ) ) ;


<s> case PCALL_INDIRECT_i64 : return CALL_INDIRECT_i64 ; case PCALL_INDIRECT_f32 : return CALL_INDIRECT_f32 ; case PCALL_INDIRECT_f64 : return CALL_INDIRECT_f64 ; case PCALL_INDIRECT_v16i8 : return CALL_INDIRECT_v16i8 ; case PCALL_INDIRECT_v8i16 : return CALL_INDIRECT_v8i16 ; case PCALL_INDIRECT_v4i32 : return CALL_INDIRECT_v4i32 ; case PCALL_INDIRECT_v2i64 : return CALL_INDIRECT_v2i64 ;


<s> MachineInstr * CPEMI = U . CPEMI ; if ( CPEIsInRange ( UserMI , UserOffset , CPEMI , U . MaxDisp , U . NegOk , true ) ) { DOUT << <STR_LIT> ; return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ;

if ( CPEIsInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . MaxDisp , U . NegOk ) ) {


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) -> getTargetLowering ( ) ;


<s> LiveIntervals & LIs = G . getMetadata ( ) . LIS ; if ( Chains . count ( Ra ) ) { if ( Rd != Ra ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Ra , & TRI ) << <STR_LIT> << PrintReg ( Rd , & TRI ) << '\n' ; ) ; Chains . remove ( Ra ) ; Chains . insert ( Rd ) ; } } else { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Rd , & TRI ) << '\n' ; ) ; Chains . insert ( Rd ) ; } PBQPRAGraph :: NodeId node1 = G . getMetadata ( ) . getNodeIdForVReg ( Rd ) ; const LiveInterval & ld = LIs . getInterval ( Rd ) ; for ( auto r : Chains ) { if ( r == Rd ) continue ; const LiveInterval & lr = LIs . getInterval ( r ) ; if ( ld . overlaps ( lr ) ) { const PBQPRAGraph :: NodeMetadata :: OptionToRegMap * vRdAllowed = & G . getNodeMetadata ( node1 ) . getOptionRegs ( ) ; PBQPRAGraph :: NodeId node2 = G . getMetadata ( ) . getNodeIdForVReg ( r ) ; const PBQPRAGraph :: NodeMetadata :: OptionToRegMap * vRrAllowed = & G . getNodeMetadata ( node2 ) . getOptionRegs ( ) ; PBQPRAGraph :: EdgeId edge = G . findEdge ( node1 , node2 ) ; assert ( edge != G . invalidEdgeId ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( G . getEdgeNode1Id ( edge ) == node2 ) { std :: swap ( node1 , node2 ) ; std :: swap ( vRdAllowed , vRrAllowed ) ; }

PBQP :: Matrix costs ( G . getEdgeCosts ( edge ) ) ;


<s> MCOperand <ISA_LIT>AsmPrinter :: GetSymbolRef ( const MCSymbol * Symbol ) { const MCExpr * Expr ; Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ;

return MCOperand :: createExpr ( Expr ) ;


<s> else if ( Op . isImm ( ) ) O << formatImm ( ( int64_t ) Op . getImm ( ) ) ; else if ( Op . isDFPImm ( ) ) O << formatImm ( ( double ) Op . getDFPImm ( ) ) ; else if ( Op . isExpr ( ) ) printExpr ( Op . getExpr ( ) , O ) ;


<s> WidenedLoad ( SmallVectorImpl < LoadInst * > & Lds , LoadInst * Wide ) : NewLd ( Wide ) { append_range ( Loads , Lds ) ;


<s> return __builtin_mve_vcvtpq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __p ) ;


<s> static bool getMRCDeprecationInfo ( MCInst & MI , const MCSubtargetInfo & STI , std :: string & Info ) { if ( STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && ( ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) ) { Info = <STR_LIT> <STR_LIT> ; return true ; }


<s> } int64_t Int ; Int = StringSwitch < int64_t > ( Value ) . Case ( <STR_LIT> , DstUnused :: UNUSED_PAD ) . Case ( <STR_LIT> , DstUnused :: UNUSED_SEXT ) . Case ( <STR_LIT> , DstUnused :: UNUSED_PRESERVE ) . Default ( <NUM_LIT> ) ; if ( Int == <NUM_LIT> ) { return MatchOperand_ParseFail ; }

Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , Int , S , <ISA_LIT>Operand :: ImmTySdwaDstUnused ) ) ;


<s> Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Result ) ; } if ( isGlobalStubReference ( OpFlag ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result ;


<s> static machine_mode rs6000_translate_mode_attribute ( machine_mode mode ) { if ( ( FLOAT128_IEEE_P ( mode ) && ieee128_float_type_node == long_double_type_node ) || ( FLOAT128_IBM_P ( mode ) && ibm128_float_type_node == long_double_type_node ) ) return COMPLEX_MODE_P ( mode ) ? E_TCmode : E_TFmode ;


<s> static machine_mode promote_return ( machine_mode mode ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ; return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : if ( Subtarget -> isTargetWindows ( ) ) return LowerDIV_Windows ( Op , DAG , false ) ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) , N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> && N0 -> getOpcode ( ) == <STR_LIT> && N1 -> getOpcode ( ) == <STR_LIT> ) { SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 -> getOperand ( <NUM_LIT> ) ; EVT N00VT = N00 . getValueType ( ) ; if ( N00VT == N10 . getValueType ( ) && ( N00VT == <STR_LIT> || N00VT == <STR_LIT> ) && N00VT . getScalarSizeInBits ( ) == <NUM_LIT> * VT . getScalarSizeInBits ( ) ) { MVT MidVT = ( N00VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ( MidVT . getVectorNumElements ( ) ) ; for ( size_t i = <NUM_LIT> ; i < Mask . size ( ) ; ++ i ) Mask [ i ] = i * <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( MidVT , dl , DAG . getNode ( <STR_LIT> , dl , MidVT , N00 ) , DAG . getNode ( <STR_LIT> , dl , MidVT , N10 ) , Mask ) ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( N0 == N1 && VT . getVectorNumElements ( ) == <NUM_LIT> ) { assert ( VT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidenVector ( N0 , DAG ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } if ( N1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue RHS = N1 -> getOperand ( <NUM_LIT> ) ; MVT RHSTy = RHS . getValueType ( ) . getSimpleVT ( ) ; if ( ! RHSTy . isVector ( ) ) return SDValue ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; MVT ConcatTy = <STR_LIT> ( RHSTy . getVectorElementType ( ) , RHSTy . getVectorNumElements ( ) * <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , ConcatTy , DAG . getNode ( <STR_LIT> , dl , RHSTy , N0 ) , RHS ) ) ;


<s> void <ISA_LIT>InstPrinter :: printLiteral ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {

const MCOperand & Op = MI -> getOperand ( OpNo ) ;


<s> } } if ( In . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Srl = In . getOperand ( <NUM_LIT> ) ; if ( Srl . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * ShiftAmt = dyn_cast < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftAmt -> getZExtValue ( ) == <NUM_LIT> ) { Out = stripBitcast ( Srl . getOperand ( <NUM_LIT> ) ) ; return true ; }


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ;


<s> unsigned GCNTTIImpl :: getMaxInterleaveFactor ( unsigned VF ) {

if ( VF == <NUM_LIT> ) return <NUM_LIT> ;


<s> return has_func_attr ( decl , <STR_LIT> ) || has_func_attr ( decl , <STR_LIT> ) ;


<s> if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize , <STR_LIT> , MachineInstr :: NoFlags ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) + ArgRegsSaveSize ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) ; } else { unsigned ScratchRegister = <STR_LIT> ; bool HasFP = hasFP ( MF ) ; for ( auto & I : MFI . getCalleeSavedInfo ( ) ) { unsigned Reg = I . getReg ( ) ; if ( is<ISA_LIT>LowRegister ( Reg ) && ! ( HasFP && Reg == FramePtr ) ) { ScratchRegister = Reg ; break ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != & * MBBI && std :: prev ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = std :: prev ( MBBI ) ; if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * PMBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes , ScratchRegister , MachineInstr :: NoFlags ) ; } else if ( ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitPrologueEpilogueSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes , ScratchRegister , MachineInstr :: NoFlags ) ; } } if ( needPopSpecialFixUp ( MF ) ) { bool Done = emitPopSpecialFixUp ( MBB , true ) ; ( void ) Done ;


<s> return <STR_LIT> ( SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc , BaseLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; BaseLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return nullptr ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return nullptr ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . parseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) {


<s> if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isMSVCEHPersonality ( Personality ) ) return false ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; auto * MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; std :: unique_ptr < WinEHFuncInfo > FuncInfoPtr ; if ( ! MMI ) FuncInfoPtr . reset ( new WinEHFuncInfo ( ) ) ; WinEHFuncInfo & FuncInfo = * ( MMI ? & MMI -> getWinEHFuncInfo ( & F ) : FuncInfoPtr . get ( ) ) ; switch ( Personality ) { default : llvm_unreachable ( <STR_LIT> ) ; case EHPersonality :: MSVC_CXX : addCXXStateStores ( F , FuncInfo ) ; break ; case EHPersonality :: MSVC_<ISA_LIT>SEH : addSEHStateStores ( F , FuncInfo ) ; break ; } PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; return true ;


<s> StringRef getPassName ( ) const override {


<s> if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( HasMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( HasNoMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) {


<s> const MCOperand & MO = MI . getOperand ( Op ) ; uint32_t v = ~ MO . getImm ( ) ; uint32_t lsb = CountTrailingZeros_32 ( v ) ;

uint32_t msb = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - <NUM_LIT> ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , STI ( TM . getMCSubtargetInfo ( ) ) {


<s> if ( isOneConstant ( Other ) && isOverflowIntrOpRes ( Sel ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Sel -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; <STR_LIT> CC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Sel . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ;

<STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand ( <NUM_LIT> ) ) -> get ( ) ;


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) { APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedElts = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( TLI . SimplifyDemandedVectorElts ( Src , DemandedElts , KnownUndef , KnownZero , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( IsStrict ) return SDValue ( ) ; if ( <STR_LIT> ( Src . getNode ( ) ) && Src . hasOneUse ( ) ) { LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( SDValue VZLoad = narrowLoadToVZLoad ( LN , <STR_LIT> , <STR_LIT> , DAG ) ) { SDLoc dl ( N ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ;

DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const {


<s> static inline int startswith ( const char * str , const char * prefix ) { return strncmp ( str , prefix , strlen ( prefix ) ) == <NUM_LIT> ;


<s> const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : { SDValue Src0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != <STR_LIT> ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == <STR_LIT> ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == <STR_LIT> ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ;

SmallVector < SDValue , <NUM_LIT> > Ops = { Src0 , Src1 , Src2 } ;


<s> case <NUM_LIT> : align = <NUM_LIT> ; break ; default : return MCDisassembler :: Fail ; } break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> IRB . CreateUnreachable ( ) ; IRB . SetInsertPoint ( Tail ) ; } Value * Cmp = IRB . CreateICmpEQ ( Threw , getAddrSizeInt ( & M , <NUM_LIT> ) , <STR_LIT> ) ; IRB . CreateCondBr ( Cmp , II -> getUnwindDest ( ) , II -> getNormalDest ( ) ) ; } else { SmallVector < Value * , <NUM_LIT> > Args ( II -> args ( ) ) ; CallInst * NewCall = IRB . CreateCall ( II -> getFunctionType ( ) , II -> getCalledOperand ( ) , Args ) ; NewCall -> takeName ( II ) ; NewCall -> setCallingConv ( II -> getCallingConv ( ) ) ; NewCall -> setDebugLoc ( II -> getDebugLoc ( ) ) ; NewCall -> setAttributes ( II -> getAttributes ( ) ) ; II -> replaceAllUsesWith ( NewCall ) ; ToErase . push_back ( II ) ; IRB . CreateBr ( II -> getNormalDest ( ) ) ; II -> getUnwindDest ( ) -> removePredecessor ( & BB ) ; } } for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { auto * RI = dyn_cast < ResumeInst > ( & I ) ; if ( ! RI ) continue ; Changed = true ; Value * Input = RI -> getValue ( ) ; IRB . SetInsertPoint ( RI ) ; Value * Low = IRB . CreateExtractValue ( Input , <NUM_LIT> , <STR_LIT> ) ; IRB . CreateCall ( ResumeF , { Low } ) ; IRB . CreateUnreachable ( ) ; ToErase . push_back ( RI ) ; } } for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { auto * CI = dyn_cast < CallInst > ( & I ) ; if ( ! CI ) continue ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee ) continue ; if ( Callee -> getIntrinsicID ( ) != <STR_LIT> ) continue ; Changed = true ; IRB . SetInsertPoint ( CI ) ; CallInst * NewCI = IRB . CreateCall ( EHTypeIDF , CI -> getArgOperand ( <NUM_LIT> ) , <STR_LIT> ) ; CI -> replaceAllUsesWith ( NewCI ) ; ToErase . push_back ( CI ) ;


<s> int regalign = <NUM_LIT> ; gimple * stmt ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { t = rs6000_gimplify_va_arg ( valist , ptrtype , pre_p , post_p ) ; return build_va_arg_indirect_ref ( t ) ; } if ( ( ( TARGET_MACHO && rs6000_darwin64_abi ) || DEFAULT_ABI == ABI_ELFv2 || ( DEFAULT_ABI == ABI_AIX && ! rs6000_compat_align_parm ) ) && integer_zerop ( TYPE_SIZE ( type ) ) ) { unsigned HOST_WIDE_INT align , boundary ; tree valist_tmp = get_initialized_tmp_var ( valist , pre_p , NULL ) ; align = PARM_BOUNDARY / BITS_PER_UNIT ; boundary = rs6000_function_arg_boundary ( TYPE_MODE ( type ) , type ) ; if ( boundary > MAX_SUPPORTED_STACK_ALIGNMENT ) boundary = MAX_SUPPORTED_STACK_ALIGNMENT ; boundary /= BITS_PER_UNIT ; if ( boundary > align ) { tree t ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - <NUM_LIT> ) ) ; gimplify_and_add ( t , pre_p ) ; t = fold_convert ( sizetype , valist_tmp ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_convert ( TREE_TYPE ( valist ) , fold_build2 ( BIT_AND_EXPR , sizetype , t , size_int ( - boundary ) ) ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; gimplify_and_add ( t , pre_p ) ; } valist_tmp = fold_convert ( build_pointer_type ( type ) , valist_tmp ) ; return build_va_arg_indirect_ref ( valist_tmp ) ; } if ( DEFAULT_ABI != ABI_V4 ) { if ( targetm . calls . split_complex_arg && TREE_CODE ( type ) == COMPLEX_TYPE ) { tree elem_type = TREE_TYPE ( type ) ; machine_mode elem_mode = TYPE_MODE ( elem_type ) ; int elem_size = GET_MODE_SIZE ( elem_mode ) ; if ( elem_size < UNITS_PER_WORD ) { tree real_part , imag_part ; gimple_seq post = NULL ; real_part = rs6000_gimplify_va_arg ( valist , elem_type , pre_p , & post ) ; real_part = get_initialized_tmp_var ( real_part , pre_p , & post ) ; gimple_seq_add_seq ( pre_p , post ) ; imag_part = rs6000_gimplify_va_arg ( valist , elem_type , pre_p , post_p ) ; return build2 ( COMPLEX_EXPR , type , real_part , imag_part ) ; } } return std_gimplify_va_arg_expr ( valist , type , pre_p , post_p ) ; } f_gpr = TYPE_FIELDS ( TREE_TYPE ( va_list_type_node ) ) ; f_fpr = DECL_CHAIN ( f_gpr ) ; f_res = DECL_CHAIN ( f_fpr ) ;


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const {

return getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ;


<s> while ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; NumBytes -= <NUM_LIT> ; } assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; if ( HasFP ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , FPOffset , TII , MachineInstr :: FrameSetup ) ; } AFI -> setLocalStackSize ( NumBytes ) ; if ( NumBytes ) { if ( ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; } if ( RegInfo -> hasBasePointer ( MF ) ) TII -> copyPhysReg ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , false ) ; if ( needsFrameMoves ) { const DataLayout * TD = MF . getSubtarget ( ) . getDataLayout ( ) ; const int StackGrowth = - TD -> getPointerSize ( <NUM_LIT> ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( HasFP ) { unsigned Reg = RegInfo -> getDwarfRegNum ( FramePtr , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> * StackGrowth ) ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOp , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = <NUM_LIT> ; IsKill = true ; }

MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false , IsKill ) ;


<s> if ( ! fp_consts_inited ) init_fp_table ( ) ;

for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( REAL_VALUES_EQUAL ( * r , values_fp [ i ] ) ) return strings_fp [ i ] ;


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ;


<s> name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = i386_pe_strip_name_encoding_full ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = <STR_LIT> ; else if ( decl_readonly_section ( decl , reloc ) ) prefix = <STR_LIT> ; else prefix = <STR_LIT> ; len = strlen ( name ) + strlen ( prefix ) ; string = alloca ( len + <NUM_LIT> ) ; sprintf ( string , <STR_LIT> , prefix , name ) ;

DECL_SECTION_NAME ( decl ) = build_string ( len , string ) ;


<s> int arg1 = <NUM_LIT> ; int arg2 = <NUM_LIT> ; int arg1sz = <NUM_LIT> ; machine_mode arg0mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; machine_mode arg1mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; machine_mode arg2mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; int expand_mpy = startswith ( helper_name , <STR_LIT> ) ; gcc_assert ( ! ( expand_mpy && const_variants ) ) ; if ( arg1mode != VOIDmode && arg2mode != VOIDmode ) gcc_assert ( arg1mode == arg2mode ) ; if ( arg1mode == VOIDmode ) arg1mode = arg0mode ; if ( arg2mode == VOIDmode ) arg2mode = arg0mode ; if ( arg1mode == SImode ) { arg2 = <NUM_LIT> ; arg1sz = <NUM_LIT> ; } else if ( arg1mode == DImode ) { arg1 = <NUM_LIT> ; arg1sz = <NUM_LIT> ; arg2 = <NUM_LIT> ; } if ( const_variants && CONST_INT_P ( operands [ <NUM_LIT> ] ) && INTVAL ( operands [ <NUM_LIT> ] ) >= <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) <= <NUM_LIT> ) { int len = strlen ( helper_name ) + <NUM_LIT> ; helper_const = ( char * ) xmalloc ( len ) ; snprintf ( helper_const , len , <STR_LIT> , helper_name , ( int ) INTVAL ( operands [ <NUM_LIT> ] ) ) ; } emit_move_insn ( gen_rtx_REG ( arg1mode , arg1 ) , operands [ <NUM_LIT> ] ) ; if ( ! helper_const ) emit_move_insn ( gen_rtx_REG ( arg2mode , arg2 ) , operands [ <NUM_LIT> ] ) ; if ( expand_mpy ) { if ( msp430_use_f5_series_hwmult ( ) ) fsym = gen_rtx_SYMBOL_REF ( VOIDmode , concat ( helper_name , <STR_LIT> , NULL ) ) ; else if ( msp430_use_32bit_hwmult ( ) ) { if ( arg1mode == HImode ) fsym = gen_rtx_SYMBOL_REF ( VOIDmode , concat ( helper_name , <STR_LIT> , NULL ) ) ; else fsym = gen_rtx_SYMBOL_REF ( VOIDmode , concat ( helper_name , <STR_LIT> , NULL ) ) ; } else if ( msp430_use_16bit_hwmult ( ) ) fsym = gen_rtx_SYMBOL_REF ( VOIDmode , concat ( helper_name , <STR_LIT> , NULL ) ) ; else fsym = gen_rtx_SYMBOL_REF ( VOIDmode , helper_name ) ; } else fsym = gen_rtx_SYMBOL_REF ( VOIDmode , helper_const ? helper_const : helper_name ) ; c = gen_call_value_internal ( gen_rtx_REG ( arg0mode , <NUM_LIT> ) , fsym , GEN_INT ( <NUM_LIT> ) ) ; c = emit_call_insn ( c ) ; RTL_CONST_CALL_P ( c ) = <NUM_LIT> ; fusage = NULL ; use_regs ( & fusage , arg1 , arg1sz ) ; if ( ! helper_const ) { if ( ! expand_mpy ) use_regs ( & fusage , arg2 , <NUM_LIT> ) ; else use_regs ( & fusage , arg2 , arg1sz ) ;


<s> MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Sym ) ; if ( const auto * FuncTy = dyn_cast < FunctionType > ( Global -> getValueType ( ) ) ) { const MachineFunction & MF = * MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const Function & CurrentFunc = * MF . getFunction ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; SmallVector < <STR_LIT> , <NUM_LIT> > Params ; <STR_LIT> iPTR = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAddr64 ( ) ? <STR_LIT> :: I64 : <STR_LIT> :: I32 ;

SmallVector < MVT , <NUM_LIT> > ResultMVTs ;


<s> bool <ISA_LIT>PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( ) ) ;


<s> const DebugLoc & DL = MI -> getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineBasicBlock * NewMBB = MF . CreateMachineBasicBlock ( MBB -> getBasicBlock ( ) ) ; MF . push_back ( NewMBB ) ; NewMBB -> setNumber ( MF . addToMBBNumbering ( NewMBB ) ) ; NewMBB -> moveAfter ( MBB ) ; NewMBB -> transferSuccessors ( MBB ) ; MBB -> addSuccessor ( NewMBB ) ; MachineBasicBlock :: iterator MBBI = MI ; ++ MBBI ; while ( MBBI != MBB -> end ( ) ) { MachineInstr * mi = MBBI ; MachineBasicBlock :: iterator NextMBBI = std :: next ( MBBI ) ; MBB -> remove ( mi ) ; NewMBB -> insert ( NewMBB -> end ( ) , mi ) ; MBBI = NextMBBI ; } NewMBB -> setIsLandingPad ( ) ; unsigned Reg = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MovOpc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , MI , DL , TII . get ( MovOpc ) , Reg ) . addMBB ( NewMBB ) ;


<s> return ( __m128i ) __builtin_ia32_cvtps2dq ( ( __v4sf ) __A ) ;


<s> static int get_reg ( enum ia64_frame_regs r ) {


<s> void <ISA_LIT>AsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + <STR_LIT> + Twine ( stackSize ) + <STR_LIT> + StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( returnReg ) ) . lower ( ) ) ;


<s> return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ;


<s> FunctionPass * create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) {

return new <ISA_LIT>DAGToDAGISel ( TM ) ;


<s> MCInst TmpInst ; TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , * this ) ) TmpInst . addOperand ( MCOp ) ;


<s> static SDValue PerformADDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) {

SDValue N0 = N -> getOperand ( <NUM_LIT> ) ;


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( AssemblerOptions . back ( ) -> isReorder ( ) ) { reportParseError ( <STR_LIT> ) ; return false ; } AssemblerOptions . back ( ) -> setNoMacro ( ) ; Parser . Lex ( ) ; return false ;


<s> } else if ( RI . hasVGPRs ( RC ) && ST . isVGPRSpillingEnabled ( MFI ) ) { switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; } } if ( Opcode != - <NUM_LIT> ) { unsigned Align = <NUM_LIT> ; FrameInfo -> setObjectAlignment ( FrameIndex , Align ) ; unsigned Size = FrameInfo -> getObjectSize ( FrameIndex ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addMemOperand ( MMO ) ; } else { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ;


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return SDValue ( ) ;

if ( Op . getValueType ( ) != <STR_LIT> ) return Op ;


<s> Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , dl , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ;


<s> static SDValue getAddrLocal ( SDValue Op , SelectionDAG & DAG , bool Has<ISA_LIT>64 ) { DebugLoc DL = Op . getDebugLoc ( ) ; EVT Ty = Op . getValueType ( ) ; unsigned GOTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , GetGlobalReg ( DAG , Ty ) , getTargetNode ( Op , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( Op , DAG , LoFlag ) ) ;

return DAG . getNode ( <STR_LIT> , DL , Ty , Load , Lo ) ;


<s> return ( __A [ <NUM_LIT> ] == __B [ <NUM_LIT> ] ) ;


<s> addr = XEXP ( orig_mem , <NUM_LIT> ) ; mem = gen_rtx_MEM ( DImode , align ) ; MEM_VOLATILE_P ( mem ) = MEM_VOLATILE_P ( orig_mem ) ; if ( MEM_ALIAS_SET ( orig_mem ) == ALIAS_SET_MEMORY_BARRIER ) set_mem_alias_set ( mem , ALIAS_SET_MEMORY_BARRIER ) ; alpha_pre_atomic_barrier ( model ) ; label = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , <NUM_LIT> ) ) ; emit_insn ( gen_load_locked ( DImode , scratch , mem ) ) ; width = GEN_INT ( GET_MODE_BITSIZE ( mode ) ) ;

mask = GEN_INT ( mode == QImode ? <NUM_LIT> : <NUM_LIT> ) ;


<s> else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ;

if ( DestReg ) MIB . addReg ( DestReg , RegState :: Define ) ;


<s> bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( TRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( SrcIsKill ) ) ; BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( TRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( SrcIsKill ) ) ; } else { BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) ; } MI . eraseFromParent ( ) ; I = NextMI ; continue ; } unsigned STOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII . get ( STOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; I = NextMI ;


<s> <ISA_LIT>AsmPrinter & Printer ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCOperand LowerSymbolOperand ( MCSymbol * Sym , int64_t Offset , bool IsFunc ) const ; public : <ISA_LIT>MCInstLower ( MCContext & ctx , <ISA_LIT>AsmPrinter & printer ) : Ctx ( ctx ) , Printer ( printer ) { }

void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ;


<s> unsigned R600InstrInfo :: getMaxAlusPerClause ( ) const {


<s> MCObjectWriter * llvm :: create<ISA_LIT>WinCOFFObjectWriter ( raw_ostream & OS , bool Is64Bit ) {

MCWinCOFFObjectTargetWriter * MOTW = new <ISA_LIT>WinCOFFObjectWriter ( Is64Bit ) ;


<s> OpFlag = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubNoDynamic ( ) ) { OpFlag = <STR_LIT> ; } SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ && ! Subtarget -> is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Result ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> addr = INTVAL ( x ) ; return ( TARGET_NORMAL_MODE || ( TARGET_H8300H && ( IN_RANGE ( addr , h1 , h2 ) || IN_RANGE ( addr , h3 , h4 ) ) ) || ( TARGET_H8300S && ( IN_RANGE ( addr , s1 , s2 ) || IN_RANGE ( addr , s3 , s4 ) ) ) ) ; case CONST : return TARGET_NORMAL_MODE ;


<s> if ( TREE_CODE ( exp ) == VAR_DECL ) { int is_const ; if ( ! TREE_READONLY ( exp ) || TREE_SIDE_EFFECTS ( exp ) || ! DECL_INITIAL ( exp ) || ( DECL_INITIAL ( exp ) != error_mark_node && ! TREE_CONSTANT ( DECL_INITIAL ( exp ) ) ) ) is_const = FALSE ; else is_const = TRUE ; switch ( v850_get_data_area ( exp ) ) { case DATA_AREA_ZDA : if ( is_const ) rozdata_section ( ) ; else zdata_section ( ) ;


<s> if ( VectorList . ElementKind != ElementKind ) return false ; return VectorList . NumElements == NumElements ;


<s> printRegName ( O , MRI . getSubReg ( AddrReg , <STR_LIT> ) ) ; O << <STR_LIT> ; printRegName ( O , MRI . getSubReg ( AddrReg , <STR_LIT> ) ) ; O << <STR_LIT> ;


<s> initialize<ISA_LIT>FixVGPRCopiesPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> SDValue Chain = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ; SDValue InFlag ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

unsigned Flags = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) . useLongCalls ( ) ? <STR_LIT> | <STR_LIT> : <STR_LIT> ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; bool HasFP = hasFP ( MF ) ; if ( CallConv == CallingConv :: <ISA_LIT>_INTR ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( CallConv == CallingConv :: <ISA_LIT>_INTR || CallConv == CallingConv :: <ISA_LIT>_SIGNAL ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! HasFP ) { return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineFunction :: iterator I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ;


<s> enum sched_fusion_type fusion = SCHED_FUSION_LD ; gcc_assert ( INSN_P ( insn ) ) ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return SCHED_FUSION_NONE ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; machine_mode dest_mode = GET_MODE ( dest ) ; if ( ! aarch64_mode_valid_for_sched_fusion_p ( dest_mode ) ) return SCHED_FUSION_NONE ; if ( GET_CODE ( src ) == SIGN_EXTEND ) { fusion = SCHED_FUSION_LD_SIGN_EXTEND ; src = XEXP ( src , <NUM_LIT> ) ;

if ( ! MEM_P ( src ) || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ;


<s> case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( ) ; default : return true ; }


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> void arm_asm_declare_function_name ( FILE * file , const char * name , tree decl ) { size_t cmse_name_len ; char * cmse_name = <NUM_LIT> ; char cmse_prefix [ ] = <STR_LIT> ; if ( use_cmse && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) { cmse_name_len = sizeof ( cmse_prefix ) + strlen ( name ) ; cmse_name = XALLOCAVEC ( char , cmse_name_len ) ;

snprintf ( cmse_name , cmse_name_len , <STR_LIT> , cmse_prefix , name ) ;


<s> CommonTTI . getUnrollingPreferences ( L , SE , UP ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_ostream & OS , uint32_t CPUType , uint32_t CPUSubtype ) {

return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( CPUType , CPUSubtype ) , OS , true ) ;


<s> bool <ISA_LIT>PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ;

auto * TPC = & getAnalysis < TargetPassConfig > ( ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ;


<s> static const RegClassWeight RCWeightTable [ ] = { { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ;

return RCWeightTable [ RC -> getID ( ) ] ;


<s> unsigned Vd = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ;

return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MachineOperand & Addr = MI . getOperand ( <NUM_LIT> ) ; if ( isStore ) BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( ValueReg ) ; unsigned opcode = isStore ? <STR_LIT> : <STR_LIT> ; auto Builder = BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( opcode ) ) . addReg ( <STR_LIT> , getDefRegState ( ! isStore ) ) ; if ( Addr . isGlobal ( ) ) Builder . addGlobalAddress ( Addr . getGlobal ( ) , Addr . getOffset ( ) ) ; else if ( Addr . isImm ( ) ) Builder . addImm ( Addr . getImm ( ) ) ; Builder . cloneMemRefs ( MI ) ; MachineInstr * New = Builder ;

if ( ! isStore ) New = BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , ValueReg ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) ;


<s> ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ;


<s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { N -> dump ( ) ; ConstantSDNode * True , * False ; if ( ( True = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) && ( False = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) && True -> isAllOnesValue ( ) && False -> isNullValue ( ) && VT == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; }


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) {


<s> if ( GET_CODE ( rhs ) == UNSPEC && XINT ( rhs , <NUM_LIT> ) == UNSPEC_PIC_BASE ) return TRUE ; if ( GET_CODE ( rhs ) == MEM && GET_CODE ( XEXP ( rhs , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( rhs , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PIC_BASE ) return TRUE ; }


<s> for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) nregs ++ ; return nregs ;


<s> basic_block * bbs = get_loop_body ( loop ) ; int nbbs = loop -> num_nodes ; int vec_cost = data -> cost [ vect_body ] , not_vec_cost = <NUM_LIT> ; int i , density_pct ; for ( i = <NUM_LIT> ; i < nbbs ; i ++ ) { basic_block bb = bbs [ i ] ; gimple_stmt_iterator gsi ; for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { gimple stmt = gsi_stmt ( gsi ) ; stmt_vec_info stmt_info = vinfo_for_stmt ( stmt ) ; if ( ! STMT_VINFO_RELEVANT_P ( stmt_info ) && ! STMT_VINFO_IN_PATTERN_P ( stmt_info ) ) not_vec_cost ++ ; } }


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) {


<s> <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ;

Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;