<s> if ( nds32_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict ) && nds32_legitimate_index_p ( mode , XEXP ( x , <NUM_LIT> ) , strict ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return true ; else if ( nds32_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict ) && nds32_legitimate_index_p ( mode , XEXP ( x , <NUM_LIT> ) , strict ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return true ; } if ( GET_CODE ( x ) != REG && GET_CODE ( x ) != SYMBOL_REF && GET_CODE ( x ) != CONST ) return false ; } switch ( GET_CODE ( x ) ) { case REG : return nds32_address_register_rtx_p ( x , strict ) ; case SYMBOL_REF : if ( TARGET_CMODEL_LARGE && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; if ( TARGET_CMODEL_MEDIUM && NDS32_SYMBOL_REF_RODATA_P ( x ) && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; return true ; case CONST : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) { rtx plus_op = XEXP ( x , <NUM_LIT> ) ; rtx op0 = XEXP ( plus_op , <NUM_LIT> ) ; rtx op1 = XEXP ( plus_op , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == SYMBOL_REF && CONST_INT_P ( op1 ) ) { if ( TARGET_CMODEL_LARGE && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; if ( TARGET_CMODEL_MEDIUM && NDS32_SYMBOL_REF_RODATA_P ( op0 ) && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; return true ; }


<s> case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; assert ( VA . getValVT ( ) != <STR_LIT> && <STR_LIT> ) ; int index = ArgLocs [ i ] . getValNo ( ) ; if ( index != lastInsIndex ) { <STR_LIT> Flags = Ins [ index ] . Flags ; if ( Flags . isByVal ( ) ) { unsigned VARegSize , VARegSaveSize ; computeRegArea ( CCInfo , MF , VARegSize , VARegSaveSize ) ; VarArgStyleRegisters ( CCInfo , DAG , dl , Chain , <NUM_LIT> ) ; unsigned Bytes = Flags . getByValSize ( ) - VARegSize ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , false ) ; InVals . push_back ( DAG . getFrameIndex ( FI , getPointerTy ( ) ) ) ; } else { int FI = MFI -> CreateFixedObject ( VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } lastInsIndex = index ; }


<s> OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy == MatchOperand_Success ) return false ; if ( ResTy == MatchOperand_ParseFail ) return true ; SMLoc S , E ; switch ( getLexer ( ) . getKind ( ) ) { default : { SMLoc S = getLoc ( ) ; const MCExpr * Expr ; if ( parseSymbolicImmVal ( Expr ) ) return Error ( S , <STR_LIT> ) ; SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Expr , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseVectorList ( Operands ) ; case AsmToken :: Identifier : { if ( isCondCode ) return parseCondCode ( Operands , invertCondCode ) ; if ( ! parseRegister ( Operands ) ) return false ; if ( ! parseOptionalShift ( Operands ) ) return false ; if ( ! parseOptionalExtend ( Operands ) ) return false ;


<s> return true ; } return false ; } case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizeImplicitArgPtr ( MI , MRI , B ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizeFDIVFastIntrin ( MI , MRI , B ) ; case <STR_LIT> : return legalizeIsAddrSpace ( MI , MRI , B , <ISA_LIT>AS :: LOCAL_ADDRESS ) ; case <STR_LIT> : return legalizeIsAddrSpace ( MI , MRI , B , <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; case <STR_LIT> : { B . setInstr ( MI ) ; B . buildConstant ( MI . getOperand ( <NUM_LIT> ) , ST . getWavefrontSize ( ) ) ; MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : return legalizeRawBufferStore ( MI , MRI , B , false ) ; case <STR_LIT> : return legalizeRawBufferStore ( MI , MRI , B , true ) ; case <STR_LIT> : return legalizeAtomicIncDec ( MI , B , true ) ;


<s> CombinerHelper Helper ( Observer , B ) ; <ISA_LIT>GenPostLegalizerLoweringHelper Generated ( GeneratedRuleCfg ) ; return Generated . tryCombineAll ( Observer , MI , B , Helper ) ;


<s> if ( VT . isVector ( ) && VT . getVectorNumElements ( ) > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; } SDValue Ret = AMDGPUTargetLowering :: LowerSTORE ( Op , DAG ) ; if ( Ret . getNode ( ) ) return Ret ; if ( VT . isVector ( ) && VT . getVectorNumElements ( ) >= <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; if ( VT == <STR_LIT> ) return DAG . getTruncStore ( Store -> getChain ( ) , DL , DAG . getSExtOrTrunc ( Store -> getValue ( ) , DL , <STR_LIT> ) , Store -> getBasePtr ( ) , <STR_LIT> , Store -> getMemOperand ( ) ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>leTarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>beTarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Z ( getTheARM64Target ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: msp430 > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> int RegNodeEscapeIndex = escapeRegNode ( F ) ; FuncInfo . EHRegNodeEscapeIndex = RegNodeEscapeIndex ; calculateSEHStateNumbers ( & F , FuncInfo ) ; addStateStoresToFunclet ( RegNode , FuncInfo , F , - <NUM_LIT> ) ;


<s> xops [ <NUM_LIT> ] = gen_rtx_MEM ( Pmode , gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; SYMBOL_REF_FLAGS ( xops [ <NUM_LIT> ] ) |= SYMBOL_FLAG_LOCAL ; output_asm_insn ( <STR_LIT> , xops ) ; return <STR_LIT> ; } xops [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , GOT_SYMBOL_NAME ) ; if ( ! flag_pic ) { if ( TARGET_MACHO ) gcc_unreachable ( ) ; xops [ <NUM_LIT> ] = gen_rtx_LABEL_REF ( Pmode , label ? label : gen_label_rtx ( ) ) ; output_asm_insn ( <STR_LIT> , xops ) ;

targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( XEXP ( xops [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ;


<s> static SDValue combineLogicBlendIntoPBLENDV ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( ( VT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) ) return SDValue ( ) ; SDValue X , Y , Mask ; if ( ! matchLogicBlend ( N , X , Y , Mask ) ) return SDValue ( ) ; Mask = peekThroughBitcasts ( Mask ) ; X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getScalarSizeInBits ( ) ; if ( ! MaskVT . isInteger ( ) || DAG . ComputeNumSignBits ( Mask ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT && DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , MaskVT ) ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V ) { SDValue SubOp1 = DAG . getNode ( <STR_LIT> , DL , MaskVT , V , Mask ) ; SDValue SubOp2 = Mask ; if ( V == Y ) std :: swap ( SubOp1 , SubOp2 ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , MaskVT , SubOp1 , SubOp2 ) ; return DAG . getBitcast ( VT , Res ) ;


<s> if ( In . Flags . isInAlloca ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( In . Flags . isNest ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( In . Flags . isInConsecutiveRegs ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( In . Flags . isInConsecutiveRegsLast ( ) ) fail ( DL , DAG , <STR_LIT> ) ; InVals . push_back ( In . Used ? DAG . getNode ( <STR_LIT> , DL , In . VT , DAG . getTargetConstant ( InVals . size ( ) , DL , <STR_LIT> ) ) : DAG . getUNDEF ( In . VT ) ) ; MFI -> addParam ( In . VT ) ; } if ( IsVarArg ) { MVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; unsigned VarargVreg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( PtrVT ) ) ; MFI -> setVarargBufferVreg ( VarargVreg ) ; Chain = DAG . getCopyToReg ( Chain , DL , VarargVreg , DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetConstant ( Ins . size ( ) , DL , <STR_LIT> ) ) ) ; MFI -> addParam ( PtrVT ) ; } SmallVector < MVT , <NUM_LIT> > Params ; SmallVector < MVT , <NUM_LIT> > Results ; ComputeSignatureVTs ( MF . getFunction ( ) . getFunctionType ( ) , MF . getFunction ( ) , DAG . getTarget ( ) , Params , Results ) ; for ( MVT VT : Results ) MFI -> addResult ( VT ) ; assert ( MFI -> getParams ( ) . size ( ) == Params . size ( ) && std :: equal ( MFI -> getParams ( ) . begin ( ) , MFI -> getParams ( ) . end ( ) , Params . begin ( ) ) ) ;


<s> static bool is_lin256 ( const int * ar ) {


<s> FunctionPass * llvm :: create<ISA_LIT>EHRestoreStackPointer ( ) {

return new <ISA_LIT>EHRestoreStackPointer ( ) ;


<s> if ( baseOpcode == - <NUM_LIT> ) { return UNKNOWN ; } switch ( baseOpcode ) { default : return UNKNOWN ; case <STR_LIT> : return BUFFER_LOAD_OFFEN ; case <STR_LIT> : return BUFFER_LOAD_OFFSET ; case <STR_LIT> : return BUFFER_STORE_OFFEN ; case <STR_LIT> : return BUFFER_STORE_OFFSET ; case <STR_LIT> : return BUFFER_LOAD_OFFEN_exact ; case <STR_LIT> : return BUFFER_LOAD_OFFSET_exact ; case <STR_LIT> : return BUFFER_STORE_OFFEN_exact ; case <STR_LIT> : return BUFFER_STORE_OFFSET_exact ; } } switch ( Opc ) { default : return UNKNOWN ;


<s> CALL_ONCE_INITIALIZATION ( initializePassOnce ) ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ;


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV , <NUM_LIT> , TF ) ) ; } else { if ( ! Subtarget -> useConstIslands ( ) ) return <NUM_LIT> ; unsigned Align = DL . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ;


<s> gen_lvsl = gen_altivec_lvsl_reg_si ; } rtx tmp = gen_reg_rtx ( shift_mode ) ; idx = convert_modes ( shift_mode , idx_mode , idx , <NUM_LIT> ) ; emit_insn ( gen_ashl ( tmp , idx , GEN_INT ( shift ) ) ) ; if ( ! BYTES_BIG_ENDIAN ) emit_insn ( gen_add ( tmp , tmp , GEN_INT ( <NUM_LIT> ) ) ) ; else emit_insn ( gen_sub ( tmp , GEN_INT ( <NUM_LIT> - width ) , tmp ) ) ; rtx mask = gen_reg_rtx ( V16QImode ) ; rtx mask_v2di = gen_reg_rtx ( V2DImode ) ; rtvec v = rtvec_alloc ( <NUM_LIT> ) ; if ( ! BYTES_BIG_ENDIAN ) { RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , mode_mask ) ; } else { RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , mode_mask ) ; RTVEC_ELT ( v , <NUM_LIT> ) = gen_rtx_CONST_INT ( DImode , <NUM_LIT> ) ; } emit_insn ( gen_vec_initv2didi ( mask_v2di , gen_rtx_PARALLEL ( V2DImode , v ) ) ) ; rtx sub_mask = simplify_gen_subreg ( V16QImode , mask_v2di , V2DImode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( mask , sub_mask ) ) ; rtx tmp_val = gen_reg_rtx ( SImode ) ; if ( inner_mode == E_SFmode ) if ( TARGET_DIRECT_MOVE_64BIT ) emit_insn ( gen_movsi_from_sf ( tmp_val , val ) ) ; else { rtx stack = rs6000_allocate_stack_temp ( SFmode , false , true ) ;

emit_insn ( gen_movsf_hardfloat ( stack , val ) ) ;


<s> static Target The<ISA_LIT>BETarget ;


<s> if ( pFormat . hasGOTPLT ( ) ) reserveOne ( llvm :: ELF :: DT_PLTGOT ) ;


<s> assert ( ITState . CurPosition == <NUM_LIT> ) ; ITState . CurPosition = ~ <NUM_LIT> ; return ;


<s> return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


<s> unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MI -> getParent ( ) , MI , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( LiveMaskReg ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateContextImm ( int64_t Val , SMLoc S , SMLoc E , bool Is<ISA_LIT>64 ) { auto Op = make_unique < <ISA_LIT>Operand > ( ContextImmediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> Is<ISA_LIT>64 = Is<ISA_LIT>64 ;


<s> std :: vector < std :: string > mov_stepj0_a0h ( ) {

return D ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> void <ISA_LIT>MCExpr :: fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const {


<s> for ( unsigned i = <NUM_LIT> , e = NumStores ; i != e ; ++ i ) { if ( LoadValue == StoreValue [ i ] && LoadOffset == StoreOffset [ i ] ) return true ;


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; assert ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; if ( ST . hasApertureRegs ( ) ) { unsigned Offset = AS == <ISA_LIT>AS :: LOCAL_ADDRESS ? <STR_LIT> :: OFFSET_SRC_SHARED_BASE : <STR_LIT> :: OFFSET_SRC_PRIVATE_BASE ; unsigned WidthM1 = AS == <ISA_LIT>AS :: LOCAL_ADDRESS ? <STR_LIT> :: WIDTH_M1_SRC_SHARED_BASE : <STR_LIT> :: WIDTH_M1_SRC_PRIVATE_BASE ; unsigned Encoding = <STR_LIT> :: ID_MEM_BASES << <STR_LIT> :: ID_SHIFT_ | Offset << <STR_LIT> :: OFFSET_SHIFT_ | WidthM1 << <STR_LIT> :: WIDTH_M1_SHIFT_ ; Register GetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( GetReg ) . addImm ( Encoding ) ; MRI . setType ( GetReg , S32 ) ; auto ShiftAmt = B . buildConstant ( S32 , WidthM1 + <NUM_LIT> ) ; return B . buildShl ( S32 , GetReg , ShiftAmt ) . getReg ( <NUM_LIT> ) ; } Register QueuePtr = MRI . createGenericVirtualRegister ( LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! loadInputValue ( QueuePtr , B , & MFI -> getArgInfo ( ) . QueuePtr ) ) return Register ( ) ; uint32_t StructOffset = ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) ? <NUM_LIT> : <NUM_LIT> ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , <NUM_LIT> , MinAlign ( <NUM_LIT> , StructOffset ) ) ; Register LoadAddr ; B . materializePtrAdd ( LoadAddr , QueuePtr , LLT :: scalar ( <NUM_LIT> ) , StructOffset ) ; return B . buildLoad ( S32 , LoadAddr , * MMO ) . getReg ( <NUM_LIT> ) ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FramePointerSaveIndex ( <NUM_LIT> ) , ReturnAddrSaveIndex ( <NUM_LIT> ) , BasePointerSaveIndex ( <NUM_LIT> ) , HasSpills ( false ) , HasNonRISpills ( false ) , SpillsCR ( false ) , SpillsVRSAVE ( false ) , LRStoreRequired ( false ) , MinReservedArea ( <NUM_LIT> ) , TailCallSPDelta ( <NUM_LIT> ) , HasFastCall ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgsStackOffset ( <NUM_LIT> ) , VarArgsNumGPR ( <NUM_LIT> ) , VarArgsNumFPR ( <NUM_LIT> ) , CRSpillFrameIndex ( <NUM_LIT> ) , MF ( MF ) , UsesPICBase ( <NUM_LIT> ) {


<s> x = gen_rtx_IOR ( SImode , x , val ) ; emit_insn ( gen_rtx_SET ( val , x ) ) ; mask = NULL ; break ; case NOT : case PLUS : case MINUS : break ; default : gcc_unreachable ( ) ; } before = gen_reg_rtx ( SImode ) ; if ( after ) after = gen_reg_rtx ( SImode ) ; store_mode = mode = SImode ; } } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( VOIDmode , label ) ; if ( before == NULL_RTX ) before = gen_reg_rtx ( mode ) ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) { x = expand_simple_binop ( mode , AND , before , val , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; after = expand_simple_unop ( mode , NOT , x , after , <NUM_LIT> ) ; } else { after = expand_simple_binop ( mode , code , before , val , after , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Op = <STR_LIT> ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) Op = <STR_LIT> ; bool writeback = ( P == <NUM_LIT> ) || ( W == <NUM_LIT> ) ; unsigned idx_mode = <NUM_LIT> ; if ( P && writeback ) idx_mode = <STR_LIT> ; else if ( ! P && writeback ) idx_mode = <STR_LIT> ; if ( writeback && ( Rn == <NUM_LIT> || Rn == Rt ) ) S = MCDisassembler :: SoftFail ; if ( reg ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> if ( Use -> getOpcode ( ) != <STR_LIT> && Use -> getOpcode ( ) != <STR_LIT> && Use -> getOpcode ( ) != <STR_LIT> && Use -> getOpcode ( ) != <STR_LIT> ) return false ; if ( isStrongerThanMonotonic ( cast < MemSDNode > ( Use ) -> getOrdering ( ) ) ) return false ; }


<s> const TargetRegisterClass * RC ; const DebugLoc & DL = I . getDebugLoc ( ) ; std :: tie ( InputPtrReg , RC ) = MFI -> getPreloadedValue ( <STR_LIT> ) ; if ( ! InputPtrReg ) report_fatal_error ( <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , & I , DL , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( MRI . getLiveInVirtReg ( InputPtrReg -> getRegister ( ) ) ) ;


<s> else if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> && reload_completed && ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) ) return <NUM_LIT> ; else if ( GET_CODE ( x ) == POST_INC && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && thumb_index_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) ) return <NUM_LIT> ; else if ( GET_CODE ( x ) == PLUS ) {

if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> && XEXP ( x , <NUM_LIT> ) != frame_pointer_rtx && XEXP ( x , <NUM_LIT> ) != frame_pointer_rtx && thumb_index_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && thumb_index_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) ) return <NUM_LIT> ;


<s> Base = CurDAG -> getRegister ( AMDGPU :: INDIRECT_BASE_ADDR , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , <STR_LIT> ) ;

} else if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) && ( C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) * <NUM_LIT> ) ) ;


<s> continue ; } } ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , CC , [ & ] ( ArrayRef < Register > Regs , LLT LLTy , LLT PartLLT , int VTSplitIdx ) { packSplitRegsToOrigType ( B , VRegs [ Idx ] [ VTSplitIdx ] , Regs , LLTy , PartLLT ) ; } ) ; ++ Idx ; } if ( CC == CallingConv :: <ISA_LIT>_PS ) { if ( ( Info -> getP<ISA_LIT>nputAddr ( ) & <NUM_LIT> ) == <NUM_LIT> || ( ( Info -> getP<ISA_LIT>nputAddr ( ) & <NUM_LIT> ) == <NUM_LIT> && Info -> isP<ISA_LIT>nputAllocated ( <NUM_LIT> ) ) ) { CCInfo . AllocateReg ( <STR_LIT> ) ; CCInfo . AllocateReg ( <STR_LIT> ) ; Info -> markP<ISA_LIT>nputAllocated ( <NUM_LIT> ) ; Info -> markP<ISA_LIT>nputEnabled ( <NUM_LIT> ) ; } if ( Subtarget . isAmdPalOS ( ) ) { unsigned PsInputBits = Info -> getP<ISA_LIT>nputAddr ( ) & Info -> getP<ISA_LIT>nputEnable ( ) ; if ( ( PsInputBits & <NUM_LIT> ) == <NUM_LIT> || ( ( PsInputBits & <NUM_LIT> ) == <NUM_LIT> && ( PsInputBits >> <NUM_LIT> & <NUM_LIT> ) ) ) Info -> markP<ISA_LIT>nputEnabled ( countTrailingZeros ( Info -> getP<ISA_LIT>nputAddr ( ) , ZB_Undefined ) ) ; } } const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( CC , F . isVarArg ( ) ) ; if ( ! MBB . empty ( ) ) B . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( B , MRI , AssignFn ) ; if ( ! handleAssignments ( CCInfo , ArgLocs , B , SplitArgs , Handler ) ) return false ; if ( ! IsEntryFunc ) { TLI . allocateSpecialInputVGPRs ( CCInfo , MF , * TRI , * Info ) ; } if ( IsEntryFunc ) { TLI . allocateSystemSGPRs ( CCInfo , MF , * Info , CC , IsShader ) ; } else { CCInfo . AllocateReg ( Info -> getScratchRSrcReg ( ) ) ; CCInfo . AllocateReg ( Info -> getScratchWaveOffsetReg ( ) ) ; CCInfo . AllocateReg ( Info -> getFrameOffsetReg ( ) ) ; TLI . allocateSpecialInputSGPRs ( CCInfo , MF , * TRI , * Info ) ; }


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) { std :: string CPUName = <STR_LIT> ;

ParseSubtargetFeatures ( CPUName , FS ) ;


<s> assert ( I . getType ( ) -> isAggregateType ( ) && <STR_LIT> ) ; SmallVector < Value * > Args ; for ( auto & Op : I . operands ( ) ) Args . push_back ( Op ) ; Args . push_back ( IRB -> getInt32 ( I . getSyncScopeID ( ) ) ) ; Args . push_back ( IRB -> getInt32 ( getMemSemantics ( I . getSuccessOrdering ( ) ) ) ) ;

Args . push_back ( IRB -> getInt32 ( getMemSemantics ( I . getFailureOrdering ( ) ) ) ) ;


<s> MachineInstr & MI = * It ++ ; if ( MI . isPosition ( ) || MI . isDebugInstr ( ) ) continue ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { auto * EHPad = TryToEHPad . lookup ( EndToBegin [ & MI ] ) ; assert ( EHPad ) ; auto NextIt = std :: next ( <STR_LIT> ( EHPad ) -> getReverseIterator ( ) ) ; if ( NextIt != EHPad -> rend ( ) ) Worklist . push_back ( NextIt ) ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : EndToBegin [ & MI ] -> getOperand ( <NUM_LIT> ) . setImm ( int32_t ( RetType ) ) ; continue ; default : return ; } } Worklist . push_back ( MBB -> getPrevNode ( ) -> rbegin ( ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , TSInfo ( * TM . getDataLayout ( ) ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) {


<s> case <STR_LIT> : return verifyInsExtInstruction ( MI , ErrInfo , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return verifyInsExtInstruction ( MI , ErrInfo , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return verifyInsExtInstruction ( MI , ErrInfo , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( LastValue . getNode ( ) ) BitGroups . push_back ( BitGroup ( LastValue , LastRLAmt , LastGroupStartIdx , Bits . size ( ) - <NUM_LIT> ) ) ; if ( BitGroups . empty ( ) ) return ; if ( BitGroups . size ( ) > <NUM_LIT> ) { if ( BitGroups [ <NUM_LIT> ] . StartIdx == <NUM_LIT> && BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . EndIdx == Bits . size ( ) - <NUM_LIT> && BitGroups [ <NUM_LIT> ] . V == BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . V && BitGroups [ <NUM_LIT> ] . RLAmt == BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . RLAmt ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . EndIdx = BitGroups [ <NUM_LIT> ] . EndIdx ; BitGroups . erase ( BitGroups . begin ( ) ) ; } }


<s> int Cost = BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , VecPred , CostKind , I ) ; if ( CostKind != TTI :: TCK_RecipThroughput ) return Cost ; return vectorCostAdjustment ( Cost , Opcode , ValTy , nullptr ) ;


<s> TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; }


<s> MCSymbolData * SD_B = & Asm . getSymbolData ( Target . getSymB ( ) -> getSymbol ( ) ) ; IsPCRel = <NUM_LIT> ; FixedValue = ( FixupAddress - Writer -> getSymbolAddress ( SD_B , Layout ) + Target . getConstant ( ) ) ; FixedValue += <NUM_LIT> << Log2Size ; } else { FixedValue = <NUM_LIT> ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = Value ; MRE . r_word1 = ( ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: GENERIC_RELOC_TLV << <NUM_LIT> ) ) ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE ) ;


<s> static bool str_prefix_p ( const char * str , const char * prefix ) {

return strncmp ( str , prefix , strlen ( prefix ) ) == <NUM_LIT> ;


<s> return StringSwitch < Optional < <STR_LIT> >> ( CPU ) . Case ( <STR_LIT> , <STR_LIT> :: V5 ) . Case ( <STR_LIT> , <STR_LIT> :: V5 ) . Case ( <STR_LIT> , <STR_LIT> :: V55 ) . Case ( <STR_LIT> , <STR_LIT> :: V60 ) . Case ( <STR_LIT> , <STR_LIT> :: V62 ) . Case ( <STR_LIT> , <STR_LIT> :: V65 ) . Case ( <STR_LIT> , <STR_LIT> :: V66 ) . Case ( <STR_LIT> , <STR_LIT> :: V67 ) . Case ( <STR_LIT> , <STR_LIT> :: V67 ) . Case ( <STR_LIT> , <STR_LIT> :: V68 ) . Case ( <STR_LIT> , <STR_LIT> :: V69 ) . Default ( None ) ;


<s> auto find_if_or_fail ( R && Range , UnaryPredicate P ) -> decltype ( adl_begin ( Range ) ) { auto It = llvm :: find_if ( Range , P ) ; assert ( It != std :: end ( Range ) ) ; return It ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> void <ISA_LIT>TargetAsmStreamer :: EmitStartOfAsmFile ( ) { OS << <STR_LIT> ; OS << <ISA_LIT>_SV_REGISTER_DECL ; OS << <ISA_LIT>_MEM_DECL ;


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && <STR_LIT> ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool Is128B = HST . useHVXDblOps ( ) ; auto * RC = ! Is128B ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpR0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned TmpR1 = MRI . createVirtualRegister ( RC ) ; BuildMI ( B , It , DL , HII . get ( <STR_LIT> ) , TmpR0 ) . addImm ( <NUM_LIT> ) ; auto * HRI = B . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; HII . loadRegFromStackSlot ( B , It , TmpR1 , FI , RC , HRI ) ; expandLoadVec ( B , std :: prev ( It ) , MRI , HII , NewRegs ) ; unsigned VandOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( VandOpc ) , DstR ) . addReg ( TmpR1 , RegState :: Kill ) . addReg ( TmpR0 , RegState :: Kill ) ; NewRegs . push_back ( TmpR0 ) ; NewRegs . push_back ( TmpR1 ) ;


<s> const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeAllocSizeInBits ( SubVecTy ) ; bool EltIs64Bits = DL . getTypeAllocSizeInBits ( EltTy ) == <NUM_LIT> ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) || EltIs64Bits ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , NumSubElts ) ; } static <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

SmallVector < Value * , <NUM_LIT> > Ops ;


<s> if ( TLI . SimplifyDemandedBits ( Addr , DemandedMask , KnownZero , KnownOne , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; return true ; } return false ;


<s> unsigned VFPThumb2PostEncoder ( const MachineInstr & MI , unsigned Val ) const {


<s> SDValue CmpOp0 = Op . getOperand ( <NUM_LIT> ) ; SDValue CmpOp1 = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueOp = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseOp = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; unsigned CCValid , CCMask ; SDValue Flags = emitCmp ( TM , DAG , DL , CmpOp0 , CmpOp1 , CC , CCValid , CCMask ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueOp ) ; Ops . push_back ( FalseOp ) ; Ops . push_back ( DAG . getConstant ( CCValid , <STR_LIT> ) ) ; Ops . push_back ( DAG . getConstant ( CCMask , <STR_LIT> ) ) ; Ops . push_back ( Flags ) ;

SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> <ISA_LIT>Z80TargetAsmStreamer :: <ISA_LIT>Z80TargetAsmStreamer ( MCStreamer & S ) : <ISA_LIT>Z80TargetStreamer ( S ) {


<s> switch ( RegEnum ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> assert ( first != m_pSectionData -> getFragmentList ( ) . end ( ) && <STR_LIT> ) ; PLTEntryBase * plt0 = & ( llvm :: cast < PLTEntryBase > ( * first ) ) ;


<s> int div = <NUM_LIT> ; if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_fp ; if ( width == <NUM_LIT> ) return <NUM_LIT> ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return <NUM_LIT> ; if ( TARGET_AVX512_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ;

width = ( width + div - <NUM_LIT> ) / div ;


<s> if ( type == error_mark_node ) return NULL_TREE ;

return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) ;


<s> <ISA_LIT>HardwareLoops ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>HardwareLoopsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> nodeType getType ( ) { return type . getNodeType ( ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> TII = MF . getTarget ( ) . getInstrInfo ( ) ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) { MachineLoop * L = * I ; if ( ! L -> getParentLoop ( ) ) { Changed |= convertToCTRLoop ( L ) ; }


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false ) ;


<s> const GlobalAddressSDNode * GN = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GN -> getGlobal ( ) ; SDValue GlobalAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , PtrVT ) ) ; return GlobalAddr ;


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { EmitByte ( Val & <NUM_LIT> , OS ) ; Val >>= <NUM_LIT> ; }


<s> for ( auto & Arg : F . args ( ) ) ArgTypes . push_back ( Arg . getType ( ) ) ; auto ThisFuncMDIt = std :: find_if ( NamedMD -> op_begin ( ) , NamedMD -> op_end ( ) , [ & F ] ( MDNode * N ) { return isa < MDString > ( N -> getOperand ( <NUM_LIT> ) ) && cast < MDString > ( N -> getOperand ( <NUM_LIT> ) ) -> getString ( ) == F . getName ( ) ; } ) ; if ( ThisFuncMDIt != NamedMD -> op_end ( ) ) { auto * ThisFuncMD = * ThisFuncMDIt ; MDNode * MD = dyn_cast < MDNode > ( ThisFuncMD -> getOperand ( <NUM_LIT> ) ) ; assert ( MD && <STR_LIT> ) ; ConstantInt * Const = getConstInt ( MD , <NUM_LIT> ) ; if ( Const ) { auto * CMeta = dyn_cast < ConstantAsMetadata > ( MD -> getOperand ( <NUM_LIT> ) ) ; assert ( CMeta && <STR_LIT> ) ; assert ( Const -> getSExtValue ( ) >= - <NUM_LIT> ) ; if ( Const -> getSExtValue ( ) == - <NUM_LIT> ) RetTy = CMeta -> getType ( ) ; else ArgTypes [ Const -> getSExtValue ( ) ] = CMeta -> getType ( ) ; } }

return FunctionType :: get ( RetTy , ArgTypes , F . isVarArg ( ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitPINSRW ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> if ( cfun -> machine -> label_is_assembled && aarch64_bti_enabled ( ) && ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { rtx_insn * insn = next_real_nondebug_insn ( get_insns ( ) ) ; if ( insn && INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , <NUM_LIT> ) == UNSPECV_BTI_C ) delete_insn ( insn ) ; asm_fprintf ( file , <STR_LIT> ) ;


<s> else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else { SmallVector < std :: string , <NUM_LIT> > ExtMatches ; for ( const auto & Ext : ExtensionMap ) { if ( ( FBS & Ext . Features ) != FeatureBitset ( ) ) ExtMatches . push_back ( Ext . Name ) ; } Str += ! ExtMatches . empty ( ) ? llvm :: join ( ExtMatches , <STR_LIT> ) : <STR_LIT> ;


<s> assert ( LDBase && <STR_LIT> ) ; EVT EltVT = LDBase -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) != EltVT . getSizeInBits ( ) * NumElems ) return SDValue ( ) ; if ( isAfterLegalize && ! DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , VT ) ) return SDValue ( ) ; SDValue NewLd = SDValue ( ) ; NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; } return NewLd ; } EVT EltVT = VT . getVectorElementType ( ) ; if ( NumElems == <NUM_LIT> && LastLoadedElt == <NUM_LIT> && ( EltVT . getSizeInBits ( ) == <NUM_LIT> ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ) { SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) } ; SDValue ResNode = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , LDBase -> getPointerInfo ( ) , LDBase -> getAlignment ( ) , false , true , false ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( ResNode . getNode ( ) , <NUM_LIT> ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , ResNode ) ; }


<s> bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ;

addPass ( createGlobalMergePass ( TM , <NUM_LIT> , OnlyOptimizeForSize ) ) ;


<s> int aarch64_simd_attr_length_rglist ( machine_mode mode ) {

return ( GET_MODE_SIZE ( mode ) . to_constant ( ) / UNITS_PER_VREG ) * <NUM_LIT> ;


<s> Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } }

if ( Addr . getOpcode ( ) == <STR_LIT> ) {


<s> void emitZerofill ( MCSection * Section , MCSymbol * Symbol = nullptr , uint64_t Size = <NUM_LIT> , unsigned ByteAlignment = <NUM_LIT> , SMLoc Loc = SMLoc ( ) ) override {


<s> C = ( ( C * <NUM_LIT> ) & <NUM_LIT> ) * <NUM_LIT> >> <NUM_LIT> ;


<s> Parser . Lex ( ) ; int64_t Temp ; if ( getParser ( ) . parseAbsoluteExpression ( Temp ) || ! ( <NUM_LIT> <= Temp && Temp <= <NUM_LIT> ) ) return MatchOperand_ParseFail ; const int shift = i * <NUM_LIT> + <NUM_LIT> ; Int += ( Temp << shift ) ; } if ( getLexer ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; } else { Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Int ) ) return MatchOperand_ParseFail ; if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= <NUM_LIT> ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= <NUM_LIT> ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= <NUM_LIT> ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = <NUM_LIT> ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = <NUM_LIT> ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = <NUM_LIT> ;


<s> if ( MemRefBegin < <NUM_LIT> ) return false ; MemRefBegin += <STR_LIT> ( Desc ) ; BaseOp = & MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ;

assert ( BaseOp -> isReg ( ) && <STR_LIT> <STR_LIT> ) ;


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) , Kind ) ) ;


<s> OpIdx = <NUM_LIT> ; if ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { unsigned Sm = decodeVFPRm ( insn , true ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Sm ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Sm + <NUM_LIT> ) ) ) ; OpIdx += <NUM_LIT> ; } else {

MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeVFPRm ( insn , false ) ) ) ) ;


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { bool HasCall = false ; InstructionCost NumStores = <NUM_LIT> ; for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == <STR_LIT> || F -> getIntrinsicID ( ) == <STR_LIT> ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( <NUM_LIT> ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , <NUM_LIT> , TTI :: TCK_RecipThroughput ) ; } } unsigned const NumStoresVal = * NumStores . getValue ( ) ; unsigned const Max = ( NumStoresVal ? ( <NUM_LIT> / NumStoresVal ) : UINT_MAX ) ; if ( HasCall ) { UP . FullUnrollMaxCount = Max ; UP . MaxCount = <NUM_LIT> ; return ; } UP . MaxCount = Max ; if ( UP . MaxCount <= <NUM_LIT> ) return ; UP . Partial = UP . Runtime = true ; UP . PartialThreshold = <NUM_LIT> ;

UP . DefaultUnrollRuntimeCount = <NUM_LIT> ;


<s> MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { customEmitInstruction ( I ++ ) ;

} while ( ( I != E ) && I -> isInsideBundle ( ) ) ;


<s> else if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { OS << <STR_LIT> ; } else printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , MII ) ;


<s> EVT ElVT = VT . getVectorElementType ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ;

SDValue VecIdx = DAG . getConstant ( NormalizedIdxVal , <STR_LIT> ) ;


<s> PM . add ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> int real_line , real_pos ; real_line_pos ( diagpos , & real_line , & real_pos ) ;

fprintf ( stderr , <STR_LIT> , ovld_path , real_line , real_pos ) ;


<s> if ( IsReg1 ) return IsReg2 ? <STR_LIT> : <STR_LIT> ; if ( IsReg2 ) return <STR_LIT> ; if ( Src2 . isImm ( ) && isInt < <NUM_LIT> > ( Src2 . getImm ( ) ) ) return <STR_LIT> ;


<s> MCSymbol * Label = Ctx . getOrCreateSymbol ( Twine ( Prefix ) + <STR_LIT> + Twine ( FunctionNumber ) + <STR_LIT> + Twine ( LabelId ) ) ; return Label ;


<s> MachineFunction * MF = MBB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; Register SuperReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; unsigned FirstPart = Offset * <NUM_LIT> ; unsigned ExecLane = <NUM_LIT> ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; assert ( SuperReg != <STR_LIT> && SuperReg != <STR_LIT> && SuperReg != <STR_LIT> && <STR_LIT> ) ; bool OnlyExecLo = isWave32 || NumSubRegs == <NUM_LIT> || SuperReg == <STR_LIT> ; unsigned ExecMovOpc = OnlyExecLo ? <STR_LIT> : <STR_LIT> ; Register ExecReg = OnlyExecLo ? <STR_LIT> : <STR_LIT> ; Register SavedExecReg ; if ( OnlyExecLo ) { SavedExecReg = NumSubRegs == <NUM_LIT> ? SuperReg : Register ( getSubReg ( SuperReg , SplitParts [ FirstPart + ExecLane ] ) ) ; } else { for ( ; ExecLane < ( NumSubRegs - <NUM_LIT> ) ; ++ ExecLane ) { SavedExecReg = getMatchingSuperReg ( getSubReg ( SuperReg , SplitParts [ FirstPart + ExecLane ] ) , <STR_LIT> , & <STR_LIT> ) ; if ( SavedExecReg ) break ; }


<s> if ( AM . Form == <STR_LIT> && ! shouldUseLA ( AM . Base . getNode ( ) , AM . Disp , AM . Index . getNode ( ) ) ) return false ; if ( ! isValidDisp ( AM . DR , AM . Disp ) ) return false ; if ( AM . isDynAlloc ( ) && ! AM . IncludesDynAlloc ) return false ;


<s> else if ( STI -> hasV8MMainlineOps ( ) ) CMSESaveClearFPRegsV8 ( MBB , MBBI , DL , LiveRegs , ScratchRegs ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Cond , Flags ) ; }


<s> const TargetRegisterClass * RC = RegInfo . intRegClass ( <NUM_LIT> ) ; unsigned VR = MRI . createVirtualRegister ( RC ) ; unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , VR ) . addReg ( Src , getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ;

TII . storeRegToStack ( MBB , I , VR , true , FI , RC , & RegInfo , <NUM_LIT> ) ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) || MO . getSubReg ( ) == <STR_LIT> || MO . getSubReg ( ) == <STR_LIT> ) return & <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) || MO . getSubReg ( ) == <STR_LIT> || MO . getSubReg ( ) == <STR_LIT> ) return & <STR_LIT> ; if ( VRM && VRM -> hasPhys ( MO . getReg ( ) ) ) { Register PhysReg = VRM -> getPhys ( MO . getReg ( ) ) ; if ( <STR_LIT> . contains ( PhysReg ) ) return & <STR_LIT> ; assert ( <STR_LIT> . contains ( PhysReg ) && <STR_LIT> ) ;


emitFrameOffset ( MBB , MBB . getFirstTerminator ( ) , DL , <STR_LIT> , <STR_LIT> , NumBytes + ArgumentPopSize , TII , MachineInstr :: FrameDestroy ) ;


<s> VariantKind getKind ( ) const { return Kind ;


<s> rtx regs [ <NUM_LIT> ] ; i = <NUM_LIT> ; regs [ i ++ ] = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; if ( hard_frame_needed ) regs [ i ++ ] = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( ! ( REGNO ( fp ) == STACK_POINTER_REGNUM || ( hard_frame_needed && REGNO ( fp ) == HARD_FRAME_POINTER_REGNUM ) ) ) regs [ i ++ ] = fp ; p = rtvec_alloc ( i ) ; while ( -- i >= <NUM_LIT> ) {

rtx mem = gen_frame_mem ( BLKmode , regs [ i ] ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc = <NUM_LIT> ;

if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) {


<s> MachineBasicBlock * NextBB = & * ++ MBB . getIterator ( ) ; if ( NewTBB == NextBB ) { ReverseBranchCondition ( Cond ) ; RemoveBranch ( MBB ) ; return InsertBranch ( MBB , TBB , nullptr , Cond , DL ) ; } } BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ; Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( EndLoopOp ) ) . addMBB ( TBB ) ; } else if ( isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ;

unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ;


<s> static SDValue LowerBITCAST ( SDValue Op , SelectionDAG & DAG ) { EVT OpVT = Op . getValueType ( ) ; if ( OpVT != <STR_LIT> && OpVT != <STR_LIT> ) return SDValue ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDLoc DL ( Op ) ;

Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , <STR_LIT> , Mang , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ;

return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 , MCSymbolRefExpr :: Create ( SSym , Ctx ) , Ctx ) ;


<s> void <ISA_LIT>MCAsmStreamer :: Finish ( ) {


<s> SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = FastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ; SrcReg = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Op , SrcReg , false ) ; } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ;


<s> if ( sanitizedGlobalValueName ( GV -> getName ( ) , NewName ) ) { GV -> setName ( Twine ( <STR_LIT> ) + Twine ( NewName ) ) ; return true ; } return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static bool isRegMaskId ( RegisterId R ) { return Register :: isStackSlot ( R ) ;


<s> } else { LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EltVT = VT ; NumElts = ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; } unsigned EltBits = EltVT . getSizeInBits ( ) ; LLVMContext * Context = DAG . getContext ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; Constant * C = ConstantInt :: get ( * Context , MaskElt ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Alignment ) ;

SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ;


<s> computeInitialLiveRanges ( IndexMap , LiveMap ) ; DEBUG ( dbgs ( ) << __func__ << <STR_LIT> << PrintRangeMap ( LiveMap , TRI ) << '\n' ) ;


<s> case <NUM_LIT> : return lmul_log2 >= - <NUM_LIT> && ! float_p ; case <NUM_LIT> : return lmul_log2 >= - <NUM_LIT> && ! float_p ; case <NUM_LIT> : return lmul_log2 >= - <NUM_LIT> ; case <NUM_LIT> : return lmul_log2 >= <NUM_LIT> ; default : return false ;


<s> } } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) { return DAG . getCommutedVectorShuffle ( * SVOp ) ; } else if ( LowV2Elements == LowV1Elements ) { int SumV1Indices = <NUM_LIT> , SumV2Indices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = SVOp -> getMask ( ) . size ( ) ; i < Size ; ++ i ) if ( SVOp -> getMask ( ) [ i ] >= NumElements ) SumV2Indices += i ; else if ( SVOp -> getMask ( ) [ i ] >= <NUM_LIT> ) SumV1Indices += i ; if ( SumV2Indices < SumV1Indices ) { return DAG . getCommutedVectorShuffle ( * SVOp ) ; } else if ( SumV2Indices == SumV1Indices ) { int NumV1OddIndices = <NUM_LIT> , NumV2OddIndices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = SVOp -> getMask ( ) . size ( ) ; i < Size ; ++ i ) if ( SVOp -> getMask ( ) [ i ] >= NumElements ) NumV2OddIndices += i % <NUM_LIT> ; else if ( SVOp -> getMask ( ) [ i ] >= <NUM_LIT> ) NumV1OddIndices += i % <NUM_LIT> ; if ( NumV2OddIndices < NumV1OddIndices ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; } } }

if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return lower128BitVectorShuffle ( Op , V1 , V2 , VT , Subtarget , DAG ) ;


<s> getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue >> & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ;

<ISA_LIT>TargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , IsCallReloc , CLI , Callee , Chain ) ;


<s> machine_mode mode = GET_MODE ( pred1 [ <NUM_LIT> ] ) ;

gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL && mode == GET_MODE ( pred2 [ <NUM_LIT> ] ) && aarch64_sve_ptrue_flag ( pred1 [ <NUM_LIT> ] , SImode ) && aarch64_sve_ptrue_flag ( pred2 [ <NUM_LIT> ] , SImode ) ) ;


<s> void <ISA_LIT>ELFStreamer :: emitPad ( int64_t Offset ) { SPOffset -= Offset ;


return ( __m256 ) __builtin_ia32_loadups256 ( __P ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) && Type == <STR_LIT> ) return true ; return IsSigned ;


<s> if ( ( GET_CODE ( op ) == POST_INC ) && ( mode_test == SImode ) ) { regno = REGNO ( XEXP ( op , <NUM_LIT> ) ) ; if ( regno < <NUM_LIT> ) return ADDRESS_POST_INC_LO_REG_IMM3U ; } if ( ( GET_CODE ( op ) == POST_MODIFY ) && ( mode_test == SImode ) && ( REG_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ) && ( CONST_INT_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) { regno = REGNO ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ; val = INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( regno < <NUM_LIT> && val < <NUM_LIT> ) return ADDRESS_POST_INC_LO_REG_IMM3U ; } if ( ( GET_CODE ( op ) == PLUS ) && ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == REG ) && ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ) { val = INTVAL ( XEXP ( op , <NUM_LIT> ) ) ; regno = REGNO ( XEXP ( op , <NUM_LIT> ) ) ; if ( regno > <NUM_LIT> && regno != SP_REGNUM && regno != FP_REGNUM ) return ADDRESS_NOT_16BIT_FORMAT ; switch ( mode_test ) { case QImode : if ( val >= <NUM_LIT> && val < <NUM_LIT> && regno < <NUM_LIT> ) return ADDRESS_LO_REG_IMM3U ; break ; case HImode : if ( val >= <NUM_LIT> && val < <NUM_LIT> && ( val % <NUM_LIT> == <NUM_LIT> ) && regno < <NUM_LIT> ) return ADDRESS_LO_REG_IMM3U ; break ; case SImode : case SFmode : case DFmode : if ( ( regno == FP_REGNUM ) && ( val >= <NUM_LIT> && val < <NUM_LIT> && ( val % <NUM_LIT> == <NUM_LIT> ) ) ) return ADDRESS_FP_IMM7U ; else if ( ( regno == SP_REGNUM ) && ( val >= <NUM_LIT> && val < <NUM_LIT> && ( val % <NUM_LIT> == <NUM_LIT> ) ) ) return ADDRESS_SP_IMM7U ; else if ( val >= <NUM_LIT> && val < <NUM_LIT> && ( val % <NUM_LIT> == <NUM_LIT> ) && regno < <NUM_LIT> ) return ADDRESS_LO_REG_IMM3U ; break ;


<s> return __builtin_mve_vmvnq_m_n_uv8hi ( __arm_vuninitializedq_u16 ( ) , __imm , __p ) ;


<s> static bool isInlineConstantIfFolded ( const <ISA_LIT>InstrInfo * TII , const MachineInstr & UseMI , unsigned OpNo , const MachineOperand & OpToFold ) { if ( TII -> isInlineConstant ( UseMI , OpNo , OpToFold ) ) return true ; unsigned Opc = UseMI . getOpcode ( ) ; unsigned NewOpc = macToMad ( Opc ) ; if ( NewOpc != <STR_LIT> ) { int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( static_cast < int > ( OpNo ) == Src2Idx ) { const MCInstrDesc & MadDesc = TII -> get ( NewOpc ) ; return TII -> isInlineConstant ( OpToFold , MadDesc . OpInfo [ OpNo ] . OperandType ) ;


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; addFullAddress ( MIB , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; if ( MMO ) MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return true ; } } Register ValReg = getRegForValue ( Val ) ; if ( ValReg == <NUM_LIT> ) return false ;


<s> MFI . stackifyVReg ( NewReg ) ; ImposeStackOrdering ( Clone ) ; if ( MRI . use_empty ( Reg ) ) { SlotIndex Idx = LIS . getInstructionIndex ( * Def ) . getRegSlot ( ) ; LIS . removePhysRegDefAt ( <STR_LIT> , Idx ) ; LIS . removeVRegDefAt ( LIS . getInterval ( Reg ) , Idx ) ; LIS . removeInterval ( Reg ) ; LIS . RemoveMachineInstrFromMaps ( * Def ) ; Def -> eraseFromParent ( ) ; } else { LIS . shrinkToUses ( & LIS . getInterval ( Reg ) ) ;


<s> virtual const <ISA_LIT>MachOWriterInfo * getMachOWriterInfo ( ) const { return & MachOWriterInfo ;


<s> if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue HiV = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoV , HiV ) ; } } } assert ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; PermMask |= IsHighZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V1 = DAG . getUNDEF ( VT ) ;

if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V2 = DAG . getUNDEF ( VT ) ;


<s> case <STR_LIT> : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ;


<s> EVT EltType = V . getValueType ( ) . getVectorElementType ( ) ;

return EltType . getSizeInBits ( ) / <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { CLI . IsTailCall = false ; switch ( CLI . CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C : return LowerCCCCallTo ( CLI , InVals ) ;


<s> static void rs6000_xcoff_output_toc_section_asm_op ( const void * data ATTRIBUTE_UNUSED ) { if ( TARGET_MINIMAL_TOC ) { if ( ! toc_initialized ) { fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; toc_initialized = <NUM_LIT> ;


<s> if ( PrevInstrIt . getNodePtr ( ) == LoadInst ) StInst = LoadInst ; MachineInstr * NewStore = BuildMI ( * MBB , StInst , StInst -> getDebugLoc ( ) , TII -> get ( NStoreOpcode ) ) . add ( StoreBase ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StoreDisp ) . addReg ( <STR_LIT> ) . addReg ( Reg1 ) . addMemOperand ( MBB -> getParent ( ) -> getMachineMemOperand ( SMMO , SMMOffset , Size ) ) ; if ( StoreBase . isReg ( ) ) getBaseOperand ( NewStore ) . setIsKill ( false ) ; MachineOperand & StoreSrcVReg = StoreInst -> getOperand ( <STR_LIT> ) ; assert ( StoreSrcVReg . isReg ( ) && <STR_LIT> ) ;

NewStore -> getOperand ( <STR_LIT> ) . setIsKill ( StoreSrcVReg . isKill ( ) ) ;


<s> handlePredUse ( i , block , curLocs , FreeLocs ) ; auto definitions = block -> getDefinitions ( ) ; if ( ! definitions . empty ( ) ) { vector < unsigned > order ; for ( auto def : definitions ) { auto pred = def . predicate ; if ( curLocs . find ( pred ) == curLocs . end ( ) ) { order . push_back ( pred ) ; } } sortFurthestNextUse ( i , order ) ; for ( auto pred : order ) { Location l = getAvailLoc ( FreeLocs ) ; map < unsigned , Location > :: iterator findCurUseLoc = curLocs . find ( pred ) ; if ( findCurUseLoc == curLocs . end ( ) ) { curLocs . insert ( make_pair ( pred , l ) ) ; } else { findCurUseLoc -> second = l ; }

if ( DefLocs . find ( pred ) == DefLocs . end ( ) ) {


<s> return <STR_LIT> ( MI . getOpcode ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printNeonUImm8OperandBare ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

const MCOperand & MOUImm = MI -> getOperand ( OpNum ) ;


<s> if ( TotalBytes > <NUM_LIT> ) { TotalBytes = <NUM_LIT> ; } else { TotalBytes = alignTo ( TotalBytes , <NUM_LIT> ) ; } int RegIdx = TotalBytes - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT VT = Args [ i ] . VT ; unsigned Reg ;


<s> unsigned getSsatBitPosValue ( const MachineInstr & MI , unsigned Op ) const {


<s> TII . storeRegToStackSlot ( MBB , MBBI , ABI . GetEhDataReg ( I ) , false , <ISA_LIT>FI -> getEhDataRegFI ( I ) , RC , & RegInfo ) ; } for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( <ISA_LIT>FI -> getEhDataRegFI ( I ) ) ; unsigned Reg = MRI -> getDwarfRegNum ( ABI . GetEhDataReg ( I ) , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , Reg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( MOVE ) , FP ) . addReg ( SP ) . addReg ( ZERO ) . setMIFlag ( MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , MRI -> getDwarfRegNum ( FP , true ) ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; if ( RegInfo . needsStackRealignment ( MF ) ) { unsigned VR = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; assert ( isInt < <NUM_LIT> > ( MFI . getMaxAlignment ( ) ) && <STR_LIT> ) ; int MaxAlign = - ( int ) MFI . getMaxAlignment ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , VR ) . addReg ( ZERO ) . addImm ( MaxAlign ) ; BuildMI ( MBB , MBBI , dl , TII . get ( AND ) , SP ) . addReg ( SP ) . addReg ( VR ) ; if ( hasBP ( MF ) ) { unsigned BP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ;

BuildMI ( MBB , MBBI , dl , TII . get ( MOVE ) , BP ) . addReg ( SP ) . addReg ( ZERO ) ;


<s> int addp4_optimize_ok ( rtx op1 , rtx op2 ) {


<s> if ( ! LiveNodes . count ( UA . Id ) ) WorkQ . push_back ( UA . Id ) ; }

for ( NodeAddr < DefNode * > TA : DFG . getRelatedRefs ( IA , DA ) ) LiveNodes . insert ( TA . Id ) ;


<s> bool <ISA_LIT>TTI :: hasBranchDivergence ( ) const {


<s> for ( int Index = Begin ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ; for ( int Index = std :: max ( <NUM_LIT> , Begin - <NUM_LIT> ) ; Index <= End ; ++ Index ) Reserved . set ( <STR_LIT> . getRegister ( Index ) ) ;


<s> } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Res ) ; } else return SDValue ( ) ; } if ( ShiftAmt != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ;


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; MCInst MCI ; MCInstLowering . Lower ( MI , MCI ) ; <ISA_LIT>InstPrinter PIP ( * OutContext . getAsmInfo ( ) , * TM . getMCInstrInfo ( ) , * TM . getMCRegisterInfo ( ) ) ;

PIP . printOperand ( & MCI , OpNo , OS ) ;


<s> rtx body = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( body ) == SET ) ; rtx src = SET_SRC ( body ) ; rtx dest = SET_DEST ( body ) ; if ( ( REG_P ( src ) || GET_CODE ( src ) == SUBREG ) && ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ) return true ; return false ; }


<s> MachineFunction * MF = blk -> getParent ( ) ; MachineInstr * NewInstr = MF -> CreateMachineInstr ( TII -> get ( NewOpcode ) , DL ) ;


<s> const auto * I = cast < Instruction > ( V ) ; return FuncInfo . MBBMap [ I -> getParent ( ) ] == FuncInfo . MBB ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t Value = CE -> getValue ( ) ; unsigned Imm = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i , Value >>= <NUM_LIT> ) { Imm |= ( Value & <NUM_LIT> ) << i ; } Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ;


<s> uint8_t Bytes [ <NUM_LIT> ] ; if ( region . readBytes ( address , <NUM_LIT> , Bytes ) == - <NUM_LIT> ) { size = <NUM_LIT> ; return MCDisassembler :: Fail ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & FS ) : <ISA_LIT>ShaderModel ( <ISA_LIT>_SM_1_0 ) , <ISA_LIT>Version ( <ISA_LIT>_VERSION_1_4 ) , SupportsDouble ( false ) , Use64BitAddresses ( false ) { std :: string TARGET = <STR_LIT> ;

ParseSubtargetFeatures ( FS , TARGET ) ;


<s> addPass ( create<ISA_LIT>PostRAScavengingPass ( ) ) ;


<s> unsigned Opcode = CurrentInst -> Inst . getOpcode ( ) ;

if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;


<s> return isInterruptHandler ( ) || isSignalHandler ( ) ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : UsesLR ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) {


<s> break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) , <NUM_LIT> ) ) ; } } if ( isVarArg ) { unsigned StackSize = CCInfo . getNextStackOffset ( ) ; <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AFI -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; } return Chain ;


<s> return new <ISA_LIT>MCCodeEmitter ( MII , Context ) ;


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ;

for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) {


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> void <ISA_LIT>InstPrinter :: printMemri ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { assert ( MI -> getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( OffsetOp . isImm ( ) ) { int64_t Offset = OffsetOp . getImm ( ) ; if ( Offset >= <NUM_LIT> ) O << '+' ; O << Offset ; } else if ( OffsetOp . isExpr ( ) ) { O << * OffsetOp . getExpr ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( SuccID == S -> getID ( ) ) return ; } if ( Succ -> isHighLatencyBlock ( ) ) ++ NumHighLatencySuccessors ; Succs . push_back ( Succ ) ; assert ( none_of ( Preds , [ = ] ( <ISA_LIT>ScheduleBlock * P ) { return SuccID == P -> getID ( ) ; } ) && <STR_LIT> ) ;


<s> unsigned getSOImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( FK_Data_4 ) ;

Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ;


<s> bool supports<ISA_LIT>21 ( ) const { return <ISA_LIT>Version >= <ISA_LIT>_VERSION_2_1 ;


<s> printFunctionParameterAttribute ( MI , NumFixedOps , O ) ; break ; case <STR_LIT> :: FPRoundingMode : printFPRoundingMode ( MI , NumFixedOps , O ) ; break ; case <STR_LIT> :: FPFastMathMode : printFPFastMathMode ( MI , NumFixedOps , O ) ; break ; case <STR_LIT> :: LinkageAttributes : case <STR_LIT> :: UserSemantic : printStringImm ( MI , NumFixedOps , O ) ; break ; default : printRemainingVariableOps ( MI , NumFixedOps , O , true ) ; break ;


<s> NodeToUsesMap :: iterator UF = Uses . find ( Node ) ; assert ( UF != Uses . end ( ) && <STR_LIT> ) ; UseSet & Us = UF -> second ; for ( UseSet :: iterator I = Us . begin ( ) , E = Us . end ( ) ; I != E ; ++ I ) { Use * U = * I ; User * R = U -> getUser ( ) ; if ( ! isa < Instruction > ( R ) ) continue ; BasicBlock * PB = isa < PHINode > ( R ) ? cast < PHINode > ( R ) -> getIncomingBlock ( * U ) : cast < Instruction > ( R ) -> getParent ( ) ;


<s> explicit <ISA_LIT>LoadStoreReplace ( ) : BasicBlockPass ( ID ) {


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( GetOppositeBranchCondition ( CC ) ) ;


<s> unsigned <STR_LIT> ( <STR_LIT> CC ) { switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> EHSecName += FnSecName ; } const MCSectionELF * EHSection = nullptr ; if ( const MCSymbol * Group = FnSection . getGroup ( ) ) { EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags | ELF :: SHF_GROUP , Kind , FnSection . getEntrySize ( ) , Group -> getName ( ) ) ; } else { EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , Kind ) ;


<s> FunctionPass * create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) {

return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) , true , true ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( tm , * this ) , TM ( tm ) {


<s> unsigned <ISA_LIT>AsmParser :: AdjustAVX512Mem ( unsigned Size , <ISA_LIT>Operand * UnsizedMemOpNext ) {

if ( ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ;


<s> return MF . getContext ( ) . getOrCreateSymbol ( Twine ( DL . getPrivateGlobalPrefix ( ) ) + Twine ( MF . getFunctionNumber ( ) ) + <STR_LIT> ) ;


<s> bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { return Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , * this ) ;


<s> } else for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , dest + i ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , src + i ) ; output_asm_insn ( <STR_LIT> , ops ) ; } } } else { gcc_assert ( MEM_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; switch ( GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) {


<s> <ISA_LIT>WinCOFFObjectWriter :: <ISA_LIT>WinCOFFObjectWriter ( bool Is64Bit ) : MCWinCOFFObjectTargetWriter ( Is64Bit ? COFF :: IMAGE_FILE_MACHINE_AMD64 : COFF :: IMAGE_FILE_MACHINE_I386 ) {


<s> } units = get_attr_units ( insn ) ; switch ( units ) { case UNITS_D : case UNITS_DL : case UNITS_DS : case UNITS_DLS : case UNITS_D_ADDR : return 'd' ; break ; case UNITS_L : case UNITS_LS :


<s> unsigned getForcedEncodingSize ( ) const {


<s> const <ISA_LIT>Subtarget & getSubtarget ( ) const { return * Subtarget ;


<s> <ISA_LIT>AsmBackend ( Target const & T , uint8_t OSABI , StringRef CPU ) : OSABI ( OSABI ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) {


<s> if ( getArgType ( FInfo ) != <ISA_LIT>LibFunc :: F32 || FInfo . getPrefix ( ) != <ISA_LIT>LibFunc :: NOPFX || ! HasNative ( FInfo . getId ( ) ) ) return false ; <ISA_LIT>LibFunc nf = FInfo ; nf . setPrefix ( <ISA_LIT>LibFunc :: NATIVE ) ; if ( Constant * FPExpr = getFunction ( M , nf ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * CI << <STR_LIT> ) ; CI -> setCalledFunction ( FPExpr ) ; LLVM_DEBUG ( dbgs ( ) << * CI << '\n' ) ; return true ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> } mask >>= <NUM_LIT> ; } gcc_assert ( i < units ) ; { switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) { case E_V8QImode : sprintf ( templ , <STR_LIT> , i ) ; break ; case E_V4HImode : sprintf ( templ , <STR_LIT> , i ) ; break ; case E_V2SImode : sprintf ( templ , <STR_LIT> , i ) ; break ; default : gcc_unreachable ( ) ;


<s> src_addr = XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) ; if ( GET_CODE ( elt ) != SET || ! REG_P ( SET_DEST ( elt ) ) || GET_MODE ( SET_DEST ( elt ) ) != SImode || REGNO ( SET_DEST ( elt ) ) != regno || ! MEM_P ( SET_SRC ( elt ) ) || GET_MODE ( SET_SRC ( elt ) ) != SImode || ! memory_address_p ( SImode , src_addr ) ) return false ; for ( setno = <NUM_LIT> ; i < XVECLEN ( op , <NUM_LIT> ) ; setno ++ , i ++ ) { rtx elt = XVECEXP ( op , <NUM_LIT> , i ) ; regno += regno_dir ; if ( GET_CODE ( elt ) != SET || ! REG_P ( SET_DEST ( elt ) ) || GET_MODE ( SET_DEST ( elt ) ) != SImode || REGNO ( SET_DEST ( elt ) ) != regno || ! MEM_P ( SET_SRC ( elt ) ) || GET_MODE ( SET_SRC ( elt ) ) != SImode || GET_CODE ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) ) != PLUS || ! rtx_equal_p ( XEXP ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) , <NUM_LIT> ) , src_addr ) || ! CONST_INT_P ( XEXP ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) , <NUM_LIT> ) ) || INTVAL ( XEXP ( XEXP ( SET_SRC ( elt ) , <NUM_LIT> ) , <NUM_LIT> ) ) != setno * <NUM_LIT> ) return false ; } return true ;


<s> unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ; Operands . push_back ( Op ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) {


<s> bool hasByvalArg ( ) const { return HasByvalArg ;


return ( int8x8_t ) __builtin_neon_vmovnv8hi ( __a ) ;


<s> return new <ISA_LIT>AsmBackendWinCOFF ( T , STI ) ; case Triple :: ELF : assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; return new <ISA_LIT>AsmBackendELF ( T , STI , OSABI , Endian ) ; }


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( MachineFunction & mf , MachineModuleInfo * mmo , DwarfWriter * dw , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < Instruction * , <NUM_LIT> > & cil ) {

return <STR_LIT> ( mf , mmo , dw , vm , bm , am , cil ) ;


<s> assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ;


<s> if ( * first_offset ) { gcc_assert ( epilogue_p || abs ( * first_offset ) <= <NUM_LIT> ) ; frame_add ( base_reg , * first_offset ) ; * first_offset = <NUM_LIT> ; } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( ( epilogue_p == <NUM_LIT> ) + n_regs + <NUM_LIT> ) ) ; if ( epilogue_p == <NUM_LIT> ) i += <NUM_LIT> ; else XVECEXP ( insn , <NUM_LIT> , n_regs ) = gen_rtx_CLOBBER ( VOIDmode , ret_addr ) ; for ( r = start_call ; r <= end_call ; r ++ , off += UNITS_PER_WORD , i ++ ) { rtx reg = gen_rtx_REG ( SImode , r ) ; rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base_reg , off ) ) ; if ( epilogue_p ) XVECEXP ( insn , <NUM_LIT> , i ) = gen_rtx_SET ( VOIDmode , reg , mem ) ; else XVECEXP ( insn , <NUM_LIT> , i ) = gen_rtx_SET ( VOIDmode , mem , reg ) ; gmask = gmask & ~ ( <NUM_LIT> << r ) ; } if ( epilogue_p == <NUM_LIT> ) sibthunk_insn = insn ; else frame_insn ( insn ) ; offset += off ; } for ( regno = <NUM_LIT> ; regno <= <NUM_LIT> ; regno ++ ) { if ( ( gmask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx addr , mem ; if ( * first_offset ) { gcc_assert ( ! offset ) ; addr = plus_constant ( Pmode , base_reg , * first_offset ) ; addr = gen_rtx_PRE_MODIFY ( Pmode , base_reg , addr ) ; * first_offset = <NUM_LIT> ; } else {


<s> SwitchToCU ( DL . getScope ( MF . getFunction ( ) -> getContext ( ) ) ) ;

SwitchToLine ( DL . getLine ( ) , IsInBeginFunction ) ;


<s> static __inline unsigned int _MM_GET_EXCEPTION_STATE ( void ) {

return _mm_getcsr ( ) & _MM_EXCEPT_MASK ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( ! isIdentityValue ( OrigMI . getOpcode ( ) , OldOpndValue ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } CombOldVGPR = getRegSubRegPair ( * Src1 ) ; if ( ! isOfRegClass ( CombOldVGPR , <STR_LIT> , * MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , DebugLoc DL ) const { unsigned NumInserted = <NUM_LIT> ; if ( Cond . size ( ) > <NUM_LIT> ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; NumInserted ++ ; } if ( Cond . empty ( ) || FBB ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( <STR_LIT> ) ) . addMBB ( Cond . empty ( ) ? TBB : FBB ) ; NumInserted ++ ;


<s> { <STR_LIT> } , { <STR_LIT> } , { <STR_LIT> } , { <STR_LIT> } , { <STR_LIT> } , { <STR_LIT> } , { <STR_LIT>


<s> for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned CallOpc = <STR_LIT> ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; EVT CalleeVT = Callee . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , CalleeVT ) ; if ( ! ST -> usingLargeMem ( ) ) { if ( GV -> isDeclaration ( ) ) { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , GA , Zero ) ; } else { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , GA , Zero ) ; } } else { Callee = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; } } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { EVT CalleeVT = Callee . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue ExtSym = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) ) ; if ( ! ST -> usingLargeMem ( ) ) { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , ExtSym , Zero ) ; } else { Callee = DAG . getNode ( <STR_LIT> , dl , PtrVT , ExtSym , Zero ) ; } } else if ( SDNode * Dest = isLSAAddress ( Callee , DAG ) ) { Callee = SDValue ( Dest , <NUM_LIT> ) ; } Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( CallOpc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;


<s> if ( OPTION_SET_P ( tilegx_cmodel ) ) { switch ( tilegx_cmodel ) { case CM_SMALL : case CM_SMALL_PIC :


<s> static bool isMatchingDecrement ( MachineInstr * MI , unsigned Base , unsigned Bytes , unsigned Limit , <STR_LIT> Pred , unsigned PredReg ) { unsigned MyPredReg = <NUM_LIT> ; if ( ! MI ) return false ; bool CheckCPSRDef = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CheckCPSRDef = true ; case <STR_LIT> :


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ;

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


<s> switch ( Desc . getOpcode ( ) ) { default : if ( Desc . getSize ( ) ) return Desc . getSize ( ) ; NumBytes = <NUM_LIT> ; break ; case TargetOpcode :: STACKMAP : NumBytes = StackMapOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ; case TargetOpcode :: PATCHPOINT : NumBytes = PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ; case TargetOpcode :: STATEPOINT : NumBytes = StatepointOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; if ( NumBytes == <NUM_LIT> ) NumBytes = <NUM_LIT> ;


<s> assert ( Kind == k_Reg && <STR_LIT> ) ;


<s> printMemReference ( MI , OpNo , O ) ;


<s> void <ISA_LIT>AsmParser :: warnIfNoMacro ( SMLoc Loc ) {

if ( ! AssemblerOptions . back ( ) -> isMacro ( ) ) Warning ( Loc , <STR_LIT> ) ;


<s> unsigned getMaxSupportedInterleaveFactor ( ) const override {


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , bool RelaxAll , bool NoExecStack ) { Triple TheTriple ( TT ) ; return createELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll , NoExecStack ) ;


<s> return __builtin_mve_vcvtpq_sv4si ( __a ) ;


<s> StaticCtorSection = getContext ( ) . getELFSection ( <STR_LIT> , MCSectionELF :: SHT_INIT_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( <STR_LIT> , MCSectionELF :: SHT_FINI_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;


<s> assert ( ( VecSize == <NUM_LIT> || VecSize == <NUM_LIT> || VecSize == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( ScalarBits == <NUM_LIT> || ScalarBits == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RawMask . size ( ) ; i < e ; ++ i ) { uint64_t M = RawMask [ i ] ; M = ( ScalarBits == <NUM_LIT> ? ( ( M >> <NUM_LIT> ) & <NUM_LIT> ) : ( M & <NUM_LIT> ) ) ; unsigned LaneOffset = i & ~ ( NumEltsPerLane - <NUM_LIT> ) ; ShuffleMask . push_back ( ( int ) ( LaneOffset + M ) ) ;


<s> Label += TAI -> getPrivateGlobalPrefix ( ) ; Label += <STR_LIT> ; Label += utostr ( LabelID ++ ) ; TOC [ Name ] = Label ; }


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override {


<s> if ( clr_p ) { insn = emit_move_insn ( sfr , const0_rtx ) ; if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; }


<s> } else { TRI . buildVGPRSpillLoadStore ( * this , Index , Offset , IsLoad , false ) ; auto Not0 = BuildMI ( * MBB , MI , DL , TII . get ( NotOpc ) , ExecReg ) . addReg ( ExecReg ) ;

Not0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> int sh_media_register_for_return ( void ) { int regno ; int tr0_used ; if ( ! crtl -> is_leaf ) return - <NUM_LIT> ; if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) ) return - <NUM_LIT> ; if ( sh_cfun_interrupt_handler_p ( ) ) return - <NUM_LIT> ; tr0_used = flag_pic && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ; for ( regno = FIRST_TARGET_REG + tr0_used ; regno <= LAST_TARGET_REG ; regno ++ ) if ( call_really_used_regs [ regno ] && ! df_regs_ever_live_p ( regno ) ) return regno ;


<s> Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ; Cond . push_back ( LastInst . getOperand ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>MCInst :: isExtended ( void ) const {


<s> int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( DECL_FIELD_ABI_IGNORED ( field ) ) { unsigned int flag ; if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( field ) ) ) flag = WARN_PSABI_NO_UNIQUE_ADDRESS ; else if ( cxx17_empty_base_field_p ( field ) ) flag = WARN_PSABI_EMPTY_CXX17_BASE ; else continue ; if ( warn_psabi_flags ) { * warn_psabi_flags |= flag ; continue ; } } else if ( DECL_BIT_FIELD ( field ) && integer_zerop ( DECL_SIZE ( field ) ) ) { if ( DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD ( field ) ) continue ; if ( warn_psabi_flags ) { * warn_psabi_flags |= WARN_PSABI_ZERO_WIDTH_BITFIELD ; continue ; } } sub_count = aapcs_vfp_sub_candidate ( TREE_TYPE ( field ) , modep , warn_psabi_flags ) ; if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ; count += sub_count ; } if ( wi :: to_wide ( TYPE_SIZE ( type ) ) != count * GET_MODE_BITSIZE ( * modep ) ) return - <NUM_LIT> ; return count ; } case UNION_TYPE : case QUAL_UNION_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ;


<s> if ( Dep . getSUnit ( ) == SU && Dep . getKind ( ) == SDep :: Data && <STR_LIT> . contains ( Dep . getReg ( ) ) ) { if ( restrictingDepExistInPacket ( I , Dep . getReg ( ) ) ) return false ; } } } } unsigned PReg1 = getPredicatedRegister ( MI1 , HII ) ; unsigned PReg2 = getPredicatedRegister ( MI2 , HII ) ;

return PReg1 == PReg2 && <STR_LIT> . contains ( PReg1 ) && <STR_LIT> . contains ( PReg2 ) && getPredicateSense ( MI1 , HII ) != getPredicateSense ( MI2 , HII ) && HII -> isDotNewInst ( & MI1 ) == HII -> isDotNewInst ( & MI2 ) ;


<s> void setPreallocatedArgOffsets ( size_t Id , ArrayRef < size_t > AO ) { PreallocatedArgOffsets [ Id ] . assign ( AO . begin ( ) , AO . end ( ) ) ;


<s> } const MCSymbolELF * Group = FnSection . getGroup ( ) ; if ( Group ) Flags |= ELF :: SHF_GROUP ; MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , true , FnSection . getUniqueID ( ) , static_cast < const MCSymbolELF * > ( FnSection . getBeginSymbol ( ) ) ) ; assert ( EHSection && <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) { const <ISA_LIT>TargetObjectFile & TLOF = ( const <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ;

if ( TLOF . IsConstantInSmallSection ( N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ;


<s> case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) != <STR_LIT> ) break ; return DCI . CombineTo ( N , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ;

Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;