<s> const TargetInstrDesc desc = MI -> getDesc ( ) ; if ( MI -> getOpcode ( ) == TargetOpcode :: COPY ) return false ; for ( unsigned i = <NUM_LIT> , e = std :: max ( MI -> findFirstPredOperandIdx ( ) , ( int ) desc . NumOperands ) ; i < e ; ++ i ) { const MachineOperand & op = MI -> getOperand ( i ) ;

if ( op . isReg ( ) && op . isUse ( ) ) {


<s> for ( i = <NUM_LIT> ; i < nunits ; i ++ ) for ( j = <NUM_LIT> ; j < usize ; j ++ ) RTVEC_ELT ( v , i * usize + j ) = GEN_INT ( ( i + <NUM_LIT> ) * usize - <NUM_LIT> - j ) ;

mask = gen_rtx_CONST_VECTOR ( V16QImode , v ) ;


<s> MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , NewDest , Br . MaxDisp ) ) { DOUT << <STR_LIT> << * BMI ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { SplitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBSizes [ MBB -> getNumber ( ) ] -= delta ; MachineBasicBlock * SplitBB = next ( MachineFunction :: iterator ( MBB ) ) ; AdjustBBOffsetsAfter ( SplitBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = next ( MachineFunction :: iterator ( MBB ) ) ; DOUT << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBSizes [ MI -> getParent ( ) -> getNumber ( ) ] -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ;


<s> const <ISA_LIT>ConstPtr * curConst = getConstPtr ( krnl , Arg ) ; if ( ! curConst ) { return <NUM_LIT> ; }


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ;

assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ;


<s> if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ;

AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; EVT ContainerVT = VT ; if ( ContainerVT . isInteger ( ) ) ContainerVT = getSVEContainerType ( ContainerVT ) ; SDVTList VTs = DAG . getVTList ( ContainerVT , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( VT ) } ; SDValue Load = DAG . getNode ( Opc , DL , VTs , Ops ) ;

SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ;


<s> assert ( ( value <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) && <STR_LIT> ) ;


<s> if ( csky_tls_symbol_p ( x ) ) return csky_legitimize_tls_address ( x , NULL_RTX ) ; if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( is_csky_address_register_rtx_p ( xop0 , <NUM_LIT> ) && CONST_INT_P ( xop1 ) ) { HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset > CSKY_LD16_MAX_OFFSET ( mode ) && offset <= ( CSKY_ADDI16_MAX_IMM + CSKY_LD16_MAX_OFFSET ( mode ) ) ) { HOST_WIDE_INT new_ld_offset = offset & CSKY_LD16_OFFSET_MASK ( mode ) ; xop0 = force_operand ( plus_constant ( Pmode , xop0 , offset - new_ld_offset ) , NULL_RTX ) ; x = plus_constant ( Pmode , xop0 , new_ld_offset ) ; } else if ( offset < <NUM_LIT> && offset >= ( - CSKY_SUBI16_MAX_IMM ) ) x = force_operand ( x , NULL_RTX ) ; else if ( offset > CSKY_LD16_MAX_OFFSET ( mode ) || offset < <NUM_LIT> ) { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } if ( is_csky_address_register_rtx_p ( xop1 , <NUM_LIT> ) && ! is_csky_address_register_rtx_p ( xop0 , <NUM_LIT> ) ) {


<s> for ( SDep & SuccDep : SU -> Succs ) { SUnit * Succ = SuccDep . getSUnit ( ) ; if ( SuccDep . isWeak ( ) || Succ -> NodeNum >= DAGSize ) continue ;

SUColors . insert ( CurrentColoring [ Succ -> NodeNum ] ) ;


<s> if ( c == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> case CallingConv :: C : case CallingConv :: <ISA_LIT>_StdCall : { NestReg = <STR_LIT> ; FunctionType * FTy = Func -> getFunctionType ( ) ; const AttributeSet & Attrs = Func -> getAttributes ( ) ; if ( ! Attrs . isEmpty ( ) && ! Func -> isVarArg ( ) ) { unsigned InRegCount = <NUM_LIT> ; unsigned Idx = <NUM_LIT> ; for ( FunctionType :: param_iterator I = FTy -> param_begin ( ) , E = FTy -> param_end ( ) ; I != E ; ++ I , ++ Idx ) if ( Attrs . hasAttribute ( Idx , Attribute :: InReg ) ) InRegCount += ( TD -> getTypeSizeInBits ( * I ) + <NUM_LIT> ) / <NUM_LIT> ; if ( InRegCount > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } break ; } case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: Fast : NestReg = <STR_LIT> ; break ; } SDValue OutChains [ <NUM_LIT> ] ; SDValue Addr , Disp ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Disp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPtr , Addr ) ; const unsigned char MOV32ri = <NUM_LIT> ; const unsigned char N86Reg = TRI -> getEncodingValue ( NestReg ) & <NUM_LIT> ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( MOV32ri | N86Reg , dl , <STR_LIT> ) , Trmp , MachinePointerInfo ( TrmpAddr ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; const unsigned char JMP = <NUM_LIT> ;


<s> return ( __m128d ) __builtin_ia32_loadhpd ( ( __v2df ) __A , __B ) ;


<s> Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeAllocSize ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Value * AlignArg = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . align = cast < ConstantInt > ( AlignArg ) -> getZExtValue ( ) ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; Info . vol = true ; Info . readMem = true ; Info . writeMem = false ; return true ; } case <STR_LIT> : case <STR_LIT> : { auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ;


<s> } } if ( ( pcum -> nregs & <NUM_LIT> ) && ARM_DOUBLEWORD_ALIGN ) { int res = arm_needs_doubleword_align ( arg . mode , arg . type ) ; if ( res < <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , arg . type ) ; else if ( res > <NUM_LIT> ) { pcum -> nregs ++ ; if ( res > <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , arg . type ) ;


<s> else if ( N -> getOpcode ( ) == <STR_LIT> ) FPOpcode = <STR_LIT> ; else if ( N -> getOpcode ( ) == <STR_LIT> ) FPOpcode = <STR_LIT> ; assert ( FPOpcode != <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> && ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 . getOperand ( <NUM_LIT> ) ; EVT N00Type = N00 . getValueType ( ) ; EVT N10Type = N10 . getValueType ( ) ; if ( N00Type . isFloatingPoint ( ) && N10Type . isFloatingPoint ( ) ) { SDValue FPLogic = DAG . getNode ( FPOpcode , DL , N00Type , N00 , N10 ) ;

return DAG . getBitcast ( VT , FPLogic ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performExtractVectorEltCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SDValue Vec = N -> getOperand ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; if ( ( Vec . getOpcode ( ) == <STR_LIT> || Vec . getOpcode ( ) == <STR_LIT> ) && allUsesHaveSourceMods ( N ) ) { SDLoc SL ( N ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; return DAG . getNode ( Vec . getOpcode ( ) , SL , EltVT , Elt ) ; } if ( Vec . hasOneUse ( ) && DCI . isBeforeLegalize ( ) ) { SDLoc SL ( N ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Vec . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; SDValue Elt1 = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; DCI . AddToWorklist ( Elt0 . getNode ( ) ) ; DCI . AddToWorklist ( Elt1 . getNode ( ) ) ; return DAG . getNode ( Opc , SL , EltVT , Elt0 , Elt1 , Vec -> getFlags ( ) ) ; } }


<s> bool <ISA_LIT>TargetLowering :: isSafeMemOpType ( MVT VT ) const {

if ( VT == <STR_LIT> ) return Subtarget . hasSSE1 ( ) ;


<s> __ev64_opaque__ t ; t = __ev_mwhsmf ( a , b ) ; return __ev_subfsmiaaw ( t ) ;


<s> static SDValue getEstimate ( const <ISA_LIT>Subtarget * ST , unsigned Opcode , SDValue Operand , SelectionDAG & DAG , int & ExtraSteps ) { EVT VT = Operand . getValueType ( ) ; if ( ST -> hasNEON ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) { if ( ExtraSteps == TargetLoweringBase :: ReciprocalEstimate :: Unspecified ) ExtraSteps = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ;

return DAG . getNode ( Opcode , SDLoc ( Operand ) , VT , Operand ) ;


<s> static unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; bool HasAVX = Subtarget -> hasAVX ( ) ; unsigned * Opc = nullptr ; switch ( RetVT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ HasAVX ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ HasAVX ] [ <NUM_LIT> ] ; break ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ;

unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ;


<s> unsigned <ISA_LIT>ClauseMergePass :: getCFAluSize ( const MachineInstr & MI ) const { assert ( isCFAlu ( MI ) ) ;

return MI . getOperand ( TII -> getOperandIdx ( MI . getOpcode ( ) , <STR_LIT> :: COUNT ) ) . getImm ( ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> auto Attr = F -> getFnAttribute ( Attribute :: VScaleRange ) ; if ( ! Attr . isValid ( ) ) return false ; unsigned MinVScale , MaxVScale ; std :: tie ( MinVScale , MaxVScale ) = Attr . getVScaleRangeArgs ( ) ; if ( MinVScale != MaxVScale || MinVScale == <NUM_LIT> ) return false ; auto * PredType = ScalableVectorType :: get ( Type :: getInt1Ty ( I -> getContext ( ) ) , <NUM_LIT> ) ; auto * FixedPredType = FixedVectorType :: get ( Type :: getInt8Ty ( I -> getContext ( ) ) , MinVScale * <NUM_LIT> ) ; auto * Store = dyn_cast < StoreInst > ( I ) ; if ( ! Store || ! Store -> isSimple ( ) ) return false ; if ( Store -> getOperand ( <NUM_LIT> ) -> getType ( ) != FixedPredType ) return false ; auto * IntrI = dyn_cast < IntrinsicInst > ( Store -> getOperand ( <NUM_LIT> ) ) ; if ( ! IntrI || IntrI -> getIntrinsicID ( ) != <STR_LIT> ) return false ; if ( ! cast < ConstantInt > ( IntrI -> getOperand ( <NUM_LIT> ) ) -> isZero ( ) ) return false ; auto * BitCast = dyn_cast < BitCastInst > ( IntrI -> getOperand ( <NUM_LIT> ) ) ; if ( ! BitCast ) return false ; if ( BitCast -> getOperand ( <NUM_LIT> ) -> getType ( ) != PredType ) return false ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; auto * PtrBitCast = Builder . CreateBitCast ( Store -> getPointerOperand ( ) , PredType -> getPointerTo ( Store -> getPointerAddressSpace ( ) ) ) ; Builder . CreateStore ( BitCast -> getOperand ( <NUM_LIT> ) , PtrBitCast ) ; Store -> eraseFromParent ( ) ;

if ( IntrI -> getNumUses ( ) == <NUM_LIT> ) IntrI -> eraseFromParent ( ) ;


<s> while ( -- i >= <NUM_LIT> ) RTX_FRAME_RELATED_P ( XVECEXP ( seq , <NUM_LIT> , i ) ) = <NUM_LIT> ; return emit_insn ( seq ) ;


<s> val_reg = force_reg ( DImode , val_exp ) ; reg = val_reg ; for ( ; ( i + <NUM_LIT> <= length ) ; i += <NUM_LIT> ) { addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , DImode , addr , i ) ; emit_move_insn ( mem , reg ) ; } } else val_reg = force_reg ( SImode , val_exp ) ; reg = ( use_strd_p ? gen_lowpart ( SImode , val_reg ) : val_reg ) ; for ( ; ( i + <NUM_LIT> <= length ) ; i += <NUM_LIT> ) { addr = plus_constant ( Pmode , dst , i ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) emit_move_insn ( mem , reg ) ; else emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; } if ( unaligned_access && i > <NUM_LIT> && ( i + <NUM_LIT> ) == length ) { addr = plus_constant ( Pmode , dst , i - <NUM_LIT> ) ; mem = adjust_automodify_address ( dstbase , SImode , addr , i - <NUM_LIT> ) ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT ) ; emit_insn ( gen_unaligned_storesi ( mem , reg ) ) ; return true ; }


<s> inline vector signed int vec_vcmpgtuw ( vector unsigned int a1 , vector unsigned int a2 ) { return ( vector signed int ) __builtin_altivec_vcmpgtuw ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> return new <ISA_LIT>ElimCompare ( TM ) ;


<s> return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Op -> getOperandUse ( <NUM_LIT> ) ) ;

Ops . push_back ( & OpIdx . value ( ) ) ;


<s> for ( unsigned I = Intr -> VAddrStart ; I < EndIdx ; I ++ ) { MachineOperand & SrcOp = MI . getOperand ( ArgOffset + I ) ; if ( ! SrcOp . isReg ( ) ) continue ; Register AddrReg = SrcOp . getReg ( ) ; if ( ( I < Intr -> GradientStart ) || ( I >= Intr -> GradientStart && I < Intr -> CoordStart && ! IsG16 ) || ( I >= Intr -> CoordStart && ! IsA16 ) ) { if ( ( I < Intr -> GradientStart ) && IsA16 && ( B . getMRI ( ) -> getType ( AddrReg ) == S16 ) ) { assert ( I == Intr -> BiasIndex && <STR_LIT> ) ; PackedAddrs . push_back ( B . buildBuildVector ( V2S16 , { AddrReg , B . buildUndef ( S16 ) . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ) ; } else { assert ( ( ! IsA16 || Intr -> NumBiasArgs == <NUM_LIT> || I != Intr -> BiasIndex ) && <STR_LIT> ) ;

AddrReg = B . buildBitcast ( V2S16 , AddrReg ) . getReg ( <NUM_LIT> ) ;


<s> if ( isIntS16Immediate ( CN , Imm ) && ( ! Align || isAligned ( * Align , Imm ) ) ) { Disp = DAG . getTargetConstant ( Imm , DL , CNType ) ; Base = DAG . getRegister ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CNType ) ; break ; } if ( ( CNType == <STR_LIT> || isInt < <NUM_LIT> > ( CNImm ) ) && ( ! Align || isAligned ( * Align , CNImm ) ) ) { int32_t Addr = ( int32_t ) CNImm ; Disp = DAG . getTargetConstant ( ( int16_t ) Addr , DL , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( int16_t ) Addr ) >> <NUM_LIT> , DL , <STR_LIT> ) ; uint32_t LIS = CNType == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Base = SDValue ( DAG . getMachineNode ( LIS , DL , CNType , Base ) , <NUM_LIT> ) ; break ; } } Disp = DAG . getTargetConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; fixupFuncForFI ( DAG , FI -> getIndex ( ) , N . getValueType ( ) ) ; } else Base = N ; break ; } case <STR_LIT> : break ; default : { FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ;

Base = FI ? N : N . getOperand ( <NUM_LIT> ) ;


<s> MachineFunction & MF = * FirstMI . getParent ( ) -> getParent ( ) ; if ( ! RegClass || ! MF . getRegInfo ( ) . tracksLiveness ( ) ) return false ; auto RegToRename = getLdStRegOp ( FirstMI ) . getReg ( ) ; if ( ! getLdStRegOp ( FirstMI ) . isKill ( ) && ! any_of ( FirstMI . operands ( ) , [ TRI , RegToRename ] ( const MachineOperand & MOP ) { return MOP . isReg ( ) && ! MOP . isDebug ( ) && MOP . getReg ( ) && MOP . isImplicit ( ) && MOP . isKill ( ) && TRI -> regsOverlap ( RegToRename , MOP . getReg ( ) ) ; } ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FirstMI << <STR_LIT> ) ; return false ; } auto canRenameMOP = [ ] ( const MachineOperand & MOP ) { return MOP . isImplicit ( ) || ( MOP . isRenamable ( ) && ! MOP . isEarlyClobber ( ) && ! MOP . isTied ( ) ) ; } ; bool FoundDef = false ; std :: function < bool ( MachineInstr & , bool ) > CheckMIs = [ & ] ( MachineInstr & MI , bool IsDef ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; if ( MI . getFlag ( MachineInstr :: FrameSetup ) ) {


<s> const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( Shift == <NUM_LIT> ) { if ( RetVT == SrcVT ) { unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) ; return ResultReg ; } else return emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; } if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return materializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ; if ( ! IsZExt ) { Op0 = emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; if ( ! Op0 ) return <NUM_LIT> ; Op0IsKill = true ; SrcVT = RetVT ; SrcBits = SrcVT . getSizeInBits ( ) ; IsZExt = true ; } unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ; unsigned ImmS = SrcBits - <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , {


<s> TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; RTLIB :: Libcall LC = isF64 ? RTLIB :: SINCOS_STRET_F64 : RTLIB :: SINCOS_STRET_F32 ; const char * LibcallName = TLI . getLibcallName ( LC ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy ) : ( Type * ) FixedVectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; if ( isF64 ) return CallResult . first ;

SDValue SinVal = DAG . getNode ( <STR_LIT> , dl , ArgVT , CallResult . first , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> bool sparc_tls_referenced_p ( rtx x ) {


<s> void <ISA_LIT>InstPrinter :: printCCOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { switch ( MI -> getOpcode ( ) ) { default :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;

return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { APInt immRaw = VFPExpandImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) , Opcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; APFloat immFP = APFloat ( immRaw , true ) ; double imm = Opcode == <STR_LIT> ? immFP . convertToDouble ( ) :


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> case <STR_LIT> : return performBitCastCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performShuffleCombine ( N , DAG , DCI , Subtarget ) ;


<s> unsigned PredState = getRegState ( PredOp ) & ~ RegState :: Kill ; MachineInstrBuilder MIB ; if ( SrcOp . isReg ( ) ) { unsigned SrcState = getRegState ( SrcOp ) ; if ( RegisterRef ( SrcOp ) == RegisterRef ( DstR , DstSR ) ) SrcState &= ~ RegState :: Kill ; MIB = BuildMI ( B , At , DL , HII -> get ( Opc ) ) . addReg ( DstR , DstState , DstSR ) . addReg ( PredOp . getReg ( ) , PredState , PredOp . getSubReg ( ) ) . addReg ( SrcOp . getReg ( ) , SrcState , SrcOp . getSubReg ( ) ) ; } else { MIB = BuildMI ( B , At , DL , HII -> get ( Opc ) ) . addReg ( DstR , DstState , DstSR ) . addReg ( PredOp . getReg ( ) , PredState , PredOp . getSubReg ( ) ) . add ( SrcOp ) ; }

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ;


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeFP ( const ConstantFP * CFP , MVT VT ) { const APFloat Val = CFP -> getValueAPF ( ) ; bool is64bit = VT == <STR_LIT> ; if ( TLI . isFPImmLegal ( Val , VT ) ) { int Imm ; unsigned Opc ; if ( is64bit ) { Imm = <STR_LIT> ( Val ) ; Opc = <STR_LIT> ; } else { Imm = <STR_LIT> ( Val ) ; Opc = <STR_LIT> ; } Register DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( Imm ) ) ; return DestReg ; } if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ;

unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Alignment ) ;


<s> putc ( '\n' , stream ) ; } else if ( write_symbols == DBX_DEBUG ) return ; else if ( name != current_function_file && strcmp ( name , current_function_file ) != <NUM_LIT> ) { num_source_filenames += <NUM_LIT> ; current_function_file = name ; fprintf ( stream , <STR_LIT> , num_source_filenames ) ;

output_quoted_string ( stream , name ) ;


<s> unsigned <STR_LIT> ( Type * Ty ) const {


<s> bool hasFineGrainedTraps ( ) const {


<s> emit_insn ( gen_rtx_CLOBBER ( VOIDmode , GEN_INT ( <NUM_LIT> ) ) ) ; return ; } emit_insn ( gen_prologue_start_marker ( ) ) ; if ( is_critical_func ( ) ) { emit_insn ( gen_push_intr_state ( ) ) ; emit_insn ( gen_disable_interrupts ( ) ) ; } else if ( is_reentrant_func ( ) ) emit_insn ( gen_disable_interrupts ( ) ) ; if ( ! cfun -> machine -> computed ) msp430_compute_frame_info ( ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> framesize ; if ( crtl -> args . pretend_args_size ) { rtx note ; gcc_assert ( crtl -> args . pretend_args_size == <NUM_LIT> ) ; p = emit_insn ( gen_grow_and_swap ( ) ) ; note = F ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , GEN_INT ( <NUM_LIT> ) ) ) ) ; add_reg_note ( p , REG_FRAME_RELATED_EXPR , note ) ; note = F ( gen_rtx_SET ( gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ) , pc_rtx ) ) ; add_reg_note ( p , REG_CFA_OFFSET , note ) ; F ( p ) ; } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( cfun -> machine -> need_to_save [ i ] ) { int seq , count ; rtx note ; for ( seq = i - <NUM_LIT> ; seq >= <NUM_LIT> && cfun -> machine -> need_to_save [ seq ] ; seq -- ) ; count = i - seq ; if ( msp430x ) { p = F ( emit_insn ( gen_pushm ( gen_rtx_REG ( Pmode , i ) , GEN_INT ( count ) ) ) ) ; note = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + <NUM_LIT> ) ) ; XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) = F ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( count * ( TARGET_LARGE ? - <NUM_LIT> : - <NUM_LIT> ) ) ) ) ) ;

for ( j = <NUM_LIT> ; j < count ; j ++ ) {


<s> void GCNPassConfig :: addPreLegalizeMachineIR ( ) {

bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ;


<s> if ( GET_MODE ( value ) == VOIDmode && size > <NUM_LIT> ) mode = Pmode ; else if ( GET_MODE_SIZE ( mode ) > GET_MODE_SIZE ( GET_MODE ( value ) ) ) mode = GET_MODE ( value ) ; } else mode = GET_MODE ( vec_value ) , value = vec_value ; } else { if ( size >= <NUM_LIT> ) mode = TARGET_AVX ? V32QImode : TARGET_SSE ? V16QImode : DImode ; else if ( size >= <NUM_LIT> ) mode = TARGET_SSE ? V16QImode : DImode ; srcmem = change_address ( srcmem , mode , srcptr ) ; } destmem = change_address ( destmem , mode , destptr ) ; modesize = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; gcc_assert ( GET_MODE_SIZE ( mode ) <= size ) ; for ( n = <NUM_LIT> ; n * GET_MODE_SIZE ( mode ) < size ; n ++ ) { if ( issetmem ) emit_move_insn ( destmem , gen_lowpart ( mode , value ) ) ; else { emit_move_insn ( destmem , srcmem ) ;

srcmem = offset_address ( srcmem , modesize , GET_MODE_SIZE ( mode ) ) ;


<s> for ( int i = ExtraSteps ; i > <NUM_LIT> ; -- i ) { SDValue Step = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Estimate , Flags ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , Flags ) ; } ExtraSteps = <NUM_LIT> ;


<s> const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ;

ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( Subtarget . hasCDI ( ) ) return LowerVectorCTLZ_AVX512CDI ( Op , DAG ) ; if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return Lower256IntUnary ( Op , DAG ) ; if ( VT . is512BitVector ( ) && ! Subtarget . hasBWI ( ) ) return Lower512IntUnary ( Op , DAG ) ; assert ( Subtarget . hasSSSE3 ( ) && <STR_LIT> ) ;

return LowerVectorCTLZInRegLUT ( Op , DL , Subtarget , DAG ) ;


<s> unsigned LOOPi = ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; for ( auto & I : PreHeader . instrs ( ) ) if ( I . getOpcode ( ) == LOOPi ) return & I ;


<s> assert ( caps < <STR_LIT> && <STR_LIT> ) ; return CapsOverride [ caps ] ;


<s> assert ( I . getOpcode ( ) == TargetOpcode :: G_UNMERGE_VALUES && <STR_LIT> ) ; if ( RBI . getRegBank ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) -> getID ( ) != <STR_LIT> || RBI . getRegBank ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) -> getID ( ) != <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } unsigned NumElts = I . getNumOperands ( ) - <NUM_LIT> ; Register SrcReg = I . getOperand ( NumElts ) . getReg ( ) ; const LLT NarrowTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const LLT WideTy = MRI . getType ( SrcReg ) ; ( void ) WideTy ; assert ( ( WideTy . isVector ( ) || WideTy . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; assert ( WideTy . getSizeInBits ( ) > NarrowTy . getSizeInBits ( ) && <STR_LIT> ) ; if ( ! NarrowTy . isScalar ( ) ) return selectSplitVectorUnmerge ( I , MRI ) ; MachineIRBuilder MIB ( I ) ; unsigned CopyOpc = <NUM_LIT> ; unsigned ExtractSubReg = <NUM_LIT> ; if ( ! getLaneCopyOpcode ( CopyOpc , ExtractSubReg , NarrowTy . getSizeInBits ( ) ) ) return false ; MachineBasicBlock & MBB = * I . getParent ( ) ; SmallVector < Register , <NUM_LIT> > InsertRegs ; unsigned NumInsertRegs = NumElts - <NUM_LIT> ; if ( NarrowTy . getSizeInBits ( ) * NumElts == <NUM_LIT> ) { InsertRegs = SmallVector < Register , <NUM_LIT> > ( NumInsertRegs , SrcReg ) ; } else { for ( unsigned Idx = <NUM_LIT> ; Idx < NumInsertRegs ; ++ Idx ) { Register ImpDefReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & ImpDefMI = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImpDefReg ) ;

Register InsertReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> DAG . getContext ( ) -> diagnose ( NoTrap ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> tau = ( ( v - sigma ) + w ) / c ; u = t + tau ; if ( nonfinite ( u ) ) return u ; z . dval [ <NUM_LIT> ] = u ; z . dval [ <NUM_LIT> ] = ( t - u ) + tau ;


<s> Lex ( ) ; const MCExpr * Value ; if ( Parser . parseExpression ( Value ) ) { TokError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { TokError ( <STR_LIT> ) ;


<s> for ( Function * Callee : AAEdges . getOptimisticEdges ( ) ) { <STR_LIT> IID = Callee -> getIntrinsicID ( ) ; if ( IID == <STR_LIT> ) { const AAAMDAttributes & AAAMD = A . getAAFor < AAAMDAttributes > ( * this , IRPosition :: function ( * Callee ) , DepClassTy :: REQUIRED ) ; * this &= AAAMD ; continue ; } bool NonKernelOnly = false ; ImplicitArgumentMask AttrMask = intrinsicToAttrMask ( IID , NonKernelOnly , NeedsImplicit , HasApertureRegs , SupportsGetDoorbellID ) ; if ( AttrMask != NOT_IMPLICIT_INPUT ) { if ( ( IsNonEntryFunc || ! NonKernelOnly ) ) removeAssumedBits ( AttrMask ) ; } } if ( NeedsImplicit ) removeAssumedBits ( IMPLICIT_ARG_PTR ) ; if ( isAssumed ( QUEUE_PTR ) && checkForQueuePtr ( A ) ) { if ( <STR_LIT> ( ) == <NUM_LIT> ) removeAssumedBits ( IMPLICIT_ARG_PTR ) ; else removeAssumedBits ( QUEUE_PTR ) ; } if ( funcRetrievesMultigridSyncArg ( A ) ) { assert ( ! isAssumed ( IMPLICIT_ARG_PTR ) && <STR_LIT> ) ; removeAssumedBits ( MULTIGRID_SYNC_ARG ) ; } if ( funcRetrievesHostcallPtr ( A ) ) { assert ( ! isAssumed ( IMPLICIT_ARG_PTR ) && <STR_LIT> ) ; removeAssumedBits ( HOSTCALL_PTR ) ;


<s> gcc_assert ( LABEL_P ( operands [ <NUM_LIT> ] ) ) ; length = get_attr_length ( insn ) ; if ( length <= <NUM_LIT> ) { return branch_if_true ; } rtx_code_label * not_taken = gen_label_rtx ( ) ; taken = operands [ <NUM_LIT> ] ;


<s> } const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstRB ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcRB ) ; if ( ! DstRC || ! SrcRC ) return false ; if ( canTurnIntoCOPY ( DstRC , SrcRC ) ) return selectTurnIntoCOPY ( I , MRI , DstReg , DstRC , SrcReg , SrcRC ) ; if ( DstRB . getID ( ) != <STR_LIT> ) return false ; unsigned SubIdx ; if ( DstRC == SrcRC ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else { return false ; } SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubIdx ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ;


<s> return parseRegs ( Operands , ( int ) <STR_LIT> ) ;


<s> static bool rs6000_use_blocks_for_decl_p ( const_tree decl ) { return ! DECL_THREAD_LOCAL_P ( decl ) ;


<s> rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && CONST_DOUBLE_P ( elt ) && ( real_equal ( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconsthalf ) || real_equal ( CONST_DOUBLE_REAL_VALUE ( elt ) , & dconst2 ) ) ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , TM ( tm ) , IsN64 ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_N64 ( ) ) , RI ( * TM . getSubtargetImpl ( ) , * this ) {


<s> unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return ( ( Size == <NUM_LIT> ) && ! Subtarget -> isMClass ( ) ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ;


<s> int64_t EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! isUInt < <NUM_LIT> > ( EncodedImm ) ) return None ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> static bool breaksVMEMSoftClause ( MachineInstr * MI ) {

return ! <ISA_LIT>InstrInfo :: isVMEM ( * MI ) && ! <ISA_LIT>InstrInfo :: isFLAT ( * MI ) ;


<s> const MCSectionMachO & RefSec = cast < MCSectionMachO > ( Symbol . getSection ( ) ) ;

return RefSec . getType ( ) != MachO :: S_CSTRING_LITERALS ;


<s> Expected < uint32_t > HSACodeObject :: getNoteSectionIdx ( ) const {

return getSectionIdxByName ( <STR_LIT> :: SectionName ) ;


<s> static int nds32_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) {


<s> uint64_t Flags = MCID . TSFlags ; if ( ( Flags & <STR_LIT> ) != <STR_LIT> ) continue ; if ( isVCTP ( & MI ) || MI . getOpcode ( ) == <STR_LIT> ) continue ; if ( isVectorPredicated ( & MI ) ) { if ( MI . mayLoad ( ) ) FalseLanesZero . insert ( & MI ) ; Predicated . insert ( & MI ) ; continue ; } if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; if ( ! producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) { if ( retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ) return false ; FalseLanesUnknown . insert ( & MI ) ; } else if ( ! isHorizontalReduction ( MI ) ) FalseLanesZero . insert ( & MI ) ; } auto HasPredicatedUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Predicated ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Predicated . count ( Use ) ) return false ; } return true ; } ; for ( auto * MI : reverse ( FalseLanesUnknown ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isDef ( ) ) continue ; if ( ! HasPredicatedUsers ( MI , MO , Predicated ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI . getRegAsmName ( MO . getReg ( ) ) << <STR_LIT> << * MI ) ; return false ; } } Predicated . insert ( MI ) ; } SmallSet < Register , <NUM_LIT> > LiveOuts ; SmallVector < MachineBasicBlock * , <NUM_LIT> > ExitBlocks ; ML . getExitBlocks ( ExitBlocks ) ; for ( auto * MBB : ExitBlocks ) for ( const MachineBasicBlock :: RegisterMaskPair & RegMask : MBB -> liveins ( ) ) if ( QPRs -> contains ( RegMask . PhysReg ) ) LiveOuts . insert ( RegMask . PhysReg ) ; SmallPtrSet < MachineInstr * , <NUM_LIT> > LiveMIs ;

assert ( ML . getNumBlocks ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( N == nullptr ) return new Node ( R ) ; if ( N -> Range == R ) { N -> Count ++ ; return N ; }

if ( R < N -> Range ) N -> Left = add ( N -> Left , R ) ;


return std :: find ( table . begin ( ) , table . end ( ) , CPU ) != table . end ( ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {

PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> else Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; return MCDisassembler :: Success ;


<s> { & getThe<ISA_LIT>Target ( ) } ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( * T ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ;

TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ;


<s> const MUBUFInfo * Info = getMUBUFInfoFromOpcode ( Opc ) ;

return Info ? Info -> BaseOpcode : - <NUM_LIT> ;


<s> if ( Op0 -> isUndef ( ) && ! IsTop ) return Op1 ;

if ( ( Op1 -> getOpcode ( ) == <STR_LIT> || Op1 -> getOpcode ( ) == <STR_LIT> ) && Op1 -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DCI . DAG . getNode ( Op1 -> getOpcode ( ) , SDLoc ( Op1 ) , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>PrepareForLiveIntervals ( ) ) ; addPass ( create<ISA_LIT>OptimizeLiveIntervals ( ) ) ; addPass ( create<ISA_LIT>StoreResults ( ) ) ; addPass ( create<ISA_LIT>RegStackify ( ) ) ; addPass ( create<ISA_LIT>RegColoring ( ) ) ; }


return ( __m128i ) __builtin_ia32_vcvtph2dq128_mask ( __A , ( __v4si ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> SDValue OpsY3 [ ] = { TmpY2 , TmpE2 , TmpY2 , TmpPR } ; TmpY3 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsY3 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpY3 . getValue ( <NUM_LIT> ) ; SDValue OpsQ0 [ ] = { Tmp1 , TmpY3 , F0 , TmpPR } ; TmpQ0 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsQ0 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpQ0 . getValue ( <NUM_LIT> ) ; SDValue OpsR0 [ ] = { Tmp2 , TmpQ0 , Tmp1 , TmpPR } ; TmpR0 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsR0 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpR0 . getValue ( <NUM_LIT> ) ; SDValue Ops [ ] = { TmpF5 , TmpY3 , TmpR0 , TmpQ0 , TmpPR } ; Result = CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; Chain = SDValue ( Result , <NUM_LIT> ) ; return Result ; } else { SDValue TmpQ2 , TmpR2 , TmpQ3 , TmpQ ; SDValue OpsQ2 [ ] = { TmpF3 , TmpY2 , F0 , TmpPR } ; TmpQ2 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsQ2 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpQ2 . getValue ( <NUM_LIT> ) ; SDValue OpsR2 [ ] = { TmpF4 , TmpQ2 , TmpF3 , TmpPR } ; TmpR2 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsR2 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpR2 . getValue ( <NUM_LIT> ) ; SDValue OpsQ3 [ ] = { TmpF5 , TmpR2 , TmpY2 , TmpQ2 , TmpPR } ; TmpQ3 = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , OpsQ3 , <NUM_LIT> ) , <NUM_LIT> ) ; Chain = TmpQ3 . getValue ( <NUM_LIT> ) ; if ( isSigned ) TmpQ = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , TmpQ3 ) , <NUM_LIT> ) ; else TmpQ = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , TmpQ3 ) , <NUM_LIT> ) ; Chain = TmpQ . getValue ( <NUM_LIT> ) ; if ( isModulus ) { SDValue FPminusB = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , minusB ) , <NUM_LIT> ) ; Chain = FPminusB . getValue ( <NUM_LIT> ) ; SDValue Remainder = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , TmpQ , FPminusB , TmpF1 ) , <NUM_LIT> ) ; Chain = Remainder . getValue ( <NUM_LIT> ) ; Result = CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , Remainder ) ; Chain = SDValue ( Result , <NUM_LIT> ) ;


<s> static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasBWI ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512BWCostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX512 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX2 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX2CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX ( ) ) if ( const auto * Entry = CostTableLookup ( AVX1CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ;

if ( ST -> hasSSE42 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE42CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ;


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS , IsLittleEndian ) ;


<s> for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , MBBE = MBB . end ( ) ; MBBI != MBBE ; ++ MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) continue ; if ( ! MI . getFlag ( MachineInstr :: FrameSetup ) ) break ; if ( ExpectEnd ) return CU :: UNWIND_MODE_DWARF ; if ( Opc == PushInstr ) { if ( SavedRegIdx >= CU_NUM_SAVED_REGS ) return CU :: UNWIND_MODE_DWARF ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Reg == ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) { ExpectEnd = true ; continue ; } SavedRegs [ SavedRegIdx ++ ] = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; StackAdjust += OffsetSize ; InstrOffset += PushInstrSize ; } else if ( Opc == MoveInstr ) { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DstReg != FramePtr || SrcReg != StackPtr ) return CU :: UNWIND_MODE_DWARF ; StackAdjust = <NUM_LIT> ; memset ( SavedRegs , <NUM_LIT> , sizeof ( SavedRegs ) ) ; SavedRegIdx = <NUM_LIT> ; InstrOffset += MoveInstrSize ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( StackSize ) return CU :: UNWIND_MODE_DWARF ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != MI . getOperand ( <NUM_LIT> ) . getReg ( ) || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != StackPtr || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return CU :: UNWIND_MODE_DWARF ; StackSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) / StackDivide ; SubtractInstrIdx += InstrOffset ; ExpectEnd = true ; } } uint32_t CompactUnwindEncoding = <NUM_LIT> ; StackAdjust /= StackDivide ; if ( HasFP ) { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust ) return CU :: UNWIND_MODE_DWARF ; uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame ( SavedRegs , Is64Bit ) ; if ( RegEnc == ~ <NUM_LIT> ) return CU :: UNWIND_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_MODE_BP_FRAME ; CompactUnwindEncoding |= ( StackAdjust & <NUM_LIT> ) << <NUM_LIT> ; CompactUnwindEncoding |= RegEnc & CU :: UNWIND_BP_FRAME_REGISTERS ; } else { ++ StackAdjust ; uint32_t TotalStackSize = StackAdjust + StackSize ; if ( ( TotalStackSize & <NUM_LIT> ) == TotalStackSize ) { CompactUnwindEncoding |= CU :: UNWIND_MODE_STACK_IMMD ; CompactUnwindEncoding |= ( TotalStackSize & <NUM_LIT> ) << <NUM_LIT> ; } else { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust ) return CU :: UNWIND_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_MODE_STACK_IND ;

CompactUnwindEncoding |= ( SubtractInstrIdx & <NUM_LIT> ) << <NUM_LIT> ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return getSubtargetImpl ( ) -> getTargetLowering ( ) ;


<s> bool isSImm6 ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( IsConstantImm ) IsValid = isInt < <NUM_LIT> > ( Imm ) ;

else IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;


<s> const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; StringRef FuncName ( <STR_LIT> ) ; if ( const ExternalSymbolSDNode * G = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) FuncName = G -> getSymbol ( ) ; else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ; DiagnosticInfoUnsupported NoCalls ( Fn , <STR_LIT> + FuncName ) ; DAG . getContext ( ) -> diagnose ( NoCalls ) ;


<s> bool <ISA_LIT>16FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { return true ;


<s> if ( ! SCEVPtr ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ;


<s> return __builtin_mve_vandq_m_sv8hi ( __arm_vuninitializedq_s16 ( ) , __a , __b , __p ) ;


return __builtin_mve_vrev32q_uv16qi ( __a ) ;


addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> <ISA_LIT>SchedStrategy :: <ISA_LIT>SchedStrategy ( const MachineSchedContext * C ) : GenericScheduler ( C ) {


<s> static SDValue extract128BitVector ( SDValue Vec , unsigned IdxVal , SelectionDAG & DAG , SDLoc dl ) { assert ( ( Vec . getValueType ( ) . is256BitVector ( ) || Vec . getValueType ( ) . is512BitVector ( ) ) && <STR_LIT> ) ;

return extractSubVector ( Vec , IdxVal , DAG , dl , <NUM_LIT> ) ;


<s> rtx tmp0 , tmp1 , cmp_op0 = * op0 , cmp_op1 = * op1 ; enum rtx_code fp_code = * code ; * code = NE ; switch ( fp_code ) { case UNORDERED : * code = EQ ; case ORDERED : tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; case UNEQ : * code = EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == HFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quiethfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == HFmode ) \ emit_insn ( gen_f ## CMP ## _quiethfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; break ; case LTGT : tmp0 = riscv_force_binary ( word_mode , LT , cmp_op0 , cmp_op1 ) ; tmp1 = riscv_force_binary ( word_mode , GT , cmp_op0 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , IOR , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ;


<s> IsNSA = Info -> MIMGEncoding == <STR_LIT> ; if ( ! IsNSA ) { if ( AddrSize > <NUM_LIT> ) AddrSize = <NUM_LIT> ; } else { if ( AddrSize > Info -> VAddrDwords ) { return MCDisassembler :: Success ; } } } unsigned DMask = MI . getOperand ( DMaskIdx ) . getImm ( ) & <NUM_LIT> ; unsigned DstSize = IsGather4 ? <NUM_LIT> : std :: max ( countPopulation ( DMask ) , <NUM_LIT> ) ; bool D16 = D16Idx >= <NUM_LIT> && MI . getOperand ( D16Idx ) . getImm ( ) ; if ( D16 && <STR_LIT> ( STI ) ) { DstSize = ( DstSize + <NUM_LIT> ) / <NUM_LIT> ; } if ( TFEIdx != - <NUM_LIT> && MI . getOperand ( TFEIdx ) . getImm ( ) ) DstSize += <NUM_LIT> ; if ( DstSize == Info -> VDataDwords && AddrSize == Info -> VAddrDwords ) return MCDisassembler :: Success ; int NewOpcode = <STR_LIT> ( Info -> BaseOpcode , Info -> MIMGEncoding , DstSize , AddrSize ) ; if ( NewOpcode == - <NUM_LIT> ) return MCDisassembler :: Success ; unsigned NewVdata = <STR_LIT> ; if ( DstSize != Info -> VDataDwords ) { auto DataRCID = MCII -> get ( NewOpcode ) . OpInfo [ VDataIdx ] . RegClass ; unsigned Vdata0 = MI . getOperand ( VDataIdx ) . getReg ( ) ; unsigned VdataSub0 = MRI . getSubReg ( Vdata0 , <STR_LIT> ) ; Vdata0 = ( VdataSub0 != <NUM_LIT> ) ? VdataSub0 : Vdata0 ; NewVdata = MRI . getMatchingSuperReg ( Vdata0 , <STR_LIT> , & MRI . getRegClass ( DataRCID ) ) ; if ( NewVdata == <STR_LIT> ) { return MCDisassembler :: Success ; } } unsigned NewVAddr0 = <STR_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] && ! IsNSA && AddrSize != Info -> VAddrDwords ) { unsigned VAddr0 = MI . getOperand ( VAddr0Idx ) . getReg ( ) ; unsigned VAddrSub0 = MRI . getSubReg ( VAddr0 , <STR_LIT> ) ; VAddr0 = ( VAddrSub0 != <NUM_LIT> ) ? VAddrSub0 : VAddr0 ; auto AddrRCID = MCII -> get ( NewOpcode ) . OpInfo [ VAddr0Idx ] . RegClass ; NewVAddr0 = MRI . getMatchingSuperReg ( VAddr0 , <STR_LIT> , & MRI . getRegClass ( AddrRCID ) ) ; if ( NewVAddr0 == <STR_LIT> ) return MCDisassembler :: Success ;


<s> if ( ptx_name ) maybe_unlink ( ptx_name ) ; if ( omp_requires_file ) maybe_unlink ( omp_requires_file ) ;


<s> case 'y' : case 'x' : case 'Y' : case 'l' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' :


<s> if ( offset + sizeof ( T ) > r . size ( ) ) return true ; T ret = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < sizeof ( T ) ; ++ i ) ret |= ( uint64_t ) r [ offset + i ] << ( i * <NUM_LIT> ) ; ptr = ret ;


<s> CompositeHandler ( Function & F ) : Func ( & F ) {


<s> int regno , indx , off , nregs ; rtx insn , reg , mem ; int frame_allocated = <NUM_LIT> ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( <NUM_LIT> << regno ) ) ; ) regno ++ ; end_reg = regno - <NUM_LIT> ; nregs = end_reg - start_reg + <NUM_LIT> ; nregs += save_blink ? <NUM_LIT> : <NUM_LIT> ; nregs += save_fp ? <NUM_LIT> : <NUM_LIT> ; if ( offset ) frame_stack_add ( offset ) ; insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + ( save_fp ? <NUM_LIT> : <NUM_LIT> ) + <NUM_LIT> ) ) ; indx = <NUM_LIT> ; reg = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - nregs * UNITS_PER_WORD ) ) ; RTX_FRAME_RELATED_P ( reg ) = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; save_blink = false ; } for ( regno = start_reg ; regno <= end_reg ; regno ++ , indx ++ , off -= UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; }


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelDyn ( ) const { assert ( m_pRelDyn != NULL ) ;


<s> int RegIdx = TotalBytes - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT VT = Args [ i ] . VT ; unsigned Reg ; if ( VT == <STR_LIT> ) { Reg = CCInfo . AllocateReg ( RegList8 [ RegIdx ] ) ; } else if ( VT == <STR_LIT> ) { Reg = CCInfo . AllocateReg ( RegList16 [ RegIdx ] ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } assert ( Reg && <STR_LIT> ) ; CCInfo . addLoc ( CCValAssign :: getReg ( i , VT , Reg , VT , CCValAssign :: Full ) ) ; RegIdx -= VT . getStoreSize ( ) ; }


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const Target & T , StringRef TT ) { MCAsmInfo * MAI = new <ISA_LIT>LinuxMCAsmInfo ( T , TT ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ;

MachineLocation Src ( <STR_LIT> , <NUM_LIT> ) ;


<s> unsigned CorrectPosV2 = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = ( int ) VT . getVectorNumElements ( ) ; i != e ; ++ i ) if ( Mask [ i ] == i ) ++ CorrectPosV1 ; else if ( Mask [ i ] == i + <NUM_LIT> ) ++ CorrectPosV2 ; if ( CorrectPosV1 == <NUM_LIT> || CorrectPosV2 == <NUM_LIT> ) return true ;


<s> static __inline __m64 _mm_setzero_si64 ( void ) { return __builtin_arm_wzero ( ) ;


<s> AU . addRequired < LegacyDivergenceAnalysis > ( ) ;

if ( ! ExpandDiv64InIR ) AU . setPreservesAll ( ) ;


<s> case UNSPEC_CHKACLR : case UNSPEC_CHKS : return may_trap_p_1 ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , flags ) ; }

return default_unspec_may_trap_p ( x , flags ) ;


<s> unsigned <STR_LIT> ( ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) const { if ( Kind != SK_Reverse ) return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; static const CostTblEntry < <STR_LIT> > NEONShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; int Idx = CostTableLookup ( NEONShuffleTbl , <STR_LIT> , LT . second ) ;

if ( Idx == - <NUM_LIT> ) return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ;


<s> struct machine_function * machine ; machine = ( machine_function * ) ggc_alloc_cleared ( sizeof ( machine_function ) ) ; machine -> func_type = ARM_FT_UNKNOWN ;


<s> void mmix_setup_frame_addresses ( ) {


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , true ) {


<s> return new <ISA_LIT>LowerControlFlowPass ( tm ) ;


<s> if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , <NUM_LIT> ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , <NUM_LIT> ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; }

else if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( SET_DEST ( curr_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && GET_CODE ( SET_SRC ( prev_set ) ) == HIGH && REGNO ( SET_DEST ( curr_set ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ;


<s> int Elt1 = MaskVals [ i * <NUM_LIT> + <NUM_LIT> ] ; if ( Elt0 < <NUM_LIT> && Elt1 < <NUM_LIT> ) continue ; if ( V1Only && ( Elt0 == i * <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; if ( V2Only && ( Elt0 == i * <NUM_LIT> + <NUM_LIT> ) && ( Elt1 == i * <NUM_LIT> + <NUM_LIT> ) ) continue ; SDValue Elt0Src = Elt0 < <NUM_LIT> ? V1 : V2 ; SDValue Elt1Src = Elt1 < <NUM_LIT> ? V1 : V2 ; SDValue InsElt ; if ( ( Elt0 >= <NUM_LIT> ) && ( ( Elt0 + <NUM_LIT> ) == Elt1 ) && ( ( Elt0 & <NUM_LIT> ) == <NUM_LIT> ) ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; NewV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV , InsElt , DAG . getIntPtrConstant ( i ) ) ; continue ; } if ( Elt1 >= <NUM_LIT> ) { InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt1Src , DAG . getIntPtrConstant ( Elt1 / <NUM_LIT> ) ) ; if ( ( Elt1 & <NUM_LIT> ) == <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , TLI . getShiftAmountTy ( InsElt . getValueType ( ) ) ) ) ; else if ( Elt0 >= <NUM_LIT> ) InsElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InsElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } if ( Elt0 >= <NUM_LIT> ) {

SDValue InsElt0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Elt0Src , DAG . getIntPtrConstant ( Elt0 / <NUM_LIT> ) ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , STI ( TM . getMCSubtargetInfo ( ) ) {


<s> if ( QII -> isPostIncrement ( PacketMI ) && PacketMI -> getDesc ( ) . mayLoad ( ) && GetPostIncrementOperand ( PacketMI , QII ) . getReg ( ) == DepReg ) { return false ; } if ( QII -> isPredicated ( PacketMI ) ) { if ( ! QII -> isPredicated ( MI ) ) return false ; unsigned predRegNumSrc = <NUM_LIT> ; unsigned predRegNumDst = <NUM_LIT> ; const TargetRegisterClass * predRegClass = NULL ; for ( unsigned opNum = <NUM_LIT> ; opNum < PacketMI -> getNumOperands ( ) ; opNum ++ ) { if ( PacketMI -> getOperand ( opNum ) . isReg ( ) ) predRegNumSrc = PacketMI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumSrc ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) ) predRegNumDst = MI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumDst ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; if ( ( predRegNumDst != predRegNumSrc ) || isDotNewInst ( PacketMI ) != isDotNewInst ( MI ) || GetPredicateSense ( MI , QII ) != GetPredicateSense ( PacketMI , QII ) ) { return false ; } } std :: vector < MachineInstr * > :: iterator VI ; std :: vector < MachineInstr * > :: iterator VE ; unsigned StartCheck = <NUM_LIT> ; for ( VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE ) ; ++ VI ) { SUnit * TempSU = MIToSUnit [ * VI ] ; MachineInstr * TempMI = TempSU -> getInstr ( ) ; if ( TempMI != PacketMI && ! StartCheck ) continue ; StartCheck = <NUM_LIT> ; if ( TempMI == PacketMI ) continue ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) && TempSU -> getInstr ( ) -> modifiesRegister ( MI -> getOperand ( opNum ) . getReg ( ) , QRI ) ) return false ; }


<s> DebugLoc DL = MI . getDebugLoc ( ) ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; assert ( MFI -> getShaderType ( ) == ShaderType :: PIXEL || MFI -> getShaderType ( ) == ShaderType :: GEOMETRY ) ; if ( ( Op . isImm ( ) || Op . isFPImm ( ) ) ) { if ( Op . isImm ( ) ? ( Op . getImm ( ) & <NUM_LIT> ) : Op . getFPImm ( ) -> isNegative ( ) ) { BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_MOV_B64 ) , AMDGPU :: EXEC ) . addImm ( <NUM_LIT> ) ; } } else {

BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: V_CMPX_LE_F32_e32 ) , AMDGPU :: VCC ) . addImm ( <NUM_LIT> ) . addOperand ( Op ) ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> const <ISA_LIT>TargetLowering * getTLI ( ) const { return TLI ;


<s> break ; } for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Count < Limit ) && RegNum == PRegNum + <NUM_LIT> ) ) && ( ! STI -> isSwift ( ) || isNotVFP || Count != <NUM_LIT> || ! ( PRegNum & <NUM_LIT> ) ) ) { Offset += Size ; PRegNum = RegNum ; ++ Count ; } else { MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps , Merges ) ; return ; }

if ( MemOps [ i ] . Position > MemOps [ insertAfter ] . Position ) insertAfter = i ;


<s> raw_string_ostream ExpectedTargetOS ( ExpectedTarget ) ; IsaInfo :: streamIsaVersion ( & getSTI ( ) , ExpectedTargetOS ) ; if ( Target != ExpectedTargetOS . str ( ) ) return Error ( TargetRange . Start , <STR_LIT> , TargetRange ) ;

getTargetStreamer ( ) . EmitDirectiveAMDGCNTarget ( Target ) ;


<s> if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onEq ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onNE ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onLT ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onLE ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) {


<s> DiagnosticInfoUnsupported NoTrap ( B . getMF ( ) . getFunction ( ) , <STR_LIT> , MI . getDebugLoc ( ) , DS_Warning ) ; LLVMContext & Ctx = B . getMF ( ) . getFunction ( ) . getContext ( ) ; Ctx . diagnose ( NoTrap ) ; } else { B . buildInstr ( <STR_LIT> ) . addImm ( static_cast < unsigned > ( GCNSubtarget :: TrapID :: LLVMAMDHSADebugTrap ) ) ; } MI . eraseFromParent ( ) ;


<s> MachineSDNode * <ISA_LIT>TargetLowering :: buildScratchRSRC ( SelectionDAG & DAG , SDLoc DL , SDValue Ptr ) const {

const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ;


<s> for ( unsigned int i = <NUM_LIT> ; i < builder . encoded_nelts ( ) ; ++ i ) if ( ( i & ( elt_size - <NUM_LIT> ) ) == <NUM_LIT> && INTVAL ( builder . elt ( i ) ) == <NUM_LIT> ) inv_builder . quick_push ( const1_rtx ) ; else inv_builder . quick_push ( const0_rtx ) ; inv_builder . finalize ( ) ; rtx inv = aarch64_expand_sve_const_pred_1 ( NULL_RTX , inv_builder , false ) ; if ( ! inv ) return NULL_RTX ; rtx mask = aarch64_ptrue_all ( elt_size ) ; mask = force_reg ( VNx16BImode , mask ) ; inv = gen_lowpart ( VNx16BImode , inv ) ;

target = aarch64_target_reg ( target , VNx16BImode ) ;


<s> rtx dst = ix86_fixup_binary_operands ( code , mode , operands ) ;

gcc_assert ( dst == operands [ <NUM_LIT> ] ) ;


<s> assert ( Subtarget -> hasFp256 ( ) && <STR_LIT> ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; static const int Mask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT> ) , & Mask [ <NUM_LIT> ] ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ;


<s> bool <ISA_LIT>ATTAsmParser :: isDstOp ( <ISA_LIT>Operand & Op ) { unsigned basereg = Is64Bit ? <STR_LIT> : <STR_LIT> ; return Op . isMem ( ) && Op . Mem . SegReg == <STR_LIT> && isa < MCConstantExpr > ( Op . Mem . Disp ) && cast < MCConstantExpr > ( Op . Mem . Disp ) -> getValue ( ) == <NUM_LIT> && Op . Mem . BaseReg == basereg && Op . Mem . IndexReg == <NUM_LIT> ;


<s> return __builtin_mve_vclzq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __p ) ;


<s> unsigned RegD = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = false ; RegD = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegD , & isSPVFP ) ; if ( ! isSPVFP ) Binary |= RegD << <STR_LIT> ; else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ;

Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ;


<s> if ( cum -> float_in_sse < <NUM_LIT> ) break ; case E_SFmode : if ( cum -> float_in_sse == - <NUM_LIT> ) error_p = true ; if ( cum -> float_in_sse < <NUM_LIT> ) break ; case E_V16HFmode : case E_V16BFmode : case E_V8SFmode : case E_V8SImode : case E_V64QImode : case E_V32HImode : case E_V16SImode : case E_V8DImode : case E_V32HFmode : case E_V32BFmode : case E_V16SFmode : case E_V8DFmode : case E_V32QImode : case E_V16HImode : case E_V4DFmode : case E_V4DImode : case E_TImode : case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V8HFmode : case E_V8BFmode : case E_V4SFmode : case E_V2DFmode : if ( ! type || ! AGGREGATE_TYPE_P ( type ) ) { cum -> sse_words += words ; cum -> sse_nregs -= <NUM_LIT> ;


<s> <ISA_LIT>Operand Op = static_cast < <ISA_LIT>Operand & > ( * Operands . back ( ) ) ; Operands . pop_back ( ) ;

Operands . push_back ( <STR_LIT> ( Op , S , E , * this ) ) ;


<s> EmitIntValue ( Entry , <NUM_LIT> , <NUM_LIT> ) ; } SwitchToExIdxSection ( * FnStart ) ; if ( PersonalityIndex == <NUM_LIT> ) EmitPersonalityFixup ( <STR_LIT> ) ; const MCSymbolRefExpr * FnStartRef = MCSymbolRefExpr :: Create ( FnStart , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( FnStartRef , <NUM_LIT> , <NUM_LIT> ) ; if ( CantUnwind ) { EmitIntValue ( EXIDX_CANTUNWIND , <NUM_LIT> , <NUM_LIT> ) ; } else { const MCSymbolRefExpr * ExTabEntryRef = MCSymbolRefExpr :: Create ( ExTab , MCSymbolRefExpr :: VK_<ISA_LIT>_PREL31 , getContext ( ) ) ; EmitValue ( ExTabEntryRef , <NUM_LIT> , <NUM_LIT> ) ;


<s> const std :: vector < MachineBasicBlock * > & Blocks = L -> getBlocks ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Blocks [ <NUM_LIT> ] -> getNumber ( ) ; ) ; for ( unsigned i = <NUM_LIT> , e = Blocks . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = Blocks [ i ] ; for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) , E = MBB -> end ( ) ; MII != E ; ++ MII ) { const MachineInstr * MI = & * MII ; if ( isInvalidLoopOperation ( MI , IsInnerHWLoop ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; MI -> dump ( ) ; ) ; return true ; } }


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ;


<s> DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; <ISA_LIT>FunctionInfo * AFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; int BccOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , dl , get ( BOpc ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false ;


<s> rtx tmp = gen_rtx_REG ( Pmode , ( * next_scratch_regno ) -- ) ; tilepro_expand_set_const32 ( tmp , imm_rtx ) ; to_add = tmp ; } insn = emit_insn ( gen_sp_adjust ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ) ; REG_NOTES ( insn ) = reg_notes ; if ( frame_related ) { rtx real = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , imm_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , real ) ; } return insn ;


<s> static bool CompareMBBNumbers ( const MachineBasicBlock * LHS , const MachineBasicBlock * RHS ) {

return LHS -> getNumber ( ) < RHS -> getNumber ( ) ;


<s> struct ix86_address addr ; if ( ! TARGET_TLS_DIRECT_SEG_REFS ) return orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) != PLUS || GET_MODE ( x ) != Pmode ) return orig_x ; if ( ix86_decompose_address ( x , & addr ) == <NUM_LIT> || addr . seg != DEFAULT_TLS_SEG_REG || addr . disp == NULL_RTX || GET_CODE ( addr . disp ) != CONST ) return orig_x ; unspec = XEXP ( addr . disp , <NUM_LIT> ) ;

if ( GET_CODE ( unspec ) == PLUS && CONST_INT_P ( XEXP ( unspec , <NUM_LIT> ) ) ) unspec = XEXP ( unspec , <NUM_LIT> ) ;


<s> SDValue TargetAddr = DAG . getTargetGlobalAddress ( GlobalAddr -> getGlobal ( ) , Op , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , Op , VT , TargetAddr ) ;


<s> if ( MI -> getOperand ( Op + <NUM_LIT> ) . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; }


<s> static void darwin_rs6000_extra_signals ( void ) { struct sigaction sact ; stack_t sigstk ; sigstk . ss_sp = ( char * ) xmalloc ( SIGSTKSZ ) ; sigstk . ss_size = SIGSTKSZ ; sigstk . ss_flags = <NUM_LIT> ; if ( sigaltstack ( & sigstk , NULL ) < <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> ) ;


<s> if ( ParseAsAbsoluteExpression ( Stepping ) ) return TokError ( <STR_LIT> ) ; if ( ! trySkipToken ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; if ( ! parseString ( VendorName , <STR_LIT> ) ) return true ; if ( ! trySkipToken ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ;

if ( ! parseString ( ArchName , <STR_LIT> ) ) return true ;


<s> return ggc_cleared_alloc < machine_function > ( ) ;


<s> const <ISA_LIT>TargetLowering * TLI = Subtarget . getTargetLowering ( ) ; ArgFlags . setInConsecutiveRegs ( false ) ; ArgFlags . setInConsecutiveRegsLast ( false ) ; bool RegsAllocated [ <NUM_LIT> ] ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) { RegsAllocated [ I ] = State . isAllocated ( ZRegList [ I ] ) ; State . AllocateReg ( ZRegList [ I ] ) ; } auto & It = PendingMembers [ <NUM_LIT> ] ; CCAssignFn * AssignFn = TLI -> CCAssignFnForCall ( State . getCallingConv ( ) , false ) ; if ( AssignFn ( It . getValNo ( ) , It . getValVT ( ) , It . getValVT ( ) , CCValAssign :: Full , ArgFlags , State ) ) llvm_unreachable ( <STR_LIT> ) ; ArgFlags . setInConsecutiveRegs ( true ) ; ArgFlags . setInConsecutiveRegsLast ( true ) ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) if ( ! RegsAllocated [ I ] ) State . DeallocateReg ( ZRegList [ I ] ) ; PendingMembers . clear ( ) ; return true ;


<s> return Kind == k_FPImm && ( getFPImm ( ) != ( unsigned ) - <NUM_LIT> ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> if ( ( Value == - <NUM_LIT> && C . CCMask == <STR_LIT> ) || ( Value == - <NUM_LIT> && C . CCMask == <STR_LIT> ) || ( Value == <NUM_LIT> && C . CCMask == <STR_LIT> ) || ( Value == <NUM_LIT> && C . CCMask == <STR_LIT> ) ) { C . CCMask ^= <STR_LIT> ; C . Op1 = DAG . getConstant ( <NUM_LIT> , C . Op1 . getValueType ( ) ) ; }


<s> auto * Ordering = dyn_cast < ConstantInt > ( Inst -> getArgOperand ( <NUM_LIT> ) ) ; auto * Volatile = dyn_cast < ConstantInt > ( Inst -> getArgOperand ( <NUM_LIT> ) ) ; if ( ! Ordering || ! Volatile ) return false ; unsigned OrderingVal = Ordering -> getZExtValue ( ) ; if ( OrderingVal > static_cast < unsigned > ( AtomicOrdering :: SequentiallyConsistent ) ) return false ; Info . PtrVal = Inst -> getArgOperand ( <NUM_LIT> ) ; Info . Ordering = static_cast < AtomicOrdering > ( OrderingVal ) ; Info . ReadMem = true ; Info . WriteMem = true ; Info . IsVolatile = ! Volatile -> isZero ( ) ; return true ; } default :


<s> if ( V2 . isUndef ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; } SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue Op = lowerVectorShuffleWithSHUFPD ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Op ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> } } ProgInfo . NumSGPR = std :: max ( ProgInfo . NumSGPR , WaveDispatchNumSGPR ) ; ProgInfo . NumArchVGPR = std :: max ( ProgInfo . NumVGPR , WaveDispatchNumVGPR ) ; ProgInfo . NumVGPR = Info . getTotalNumVGPRs ( STM , Info . NumAGPR , ProgInfo . NumArchVGPR ) ; } ProgInfo . NumSGPRsForWavesPerEU = std :: max ( std :: max ( ProgInfo . NumSGPR , <NUM_LIT> ) , STM . getMinNumSGPRs ( MFI -> getMaxWavesPerEU ( ) ) ) ; ProgInfo . NumVGPRsForWavesPerEU = std :: max ( std :: max ( ProgInfo . NumVGPR , <NUM_LIT> ) , STM . getMinNumVGPRs ( MFI -> getMaxWavesPerEU ( ) ) ) ; if ( STM . getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS || STM . hasSGPRInitBug ( ) ) { unsigned MaxAddressableNumSGPRs = STM . getAddressableNumSGPRs ( ) ; if ( ProgInfo . NumSGPR > MaxAddressableNumSGPRs ) { LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; DiagnosticInfoResourceLimit Diag ( MF . getFunction ( ) , <STR_LIT> , ProgInfo . NumSGPR , MaxAddressableNumSGPRs , DS_Error , DK_ResourceLimit ) ; Ctx . diagnose ( Diag ) ; ProgInfo . NumSGPR = MaxAddressableNumSGPRs ; ProgInfo . NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs ; } } if ( STM . hasSGPRInitBug ( ) ) { ProgInfo . NumSGPR = <STR_LIT> :: FIXED_NUM_SGPRS_FOR_INIT_BUG ; ProgInfo . NumSGPRsForWavesPerEU = <STR_LIT> :: FIXED_NUM_SGPRS_FOR_INIT_BUG ; } if ( MFI -> getNumUserSGPRs ( ) > STM . getMaxNumUserSGPRs ( ) ) { LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; DiagnosticInfoResourceLimit Diag ( MF . getFunction ( ) , <STR_LIT> , MFI -> getNumUserSGPRs ( ) , STM . getMaxNumUserSGPRs ( ) , DS_Error ) ; Ctx . diagnose ( Diag ) ; } if ( MFI -> getLDSSize ( ) > static_cast < unsigned > ( STM . getLocalMemorySize ( ) ) ) { LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; DiagnosticInfoResourceLimit Diag ( MF . getFunction ( ) , <STR_LIT> , MFI -> getLDSSize ( ) , STM . getLocalMemorySize ( ) , DS_Error ) ; Ctx . diagnose ( Diag ) ; } ProgInfo . SGPRBlocks = IsaInfo :: getNumSGPRBlocks ( & STM , ProgInfo . NumSGPRsForWavesPerEU ) ; ProgInfo . VGPRBlocks = IsaInfo :: getNumVGPRBlocks ( & STM , ProgInfo . NumVGPRsForWavesPerEU ) ; const <ISA_LIT>ModeRegisterDefaults Mode = MFI -> getMode ( ) ; ProgInfo . FloatMode = getFPMode ( Mode ) ; ProgInfo . IEEEMode = Mode . IEEE ; ProgInfo . DX10Clamp = Mode . DX10Clamp ; unsigned LDSAlignShift ; if ( STM . getGeneration ( ) < <ISA_LIT>Subtarget :: SEA_ISLANDS ) { LDSAlignShift = <NUM_LIT> ; } else { LDSAlignShift = <NUM_LIT> ; }

unsigned LDSSpillSize = MFI -> getLDSWaveSpillSize ( ) * MFI -> getMaxFlatWorkGroupSize ( ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateFGRReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) {

return CreateReg ( Index , RegKind_FGR , RegInfo , S , E , Parser ) ;


<s> static __inline qword si_fms ( qword a , qword b , qword c ) {

return ( ( qword ) ( vec_madd ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) , vec_sub ( ( ( vec_float4 ) { <NUM_LIT> } ) , ( vec_float4 ) ( c ) ) ) ) ) ;


<s> constexpr sve_vec_cost ( const simd_vec_cost & base , unsigned int clast_cost , unsigned int fadda_f16_cost , unsigned int fadda_f32_cost , unsigned int fadda_f64_cost , unsigned int scatter_store_elt_cost ) : simd_vec_cost ( base ) , clast_cost ( clast_cost ) , fadda_f16_cost ( fadda_f16_cost ) , fadda_f32_cost ( fadda_f32_cost ) , fadda_f64_cost ( fadda_f64_cost ) , scatter_store_elt_cost ( scatter_store_elt_cost ) {


<s> return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> case NE : return <NUM_LIT> ; case LTU : return <NUM_LIT> ; case GEU : return <NUM_LIT> ; case GT : return <NUM_LIT> ; case LE : return <NUM_LIT> ; case GE : return <NUM_LIT> ; case LT : return <NUM_LIT> ; case GTU : return <NUM_LIT> ; case LEU : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } case CC_N_NEmode : switch ( GET_CODE ( comparison ) ) { case EQ : return <NUM_LIT> ; case NE : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } case CC_C_LTUmode : switch ( GET_CODE ( comparison ) ) { case GEU : return <NUM_LIT> ; case LTU : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } case CC_C_GTUmode : switch ( GET_CODE ( comparison ) ) { case LEU : return <NUM_LIT> ; case GTU : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } case CC_FPmode : switch ( GET_CODE ( comparison ) ) { case EQ : return <NUM_LIT> ; case NE : return <NUM_LIT> ; case LT : return <NUM_LIT> ; case LE : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } case CC_FP_EQmode : switch ( GET_CODE ( comparison ) ) { case EQ : return <NUM_LIT> ; case NE : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } case CC_FP_GTEmode : switch ( GET_CODE ( comparison ) ) { case EQ : return <NUM_LIT> ; case NE : return <NUM_LIT> ; case GT : return <NUM_LIT> ; case GE : return <NUM_LIT> ; case UNLE : return <NUM_LIT> ; case UNLT : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } case CC_FP_ORDmode : switch ( GET_CODE ( comparison ) ) { case ORDERED : return <NUM_LIT> ; case UNORDERED : return <NUM_LIT> ; default : gcc_unreachable ( ) ;


<s> const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Register ) ; Op -> Reg . Num = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> } else { cpp_define ( pfile , <STR_LIT> ) ; } if ( AVR_HAVE_8BIT_SP ) cpp_define ( pfile , <STR_LIT> ) ; else cpp_define ( pfile , <STR_LIT> ) ; if ( AVR_HAVE_SPH ) cpp_define ( pfile , <STR_LIT> ) ; else cpp_define ( pfile , <STR_LIT> ) ; if ( TARGET_NO_INTERRUPTS ) cpp_define ( pfile , <STR_LIT> ) ; if ( TARGET_SKIP_BUG ) { cpp_define ( pfile , <STR_LIT> ) ; if ( AVR_HAVE_JMP_CALL ) cpp_define ( pfile , <STR_LIT> ) ; } if ( TARGET_RMW ) cpp_define ( pfile , <STR_LIT> ) ; cpp_define_formatted ( pfile , <STR_LIT> , avr_arch -> sfr_offset ) ; cpp_define ( pfile , <STR_LIT> ) ; if ( lang_GNU_C ( ) ) {

for ( int i = <NUM_LIT> ; i < ADDR_SPACE_COUNT ; i ++ ) if ( ! ADDR_SPACE_GENERIC_P ( i ) && avr_addr_space_supported_p ( ( addr_space_t ) i ) ) {


<s> if ( ! isMemoryBound ( ) && ! needsWaveLimiter ( ) ) return Occupancy ;

return ( Occupancy < <NUM_LIT> ) ? Occupancy : <NUM_LIT> ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( const auto & OpIdx : enumerate ( Op -> ops ( ) ) ) { SDValue V = OpIdx . value ( ) ; assert ( ! isa < VTSDNode > ( V ) && <STR_LIT> ) ; if ( ! V . getValueType ( ) . isFixedLengthVector ( ) ) { Ops . push_back ( V ) ; continue ; } MVT OpVT = V . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( OpVT ) ; assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; }

if ( ! VT . isFixedLengthVector ( ) ) return DAG . getNode ( <ISA_LIT>ISDOpc , DL , VT , Ops ) ;


<s> if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) {

BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( RoundMode . Val ) ) ;


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . BaseRegNum != <STR_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ;

int64_t Val = Memory . OffsetImm -> getValue ( ) ;


<s> if ( ! SchedModel . hasInstrSchedModel ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; unsigned BaseReg ; int64_t Offset ; if ( TII -> getMemOpBaseRegImmOfs ( MI , BaseReg , Offset , TRI ) ) { if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; SuppressSTP = true ; TII -> suppressLdStPair ( MI ) ; } PrevBaseReg = BaseReg ; } else PrevBaseReg = <NUM_LIT> ; } } return false ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ;

return ( <STR_LIT> ( Value ) != - <NUM_LIT> || <STR_LIT> ( - Value ) != - <NUM_LIT> ) ;


<s> df_analyze ( ) ; shorten_branches ( get_insns ( ) ) ; pru_reorg_loop ( insns ) ;


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; } if ( ! InConstantPool ) return ;


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: AllVRegsAllocated ) ;


<s> HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasMPX = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMWrite = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ;


<s> MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> void tilepro_emit_conditional_branch ( rtx operands [ ] , machine_mode cmp_mode ) { rtx cmp_rtx = tilepro_emit_cc_test ( GET_CODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , cmp_mode , false ) ;

rtx branch_rtx = gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) , pc_rtx ) ) ;


<s> MDNode * CU = Loc . getScope ( ) . getNode ( ) ; unsigned line = Loc . getLineNumber ( ) ;


<s> static SDValue LowerToTLSGeneralDynamicModel32 ( GlobalAddressSDNode * GA , SelectionDAG & DAG , const MVT PtrVT ) { SDValue InFlag ; DebugLoc dl = GA -> getDebugLoc ( ) ;

SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , DebugLoc :: getUnknownLoc ( ) , PtrVT ) , InFlag ) ;


<s> if ( auto * I = dyn_cast < Instruction > ( V ) ) { switch ( I -> getOpcode ( ) ) { case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: LShr : case Instruction :: Select : case Instruction :: ICmp : case Instruction :: PHI : return true ; } } return false ;


<s> for ( unsigned i = <NUM_LIT> , n = MI . getNumOperands ( ) ; i < n ; ++ i ) if ( & MI . getOperand ( i ) == & MO ) { OperandNumber = i ; break ; } assert ( ( OperandNumber != ~ <NUM_LIT> ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isNewValue ( MCII , MI ) && & MO == & <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , MI ) ) { unsigned SOffset = <NUM_LIT> ; unsigned VOffset = <NUM_LIT> ; unsigned UseReg = MO . getReg ( ) ; unsigned DefReg1 = <STR_LIT> ; unsigned DefReg2 = <STR_LIT> ; auto Instrs = <ISA_LIT>MCInstrInfo :: bundleInstructions ( * State . Bundle ) ; const MCOperand * I = Instrs . begin ( ) + State . Index - <NUM_LIT> ; for ( ; ; -- I ) { assert ( I != Instrs . begin ( ) - <NUM_LIT> && <STR_LIT> ) ; MCInst const & Inst = * I -> getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( Inst ) ) continue ; DefReg1 = <STR_LIT> ; DefReg2 = <STR_LIT> ; ++ SOffset ; if ( <ISA_LIT>MCInstrInfo :: isVector ( MCII , Inst ) ) { ++ VOffset ; } if ( <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , Inst ) ) DefReg1 = <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , Inst ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , Inst ) ) DefReg2 = <ISA_LIT>MCInstrInfo :: getNewValueOperand2 ( MCII , Inst ) . getReg ( ) ; if ( ! RegisterMatches ( UseReg , DefReg1 , DefReg2 ) ) { continue ; } if ( ! <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , Inst ) ) { break ; } assert ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MI ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , Inst ) == <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MI ) ) break ; } unsigned Offset = <ISA_LIT>MCInstrInfo :: isVector ( MCII , MI ) ? VOffset : SOffset ; Offset <<= <NUM_LIT> ; Offset |= <ISA_LIT>MCInstrInfo :: SubregisterBit ( UseReg , DefReg1 , DefReg2 ) ; return Offset ; } assert ( ! MO . isImm ( ) ) ; if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; switch ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MI ) . OpInfo [ OperandNumber ] . RegClass ) { case GeneralSubRegsRegClassID : case GeneralDoubleLow8RegsRegClassID : return <ISA_LIT>MCInstrInfo :: getDuplexRegisterNumbering ( Reg ) ; default : break ; }

return MCT . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> function_expander :: function_expander ( const function_instance & instance , tree fndecl , tree call_expr_in , rtx possible_target_in ) : function_call_info ( EXPR_LOCATION ( call_expr_in ) , instance , fndecl ) , call_expr ( call_expr_in ) , possible_target ( possible_target_in ) {


<s> switch ( BrOpc ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( ! MFI . hasVarSizedObjects ( ) && ! MFI . hasOpaqueSPAdjustment ( ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned BaseReg = TRI -> getBaseRegister ( ) ; for ( unsigned R : ClobberSet ) if ( BaseReg == R ) return true ; return false ;


<s> EmitLabel ( Start ) ; MCSymbol * Symbol = getContext ( ) . GetOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ; MCELF :: SetType ( SD , ELF :: STT_NOTYPE ) ; MCELF :: SetBinding ( SD , ELF :: STB_LOCAL ) ; SD . setExternal ( false ) ; AssignSection ( Symbol , getCurrentSection ( ) . first ) ; const MCExpr * Value = MCSymbolRefExpr :: Create ( Start , getContext ( ) ) ;


<s> <ISA_LIT>WinCOFFObjectWriter ( ) : MCWinCOFFObjectTargetWriter ( COFF :: IMAGE_FILE_MACHINE_ARM64 ) {


<s> else if ( <STR_LIT> ( Op . getNode ( ) ) || <STR_LIT> ( Op . getNode ( ) ) ) { if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue WrapperOp = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( WrapperOp ) ) if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ; } } else if ( Op -> getOpcode ( ) == <STR_LIT> && Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue BitcastOp = Op -> getOperand ( <NUM_LIT> ) ; if ( BitcastOp -> getOpcode ( ) == <STR_LIT> && isNullConstant ( BitcastOp -> getOperand ( <NUM_LIT> ) ) ) return true ; } return false ;


<s> bool generateAllocationMacros ( ) const { return true ;


<s> if ( cfun -> machine -> is_interrupt ) return <NUM_LIT> ;


<s> rtx src = op [ <NUM_LIT> ] ; rtx x = XEXP ( dest , <NUM_LIT> ) ; if ( CONSTANT_ADDRESS_P ( x ) ) { int n_words = AVR_TINY ? <NUM_LIT> : <NUM_LIT> ; return optimize > <NUM_LIT> && io_address_operand ( x , QImode ) ? avr_asm_len ( <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> , op , plen , - n_words ) ; } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) {

int disp = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ;


if ( strcmp ( <STR_LIT> , cris_cpu_str ) == <NUM_LIT> || strcmp ( <STR_LIT> , cris_cpu_str ) == <NUM_LIT> ) cris_cpu_version = <NUM_LIT> ;


<s> Value * MemIntrinsicsHandler :: CreateCompositeElemAccessGEP ( IRBuilder < > & IRB , Value * Mem , Type * CompType , Value * * Offset ) { SmallVector < Value * , <NUM_LIT> > Indices ; Indices . push_back ( ConstantInt :: get ( TargetIdxTy , <NUM_LIT> ) ) ;

GetIndicesForCompositeElemAccess ( IRB , Indices , CompType , Offset ) ;


<s> HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ;


<s> Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ;


<s> } else { MachineOperand & FlagOp = getFlagOp ( MI ) ; unsigned InstFlags = FlagOp . getImm ( ) ;

InstFlags &= ~ ( Flag << ( NUM_MO_FLAGS * Operand ) ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Src , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; } else if ( ValueType == <STR_LIT> ) { SDValue SrcLo , SrcHi ; GetExpandedParts ( Src , DAG , SrcLo , SrcHi ) ; SDValue ChainLo = Chain , ChainHi = Chain ; if ( Chain . getOpcode ( ) == <STR_LIT> ) { ChainLo = Chain . getOperand ( <NUM_LIT> ) ; ChainHi = Chain . getOperand ( <NUM_LIT> ) ; } SDValue Store1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ChainLo , SrcLo , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; SDValue Store2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ChainHi , SrcHi , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , getChain ( Store1 ) , getChain ( Store2 ) ) ; } else if ( ValueType == <STR_LIT> ) { SDValue SrcLo , SrcHi ; GetExpandedParts ( Src , DAG , SrcLo , SrcHi ) ; SDValue SrcLo1 , SrcLo2 , SrcHi1 , SrcHi2 ; GetExpandedParts ( SrcLo , DAG , SrcLo1 , SrcLo2 ) ; GetExpandedParts ( SrcHi , DAG , SrcHi1 , SrcHi2 ) ; SDValue ChainLo = Chain , ChainHi = Chain ; if ( Chain . getOpcode ( ) == <STR_LIT> ) { ChainLo = Chain . getOperand ( <NUM_LIT> ) ; ChainHi = Chain . getOperand ( <NUM_LIT> ) ; } SDValue ChainLo1 = ChainLo , ChainLo2 = ChainLo , ChainHi1 = ChainHi , ChainHi2 = ChainHi ; if ( ChainLo . getOpcode ( ) == <STR_LIT> ) {

ChainLo1 = ChainLo . getOperand ( <NUM_LIT> ) ;


<s> static bool riscv_valid_offset_p ( rtx x , machine_mode mode ) { if ( ! const_arith_operand ( x , Pmode ) ) return false ; if ( GET_MODE_SIZE ( mode ) . to_constant ( ) > UNITS_PER_WORD && ! SMALL_OPERAND ( INTVAL ( x ) + GET_MODE_SIZE ( mode ) . to_constant ( ) - UNITS_PER_WORD ) ) return false ; return true ;


<s> void addRegCRBITRCOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ;