<s> case CallingConv :: C : case CallingConv :: Fast : break ; default : report_fatal_error ( <STR_LIT> ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function & Func = MF . getFunction ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { if ( ! Func . arg_empty ( ) ) report_fatal_error ( <STR_LIT> ) ; StringRef Kind = MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; } return Chain ;


<s> if ( ! Res . getNode ( ) ) return ; if ( N -> getNumValues ( ) == <NUM_LIT> ) { Results . push_back ( Res ) ; return ; } assert ( ( N -> getNumValues ( ) == Res -> getNumValues ( ) ) && <STR_LIT> ) ;

for ( unsigned I = <NUM_LIT> , E = N -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ;


<s> bool <ISA_LIT>PostLegalizerLoweringInfo :: combine ( GISelChangeObserver & Observer , MachineInstr & MI , MachineIRBuilder & B ) const { CombinerHelper Helper ( Observer , B ) ;

<ISA_LIT>GenPostLegalizerLoweringHelper Generated ( GeneratedRuleCfg ) ;


<s> if ( SOp . getOpcode ( ) == <STR_LIT> && SOp . getNode ( ) -> hasOneUse ( ) ) { SDValue SC = SOp . getOperand ( <NUM_LIT> ) ; SDValue SX = SOp . getOperand ( <NUM_LIT> ) ; SDValue SY = SOp . getOperand ( <NUM_LIT> ) ; SDLoc DLS = SOp ; if ( IsZero ( SY ) ) { SDValue NewOr = DAG . getNode ( <STR_LIT> , DLS , VT , SX , VOp ) ; SDValue NewSel = DAG . getNode ( <STR_LIT> , DLS , VT , SC , NewOr , VOp ) ; DAG . ReplaceAllUsesWith ( I , NewSel . getNode ( ) ) ; } else if ( IsZero ( SX ) ) { SDValue NewOr = DAG . getNode ( <STR_LIT> , DLS , VT , SY , VOp ) ; SDValue NewSel = DAG . getNode ( <STR_LIT> , DLS , VT , SC , VOp , NewOr ) ; DAG . ReplaceAllUsesWith ( I , NewSel . getNode ( ) ) ; } }


<s> int Val = StringSwitch < int > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: Create ( Val , getContext ( ) ) , S , Tok . getEndLoc ( ) ) ) ; return MatchOperand_Success ;


<s> unsigned ShAmt = <NUM_LIT> ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } }

Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , ShAmt , ShOpcVal ) , <STR_LIT> ) ;


<s> unsigned __int128 __res = ( unsigned __int128 ) __X * __Y ; * __P = ( unsigned long long ) ( __res >> <NUM_LIT> ) ;


<s> const char * mc = FLOAT_MODE_P ( mode ) ? <STR_LIT> : <STR_LIT> ; if ( TARGET_GENERAL_REGS_ONLY ) error ( <STR_LIT> , <STR_LIT> , mc , msg ) ; else error ( <STR_LIT> , <STR_LIT> , mc , msg ) ;


<s> void onNot ( ) { IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_OR : case IES_XOR : case IES_AND : case IES_LSHIFT : case IES_RSHIFT : case IES_PLUS : case IES_MINUS : case IES_NOT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_LBRAC : State = IES_NOT ;


<s> unsigned <ISA_LIT>FunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; if ( <ISA_LIT>FixGlobalBaseReg ) return GlobalBaseReg = <STR_LIT> ; const TargetRegisterClass * RC ;

RC = ( const TargetRegisterClass * ) & <STR_LIT> ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_prefetch_i64scatter_ps ( void * addr , __m512i index , int scale , int hint ) {

__builtin_ia32_scatterpfqps ( ( __mmask8 ) <NUM_LIT> , ( __v8di ) index , ( int const * ) addr , scale , hint ) ;


<s> unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue ZeroBits = DAG . getConstant ( <NUM_LIT> , dl , MaskVT ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ;

return DAG . getSetCC ( dl , <STR_LIT> , Mask , ZeroBits , <STR_LIT> ) ;


<s> unsigned BestGrowth = ~ <NUM_LIT> ; for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << WaterBB -> getNumber ( ) << <STR_LIT> << Growth << '\n' ) ;

if ( BestGrowth == <NUM_LIT> ) return true ;


<s> void emitImportName ( const MCSymbolWasm * , StringRef ) override {


<s> for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( MemOpndSlot + i ) , LabelOffset ) ; else MIB . add ( MI . getOperand ( MemOpndSlot + i ) ) ; } if ( ! UseImmLabel ) MIB . addReg ( LabelReg ) ; else MIB . addMBB ( restoreMBB ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( restoreMBB ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; MIB . addRegMask ( RegInfo -> getNoPreservedMask ( ) ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( restoreMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , mainDstReg ) ; mainMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( mainDstReg ) . addMBB ( mainMBB ) . addReg ( restoreDstReg ) . addMBB ( restoreMBB ) ; if ( RegInfo -> hasBasePointer ( * MF ) ) { const bool Uses64BitFramePtr = Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FI -> setRestoreBasePointer ( MF ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( * MF ) ; unsigned BasePtr = RegInfo -> getBaseRegister ( ) ; unsigned Opm = Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( restoreMBB , DL , TII -> get ( Opm ) , BasePtr ) , FramePtr , true , <ISA_LIT>FI -> getRestoreBasePointerOffset ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } BuildMI ( restoreMBB , DL , TII -> get ( <STR_LIT> ) , restoreDstReg ) . addImm ( <NUM_LIT> ) ;

BuildMI ( restoreMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ;


<s> else if ( ( REG_P ( rs1 ) || GET_CODE ( rs1 ) == SUBREG ) && ( REG_P ( rs2 ) || GET_CODE ( rs2 ) == SUBREG ) ) { if ( mode == TFmode && ! ( TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD ) ) return <NUM_LIT> ; if ( TARGET_ARCH32 && ! optimize && ( mode == DFmode || mode == DImode ) ) return <NUM_LIT> ; } else if ( USE_AS_OFFSETABLE_LO10 && GET_CODE ( rs1 ) == LO_SUM && TARGET_ARCH64 && ! TARGET_CM_MEDMID && RTX_OK_FOR_OLO10_P ( rs2 ) ) { rs2 = NULL ; imm1 = XEXP ( rs1 , <NUM_LIT> ) ; rs1 = XEXP ( rs1 , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || SPARC_SYMBOL_REF_TLS_P ( rs1 ) ) return <NUM_LIT> ; } } else if ( GET_CODE ( addr ) == LO_SUM ) { rs1 = XEXP ( addr , <NUM_LIT> ) ; imm1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || SPARC_SYMBOL_REF_TLS_P ( rs1 ) ) return <NUM_LIT> ; if ( mode == TFmode && TARGET_ARCH32 ) return <NUM_LIT> ; } else if ( GET_CODE ( addr ) == CONST_INT && SMALL_INT ( addr ) ) return <NUM_LIT> ;


<s> const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * SuperRC = RI . getLargestLegalSuperClass ( RC , * MF ) ; if ( ! SuperRC ) return false ;

DRC = RI . getMatchingSuperRegClass ( SuperRC , DRC , MO . getSubReg ( ) ) ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseInterpAttr ( OperandVector & Operands ) { if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Str = Parser . getTok ( ) . getString ( ) ; if ( ! Str . startswith ( <STR_LIT> ) ) return MatchOperand_NoMatch ; StringRef Chan = Str . take_back ( <NUM_LIT> ) ; int AttrChan = StringSwitch < int > ( Chan ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; if ( AttrChan == - <NUM_LIT> ) return MatchOperand_ParseFail ; Str = Str . drop_back ( <NUM_LIT> ) . drop_front ( <NUM_LIT> ) ; uint8_t Attr ; if ( Str . getAsInteger ( <NUM_LIT> , Attr ) ) return MatchOperand_ParseFail ;

SMLoc S = Parser . getTok ( ) . getLoc ( ) ;


<s> return constrainSelectedInstRegOperands ( * AddP , TII , TRI , RBI ) ; } unsigned Opc = <NUM_LIT> ; if ( VecTy == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( VecTy == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( VecTy == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) Opc = <STR_LIT> ; else if ( VecTy == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) Opc = <STR_LIT> ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } I . setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } if ( I . getOpcode ( ) == TargetOpcode :: G_VECREDUCE_FADD ) { unsigned Opc = <NUM_LIT> ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> return ; } assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; * ( uint16_t * ) & Data [ Fixup . getOffset ( ) + <NUM_LIT> ] = ( uint16_t ) ( ( Value - <NUM_LIT> ) / <NUM_LIT> ) ;


<s> if ( ! G ) return false ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> isDeclaration ( ) ) return false ; switch ( GV -> getLinkage ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: AvailableExternallyLinkage : case GlobalValue :: ExternalWeakLinkage : return false ;

case GlobalValue :: LinkOnceAnyLinkage :


<s> MVT VT ; if ( ! Alignment || Alignment >= <NUM_LIT> ) { if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else { VT = <STR_LIT> ; } } else { if ( Len >= <NUM_LIT> && Alignment == <NUM_LIT> ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> && Alignment == <NUM_LIT> ) VT = <STR_LIT> ; else { VT = <STR_LIT> ; } }


<s> gcc_assert ( tmp_arch ) ; selected_arch = tmp_arch ; explicit_arch = selected_arch -> arch ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , pragma_or_attr ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str , pragma_or_attr ) ; aarch64_print_hint_for_arch ( str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> , str , pragma_or_attr ) ; break ;


<s> assert ( Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX ) ; return MCOperand :: createImm ( ( Imm <= INLINE_INTEGER_C_PO<ISA_LIT>TIVE_MAX ) ? ( static_cast < int64_t > ( Imm ) - INLINE_INTEGER_C_MIN ) : ( INLINE_INTEGER_C_PO<ISA_LIT>TIVE_MAX - static_cast < int64_t > ( Imm ) ) ) ;


<s> poly_uint64 nunits = GET_MODE_NUNITS ( fi . vector_mode ( <NUM_LIT> ) ) ;

return aarch64_sve_data_mode ( m_to_mode , nunits ) . require ( ) ;


<s> assert ( isToken ( ) && <STR_LIT> ) ; return StringRef ( Tok . Data , Tok . Length ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , DL ( computeDataLayout ( * this ) ) , TSInfo ( DL ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - <NUM_LIT> : - <NUM_LIT> ) , JITInfo ( hasSSE1 ( ) ) {


<s> static inline __ev64_opaque__ __internal_ev_mwhgsmfaa ( __ev64_opaque__ a , __ev64_opaque__ b ) {


<s> const char * output_387_reg_move ( rtx insn , rtx * operands ) {

if ( REG_P ( operands [ <NUM_LIT> ] ) && find_regno_note ( insn , REG_DEAD , REGNO ( operands [ <NUM_LIT> ] ) ) ) {


<s> return new <ISA_LIT>DAGToDAGISel ( TM ) ;


<s> ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2 ; } SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , TargetConst0 , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_3 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ;


<s> RRC = & <STR_LIT> ; if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ;


<s> assert ( regions . count ( region ) == <NUM_LIT> && <STR_LIT> ) ; regions . erase ( region ) ; assert ( region -> MBB ) ; makeReady ( ready , region ) ; unsigned region_size = <NUM_LIT> ; num_regions ++ ; DEBUG ( dbgs ( ) << <STR_LIT> << num_regions << <STR_LIT> << region -> getName ( ) << <STR_LIT> ) ; while ( ! ready . empty ( ) ) { ready_set :: iterator it = selectBlock ( region , ready , order . empty ( ) ? NULL : order . back ( ) ) ; const ready_block next = * it ; ready . erase ( it ) ; visitBlock ( region , region_size , next . block , ready , regions , order ) ; } DEBUG ( dbgs ( ) << <STR_LIT> << region -> getName ( ) << <STR_LIT> << region_size << <STR_LIT> ) ; } int UnassignedBlocks = <NUM_LIT> ; for ( ablocks :: iterator i ( Blocks . begin ( ) ) , ie ( Blocks . end ( ) ) ; i != ie ; i ++ ) { if ( ( * i ) -> Region == NULL && ( * i ) -> MBB ) {

errs ( ) << <STR_LIT> + ( * i ) -> getName ( ) << <STR_LIT> << ( * i ) -> SCCSize << <STR_LIT> ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; }

AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> emit_insn ( GEN_FCN ( CODE_FOR_tcommit ) ( ) ) ; break ; case AARCH64_TME_BUILTIN_TCANCEL : { tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; if ( CONST_INT_P ( op0 ) && UINTVAL ( op0 ) <= <NUM_LIT> ) emit_insn ( GEN_FCN ( CODE_FOR_tcancel ) ( op0 ) ) ; else { error_at ( EXPR_LOCATION ( exp ) , <STR_LIT> ) ; return const0_rtx ; } } break ; default :


<s> StringRef getPassName ( ) const override {


<s> if ( TuneCPU . empty ( ) ) TuneCPU = <STR_LIT> ; std :: string FullFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple ) ; assert ( ! FullFS . empty ( ) && <STR_LIT> ) ; if ( ! FS . empty ( ) ) FullFS = ( Twine ( FullFS ) + <STR_LIT> + FS ) . str ( ) ; ParseSubtargetFeatures ( CPU , TuneCPU , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetKFreeBSD ( ) || isTargetNaCl ( ) || In64BitMode ) stackAlignment = Align ( <NUM_LIT> ) ; if ( PreferVectorWidthOverride ) PreferVectorWidth = PreferVectorWidthOverride ;

else if ( Prefer128Bit ) PreferVectorWidth = <NUM_LIT> ;


<s> if ( ! isSysReg ( ) ) return false ;


<s> if ( MO . isReg ( ) ) { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO ) ) REX |= <NUM_LIT> << Bit ; Bit ++ ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned e = ( isTwoAddr ? <STR_LIT> + <NUM_LIT> : <STR_LIT> ) ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; if ( NumOps > e && <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( e ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; unsigned Bit = <NUM_LIT> ; for ( ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO ) ) REX |= <NUM_LIT> << Bit ; Bit ++ ; } } break ; } default : { if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MI . getOperand ( <NUM_LIT> ) ) ) REX |= <NUM_LIT> << <NUM_LIT> ; i = isTwoAddr ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned e = NumOps ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( <ISA_LIT>InstrInfo :: is<ISA_LIT>_64ExtendedReg ( MO ) ) REX |= <NUM_LIT> << <NUM_LIT> ;


<s> explicit <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; if ( VT == <STR_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) { ConstantSDNode * MaskN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( MaskN -> getZExtValue ( ) != RISBG . Mask ) { SDValue NewMask = CurDAG -> getConstant ( RISBG . Mask , VT ) ; N = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , NewMask ) ; return SelectCode ( N ) ; } return <NUM_LIT> ; }


<s> static inline vec_int4 vec_rl ( vec_int4 a , vec_uint4 b ) { return ( spu_rl ( a , ( vec_int4 ) ( b ) ) ) ;


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return Opc ; } else switch ( MemSizeInBytes ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return Opc == TargetOpcode :: G_SEXTLOAD ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Opc == TargetOpcode :: G_SEXTLOAD ? <STR_LIT> : <STR_LIT> ; default : return Opc ; } } if ( RegBank == <STR_LIT> ) { switch ( MemSizeInBytes ) { case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( isFP64 ) return isStore ? <STR_LIT> : <STR_LIT> ;

else return isStore ? <STR_LIT> : <STR_LIT> ;


<s> if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CallingConv :: ID CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = <NUM_LIT> ; i != Ins . size ( ) ; i ++ ) { <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) return false ; } if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } return false ;


<s> return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ;


<s> static unsigned getSubOpcode ( bool Is64Bit , int64_t Amount ) {

if ( Is64Bit ) return isInt < <NUM_LIT> > ( Amount ) ? <STR_LIT> : <STR_LIT> ;


<s> MachineBasicBlock * DestBB = nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( MI -> getOperand ( i ) . isMBB ( ) ) { DestBB = MI -> getOperand ( i ) . getMBB ( ) ; break ; } } assert ( DestBB && <STR_LIT> ) ;

if ( isBBInRange ( MI , DestBB , Br . OffsetBits ) ) return false ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {


<s> for ( MachineOperand & Use : MI . implicit_operands ( ) ) {

if ( Use . isUse ( ) && ( Use . getReg ( ) == <STR_LIT> || Use . getReg ( ) == <STR_LIT> ) ) {


<s> const MCOperand & MO = MI . getOperand ( Op ) ;

if ( MO . getReg ( ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> if ( Constraint . length ( ) > <NUM_LIT> ) return ; char ConstraintLetter = Constraint [ <NUM_LIT> ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == <NUM_LIT> ) { Result = DAG . getTargetConstant ( <NUM_LIT> , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - <NUM_LIT> ) && ( Val <= <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , Op . getValueType ( ) ) ; break ; }


<s> unsigned imm = <NUM_LIT> ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> static bool canUseSiblingCall ( CCState ArgCCInfo , SmallVectorImpl < CCValAssign > & ArgLocs ) { for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ;

if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ;


<s> UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) continue ; const UUPair & Pr = F -> second ; Register NewDR = MRI -> createVirtualRegister ( DoubleRC ) ; BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , NewDR ) . addReg ( Pr . first ) . addImm ( <STR_LIT> ) . addReg ( Pr . second ) . addImm ( <STR_LIT> ) ;


<s> unsigned int alignment = <NUM_LIT> ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) alignment = std :: max ( alignment , DECL_ALIGN ( field ) ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( * this ) {


<s> SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } else { MVT TruncVT = <STR_LIT> ( MaskVT . getSizeInBits ( ) ) ; return DAG . getBitcast ( MaskVT , DAG . getNode ( <STR_LIT> , dl , TruncVT , Mask ) ) ; } } else {

MVT BitcastVT = <STR_LIT> ( <STR_LIT> , Mask . getSimpleValueType ( ) . getSizeInBits ( ) ) ;


<s> return buildRSRC ( DAG , DL , Ptr , <NUM_LIT> , TII -> getScratchRsrcWords23 ( ) ) ;


<s> static std :: vector < CalleeSavedInfo > :: iterator getSavedReg ( std :: vector < CalleeSavedInfo > & V , unsigned reg ) {

for ( auto I = V . begin ( ) , E = V . end ( ) ; I != E ; ++ I ) {


<s> <ISA_LIT>Operand :: Ptr <ISA_LIT>AsmParser :: defaultSDWASrc1Sel ( ) const {

return defaultSDWASel ( <ISA_LIT>Operand :: ImmTySdwaSrc1Sel ) ;


<s> for ( SUnit :: const_pred_iterator I = SU -> Preds . begin ( ) , E = SU -> Preds . end ( ) ; I != E ; ++ I ) { SUnit & Pred = * I -> getSUnit ( ) ; if ( ! Pred . isScheduled ) { if ( OnlyAvailablePred && OnlyAvailablePred != & Pred ) return <NUM_LIT> ; OnlyAvailablePred = & Pred ; } } return OnlyAvailablePred ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>TargetMachine & tm ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) , TM ( tm ) {


<s> if ( VT == <STR_LIT> ) return LowerFDIV32 ( Op , DAG ) ; if ( VT == <STR_LIT> ) return LowerFDIV64 ( Op , DAG ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> BitsPerBool = <NUM_LIT> ; BoolMask = <NUM_LIT> ; } else if ( NumElts == <NUM_LIT> ) { BitsPerBool = <NUM_LIT> ; BoolMask = <NUM_LIT> ; } else if ( NumElts == <NUM_LIT> ) { BitsPerBool = <NUM_LIT> ; BoolMask = <NUM_LIT> ; } else return SDValue ( ) ; SDValue FirstOp = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( FirstOp ) && std :: all_of ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) , [ & FirstOp ] ( SDUse & U ) { return U . get ( ) . isUndef ( ) || U . get ( ) == FirstOp ; } ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FirstOp , DAG . getValueType ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Ext ) ; } unsigned Bits32 = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( ! isa < ConstantSDNode > ( V ) && ! V . isUndef ( ) ) continue ; bool BitSet = V . isUndef ( ) ? false : cast < ConstantSDNode > ( V ) -> getZExtValue ( ) ; if ( BitSet ) Bits32 |= BoolMask << ( i * BitsPerBool ) ; } SDValue Base = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( Bits32 , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( isa < ConstantSDNode > ( V ) || V . isUndef ( ) ) continue ; Base = DAG . getNode ( <STR_LIT> , dl , VT , Base , V , DAG . getConstant ( i , dl , <STR_LIT> ) ) ; }


<s> static int tilegx_mode_rep_extended ( scalar_int_mode mode , scalar_int_mode mode_rep ) {

if ( mode == SImode && mode_rep == DImode ) return SIGN_EXTEND ;


<s> HasAltivec = false ; HasSPE = false ; HasQPX = false ; HasVSX = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false ; HasHTM = false ; HasFusion = false ; HasFloat128 = false ; IsISA3_0 = false ; UseLongCalls = false ; HasPOPCNTD = POPCNTD_Unavailable ;


<s> case TargetOpcode :: DBG_VALUE : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OutStreamer . emitRawComment ( <STR_LIT> ) ; return ; case <STR_LIT> : case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OutStreamer . AddComment ( StringRef ( <STR_LIT> ) + <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OutStreamer . AddComment ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerTlsAddr ( OutStreamer , MCInstLowering , * MI , getSubtargetInfo ( ) ) ; case <STR_LIT> : { MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitLabel ( PICBase ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; return ; } case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ;

MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( <NUM_LIT> ) ) ;


reg = SET_DEST ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ;


<s> if ( IsPCRel && RelocType == MachO :: <ISA_LIT>_RELOC_VANILLA ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && A && ! Writer -> doesSymbolRequireExternRelocation ( * A ) ) return Record<ISA_LIT>ScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , RelocType , Log2Size , FixedValue ) ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; const MCSymbol * RelSymbol = nullptr ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( A -> isVariable ( ) ) { int64_t Res ; if ( A -> getVariableValue ( ) -> evaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( requiresExternRelocation ( Writer , Asm , * Fragment , RelocType , * A , FixedValue ) ) { RelSymbol = A ; if ( ! A -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( * A ) ; } else { const MCSection & Sec = A -> getSection ( ) ; Index = Sec . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & Sec ) ; } if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ; Type = RelocType ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ; if ( Type == MachO :: <ISA_LIT>_RELOC_HALF ) { uint32_t Value = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : Value = ( FixedValue >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Value = FixedValue & <NUM_LIT> ; break ; } MachO :: any_relocation_info MREPair ; MREPair . r_word0 = Value ; MREPair . r_word1 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) ) ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MREPair ) ; }

Writer -> addRelocation ( RelSymbol , Fragment -> getParent ( ) , MRE ) ;


<s> bool local_alias_traits :: equal_keys ( rtx func1 , rtx func2 ) { return rtx_equal_p ( func1 , func2 ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { const DataLayout * DL = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; const MachineOperand & MO = MI -> getOperand ( opNum ) ; bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) {


<s> } } } else if ( SwapVector [ EntryIdx ] . IsStore && SwapVector [ EntryIdx ] . IsSwap ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned UseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( UseReg ) ; unsigned DefReg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int DefIdx = SwapMap [ DefMI ] ; if ( ! SwapVector [ DefIdx ] . IsSwap || SwapVector [ DefIdx ] . IsLoad || SwapVector [ DefIdx ] . IsStore ) { SwapVector [ Repr ] . WebRejected = <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , Repr ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DefIdx << <STR_LIT> ) ; DEBUG ( DefMI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EntryIdx << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } for ( MachineInstr & UseMI : MRI -> use_nodbg_instructions ( DefReg ) ) { int UseIdx = SwapMap [ & UseMI ] ; if ( SwapVector [ UseIdx ] . VSEMI -> getOpcode ( ) != MI -> getOpcode ( ) ) { SwapVector [ Repr ] . WebRejected = <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , Repr ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; DEBUG ( DefMI -> dump ( ) ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << UseIdx << <STR_LIT> ) ;


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else { const MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) . add ( Cond [ <NUM_LIT> ] ) ; if ( Cond . size ( ) > <NUM_LIT> ) MIB . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>Target32 ( ) , & getThe<ISA_LIT>Target64 ( ) } ) { RegisterMCAsmInfoFn X ( * T , createMCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , createMCInstrInfo ) ; TargetRegistry :: registerMCAdjustCodeGenOpts ( * T , adjustCodeGenOpts ) ; TargetRegistry :: RegisterMCRegInfo ( * T , createMCRegisterInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , createMCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , createCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , createAsmBackend ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , createMCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createAsmTargetStreamer ) ;


<s> return runNVVMIntrRange ( F , SmVersion ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ;


<s> } } else { latency = <STR_LIT> [ src ] . first - <STR_LIT> + <NUM_LIT> ; } assert ( latency > <NUM_LIT> && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << src . str ( ) << <STR_LIT> ) ; if ( DestPresent ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << dest . str ( ) << <STR_LIT> ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << latency << <STR_LIT> ) ; } else {


<s> SDValue CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const {

return CreateLiveInRegister ( DAG , RC , Reg , VT , SDLoc ( DAG . getEntryNode ( ) ) ) ;


<s> <ISA_LIT>ScheduleBlockScheduler Scheduler ( DAG , ScheduleVariant , Blocks ) ; std :: vector < <ISA_LIT>ScheduleBlock * > ScheduledBlocks ; struct <ISA_LIT>ScheduleBlockResult Res ; ScheduledBlocks = Scheduler . getBlocks ( ) ;

for ( unsigned b = <NUM_LIT> ; b < ScheduledBlocks . size ( ) ; ++ b ) {


<s> if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; }


<s> MachineBasicBlock * BB = I . getParent ( ) ; MachineFunction * MF = BB -> getParent ( ) ; const GCNSubtarget & Subtarget = MF -> getSubtarget < GCNSubtarget > ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; unsigned Opcode ; unsigned LoadSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; if ( ! AddrInfo . empty ( ) && AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) == <NUM_LIT> ) { const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; int64_t EncodedImm = <STR_LIT> ( Subtarget , GEPInfo . Imm ) ; if ( <STR_LIT> ( Subtarget , GEPInfo . Imm ) ) { Opcode = getSmrdOpcode ( <STR_LIT> , LoadSize ) ; MachineInstr * SMRD = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addReg ( PtrReg ) . addImm ( EncodedImm ) . addImm ( <NUM_LIT> ) ; return constrainSelectedInstRegOperands ( * SMRD , TII , TRI , RBI ) ; }

if ( Subtarget . getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedImm ) ) {


<s> const LoadSDNode * LD = cast < LoadSDNode > ( Node ) ; uint64_t size = LD -> getMemOperand ( ) -> getSize ( ) ; if ( ! size || size > <NUM_LIT> || ( size & ( size - <NUM_LIT> ) ) ) continue ; SDNode * LDAddrNode = LD -> getOperand ( <NUM_LIT> ) . getNode ( ) ; unsigned opcode = LDAddrNode -> getOpcode ( ) ; if ( opcode == <STR_LIT> ) { SDValue OP1 = LDAddrNode -> getOperand ( <NUM_LIT> ) ; SDValue OP2 = LDAddrNode -> getOperand ( <NUM_LIT> ) ; SDNode * OP1N = OP1 . getNode ( ) ; if ( OP1N -> getOpcode ( ) <= <STR_LIT> || OP1N -> getNumOperands ( ) == <NUM_LIT> ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ; LD -> dump ( ) ; dbgs ( ) << '\n' ) ; const GlobalAddressSDNode * GADN = dyn_cast < GlobalAddressSDNode > ( OP1N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ;

const ConstantSDNode * CDN = dyn_cast < ConstantSDNode > ( OP2 . getNode ( ) ) ;


<s> return new ELF<ISA_LIT>AsmBackend ( T , TT , TheTriple . getOS ( ) , false ) ;


<s> uint32_t Encoding = BTy -> getEncoding ( ) ; return ( Encoding == dwarf :: DW_ATE_signed || Encoding == dwarf :: DW_ATE_signed_char ) ; } if ( InfoKind == <STR_LIT> ) { const Triple & Triple = TM -> getTargetTriple ( ) ; DIDerivedType * MemberTy = nullptr ; bool IsBitField = false ; uint32_t SizeInBits ; if ( Tag == dwarf :: DW_TAG_array_type ) { auto * EltTy = stripQualifiers ( CTy -> getBaseType ( ) ) ; SizeInBits = calcArraySize ( CTy , <NUM_LIT> ) * EltTy -> getSizeInBits ( ) ; } else { MemberTy = cast < DIDerivedType > ( CTy -> getElements ( ) [ AccessIndex ] ) ; SizeInBits = MemberTy -> getSizeInBits ( ) ; IsBitField = MemberTy -> isBitField ( ) ; } if ( ! IsBitField ) { if ( SizeInBits > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return <NUM_LIT> - SizeInBits ; } unsigned SBitOffset , NextSBitOffset ; GetStorageBitRange ( MemberTy , RecordAlignment , SBitOffset , NextSBitOffset ) ; if ( NextSBitOffset - SBitOffset > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; unsigned OffsetInBits = MemberTy -> getOffsetInBits ( ) ; if ( Triple . getArch ( ) == Triple :: bpfel ) return SBitOffset + <NUM_LIT> - OffsetInBits - SizeInBits ; else return OffsetInBits + <NUM_LIT> - NextSBitOffset ; } if ( InfoKind == <STR_LIT> ) { DIDerivedType * MemberTy = nullptr ; bool IsBitField = false ; uint32_t SizeInBits ; if ( Tag == dwarf :: DW_TAG_array_type ) { auto * EltTy = stripQualifiers ( CTy -> getBaseType ( ) ) ; SizeInBits = calcArraySize ( CTy , <NUM_LIT> ) * EltTy -> getSizeInBits ( ) ; } else { MemberTy = cast < DIDerivedType > ( CTy -> getElements ( ) [ AccessIndex ] ) ; SizeInBits = MemberTy -> getSizeInBits ( ) ; IsBitField = MemberTy -> isBitField ( ) ; } if ( ! IsBitField ) { if ( SizeInBits > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return <NUM_LIT> - SizeInBits ; } unsigned SBitOffset , NextSBitOffset ; GetStorageBitRange ( MemberTy , RecordAlignment , SBitOffset , NextSBitOffset ) ; if ( NextSBitOffset - SBitOffset > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return <NUM_LIT> - SizeInBits ;


<s> unsigned getMaxNumSGPRs ( unsigned WavesPerEU , bool Addressable ) const {

return <STR_LIT> :: getMaxNumSGPRs ( this , WavesPerEU , Addressable ) ;


<s> bool AMDGPUAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { setForcedEncodingSize ( <NUM_LIT> ) ; if ( Name . endswith ( <STR_LIT> ) ) setForcedEncodingSize ( <NUM_LIT> ) ; else if ( Name . endswith ( <STR_LIT> ) ) setForcedEncodingSize ( <NUM_LIT> ) ; Operands . push_back ( AMDGPUOperand :: CreateToken ( Name , NameLoc ) ) ; while ( ! getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { AMDGPUAsmParser :: OperandMatchResultTy Res = parseOperand ( Operands , Name ) ; if ( getLexer ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ;


<s> EVT ValVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return LowerSTOREi1 ( Op , DAG ) ; default :

if ( ValVT . isVector ( ) ) return LowerSTOREVector ( Op , DAG ) ;


<s> void aarch64_init_simd_builtins ( void ) { if ( aarch64_simd_builtins_initialized_p ) return ; aarch64_simd_builtins_initialized_p = true ; aarch64_init_simd_builtin_types ( ) ;

aarch64_init_simd_builtin_scalar_types ( ) ;


<s> case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( ABI . IsCheriPureCap ( ) ) { unsigned Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( CapType ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SV = SV -> stripPointerCasts ( ) ; assert ( isCheriPointer ( SV -> getType ( ) , & DAG . getDataLayout ( ) ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ;

SDValue CapAddr = Op . getOperand ( <NUM_LIT> ) ;


<s> if ( m32c_compare_redundant ( insn , operands ) ) { fprintf ( stderr , <STR_LIT> ) ; return templ ; }

fprintf ( stderr , <STR_LIT> , templ + <NUM_LIT> ) ;


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) , IsThumb ) ; S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ;

if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ;


<s> return __builtin_ia32_vcvtpd2ph128_mask ( ( __v2df ) __A , _mm_setzero_ph ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> emit_note ( NOTE_INSN_PROLOGUE_END ) ; fnaddr = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; use_sibcall_p = ( mips_function_ok_for_sibcall ( function , NULL ) && const_call_insn_operand ( fnaddr , Pmode ) ) ; if ( ! use_sibcall_p && ( mips_got_symbol_type_p ( mips_classify_symbol ( fnaddr , SYMBOL_CONTEXT_LEA ) ) ) ) { cfun -> machine -> global_pointer = TARGET_CALL_SAVED_GP ? <NUM_LIT> : GLOBAL_POINTER_REGNUM ; cfun -> machine -> must_initialize_gp_p = true ; SET_REGNO ( pic_offset_table_rtx , cfun -> machine -> global_pointer ) ; mips_emit_loadgp ( ) ; } temp1 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; temp2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( delta != <NUM_LIT> ) { rtx offset = GEN_INT ( delta ) ; if ( ! SMALL_OPERAND ( delta ) ) { mips_emit_move ( temp1 , offset ) ; offset = temp1 ; } emit_insn ( gen_add3_insn ( this_rtx , this_rtx , offset ) ) ; } if ( vcall_offset != <NUM_LIT> ) { rtx addr ; mips_emit_move ( temp1 , gen_rtx_MEM ( Pmode , this_rtx ) ) ; addr = mips_add_offset ( temp2 , temp1 , vcall_offset ) ; mips_emit_move ( temp1 , gen_rtx_MEM ( Pmode , addr ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp1 ) ) ; } if ( use_sibcall_p ) { insn = emit_call_insn ( gen_sibcall_internal ( fnaddr , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; } else { if ( TARGET_USE_PIC_FN_ADDR_REG && ! TARGET_MIPS16 && ! mips_dangerous_for_la25_p ( fnaddr ) ) temp1 = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; mips_load_call_address ( MIPS_CALL_SIBCALL , temp1 , fnaddr ) ; if ( TARGET_USE_PIC_FN_ADDR_REG && REGNO ( temp1 ) != PIC_FUNCTION_ADDR_REGNUM ) mips_emit_move ( gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) , temp1 ) ; emit_jump_insn ( gen_indirect_jump ( temp1 ) ) ; } insn = get_insns ( ) ; split_all_insns_noflow ( ) ; mips16_lay_out_constants ( true ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ;


<s> SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT , Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ;


<s> void <ISA_LIT>_64GNULDBackend :: setRelDynSize ( ) { ELFFileFormat * file_format = getOutputFormat ( ) ;

file_format -> getRelaDyn ( ) . setSize ( m_pRelDyn -> numOfRelocs ( ) * getRelaEntrySize ( ) ) ;


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , NULL , <NUM_LIT> , NULL , <NUM_LIT> ) ;


<s> moveSMRDToVALU ( Inst , MRI , Worklist ) ; continue ; } break ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBinaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitUnaryOp ( Worklist , Inst , <STR_LIT> ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : splitScalar64BitBCNT ( Worklist , Inst ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : { splitScalar64BitBFE ( Worklist , Inst ) ; Inst -> eraseFromParent ( ) ; continue ; } case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { NewOpcode = <STR_LIT> ; swapOperands ( Inst ) ; } break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpcode == <STR_LIT> ) { legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) Inst -> RemoveOperand ( i ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; }

Inst -> addImplicitDefUseOperands ( * Inst -> getParent ( ) -> getParent ( ) ) ;


<s> int n_regs ; if ( h8300_os_task_function_p ( current_function_decl ) ) return ; if ( h8300_monitor_function_p ( current_function_decl ) ) emit_insn ( gen_monitor_prologue ( ) ) ; if ( frame_pointer_needed ) { push ( HARD_FRAME_POINTER_REGNUM ) ; emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; } saved_regs = compute_saved_regs ( ) ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno += n_regs ) { n_regs = <NUM_LIT> ; if ( saved_regs & ( <NUM_LIT> << regno ) ) { if ( TARGET_H8300S ) { if ( ( ! TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) n_regs = <NUM_LIT> ; else if ( ( ! TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) n_regs = <NUM_LIT> ; else if ( ( ! TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) n_regs = <NUM_LIT> ; } h8300_push_pop ( regno , n_regs , <NUM_LIT> , <NUM_LIT> ) ; } }

h8300_emit_stack_adjustment ( - <NUM_LIT> , round_frame_size ( get_frame_size ( ) ) ) ;


<s> if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef IFlagsStr = Tok . getString ( ) ; unsigned IFlags = <NUM_LIT> ; if ( IFlagsStr != <STR_LIT> ) { for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) {

unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ;


<s> Vec = concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } else { Vec = DAG . getConstant ( Ones , dl , <STR_LIT> ( <STR_LIT> , NumElts ) ) ; }


<s> explicit <ISA_LIT>ReFunc ( ) : ModulePass ( ID ) {


<s> for ( unsigned i = l * NumLaneElts , j = l * NumLaneElts ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) ) return false ; if ( V2IsSplat ) { if ( ! isUndefOrEqual ( BitI1 , NumElts ) ) return false ; } else { if ( ! isUndefOrEqual ( BitI1 , j + NumElts ) ) return false ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) != CodeModel :: Kernel ) return NULL ; unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; const Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; const Constant * C = LoadMI -> getOpcode ( ) == <STR_LIT> ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; }


<s> MVT SrcVT = Src . getSimpleValueType ( ) ; MVT DstVT = Op . getSimpleValueType ( ) ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && DstVT . isScalarInteger ( ) ) { assert ( ! Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; MVT SExtVT = SrcVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( Op ) ; SDValue V = DAG . getSExtOrTrunc ( Src , DL , SExtVT ) ; V = getPMOVMSKB ( DL , V , DAG , Subtarget ) ; return DAG . getZExtOrTrunc ( V , DL , DstVT ) ; } assert ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; if ( ! ( DstVT == <STR_LIT> && SrcVT == <STR_LIT> ) && ! ( DstVT == <STR_LIT> && SrcVT . isVector ( ) ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; if ( SrcVT . isVector ( ) ) { MVT NewVT = <STR_LIT> ( SrcVT . getVectorElementType ( ) , SrcVT . getVectorNumElements ( ) * <NUM_LIT> ) ; Src = DAG . getNode ( <STR_LIT> , dl , NewVT , Src , DAG . getUNDEF ( SrcVT ) ) ; } else { assert ( SrcVT == <STR_LIT> && ! Subtarget . is64Bit ( ) && <STR_LIT> ) ;

Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ;


<s> MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) ; if ( llvm :: next ( I ) == MRI -> use_end ( ) && I . getOperand ( ) . getParent ( ) -> isPHI ( ) ) { MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ; for ( unsigned j = <NUM_LIT> , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( OPO . isReg ( ) && OPO . isDef ( ) ) { unsigned OPReg = OPO . getReg ( ) ; MachineRegisterInfo :: use_iterator nextJ ; for ( MachineRegisterInfo :: use_iterator J = MRI -> use_begin ( OPReg ) , E = MRI -> use_end ( ) ; J != E ; J = nextJ ) { nextJ = llvm :: next ( J ) ; MachineOperand & Use = J . getOperand ( ) ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) { return false ; } } } } DeadPhis . push_back ( OnePhi ) ; } else {


<s> SDValue <ISA_LIT>TargetLowering :: getReturnAddressFrameIndex ( SelectionDAG & DAG ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { uint64_t SlotSize = TD -> getPointerSize ( ) ;

ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , false , false ) ;


<s> BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Ws2 ) . addReg ( Ws1 ) ;

BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Ws2 ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> bool trace ( ) const { return Trace ;


<s> return isAISrcF16 ( ) || isAISrcB32 ( ) ;


<s> const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ;

for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) ISRDataRegFI [ I ] = MF . getFrameInfo ( ) . CreateStackObject ( TRI . getSpillSize ( RC ) , TRI . getSpillAlignment ( RC ) , false ) ;


<s> cost += inline_memory_move_cost ( mode , class1 , <NUM_LIT> ) ; cost += inline_memory_move_cost ( mode , class2 , <NUM_LIT> ) ; if ( GET_MODE_BITSIZE ( mode ) > BITS_PER_WORD && TARGET_MEMORY_MISMATCH_STALL && targetm . class_max_nregs ( class1 , mode ) > targetm . class_max_nregs ( class2 , mode ) ) cost += <NUM_LIT> ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += <NUM_LIT> ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) gcc_unreachable ( ) ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return ( SSE_CLASS_P ( class1 ) ? ix86_cost -> hard_register . sse_to_integer : ix86_cost -> hard_register . integer_to_sse ) ; if ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) { return ( MASK_CLASS_P ( class1 ) ? ix86_cost -> hard_register . mask_to_integer : ix86_cost -> hard_register . integer_to_mask ) ; } if ( MASK_CLASS_P ( class1 ) && MASK_CLASS_P ( class2 ) ) return ix86_cost -> hard_register . mask_move ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return ix86_cost -> hard_register . fp_move ; if ( MAYBE_SSE_CLASS_P ( class1 ) ) { if ( GET_MODE_BITSIZE ( mode ) <= <NUM_LIT> ) return ix86_cost -> hard_register . xmm_move ; if ( GET_MODE_BITSIZE ( mode ) <= <NUM_LIT> ) return ix86_cost -> hard_register . ymm_move ; return ix86_cost -> hard_register . zmm_move ; } if ( MAYBE_MMX_CLASS_P ( class1 ) ) return ix86_cost -> hard_register . mmx_move ; return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static unsigned getRRMOpcodeVariant ( unsigned Opcode ) { switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; }


<s> } else { <ISA_LIT>Operand const & Op = ( <ISA_LIT>Operand const & ) * Operands [ ErrorInfo ] ; if ( Op . getStartLoc ( ) != SMLoc ( ) ) { ErrorLoc = Op . getStartLoc ( ) ; } }


<s> SDValue InChain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; EVT PtrVT = VAListPtr . getValueType ( ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Node ) ; SDValue VAList = DAG . getLoad ( PtrVT , DL , InChain , VAListPtr , MachinePointerInfo ( SV ) , false , false , false , <NUM_LIT> ) ;

SDValue NextPtr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getIntPtrConstant ( VT . getSizeInBits ( ) / <NUM_LIT> ) ) ;


<s> break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } if ( pa_symbolic_expression_p ( x ) ) { if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , <NUM_LIT> ) ; if ( flag_pic || ! read_only_operand ( x , VOIDmode ) ) { switch ( mode ) { case E_SImode : sri -> icode = CODE_FOR_reload_insi_r1 ; break ; case E_DImode : sri -> icode = CODE_FOR_reload_indi_r1 ; break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } } if ( regno >= FIRST_PSEUDO_REGISTER || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; if ( ( regno >= FIRST_PSEUDO_REGISTER || regno == - <NUM_LIT> ) && FP_REG_CLASS_P ( rclass ) ) { if ( MEM_P ( x ) ) { x = XEXP ( x , <NUM_LIT> ) ; if ( IS_INDEX_ADDR_P ( x ) ) return NO_REGS ; } sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ;


<s> StringRef getToken ( ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( ! NONJUMP_INSN_P ( next ) ) return false ; set = single_set ( top ) ; if ( ! set ) return false ; set = single_set ( next ) ; if ( ! set ) return false ; if ( INSN_PRIORITY_KNOWN ( top ) && INSN_PRIORITY_KNOWN ( next ) ) { if ( INSN_PRIORITY ( top ) != INSN_PRIORITY ( next ) ) return false ; FOR_EACH_DEP ( top , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock1 ) clock1 = INSN_TICK ( pro ) ; } FOR_EACH_DEP ( next , SD_LIST_RES_BACK , sd_it , dep ) { rtx pro ; pro = DEP_PRO ( dep ) ; if ( ! NONDEBUG_INSN_P ( pro ) ) continue ; if ( INSN_TICK ( pro ) > clock2 ) clock2 = INSN_TICK ( pro ) ; } if ( clock1 == clock2 ) { enum attr_memory memory1 , memory2 ; memory1 = get_attr_memory ( top ) ; memory2 = get_attr_memory ( next ) ; if ( memory2 == MEMORY_LOAD && memory1 != MEMORY_LOAD ) return true ; }


<s> bool isProfitableForNoCSROpt ( const Function & F ) const override {


<s> if ( auto * Store = dyn_cast < StoreInst > ( V ) ) return LessOrEqualTypeSize ( Store -> getValueOperand ( ) ) ; if ( auto * Return = dyn_cast < ReturnInst > ( V ) ) return LessOrEqualTypeSize ( Return -> getReturnValue ( ) ) ; if ( auto * ZExt = dyn_cast < ZExtInst > ( V ) ) return GreaterThanTypeSize ( ZExt ) ; if ( auto * Switch = dyn_cast < SwitchInst > ( V ) ) return LessThanTypeSize ( Switch -> getCondition ( ) ) ; if ( auto * ICmp = dyn_cast < ICmpInst > ( V ) ) return ICmp -> isSigned ( ) || LessThanTypeSize ( ICmp -> getOperand ( <NUM_LIT> ) ) ; return isa < CallInst > ( V ) ;


<s> if ( TARGET_64BIT ) return false ; return ( decl && ! TREE_PUBLIC ( decl ) ) ;


<s> switch ( Kind ) { case Register : Reg = o . Reg ; break ; case Immediate : Imm = o . Imm ; break ;


<s> return false ; } case Match_MissingFeature : return Parser . Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Parser . Error ( IDLoc , <STR_LIT> ) ; case Match_NearMisses : return Parser . Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidTiedOperand : case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Parser . Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = Operands [ ErrorInfo ] -> getStartLoc ( ) ;

if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ;


<s> std :: vector < PredicatedBlock * > SPScope :: getFcfgBlocks ( ) const { auto result = getScopeBlocks ( ) ;

auto subheaders = Priv -> getSubheaders ( ) ;


<s> if ( isSimpleIndexCalc ( * I , EntryReg , BaseReg ) ) { RemovableAdd = & * I ; break ; } for ( unsigned K = <NUM_LIT> , E = I -> getNumOperands ( ) ; K != E ; ++ K ) { const MachineOperand & MO = I -> getOperand ( K ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) == BaseReg ) return false ; if ( MO . isUse ( ) && MO . getReg ( ) == BaseReg ) { BaseRegKill = BaseRegKill || MO . isKill ( ) ; CanDeleteLEA = false ; } } } if ( ! RemovableAdd ) return true ; for ( ++ I ; & * I != JumpMI ; ++ I ) { for ( unsigned K = <NUM_LIT> , E = I -> getNumOperands ( ) ; K != E ; ++ K ) { const MachineOperand & MO = I -> getOperand ( K ) ;


<s> HasLEB128 = true ; PrivateGlobalPrefix = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opcode = Op . getOpcode ( ) ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; if ( Subtarget . hasAVX512 ( ) ) { APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Amt , EltSizeInBits , UndefElts , EltBits ) ) { if ( ! UndefElts && llvm :: all_of ( EltBits , [ EltBits ] ( APInt & V ) { return EltBits [ <NUM_LIT> ] == V ; } ) ) { unsigned Op = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; uint64_t RotateAmt = EltBits [ <NUM_LIT> ] . urem ( EltSizeInBits ) ; return DAG . getNode ( Op , DL , VT , R , DAG . getConstant ( RotateAmt , DL , <STR_LIT> ) ) ; } } return Op ; } assert ( VT . isVector ( ) && <STR_LIT> ) ; assert ( Subtarget . hasXOP ( ) && <STR_LIT> ) ; assert ( ( Opcode == <STR_LIT> ) && <STR_LIT> ) ; if ( VT . is256BitVector ( ) ) return Lower256IntArith ( Op , DAG ) ;

assert ( VT . is128BitVector ( ) && <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: parseHwregBody ( OperandInfoTy & HwReg , OperandInfoTy & Offset , OperandInfoTy & Width ) { using namespace llvm :: <STR_LIT> ; HwReg . Loc = getLoc ( ) ;

if ( isToken ( AsmToken :: Identifier ) && ( HwReg . Id = getHwregId ( getTokenStr ( ) ) ) >= <NUM_LIT> ) {


<s> static SDValue emitConditionalComparison ( SDValue LHS , SDValue RHS , <STR_LIT> CC , SDValue CCOp , SDValue Condition , unsigned NZCV , SDLoc DL , SelectionDAG & DAG ) { unsigned Opcode = <NUM_LIT> ; if ( LHS . getValueType ( ) . isFloatingPoint ( ) ) Opcode = <STR_LIT> ; else if ( RHS . getOpcode ( ) == <STR_LIT> ) { SDValue SubOp0 = RHS . getOperand ( <NUM_LIT> ) ; if ( const ConstantSDNode * SubOp0C = dyn_cast < ConstantSDNode > ( SubOp0 ) ) if ( SubOp0C -> isNullValue ( ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) {


<s> } else { const MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) . addOperand ( Cond [ <NUM_LIT> ] ) ; if ( Cond . size ( ) > <NUM_LIT> ) MIB . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> const <ISA_LIT>Z80SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {

return LowerOperationWrapper ( N , Results , DAG ) ;


<s> return ( uint8x16_t ) __builtin_neon_vqsubuv16qi ( ( int8x16_t ) __a , ( int8x16_t ) __b ) ;


<s> if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } for ( Function & F : M ) { if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) FuncsToClone . push_back ( & F ) ; } for ( Function * F : FuncsToClone ) { ValueToValueMapTy VMap ;

Function * NewFunc = CloneFunction ( F , VMap ) ;


<s> if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MachineInstrBuilder ( MI ) ) ;

MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ;


<s> if ( DisableBackwardSearch ) return false ; RegDefsUses RegDU ( * MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ) ; MemDefsUses MemDU ( * TM . getDataLayout ( ) , MBB . getParent ( ) -> getFrameInfo ( ) ) ; ReverseIter Filler ; RegDU . init ( * Slot ) ; if ( ! searchRange ( MBB , ReverseIter ( Slot ) , MBB . rend ( ) , RegDU , MemDU , Slot , Filler ) ) return false ; MBB . splice ( std :: next ( Slot ) , & MBB , std :: next ( Filler ) . base ( ) ) ; MIBundleBuilder ( MBB , Slot , std :: next ( Slot , <NUM_LIT> ) ) ;


<s> switch ( GET_MODE_SIZE ( mode ) ) { case <NUM_LIT> : return val >= <NUM_LIT> && val < <NUM_LIT> ; case <NUM_LIT> : return val >= <NUM_LIT> && val < <NUM_LIT> && ( val & <NUM_LIT> ) == <NUM_LIT> ; default : return ( val >= <NUM_LIT> && ( val + GET_MODE_SIZE ( mode ) ) <= <NUM_LIT> && ( val & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> ; TrueCycles = <NUM_LIT> ; FalseCycles = <NUM_LIT> ; return true ; } return false ;


<s> void BlackfinDAGToDAGISel :: PostprocessISelDAG ( ) {


<s> EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; } else { Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; } Operands . push_back ( SEW ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , ScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( <STR_LIT> ) ) ;

SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ;


<s> struct cgraph_node * default_node = NULL ; struct cgraph_function_version_info * node_v = NULL ; struct cgraph_function_version_info * first_v = NULL ; tree dispatch_decl = NULL ; struct cgraph_function_version_info * default_version_info = NULL ; gcc_assert ( fn != NULL && DECL_FUNCTION_VERSIONED ( fn ) ) ; if ( TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> , get_decl_name ( fn ) ) ; node = cgraph_node :: get ( fn ) ; gcc_assert ( node != NULL ) ; node_v = node -> function_version ( ) ; gcc_assert ( node_v != NULL ) ; if ( node_v -> dispatcher_resolver != NULL ) return node_v -> dispatcher_resolver ; first_v = node_v ; while ( first_v -> prev != NULL ) first_v = first_v -> prev ;


<s> } if ( NumSuccessfulMatches > <NUM_LIT> ) { char MatchChars [ <NUM_LIT> ] ; unsigned NumMatches = <NUM_LIT> ; if ( Match1 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; if ( Match2 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; if ( Match3 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; if ( Match4 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) , EmptyRanges , MatchingInlineAsm ) ; return true ; } if ( ( Match1 == Match_MnemonicFail ) && ( Match2 == Match_MnemonicFail ) && ( Match3 == Match_MnemonicFail ) && ( Match4 == Match_MnemonicFail ) ) { if ( ! WasOriginallyInvalidOperand ) { ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : Op -> getLocRange ( ) ; return Error ( IDLoc , <STR_LIT> + Base + <STR_LIT> , Ranges , MatchingInlineAsm ) ; } if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> , EmptyRanges , MatchingInlineAsm ) ; <ISA_LIT>Operand * Operand = ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ; if ( Operand -> getStartLoc ( ) . isValid ( ) ) { SMRange OperandRange = Operand -> getLocRange ( ) ; return Error ( Operand -> getStartLoc ( ) , <STR_LIT> , OperandRange , MatchingInlineAsm ) ; } } return Error ( IDLoc , <STR_LIT> , EmptyRanges , MatchingInlineAsm ) ; } if ( ( Match1 == Match_MissingFeature ) + ( Match2 == Match_MissingFeature ) + ( Match3 == Match_MissingFeature ) + ( Match4 == Match_MissingFeature ) == <NUM_LIT> ) { std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfoMissingFeature ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfoMissingFeature & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfoMissingFeature & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg , EmptyRanges , MatchingInlineAsm ) ; }

if ( ( Match1 == Match_InvalidOperand ) + ( Match2 == Match_InvalidOperand ) + ( Match3 == Match_InvalidOperand ) + ( Match4 == Match_InvalidOperand ) == <NUM_LIT> ) {


<s> TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { RM = Reloc :: Static ;


<s> setRegionSize ( <NUM_LIT> ) ; return StartOffset ; } for ( std :: vector < unsigned > :: iterator i = CSRs . begin ( ) ; i != CSRs . end ( ) ; ) { if ( ! MRI -> isPhysRegModified ( * i ) ) i = CSRs . erase ( i ) ; else ++ i ; } unsigned Count = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> getObjectRegion ( i ) == this ) { unsigned ObjSize = MFI -> getObjectSize ( i ) ; unsigned Offset = StartOffset + Count ; unsigned Alignment = MFI -> getObjectAlignment ( i ) ;


<s> unsigned Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * Mov = BuildMI ( * MI . getParent ( ) , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( Val ) ; ( void ) Mov ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Mov -> dump ( ) ) ;

return MachineOperand :: CreateReg ( Reg , false ) ;


<s> auto LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ;

if ( cast < VectorType > ( Src ) -> getElementCount ( ) == ElementCount :: getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T , const StringRef TT ) : MCAsmBackend ( ) , STI ( <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ( TT , <STR_LIT> , <STR_LIT> ) ) {


<s> <ISA_LIT>WinCOFFStreamer ( MCContext & C , MCAsmBackend & AB , MCCodeEmitter * CE , raw_pwrite_stream & OS ) : MCWinCOFFStreamer ( C , AB , * CE , OS ) {


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {


<s> if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ; return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD ;


<s> unsigned zeroedSubInstS0 = subinstOpcodeMap . find ( SubInst0 . getOpcode ( ) ) -> second ; unsigned zeroedSubInstS1 = subinstOpcodeMap . find ( SubInst1 . getOpcode ( ) ) -> second ; if ( zeroedSubInstS0 < zeroedSubInstS1 ) return false ; } if ( MIb . getOpcode ( ) == <STR_LIT> ) return false ; if ( ( MIaG != <STR_LIT> ) && ( MIbG != <STR_LIT> ) ) { if ( subInstWouldBeExtended ( MIa ) ) return false ; if ( subInstWouldBeExtended ( MIb ) && ! ExtendedB ) return false ; } if ( MIbG == <STR_LIT> ) { if ( ( MIb . getNumOperands ( ) > <NUM_LIT> ) && MIb . getOperand ( <NUM_LIT> ) . isReg ( ) && ( MIb . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ; if ( ( MIb . getNumOperands ( ) > <NUM_LIT> ) && MIb . getOperand ( <NUM_LIT> ) . isReg ( ) && ( MIb . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ; } if ( ( MIbG == <STR_LIT> ) || ( MIbG == <STR_LIT> ) ) { if ( ( MIaG != <STR_LIT> ) && ( MIaG != <STR_LIT> ) ) return false ;


<s> ParseLiteralValues ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower ( ) == <STR_LIT> ) { ParseLiteralValues ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; } else if ( IDVal . lower ( ) == <STR_LIT> ) {

return ParseDirectiveRefSym ( DirectiveID ) ;


<s> if ( ! nested && ( ! TYPE_SIZE ( type ) || integer_zerop ( TYPE_SIZE ( type ) ) ) ) return VOIDmode ; switch ( code ) { case VOID_TYPE : case INTEGER_TYPE : case ENUMERAL_TYPE : case BOOLEAN_TYPE : case CHAR_TYPE : case POINTER_TYPE : case OFFSET_TYPE : case REFERENCE_TYPE : case METHOD_TYPE : case LANG_TYPE : case FUNCTION_TYPE : return VOIDmode ; case COMPLEX_TYPE : if ( GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_COMPLEX_FLOAT && TYPE_MODE ( type ) != TCmode ) return GET_MODE_INNER ( TYPE_MODE ( type ) ) ; else return VOIDmode ; case REAL_TYPE : if ( nested && TYPE_MODE ( type ) != TFmode ) return TYPE_MODE ( type ) ; else return VOIDmode ; case ARRAY_TYPE :

return hfa_element_mode ( TREE_TYPE ( type ) , <NUM_LIT> ) ;


<s> } switch ( Ext ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ;


<s> else if ( X87_FLOAT_MODE_P ( mode ) ) return cost -> fdiv ; else if ( FLOAT_MODE_P ( mode ) ) return ix86_vec_cost ( mode , inner_mode == DFmode ? cost -> divsd : cost -> divss , true ) ; else return cost -> divide [ MODE_INDEX ( mode ) ] ;


<s> emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushsi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushsi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } else { tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , fnaddr ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , chain_value ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , force_reg ( Pmode , plus_constant ( Pmode , r_tramp , <NUM_LIT> ) ) ) ; tmp = adjust_address ( m_tramp , Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , r_tramp , <NUM_LIT> ) ) ; emit_insn ( gen_anddi3 ( start_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; tmp = force_reg ( Pmode , plus_constant ( Pmode , tmp , TRAMPOLINE_CODE_SIZE - <NUM_LIT> ) ) ; emit_insn ( gen_anddi3 ( end_addr , tmp , GEN_INT ( - MIN_CACHELINE_SIZE ) ) ) ; emit_move_insn ( line_length , GEN_INT ( MIN_CACHELINE_SIZE ) ) ; emit_insn ( gen_dcacheflushdi ( start_addr , end_addr , line_length ) ) ; emit_insn ( gen_icacheflushdi ( start_addr , end_addr , line_length , gen_reg_rtx ( Pmode ) , gen_reg_rtx ( Pmode ) ) ) ; } emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) , LCT_NORMAL , VOIDmode , XEXP ( m_tramp , <NUM_LIT> ) , Pmode ) ;


<s> PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , OptLevel , Verbose ) ) ; return false ;


<s> } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( hasQPX ( ) || isBGQ ( ) ) StackAlignment = <NUM_LIT> ;

IsLittleEndian = ( TargetTriple . getArch ( ) == Triple :: ppc64le ) ;


<s> return static_cast < unsigned > ( ( MCInstD . TSFlags >> ImmOpNumStart ) & <ISA_LIT>II :: ImmOpNumMask ) ;


<s> inline static bool isRedundantFlagInstr ( const MachineInstr & FlagI , Register SrcReg , Register SrcReg2 , int64_t ImmMask , int64_t ImmValue , const MachineInstr & OI ) { if ( ( ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) ) && ( ( OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) || ( OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) ) return true ; if ( ImmMask != <NUM_LIT> && ( ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) ) && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI . getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ; return false ;


<s> unsigned <ISA_LIT>InstrInfo :: getIssueWidth ( const MachineInstr * MI ) const { if ( MI -> isInlineAsm ( ) ) return PST . getSchedModel ( ) -> IssueWidth ;

return PST . getIssueWidth ( MI -> getDesc ( ) . SchedClass ) ;


<s> const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFFrame -> getCalleeSavedInfo ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL ; int64_t SPOffsetFromCFA = - <STR_LIT> ; if ( ZFI -> getLowSavedGPR ( ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int64_t Offset = SPOffsetFromCFA + RegSpillOffsets [ Reg ] ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; }

SmallVector < unsigned , <NUM_LIT> > CFIIndexes ;


<s> } if ( Ctl . size ( ) != BITMASK_WIDTH ) { Error ( StrLoc , <STR_LIT> ) ; return false ; } unsigned AndMask = <NUM_LIT> ; unsigned OrMask = <NUM_LIT> ; unsigned XorMask = <NUM_LIT> ; for ( size_t i = <NUM_LIT> ; i < Ctl . size ( ) ; ++ i ) { unsigned Mask = <NUM_LIT> << ( BITMASK_WIDTH - <NUM_LIT> - i ) ; switch ( Ctl [ i ] ) { default : Error ( StrLoc , <STR_LIT> ) ; return false ; case '0' : break ; case '1' :


<s> if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) && ! MEM_P ( operands [ <NUM_LIT> ] ) ) return <NUM_LIT> ; if ( rl78_far_p ( operands [ <NUM_LIT> ] ) ) { rtx temp_reg = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; emit_move_insn ( temp_reg , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = temp_reg ; did = <NUM_LIT> ; } if ( rl78_far_p ( operands [ <NUM_LIT> ] ) ) { temp_reg = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ;


<s> if ( Op . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDLoc DL ( Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; return SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , Op , DAG . getTargetConstant ( <STR_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto IsHardwareLoopIntrinsic = [ ] ( Instruction & I ) { if ( auto * Call = dyn_cast < IntrinsicInst > ( & I ) ) { switch ( Call -> getIntrinsicID ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } return false ; } ; bool IsTailPredLoop = false ; auto ScanLoop = [ & ] ( Loop * L ) { for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( maybeLoweredToCall ( I ) || IsHardwareLoopIntrinsic ( I ) || isa < InlineAsm > ( I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I << <STR_LIT> ) ; return false ; } if ( auto * II = dyn_cast < IntrinsicInst > ( & I ) ) IsTailPredLoop |= II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> ; } } return true ; } ; for ( auto Inner : * L ) if ( ! ScanLoop ( Inner ) ) return false ; if ( ! ScanLoop ( L ) ) return false ; LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CounterInReg = true ; HWLoopInfo . IsNestingLegal = false ; HWLoopInfo . PerformEntryTest = AllowWLSLoops && ! IsTailPredLoop ; HWLoopInfo . CountType = Type :: getInt32Ty ( C ) ;

HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType , <NUM_LIT> ) ;


<s> } if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG || ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SIGN_EXTEND && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && GET_MODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == HImode ) ) { rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; emit_move_insn ( temp , val ) ; COPY_ONCE ( x ) ; XEXP ( x , <NUM_LIT> ) = temp ; if ( TARGET_COLDFIRE_FPU && GET_MODE_CLASS ( mode ) == MODE_FLOAT && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG ) x = force_operand ( x , <NUM_LIT> ) ; } else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG || ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SIGN_EXTEND && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && GET_MODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == HImode ) ) {


<s> <ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType _OSType , bool _isLittle , bool _is64Bit ) : MCAsmBackend ( ) , OSType ( _OSType ) , IsLittle ( _isLittle ) , Is64Bit ( _is64Bit ) {


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> return std :: make_unique < <ISA_LIT>ELFObjectWriter > ( Is64Bit , OSABI ) ;


<s> std :: string defCPU = <STR_LIT> ; if ( FS . empty ( ) && CPU . empty ( ) ) TargetName = defCPU ; else if ( ! CPU . empty ( ) ) TargetName = CPU ; else llvm_unreachable ( <STR_LIT> ) ; SmVersion = atoi ( TargetName . c_str ( ) + <NUM_LIT> ) ;


<s> case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> MachineInstr * Op3 = getDefIgnoringCopies ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( Op3 -> getOpcode ( ) == TargetOpcode :: G_FCONSTANT ) return Op3 -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> isExactlyValue ( <NUM_LIT> ) ; return false ; } ; if ( isKnownNeverNaN ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) || ( getIEEE ( ) && getDX10Clamp ( ) && ( isKnownNeverSNaN ( Val , MRI ) || isOp3Zero ( ) ) ) ) { Reg = Val ; return true ; } return false ;


<s> const avr_mcu_t * mcu ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; for ( mcu = avr_mcu_types ; mcu -> name ; mcu ++ ) { if ( mcu -> macro == NULL ) { arch_id = mcu -> arch_id ; print_mcus ( n_mcus ) ; n_mcus = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < sizeof ( avr_texinfo ) / sizeof ( * avr_texinfo ) ; i ++ ) if ( arch_id == avr_texinfo [ i ] . arch_id ) printf ( <STR_LIT> , mcu -> name , avr_texinfo [ i ] . texinfo ) ; }

else if ( arch_id == ( enum avr_arch_id ) mcu -> arch_id ) {


<s> return STI . getFeatureBits ( ) & <STR_LIT> ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ; if ( Subtarget . isCortexA9 ( ) && ! isPredicated ( MI ) && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) return std :: make_pair ( ExeVFP , ( <NUM_LIT> << ExeVFP ) | ( <NUM_LIT> << ExeNEON ) ) ; unsigned Domain = MI -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ; if ( ( Domain & <STR_LIT> ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , <NUM_LIT> ) ;

if ( Domain & <STR_LIT> ) return std :: make_pair ( ExeVFP , <NUM_LIT> ) ;


<s> if ( Dec && End && Revert ) break ; } LLVM_DEBUG ( if ( Start ) dbgs ( ) << <STR_LIT> << * Start ; if ( Dec ) dbgs ( ) << <STR_LIT> << * Dec ; if ( End ) dbgs ( ) << <STR_LIT> << * End ; ) ; if ( ! Start && ! Dec && ! End ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } else if ( ! ( Start && Dec && End ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! End -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( End -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getHeader ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; } if ( BBUtils -> getOffsetOf ( End ) < BBUtils -> getOffsetOf ( ML -> getHeader ( ) ) || ! BBUtils -> isBBInRange ( End , ML -> getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ;


<s> case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( ( Idx == ImmIdx ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; return <ISA_LIT>TTI :: getIntImmCost ( Imm , Ty ) ;


<s> return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else return false ; assert ( FI != INT_MAX ) ; if ( ! MFI . isFixedObjectIndex ( FI ) ) return false ; return Offset == MFI . getObjectOffset ( FI ) && Bytes == MFI . getObjectSize ( FI ) ;


<s> if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , * S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; EVT HalfVT = VT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned NumElts = HalfVT . getVectorNumElements ( ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> getAlignment ( ) , S -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SubVector1 , OffsetPtr , S -> getPointerInfo ( ) , S -> getAlignment ( ) , S -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> static int nds32_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) {


<s> if ( CVal ) O << CVal -> getName ( ) ; else O << S ; if ( Modifier ) O << <STR_LIT> << getModifierText ( ) << <STR_LIT> ; if ( PCAdjust != <NUM_LIT> ) { O << <STR_LIT> << LabelId << <STR_LIT> << ( unsigned ) PCAdjust ; if ( AddCurrentAddress ) O << <STR_LIT> ; O << <STR_LIT> ; }


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> MachineInstrBuilder buildMI ( Block & MBB , BlockIt MBBI , unsigned Opcode , Register DstReg ) {

return BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( Opcode ) , DstReg ) ;


<s> MachineBasicBlock :: iterator NewMI = mergeWrite2Pair ( CI ) ; CI . setMI ( NewMI , * TII , * STM ) ; } break ; case S_BUFFER_LOAD_IMM : if ( findMatchingInst ( CI ) ) { Modified = true ; removeCombinedInst ( MergeList , * CI . Paired ) ; MachineBasicBlock :: iterator NewMI = mergeSBufferLoadImmPair ( CI ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width0 + CI . Width1 ) < <NUM_LIT> ; } break ; case BUFFER_LOAD : if ( findMatchingInst ( CI ) ) { Modified = true ; removeCombinedInst ( MergeList , * CI . Paired ) ; MachineBasicBlock :: iterator NewMI = mergeBufferLoadPair ( CI ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width0 + CI . Width1 ) < <NUM_LIT> ; } break ; case BUFFER_STORE : if ( findMatchingInst ( CI ) ) { Modified = true ; removeCombinedInst ( MergeList , * CI . Paired ) ; MachineBasicBlock :: iterator NewMI = mergeBufferStorePair ( CI ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width0 + CI . Width1 ) < <NUM_LIT> ; } break ; } CI . InstsToMove . clear ( ) ; }


<s> static void insertCondBranchBefore ( MachineBasicBlock * blk , MachineBasicBlock :: iterator insertPos , int newOpcode , AMDGPUCFGStructurizer * passRep , RegiT regNum , DebugLoc DL ) {

const TargetInstrInfo * tii = passRep -> getTargetInstrInfo ( ) ;


<s> EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCOffsetDeltaExpr ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } MCSymbol * LocalEntryLabel = <ISA_LIT>FI -> getLocalEPSymbol ( ) ; OutStreamer -> emitLabel ( LocalEntryLabel ) ; const MCSymbolRefExpr * LocalEntryLabelExp = MCSymbolRefExpr :: create ( LocalEntryLabel , OutContext ) ; const MCExpr * LocalOffsetExp = MCBinaryExpr :: createSub ( LocalEntryLabelExp , GlobalEntryLabelExp , OutContext ) ; <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; if ( TS ) TS -> emitLocalEntry ( cast < MCSymbolELF > ( CurrentFnSym ) , LocalOffsetExp ) ; }


<s> unsigned TO = MaskVal . countTrailingOnes ( ) ; if ( TO >= <NUM_LIT> && isPowerOf2_32 ( TO ) ) return SDValue ( ) ; } APInt NewMaskVal = MaskVal . lshr ( ShiftC -> getAPIntValue ( ) ) ; unsigned OldMaskSize = MaskVal . getMinSignedBits ( ) ; unsigned NewMaskSize = NewMaskVal . getMinSignedBits ( ) ; if ( ( OldMaskSize > <NUM_LIT> && NewMaskSize <= <NUM_LIT> ) || ( OldMaskSize > <NUM_LIT> && NewMaskSize <= <NUM_LIT> ) ) { SDLoc DL ( N ) ; SDValue NewMask = DAG . getConstant ( NewMaskVal , DL , VT ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NewShift , NewMask ) ;


<s> } aa , bb ; aa . v = ( vector unsigned int ) ( a ) ; bb . v = ( vector unsigned int ) ( b ) ;

if ( aa . i [ <NUM_LIT> ] > bb . i [ <NUM_LIT> ] ) { SPU_HALT_ACTION ; } ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> unsigned Flags = MI . getFlags ( ) ; LLT Ty = B . getMRI ( ) -> getType ( Dst ) ; B . setInstr ( MI ) ; auto K = B . buildFConstant ( Ty , numbers :: log2e ) ; auto Mul = B . buildFMul ( Ty , Src , K , Flags ) ; B . buildFExp2 ( Dst , Mul , Flags ) ;