<s> return SDValue ( ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : fail ( DL , DAG , <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> :


<s> unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ;

MCCFIInstruction Inst = MCCFIInstruction :: createDefCfaRegister ( nullptr , SP ) ;


<s> bool isIntrinsic ( ) const { return ( Attributes & <ISA_LIT>FMA3Intrinsic ) != <NUM_LIT> ;


<s> reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RC ) ) { if ( ! ( RI . getRegSizeInBits ( * RC ) % <NUM_LIT> ) ) { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } else { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } if ( ! RI . isSGPRClass ( RI . getPhysRegClass ( SrcReg ) ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } } ArrayRef < int16_t > SubIndices = RI . getRegSplitParts ( RC , EltSize ) ; bool Forward = RI . getHWRegIndex ( DestReg ) <= RI . getHWRegIndex ( SrcReg ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < SubIndices . size ( ) ; ++ Idx ) { unsigned SubIdx ; if ( Forward ) SubIdx = SubIndices [ Idx ] ; else SubIdx = SubIndices [ SubIndices . size ( ) - Idx - <NUM_LIT> ] ; MachineInstrBuilder Builder = BuildMI ( MBB , MI , DL , get ( Opcode ) , RI . getSubReg ( DestReg , SubIdx ) ) ; Builder . addReg ( RI . getSubReg ( SrcReg , SubIdx ) ) ;

if ( Idx == <NUM_LIT> ) Builder . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ;


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; assert ( ( ( Val && VReg ) || ( ! Val && ! VReg ) ) && <STR_LIT> ) ; bool Success = true ; if ( VReg ) { const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ;

setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ;


<s> return new <ISA_LIT>ExpandPseudo ( ) ;


<s> uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( SizeVal < <NUM_LIT> || ( SizeVal % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ;


<s> const DebugLoc & dl = MI . getDebugLoc ( ) ; ASSERT_SORTED ( PopTable ) ; if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; RegMap [ Stack [ -- StackTop ] ] = ~ <NUM_LIT> ;

int Opcode = Lookup ( PopTable , I -> getOpcode ( ) ) ;


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS ) ;


<s> return parseRegister ( Operands , GR32Reg ) ;


<s> void <ISA_LIT>ScheduleBlockCreator :: colorHighLatenciesAlone ( ) { unsigned DAGSize = DAG -> SUnits . size ( ) ; for ( unsigned i = <NUM_LIT> , e = DAGSize ; i != e ; ++ i ) {


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; SDValue SplattedVal = splatSplitI64WithVL ( DL , VT , Scalar , VL , DAG ) ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , VL ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , VL ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; SDValue SelectCond = DAG . getNode ( <STR_LIT> , DL , MaskVT , VID , SplattedIdx , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectCond , SplattedVal , Vec , VL ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = Op . getNumOperands ( ) ; bool IsMasked = NumOps == <NUM_LIT> ; unsigned OpOffset = IsMasked ? <NUM_LIT> : <NUM_LIT> ; SDValue Scalar = Op . getOperand ( <NUM_LIT> + OpOffset ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) break ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( Scalar ) ) if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) break ; MVT VT = Op . getSimpleValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT I32VT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue Vec = DAG . getBitcast ( I32VT , Op . getOperand ( <NUM_LIT> + OpOffset ) ) ; SDValue ScalarLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue ScalarHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;

SDValue VL = Op . getOperand ( NumOps - ( <NUM_LIT> + OpOffset ) ) ;


<s> for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( Inst ) ) { MCInst & CrntHMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; if ( * RelaxTarget == & CrntHMI ) { Update = true ; assert ( ( <ISA_LIT>MCInstrInfo :: bundleSize ( Res ) < HEXAGON_PACKET_SIZE ) && <STR_LIT> ) ;


<s> static unsigned getCRBitValue ( unsigned CRBit ) { unsigned Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; assert ( Ret != <NUM_LIT> && <STR_LIT> ) ;


<s> return __builtin_ia32_vcvtpd2ph512_mask_round ( ( __v8df ) __A , _mm_setzero_ph ( ) , ( __mmask8 ) - <NUM_LIT> , __B ) ;


<s> DiagnosticPredicate isMatrixRegOperand ( ) const { if ( ! isMatrix ( ) ) return DiagnosticPredicateTy :: NoMatch ; if ( getMatrixKind ( ) != Kind || ! <ISA_LIT>MCRegisterClasses [ RegClass ] . contains ( getMatrixReg ( ) ) || EltSize != getMatrixElementWidth ( ) ) return DiagnosticPredicateTy :: NearMatch ; return DiagnosticPredicateTy :: Match ;


<s> return ( uint64x2_t ) __builtin_neon_vdup_nv2di ( ( __builtin_neon_di ) __a ) ;


<s> const ConstantInt * CI = cast < ConstantInt > ( C ) ; unsigned ImmReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CI -> isZero ( ) ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getSExtValue ( ) ) ; return ImmReg ; }


<s> value_rtx = convert_to_mode ( Pmode , value_rtx , <NUM_LIT> ) ; emit_library_call ( sym , LCT_NORMAL , VOIDmode , <NUM_LIT> , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> <NUM_LIT> ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ;


<s> case <STR_LIT> :: Generic : return <NUM_LIT> ; case <STR_LIT> :: Input : return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> int IK = getInstKind ( SU ) ; if ( IK == IDOther ) Available [ IDOther ] . push_back ( SU ) ; else Pending [ IK ] . push_back ( SU ) ;


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; Offset += <NUM_LIT> ;

if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) . getStackSize ( ) ;


<s> if ( CC == CallingConv :: CXX_FAST_TLS ) return CSR_<ISA_LIT>_CXX_TLS_Darwin_RegMask ; if ( CC == CallingConv :: <ISA_LIT>_VectorCall ) return CSR_Darwin_<ISA_LIT>_AAVPCS_RegMask ; if ( CC == CallingConv :: <ISA_LIT>_SVE_VectorCall ) report_fatal_error ( <STR_LIT> ) ; if ( CC == CallingConv :: CFGuard_Check ) report_fatal_error ( <STR_LIT> ) ;


<s> int arx_reg_operand ( rtx op , enum machine_mode mode ) {

if ( mode != VOIDmode && mode != GET_MODE ( op ) ) return <NUM_LIT> ;


<s> void <ISA_LIT>TargetLowering :: LowerFP_TO_INTForReuse ( SDValue Op , ReuseLoadInfo & RLI , SelectionDAG & DAG , const SDLoc & dl ) const { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; SDValue Tmp ; switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : ( Subtarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && Subtarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ; SDValue Chain ;

Align Alignment ( DAG . getEVTAlign ( Tmp . getValueType ( ) ) ) ;


<s> MachineFunctionPass ( ID ) , TM ( tm ) , STC ( tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( tm . getInstrInfo ( ) ) ) , TRI ( static_cast < const <ISA_LIT>RegisterInfo * > ( tm . getRegisterInfo ( ) ) ) {


<s> assert ( ( TyWidth % ElemWidth ) == <NUM_LIT> ) ; return <STR_LIT> ( ElemTy , TyWidth / ElemWidth ) ;


<s> location_t loc = * ( ( location_t * ) data ) ; if ( TYPE_P ( * tp ) ) { * walk_subtrees = <NUM_LIT> ; return NULL_TREE ; } if ( bpf_core_is_maybe_aggregate_access ( * tp ) ) {

tree newdecl = bpf_core_newdecl ( TREE_TYPE ( * tp ) ) ;


<s> -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) { StoreI = MBBI ; return true ; } if ( MI . isCall ( ) ) return false ; TII -> trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] ) return false ; if ( MI . mayStore ( ) && mayAlias ( LoadMI , MI , AA ) ) return false ; } while ( MBBI != B && Count < Limit ) ; return false ;


<s> NegatibleCost N2Cost = NegatibleCost :: Expensive ; SDValue NegN2 = getNegatedExpression ( N2 , DAG , LegalOps , OptForSize , N2Cost , Depth + <NUM_LIT> ) ; if ( ! NegN2 ) return SDValue ( ) ; if ( Flags . hasNoSignedZeros ( ) || Options . NoSignedZerosFPMath ) { NegatibleCost N0Cost = NegatibleCost :: Expensive ; SDValue NegN0 = getNegatedExpression ( N0 , DAG , LegalOps , OptForSize , N0Cost , Depth + <NUM_LIT> ) ; NegatibleCost N1Cost = NegatibleCost :: Expensive ; SDValue NegN1 = getNegatedExpression ( N1 , DAG , LegalOps , OptForSize , N1Cost , Depth + <NUM_LIT> ) ; if ( NegN0 && N0Cost <= N1Cost ) { Cost = std :: min ( N0Cost , N2Cost ) ; return DAG . getNode ( Opc , Loc , VT , NegN0 , N1 , NegN2 , Flags ) ; } else if ( NegN1 ) { Cost = std :: min ( N1Cost , N2Cost ) ;

return DAG . getNode ( Opc , Loc , VT , N0 , NegN1 , NegN2 , Flags ) ;


<s> case Instruction :: Add : case Instruction :: Sub : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Mul : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Or : case Instruction :: Xor : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Free ; } break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( BitSize <= <NUM_LIT> ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( ~ Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ;


<s> for ( unsigned i = <NUM_LIT> ; i < VF -> Values . size ( ) ; i ++ ) { yaml :: Value Val = VF -> Values [ i ] ; if ( Val . Symbol . empty ( ) && ( Val . Max - Val . Min > ( <NUM_LIT> << BypassRangeThreshold ) ) ) { return true ; } }


<s> assert ( MemRefBeginIdx >= <NUM_LIT> && <STR_LIT> ) ; MemRefBeginIdx += <STR_LIT> ( Desc ) ; MachineOperand & BaseMO = UseMI . getOperand ( MemRefBeginIdx + <STR_LIT> ) ; MachineOperand & IndexMO = UseMI . getOperand ( MemRefBeginIdx + <STR_LIT> ) ; if ( ( BaseMO . isReg ( ) && BaseMO . getReg ( ) == DefReg ) || ( IndexMO . isReg ( ) && IndexMO . getReg ( ) == DefReg ) ) return { } ; continue ; } if ( SingleUseMI ) return { } ; if ( ! <ISA_LIT>InstrInfo :: isDataInvariant ( UseMI ) || UseMI . getParent ( ) != MI . getParent ( ) || isEFLAGSDefLive ( UseMI ) ) return { } ; if ( UseMI . getDesc ( ) . getNumDefs ( ) > <NUM_LIT> ) return { } ; Register UseDefReg = UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( UseDefReg ) || ! canHardenRegister ( UseDefReg ) ) return { } ; SingleUseMI = & UseMI ; } return { SingleUseMI } ; } ; MachineInstr * MI = & InitialMI ; while ( Optional < MachineInstr * > SingleUse = SinkCheckToSingleUse ( * MI ) ) { MI = * SingleUse ; if ( ! MI ) break ; } return MI ;


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } unsigned Reg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ;

return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , VT ) ;


<s> void <ISA_LIT>TargetStreamer :: emitRRX ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , MCOperand Op2 , SMLoc IDLoc , const MCSubtargetInfo * STI ) {


<s> FunctionPass * llvm :: create<ISA_LIT>LowOverheadLoopsPass ( ) {

return new <ISA_LIT>LowOverheadLoops ( ) ;


<s> void <ISA_LIT>BitcodeWriter :: writeModuleConstants ( ) { const ValueEnumerator :: ValueList & Vals = VE . getValues ( ) ; for ( unsigned i = <NUM_LIT> , e = Vals . size ( ) ; i != e ; ++ i ) { if ( ! isa < GlobalValue > ( Vals [ i ] . first ) ) { writeConstants ( i , Vals . size ( ) , true ) ; return ; }


<s> bool ContainsWWM = false ; for ( auto WWM : WWMs ) { if ( Loop -> contains ( WWM -> getParent ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * WWM ) ; ContainsWWM = true ; break ; } } if ( ! ContainsWWM ) return false ; unsigned Reg = DefOpnd -> getReg ( ) ; for ( auto & Use : MRI -> use_operands ( Reg ) ) Use . setIsKill ( false ) ; SmallVector < MachineInstr * , <NUM_LIT> > Defs ; for ( auto & Def : MRI -> def_instructions ( Reg ) ) Defs . push_back ( & Def ) ; for ( auto Def : Defs ) { if ( DefOpnd -> getParent ( ) == Def ) continue ;

Def -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true ) ) ;


<s> void <ISA_LIT>TargetMachine :: addAnalysisPasses ( PassManagerBase & PM ) { if ( Subtarget . allowMixed16_32 ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ) ; PM . add ( createNoTargetTransformInfoPass ( ) ) ;

} else LLVMTargetMachine :: addAnalysisPasses ( PM ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ;


<s> rtx insn ; bool need_barrier_p = known_ne ( get_frame_size ( ) + cfun -> machine -> frame . arg_pointer_offset , <NUM_LIT> ) ; if ( cfun -> machine -> naked_p ) { gcc_assert ( style == NORMAL_RETURN ) ; emit_jump_insn ( gen_return ( ) ) ; return ; } if ( ( style == NORMAL_RETURN ) && riscv_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } epilogue_cfa_sp_offset = <NUM_LIT> ; if ( cfun -> calls_alloca ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; poly_int64 adjust_offset = - frame -> hard_frame_pointer_offset ; rtx adjust = NULL_RTX ; if ( ! adjust_offset . is_constant ( ) ) { rtx tmp1 = RISCV_PROLOGUE_TEMP ( Pmode ) ; rtx tmp2 = RISCV_PROLOGUE_TEMP2 ( Pmode ) ; riscv_legitimize_poly_move ( Pmode , tmp1 , tmp2 , gen_int_mode ( adjust_offset , Pmode ) ) ; adjust = tmp1 ; } else { if ( ! SMALL_OPERAND ( adjust_offset . to_constant ( ) ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( adjust_offset . to_constant ( ) ) ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } else adjust = GEN_INT ( adjust_offset . to_constant ( ) ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_value = gen_rtx_PLUS ( Pmode , hard_frame_pointer_rtx , gen_int_mode ( - frame -> hard_frame_pointer_offset , Pmode ) ) ; rtx cfa_adjust_rtx = gen_rtx_SET ( stack_pointer_rtx , cfa_adjust_value ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { step2 = riscv_first_stack_step ( frame ) ; step1 -= step2 ; } if ( known_gt ( step1 , <NUM_LIT> ) ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; if ( ! step1 . is_constant ( ) ) {


<s> case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI . getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ; else return nullptr ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) . getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = Type :: getFP128Ty ( MF . getFunction ( ) . getContext ( ) ) ;

else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return true ; } } if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && RegSize > <NUM_LIT> ) { switch ( UserOpc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( VT . getVectorNumElements ( ) == <NUM_LIT> ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = scalarizeVectorLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SL ) ; } SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = getSplitDestVTs ( VT , DAG ) ; std :: tie ( LoMemVT , HiMemVT ) = getSplitDestVTs ( MemVT , DAG ) ; std :: tie ( Lo , Hi ) = splitVector ( Op , SL , LoVT , HiVT , DAG ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ;

unsigned HiAlign = MinAlign ( BaseAlign , Size ) ;


<s> if ( Opcode == <STR_LIT> ) return { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; llvm_unreachable ( <STR_LIT> ) ; } ( ) ; const bool IsSet = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; for ( auto Op : Ops ) { int i = <NUM_LIT> ; auto MCIB = MCInstBuilder ( Op ) ; MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; if ( ! IsSet ) MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ; MCIB . addReg ( MI . getOperand ( i ++ ) . getReg ( ) ) ;


<s> const RegisterBank & <ISA_LIT>RegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC ) const { if ( & RC == & <STR_LIT> ) return <STR_LIT> ; if ( TRI -> isSGPRClass ( & RC ) ) return <STR_LIT> ; if ( TRI -> isAGPRClass ( & RC ) ) return <STR_LIT> ;


<s> static int ix86_avx_u128_mode_after ( int mode , rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; if ( vzeroupper_pattern ( pat , VOIDmode ) || vzeroall_pattern ( pat , VOIDmode ) ) return AVX_U128_CLEAN ;


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; } addPass ( create<ISA_LIT>GatherPacketize ( ) , false ) ;

if ( ! NoOpt ) addPass ( create<ISA_LIT>Packetizer ( ) , false ) ;


<s> <ISA_LIT>Type * <ISA_LIT>GlobalRegistry :: getOrCreate<ISA_LIT>IntegerType ( unsigned BitWidth , MachineInstr & I , const <ISA_LIT>InstrInfo & TII ) { Type * LLVMTy = IntegerType :: get ( CurMF -> getFunction ( ) . getContext ( ) , BitWidth ) ;

MachineBasicBlock & BB = * I . getParent ( ) ;


<s> for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) { if ( ! MRI . isPhysRegUsed ( reg ) ) continue ; unsigned mapped_reg = ( reg - <STR_LIT> + <STR_LIT> ) ; assert ( ! MRI . isPhysRegUsed ( mapped_reg ) ) ; MRI . replaceRegWith ( reg , mapped_reg ) ; MRI . setPhysRegUnused ( reg ) ;


<s> unsigned getHWRegIndex ( unsigned Reg ) const {

return getEncodingValue ( Reg ) & <NUM_LIT> ;


<s> unsigned int OffsetReg = loadConstant ( MBB , MBBI , Amount ) ;

BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( OffsetReg , RegState :: Kill ) ;


<s> <ISA_LIT>Z80RegisterInfo :: <ISA_LIT>Z80RegisterInfo ( <ISA_LIT>Z80TargetMachine & tm , const TargetInstrInfo & tii ) : <ISA_LIT>Z80GenRegisterInfo ( <STR_LIT> ) , TM ( tm ) , TII ( tii ) {


<s> if ( Opcode == <STR_LIT> && ST . hasGFX90AInsts ( ) ) return false ; int Op32 = <STR_LIT> ( Opcode ) ;

if ( Op32 == - <NUM_LIT> ) return false ;


<s> unsigned Opcode = MI . getOpcode ( ) ; return Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> AMDGPURegisterInfo :: AMDGPURegisterInfo ( TargetMachine & tm , const TargetInstrInfo & tii ) : AMDGPUGenRegisterInfo ( <NUM_LIT> ) , TM ( tm ) , TII ( tii ) {


<s> return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> if ( isCPLoad ( N ) || isConstantLoad ( N , - <NUM_LIT> ) ) { return false ; } } const Value * MemVal = N -> getMemOperand ( ) -> getValue ( ) ; if ( ! checkType ( MemVal , <ISA_LIT>AS :: LOCAL_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: GLOBAL_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: FLAT_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: REGION_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: CONSTANT_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: PARAM_D_ADDRESS ) && ! checkType ( MemVal , <ISA_LIT>AS :: PARAM_I_ADDRESS ) ) { return true ; }


<s> return isXXBRShuffleMaskHelper ( N , <NUM_LIT> ) ;


<s> if ( size ( ) > <NUM_LIT> && check ( ) ) for ( unsigned nSlot = <NUM_LIT> , emptySlots = <NUM_LIT> ; nSlot < HEXAGON_PACKET_SIZE ; ++ nSlot ) { iterator ISJ , ISK ; unsigned slotSkip , slotWeight ; for ( ISJ = ISK = Packet . begin ( ) , slotSkip = slotWeight = <NUM_LIT> ; ISK != Packet . end ( ) ; ++ ISK , ++ slotSkip ) if ( slotSkip < nSlot - emptySlots ) ++ ISJ ; else slotWeight += ISK -> Core . setWeight ( HEXAGON_PACKET_SIZE - nSlot - <NUM_LIT> ) ; if ( slotWeight ) std :: sort ( ISJ , Packet . end ( ) ) ; else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ISJ -> getDesc ( ) ) . getOpcode ( ) ;


<s> static htab_t htab ; unsigned int flags ; unsigned int * * slot ; if ( ! htab ) htab = htab_create ( <NUM_LIT> , htab_hash_pointer , htab_eq_pointer , NULL ) ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) flags = SECTION_CODE ; else if ( decl && decl_readonly_section ( decl , reloc ) ) flags = <NUM_LIT> ; else { flags = SECTION_WRITE ; if ( decl && TREE_CODE ( decl ) == VAR_DECL && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) flags |= SECTION_PE_SHARED ; } if ( decl && DECL_ONE_ONLY ( decl ) ) flags |= SECTION_LINKONCE ;

slot = ( unsigned int * * ) htab_find_slot ( htab , name , INSERT ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {


<s> AMDGPU770Device :: AMDGPU770Device ( AMDGPUSubtarget * ST ) : AMDGPU7XXDevice ( ST ) {


<s> OptLEA = ST . LEAusesAG ( ) || ST . slowLEA ( ) || ST . slow3OpsLEA ( ) ; if ( ! OptLEA && ! OptIncDec ) return false ; TII = ST . getInstrInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I ) processBasicBlock ( Func , I ) ;


<s> static SDValue foldMaskedMergeImpl ( SDValue And0_L , SDValue And0_R , SDValue And1_L , SDValue And1_R , SDLoc DL , SelectionDAG & DAG ) { if ( ! isBitwiseNot ( And0_L , true ) || ! And0_L -> hasOneUse ( ) ) return SDValue ( ) ; SDValue NotOp = And0_L -> getOperand ( <NUM_LIT> ) ; if ( NotOp == And1_R ) std :: swap ( And1_R , And1_L ) ; if ( NotOp != And1_L ) return SDValue ( ) ; EVT VT = And1_L -> getValueType ( <NUM_LIT> ) ; SDValue Freeze_And0_R = DAG . getNode ( <STR_LIT> , SDLoc ( ) , VT , And0_R ) ; SDValue Xor0 = DAG . getNode ( <STR_LIT> , DL , VT , And1_R , Freeze_And0_R ) ;

SDValue And = DAG . getNode ( <STR_LIT> , DL , VT , Xor0 , NotOp ) ;


<s> <ISA_LIT>CopyToCombine ( ) : MachineFunctionPass ( ID ) {


<s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {


<s> if ( ! GV -> isThreadLocal ( ) ) return false ; if ( ! rewriteNonInstructionUses ( GV , this ) || ! GV -> getType ( ) -> isSized ( ) || isZeroLengthArray ( GV -> getType ( ) ) ) return false ; ArrayType * NewType = createLoweredType ( GV -> getValueType ( ) ) ; Constant * NewInitializer = nullptr ; if ( GV -> hasInitializer ( ) ) NewInitializer = createLoweredInitializer ( NewType , GV -> getInitializer ( ) ) ; GlobalVariable * NewGV = new GlobalVariable ( * M , NewType , GV -> isConstant ( ) , GV -> getLinkage ( ) , NewInitializer , <STR_LIT> , nullptr , GlobalVariable :: NotThreadLocal , GV -> getType ( ) -> getAddressSpace ( ) , GV -> isExternallyInitialized ( ) ) ; SmallVector < User * , <NUM_LIT> > Users ( GV -> users ( ) ) ; for ( unsigned I = <NUM_LIT> , E = Users . size ( ) ; I != E ; ++ I ) { User * U = Users [ I ] ; Instruction * Inst = cast < Instruction > ( U ) ; IRBuilder < > Builder ( Inst ) ; Function * GetID = <STR_LIT> ( GV -> getParent ( ) , <STR_LIT> ) ; Value * ThreadID = Builder . CreateCall ( GetID , { } ) ; Value * Addr = Builder . CreateInBoundsGEP ( NewGV -> getValueType ( ) , NewGV , { Builder . getInt64 ( <NUM_LIT> ) , ThreadID } ) ; U -> replaceUsesOfWith ( GV , Addr ) ; } NewGV -> takeName ( GV ) ; GV -> eraseFromParent ( ) ;


<s> return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ;


<s> if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm * <NUM_LIT> ;

else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm * <NUM_LIT> ;


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> BR -> RemoveOperand ( BR -> getNumExplicitOperands ( ) - <NUM_LIT> ) ; BR -> addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , false , true ) ) ; opcode = opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } } BR -> setDesc ( PII . get ( opcode ) ) ; int delaySlots = PTM . getSubtargetImpl ( ) -> getCFLDelaySlotCycles ( false ) ; int cycles = delaySlots - PTM . getSubtargetImpl ( ) -> getCFLDelaySlotCycles ( true ) ; MachineBasicBlock :: iterator I = II ; if ( PTM . getSubtargetImpl ( ) -> getCFLType ( ) != <ISA_LIT>Subtarget :: CFL_NON_DELAYED && ! PII . hasRegUse ( & * I ) && PII . canRemoveFromSchedule ( MBB , I ) ) { cycles = PII . moveUp ( MBB , I , cycles ) ; } PII . advanceCycles ( MBB , I , delaySlots - cycles + <NUM_LIT> ) ;

for ( int i = <NUM_LIT> ; i < cycles ; i ++ ) {


<s> if ( argtype == error_mark_node || VOID_TYPE_P ( argtype ) ) break ; if ( TYPE_EMPTY_P ( argtype ) ) seen_empty_type = true ; else if ( seen_empty_type ) {


<s> <STR_LIT> Cmp ; std :: tie ( Imm , Opc , Cmp ) = Info ; MachineBasicBlock * const MBB = CmpMI -> getParent ( ) ; BuildMI ( * MBB , CmpMI , CmpMI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm ) . addOperand ( CmpMI -> getOperand ( <NUM_LIT> ) ) ; CmpMI -> eraseFromParent ( ) ;

MachineInstr * BrMI = MBB -> getFirstTerminator ( ) ;


<s> int i ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) if ( ( HOST_WIDE_INT_1 << i ) - <NUM_LIT> == INTVAL ( x ) || ( HOST_WIDE_INT_1 << i ) - <NUM_LIT> == ~ INTVAL ( x ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer == ASHIFT || outer == ASHIFTRT || outer == LSHIFTRT ) return <NUM_LIT> ; return COSTS_N_INSNS ( <NUM_LIT> ) ; case CONST : case CONST_DOUBLE : case LABEL_REF : case SYMBOL_REF : return COSTS_N_INSNS ( <NUM_LIT> ) ; case UDIV : case UMOD : case DIV : case MOD : return <NUM_LIT> ; case TRUNCATE : return <NUM_LIT> ; case AND : case XOR : case IOR : return <NUM_LIT> ; case MEM : return ( <NUM_LIT> + <NUM_LIT> * ( ( GET_MODE_SIZE ( mode ) - <NUM_LIT> ) / UNITS_PER_WORD ) + ( ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) ? <NUM_LIT> : <NUM_LIT> ) ) ; case IF_THEN_ELSE : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PC || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PC ) return <NUM_LIT> ; return <NUM_LIT> ; case SIGN_EXTEND : case ZERO_EXTEND : total = mode == DImode ? COSTS_N_INSNS ( <NUM_LIT> ) : <NUM_LIT> ; total += thumb1_rtx_costs ( XEXP ( x , <NUM_LIT> ) , GET_CODE ( XEXP ( x , <NUM_LIT> ) ) , code ) ;


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ;

if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) {


<s> if ( FP32OutputDenormals ) return FP_DENORM_FLUSH_IN ;


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ;


if ( parseImmExpr ( Offset ) ) return true ;


<s> if ( UnsignedFixup ) { APFloat Thresh ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ; SDValue Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) , Value , ThreshVal , <STR_LIT> ) ; Adjust = DAG . getSelect ( DL , <STR_LIT> , Cmp , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( APInt :: getSignMask ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , DL , TheVT , Value , ThreshVal ) ; Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) , Value , ThreshVal , <STR_LIT> ) ; Value = DAG . getSelect ( DL , TheVT , Cmp , Value , Sub ) ; } MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , SSFI ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MPI ) ; SDVTList Tys = DAG . getVTList ( TheVT , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot } ; unsigned FLDSize = TheVT . getStoreSize ( ) ; assert ( FLDSize <= MemSize && <STR_LIT> ) ;

MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOLoad , FLDSize , FLDSize ) ;


<s> LocVT = <STR_LIT> ; if ( ! Reg ) { unsigned StackOffset = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ; return false ; } if ( ! State . AllocateReg ( ArgGPRs ) ) State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } Register Reg ; if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR16s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF16_F32 ) Reg = State . AllocateReg ( ArgFPR32s ) ; else if ( ValVT == <STR_LIT> && ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s ) ; else if ( ValVT . isScalableVector ( ) ) { const TargetRegisterClass * RC = TLI . getRegClassFor ( ValVT ) ; if ( RC == & <STR_LIT> ) { if ( FirstMaskArgument . hasValue ( ) && ValNo == FirstMaskArgument . getValue ( ) ) { Reg = State . AllocateReg ( <STR_LIT> ) ; } else { Reg = State . AllocateReg ( ArgVRs ) ; } } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM2s ) ; } else if ( RC == & <STR_LIT> ) { Reg = State . AllocateReg ( ArgVRM4s ) ; } else if ( RC == & <STR_LIT> ) {

Reg = State . AllocateReg ( ArgVRM8s ) ;


<s> return isUImm < <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> return __builtin_mve_vmovntq_uv8hi ( __a , __b ) ;


<s> if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt ( C , VT ) ; return <NUM_LIT> ;


<s> case tcGPRRegClassID : case tGPRRegClassID : case tGPREvenRegClassID : case tGPROddRegClassID : case tGPR_and_tGPREvenRegClassID : case tGPR_and_tGPROddRegClassID : case tGPREven_and_tcGPRRegClassID : case tGPREven_and_tGPR_and_tcGPRRegClassID : case tGPROdd_and_tcGPRRegClassID : return getRegBank ( <STR_LIT> ) ; case HPRRegClassID :


<s> CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; } Cond [ <NUM_LIT> ] . setImm ( CC ) ; return false ;


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isImm ( ) ) O << Op . getImm ( ) ;


<s> if ( ! LastInstInFunction ) { std :: pair < Iter , bool > Res = getNextMachineInstr ( std :: next ( I ) , & * FI ) ; LastInstInFunction |= Res . second ; IInSlot = Res . first ; } if ( LastInstInFunction || ! SafeInSlot ( * IInSlot , * I ) ) { MachineBasicBlock :: instr_iterator Iit = I -> getIterator ( ) ; if ( std :: next ( Iit ) == FI -> end ( ) || std :: next ( Iit ) -> getOpcode ( ) != <STR_LIT> ) { Changed = true ; MIBundleBuilder ( & * I ) . append ( BuildMI ( * MFp , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ) ; NumInsertedNops ++ ; } } } }


<s> unsigned Width = ShrunkMask . getActiveBits ( ) ; if ( Width == <NUM_LIT> ) return false ; Width = PowerOf2Ceil ( std :: max ( Width , <NUM_LIT> ) ) ; Width = std :: min ( Width , Size ) ; APInt ZeroExtendMask = APInt :: getLowBitsSet ( Size , Width ) ; if ( ZeroExtendMask == Mask ) return true ; if ( ! ZeroExtendMask . isSubsetOf ( Mask | ~ Demanded ) ) return false ; SDLoc DL ( Op ) ; SDValue NewC = TLO . DAG . getConstant ( ZeroExtendMask , DL , VT ) ; SDValue NewOp = TLO . DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , NewC ) ;


<s> convert_op ( & XEXP ( src , <NUM_LIT> ) , insn ) ; PUT_MODE ( src , V2DImode ) ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : convert_op ( & XEXP ( src , <NUM_LIT> ) , insn ) ; convert_op ( & XEXP ( src , <NUM_LIT> ) , insn ) ; PUT_MODE ( src , V2DImode ) ; break ; case NEG : src = XEXP ( src , <NUM_LIT> ) ; convert_op ( & src , insn ) ; subreg = gen_reg_rtx ( V2DImode ) ; emit_insn_before ( gen_move_insn ( subreg , CONST0_RTX ( V2DImode ) ) , insn ) ; src = gen_rtx_MINUS ( V2DImode , subreg , src ) ; break ; case NOT : src = XEXP ( src , <NUM_LIT> ) ; convert_op ( & src , insn ) ; subreg = gen_reg_rtx ( V2DImode ) ; emit_insn_before ( gen_move_insn ( subreg , CONSTM1_RTX ( V2DImode ) ) , insn ) ; src = gen_rtx_XOR ( V2DImode , src , subreg ) ; break ; case MEM : if ( ! REG_P ( dst ) ) convert_op ( & src , insn ) ; break ; case REG : if ( ! MEM_P ( dst ) ) convert_op ( & src , insn ) ; break ; case SUBREG : gcc_assert ( GET_MODE ( src ) == V2DImode ) ; break ; case COMPARE : src = SUBREG_REG ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ) ; gcc_assert ( ( REG_P ( src ) && GET_MODE ( src ) == DImode ) || ( SUBREG_P ( src ) && GET_MODE ( src ) == V2DImode ) ) ;

if ( REG_P ( src ) ) subreg = gen_rtx_SUBREG ( V2DImode , src , <NUM_LIT> ) ;


<s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . set ( <STR_LIT> ) ;


<s> FQ -> copyFastMathFlags ( Builder . getFastMathFlags ( ) ) ; Value * FQNeg = Builder . CreateFNeg ( FQ ) ; Value * FR = Builder . CreateIntrinsic ( <STR_LIT> , { FQNeg -> getType ( ) } , { FQNeg , FB , FA } , FQ ) ; Value * IQ = IsSigned ? Builder . CreateFPTo<ISA_LIT> ( FQ , I32Ty ) : Builder . CreateFPToUI ( FQ , I32Ty ) ; FR = Builder . CreateUnaryIntrinsic ( <STR_LIT> , FR , FQ ) ; FB = Builder . CreateUnaryIntrinsic ( <STR_LIT> , FB , FQ ) ; Value * CV = Builder . CreateFCmpOGE ( FR , FB ) ; JQ = Builder . CreateSelect ( CV , JQ , Builder . getInt32 ( <NUM_LIT> ) ) ; Value * Div = Builder . CreateAdd ( IQ , JQ ) ; Value * Res = Div ; if ( ! IsDiv ) { Value * Rem = Builder . CreateMul ( Div , Den ) ; Res = Builder . CreateSub ( Num , Rem ) ; } if ( DivBits != <NUM_LIT> && DivBits < <NUM_LIT> ) { if ( IsSigned ) { int InRegBits = <NUM_LIT> - DivBits ; Res = Builder . CreateShl ( Res , InRegBits ) ; Res = Builder . CreateAShr ( Res , InRegBits ) ; } else {

ConstantInt * TruncMask = Builder . getInt32 ( ( UINT64_C ( <NUM_LIT> ) << DivBits ) - <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>FastISel :: FastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; }


<s> int did = <NUM_LIT> ; rtx temp_reg = NULL ; if ( rl78_far_p ( operands [ <NUM_LIT> ] ) ) { temp_reg = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; did = <NUM_LIT> ; }


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> if ( ReportErrors ) Context . reportError ( Loc , Msg ) ;


<s> O << RegName ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = getSymbol ( GV ) ; } } else { SymToPrint = getSymbol ( GV ) ; } O << * SymToPrint ; printOffset ( MO . getOffset ( ) , O ) ; return ;


<s> while ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> << shift ) & power ) == <NUM_LIT> ) { gcc_assert ( shift <= <NUM_LIT> ) ; shift ++ ; } return shift ;


<s> r = gen_rtx_ZERO_EXTRACT ( HImode , addr , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; r = gen_rtx_CONST ( HImode , r ) ; }

else r = rl78_subreg ( HImode , addr , SImode , <NUM_LIT> ) ;


<s> __arm_uqrshll_sat48 ( uint64_t value , int32_t shift ) { return __builtin_mve_uqrshll_sat48_di ( value , shift ) ;


<s> auto & InfoCache = static_cast < <ISA_LIT>InformationCache & > ( A . getInfoCache ( ) ) ; unsigned MinGroupSize , MaxGroupSize ; std :: tie ( MinGroupSize , MaxGroupSize ) = InfoCache . getFlatWorkGroupSizes ( * F ) ;

intersectKnown ( ConstantRange ( APInt ( <NUM_LIT> , MinGroupSize ) , APInt ( <NUM_LIT> , MaxGroupSize + <NUM_LIT> ) ) ) ;


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>TargetMachine & TM = ( const <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + <NUM_LIT> ; Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; assert ( isUInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> unsigned getOccupancyWithLocalMemSize ( const MachineFunction & MF ) const {

const auto * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> OutStreamer . EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: Create ( PICBase , OutContext ) , OutContext ) ; OutStreamer . EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget . isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , <NUM_LIT> ) ;

MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ;


<s> if ( MBBI == MBB . begin ( ) ) return false ; MachineBasicBlock :: iterator Prev = std :: prev ( MBBI ) ; if ( ! Prev -> isCall ( ) || ! Prev -> getOperand ( <NUM_LIT> ) . isRegMask ( ) ) return false ; unsigned Regs [ <NUM_LIT> ] ; unsigned FoundRegs = <NUM_LIT> ; auto RegMask = Prev -> getOperand ( <NUM_LIT> ) ; auto & RegClass = Is64Bit ? <STR_LIT> : <STR_LIT> ; for ( auto Candidate : RegClass ) { if ( ! RegMask . clobbersPhysReg ( Candidate ) ) continue ; bool IsDef = false ; for ( const MachineOperand & MO : Prev -> implicit_operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == Candidate ) { IsDef = true ; break ; } } if ( IsDef ) continue ; Regs [ FoundRegs ++ ] = Candidate ; if ( FoundRegs == ( unsigned ) NumPops ) break ; } if ( FoundRegs == <NUM_LIT> ) return false ;

while ( FoundRegs < ( unsigned ) NumPops ) Regs [ FoundRegs ++ ] = Regs [ <NUM_LIT> ] ;


<s> if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isVector ( ) || TLI . isTypeLegal ( ResVT ) ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isSimple ( ) || ! SrcVT . isSimple ( ) ) return SDValue ( ) ; if ( SrcVT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; unsigned SrcEltSize = SrcVT . getScalarSizeInBits ( ) ; unsigned ElementCount = SrcVT . getVectorNumElements ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , ElementCount ) ; SDLoc DL ( N ) ; Src = DAG . getNode ( N -> getOpcode ( ) , DL , SrcVT , Src ) ; EVT LoVT , HiVT ; SDValue Lo , Hi ; unsigned NumElements = ResVT . getVectorNumElements ( ) ; assert ( ! ( NumElements & <NUM_LIT> ) && <STR_LIT> ) ; LoVT = HiVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ResVT . getVectorElementType ( ) , NumElements / <NUM_LIT> ) ;

EVT InNVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT . getVectorElementType ( ) , LoVT . getVectorNumElements ( ) ) ;


<s> case RTLIB :: SINTTOFP_I32_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: FPTOUINT_F32_I8 : Basename = <STR_LIT> ; break ; case RTLIB :: FPTOUINT_F32_I16 : Basename = <STR_LIT> ; break ; case RTLIB :: FPTOUINT_F32_I32 : Basename = <STR_LIT> ; break ; case RTLIB :: UINTTOFP_I32_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: ADD_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: SUB_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: MUL_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: DIV_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: O_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: UO_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: OLE_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: OGE_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: OLT_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: OGT_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: OEQ_F32 : Basename = <STR_LIT> ; break ; case RTLIB :: UNE_F32 : Basename = <STR_LIT> ; break ; } std :: string prefix = PAN :: getTagName ( PAN :: PREFIX_SYMBOL ) ; std :: string tagname = PAN :: getTagName ( PAN :: LIBCALL ) ; std :: string Fullname = prefix + tagname + Basename ;


<s> n = riscv_flatten_aggregate_field ( TREE_TYPE ( f ) , fields , n , pos , ignore_zero_width_bit_field_p ) ; } if ( n < <NUM_LIT> ) return - <NUM_LIT> ; } return n ; case ARRAY_TYPE : { HOST_WIDE_INT n_elts ; riscv_aggregate_field subfields [ <NUM_LIT> ] ; tree index = TYPE_DOMAIN ( type ) ; tree elt_size = TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) ; int n_subfields = riscv_flatten_aggregate_field ( TREE_TYPE ( type ) , subfields , <NUM_LIT> , offset , ignore_zero_width_bit_field_p ) ; if ( n_subfields <= <NUM_LIT> || ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || ! tree_fits_uhwi_p ( elt_size ) ) return - <NUM_LIT> ; n_elts = <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ; gcc_assert ( n_elts >= <NUM_LIT> ) ; for ( HOST_WIDE_INT i = <NUM_LIT> ; i < n_elts ; i ++ ) for ( int j = <NUM_LIT> ; j < n_subfields ; j ++ ) { if ( n >= <NUM_LIT> ) return - <NUM_LIT> ; fields [ n ] = subfields [ j ] ; fields [ n ++ ] . offset += i * tree_to_uhwi ( elt_size ) ; } return n ; } case COMPLEX_TYPE : { if ( n != <NUM_LIT> ) return - <NUM_LIT> ; HOST_WIDE_INT elt_size = GET_MODE_SIZE ( TYPE_MODE ( TREE_TYPE ( type ) ) ) ; if ( elt_size <= UNITS_PER_FP_ARG ) { fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ; fields [ <NUM_LIT> ] . offset = offset ; fields [ <NUM_LIT> ] . type = TREE_TYPE ( type ) ;

fields [ <NUM_LIT> ] . offset = offset + elt_size ;


<s> unsigned idx ( iterator It ) const {


<s> bool <ISA_LIT>TargetLowering :: hasBitPreservingFPLogic ( EVT VT ) const { if ( ! Subtarget . hasVSX ( ) ) return false ; if ( Subtarget . hasP9Vector ( ) && VT == <STR_LIT> ) return true ; return VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ;


<s> Stride = Builder . getInt64 ( <NUM_LIT> ) ; } ; if ( AMXCast -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { if ( AMXCast -> use_empty ( ) ) { AMXCast -> eraseFromParent ( ) ; return true ; } Use & U = * ( AMXCast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( AMXCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Builder . CreateSExt ( Col , Builder . getInt64Ty ( ) ) } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; AMXCast -> replaceAllUsesWith ( NewInst ) ; AMXCast -> eraseFromParent ( ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( N -> getOperand ( i + <NUM_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( ParamVal , DL , <STR_LIT> ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( OffsetVal , DL , <STR_LIT> ) ) ; Ops . push_back ( Chain ) ; Ops . push_back ( Flag ) ; Optional < unsigned > Opcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : switch ( NumElts ) { default : return false ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : Opcode = pickOpcodeForVT ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ; break ; } if ( ! Opcode ) return false ; break ; case <STR_LIT> : { Opcode = <STR_LIT> ; SDValue CvtNone = CurDAG -> getTargetConstant ( <STR_LIT> :: NONE , DL , <STR_LIT> ) ; SDNode * Cvt = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , CvtNone ) ; Ops [ <NUM_LIT> ] = SDValue ( Cvt , <NUM_LIT> ) ; break ; } case <STR_LIT> : { Opcode = <STR_LIT> ; SDValue CvtNone = CurDAG -> getTargetConstant ( <STR_LIT> :: NONE , DL , <STR_LIT> ) ; SDNode * Cvt = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ <NUM_LIT> ] , CvtNone ) ;


<s> } gcc_assert ( MEM_VOLATILE_P ( mem ) ) ; old_reg = gen_reg_rtx ( DImode ) ; cmp_reg = gen_reg_rtx ( DImode ) ; label = gen_label_rtx ( ) ; if ( mode != DImode ) { val = simplify_gen_subreg ( DImode , val , mode , <NUM_LIT> ) ; emit_insn ( gen_extend_insn ( cmp_reg , mem , DImode , mode , <NUM_LIT> ) ) ; } else emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; ar_ccv = gen_rtx_REG ( DImode , AR_CCV_REGNUM ) ; emit_move_insn ( old_reg , cmp_reg ) ; emit_move_insn ( ar_ccv , cmp_reg ) ; if ( old_dst ) emit_move_insn ( old_dst , gen_lowpart ( mode , cmp_reg ) ) ; new_reg = cmp_reg ; if ( code == NOT ) { new_reg = expand_simple_unop ( DImode , NOT , new_reg , NULL_RTX , true ) ; code = AND ; } new_reg = expand_simple_binop ( DImode , code , new_reg , val , NULL_RTX , true , OPTAB_DIRECT ) ; if ( mode != DImode ) new_reg = gen_lowpart ( mode , new_reg ) ;


<s> Value * <ISA_LIT>IREmitter :: visitTC_RETURN ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { Ops . push_back ( Callee ) ;

<ISA_LIT>TargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ;


return Kind == k_Register && Reg . Kind == RegKind :: NeonVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> if ( Reg == - <NUM_LIT> ) return true ;

Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( Reg , RegKind :: Scalar , S , getLoc ( ) , getContext ( ) ) ) ;


<s> const bool srcGPR = <STR_LIT> . contains ( SrcReg ) ; if ( destGPR && srcGPR ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; addDefaultPred ( MIB ) ; return ; }


<s> rtx got_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; start_sequence ( ) ; emit_move_insn ( got_rtx , s390_got_symbol ( ) ) ; insns = get_insns ( ) ; end_sequence ( ) ;


<s> ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; SDNode * Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ) ; SDNode * Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getConstant ( Imm >> <NUM_LIT> , DL , <STR_LIT> ) ) ; const SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Lo , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Hi , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { N = glueCopyToM0 ( N ) ; break ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; bool Signed = Opc == <STR_LIT> ; uint32_t OffsetVal = Offset -> getZExtValue ( ) ; uint32_t WidthVal = Width -> getZExtValue ( ) ; ReplaceNode ( N , getS_BFE ( Signed ? <STR_LIT> : <STR_LIT> , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) , OffsetVal , WidthVal ) ) ; return ; } case <STR_LIT> : { SelectDIV_SCALE ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { SelectMAD_64_32 ( N ) ; return ; } case <STR_LIT> : { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; N = Lowering . legalizeTargetIndependentNode ( N , * CurDAG ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SelectS_BFE ( N ) ; return ; case <STR_LIT> : SelectBRCOND ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : SelectFMAD_FMA ( N ) ;


<s> rmap_ty :: iterator iter = RegisterMap . find ( Name . str ( ) ) ; if ( iter != RegisterMap . end ( ) ) return iter -> second ;


<s> case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( SSECC == <NUM_LIT> ) { if ( SetCCOpcode == <STR_LIT> ) { SDValue UNORD , EQ ; UNORD = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; EQ = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , UNORD , EQ ) ; } else if ( SetCCOpcode == <STR_LIT> ) { SDValue ORD , NEQ ; ORD = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; NEQ = DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ORD , NEQ ) ; } llvm_unreachable ( <STR_LIT> ) ; } return DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , <STR_LIT> ) ) ; } if ( ! isFP && VT . getSizeInBits ( ) == <NUM_LIT> ) return Lower256IntVSETCC ( Op , DAG ) ; unsigned Opc = <NUM_LIT> , EQOpc = <NUM_LIT> , GTOpc = <NUM_LIT> ; bool Swap = false , Invert = false , FlipSigns = false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ; case <STR_LIT> : EQOpc = <STR_LIT> ; GTOpc = <STR_LIT> ; break ;


<s> <ISA_LIT>AsmBackendDarwin ( const Target & T , StringRef TT , MachO :: CPUSubType<ISA_LIT> st ) : <ISA_LIT>AsmBackend ( T , TT , true ) , Subtype ( st ) {


<s> if ( Src . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . bitsGE ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) ) ; if ( Subtarget . hasStdExtZbb ( ) && Subtarget . is64Bit ( ) && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && VT == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) == <STR_LIT> && DAG . ComputeNumSignBits ( Src . getOperand ( <NUM_LIT> ) ) > <NUM_LIT> ) { SDLoc DL ( N ) ; SDValue Freeze = DAG . getFreeze ( Src . getOperand ( <NUM_LIT> ) ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Freeze ) ; Neg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Neg , DAG . getValueType ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Freeze , Neg ) ; } return SDValue ( ) ;


<s> case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : return <NUM_LIT> ; case FK_Data_4 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeImm5S ( SDValue N , unsigned Scale , SDValue & Base , SDValue & OffImm ) { if ( Scale == <NUM_LIT> ) { SDValue TmpBase , TmpOffImm ; if ( SelectThumbAddrModeSP ( N , TmpBase , TmpOffImm ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) {


<s> return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } return false ;


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { auto Result = tryParseRegister ( RegNo , StartLoc , EndLoc ) ;


<s> } if ( TARGET_ISA_V3 ) { } if ( TARGET_ISA_V3M ) { target_flags |= MASK_REDUCED_REGS ; target_flags &= ~ MASK_PERF_EXT ; } if ( TARGET_REDUCED_REGS ) { int r ;

for ( r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) fixed_regs [ r ] = call_used_regs [ r ] = <NUM_LIT> ;


<s> return __builtin_neon_vld1v4bf ( __ptr ) ;


<s> const char * Pfx = <STR_LIT> ; switch ( FKind ) { case NATIVE : Pfx = <STR_LIT> ; break ; case HALF : Pfx = <STR_LIT> ; break ; default : break ; } if ( ! Name . empty ( ) ) {


<s> op [ nopnds ] = expand_normal ( arg ) ; if ( ! insn_op -> predicate ( op [ nopnds ] , insn_op -> mode ) ) { if ( ! strcmp ( insn_op -> constraint , <STR_LIT> ) ) { int arg_num = nonvoid ? nopnds : nopnds + <NUM_LIT> ; if ( ! CONST_INT_P ( op [ nopnds ] ) ) error ( <STR_LIT> , arg_num ) ; else error ( <STR_LIT> <STR_LIT> , arg_num ) ; return const0_rtx ;


<s> return __builtin_mve_vminvq_uv16qi ( __a , __b ) ;


<s> int Cost = ( ( Val -> getScalarSizeInBits ( ) == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( Index == <NUM_LIT> && Val -> isIntOrIntVectorTy ( ) ) Cost += <NUM_LIT> ; return Cost ; } return BaseT :: getVectorInstrCost ( Opcode , Val , Index ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const unsigned Shift = countTrailingZeros < unsigned > ( Mask ) ; auto ShiftAmt = B . buildConstant ( S32 , Shift ) ; auto LShr = B . buildLShr ( S32 , LiveIn , ShiftAmt ) ; B . buildAnd ( DstReg , LShr , B . buildConstant ( S32 , Mask >> Shift ) ) ; } else B . buildCopy ( DstReg , LiveIn ) ;


<s> xc2pu ( unsigned i , unsigned j , unsigned k ) : tripleChange ( false , false , true , i , j , k ) {


<s> SmallVector < unsigned , <NUM_LIT> > StBases ; unsigned Loc = <NUM_LIT> ; MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; MachineBasicBlock :: iterator E = MBB -> end ( ) ; while ( MBBI != E ) { for ( ; MBBI != E ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isCall ( ) || MI -> isTerminator ( ) ) { ++ MBBI ; break ; } if ( ! MI -> isDebugValue ( ) ) MI2LocMap [ MI ] = ++ Loc ; if ( ! isMemoryOp ( * MI ) ) continue ; unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) != <STR_LIT> ) continue ; int Opc = MI -> getOpcode ( ) ; bool isLd = isLoadSingle ( Opc ) ; unsigned Base = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = getMemoryOpOffset ( MI ) ; bool StopHere = false ; if ( isLd ) { DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > :: iterator BI = Base2LdsMap . find ( Base ) ; if ( BI != Base2LdsMap . end ( ) ) { for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( MI ) ; } else { Base2LdsMap [ Base ] . push_back ( MI ) ; LdBases . push_back ( Base ) ; } } else { DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> > > :: iterator BI = Base2StsMap . find ( Base ) ; if ( BI != Base2StsMap . end ( ) ) { for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( BI -> second [ i ] ) ) { StopHere = true ;


<s> AMDGPUTargetMachine :: AMDGPUTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , TargetOptions Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OptLevel ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OptLevel ) , Subtarget ( TT , CPU , FS ) , Layout ( computeDataLayout ( Subtarget ) ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , <NUM_LIT> * <NUM_LIT> , <NUM_LIT> ) , IntrinsicInfo ( this ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) { if ( Subtarget . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { TLInfo . reset ( new R600TargetLowering ( * this ) ) ; } else {

TLInfo . reset ( new <ISA_LIT>TargetLowering ( * this ) ) ;


<s> void <ISA_LIT>FrameLowering :: BuildCFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , const MCCFIInstruction & CFIInst ) const { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFIIndex = MF . addFrameInst ( CFIInst ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> int CurOpcode = HII -> getDotCurOp ( MI ) ; MI -> setDesc ( HII -> get ( CurOpcode ) ) ; return true ;


<s> if ( Op1 . isUndef ( ) ) return nullptr ; RSR = getRegSubRegPair ( Op1 ) ; DefInst = MRI . getVRegDef ( RSR . Reg ) ; } break ; } default : if ( followSubRegDef ( * MI , RSR ) ) { if ( ! RSR . Reg ) return nullptr ; DefInst = MRI . getVRegDef ( RSR . Reg ) ; } }


<s> bool <ISA_LIT>AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCStreamer & Out ) { MCInst Inst ; SMLoc ErrorLoc ; unsigned ErrorInfo ; switch ( MatchInstructionImpl ( Operands , Inst , ErrorInfo ) ) { default : break ; case Match_Success : Out . EmitInstruction ( Inst ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> temp . val [ <NUM_LIT> ] = vcombine_f32 ( val . val [ <NUM_LIT> ] , vcreate_f32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_f32 ( val . val [ <NUM_LIT> ] , vcreate_f32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv4sf ( __o , ( float32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv4sf ( __o , ( float32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; if ( MO1 . isExpr ( ) ) O << * MO1 . getExpr ( ) ; else if ( MO1 . isImm ( ) ) { O << markup ( <STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( MO1 . getImm ( ) ) << markup ( <STR_LIT> , <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ;


<s> if ( Opcode == <STR_LIT> ) { CanPushNegate = true ; return true ; } if ( Depth > <NUM_LIT> ) return false ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { SDValue O0 = Val -> getOperand ( <NUM_LIT> ) ; SDValue O1 = Val -> getOperand ( <NUM_LIT> ) ; bool CanPushNegateL ; if ( ! isConjunctionDisjunctionTree ( O0 , CanPushNegateL , Depth + <NUM_LIT> ) ) return false ; bool CanPushNegateR ; if ( ! isConjunctionDisjunctionTree ( O1 , CanPushNegateR , Depth + <NUM_LIT> ) ) return false ; CanPushNegate = ( Opcode == <STR_LIT> ) && CanPushNegateL && CanPushNegateR ; return true ;


<s> t = __ev_mwhsmi ( a , b ) ; return __ev_addssiaaw ( t ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> VGPRBlocks ( <NUM_LIT> ) , SGPRBlocks ( <NUM_LIT> ) , Priority ( <NUM_LIT> ) , FloatMode ( <NUM_LIT> ) , Priv ( <NUM_LIT> ) , DX10Clamp ( <NUM_LIT> ) , DebugMode ( <NUM_LIT> ) , IEEEMode ( <NUM_LIT> ) , ScratchSize ( <NUM_LIT> ) , ComputePGMRSrc1 ( <NUM_LIT> ) , LDSBlocks ( <NUM_LIT> ) , ScratchBlocks ( <NUM_LIT> ) , ComputePGMRSrc2 ( <NUM_LIT> ) , NumVGPR ( <NUM_LIT> ) , NumSGPR ( <NUM_LIT> ) , FlatUsed ( false ) , VCCUsed ( false ) , CodeLen ( <NUM_LIT> ) {


<s> return <ISA_LIT>Operand :: CreateImm ( <NUM_LIT> , SMLoc ( ) , <ISA_LIT>Operand :: ImmTySLC ) ;


<s> unsigned Alignment = LN -> getAlignment ( ) ; if ( Alignment >= MemVT . getStoreSize ( ) ) return Op ; EVT ScalarVT = Op . getValueType ( ) . getScalarType ( ) , ScalarMemVT = MemVT . getScalarType ( ) ; unsigned Stride = ScalarMemVT . getStoreSize ( ) ; SDValue Vals [ <NUM_LIT> ] , LoadChains [ <NUM_LIT> ] ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) { SDValue Load ; if ( ScalarVT != ScalarMemVT ) Load = DAG . getExtLoad ( LN -> getExtensionType ( ) , dl , ScalarVT , LoadChain , BasePtr , LN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , ScalarMemVT , LN -> isVolatile ( ) , LN -> isNonTemporal ( ) , LN -> isInvariant ( ) , MinAlign ( Alignment , Idx * Stride ) , LN -> getAAInfo ( ) ) ; else Load = DAG . getLoad ( ScalarVT , dl , LoadChain , BasePtr , LN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , LN -> isVolatile ( ) , LN -> isNonTemporal ( ) , LN -> isInvariant ( ) , MinAlign ( Alignment , Idx * Stride ) , LN -> getAAInfo ( ) ) ; if ( Idx == <NUM_LIT> && LN -> isIndexed ( ) ) { assert ( LN -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; Load = DAG . getIndexedLoad ( Load , dl , BasePtr , LN -> getOffset ( ) , LN -> getAddressingMode ( ) ) ; } Vals [ Idx ] = Load ;

LoadChains [ Idx ] = Load . getValue ( <NUM_LIT> ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> && ! MayFoldIntoZeroExtend ( Op ) && ! ( Subtarget . hasSSE41 ( ) && MayFoldIntoStore ( Op ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal / <NUM_LIT> ; if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( WordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ;

int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ;


<s> static Target The<ISA_LIT>leTarget ; return The<ISA_LIT>leTarget ;


<s> bool isDstIdx16 ( ) const { return isMem16 ( ) && isDstIdx ( ) ;


<s> virtual const TargetRegisterClass * getCFGStructurizerRegClass ( MVT VT ) const { assert ( ! <STR_LIT> ) ; return NULL ;


<s> if ( FS == DefM . end ( ) || FS -> second . empty ( ) ) return ; Copies . push_back ( SA . Id ) ; RDefMap [ SrcR ] [ SA . Id ] = FS -> second . top ( ) -> Id ; RDefMap [ DstR ] ;


<s> case TargetOpcode :: G_FDIV : return legalizeFDIV ( MI , MRI , B ) ; case TargetOpcode :: G_UDIV : case TargetOpcode :: G_UREM : return legalizeUDIV_UREM ( MI , MRI , B ) ; case TargetOpcode :: G_SDIV : case TargetOpcode :: G_SREM : return legalizeSDIV_SREM ( MI , MRI , B ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpXChg ( MI , MRI , B ) ; case TargetOpcode :: G_FLOG : return legalizeFlog ( MI , B , numbers :: ln2f ) ; case TargetOpcode :: G_FLOG10 : return legalizeFlog ( MI , B , numbers :: ln2f / numbers :: ln10f ) ; case TargetOpcode :: G_FEXP : return legalizeFExp ( MI , B ) ; case TargetOpcode :: G_FPOW : return legalizeFPow ( MI , B ) ; case TargetOpcode :: G_FFLOOR : return legalizeFFloor ( MI , MRI , B ) ; case TargetOpcode :: G_BUILD_VECTOR : return legalizeBuildVector ( MI , MRI , B ) ;


<s> unshifted_mask_reg = force_reg ( SImode , unshifted_mask ) ; mask = mips_force_binary ( SImode , ASHIFT , unshifted_mask_reg , shiftsi ) ; inverted_mask = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , inverted_mask , gen_rtx_NOT ( SImode , mask ) ) ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , true ) ; oldval = force_reg ( SImode , oldval ) ; oldval = mips_force_binary ( SImode , ASHIFT , oldval , shiftsi ) ; } if ( newval && newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , true ) ; newval = force_reg ( SImode , newval ) ; newval = mips_force_binary ( SImode , ASHIFT , newval , shiftsi ) ; } if ( result ) res = gen_reg_rtx ( SImode ) ; if ( newval ) si_op = generator . fn_6 ( res , memsi , mask , inverted_mask , oldval , newval ) ;

else if ( result ) si_op = generator . fn_5 ( res , memsi , mask , inverted_mask , oldval ) ;


<s> assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; if ( StackAdj ) { StackAdj += <ISA_LIT>FL -> mergeSPUpdates ( MBB , MBBI , true ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , StackAdj , true ) ; } bool IsWin64 = STI -> isTargetWin64 ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) MIB . addOperand ( MBBI -> getOperand ( i ) ) ; } else if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ;


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . getReg ( ) ) { unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; O << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs ;


<s> O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; default :


<s> SDValue Est = DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; DCI . AddToWorklist ( Est . getNode ( ) ) ; SDValue HalfArg = DAG . getNode ( <STR_LIT> , dl , VT , FPThreeHalves , Op ) ; DCI . AddToWorklist ( HalfArg . getNode ( ) ) ; HalfArg = DAG . getNode ( <STR_LIT> , dl , VT , HalfArg , Op ) ; DCI . AddToWorklist ( HalfArg . getNode ( ) ) ; for ( int i = <NUM_LIT> ; i < Iterations ; ++ i ) { SDValue NewEst = DAG . getNode ( <STR_LIT> , dl , VT , Est , Est ) ; DCI . AddToWorklist ( NewEst . getNode ( ) ) ; NewEst = DAG . getNode ( <STR_LIT> , dl , VT , HalfArg , NewEst ) ; DCI . AddToWorklist ( NewEst . getNode ( ) ) ; NewEst = DAG . getNode ( <STR_LIT> , dl , VT , FPThreeHalves , NewEst ) ; DCI . AddToWorklist ( NewEst . getNode ( ) ) ; Est = DAG . getNode ( <STR_LIT> , dl , VT , Est , NewEst ) ; DCI . AddToWorklist ( Est . getNode ( ) ) ; } return Est ; }


<s> bool enableSubRegLiveness ( ) const override { return true ;


<s> Cond . push_back ( MachineOperand :: CreateImm ( Opc ) ) ; for ( int i = <NUM_LIT> ; i < NumOp - <NUM_LIT> ; i ++ ) Cond . push_back ( Inst -> getOperand ( i ) ) ;


<s> LoadMI = MRI . getUniqueVRegDef ( LoadReg ) ; assert ( LoadMI && <STR_LIT> ) ; } if ( ! ( IsZExt && isZExtLoad ( LoadMI ) ) && ! ( ! IsZExt && isSExtLoad ( LoadMI ) ) ) return false ; if ( RetVT != <STR_LIT> || SrcVT > <STR_LIT> ) { updateValueMap ( I , Reg ) ; return true ; } if ( IsZExt ) { Register Reg64 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Reg64 ) . addImm ( <NUM_LIT> ) . addReg ( Reg , getKillRegState ( true ) ) . addImm ( <STR_LIT> ) ; Reg = Reg64 ; } else {

assert ( ( MI -> getOpcode ( ) == TargetOpcode :: COPY && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) && <STR_LIT> ) ;


<s> const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; bool Ok = TII -> copyRegToReg ( FirstMBB , MBBI , GlobalBaseReg , <STR_LIT> , & <STR_LIT> , & <STR_LIT> ) ;


<s> long __lexf2 ( long double x1 , long double x2 ) {

return __cmpdf2 ( ( double ) x1 , ( double ) x2 ) ;


<s> MachineInstrBuilder copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; MachineOperand which = Instr -> getOperand ( <NUM_LIT> + i ) ; assert ( which . isImm ( ) && <STR_LIT> ) ; int src = which . getImm ( ) ; int elem = src % numcopies ; if ( which . getImm ( ) < numcopies ) copy . addReg ( src1 [ elem ] ) ; else copy . addReg ( src2 [ elem ] ) ;


<s> std :: unique_ptr < MCObjectWriter > <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , Is64Bit ) ;


<s> if ( ! S . isValid ( ) ) { LV . set ( I . PhysReg ) ; continue ; } do { LaneBitmask M = TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ; if ( ( M & I . LaneMask ) . any ( ) ) LV . set ( S . getSubReg ( ) ) ; ++ S ; } while ( S . isValid ( ) ) ; } } ; BitVector LiveIn ( TRI . getNumRegs ( ) ) , Live ( TRI . getNumRegs ( ) ) ; CopyLiveIns ( B , LiveIn ) ; for ( auto SI : B -> successors ( ) ) CopyLiveIns ( SI , Live ) ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> isDebugValue ( ) ) continue ;


<s> SmallVector < MachineOperand * , <NUM_LIT> > UsesToProcess ; for ( auto & Use : MRI -> use_nodbg_operands ( Dst . getReg ( ) ) ) UsesToProcess . push_back ( & Use ) ; for ( auto U : UsesToProcess ) { MachineInstr * UseMI = U -> getParent ( ) ; foldOperand ( OpToFold , UseMI , UseMI -> getOperandNo ( U ) , FoldList , CopiesToReplace ) ; } } if ( CopiesToReplace . empty ( ) && FoldList . empty ( ) ) return Changed ; MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; for ( MachineInstr * Copy : CopiesToReplace ) Copy -> addImplicitDefUseOperands ( * MF ) ; for ( FoldCandidate & Fold : FoldList ) { assert ( ! Fold . isReg ( ) || Fold . OpToFold ) ; if ( Fold . isReg ( ) && Fold . OpToFold -> getReg ( ) . isVirtual ( ) ) { Register Reg = Fold . OpToFold -> getReg ( ) ; MachineInstr * DefMI = Fold . OpToFold -> getParent ( ) ; if ( DefMI -> readsRegister ( <STR_LIT> , TRI ) && execMayBeModifiedBeforeUse ( * MRI , Reg , * DefMI , * Fold . UseMI ) ) continue ;


<s> tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , <NUM_LIT> ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , <NUM_LIT> ) ; tocrel_offset = XEXP ( op , <NUM_LIT> ) ;


<s> ( ( <ISA_LIT>Operand & ) * Operands [ I - <NUM_LIT> ] ) . addRegOperands ( Inst , <NUM_LIT> ) ; } OptionalImmIndexMap OptionalIdx ; for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( Op . isReg ( ) ) { Op . addRegOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImmModifier ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else if ( ! Op . isToken ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } } bool IsGFX10Plus = isGFX10Plus ( ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDMask ) ; if ( IsGFX10Plus ) addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDim , - <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyUNorm ) ; if ( IsGFX10Plus ) addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDLC ) ;

addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyGLC ) ;


<s> SDLoc DL ( Op ) ; unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; MVT VT = Op . getSimpleValueType ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & DAG . getTarget ( ) ) ; TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( <STR_LIT> ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ; SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , <NUM_LIT> ) ; if ( isPositionIndependent ( ) ) { Addr = makeHiLoPair ( Addr , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_HI32 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTOFF_LO32 , DAG ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , DL , VT ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , GlobalBase , Addr ) ;


<s> const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - Imm ) . isPowerOf2 ( ) || ( - <NUM_LIT> - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ;

if ( ! Imm . isSignedIntN ( <NUM_LIT> ) && Imm . countTrailingZeros ( ) < <NUM_LIT> ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> assert ( Kind == Register && <STR_LIT> ) ; return Reg . RegNum ;


<s> MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = ( <ISA_LIT>TargetLowering * ) getTargetLowering ( ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) {

if ( N -> getOpcode ( ) == <STR_LIT> ) continue ;


<s> Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; } else { assert ( model == TLSModel :: LocalExec ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; }

return DAG . getNode ( <STR_LIT> , dl , PtrVT , ThreadPointer , Offset ) ;


<s> static bool ArgsAreStructReturn ( SDValue Op ) { unsigned NumArgs = Op . getNode ( ) -> getNumValues ( ) - <NUM_LIT> ; if ( ! NumArgs ) return false ;

return cast < ARG_FLAGSSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getArgFlags ( ) . isSRet ( ) ;


<s> return __builtin_mve_vminnmaq_fv8hf ( __a , __b ) ;


<s> const MCRegisterInfo * getRegInfo ( ) const {


<s> void AMDGPUInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { assert ( ! <STR_LIT> ) ;


<s> else p_mem = ( rtx * ) <NUM_LIT> ; if ( p_mem ) { rtx addr = XEXP ( * p_mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == REG && REGNO ( addr ) == ( unsigned ) regno ) * p_mem = change_address ( * p_mem , VOIDmode , * p_ep ) ; else if ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( addr , <NUM_LIT> ) ) == ( unsigned ) regno && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT && ( ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ) < ep_memory_offset ( GET_MODE ( * p_mem ) , unsignedp ) ) && ( ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ) >= <NUM_LIT> ) ) * p_mem = change_address ( * p_mem , VOIDmode , gen_rtx_PLUS ( Pmode , * p_ep , XEXP ( addr , <NUM_LIT> ) ) ) ; } } } } insn = prev_nonnote_insn ( first_insn ) ; if ( insn && NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SET && SET_DEST ( PATTERN ( insn ) ) == * p_ep && SET_SRC ( PATTERN ( insn ) ) == * p_r1 ) delete_insn ( insn ) ; else emit_insn_before ( gen_rtx_SET ( Pmode , * p_r1 , * p_ep ) , first_insn ) ; emit_insn_before ( gen_rtx_SET ( Pmode , * p_ep , reg ) , first_insn ) ;

emit_insn_before ( gen_rtx_SET ( Pmode , * p_ep , * p_r1 ) , last_insn ) ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; bool Changed = false ; initialize ( MF ) ; if ( gatherVectorInstructions ( ) ) { formWebs ( ) ; recordUnoptimizableWebs ( ) ; markSwapsForRemoval ( ) ;


return TARGET_VECT_DOUBLE ? DImode : SImode ;


<s> virtual void releaseBottomNode ( SUnit * SU ) {


<s> for ( auto & MI : MRI -> use_nodbg_instructions ( SrcReg ) ) { if ( MI . isBundle ( ) ) continue ;

if ( ! Visited . insert ( & MI ) . second ) continue ;


<s> if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && ( Val <= <NUM_LIT> || <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( ~ Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ;