<s> return D ( <STR_LIT> , A18 ( addr_low , addr_high ) , cond ) ;


<s> SmallVector < MachineBasicBlock * , <NUM_LIT> > Worklist ( Begin -> successors ( ) ) ; while ( ! Worklist . empty ( ) ) { MachineBasicBlock * MBB = Worklist . pop_back_val ( ) ; if ( MBB == End || ! Visited . insert ( MBB ) . second ) continue ; for ( auto & Term : MBB -> terminators ( ) ) if ( TII -> isKillTerminator ( Term . getOpcode ( ) ) ) return true ;

Worklist . append ( MBB -> succ_begin ( ) , MBB -> succ_end ( ) ) ;


<s> bool isDeprecatedDST ( ) const { return DeprecatedDST ;


<s> byval_iterator byval_end ( ) const { return ByValArgs . end ( ) ;


<s> if ( ArgMode == <NUM_LIT> ) { assert ( ! Subtarget . useSoftFloat ( ) && ! ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget . hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getTargetConstant ( ArgSize , dl , <STR_LIT> ) , DAG . getTargetConstant ( ArgMode , dl , <STR_LIT> ) , DAG . getTargetConstant ( Align , dl , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList ( getPointerTy ( DAG . getDataLayout ( ) ) , <STR_LIT> ) ;

SDValue VAARG = DAG . getMemIntrinsicNode ( Subtarget . isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> , dl , VTs , InstOps , <STR_LIT> , MachinePointerInfo ( SV ) , None , MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ) ;


<s> SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } else { Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ;

ArgValue2 = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ;


<s> ReachedBB . insert ( Edge . second ) ; const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ; while ( It != End && It -> isPHI ( ) ) { const MachineInstr & PI = * It ++ ; InstrExec . insert ( & PI ) ; visitPHI ( PI ) ; } if ( BlockScanned [ Edge . second ] ) continue ; BlockScanned [ Edge . second ] = true ; while ( It != End && ! It -> isBranch ( ) ) { const MachineInstr & MI = * It ++ ; InstrExec . insert ( & MI ) ; visitNonBranch ( MI ) ; } if ( It == End ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) && B . isSuccessor ( & * Next ) ) { int ThisN = B . getNumber ( ) ; int NextN = Next -> getNumber ( ) ; FlowQ . push ( CFGEdge ( ThisN , NextN ) ) ;


<s> static inline <STR_LIT> GetOppositeBranchCondition ( <STR_LIT> CC ) { switch ( CC ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override {


<s> static tree build_const_pointer ( tree t ) { return build_pointer_type ( build_qualified_type ( t , TYPE_QUAL_CONST ) ) ;


<s> static bool sparc_vector_mode_supported_p ( enum machine_mode mode ) {

return TARGET_VIS && VECTOR_MODE_P ( mode ) ? true : false ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; InstructionCost Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * > Operands ( I . operand_values ( ) ) ; Cost += getUserCost ( & I , Operands , TargetTransformInfo :: TCK_SizeAndLatency ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ;


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) llvm_unreachable ( <STR_LIT> ) ; unsigned ScaleVal = C -> getZExtValue ( ) ; if ( ScaleVal > <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; EVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue MaskInReg ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ; if ( MaskC ) MaskInReg = DAG . getTargetConstant ( MaskC -> getSExtValue ( ) , dl , MaskVT ) ;


<s> SDValue PassThru = MGT -> getPassThru ( ) ; SDValue Mask = MGT -> getMask ( ) ; SDValue BasePtr = MGT -> getBasePtr ( ) ; <STR_LIT> ExtTy = MGT -> getExtensionType ( ) ; <STR_LIT> IndexType = MGT -> getIndexType ( ) ; bool IsScaled = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IsSigned = IndexType == <STR_LIT> || IndexType == <STR_LIT> ; bool IdxNeedsExtend = getGatherScatterIndexIsExtended ( Index ) || Index . getSimpleValueType ( ) . getVectorElementType ( ) == <STR_LIT> ; bool ResNeedsSignExtend = ExtTy == <STR_LIT> || ExtTy == <STR_LIT> ; EVT VT = PassThru . getSimpleValueType ( ) ; EVT MemVT = MGT -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( VT . isFloatingPoint ( ) ) { EVT PassThruVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; PassThru = getSVESafeBitCast ( PassThruVT , PassThru , DAG ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } SDVTList VTs = DAG . getVTList ( PassThru . getSimpleValueType ( ) , <STR_LIT> ) ; if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ; unsigned Opcode = getGatherVecOpcode ( IsScaled , IsSigned , IdxNeedsExtend ) ; selectGatherScatterAddrMode ( BasePtr , Index , MemVT , Opcode , true , DAG ) ;

if ( ResNeedsSignExtend ) Opcode = getSignExtendedGatherOpcode ( Opcode ) ;


<s> bool NVVMIntrRange :: runOnFunction ( Function & F ) {

return runNVVMIntrRange ( F , SmVersion ) ;


<s> void HSACodeObject :: InitMarkers ( ) const { auto TextSecOr = getTextSection ( ) ; if ( ! TextSecOr ) return ; auto TextSec = TextSecOr . get ( ) ; FunctionMarkers . push_back ( TextSec -> sh_size ) ; for ( const auto & Sym : functions ( ) ) { auto ExpectedFunction = FunctionSym :: asFunctionSym ( getSymbol ( Sym . getRawDataRefImpl ( ) ) ) ; if ( ! ExpectedFunction ) {

consumeError ( ExpectedFunction . takeError ( ) ) ;


<s> return ( __m128i ) __builtin_ia32_pbroadcastw128 ( ( __v8hi ) __X ) ;


<s> static void cris_file_end ( void ) {

if ( TARGET_LINUX && trampolines_created ) file_end_indicate_exec_stack ( ) ;


<s> virtual void EmitULEB128Value ( const MCExpr * Value ) {


<s> unsigned Opc = Cmp . getOpcode ( ) ; EVT VT = Op . getValueType ( ) ; bool IllegalFPCMov = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && ! isScalarFPTypeInSSEReg ( VT ) ) IllegalFPCMov = ! hasFPCMov ( cast < ConstantSDNode > ( CC ) -> getSExtValue ( ) ) ; if ( ( is<ISA_LIT>LogicalCmp ( Cmp ) && ! IllegalFPCMov ) || Opc == <STR_LIT> ) { Cond = Cmp ; addTest = false ; } } else if ( CondOpcode == <STR_LIT> || CondOpcode == <STR_LIT> || CondOpcode == <STR_LIT> || CondOpcode == <STR_LIT> || ( ( CondOpcode == <STR_LIT> || CondOpcode == <STR_LIT> ) && Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) ) { SDValue LHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; unsigned <ISA_LIT>Opcode ; unsigned <ISA_LIT>Cond ; SDVTList VTs ; switch ( CondOpcode ) { case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; case <STR_LIT> : <ISA_LIT>Opcode = <STR_LIT> ; <ISA_LIT>Cond = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( CondOpcode == <STR_LIT> ) VTs = DAG . getVTList ( LHS . getValueType ( ) , LHS . getValueType ( ) , <STR_LIT> ) ; else VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue <ISA_LIT>Op = DAG . getNode ( <ISA_LIT>Opcode , DL , VTs , LHS , RHS ) ; if ( CondOpcode == <STR_LIT> ) Cond = <ISA_LIT>Op . getValue ( <NUM_LIT> ) ; else Cond = <ISA_LIT>Op . getValue ( <NUM_LIT> ) ; CC = DAG . getConstant ( <ISA_LIT>Cond , <STR_LIT> ) ; addTest = false ; } if ( addTest ) { if ( isTruncWithZeroHighBitsInput ( Cond , DAG ) ) Cond = Cond . getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> && Cond . hasOneUse ( ) ) { SDValue NewSetCC = LowerToBT ( Cond , <STR_LIT> , DL , DAG ) ; if ( NewSetCC . getNode ( ) ) { CC = NewSetCC . getOperand ( <NUM_LIT> ) ; Cond = NewSetCC . getOperand ( <NUM_LIT> ) ; addTest = false ; } } } if ( addTest ) {

CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printU16ImmOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { int64_t Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) O << formatHex ( static_cast < uint64_t > ( Imm & <NUM_LIT> ) ) ;

else printU32ImmOperand ( MI , OpNo , STI , O ) ;


<s> } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; nios2_adjust_call_address ( & funexp , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; insn = emit_call_insn ( gen_sibcall_internal ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; insn = get_insns ( ) ; shorten_branches ( insn ) ;

final_start_function ( insn , file , <NUM_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ; initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ;

initializeGenericToNVVMPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addReg ( Op1 ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; }


<s> int <ISA_LIT>TTIImpl :: getCostOfKeepingLiveOverCall ( ArrayRef < Type * > Tys ) { int Cost = <NUM_LIT> ; for ( auto * I : Tys ) { if ( ! I -> isVectorTy ( ) ) continue ; if ( I -> getScalarSizeInBits ( ) * cast < VectorType > ( I ) -> getNumElements ( ) == <NUM_LIT> ) Cost += getMemoryOpCost ( Instruction :: Store , I , Align ( <NUM_LIT> ) , <NUM_LIT> ) + getMemoryOpCost ( Instruction :: Load , I , Align ( <NUM_LIT> ) , <NUM_LIT> ) ;


<s> static inline bool isDefADRF ( SUnit * SU ) { unsigned Opcode = SU -> getInstr ( ) -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) {


<s> if ( <ISA_LIT>InstrInfo :: isSMRD ( * MI ) ) return std :: max ( <NUM_LIT> , checkSMRDHazards ( MI ) ) ;

if ( <ISA_LIT>InstrInfo :: isVMEM ( * MI ) ) return std :: max ( <NUM_LIT> , checkVMEMHazards ( MI ) ) ;


<s> void <ISA_LIT>DAGToDAGISel :: InstructionSelect ( ) { DEBUG ( BB -> dump ( ) ) ; SelectRoot ( * CurDAG ) ; CurDAG -> RemoveDeadNodes ( ) ;


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> return ( poly16x4_t ) __builtin_neon_vdup_nv4hi ( ( __builtin_neon_hi ) __a ) ;


<s> int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MachinePointerInfo <ISA_LIT>FunctionInfo :: callPtrInfo ( const GlobalValue * Val ) { std :: unique_ptr < const <ISA_LIT>CallEntry > & E = GlobalCallEntries [ Val ] ; if ( ! E ) E = llvm :: make_unique < <ISA_LIT>CallEntry > ( Val ) ; return MachinePointerInfo ( E . get ( ) ) ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) {

addPass ( create<ISA_LIT>AtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> static SDValue LowerFP_TO_INT ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { EVT OpVT = Op . getValueType ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; EVT Op0VT = Op0 . getValueType ( ) ; if ( ( OpVT == <STR_LIT> && Op0VT == <STR_LIT> ) || OpVT == <STR_LIT> ) { RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getFPTOSINT ( Op0VT , OpVT ) : RTLIB :: getFPTOUINT ( Op0VT , OpVT ) ;

assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ;


<s> case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_Data_4 : return <NUM_LIT> ;


<s> if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ; if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> Op -> RegList . List1From = <NUM_LIT> ; Op -> RegList . List1To = <NUM_LIT> ; Op -> RegList . List2From = <NUM_LIT> ; Op -> RegList . List2To = <NUM_LIT> ; Op -> RegList . List3From = <NUM_LIT> ; Op -> RegList . List3To = <NUM_LIT> ; Op -> RegList . List4From = <NUM_LIT> ; Op -> RegList . List4To = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < reglist . size ( ) ; i += <NUM_LIT> ) { if ( Op -> RegList . List1From == <NUM_LIT> ) { Op -> RegList . List1From = reglist [ i ] ; Op -> RegList . List1To = reglist [ i + <NUM_LIT> ] ; } else if ( Op -> RegList . List2From == <NUM_LIT> ) { Op -> RegList . List2From = reglist [ i ] ; Op -> RegList . List2To = reglist [ i + <NUM_LIT> ] ; } else if ( Op -> RegList . List3From == <NUM_LIT> ) { Op -> RegList . List3From = reglist [ i ] ;

Op -> RegList . List3To = reglist [ i + <NUM_LIT> ] ;


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ;

MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ;


<s> SDValue getAddrLocal ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , bool IsN32OrN64 ) const { unsigned GOTFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , LoFlag ) ) ;

return DAG . getNode ( <STR_LIT> , DL , Ty , Load , Lo ) ;


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { SDValue Src = LHS . getOperand ( <NUM_LIT> ) ; if ( Src != RHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; const ConstantSDNode * CLHS = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! CLHS || ! CRHS ) return SDValue ( ) ;

static const uint32_t MaxMask = <NUM_LIT> ;


<s> unsigned getMaxBytesForLoopAlignment ( ) const {


<s> switch ( code ) { case EQ : if ( dest_mode == V16QImode && op_mode == V16QImode ) return UNSPEC_VCMPEQUB ; if ( dest_mode == V8HImode && op_mode == V8HImode ) return UNSPEC_VCMPEQUH ; if ( dest_mode == V4SImode && op_mode == V4SImode ) return UNSPEC_VCMPEQUW ; if ( dest_mode == V4SImode && op_mode == V4SFmode ) return UNSPEC_VCMPEQFP ; break ; case GE : if ( dest_mode == V4SImode && op_mode == V4SFmode ) return UNSPEC_VCMPGEFP ; case GT : if ( dest_mode == V16QImode && op_mode == V16QImode ) return UNSPEC_VCMPGTSB ; if ( dest_mode == V8HImode && op_mode == V8HImode ) return UNSPEC_VCMPGTSH ; if ( dest_mode == V4SImode && op_mode == V4SImode ) return UNSPEC_VCMPGTSW ; if ( dest_mode == V4SImode && op_mode == V4SFmode ) return UNSPEC_VCMPGTFP ; break ; case GTU : if ( dest_mode == V16QImode && op_mode == V16QImode ) return UNSPEC_VCMPGTUB ; if ( dest_mode == V8HImode && op_mode == V8HImode ) return UNSPEC_VCMPGTUH ; if ( dest_mode == V4SImode && op_mode == V4SImode ) return UNSPEC_VCMPGTUW ; break ;


<s> if ( RI . isReg ( ) ) { unsigned Reg = RI . getReg ( ) ; if ( TRI -> isVirtualRegister ( Reg ) ) { if ( hasNoDef ( Reg , MRI ) ) continue ; if ( ! MRI -> hasOneDef ( Reg ) ) { LLVM_DEBUG ( this -> getEntry ( ) -> getParent ( ) -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << printReg ( Reg , TRI ) << <STR_LIT> ) ; } if ( MRI -> def_begin ( Reg ) == MRI -> def_end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; } else if ( ! MRI -> hasOneDef ( Reg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; } assert ( MRI -> hasOneDef ( Reg ) && <STR_LIT> ) ; MachineOperand * Def = & ( * ( MRI -> def_begin ( Reg ) ) ) ; MachineOperand * UseOperand = & ( RI ) ; bool UseIsOutsideDefMBB = Def -> getParent ( ) -> getParent ( ) != MBB ; if ( UseIsOutsideDefMBB && UseOperand -> isKill ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> ) ; UseOperand -> setIsKill ( false ) ; } } } }


<s> unsigned CFIIndex = MBB . getParent ( ) -> addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , - Offset ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else { EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; } } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( SrcRegs [ I ] != DestRegs [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ; if ( isPositionIndependent ( ) ) TOp . setTargetFlags ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addOperand ( MCIL . LowerSymbolOperand ( TOp , TSym ) ) ) ; for ( unsigned I = sizeof UsedMask ; I -- > <NUM_LIT> ; ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; else EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ;

OutStreamer -> AddComment ( <STR_LIT> ) ;


<s> std :: string VDescStr = <STR_LIT> + getStringReg ( Reg ) ; const char * cstr = Fn . createExternalSymbolName ( VDescStr . c_str ( ) ) ;

unsigned ExtraInfo = InlineAsm :: Extra_HasSideEffects ;


<s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; switch ( Imm ) {

case DstUnused :: UNUSED_PAD : O << <STR_LIT> ; break ;


<s> int end ; if ( i <= <NUM_LIT> ) i += <NUM_LIT> ; if ( remainder & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) { end = i - <NUM_LIT> ; if ( end < <NUM_LIT> ) end += <NUM_LIT> ; temp1 = remainder & ( ( <NUM_LIT> << end ) | ( ( i < end ) ? ( <NUM_LIT> >> ( <NUM_LIT> - end ) ) : <NUM_LIT> ) ) ;


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> return ArgInfo . ImplicitBufferPtr . getRegister ( ) ;


<s> EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = <NUM_LIT> ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ;


<s> static const MCPhysReg ReservedCPURegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ;

for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ;


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( * MF ) ) return CalleeSavedRegsFP ; return CalleeSavedRegs ;


<s> vld1q_dup_u64 ( const uint64_t * __a ) { return ( uint64x2_t ) __builtin_neon_vld1_dupv2di ( ( const __builtin_neon_di * ) __a ) ;


<s> temp = expand_binop ( mode , add_optab , count , constm1_rtx , count , <NUM_LIT> , <NUM_LIT> ) ; if ( temp != count ) emit_move_insn ( count , temp ) ; temp = expand_binop ( mode , ashr_optab , count , GEN_INT ( <NUM_LIT> ) , blocks , <NUM_LIT> , <NUM_LIT> ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , loop_end_label ) ; emit_label ( loop_start_label ) ; emit_insn ( gen_cmpmem_short ( op0 , op1 , GEN_INT ( <NUM_LIT> ) ) ) ; temp = gen_rtx_NE ( VOIDmode , ccreg , const0_rtx ) ; temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , end_label ) , pc_rtx ) ; temp = gen_rtx_SET ( VOIDmode , pc_rtx , temp ) ; emit_jump_insn ( temp ) ; s390_load_address ( addr0 , gen_rtx_PLUS ( Pmode , addr0 , GEN_INT ( <NUM_LIT> ) ) ) ; s390_load_address ( addr1 , gen_rtx_PLUS ( Pmode , addr1 , GEN_INT ( <NUM_LIT> ) ) ) ; temp = expand_binop ( mode , add_optab , blocks , constm1_rtx , blocks , <NUM_LIT> , <NUM_LIT> ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , loop_end_label ) ; emit_jump ( loop_start_label ) ; emit_label ( loop_end_label ) ; emit_insn ( gen_cmpmem_short ( op0 , op1 , convert_to_mode ( Pmode , count , <NUM_LIT> ) ) ) ; emit_label ( end_label ) ; emit_insn ( gen_cmpint ( target , ccreg ) ) ;


<s> unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) >> <NUM_LIT> ;

return ( OffBits & <NUM_LIT> ) | RegBits ;


<s> MachineOperand Segment = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( Segment . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , Modifier ) ; O << ':' ; }

printLeaMemReference ( MI , Op , Modifier ) ;


<s> case Type :: FloatTyID : return RuntimeMD :: KernelArg :: F32 ; case Type :: DoubleTyID : return RuntimeMD :: KernelArg :: F64 ; case Type :: IntegerTyID : { bool Signed = ! TypeName . startswith ( <STR_LIT> ) ; switch ( Ty -> getIntegerBitWidth ( ) ) { case <NUM_LIT> : return Signed ? RuntimeMD :: KernelArg :: I8 : RuntimeMD :: KernelArg :: U8 ; case <NUM_LIT> :

return Signed ? RuntimeMD :: KernelArg :: I16 : RuntimeMD :: KernelArg :: U16 ;


<s> bool <ISA_LIT>InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { -- I ; } if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ;


<s> static bool isUnsafeToMoveAcross ( MachineInstr & MI , unsigned UseReg , unsigned DestReg , const TargetRegisterInfo * TRI ) { return ( UseReg && ( MI . modifiesRegister ( UseReg , TRI ) ) ) || MI . modifiesRegister ( DestReg , TRI ) || MI . readsRegister ( DestReg , TRI ) || MI . hasUnmodeledSideEffects ( ) || MI . isInlineAsm ( ) || MI . isMetaInstruction ( ) ;


<s> static int interrupt_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return <NUM_LIT> ; a = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func ) ) ;


<s> rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , <NUM_LIT> ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , <NUM_LIT> ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( result , condition_rtx ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasSIMD128 ( false ) , HasAtomics ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) {


<s> const MCExpr * getSubExpr ( ) const { return Expr ;


<s> explicit CountValue ( int64_t i ) : Kind ( CV_Immediate ) , Contents ( i ) , isNegative ( i < <NUM_LIT> ) {


<s> return HasStdExtV || HasStdExtZve32x ;


<s> Value * Src2 = Vals [ Next ( ) ] ; Type * VecTy = ResEVT . getTypeForEVT ( * Ctx ) ; assert ( VecTy -> isVectorTy ( ) ) ; assert ( VecTy == Src1 -> getType ( ) && VecTy == Src2 -> getType ( ) ) ; unsigned NumElt = VecTy -> getVectorNumElements ( ) ;

Value * Res = UndefValue :: get ( VecTy ) ;


<s> gcc_assert ( scratch2 == NULL || ( GET_CODE ( scratch2 ) == SCRATCH ) || ( GET_MODE ( scratch2 ) == SImode && REG_P ( scratch2 ) ) ) ; gcc_assert ( ! REG_P ( out ) || ! REG_P ( amount ) || ! HARD_REGISTER_P ( out ) || ( REGNO ( out ) != REGNO ( amount ) && REGNO ( out ) + <NUM_LIT> != REGNO ( amount ) ) ) ; gen_addsi3 ( ( DEST ) , ( SRC ) , GEN_INT ( - <NUM_LIT> ) ) gen_subsi3 ( ( DEST ) , GEN_INT ( <NUM_LIT> ) , ( SRC ) ) gen_addsi3_compare0 ( ( DEST ) , ( SRC ) , \ GEN_INT ( - <NUM_LIT> ) ) gen_rtx_SET ( ( DEST ) , ( SRC ) ) gen_rtx_fmt_ee ( ( CODE ) , SImode , ( SRC ) , ( AMOUNT ) ) gen_rtx_fmt_ee ( ( CODE ) == ASHIFT ? ASHIFT : LSHIFTRT , \ SImode , ( SRC ) , ( AMOUNT ) ) gen_rtx_fmt_ee ( ( CODE ) == ASHIFT ? LSHIFTRT : ASHIFT , \ SImode , ( SRC ) , ( AMOUNT ) ) gen_rtx_IOR ( SImode , ( A ) , ( B ) ) gen_arm_cond_branch ( ( LABEL ) , \ gen_rtx_ ## COND ( CCmode , cc_reg , \ const0_rtx ) , \ cc_reg ) if ( CONST_INT_P ( amount ) ) { if ( INTVAL ( amount ) <= <NUM_LIT> ) emit_insn ( gen_movdi ( out , in ) ) ; else if ( INTVAL ( amount ) >= <NUM_LIT> ) { if ( code == ASHIFTRT ) { rtx const31_rtx = GEN_INT ( <NUM_LIT> ) ; emit_insn ( SET ( out_down , SHIFT ( code , in_up , const31_rtx ) ) ) ; emit_insn ( SET ( out_up , SHIFT ( code , in_up , const31_rtx ) ) ) ; } else emit_insn ( gen_movdi ( out , const0_rtx ) ) ; } else if ( INTVAL ( amount ) < <NUM_LIT> ) { rtx reverse_amount = GEN_INT ( <NUM_LIT> - INTVAL ( amount ) ) ; emit_insn ( SET ( out_down , LSHIFT ( code , in_down , amount ) ) ) ; emit_insn ( SET ( out_down , ORR ( REV_LSHIFT ( code , in_up , reverse_amount ) , out_down ) ) ) ; emit_insn ( SET ( out_up , SHIFT ( code , in_up , amount ) ) ) ; } else { rtx adj_amount = GEN_INT ( INTVAL ( amount ) - <NUM_LIT> ) ;

emit_insn ( SET ( out_down , SHIFT ( code , in_up , adj_amount ) ) ) ;


<s> return ( unsigned long long ) __builtin_absv4hi2 ( ( v4hi ) mm ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getNumSGPRsAllowed ( unsigned WaveCount ) const { switch ( WaveCount ) { case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ;


<s> HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ; break ; } default : { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; break ; } } LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) ; if ( RequiresBundling ) finalizeBundle ( MBB , LO16 -> getIterator ( ) , MBBI -> getIterator ( ) ) ; if ( isCC ) LO16 . add ( makeImplicit ( MI . getOperand ( <NUM_LIT> ) ) ) ;


<s> if ( * RM == Reloc :: DynamicNoPIC && ! TT . isOSDarwin ( ) ) return Reloc :: Static ; return * RM ;


<s> return ( uint8x16_t ) __builtin_neon_vcgtv16qi ( __b , __a ) ;


<s> assert ( IsAbsolute && <STR_LIT> ) ; ( void ) IsAbsolute ; Data . clear ( ) ; Fixups . clear ( ) ; raw_svector_ostream OS ( Data ) ; assert ( Layout . getAssembler ( ) . getContext ( ) . getAsmInfo ( ) -> getMinInstAlignment ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Value == <NUM_LIT> ) { WasRelaxed = OldSize != Data . size ( ) ; return true ; } auto AddFixups = [ & Fixups , & AddrDelta ] ( unsigned Offset , std :: pair < unsigned , unsigned > Fixup ) { const MCBinaryExpr & MBE = cast < MCBinaryExpr > ( AddrDelta ) ; Fixups . push_back ( MCFixup :: create ( Offset , MBE . getLHS ( ) , static_cast < MCFixupKind > ( std :: get < <NUM_LIT> > ( Fixup ) ) ) ) ; Fixups . push_back ( MCFixup :: create ( Offset , MBE . getRHS ( ) , static_cast < MCFixupKind > ( std :: get < <NUM_LIT> > ( Fixup ) ) ) ) ; } ; if ( isUIntN ( <NUM_LIT> , Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc ) ; AddFixups ( <NUM_LIT> , { <STR_LIT> , <STR_LIT> } ) ; } else if ( isUInt < <NUM_LIT> > ( Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc1 ) ; <STR_LIT> :: write < uint8_t > ( OS , <NUM_LIT> , <STR_LIT> ) ; AddFixups ( <NUM_LIT> , { <STR_LIT> , <STR_LIT> } ) ; } else if ( isUInt < <NUM_LIT> > ( Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc2 ) ; <STR_LIT> :: write < uint16_t > ( OS , <NUM_LIT> , <STR_LIT> ) ; AddFixups ( <NUM_LIT> , { <STR_LIT> , <STR_LIT> } ) ; } else if ( isUInt < <NUM_LIT> > ( Value ) ) { OS << uint8_t ( dwarf :: DW_CFA_advance_loc4 ) ; <STR_LIT> :: write < uint32_t > ( OS , <NUM_LIT> , <STR_LIT> ) ;


<s> ++ OpIdx ; if ( TwoReg ) { assert ( ! NoDstReg && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; unsigned imm12 = getIImm3Imm8 ( insn ) ;

MI . addOperand ( MCOperand :: CreateImm ( ThumbExpandImm ( imm12 ) ) ) ;


<s> expandRetRA ( MBB , MI ) ; break ; case <STR_LIT> : expandERet ( MBB , MI ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandPseudoMFHiLo ( MBB , MI , Opc ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMFHiLo ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case <STR_LIT> : case <STR_LIT> : expandEhReturn ( MBB , MI ) ; break ;


<s> if ( ! DirectCallee ) { const Instruction * CalleeI = CS -> getInstruction ( ) ; assert ( CalleeI && <STR_LIT> ) ; if ( isa < CallInst > ( CalleeI ) ) { if ( getAlign ( * cast < CallInst > ( CalleeI ) , Idx , Align ) ) return Align ;

const Value * CalleeV = cast < CallInst > ( CalleeI ) -> getCalledValue ( ) ;


<s> DiagnosticPredicate isSVEAddSubImm ( ) const { if ( ! isShiftedImm ( ) && ( ! isImm ( ) || ! isa < MCConstantExpr > ( getImm ( ) ) ) ) return DiagnosticPredicateTy :: NoMatch ;

bool IsByte = std :: is_same < int8_t , std :: make_signed_t < T >> :: value || std :: is_same < int8_t , T > :: value ;


<s> HOST_WIDE_INT valm ; HOST_WIDE_INT tval ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) { valm = ( valp & <NUM_LIT> ) ; if ( valm != <NUM_LIT> ) ++ zcount ; if ( valm != <NUM_LIT> ) ++ ncount ; valp >>= <NUM_LIT> ; } if ( ncount < zcount ) { if ( generate ) emit_move_insn ( gen_rtx_REG ( Pmode , regnum ) , GEN_INT ( val | ~ ( HOST_WIDE_INT ) <NUM_LIT> ) ) ; tval = <NUM_LIT> ; insns ++ ; } else { if ( generate ) emit_move_insn ( gen_rtx_REG ( Pmode , regnum ) , GEN_INT ( val & <NUM_LIT> ) ) ; tval = <NUM_LIT> ; insns ++ ;


<s> if ( ! V0 || V0 -> getZExtValue ( ) != Size ) return false ; NBits = ShiftAmt . getOperand ( <NUM_LIT> ) ; return true ; } ; auto matchPatternC = [ & checkOneUse , matchShiftAmt ] ( SDValue Mask ) -> bool { if ( Mask . getOpcode ( ) != <STR_LIT> || ! checkOneUse ( Mask ) ) return false ; if ( ! isAllOnesConstant ( Mask . getOperand ( <NUM_LIT> ) ) ) return false ; SDValue M1 = Mask . getOperand ( <NUM_LIT> ) ; if ( ! checkOneUse ( M1 ) ) return false ; return matchShiftAmt ( M1 ) ; } ; SDValue X ; auto matchPatternD = [ & checkOneUse , & checkTwoUse , matchShiftAmt , & X ] ( SDNode * Node ) -> bool { if ( Node -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue N0 = Node -> getOperand ( <NUM_LIT> ) ; if ( N0 -> getOpcode ( ) != <STR_LIT> || ! checkOneUse ( N0 ) ) return false ; SDValue N1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; if ( N1 != N01 || ! checkTwoUse ( N1 ) ) return false ; if ( ! matchShiftAmt ( N1 ) ) return false ; X = N0 -> getOperand ( <NUM_LIT> ) ; return true ; } ; auto matchLowBitMask = [ & matchPatternA , & matchPatternB , & matchPatternC ] ( SDValue Mask ) -> bool { return matchPatternA ( Mask ) || matchPatternB ( Mask ) || matchPatternC ( Mask ) ; } ; if ( Node -> getOpcode ( ) == <STR_LIT> ) { X = Node -> getOperand ( <NUM_LIT> ) ; SDValue Mask = Node -> getOperand ( <NUM_LIT> ) ; if ( matchLowBitMask ( Mask ) ) { } else { std :: swap ( X , Mask ) ; if ( ! matchLowBitMask ( Mask ) ) return false ; } } else if ( ! matchPatternD ( Node ) ) return false ; SDLoc DL ( Node ) ; MVT XVT = NVT ; if ( ! Subtarget -> hasBMI2 ( ) && X . getOpcode ( ) == <STR_LIT> && X . hasOneUse ( ) && X . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( NVT == <STR_LIT> && <STR_LIT> ) ; X = X . getOperand ( <NUM_LIT> ) ; XVT = X . getSimpleValueType ( ) ; assert ( XVT == <STR_LIT> && <STR_LIT> ) ; } NBits = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NBits ) ; insertDAGNode ( * CurDAG , SDValue ( Node , <NUM_LIT> ) , NBits ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) , <NUM_LIT> ) ; insertDAGNode ( * CurDAG , SDValue ( Node , <NUM_LIT> ) , ImplDef ) ;

NBits = CurDAG -> getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , ImplDef , NBits ) ;


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFISaveRegP ( unsigned Reg , int Offset ) { emitARM64WinUnwindCode ( Win64EH :: UOP_SaveRegP , Reg , Offset ) ;


<s> virtual void EmitGlobalVariable ( const GlobalVariable * GV ) {


<s> if ( ! BaseOp . isReg ( ) || BaseOp . getReg ( ) != AddDefR ) return false ; MachineOperand OffsetOp = MID . mayLoad ( ) ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; if ( ! OffsetOp . isImm ( ) ) return false ; int64_t newOffset = OffsetOp . getImm ( ) + AddMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isValidOffset ( MI , newOffset ) ) return false ; Register BaseReg = AddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isSafeToExtLR ( AddSN , AddMI , BaseReg , UNodeList ) ) return false ; } bool Changed = false ; for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UseN = * I ; assert ( ! ( UseN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && <STR_LIT> ) ; NodeAddr < StmtNode * > OwnerN = UseN . Addr -> getOwner ( * DFG ) ; MachineInstr * UseMI = OwnerN . Addr -> getCode ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << UseMI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * UseMI << <STR_LIT> ) ;

Changed |= updateAddUses ( AddMI , UseMI ) ;


<s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; if ( ( TT . isArch64Bit ( ) && ( TT . getEnvironment ( ) == Triple :: GNUX32 || TT . isOSNaCl ( ) ) ) || ! TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) || TT . isOSWindows ( ) || TT . isOSNaCl ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) ) ; else if ( TT . isArch64Bit ( ) || TT . isOSDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) ) Ret += <STR_LIT> ;


<s> RegisterTarget < Triple :: sic , false > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> return isTruncStoreLegal ( ValVT , MemVT ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { switch ( CallConv ) { default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : break ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , getHasAlu32 ( ) ? CC_<ISA_LIT>32 : CC_<ISA_LIT>64 ) ; for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; <STR_LIT> SimpleTy = RegVT . getSimpleVT ( ) . SimpleTy ; switch ( SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << '\n' ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : Register VReg = RegInfo . createVirtualRegister ( SimpleTy == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ;

RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ;


<s> if ( insn == BB_END ( bb ) ) break ; insn = NEXT_INSN ( insn ) ; } live = df_get_live_out ( bb ) ; return ! REGNO_REG_SET_P ( live , FLAGS_REG ) ;


<s> default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsShift = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op -> getSplatValue ( ) ) return SDValue ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Opcode , VT ) ) return SDValue ( ) ; break ; } SmallVector < SDValue , <NUM_LIT> > LHSElts , RHSElts ; for ( SDValue Elt : Op -> ops ( ) ) { SDValue LHS = Elt . getOperand ( <NUM_LIT> ) ; SDValue RHS = Elt . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( RHS ) ) return SDValue ( ) ; if ( RHS . getValueSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { if ( ! IsShift ) return SDValue ( ) ; RHS = DAG . getZExtOrTrunc ( RHS , DL , VT . getScalarType ( ) ) ; } LHSElts . push_back ( LHS ) ; RHSElts . push_back ( RHS ) ; } if ( IsShift && any_of ( RHSElts , [ & ] ( SDValue V ) { return RHSElts [ <NUM_LIT> ] != V ; } ) ) return SDValue ( ) ; SDValue LHS = DAG . getBuildVector ( VT , DL , LHSElts ) ; SDValue RHS = DAG . getBuildVector ( VT , DL , RHSElts ) ; SDValue Res = DAG . getNode ( Opcode , DL , VT , LHS , RHS ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result ;


<s> MachineBasicBlock :: const_instr_iterator I = BundleIt . getInstrIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = B . instr_end ( ) ; unsigned Size = <NUM_LIT> ; for ( ++ I ; I != E && I -> isBundledWithPred ( ) ; ++ I ) ++ Size ; if ( Size > <NUM_LIT> ) return BundleIt ; MachineBasicBlock :: iterator NextIt = std :: next ( BundleIt ) ; MachineInstr & SingleI = * BundleIt -> getNextNode ( ) ;


<s> if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; <ISA_LIT>PreLegalizerCombinerInfo PCInfo ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ;


<s> const DataLayout & DL = MF . getDataLayout ( ) ; MCSymbol * Sym = nullptr ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ;

AsmPrinter . getNameWithPrefix ( Name , GV ) ;


<s> if ( ! Layout ) return false ; return getSubExpr ( ) -> EvaluateAsRelocatable ( Res , * Layout ) ;


<s> uint64_t SlotSize = TD -> getPointerSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; }

return DAG . getFrameIndex ( ReturnAddrIndex , getPointerTy ( ) ) ;


<s> DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugValue ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ;

const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ;


<s> unsigned <ISA_LIT>AsmBackend :: getRelaxedOpcode ( unsigned Op ) const { bool HasThumb2 = STI . getFeatureBits ( ) [ <STR_LIT> ] ; bool HasV8MBaselineOps = STI . getFeatureBits ( ) [ <STR_LIT> ] ; switch ( Op ) { default : return Op ; case <STR_LIT> : return HasThumb2 ? ( unsigned ) <STR_LIT> : Op ;


<s> getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( STI . isTargetDarwin ( ) || hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( <STR_LIT> ) ; return Reserved ;


<s> MachineBasicBlock :: iterator getCurrentTop ( ) {


<s> return __arm_vqmovunbq_s32 ( __a , __b ) ;


<s> HasSingleParameterDotFile = true ; CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: None ; UseParensForSymbolVariant = true ; UseIntegratedAssembler = false ; DwarfRegNumForCFI = true ;


<s> if ( HasPerspectiveInterpolation ) return <NUM_LIT> ;


<s> const MCallGraph & G ( * PCGB . getCallGraph ( ) ) ; MCGNode * main = G . getEntryNode ( ) ; checkCallFreePaths ( G ) ; propagateLiveArea ( G ) ; computeMinMaxDisplacement ( G , true ) ; analyzeEnsures ( G ) ; computeMinMaxDisplacement ( G , false ) ; propagateWorstCaseOccupancyAtSite ( G ) ; propagateMaxOccupancy ( G , main ) ; if ( EnablePreemptionSCA ) { propagateDeadArea ( G ) ; propagateLocalEnsureFilling ( G ) ; propagateGlobalEnsureFilling ( G ) ; propagateReserveGain ( G ) ; computeWorstCaseSavingOccupancy ( G ) ; computeWorstCaseRestoringOccupancy ( G ) ; } if ( ! SCAPMLExport . empty ( ) ) exportPML ( G , SCAGraph ) ;


<s> Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } } return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - imm ) ) ; return S ;


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { const RegisterSDNode * R = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( R != NULL && R -> getReg ( ) == <NUM_LIT> ) return CurDAG -> getConstant ( <NUM_LIT> , <STR_LIT> ) ; }


<s> std :: string FullFS = FS ; if ( CPUString == <STR_LIT> ) { if ( FullFS . empty ( ) ) FullFS = <STR_LIT> ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineBasicBlock :: iterator I ( & MI ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned SaveExec = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , SaveExec ) . addReg ( <STR_LIT> ) ; for ( auto & MO : MI . uses ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) ) { MRI . clearKillFlags ( MO . getReg ( ) ) ; } } MachineBasicBlock * LoopBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF . CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( LoopBB ) ;

LoopBB -> addSuccessor ( RemainderBB ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> } else if ( dwords > numregs ) { int pushregs = numregs ; if ( TARGET_SHCOMPACT ) ca -> stack_regs += numregs ; while ( pushregs < NPARM_REGS ( SImode ) - <NUM_LIT> && ( CALL_COOKIE_INT_REG_GET ( ca -> call_cookie , NPARM_REGS ( SImode ) - pushregs ) == <NUM_LIT> ) ) { ca -> call_cookie &= ~ CALL_COOKIE_INT_REG ( NPARM_REGS ( SImode ) - pushregs , <NUM_LIT> ) ; pushregs ++ ; } if ( numregs == NPARM_REGS ( SImode ) ) ca -> call_cookie |= CALL_COOKIE_INT_REG ( <NUM_LIT> , <NUM_LIT> ) | CALL_COOKIE_STACKSEQ ( numregs - <NUM_LIT> ) ; else ca -> call_cookie |= CALL_COOKIE_STACKSEQ ( numregs ) ; } } if ( GET_SH_ARG_CLASS ( mode2 ) == SH_ARG_FLOAT && ( named || ! ca -> prototype_p ) ) { if ( mode2 == SFmode && ca -> free_single_fp_reg ) ca -> free_single_fp_reg = <NUM_LIT> ; else if ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { int numfpregs = MIN ( ( GET_MODE_SIZE ( mode2 ) + <NUM_LIT> ) / <NUM_LIT> * <NUM_LIT> , NPARM_REGS ( SFmode ) - ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; ca -> arg_count [ ( int ) SH_ARG_FLOAT ] += numfpregs ; if ( TARGET_SHCOMPACT && ! ca -> prototype_p ) { if ( ca -> outgoing && numregs > <NUM_LIT> ) do { ca -> call_cookie |= ( CALL_COOKIE_INT_REG ( ca -> arg_count [ ( int ) SH_ARG_INT ] - numregs + ( ( numfpregs - <NUM_LIT> ) / <NUM_LIT> ) , <NUM_LIT> + ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] - numfpregs ) / <NUM_LIT> ) ) ; } while ( numfpregs -= <NUM_LIT> ) ; }

else if ( mode2 == SFmode && ( named ) && ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) ) ca -> free_single_fp_reg = FIRST_FP_PARM_REG - numfpregs + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] + <NUM_LIT> ;


<s> section = buf ; } switch_to_section ( get_section ( section , SECTION_WRITE , NULL ) ) ; assemble_align ( POINTER_SIZE ) ; if ( TARGET_RELOCATABLE ) {


<s> <ISA_LIT>FrameLowering ( StackDirection D , Align StackAl , int LAO , Align TransAl = Align ( <NUM_LIT> ) ) : <ISA_LIT>FrameLowering ( D , StackAl , LAO , TransAl ) {


<s> return create<ISA_LIT>MachObjectWriter ( OS , false , object :: mach :: CTM_<ISA_LIT> , Subtype ) ;


<s> return ( __m512i ) __builtin_ia32_punpckldq512_mask ( ( __v16si ) __A , ( __v16si ) __B , ( __v16si ) _mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> if ( isa < FixedVectorType > ( DataType ) || ! ST -> hasSVE ( ) ) return false ;

return isLegalElementTypeForSVE ( DataType -> getScalarType ( ) ) ;


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> StringRef getDesc ( ) const { return StringRef ( getName ( ) . data ( ) + alignTo ( namesz , ALIGN ) , descsz ) ;


<s> int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {

real_from_string ( & ext_80387_constants_table [ i ] , cst [ i ] ) ;


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT ExtractVT = VT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned Mull2VectorIdx = VT . getVectorNumElements ( ) / <NUM_LIT> ; SDValue VMullIdx = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue VMull2Idx = DAG . getConstant ( Mull2VectorIdx , DL , <STR_LIT> ) ; SDValue VMullV0 = DAG . getNode ( <STR_LIT> , DL , ExtractVT , V0 , VMullIdx ) ; SDValue VMullV1 = DAG . getNode ( <STR_LIT> , DL , ExtractVT , V1 , VMullIdx ) ;

SDValue VMull2V0 = DAG . getNode ( <STR_LIT> , DL , ExtractVT , V0 , VMull2Idx ) ;


<s> if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ;


<s> SDNode * Node = Op . getNode ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue InChain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; EVT PtrVT = VAListPtr . getValueType ( ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc dl ( Node ) ; SDValue VAList = DAG . getLoad ( PtrVT , dl , InChain , VAListPtr , MachinePointerInfo ( SV ) , false , false , false , <NUM_LIT> ) ;

SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAList , DAG . getIntPtrConstant ( VT . getSizeInBits ( ) / <NUM_LIT> ) ) ;


<s> if ( ! LdSt . mayLoadOrStore ( ) ) return false ; if ( LdSt . getNumExplicitOperands ( ) != <NUM_LIT> ) return false ; if ( ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) || ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ;

Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ;


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( Name == <STR_LIT> ) { enableArchExtFeature ( <STR_LIT> , ExtLoc ) ; enableArchExtFeature ( <STR_LIT> , ExtLoc ) ; } if ( enableArchExtFeature ( Name , ExtLoc ) ) return false ;

return Error ( ExtLoc , <STR_LIT> + Name ) ;


<s> if ( FpABI == <STR_LIT> :: SOFT ) OS << <STR_LIT> ; else OS << <STR_LIT> << ABIFlagsSection . getFpABIString ( FpABI ) << <STR_LIT> ;


<s> unsigned MOHiFlag , MOLoFlag ; bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag ) ; SDValue TgtBAHi = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOHiFlag ) ; SDValue TgtBALo = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( TgtBAHi , TgtBALo , IsPIC , DAG ) ;


<s> <ISA_LIT>MCCodeEmitter :: <ISA_LIT>MCCodeEmitter ( MCInstrInfo const & aMII , MCSubtargetInfo const & aMST , MCContext & aMCT ) : MST ( aMST ) , MCT ( aMCT ) {


<s> return __builtin_loongson_pshufh_s ( s , order ) ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) {

MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;


<s> if ( ST . hasFuseLiterals ( ) && isLiteralsPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseAddress ( ) && isAddressLdStPair ( FirstMI , SecondMI ) ) return true ;

if ( ST . hasFuseCCSelect ( ) && isCCSelectPair ( FirstMI , SecondMI ) ) return true ;


<s> static bool isUseSafeToFold ( const <ISA_LIT>InstrInfo * TII , const MachineInstr & MI , const MachineOperand & UseMO ) { return ! UseMO . isUndef ( ) && ! TII -> isSDWA ( MI ) ;


<s> bool isTypedVectorList ( ) const { if ( Kind != k_VectorList ) return false ;

if ( VectorList . Count != NumRegs ) return false ;


<s> if ( CONST_INT_P ( lane_idx ) ) aarch64_simd_lane_bounds ( lane_idx , <NUM_LIT> , UINTVAL ( totalsize ) / UINTVAL ( elementsize ) , exp ) ; else error ( <STR_LIT> , exp ) ; } else error ( <STR_LIT> , exp ) ; return const0_rtx ; } aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ fcode - AARCH64_SIMD_PATTERN_START ] ; enum insn_code icode = d -> code ; builtin_simd_arg args [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = <NUM_LIT> ; int k ; is_void = ! ! ( d -> qualifiers [ <NUM_LIT> ] & qualifier_void ) ; num_args += is_void ; for ( k = <NUM_LIT> ; k < num_args ; k ++ ) { int qualifiers_k = k ;


<s> return pParent . getTarget ( ) . getGOT ( ) . addr ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { unsigned val = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( val != <NUM_LIT> ) ; } break ; } return false ;


<s> assert ( B < RC . width ( ) && B + W <= RC . width ( ) ) ; int64_t T = <NUM_LIT> ; for ( uint16_t i = B + W ; i > B ; -- i ) { const BitTracker :: BitValue & BV = RC [ i - <NUM_LIT> ] ; T <<= <NUM_LIT> ; if ( BV . is ( <NUM_LIT> ) ) T |= <NUM_LIT> ; else if ( ! BV . is ( <NUM_LIT> ) ) return false ; }


<s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) emitLineNumberAsDotLoc ( * MI ) ; MCInst Inst ; lowerToMCInst ( MI , Inst ) ;


<s> O << <STR_LIT> << utohexstr ( MI -> getOperand ( OpNum ) . getImm ( ) & <NUM_LIT> ) ;


<s> emit_insn ( gen_zero_extendqisi2 ( reg [ <NUM_LIT> ] , sub_reg ) ) ; while ( width > <NUM_LIT> ) { offset = offset + offset_adj ; shift ++ ; width -- ; mem [ <NUM_LIT> ] = gen_rtx_MEM ( QImode , plus_constant ( Pmode , operands [ <NUM_LIT> ] , offset ) ) ; emit_move_insn ( temp_sub_reg , mem [ <NUM_LIT> ] ) ; emit_insn ( gen_ashlsi3 ( temp_reg , temp_reg , GEN_INT ( shift * <NUM_LIT> ) ) ) ; emit_insn ( gen_iorsi3 ( reg [ <NUM_LIT> ] , reg [ <NUM_LIT> ] , temp_reg ) ) ; } if ( mode == DImode ) { reg [ <NUM_LIT> ] = reg [ <NUM_LIT> ] ;


<s> using namespace Dim ; switch ( dim ) { case DIM_1D : case DIM_Buffer : return <NUM_LIT> ; case DIM_2D : case DIM_Cube : case DIM_Rect : return <NUM_LIT> ; case DIM_3D :


<s> unsigned Val = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Val |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Val |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ;


<s> insn = emit_insn ( insn ) ; } else { if ( ! CONST_OK_FOR_K ( INTVAL ( frame_off ) ) ) frame_off = force_const_mem ( Pmode , frame_off ) ; insn = emit_insn ( gen_add2_insn ( frame_pointer , frame_off ) ) ; annotate_constant_pool_refs ( & PATTERN ( insn ) ) ; } add_reg_note ( insn , REG_CFA_ADJUST_CFA , cfa ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( TARGET_64BIT ) { if ( cfun_save_high_fprs_p ) { next_offset = cfun_frame_layout . f8_offset ; for ( i = FPR8_REGNUM ; i <= FPR15_REGNUM ; i ++ ) { if ( cfun_fpr_save_p ( i ) ) { restore_fpr ( frame_pointer , offset + next_offset , i ) ; cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( DFmode , i ) , cfa_restores ) ; next_offset += <NUM_LIT> ; } } } } else { next_offset = cfun_frame_layout . f4_offset ; for ( i = FPR4_REGNUM ; i <= FPR4_REGNUM + <NUM_LIT> ; i ++ ) { if ( cfun_fpr_save_p ( i ) ) { restore_fpr ( frame_pointer , offset + next_offset , i ) ; cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( DFmode , i ) , cfa_restores ) ; next_offset += <NUM_LIT> ; } else if ( ! TARGET_PACKED_STACK ) next_offset += <NUM_LIT> ; } } return_reg = gen_rtx_REG ( Pmode , RETURN_REGNUM ) ; if ( cfun_frame_layout . first_restore_gpr != - <NUM_LIT> ) { rtx insn , addr ; int i ; for ( i = cfun_frame_layout . first_restore_gpr ; i <= cfun_frame_layout . last_restore_gpr ; i ++ ) { if ( global_not_special_regno_p ( i ) ) { addr = plus_constant ( Pmode , frame_pointer , offset + cfun_frame_layout . gprs_offset + ( i - cfun_frame_layout . first_save_gpr_slot ) * UNITS_PER_LONG ) ; addr = gen_rtx_MEM ( Pmode , addr ) ;

set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ;


<s> static void basicCheckForEHAndSjLj ( TargetMachine * TM ) { TM -> Options . ExceptionModel = TM -> getMCAsmInfo ( ) -> getExceptionHandlingType ( ) ; if ( TM -> Options . ExceptionModel != ExceptionHandling :: None && TM -> Options . ExceptionModel != ExceptionHandling :: Wasm ) report_fatal_error ( <STR_LIT> ) ; if ( WasmEnableEmEH && TM -> Options . ExceptionModel == ExceptionHandling :: Wasm ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; if ( WasmEnableEH && TM -> Options . ExceptionModel != ExceptionHandling :: Wasm ) report_fatal_error ( <STR_LIT> ) ; if ( WasmEnableSjLj && TM -> Options . ExceptionModel != ExceptionHandling :: Wasm ) report_fatal_error ( <STR_LIT> ) ;

if ( ( ! WasmEnableEH && ! WasmEnableSjLj ) && TM -> Options . ExceptionModel == ExceptionHandling :: Wasm ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ;


<s> ASM_OUTPUT_ALIGN ( asm_out_file , floor_log2 ( align / BITS_PER_UNIT ) ) ; for ( i = <NUM_LIT> ; VEC_iterate ( int , funcdef_nos , i , n ) ; i ++ ) { targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , n ) ; assemble_integer ( const0_rtx , LONG_TYPE_SIZE / BITS_PER_UNIT , align , <NUM_LIT> ) ; } VEC_free ( int , heap , funcdef_nos ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; EVT PtrVT = Op . getValueType ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , PtrVT , Offset ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , PtrVT , Result ) ;


<s> void <ISA_LIT>AsmPrinter :: emitFrameDirective ( ) {


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { return VT == <STR_LIT> || VT == <STR_LIT> ;


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MachineInstr & MI = * I ; DebugLoc dl = MI . getDebugLoc ( ) ; int Size = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) Size = - Size ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( Size ) BuildMI ( MBB , I , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Size ) ; MBB . erase ( I ) ;


<s> const uint64_t F = MCID -> TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> static bool fusion_load_store ( rtx_insn * insn , rtx * base , rtx * offset , bool * is_load ) { rtx x , dest , src ; gcc_assert ( INSN_P ( insn ) ) ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return false ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; if ( REG_P ( src ) && MEM_P ( dest ) ) { * is_load = false ;

extract_base_offset_in_addr ( dest , base , offset ) ;


<s> int RegNo = matchRegisterName ( RegisterName ) ; if ( RegNo == <NUM_LIT> ) return true ; Operands . push_back ( <STR_LIT> ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ;


<s> if ( ! is_call ) emit_insn ( gen_nvptx_joining ( op ) ) ;


<s> const MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opcode ) ) ; AddSubReg ( MIB , DestReg , Indices [ SubReg ] , RegState :: Define , TRI ) ; AddSubReg ( MIB , SrcReg , Indices [ SubReg ] , <NUM_LIT> , TRI ) ; AddSubReg ( MIB , SrcReg , Indices [ SubReg ] , getKillRegState ( KillSrc ) , TRI ) ;


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) {


<s> return false ; } Triple T ; STI . setDefaultFeatures ( T . get<ISA_LIT>CPUForArch ( Arch ) ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . emitArch ( ID ) ; return false ;


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ;

MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ;


<s> int i ; machine_mode mode ; rtx * regs ; if ( ! ISA_HAS_LWL_LWR ) bits = MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ; else { if ( MEM_ALIGN ( src ) == BITS_PER_WORD / <NUM_LIT> && MEM_ALIGN ( dest ) == BITS_PER_WORD / <NUM_LIT> ) bits = BITS_PER_WORD / <NUM_LIT> ; else bits = BITS_PER_WORD ; } mode = int_mode_for_size ( bits , <NUM_LIT> ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; if ( MEM_ALIGN ( src ) >= bits ) mips_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; else { rtx part = adjust_address ( src , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ext_as_unaligned_load ( regs [ i ] , part , bits , <NUM_LIT> , <NUM_LIT> ) ) gcc_unreachable ( ) ; } } for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) mips_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; set_mem_size ( part , delta ) ;

if ( ! mips_expand_ins_as_unaligned_store ( part , regs [ i ] , bits , <NUM_LIT> ) ) gcc_unreachable ( ) ;


<s> } Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) ; emitWordLE ( Binary ) ;


<s> unsigned getPointerSize ( ) const { return <NUM_LIT> ;


<s> for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( Op . isRegOrImmWithInputMods ( ) ) { Op . addRegOrImmWithInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { assert ( false ) ;


<s> bool <ISA_LIT>IfConversion :: canPredicateBlock ( BBInfo & MBBInfo ) const { return MBBInfo . predicable && MBBInfo . MBB -> succ_size ( ) == <NUM_LIT> ;


<s> microblaze_elf_asm_cdtor ( symbol , priority , true ) ;


<s> } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) ) { Mnemonic = parseRD ( Name , <NUM_LIT> , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { bool ICC = Name [ <NUM_LIT> ] == 'l' || Name [ <NUM_LIT> ] == 'w' ? true : false ; Mnemonic = parseCC ( Name , <NUM_LIT> , Name . size ( ) , ICC , true , NameLoc , Operands ) ; } else if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) { bool ICC = Name [ <NUM_LIT> ] == 'l' || Name [ <NUM_LIT> ] == 'w' ? true : false ; Mnemonic = parseCC ( Name , <NUM_LIT> , Name . size ( ) , ICC , true , NameLoc , Operands ) ;


<s> const MachineBasicBlock * Succ = * MBB . succ_begin ( ) ; if ( ! MBB . isLayoutSuccessor ( Succ ) ) continue ; auto I = std :: next ( Lead ) ; for ( ; I != E ; ++ I ) if ( ! TII -> isSALU ( * I ) || I -> readsRegister ( <STR_LIT> , TRI ) ) break ; if ( I != E ) continue ; const auto NextLead = Succ -> begin ( ) ; if ( NextLead == Succ -> end ( ) || ! isEndCF ( * NextLead , TRI ) || ! getOrExecSource ( * NextLead , * TII , MRI ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * Lead << '\n' ) ; auto SaveExec = getOrExecSource ( * Lead , * TII , MRI ) ; unsigned SaveExecReg = getOrNonExecReg ( * Lead , * TII ) ; for ( auto & Op : Lead -> operands ( ) ) { if ( Op . isReg ( ) ) RecalcRegs . insert ( Op . getReg ( ) ) ; } LIS -> RemoveMachineInstrFromMaps ( * Lead ) ; Lead -> eraseFromParent ( ) ; if ( SaveExecReg ) { LIS -> removeInterval ( SaveExecReg ) ; LIS -> createAndComputeVirtRegInterval ( SaveExecReg ) ; } Changed = true ; if ( ! SaveExec || ! SaveExec -> isFullCopy ( ) ) continue ; unsigned SavedExec = SaveExec -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool SafeToReplace = true ; for ( auto & U : MRI . use_nodbg_instructions ( SavedExec ) ) { if ( U . getParent ( ) != SaveExec -> getParent ( ) ) { SafeToReplace = false ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> << * SaveExec << '\n' ) ; } if ( SafeToReplace ) { LIS -> RemoveMachineInstrFromMaps ( * SaveExec ) ; SaveExec -> eraseFromParent ( ) ; MRI . replaceRegWith ( SavedExec , <STR_LIT> ) ; LIS -> removeInterval ( SavedExec ) ; } }


<s> return AluT_XYZW ; case AMDGPU :: COPY : if ( MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) { return AluDiscarded ; } default : break ; } if ( TII -> isVector ( * MI ) || TII -> isCubeOp ( MI -> getOpcode ( ) ) || TII -> isReductionOp ( MI -> getOpcode ( ) ) || MI -> getOpcode ( ) == AMDGPU :: GROUP_BARRIER ) { return AluT_XYZW ; } if ( TII -> isLD<ISA_LIT>nstr ( MI -> getOpcode ( ) ) ) { return AluT_X ; } unsigned DestSubReg = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ;


<s> for ( auto & I : * BB ) { if ( I . mayWriteToMemory ( ) ) Writes . push_back ( & I ) ; auto * Ld = dyn_cast < LoadInst > ( & I ) ; if ( ! Ld || ! Ld -> isSimple ( ) || ! Ld -> hasOneUse ( ) || ! isa < SExtInst > ( Ld -> user_back ( ) ) ) continue ; Loads . push_back ( Ld ) ; } using InstSet = std :: set < Instruction * > ; using DepMap = std :: map < Instruction * , InstSet > ; DepMap RAWDeps ; const auto Size = LocationSize :: unknown ( ) ; for ( auto Read : Loads ) { for ( auto Write : Writes ) { MemoryLocation ReadLoc = MemoryLocation ( Read -> getPointerOperand ( ) , Size ) ; if ( ! isModOrRefSet ( intersectModRef ( AA -> getModRefInfo ( Write , ReadLoc ) , ModRefInfo :: ModRef ) ) ) continue ; if ( DT -> dominates ( Write , Read ) ) RAWDeps [ Read ] . insert ( Write ) ; } } auto SafeToPair = [ & ] ( LoadInst * Base , LoadInst * Offset ) {

LoadInst * Dominator = DT -> dominates ( Base , Offset ) ? Base : Offset ;


<s> MFI -> setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;


return ( __m128i ) __builtin_ia32_cvtpd2uqq128_mask ( ( __v2df ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) __U ) ;


<s> ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In<ISA_LIT>16Mode && ! IsSoftFloat ) In<ISA_LIT>16HardFloat = true ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isABI_N32 ( ) || isABI_N64 ( ) ) stackAlignment = <NUM_LIT> ; else { assert ( isABI_O32 ( ) && <STR_LIT> ) ;


<s> static inline MachineOperand t1CondCodeOp ( bool isDead = false ) {

return MachineOperand :: CreateReg ( <STR_LIT> , true , false , false , isDead ) ;


<s> if ( ! TARGET_USE_MOV0 || optimize_insn_for_size_p ( ) ) { rtx clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , tmp , clob ) ) ;


<s> MachineBasicBlock * BB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( BB ) ; unsigned MaxAlign = Log2_32 ( MCP -> getConstantPoolAlignment ( ) ) ; BB -> setAlignment ( MaxAlign ) ; MF -> ensureAlignment ( BB -> getAlignment ( ) ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = * MF -> getTarget ( ) . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ;


ret . val [ <NUM_LIT> ] = ( uint32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ;


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; } return SDValue ( ) ;


<s> SDValue Four = DAG . getConstant ( <NUM_LIT> , dl , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , dl , VT , RetVal ) ;


<s> if ( Subtarget . useXGOT ( ) ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false ) ; return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) , false ) ;


<s> bool ix86_lea_for_add_ok ( rtx_insn * insn , rtx operands [ ] ) { unsigned int regno0 = true_regnum ( operands [ <NUM_LIT> ] ) ; unsigned int regno1 = true_regnum ( operands [ <NUM_LIT> ] ) ; unsigned int regno2 = true_regnum ( operands [ <NUM_LIT> ] ) ; if ( regno0 != regno1 && regno0 != regno2 ) return true ;

if ( ! TARGET_OPT_AGU || optimize_function_for_size_p ( cfun ) ) return false ;


<s> if ( ! isV60VectorInstruction ( I ) ) return false ; if ( ! I -> mayLoad ( ) && ! I -> mayStore ( ) ) return false ; return J -> isIndirectBranch ( ) || isIndirectCall ( J ) || isIndirectL4Return ( J ) ;


<s> bool <ISA_LIT>BranchRelaxation :: isBlockInRange ( const MachineInstr & MI , const MachineBasicBlock & DestBB ) const { unsigned BrOffset = getInstrOffset ( MI ) ; unsigned DestOffset = BlockInfo [ DestBB . getNumber ( ) ] . Offset ; if ( TII -> isBranchInRange ( MI . getOpcode ( ) , BrOffset , DestOffset ) ) return true ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB . getNumber ( ) << <STR_LIT> << MI . getParent ( ) -> getNumber ( ) << <STR_LIT> << DestOffset << <STR_LIT> << static_cast < int > ( DestOffset - BrOffset ) << '\t' << MI ) ; return false ;


<s> FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { if ( Flags == <STR_LIT> || Flags == <STR_LIT> ) Flags = <STR_LIT> ; for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return MatchOperand_NoMatch ; if ( SpecReg == <STR_LIT> ) FlagsVal |= <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ;


<s> return ( ( qword ) ( vec_xor ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) ( b ) ) ) ) ;


<s> machine_mode elt_mode ; int n_elts ; rs6000_discover_homogeneous_aggregate ( mode , type , & elt_mode , & n_elts ) ; if ( DEFAULT_ABI == ABI_V4 && ( GET_MODE_SIZE ( mode ) == <NUM_LIT> || ( TARGET_HARD_FLOAT && ! is_complex_IBM_long_double ( mode ) && FLOAT128_2REG_P ( mode ) ) ) ) return <NUM_LIT> ; else if ( FLOAT128_VECTOR_P ( mode ) ) return <NUM_LIT> ;

else if ( PAIRED_VECTOR_MODE ( mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= <NUM_LIT> && int_size_in_bytes ( type ) < <NUM_LIT> ) ) return <NUM_LIT> ;


<s> const __v4si vzero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __asm__ ( <STR_LIT> : <STR_LIT> ( temp ) : <STR_LIT> ( rounded ) : ) ; temp = vec_mergeo ( temp , temp ) ; temp = vec_mergee ( temp , temp ) ; result = ( __v4si ) vec_vpkudum ( ( __vector long long ) temp , ( __vector long long ) vzero ) ; { const __v16qu pkperm = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; result = ( __v4si ) vec_perm ( ( __v16qu ) temp , ( __v16qu ) vzero , pkperm ) ; }


<s> mErrors . insert ( msg ) ; } else if ( val == ALWAYS ) { mErrors . insert ( msg ) ; }


<s> for ( ; ; ) { enum tree_code code ; stmt = SSA_NAME_DEF_STMT ( lhs ) ; if ( gimple_code ( stmt ) == GIMPLE_PHI ) return stmt ; if ( ! is_gimple_assign ( stmt ) || gimple_assign_lhs ( stmt ) != lhs ) return NULL ; if ( TREE_CODE ( gimple_assign_rhs1 ( stmt ) ) != SSA_NAME ) return stmt ; code = gimple_assign_rhs_code ( stmt ) ;

if ( ! CONVERT_EXPR_CODE_P ( code ) && ( ( code != PLUS_EXPR && code != POINTER_PLUS_EXPR ) || TREE_CODE ( gimple_assign_rhs2 ( stmt ) ) != INTEGER_CST || ! tree_fits_uhwi_p ( gimple_assign_rhs2 ( stmt ) ) ) ) return stmt ;


<s> default : return false ; case <STR_LIT> : expandLDImm ( MI ) ; return true ; case <STR_LIT> : expandLDAddr ( MI ) ; return true ; }


<s> if ( TT . isOSDarwin ( ) ) return Reloc :: DynamicNoPIC ; if ( TT . getArch ( ) == Triple :: ppc64 ) return Reloc :: PIC_ ;


<s> return AllParams . find ( Param ) -> second . Arg ;


<s> const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; if ( ! IsEntryFunc ) { Register ReturnAddrReg = TRI -> getReturnAddressReg ( MF ) ; Register LiveInReturn = MF . addLiveIn ( ReturnAddrReg , & <STR_LIT> ) ; MBB . addLiveIn ( ReturnAddrReg ) ; MIRBuilder . buildCopy ( LiveInReturn , ReturnAddrReg ) ; } if ( Info -> hasImplicitBufferPtr ( ) ) { Register ImplicitBufferPtrReg = Info -> addImplicitBufferPtr ( * TRI ) ; MF . addLiveIn ( ImplicitBufferPtrReg , & <STR_LIT> ) ; CCInfo . AllocateReg ( ImplicitBufferPtrReg ) ; } SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ; unsigned P<ISA_LIT>nputNum = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == <NUM_LIT> ) continue ; const bool InReg = Arg . hasAttribute ( Attribute :: InReg ) ; if ( ! IsShader && InReg ) return false ; if ( Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; if ( CC == CallingConv :: <ISA_LIT>_PS && ! InReg && P<ISA_LIT>nputNum <= <NUM_LIT> ) { const bool ArgUsed = ! Arg . use_empty ( ) ; bool SkipArg = ! ArgUsed && ! Info -> isP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( ! SkipArg ) { Info -> markP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( ArgUsed ) Info -> markP<ISA_LIT>nputEnabled ( P<ISA_LIT>nputNum ) ;


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ;


<s> auto * MemIntrin = cast < MemIntrinsicSDNode > ( N ) ; SDValue Ptr = MemIntrin -> getBasePtr ( ) ; SDValue Chain = MemIntrin -> getChain ( ) ; EVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; EVT MemVT = MemIntrin -> getMemoryVT ( ) ; for ( SDNode * User : Ptr -> uses ( ) ) if ( User != N && User -> getOpcode ( ) == <STR_LIT> && cast < MemIntrinsicSDNode > ( User ) -> getBasePtr ( ) == Ptr && cast < MemIntrinsicSDNode > ( User ) -> getChain ( ) == Chain && cast < MemIntrinsicSDNode > ( User ) -> getMemoryVT ( ) . getSizeInBits ( ) == MemVT . getSizeInBits ( ) && ! User -> hasAnyUseOfValue ( <NUM_LIT> ) && User -> getValueSizeInBits ( <NUM_LIT> ) . getFixedSize ( ) > VT . getFixedSizeInBits ( ) ) { SDValue Extract = extractSubVector ( SDValue ( User , <NUM_LIT> ) , <NUM_LIT> , DAG , SDLoc ( N ) , VT . getSizeInBits ( ) ) ; Extract = DAG . getBitcast ( VT , Extract ) ; return DCI . CombineTo ( N , Extract , SDValue ( User , <NUM_LIT> ) ) ;


<s> case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { if ( ! ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; return S ; } return DecodeRFEInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeRegListOperand ( Inst , reglist , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> static InsnType buildBranchInsn ( ) { return <NUM_LIT> ;


<s> unsigned Opc = getStoreRegOpcode ( RC , isAligned ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , false , false , isKill ) ;


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] && ExtraCode [ <NUM_LIT> ] != 'a' ) return true ;

const MachineOperand & MO = MI -> getOperand ( OpNum ) ;


<s> type = TREE_TYPE ( type ) ; decl_or_type = type ; } a = ix86_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = ix86_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( STACK_REG_P ( a ) || STACK_REG_P ( b ) ) { if ( ! rtx_equal_p ( a , b ) ) return false ; } else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( TARGET_64BIT ) { if ( cfun -> machine -> call_abi == MS_ABI && ix86_function_type_abi ( type ) == SYSV_ABI ) return false ; } else {

if ( ! decl || ( bind_global && flag_pic && ! flag_plt ) || ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P ( decl ) ) ) {


<s> O << <STR_LIT> ; O . write_hex ( MO . getImm ( ) ) ; } else O << * MO . getExpr ( ) ;


<s> static int current_file_function_operand ( rtx sym_ref ) {

if ( ENCODED_SHORT_CALL_ATTR_P ( XSTR ( sym_ref , <NUM_LIT> ) ) ) return <NUM_LIT> ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> unsigned HOST_WIDE_INT temp ; if ( op_const == <NUM_LIT> ) return NULL ; temp = opint [ <NUM_LIT> ] & <NUM_LIT> ; temp |= ( opint [ <NUM_LIT> ] >> <NUM_LIT> ) & <NUM_LIT> ; return build_int_cst ( alpha_dimode_u , temp ) ;


<s> MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; if ( ! LI . isLoopHeader ( & MBB ) ) return false ; for ( auto I = MBB . pred_begin ( ) ; I != MBB . pred_end ( ) ; ++ I ) { const MachineBasicBlock * PMBB = * I ; if ( LI . getLoopFor ( PMBB ) != LI . getLoopFor ( & MBB ) ) { continue ; }

if ( const BasicBlock * PBB = PMBB -> getBasicBlock ( ) ) {


<s> BuildMI ( loop1MBB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop1MBB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( Dest ) . addReg ( Mask ) ; BuildMI ( loop1MBB , DL , TII -> get ( BNE ) ) . addReg ( Mask ) . addReg ( ShiftCmpVal ) . addMBB ( sinkMBB ) ; loop1MBB -> addLiveIn ( Ptr ) ; loop1MBB -> addLiveIn ( Mask ) ; loop1MBB -> addLiveIn ( ShiftCmpVal ) ; BuildMI ( loop2MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addReg ( Mask2 ) ; BuildMI ( loop2MBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addReg ( ShiftNewVal ) ; BuildMI ( loop2MBB , DL , TII -> get ( SC ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop2MBB , DL , TII -> get ( BEQ ) ) . addReg ( Dest , RegState :: Kill ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; loop2MBB -> addLiveIn ( Ptr ) ; loop2MBB -> addLiveIn ( Mask2 ) ; loop2MBB -> addLiveIn ( Dest ) ; loop2MBB -> addLiveIn ( ShiftNewVal ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Mask ) . addReg ( ShiftAmnt ) ; if ( STI -> has<ISA_LIT>32r2 ( ) ) { BuildMI ( sinkMBB , DL , TII -> get ( SEOp ) , Dest ) . addReg ( Dest ) ; } else { const unsigned ShiftImm = I -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addImm ( ShiftImm ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addImm ( ShiftImm ) ; } sinkMBB -> addLiveIn ( Mask ) ; sinkMBB -> addLiveIn ( ShiftAmnt ) ; addPostLoopLiveIns ( exitMBB , LiveRegs ) ; exitMBB -> addLiveIn ( Dest ) ;


<s> PrintFP ( const FlowPattern & P , const TargetRegisterInfo & T ) : FP ( P ) , TRI ( T ) {


<s> bool <ISA_LIT>AsmParser :: invalidOperand ( SMLoc const & Loc , OperandVector const & Operands , uint64_t const & ErrorInfo ) { SMLoc ErrorLoc = Loc ; char const * Diag = <NUM_LIT> ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) { Diag = <STR_LIT> ; } else { auto const & Op = ( <ISA_LIT>Operand const & ) * Operands [ ErrorInfo ] ; if ( Op . getStartLoc ( ) != SMLoc ( ) ) { ErrorLoc = Op . getStartLoc ( ) ; } } } if ( ! Diag ) { Diag = <STR_LIT> ;


<s> if ( CC == <STR_LIT> ) { ++ MBBI ; continue ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; while ( MBBI != E && Pos && ( ! MI -> getDesc ( ) . isBranch ( ) && ! MI -> getDesc ( ) . isReturn ( ) ) ) { MachineInstr * NMI = & * MBBI ; MI = NMI ;


<s> bool <ISA_LIT>InstrInfo :: isPredicated ( const MachineInstr & MI ) const { return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> bool <ISA_LIT>TTIImpl :: shouldFavorPostInc ( ) const { return true ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadCopies ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isVreg1 ( SrcReg ) ) continue ; if ( isLaneMaskReg ( DstReg ) || isVreg1 ( DstReg ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; DebugLoc DL = MI . getDebugLoc ( ) ; assert ( TII -> getRegisterInfo ( ) . getRegSizeInBits ( DstReg , * MRI ) == <NUM_LIT> ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; ConstrainRegs . insert ( SrcReg ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( SrcReg ) ; DeadCopies . push_back ( & MI ) ; } for ( MachineInstr * MI : DeadCopies ) MI -> eraseFromParent ( ) ; DeadCopies . clear ( ) ;


<s> unsigned getArgRegsSaveSize ( ) const { return ArgRegsSaveSize ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> if ( isVSrc ( OpClassID ) ) return getRegClassForNode ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; return TRI . getRegClass ( OpClassID ) ; case AMDGPU :: EXTRACT_SUBREG : { int SubIdx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; const TargetRegisterClass * SuperClass = getRegClassForNode ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; return TRI . getSubClassWithSubReg ( SuperClass , SubIdx ) ; } case AMDGPU :: REG_SEQUENCE : return TRI . getRegClass ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; default : return getRegClassFor ( Op . getSimpleValueType ( ) ) ; }


<s> MachineInstr & MI = * I ; Next = std :: next ( I ) ; if ( ! TII -> isSGPRSpill ( MI ) ) continue ; int FI = TII -> getNamedOperand ( MI , <STR_LIT> :: addr ) -> getIndex ( ) ; assert ( MFI . getStackID ( FI ) == TargetStackID :: SGPRSpill ) ; if ( FuncInfo -> allocateSGPRSpillToVGPR ( MF , FI ) ) { NewReservedRegs = true ; bool Spilled = TRI -> eliminateSGPRToVGPRSpillFrameIndex ( MI , FI , nullptr , LIS ) ; ( void ) Spilled ; assert ( Spilled && <STR_LIT> ) ; SpillFIs . set ( FI ) ; } } } for ( MachineBasicBlock & MBB : MF ) { for ( auto SSpill : FuncInfo -> getSGPRSpillVGPRs ( ) ) MBB . addLiveIn ( SSpill . VGPR ) ; MBB . sortUniqueLiveIns ( ) ; for ( MachineInstr & MI : MBB ) { if ( MI . isDebugValue ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && SpillFIs [ MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ] ) { MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Register ( ) , false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDebug ( ) ; } } } MadeChange = true ; } else if ( FuncInfo -> VGPRReservedForSGPRSpill ) { FuncInfo -> removeVGPRForSGPRSpill ( FuncInfo -> VGPRReservedForSGPRSpill , MF ) ; } SaveBlocks . clear ( ) ; RestoreBlocks . clear ( ) ;

if ( NewReservedRegs ) MRI . freezeReservedRegs ( MF ) ;


<s> if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . readsRegister ( <STR_LIT> , & RI ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . readsRegister ( <STR_LIT> , & RI ) ) { if ( MI . mayLoadOrStore ( ) ) { unsigned Base ; int64_t Offset ; unsigned DummyWidth ; if ( ! getMemOpBaseRegImmOfsWidth ( MI , Base , Offset , DummyWidth , & RI ) || Base != <STR_LIT> ) return MachineOutlinerInstrType :: Illegal ; int64_t MinOffset , MaxOffset ; unsigned DummyScale ; getMemOpInfo ( MI . getOpcode ( ) , DummyScale , DummyWidth , MinOffset , MaxOffset ) ; if ( Offset + <NUM_LIT> < MinOffset || Offset + <NUM_LIT> > MaxOffset ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; } return MachineOutlinerInstrType :: Illegal ; } return MachineOutlinerInstrType :: Legal ;


<s> bool Code = false ; StringRef CodeID ; if ( getLexer ( ) . is ( AsmToken :: At ) ) { SMLoc startLoc = getLexer ( ) . getLoc ( ) ; getParser ( ) . Lex ( ) ; if ( ! getParser ( ) . parseIdentifier ( CodeID ) ) { if ( CodeID != <STR_LIT> ) return Error ( startLoc , <STR_LIT> ) ; Code = true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ;


<s> unsigned PHILinearize :: getNumSources ( unsigned DestReg ) { return phiInfoElementGetSources ( findPHIInfoElement ( DestReg ) ) . size ( ) ;


<s> <ISA_LIT>AddressSanitizer32 ( const MCSubtargetInfo * & STI ) : <ISA_LIT>AddressSanitizer ( STI ) {


<s> static unsigned int mips_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment ; alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ;

if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( class AsmPrinter & asmprinter ) : Printer ( asmprinter ) {


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { ofst = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , ofst , LocVT , LocInfo ) ) ; return false ; }


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , DL ( <STR_LIT> ) , InstrInfo ( ) , TLInfo ( TM ) , TSInfo ( DL ) , FrameLowering ( ) {


<s> machine_mode s390_dwarf_frame_reg_mode ( int regno ) { machine_mode save_mode = default_dwarf_frame_reg_mode ( regno ) ; if ( GENERAL_REGNO_P ( regno ) ) save_mode = Pmode ;

if ( GET_MODE_SIZE ( save_mode ) > <NUM_LIT> ) save_mode = DImode ;


<s>
if
(
!
TAI
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(
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)
return
;
if
(
Subtarget
->
isPICStyleGOT
(
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return
;
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(
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->
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(
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;
printBasicBlockLabel
(
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,
false
,
false
,
false
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
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(
)
<<
<STR_LIT>
<<
getFunctionNumber
(
)
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<<
uid
<<
'\n'
;
else
{
O
<<
'-'
;


<s> if ( ! isCmp ) TmpInst . addOperand ( MCOperand :: createReg ( Reg ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg ) ) ; TmpInst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ;


<s> const char * <ISA_LIT>InstPrinter :: getRegisterName ( unsigned RegNo ) {

return getRegisterName ( RegNo , ArchRegNames ? <STR_LIT> : <STR_LIT> ) ;


<s> aarch64_builtin_decls [ AARCH64_SIMD_BUILTIN_LANE_CHECK ] = add_builtin_function ( <STR_LIT> , lane_check_fpr , AARCH64_SIMD_BUILTIN_LANE_CHECK , BUILT_IN_MD , NULL , NULL_TREE ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_simd_builtin_data ) ; i ++ , fcode ++ ) { bool print_type_signature_p = false ; char type_signature [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] = { <NUM_LIT> } ; aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ i ] ; char namebuf [ <NUM_LIT> ] ; tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - <NUM_LIT> ; int arg_num = d -> qualifiers [ <NUM_LIT> ] & qualifier_void ? op_num + <NUM_LIT> : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= <NUM_LIT> ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum aarch64_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ; if ( qualifiers & qualifier_unsigned ) { type_signature [ op_num ] = 'u' ; print_type_signature_p = true ; } else if ( qualifiers & qualifier_poly ) { type_signature [ op_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ op_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; eltype = aarch64_simd_builtin_type ( op_mode , ( qualifiers & qualifier_unsigned ) != <NUM_LIT> , ( qualifiers & qualifier_poly ) != <NUM_LIT> ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; if ( arg_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } ftype = build_function_type ( return_type , args ) ; gcc_assert ( ftype != NULL ) ; if ( print_type_signature_p ) snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> , d -> name , type_signature ) ;

else snprintf ( namebuf , sizeof ( namebuf ) , <STR_LIT> , d -> name ) ;


<s> vld1q_dup_s64 ( const int64_t * __a ) { return vdupq_n_s64 ( * __a ) ;


<s> unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ;

if ( Format == FP_FORMAT_S || Format == FP_FORMAT_W ) return getReg ( <STR_LIT> , IntVal ) ;


<s> assert ( isLEA ( First ) && isLEA ( Last ) && <STR_LIT> ) ; if ( MRI -> getRegClass ( First . getOperand ( <NUM_LIT> ) . getReg ( ) ) != MRI -> getRegClass ( Last . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; AddrDispShift = getAddrDispShift ( Last , <NUM_LIT> , First , <NUM_LIT> ) ; for ( auto & MO : MRI -> use_nodbg_operands ( Last . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { MachineInstr & MI = * MO . getParent ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) ; if ( MemOpNo < <NUM_LIT> ) return false ; MemOpNo += <STR_LIT> ( Desc ) ; if ( ! isIdenticalOp ( MI . getOperand ( MemOpNo + <STR_LIT> ) , MO ) ) return false ;

for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) if ( i != ( unsigned ) ( MemOpNo + <STR_LIT> ) && isIdenticalOp ( MI . getOperand ( i ) , MO ) ) return false ;


<s> void printT2AddrModeImm8s4OffsetOperand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) {