<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isFI ( ) ) continue ; if ( MI . isDebugValue ( ) ) { assert ( i == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; Register Reg ; int64_t Offset = TFI . getFrameIndexReference ( MF , MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , Reg ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Reg , false ) ; MI . getOperand ( <NUM_LIT> ) . setIsDebug ( ) ;

auto * DIExpr = DIExpression :: prepend ( MI . getDebugExpression ( ) , DIExpression :: ApplyOffset , Offset ) ;


<s> bool MadeChange = true ; bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( ( I -> getOpcode ( ) != <STR_LIT> || I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && I -> getOpcode ( ) != <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ;


<s> if ( ! Subtarget . useRVVForFixedLengthVectors ( ) ) return false ; if ( VT . getFixedSizeInBits ( ) > <NUM_LIT> * <NUM_LIT> ) return false ; unsigned MinVLen = Subtarget . getMinRVVVectorSizeInBits ( ) ; switch ( VT . getVectorElementType ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : if ( VT . getVectorNumElements ( ) > MinVLen ) return false ; MinVLen /= <NUM_LIT> ; break ; case <STR_LIT> :


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override {


<s> DebugLoc DL = CI . I -> getDebugLoc ( ) ; Register BaseReg = AddrReg -> getReg ( ) ; unsigned BaseSubReg = AddrReg -> getSubReg ( ) ; unsigned BaseRegFlags = <NUM_LIT> ; if ( CI . BaseOff ) { Register ImmReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , ImmReg ) . addImm ( CI . BaseOff ) ; BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BaseRegFlags = RegState :: Kill ; TII -> getAddNoCarry ( * MBB , CI . Paired , DL , BaseReg ) . addReg ( ImmReg ) . addReg ( AddrReg -> getReg ( ) , <NUM_LIT> , BaseSubReg ) . addImm ( <NUM_LIT> ) ; BaseSubReg = <NUM_LIT> ; } MachineInstrBuilder Write2 = BuildMI ( * MBB , CI . Paired , DL , Write2Desc ) . addReg ( BaseReg , BaseRegFlags , BaseSubReg ) . add ( * Data0 ) . add ( * Data1 ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ; moveInstsAfter ( Write2 , CI . InstsToMove ) ; CI . I -> eraseFromParent ( ) ; CI . Paired -> eraseFromParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Write2 << '\n' ) ; return Write2 ;


<s> bool RequiresMod4Offset = false ; switch ( StorageOpcode ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RequiresMod4Offset = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RequiresMod4Offset = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( RequiresMod4Offset && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; MaxDisplacement = std :: min ( ( int ) GV -> getAlignment ( ) - <NUM_LIT> , MaxDisplacement ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> tree ix86_handle_shared_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) {

if ( TREE_CODE ( * node ) != VAR_DECL ) {


<s> add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , <NUM_LIT> ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( reg_mode , <NUM_LIT> ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ;


<s> void <ISA_LIT>XPLINKFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> return __builtin_mve_vcmpgeq_n_v4si ( __a , __b ) ;


<s> break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { uint64_t Mask = V . getConstantOperandVal ( <NUM_LIT> ) ; const SmallVector < ValueBit , <NUM_LIT> > * LHSBits ; std :: tie ( Interesting , LHSBits ) = getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) if ( ( ( Mask >> i ) & <NUM_LIT> ) == <NUM_LIT> ) Bits [ i ] = ( * LHSBits ) [ i ] ; else { if ( ( * LHSBits ) [ i ] . isZero ( ) ) Bits [ i ] = ( * LHSBits ) [ i ] ; else Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; } return std :: make_pair ( Interesting , & Bits ) ; } break ; case <STR_LIT> : { const auto & LHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; const auto & RHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; bool AllDisjoint = true ; SDValue LastVal = SDValue ( ) ; unsigned LastIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) { if ( LHSBits [ i ] . isZero ( ) && RHSBits [ i ] . isZero ( ) ) { if ( LHSBits [ i ] . hasValue ( ) && LHSBits [ i ] . getValue ( ) == LastVal && LHSBits [ i ] . getValueBitIndex ( ) == LastIdx + <NUM_LIT> ) Bits [ i ] = LHSBits [ i ] ; else if ( RHSBits [ i ] . hasValue ( ) && RHSBits [ i ] . getValue ( ) == LastVal && RHSBits [ i ] . getValueBitIndex ( ) == LastIdx + <NUM_LIT> ) Bits [ i ] = RHSBits [ i ] ; else Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; } else if ( LHSBits [ i ] . isZero ( ) ) Bits [ i ] = RHSBits [ i ] ; else if ( RHSBits [ i ] . isZero ( ) ) Bits [ i ] = LHSBits [ i ] ; else { AllDisjoint = false ; break ; } if ( Bits [ i ] . hasValue ( ) ) { LastVal = Bits [ i ] . getValue ( ) ; LastIdx = Bits [ i ] . getValueBitIndex ( ) ; } else {


<s> else if ( <STR_LIT> ( Op . getNode ( ) ) || <STR_LIT> ( Op . getNode ( ) ) ) { if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue WrapperOp = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( WrapperOp ) ) if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CP -> getConstVal ( ) ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ;


<s> } else { DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Register , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> << printReg ( NewRegister , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; O . setReg ( NewRegister ) ; } } PHIInfo . deleteDef ( Register ) ;

getRegionMRT ( ) -> replaceLiveOutReg ( Register , NewRegister ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( unsigned ( getMSRMask ( ) ) ) ) ;


<s> } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; printOperand ( MI , Op + <NUM_LIT> , O , Modifier , AsmVariant ) ; NeedPlus = true ; } assert ( DispSpec . isImm ( ) && <STR_LIT> ) ; int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) { if ( NeedPlus ) { if ( DispVal > <NUM_LIT> ) O << <STR_LIT> ;


<s> ~ <ISA_LIT>Disassembler ( ) override {


<s> if ( FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( ImmOffset ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( ImmOffset , Ctx ) , Ctx ) ; Fixups . push_back ( MCFixup :: Create ( CurByte , Expr , FixupKind ) ) ; EmitConstant ( <NUM_LIT> , Size , CurByte , OS ) ;


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override {


<s> return nullptr ; } const TargetRegisterClass * DstRC = getRegClassForTypeOnBank ( ScalarTy , DstRB , RBI , true ) ; if ( ! DstRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } const RegisterBank & VecRB = * RBI . getRegBank ( VecReg , MRI , TRI ) ; const LLT & VecTy = MRI . getType ( VecReg ) ; const TargetRegisterClass * VecRC = getRegClassForTypeOnBank ( VecTy , VecRB , RBI , true ) ; if ( ! VecRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } unsigned InsertReg = VecReg ; if ( ! DstReg ) DstReg = MRI . createVirtualRegister ( DstRC ) ; if ( LaneIdx == <NUM_LIT> ) { auto Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , { * DstReg } , { } ) . addReg ( VecReg , <NUM_LIT> , ExtractSubReg ) ; RBI . constrainGenericRegister ( * DstReg , * DstRC , MRI ) ;


<s> } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = <ISA_LIT>FrameInfo :: getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ;

MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ;


<s> op0 = force_reg ( Pmode , op0 ) ; op1 = force_reg ( Pmode , op1 ) ; if ( REG_POINTER ( op1 ) ) std :: swap ( op0 , op1 ) ; if ( virt_or_elim_regno_p ( REGNO ( op0 ) ) ) { base = expand_binop ( Pmode , add_optab , op0 , offset_rtx , NULL_RTX , true , OPTAB_DIRECT ) ; return gen_rtx_PLUS ( Pmode , base , op1 ) ; } base = expand_binop ( Pmode , add_optab , op0 , op1 , NULL_RTX , true , OPTAB_DIRECT ) ; x = gen_rtx_PLUS ( Pmode , base , offset_rtx ) ; } HOST_WIDE_INT size ; if ( GET_MODE_SIZE ( mode ) . is_constant ( & size ) ) { HOST_WIDE_INT base_offset = aarch64_anchor_offset ( offset , size , mode ) ;


<s> SDValue CmpOp = getSelectableIntSetCC ( LHS , RHS , CC , A64cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , CmpOp , A64cc , DestBB ) ; } <STR_LIT> CondCode , Alternative = <STR_LIT> ; CondCode = FPCCToA64CC ( CC , Alternative ) ; SDValue A64cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , DAG . getCondCode ( CC ) ) ; SDValue A64BR_CC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , SetCC , A64cc , DestBB ) ; if ( Alternative != <STR_LIT> ) { A64cc = DAG . getConstant ( Alternative , <STR_LIT> ) ; A64BR_CC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A64BR_CC , SetCC , A64cc , DestBB ) ; } return A64BR_CC ;


<s> assert ( HalfMask . size ( ) == HalfNumElts && <STR_LIT> ) ; unsigned NumLowerHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; unsigned NumUpperHalves = ( HalfIdx1 == <NUM_LIT> || HalfIdx1 == <NUM_LIT> ) + ( HalfIdx2 == <NUM_LIT> || HalfIdx2 == <NUM_LIT> ) ; assert ( NumLowerHalves + NumUpperHalves <= <NUM_LIT> && <STR_LIT> ) ; unsigned EltWidth = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! UndefLower ) { if ( NumUpperHalves == <NUM_LIT> ) return getShuffleHalfVectors ( DL , V1 , V2 , HalfMask , HalfIdx1 , HalfIdx2 , UndefLower , DAG ) ; if ( NumUpperHalves == <NUM_LIT> ) { if ( Subtarget . hasAVX2 ( ) ) { if ( EltWidth == <NUM_LIT> && NumLowerHalves && HalfVT . is128BitVector ( ) && ! is128BitUnpackShuffleMask ( HalfMask ) && ( ! isSingleSHUFPSMask ( HalfMask ) || Subtarget . hasFastVariableCrossLaneShuffle ( ) ) ) return SDValue ( ) ; if ( EltWidth == <NUM_LIT> && V2 . isUndef ( ) ) return SDValue ( ) ; } if ( Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) ) return SDValue ( ) ; return getShuffleHalfVectors ( DL , V1 , V2 , HalfMask , HalfIdx1 , HalfIdx2 , UndefLower , DAG ) ; } assert ( NumUpperHalves == <NUM_LIT> && <STR_LIT> ) ; return SDValue ( ) ; } if ( NumUpperHalves == <NUM_LIT> ) {

if ( Subtarget . hasAVX2 ( ) && EltWidth == <NUM_LIT> ) return SDValue ( ) ;


<s> unsigned getFGRH32Reg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_FGR ) && <STR_LIT> ) ; return RegIdx . RegInfo -> getRegClass ( <STR_LIT> ) . getRegister ( RegIdx . Index ) ;


<s> for ( unsigned OpIdx = <NUM_LIT> , EndIdx = Instr . getNumOperands ( ) ; OpIdx < EndIdx ; ++ OpIdx ) { MachineOperand & MO = Instr . getOperand ( OpIdx ) ; const TargetRegisterClass * OpRegCstraints = Instr . getRegClassConstraint ( OpIdx , TII , TRI ) ; if ( ! OpRegCstraints ) continue ; if ( MO . isFI ( ) ) continue ; assert ( MO . isReg ( ) && <STR_LIT> ) ; Register Reg = MO . getReg ( ) ;

if ( Register :: isPhysicalRegister ( Reg ) ) {


<s> return MO . getSubReg ( ) == <NUM_LIT> ? MRI -> getMaxLaneMaskForVReg ( MO . getReg ( ) ) : MRI -> getTargetRegisterInfo ( ) -> getSubRegIndexLaneMask ( MO . getSubReg ( ) ) ;


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>InstrInfo :: getRegisterInfo ( ) const { return RI ;


<s> } if ( MaskRegClassContains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { SrcReg = get<ISA_LIT>SubSuperRegister ( SrcReg , <NUM_LIT> ) ; return <STR_LIT> ; } return <NUM_LIT> ;


<s> while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; switch ( MBBI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : expandStore ( MF , MBBI ) ; Expanded = true ; break ; case <STR_LIT> : expandCTLZ ( MF , MBBI ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ;

return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> return II -> getRegisterInfo ( ) . get<ISA_LIT>RegNum ( RegNo ) ;


<s> static std :: pair < Value * , Value * > getShape ( PHINode * Phi ) { Use & U = * ( Phi -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; User * V = U . getUser ( ) ; while ( V ) { if ( isAMXCast ( dyn_cast < Instruction > ( V ) ) ) { if ( V -> use_empty ( ) ) break ; Use & U = * ( V -> use_begin ( ) ) ;


<s> if ( GET_CODE ( op0 ) == SIGN_EXTEND ) return false ; if ( GET_CODE ( x ) == ASHIFT && CONST_INT_P ( op1 ) && UINTVAL ( op1 ) <= <NUM_LIT> ) return true ; if ( GET_CODE ( x ) != MULT || ! CONST_INT_P ( op1 ) ) return false ; HOST_WIDE_INT l2 = exact_log2 ( INTVAL ( op1 ) ) ; if ( l2 > <NUM_LIT> && l2 <= <NUM_LIT> ) return true ;


<s> if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; BaseReg = & LdSt . getOperand ( <NUM_LIT> ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ;


<s> pa_file_start_level ( ) ; pa_file_start_space ( <NUM_LIT> ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getCFInstrCost ( unsigned Opcode , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( CostKind != TTI :: TCK_RecipThroughput ) return Opcode == Instruction :: PHI ? <NUM_LIT> : <NUM_LIT> ;


<s> lowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , Size ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ;

SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP , ArgAdjust ) ;


<s> if ( SubIdx == AMDGPU :: sub1 ) return MachineOperand :: CreateImm ( Op . getImm ( ) >> <NUM_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; }

unsigned SubReg = buildExtractSubReg ( MII , MRI , Op , SuperRC , SubIdx , SubRC ) ;


<s> Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Amp ) || getLexer ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ; int CntShift ; int CntMask ; if ( CntName == <STR_LIT> ) { CntMask = <NUM_LIT> ; CntShift = <NUM_LIT> ; } else if ( CntName == <STR_LIT> ) { CntMask = <NUM_LIT> ; CntShift = <NUM_LIT> ; } else if ( CntName == <STR_LIT> ) { CntMask = <NUM_LIT> ;


<s> return ggc_cleared_alloc < machine_function > ( ) ;


<s> assert ( Kind == OpKind :: Comparison && <STR_LIT> ) ;


<s> if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ;


<s> static const struct { const HOST_WIDE_INT no_flag ; const HOST_WIDE_INT dep_flags ; const char * const name ; } flags [ ] = { { OPTION_MASK_POWER10 , OTHER_POWER10_MASKS , <STR_LIT> } , { OPTION_MASK_P9_VECTOR , OTHER_P9_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_P8_VECTOR , OTHER_P8_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_VSX , OTHER_VSX_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_ALTIVEC , OTHER_ALTIVEC_MASKS , <STR_LIT> } , } ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( flags ) ; i ++ ) { HOST_WIDE_INT no_flag = flags [ i ] . no_flag ;

if ( ( rs6000_isa_flags & no_flag ) == <NUM_LIT> && ( rs6000_isa_flags_explicit & no_flag ) != <NUM_LIT> ) {


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( class AsmPrinter & asmprinter ) : Printer ( asmprinter ) {


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken ) {


<s> static bool frv_pack_insn_p ( rtx insn ) { if ( frv_packet . num_insns == frv_packet . issue_rate ) return false ; if ( frv_packet . num_insns > <NUM_LIT> && GET_CODE ( insn ) == INSN && GET_MODE ( insn ) == TImode && GET_CODE ( PATTERN ( insn ) ) != COND_EXEC ) return false ; if ( get_attr_type ( insn ) != TYPE_SETLO ) if ( frv_registers_conflict_p ( PATTERN ( insn ) ) ) return false ;

return state_transition ( frv_packet . dfa_state , insn ) < <NUM_LIT> ;


<s> case CODE_FOR_nvptx_forked : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , <NUM_LIT> , <NUM_LIT> ) ) ; gcc_assert ( mask ) ; par = new parallel ( par , mask ) ; par -> forked_block = block ; par -> forked_insn = end ; if ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) && ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) ) par -> fork_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_fork ) ; } break ; case CODE_FOR_nvptx_join : { unsigned mask = UINTVAL ( XVECEXP ( PATTERN ( end ) , <NUM_LIT> , <NUM_LIT> ) ) ; gcc_assert ( par -> mask == mask ) ; par -> join_block = block ; par -> join_insn = end ; if ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) && ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) ) par -> joining_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_joining ) ; par = par -> parent ; } break ; default : gcc_unreachable ( ) ; } }

if ( par ) par -> blocks . safe_push ( block ) ;


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo ;


<s> is_weak = ( operands [ <NUM_LIT> ] != const0_rtx ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; scratch = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( mod_s == MEMMODEL_RELAXED || mod_s == MEMMODEL_CONSUME || mod_s == MEMMODEL_RELEASE ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( mod_s == MEMMODEL_RELAXED || mod_s == MEMMODEL_CONSUME || mod_s == MEMMODEL_ACQUIRE ) ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; cond = arm_gen_compare_reg ( NE , rval , oldval , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; arm_emit_store_exclusive ( mode , scratch , mem , newval , use_release ) ;

cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ;


<s> int PIdx = MI -> findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> && MI -> getOperand ( PIdx ) . getImm ( ) != <STR_LIT> ;


<s> void <ISA_LIT>TargetLowering :: VarArgStyleRegisters ( CCState & CCInfo , SelectionDAG & DAG , SDLoc dl , SDValue & Chain , unsigned ArgOffset , bool ForceMutable ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ;

<ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> while ( GET_CODE ( x ) == SUBREG ) x = XEXP ( x , <NUM_LIT> ) ; return ( GET_CODE ( x ) == REG && CR_REGNO_P ( REGNO ( x ) ) ) ;


<s> return getTargetMachine ( ) . getInstrInfo ( ) ;


<s> ElemSize esize = Opcode == <STR_LIT> ? ESize32 : ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ? ESize16 : ESize32 ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeNEONRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( decodeNVLaneOpIndex ( insn , esize ) ) ) ; NumOpsAdded = <NUM_LIT> ;


<s> bool constant_address_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case LABEL_REF : case CONST_INT : case HIGH : return true ; case CONST : if ( flag_pic && pic_address_needs_scratch ( x ) ) return false ; return sparc_legitimate_constant_p ( Pmode , x ) ; case SYMBOL_REF : return ! flag_pic && sparc_legitimate_constant_p ( Pmode , x ) ;


<s> case Integer : OS << <STR_LIT> << Int . Val ; break ; case Float : OS << <STR_LIT> << Flt . Val ; break ; case Symbol : OS << <STR_LIT> << Sym . Exp ; break ; case BrList : OS << <STR_LIT> << BrL . List . size ( ) ;


<s> bool SpillToSMEM = spillSGPRToSMEM ( ) ; if ( SpillToSMEM && OnlyToVGPR ) return false ; Register FrameReg = getFrameRegister ( * MF ) ; assert ( SpillToVGPR || ( SuperReg != MFI -> getStackPtrOffsetReg ( ) && SuperReg != MFI -> getFrameOffsetReg ( ) && SuperReg != MFI -> getScratchWaveOffsetReg ( ) ) ) ; assert ( SuperReg != <STR_LIT> && <STR_LIT> ) ; unsigned OffsetReg = <STR_LIT> ; unsigned M0CopyReg = <STR_LIT> ; if ( SpillToSMEM ) { if ( RS -> isRegUsed ( <STR_LIT> ) ) { M0CopyReg = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> , false ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , M0CopyReg ) . addReg ( <STR_LIT> ) ; } } unsigned ScalarStoreOp ; unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; if ( SpillToSMEM && isSGPRClass ( RC ) ) { std :: tie ( EltSize , ScalarStoreOp ) = getSpillEltSize ( getRegSizeInBits ( * RC ) / <NUM_LIT> , true ) ; } ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; Register TmpVGPR ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; if ( SpillToSMEM ) { int64_t FrOffset = FrameInfo . getObjectOffset ( Index ) ; unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , EltSize , MinAlign ( Align , EltSize * i ) ) ; int64_t Offset = ( ST . getWavefrontSize ( ) * FrOffset ) + ( EltSize * i ) ; if ( Offset != <NUM_LIT> ) {

BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addReg ( FrameReg ) . addImm ( Offset ) ;


<s> case <ISA_LIT>InstrInfo :: MO_GOTPCREL : return MCSymbolRefExpr :: VK_GOTPCREL ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL32_LO : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_LO ; case <ISA_LIT>InstrInfo :: MO_GOTPCREL32_HI : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_HI ; case <ISA_LIT>InstrInfo :: MO_REL32_LO :

return MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_LO ;


<s> SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SaveCount = <NUM_LIT> ; break ; } } if ( I < SaveCount ) { Saved [ I ++ ] = Inst ; if ( I < SaveCount ) return true ; } if ( SaveCount > <NUM_LIT> ) { assert ( I == SaveCount && <STR_LIT> ) ; SaveCount = <NUM_LIT> ; RecurseGuard = true ; switch ( Saved [ <NUM_LIT> ] . getOpcode ( ) ) { default : break ; case <STR_LIT> : EmitDataMask ( I , Saved , Out ) ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : EmitDirectGuardCall ( I , Saved , Out ) ; break ; case <STR_LIT> :

EmitIndirectGuardCall ( I , Saved , Out ) ;


<s> return ( int16x4_t ) __builtin_neon_vqrdmulh_nv4hi ( __a , ( __builtin_neon_hi ) __b ) ;


<s> const TargetInstrInfo * TII = STI -> getInstrInfo ( ) ; const DebugLoc & DL = VAStartPseudoInstr -> getDebugLoc ( ) ; Register CountReg = VAStartPseudoInstr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; LivePhysRegs LiveRegs ( * STI -> getRegisterInfo ( ) ) ; SmallVector < std :: pair < MCPhysReg , const MachineOperand * > , <NUM_LIT> > Clobbers ; LiveRegs . addLiveIns ( * EntryBlk ) ; for ( MachineInstr & MI : EntryBlk -> instrs ( ) ) { if ( MI . getOpcode ( ) == VAStartPseudoInstr -> getOpcode ( ) ) break ; LiveRegs . stepForward ( MI , Clobbers ) ; } const BasicBlock * LLVMBlk = EntryBlk -> getBasicBlock ( ) ; MachineFunction :: iterator EntryBlkIter = ++ EntryBlk -> getIterator ( ) ; MachineBasicBlock * GuardedRegsBlk = Func -> CreateMachineBasicBlock ( LLVMBlk ) ; MachineBasicBlock * TailBlk = Func -> CreateMachineBasicBlock ( LLVMBlk ) ; Func -> insert ( EntryBlkIter , GuardedRegsBlk ) ; Func -> insert ( EntryBlkIter , TailBlk ) ; TailBlk -> splice ( TailBlk -> begin ( ) , EntryBlk , std :: next ( MachineBasicBlock :: iterator ( VAStartPseudoInstr ) ) , EntryBlk -> end ( ) ) ; TailBlk -> transferSuccessorsAndUpdatePHIs ( EntryBlk ) ; uint64_t FrameOffset = VAStartPseudoInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t VarArgsRegsOffset = VAStartPseudoInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ;

unsigned MOVOpc = STI -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ;


<s> int base0 ; int base1 ; int incdec0 ; int incdec1 ; int index0 ; int index1 ; int disp0 ; int disp1 ; if ( MEM_VOLATILE_P ( op0 ) && MEM_VOLATILE_P ( op1 ) ) return <NUM_LIT> ; c4x_S_address_parse ( op0 , & base0 , & incdec0 , & index0 , & disp0 ) ;


<s> int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int SrcReg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int SrcReg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != SrcReg1 ) { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SrcReg1 ) ; } if ( DestReg != SrcReg2 ) { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SrcReg2 ) ; } MII = MBB -> erase ( MI ) ; -- MII ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int SrcReg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Immed1 = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int Immed2 = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg1 ) . addImm ( Immed1 ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg1 ) . addImm ( Immed2 ) ; MII = MBB -> erase ( MI ) ; -- MII ; } } } return true ;


<s> return __builtin_mve_vcmpneq_n_uv4si ( __a , __b ) ;


<s> assert ( Kind == Register && <STR_LIT> ) ; return Reg . RegNo ;


<s> void chksetELFHeaderEFlags ( unsigned flags ) {

if ( getAssembler ( ) ) getAssembler ( ) -> setELFHeaderEFlags ( flags ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parsePCRel ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , int64_t MinVal , int64_t MaxVal ) { MCContext & Ctx = getContext ( ) ; MCStreamer & Out = getStreamer ( ) ; const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . CreateTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: CreateAdd ( Base , Expr , Ctx ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ;


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * ) const { if ( hasFP ( MF ) ) { int FrameIdx = MF . getFrameInfo ( ) . CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> , true ) ; ( void ) FrameIdx ; assert ( FrameIdx == MF . getFrameInfo ( ) . getObjectIndexBegin ( ) && <STR_LIT> ) ;


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { StringRef CPUName = CPU ;

if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ;


<s> static __inline qword si_lqr ( unsigned int imm ) {

return ( ( qword ) ( vec_ld ( <NUM_LIT> , ( vector unsigned char * ) ( imm ) ) ) ) ;


<s> auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const <ISA_LIT>TargetMachine & TM = TPC -> getTM < <ISA_LIT>TargetMachine > ( ) ; ST = & TM . getSubtarget < GCNSubtarget > ( F ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ;

HasUnsafeFPMath = hasUnsafeFPMath ( F ) ;


<s> } if ( GET_CODE ( operand ) != MEM ) return <NUM_LIT> ; operand = XEXP ( operand , <NUM_LIT> ) ;


<s> AsmPrinter :: emitFunctionEntryLabel ( ) ; return ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const GCNSubtarget & STM = MF -> getSubtarget < GCNSubtarget > ( ) ;

if ( MFI -> isEntryFunction ( ) && STM . isAmdHsaOrMesa ( MF -> getFunction ( ) ) ) {


<s> TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToAddr ( MachineFunction & MF , unsigned SrcReg , bool isKill , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , MachineInstr :: mmo_iterator MMOBegin , MachineInstr :: mmo_iterator MMOEnd , SmallVectorImpl < MachineInstr * > & NewMIs ) const { unsigned Alignment = ( RC -> getSize ( ) / <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; bool isAligned = MMOBegin != MMOEnd && ( * MMOBegin ) -> getAlignment ( ) >= Alignment ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL ;

MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ;


<s> if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasMed3_16 ( ) ) ) { SDValue Var = Op0 . getOperand ( <NUM_LIT> ) ; if ( ! isKnownNeverSNan ( DAG , Var ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SL , K0 -> getValueType ( <NUM_LIT> ) , Var , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ;


<s> unsigned last_fixed_arg = ArgLocs . size ( ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ArgLocs . size ( ) ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; EVT ObjectVT = VA . getValVT ( ) ; switch ( ObjectVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Ins [ i ] . Used && ( ! isVarArg || i != last_fixed_arg ) ) { if ( arg_idx < <NUM_LIT> ) arg_idx ++ ; else stack_offset += <NUM_LIT> ; InVals . push_back ( DAG . getUNDEF ( ObjectVT ) ) ; } else if ( arg_idx < <NUM_LIT> && ( ! isVarArg || i != last_fixed_arg ) ) { unsigned arg_reg = VA . getLocReg ( ) ; reg = RegInfo . createVirtualRegister ( & GPRegsRegClass ) ; MF . getRegInfo ( ) . addLiveIn ( arg_reg , reg ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , dl , reg , <STR_LIT> ) ; if ( ObjectVT != <STR_LIT> ) {

Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getValueType ( ObjectVT ) ) ;


<s> return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT> ; case TargetOpcode :: G_SDIV : return <STR_LIT> ; case TargetOpcode :: G_UDIV : return <STR_LIT> ; default : return GenericOpc ; } } case <STR_LIT> : switch ( OpSize ) { case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT> ; case TargetOpcode :: G_FDIV : return <STR_LIT> ; default : return GenericOpc ; } case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL :


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrRRI12 ( SDValue Op , SDValue Addr , SDValue & Base , SDValue & Disp , SDValue & Index ) { <ISA_LIT>RRIAddressMode AM20 , AM12 ; bool Done = false ; if ( ! Addr . hasOneUse ( ) ) { unsigned Opcode = Addr . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM12 ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr , AM12 , true ) ) return false ; if ( ! Done && ! MatchAddress ( Addr , AM20 , false ) ) if ( AM12 . Disp == <NUM_LIT> && AM20 . Disp != <NUM_LIT> ) return false ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> ; DEBUG ( AM12 . dump ( ) ) ;


<s> case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return lowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ;

case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op , Subtarget , DAG ) ;


<s> if ( Subtarget . is64Bit ( ) ) { if ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) setRelocationModel ( Reloc :: PIC_ ) ; if ( getCodeModel ( ) == CodeModel :: Default ) setCodeModel ( CodeModel :: Small ) ; } if ( Subtarget . isTargetCygMing ( ) ) Subtarget . setPICStyle ( PICStyles :: WinPIC ) ; else if ( Subtarget . isTargetDarwin ( ) ) { if ( Subtarget . is64Bit ( ) ) Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; else Subtarget . setPICStyle ( PICStyles :: Stub ) ; } else if ( Subtarget . isTargetELF ( ) ) { if ( Subtarget . is64Bit ( ) ) Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; else Subtarget . setPICStyle ( PICStyles :: GOT ) ; }


<s> Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = llvm :: <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ;

Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ;


<s> if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align - <NUM_LIT> ) ; unsigned ListTmp = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildGEP ( ListTmp , List , AlignMinus1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DstPtr = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildPtrMask ( DstPtr , ListTmp , Log2_64 ( Align ) ) ; } else DstPtr = List ; uint64_t ValSize = MRI . getType ( Dst ) . getSizeInBits ( ) / <NUM_LIT> ;

MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValSize , std :: max ( Align , PtrSize ) ) ) ;


<s> if ( SDValue V = combineShiftToPMULH ( N , DAG , Subtarget ) ) return V ; if ( ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; auto * ShiftC = dyn_cast < ConstantSDNode > ( N1 ) ; auto * AndC = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! ShiftC || ! AndC ) return SDValue ( ) ; APInt MaskVal = AndC -> getAPIntValue ( ) ; if ( MaskVal . isMask ( ) ) { unsigned TO = MaskVal . countTrailingOnes ( ) ; if ( TO >= <NUM_LIT> && isPowerOf2_32 ( TO ) ) return SDValue ( ) ; } APInt NewMaskVal = MaskVal . lshr ( ShiftC -> getAPIntValue ( ) ) ; unsigned OldMaskSize = MaskVal . getMinSignedBits ( ) ; unsigned NewMaskSize = NewMaskVal . getMinSignedBits ( ) ; if ( ( OldMaskSize > <NUM_LIT> && NewMaskSize <= <NUM_LIT> ) || ( OldMaskSize > <NUM_LIT> && NewMaskSize <= <NUM_LIT> ) ) { SDLoc DL ( N ) ; SDValue NewMask = DAG . getConstant ( NewMaskVal , DL , VT ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NewShift , NewMask ) ;


<s> for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) { bool FoundIt = false ; for ( MBBI = I -> end ( ) ; MBBI != I -> begin ( ) ; ) { -- MBBI ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { MBBI -> eraseFromParent ( ) ; FoundIt = true ; break ; }


<s> <ISA_LIT>64TargetMachine :: <ISA_LIT>64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> unsigned CC ; if ( ! ITBlock . empty ( ) ) { CC = ITBlock . back ( ) ; ITBlock . pop_back ( ) ; } else CC = <STR_LIT> ; const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; MCInst :: iterator I = MI . begin ( ) ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( OpInfo [ i ] . isPredicate ( ) ) { I -> setImm ( CC ) ;


<s> if ( ! Val -> hasName ( ) ) Val -> setName ( ( Twine ( getSFName ( SF ) ) + <STR_LIT> + utostr ( SFAssignments [ SF ] ++ ) ) . str ( ) ) ;


<s> report_fatal_error ( <STR_LIT> + MBB . getParent ( ) -> getName ( ) + <STR_LIT> , false ) ; } DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; if ( RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> __asm volatile ( <STR_LIT> : : <STR_LIT> ( fg ) ) ;


<s> virtual void PrintSwitchToSection ( const MCAsmInfo & MAI , raw_ostream & OS ) const {


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , CSI [ i ] . getReg ( ) ) ; return true ;


<s> loc = opint [ <NUM_LIT> ] & <NUM_LIT> ; if ( BYTES_BIG_ENDIAN ) loc ^= <NUM_LIT> ; bytemask <<= loc ; temp = opint [ <NUM_LIT> ] ; if ( is_high ) { byteloc = ( <NUM_LIT> - ( loc * <NUM_LIT> ) ) & <NUM_LIT> ; if ( byteloc == <NUM_LIT> ) zap_op = op ; else temp >>= byteloc ; bytemask >>= <NUM_LIT> ; } else {


<s> if ( ObjectSize == <NUM_LIT> ) SortingObjects [ Obj ] . ObjectSize = <NUM_LIT> ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= <NUM_LIT> && Index < MFI -> getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , <ISA_LIT>FrameSortingComparator ( ) ) ; int i = <NUM_LIT> ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ;

ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ;


<s> virtual EVT getSetCCResultType ( EVT VT ) const { return <STR_LIT> ;


<s> static void demoteInst ( MCInst & Inst , const MCInstrInfo & InstInfo ) { unsigned NewOpc = demoteOpcode ( Inst . getOpcode ( ) ) ; Inst . setOpcode ( NewOpc ) ;

const MCOperandInfo * OpInfo = InstInfo . get ( Inst . getOpcode ( ) ) . OpInfo ;


<s> const MCExpr * EVal ; switch ( getLexer ( ) . getKind ( ) ) { default : return true ; case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : if ( getParser ( ) . parseExpression ( EVal ) ) return true ; Operands . push_back ( <STR_LIT> ( EVal , S , E ) ) ; return false ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSIGN_EXTEND ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op -> getValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; EVT InVT = In . getValueType ( ) ; DebugLoc dl = Op -> getDebugLoc ( ) ; if ( ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask2 [ <NUM_LIT> ] ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getScalarType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpHi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpHi ) ;


<s> LLVMContext * Context = DAG . getContext ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; Constant * C = ConstantInt :: get ( * Context , MaskElt ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; if ( VT . isVector ( ) ) { MVT VecVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ;

SDValue MaskCasted = DAG . getBitcast ( VecVT , Mask ) ;


<s> SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ;

MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ;


<s> static __inline__ double __fnmadd ( double x , double y , double z ) { double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ;


<s> p = ( struct export_list * ) ggc_alloc ( sizeof * p ) ;


<s> static SDValue PromoteMVEPredVector ( SDLoc dl , SDValue Pred , EVT VT , SelectionDAG & DAG ) { SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue AllZeroes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , dl , <STR_LIT> ) ;

AllZeroes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllZeroes ) ;


<s> void <ISA_LIT>FunctionInfo :: initializeBaseYamlFields ( const yaml :: <ISA_LIT>FunctionInfo & YamlMFI ) { CFGStackified = YamlMFI . CFGStackified ;


<s> if ( cfun -> machine -> split_stack_argp_used ) add_to_hard_reg_set ( & set -> set , Pmode , <NUM_LIT> ) ;


<s> if ( I -> getName ( ) . startswith ( <STR_LIT> ) || I -> getName ( ) . startswith ( <STR_LIT> ) ) continue ; if ( TD -> getTypeAllocSize ( I -> getType ( ) -> getElementType ( ) ) < MaxOffset ) { const TargetLoweringObjectFile & TLOF = TLI -> getObjFileLowering ( ) ; if ( TLOF . getKindForGlobal ( I , TLI -> getTargetMachine ( ) ) . isBSSLocal ( ) ) BSSGlobals . push_back ( I ) ; else if ( I -> isConstant ( ) ) ConstGlobals . push_back ( I ) ; else Globals . push_back ( I ) ; } } if ( Globals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( Globals , M , false ) ; if ( BSSGlobals . size ( ) > <NUM_LIT> ) Changed |= doMerge ( BSSGlobals , M , false ) ;


<s> unsigned Kind = Fixup . getTargetKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return Kind - FirstLiteralRelocationKind ;


<s> RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> hasAVX512 ( ) ) ; Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ;


<s> EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType ( <NUM_LIT> ) , Ops ) ;


<s> MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ;


<s> static bool aarch64_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SIMD && ( mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V2DImode || mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == V2SFmode || mode == V4SFmode || mode == V2DFmode || mode == V1DFmode ) ) return true ;


<s> SmallVector < Type * , <NUM_LIT> > ArgTys ; Value * Callee = CI -> getCalledValue ( ) ; FunctionType * CalleeFTy ; if ( auto * F = dyn_cast < Function > ( Callee ) ) CalleeFTy = F -> getFunctionType ( ) ; else { auto * CalleeTy = cast < PointerType > ( Callee -> getType ( ) ) -> getElementType ( ) ; CalleeFTy = cast < FunctionType > ( CalleeTy ) ; } std :: string Sig = getSignature ( CalleeFTy ) ; if ( InvokeWrappers . find ( Sig ) != InvokeWrappers . end ( ) ) return InvokeWrappers [ Sig ] ; ArgTys . push_back ( PointerType :: getUnqual ( CalleeFTy ) ) ;

ArgTys . append ( CalleeFTy -> param_begin ( ) , CalleeFTy -> param_end ( ) ) ;


<s> bool atInsnStart = true ; unsigned Length = <NUM_LIT> ; const unsigned MaxInstLength = MAI . getMaxInstLength ( STI ) ; for ( ; * Str ; ++ Str ) { if ( * Str == '\n' || strncmp ( Str , MAI . getSeparatorString ( ) , strlen ( MAI . getSeparatorString ( ) ) ) == <NUM_LIT> ) atInsnStart = true ; if ( atInsnStart && ! isSpace ( static_cast < unsigned char > ( * Str ) ) ) { Length += MaxInstLength ; atInsnStart = false ; } if ( atInsnStart && strncmp ( Str , MAI . getCommentString ( ) . data ( ) , MAI . getCommentString ( ) . size ( ) ) == <NUM_LIT> ) atInsnStart = false ;


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const {

<STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> const MCExpr * getConstantPoolImm ( ) const { assert ( isConstantPoolImm ( ) && <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isHWTrueValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) {

return CFP -> isExactlyValue ( <NUM_LIT> ) ;


<s> static SDValue PerformShiftCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSHLCombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) != <STR_LIT> ) if ( SDValue V = performShiftToAllZeros ( N , DAG , Subtarget ) ) return V ;


<s> EncodeAddrModeOpValues ( const MCInst & MI , unsigned OpIdx , unsigned & Reg , unsigned & Imm , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ;

Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


<s> unsigned int end_bitpos = start_bitpos + align ; switch ( kind ) { case BPF_RELO_FIELD_BYTE_OFFSET : { if ( var_off != NULL_TREE ) { error_at ( loc , <STR_LIT> ) ; return error_mark_node ; } if ( bitfieldp ) result = start_bitpos / <NUM_LIT> ; else result = bitpos / <NUM_LIT> ; } break ; case BPF_RELO_FIELD_BYTE_SIZE : { if ( mode == BLKmode && bitsize == - <NUM_LIT> ) { error_at ( loc , <STR_LIT> ) ; return error_mark_node ; } if ( bitfieldp ) { result = end_bitpos - start_bitpos ; if ( result & ( result - <NUM_LIT> ) ) { error_at ( loc , <STR_LIT> ) ; return error_mark_node ; } result = result / <NUM_LIT> ; } else result = bitsize / <NUM_LIT> ; } break ; case BPF_RELO_FIELD_EXISTS : result = <NUM_LIT> ; break ; case BPF_RELO_FIELD_SIGNED : result = ! unsignedp ; break ; case BPF_RELO_FIELD_LSHIFT_U64 : case BPF_RELO_FIELD_RSHIFT_U64 : { if ( mode == BLKmode && bitsize == - <NUM_LIT> ) { error_at ( loc , <STR_LIT> ) ; return error_mark_node ; } if ( var_off != NULL_TREE ) { error_at ( loc , <STR_LIT> ) ; return error_mark_node ; } if ( ! bitfieldp ) { if ( bitsize > <NUM_LIT> ) { error_at ( loc , <STR_LIT> ) ; return error_mark_node ; } result = <NUM_LIT> - bitsize ; break ; } if ( end_bitpos - start_bitpos > <NUM_LIT> ) {


<s> unsigned StoreSize = VT . getStoreSizeInBits ( ) ; if ( StoreSize <= <NUM_LIT> ) return EVT :: getIntegerVT ( Ctx , StoreSize ) ; assert ( StoreSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ;

return EVT :: getVectorVT ( Ctx , <STR_LIT> , StoreSize / <NUM_LIT> ) ;


<s> return __builtin_aarch64_crypto_pmulldi_ppp ( a , b ) ;


<s> unsigned getMemDefaultBaseReg ( ) const {

assert ( Kind == Memory && <STR_LIT> ) ;


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ISBarrierID ; if ( getParser ( ) . parseExpression ( ISBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ISBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val & ~ <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; }


<s> if ( mcore_dllexport_name_p ( oldname ) ) return ; newname = alloca ( strlen ( oldname ) + <NUM_LIT> ) ; sprintf ( newname , <STR_LIT> , oldname ) ; idp = get_identifier ( newname ) ; XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) = gen_rtx_SYMBOL_REF ( Pmode , IDENTIFIER_POINTER ( idp ) ) ;


<s> Reg = mapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits ( ) , IsValidSpecialReg ) ; if ( IsValidSpecialReg ) return CurDAG -> getMachineNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> enum { N = <NUM_LIT> , Z = <NUM_LIT> , C = <NUM_LIT> , V = <NUM_LIT> } ; switch ( Code ) { default : llvm_unreachable ( <STR_LIT> ) ; case EQ : return Z ; case NE : return <NUM_LIT> ; case HS : return C ; case LO : return <NUM_LIT> ; case MI : return N ; case PL : return <NUM_LIT> ; case VS : return V ; case VC : return <NUM_LIT> ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool RelaxAll ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ;

if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ;


<s> void <ISA_LIT>16FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( STI . getInstrInfo ( ) ) ; TII . adjustStackPtr ( <STR_LIT> , Amount , MBB , I ) ; }


return overlaps_hard_reg_set_p ( caller_saved_set , mode , regno ) && overlaps_hard_reg_set_p ( callee_saved_set , mode , regno ) ;


<s> assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> evaluateAsAbsolute ( Address ) ) { O << formatHex ( ( uint64_t ) Address ) ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( <ISA_LIT>AsmPrinter & asmprinter ) : AsmPrinter ( asmprinter ) {


<s> SmallVector < const Value * , <NUM_LIT> > Objs ; if ( getUnderlyingObjects ( MI , Objs ) ) {

for ( SmallVector < const Value * , <NUM_LIT> > :: const_iterator I = Objs . begin ( ) ;


<s> for ( MachineBasicBlock :: instr_iterator i ( MBB -> instr_begin ( ) ) , ie ( MBB -> instr_end ( ) ) ; i != ie ; i ++ ) {

if ( PTM . getInstrInfo ( ) -> hasCall ( & * i ) ) return true ;


<s> static inline bool isImmU6 ( unsigned val ) { return val < ( <NUM_LIT> << <NUM_LIT> ) ;


<s> for ( auto I = PendingQueue . begin ( ) , E = PendingQueue . end ( ) ; I != E ; ) {


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPseudoPass ( ) {


<s> bool <ISA_LIT>TargetLowering :: useLoadStackGuardNode ( ) const {

if ( ! Subtarget -> isTargetAndroid ( ) ) return true ;


<s> MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; BuildMI ( FirstMBB , MBBI , dl , get ( <STR_LIT> ) , GlobalBaseReg ) ; <ISA_LIT>FI -> setGlobalBaseReg ( GlobalBaseReg ) ;


<s> const MCInstrDesc & MCID = MI -> getDesc ( ) ; auto Flags = MachineMemOperand :: MONone ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame . getObjectSize ( FI ) , MFFrame . getObjectAlign ( FI ) ) ;

return MIB . addFrameIndex ( FI ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> <ISA_LIT>DbgInfo ( formatted_raw_ostream & o , const MCAsmInfo * T ) : O ( o ) , MAI ( T ) { CurFile = <STR_LIT> ; CurLine = <NUM_LIT> ; EmitDebugDirectives = false ;


<s> const DataLayout * getDataLayout ( ) const override { return & DL ;


<s> static DecodeStatus decodeRegisterClass ( MCInst & Inst , uint64_t RegNo , const unsigned * Regs ) {

assert ( RegNo < <NUM_LIT> && <STR_LIT> ) ;


<s> std :: vector < std :: string > cmp_b0_b1 ( ) {

return D ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> void <ISA_LIT>CallLowering :: lowerParameter ( MachineIRBuilder & B , ArgInfo & OrigArg , uint64_t Offset , Align Alignment ) const { MachineFunction & MF = B . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; LLT PtrTy = LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; SmallVector < uint64_t > FieldOffsets ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) , & FieldOffsets ) ; unsigned Idx = <NUM_LIT> ; for ( ArgInfo & SplitArg : SplitArgs ) { Register PtrReg = B . getMRI ( ) -> createGenericVirtualRegister ( PtrTy ) ; lowerParameterPtr ( PtrReg , B , Offset + FieldOffsets [ Idx ] ) ; LLT ArgTy = getLLTForType ( * SplitArg . Ty , DL ) ; if ( SplitArg . Flags [ <NUM_LIT> ] . isPointer ( ) ) { LLT PtrTy = LLT :: pointer ( SplitArg . Flags [ <NUM_LIT> ] . getPointerAddrSpace ( ) , ArgTy . getScalarSizeInBits ( ) ) ; ArgTy = ArgTy . isVector ( ) ? LLT :: vector ( ArgTy . getElementCount ( ) , PtrTy ) : PtrTy ; }

MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , ArgTy , commonAlignment ( Alignment , FieldOffsets [ Idx ] ) ) ;


<s> if ( Reg == <STR_LIT> ) { Result . push_back ( std :: make_pair ( Index , <NUM_LIT> ) ) ; } if ( PV . find ( Reg ) != PV . end ( ) ) { Result . push_back ( std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ) ; continue ; } if ( Index > <NUM_LIT> ) { ConstCount ++ ; Result . push_back ( DummyPair ) ; continue ; } unsigned Chan = RI . getHWRegChan ( Reg ) ; Result . push_back ( std :: make_pair ( Index , Chan ) ) ; }

for ( ; i < <NUM_LIT> ; ++ i ) Result . push_back ( DummyPair ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; int Reg = MatchCoprocessorOperandName ( Tok . getString ( ) , 'c' ) ; if ( Reg == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocReg ( Reg , S ) ) ; return MatchOperand_Success ;


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'd' : case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Has<ISA_LIT>64 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Has<ISA_LIT>64 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( ( VT == <STR_LIT> ) && ( ! Subtarget -> isSingleFloat ( ) ) ) { if ( Subtarget -> isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;


<s> else if ( ShiftName == <STR_LIT> || ShiftName == <STR_LIT> ) St = <STR_LIT> ; else return true ; Parser . Lex ( ) ; if ( St == <STR_LIT> ) return false ; const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getParser ( ) . ParseExpression ( ShiftAmount ) ) return true ;


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) : FastISel ( FuncInfo , LibInfo , true ) { Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( FuncInfo . MF -> getSubtarget ( ) ) ; Context = & FuncInfo . Fn -> getContext ( ) ;


<s> return ( regno == <NUM_LIT> || ( TARGET_FPU && regno == <NUM_LIT> ) ) ;


<s> MCArgs . push_back ( LabelIt -> second ) ; } OutStreamer -> emitLOHDirective ( D . getKind ( ) , MCArgs ) ; MCArgs . clear ( ) ; }


<s> const Function * F = MF . getFunction ( ) ;

unsigned StackAlign = MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddr16 ( SDValue Addr , SDValue & Base , SDValue & Offset ) {


<s> EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; if ( ! IsPIC ) { SDValue Ops [ ] = { JTI } ; HiPart = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> ) ; } else { JTI = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; HiPart = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , JTI , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; }

SDValue JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ;


<s> if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeDataRegsRegisterClass ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeDataRegsRegisterClass ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( const4 ) ) ; status = DecodeDataRegsRegisterClass ( Inst , s3 , Address , Decoder ) ;


<s> static SDValue getTargetVShiftByConstNode ( unsigned Opc , SDLoc dl , MVT VT , SDValue SrcOp , uint64_t ShiftAmt , SelectionDAG & DAG ) { MVT ElementType = VT . getVectorElementType ( ) ; if ( ShiftAmt == <NUM_LIT> ) return SrcOp ; if ( ShiftAmt >= ElementType . getSizeInBits ( ) ) { if ( Opc == <STR_LIT> ) ShiftAmt = ElementType . getSizeInBits ( ) - <NUM_LIT> ; else return DAG . getConstant ( <NUM_LIT> , VT ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; if ( VT == SrcOp . getSimpleValueType ( ) && <STR_LIT> ( SrcOp . getNode ( ) ) ) { SmallVector < SDValue , <NUM_LIT> > Elts ; unsigned NumElts = SrcOp -> getNumOperands ( ) ; ConstantSDNode * ND ; switch ( Opc ) { default : llvm_unreachable ( nullptr ) ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> getOpcode ( ) == <STR_LIT> ) { Elts . push_back ( CurrentOp ) ; continue ;


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( BVN -> isConstant ( ) ) { if ( <ISA_LIT>VectorConstantInfo ( BVN ) . isVectorConstantLegal ( Subtarget ) ) return Op ; return SDValue ( ) ; } if ( SDValue Res = tryBuildVectorShuffle ( DAG , BVN ) ) return Res ; if ( isOperationLegal ( <STR_LIT> , VT ) && isScalarToVector ( Op ) ) return buildScalarToVector ( DAG , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; unsigned NumElements = Op . getNumOperands ( ) ;

SmallVector < SDValue , <STR_LIT> > Ops ( NumElements ) ;


<s> void printJTBlockOperand ( const MCInst * MI , unsigned OpNum ) {


<s> if ( GV -> hasInitializer ( ) ) { if ( GV -> getName ( ) == <STR_LIT> || GV -> getSection ( ) == <STR_LIT> || GV -> hasAvailableExternallyLinkage ( ) || GV -> getName ( ) == <STR_LIT> || GV -> getName ( ) == <STR_LIT> ) return ; } MCSymbol * GVSym = getSymbol ( GV ) ; if ( ! GV -> hasInitializer ( ) ) return ; SectionKind GVKind = TargetLoweringObjectFile :: getKindForGlobal ( GV , TM ) ; const MCSection * TheSection = getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , Mang , TM ) ; OutStreamer . SwitchSectionNoChange ( TheSection ) ;


<s> pos += SUBREG_BYTE ( dst ) * BITS_PER_UNIT ; dst = SUBREG_REG ( dst ) ; } switch ( GET_MODE ( dst ) ) { case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V1TImode : { machine_mode srcmode , dstmode ; rtx ( * pinsr ) ( rtx , rtx , rtx , rtx ) ; rtx d ; if ( ! int_mode_for_size ( size , <NUM_LIT> ) . exists ( & srcmode ) ) return false ; switch ( srcmode ) { case E_QImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V16QImode ; pinsr = gen_sse4_1_pinsrb ; break ; case E_HImode : if ( ! TARGET_SSE2 ) return false ; dstmode = V8HImode ; pinsr = gen_sse2_pinsrw ; break ; case E_SImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V4SImode ; pinsr = gen_sse4_1_pinsrd ; break ; case E_DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; dstmode = V2DImode ; pinsr = gen_sse4_1_pinsrq ; break ; default : return false ; } if ( pos & ( size - <NUM_LIT> ) ) return false ; if ( SUBREG_P ( src ) ) { unsigned int srcpos = SUBREG_BYTE ( src ) ; if ( srcpos > <NUM_LIT> ) { rtx extr_ops [ <NUM_LIT> ] ; extr_ops [ <NUM_LIT> ] = gen_reg_rtx ( srcmode ) ; extr_ops [ <NUM_LIT> ] = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; extr_ops [ <NUM_LIT> ] = GEN_INT ( size ) ; extr_ops [ <NUM_LIT> ] = GEN_INT ( srcpos * BITS_PER_UNIT ) ; if ( ! ix86_expand_pextr ( extr_ops ) ) return false ; src = extr_ops [ <NUM_LIT> ] ; } else src = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; } if ( GET_MODE ( dst ) == dstmode ) d = dst ; else d = gen_reg_rtx ( dstmode ) ; emit_insn ( pinsr ( d , gen_lowpart ( dstmode , dst ) , gen_lowpart ( srcmode , src ) , GEN_INT ( <NUM_LIT> << ( pos / size ) ) ) ) ; if ( d != dst ) emit_move_insn ( dst , gen_lowpart ( GET_MODE ( dst ) , d ) ) ; return true ;


<s> case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; } BuildMI ( MBB , MI , MBB . findDebugLoc ( MI ) , get ( Opc ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; unsigned RC , LoOpc , LoIdx , HiOpc , HiIdx , HiOff ; bool Split = <STR_LIT> ( TRI -> getSpillSize ( * TRC ) , <STR_LIT> , RC , LoOpc , LoIdx , HiOpc , HiIdx , HiOff ) ; MachineInstrBuilder LoMIB = addSubReg ( BuildMI ( MBB , MI , MBB . findDebugLoc ( MI ) , get ( LoOpc ) ) , DstReg , LoIdx , TRI , RegState :: DefineNoRead ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; if ( Split ) {

MachineInstrBuilder HiMIB = addSubReg ( BuildMI ( MBB , MI , MBB . findDebugLoc ( MI ) , get ( HiOpc ) ) , DstReg , HiIdx , TRI , RegState :: Define ) . addFrameIndex ( FI ) . addImm ( HiOff ) ;


<s> if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) || check ( ! hasThumb ( ) , L , <STR_LIT> ) ) return true ;


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; if ( HasVecOffset ) { const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; } else { const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; } CurDAG -> RemoveDeadNode ( LD ) ; return ; } else { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; CurDAG -> RemoveDeadNode ( LD ) ; return ;


<s> if ( It == BlockInfoMap . end ( ) ) return INVALIDSCCNUM ; return ( * It ) . second -> SccNum ;


return ( __m256i ) __builtin_ia32_cvtps2uqq256_mask ( ( __v4sf ) __A , ( __v4di ) _mm256_setzero_si256 ( ) , ( __mmask8 ) __U ) ;


<s> Darwin<ISA_LIT>_64AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MachO :: CPUSubType<ISA_LIT> st ) : Darwin<ISA_LIT>AsmBackend ( T , MRI , STI , true ) , Subtype ( st ) {


<s> for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , ( int ) Lo , ( int ) Hi ) ) return false ;


<s> MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? i : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? i : ( FullSize - <NUM_LIT> - i ) ;

Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> bool hasFPU ( ) const { return HasFPU ;


<s> MVT HalfT = <STR_LIT> ; SDLoc dl ( N ) ; SDValue Hi , Lo , Tmp ; if ( ! isOperationLegalOrCustom ( <STR_LIT> , HalfT ) || ! isOperationLegalOrCustom ( <STR_LIT> , HalfT ) ) return ; unsigned OpTypeBits = HalfT . getScalarSizeInBits ( ) ; SDVTList VTList = DAG . getVTList ( HalfT , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , HalfT ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , HalfT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , HalfT ) ) ; Tmp = DAG . getNode ( <STR_LIT> , dl , HalfT , Hi , DAG . getConstant ( OpTypeBits - <NUM_LIT> , dl , getShiftAmountTy ( HalfT , DAG . getDataLayout ( ) ) ) ) ; Lo = DAG . getNode ( <STR_LIT> , dl , VTList , Tmp , Lo ) ;

Hi = DAG . getNode ( <STR_LIT> , dl , VTList , Tmp , Hi , SDValue ( Lo . getNode ( ) , <NUM_LIT> ) ) ;


<s> if ( ! Src ) return false ; if ( const PointerType * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) return ( PT -> getAddressSpace ( ) == spN ) ; return false ;


<s> BlackfinTargetMachine :: BlackfinTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , FS ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( Subtarget ) {


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> return new <ISA_LIT>PreLegalizerCombiner ( IsOptNone ) ;


<s> static bool has_vsetvl_killed_avl_p ( const bb_info * bb , const vector_insn_info & info ) { if ( info . dirty_with_killed_avl_p ( ) ) { rtx avl = info . get_avl ( ) ; if ( vlmax_avl_p ( avl ) ) return find_reg_killed_by ( bb , info . get_avl_reg_rtx ( ) ) != nullptr ; for ( const insn_info * insn : bb -> reverse_real_nondebug_insns ( ) ) {

def_info * def = find_access ( insn -> defs ( ) , REGNO ( avl ) ) ;


<s> SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) , DL ) , VIdx , Disp , Segment , VMask , Chain } ;

SDNode * ResNode = CurDAG -> getMachineNode ( Opc , DL , VTs , Ops ) ;


<s> SDValue LHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , Zero ) ; SDValue RHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , Zero ) ; SDValue DIVREM = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( HalfVT , HalfVT ) , LHS_Lo , RHS_Lo ) ; SDValue Res [ <NUM_LIT> ] = { DAG . getNode ( <STR_LIT> , DL , VT , DIVREM . getValue ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , DIVREM . getValue ( <NUM_LIT> ) ) } ; return DAG . getMergeValues ( Res , DL ) ; } SDValue LHSign = DAG . getSelectCC ( DL , LHS , Zero , NegOne , Zero , <STR_LIT> ) ; SDValue RHSign = DAG . getSelectCC ( DL , RHS , Zero , NegOne , Zero , <STR_LIT> ) ; SDValue DSign = DAG . getNode ( <STR_LIT> , DL , VT , LHSign , RHSign ) ; SDValue RSign = LHSign ; LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHSign ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS , RHSign ) ; LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHSign ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS , RHSign ) ;

SDValue Div = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT ) , LHS , RHS ) ;


<s> return new <ISA_LIT>PassConfig ( this , PM ) ;


<s> void <ISA_LIT>TargetWasmStreamer :: emitGlobal ( ArrayRef < <STR_LIT> > Globals ) { Streamer . PushSection ( ) ; Streamer . SwitchSection ( Streamer . getContext ( ) . getWasmSection ( <STR_LIT> , SectionKind :: getMetadata ( ) ) ) ; for ( const <STR_LIT> & G : Globals ) { Streamer . EmitIntValue ( int32_t ( G . Type ) , <NUM_LIT> ) ; Streamer . EmitIntValue ( G . Mutable , <NUM_LIT> ) ; if ( G . InitialModule . empty ( ) ) { Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitSLEB128IntValue ( <NUM_LIT> ) ;


<s> MachineInstr * <ISA_LIT>LDCleanup :: SetRegister ( MachineInstr * I , unsigned * TLSBaseAddrReg ) { MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * Next = I -> getNextNode ( ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , Next , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * TLSBaseAddrReg ) . addReg ( <STR_LIT> ) ; return Copy ;


<s> if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] , getDefRegState ( true ) ) ; if ( DeleteRet ) { MIB . copyImplicitOps ( & * MI ) ; MI -> eraseFromParent ( ) ; } MI = MIB ; } else if ( Regs . size ( ) == <NUM_LIT> ) { if ( Regs [ <NUM_LIT> ] == <STR_LIT> ) Regs [ <NUM_LIT> ] = <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) , Regs [ <NUM_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ;

if ( LdrOpc == <STR_LIT> || LdrOpc == <STR_LIT> ) {


<s> if ( code == EQ || code == NE ) { rtx zie = mips_zero_if_equal ( cmp_operands [ <NUM_LIT> ] , cmp_operands [ <NUM_LIT> ] ) ;

mips_emit_binary ( code , target , zie , const0_rtx ) ;


<s> MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { Register DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; if ( RegRewriteTable . find ( Op1Reg ) != RegRewriteTable . end ( ) ) Op1Reg = RegRewriteTable [ Op1Reg ] . first ; if ( RegRewriteTable . find ( Op2Reg ) != RegRewriteTable . end ( ) ) Op2Reg = RegRewriteTable [ Op2Reg ] . second ; MIB = BuildMI ( * SinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( Op1Reg ) . addMBB ( FalseMBB ) . addReg ( Op2Reg ) . addMBB ( TrueMBB ) ; RegRewriteTable [ DestReg ] = std :: make_pair ( Op1Reg , Op2Reg ) ; } return MIB ;


<s> unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result ) ;


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( create<ISA_LIT>ISelDag ( * this , getOptLevel ( ) ) ) ;


<s> void recordReplacement ( int OFI , int NFI ) {

FIReplacements . insert ( std :: make_pair ( OFI , NFI ) ) ;


<s> if ( isIntr ) { int MSRFI = MFI -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false , false ) ; BuildMI ( MENT , MENTI , ENTDL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MENT , MENTI , ENTDL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( MSRFI ) . addImm ( <NUM_LIT> ) ; BuildMI ( MEXT , MEXTI , EXTDL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( MSRFI ) . addImm ( <NUM_LIT> ) ; BuildMI ( MEXT , MEXTI , EXTDL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } BuildMI ( MEXT , MEXTI , EXTDL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( R18FI ) . addImm ( <NUM_LIT> ) ; BuildMI ( MEXT , MEXTI , EXTDL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( R17FI ) . addImm ( <NUM_LIT> ) ; for ( unsigned r = <STR_LIT> , i = VFI . size ( ) ; r >= <STR_LIT> ; -- r ) {

if ( ! MRI . isPhysRegUsed ( r ) ) continue ;


<s> Pass * llvm :: createMVELaneInterleavingPass ( ) { return new MVELaneInterleaving ( ) ;


<s> static bool cr16_class_likely_spilled_p ( reg_class_t rclass ) {

if ( ( rclass ) == SHORT_REGS || ( rclass ) == DOUBLE_BASE_REGS || ( rclass ) == LONG_REGS || ( rclass ) == GENERAL_REGS ) return true ;


<s> unsigned Count = <NUM_LIT> ; while ( expandRxSBG ( RISBG ) ) if ( RISBG . Input . getOpcode ( ) != <STR_LIT> && RISBG . Input . getOpcode ( ) != <STR_LIT> ) Count += <NUM_LIT> ; if ( Count == <NUM_LIT> ) return false ; if ( Count == <NUM_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ; if ( RISBG . Rotate == <NUM_LIT> ) { bool PreferAnd = false ; if ( VT == <STR_LIT> ) PreferAnd = true ; else if ( RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) PreferAnd = true ; else if ( auto * Load = dyn_cast < LoadSDNode > ( RISBG . Input ) ) { if ( Load -> getMemoryVT ( ) == <STR_LIT> && ( Load -> getExtensionType ( ) == <STR_LIT> || Load -> getExtensionType ( ) == <STR_LIT> ) && RISBG . Mask == <NUM_LIT> && Subtarget -> hasLoadAndZeroRightmostByte ( ) ) PreferAnd = true ; } if ( PreferAnd ) { SDValue In = convertTo ( DL , VT , RISBG . Input ) ; SDValue Mask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; SDValue New = CurDAG -> getNode ( <STR_LIT> , DL , VT , In , Mask ) ; if ( N != New . getNode ( ) ) { insertDAGNode ( CurDAG , N , Mask ) ; insertDAGNode ( CurDAG , N , New ) ; ReplaceNode ( N , New . getNode ( ) ) ;


<s> result . insert ( InstrPred . begin ( ) , InstrPred . end ( ) ) ;


<s> void prepare ( ) { assert ( RS && <STR_LIT> ) ; TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> , false ) ; TmpVGPRIndex = MFI . getScavengeFI ( MF . getFrameInfo ( ) , TRI ) ; if ( TmpVGPR ) { TmpVGPRLive = false ; } else { TmpVGPR = <STR_LIT> ; TmpVGPRLive = true ; } assert ( ! SavedExecReg && <STR_LIT> ) ; const TargetRegisterClass & RC = IsWave32 ? <STR_LIT> : <STR_LIT> ; RS -> setRegUsed ( SuperReg ) ; SavedExecReg = RS -> scavengeRegister ( & RC , MI , <NUM_LIT> , false ) ; int64_t VGPRLanes = getPerVGPRData ( ) . VGPRLanes ; if ( SavedExecReg ) { RS -> setRegUsed ( SavedExecReg ) ; BuildMI ( * MBB , MI , DL , TII . get ( MovOpc ) , SavedExecReg ) . addReg ( ExecReg ) ; auto I = BuildMI ( * MBB , MI , DL , TII . get ( MovOpc ) , ExecReg ) . addImm ( VGPRLanes ) ; if ( ! TmpVGPRLive ) I . addReg ( TmpVGPR , RegState :: ImplicitDefine ) ; TRI . buildVGPRSpillLoadStore ( * this , TmpVGPRIndex , <NUM_LIT> , false ) ; } else { if ( TmpVGPRLive ) TRI . buildVGPRSpillLoadStore ( * this , TmpVGPRIndex , <NUM_LIT> , false , false ) ;

auto I = BuildMI ( * MBB , MI , DL , TII . get ( NotOpc ) , ExecReg ) . addReg ( ExecReg ) ;


<s> if ( ! constrainSelectedInstRegOperands ( * ReadI , TII , TRI , RBI ) ) return false ; } auto Mov1I = BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( Helper . SelectResultOpcode ) ) . addDef ( ResReg ) . addUse ( PrevRes ) . addImm ( <NUM_LIT> ) . add ( predOps ( Cond , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ; return true ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( * TM . getDataLayout ( ) ) {


<s> case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_REL32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_PLT : Type = ELF :: R_<ISA_LIT>_PLT32 ; break ; default : Type = ELF :: R_<ISA_LIT>_CALL ; break ; } break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_PREL ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> :


<s> if ( isLd && TID . mayStore ( ) ) return false ; if ( ! isLd ) { if ( TID . mayLoad ( ) ) return false ; if ( TID . mayStore ( ) ) return false ; } for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ;


<s> U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportStorageClass ( ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { AM . GVOpFlags = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { AM . GVOpFlags = <STR_LIT> ; } return true ; } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; }


<s> } } llvm_unreachable ( <STR_LIT> ) ; } if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; SDLoc DL ( Op ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget -> isTargetKnownWindowsMSVC ( ) || Subtarget -> isTargetWindowsGNU ( ) ) { SDLoc dl ( GA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ;

SDValue TlsArray = Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : ( Subtarget -> isTargetWindowsGNU ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ) ;


<s> Register Def = Use . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Use . getOpcode ( ) == <STR_LIT> && isVgprRegBank ( Def ) ) return Def ; }

Register VgprReg = B . buildCopy ( MRI . getType ( Reg ) , Reg ) . getReg ( <NUM_LIT> ) ;


<s> if ( CannotTailPredicate ) return false ; if ( isVCTP ( MI ) && VCTP ) return false ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { VPTBlocks . emplace_back ( MI , CurrentPredicate ) ; CurrentBlock = & VPTBlocks . back ( ) ; return true ; } else if ( isVCTP ( MI ) ) VCTP = MI ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) return false ; bool IsUse = false ; bool IsDef = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { CurrentPredicate . insert ( MI ) ; IsDef = true ; } else if ( <STR_LIT> ( MCID . OpInfo [ i ] . OperandType ) ) { CurrentBlock -> addInst ( MI , CurrentPredicate ) ; IsUse = true ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } if ( IsDef && ! IsUse && VCTP && ! isVCTP ( MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredCmp ( MachineInstr & MI , MachineBasicBlock * BB ) const { bool Is24Bit = MI . getOpcode ( ) == <STR_LIT> ; assert ( ( Is24Bit || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ;

BuildMI ( * BB , MI , DL , TII -> get ( Is24Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> if ( GET_CODE ( pattern ) == PARALLEL ) pattern = XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ; rtx src = SET_SRC ( pattern ) ; rtx sel = GET_CODE ( src ) == VEC_DUPLICATE ? XEXP ( src , <NUM_LIT> ) : src ; rtx par = XEXP ( sel , <NUM_LIT> ) ; int half_elts = GET_MODE_NUNITS ( GET_MODE ( XEXP ( sel , <NUM_LIT> ) ) ) >> <NUM_LIT> ; int lane = INTVAL ( XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ) ; lane = lane >= half_elts ? lane - half_elts : lane + half_elts ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = GEN_INT ( lane ) ;


<s> unsigned SR1 = Src1 -> isReg ( ) ? Src1 -> getReg ( ) : <NUM_LIT> ; unsigned SR2 = Src2 -> isReg ( ) ? Src2 -> getReg ( ) : <NUM_LIT> ; bool Failure = false , CanUp = true , CanDown = true ; for ( unsigned X = MinX + <NUM_LIT> ; X < MaxX ; X ++ ) { const DefUseInfo & DU = DUM . lookup ( X ) ; if ( DU . Defs [ PR ] || DU . Defs [ DR ] || DU . Uses [ DR ] ) { Failure = true ; break ; } if ( CanDown && DU . Defs [ SR1 ] ) CanDown = false ; if ( CanUp && DU . Defs [ SR2 ] ) CanUp = false ; } if ( Failure || ( ! CanUp && ! CanDown ) ) continue ; MachineOperand * SrcT = ( MinX == CI . TrueX ) ? Src1 : Src2 ; MachineOperand * SrcF = ( MinX == CI . FalseX ) ? Src1 : Src2 ; MachineBasicBlock :: iterator At = CanDown ? Def2 : Def1 ; ML . push_back ( MuxInfo ( At , DR , PR , SrcT , SrcF , Def1 , Def2 ) ) ; } for ( MuxInfo & MX : ML ) { unsigned MxOpc = getMuxOpcode ( * MX . SrcT , * MX . SrcF ) ; if ( ! MxOpc ) continue ; MachineBasicBlock & B = * MX . At -> getParent ( ) ; const DebugLoc & DL = B . findDebugLoc ( MX . At ) ; auto NewMux = BuildMI ( B , MX . At , DL , HII -> get ( MxOpc ) , MX . DefR ) . addReg ( MX . PredR ) . add ( * MX . SrcT ) . add ( * MX . SrcF ) ; NewMux -> clearKillInfo ( ) ; B . erase ( MX . Def1 ) ; B . erase ( MX . Def2 ) ; Changed = true ; } LivePhysRegs LPR ( * HRI ) ; LPR . addLiveOuts ( B ) ; auto IsLive = [ & LPR , this ] ( unsigned Reg ) -> bool {

for ( MCSubRegIterator S ( Reg , HRI , true ) ; S . isValid ( ) ; ++ S ) if ( LPR . contains ( * S ) ) return true ;


<s> if ( Header != TheLoop -> getLoopLatch ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } Function & F = * Header -> getParent ( ) ; M = F . getParent ( ) ; DL = & M -> getDataLayout ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> allowsUnalignedMem ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! ST -> hasDSP ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } LoopAccessInfo LAI ( L , SE , TLI , AA , DT , LI ) ; bool Changes = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> case <STR_LIT> : shift = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : shift = <NUM_LIT> ; break ; default : assert ( false ) ; break ; } if ( Val % ( <NUM_LIT> << shift ) ) * CommentStream << <STR_LIT> << getRegClassName ( SRegClassID ) << <STR_LIT> << Val ; return createRegOperand ( SRegClassID , Val >> shift ) ;


<s> if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned Opcode = ( * Slot ) . getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * CurrI ) == <NUM_LIT> && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ;

if ( InMicro<ISA_LIT>Mode && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ;


<s> <ISA_LIT>TargetStreamer & TTS = static_cast < <ISA_LIT>TargetStreamer & > ( TS ) ;

TTS . EmitInstructionLabel ( instructionCount ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : HasSpills ( false ) , HasAllocas ( false ) , HasStackArgs ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) {

unsigned CallConv = MF . getFunction ( ) . getCallingConv ( ) ;


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ;

const Function * F = MF . getFunction ( ) ;


<s> int idx , vlen = XVECLEN ( body , <NUM_LIT> ) ; targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( lab ) ) ; if ( TARGET_GAS ) fputs ( <STR_LIT> , asm_out_file ) ; for ( idx = <NUM_LIT> ; idx < vlen ; idx ++ ) { ASM_OUTPUT_ADDR_DIFF_ELT ( asm_out_file , body , CODE_LABEL_NUMBER ( XEXP ( XVECEXP ( body , <NUM_LIT> , idx ) , <NUM_LIT> ) ) , CODE_LABEL_NUMBER ( base ) ) ; }