<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> bool isMachineVerifierClean ( ) const override {


<s> <ISA_LIT>LDBackend & ld_backend = pParent . getTarget ( ) ; assert ( pParent . getSymGOTMap ( ) . lookUp ( * rsym ) == NULL ) ; <ISA_LIT>GOTEntry * got_entry = ld_backend . getGOT ( ) . create ( ) ; pParent . getSymGOTMap ( ) . record ( * rsym , * got_entry ) ;


<s> case <STR_LIT> : return ELF :: R_MIPS_PCHI16 ; case <STR_LIT> : return ELF :: R_MIPS_PCLO16 ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Kind ) { case <STR_LIT> : case FK_Data_8 : return ELF :: R_MIPS_64 ; case FK_DTPRel_4 : return ELF :: R_MIPS_TLS_DTPREL32 ; case FK_DTPRel_8 : return ELF :: R_MIPS_TLS_DTPREL64 ; case FK_TPRel_4 : return ELF :: R_MIPS_TLS_TPREL32 ; case FK_TPRel_8 : return ELF :: R_MIPS_TLS_TPREL64 ; case FK_GPRel_4 : if ( isN64 ( ) ) { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; return Type ; } return ELF :: R_MIPS_GPREL32 ; case <STR_LIT> : return ELF :: R_MIPS_GPREL16 ; case <STR_LIT> : return ELF :: R_MIPS_26 ; case <STR_LIT> : return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; return Type ; } case <STR_LIT> : return ELF :: R_MIPS_HIGHER ; case <STR_LIT> : return ELF :: R_MIPS_HIGHEST ; case <STR_LIT> : return ELF :: R_MIPS_SUB ; case <STR_LIT> : return ELF :: R_MIPS_GOT_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_LO16 ;


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , dm_off ) . addReg ( dm_off_reg ) . addImm ( <NUM_LIT> << <NUM_LIT> ) ; Register PtrReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( PtrReg ) . addReg ( dm_off , RegState :: Kill ) ;


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> } cfun -> machine -> return_used_this_function = <NUM_LIT> ; } else { offsets = arm_get_frame_offsets ( ) ;

gcc_assert ( ! use_return_insn ( FALSE , NULL ) || ( cfun -> machine -> return_used_this_function != <NUM_LIT> ) || offsets -> saved_regs == offsets -> outgoing_args || frame_pointer_needed ) ;


<s> bool isProgramMemoryAddress ( T * V ) { return cast < PointerType > ( V -> getType ( ) ) -> getAddressSpace ( ) == ProgramMemory ;


<s> for ( MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; } BitVector Available = RS . getRegsAvailable ( & <STR_LIT> ) ; Available &= Candidates ; signed Reg = Available . find_first ( ) ;

assert ( Reg != - <NUM_LIT> && <STR_LIT> ) ;


<s> return __builtin_mve_vminnmvq_fv4sf ( __a , __b ) ;


<s> int nelt = GET_MODE_NUNITS ( mode ) ; if ( ! INTEGRAL_MODE_P ( mode ) ) return false ; if ( ! ( MEM_P ( mem ) ) || ! SYMBOL_REF_P ( XEXP ( mem , <NUM_LIT> ) ) || ! CONSTANT_POOL_ADDRESS_P ( XEXP ( mem , <NUM_LIT> ) ) ) return false ; rtx constant = get_pool_constant ( XEXP ( mem , <NUM_LIT> ) ) ; if ( GET_CODE ( constant ) != CONST_VECTOR ) return false ; if ( GET_MODE ( constant ) != mode ) { constant = simplify_subreg ( mode , constant , GET_MODE ( constant ) , <NUM_LIT> ) ; if ( constant == nullptr || GET_CODE ( constant ) != CONST_VECTOR ) return false ; }

for ( int i = <NUM_LIT> ; i != nelt ; i ++ ) perm [ i ] = UINTVAL ( XVECEXP ( constant , <NUM_LIT> , i ) ) ;


<s> if ( ! OutgoingArg ) std :: tie ( OutgoingArg , ArgRC , ArgTy ) = CalleeArgInfo -> getPreloadedValue ( <STR_LIT> ) ; if ( ! OutgoingArg ) std :: tie ( OutgoingArg , ArgRC , ArgTy ) = CalleeArgInfo -> getPreloadedValue ( <STR_LIT> ) ; if ( ! OutgoingArg ) return false ; auto WorkitemIDX = CallerArgInfo . getPreloadedValue ( <STR_LIT> ) ; auto WorkitemIDY = CallerArgInfo . getPreloadedValue ( <STR_LIT> ) ; auto WorkitemIDZ = CallerArgInfo . getPreloadedValue ( <STR_LIT> ) ; const ArgDescriptor * IncomingArgX = std :: get < <NUM_LIT> > ( WorkitemIDX ) ; const ArgDescriptor * IncomingArgY = std :: get < <NUM_LIT> > ( WorkitemIDY ) ; const ArgDescriptor * IncomingArgZ = std :: get < <NUM_LIT> > ( WorkitemIDZ ) ; const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; const bool NeedWorkItemIDX = ! Info . CB -> hasFnAttr ( <STR_LIT> ) ; const bool NeedWorkItemIDY = ! Info . CB -> hasFnAttr ( <STR_LIT> ) ; const bool NeedWorkItemIDZ = ! Info . CB -> hasFnAttr ( <STR_LIT> ) ; Register InputReg ; if ( IncomingArgX && ! IncomingArgX -> isMasked ( ) && CalleeArgInfo -> WorkItemIDX && NeedWorkItemIDX ) { InputReg = MRI . createGenericVirtualRegister ( S32 ) ; LI -> loadInputValue ( InputReg , MIRBuilder , IncomingArgX , std :: get < <NUM_LIT> > ( WorkitemIDX ) , std :: get < <NUM_LIT> > ( WorkitemIDX ) ) ; } if ( IncomingArgY && ! IncomingArgY -> isMasked ( ) && CalleeArgInfo -> WorkItemIDY && NeedWorkItemIDY ) { Register Y = MRI . createGenericVirtualRegister ( S32 ) ; LI -> loadInputValue ( Y , MIRBuilder , IncomingArgY , std :: get < <NUM_LIT> > ( WorkitemIDY ) , std :: get < <NUM_LIT> > ( WorkitemIDY ) ) ; Y = MIRBuilder . buildShl ( S32 , Y , MIRBuilder . buildConstant ( S32 , <NUM_LIT> ) ) . getReg ( <NUM_LIT> ) ; InputReg = InputReg ? MIRBuilder . buildOr ( S32 , InputReg , Y ) . getReg ( <NUM_LIT> ) : Y ; } if ( IncomingArgZ && ! IncomingArgZ -> isMasked ( ) && CalleeArgInfo -> WorkItemIDZ && NeedWorkItemIDZ ) { Register Z = MRI . createGenericVirtualRegister ( S32 ) ; LI -> loadInputValue ( Z , MIRBuilder , IncomingArgZ , std :: get < <NUM_LIT> > ( WorkitemIDZ ) , std :: get < <NUM_LIT> > ( WorkitemIDZ ) ) ; Z = MIRBuilder . buildShl ( S32 , Z , MIRBuilder . buildConstant ( S32 , <NUM_LIT> ) ) . getReg ( <NUM_LIT> ) ; InputReg = InputReg ? MIRBuilder . buildOr ( S32 , InputReg , Z ) . getReg ( <NUM_LIT> ) : Z ; } if ( ! InputReg && ( NeedWorkItemIDX || NeedWorkItemIDY || NeedWorkItemIDZ ) ) {


<s> AM . Disp = Offset ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; AM . SymbolFlags = cast < BlockAddressSDNode > ( N0 ) -> getTargetFlags ( ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) AM . setBaseReg ( CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return false ; } if ( ! Subtarget -> is64Bit ( ) || ( ( M == CodeModel :: Small || M == CodeModel :: Kernel ) && TM . getRelocationModel ( ) == Reloc :: Static ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) {


<s> bool isSegmentSpecificFLAT ( uint16_t Opcode ) const { auto Flags = get ( Opcode ) . TSFlags ; return Flags & ( <STR_LIT> | <STR_LIT> ) ;


<s> switch ( Opc ) { default : continue ; case <STR_LIT> : T2JumpTables . push_back ( & I ) ; continue ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : isCond = true ; UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( & I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I . getNumOperands ( ) ; op != e ; ++ op ) if ( I . getOperand ( op ) . isCPI ( ) || I . getOperand ( op ) . isJTI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ;


<s> MachineBasicBlock * Bottom = Loop -> getHeader ( ) ; for ( MachineBasicBlock * MBB : Loop -> blocks ( ) ) if ( MBB -> getNumber ( ) > Bottom -> getNumber ( ) ) Bottom = MBB ;


<s> unsigned Reg = Use . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( Reg == <STR_LIT> ) continue ; for ( MCRegUnitIterator RegUnit ( Reg , TRI ) ; RegUnit . isValid ( ) ; ++ RegUnit ) { LiveRange & LR = LIS -> getRegUnit ( * RegUnit ) ; const VNInfo * Value = LR . Query ( LIS -> getInstructionIndex ( MI ) ) . valueIn ( ) ; if ( ! Value ) continue ; if ( Value -> isPHIDef ( ) ) continue ; markInstruction ( * LIS -> getInstructionFromIndex ( Value -> def ) , StateWQM , Worklist ) ; } continue ;


<s> const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: createExpr ( Expr ) ;


<s> if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; unsigned CC = StringSwitch < unsigned > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( <STR_LIT> ( CC ) , S ) ) ;


<s> bool hasVirt ( ) const { return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Skip , OffsetOfLoc , <NUM_LIT> ) ) ; unsigned RegNo = is64BitMode ( ) ? <STR_LIT> : ( is32BitMode ( ) ? <STR_LIT> : <STR_LIT> ) ; return <STR_LIT> ( RegNo , Start , End , true , OffsetOfLoc , Identifier , Info . OpDecl ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectDSGW<ISA_LIT>ntrinsic ( MachineInstr & MI , <STR_LIT> IID ) const { if ( IID == <STR_LIT> && ! STI . hasGWSSemaReleaseAll ( ) ) return false ; const bool HasVSrc = MI . getNumOperands ( ) == <NUM_LIT> ; assert ( HasVSrc || MI . getNumOperands ( ) == <NUM_LIT> ) ; Register BaseOffset = MI . getOperand ( HasVSrc ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; const RegisterBank * OffsetRB = RBI . getRegBank ( BaseOffset , * MRI , TRI ) ; if ( OffsetRB -> getID ( ) != <STR_LIT> ) return false ; MachineInstr * OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; assert ( OffsetDef ) ; unsigned ImmOffset ; MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineInstr * Readfirstlane = nullptr ; if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { Readfirstlane = OffsetDef ; BaseOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetDef = getDefIgnoringCopies ( BaseOffset , * MRI ) ; } if ( OffsetDef -> getOpcode ( ) == <STR_LIT> ) { ImmOffset = OffsetDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { std :: tie ( BaseOffset , ImmOffset ) = <STR_LIT> ( * MRI , BaseOffset ) ; if ( Readfirstlane ) { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; Readfirstlane -> getOperand ( <NUM_LIT> ) . setReg ( BaseOffset ) ; BaseOffset = Readfirstlane -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; }

Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT> ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateVectorIndex ( int Idx , SMLoc S , SMLoc E , MCContext & Ctx ) {

auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_VectorIndex , Ctx ) ;


<s> static bool csky_cannot_copy_insn_p ( rtx_insn * insn ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) { const_rtx x = * iter ;

if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , <NUM_LIT> ) == UNSPEC_TLS_LABEL || XINT ( x , <NUM_LIT> ) == UNSPEC_PIC_SYMBOL_GOTPC_GRS ) ) return true ;


<s> if ( ! ST -> hasVInstructions ( ) ) return false ; if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ;

if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ;


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; unsigned Start , End ;

return analyzeFPImm ( Imm , VT . getSizeInBits ( ) , Start , End , TII ) ;


<s> gcc_assert ( GET_MODE ( value ) == QImode || CONST_INT_P ( value ) ) ; if ( CONST_INT_P ( value ) ) { unsigned HOST_WIDE_INT val = UINTVAL ( value ) & GET_MODE_MASK ( QImode ) ; rtx new_val = gen_int_mode ( val | ( val << <NUM_LIT> ) | ( val << <NUM_LIT> ) | ( val << <NUM_LIT> ) , SImode ) ; emit_move_insn ( value4word , new_val ) ; } else { if ( NDS32_EXT_DSP_P ( ) ) { rtx tmp = gen_reg_rtx ( SImode ) ; convert_move ( tmp , value , true ) ; emit_insn ( gen_insvsi_internal ( tmp , gen_int_mode ( <NUM_LIT> , SImode ) , tmp ) ) ; emit_insn ( gen_pkbbsi_1 ( value4word , tmp , tmp ) ) ; }


<s> PrivateGlobalPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: WinEH ; } else { ExceptionsType = ExceptionHandling :: DwarfCFI ; } AssemblerDialect = AsmWriterFlavor ;


<s> void <ISA_LIT>EarlyIfConversion :: replacePhiEdges ( MachineBasicBlock * OldB , MachineBasicBlock * NewB ) { for ( auto I = OldB -> succ_begin ( ) , E = OldB -> succ_end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = * I ; MachineBasicBlock :: iterator P , N = SB -> getFirstNonPHI ( ) ; for ( P = SB -> begin ( ) ; P != N ; ++ P ) { MachineInstr & PN = * P ; for ( MachineOperand & MO : PN . operands ( ) ) if ( MO . isMBB ( ) && MO . getMBB ( ) == OldB ) MO . setMBB ( NewB ) ;


<s> unsigned LabelId = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( ! InConstantPool ) { OutStreamer . EmitDataRegion ( MCDR_DataRegion ) ; InConstantPool = true ; } OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ;


<s> unsigned R = I . first ; NewSense & US = I . second ; if ( ! hasValidNewValueDef ( US , NewDefs [ R ] ) ) { errInfo . setError ( <STR_LIT> , R ) ; addErrInfo ( errInfo ) ; return false ; } } return true ;


<s> if ( ! optimize ) return ; edge e ; edge_iterator ei ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { basic_block cfg_bb = bb -> cfg_bb ( ) ; auto & curr_prob = m_vector_manager -> vector_block_infos [ cfg_bb -> index ] . probability ; if ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) == cfg_bb ) curr_prob = profile_probability :: always ( ) ; if ( EXIT_BLOCK_PTR_FOR_FN ( cfun ) == cfg_bb ) continue ; gcc_assert ( curr_prob . initialized_p ( ) ) ; FOR_EACH_EDGE ( e , ei , cfg_bb -> succs ) { auto & new_prob = m_vector_manager -> vector_block_infos [ e -> dest -> index ] . probability ;

if ( ! new_prob . initialized_p ( ) ) new_prob = curr_prob * e -> probability ;


<s> if ( flags == MASK_MIPS16 ) return <STR_LIT> ; if ( flags == MASK_MICROMIPS ) return <STR_LIT> ; return <STR_LIT> ;


return ( __m128i ) __builtin_ia32_pmovuswb128_mask ( ( __v8hi ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> const unsigned VReg = MF . addLiveIn ( PhysReg , RegClass ) ; SDValue CopyFrom = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; SDValue Store = DAG . getStore ( CopyFrom . getValue ( <NUM_LIT> ) , dl , CopyFrom , DAG . getObjectPtrOffset ( dl , FIN , TypeSize :: Fixed ( Offset ) ) , MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) ) ; MemOps . push_back ( Store ) ; } ; unsigned Offset = <NUM_LIT> ; HandleRegLoc ( VA . getLocReg ( ) , Offset ) ; Offset += PtrByteSize ; for ( ; Offset != StackSize && ArgLocs [ I ] . isRegLoc ( ) ; Offset += PtrByteSize ) { assert ( ArgLocs [ I ] . getValNo ( ) == VA . getValNo ( ) && <STR_LIT> ) ; const CCValAssign RL = ArgLocs [ I ++ ] ; HandleRegLoc ( RL . getLocReg ( ) , Offset ) ; FuncInfo -> appendParameterType ( <ISA_LIT>FunctionInfo :: FixedType ) ; } if ( Offset != StackSize ) { assert ( ArgLocs [ I ] . getValNo ( ) == VA . getValNo ( ) && <STR_LIT> ) ; assert ( ArgLocs [ I ] . isMemLoc ( ) && <STR_LIT> ) ; ++ I ; } continue ; } EVT ValVT = VA . getValVT ( ) ; if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { <STR_LIT> SVT = ValVT . getSimpleVT ( ) . SimpleTy ; unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassForSVT ( SVT , Is<ISA_LIT>64 ) ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; if ( ValVT . isScalarInteger ( ) && ( ValVT . getFixedSizeInBits ( ) < LocVT . getFixedSizeInBits ( ) ) ) { ArgValue = truncateScalarIntegerArg ( Flags , ValVT , DAG , ArgValue , LocVT , dl ) ; } InVals . push_back ( ArgValue ) ; continue ; } if ( VA . isMemLoc ( ) ) { const unsigned LocSize = LocVT . getStoreSize ( ) ; const unsigned ValSize = ValVT . getStoreSize ( ) ; assert ( ( ValSize <= LocSize ) && <STR_LIT> ) ; int CurArgOffset = VA . getLocMemOffset ( ) ; if ( LocSize > ValSize ) CurArgOffset += LocSize - ValSize ; const bool IsImmutable = ! ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt && ( CallConv == CallingConv :: Fast ) ) ; int FI = MFI . CreateFixedObject ( ValSize , CurArgOffset , IsImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue ArgValue = DAG . getLoad ( ValVT , dl , Chain , FIN , MachinePointerInfo ( ) ) ; InVals . push_back ( ArgValue ) ;


<s> static SDValue LowerVAARG ( SDValue Op , SelectionDAG & DAG ) { SDNode * Node = Op . getNode ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue InChain = Node -> getOperand ( <NUM_LIT> ) ; SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; EVT PtrVT = VAListPtr . getValueType ( ) ;

const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> return ( int64x1_t ) __builtin_neon_vreinterpretdidi ( ( int64x1_t ) __a ) ;


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > RetInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; ArgInfo ArgRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( DL , ArgRetInfo , <NUM_LIT> , RetInfos , OrigArgIndices ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( F , RetInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; setLocInfo ( ArgLocs , Outs ) ; <ISA_LIT>OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret ) ; return true ;


<s> } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ;

return VisitNode ( DT -> getRootNode ( ) , <NUM_LIT> ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & <STR_LIT> ) return & <STR_LIT> ; return RC ;


<s> return __builtin_mve_vqdmulhq_sv8hi ( __a , __b ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & sti ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) , STI ( sti ) {


<s> if ( pa_can_combine_p ( new_rtx , anchor , floater , <NUM_LIT> , SET_DEST ( PATTERN ( floater ) ) , XEXP ( SET_SRC ( PATTERN ( floater ) ) , <NUM_LIT> ) , XEXP ( SET_SRC ( PATTERN ( floater ) ) , <NUM_LIT> ) ) ) break ; } else if ( anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH && floater_attr == PA_COMBINE_TYPE_ADDMOVE ) { if ( GET_CODE ( SET_SRC ( PATTERN ( floater ) ) ) == PLUS ) { if ( pa_can_combine_p ( new_rtx , anchor , floater , <NUM_LIT> , SET_DEST ( PATTERN ( floater ) ) , XEXP ( SET_SRC ( PATTERN ( floater ) ) , <NUM_LIT> ) , XEXP ( SET_SRC ( PATTERN ( floater ) ) , <NUM_LIT> ) ) ) break ; } else { if ( pa_can_combine_p ( new_rtx , anchor , floater , <NUM_LIT> , SET_DEST ( PATTERN ( floater ) ) , SET_SRC ( PATTERN ( floater ) ) , SET_SRC ( PATTERN ( floater ) ) ) ) break ; } } } if ( ! floater && ( anchor_attr == PA_COMBINE_TYPE_FMPY || anchor_attr == PA_COMBINE_TYPE_FADDSUB ) ) { for ( floater = anchor ; floater ; floater = NEXT_INSN ( floater ) ) { if ( NOTE_P ( floater ) || ( NONJUMP_INSN_P ( floater ) && ( GET_CODE ( PATTERN ( floater ) ) == USE || GET_CODE ( PATTERN ( floater ) ) == CLOBBER ) ) ) continue ; if ( ! NONJUMP_INSN_P ( floater ) ) { floater = NULL ; break ; } floater_attr = get_attr_pa_combine_type ( floater ) ; if ( ( anchor_attr == PA_COMBINE_TYPE_FMPY && floater_attr == PA_COMBINE_TYPE_FADDSUB ) || ( anchor_attr == PA_COMBINE_TYPE_FADDSUB && floater_attr == PA_COMBINE_TYPE_FMPY ) ) { if ( pa_can_combine_p ( new_rtx , anchor , floater , <NUM_LIT> , SET_DEST ( PATTERN ( floater ) ) , XEXP ( SET_SRC ( PATTERN ( floater ) ) , <NUM_LIT> ) , XEXP ( SET_SRC ( PATTERN ( floater ) ) , <NUM_LIT> ) ) ) break ; } } } if ( floater && ( anchor_attr == PA_COMBINE_TYPE_FADDSUB || anchor_attr == PA_COMBINE_TYPE_FMPY ) ) { rtvec vtemp = gen_rtvec ( <NUM_LIT> , copy_rtx ( PATTERN ( anchor ) ) , copy_rtx ( PATTERN ( floater ) ) ) ;

rtx temp = gen_rtx_PARALLEL ( VOIDmode , vtemp ) ;


<s> OptimizeSize = MinimizeSize = false ; for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReduceTable ) ; i != e ; ++ i ) { unsigned FromOpc = ReduceTable [ i ] . WideOpc ; if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i ) ) . second ) llvm_unreachable ( <STR_LIT> ) ; }


<s> return CurDAG -> getTargetConstant ( Imm , SDLoc ( Node ) , Node -> getValueType ( <NUM_LIT> ) ) ;


<s> return __builtin_mve_vmulq_fv8hf ( __a , __b ) ;


<s> bool iq2000_function_value_regno_p ( const unsigned int regno ) { return ( regno == GP_RETURN ) ;


<s> else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ;

MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ;


<s> isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } else if ( RHSC > <NUM_LIT> && RHSC < Limit * Scale && RHSC % Scale == <NUM_LIT> ) { isInc = Ptr -> getOpcode ( ) == <STR_LIT> ; Offset = DAG . getConstant ( RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } return false ; } ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { if ( Alignment >= <NUM_LIT> && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; } else if ( Alignment >= <NUM_LIT> && ( CanChangeType || VT == <STR_LIT> || VT == <STR_LIT> ) && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; else if ( Alignment >= <NUM_LIT> && ( CanChangeType || VT == <STR_LIT> || VT == <STR_LIT> ) && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; else if ( ( CanChangeType || VT == <STR_LIT> ) && IsInRange ( RHSC , <NUM_LIT> , <NUM_LIT> ) ) return true ; return false ;


<s> <ISA_LIT>AtomicLower ( ) : FunctionPass ( ID ) {


<s> BlockT * newLandBlk = landBlk ; if ( inpathBlks . size ( ) != landBlk -> pred_size ( ) ) { newLandBlk = funcRep -> CreateMachineBasicBlock ( ) ; funcRep -> push_back ( newLandBlk ) ; newLandBlk -> addSuccessor ( landBlk ) ; for ( typename SmallVectorImpl < BlockT * > :: iterator iter = inpathBlks . begin ( ) , iterEnd = inpathBlks . end ( ) ; iter != iterEnd ; ++ iter ) { BlockT * curBlk = * iter ; CFGTraits :: replaceInstrUseOfBlockWith ( curBlk , landBlk , newLandBlk ) ; curBlk -> removeSuccessor ( landBlk ) ; curBlk -> addSuccessor ( newLandBlk ) ; } for ( size_t i = <NUM_LIT> , tot = exitBlks . size ( ) ; i < tot ; ++ i ) { if ( exitBlks [ i ] == landBlk ) {


<s> bool SelectAddrImmOffs ( SDValue N , SDValue & Out ) const { Out = N ; return true ;


<s> static DecodeStatus DecodeCPSInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned imod = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned M = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned iflags = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned mode = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( imod == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; if ( iflags ) S = MCDisassembler :: SoftFail ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; S = MCDisassembler :: SoftFail ; }


<s> if ( GV -> hasLocalLinkage ( ) ) return false ;

if ( ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV -> hasCommonLinkage ( ) ) ) return false ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; unsigned NumArgs = MI -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } if ( MI -> hasOneMemOperand ( ) ) MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ;


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return true ; return false ;


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , const MCSubtargetInfo & STI , bool RelaxAll , bool NoExecStack ) { return createELFStreamer ( Ctx , MAB , _OS , _Emitter , false , false ) ;


<s> if ( TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( arm_libcall_uses_aapcs_base ( libcall ) ) return gen_rtx_REG ( mode , ARG_REGISTER ( <NUM_LIT> ) ) ; } return arm_libcall_value_1 ( mode ) ;


<s> MachineInstr * MI = I ; int opcode = MI -> getOpcode ( ) ; const MCInstrDesc & Desc = MI -> getDesc ( ) ; int AddrOffset = <STR_LIT> ( Desc . TSFlags , opcode ) ; if ( AddrOffset >= <NUM_LIT> ) { AddrOffset += <STR_LIT> ( Desc ) ; MachineOperand & p = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; if ( p . isReg ( ) && p . getReg ( ) != <STR_LIT> ) { seekLEAFixup ( p , I , MFI ) ; } MachineOperand & q = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; if ( q . isReg ( ) && q . getReg ( ) != <STR_LIT> ) { seekLEAFixup ( q , I , MFI ) ; }


<s> auto * Def = RDA -> getReachingMIDef ( MI , <STR_LIT> ) ; if ( ! Def ) return nullptr ; if ( ! ( NewOpcode = VCMPOpcodeToVPT ( Def -> getOpcode ( ) ) ) ) return nullptr ;

if ( ! RDA -> hasSameReachingDef ( Def , MI , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) || ! RDA -> hasSameReachingDef ( Def , MI , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ;


<s> case <STR_LIT> : return true ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <STR_LIT> ) return false ; break ; } } if ( Ops . size ( ) != <NUM_LIT> ) return false ; unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = nullptr ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { if ( Opc == <STR_LIT> ) return true ; OpcodeTablePtr = & RegOp2MemOpTable0 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable1 ; } else if ( OpNum == <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2 ;


<s> return <NUM_LIT> ; case AVR_BUILTIN_DELAY_CYCLES : { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op0 ) ) error ( <STR_LIT> , bname ) ; else avr_expand_delay_cycles ( op0 ) ; return NULL_RTX ; } case AVR_BUILTIN_INSERT_BITS : { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op0 ) ) { error ( <STR_LIT> <STR_LIT> , bname ) ; return target ; } break ; } case AVR_BUILTIN_ROUNDHR : case AVR_BUILTIN_ROUNDUHR : case AVR_BUILTIN_ROUNDR : case AVR_BUILTIN_ROUNDUR : case AVR_BUILTIN_ROUNDLR : case AVR_BUILTIN_ROUNDULR : case AVR_BUILTIN_ROUNDLLR : case AVR_BUILTIN_ROUNDULLR : case AVR_BUILTIN_ROUNDHK : case AVR_BUILTIN_ROUNDUHK : case AVR_BUILTIN_ROUNDK : case AVR_BUILTIN_ROUNDUK : case AVR_BUILTIN_ROUNDLK : case AVR_BUILTIN_ROUNDULK : case AVR_BUILTIN_ROUNDLLK : case AVR_BUILTIN_ROUNDULLK : if ( TREE_CODE ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) != INTEGER_CST ) break ; int rbit = ( int ) TREE_INT_CST_LOW ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( rbit >= ( int ) GET_MODE_FBIT ( mode ) ) {

warning ( OPT_Wextra , <STR_LIT> <STR_LIT> , rbit , GET_MODE_FBIT ( mode ) ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! MFI . hasStackObjects ( ) && ! HasCSRs ) { SaveBlocks . clear ( ) ; RestoreBlocks . clear ( ) ; return false ; } bool MadeChange = false ; bool NewReservedRegs = false ; const bool HasSGPRSpillToVGPR = TRI -> spillSGPRToVGPR ( ) && ( HasCSRs || FuncInfo -> hasSpilledSGPRs ( ) ) ; if ( HasSGPRSpillToVGPR ) { BitVector SpillFIs ( MFI . getObjectIndexEnd ( ) , false ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( MBB ) ) { if ( ! TII -> isSGPRSpill ( MI ) ) continue ; int FI = TII -> getNamedOperand ( MI , <STR_LIT> :: addr ) -> getIndex ( ) ; assert ( MFI . getStackID ( FI ) == TargetStackID :: SGPRSpill ) ; if ( FuncInfo -> allocateSGPRSpillToVGPR ( MF , FI ) ) { NewReservedRegs = true ; bool Spilled = TRI -> eliminateSGPRToVGPRSpillFrameIndex ( MI , FI , nullptr , LIS ) ; ( void ) Spilled ; assert ( Spilled && <STR_LIT> ) ; SpillFIs . set ( FI ) ; } } } for ( MachineBasicBlock & MBB : MF ) { for ( auto SSpill : FuncInfo -> getSGPRSpillVGPRs ( ) ) MBB . addLiveIn ( SSpill . VGPR ) ; MBB . sortUniqueLiveIns ( ) ; for ( MachineInstr & MI : MBB ) { if ( MI . isDebugValue ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && SpillFIs [ MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ] ) { MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Register ( ) , false ) ; } } } FuncInfo -> removeDeadFrameIndices ( MFI , false ) ; MadeChange = true ; } SaveBlocks . clear ( ) ; RestoreBlocks . clear ( ) ;

if ( NewReservedRegs ) MRI . freezeReservedRegs ( MF ) ;


<s> bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ; const Function * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; if ( ConstSplatVal && ( Subtarget -> hasAVX2 ( ) || OptForSize ) ) { EVT CVT = Ld . getValueType ( ) ; assert ( ! CVT . isVector ( ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( OptForSize && ( ScalarSize == <NUM_LIT> || Subtarget -> hasAVX2 ( ) ) ) ) { const Constant * C = nullptr ; if ( ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Ld ) ) C = CI -> getConstantIntValue ( ) ; else if ( ConstantFPSDNode * CF = dyn_cast < ConstantFPSDNode > ( Ld ) ) C = CF -> getConstantFPValue ( ) ; assert ( C && <STR_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; } } bool IsLoad = <STR_LIT> ( Ld . getNode ( ) ) ; if ( ! IsLoad && Subtarget -> hasInt256 ( ) && ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; if ( ! IsLoad ) return SDValue ( ) ;

if ( ScalarSize == <NUM_LIT> || ( IsGE256 && ScalarSize == <NUM_LIT> ) || ( Subtarget -> hasVLX ( ) && ScalarSize == <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ;


<s> bool ShouldPrint = false ; if ( OptLevel != CodeGenOpt :: None && ( Subtarget . hasSSE2 ( ) || Subtarget . hasAVX ( ) ) ) { PM . add ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; ShouldPrint = true ; } if ( Subtarget . hasAVX ( ) && UseVZeroUpper ) { PM . add ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ;


<s> if ( ShiftName != LowerOp && ShiftName != UpperOp ) { Error ( Parser . getTok ( ) . getLoc ( ) , Op + <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * ShiftAmount ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( ShiftAmount ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ;


<s> fparg = mips_arg_regno ( & info , true ) ; if ( mode == SFmode ) mips_output_32bit_xfer ( direction , gparg , fparg ) ; else mips_output_64bit_xfer ( direction , gparg , fparg ) ; function_arg_info arg ( mode , true ) ; mips_function_arg_advance ( pack_cumulative_args ( & cum ) , arg ) ;


<s> <ISA_LIT>LDBackend :: <ISA_LIT>LDBackend ( const LinkerConfig & pConfig , <ISA_LIT>GNUInfo * pInfo ) : GNULDBackend ( pConfig , pInfo ) , m_pRelocator ( NULL ) , m_pGOT ( NULL ) , m_pGOTPLT ( NULL ) , m_pPLT ( NULL ) , m_pRelaDyn ( NULL ) , m_pRelaPLT ( NULL ) , m_pDynamic ( NULL ) , m_pGOTSymbol ( NULL ) , m_CopyRel ( llvm :: ELF :: R_HEX_COPY ) {


<s> bool DPRRegs = llvm :: <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; unsigned Binary = <NUM_LIT> ; if ( SPRRegs || DPRRegs ) { unsigned RegNo = get<ISA_LIT>RegisterNumbering ( Reg ) ; unsigned NumRegs = ( MI . getNumOperands ( ) - Op ) & <NUM_LIT> ; Binary |= ( RegNo & <NUM_LIT> ) << <NUM_LIT> ; if ( SPRRegs ) Binary |= NumRegs ; else Binary |= NumRegs * <NUM_LIT> ; } else { for ( unsigned I = Op , E = MI . getNumOperands ( ) ; I < E ; ++ I ) { unsigned RegNo = get<ISA_LIT>RegisterNumbering ( MI . getOperand ( I ) . getReg ( ) ) ; Binary |= <NUM_LIT> << RegNo ; } }


<s> const Constant * mask2 = shaf_us -> getMask ( ) ; Value * op1_1 = shufinstr -> getOperand ( <NUM_LIT> ) ; Value * op1_2 = shaf_us -> getOperand ( <NUM_LIT> ) ; if ( mask1 == mask2 && op1_1 == op1_2 ) { if ( shaf_us -> getOperand ( <NUM_LIT> ) == shufinstr ) { shaf_us -> replaceAllUsesWith ( shufinstr ) ; } } }


<s> bool <ISA_LIT>InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ;

if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) {


<s> bool hasUnimplementedSIMD128 ( ) const { return SIMDLevel >= UnimplementedSIMD128 ;


<s> if ( ! TRI -> isVirtualRegister ( * I ) ) continue ; MachineInstr * Def = MRI -> getVRegDef ( * I ) ; if ( ! Def ) continue ; elideCopiesAndPHIs ( Def , DefSrcs ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator II = DefSrcs . begin ( ) , EE = DefSrcs . end ( ) ; II != EE ; ++ II ) { MachineInstr * MI = * II ; if ( Replacements . find ( MI ) != Replacements . end ( ) ) continue ; if ( ! hasPartialWrite ( MI ) ) continue ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; unsigned DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( DPRDefReg ) , E = MRI -> use_end ( ) ; I != E ; ++ I ) Uses . push_back ( & I . getOperand ( ) ) ; unsigned NewReg = optimizeSDPattern ( MI ) ; if ( NewReg != <NUM_LIT> ) { Modified = true ; for ( SmallVectorImpl < MachineOperand * > :: const_iterator I = Uses . begin ( ) , E = Uses . end ( ) ; I != E ; ++ I ) { DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> << PrintReg ( NewReg ) << <STR_LIT> ) ; ( * I ) -> substVirtReg ( NewReg , <NUM_LIT> , * TRI ) ;


<s> return __builtin_ia32_vcvtph2uqq512_mask_round ( __A , _mm512_setzero_si512 ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( VT == <STR_LIT> ) if ( ( ! Subtarget -> isSingleFloat ( ) ) && ( ! Subtarget -> isFP64bit ( ) ) ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


<s> static SDValue combineSBB ( SDNode * N , SelectionDAG & DAG ) { if ( SDValue Flags = combineCarryThroughADD ( N -> getOperand ( <NUM_LIT> ) , DAG ) ) { MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Flags ) ; } SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && isNullConstant ( Op1 ) && ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getVTList ( ) , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ;


<s> Relocator :: DWord A = pReloc . target ( ) + pReloc . addend ( ) ; Relocator :: Address S = pReloc . symValue ( ) ;


<s> unsigned ScratchRsrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRsrcReg == <STR_LIT> ) return <STR_LIT> ; if ( ST . hasSGPRInitBug ( ) || ScratchRsrcReg != TRI -> reservedPrivateSegmentBufferReg ( MF ) ) return ScratchRsrcReg ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumPreloaded = ( MFI -> getNumPreloadedSGPRs ( ) + <NUM_LIT> ) / <NUM_LIT> ; ArrayRef < MCPhysReg > AllSGPR128s = getAllSGPR128 ( ST , MF ) ;

AllSGPR128s = AllSGPR128s . slice ( std :: min ( static_cast < unsigned > ( AllSGPR128s . size ( ) ) , NumPreloaded ) ) ;


<s> IsDead = false ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> << ( IsDead ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ) ; if ( IsDead ) { LRegion -> removeLiveOut ( Reg ) ; } WasLiveOut = true ; } }

if ( WasLiveOut ) LRegion -> addLiveOut ( CombinedSourceReg ) ;


<s> Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : if ( ( Value & <NUM_LIT> ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; } Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else if ( MI . getOpcode ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else if ( MI . getOpcode ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; OriginalCall = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . getInstr ( ) ; bool RAXImplicitDead = false ; for ( MachineOperand & Op : llvm :: drop_begin ( MI . operands ( ) ) ) { if ( Op . isReg ( ) && Op . isImplicit ( ) && Op . isDead ( ) && TRI -> regsOverlap ( Op . getReg ( ) , <STR_LIT> ) ) { Op . setIsDead ( false ) ;


<s> CurArgIdx = Ins [ VA . getValNo ( ) ] . OrigArgIndex ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = AFI -> isThumb1OnlyFunction ( ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ;

SDValue RHS = Op . getOperand ( <NUM_LIT> ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opcode ) , DstReg ) ; if ( Src1Reg ) { MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( Src0Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ; if ( Src1Reg ) {

MIB . addReg ( Src1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ;


<s> LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; int Ops [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Ops [ i ] = i + Amt ; SDValue T = DAG . getVectorShuffle ( <STR_LIT> , dl , LHS , RHS , Ops ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , T ) ;


<s> return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntReduction ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return LowerSVEIntrinsicIndex ( N , DAG ) ; case <STR_LIT> : return LowerSVEIntrinsicDUP ( N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return LowerSVEIntrinsicEXT ( N , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return combineSVEReductionOrderedFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return combineSVEReductionFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return combineSVEReductionFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return combineSVEReductionFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return combineSVEReductionFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return combineSVEReductionFP ( N , <STR_LIT> , DAG ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , false , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> : return tryConvertSVEWideCompare ( N , <STR_LIT> , true , DCI , DAG ) ; case <STR_LIT> :

return getPTest ( DAG , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , <STR_LIT> ) ;


<s> <ISA_LIT>ConstantPoolMBB :: <ISA_LIT>ConstantPoolMBB ( LLVMContext & C , const MachineBasicBlock * mbb , unsigned id , unsigned char PCAdj , <STR_LIT> Modifier , bool AddCurrentAddress ) : <ISA_LIT>ConstantPoolValue ( C , id , <STR_LIT> , PCAdj , Modifier , AddCurrentAddress ) , MBB ( mbb ) {


<s> bool <ISA_LIT>IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ;


<s> if ( flag_pic ) return false ; if ( SYMBOL_REF_SMALL_P ( symbol ) ) return false ; return default_use_anchors_for_symbol_p ( symbol ) ;


<s> if ( need_atomic_barrier_p ( model , true ) ) emit_insn ( gen_memory_barrier ( ) ) ;


<s> else { if ( state_transition ( state , mips_ls2 . alu2_turn_enabled_insn ) >= <NUM_LIT> ) gcc_unreachable ( ) ; } if ( cpu_unit_reservation_p ( state , mips_ls2 . falu1_core_unit_code ) ) { gcc_unreachable ( ) ; mips_ls2 . falu1_turn_p = false ; } if ( cpu_unit_reservation_p ( state , mips_ls2 . falu2_core_unit_code ) ) mips_ls2 . falu1_turn_p = true ; if ( mips_ls2 . falu1_turn_p ) { if ( state_transition ( state , mips_ls2 . falu1_turn_enabled_insn ) >= <NUM_LIT> ) gcc_unreachable ( ) ; }


<s> StringRef DispatchPtrName = <STR_LIT> ( <STR_LIT> ) ; Function * DispatchPtr = F . getParent ( ) -> getFunction ( DispatchPtrName ) ; if ( ! DispatchPtr ) return PreservedAnalyses :: all ( ) ; for ( Instruction & I : instructions ( F ) ) { if ( CallInst * CI = dyn_cast < CallInst > ( & I ) ) { if ( CI -> getCalledFunction ( ) == DispatchPtr ) processUse ( CI ) ; } } return PreservedAnalyses :: all ( ) ;


return ( int16x4_t ) __builtin_neon_vld1_lanev4hi ( ( const __builtin_neon_hi * ) __a , __b , __c ) ;


<s> RTLIB :: Libcall LC ; if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; else LC = RTLIB :: getFPTOUINT ( Op0 . getValueType ( ) , N -> getValueType ( <NUM_LIT> ) ) ; MakeLibCallOptions CallOptions ; EVT OpVT = Op0 . getValueType ( ) ; CallOptions . setTypeListBeforeSoften ( OpVT , N -> getValueType ( <NUM_LIT> ) , true ) ; SDValue Chain = IsStrict ? N -> getOperand ( <NUM_LIT> ) : SDValue ( ) ; SDValue Result ; std :: tie ( Result , Chain ) = makeLibCall ( DAG , LC , N -> getValueType ( <NUM_LIT> ) , Op0 , CallOptions , DL , Chain ) ; Results . push_back ( Result ) ; if ( IsStrict ) Results . push_back ( Chain ) ; break ; } case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RCW ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOpWithSExt ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ;


<s> MandarinGenSubtargetInfo ( TT , CPU , FS ) {


<s> if ( argspace_offset ) { emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( argspace_offset ) ) ) ; argspace_offset = <NUM_LIT> ; } mem = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; insn = emit_move_insn ( gen_raw_REG ( SImode , regno ) , mem ) ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_INC , stack_pointer_rtx , REG_NOTES ( insn ) ) ; } if ( last_movem_reg != - <NUM_LIT> ) { rtx insn ; if ( argspace_offset ) { emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( argspace_offset ) ) ) ; argspace_offset = <NUM_LIT> ; } mem = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; insn = emit_insn ( cris_gen_movem_load ( mem , GEN_INT ( last_movem_reg + <NUM_LIT> ) ) ) ; if ( side_effects_p ( PATTERN ( insn ) ) ) REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_INC , stack_pointer_rtx , REG_NOTES ( insn ) ) ; } if ( frame_pointer_needed ) { rtx insn ; emit_insn ( gen_cris_frame_deallocated_barrier ( ) ) ; emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; mem = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; insn = emit_move_insn ( hard_frame_pointer_rtx , mem ) ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_INC , stack_pointer_rtx , REG_NOTES ( insn ) ) ; } else if ( ( size + argspace_offset ) != <NUM_LIT> ) { emit_insn ( gen_cris_frame_deallocated_barrier ( ) ) ; size += argspace_offset ; emit_insn ( gen_add2_insn ( stack_pointer_rtx , GEN_INT ( size ) ) ) ; } if ( return_address_on_stack && pretend == <NUM_LIT> ) { if ( crtl -> calls_eh_return ) { rtx mem ; rtx insn ; rtx srpreg = gen_raw_REG ( SImode , CRIS_SRP_REGNUM ) ; mem = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; insn = emit_move_insn ( srpreg , mem ) ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_INC , stack_pointer_rtx , REG_NOTES ( insn ) ) ; if ( crtl -> calls_eh_return ) emit_insn ( gen_add2_insn ( stack_pointer_rtx , gen_raw_REG ( SImode , CRIS_STACKADJ_REG ) ) ) ; cris_expand_return ( false ) ; } else cris_expand_return ( true ) ; return ; } if ( pretend != <NUM_LIT> ) { if ( return_address_on_stack ) { rtx mem ; rtx srpreg = gen_raw_REG ( SImode , CRIS_SRP_REGNUM ) ; rtx insn ; mem = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; insn = emit_move_insn ( srpreg , mem ) ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_INC , stack_pointer_rtx , REG_NOTES ( insn ) ) ;


<s> const DivRemEntry & TypeEntry = * OpEntryIt ; const DivRemEntry :: DivRemResult & OpEntry = TypeEntry . ResultTable [ OpIndex ] ; const TargetRegisterClass * RegRC = getRegClass ( RegTy , * RegRB ) ; if ( ! RBI . constrainGenericRegister ( Op1Reg , * RegRC , MRI ) || ! RBI . constrainGenericRegister ( Op2Reg , * RegRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * RegRC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( OpEntry . OpCopy ) , TypeEntry . LowInReg ) . addReg ( Op1Reg ) ; if ( OpEntry . OpSignExtend ) { if ( OpEntry . IsOpSigned ) BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( OpEntry . OpSignExtend ) ) ; else { Register Zero32 = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Zero32 ) ; if ( RegTy . getSizeInBits ( ) == <NUM_LIT> ) { BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Copy ) , TypeEntry . HighInReg ) . addReg ( Zero32 , <NUM_LIT> , <STR_LIT> ) ; } else if ( RegTy . getSizeInBits ( ) == <NUM_LIT> ) { BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Copy ) , TypeEntry . HighInReg ) . addReg ( Zero32 ) ; } else if ( RegTy . getSizeInBits ( ) == <NUM_LIT> ) { BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , TypeEntry . HighInReg ) . addImm ( <NUM_LIT> ) . addReg ( Zero32 ) . addImm ( <STR_LIT> ) ; } } } BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( OpEntry . OpDivRem ) ) . addReg ( Op2Reg ) ;

if ( ( I . getOpcode ( ) == Instruction :: SRem || I . getOpcode ( ) == Instruction :: URem ) && OpEntry . DivRemResultReg == <STR_LIT> && STI . is64Bit ( ) ) {


<s> bool AMDGPUPassConfig :: addInstSelector ( ) {

addPass ( createAMDGPUPeepholeOpt ( * TM ) ) ;


<s> } theEntry -> contOnRegs . insert ( regNum ) ; if ( DEBUGME ) { errs ( ) << <STR_LIT> << loopRep -> getHeader ( ) -> getNumber ( ) << <STR_LIT> << regNum << <STR_LIT> ; }


<s> if ( Flags . isByVal ( ) ) { return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ; } return DAG . getStore ( Chain , dl , Arg , PtrOff , PseudoSourceValue :: getStack ( ) , LocMemOffset , false , false , <NUM_LIT> ) ;


<s> } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getNumExplicitOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> BranchCode = <STR_LIT> ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ;


if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ;


<s> delete m_pRelaDyn ; delete m_pRelaPLT ; delete m_pDynamic ;


<s> for ( unsigned i = <NUM_LIT> , N = Elements . getNumElements ( ) ; i < N ; ++ i ) { DIDescriptor Element = Elements . getElement ( i ) ; if ( Element . getTag ( ) == dwarf :: DW_TAG_subrange_type ) { TypeNo = TypeNo << <STR_LIT> ; TypeNo = TypeNo | <STR_LIT> ; DISubrange SubRange = DISubrange ( Element . getGV ( ) ) ; Dimension [ i ] = SubRange . getHi ( ) - SubRange . getLo ( ) + <NUM_LIT> ;

Aux [ <NUM_LIT> + i * <NUM_LIT> + <NUM_LIT> ] = Dimension [ i ] ;


<s> break ; case MEM : operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , DImode , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , DImode , <NUM_LIT> ) ; break ; case CONST_DOUBLE : gcc_assert ( operands [ <NUM_LIT> ] == CONST0_RTX ( TFmode ) ) ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] = const0_rtx ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case REG :

operands [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ;


<s> return IsDoLoop ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsDoLoop ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsDoLoop ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsDoLoop ? <STR_LIT> : <STR_LIT> ;


<s> bool findAllNVVMAnnotation ( const GlobalValue * gv , const std :: string & prop , std :: vector < unsigned > & retval ) { MutexGuard Guard ( Lock ) ; const Module * m = gv -> getParent ( ) ; if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;

else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;


<s> MI . setDesc ( HII -> get ( NewOpcode ) ) ; return true ;


<s> tilepro_expand_high_multiply ( op0 , op1 , op2 , false ) ;


<s> case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ;

return TII . getInlineAsmLength ( MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;


<s> CallingConv :: ID CC = MF -> getFunction ( ) . getCallingConv ( ) ; return ( ( CC == CallingConv :: <ISA_LIT>_INTR || CC == CallingConv :: <ISA_LIT>_SIGNAL ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ) ;


<s> assert ( TRI -> isVGPR ( * MRI , Opnd . getReg ( ) ) ) ; } ) ; for ( signed RegNo = Interval . first ; RegNo < Interval . second ; ++ RegNo ) { setRegScore ( RegNo , EXP_CNT , Val ) ; }


<s> assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; MVT MaskEltVT = <STR_LIT> ( VT . getScalarSizeInBits ( ) ) ; MVT MaskVecVT = <STR_LIT> ( MaskEltVT , VT . getVectorNumElements ( ) ) ; SDValue MaskNode = getConstVector ( Mask , MaskVecVT , DAG , DL , true ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , VT , MaskNode , V1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , MaskNode , V2 ) ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizeBSwap ( LegalizerHelper & Helper , MachineRegisterInfo & MRI , MachineInstr & MI ) const { LLT S8 = LLT :: scalar ( <NUM_LIT> ) ; assert ( MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) == S8 ) ; assert ( MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) == S8 ) ;

Helper . Observer . changingInstr ( MI ) ;


<s> const Triple & TheTriple = STI . getTargetTriple ( ) ; Is<ISA_LIT>64 = TheTriple . is<ISA_LIT>64 ( ) ;


<s> return false ; } else if ( which_group == previous_group ) { if ( is_dispatch_slot_restricted ( insn ) ) return true ; return false ; }


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ;

Init<ISA_LIT>MCRegisterInfo ( X , llvm :: <STR_LIT> , <NUM_LIT> , <NUM_LIT> , llvm :: <STR_LIT> ) ;


<s> if ( ! isValid ( ) ) return Other ; if ( * this == Other ) return * this ; return <STR_LIT> ( ) ;


<s> auto & Callee = CLI . Callee ; auto CalleeCC = CLI . CallConv ; auto IsVarArg = CLI . IsVarArg ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) return false ; if ( IsVarArg ) return false ; if ( CCInfo . getNextStackOffset ( ) != <NUM_LIT> ) return false ;

auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ;


<s> if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ;


<s> if ( N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N -> getMaskElt ( i ) ; if ( Elt >= <NUM_LIT> && Elt != <NUM_LIT> ) return false ; } bool HasHi = false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) {


<s> bool stack_top_dies = find_regno_note ( insn , REG_DEAD , FIRST_STACK_REG ) ; bool dimode_p = GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ; int round_mode = get_attr_i387_cw ( insn ) ; static char buf [ <NUM_LIT> ] ; const char * p ; if ( ( dimode_p || fisttp ) && ! stack_top_dies ) output_asm_insn ( <STR_LIT> , operands ) ; gcc_assert ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( MEM_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( GET_MODE ( operands [ <NUM_LIT> ] ) != TFmode ) ; if ( fisttp ) return <STR_LIT> ; strcpy ( buf , <STR_LIT> ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( <STR_LIT> , operands ) ; p = <STR_LIT> ; strcat ( buf , p + ! ( stack_top_dies || dimode_p ) ) ;


<s> arch_id = mcu -> arch_id ; print_mcus ( n_mcus ) ; n_mcus = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < sizeof ( avr_texinfo ) / sizeof ( * avr_texinfo ) ; i ++ ) if ( arch_id == avr_texinfo [ i ] . arch_id ) printf ( <STR_LIT> , mcu -> name , avr_texinfo [ i ] . texinfo ) ;


<s> unsigned getNumFixupKinds ( ) const override {


<s> for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) if ( Contents [ i ] . Tag == Attribute ) return & Contents [ i ] ;


<s> const InstructionSelector * getInstructionSelector ( ) const override { assert ( GISel && <STR_LIT> ) ;

return GISel -> getInstructionSelector ( ) ;


<s> assert ( Base < <NUM_LIT> && <STR_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: CreateReg ( GP0Regs [ Base ] ) ) ; else if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . insert ( Inst . begin ( ) , MCOperand :: CreateReg ( GP0Regs [ Base ] ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( SignExtend64 < <NUM_LIT> > ( Disp << <NUM_LIT> ) ) ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , PartialBits , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , DCI , Subtarget ) ) return FPLogic ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue R = combineAndNotIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; }

if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) {


<s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {

addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ;


<s> ThumbBETargetMachine :: ThumbBETargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : ThumbTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> static struct machine_function * moxie_init_machine_status ( void ) {

return ggc_cleared_alloc < machine_function > ( ) ;


<s> assert ( isImm ( ) ) ; Imm . Kind = ImmKindTyConst ;


<s> } else { assert ( VA . isMemLoc ( ) ) ; ResultMemLocs . push_back ( std :: make_pair ( VA . getLocMemOffset ( ) , InVals . size ( ) ) ) ; InVals . push_back ( SDValue ( ) ) ; } } SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( unsigned i = <NUM_LIT> , e = ResultMemLocs . size ( ) ; i != e ; ++ i ) { int offset = ResultMemLocs [ i ] . first ; unsigned index = ResultMemLocs [ i ] . second ;

SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;


<s> return C_Other ; case 'x' : case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ;


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetGlobalAddressSymbol ( const MachineOperand & MO ) const { switch ( MO . getTargetFlags ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : break ; }

return Printer . GetGlobalValueSymbol ( MO . getGlobal ( ) ) ;


<s> return new <ISA_LIT>MCInstrAnalysis ( Info ) ;


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitST_F16_PSEUDO ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; Register Ws = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Rt = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineMemOperand & MMO = * * MI . memoperands_begin ( ) ; unsigned Imm = MMO . getOffset ( ) ; const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? RegInfo . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : ( Subtarget . isABI_O32 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; const bool Using<ISA_LIT>32 = RC == & <STR_LIT> ; Register Rs = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Rs ) . addReg ( Ws ) . addImm ( <NUM_LIT> ) ; if ( ! Using<ISA_LIT>32 ) { Register Tmp = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addImm ( <NUM_LIT> ) . addReg ( Rs ) . addImm ( <STR_LIT> ) ; Rs = Tmp ; } BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Rs ) . addReg ( Rt ) . addImm ( Imm ) . addMemOperand ( BB -> getParent ( ) -> getMachineMemOperand ( & MMO , MMO . getOffset ( ) , MMO . getSize ( ) ) ) ; MI . eraseFromParent ( ) ;


<s> virtual bool hasScatteredSymbols ( ) const {


<s> switch ( ByteSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : RC = <STR_LIT> ; LoOpc = HiOpc = Opc8 ; LoIdx = HiIdx = <STR_LIT> ; HiOff = <NUM_LIT> ; return false ; case <NUM_LIT> : if ( Has16BitE<ISA_LIT>Ops ) { RC = <STR_LIT> ; LoOpc = HiOpc = Opc16 ; LoIdx = HiIdx = <STR_LIT> ; HiOff = <NUM_LIT> ; return false ; } RC = <STR_LIT> ; LoOpc = HiOpc = Opc8 ; LoIdx = <STR_LIT> ;


<s> if ( ! F . hasFnAttribute ( Attribute :: AlwaysInline ) ) F . addFnAttr ( Attribute :: AlwaysInline ) ; F . setLinkage ( GlobalValue :: LinkageTypes :: AvailableExternallyLinkage ) ;


<s> const auto & HRI = static_cast < const <ISA_LIT>RegisterInfo & > ( TRI ) ; bool IsSubLo = ( Idx == HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ) ; bool IsSubHi = ( Idx == HRI . get<ISA_LIT>SubRegIndex ( RC , <STR_LIT> ) ) ; assert ( IsSubLo != IsSubHi && <STR_LIT> ) ;


<s> if ( IsEVEX_V256 ) { auto It = EvexToVex256Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex256Table . end ( ) ) NewOpc = It -> second ; } else if ( IsEVEX_V128 ) { auto It = EvexToVex128Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex128Table . end ( ) ) NewOpc = It -> second ; } if ( ! NewOpc ) return false ;

if ( usesExtendedRegister ( MI ) ) return false ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getShiftRight8Imm ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return <NUM_LIT> - MI . getOperand ( Op ) . getImm ( ) ;


<s> <ISA_LIT>VectorPrint ( ) : MachineFunctionPass ( ID ) , QST ( <NUM_LIT> ) , QII ( <NUM_LIT> ) , QRI ( <NUM_LIT> ) { initialize<ISA_LIT>VectorPrintPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> case MCBinaryExpr :: Opcode :: Add : OS << <STR_LIT> ; break ; case MCBinaryExpr :: Opcode :: Sub : OS << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } printExpr ( BinExp -> getRHS ( ) , OS ) ; break ; case MCExpr :: ExprKind :: Constant :

OS << dyn_cast < MCConstantExpr > ( Expr ) -> getValue ( ) ;


<s> vec_safe_push ( params , args [ <NUM_LIT> ] ) ; tree decl = rs6000_builtin_decls [ RS6000_OVLD_VEC_CMPEQ ] ; tree call = altivec_resolve_overloaded_builtin ( loc , decl , params ) ; call = save_expr ( call ) ; params = make_tree_vector ( ) ; vec_safe_push ( params , call ) ; vec_safe_push ( params , call ) ; decl = rs6000_builtin_decls [ RS6000_OVLD_VEC_NOR ] ; * res = resolved ; return altivec_resolve_overloaded_builtin ( loc , decl , params ) ; } default : * res = resolved_bad ; return error_mark_node ; }


<s> case AppleA10 : case AppleA11 : case AppleA12 : case AppleA13 : case AppleA14 : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN2 : PrefFunctionLogAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case NeoverseV1 : PrefFunctionLogAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 :


<s> bool isMem ( ) const override { return Kind == Memory ;


<s> bool <ISA_LIT>TargetLowering :: useStackGuardXorFP ( ) const {

return Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ;


<s> MCSection * <ISA_LIT>TargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { assert ( false && <STR_LIT> <STR_LIT> ) ; return <NUM_LIT> ;


<s> assert ( Offset >= <NUM_LIT> && Offset <= <NUM_LIT> && <STR_LIT> ) ; emitARM64WinUnwindCode ( Win64EH :: UOP_SaveFReg , Reg , Offset ) ;


<s> return ( __m512i ) __builtin_ia32_vcvttph2uw512_mask_round ( __A , ( __v32hi ) _mm512_setzero_si512 ( ) , ( __mmask32 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> bool <ISA_LIT>TargetObjectFile :: IsGlobalInSmallSectionImpl ( const GlobalObject * GO , const TargetMachine & TM ) const { const <ISA_LIT>Subtarget & Subtarget = * static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GO ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t OSABI ) {

MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ;


<s> if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ;


<s> SDValue CC = Op . getOperand ( <NUM_LIT> ) ; SDValue Lo = CC . getOperand ( <NUM_LIT> ) ; SDValue Hi = CC . getOperand ( <NUM_LIT> ) ; EVT CCVT = CC . getValueType ( ) ; EVT LoVT = Lo . getValueType ( ) ; if ( CCVT . getVectorNumElements ( ) == ( LoVT . getVectorNumElements ( ) * <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Lo , Hi ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: hasNumUsesBelowThresGA ( SDNode * N ) const { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) return true ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( N ) ; DenseMap < const GlobalValue * , unsigned > :: const_iterator GI = GlobalAddressUseCountMap . find ( GA -> getGlobal ( ) ) ; if ( GI == GlobalAddressUseCountMap . end ( ) ) return false ; return GI -> second <= MaxNumOfUsesForConstExtenders ;


<s> DataAddr_Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Call , OperFlag ) ; SeqStart = DAG . getCALLSEQ_START ( Chain , ZeroOperand ) ; Chain = getChain ( SeqStart ) ; OperFlag = getOutFlag ( SeqStart ) ; Data_Lo = DAG . getNode ( <STR_LIT> , dl , VTList , Lo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue HiOps [ <NUM_LIT> ] = { Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Data_Lo . getValue ( <NUM_LIT> ) } ; Data_Hi = DAG . getNode ( <STR_LIT> , dl , VTList , HiOps , <NUM_LIT> ) ; PCLATH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Data_Hi ) ; Callee = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Data_Lo , PCLATH ) ; Call = DAG . getNode ( <STR_LIT> , dl , Tys , Chain , Callee , OperFlag ) ; Chain = getChain ( Call ) ;


<s> if ( PHINode * PhiInst = dyn_cast < PHINode > ( User ) ) return PhiInst -> getIncomingBlock ( Use . getOperandNo ( ) ) -> getTerminator ( ) ; return User ;


<s> return __builtin_loongson_pinsrh_1_s ( s , t ) ;


<s> bool isImm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool hasAsi = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned asi = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned rs2 = <NUM_LIT> ; unsigned simm13 = <NUM_LIT> ; if ( isImm ) simm13 = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; else rs2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus status ; if ( isLoad ) { status = DecodeRD ( MI , rd , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } status = DecodeIntRegsRegisterClass ( MI , rs1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( isImm ) MI . addOperand ( MCOperand :: createImm ( simm13 ) ) ; else { status = DecodeIntRegsRegisterClass ( MI , rs2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } if ( hasAsi ) MI . addOperand ( MCOperand :: createImm ( asi ) ) ; if ( ! isLoad ) { status = DecodeRD ( MI , rd , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } return MCDisassembler :: Success ;


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RegClass = OpInfo [ OpIdx ] . RegClass ; assert ( ( RegClass == <STR_LIT> || RegClass == <STR_LIT> ) && <STR_LIT> ) ; bool isSP = ( RegClass == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , decodeVFPRd ( insn , isSP ) ) ) ) ; ++ OpIdx ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;


<s> ForCodeSize = MF . getFunction ( ) . hasOptSize ( ) ;

Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> return OpRef ( Whole | ( N & Index ) ) ;


<s> return MF -> getTarget ( ) . getTargetAsmInfo ( ) -> getInlineAsmLength ( AsmStr ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; default : return <NUM_LIT> ;


<s> if ( SYMBOL_REF_P ( x ) ) return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; else return false ;


<s> if ( ! OrigOp . isMem ( ) ) return false ; unsigned OrigReg = OrigOp . Mem . BaseReg ; unsigned FinalReg = FinalOp . Mem . BaseReg ; if ( RegClassID != - <NUM_LIT> && ! <ISA_LIT>MCRegisterClasses [ RegClassID ] . contains ( OrigReg ) ) { return Error ( OrigOp . getStartLoc ( ) , <STR_LIT> ) ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( OrigReg ) ) RegClassID = <STR_LIT> ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( OrigReg ) ) RegClassID = <STR_LIT> ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( OrigReg ) ) RegClassID = <STR_LIT> ; else return false ; bool IsSI = IsSIReg ( FinalReg ) ; FinalReg = GetSIDIForRegClass ( RegClassID , FinalReg , IsSI ) ; if ( FinalReg != OrigReg ) { std :: string RegName = IsSI ? <STR_LIT> : <STR_LIT> ; Warnings . push_back ( std :: make_pair ( OrigOp . getStartLoc ( ) , <STR_LIT> + RegName + <STR_LIT> ) ) ; } FinalOp . Mem . Size = OrigOp . Mem . Size ; FinalOp . Mem . SegReg = OrigOp . Mem . SegReg ; FinalOp . Mem . BaseReg = FinalReg ; } } for ( auto & WarningMsg : Warnings ) { Warning ( WarningMsg . first , WarningMsg . second ) ; } for ( unsigned int i = <NUM_LIT> ; i < FinalOperands . size ( ) ; ++ i ) OrigOperands . pop_back ( ) ; } for ( unsigned int i = <NUM_LIT> ; i < FinalOperands . size ( ) ; ++ i ) OrigOperands . push_back ( std :: move ( FinalOperands [ i ] ) ) ;


<s> } case <STR_LIT> : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; MachineInstrBuilder LO16 , HI16 ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , getDefRegState ( true ) ) . addReg ( DstReg ) ; if ( MO . isImm ( ) ) { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; HI16 = HI16 . addGlobalAddress ( GV , MO . getOffset ( ) , TF | <STR_LIT> ) ; } AddDefaultPred ( LO16 ) ; AddDefaultPred ( HI16 ) ; } MI . eraseFromParent ( ) ; Modified = true ; } } MBBI = NMBBI ; }


<s> const std :: vector < MachineDomTreeNode * > & Children = Node -> getChildren ( ) ; OpenChildren [ Node ] = Children . size ( ) ; for ( MachineDomTreeNode * Child : Children ) WorkList . push_back ( Child ) ;


<s> assert ( Base < <NUM_LIT> && <STR_LIT> ) ; switch ( Inst . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( GP0Regs [ Base ] ) ) ; break ; case <STR_LIT> :


<s> unsigned Binary = <NUM_LIT> ; bool isSPVFP = false ; RegN = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegN , & isSPVFP ) ; if ( ! isSPVFP ) Binary |= RegN << <STR_LIT> ; else { Binary |= ( ( RegN & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( RegN & <NUM_LIT> ) << <STR_LIT> ; } return Binary ;


<s> if ( ! isU6 && ! isImmU16 ( Offset ) ) { cerr << <STR_LIT> << Offset << <STR_LIT> ; abort ( ) ; }


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; MCB . setLoc ( IDLoc ) ; const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; <ISA_LIT>MCChecker Check ( getContext ( ) , MCII , getSTI ( ) , MCB , * RI ) ; bool CheckOk = <ISA_LIT>MCInstrInfo :: canonicalizePacket ( MCII , getSTI ( ) , getContext ( ) , MCB , & Check ) ; if ( CheckOk ) { if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) == <NUM_LIT> ) { assert ( ! <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCB ) ) ; assert ( ! <ISA_LIT>MCInstrInfo :: isOuterLoop ( MCB ) ) ;


<s> return <ISA_LIT>_EXPAND_PSEUDO_NAME ;


<s> assert ( ScratchReg != MaskReg && <STR_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( OldValReg ) . addReg ( NewValReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( MaskReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( OldValReg ) . addReg ( ScratchReg ) ;


<s> unsigned int flags = call_properties ( ) ; if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ; return flags & ( CP_WRITE_MEMORY | CP_WRITE_CSR ) ;


<s> int Size = Mask . size ( ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return true ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ;

addPass ( create<ISA_LIT>CleanupVSETVLIPass ( ) ) ;


<s> if ( reload_completed && cfun -> machine && ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal ) ) return <NUM_LIT> ;


<s> static int c6x_save_reg ( unsigned int regno ) { return ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || ( regno == RETURN_ADDR_REGNO && ( df_regs_ever_live_p ( regno ) || ! crtl -> is_leaf ) ) || ( regno == PIC_OFFSET_TABLE_REGNUM && must_reload_pic_reg_p ( ) ) ) ;


<s> } return cast < ConstantSDNode > ( VOffset ) -> getSExtValue ( ) + cast < ConstantSDNode > ( SOffset ) -> getSExtValue ( ) + cast < ConstantSDNode > ( Offset ) -> getSExtValue ( ) ;


return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> if ( ! AUIPCSymbol ) return false ; const MCFixup * TargetFixup = getPCRelHiFixup ( ) ; if ( ! TargetFixup ) return false ; if ( ( unsigned ) TargetFixup -> getKind ( ) != <STR_LIT> ) return false ; MCValue Target ; if ( ! TargetFixup -> getValue ( ) -> evaluateAsValue ( Target , * Layout ) ) return false ; if ( ! Target . getSymA ( ) || ! Target . getSymA ( ) -> getSymbol ( ) . isInSection ( ) ) return false ; if ( & Target . getSymA ( ) -> getSymbol ( ) . getSection ( ) != findAssociatedFragment ( ) -> getParent ( ) ) return false ; uint64_t AUIPCOffset = AUIPCSymbol -> getOffset ( ) ; Res = MCValue :: get ( Target . getSymA ( ) , nullptr , Target . getConstant ( ) + ( Fixup -> getOffset ( ) - AUIPCOffset ) ) ; return true ;


<s> break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) || ( isTargetMachO ( ) && ! HasV6Ops ) ) ReservedGPRegisters . set ( <NUM_LIT> ) ; const int restFP = ( useR7AsFramePointer ( ) ) ? <NUM_LIT> : <NUM_LIT> ; if ( isGPRegisterReserved ( restFP ) ) report_fatal_error ( <STR_LIT> + std :: to_string ( restFP ) + <STR_LIT> ) ; if ( MVEVectorCostFactor == <NUM_LIT> ) MVEVectorCostFactor = <NUM_LIT> ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA9 : LdStMultipleTiming = DoubleIssueCheckUnalignedAccess ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case CortexA12 : break ; case CortexA15 : MaxInterleaveFactor = <NUM_LIT> ; PreISelOperandLatencyAdjustment = <NUM_LIT> ; PartialUpdateClearance = <NUM_LIT> ; break ; case CortexA17 : case CortexA32 : case CortexA35 : case CortexA53 : case CortexA55 : case CortexA57 : case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : case CortexR4 : case CortexR4F : case CortexR5 : case CortexR7 : case CortexM3 : case CortexR52 : break ; case Exynos : LdStMultipleTiming = SingleIssuePlusExtras ; MaxInterleaveFactor = <NUM_LIT> ; if ( ! isThumb ( ) ) PrefLoopLogAlignment = <NUM_LIT> ; break ; case Kryo : break ; case Krait : PreISelOperandLatencyAdjustment = <NUM_LIT> ; break ; case NeoverseN1 : break ; case Swift : MaxInterleaveFactor = <NUM_LIT> ; LdStMultipleTiming = SingleIssuePlusExtras ; PreISelOperandLatencyAdjustment = <NUM_LIT> ;


<s> MCSubtargetInfo * X = new MCSubtargetInfo ( ) ;

Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ;


<s> InstrItins = getInstrItineraryForCPU ( CPU ) ; StringRef GPU = CPU ; Is64bit = false ; DefaultSize [ <NUM_LIT> ] = <NUM_LIT> ; DefaultSize [ <NUM_LIT> ] = <NUM_LIT> ; DefaultSize [ <NUM_LIT> ] = <NUM_LIT> ; HasVertexCache = false ; TexVTXClauseSize = <NUM_LIT> ; Gen = AMDGPUSubtarget :: R600 ;


<s> i != ie ; ++ i ) { unsigned align ; if ( PMFI -> isMethodCacheRegionEntry ( & * i ) ) { align = MinSubfunctionAlignment ; } else { align = i -> getAlignment ( ) . value ( ) ; }

if ( align > i -> getAlignment ( ) . value ( ) ) {


<s> if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> isBarrier ( ) ;


<s> unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( is32Bit ) return MCDisassembler :: Fail ; status = DecodeDataRegsRegisterClass ( Inst , s1_d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeDataRegsRegisterClass ( Inst , s2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( n ) ) ; return MCDisassembler :: Success ;


<s> return ( ( qword ) ( vec_rsqrte ( ( vec_float4 ) ( a ) ) ) ) ;


<s> SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return ErrorIfNotPending ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return ErrorIfNotPending ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ; Parser . Lex ( ) ; } else while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return ErrorIfNotPending ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { if ( parseBracketSuffix ( Name , Operands ) ) return true ; } else if ( getLexer ( ) . is ( AsmToken :: LParen ) && parseParenSuffix ( Name , Operands ) ) return true ; } }

if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) {


<s> EmitByte ( ( Value >> ( <NUM_LIT> * i ) ) & <NUM_LIT> , OS ) ;


<s> CurrSrcOffset = <NUM_LIT> ; CurrSrc = nullptr ;


<s> bool <ISA_LIT>FrameLowering :: needsFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) return false ;


<s> else if ( rclass == CR_REGS ) ret = <NUM_LIT> ; else if ( ( rs6000_cpu == PROCESSOR_POWER6 || rs6000_cpu == PROCESSOR_POWER7 || rs6000_cpu == PROCESSOR_POWER8 || rs6000_cpu == PROCESSOR_POWER9 ) && reg_classes_intersect_p ( rclass , LINK_OR_CTR_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; else ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; } else if ( VECTOR_MEM_VSX_P ( mode ) && reg_classes_intersect_p ( to , VSX_REGS ) && reg_classes_intersect_p ( from , VSX_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( FIRST_FPR_REGNO , mode ) ; else if ( reg_classes_intersect_p ( to , from ) ) ret = ( FLOAT128_2REG_P ( mode ) ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode , from , GENERAL_REGS ) ) ; if ( TARGET_DEBUG_COST ) { if ( dbg_cost_ctrl == <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , ret , GET_MODE_NAME ( mode ) , reg_class_names [ from ] , reg_class_names [ to ] ) ; dbg_cost_ctrl -- ; } return ret ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ;

return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ;


<s> bool Success = HSAMetadataStream -> emitTo ( * getTargetStreamer ( ) ) ; ( void ) Success ; assert ( Success && <STR_LIT> ) ; } if ( ! IsaInfo :: hasCodeObjectV3 ( getGlobalSTI ( ) ) ) { if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) {


<s> case <NUM_LIT> : return ( regno % <NUM_LIT> ) == <NUM_LIT> ; case <NUM_LIT> : return ( regno % <NUM_LIT> ) == <NUM_LIT> ; case <NUM_LIT> : return ( regno % <NUM_LIT> ) == <NUM_LIT> ; case <NUM_LIT> : return ( regno % <NUM_LIT> ) == <NUM_LIT> ; default : gcc_assert ( mode == BLKmode || mode == VOIDmode ) ; return ( regno % <NUM_LIT> ) == <NUM_LIT> ;


<s> RegisterRef ( Register R = <NUM_LIT> , unsigned S = <NUM_LIT> ) : Reg ( R ) , Sub ( S ) {


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( CmpMask != MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; if ( SrcReg == MI -> getOperand ( CommonUse ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ) return true ; break ; case <STR_LIT> : { const MachineInstr & Copy = * MI ; MachineBasicBlock :: iterator AND ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) ; if ( AND == MI -> getParent ( ) -> end ( ) ) return false ; MI = AND ;

return isSuitableForMask ( MI , Copy . getOperand ( <NUM_LIT> ) . getReg ( ) , CmpMask , true ) ;