<s> for ( auto & Node1 : VectorNode ) Node1 -> setVisit ( false ) ; val += printTreeVal ( Root ) ; return val ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override {


<s> static SDValue PerformBLENDICombine ( SDNode * N , SelectionDAG & DAG ) { SDValue V0 = N -> getOperand ( <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) if ( auto * Mask = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( Mask -> getZExtValue ( ) == <NUM_LIT> && ! isShuffleFoldableLoad ( V0 ) ) { SDValue NewMask = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V0 , NewMask ) ; } return SDValue ( ) ;


<s> enum ix86_builtin_func_type ftype ; const struct builtin_description * d ; size_t i ; tree decl ; tree attrs_load , attrs_type_load , attrs_store , attrs_type_store ; tree attrs_log , attrs_type_log ; if ( ! flag_tm ) return ; if ( ! builtin_decl_explicit_p ( BUILT_IN_TM_LOAD_1 ) ) return ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOAD_1 ) ; attrs_load = DECL_ATTRIBUTES ( decl ) ; attrs_type_load = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_STORE_1 ) ; attrs_store = DECL_ATTRIBUTES ( decl ) ; attrs_type_store = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOG ) ;


auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < <NUM_LIT> ; } ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_<ISA_LIT> , false ) {


<s> if ( ! ( MOpSHMI . isImm ( ) && MOpMEMI . isImm ( ) ) ) return false ; uint64_t SHMI = MOpSHMI . getImm ( ) ; uint64_t MEMI = MOpMEMI . getImm ( ) ; if ( SHMI + MEMI != <NUM_LIT> ) return false ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI -> getOpcode ( ) != <STR_LIT> && SrcMI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! MRI -> hasOneNonDBGUse ( SrcReg ) ) return false ;

assert ( SrcMI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> assert ( Reg < <NUM_LIT> && <STR_LIT> ) ;

if ( StackTop >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ;


<s> case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_8 ; insn -> displacementSize = <NUM_LIT> ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_16 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaRegBase + rm ) ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; } break ; case <NUM_LIT> : case <NUM_LIT> : insn -> eaBaseBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_EAX : EA_BASE_RAX ) ; switch ( mod ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_NONE ; switch ( rm & <NUM_LIT> ) { case <NUM_LIT> : insn -> eaBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_sib : EA_BASE_sib64 ) ; if ( readSIB ( insn ) || readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = EA_BASE_NONE ; insn -> eaDisplacement = EA_DISP_32 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; default : insn -> eaBase = ( EABase ) ( insn -> eaBaseBase + rm ) ; break ; } break ; case <NUM_LIT> : insn -> displacementSize = <NUM_LIT> ; case <NUM_LIT> : insn -> eaDisplacement = ( mod == <NUM_LIT> ? EA_DISP_8 : EA_DISP_32 ) ;


<s> MCInst TmpInst ; Lower<ISA_LIT>MachineInstrToMCInst ( MI , TmpInst , * this ) ;


<s> fixIMPLICITDEF ( MF ) ; fixNoReturn ( MF ) ;


<s> temp . val [ <NUM_LIT> ] = vcombine_s64 ( val . val [ <NUM_LIT> ] , vcreate_s64 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ;

__o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> auto DenominatorScaled = B . buildIntrinsic ( <STR_LIT> , { S32 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto NumeratorScaled = B . buildIntrinsic ( <STR_LIT> , { S32 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto ApproxRcp = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( DenominatorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto NegDivScale0 = B . buildFNeg ( S32 , DenominatorScaled , Flags ) ; if ( ! Mode . allFP32Denormals ( ) ) toggleSPDenormMode ( true , B , ST , Mode ) ; auto Fma0 = B . buildFMA ( S32 , NegDivScale0 , ApproxRcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S32 , Fma0 , ApproxRcp , ApproxRcp , Flags ) ; auto Mul = B . buildFMul ( S32 , NumeratorScaled , Fma1 , Flags ) ; auto Fma2 = B . buildFMA ( S32 , NegDivScale0 , Mul , NumeratorScaled , Flags ) ; auto Fma3 = B . buildFMA ( S32 , Fma2 , Fma1 , Mul , Flags ) ; auto Fma4 = B . buildFMA ( S32 , NegDivScale0 , Fma3 , NumeratorScaled , Flags ) ; if ( ! Mode . allFP32Denormals ( ) ) toggleSPDenormMode ( false , B , ST , Mode ) ;

auto Fmas = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( Fma4 . getReg ( <NUM_LIT> ) ) . addUse ( Fma1 . getReg ( <NUM_LIT> ) ) . addUse ( Fma3 . getReg ( <NUM_LIT> ) ) . addUse ( NumeratorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ;


<s> return ( __m256i ) __builtin_ia32_pmovsxwq256 ( ( __v8hi ) __X ) ;


<s> Immediate |= cast < ConstantSDNode > ( In ) -> getZExtValue ( ) << idx ; HasConstElts = true ; } if ( SplatIdx == - <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( SplatIdx ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; SDValue DstVec ; SDValue Imm ; if ( Immediate ) { MVT ImmVT = <STR_LIT> ( std :: max ( ( int ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; } else if ( HasConstElts ) Imm = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else Imm = DAG . getUNDEF ( VT ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) DstVec = DAG . getBitcast ( VT , Imm ) ; else { SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } for ( unsigned i = <NUM_LIT> ; i < NonConstIdx . size ( ) ; ++ i ) { unsigned InsertIdx = NonConstIdx [ i ] ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , DstVec , Op . getOperand ( InsertIdx ) , DAG . getIntPtrConstant ( InsertIdx , dl ) ) ; }


<s> TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) } ) TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; for ( Target * T : { & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) TargetRegistry :: RegisterMCInstrAnalysis ( * T , createThumbMCInstrAnalysis ) ; for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getTheThumbLETarget ( ) } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ;

for ( Target * T : { & getThe<ISA_LIT>BETarget ( ) , & getTheThumbBETarget ( ) } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ;


<s> if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op1 ) ) if ( C -> getAPIntValue ( ) == <NUM_LIT> ) return EmitTest ( Op0 , <ISA_LIT>CC , DAG ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r ;


<s> void setHasPushSequences ( bool HasPush ) { HasPushSequences = HasPush ;


<s> unsigned MLxExpansion :: getDefReg ( MachineInstr * MI ) const { Register Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isPhysicalRegister ( Reg ) || ! MRI -> hasOneNonDBGUse ( Reg ) ) return Reg ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * UseMI = & * MRI -> use_instr_nodbg_begin ( Reg ) ;

if ( UseMI -> getParent ( ) != MBB ) return Reg ;


<s> bool <ISA_LIT>InstructionSelector :: selectPhi ( Register ResVReg , const <ISA_LIT>Type * ResType , MachineInstr & I ) const { auto MIB = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) ; const unsigned NumOps = I . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; i += <NUM_LIT> ) { MIB . addUse ( I . getOperand ( i + <NUM_LIT> ) . getReg ( ) ) ; MIB . addMBB ( I . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ) ; }

return MIB . constrainAllUses ( TII , TRI , RBI ) ;


<s> unsigned Opc = II -> getOpcode ( ) ; if ( ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; Register BasePtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Opc == <STR_LIT> ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; Register NewDestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const <ISA_LIT>InstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ;

TII -> copyPhysReg ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , NewDestReg , BasePtr , MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetWin64 ( ) ) return & <STR_LIT> ;


<s> if ( last_two_def_reg == NULL_RTX ) return false ; gcc_assert ( REG_P ( last_two_def_reg ) || GET_CODE ( last_two_def_reg ) == SUBREG ) ;

return n8_consumed_by_addr_in_p ( consumer , last_two_def_reg ) ;


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isRegMask ( ) ) { bool ClobbersFP0 = Op . clobbersPhysReg ( <STR_LIT> ) ; static_assert ( <STR_LIT> - <STR_LIT> == <NUM_LIT> , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) assert ( Op . clobbersPhysReg ( <STR_LIT> + i ) == ClobbersFP0 && <STR_LIT> ) ; if ( ClobbersFP0 ) ClobbersFPStack = true ; } if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isImplicit ( ) && <STR_LIT> ) ; if ( Op . isDef ( ) ) STReturns |= <NUM_LIT> << getFPReg ( Op ) ; MI . RemoveOperand ( i ) ; -- i ; -- e ; } assert ( ( ClobbersFPStack || STReturns == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! ClobbersFPStack ) return ;

unsigned N = countTrailingOnes ( STReturns ) ;


<s> SDValue <ISA_LIT>SETargetLowering :: lowerSELECT ( SDValue Op , SelectionDAG & DAG ) const { if ( ! Subtarget . has<ISA_LIT>32r6 ( ) ) return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG ) ;

EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } break ; case <NUM_LIT> : if ( Constraint [ <NUM_LIT> ] == 'T' ) {


<s> void <ISA_LIT>UnifyDivergentExitNodes :: getAnalysisUsage ( AnalysisUsage & AU ) const { if ( RequireAndPreserveDomTree ) AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < PostDominatorTreeWrapperPass > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ; if ( RequireAndPreserveDomTree ) { AU . addPreserved < DominatorTreeWrapperPass > ( ) ; } AU . addPreserved < LegacyDivergenceAnalysis > ( ) ;

AU . addPreservedID ( BreakCriticalEdgesID ) ;


<s> HSAMD :: Metadata HSAMetadata ; if ( HSAMD :: fromString ( HSAMetadataString , HSAMetadata ) ) return false ; return EmitHSAMetadata ( HSAMetadata ) ;


<s> <ISA_LIT>LowerAMXType ( Function & F ) : Func ( F ) {


<s> assert ( ( value >= <NUM_LIT> && value < <NUM_LIT> ) && <STR_LIT> ) ; O << - value ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; } int AddrSpace = dyn_cast < PointerType > ( ValueType ) -> getAddressSpace ( ) ; if ( AddrSpace == <STR_LIT> ) return true ; return false ;


<s> const MCExpr * <ISA_LIT>TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const {

if ( Subtarget -> isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ;


<s> if ( MF . size ( ) < <NUM_LIT> ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ;


<s> return ( poly8x16_t ) __builtin_aarch64_popcountv16qi ( ( int8x16_t ) __a ) ;


<s> if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_SPE_WORD - <NUM_LIT> ) / UNITS_PER_SPE_WORD ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_ALTIVEC_WORD - <NUM_LIT> ) / UNITS_PER_ALTIVEC_WORD ;

return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;


<s> } else if ( LHS . getValueType ( ) == <STR_LIT> ) { Cond = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , <STR_LIT> , LHS , RHS , DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) , CC ) ; Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond ) ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Cond ) ; return Cond ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ;

Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ;


<s> machine = ggc_cleared_alloc < machine_function > ( ) ;

machine -> func_type = CSKY_FT_UNKNOWN ;


<s> static inline int getMClassFlagsMask ( StringRef Flags ) {

if ( Flags . empty ( ) ) return <NUM_LIT> ;


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( ) ; clearRegisterClasses ( ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( <ISA_LIT>16HardFloat ) set<ISA_LIT>16HardFloatLibCalls ( ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm , JITCodeEmitter & mce ) : MachineFunctionPass ( ID ) , JTI ( <NUM_LIT> ) , II ( <NUM_LIT> ) , TD ( <NUM_LIT> ) , TM ( tm ) , MCE ( mce ) , MCPEs ( <NUM_LIT> ) , MJTEs ( <NUM_LIT> ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else {


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AndResult ) . addReg ( ValReg , getKillRegState ( ValIsKill ) ) . addImm ( <NUM_LIT> ) ; ValReg = AndResult ; } case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsNonTemporal && HasSSE2 ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsNonTemporal && HasSSE2 ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { if ( IsNonTemporal && HasSSE4A ) Opc = <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { if ( IsNonTemporal && HasSSE4A ) Opc = <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) Opc = IsNonTemporal ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { Opc = IsNonTemporal ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ;


<s> <ISA_LIT>64TargetMachine :: <ISA_LIT>64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( ! FIST . getNode ( ) ) return Op ;

if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> const MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ;

JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & ST , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( ST ) , TII ( tii ) {


<s> int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { uint64_t SlotSize = TD -> getPointerSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; } return DAG . getFrameIndex ( ReturnAddrIndex , getPointerTy ( ) ) ;


<s> bool isVReg ( ) const { return isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) ;


<s> static DecodeStatus DecodePtrRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) {

if ( static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) -> isGP64 ( ) ) return DecodeGPR64RegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> if ( TLI . SimplifyDemandedVectorElts ( Src , DemandedElts , KnownUndef , KnownZero , DCI ) ) { DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( <STR_LIT> ( Src . getNode ( ) ) && Src . hasOneUse ( ) ) { LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( LN -> isSimple ( ) ) { SDLoc dl ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , LN -> getPointerInfo ( ) , LN -> getAlignment ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N , <NUM_LIT> ) ; } } } return SDValue ( ) ;


<s> if ( analyzeBranch ( MBB , TBB , FBB , Cond , AllowModify ) ) return true ; return true ;


<s> virtual const char * getPassName ( ) const override { return <STR_LIT> ;


<s> __o = __builtin_aarch64_set_qregoiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> assert ( Domain > <NUM_LIT> && Domain < <NUM_LIT> && <STR_LIT> ) ; uint16_t dom = ( MI -> getDesc ( ) . TSFlags >> <STR_LIT> ) & <NUM_LIT> ; assert ( dom && <STR_LIT> ) ; const uint16_t * table = lookup ( MI -> getOpcode ( ) , dom ) ; if ( ! table ) {

assert ( ( Subtarget . hasAVX2 ( ) || Domain < <NUM_LIT> ) && <STR_LIT> ) ;


<s> while ( theCurLine < lineNum ) { fstr . getline ( buff , <NUM_LIT> ) ;


<s> if ( ITBlockSize ) { -- ITBlockSize ; } else if ( Opcode == <STR_LIT> ) { unsigned Mask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned NumTZ = CountTrailingZeros_32 ( Mask ) ; assert ( NumTZ <= <NUM_LIT> && <STR_LIT> ) ; ITBlockSize = <NUM_LIT> - NumTZ ; MachineBasicBlock :: iterator I = MI ; for ( unsigned i = <NUM_LIT> ; i < ITBlockSize ; ++ i ) { do { ++ I ;


<s> if ( ! TargetSupported ) return <NUM_LIT> ; EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ;

if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ( UnsupportedFPMode ) ? <NUM_LIT> : materializeFP ( CFP , VT ) ;


<s> EmitImmediate ( const MCOperand & DispOp , unsigned Size , MCFixupKind FixupKind , unsigned & CurByte , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , int ImmOffset ) const { if ( DispOp . isImm ( ) ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } const MCExpr * Expr = DispOp . getExpr ( ) ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) || FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ;

if ( ImmOffset ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( ImmOffset , Ctx ) , Ctx ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const {

return create<ISA_LIT>ELFObjectWriter ( OSABI , Is64Bit ) ;


<s> if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; if ( ! usesRegClass ( MO , & <STR_LIT> ) && ! usesRegClass ( MO , & <STR_LIT> ) && ! usesRegClass ( MO , & <STR_LIT> ) ) continue ; Defs . push_back ( MO . getReg ( ) ) ; }


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && LHS . getOpcode ( ) == <STR_LIT> ) if ( isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) && LHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , RHS , LHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , DL , addV . getValueType ( ) ) , CC ) ; } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && RHS . getOpcode ( ) == <STR_LIT> ) if ( isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , DL , addV . getValueType ( ) ) , CC ) ; } if ( VT . getScalarType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! IsSEXT0 || ! IsVZero1 ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ;


<s> size_t uns_fcode = ( size_t ) fcode ; const struct builtin_description * d ; size_t i ; rtx ret ; bool success ; HOST_WIDE_INT mask = rs6000_builtin_info [ uns_fcode ] . mask ; bool func_valid_p = ( ( rs6000_builtin_mask & mask ) == mask ) ; if ( TARGET_DEBUG_BUILTIN ) { enum insn_code icode = rs6000_builtin_info [ uns_fcode ] . icode ; const char * name1 = rs6000_builtin_info [ uns_fcode ] . name ; const char * name2 = ( ( icode != CODE_FOR_nothing ) ? get_insn_name ( ( int ) icode ) : <STR_LIT> ) ; const char * name3 ; switch ( rs6000_builtin_info [ uns_fcode ] . attr & RS6000_BTC_TYPE_MASK ) { default : name3 = <STR_LIT> ; break ; case RS6000_BTC_SPECIAL : name3 = <STR_LIT> ; break ; case RS6000_BTC_UNARY : name3 = <STR_LIT> ; break ; case RS6000_BTC_BINARY : name3 = <STR_LIT> ; break ; case RS6000_BTC_TERNARY : name3 = <STR_LIT> ; break ; case RS6000_BTC_PREDICATE : name3 = <STR_LIT> ; break ; case RS6000_BTC_ABS : name3 = <STR_LIT> ; break ; case RS6000_BTC_EVSEL : name3 = <STR_LIT> ; break ; case RS6000_BTC_DST : name3 = <STR_LIT> ; break ; } fprintf ( stderr , <STR_LIT> , ( name1 ) ? name1 : <STR_LIT> , fcode , ( name2 ) ? name2 : <STR_LIT> , ( int ) icode , name3 , func_valid_p ? <STR_LIT> : <STR_LIT> ) ; } if ( ! func_valid_p ) { rs6000_invalid_builtin ( fcode ) ; return expand_call ( exp , target , ignore ) ; } switch ( fcode ) { case RS6000_BUILTIN_RECIP : return rs6000_expand_binop_builtin ( CODE_FOR_recipdf3 , exp , target ) ; case RS6000_BUILTIN_RECIPF : return rs6000_expand_binop_builtin ( CODE_FOR_recipsf3 , exp , target ) ; case RS6000_BUILTIN_RSQRTF : return rs6000_expand_unop_builtin ( CODE_FOR_rsqrtsf2 , exp , target ) ; case RS6000_BUILTIN_RSQRT : return rs6000_expand_unop_builtin ( CODE_FOR_rsqrtdf2 , exp , target ) ; case POWER7_BUILTIN_BPERMD : return rs6000_expand_binop_builtin ( ( ( TARGET_64BIT ) ? CODE_FOR_bpermd_di : CODE_FOR_bpermd_si ) , exp , target ) ; case RS6000_BUILTIN_GET_TB : return rs6000_expand_zeroop_builtin ( CODE_FOR_rs6000_get_timebase , target ) ; case RS6000_BUILTIN_MFTB : return rs6000_expand_zeroop_builtin ( ( ( TARGET_64BIT ) ? CODE_FOR_rs6000_mftb_di : CODE_FOR_rs6000_mftb_si ) , target ) ; case RS6000_BUILTIN_MFFS : return rs6000_expand_zeroop_builtin ( CODE_FOR_rs6000_mffs , target ) ; case RS6000_BUILTIN_MTFSF : return rs6000_expand_mtfsf_builtin ( CODE_FOR_rs6000_mtfsf , exp ) ; case RS6000_BUILTIN_CPU_INIT : case RS6000_BUILTIN_CPU_IS : case RS6000_BUILTIN_CPU_SUPPORTS :

return cpu_expand_builtin ( fcode , exp , target ) ;


<s> if ( Func -> isDeclaration ( ) ) { Changed |= CreatedNewF ; continue ; } if ( CreatedNewF ) Func -> eraseFromParent ( ) ; } return Changed ;


<s> rtx rs6000_emit_fp_cror ( rtx_code code , machine_mode mode , rtx x ) { rtx cond [ <NUM_LIT> ] ; int n = <NUM_LIT> ; if ( code == LTGT || code == LE || code == UNLT ) cond [ n ++ ] = gen_rtx_fmt_ee ( LT , mode , x , const0_rtx ) ; if ( code == LTGT || code == GE || code == UNGT ) cond [ n ++ ] = gen_rtx_fmt_ee ( GT , mode , x , const0_rtx ) ; if ( code == LE || code == GE || code == UNEQ ) cond [ n ++ ] = gen_rtx_fmt_ee ( EQ , mode , x , const0_rtx ) ; if ( code == UNLT || code == UNGT || code == UNEQ ) cond [ n ++ ] = gen_rtx_fmt_ee ( UNORDERED , mode , x , const0_rtx ) ; gcc_assert ( n == <NUM_LIT> ) ; rtx cc = gen_reg_rtx ( CCEQmode ) ; rtx logical = gen_rtx_IOR ( mode , cond [ <NUM_LIT> ] , cond [ <NUM_LIT> ] ) ;

emit_insn ( gen_cceq_ior_compare ( mode , cc , logical , cond [ <NUM_LIT> ] , x , cond [ <NUM_LIT> ] , x ) ) ;


<s> if ( save_p ( i , leaf_function ) ) { mem = gen_frame_mem ( DImode , plus_constant ( Pmode , base , offset ) ) ; if ( action_true == SORR_SAVE ) { insn = emit_move_insn ( mem , gen_rtx_REG ( DImode , i ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else { if ( i == HARD_FRAME_POINTER_REGNUM ) fp_offset = offset ; else emit_move_insn ( gen_rtx_REG ( DImode , i ) , mem ) ; } offset += <NUM_LIT> ; } else if ( action_false == SORR_ADVANCE ) offset += <NUM_LIT> ; } if ( fp_offset >= <NUM_LIT> ) { mem = gen_frame_mem ( DImode , plus_constant ( Pmode , base , fp_offset ) ) ; emit_move_insn ( hard_frame_pointer_rtx , mem ) ; } } else { for ( i = low ; i < high ; i += <NUM_LIT> ) { bool reg0 = save_p ( i , leaf_function ) ; bool reg1 = save_p ( i + <NUM_LIT> , leaf_function ) ; machine_mode mode ; int regno ; if ( reg0 && reg1 ) { mode = SPARC_INT_REG_P ( i ) ? DImode : DFmode ; regno = i ; } else if ( reg0 ) { mode = SPARC_INT_REG_P ( i ) ? SImode : SFmode ; regno = i ; } else if ( reg1 ) { mode = SPARC_INT_REG_P ( i ) ? SImode : SFmode ; regno = i + <NUM_LIT> ; offset += <NUM_LIT> ; } else { if ( action_false == SORR_ADVANCE ) offset += <NUM_LIT> ; continue ; } mem = gen_frame_mem ( mode , plus_constant ( Pmode , base , offset ) ) ; if ( action_true == SORR_SAVE ) { insn = emit_move_insn ( mem , gen_rtx_REG ( mode , regno ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( mode == DImode ) { rtx set1 , set2 ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base , offset ) ) ; set1 = gen_rtx_SET ( mem , gen_rtx_REG ( SImode , regno ) ) ; RTX_FRAME_RELATED_P ( set1 ) = <NUM_LIT> ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base , offset + <NUM_LIT> ) ) ; set2 = gen_rtx_SET ( mem , gen_rtx_REG ( SImode , regno + <NUM_LIT> ) ) ; RTX_FRAME_RELATED_P ( set2 ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set1 , set2 ) ) ) ; } } else emit_move_insn ( gen_rtx_REG ( mode , regno ) , mem ) ;

offset = ROUND_DOWN ( offset + <NUM_LIT> , <NUM_LIT> ) ;


<s> MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( VT . is512BitVector ( ) || InVT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; if ( ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) ) return SDValue ( ) ;

if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ;


<s> Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; } else { assert ( model == TLSModel :: LocalExec ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , PtrVT , ThreadPointer , Offset ) ;


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override {


<s> unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ;

unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ;


<s> unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( CopyVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . InRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; CLI . ResultReg = ResultReg ; CLI . NumResultRegs = <NUM_LIT> ; }


<s> if ( Register :: isPhysicalRegister ( Reg ) ) { if ( Reg == <STR_LIT> ) continue ; if ( ! MRI . isPhysRegModified ( Reg ) ) continue ; return false ; } if ( ! MO . isDef ( ) && ! MRI . hasOneDef ( Reg ) ) MutableRegisters . push_back ( Reg ) ; } bool Read = false , Write = false , Effects = false , StackPointer = false ; query ( * DefI , AA , Read , Write , Effects , StackPointer ) ; bool HasMutableRegisters = ! MutableRegisters . empty ( ) ; if ( ! Read && ! Write && ! Effects && ! StackPointer && ! HasMutableRegisters ) return true ; MachineBasicBlock :: const_iterator D ( DefI ) , I ( Insert ) ; for ( -- I ; I != D ; -- I ) { bool InterveningRead = false ; bool InterveningWrite = false ; bool InterveningEffects = false ; bool InterveningStackPointer = false ; query ( * I , AA , InterveningRead , InterveningWrite , InterveningEffects , InterveningStackPointer ) ;

if ( Effects && InterveningEffects ) return false ;


<s> int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else if ( OffImm > <NUM_LIT> ) O << <STR_LIT> << OffImm ;


<s> } if ( TARGET_SOFT_FLOAT ) arm_fpu_attr = FPU_NONE ; else arm_fpu_attr = FPU_VFP ; if ( TARGET_AAPCS_BASED ) { if ( TARGET_CALLER_INTERWORKING ) error ( <STR_LIT> ) ; else if ( TARGET_CALLEE_INTERWORKING ) error ( <STR_LIT> ) ; } if ( ! arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE ) sorry ( <STR_LIT> ) ; if ( use_cmse && ! arm_arch_cmse ) error ( <STR_LIT> ) ; if ( use_cmse && TARGET_HARD_FLOAT && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM ) error ( <STR_LIT> ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , StringRef TT ) { Triple TheTriple ( TT ) ; MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , Reg , <NUM_LIT> ) ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> MRI = & getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition = ~ <NUM_LIT> ; if ( MCELFStreamer * MES = dyn_cast < MCELFStreamer > ( & Parser . getStreamer ( ) ) ) MES -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ;


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {

FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> return ( poly8x8_t ) __builtin_aarch64_ld1v8qi ( ( const __builtin_aarch64_simd_qi * ) a ) ;


<s> if ( FLOAT_MODE_P ( mode ) ) return ix86_fp_cmp_code_to_pcmp_immediate ( code ) ; return ix86_int_cmp_code_to_pcmp_immediate ( code ) ;


<s> for ( auto I : B . liveins ( ) ) { if ( I . LaneMask . all ( ) ) { Tmp . insert ( { I . PhysReg , <NUM_LIT> } ) ; continue ; } for ( MCSubRegIndexIterator S ( I . PhysReg , & TRI ) ; S . isValid ( ) ; ++ S ) { LaneBitmask M = TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ; if ( ( M & I . LaneMask ) . any ( ) ) Tmp . insert ( { S . getSubReg ( ) , <NUM_LIT> } ) ; } } for ( auto R : Tmp ) { if ( ! Reserved [ R . Reg ] ) LiveIns . insert ( R ) ; for ( auto S : expandToSubRegs ( R , MRI , TRI ) ) if ( ! Reserved [ S . Reg ] ) LiveIns . insert ( S ) ; } return LiveIns ;


<s> SDValue MinC = DAG . getConstant ( APInt :: getSignedMaxValue ( SatWidth ) . sextOrSelf ( DstWidth ) , DL , DstVT ) ; SDValue Min = DAG . getNode ( <STR_LIT> , DL , DstVT , NativeCvt , MinC ) ; SDValue MaxC = DAG . getConstant ( APInt :: getSignedMinValue ( SatWidth ) . sextOrSelf ( DstWidth ) , DL , DstVT ) ; Sat = DAG . getNode ( <STR_LIT> , DL , DstVT , Min , MaxC ) ; } else { SDValue MinC = DAG . getConstant ( APInt :: getAllOnesValue ( SatWidth ) . zextOrSelf ( DstWidth ) , DL , DstVT ) ; Sat = DAG . getNode ( <STR_LIT> , DL , DstVT , NativeCvt , MinC ) ; }

return DAG . getNode ( <STR_LIT> , DL , DstVT , Sat ) ;


<s> <STR_LIT> getCmpLibcallReturnType ( ) const override { return <STR_LIT> ;


<s> if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; if ( Opcode == <STR_LIT> ) O << <STR_LIT> ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; return ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { O << '\t' << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> , O ) ; O << '\t' ; printRegisterList ( MI , <NUM_LIT> , O ) ; return ; } printInstruction ( MI , O ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return <STR_LIT> ;


<s> if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) , V1 ) ;


<s> emit_move_insn ( scratch , val ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ;


<s> static bool isEqual ( const TOCKey & A , const TOCKey & B ) {


<s> if ( CONSTANT_P ( op ) && letter != 'u' && letter != 's' && letter != 'r' && letter != 'S' && letter != 'B' ) fprintf ( file , <STR_LIT> ) ;

rl78_print_operand_1 ( file , op , letter ) ;


<s> bool ShortInstrPeephole :: updateJAL ( MachineInstr & MI ) const {

unsigned TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first ) ) ; cast < MCSymbolXCOFF > ( I . second ) -> setContainingCsect ( TCEntry ) ; OutStreamer -> SwitchSection ( TCEntry ) ; OutStreamer -> EmitLabel ( I . second ) ;


<s> int Opc = MI . getOpcode ( ) ; if ( <STR_LIT> ( Opc ) == - <NUM_LIT> ) Opc = <STR_LIT> ( Opc ) ; if ( Opc == - <NUM_LIT> || <STR_LIT> ( Opc ) == - <NUM_LIT> ) return false ; if ( ! ST . hasSDWAOmod ( ) && TII -> hasModifiersSet ( MI , <STR_LIT> :: omod ) ) return false ; if ( TII -> isVOPC ( Opc ) ) { if ( ! ST . hasSDWASdst ( ) ) {

const MachineOperand * SDst = TII -> getNamedOperand ( MI , <STR_LIT> :: sdst ) ;


<s> ClauseFile MakeFetchClause ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & I ) const { MachineBasicBlock :: iterator ClauseHead = I ; std :: vector < MachineInstr * > ClauseContent ; unsigned AluInstCount = <NUM_LIT> ; bool IsTex = TII -> usesTextureCache ( ClauseHead ) ; std :: set < unsigned > DstRegs ; for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ++ I ) { if ( IsTrivialInst ( I ) ) continue ; if ( AluInstCount >= MaxFetchInst ) break ; if ( ( IsTex && ! TII -> usesTextureCache ( I ) ) || ( ! IsTex && ! TII -> usesVertexCache ( I ) ) ) break ; if ( ! isCompatibleWithClause ( I , DstRegs ) ) break ;


<s> assert ( ( FrameSize & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( FrameSize > <NUM_LIT> || MFI -> adjustsStack ( ) ) { FrameSize = FrameSize + <ISA_LIT>FrameLowering :: minStackSize ( ) ; if ( isInt < <NUM_LIT> > ( FrameSize + LinkSlotOffset ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize + LinkSlotOffset ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( FrameSize ) ; } else if ( FrameSize <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && FrameSize >= - ( <NUM_LIT> << <NUM_LIT> ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( FrameSize ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * Last = & MBB -> back ( ) ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; if ( Last -> getOpcode ( ) == <STR_LIT> ) Ignore . insert ( Last ) ; bool SetFlags = RDA -> isSafeToDefRegAt ( MI , <STR_LIT> , Ignore ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <NUM_LIT> ) ;


<s> unsigned Opc = <NUM_LIT> ; if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { if ( isHReg ( DestReg ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == & <STR_LIT> ) {


<s> SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) && isIntRegForSubInst ( SrcReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && isIntRegForSubInst ( Src1Reg ) && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( <STR_LIT> . contains ( Src1Reg ) && ( <STR_LIT> == Src1Reg || <STR_LIT> == Src1Reg ) ) return <STR_LIT> ;


<s> auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < MaxPacketSize ) { MCInst * Nop = Context . createMCInst ( ) ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( Context , * MCII , * RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) {

Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ;


<s> return ( ( int ) ( spu_extract ( spu_gather ( spu_cmpgt ( b , a ) ) , <NUM_LIT> ) == <NUM_LIT> ) ) ;


<s> <ISA_LIT>TargetXCOFFStreamer ( MCStreamer & S ) : <ISA_LIT>TargetStreamer ( S ) {


<s> const BasicBlockInfo & BBI = BBInfo [ Block ] ;

dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << printMBBReference ( * MI -> getParent ( ) ) << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI << format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ;


<s> const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OrigSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Flags = MI . getFlags ( ) ; assert ( ST . hasFractBug ( ) && MRI . getType ( Dst ) == S64 && <STR_LIT> ) ; auto Fract = B . buildIntrinsic ( <STR_LIT> , { S64 } , false ) . addUse ( OrigSrc ) . setMIFlags ( Flags ) ; Register ModSrc = stripAnySourceMods ( OrigSrc , MRI ) ; auto Const = B . buildFConstant ( S64 , BitsToDouble ( <NUM_LIT> ) ) ; Register Min = MRI . createGenericVirtualRegister ( S64 ) ; const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> getMode ( ) . IEEE ) B . buildFMinNumIEEE ( Min , Fract , Const , Flags ) ; else B . buildFMinNum ( Min , Fract , Const , Flags ) ; Register CorrectedFract = Min ; if ( ! MI . getFlag ( MachineInstr :: FmNoNans ) ) { auto IsNan = B . buildFCmp ( CmpInst :: FCMP_ORD , S1 , ModSrc , ModSrc , Flags ) ; CorrectedFract = B . buildSelect ( S64 , IsNan , ModSrc , Min , Flags ) . getReg ( <NUM_LIT> ) ; } auto NegFract = B . buildFNeg ( S64 , CorrectedFract , Flags ) ; B . buildFAdd ( Dst , OrigSrc , NegFract , Flags ) ; MI . eraseFromParent ( ) ;


<s> return E -> getKind ( ) == MCExpr :: Target ;


<s> void <ISA_LIT>64CompilationCallback ( ) { llvm_unreachable ( <STR_LIT> ) ;


<s> const MachineOperand & MO = getLoadStoreRegOp ( * MI ) ; unsigned Reg = MO . getReg ( ) ; bool IsKill = MO . isKill ( ) ; if ( IsKill ) KilledRegs . insert ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , IsKill ) ) ; UsedRegs . insert ( Reg ) ; if ( IsLoad ) { for ( const MachineOperand & MO : MI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || MO . isDead ( ) ) continue ; assert ( MO . isImplicit ( ) ) ; unsigned DefReg = MO . getReg ( ) ; if ( is_contained ( ImpDefs , DefReg ) ) continue ; if ( MI -> readsRegister ( DefReg ) ) continue ; ImpDefs . push_back ( DefReg ) ; } } } using iterator = MachineBasicBlock :: iterator ; MachineInstr * LatestMI = Cand . Instrs [ Cand . LatestMIIdx ] ; iterator InsertBefore = std :: next ( iterator ( LatestMI ) ) ; MachineBasicBlock & MBB = * LatestMI -> getParent ( ) ; unsigned Offset = getMemoryOpOffset ( * First ) ; unsigned Base = getLoadStoreBaseOp ( * First ) . getReg ( ) ; bool BaseKill = LatestMI -> killsRegister ( Base ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * First , PredReg ) ; DebugLoc DL = First -> getDebugLoc ( ) ; MachineInstr * Merged = nullptr ; if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged ) return nullptr ; iterator EarliestI ( Cand . Instrs [ Cand . EarliestMIIdx ] ) ; bool EarliestAtBegin = false ; if ( EarliestI == MBB . begin ( ) ) { EarliestAtBegin = true ;


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( MF . getDataLayout ( ) ) , StackPtr , PtrOff ) ; SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ; SDValue NewCallSeqStart = DAG . getCALLSEQ_START ( MemcpyCall , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , SDLoc ( MemcpyCall ) ) ; DAG . ReplaceAllUsesWith ( CallSeqStart . getNode ( ) , NewCallSeqStart . getNode ( ) ) ; Chain = CallSeqStart = NewCallSeqStart ; Arg = PtrOff ; } if ( VA . isRegLoc ( ) ) { if ( Arg . getValueType ( ) == <STR_LIT> ) Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg ) ; seenFloatArg |= VA . getLocVT ( ) . isFloatingPoint ( ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned LocMemOffset = VA . getLocMemOffset ( ) ; if ( ! isTailCall ) { SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( MF . getDataLayout ( ) ) , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } else { CalculateTailCallArgDest ( DAG , MF , false , Arg , SPDiff , LocMemOffset , TailCallArguments ) ; } } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ;

InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> rtx op0 , op1 , ret ; op0 = ix86_compare_op0 ; op1 = ix86_compare_op1 ; if ( second_test ) * second_test = NULL_RTX ; if ( bypass_test ) * bypass_test = NULL_RTX ; if ( ix86_compare_emitted ) { ret = gen_rtx_fmt_ee ( code , VOIDmode , ix86_compare_emitted , const0_rtx ) ;


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & ) const { Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Register ( ) ) ; if ( Reg ) return Reg ;


<s> <ISA_LIT>CFGOptimizer ( const <ISA_LIT>TargetMachine & TM ) : MachineFunctionPass ( ID ) , QTM ( TM ) , QST ( * TM . getSubtargetImpl ( ) ) {

initialize<ISA_LIT>CFGOptimizerPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> static DecodeStatus DecodeAddrMode7Operand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) {

return DecodeGPRRegisterClass ( Inst , Val , Address , Decoder ) ;


<s> if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ; if ( VecSize <= <NUM_LIT> ) return <STR_LIT> ;


<s> OS . EmitIntValue ( GPRInfoSet ? GPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( GPRInfoSet ? GPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameOffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameReg : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? ReturnReg : <NUM_LIT> , <NUM_LIT> ) ; GPRInfoSet = FPRInfoSet = FrameInfoSet = false ; OS . PopSection ( ) ; MCSymbol * CurPCSym = Context . createTempSymbol ( ) ; OS . EmitLabel ( CurPCSym ) ; const MCExpr * Size = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( CurPCSym , MCSymbolRefExpr :: VK_None , Context ) , ExprRef , Context ) ; int64_t AbsSize ; if ( ! Size -> evaluateAsAbsolute ( AbsSize , MCA ) ) llvm_unreachable ( <STR_LIT> ) ; Size = MCConstantExpr :: create ( AbsSize , Context ) ; static_cast < MCSymbolELF * > ( Sym ) -> setSize ( Size ) ;


<s> unsigned NumInputs = getPHINumInputs ( PHI ) ; for ( unsigned i = <NUM_LIT> ; i < NumInputs ; ++ i ) { MachineBasicBlock * Pred = getPHIPred ( PHI , i ) ; if ( ! Region -> contains ( Pred ) ) { PHINonRegionIndices . push_back ( i ) ; }


return __builtin_shuffle ( a , ( uint32x4_t ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> return gen_rtx_MEM ( mode , gen_rtx_PLUS ( Pmode , base , frv_frame_offset_rtx ( offset ) ) ) ;


<s> const Function * F = MF . getFunction ( ) ; unsigned StackAlign = Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: StackAlignment ) ) ; return requiresRealignment && canRealignStack ( MF ) ;


<s> case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( SSECC == <NUM_LIT> ) { unsigned CC0 , CC1 ; unsigned CombineOpc ; if ( SetCCOpcode == <STR_LIT> ) { CC0 = <NUM_LIT> ; CC1 = <NUM_LIT> ; CombineOpc = <STR_LIT> ; } else { assert ( SetCCOpcode == <STR_LIT> ) ; CC0 = <NUM_LIT> ; CC1 = <NUM_LIT> ; CombineOpc = <STR_LIT> ; } SDValue Cmp0 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( CC0 , <STR_LIT> ) ) ; SDValue Cmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( CC1 , <STR_LIT> ) ) ; return DAG . getNode ( CombineOpc , dl , VT , Cmp0 , Cmp1 ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , <STR_LIT> ) ) ; } if ( VT . is256BitVector ( ) && ! Subtarget -> hasAVX2 ( ) ) return Lower256IntVSETCC ( Op , DAG ) ; unsigned Opc ; bool Swap = false , Invert = false , FlipSigns = false ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; Invert = true ; break ; case <STR_LIT> : Swap = true ;

case <STR_LIT> : Opc = <STR_LIT> ; FlipSigns = true ; break ;


<s> else fprintf ( asm_out_file , with_offset , REGNO ( dst ) , REGNO ( cfun -> machine -> red_partition ) , UINTVAL ( offset ) ) ; return <STR_LIT> ;


<s> if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveRegX ( Reg , Offset ) ; return false ;


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForNode ( CallingConv :: ID CC ) const { if ( Subtarget -> is64Bit ( ) ) {

if ( CC == CallingConv :: GHC ) return CC_<ISA_LIT>_64_GHC ;


<s> } MachineInstr * New ; if ( Old -> getOpcode ( ) == <STR_LIT> ) { int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opcode ) ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == <STR_LIT> ) ; int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opcode ) , <STR_LIT> ) . addImm ( Amount ) ; }


<s> void DecodePSHUFMask ( unsigned NumElts , unsigned ScalarBits , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) { unsigned Size = NumElts * ScalarBits ;


<s> static DecodeStatus DecodeDPR_VFP2RegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; return DecodeDPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const {

SmallVector < CCValAssign , <NUM_LIT> > RVLocs ;


<s> <ISA_LIT>Operand & Operand = static_cast < <ISA_LIT>Operand & > ( * Operands . front ( ) ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getTLSRegEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ;

Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> static bool rs6000_must_pass_in_stack ( machine_mode mode , const_tree type ) {

if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size ( mode , type ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; return Reserved ;


<s> static bool mips_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return mips_hard_regno_mode_ok_p [ mode ] [ regno ] ;


<s> OS << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; OS << '[' ; printOperand ( MI , <NUM_LIT> , OS ) ; OS << '+' ; printOperand ( MI , <NUM_LIT> , OS ) ; OS << ']' ; OS << <STR_LIT> ; printOperand ( MI , NOps - <NUM_LIT> , OS ) ;


<s> case ENCODING_RD : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RO : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Rv : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_I : if ( readOpcodeModifier ( insn ) ) return - <NUM_LIT> ; break ; case ENCODING_VVVV : if ( readVVVV ( insn ) ) return - <NUM_LIT> ; if ( fixupReg ( insn , & insn -> spec -> operands [ index ] ) ) return - <NUM_LIT> ; break ; case ENCODING_DUP : break ; default : dbgprintf ( insn , <STR_LIT> ) ; return - <NUM_LIT> ; } }


<s> unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Ra = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( pred == <NUM_LIT> ) return DecodeCPSInstruction ( Inst , Insn , Address , Decoder ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Ra , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> <ISA_LIT>Relocator :: ~ <ISA_LIT>Relocator ( ) {


<s> const int mov_insn_sz = mov_insn_size ( mode , false ) ; const int max_disp = sh_max_mov_insn_displacement ( mode , false ) ; const int max_disp_next = max_disp + mov_insn_sz ; HOST_WIDE_INT align_modifier = offset > <NUM_LIT> ? mov_insn_sz : <NUM_LIT> ; HOST_WIDE_INT offset_adjust ; if ( mode_sz < <NUM_LIT> || mode_sz > <NUM_LIT> || max_disp < <NUM_LIT> ) return res ; if ( mov_insn_sz == <NUM_LIT> ) align_modifier = <NUM_LIT> ; offset_adjust = ( ( offset + align_modifier ) & ~ max_disp ) - align_modifier ; if ( mode_sz + offset - offset_adjust <= max_disp_next ) { res . offset_adjust = GEN_INT ( offset_adjust ) ; res . mov_disp = GEN_INT ( offset - offset_adjust ) ; }


<s> void AMDGPUInstPrinter :: printClamp<ISA_LIT> ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O << <STR_LIT> ;


<s> target_flag_set_p ( unsigned int mask ) : m_mask ( mask ) {


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; Register SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;


<s> unsigned TargetAlign = Target . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask ) & ~ AlignMask ;


assert ( ( Kind == k_Memory ) && <STR_LIT> ) ;


<s> const IntrinsicData * Data = lower_bound ( IntrinsicsWithChain , IntNo ) ;

if ( Data != std :: end ( IntrinsicsWithChain ) && Data -> Id == IntNo ) return Data ;


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtps_pi32 ( __m128 __A ) { __v4sf temp , rounded ; __vector unsigned long long result ; temp = ( __v4sf ) vec_splat ( ( __vector long long ) __A , <NUM_LIT> ) ; rounded = vec_rint ( temp ) ;

result = ( __vector unsigned long long ) vec_cts ( rounded , <NUM_LIT> ) ;


<s> for ( const FPOInstruction & Inst : FPO -> Instructions ) { switch ( Inst . Op ) { case FPOInstruction :: PushReg : FSM . CurOffset += <NUM_LIT> ; FSM . SavedRegSize += <NUM_LIT> ; FSM . RegSaveOffsets . push_back ( { Inst . RegOrOffset , FSM . CurOffset } ) ; break ; case FPOInstruction :: SetFrame : FSM . FrameReg = Inst . RegOrOffset ; FSM . FrameRegOff = FSM . CurOffset ; break ; case FPOInstruction :: StackAlloc : FSM . CurOffset += Inst . RegOrOffset ; FSM . LocalSize += Inst . RegOrOffset ; if ( FSM . FrameReg ) continue ; break ; } FSM . emitFrameDataRecord ( OS , Inst . Label ) ; }

OS . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; if ( ! Op -> hasOneUse ( ) ) return SDValue ( ) ; SDNode * N = Op . getNode ( ) ; SDLoc DL ( N ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; DenseMap < SDValue , unsigned > VecInMap ; SmallVector < SDValue , <NUM_LIT> > VecIns ; EVT VT = <STR_LIT> ; Opnds . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned Slot = <NUM_LIT> , e = Opnds . size ( ) ; Slot < e ; ++ Slot ) { SmallVectorImpl < SDValue > :: const_iterator I = Opnds . begin ( ) + Slot ; if ( I -> getOpcode ( ) == <STR_LIT> ) { Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; e += <NUM_LIT> ; continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Idx = I -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue ExtractedFromVec = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , unsigned > :: iterator M = VecInMap . find ( ExtractedFromVec ) ; if ( M == VecInMap . end ( ) ) { VT = ExtractedFromVec . getValueType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( VecInMap . begin ( ) != VecInMap . end ( ) && VT != VecInMap . begin ( ) -> first . getValueType ( ) ) return SDValue ( ) ; M = VecInMap . insert ( std :: make_pair ( ExtractedFromVec , <NUM_LIT> ) ) . first ; VecIns . push_back ( ExtractedFromVec ) ; } M -> second |= <NUM_LIT> << cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; } assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned FullMask = ( <NUM_LIT> << VT . getVectorNumElements ( ) ) - <NUM_LIT> ; for ( DenseMap < SDValue , unsigned > :: const_iterator I = VecInMap . begin ( ) , E = VecInMap . end ( ) ; I != E ; ++ I ) { if ( I -> second != FullMask ) return SDValue ( ) ;


<s> static uint64_t getStackValueStoreSizeHack ( const CCValAssign & VA ) { const MVT ValVT = VA . getValVT ( ) ; return ( ValVT == <STR_LIT> || ValVT == <STR_LIT> ) ? ValVT . getStoreSize ( ) : VA . getLocVT ( ) . getStoreSize ( ) ;


<s> if ( auto Error = Metadata :: fromYamlString ( YamlString , CodeObjectMetadata ) ) return Error ; return toYamlString ( ) ;


<s> Op -> Mem . RegKind = RegKind ; Op -> Mem . Base = Base ; Op -> Mem . Index = Index ; Op -> Mem . Disp = Disp ; Op -> Mem . Length = Length ;


<s> int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> static BasicBlock * unifyReturnBlockSet ( Function & F , ArrayRef < BasicBlock * > ReturningBlocks , const TargetTransformInfo & TTI , StringRef Name ) { BasicBlock * NewRetBlock = BasicBlock :: Create ( F . getContext ( ) , Name , & F ) ; PHINode * PN = nullptr ; if ( F . getReturnType ( ) -> isVoidTy ( ) ) { ReturnInst :: Create ( F . getContext ( ) , nullptr , NewRetBlock ) ; } else { PN = PHINode :: Create ( F . getReturnType ( ) , ReturningBlocks . size ( ) , <STR_LIT> ) ; NewRetBlock -> getInstList ( ) . push_back ( PN ) ; ReturnInst :: Create ( F . getContext ( ) , PN , NewRetBlock ) ; }

for ( BasicBlock * BB : ReturningBlocks ) {


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : return Value ; case <STR_LIT> : case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( Value == <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { assert ( ( ! TT . isOSAIX ( ) || ! RM . hasValue ( ) || * RM == Reloc :: PIC_ ) && <STR_LIT> ) ; if ( RM . hasValue ( ) ) return * RM ; if ( TT . isOSDarwin ( ) ) return Reloc :: DynamicNoPIC ;

if ( TT . getArch ( ) == Triple :: ppc64 || TT . isOSAIX ( ) ) return Reloc :: PIC_ ;


<s> if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( getFrameLowering ( MF ) -> hasReservedCallFrame ( MF ) ) return true ;


<s> if ( ! Subtarget . hasFPExtension ( ) ) setOperationAction ( <STR_LIT> , VT , Expand ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! Subtarget . hasFPExtension ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; } setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( unsigned I = <STR_LIT> ; I <= <STR_LIT> ; ++ I ) { MVT VT = <STR_LIT> ( I ) ; if ( isTypeLegal ( VT ) ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; if ( Subtarget . hasFPExtension ( ) ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ;


<s> bool hfp = frame_pointer_needed || stack_realign_fp ; unsigned i ; for ( i = <NUM_LIT> ; i < count ; ++ i ) { gcc_assert ( i < MAX_REGS ) ; if ( REG_ORDER [ i ] == BP_REG && hfp ) ++ count ; else if ( REG_ORDER [ i ] == regno ) return true ; }


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> std :: vector < RegionNode * > & Nodes = * I ;

Order . append ( Nodes . begin ( ) , Nodes . end ( ) ) ;


<s> I != E ; ++ I ) printModuleLevelGV ( I ) ; O << <STR_LIT> ; for ( std :: set < std :: string > :: iterator i = ExternalFunctionNames . begin ( ) , e = ExternalFunctionNames . end ( ) ; i != e ; ++ i ) { O << <STR_LIT> << * i << <STR_LIT> << * i << <STR_LIT> ; } O << <STR_LIT> ; O << <STR_LIT> ; for ( std :: set < std :: string > :: iterator i = ExternalObjectNames . begin ( ) , e = ExternalObjectNames . end ( ) ; i != e ; ++ i ) {


<s> if ( MBB . getParent ( ) -> getFrameInfo ( ) -> isReturnAddressTaken ( ) && MBB . getParent ( ) -> getRegInfo ( ) . isLiveIn ( Reg ) ) return false ;


<s> RegisterKind RegKind ; unsigned Reg , RegNum , RegWidth ; if ( ! Parse<ISA_LIT>Register ( RegKind , Reg , RegNum , RegWidth ) ) { Error ( StartLoc , <STR_LIT> ) ; return nullptr ; }

if ( <STR_LIT> :: hasCodeObjectV3 ( & getSTI ( ) ) ) {


<s> static const Function * getCallee ( const MachineConstantPoolEntry & E ) {

auto * CPC = static_cast < <ISA_LIT>ConstantPoolConstant * > ( E . Val . MachineCPVal ) ;


<s> } auto loop_bounds = getLoopBounds ( MBB ) ; if ( loop_bounds . first > - <NUM_LIT> || loop_bounds . second > - <NUM_LIT> ) { OutStreamer . GetCommentOS ( ) << <STR_LIT> ; if ( loop_bounds . first > - <NUM_LIT> ) { OutStreamer . GetCommentOS ( ) << loop_bounds . first ; } else { OutStreamer . GetCommentOS ( ) << <STR_LIT> ; } OutStreamer . GetCommentOS ( ) << <STR_LIT> ; if ( loop_bounds . second > - <NUM_LIT> ) {

OutStreamer . GetCommentOS ( ) << loop_bounds . second ;


<s> for ( unsigned i = NumElts / <NUM_LIT> ; i != NumElts ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , NumElts / <NUM_LIT> ) ) return false ;


<s> switch ( Kind ) { case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ;


<s> assert ( I != TypeMap . end ( ) && <STR_LIT> ) ;


<s> uint16_t HI16 = static_cast < uint16_t > ( Bin >> <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) <STR_LIT> :: write < uint16_t > ( OS , HI16 , <STR_LIT> ) ; <STR_LIT> :: write < uint16_t > ( OS , LO16 , <STR_LIT> ) ;


__builtin_ia32_storedqu256 ( ( char * ) __P , ( __v32qi ) __A ) ;


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {

assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ;


<s> unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = <NUM_LIT> + VA . getLocMemOffset ( ) ;

MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ;


<s> if ( OpNo < MI -> getNumOperands ( ) ) { <STR_LIT> e = static_cast < <STR_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ;


<s> default : return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : { SDValue Result = LowerLOAD ( Op , DAG ) ; assert ( ( ! Result . getNode ( ) || Result . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ) && <STR_LIT> ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return LowerTrig ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerFDIV ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return LowerGlobalAddress ( MFI , Op , DAG ) ; } case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_VOID ( Op , DAG ) ; case <STR_LIT> : return lowerADDRSPACECAST ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return lowerTRAP ( Op , DAG ) ; case <STR_LIT> : return lowerDEBUGTRAP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> :


<s> __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ;


<s> bool ISASupported = ! Subtarget -> has<ISA_LIT>32r6 ( ) && ! Subtarget -> inMicro<ISA_LIT>Mode ( ) && Subtarget -> has<ISA_LIT>32 ( ) ; TargetSupported = ISASupported && ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) ) ; UnsupportedFPMode = Subtarget -> isFP64bit ( ) ;


<s> <ISA_LIT>CallFrameOptimization ( ) : MachineFunctionPass ( ID ) {


<s> LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const { llvm_unreachable ( <STR_LIT> ) ; SDNode * Node = Op . getNode ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; const Value * V = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

EVT VT = Node -> getValueType ( <NUM_LIT> ) ;


<s> if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> static void simple_poly_selftest ( const char * arch , enum riscv_abi_type abi , const std :: vector < machine_mode > & modes ) { riscv_selftest_arch_abi_setter rv ( arch , abi ) ; rtl_dump_test t ( SELFTEST_LOCATION , locate_file ( <STR_LIT> ) ) ;

set_new_first_and_last_insn ( NULL , NULL ) ;


<s> assert ( MI . getOperand ( OpNo - <NUM_LIT> ) . isImm ( ) ) ; assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned Position = getMachineOpValue ( MI , MI . getOperand ( OpNo - <NUM_LIT> ) , Fixups , STI ) ;

unsigned Size = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ;


<s> case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addExpr ( Lower . getExpr ( MI -> getOperand ( <NUM_LIT> ) , MCSymbolRefExpr :: VK_PLT ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : LoweredMI = lowerRIEfLow ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : LoweredMI = lowerRIEfLow ( MI , <STR_LIT> ) ; break ; case <STR_LIT> ## <NUM_LIT> : LoweredMI = lowerRILow ( MI , <STR_LIT> ) ; break LOWER_LOW ( IILL ) ; LOWER_LOW ( IILH ) ; LOWER_LOW ( TMLL ) ; LOWER_LOW ( TMLH ) ; LOWER_LOW ( NILL ) ; LOWER_LOW ( NILH ) ; LOWER_LOW ( NILF ) ; LOWER_LOW ( OILL ) ; LOWER_LOW ( OILH ) ; LOWER_LOW ( OILF ) ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : case 'f' :


<s> Size = Info . Type * <NUM_LIT> ; if ( Size ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_SizeDirective , Start , <NUM_LIT> , Size ) ) ; } } BaseReg = BaseReg ? BaseReg : <NUM_LIT> ;

return <STR_LIT> ( SegReg , Disp , BaseReg , IndexReg , Scale , Start , End , Size , Identifier , Info . OpDecl ) ;


<s> Parser . Lex ( ) ; SMLoc S = getLoc ( ) ; const MCExpr * ImmVal ; if ( ! Parser . parseExpression ( ImmVal ) ) if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( MCE -> getValue ( ) , getContext ( ) ) , S , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; } } return Error ( getLoc ( ) , <STR_LIT> ) ;


<s> Register B = Base . getReg ( ) ; if ( Register :: isStackSlot ( B ) || ! Register :: isVirtualRegister ( B ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ;

dbgs ( ) << <STR_LIT> << * First << <STR_LIT> << * Last << <STR_LIT> ;


<s> return BuildMI ( MF , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( priority ) ;


<s> static bool ix86_print_operand_punct_valid_p ( unsigned char code ) {


<s> unsigned getSpillScalarDataSize ( ) const { return SpillScalarDataSize ;


<s> bool Changed = false ; SmallVector < MBBInfo , <NUM_LIT> > WorkList ( <NUM_LIT> , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateBTIHint ( unsigned Val , StringRef Str , SMLoc S , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_BTIHint , Ctx ) ; Op -> BTIHint . Val = Val << <NUM_LIT> | <NUM_LIT> ; Op -> BTIHint . Data = Str . data ( ) ; Op -> BTIHint . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setMinFunctionAlignment ( <NUM_LIT> ) ; computeRegisterProperties ( ) ;


<s> SDNode * ABDNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDValue NewABD = tryCombineLongOpWithDup ( <STR_LIT> , ABDNode , DCI , DAG ) ; if ( ! NewABD . getNode ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , NewABD ) ; } if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isVector ( ) || TLI . isTypeLegal ( ResVT ) ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src -> getValueType ( <NUM_LIT> ) ; if ( ! ResVT . isSimple ( ) || ! SrcVT . isSimple ( ) ) return SDValue ( ) ; if ( SrcVT . getSizeInBits ( ) . getKnownMinSize ( ) != <NUM_LIT> ) return SDValue ( ) ; unsigned SrcEltSize = SrcVT . getScalarSizeInBits ( ) ; ElementCount SrcEC = SrcVT . getVectorElementCount ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , SrcEC ) ; SDLoc DL ( N ) ; Src = DAG . getNode ( N -> getOpcode ( ) , DL , SrcVT , Src ) ; EVT LoVT , HiVT ;


<s> MCInst MI ; MI . setOpcode ( Opcode ) ; if ( DefRegister != <STR_LIT> ) MI . addOperand ( MCOperand :: createReg ( DefRegister ) ) ; for ( auto I = FaultingMI . operands_begin ( ) + OperandsBeginIdx , E = FaultingMI . operands_end ( ) ; I != E ; ++ I ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & FaultingMI , * I ) ) MI . addOperand ( MaybeOperand . getValue ( ) ) ;

OutStreamer -> AddComment ( <STR_LIT> + HandlerLabel -> getName ( ) ) ;


<s> } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) return false ; } if ( Subtarget -> isCortexA9 ( ) && ! N . hasOneUse ( ) ) return false ; <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isCortexA9 ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) ) ;


<s> RegisterSet AS ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; for ( MCRegAliasIterator AI ( Reg , & TRI , false ) ; AI . isValid ( ) ; ++ AI ) AS . insert ( RegisterRef ( * AI ) ) ;


<s> if ( Index != - <NUM_LIT> ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned Width = LT . second . getVectorNumElements ( ) ; Index = Index % Width ;

if ( Index == <NUM_LIT> ) return <NUM_LIT> ;


<s> MVT EltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; assert ( EltVT == Src . getSimpleValueType ( ) . getVectorElementType ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ;

SDValue Lo = extractSubVector ( Src , <NUM_LIT> , DAG , dl , SizeInBits / <NUM_LIT> ) ;


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( O , TM , Streamer ) , Subtarget ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> <ISA_LIT>ShrinkInstructions ( ) : MachineFunctionPass ( ID ) {


<s> } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( ! isTailCall && <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( CallOpc == <STR_LIT> ) { Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { InFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InFlag ) ; } } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( BytesCalleePops , true ) , InFlag ) ;

if ( ! Ins . empty ( ) ) InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> if ( reg_class_subset_p ( GR_REGS , rclass ) ) return riscv_hard_regno_nregs ( GP_REG_FIRST , mode ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> virtual unsigned getFunctionAlignment ( const Function * F ) const {


<s> bool ProfitableArch = Subtarget -> isCortexA57 ( ) ;

return ProfitableArch && ! Subtarget -> requiresStrictAlign ( ) ;


<s> for ( MCSubRegIterator SubRegs ( VA . getLocReg ( ) , TRI , true ) ; SubRegs . isValid ( ) ; ++ SubRegs ) RegMask [ * SubRegs / <NUM_LIT> ] &= ~ ( <NUM_LIT> << ( * SubRegs % <NUM_LIT> ) ) ; } if ( ! Subtarget . hasSSE1 ( ) && <STR_LIT> . contains ( VA . getLocReg ( ) ) ) { errorUnsupported ( DAG , dl , <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> ) VA . convertToReg ( <STR_LIT> ) ; else VA . convertToReg ( <STR_LIT> ) ; } else if ( ! Subtarget . hasSSE2 ( ) && <STR_LIT> . contains ( VA . getLocReg ( ) ) && CopyVT == <STR_LIT> ) { errorUnsupported ( DAG , dl , <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> ) VA . convertToReg ( <STR_LIT> ) ; else VA . convertToReg ( <STR_LIT> ) ; } bool RoundAfterCopy = false ; if ( ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) { if ( ! Subtarget . hasX87 ( ) ) report_fatal_error ( <STR_LIT> ) ; CopyVT = <STR_LIT> ; RoundAfterCopy = ( CopyVT != VA . getLocVT ( ) ) ; } SDValue Val ; if ( VA . needsCustom ( ) ) { assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Val = getv64i1Argument ( VA , RVLocs [ ++ I ] , Chain , DAG , dl , Subtarget , & InFlag ) ;


<s> bool aarch64_sve_ldff1_operand_p ( rtx op ) { if ( ! MEM_P ( op ) ) return false ; struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , XEXP ( op , <NUM_LIT> ) , GET_MODE ( op ) , false ) ) return false ; if ( addr . type == ADDRESS_REG_IMM ) return known_eq ( addr . const_offset , <NUM_LIT> ) ; return addr . type == ADDRESS_REG_REG ;


<s> } return ; case CC_CLOBBER : CC_STATUS_INIT ; return ; case CC_REV : case CC_NOOV32 : case CC_NORMAL : cris_normal_notice_update_cc ( exp , insn ) ; if ( attrval == CC_NOOV32 && TARGET_V32 ) cc_status . flags |= CC_NO_OVERFLOW ; return ; default : internal_error ( <STR_LIT> ) ; }


<s> LLVM_FALLTHROUGH ; default : return Error ( S , <STR_LIT> ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( EVal , S , E , is<ISA_LIT>64 ( ) ) ) ; bool TLSCall = false ; if ( const MCSymbolRefExpr * Ref = dyn_cast < MCSymbolRefExpr > ( EVal ) ) TLSCall = Ref -> getSymbol ( ) . getName ( ) == <STR_LIT> ; if ( TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { const MCExpr * TLSSym ; Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; if ( ParseExpression ( TLSSym ) ) return Error ( S , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; E = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateFromMCExpr ( TLSSym , S , E , is<ISA_LIT>64 ( ) ) ) ; } if ( ! TLSCall && getLexer ( ) . is ( AsmToken :: LParen ) ) { Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal ;


<s> for ( auto MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { s32 , s64 } ) setAction ( MemOp , Ty , Legal ) ; for ( auto Ty : { s32 , s64 } ) { setAction ( TargetOpcode :: G_CONSTANT , Ty , Legal ) ; setAction ( TargetOpcode :: G_FCONSTANT , Ty , Legal ) ; } for ( auto Ty : { s1 , s8 , s16 } ) setAction ( TargetOpcode :: G_CONSTANT , Ty , WidenScalar ) ; setAction ( TargetOpcode :: G_FCONSTANT , s16 , WidenScalar ) ; setAction ( G_BR , LLT :: unsized ( ) , Legal ) ; setAction ( G_FRAME_INDEX , LLT :: pointer ( <NUM_LIT> ) , Legal ) ; computeTables ( ) ;


<s> case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS ) ;


<s> break ; case <STR_LIT> : Type = ELF :: R_CPU0_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_TLS_GOTTPREL ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_CPU0_PC24 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_GOT_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_CPU0_GOT_LO16 ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> :


<s> const TargetFrameLowering * getFrameLowering ( ) const override {


<s> if ( MOReg . isPhysical ( ) || ! TRI -> isVectorRegister ( * MRI , MOReg ) ) continue ; if ( MO . readsReg ( ) ) { MachineBasicBlock * DefMBB = MRI -> getVRegDef ( MOReg ) -> getParent ( ) ; if ( ! Blocks . contains ( DefMBB ) && ! CandidateRegs . contains ( MOReg ) ) { LiveVariables :: VarInfo & OldVarInfo = LV -> getVarInfo ( MOReg ) ; bool IsUsed = false ; for ( auto * Succ : LoopEnd -> successors ( ) ) { if ( ! Blocks . contains ( Succ ) && OldVarInfo . isLiveIn ( * Succ , MOReg , * MRI ) ) { IsUsed = true ; break ; } } if ( ! IsUsed ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOReg , TRI , <NUM_LIT> , MRI ) << '\n' ) ; CandidateRegs . insert ( MOReg ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOReg , TRI , <NUM_LIT> , MRI ) << '\n' ) ; }


<s> if ( Type == <STR_LIT> ) return <STR_LIT> :: I32 ; if ( Type == <STR_LIT> ) return <STR_LIT> :: I64 ; if ( Type == <STR_LIT> ) return <STR_LIT> :: F32 ; if ( Type == <STR_LIT> ) return <STR_LIT> :: F64 ; if ( Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> || Type == <STR_LIT> ) return <STR_LIT> :: V128 ; if ( Type == <STR_LIT> ) return <STR_LIT> :: EXNREF ; if ( Type == <STR_LIT> ) return <STR_LIT> :: EXTERNREF ;


<s> addPass ( & <ISA_LIT>FoldOperandsID ) ; if ( EnableDPPCombine ) addPass ( & GCNDPPCombineID ) ; addPass ( & DeadMachineInstructionElimID ) ; addPass ( & <ISA_LIT>LoadStoreOptimizerID ) ; if ( EnableSDWAPeephole ) { addPass ( & <ISA_LIT>PeepholeSDWAID ) ; addPass ( & EarlyMachineLICMID ) ; addPass ( & MachineCSEID ) ; addPass ( & <ISA_LIT>FoldOperandsID ) ;


<s> inline bool isFlatGlobalAddrSpace ( unsigned AS ) {

return AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS > <ISA_LIT>AS :: MAX_<ISA_LIT>_ADDRESS ;


<s> phiInfoElementAddSource ( findPHIInfoElement ( DestReg ) , SourceReg , SourceMBB ) ;


<s> return ( * ( int * ) key ) - * ( ( int * ) t ) ;


<s> static unsigned getWARegStackId ( unsigned Reg ) { assert ( Reg & INT32_MIN ) ; return Reg & INT32_MAX ;