<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ;


<s> uint32_t ImmOffset = <NUM_LIT> ; APInt ImmValue ( InstructionSizeInBits , IMM ) ; ImmValue = ImmValue . shl ( ImmOffset ) ;


<s> const char * <ISA_LIT>AsmPrinter :: getCurrentABIString ( ) const {


<s> SDValue TV = Op . getOperand ( <NUM_LIT> ) ; SDValue FV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; SDValue TargetCC ;

SDValue Flag = EmitCmp ( LHS , RHS , TargetCC , CC , DL , DAG ) ;


<s> clobbered_regs [ RETURN_REGNUM ] |= ( TARGET_TPF_PROFILING || cfun_frame_layout . save_return_addr_p || crtl -> calls_eh_return ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ! clobbered_regs [ i ] || call_used_regs [ i ] ) cfun_gpr_save_slot ( i ) = SAVE_SLOT_NONE ; s390_register_info_set_ranges ( ) ; s390_register_info_arg_gpr ( ) ;


getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


<s> if ( VT == <STR_LIT> && ! all_of ( Mask , [ LaneSize ] ( int M ) { return M < LaneSize ; } ) ) if ( SDValue V = lowerShuffleAsLanePermuteAndSHUFP ( DL , VT , V1 , V2 , Mask , DAG ) ) return V ; bool AllLanes ; if ( ! Subtarget . hasAVX2 ( ) ) { bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( ( Mask [ i ] % Size ) / LaneSize ) != ( i / LaneSize ) ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; AllLanes = LaneCrossing [ <NUM_LIT> ] && LaneCrossing [ <NUM_LIT> ] ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] % Size ) / LaneSize ] = true ; AllLanes = LaneUsed [ <NUM_LIT> ] && LaneUsed [ <NUM_LIT> ] ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > InLaneMask ( Mask . begin ( ) , Mask . end ( ) ) ;

for ( int i = <NUM_LIT> ; i < Size ; ++ i ) {


<s> case <STR_LIT> : getTargetStreamer ( ) . emitDirectiveSetMicro<ISA_LIT> ( ) ; break ; case <STR_LIT> : getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>16 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>1 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>4 ( ) ;


<s> unsigned <ISA_LIT>Subtarget :: getMinBasicBlockAlignment ( ) const {

return ceil ( log2 ( MinBasicBlockAlign ) ) ;


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCRegisterInfo ) ;

TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>MCSubtargetInfo ) ;


<s> return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , Flag , MFI . getObjectSize ( FI ) , Align ) ;


<s> ++ I ; while ( I != MBB -> end ( ) && I -> isInsideBundle ( ) ) { MCInst MCBundleInst ; const MachineInstr * BundledInst = I ; MCInstLowering . lower ( BundledInst , MCBundleInst ) ; OutStreamer . EmitInstruction ( MCBundleInst ) ; ++ I ; } } else { MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; }


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( bool Is64Bit , uint8_t OSABI , bool HasRelocationAddend ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , ELF :: EM_<ISA_LIT> , HasRelocationAddend ) {


<s> void addImm0_15Operands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res ;


<s> if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else return false ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , DL , <STR_LIT> ) ;


<s> unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , OutVals [ i ] , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( ! VA . isRegLoc ( ) ) continue ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


<s> assert ( FIOperandNum < MI . getNumOperands ( ) && <STR_LIT> ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BaseReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + Offset ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { const MachineOperand & GEPOp = PtrMI -> getOperand ( i ) ; const MachineInstr * OpDef = MRI . getUniqueVRegDef ( GEPOp . getReg ( ) ) ; assert ( OpDef ) ; if ( i == <NUM_LIT> && isConstant ( * OpDef ) ) { assert ( GEPInfo . Imm == <NUM_LIT> ) ; GEPInfo . Imm = OpDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; continue ; } const RegisterBank * OpBank = RBI . getRegBank ( GEPOp . getReg ( ) , MRI , TRI ) ;

if ( OpBank -> getID ( ) == <STR_LIT> ) GEPInfo . SgprParts . push_back ( GEPOp . getReg ( ) ) ;


<s> rtx par = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( par ) == PARALLEL ) ; rtx set = XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; rtx mem = SET_DEST ( set ) ; gcc_assert ( MEM_P ( mem ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - size_int ) ) ) ) ; if ( flag_stack_clash_protection ) { add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; }


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( bool Is64Bit , uint8_t OSABI ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , Is64Bit ? ELF :: EM_<ISA_LIT>64 : ELF :: EM_<ISA_LIT> , true ) {


<s> if ( TARGET_LITTLE_END && ! TARGET_M340 ) target_flags |= MASK_M340 ;


<s> PHINode * NPN = Builder . CreatePHI ( RequiredType , PN -> getNumIncomingValues ( ) ) ; Worklist . push_back ( PN ) ; for ( unsigned I = <NUM_LIT> ; I < PN -> getNumIncomingValues ( ) ; I ++ ) { auto * Reinterpret = cast < Instruction > ( PN -> getIncomingValue ( I ) ) ; NPN -> addIncoming ( Reinterpret -> getOperand ( <NUM_LIT> ) , PN -> getIncomingBlock ( I ) ) ;


<s> bool isLinux ( ) const { return false ;


<s> void clearModuleFeatureBits ( uint64_t Feature , StringRef FeatureString ) { clearFeatureBits ( Feature , FeatureString ) ; AssemblerOptions . front ( ) -> setFeatures ( getSTI ( ) . getFeatureBits ( ) ) ;


<s> for ( insn = get_last_insn ( ) ; insn != first ; insn = PREV_INSN ( insn ) ) if ( INSN_P ( insn ) ) PATTERN ( insn ) = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( cond ) , PATTERN ( insn ) ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OL ) : SelectionDAGISel ( TM , OL ) , Subtarget ( nullptr ) {


<s> BuildMI ( MBB , MI , <NUM_LIT> , TII -> get ( <STR_LIT> ) ) . addImm ( Value ) . addImm ( ( ( Width - <NUM_LIT> ) << <STR_LIT> :: WIDTH_M1_SHIFT_ ) | ( Offset << <STR_LIT> :: OFFSET_SHIFT_ ) | ( <STR_LIT> :: ID_MODE << <STR_LIT> :: ID_SHIFT_ ) ) ; ++ NumSetregInserted ; InstrMode . Mask &= ~ ( ( ( <NUM_LIT> << Width ) - <NUM_LIT> ) << Offset ) ;


<s> ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( AndOp1 . getNode ( ) ) ; if ( ! Mask ) return ; uint64_t MaskVal = Mask -> getZExtValue ( ) ; unsigned BitSize = CmpOp0 . getValueType ( ) . getSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( ICmpType != <STR_LIT> && AndOp0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( AndOp0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { AndOp0 = AndOp0 . getOperand ( <NUM_LIT> ) ;

AndOp1 = DAG . getConstant ( MaskVal >> ShiftVal , AndOp0 . getValueType ( ) ) ;


<s> Load . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; Load . addOperand ( MCOperand :: CreateReg ( DestReg ) ) ; Load . addOperand ( MCOperand :: CreateReg ( BaseReg ) ) ; Load . addOperand ( MCOperand :: CreateImm ( Scale ) ) ;

Load . addOperand ( MCOperand :: CreateReg ( IndexReg ) ) ;


<s> bool <ISA_LIT>AsmParser :: validateOpSel ( const MCInst & Inst ) { const unsigned Opc = Inst . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { int OpSelIdx = <STR_LIT> ( Opc , <STR_LIT> :: op_sel ) ; unsigned OpSel = Inst . getOperand ( OpSelIdx ) . getImm ( ) ; if ( OpSel & ~ <NUM_LIT> ) return false ; } if ( isGFX940 ( ) && ( MII . get ( Opc ) . TSFlags & <STR_LIT> ) ) { int OpSelIdx = <STR_LIT> ( Opc , <STR_LIT> :: op_sel ) ; if ( OpSelIdx != - <NUM_LIT> ) { if ( Inst . getOperand ( OpSelIdx ) . getImm ( ) != <NUM_LIT> ) return false ; }

int OpSelHiIdx = <STR_LIT> ( Opc , <STR_LIT> :: op_sel_hi ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & ST ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , ST . is64Bit ( ) ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) , <NUM_LIT> , ST . is64Bit ( ) ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) {


<s> const StoreInst * S = cast < StoreInst > ( I ) ; if ( S -> isAtomic ( ) ) return false ;

unsigned SABIAlignment = TD . getABITypeAlignment ( S -> getValueOperand ( ) -> getType ( ) ) ;


<s> if ( can_create_pseudo_p ( ) ) return force_reg ( Pmode , value ) ; else { riscv_emit_move ( dest , value ) ; return dest ; }


<s> if ( std :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ;

MachineBasicBlock * NextBB = & * std :: next ( MBBI ) ;


<s> MachineInstr * Ear1MI = MF . CloneMachineInstr ( MI ) ; MBB -> insert ( MI , Ear1MI ) ; Ear1MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , Ear1MI ) . addImm ( <NUM_LIT> ) ; MachineInstr * SllgMI = MF . CloneMachineInstr ( MI ) ; MBB -> insert ( MI , SllgMI ) ; SllgMI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , SllgMI ) . addReg ( Reg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Ear2MI = MF . CloneMachineInstr ( MI ) ; MBB -> insert ( MI , Ear2MI ) ; Ear2MI -> setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( MF , Ear2MI ) . addImm ( <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ;

MachineInstrBuilder ( MF , MI ) . addReg ( Reg ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> void addImmWithLSLOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> for ( auto & Entry : ValToSExtendedUses ) { Instructions & Insts = Entry . second ; Instructions CurPts ; for ( Instruction * Inst : Insts ) { if ( ToRemove . count ( Inst ) ) continue ; bool inserted = false ; for ( auto Pt : CurPts ) { if ( DT . dominates ( Inst , Pt ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * Pt << <STR_LIT> << * Inst << '\n' ) ; ( Pt ) -> replaceAllUsesWith ( Inst ) ; ToRemove . insert ( Pt ) ; Pt = Inst ; inserted = true ; break ;


<s> EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG , Has<ISA_LIT>64 ) ;


<s> delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) emit_move_insn ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) {

src = adjust_address ( src , BLKmode , offset ) ;


<s> switch ( DestSubReg ) { case <STR_LIT> : return AluT_X ; case <STR_LIT> : return AluT_Y ; case <STR_LIT> : return AluT_Z ; case <STR_LIT> : return AluT_W ; default : break ; } unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( regBelongsToClass ( DestReg , & <STR_LIT> ) || regBelongsToClass ( DestReg , & <STR_LIT> ) ) return AluT_X ; if ( regBelongsToClass ( DestReg , & <STR_LIT> ) ) return AluT_Y ; if ( regBelongsToClass ( DestReg , & <STR_LIT> ) ) return AluT_Z ; if ( regBelongsToClass ( DestReg , & <STR_LIT> ) ) return AluT_W ; if ( regBelongsToClass ( DestReg , & <STR_LIT> ) ) return AluT_XYZW ; if ( TII -> readsLDSSrcReg ( * MI ) ) return AluT_XYZW ;


<s> s += strlen ( s ) ; n = XVECLEN ( pattern , <NUM_LIT> ) ; set = XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ; mem = save_p ? SET_DEST ( set ) : SET_SRC ( set ) ; mips_split_plus ( XEXP ( mem , <NUM_LIT> ) , & base , & offset ) ; last_set = XVECEXP ( pattern , <NUM_LIT> , n - <NUM_LIT> ) ; last_reg = save_p ? SET_SRC ( last_set ) : SET_DEST ( last_set ) ; if ( REGNO ( last_reg ) == <NUM_LIT> ) n -- ; gcc_assert ( n <= <NUM_LIT> ) ; if ( n == <NUM_LIT> ) ; else if ( n == <NUM_LIT> ) s += sprintf ( s , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; else if ( n < <NUM_LIT> ) s += sprintf ( s , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> + n ] ) ; else if ( n == <NUM_LIT> ) s += sprintf ( s , <STR_LIT> , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] , reg_names [ <NUM_LIT> ] ) ; if ( REGNO ( last_reg ) == <NUM_LIT> ) s += sprintf ( s , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; s += sprintf ( s , <STR_LIT> , ( int ) offset , reg_names [ REGNO ( base ) ] ) ;


<s> assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; FrameOffsetReg = Reg ;


<s> unsigned GCNTTIImpl :: getHardwareNumberOfRegisters ( bool Vec ) const {


<s> machine_mode mode = ( machine_mode ) i ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ;

if ( vec_flags & VEC_ANY_SVE ) bitmap_set_bit ( modes , i ) ;


<s> BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addDef ( <STR_LIT> , RegState :: Dead ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( LoadCmpBB , DL , TII -> get ( <STR_LIT> ) , StatusReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; } } MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( AddrReg ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , StatusReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ;

DoneBB -> transferSuccessors ( & MBB ) ;


<s> static inline unsigned getUnconditionalBrDisp ( int Opc ) { return ( Opc == <STR_LIT> ) ? ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> : ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ;


return ( __m64 ) __builtin_ia32_psrld ( ( __v2si ) __m , ( long long ) __count ) ;


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val >= <NUM_LIT> && Val <= <NUM_LIT> && ( Val % <NUM_LIT> ) == <NUM_LIT> ;


<s> } if ( SDValue V = reassociateScalarOps ( N , DAG ) ) { return V ; } if ( VT != <STR_LIT> || ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; unsigned Opc = LHS . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) std :: swap ( RHS , LHS ) ; Opc = RHS . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto Cond = RHS . getOperand ( <NUM_LIT> ) ; if ( ! isBoolSGPR ( Cond ) ) break ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { LHS , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Cond } ; Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , SL , VTList , Args ) ; } case <STR_LIT> : {

auto C = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ;


<s> OrTermrOpc = <STR_LIT> ; OrSaveExecOpc = <STR_LIT> ; Exec = <STR_LIT> ; } else { AndOpc = <STR_LIT> ; OrOpc = <STR_LIT> ; XorOpc = <STR_LIT> ; MovTermOpc = <STR_LIT> ; Andn2TermOpc = <STR_LIT> ; XorTermrOpc = <STR_LIT> ; OrTermrOpc = <STR_LIT> ; OrSaveExecOpc = <STR_LIT> ; Exec = <STR_LIT> ; } const bool CanDemote = MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS ; for ( auto & MBB : MF ) { bool IsKillBlock = false ; for ( auto & Term : MBB . terminators ( ) ) { if ( TII -> isKillTerminator ( Term . getOpcode ( ) ) ) { KillBlocks . insert ( & MBB ) ; IsKillBlock = true ; break ; } } if ( CanDemote && ! IsKillBlock ) { for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { KillBlocks . insert ( & MBB ) ; break ; } } } } MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) ; BI != MF . end ( ) ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock * MBB = & * BI ; MachineBasicBlock :: iterator I , E , Next ;


<s> const SDNode * N = Op . getNode ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( N ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; }


<s> <ISA_LIT>BasicMCBuilder ( <ISA_LIT>BasicMCBuilder & B ) : Opcode ( B . Opcode ) , Format ( B . Format ) , NumOps ( B . NumOps ) , Disasm ( B . Disasm ) , SP ( B . SP ) {


<s> CONSTEXPR svldxf1_impl ( int unspec ) : m_unspec ( unspec ) {


<s> void <ISA_LIT>UnHardwareLoops :: TakeSPScaleReg ( unsigned nreg ) { SPScale |= ( <NUM_LIT> << nreg ) ;


<s> void <ISA_LIT>InstPrinter :: printVectorIndex ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm ( ) << <STR_LIT> ;


<s> SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Flag = <ISA_LIT>_EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { TrueV , FalseV , TargetCC , Flag } ; return DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ;


<s> return isLD<ISA_LIT>nstr ( Opcode ) && getOperandIdx ( Opcode , <STR_LIT> :: dst ) != - <NUM_LIT> ;


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , StringRef CPU ) : <ISA_LIT>AsmBackend ( T , CPU ) {


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override {


<s> if ( isVOP2 ( MI -> getOpcode ( ) ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && RI . isSGPRClass ( MRI . getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) return nullptr ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( NewMI || MI -> getOperand ( <NUM_LIT> ) . isFPImm ( ) || ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) ) { return nullptr ; }

if ( isVOP3 ( MI -> getOpcode ( ) ) && ( MI -> getOperand ( AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: abs ) ) . getImm ( ) || MI -> getOperand ( AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: neg ) ) . getImm ( ) ) ) return nullptr ;


<s> void <ISA_LIT>DAGToDAGISel :: transferMemOperands ( SDNode * N , SDNode * Result ) {

MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ;


<s> const TargetMachine & TM = mf . getTarget ( ) ; MRI = & mf . getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; for ( MachineFunction :: iterator I = mf . begin ( ) , E = mf . end ( ) ; I != E ; ++ I ) if ( processMachineBasicBlock ( I ) ) Changed = true ; return Changed ;


aarch64_last_printed_arch_string = default_arch -> name + extension ;


<s> MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; const char * SpillLibCall = getSpillLibCallName ( * MF , CSI ) ; if ( SpillLibCall ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( SpillLibCall , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( auto & CS : CSI ) MBB . addLiveIn ( CS . getReg ( ) ) ; } const auto & NonLibcallCSI = getNonLibcallCSI ( CSI ) ; for ( auto & CS : NonLibcallCSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;

TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ;


<s> } unsigned NumOps = ( Src -> isVectorTy ( ) ? getNumVectorRegs ( Src ) : getNumberOfParts ( Src ) ) ; if ( ! Src -> isVectorTy ( ) && NumOps == <NUM_LIT> && I != nullptr ) { if ( Opcode == Instruction :: Load && I -> hasOneUse ( ) ) { const Instruction * LdUser = cast < Instruction > ( * I -> user_begin ( ) ) ; if ( isBswapIntrinsicCall ( LdUser ) && ( ! LdUser -> hasOneUse ( ) || ! isa < StoreInst > ( * LdUser -> user_begin ( ) ) ) ) return <NUM_LIT> ; } else if ( const StoreInst * SI = dyn_cast < StoreInst > ( I ) ) {

const Value * StoredVal = SI -> getValueOperand ( ) ;


<s> assert ( ( value <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) && <STR_LIT> ) ; O << value ;


<s> if ( P . isABI_N32 ( ) || P . isABI_N64 ( ) ) FpABI = FpABIKind :: S64 ;


<s> Segment ( Value * Val , int Begin , int Len ) : Val ( Val ) , Start ( Begin ) , Size ( Len ) {


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new <ISA_LIT>PassConfig ( this , PM ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

return Subtarget . hasPOPCNTFalseDeps ( ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Chains ; unsigned EltSize = MemEltVT . getStoreSize ( ) ; MachinePointerInfo SrcValue ( Store -> getMemOperand ( ) -> getValue ( ) ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Val = DAG . getNode ( <STR_LIT> , SL , EltVT , Store -> getValue ( ) , DAG . getConstant ( i , SL , <STR_LIT> ) ) ; SDValue Offset = DAG . getConstant ( i * MemEltVT . getStoreSize ( ) , SL , PtrVT ) ;

SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Store -> getBasePtr ( ) , Offset ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MII , const MCRegisterInfo & MRI , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MII ) ;


<s> break ; } case k_CondCode : OS << <STR_LIT> << getCondCode ( ) << <STR_LIT> ; break ; case k_VectorList : { OS << <STR_LIT> ; unsigned Reg = getVectorListStart ( ) ; for ( unsigned i = <NUM_LIT> , e = getVectorListCount ( ) ; i != e ; ++ i ) OS << Reg + i << <STR_LIT> ; OS << <STR_LIT> ; break ; } case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ; break ; case k_SysReg : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; case k_Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case k_SysCR :


<s> EVT VT = Op . getValueType ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && <STR_LIT> ) ; assert ( ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && <STR_LIT> ) ;


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ; MinInstAlignment = <NUM_LIT> ;


<s> bool isMemImm12Offset ( ) const { if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val == std :: numeric_limits < int32_t > :: min ( ) ) ; } return true ;


<s> const Function & CurrentFunc = MF . getFunction ( ) ; SmallVector < MVT , <NUM_LIT> > ResultMVTs ; SmallVector < MVT , <NUM_LIT> > ParamMVTs ; const auto * const F = dyn_cast < Function > ( Global ) ; computeSignatureVTs ( FuncTy , F , CurrentFunc , TM , ParamMVTs , ResultMVTs ) ; auto Signature = signatureFromMVTs ( ResultMVTs , ParamMVTs ) ; bool InvokeDetected = false ; auto * WasmSym = Printer . getMCSymbolForFunction ( F , EnableEmException || EnableEmSjLj , Signature . get ( ) , InvokeDetected ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; Printer . addSignature ( std :: move ( Signature ) ) ;


<s> } Parser . Lex ( ) ; Parser . Lex ( ) ; } if ( parseToken ( AsmToken :: LParen , <STR_LIT> ) ) return true ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; StringRef KeyStr = Parser . getTok ( ) . getIdentifier ( ) ; auto KeyIDOrNone = <ISA_LIT>StringToPACKeyID ( KeyStr ) ; if ( ! KeyIDOrNone ) return TokError ( <STR_LIT> + KeyStr + <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) return TokError ( <STR_LIT> ) ; int64_t Discriminator = Parser . getTok ( ) . getIntVal ( ) ; if ( ! isUInt < <NUM_LIT> > ( Discriminator ) ) return TokError ( <STR_LIT> + itostr ( Discriminator ) + <STR_LIT> ) ; Parser . Lex ( ) ; bool UseAddressDiversity = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) || Parser . getTok ( ) . getIdentifier ( ) != <STR_LIT> ) return TokError ( <STR_LIT> ) ; UseAddressDiversity = true ;


if ( ! ( Subtarget . hasAVX2 ( ) && ( isShuffleMaskInputInPlace ( <NUM_LIT> , Mask ) || isShuffleMaskInputInPlace ( <NUM_LIT> , Mask ) ) ) ) if ( SDValue Result = lowerVectorShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Result ;


<s> break ; case E_HImode : if ( TARGET_SMALL_SLD ) max_offset = ( <NUM_LIT> << <NUM_LIT> ) ; else if ( ( TARGET_V850E_UP ) && unsignedp ) max_offset = ( <NUM_LIT> << <NUM_LIT> ) ;

else max_offset = ( <NUM_LIT> << <NUM_LIT> ) ;


<s> } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) {

if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ;


<s> DebugLoc DL = N -> getDebugLoc ( ) ; if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; SDValue NewMul ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , VT ) ) ;

if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , <STR_LIT> ) ) ;


<s> if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) return splitVectorIntBinary ( Op , DAG ) ;

if ( VT == <STR_LIT> || VT == <STR_LIT> ) return splitVectorIntBinary ( Op , DAG ) ;


<s> frv_packet . mems [ frv_packet . num_mems ] . mem = x ; frv_packet . mems [ frv_packet . num_mems ] . cond = * ( regstate_t * ) data ; } frv_packet . num_mems ++ ;


<s> case <STR_LIT> : O << <STR_LIT> ; O << <STR_LIT> ; } if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : O << <STR_LIT> ; }


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getSubRegClass ( const TargetRegisterClass * RC , unsigned SubIdx ) const { if ( SubIdx == AMDGPU :: NoSubRegister ) return RC ; if ( isSGPRClass ( RC ) ) { return & AMDGPU :: SGPR_32RegClass ; } else { return & AMDGPU :: VGPR_32RegClass ; }


<s> if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } StringRef ArchName = has<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! has<ISA_LIT>32r5 ( ) && hasMSA ( ) && ! MSAWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; MSAWarningPrinted = true ; } if ( ! has<ISA_LIT>32r5 ( ) && hasVirt ( ) && ! VirtWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; VirtWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasCRC ( ) && ! CRCWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; CRCWarningPrinted = true ; } if ( ! has<ISA_LIT>32r6 ( ) && hasGINV ( ) && ! GINVWarningPrinted ) { errs ( ) << <STR_LIT> << ArchName << <STR_LIT> ; GINVWarningPrinted = true ; } CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ;


<s> if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { APInt Value = C -> getAPIntValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( Value . isNonNegative ( ) ) { APInt VM1 = Value - <NUM_LIT> ; if ( VM1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VM1 . logBase2 ( ) , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; } APInt VP1 = Value + <NUM_LIT> ; if ( VP1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VP1 . logBase2 ( ) , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; } } else { APInt VNM1 = - Value - <NUM_LIT> ; if ( VNM1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VNM1 . logBase2 ( ) , <STR_LIT> ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , DAG . getConstant ( <NUM_LIT> , VT ) , Add ) ; } APInt VNP1 = - Value + <NUM_LIT> ; if ( VNP1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VNP1 . logBase2 ( ) , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , ShiftedVal ) ; } } }


<s> PreallocatedArgOffsets [ Id ] . assign ( AO . begin ( ) , AO . end ( ) ) ;


<s> if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ; unsigned OpNo = getOpIdxForMO ( MI , MO ) ; unsigned Reg = <ISA_LIT>InstrInfo :: getRegNumForOperand ( MCII . get ( MI . getOpcode ( ) ) , MO . getReg ( ) , OpNo ) ;

return CTX . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ;


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , TII ( nullptr ) {


<s> const EVT VT = AddNode . getValueType ( ) ; if ( VT . isVector ( ) || VT . getScalarSizeInBits ( ) > <NUM_LIT> ) return true ;

const ConstantSDNode * C0Node = cast < ConstantSDNode > ( AddNode . getOperand ( <NUM_LIT> ) ) ;


<s> if ( Result == MCDisassembler :: Fail ) return Result ; if ( Size > HEXAGON_MAX_PACKET_SIZE ) return MCDisassembler :: Fail ; <ISA_LIT>MCChecker Checker ( getContext ( ) , * MCII , STI , MI , * getContext ( ) . getRegisterInfo ( ) , false ) ; if ( ! Checker . check ( ) ) return MCDisassembler :: Fail ; remapInstruction ( MI ) ; return MCDisassembler :: Success ;


<s> case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ; } return <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printMemRiOperand ( const MCInst * MI , int OpNo , raw_ostream & OS , const char * Modifier ) {

const MCOperand & RegOp = MI -> getOperand ( OpNo ) ;


<s> <ISA_LIT>MCAsmInfoDarwin :: <ISA_LIT>MCAsmInfoDarwin ( const Triple & TheTriple ) {

if ( ( TheTriple . getArch ( ) == Triple :: armeb ) || ( TheTriple . getArch ( ) == Triple :: thumbeb ) ) IsLittleEndian = false ;


<s> else if ( sel . all_from_input_p ( <NUM_LIT> ) ) { d . one_vector_p = true ; op0 = op1 ; } else d . one_vector_p = false ; d . perm . new_vector ( sel . encoding ( ) , d . one_vector_p ? <NUM_LIT> : <NUM_LIT> , sel . nelts_per_input ( ) ) ; d . vmode = vmode ; d . vec_flags = aarch64_classify_vector_mode ( d . vmode ) ; d . target = target ; d . op0 = op0 ; d . op1 = op1 ; d . testing_p = ! target ; if ( ! d . testing_p ) return aarch64_expand_vec_perm_const_1 ( & d ) ; rtx_insn * last = get_last_insn ( ) ; bool ret = aarch64_expand_vec_perm_const_1 ( & d ) ; gcc_assert ( last == get_last_insn ( ) ) ; return ret ;


<s> else if ( first_preg_to_save == <NUM_LIT> ) sprintf ( buf , <STR_LIT> , first_dreg_to_save ) ; else sprintf ( buf , <STR_LIT> , first_dreg_to_save , first_preg_to_save ) ;


<s> bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; bool isX32 = T . getEnvironment ( ) == Triple :: GNUX32 ; CodePointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ;


<s> void <ISA_LIT>LoadStoreOpt :: UpdateBaseRegUses ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned Base , unsigned WordOffset , <STR_LIT> Pred , unsigned PredReg ) { assert ( isThumb1 && <STR_LIT> ) ; for ( ; MBBI != MBB . end ( ) ; ++ MBBI ) { bool InsertSub = false ; unsigned Opc = MBBI -> getOpcode ( ) ; if ( MBBI -> readsRegister ( Base ) ) { int Offset ; bool IsLoad = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsStore = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( IsLoad || IsStore ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = MO . getImm ( ) - WordOffset * getImmScale ( Opc ) ; Register InstrSrcReg = getLoadStoreRegOp ( * MBBI ) . getReg ( ) ; if ( Offset >= <NUM_LIT> && ! ( IsStore && InstrSrcReg == Base ) ) MO . setImm ( Offset ) ; else InsertSub = true ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! definesCPSR ( * MBBI ) ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = ( Opc == <STR_LIT> ) ? MO . getImm ( ) + WordOffset * <NUM_LIT> : MO . getImm ( ) - WordOffset * <NUM_LIT> ; if ( Offset >= <NUM_LIT> && TL -> isLegalAddImmediate ( Offset ) ) { MO . setImm ( Offset ) ; return ; } else { InsertSub = true ; } } else { InsertSub = true ; } } else if ( definesCPSR ( * MBBI ) || MBBI -> isCall ( ) || MBBI -> isBranch ( ) ) { InsertSub = true ; } if ( InsertSub ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Base ) . add ( t1CondCodeOp ( true ) ) . addReg ( Base ) . addImm ( WordOffset * <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) ;


<s> if ( ( RegNum = matchSVEDataVectorRegName ( Name ) ) ) return Kind == RegKind :: SVEDataVector ? RegNum : <NUM_LIT> ; if ( ( RegNum = matchSVEPredicateVectorRegName ( Name ) ) ) return Kind == RegKind :: SVEPredicateVector ? RegNum : <NUM_LIT> ; if ( ( RegNum = MatchNeonVectorRegName ( Name ) ) ) return Kind == RegKind :: NeonVector ? RegNum : <NUM_LIT> ; if ( ( RegNum = MatchRegisterName ( Name ) ) ) return Kind == RegKind :: Scalar ? RegNum : <NUM_LIT> ; if ( ! RegNum ) { auto Entry = RegisterReqs . find ( Name . lower ( ) ) ; if ( Entry == RegisterReqs . end ( ) ) return <NUM_LIT> ; if ( Kind == Entry -> getValue ( ) . first ) RegNum = Entry -> getValue ( ) . second ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateImm ( getShifter ( ) ) ) ;


<s> assert ( ! Features [ <STR_LIT> ] || ! Features [ <STR_LIT> ] ) ; M . addModuleFlag ( Module :: ModFlagBehavior :: Error , MDKey , <STR_LIT> ) ; } else if ( Features [ KV . Value ] ) {


<s> unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ;

O << <STR_LIT> << ( Val * Angle ) + Remainder ;


<s> RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;

RegisterTarget < Triple :: riscv64 > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; return true ;


<s> static bool isHardwareLoop ( const MachineInstr * MI ) {

return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> for ( auto * Entry : Pred -> successors ( ) ) { if ( ! Entries . count ( Entry ) || Map . count ( std :: make_pair ( InLoop . count ( Pred ) , Entry ) ) ) continue ; if ( EntryToLayoutPred . count ( std :: make_pair ( PredInLoop , Entry ) ) && EntryToLayoutPred [ std :: make_pair ( PredInLoop , Entry ) ] != Pred ) continue ; MachineBasicBlock * Routing = MF . CreateMachineBasicBlock ( ) ; MF . insert ( Pred -> isLayoutSuccessor ( Entry ) ? MachineFunction :: iterator ( Entry ) : MF . end ( ) , Routing ) ; Blocks . insert ( Routing ) ; BuildMI ( Routing , DebugLoc ( ) , TII . get ( <STR_LIT> ) , Reg ) . addImm ( Indices [ Entry ] ) ; BuildMI ( Routing , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( Dispatch ) ; Routing -> addSuccessor ( Dispatch ) ; Map [ std :: make_pair ( PredInLoop , Entry ) ] = Routing ; } } for ( auto * Pred : AllPreds ) { bool PredInLoop = InLoop . count ( Pred ) ; for ( MachineInstr & Term : Pred -> terminators ( ) ) for ( auto & Op : Term . explicit_uses ( ) ) if ( Op . isMBB ( ) && Indices . count ( Op . getMBB ( ) ) ) Op . setMBB ( Map [ std :: make_pair ( PredInLoop , Op . getMBB ( ) ) ] ) ; for ( auto * Succ : Pred -> successors ( ) ) { if ( ! Entries . count ( Succ ) ) continue ; auto * Routing = Map [ std :: make_pair ( PredInLoop , Succ ) ] ;

Pred -> replaceSuccessor ( Succ , Routing ) ;


<s> default : return true ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : SDLoc DL ( Op ) ; SDValue RC = CurDAG -> getTargetConstant ( <STR_LIT> . getID ( ) , DL , <STR_LIT> ) ; SDNode * N = CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , DL , Op . getValueType ( ) , Op , RC ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; OutOps . push_back ( SDValue ( N , <NUM_LIT> ) ) ; OutOps . push_back ( Zero ) ; break ; }


<s> MachineBasicBlock & BB = * I . getParent ( ) ; auto MIB = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( I . getNumMemOperands ( ) ) addMemoryOperands ( * I . memoperands_begin ( ) , MIB ) ; bool Result = MIB . constrainAllUses ( TII , TRI , RBI ) ;

if ( ResVReg . isValid ( ) && ResVReg != MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ) BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , ResVReg ) . addUse ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ;


<s> unsigned ID = MI -> getOperand ( OpNum ) . getImm ( ) ; OutStreamer . EmitLabel ( GetCPISymbol ( ID ) ) ; } else { assert ( ! strcmp ( Modifier , <STR_LIT> ) && <STR_LIT> ) ; unsigned CPI = MI -> getOperand ( OpNum ) . getIndex ( ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPI ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) { EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; } else { EmitGlobalConstant ( MCPE . Val . ConstVal ) ; }


<s> if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ;

return CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


<s> s << mcgNode -> getMF ( ) -> getFunction ( ) . getName ( ) ; }

s << ( N -> hasCallFreePath ( ) ? <STR_LIT> : <STR_LIT> ) << N -> getOccupancy ( ) << <STR_LIT> << N -> getSpillCost ( ) << <STR_LIT> << <STR_LIT> << N -> getRemainingOccupancy ( ) << <STR_LIT> << N -> getMaxDisplacement ( ) << <STR_LIT> ;


<s> bool isU32Imm ( ) const { return isImm ( <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;


<s> BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DstReg ) . addReg ( SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; } else BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DstReg ) . addReg ( SubReg ) ;


<s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; static const TargetRegisterClass * const ThumbCalleeSavedRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; return STI . isThumb ( ) ? ThumbCalleeSavedRegClasses : CalleeSavedRegClasses ;


<s> bool <ISA_LIT>TargetLowering :: hasCopyImplyingStackAdjustment ( MachineFunction * MF ) const { const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ;

return any_of ( MRI . reg_instructions ( <STR_LIT> ) , [ ] ( const MachineInstr & RI ) { return RI . isCopy ( ) ; } ) ;


<s> add_mem_operand ( mem_mode , get_contiguous_base ( mem_mode ) ) ; add_input_operand ( icode , args . last ( ) ) ;

add_input_operand ( icode , args [ <NUM_LIT> ] ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getSqrtEstimate ( SDValue Operand , SelectionDAG & DAG , int Enabled , int & RefinementSteps , bool & UseOneConstNR , bool Reciprocal ) const { EVT VT = Operand . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRSQRTES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRSQRTE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) || ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) || ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; UseOneConstNR = ! Subtarget . needsTwoConstNR ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ; }


<s> switch ( OpSize ) { case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return isStore ? <STR_LIT> : <STR_LIT> ; } } ;


<s> unsigned AccessSize = <NUM_LIT> ; OffsetIsScalable = false ; const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , AccessSize ) ;

if ( ! BaseOp || ! BaseOp -> isReg ( ) ) return false ;


<s> if ( F == Masks . end ( ) ) return false ; return ( NR . Mask & F -> second ) == NR . Mask ;


<s> if ( MO . isImm ( ) ) return ( MO . getImm ( ) >> shift ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = getTargetFixup ( MO . getExpr ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( ) ; Register SPReg = getSPReg ( ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ;


<s> FunctionPass * llvm :: createSandBoxingPass ( ) { return new SandBoxingPass ( ) ;


<s> bool SVEIntrinsicOpts :: optimizeConvertFromSVBool ( IntrinsicInst * I ) { assert ( I -> getIntrinsicID ( ) == <STR_LIT> && <STR_LIT> ) ;

if ( isa < PHINode > ( I -> getArgOperand ( <NUM_LIT> ) ) ) return processPhiNode ( I ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ;


<s> assert ( Arg . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) && <STR_LIT> ) ; Arg = DAG . getBitcast ( <STR_LIT> , Arg ) ; SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Lo ) ) ;

RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Hi ) ) ;


<s> switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> rtx mmix_gen_compare_reg ( RTX_CODE code , rtx x , rtx y ) { enum machine_mode ccmode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg ; enum machine_mode mode = GET_MODE ( x ) == VOIDmode ? GET_MODE ( y ) : GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ? DFmode : DImode ;

if ( ! mmix_valid_comparison ( code , mode , x ) ) return NULL_RTX ;


<s> ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; xops [ <NUM_LIT> ] = reg3 ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; strcpy ( tmp , <STR_LIT> ) ; if ( TARGET_64BIT ) output_asm_insn ( <STR_LIT> , xops ) ; else output_asm_insn ( <STR_LIT> , xops ) ; output_asm_insn ( strcat ( tmp , & loop_lab [ <NUM_LIT> ] ) , xops ) ; return <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const <ISA_LIT>MCInst * MI , raw_ostream & O , StringRef Annot ) { const char startPacket = '{' , endPacket = '}' ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> isPacketEnd ( ) && <STR_LIT> ) ; if ( MI -> isPacketBegin ( ) ) { <ISA_LIT>MCInst Nop ( <STR_LIT> ) ; StringRef NoAnnot ; Nop . setPacketBegin ( MI -> isPacketBegin ( ) ) ; printInst ( & Nop , O , NoAnnot ) ; } if ( MI -> isPacketEnd ( ) ) O << PacketPadding << endPacket ; printInstruction ( MI , O ) ; } else { if ( MI -> isPacketBegin ( ) ) O << PacketPadding << startPacket << '\n' ; printInstruction ( MI , O ) ; if ( MI -> isPacketEnd ( ) ) O << '\n' << PacketPadding << endPacket ; }


<s> int8_t d8 ; int16_t d16 ; int32_t d32 ; dbgprintf ( insn , <STR_LIT> ) ; if ( insn -> consumedDisplacement ) return <NUM_LIT> ; insn -> consumedDisplacement = TRUE ; insn -> displacementOffset = insn -> readerCursor - insn -> startLocation ; switch ( insn -> eaDisplacement ) { case EA_DISP_NONE : insn -> consumedDisplacement = FALSE ; break ; case EA_DISP_8 : if ( consumeInt8 ( insn , & d8 ) ) return - <NUM_LIT> ; insn -> displacement = d8 ;


<s> if ( INSN_P ( insn ) && ( get_attr_is_g13_muldiv_insn ( insn ) == IS_G13_MULDIV_INSN_YES ) ) return true ; }


<s> SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) { return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; } else { MVT ResVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( VT . getVectorNumElements ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) / <NUM_LIT> ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + VT . getVectorNumElements ( ) ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getNode ( <STR_LIT> , DL , ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) / <NUM_LIT> ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + VT . getVectorNumElements ( ) / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + VT . getVectorNumElements ( ) * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getNode ( <STR_LIT> , DL , ResVT , ResHi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } } else { SmallVector < SDValue , <NUM_LIT> > Ops ( RegSize / ReducedVT . getSizeInBits ( ) , DAG . getUNDEF ( ReducedVT ) ) ; Ops [ <NUM_LIT> ] = NewN0 ; NewN0 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; Ops [ <NUM_LIT> ] = NewN1 ; NewN1 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; if ( Mode == MULU8 || Mode == MULS8 ) { SDValue Mul = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ;

MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ;


<s> return Create ( VK_AARCH64_TPREL_G1 , Expr , Ctx ) ;


<s> MinG8R = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) ) { HasFPSaveArea = true ; FPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { ; } else if ( <STR_LIT> . contains ( Reg ) ) { HasVRSAVESaveArea = true ; } else if ( <STR_LIT> . contains ( Reg ) ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) { int FI = FPRegs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } LowerBound -= ( <NUM_LIT> - TRI -> getEncodingValue ( MinFPR ) + <NUM_LIT> ) * <NUM_LIT> ; } if ( needsFP ( MF ) ) { int FI = PFI -> getFramePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; HasGPSaveArea = true ; } if ( PFI -> usesPICBase ( ) ) { int FI = PFI -> getPICBasePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; MinGPR = std :: min < unsigned > ( MinGPR , <STR_LIT> ) ; HasGPSaveArea = true ; } const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( RegInfo -> hasBasePointer ( MF ) ) {

int FI = PFI -> getBasePointerSaveIndex ( ) ;


<s> MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( HighBits ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo ( ) ; if ( isStackPtrRelative ( PtrInfo ) ) MIB . addReg ( Info -> getStackPtrOffsetReg ( ) ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset & <NUM_LIT> ) ; } } } ; } assert ( Offset == <NUM_LIT> ) ; Optional < int > FI ; Register VAddr = Root . getReg ( ) ; if ( const MachineInstr * RootDef = MRI -> getVRegDef ( Root . getReg ( ) ) ) { if ( isBaseWithConstantOffset ( Root , * MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || KnownBits -> signBitIsZero ( LHS . getReg ( ) ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; } } return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( FI . hasValue ( ) ) MIB . addFrameIndex ( FI . getValue ( ) ) ; else MIB . addReg ( VAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( ! Info -> isEntryFunction ( ) && FI . hasValue ( ) ) MIB . addReg ( Info -> getStackPtrOffsetReg ( ) ) ; else MIB . addImm ( <NUM_LIT> ) ;


<s> if ( ! checkOneUse ( M1 ) ) return false ; return matchShiftAmt ( M1 ) ; } ; SDValue X ; auto matchPatternD = [ & checkOneUse , & checkTwoUse , matchShiftAmt , & X ] ( SDNode * Node ) -> bool { if ( Node -> getOpcode ( ) != <STR_LIT> ) return false ; SDValue N0 = Node -> getOperand ( <NUM_LIT> ) ; if ( N0 -> getOpcode ( ) != <STR_LIT> || ! checkOneUse ( N0 ) ) return false ; SDValue N1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; if ( N1 != N01 || ! checkTwoUse ( N1 ) ) return false ; if ( ! matchShiftAmt ( N1 ) ) return false ; X = N0 -> getOperand ( <NUM_LIT> ) ; return true ; } ; auto matchLowBitMask = [ & matchPatternA , & matchPatternB , & matchPatternC ] ( SDValue Mask ) -> bool { return matchPatternA ( Mask ) || matchPatternB ( Mask ) || matchPatternC ( Mask ) ; } ; if ( Node -> getOpcode ( ) == <STR_LIT> ) { X = Node -> getOperand ( <NUM_LIT> ) ; SDValue Mask = Node -> getOperand ( <NUM_LIT> ) ; if ( matchLowBitMask ( Mask ) ) { } else { std :: swap ( X , Mask ) ; if ( ! matchLowBitMask ( Mask ) ) return false ; } } else if ( ! matchPatternD ( Node ) ) return false ; SDLoc DL ( Node ) ; SDValue OrigNBits = NBits ; if ( NBits . getValueType ( ) != NVT ) { NBits = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , NBits ) ; insertDAGNode ( * CurDAG , OrigNBits , NBits ) ;

SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , NVT ) , <NUM_LIT> ) ;


<s> if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ;

if ( FP_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - <NUM_LIT> ) / UNITS_PER_FPREG ;


<s> enum rtx_code rs6000_reverse_condition ( machine_mode mode , enum rtx_code code ) {

if ( mode == CCFPmode && ( ! flag_finite_math_only || code == UNLT || code == UNLE || code == UNGT || code == UNGE || code == UNEQ || code == LTGT ) ) return reverse_condition_maybe_unordered ( code ) ;


<s> CombinerHelper Helper ( Observer , B , KB , MDT ) ; if ( Generated . tryCombineAll ( Observer , MI , B , Helper ) ) return true ; switch ( MI . getOpcode ( ) ) {


<s> return msp430_code_region == EITHER || msp430_code_region == LOWER || has_attr ( ATTR_EITHER , current_function_decl ) || has_attr ( ATTR_LOWER , current_function_decl ) ;


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( i == OpNo ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; addOperands ( MIB , MOs , PtrOffset ) ; } else { MIB . add ( MO ) ; } } updateOperandRegConstraints ( MF , * NewMI , TII ) ; if ( MI . getFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ) NewMI -> setFlag ( MachineInstr :: MIFlag :: NoFPExcept ) ; MachineBasicBlock * MBB = InsertPt -> getParent ( ) ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Lowering ( * TM . getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


<s> static bool hasOnlySGPRSpills ( const <ISA_LIT>MachineFunctionInfo * FuncInfo , const MachineFrameInfo * FrameInfo ) { return FuncInfo -> hasSpilledSGPRs ( ) && ( ! FuncInfo -> hasSpilledVGPRs ( ) && ! FuncInfo -> hasNonSpillStackObjects ( ) ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) return ErrorOperand ( Start , <STR_LIT> ) ; getParser ( ) . Lex ( ) ; return ParseMemOperand ( RegNo , Start ) ; } case AsmToken :: Dollar : { SMLoc Start = Parser . getTok ( ) . getLoc ( ) , End ; Parser . Lex ( ) ; const MCExpr * Val ; if ( getParser ( ) . parseExpression ( Val , End ) ) return nullptr ; return <STR_LIT> ( Val , Start , End ) ; }


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) {


<s> TryCand . Reason = NodeOrder ; return ; } if ( Cand . SGPRUsage > <NUM_LIT> && <STR_LIT> ( TryCand . SGPRUsage , Cand . SGPRUsage , TryCand , Cand , RegUsage ) ) return ; if ( <STR_LIT> ( TryCand . HasLowLatencyNonWaitedParent , Cand . HasLowLatencyNonWaitedParent , TryCand , Cand , <STR_LIT> ) ) return ; if ( <STR_LIT> ( TryCand . IsLowLatency , Cand . IsLowLatency , TryCand , Cand , <STR_LIT> ) ) return ; if ( TryCand . IsLowLatency && <STR_LIT> ( TryCand . LowLatencyOffset , Cand . LowLatencyOffset , TryCand , Cand , <STR_LIT> ) ) return ; if ( <STR_LIT> ( TryCand . VGPRUsage , Cand . VGPRUsage , TryCand , Cand , RegUsage ) ) return ; if ( TryCand . SU -> NodeNum < Cand . SU -> NodeNum ) {


<s> case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: CreateUpper16 ( Expr , OutContext ) ; break ; } break ; } case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_PLT , OutContext ) ; break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , OutContext ) , OutContext ) ;

return MCOperand :: CreateExpr ( Expr ) ;


<s> unsigned GCNRegPressure :: getRegKind ( Register Reg , const MachineRegisterInfo & MRI ) { assert ( Reg . isVirtual ( ) ) ; const auto RC = MRI . getRegClass ( Reg ) ; auto STI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ;

return STI -> isSGPRClass ( RC ) ? ( STI -> getRegSizeInBits ( * RC ) == <NUM_LIT> ? SGPR32 : SGPR_TUPLE ) : STI -> isAGPRClass ( RC ) ? ( STI -> getRegSizeInBits ( * RC ) == <NUM_LIT> ? AGPR32 : AGPR_TUPLE ) : ( STI -> getRegSizeInBits ( * RC ) == <NUM_LIT> ? VGPR32 : VGPR_TUPLE ) ;


<s> BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , SwapVector [ EntryIdx ] . VSEId ) ) ; DEBUG ( MI -> dump ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case E_SImode : gen = gen_and_one_cmpl_lshrsi3 ; break ; case E_DImode : gen = gen_and_one_cmpl_lshrdi3 ; break ; default : gcc_unreachable ( ) ;


<s> if ( check ( getParser ( ) . parseAbsoluteExpression ( AbiVersion ) , L , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement ) ) return addErrorSuffix ( <STR_LIT> ) ; <ISA_LIT>TargetStreamer * TStreamer = static_cast < <ISA_LIT>TargetStreamer * > ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ) ; if ( TStreamer != nullptr ) TStreamer -> emitAbiVersion ( AbiVersion ) ; return false ;


<s> TypeNo = TypeNo << <STR_LIT> ; TypeNo = TypeNo | <STR_LIT> ; break ; default : TypeNo = TypeNo << <STR_LIT> ; }

DIType BaseType = DIDerivedType ( Ty ) . getTypeDerivedFrom ( ) ;


<s> void <ISA_LIT>CFGStructurizer :: retireBlock ( MachineBasicBlock * MBB ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ; ) ; BlockInformation * & SrcBlkInfo = BlockInfoMap [ MBB ] ; if ( ! SrcBlkInfo ) SrcBlkInfo = new BlockInformation ( ) ;


<s> HasV5TEOps = false ; HasV6Ops = false ; HasV6MOps = false ; HasV6KOps = false ; HasV6T2Ops = false ; HasV7Ops = false ; HasV8Ops = false ; HasV8_1aOps = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; UseSoftFloat = false ; HasThumb2 = false ; No<ISA_LIT> = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ; HasZeroCycleZeroing = false ;


<s> void printPostIncOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {

printPostIncOperand ( MI , OpNo , Amount , O ) ;


<s> case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ;

case <STR_LIT> : return lowerSTORE ( Op , DAG ) ;


<s> if ( isIntraBin ( MI , BinPrefix ) ) Worklist . push_back ( & MI ) ; } } for ( auto * MI : Worklist ) optimizeCalls ( MI ) ; return ! Worklist . empty ( ) ;


<s> if ( TREE_CODE ( TREE_TYPE ( valist ) ) == ERROR_MARK ) return ; if ( NUM_ARGS < <NUM_LIT> ) offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : <NUM_LIT> * UNITS_PER_WORD ; else offset = - <NUM_LIT> * UNITS_PER_WORD + crtl -> args . pretend_args_size ; if ( TARGET_ABI_OPEN_VMS ) { t = make_tree ( ptr_type_node , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , offset + NUM_ARGS * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } else { base_field = TYPE_FIELDS ( TREE_TYPE ( valist ) ) ; offset_field = DECL_CHAIN ( base_field ) ; base_field = build3 ( COMPONENT_REF , TREE_TYPE ( base_field ) , valist , base_field , NULL_TREE ) ; offset_field = build3 ( COMPONENT_REF , TREE_TYPE ( offset_field ) , valist , offset_field , NULL_TREE ) ; t = make_tree ( ptr_type_node , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( base_field ) , base_field , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ;


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ;

return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ;


<s> EmitBranchToAt ( CameFromStub , Target ) ; } else { DEBUG ( errs ( ) << <STR_LIT> << CameFromStub << <STR_LIT> << oldpv << <STR_LIT> << Target << <STR_LIT> ) ; } * oldpv = ( long ) Target ;


<s> if ( Bits == <NUM_LIT> || Bits > <NUM_LIT> ) return false ; return true ;


<s> MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; DEBUG ( MDT -> print ( dbgs ( ) , ( const llvm :: Module * ) nullptr ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ;


<s> continue ; } if ( i == Mask [ i ] ) { V1UsedInPlace = true ; continue ; } if ( V1DstIndex != - <NUM_LIT> || V2DstIndex != - <NUM_LIT> ) return SDValue ( ) ; if ( Mask [ i ] < <NUM_LIT> ) { V1DstIndex = i ; } else { V2DstIndex = i ; } } if ( V1DstIndex == - <NUM_LIT> && V2DstIndex == - <NUM_LIT> ) return SDValue ( ) ; unsigned V2SrcIndex = <NUM_LIT> ; if ( V1DstIndex != - <NUM_LIT> ) { V2SrcIndex = Mask [ V1DstIndex ] ; V2DstIndex = V1DstIndex ;


<s> bool AMDGPUDAGToDAGISel :: SelectVOP3Mods0Clamp0OMod ( SDValue In , SDValue & Src , SDValue & SrcMods , SDValue & Clamp , SDValue & Omod ) const { Clamp = Omod = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;

return SelectVOP3Mods ( In , Src , SrcMods ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static bool canVectorizeInst ( Instruction * Inst , User * User , const DataLayout & DL ) { switch ( Inst -> getOpcode ( ) ) { case Instruction :: Load : { LoadInst * LI = cast < LoadInst > ( Inst ) ; if ( isa < AllocaInst > ( User ) && LI -> getPointerOperandType ( ) == User -> getType ( ) && isa < VectorType > ( LI -> getType ( ) ) ) return true ; Instruction * PtrInst = dyn_cast < Instruction > ( LI -> getPointerOperand ( ) ) ; if ( ! PtrInst ) return false ; return ( PtrInst -> getOpcode ( ) == Instruction :: GetElementPtr || PtrInst -> getOpcode ( ) == Instruction :: BitCast ) && LI -> isSimple ( ) ; } case Instruction :: BitCast : return true ; case Instruction :: Store : { StoreInst * <ISA_LIT> = cast < StoreInst > ( Inst ) ; if ( isa < AllocaInst > ( User ) && <ISA_LIT> -> getPointerOperandType ( ) == User -> getType ( ) && isa < VectorType > ( <ISA_LIT> -> getValueOperand ( ) -> getType ( ) ) ) return true ; Instruction * UserInst = dyn_cast < Instruction > ( User ) ; if ( ! UserInst ) return false ; return ( <ISA_LIT> -> getPointerOperand ( ) == User ) && ( UserInst -> getOpcode ( ) == Instruction :: GetElementPtr || UserInst -> getOpcode ( ) == Instruction :: BitCast ) && <ISA_LIT> -> isSimple ( ) ; } default : return false ;


<s> bool HasHazard = false ; for ( unsigned I = Begin ; I != End ; ++ I ) { const MachineOperand & MO = MI . getOperand ( I ) ; if ( MO . isReg ( ) && MO . getReg ( ) ) HasHazard |= checkRegDefsUses ( NewDefs , NewUses , MO . getReg ( ) , MO . isDef ( ) ) ; } Defs |= NewDefs ; Uses |= NewUses ; return HasHazard ;


<s> case CCValAssign :: AExt : OutVal = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , OutVal ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) { OutVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; if ( i + <NUM_LIT> < RVLocs . size ( ) && RVLocs [ i + <NUM_LIT> ] . getLocReg ( ) == VA . getLocReg ( ) ) { SDValue NV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVals [ i + <NUM_LIT> ] ) ; OutVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutVal , NV ) ; ++ i ; } } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVal , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; }


<s> } else { if ( ContainerVT . isInteger ( ) ) PassThru = DAG . getConstant ( <NUM_LIT> , DL , ContainerVT ) ; else PassThru = DAG . getConstantFP ( <NUM_LIT> , DL , ContainerVT ) ; if ( isZerosVector ( Load -> getPassThru ( ) . getNode ( ) ) ) IsPassThruZeroOrUndef = true ; } auto NewLoad = DAG . getMaskedLoad ( ContainerVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getOffset ( ) , Mask , PassThru , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) , Load -> getAddressingMode ( ) , Load -> getExtensionType ( ) ) ;


[ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrWithOffset . first ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PtrWithOffset . second ) ; } , } } ;


<s> const <ISA_LIT>Subtarget * <ISA_LIT>BaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = F . getFnAttribute ( <STR_LIT> ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == <STR_LIT> : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? <STR_LIT> : <STR_LIT> ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ;


<s> SDValue r10 = DAG . getSetCC ( DL , OVT , r0 , DAG . getConstant ( <NUM_LIT> , OVT ) , <STR_LIT> ) ; SDValue r11 = DAG . getSetCC ( DL , OVT , r1 , DAG . getConstant ( <NUM_LIT> , OVT ) , <STR_LIT> ) ; r0 = DAG . getNode ( <STR_LIT> , DL , OVT , r0 , r10 ) ; r1 = DAG . getNode ( <STR_LIT> , DL , OVT , r1 , r11 ) ; r0 = DAG . getNode ( <STR_LIT> , DL , OVT , r0 , r10 ) ; r1 = DAG . getNode ( <STR_LIT> , DL , OVT , r1 , r11 ) ; SDValue r20 = DAG . getNode ( <STR_LIT> , DL , OVT , r0 , r1 ) ;

r20 = DAG . getNode ( <STR_LIT> , DL , OVT , r20 , r1 ) ;


<s> bool IsConstant = evaluateConstantImm ( Expr , Imm , VK ) ; if ( IsConstant ) Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> MCRegister <ISA_LIT>RegisterInfo :: getVCC ( ) const { return isWave32 ? <STR_LIT> : <STR_LIT> ;


<s> ImmutableCallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ; return true ;


<s> for ( cpu = & cpu_table [ <NUM_LIT> ] ; cpu -> name ; ++ cpu ) if ( ! strcmp ( sel -> string , cpu -> name ) ) { if ( sel -> set_tune_p ) sparc_cpu = cpu -> processor ; if ( sel -> set_arch_p ) { target_flags &= ~ cpu -> disable ; target_flags |= cpu -> enable ; } break ; } if ( ! cpu -> name ) error ( <STR_LIT> , sel -> string , sel -> name ) ; } } if ( fpu_option_set ) target_flags = ( target_flags & ~ MASK_FPU ) | fpu ; if ( ! TARGET_FPU ) target_flags &= ~ MASK_VIS ; if ( TARGET_VIS || TARGET_ARCH64 ) { target_flags |= MASK_V9 ; target_flags &= ~ ( MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE ) ; } if ( TARGET_V9 && TARGET_ARCH32 ) target_flags |= MASK_DEPRECATED_V8_INSNS ; if ( ! TARGET_V9 || TARGET_ARCH64 ) target_flags &= ~ MASK_V8PLUS ; if ( TARGET_ARCH32 ) target_flags &= ~ MASK_STACK_BIAS ; if ( align_functions == <NUM_LIT> && ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 ) ) align_functions = <NUM_LIT> ; if ( flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN ) flag_pcc_struct_return = ( TARGET_ARCH64 ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! TARGET_ARCH64 ) targetm . asm_out . unaligned_op . di = NULL ; sparc_init_modes ( ) ; sparc_sr_alias_set = new_alias_set ( ) ; struct_value_alias_set = new_alias_set ( ) ; init_machine_status = sparc_init_machine_status ; switch ( sparc_cpu ) { case PROCESSOR_V7 : case PROCESSOR_CYPRESS : sparc_costs = & cypress_costs ; break ; case PROCESSOR_V8 : case PROCESSOR_SPARCLITE : case PROCESSOR_SUPERSPARC : sparc_costs = & supersparc_costs ; break ; case PROCESSOR_F930 : case PROCESSOR_F934 : case PROCESSOR_HYPERSPARC : case PROCESSOR_SPARCLITE86X : sparc_costs = & hypersparc_costs ; break ; case PROCESSOR_SPARCLET : case PROCESSOR_TSC701 : sparc_costs = & sparclet_costs ; break ; case PROCESSOR_V9 : case PROCESSOR_ULTRASPARC : sparc_costs = & ultrasparc_costs ; break ; case PROCESSOR_ULTRASPARC3 :


<s> bool hasAddLogicalFusion ( ) const {


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) if ( ! ( isUndefOrEqual ( Mask [ i ] , i + NumOps ) || ( V2IsUndef && isUndefOrInRange ( Mask [ i ] , NumOps , NumOps * <NUM_LIT> ) ) || ( V2IsSplat && isUndefOrEqual ( Mask [ i ] , NumOps ) ) ) ) return false ; return true ;


<s> if ( * cum < <NUM_LIT> ) return gen_rtx_REG ( arg . mode , * cum + <NUM_LIT> ) ;


<s> static SDValue performBitcastCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; if ( VT . getSimpleVT ( ) . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) != <STR_LIT> && ! ( Op0 -> isMachineOpcode ( ) && Op0 -> getMachineOpcode ( ) == <STR_LIT> ) ) return SDValue ( ) ; uint64_t idx = cast < ConstantSDNode > ( Op0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { if ( Op0 -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) != idx && idx != <NUM_LIT> ) return SDValue ( ) ; } else if ( Op0 -> getMachineOpcode ( ) == <STR_LIT> ) { if ( idx != <STR_LIT> ) return SDValue ( ) ; idx = <NUM_LIT> ; } if ( Op0 -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Source = Op0 -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ; EVT SVT = Source -> getValueType ( <NUM_LIT> ) ;

if ( ! SVT . isVector ( ) || SVT . getVectorNumElements ( ) != VT . getVectorNumElements ( ) * <NUM_LIT> ) return SDValue ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : Op . getNode ( ) -> dumpr ( & DAG ) ; if ( Opc > <STR_LIT> && Opc < <STR_LIT> ) errs ( ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ;

case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ;

InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ;

BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( Rs . Reg , <NUM_LIT> , Rs . Sub ) . addReg ( Rt . Reg , <NUM_LIT> , Rt . Sub ) ;


<s> static unsigned getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL ) {

return ( DL . getTypeSizeInBits ( VecTy ) + <NUM_LIT> ) / <NUM_LIT> ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { auto * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getSimpleValueType ( <NUM_LIT> ) != EltVT ) return SDValue ( ) ; if ( Elt -> getAPIntValue ( ) . isNullValue ( ) ) return SDValue ( ) ;

NewVecC . push_back ( DAG . getConstant ( Elt -> getAPIntValue ( ) - <NUM_LIT> , DL , EltVT ) ) ;


<s> static SDValue PerformVLDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ;


<s> assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; const TargetRegisterClass * RC = TII -> getOpRegClass ( MI , <NUM_LIT> ) ; unsigned Size = RC -> getSize ( ) ; Result . Named . LGKM = Size > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } else { Result . Named . LGKM = <NUM_LIT> ; } } else { Result . Named . LGKM = <NUM_LIT> ; } } else { Result . Named . LGKM = <NUM_LIT> ; } return Result ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> unsigned int align ; align = rs6000_function_arg_boundary ( mode , type ) / PARM_BOUNDARY - <NUM_LIT> ; return nwords + ( - ( rs6000_parm_offset ( ) + nwords ) & align ) ;


<s> break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( Symbol , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ;

const MCExpr * PB = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , Ctx ) ;


<s> return Create ( VK_<ISA_LIT>_LO16 , Expr , Ctx ) ;


<s> return ( ( qword ) ( vec_sub ( ( vec_ushort8 ) ( b ) , ( vec_ushort8 ) ( a ) ) ) ) ;


<s> bool Changed = false ; for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) { Changed |= findInnermostLoop ( * I ) ; } return Changed ;


<s> void <ISA_LIT>InstPrinter :: printFPRRegName ( raw_ostream & O , unsigned RegNo ) const { if ( PrintBranchImmAsAddress ) O << getRegisterName ( RegNo , <STR_LIT> ) ; else O << getRegisterName ( RegNo ) ;


<s> SDValue Y = Op . getOperand ( <NUM_LIT> ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; SDVTList ScaleVT = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue DivScale0 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , Y , Y , X ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Rcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Rcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Rcp , Fma0 , Rcp ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma1 , One ) ; SDValue DivScale1 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , X , Y , X ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma1 , Fma2 , Fma1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 , Fma3 ) ; SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , DivScale1 ) ; SDValue Scale ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { const SDValue Hi = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NumBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue DenBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Y ) ; SDValue Scale0BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Scale1BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 ) ; SDValue NumHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumBC , Hi ) ; SDValue DenHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenBC , Hi ) ; SDValue Scale0Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale0BC , Hi ) ; SDValue Scale1Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale1BC , Hi ) ; SDValue CmpDen = DAG . getSetCC ( SL , <STR_LIT> , DenHi , Scale0Hi , <STR_LIT> ) ;

SDValue CmpNum = DAG . getSetCC ( SL , <STR_LIT> , NumHi , Scale1Hi , <STR_LIT> ) ;


<s> <ISA_LIT>_32TargetMachine :: <ISA_LIT>_32TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>TargetMachine ( T , TT , FS , false ) , DataLayout ( getSubtargetImpl ( ) -> isTargetDarwin ( ) ? <STR_LIT> :

( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> :


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const Target & T , StringRef TT ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( T , TT ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ;

MachineLocation Src ( <STR_LIT> , <NUM_LIT> ) ;


return ( uint64x1_t ) ( __a > __AARCH64_INT64_C ( <NUM_LIT> ) ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( <NUM_LIT> ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ;


<s> void rs6000_secondary_reload_gpr ( rtx reg , rtx mem , rtx scratch , bool store_p ) { int regno = true_regnum ( reg ) ; enum reg_class rclass ; rtx addr ; rtx scratch_or_premodify = scratch ; if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> , store_p ? <STR_LIT> : <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( reg ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( mem ) ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( scratch ) ; } gcc_assert ( regno >= <NUM_LIT> && HARD_REGISTER_NUM_P ( regno ) ) ;


<s> UseCycle -- ; } if ( UseCycle > <ISA_LIT>_MAX_LATENCY ) { break ; } DefCycle = <NUM_LIT> ; for ( MachineBasicBlock :: iterator J = PBB -> end ( ) , PE = PBB -> begin ( ) ; J != PE ; ) { -- J ; MachineInstr & DefMI = * J ; if ( ignoreInstr ( & DefMI ) ) { continue ; } if ( DefMI . getOpcode ( ) != <STR_LIT> ) { DefCycle ++ ; } if ( isJmpInstr ( & DefMI ) ) { MachineBasicBlock * DestMBB = getJmpDest ( & DefMI ) ; if ( DestMBB && DestMBB -> getNumber ( ) == SBB -> getNumber ( ) ) { DefCycle = <NUM_LIT> ; } } if ( ignore_loop_instr && <ISA_LIT>II :: isLoopInst ( DefMI . getDesc ( ) ) && ( DefMI . getOpcode ( ) != <STR_LIT> ) ) { DefCycle -- ; } if ( ( UseCycle + DefCycle ) > <ISA_LIT>_MAX_LATENCY ) { break ; } int lat ; if ( DefMI . getOpcode ( ) == <STR_LIT> && UseMI . getOpcode ( ) != <STR_LIT> ) { lat = <NUM_LIT> ; } else {

lat = getRequiredDistance ( DefMI , UseMI , UseCycle + DefCycle - <NUM_LIT> ) ;


<s> APInt DemandedMask ( APInt :: getSignMask ( Mask . getScalarValueSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Mask , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const {


return AsmPrinter :: doFinalization ( M ) ;


<s> RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; } case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ;


<s> return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;


if ( cfun && cfun -> decl ) return lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( cfun -> decl ) ) ;


<s> int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } unsigned FrameReg ; FrameReg = <STR_LIT> ; int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ;

FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ;


<s> return new <ISA_LIT>Disassembler ( STI ) ;


<s> static bool isNonZeroElementsInOrder ( const SmallBitVector Zeroable , ArrayRef < int > Mask , const EVT & VectorType , bool & IsZeroSideLeft ) { int NextElement = - <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Zeroable . size ( ) ; i < e ; i ++ ) {

if ( Mask [ i ] == - <NUM_LIT> ) return false ;


<s> bool <ISA_LIT>SinglePathInfo :: isMaybe ( const MachineFunction & MF ) {

return MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ;


<s> if ( Function * F = dyn_cast < Function > ( v ) ) return F ; if ( Instruction * I = dyn_cast < Instruction > ( v ) ) return I -> getParent ( ) -> getParent ( ) ; if ( BasicBlock * B = dyn_cast < BasicBlock > ( v ) ) return B -> getParent ( ) ;


<s> bool isMemWithUimmOffsetSP ( ) const {

return isMem ( ) && isConstantMemOff ( ) && isUInt < Bits > ( getConstantMemOff ( ) ) && getMemBase ( ) -> isRegIdx ( ) && ( getMemBase ( ) -> getGPR32Reg ( ) == <STR_LIT> ) ;


<s> if ( SrcSize == <NUM_LIT> ) { EVT VecIdxTy = getVectorIdxTy ( DAG . getDataLayout ( ) ) ; EVT SplitVT = N1 . getValueType ( ) . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned SplitNumElts = SplitVT . getVectorNumElements ( ) ; Op1 = DAG . getNode ( <STR_LIT> , DL , SplitVT , N1 , DAG . getConstant ( <NUM_LIT> , DL , VecIdxTy ) ) ; Op2 = DAG . getNode ( <STR_LIT> , DL , SplitVT , N1 , DAG . getConstant ( SplitNumElts , DL , VecIdxTy ) ) ; } else { Op1 = SrcSize == <NUM_LIT> ? N1 : widenVec ( DAG , N1 , DL ) ; Op2 = DAG . getUNDEF ( WideVT ) ; } unsigned SizeMult = SrcSize / TrgVT . getSizeInBits ( ) ; SmallVector < int , <NUM_LIT> > ShuffV ; if ( Subtarget . isLittleEndian ( ) ) for ( unsigned i = <NUM_LIT> ; i < TrgNumElts ; ++ i ) ShuffV . push_back ( i * SizeMult ) ; else for ( unsigned i = <NUM_LIT> ; i <= TrgNumElts ; ++ i ) ShuffV . push_back ( i * SizeMult - <NUM_LIT> ) ;

for ( unsigned i = TrgNumElts ; i < WideNumElts ; ++ i ) ShuffV . push_back ( WideNumElts + <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , <STR_LIT> ) ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ;


<s> if ( parseSwizzleOperand ( LaneIdx , <NUM_LIT> , GroupSize - <NUM_LIT> , <STR_LIT> , Loc ) ) { Imm = encodeBitmaskPerm ( BITMASK_MAX - GroupSize + <NUM_LIT> , LaneIdx , <NUM_LIT> ) ; return true ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) {