<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & LIS = getAnalysis < LiveIntervals > ( ) ; MRI . leaveSSA ( ) ; assert ( MRI . tracksLiveness ( ) && <STR_LIT> ) ; SmallVector < LiveInterval * , <NUM_LIT> > SplitLIs ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I < E ; ++ I ) { unsigned Reg = Register :: index2VirtReg ( I ) ; auto & TRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; if ( MRI . reg_nodbg_empty ( Reg ) ) continue ; LIS . splitSeparateComponents ( LIS . getInterval ( Reg ) , SplitLIs ) ; if ( Reg == TRI . getFrameRegister ( MF ) && SplitLIs . size ( ) > <NUM_LIT> ) { MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setFrameBaseVreg ( SplitLIs . back ( ) -> reg ( ) ) ; } SplitLIs . clear ( ) ;


<s> getReadTimeStampCounter ( Op . getNode ( ) , DL , <STR_LIT> , DAG , Subtarget , Results ) ; return DAG . getMergeValues ( Results , DL ) ;


<s> assert ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) || ( <STR_LIT> <= Opcode && Opcode <= <STR_LIT> ) ) { return DisassembleThumb2LdStEx ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { return DisassembleThumb2LdStDual ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { return DisassembleThumb2TB ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } } else if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { return DisassembleThumb2DPSoReg ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ; } break ; case <NUM_LIT> : if ( op == <NUM_LIT> ) { if ( slice ( op2 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) {

return DisassembleThumb2DPModImm ( MI , Opcode , insn , NumOps , NumOpsAdded , B ) ;


<s> bool HasAnyUndefs ; if ( ! BVN || ! BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs , ElementBits ) || SplatBitSize > ElementBits ) return false ; Cnt = SplatBits . getSExtValue ( ) ;


<s> static char one_inst_str [ <NUM_LIT> ] ; int i , start_reg ; int word_cnt ; int print_ra ; char * return_str ; char * temp_str ; return_str = ( char * ) xmalloc ( <NUM_LIT> ) ; temp_str = ( char * ) xmalloc ( <NUM_LIT> ) ; memset ( return_str , <NUM_LIT> , <NUM_LIT> ) ; i = <NUM_LIT> ; while ( i <= current_frame_info . last_reg_to_save ) { one_inst_str [ <NUM_LIT> ] = <NUM_LIT> ; word_cnt = <NUM_LIT> ; start_reg = i ; print_ra = <NUM_LIT> ; while ( ( word_cnt < MAX_COUNT ) && ( i <= current_frame_info . last_reg_to_save ) ) { if ( ! current_frame_info . save_regs [ i ] ) { ++ i ; break ; } if ( i == RETURN_ADDRESS_REGNUM ) print_ra = <NUM_LIT> ; else { if ( ( word_cnt + ( ( i < CR16_FIRST_DWORD_REGISTER ) ? <NUM_LIT> : <NUM_LIT> ) ) >= MAX_COUNT ) break ; word_cnt += ( ( i < CR16_FIRST_DWORD_REGISTER ) ? <NUM_LIT> : <NUM_LIT> ) ; } ++ i ; } if ( ( word_cnt == <NUM_LIT> ) && ( print_ra == <NUM_LIT> ) ) continue ; if ( word_cnt > <NUM_LIT> ) { sprintf ( one_inst_str , <STR_LIT> , word_cnt , reg_names [ start_reg ] ) ; if ( print_ra ) strcat ( one_inst_str , <STR_LIT> ) ; } else strcat ( one_inst_str , <STR_LIT> ) ; if ( push_or_pop == <NUM_LIT> ) { if ( print_ra && ! cr16_interrupt_function_p ( ) && ! crtl -> calls_eh_return ) strcpy ( temp_str , <STR_LIT> ) ; else strcpy ( temp_str , <STR_LIT> ) ; strcat ( temp_str , one_inst_str ) ; strcat ( return_str , temp_str ) ; } else { strcpy ( temp_str , <STR_LIT> ) ; strcat ( temp_str , one_inst_str ) ; strcat ( temp_str , return_str ) ; strcpy ( return_str , temp_str ) ; } } if ( push_or_pop == <NUM_LIT> ) { if ( cr16_interrupt_function_p ( ) ) strcat ( return_str , <STR_LIT> ) ; else if ( crtl -> calls_eh_return ) { strcat ( return_str , <STR_LIT> ) ; strcat ( return_str , <STR_LIT> ) ; strcpy ( temp_str , <STR_LIT> ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getAllAGPRRegMask ( ) const { return <ISA_LIT>_AllAGPRs_RegMask ;


<s> case <STR_LIT> : return lowerV2I64VectorShuffle ( DL , Mask , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV2F64VectorShuffle ( DL , Mask , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I32VectorShuffle ( DL , Mask , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4F32VectorShuffle ( DL , Mask , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> :

return lowerV8I16VectorShuffle ( DL , Mask , V1 , V2 , Subtarget , DAG ) ;


<s> IncomingArgSize = Size ; HasByvalArg = HasByval ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ;


<s> static tree aarch64_get_attributes ( aarch64_simd_builtin_datum * d ) { tree attrs = NULL_TREE ; if ( ! aarch64_modifies_global_state_p ( d ) ) {

if ( aarch64_reads_global_state_p ( d ) ) attrs = aarch64_add_attribute ( <STR_LIT> , attrs ) ;


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , const DebugLoc & dl , const ThumbRegisterInfo & MRI , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags ) { emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , NumBytes , TII , MRI , MIFlags ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && ! Subtarget . is<ISA_LIT>64 ( ) ) return SDValue ( ) ; if ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; bool IsNegPow2 = ( - Divisor ) . isPowerOf2 ( ) ; unsigned Lg2 = ( IsNegPow2 ? - Divisor : Divisor ) . countTrailingZeros ( ) ; SDValue ShiftAmt = DAG . getConstant ( Lg2 , DL , VT ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , VT , N0 , ShiftAmt ) ; if ( Created ) Created -> push_back ( Op . getNode ( ) ) ; if ( IsNegPow2 ) { Op = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Op ) ; if ( Created ) Created -> push_back ( Op . getNode ( ) ) ;


<s> fixELFSymbolsInTLSFixupsImpl ( expr , Asm ) ;


<s> return code == SYMBOL_REF || code == LABEL_REF || code == CONST ;


<s> unsigned <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) {

if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ;


<s> } SetjmpF2 -> replaceAllUsesWith ( SetjmpF ) ; } if ( LongjmpF2 ) { if ( LongjmpF ) { if ( LongjmpF -> getFunctionType ( ) != LongjmpF2 -> getFunctionType ( ) ) report_fatal_error ( <STR_LIT> ) ; } else { LongjmpF = Function :: Create ( LongjmpF2 -> getFunctionType ( ) , GlobalValue :: ExternalLinkage , <STR_LIT> , M ) ; } LongjmpF2 -> replaceAllUsesWith ( LongjmpF ) ; } auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; assert ( TPC && <STR_LIT> ) ; auto & TM = TPC -> getTM < <ISA_LIT>TargetMachine > ( ) ; ThrewGV = getGlobalVariable ( M , getAddrIntType ( & M ) , TM , <STR_LIT> ) ; ThrewValueGV = getGlobalVariable ( M , IRB . getInt32Ty ( ) , TM , <STR_LIT> ) ; GetTempRet0F = getEmscriptenFunction ( FunctionType :: get ( IRB . getInt32Ty ( ) , false ) , <STR_LIT> , & M ) ; SetTempRet0F = getEmscriptenFunction ( FunctionType :: get ( IRB . getVoidTy ( ) , IRB . getInt32Ty ( ) , false ) , <STR_LIT> , & M ) ; GetTempRet0F -> setDoesNotThrow ( ) ; SetTempRet0F -> setDoesNotThrow ( ) ; bool Changed = false ; if ( EnableEmEH ) { FunctionType * ResumeFTy = FunctionType :: get ( IRB . getVoidTy ( ) , IRB . getInt8PtrTy ( ) , false ) ; ResumeF = getEmscriptenFunction ( ResumeFTy , <STR_LIT> , & M ) ; ResumeF -> addFnAttr ( Attribute :: NoReturn ) ; FunctionType * EHTypeIDTy = FunctionType :: get ( IRB . getInt32Ty ( ) , IRB . getInt8PtrTy ( ) , false ) ; EHTypeIDF = getEmscriptenFunction ( EHTypeIDTy , <STR_LIT> , & M ) ; } SmallPtrSet < Function * , <NUM_LIT> > SetjmpUsersToNullify ; if ( ( EnableEmSjLj || EnableWasmSjLj ) && SetjmpF ) { for ( User * U : SetjmpF -> users ( ) ) { if ( auto * CB = dyn_cast < CallBase > ( U ) ) { auto * UserF = CB -> getFunction ( ) ; if ( containsLongjmpableCalls ( UserF ) ) SetjmpUsers . insert ( UserF ) ; else SetjmpUsersToNullify . insert ( UserF ) ; } else { std :: string S ; raw_string_ostream SS ( S ) ; SS << * U ; report_fatal_error ( Twine ( <STR_LIT> ) + SS . str ( ) ) ; } } } bool SetjmpUsed = SetjmpF && ! SetjmpUsers . empty ( ) ; bool LongjmpUsed = LongjmpF && ! LongjmpF -> use_empty ( ) ; DoSjLj = ( EnableEmSjLj | EnableWasmSjLj ) && ( SetjmpUsed || LongjmpUsed ) ; if ( DoSjLj ) { assert ( EnableEmSjLj || EnableWasmSjLj ) ; if ( EnableEmSjLj ) { FunctionType * FTy = FunctionType :: get ( IRB . getVoidTy ( ) , { getAddrIntType ( & M ) , IRB . getInt32Ty ( ) } , false ) ; EmLongjmpF = getEmscriptenFunction ( FTy , <STR_LIT> , & M ) ;

EmLongjmpF -> addFnAttr ( Attribute :: NoReturn ) ;


<s> if ( C -> getZExtValue ( ) == <NUM_LIT> || C -> getZExtValue ( ) == <NUM_LIT> || ( Subtarget -> is64Bit ( ) && C -> getZExtValue ( ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; case 'e' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , <STR_LIT> ) ; break ; } } return ; } case 'Z' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ; break ; } } return ; } case 'i' : { if ( ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ) { Result = DAG . getTargetConstant ( CST -> getSExtValue ( ) , <STR_LIT> ) ; break ; } if ( Subtarget -> isPICStyleGOT ( ) || Subtarget -> isPICStyleStubPIC ( ) ) return ; GlobalAddressSDNode * GA = nullptr ; int64_t Offset = <NUM_LIT> ; while ( <NUM_LIT> ) { if ( ( GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) ) { Offset += GA -> getOffset ( ) ; break ; } else if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { Offset += C -> getZExtValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ; continue ;


<s> if ( GET_CODE ( orig ) == LABEL_REF || ( GET_CODE ( orig ) == SYMBOL_REF && SYMBOL_REF_LOCAL_P ( orig ) ) ) { if ( reg == <NUM_LIT> ) reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOTOFF2reg ( reg , orig ) ) ; return reg ; } else if ( GET_CODE ( orig ) == SYMBOL_REF ) { if ( reg == <NUM_LIT> ) reg = gen_reg_rtx ( Pmode ) ;

emit_insn ( gen_symGOT2reg ( reg , orig ) ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Insn ) ) ) ;


<s> return RC -> contains ( Reg ) ; } else {

return MRI -> getRegClass ( Reg ) == RC ;


<s> if ( MO . getReg ( ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> unsigned arm_cde_end_args ( tree fndecl ) {


<s> const MCSymbolRefExpr * SR = dyn_cast < MCSymbolRefExpr > ( Imm . Val ) ; assert ( SR && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createExpr ( SR ) ) ; return ; } assert ( isGPRMem ( ) && <STR_LIT> ) ; assert ( isa < MCConstantExpr > ( Memory . OffsetImm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Memory . OffsetImm -> getValue ( ) ) ) ;


<s> int fma_forest :: get_target_parity ( ) {


<s> case 'k' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'q' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; } O << '%' << TRI -> getAsmName ( Reg ) ;


<s> if ( DstRB . getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * DstRC = getRegClassForTypeOnBank ( DstTy , DstRB ) ; if ( ! DstRC ) return false ; const TargetRegisterClass * SrcRC = getRegClassForTypeOnBank ( SrcTy , SrcRB ) ; if ( ! SrcRC ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstRC == SrcRC ) { } else if ( DstRC == & <STR_LIT> ) { I . getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; } else if ( DstRC == & <STR_LIT> ) { I . getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; } else if ( DstRC == & <STR_LIT> ) { I . getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; } else { return false ; } I . setDesc ( TII . get ( <STR_LIT> ) ) ; return true ;


<s> unsigned DestSub0 = MRI . createVirtualRegister ( DestRC ) ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) . addOperand ( SrcReg1Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , AMDGPU :: sub1 , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , AMDGPU :: sub1 , Src1SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( DestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) . addOperand ( SrcReg1Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( DestRC ) ;

BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( AMDGPU :: sub0 ) . addReg ( DestSub1 ) . addImm ( AMDGPU :: sub1 ) ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; IndirectTlsSegRefs = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ; new <ISA_LIT>TargetAsmStreamer ( * S , OS ) ;


<s> USet Rs ; for ( unsigned i = <NUM_LIT> , n = WorkQ . size ( ) ; i < n ; ++ i ) { MachineLoop * L = WorkQ [ i ] ; Rs . clear ( ) ; collectIndRegsForLoop ( L , Rs ) ; if ( ! Rs . empty ( ) ) IRM . insert ( std :: make_pair ( L , Rs ) ) ;


<s> <ISA_LIT>BundlingPass ( <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( & ID ) , TM ( tm ) {


<s> return __builtin_aarch64_sqdmull2v8hi ( __a , __b ) ;


<s> else if ( from == GENERAL_REGS ) return regmove_cost -> GP2FP * <NUM_LIT> ; else if ( to == GENERAL_REGS ) return regmove_cost -> FP2GP * <NUM_LIT> ; if ( ! TARGET_SIMD ) return regmove_cost -> GP2FP + regmove_cost -> FP2GP + regmove_cost -> FP2FP ; return regmove_cost -> FP2FP ; } if ( from == GENERAL_REGS && to == GENERAL_REGS ) return regmove_cost -> GP2GP ; else if ( from == GENERAL_REGS ) return regmove_cost -> GP2FP ;

else if ( to == GENERAL_REGS ) return regmove_cost -> FP2GP ;


<s> unsigned <ISA_LIT>ParamManager :: addCallRetParam ( Type * Ty , const StringRef ParamName ) { return addParam ( <ISA_LIT>_PARAM_TYPE_CALL_RET , Ty , ParamName ) ;


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; O << <STR_LIT> ; printOperand ( MI , OpNo ) ; O << <STR_LIT> ;


<s> case <STR_LIT> : TCC = <STR_LIT> ; if ( LHS . getOpcode ( ) == <STR_LIT> ) std :: swap ( LHS , RHS ) ; break ; } TargetCC = DAG . getConstant ( TCC , <STR_LIT> ) ; if ( LHS . getValueType ( ) . isFloatingPoint ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ;


<s> <ISA_LIT>MCELFStreamer :: <ISA_LIT>MCELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > Emitter , MCAssembler * Assembler ) : MCELFStreamer ( Context , std :: move ( TAB ) , OS , std :: move ( Emitter ) ) , MCII ( create<ISA_LIT>MCInstrInfo ( ) ) {


<s> Helper . Ownership [ New ] = Owner ; IndependentGroups [ Owner ] . insert ( New ) ; Queue . push_back ( New ) ; continue ; } Block * NewOwner = Known -> second ; if ( ! NewOwner ) continue ; if ( NewOwner != Owner ) Helper . InvalidateWithChildren ( New ) ; } } for ( const auto & iter : Entries ) { BlockSet & CurrGroup = IndependentGroups [ iter ] ; BlockList ToInvalidate ; for ( const auto & iter : CurrGroup ) { Block * Child = iter ; for ( const auto & iter : Child -> BranchesIn ) { Block * Parent = iter ; if ( Ignore && contains ( * Ignore , Parent ) ) continue ; if ( Helper . Ownership [ Parent ] != Helper . Ownership [ Child ] ) ToInvalidate . push_back ( Child ) ; } } while ( ! ToInvalidate . empty ( ) ) {

Block * Invalidatee = ToInvalidate . front ( ) ;


<s> virtual ~ <ISA_LIT>Disassembler ( ) {


<s> tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . setOpcode ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ;

tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue & <NUM_LIT> ) ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & T ) { CodePointerSize = CalleeSaveStackSlotSize = T . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; UseDataRegionDirectives = true ; ZeroDirective = <STR_LIT> ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; COMMDirectiveAlignmentIsInBytes = false ;

LCOMMDirectiveAlignmentType = LCOMM :: Log2Alignment ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getSetCC ( dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , CC ) ) ; } return SDValue ( ) ; } return Op ; } if ( SDValue V = lowerCmpEqZeroToCtlzSrl ( Op , DAG ) ) return V ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) {

if ( C -> isAllOnesValue ( ) || C -> isNullValue ( ) ) return SDValue ( ) ;


<s> for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ;


<s> unsigned getMaxWavesPerEU ( unsigned FlatWorkGroupSize ) const override { return <STR_LIT> :: getMaxWavesPerEU ( this , FlatWorkGroupSize ) ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const {

if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ;


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; assert ( Op . isImm ( ) && <STR_LIT> ) ; switch ( Op . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;

case <NUM_LIT> : O << <STR_LIT> ; break ;


<s> static DecodeStatus DecodeGPRNoX0RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo == <NUM_LIT> ) { return MCDisassembler :: Fail ; } return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> void printAS32Mem ( const MCInst * MI , unsigned opNum , raw_ostream & O ) { printAbsMem ( MI , opNum , O ) ;


<s> if ( Kind . isReadOnly ( ) ) { const auto * GVar = dyn_cast < GlobalVariable > ( GO ) ;

if ( GVar && GVar -> isConstant ( ) && GVar -> getInitializer ( ) -> needsDynamicRelocation ( ) ) Kind = SectionKind :: getReadOnlyWithRel ( ) ;


<s> GetElementPtrInst * GEP = cast < GetElementPtrInst > ( stripBitcasts ( Ptr ) ) ; auto I = GEPIdx . find ( GEP ) ;

return I == GEPIdx . end ( ) ? nullptr : I -> second ;


<s> if ( ( SignedDivRem || UnsignedDivRem ) && Args . size ( ) == <NUM_LIT> ) { if ( const Constant * C = dyn_cast < Constant > ( Args [ <NUM_LIT> ] ) ) { const ConstantInt * CVal = ( C -> getType ( ) -> isVectorTy ( ) ? dyn_cast_or_null < const ConstantInt > ( C -> getSplatValue ( ) ) : dyn_cast < const ConstantInt > ( C ) ) ; if ( CVal != nullptr && ( CVal -> getValue ( ) . isPowerOf2 ( ) || ( - CVal -> getValue ( ) ) . isPowerOf2 ( ) ) ) DivRemConstPow2 = true ; else DivRemConst = true ; } } if ( Ty -> isVectorTy ( ) ) { assert ( ST -> hasVector ( ) && <STR_LIT> ) ; unsigned VF = Ty -> getVectorNumElements ( ) ; unsigned NumVectors = getNumVectorRegs ( Ty ) ; if ( Opcode == Instruction :: Shl || Opcode == Instruction :: LShr || Opcode == Instruction :: AShr ) { return NumVectors ; } if ( DivRemConstPow2 ) return ( NumVectors * ( SignedDivRem ? SDivPow2Cost : <NUM_LIT> ) ) ; if ( DivRemConst ) return VF * DivMulSeqCost + getScalarizationOverhead ( Ty , Args ) ; if ( ( SignedDivRem || UnsignedDivRem ) && VF > <NUM_LIT> ) return <NUM_LIT> ; if ( Opcode == Instruction :: FAdd || Opcode == Instruction :: FSub || Opcode == Instruction :: FMul || Opcode == Instruction :: FDiv ) { switch ( ScalarBits ) { case <NUM_LIT> : { if ( ST -> hasVectorEnhancements1 ( ) ) return NumVectors ; unsigned ScalarCost = getArithmeticInstrCost ( Opcode , Ty -> getScalarType ( ) ) ; unsigned Cost = ( VF * ScalarCost ) + getScalarizationOverhead ( Ty , Args ) ; if ( VF == <NUM_LIT> ) Cost *= <NUM_LIT> ; return Cost ; } case <NUM_LIT> : case <NUM_LIT> : return NumVectors ; default : break ; } }


<s> TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) {


<s> SDLoc DL ( N ) ; if ( N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) ) { if ( N -> getOpcode ( ) == <STR_LIT> ) return getOnesVector ( VT , Subtarget , DAG , DL ) ;

if ( N -> getOpcode ( ) == <STR_LIT> ) return getZeroVector ( VT , Subtarget , DAG , DL ) ;


<s> CASE_CONST_SCALAR_INT : case CONST_DOUBLE : gcc_assert ( operands [ <NUM_LIT> ] == CONST0_RTX ( mode ) ) ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] = const0_rtx ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case REG : operands [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; break ; case MEM : operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , DImode , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , DImode , <NUM_LIT> ) ;


<s> Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getLocRange ( ) ) ;


<s> GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , <NUM_LIT> , Name ) ; return <ISA_LIT>MaterializeGV ( GV , TLI . getValueType ( GV -> getType ( ) ) ) ;


<s> Tile64RegisterInfo :: Tile64RegisterInfo ( const TargetInstrInfo & tii ) : Tile64GenRegisterInfo ( <STR_LIT> ) , TII ( tii ) {


<s> case VK_CALL : return <STR_LIT> ; case VK_LO12 : return <STR_LIT> ; case VK_ABS_G3 : return <STR_LIT> ; case VK_ABS_G2 : return <STR_LIT> ; case VK_ABS_G2_S : return <STR_LIT> ; case VK_ABS_G2_NC : return <STR_LIT> ; case VK_ABS_G1 : return <STR_LIT> ; case VK_ABS_G1_S : return <STR_LIT> ; case VK_ABS_G1_NC : return <STR_LIT> ; case VK_ABS_G0 : return <STR_LIT> ; case VK_ABS_G0_S : return <STR_LIT> ; case VK_ABS_G0_NC : return <STR_LIT> ; case VK_PREL_G3 : return <STR_LIT> ; case VK_PREL_G2 : return <STR_LIT> ; case VK_PREL_G2_NC : return <STR_LIT> ; case VK_PREL_G1 : return <STR_LIT> ; case VK_PREL_G1_NC : return <STR_LIT> ; case VK_PREL_G0 : return <STR_LIT> ; case VK_PREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_G2 : return <STR_LIT> ; case VK_DTPREL_G1 : return <STR_LIT> ; case VK_DTPREL_G1_NC : return <STR_LIT> ; case VK_DTPREL_G0 : return <STR_LIT> ; case VK_DTPREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_HI12 : return <STR_LIT> ; case VK_DTPREL_LO12 : return <STR_LIT> ; case VK_DTPREL_LO12_NC : return <STR_LIT> ; case VK_TPREL_G2 : return <STR_LIT> ; case VK_TPREL_G1 : return <STR_LIT> ; case VK_TPREL_G1_NC : return <STR_LIT> ; case VK_TPREL_G0 : return <STR_LIT> ; case VK_TPREL_G0_NC : return <STR_LIT> ; case VK_TPREL_HI12 : return <STR_LIT> ; case VK_TPREL_LO12 : return <STR_LIT> ; case VK_TPREL_LO12_NC : return <STR_LIT> ; case VK_TLSDESC_LO12 : return <STR_LIT> ;


<s> llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : case FK_PCRel_4 : return RT_32 ; case FK_PCRel_2 :


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo / <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> return ApplyFunctions [ pType ] . size ;


<s> Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; default : <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) , * this ) ; Lower . lower ( & * I , LoweredMI ) ; break ; } EmitToStreamer ( * OutStreamer , LoweredMI ) ;

} while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ;


<s> __builtin_sh_media_STHI_Q ( ( char * ) p + s , mw ) ;


<s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override {


<s> unsigned int i , high , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ^ is_swapped ] ; high = nelt / <NUM_LIT> ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) high = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , <NUM_LIT> * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , <NUM_LIT> * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) {

case E_V16QImode : gen = gen_neon_vzipv16qi_internal ; break ;


<s> else { templ = <STR_LIT> ; ops [ <NUM_LIT> ] = mem ; } ops [ <NUM_LIT> ] = reg ; break ; case PRE_DEC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; case POST_MODIFY : gcc_unreachable ( ) ; case REG : if ( nregs > <NUM_LIT> ) { if ( nregs > <NUM_LIT> ) templ = <STR_LIT> ; else templ = <STR_LIT> ; ops [ <NUM_LIT> ] = mem ; ops [ <NUM_LIT> ] = reg ; break ; } case LABEL_REF : case PLUS : { int i ; int overlap = - <NUM_LIT> ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( reg ) + <NUM_LIT> * i ) ; ops [ <NUM_LIT> ] = adjust_address ( mem , DImode , <NUM_LIT> * i ) ; if ( reg_overlap_mentioned_p ( ops [ <NUM_LIT> ] , mem ) ) { gcc_assert ( overlap == - <NUM_LIT> ) ; overlap = i ; } else { sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ; } } if ( overlap != - <NUM_LIT> ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( reg ) + <NUM_LIT> * overlap ) ; ops [ <NUM_LIT> ] = adjust_address ( mem , SImode , <NUM_LIT> * overlap ) ; sprintf ( buff , <STR_LIT> , load ? <STR_LIT> : <STR_LIT> ) ; output_asm_insn ( buff , ops ) ; } return <STR_LIT> ; } default :


<s> FOREACH_FUNCTION_ARGS ( m_fntype , type , iter ) { if ( type == void_type_node || i >= m_nargs ) break ; if ( i >= m_base_arg && TREE_CODE ( type ) == ENUMERAL_TYPE && ! require_immediate_enum ( i - m_base_arg , type ) ) return false ;


<s> static DecodeStatus decodeImmShiftOpValue ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( Log2 ( Imm ) ) ) ;


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const {


<s> bool empty ( ) const { return ! BitVector :: any ( ) ;


<s> int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; WarnSize ( Offset , MF , DL ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; Register reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) llvm_unreachable ( <STR_LIT> ) ; WarnSize ( Offset , MF , DL ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Register reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( FrameReg ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; MI . eraseFromParent ( ) ;


<s> auto UpdatedVal = std :: get < <NUM_LIT> > ( DiffCBegin -> second ) + StrideVal ; DiffCoords . erase ( DiffCBegin ) ; DiffCoords . insert ( { TensorId , std :: make_tuple ( Index , UpdatedVal , Formula , CurrLoop , PHI ) } ) ; Update = true ; break ; } DiffCBegin ++ ; } if ( ! Update ) { DiffCoords . insert ( { TensorId , std :: make_tuple ( Index , StrideVal , Formula , CurrLoop , PHI ) } ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectG_<ISA_LIT>TOFP_UITOFP ( MachineInstr & I ) const { MachineBasicBlock * MBB = I . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register Src = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isSCC ( Src , MRI ) ) return selectImpl ( I , * CoverageInfo ) ; bool Signed = I . getOpcode ( ) == <STR_LIT> ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;

const LLT DstTy = MRI . getType ( DstReg ) ;


<s> const <ISA_LIT>FrameLowering * TFI = MF . getSubtarget < GCNSubtarget > ( ) . getFrameLowering ( ) ; const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : FuncInfo -> getStackPtrOffsetReg ( ) ;


<s> return MatchOperand_ParseFail ; } int64_t LSB = CE -> getValue ( ) ; if ( LSB < <NUM_LIT> || LSB > <NUM_LIT> ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * WidthExpr ; SMLoc EndLoc ; if ( getParser ( ) . ParseExpression ( WidthExpr , EndLoc ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } CE = dyn_cast < MCConstantExpr > ( WidthExpr ) ; if ( ! CE ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> vdup_n_u64 ( uint64_t __a ) { return ( uint64x1_t ) { __a } ;


return ( __m128i ) __builtin_ia32_cvttpd2dq256 ( ( __v4df ) __A ) ;


<s> unsigned DstSize = countPopulation ( DMask ) ; if ( DstSize == <NUM_LIT> ) return MCDisassembler :: Success ; bool D16 = MCII -> get ( MI . getOpcode ( ) ) . TSFlags & <STR_LIT> ; if ( D16 && <STR_LIT> ( STI ) ) { DstSize = ( DstSize + <NUM_LIT> ) / <NUM_LIT> ; } if ( MI . getOperand ( TFEIdx ) . getImm ( ) ) return MCDisassembler :: Success ; int NewOpcode = - <NUM_LIT> ; if ( isAtomic ) { if ( DMask == <NUM_LIT> || DMask == <NUM_LIT> || DMask == <NUM_LIT> ) { NewOpcode = <STR_LIT> ( * MCII , MI . getOpcode ( ) , DstSize ) ; } if ( NewOpcode == - <NUM_LIT> ) return MCDisassembler :: Success ; } else { NewOpcode = <STR_LIT> ( * MCII , MI . getOpcode ( ) , DstSize ) ; assert ( NewOpcode != - <NUM_LIT> && <STR_LIT> ) ; }

auto RCID = MCII -> get ( NewOpcode ) . OpInfo [ VDataIdx ] . RegClass ;


<s> } <ISA_LIT>Section * NewBSS = FoundBSS ; if ( NewBSS == NULL ) { const MCSection<ISA_LIT> * NewSection = get<ISA_LIT>Section ( Name . c_str ( ) , SectionKind :: getBSS ( ) ) ; NewBSS = new <ISA_LIT>Section ( NewSection ) ; BSSSections . push_back ( NewBSS ) ; } NewBSS -> Items . push_back ( GV ) ; NewBSS -> Size = DataBankSize ;


<s> if ( ! IsSigned ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget -> is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ;


<s> if ( UnsupportedFPMode ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; Register SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; Register DestReg = createResultReg ( & <STR_LIT> ) ; if ( ! DestReg ) return false ; emitInst ( <STR_LIT> , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( I , DestReg ) ; return true ;


<s> if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! OpToFold . getReg ( ) . isVirtual ( ) ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ) continue ; foldInstOperand ( MI , OpToFold ) ; auto * InstToErase = & MI ; while ( MRI -> use_nodbg_empty ( InstToErase -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { auto & SrcOp = InstToErase -> getOperand ( <NUM_LIT> ) ; auto SrcReg = SrcOp . isReg ( ) ? SrcOp . getReg ( ) : Register ( ) ; InstToErase -> eraseFromParent ( ) ; InstToErase = nullptr ; if ( ! SrcReg || SrcReg . isPhysical ( ) ) break ; InstToErase = MRI -> getVRegDef ( SrcReg ) ; if ( ! InstToErase || ! TII -> isFoldableCopy ( * InstToErase ) ) break ; } if ( InstToErase && InstToErase -> isRegSequence ( ) && MRI -> use_nodbg_empty ( InstToErase -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) InstToErase -> eraseFromParent ( ) ;


<s> auto Ins = MIRBuilder . buildInstr ( TargetOpcode :: INSERT_SUBREG , { DstRC } , { Undef , Scalar } ) . addImm ( SubregIndex ) ; constrainSelectedInstRegOperands ( * Undef , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( * Ins , TII , TRI , RBI ) ; return & * Ins ; } ; switch ( EltSize ) { case <NUM_LIT> : return BuildFn ( <STR_LIT> ) ; case <NUM_LIT> : return BuildFn ( <STR_LIT> ) ; case <NUM_LIT> : return BuildFn ( <STR_LIT> ) ; default : return nullptr ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { switch ( CallConv ) {


if ( TARGET_HAVE_MVE ) return arm_mode_to_pred_mode ( mode ) ;


<s> return ( int8_t ) __builtin_neon_vget_lanev8qi ( __a , __b ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( KindReg , StartLoc , EndLoc ) ; Op -> Reg . Kind = Kind ; Op -> Reg . Num = Num ; return Op ;


<s> unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_OR_B64 ) , Dst ) . addReg ( AMDGPU :: EXEC ) . addReg ( Src ) ; MI . eraseFromParent ( ) ;


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ OpId ] . OperandType != MCOI :: OPERAND_PCREL ) return false ;

Target = Addr + Inst . getOperand ( OpId ) . getImm ( ) + <NUM_LIT> ;


assert ( Kind == K_Register && <STR_LIT> ) ;


<s> static int avr_naked_function_p ( tree func ) { return avr_lookup_function_attribute1 ( func , <STR_LIT> ) ;


<s> bool GCNPassConfig :: addInstSelector ( ) { <ISA_LIT>PassConfig :: addInstSelector ( ) ; addPass ( & <ISA_LIT>FixSGPRCopiesID ) ; addPass ( create<ISA_LIT>LowerI1CopiesPass ( ) ) ; return false ;


<s> return __builtin_mve_vshrq_m_n_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a , __imm , __p ) ;


<s> switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ;


<s> if ( ! riscv_vector_chunks . is_constant ( ) && riscv_v_ext_vector_mode_p ( mode ) ) return BYTES_PER_RISCV_VECTOR ;


<s> bool isCaptableOff ( ) const { <ISA_LIT>ExprKind Kind ; return isOffImpl ( Kind , MEK_CAPTABLEREL ) ;


<s> PromoteTree ( Visited , Sources , Sinks , SafeToPromote ) ; TruncateSinks ( Sources , Sinks ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) ; for ( auto * V : Sources ) V -> dump ( ) ; for ( auto * I : NewInsts ) I -> dump ( ) ; for ( auto * V : Visited ) { if ( ! Sources . count ( V ) ) V -> dump ( ) ;


<s> i = __builtin_spe_mfspefscr ( ) ; i &= ~ __SPEFSCR_FRMC ; i |= rnd ; __builtin_spe_mtspefscr ( i ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _xbegin ( void ) { return __builtin_ia32_xbegin ( ) ;


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ;


<s> static void emitShadowCallStackEpilogue ( const TargetInstrInfo & TII , MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ;


<s> static bool isZeroExtended ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N ) ) return true ; if ( isExtendedBUILD_VECTOR ( N , DAG , false ) ) return true ; return false ;


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: AllVRegsAllocated ) ;


<s> CCAssignFn * <ISA_LIT>FastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { return CC_<ISA_LIT>O32 ;


<s> IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } for ( Module :: named_metadata_iterator I = M . named_metadata_begin ( ) , E = M . named_metadata_end ( ) ;


<s> const SCEV * LoopCost :: getLoopCostInSCEV ( DominatorTree & DT ) { const SCEV * first = SE . getConstant ( ConstantInt :: get ( Type :: getInt32Ty ( LoopHead -> getBasicBlock ( ) -> getContext ( ) ) , <NUM_LIT> ) ) ; if ( NodeCircle . size ( ) > <NUM_LIT> ) { for ( auto Node = NodeCircle . begin ( ) ; Node != NodeCircle . end ( ) ; Node ++ ) { if ( ! ( * Node ) -> getTaken ( ) ) { if ( ! isDominator ( ( * Node ) -> getSCEVValue ( ) , first , DT ) ) return nullptr ; first = SE . getAddExpr ( first , ( * Node ) -> getSCEVValue ( ) ) ; const SCEV * zero = SE . getConstant ( ConstantInt :: get ( Type :: getInt32Ty ( LoopHead -> getBasicBlock ( ) -> getContext ( ) ) , <NUM_LIT> ) ) ; ( * Node ) -> setSCEVValue ( zero ) ; ( * Node ) -> setTaken ( true ) ; } }


return TargetTriple . getOS ( ) == Triple :: AMDHSA ;


<s> return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_BlockAddress : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ConstantPoolIndex :


<s> bool <ISA_LIT>AsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int Lower , int Upper , Twine Msg = <STR_LIT> ) { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ;

return Error ( ErrorLoc , Msg + <STR_LIT> + Twine ( Lower ) + <STR_LIT> + Twine ( Upper ) + <STR_LIT> ) ;


<s> break ; } switch ( fcode ) { case SPE_BUILTIN_EVSPLATFI : return rs6000_expand_unop_builtin ( CODE_FOR_spe_evsplatfi , arglist , target ) ; case SPE_BUILTIN_EVSPLATI : return rs6000_expand_unop_builtin ( CODE_FOR_spe_evsplati , arglist , target ) ; default : break ; } d = ( struct builtin_description * ) bdesc_2arg_spe ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_2arg_spe ) ; ++ i , ++ d ) if ( d -> code == fcode ) return rs6000_expand_binop_builtin ( d -> icode , arglist , target ) ; d = ( struct builtin_description * ) bdesc_spe_predicates ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_spe_predicates ) ; ++ i , ++ d ) if ( d -> code == fcode ) return spe_expand_predicate_builtin ( d -> icode , arglist , target ) ; d = ( struct builtin_description * ) bdesc_spe_evsel ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_spe_evsel ) ; ++ i , ++ d ) if ( d -> code == fcode ) return spe_expand_evsel_builtin ( d -> icode , arglist , target ) ; switch ( fcode ) { case SPE_BUILTIN_EVSTDDX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstddx , arglist ) ; case SPE_BUILTIN_EVSTDHX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstdhx , arglist ) ; case SPE_BUILTIN_EVSTDWX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstdwx , arglist ) ; case SPE_BUILTIN_EVSTWHEX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwhex , arglist ) ; case SPE_BUILTIN_EVSTWHOX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwhox , arglist ) ; case SPE_BUILTIN_EVSTWWEX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwwex , arglist ) ; case SPE_BUILTIN_EVSTWWOX : return spe_expand_stv_builtin ( CODE_FOR_spe_evstwwox , arglist ) ;


<s> bool isSource ( MachineBasicBlock & MBB ) const {

return ReachableMap . find ( & MBB ) -> second ;


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; bool Changed = false ; SmallVector < int , <NUM_LIT> > MaskVec ; SVOp -> getMask ( MaskVec ) ;

for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) {


<s> Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> :

ReplaceCMP_SWAP_64Results ( N , Results , DAG ) ;


<s> RegInfoRecord = new <ISA_LIT>RegInfoRecord ( this , Context ) ; <ISA_LIT>OptionRecords . push_back ( std :: unique_ptr < <ISA_LIT>RegInfoRecord > ( RegInfoRecord ) ) ;


<s> for ( SmallVectorImpl < unsigned > :: iterator I = Defs . begin ( ) , E = Defs . end ( ) ; I != E ; ++ I ) { SmallVector < MachineInstr * , <NUM_LIT> > DefSrcs ; if ( ! Register :: isVirtualRegister ( * I ) ) continue ; MachineInstr * Def = MRI -> getVRegDef ( * I ) ; if ( ! Def ) continue ; elideCopiesAndPHIs ( Def , DefSrcs ) ; for ( MachineInstr * MI : DefSrcs ) { if ( Replacements . find ( MI ) != Replacements . end ( ) ) continue ; if ( ! hasPartialWrite ( MI ) ) continue ; SmallVector < MachineOperand * , <NUM_LIT> > Uses ; Register DPRDefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( DPRDefReg ) , E = MRI -> use_end ( ) ; I != E ; ++ I ) Uses . push_back ( & * I ) ; unsigned NewReg = optimizeSDPattern ( MI ) ; if ( NewReg != <NUM_LIT> ) { Modified = true ; for ( SmallVectorImpl < MachineOperand * > :: const_iterator I = Uses . begin ( ) , E = Uses . end ( ) ; I != E ; ++ I ) { MRI -> constrainRegClass ( NewReg , MRI -> getRegClass ( ( * I ) -> getReg ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> << printReg ( NewReg ) << <STR_LIT> ) ; ( * I ) -> substVirtReg ( NewReg , <NUM_LIT> , * TRI ) ; } }


<s> xpattern = gen_rtx_SET ( VOIDmode , xop [ <NUM_LIT> ] , xsrc ) ; op [ <NUM_LIT> ] = xop [ <NUM_LIT> ] ; op [ <NUM_LIT> ] = xop [ <NUM_LIT> ] ; op [ <NUM_LIT> ] = xadd ; avr_out_plus ( xpattern , op , plen_add , NULL , false ) ; avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , NULL , plen_add , <NUM_LIT> ) ; rtx xreg = simplify_gen_subreg ( imode , xop [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; rtx xmask = immed_wide_int_const ( - wi_add - wi_add , imode ) ; xpattern = gen_rtx_SET ( VOIDmode , xreg , gen_rtx_AND ( imode , xreg , xmask ) ) ; op [ <NUM_LIT> ] = xreg ; op [ <NUM_LIT> ] = xreg ; op [ <NUM_LIT> ] = xmask ; op [ <NUM_LIT> ] = gen_rtx_SCRATCH ( QImode ) ; avr_out_bitop ( xpattern , op , plen_and ) ; avr_asm_len ( <STR_LIT> , NULL , plen , <NUM_LIT> ) ;

if ( plen ) * plen = len_add + len_and ;


<s> return new <ISA_LIT>Disassembler ( STI , Ctx , true ) ;


<s> gcc_assert ( cycles < <NUM_LIT> ) ; insn = emit_insn_after ( gen_nop_count ( GEN_INT ( cycles ) ) , after ) ;


<s> CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; HexadecimalPrefix = <STR_LIT> ; UseIntegratedAssembler = false ; AsciiDirective = nullptr ; AscizDirective = nullptr ; MaxInstLength = <NUM_LIT> ; ZeroDirective = nullptr ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; GlobalDirective = <STR_LIT> ; HasDotTypeDotSizeDirective = false ; HasSingleParameterDotFile = false ;


<s> fprintf ( stream , <STR_LIT> , ( int ) ( value & <NUM_LIT> ) ) ; return ; } value >>= <NUM_LIT> ; } fprintf ( stream , <STR_LIT> ) ;


<s> static bool ix86_vector_duplicate_value ( machine_mode mode , rtx target , rtx val ) { bool ok ; rtx_insn * insn ; rtx dup ; recog_data_d recog_data_save = recog_data ; dup = gen_vec_duplicate ( mode , val ) ; insn = emit_insn ( gen_rtx_SET ( target , dup ) ) ; if ( recog_memoized ( insn ) < <NUM_LIT> ) { rtx_insn * seq ; machine_mode innermode = GET_MODE_INNER ( mode ) ; rtx reg ; start_sequence ( ) ; reg = force_reg ( innermode , val ) ; if ( GET_MODE ( reg ) != innermode ) reg = gen_lowpart ( innermode , reg ) ; SET_SRC ( PATTERN ( insn ) ) = gen_vec_duplicate ( mode , reg ) ; seq = get_insns ( ) ; end_sequence ( ) ; if ( seq ) emit_insn_before ( seq , insn ) ; ok = recog_memoized ( insn ) >= <NUM_LIT> ; gcc_assert ( ok ) ; } recog_data = recog_data_save ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> inline vector unsigned int vec_vrlw ( vector unsigned int a1 , vector unsigned int a2 ) { return ( vector unsigned int ) __builtin_altivec_vrlw ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> if ( Info -> getMode ( ) . DX10Clamp ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( <NUM_LIT> ) , SNaN , Depth + <NUM_LIT> ) ;


<s> int Scale = AM . Scale ; if ( Scale < <NUM_LIT> ) Scale = - Scale ; switch ( Scale ) { case <NUM_LIT> : break ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = <NUM_LIT> ; SelectionDAGISel :: runOnMachineFunction ( MF ) ;

if ( ! <ISA_LIT>SubTarget . isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ;


<s> <ISA_LIT>64elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) :

<ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM , OL , true ) {


<s> assert ( ( RC == & <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) && <STR_LIT> ) ; if ( RC == & <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && is<ISA_LIT>LowRegister ( SrcReg ) ) ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ;

MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


<s> MRI . addLiveIn ( FlatScratchInitReg ) ; MBB . addLiveIn ( FlatScratchInitReg ) ; Register FlatScrInitLo = TRI -> getSubReg ( FlatScratchInitReg , <STR_LIT> ) ; Register FlatScrInitHi = TRI -> getSubReg ( FlatScratchInitReg , <STR_LIT> ) ; if ( ST . flatScratchIsPointer ( ) ) { if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitLo ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitHi ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FlatScrInitLo ) . addImm ( int16_t ( <STR_LIT> :: ID_FLAT_SCR_LO | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FlatScrInitHi ) . addImm ( int16_t ( <STR_LIT> :: ID_FLAT_SCR_HI | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ) ) ; return ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; return ; } assert ( ST . getGeneration ( ) < <ISA_LIT>Subtarget :: GFX9 ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitHi , RegState :: Kill ) ;


<s> IsQRegs = false ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = false ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { SubRegs = <NUM_LIT> ; IsQRegs = true ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned BeginIdx = IsQRegs ? <STR_LIT> : <STR_LIT> ; int Spacing = <NUM_LIT> ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( SubRegs - <NUM_LIT> ) ; Spacing = - <NUM_LIT> ; } unsigned Opc = IsQRegs ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing ) ; unsigned Src = TRI -> getSubReg ( SrcReg , BeginIdx + i * Spacing ) ; assert ( Dst && Src && <STR_LIT> ) ;

BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , Dst ) . addReg ( Src ) . addReg ( Src ) ;


<s> number_of_regs_before_varargs = * args_so_far ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) number_of_regs_before_varargs += mcore_num_arg_regs ( arg . mode , arg . type ) ; number_of_regs_before_varargs = * args_so_far ;


<s> unsigned Reg = MI . getOperand ( RegIdx ) . getReg ( ) ; assert ( ARC -> contains ( Reg ) != ORC -> contains ( Reg ) && <STR_LIT> ) ; MI . setDesc ( get ( ARC -> contains ( Reg ) ? AOpc : OOpc ) ) ;


<s> void emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const override {


<s> void <ISA_LIT>AnnotateControlFlow :: push ( BasicBlock * BB , Value * Saved ) { Stack . push_back ( std :: make_pair ( BB , Saved ) ) ;


<s> SDValue Base = N -> getOperand ( BaseOpIdx ) ; if ( ! Base . isMachineOpcode ( ) || Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; SDValue ImmOperand = Base . getOperand ( <NUM_LIT> ) ; uint64_t Offset2 = N -> getConstantOperandVal ( OffsetOpIdx ) ; if ( auto * Const = dyn_cast < ConstantSDNode > ( ImmOperand ) ) { int64_t Offset1 = Const -> getSExtValue ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; if ( ! isInt < <NUM_LIT> > ( CombinedOffset ) ) continue ; ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ; } else if ( auto * GA = dyn_cast < GlobalAddressSDNode > ( ImmOperand ) ) { const DataLayout & DL = CurDAG -> getDataLayout ( ) ; Align Alignment = GA -> getGlobal ( ) -> getPointerAlignment ( DL ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = GA -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ; ImmOperand = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) , CombinedOffset , GA -> getTargetFlags ( ) ) ; } else if ( auto * CP = dyn_cast < ConstantPoolSDNode > ( ImmOperand ) ) { Align Alignment = CP -> getAlign ( ) ; if ( Offset2 != <NUM_LIT> && Alignment <= Offset2 ) continue ; int64_t Offset1 = CP -> getOffset ( ) ; int64_t CombinedOffset = Offset1 + Offset2 ;

ImmOperand = CurDAG -> getTargetConstantPool ( CP -> getConstVal ( ) , ImmOperand . getValueType ( ) , CP -> getAlign ( ) , CombinedOffset , CP -> getTargetFlags ( ) ) ;


<s> MVT VT = SVOp -> getSimpleValueType ( <NUM_LIT> ) ; SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( SVOp ) ; SmallVector < int , <NUM_LIT> > MaskVals ( SVOp -> getMask ( ) . begin ( ) , SVOp -> getMask ( ) . end ( ) ) ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ;

bool V1IsAllZero = <STR_LIT> ( V1 . getNode ( ) ) ;


<s> const SDValue Dividend = Op -> getOperand ( <NUM_LIT> ) ; const SDValue Divisor = Op -> getOperand ( <NUM_LIT> ) ; SDValue Div = DAG . getNode ( DivOpcode , dl , VT , Dividend , Divisor ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , dl , VT , Div , Divisor ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , dl , VT , Dividend , Mul ) ; SDValue Values [ <NUM_LIT> ] = { Div , Rem } ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , Values ) ; } RTLIB :: Libcall LC = getDivRemLibcall ( Op . getNode ( ) , VT . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) , Subtarget ) ; SDValue Callee = DAG . getExternalFunctionSymbol ( getLibcallName ( LC ) ) ; Type * RetTy = StructType :: get ( Ty , Ty ) ; if ( Subtarget -> isTargetWindows ( ) ) InChain = WinDBZCheckDenominator ( DAG , Op . getNode ( ) , InChain ) ;

TargetLowering :: CallLoweringInfo CLI ( DAG ) ;


<s> <ISA_LIT>IncomingValueHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI ) : <ISA_LIT>Handler ( MIRBuilder , MRI ) {


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && N -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ( UnitSize == <NUM_LIT> || UnitSize == <NUM_LIT> || UnitSize == <NUM_LIT> ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> / UnitSize ; ++ i ) for ( unsigned j = <NUM_LIT> ; j != UnitSize ; ++ j ) { if ( ! isConstantOrUndef ( N -> getOperand ( i * UnitSize * <NUM_LIT> + j ) , LHSStart + j + i * UnitSize ) || ! isConstantOrUndef ( N -> getOperand ( i * UnitSize * <NUM_LIT> + UnitSize + j ) , RHSStart + j + i * UnitSize ) ) return false ; } return true ;


if ( N . getKind ( ) != msgpack :: Type :: UInt ) return <NUM_LIT> ;


<s> } if ( auto * PHI = dyn_cast < PHINode > ( V ) ) { IRBuilder < > Builder ( PHI ) ; unsigned NIncome = PHI -> getNumOperands ( ) ; ++ NumTransformed ; PHINode * NewPhi = Builder . CreatePHI ( DType , NIncome ) ; for ( unsigned I = <NUM_LIT> ; I != NIncome ; ++ I ) { Value * Op = PHI -> getIncomingValue ( I ) ; Value * NewOp = replace ( Op , DType ) ; NewPhi -> addIncoming ( NewOp , PHI -> getIncomingBlock ( I ) ) ; } return NewPhi ; } if ( auto * EEI = dyn_cast < ExtractElementInst > ( V ) ) { Value * Src = EEI -> getOperand ( <NUM_LIT> ) ; ConstantInt * Ndx = cast < ConstantInt > ( EEI -> getOperand ( <NUM_LIT> ) ) ; auto SVT = cast < VectorType > ( Src -> getType ( ) ) ; unsigned Factor = SVT -> getBitWidth ( ) / DType -> getBitWidth ( ) ; unsigned NewVSize = Factor * DType -> getNumElements ( ) ; auto * NewDVT = VectorType :: get ( DType -> getVectorElementType ( ) , NewVSize ) ; Value * NewSrc = replace ( Src , NewDVT ) ; IRBuilder < > Builder ( EEI ) ; SmallVector < unsigned , <NUM_LIT> > Mask ; unsigned DVSize = DType -> getVectorNumElements ( ) ; Mask . reserve ( DVSize ) ;

unsigned Offset = Ndx -> getLimitedValue ( ) * DVSize ;


<s> void VectorElementize :: createLoadCopy ( MachineFunction & F , MachineInstr * Instr , std :: vector < MachineInstr * > & copies ) { copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; MachineInstr * copy = copies [ <NUM_LIT> ] ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( copy ) ) ) ; MachineOperand dest = copy -> getOperand ( <NUM_LIT> ) ;


<s> error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl , value0 , value1 , value2 , value3 ) ;


<s> runOnMachineBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; LastFiller = MBB . end ( ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) if ( I -> getDesc ( ) . hasDelaySlot ( ) ) { ++ FilledSlots ; Changed = true ; MachineBasicBlock :: iterator D ; if ( EnableDelaySlotFiller && findDelayInstr ( MBB , I , D ) ) { MBB . splice ( llvm :: next ( I ) , & MBB , D ) ; ++ UsefulSlots ; } else BuildMI ( MBB , llvm :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; LastFiller = ++ I ; } return Changed ;


<s> case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxBitcast ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxCttz ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerHvxShift ( Op , DAG ) ; case <STR_LIT> : return LowerHvxMul ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerHvxMulh ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtend ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return Op ; case <STR_LIT> : return LowerHvxIntrinsic ( Op , DAG ) ; case <STR_LIT> : return LowerHvxStore ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; } Op . dumpr ( & DAG ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> rtx pushm ; if ( reg_mask ) { XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( GET_MODE ( stack_pointer_rtx ) , stack_pointer_rtx , GEN_INT ( - byte_count ) ) ) ; F ( XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < n_dwarfs ; i ++ ) XVECEXP ( note , <NUM_LIT> , i + <NUM_LIT> ) = dwarf_set [ i ] ; pushm = F ( emit_insn ( gen_pushm ( GEN_INT ( reg_mask ) ) ) ) ; REG_NOTES ( pushm ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , note , REG_NOTES ( pushm ) ) ; } if ( cfun -> machine -> is_interrupt ) for ( i = MEM0_REGNO ; i <= MEM7_REGNO ; i ++ ) if ( cfun -> machine -> intr_pushmem [ i - MEM0_REGNO ] ) { if ( TARGET_A16 ) pushm = emit_insn ( gen_pushhi_16 ( gen_rtx_REG ( HImode , i ) ) ) ; else pushm = emit_insn ( gen_pushhi_24 ( gen_rtx_REG ( HImode , i ) ) ) ; F ( pushm ) ; } } if ( ppt == PP_popm && byte_count ) { if ( cfun -> machine -> is_interrupt ) for ( i = MEM7_REGNO ; i >= MEM0_REGNO ; i -- ) if ( cfun -> machine -> intr_pushmem [ i - MEM0_REGNO ] ) { if ( TARGET_A16 ) emit_insn ( gen_pophi_16 ( gen_rtx_REG ( HImode , i ) ) ) ; else emit_insn ( gen_pophi_24 ( gen_rtx_REG ( HImode , i ) ) ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> -> hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> -> hasSubClassEq ( RC ) ) {


<s> const unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; assert ( DstRB . getID ( ) == SrcRB . getID ( ) && <STR_LIT> ) ; assert ( DstTy . getSizeInBits ( ) > SrcTy . getSizeInBits ( ) && <STR_LIT> ) ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstRB ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcRB ) ; if ( canTurnIntoCOPY ( SrcRC , DstRC ) ) return selectTurnIntoCOPY ( I , MRI , SrcReg , SrcRC , DstReg , DstRC ) ; if ( DstRB . getID ( ) != <STR_LIT> ) return false ;

if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) {


<s> const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) { return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : Register ( ) ; }

return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : FuncInfo -> getStackPtrOffsetReg ( ) ;


<s> lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; new_optimize = build_optimization_node ( & func_options ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) {

DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ;


<s> CCValAssign & VA = ArgLocs [ i ] ; MVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; InVals . push_back ( ArgValue ) ; }


<s> virtual void emitARM64WinCFIPrologEnd ( ) {


return ( unsigned short ) __builtin_ia32_vec_ext_v4hi ( ( __v4hi ) __A , __N ) ;


<s> tree high = ub ? build_zero_cst ( pointer_sized_int_node ) : build_minus_one_cst ( pointer_sized_int_node ) ; gcc_assert ( ( lb == <NUM_LIT> && ub == - <NUM_LIT> ) || ( lb == - <NUM_LIT> && ub == <NUM_LIT> ) ) ;

return build_complex ( NULL , low , high ) ;


<s> uint32_t getPostIdxRegOpValue ( const MachineInstr & MI , unsigned OpIdx ) const { return <NUM_LIT> ;


<s>
if
(
!
full
)
return
;
dbgs
(
)
<<
<STR_LIT>
<<
HighLatencyBlock
<<
'\n'
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
<ISA_LIT>ScheduleBlock
*
P
:
Preds
)
{
P
->
printDebug
(
false
)
;
}
dbgs
(
)
<<
<STR_LIT>
;
for
(
std
::
pair
<
<ISA_LIT>ScheduleBlock
*
,
<ISA_LIT>ScheduleBlockLinkKind
>
S
:
Succs
)
{
if
(
S
.
second
==
<STR_LIT>
)
dbgs
(
)
<<
<STR_LIT>
;
S
.
first
->
printDebug
(
false
)
;
}
if
(
Scheduled
)
{
dbgs
(
)
<<
<STR_LIT>
<<
LiveInPressure
[
<STR_LIT>
::
SReg_32
]
<<
' '
<<
LiveInPressure
[
<STR_LIT>
::
VGPR_32
]
<<
'\n'
;
dbgs
(
)
<<
<STR_LIT>
<<
LiveOutPressure
[
<STR_LIT>
::
SReg_32
]
<<
' '
<<
LiveOutPressure
[
<STR_LIT>
::
VGPR_32
]
<<
<STR_LIT>
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
LiveInRegs
)
dbgs
(
)
<<
printVRegOrUnit
(
Reg
,
DAG
->
getTRI
(
)
)
<<
' '
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
LiveOutRegs
)
dbgs
(
)
<<
printVRegOrUnit
(
Reg
,
DAG
->
getTRI
(
)
)
<<
' '
;


<s> return ( uint8x8_t ) __builtin_neon_vqmovunv8hi ( __a ) ;


<s> return decodeRegisterClass ( Inst , RegNo , VSRegs ) ;


<s> if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ;


<s> unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { APInt Zeros , Ones ; DAG . computeKnownBits ( Op0 , Zeros , Ones ) ; if ( Zeros . countLeadingOnes ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } if ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS ; RHS = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , LHS . getValueType ( ) ) ; } } if ( LHS . getNode ( ) ) { if ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; if ( LHS . getValueType ( ) != RHS . getValueType ( ) ) RHS = DAG . getNode ( <STR_LIT> , dl , LHS . getValueType ( ) , RHS ) ; SDValue BT = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; <STR_LIT> Cond = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Cond , <STR_LIT> ) , BT ) ; }


<s> Value <<= Info . TargetOffset ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; uint32_t Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset + i ] |= static_cast < uint8_t > ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> gen_shift = gen_lshrv2si3 ; break ; case E_V8HImode : if ( ! TARGET_SSE4_1 ) return false ; c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V4SImode ; gen_and = gen_andv4si3 ; gen_pack = gen_sse4_1_packusdw ; gen_shift = gen_lshrv4si3 ; break ; case E_V8QImode : c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V4HImode ; gen_and = gen_andv4hi3 ; gen_pack = gen_mmx_packuswb ; gen_shift = gen_lshrv4hi3 ; break ; case E_V16QImode : c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V8HImode ; gen_and = gen_andv8hi3 ; gen_pack = gen_sse2_packuswb ; gen_shift = gen_lshrv8hi3 ; break ; case E_V16HImode : if ( ! TARGET_AVX2 ) return false ; c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V8SImode ; gen_and = gen_andv8si3 ; gen_pack = gen_avx2_packusdw ; gen_shift = gen_lshrv8si3 ; end_perm = true ; break ; case E_V32QImode : if ( ! TARGET_AVX2 ) return false ; c = <NUM_LIT> ; s = <NUM_LIT> ; half_mode = V16HImode ; gen_and = gen_andv16hi3 ; gen_pack = gen_avx2_packuswb ; gen_shift = gen_lshrv16hi3 ; end_perm = true ; break ; default : return false ; } odd = d -> perm [ <NUM_LIT> ] ; if ( odd > <NUM_LIT> ) return false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != <NUM_LIT> * i + odd ) return false ; if ( d -> testing_p ) return true ; dop0 = gen_reg_rtx ( half_mode ) ; dop1 = gen_reg_rtx ( half_mode ) ; if ( odd == <NUM_LIT> ) { t = gen_const_vec_duplicate ( half_mode , GEN_INT ( c ) ) ; t = force_reg ( half_mode , t ) ; emit_insn ( gen_and ( dop0 , t , gen_lowpart ( half_mode , d -> op0 ) ) ) ; emit_insn ( gen_and ( dop1 , t , gen_lowpart ( half_mode , d -> op1 ) ) ) ; } else { emit_insn ( gen_shift ( dop0 , gen_lowpart ( half_mode , d -> op0 ) , GEN_INT ( s ) ) ) ; emit_insn ( gen_shift ( dop1 , gen_lowpart ( half_mode , d -> op1 ) , GEN_INT ( s ) ) ) ; } if ( TARGET_AVX2 && end_perm ) { op = gen_reg_rtx ( d -> vmode ) ; t = gen_reg_rtx ( V4DImode ) ; emit_insn ( gen_pack ( op , dop0 , dop1 ) ) ;


return ( __m128i ) __builtin_ia32_pbroadcastw128_mask ( ( __v8hi ) __A , ( __v8hi ) _mm_setzero_si128 ( ) , __M ) ;


<s> case AtomicOrdering :: Release : return nullptr ; case AtomicOrdering :: Acquire : case AtomicOrdering :: AcquireRelease : case AtomicOrdering :: SequentiallyConsistent : return makeDMB ( Builder , <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ;


<s> return __builtin_mve_vabdq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a , __b , __p ) ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) {


<s> initialize<ISA_LIT>InlinerPass ( * PassRegistry :: getPassRegistry ( ) ) ;


return lowerVectorShuffleAsSplitOrBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; default : dbgs ( ) << <STR_LIT> << reg << <STR_LIT> ;


<s> bool <ISA_LIT>RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const <ISA_LIT>FrameLowering * AFI = static_cast < const <ISA_LIT>FrameLowering * > ( TFI ) ; return AFI -> useFPForAddressing ( MF ) ;


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const <ISA_LIT>Subtarget * STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ;


<s> AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; bool Changed = false ; for ( auto & B : MFn ) Changed |= processBasicBlock ( B ) ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( <ISA_LIT>AsmPrinter & asmprinter ) : Printer ( asmprinter ) {


<s> MCSection * <ISA_LIT>ELFTargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { if ( Kind . isBSS ( ) && isGlobalInSmallSection ( GO , TM ) ) return SmallBSSSection ; if ( Kind . isData ( ) && isGlobalInSmallSection ( GO , TM ) ) return SmallDataSection ;

return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM ) ;


<s> if ( Add . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Lo = Add . getOperand ( <NUM_LIT> ) ; if ( ( Lo . getOpcode ( ) != <STR_LIT> ) || ( Lo . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Target & T , const StringRef & TT ) { PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ;


<s> static bool csky_class_likely_spilled_p ( reg_class_t rclass ) {

if ( ( TARGET_MINI_REGISTERS && rclass == MINI_REGS ) || rclass == C_REGS ) return true ;


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; PSetIterator PSetI = MRI . getPressureSets ( Reg ) ; for ( ; PSetI . isValid ( ) ; ++ PSetI ) {

if ( * PSetI == VGPRSetID ) VgprUsage += PSetI . getWeight ( ) ;


<s> case AMDGPU :: S_LOAD_DWORDX4_IMM : case AMDGPU :: S_LOAD_DWORDX4_SGPR : { if ( NewOpcode == N -> getMachineOpcode ( ) ) { NewOpcode = AMDGPU :: BUFFER_LOAD_DWORDX4_ADDR64 ; } if ( fitsRegClass ( DAG , N -> getOperand ( <NUM_LIT> ) , AMDGPU :: SReg_64RegClassID ) ) { return N ; } ConstantSDNode * Offset = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ;


<s> static DecodeStatus DecodeBranchTarget ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = ( SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ) + <NUM_LIT> ;

Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ; SDValue ZeroVal = DAG . getConstant ( <NUM_LIT> , dl , Mask . getValueType ( ) ) ; Ops [ <NUM_LIT> ] = Mask ; for ( unsigned i = <NUM_LIT> ; i != NumConcat ; ++ i ) Ops [ i ] = ZeroVal ; NewMask = DAG . getNode ( <STR_LIT> , dl , NewMaskVT , Ops ) ;


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_PCRel_1 : case FK_SecRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_SecRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_SecRel_4 :


<s> getParser ( ) . getStreamer ( ) . SwitchSection ( <STR_LIT> ( getContext ( ) ) ) ; return false ;


<s> static void mips_adjust_block_mem ( rtx mem , HOST_WIDE_INT length , rtx * loop_reg , rtx * loop_mem ) {

* loop_reg = copy_addr_to_reg ( XEXP ( mem , <NUM_LIT> ) ) ;


<s> if ( const auto * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ; if ( isa < UndefValue > ( C ) ) { unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : break ; case <STR_LIT> : if ( ! <ISA_LIT>ScalarSSEf32 ) Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ! <ISA_LIT>ScalarSSEf64 ) Opc = <STR_LIT> ; break ; case <STR_LIT> :


<s> Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) / <NUM_LIT> ) ) ;


<s> return decodeRegisterClass ( Inst , RegNo , RRegs ) ;


<s> static bool rs6000_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case rsqrt_optab : return ( opt_type == OPTIMIZE_FOR_SPEED && RS6000_RECIP_AUTO_RSQRTE_P ( mode1 ) ) ;


<s> CMPTermIdx_match ( Register & LHS , MachineOperand & Addr , Register & Idx , Register & Flag , MachineInstr * & Load , AAResults * AA ) : Cmp_match ( LHS , Flag ) , Addr ( Addr ) , Idx ( Idx ) , Load ( Load ) , AA ( AA ) {


<s> if ( RHSSignBits < <NUM_LIT> ) return nullptr ; unsigned SignBits = std :: min ( LHSSignBits , RHSSignBits ) ; unsigned DivBits = <NUM_LIT> - SignBits ; if ( IsSigned ) ++ DivBits ; Type * Ty = Num -> getType ( ) ; Type * I32Ty = Builder . getInt32Ty ( ) ; Type * F32Ty = Builder . getFloatTy ( ) ; ConstantInt * One = Builder . getInt32 ( <NUM_LIT> ) ; Value * JQ = One ; if ( IsSigned ) { JQ = Builder . CreateXor ( Num , Den ) ; JQ = Builder . CreateAShr ( JQ , Builder . getInt32 ( <NUM_LIT> ) ) ; JQ = Builder . CreateOr ( JQ , One ) ; } Value * IA = Num ; Value * IB = Den ; Value * FA = IsSigned ? Builder . Create<ISA_LIT>ToFP ( IA , F32Ty ) : Builder . CreateUIToFP ( IA , F32Ty ) ; Value * FB = IsSigned ? Builder . Create<ISA_LIT>ToFP ( IB , F32Ty ) : Builder . CreateUIToFP ( IB , F32Ty ) ; Value * RCP = Builder . CreateFDiv ( ConstantFP :: get ( F32Ty , <NUM_LIT> ) , FB ) ; Value * FQM = Builder . CreateFMul ( FA , RCP ) ; CallInst * FQ = Builder . CreateUnaryIntrinsic ( <STR_LIT> , FQM ) ; FQ -> copyFastMathFlags ( Builder . getFastMathFlags ( ) ) ; Value * FQNeg = Builder . CreateFNeg ( FQ ) ; Value * FR = Builder . CreateIntrinsic ( <STR_LIT> , { FQNeg -> getType ( ) } , { FQNeg , FB , FA } , FQ ) ; Value * IQ = IsSigned ? Builder . CreateFPTo<ISA_LIT> ( FQ , I32Ty ) : Builder . CreateFPToUI ( FQ , I32Ty ) ; FR = Builder . CreateUnaryIntrinsic ( <STR_LIT> , FR , FQ ) ; FB = Builder . CreateUnaryIntrinsic ( <STR_LIT> , FB , FQ ) ;

Value * CV = Builder . CreateFCmpOGE ( FR , FB ) ;


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ( Subtarget -> isThumb ( ) || Subtarget -> isTargetDarwin ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( DR . R ) ) continue ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SR . R ) ) continue ; if ( MRI -> getRegClass ( DR . R ) != PredRC ) continue ; if ( MRI -> getRegClass ( SR . R ) != PredRC ) continue ; assert ( ! DR . S && ! SR . S && <STR_LIT> ) ;

MRI -> replaceRegWith ( DR . R , SR . R ) ;


<s> return ( int32x2_t ) __builtin_aarch64_addhnv2di ( __a , __b ) ;


<s> static SDValue LowerLabelRef ( SDValue HiPart , SDValue LoPart , bool isPIC , SelectionDAG & DAG ) { EVT PtrVT = HiPart . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ;


<s> if ( ready_index == <NUM_LIT> ) return <NUM_LIT> ; if ( rs6000_cpu_attr != CPU_CELL ) return <NUM_LIT> ;

gcc_assert ( insn != NULL_RTX && INSN_P ( insn ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , & MI -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , & MI -> getOperand ( <NUM_LIT> ) ) ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> Value * <ISA_LIT>IREmitter :: visitLCMPXCHG_DAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> static unsigned sizeExternalSymbolAddress ( bool dword ) {


<s> if ( VT == <STR_LIT> && ! <ISA_LIT>ScalarSSEf64 ) return false ; if ( VT == <STR_LIT> && ! <ISA_LIT>ScalarSSEf32 ) return false ; if ( VT == <STR_LIT> ) return false ;

return ( AllowI1 && VT == <STR_LIT> ) || TLI . isTypeLegal ( VT ) ;


<s> unsigned NumArgs = MI -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { auto & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = TargetRegisterInfo :: isVirtualRegister ( DestReg ) ? MRI . getRegClass ( DestReg ) : MRI . getTargetRegisterInfo ( ) -> getMinimalPhysRegClass ( DestReg ) ; unsigned CopyOpcode ;

if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ;


<s> assert ( ( NumLoads > <NUM_LIT> ) && ( NumBytes > <NUM_LIT> ) && ( NumBytes >= NumLoads ) && <STR_LIT> ) ; unsigned MaxNumLoads ; if ( NumBytes <= <NUM_LIT> * NumLoads ) { MaxNumLoads = <NUM_LIT> ; } else { MaxNumLoads = <NUM_LIT> ;


<s> if ( Op32 == - <NUM_LIT> ) return false ;

return pseudoToMCOpcode ( Op32 ) != - <NUM_LIT> ;


<s> return createELFObjectWriter ( MOTW , OS , false ) ;


<s> return TM . getABIInfo ( ) . getABIType ( ) == <STR_LIT> ;


<s> getTargetStreamer ( ) . emit<ISA_LIT>WinCFISaveLR ( Offset ) ;


<s> assert ( getFlags ( ) & NodeAttrs :: PhiRef ) ; return Ref . PhiU . PredB ;


<s> MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , getUndefRegState ( SrcIsUndef ) ) ;


<s> bool <ISA_LIT>RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return false ;


<s> const bool IsCompute = <STR_LIT> ( CC ) ; <ISA_LIT>ModeRegisterDefaults Mode ; Mode . DX10Clamp = true ; Mode . IEEE = IsCompute ; Mode . FP32Denormals = false ; Mode . FP64FP16Denormals = true ;


<s> unsigned PO = Offset + Size ; const Align PA = std :: max ( PostAlign , Alignment ) ;

if ( PA == Align ( <NUM_LIT> ) ) return PO ;


<s> register int j ; for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( ! legitimate_pic_operand_p ( XVECEXP ( x , i , j ) ) ) return <NUM_LIT> ; } else if ( fmt [ i ] == 'e' && ! legitimate_pic_operand_p ( XEXP ( x , i ) ) ) return <NUM_LIT> ; } return <NUM_LIT> ;


<s> Scale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( & I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) PushPopMIs . push_back ( & I ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I . getNumOperands ( ) ; op != e ; ++ op ) if ( I . getOperand ( op ) . isCPI ( ) || I . getOperand ( op ) . isJTI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; bool IsSoImm = false ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; IsSoImm = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Bits = <NUM_LIT> ; NegOk = true ; break ; case <STR_LIT> : Bits = <NUM_LIT> ;


<s> reg_size = <NUM_LIT> ; } else if ( reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM ) { asm_fprintf ( asm_out_file , <STR_LIT> , reg , nregs ) ; return ; } else abort ( ) ; if ( offset != nregs * reg_size ) abort ( ) ; fprintf ( asm_out_file , <STR_LIT> ) ; offset = <NUM_LIT> ; lastreg = <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= nregs ; i ++ ) { e = XVECEXP ( p , <NUM_LIT> , i ) ; if ( GET_CODE ( e ) != SET || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != MEM || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != REG ) abort ( ) ; reg = REGNO ( XEXP ( e , <NUM_LIT> ) ) ; if ( reg < lastreg ) abort ( ) ;

if ( i != <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> ) ;


<s> if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasF16C = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRDRAND = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasCmpxchg16b = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; <ISA_LIT>_MC :: DetectFamilyModel ( EAX , Family , Model ) ; if ( IsAMD || ( Family == <NUM_LIT> && Model >= <NUM_LIT> ) ) { IsBTMemSlow = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) ) ) { IsUAMemFast = true ; ToggleFeature ( <STR_LIT> ) ; } if ( Family == <NUM_LIT> && ( Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> ) ) { <ISA_LIT>ProcFamily = IntelAtom ; UseLeaForSP = true ; ToggleFeature ( <STR_LIT> ) ; } unsigned MaxExtLevel ; <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & MaxExtLevel , & EBX , & ECX , & EDX ) ; if ( MaxExtLevel >= <NUM_LIT> ) { <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) { Has<ISA_LIT>_64 = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsAMD ) { if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasSSE4A = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasXOP = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasFMA4 = true ; ToggleFeature ( <STR_LIT> ) ; } } } } if ( MaxLevel >= <NUM_LIT> ) { if ( ! <ISA_LIT>_MC :: GetCpuIDAndInfoEx ( <NUM_LIT> , <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ) { if ( IsIntel && ( EBX & <NUM_LIT> ) ) { HasFSGSBase = true ; ToggleFeature ( <STR_LIT> ) ; }


if ( RedZone && AfterCSRPopSize == <NUM_LIT> ) return ;


<s> std :: vector < std :: string > table {


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_ITCondMask ) ; Op -> ITMask . Mask = Mask ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> StringRef getPassName ( ) const override {


<s> unsigned getFramePtrSpillOffset ( ) const {


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( Start , Next ) ; if ( Mnemonic == <STR_LIT> ) Mnemonic = <STR_LIT> ; Operands . push_back ( <STR_LIT> ( Mnemonic , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; }


<s> setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> PtrI = noClobberClones [ Ptr ] ; } else { Function * F = I . getParent ( ) -> getParent ( ) ; Value * Idx = Constant :: getIntegerValue ( Type :: getInt32Ty ( Ptr -> getContext ( ) ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; PtrI = GetElementPtrInst :: Create ( I . getType ( ) , Ptr , ArrayRef < Value * > ( Idx ) , Twine ( <STR_LIT> ) , F -> getEntryBlock ( ) . getFirstNonPHI ( ) ) ; } I . replaceUsesOfWith ( Ptr , PtrI ) ; } } if ( PtrI ) { setUniformMetadata ( PtrI ) ; if ( NotClobbered ) setNoClobberMetadata ( PtrI ) ;


<s> if ( parseRegister ( Operands ) == MatchOperand_Success || parseImmediate ( Operands ) == MatchOperand_Success ) return false ; Error ( getLoc ( ) , <STR_LIT> ) ;


<s> if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ) ; return SDValue ( ) ; } std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> virtual const char * getPassName ( ) const {


<s> std :: pair < SDValue , SDValue > <ISA_LIT>TargetLowering :: splitBufferOffsets ( SDValue Offset , SelectionDAG & DAG ) const { SDLoc DL ( Offset ) ; const unsigned MaxImm = <NUM_LIT> ; SDValue N0 = Offset ; ConstantSDNode * C1 = nullptr ; if ( ( C1 = dyn_cast < ConstantSDNode > ( N0 ) ) ) N0 = SDValue ( ) ; else if ( DAG . isBaseWithConstantOffset ( N0 ) ) { C1 = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; N0 = N0 . getOperand ( <NUM_LIT> ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) {


<s> return ( ( qword ) ( vec_add ( ( vec_int4 ) ( a ) , vec_splat ( ( vec_int4 ) ( si_from_int ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && VT == <STR_LIT> ) return false ; if ( VT == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } }


<s> int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT> && Value <= <NUM_LIT> ;


<s> static bool getTargetShuffleMaskIndices ( SDValue MaskNode , unsigned MaskEltSizeInBits , SmallVectorImpl < uint64_t > & RawMask , APInt & UndefElts ) {

SmallVector < APInt , <NUM_LIT> > EltBits ;


mips_split_plus ( x , & given_base , & given_offset ) ;


<s> return ( vector unsigned int ) __builtin_altivec_vsraw ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> ConstPoolId2AddrMap . resize ( AFI -> getNumPICLabels ( ) ) ; JumpTableId2AddrMap . resize ( AFI -> getNumJumpTables ( ) ) ; IsPIC = isPIC ;


<s> case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case FK_SecRel_4 : case FK_Data_4 : return <NUM_LIT> ; }


<s> case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { Register MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( SrcReg ) ) ; SrcReg = MoveReg ; VT = <STR_LIT> ; StrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ;

if ( Alignment && Alignment < <NUM_LIT> ) return false ;


<s> StringRef getPassName ( ) const override { return <ISA_LIT>_BRANCH_TARGETS_NAME ;


<s> RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; case <STR_LIT> : if ( RxSBG . Opcode != <STR_LIT> ) { unsigned InnerBitSize = N . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; if ( ! refineRxSBGMask ( RxSBG , allOnes ( InnerBitSize ) ) ) return false ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } LLVM_FALLTHROUGH ; case <STR_LIT> : { unsigned BitSize = N . getValueSizeInBits ( ) ; unsigned InnerBitSize = N . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ; if ( maskMatters ( RxSBG , allOnes ( BitSize ) - allOnes ( InnerBitSize ) ) ) { if ( RxSBG . Mask == <NUM_LIT> && RxSBG . Rotate == <NUM_LIT> ) RxSBG . Rotate += ( BitSize - InnerBitSize ) ; else return false ; } RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : { auto * CountNode = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! CountNode ) return false ; uint64_t Count = CountNode -> getZExtValue ( ) ; unsigned BitSize = N . getValueSizeInBits ( ) ; if ( Count < <NUM_LIT> || Count >= BitSize ) return false ; if ( RxSBG . Opcode == <STR_LIT> ) { if ( maskMatters ( RxSBG , allOnes ( Count ) ) ) return false ; } else { if ( ! refineRxSBGMask ( RxSBG , allOnes ( BitSize - Count ) << Count ) ) return false ; } RxSBG . Rotate = ( RxSBG . Rotate + Count ) & <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printMemRrOperand ( const MCInst * MI , int OpNo , raw_ostream & OS , const char * ) { const MCOperand & RegOp = MI -> getOperand ( OpNo ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ;

const MCOperand & AluOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ;


<s> APInt ShAmt = N1C -> getAPIntValue ( ) ; Mask = Mask . shl ( ShAmt ) ; if ( Mask != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N00 , DAG . getConstant ( Mask , VT ) ) ; } } if ( auto * N1BV = dyn_cast < BuildVectorSDNode > ( N1 ) ) if ( auto * N1SplatC = N1BV -> getConstantSplatNode ( ) ) { assert ( N0 . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; if ( N1SplatC -> getZExtValue ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N0 ) ; }


<s> FirstReg = State -> getFirstUnallocated ( IntArgRegs ) ; if ( ( Align > RegSizeInBytes ) && ( FirstReg % <NUM_LIT> ) ) { State -> AllocateReg ( IntArgRegs [ FirstReg ] , ShadowRegs [ FirstReg ] ) ; ++ FirstReg ; } Size = alignTo ( Size , RegSizeInBytes ) ; for ( unsigned I = FirstReg ; Size > <NUM_LIT> && ( I < IntArgRegs . size ( ) ) ; Size -= RegSizeInBytes , ++ I , ++ NumRegs ) State -> AllocateReg ( IntArgRegs [ I ] , ShadowRegs [ I ] ) ; } State -> addInRegsParamInfo ( FirstReg , FirstReg + NumRegs ) ;


<s> fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; } } if ( epiphany_m1reg >= <NUM_LIT> ) { fixed_regs [ epiphany_m1reg ] = <NUM_LIT> ; call_used_regs [ epiphany_m1reg ] = <NUM_LIT> ; } if ( ! TARGET_PREFER_SHORT_INSN_REGS ) CLEAR_HARD_REG_SET ( reg_class_contents [ SHORT_INSN_REGS ] ) ; COPY_HARD_REG_SET ( reg_class_contents [ SIBCALL_REGS ] , reg_class_contents [ GENERAL_REGS ] ) ;

for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! call_used_regs [ i ] ) CLEAR_HARD_REG_BIT ( reg_class_contents [ SIBCALL_REGS ] , i ) ;


<s> if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , <NUM_LIT> ) ; if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - <NUM_LIT> ) ;

return TargetLowering :: getIRStackGuard ( IRB ) ;


<s> if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , getUndefRegState ( SrcIsUndef ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcIsKill && ! SrcIsUndef ) MIB -> addRegisterKilled ( SrcReg , TRI , true ) ; else if ( ! SrcIsUndef ) MIB . addReg ( SrcReg , RegState :: Implicit ) ; TransferImpOps ( MI , MIB , MIB ) ; MIB -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; MI . eraseFromParent ( ) ;


<s> MachineInstr * SetRegister ( MachineInstr * I , unsigned * TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const bool is64Bit = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; const <ISA_LIT>InstrInfo * TII = TM -> getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( is64Bit ? & <STR_LIT> : & <STR_LIT> ) ; MachineInstr * Next = I -> getNextNode ( ) ;

MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , Next , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * TLSBaseAddrReg ) . addReg ( is64Bit ? <STR_LIT> : <STR_LIT> ) ;


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_VS_32 ( unsigned Val ) const { return decodeSrcOp ( OPW32 , Val ) ;