<s> return TRI . getEncodingValue ( LHS . first ) < TRI . getEncodingValue ( RHS . first ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) {

BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . addImm ( - <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> ReturnInst :: Create ( F . getContext ( ) , PN , NewRetBlock ) ; } for ( BasicBlock * BB : ReturningBlocks ) { if ( PN ) PN -> addIncoming ( BB -> getTerminator ( ) -> getOperand ( <NUM_LIT> ) , BB ) ; BB -> getTerminator ( ) -> eraseFromParent ( ) ; BranchInst :: Create ( NewRetBlock , BB ) ;


<s> assert ( Reg . isReg ( ) && <STR_LIT> ) ; assert ( Reg . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( Reg . getReg ( ) ) ; const MachineOperand & Operand1 = MI -> getOperand ( <NUM_LIT> ) ; if ( Operand1 . isImm ( ) || Operand1 . isGlobal ( ) ) break ; assert ( Operand1 . isReg ( ) && <STR_LIT> ) ; assert ( Operand1 . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( Operand1 . getReg ( ) ) ;


<s> if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , AddrDecoder ( Inst , addr , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> size_t i ; for ( i = <NUM_LIT> ; i < count ; ++ i , ++ p ) if ( ( target_flags & p -> target_mask ) == p -> target_mask ) alpha_builtin_function ( p -> name , ftype , p -> code , ( p -> is_const ? ECF_CONST : <NUM_LIT> ) | ECF_NOTHROW ) ;


<s> unsigned b = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( addr ) ) ;

Inst . addOperand ( MCOperand :: createImm ( b ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ;

return ( VT1 . getSizeInBits ( ) > VT2 . getSizeInBits ( ) ) ;


<s> unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { unsigned Base = i + Offset ; if ( Base >= NumLaneElts ) Base += NumElts - NumLaneElts ; ShuffleMask . push_back ( Base + l ) ;


<s> std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS ) ; return Error ( IDLoc , <STR_LIT> + Suggestion , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) {

if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ;


<s> ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> <STR_LIT> :

<STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this ) , JITInfo ( * this ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> if ( TII -> analyzeBranch ( * HBB , TBB , FBB , HeadCond ) ) { continue ; } if ( ! TBB || TBB == HBB ) { continue ; } SmallVector < MachineOperand , <NUM_LIT> > TrueCond ; MachineBasicBlock * TBB_TBB = nullptr , * TBB_FBB = nullptr ; if ( TII -> analyzeBranch ( * TBB , TBB_TBB , TBB_FBB , TrueCond ) ) { continue ; } MachineInstr * HeadCmpMI = findSuitableCompare ( HBB ) ; if ( ! HeadCmpMI ) { continue ; } MachineInstr * TrueCmpMI = findSuitableCompare ( TBB ) ; if ( ! TrueCmpMI ) { continue ; } <STR_LIT> HeadCmp ; if ( HeadCond . empty ( ) || ! parseCond ( HeadCond , HeadCmp ) ) { continue ; } <STR_LIT> TrueCmp ; if ( TrueCond . empty ( ) || ! parseCond ( TrueCond , TrueCmp ) ) { continue ; } const int HeadImm = ( int ) HeadCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int TrueImm = ( int ) TrueCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmp ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << HeadImm << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ; CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp ) ; if ( std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) && std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) ) { modifyCmp ( HeadCmpMI , HeadCmpInfo ) ; modifyCmp ( TrueCmpMI , TrueCmpInfo ) ; Changed = true ; } } else if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) {

bool adjustHeadCond = ( HeadImm < TrueImm ) ;


<s> static void compile_for_target ( struct obstack * argv_obstack ) { switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( argv_obstack , NULL ) ; char * * argv = XOBFINISH ( argv_obstack , char * * ) ; const char * epath = getenv ( <STR_LIT> ) ; const char * cpath = getenv ( <STR_LIT> ) ; const char * lpath = getenv ( <STR_LIT> ) ; const char * rpath = getenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ;


<s> bool isMovImm64Shifter ( ) const { if ( ! isShifter ( ) ) return false ; <STR_LIT> ST = <STR_LIT> ( Shifter . Val ) ; if ( ST != <STR_LIT> ) return false ; uint64_t Val = <STR_LIT> ( Shifter . Val ) ;

return ( Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> ) ;


<s> break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; } bool i32Stack = Op . getValueType ( ) == <STR_LIT> && Subtarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || Subtarget . hasFPCVT ( ) ) ; SDValue FIPtr = DAG . CreateStackTemporary ( i32Stack ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( FIPtr ) -> getIndex ( ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ; SDValue Chain ; unsigned Alignment = DAG . getEVTAlignment ( Tmp . getValueType ( ) ) ; if ( i32Stack ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; Alignment = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , Alignment ) ; SDValue Ops [ ] = { DAG . getEntryNode ( ) , Tmp , FIPtr } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MMO ) ; } else Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Tmp , FIPtr , MPI , Alignment ) ; if ( Op . getValueType ( ) == <STR_LIT> && ! i32Stack ) { FIPtr = DAG . getNode ( <STR_LIT> , dl , FIPtr . getValueType ( ) , FIPtr , DAG . getConstant ( <NUM_LIT> , dl , FIPtr . getValueType ( ) ) ) ; MPI = MPI . getWithOffset ( Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } RLI . Chain = Chain ; RLI . Ptr = FIPtr ; RLI . MPI = MPI ;


<s> if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == <NUM_LIT> ) return <STR_LIT> ; if ( TYPE_NAME ( type ) != NULL ) {


<s> int n_words = AVR_TINY ? <NUM_LIT> : <NUM_LIT> ; return optimize > <NUM_LIT> && io_address_operand ( x , QImode ) ? avr_asm_len ( <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> , op , plen , - n_words ) ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { int disp = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( AVR_TINY ) return avr_out_movqi_r_mr_reg_disp_tiny ( insn , op , plen ) ; if ( disp - GET_MODE_SIZE ( GET_MODE ( src ) ) >= <NUM_LIT> ) { if ( REGNO ( XEXP ( x , <NUM_LIT> ) ) != REG_Y ) fatal_insn ( <STR_LIT> , insn ) ; if ( disp <= <NUM_LIT> + MAX_LD_OFFSET ( GET_MODE ( src ) ) ) return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ;


<s> bool <ISA_LIT>AdjustOpt :: runOnModule ( Module & M ) { return <ISA_LIT>AdjustOptImpl ( & M ) . run ( ) ;


<s> inline static uint64_t mimm2Val ( uint64_t Val ) { if ( Val == <NUM_LIT> ) return <NUM_LIT> ;

if ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) return ( uint64_t ) ( ( <NUM_LIT> << <NUM_LIT> ) >> ( Val & <NUM_LIT> ) ) ;


<s> SMLoc Loc = getLoc ( ) ; StringRef NextKind ; int64_t Reg = tryMatchVectorRegister ( NextKind , true ) ; if ( Reg == - <NUM_LIT> ) return true ; if ( Kind != NextKind ) return Error ( Loc , <STR_LIT> ) ; if ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( Reg ) != ( getContext ( ) . getRegisterInfo ( ) -> getEncodingValue ( PrevReg ) + <NUM_LIT> ) % <NUM_LIT> ) return Error ( Loc , <STR_LIT> ) ; PrevReg = Reg ; ++ Count ; } } if ( Parser . getTok ( ) . is ( AsmToken :: EndOfStatement ) ) Error ( getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; unsigned NumElements = <NUM_LIT> ; char ElementKind = <NUM_LIT> ; if ( ! Kind . empty ( ) ) parseValidVectorKind ( Kind , NumElements , ElementKind ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorList ( FirstReg , Count , NumElements , ElementKind , S , getLoc ( ) , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return false ; } SMLoc E = getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) {


<s> void setVarArgsGPRIndex ( int Index ) {


<s> if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; ProcessorIMod = IMod ; } } if ( Mnemonic . startswith ( <STR_LIT> ) ) { ITMask = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) ) ; Mnemonic = Mnemonic . slice ( <NUM_LIT> , <NUM_LIT> ) ; } return Mnemonic ;


<s> DIExpression :: appendOffset ( Ops , Offset . getFixed ( ) ) ; unsigned VLENB = getDwarfRegNum ( <STR_LIT> , true ) ; int64_t VLENBSized = Offset . getScalable ( ) / <NUM_LIT> ; if ( VLENBSized > <NUM_LIT> ) { Ops . push_back ( dwarf :: DW_OP_constu ) ; Ops . push_back ( VLENBSized ) ; Ops . append ( { dwarf :: DW_OP_bregx , VLENB , <NUM_LIT> } ) ; Ops . push_back ( dwarf :: DW_OP_mul ) ; Ops . push_back ( dwarf :: DW_OP_plus ) ; } else if ( VLENBSized < <NUM_LIT> ) { Ops . push_back ( dwarf :: DW_OP_constu ) ; Ops . push_back ( - VLENBSized ) ; Ops . append ( { dwarf :: DW_OP_bregx , VLENB , <NUM_LIT> } ) ; Ops . push_back ( dwarf :: DW_OP_mul ) ; Ops . push_back ( dwarf :: DW_OP_minus ) ; }


assert ( std :: adjacent_find ( Table . begin ( ) , Table . end ( ) ) == Table . end ( ) && <STR_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : return ( PredReg == <STR_LIT> ) ? fp0_jump_nt : fp1_jump_nt ; case <STR_LIT> : return ( PredReg == <STR_LIT> ) ? fp0_jump_t : fp1_jump_t ; case <STR_LIT> : return ( PredReg == <STR_LIT> ) ? tp0_jump_nt : tp1_jump_nt ;


<s> SDValue ExtsSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( ExtsSrc . getOpcode ( ) == <STR_LIT> && ExtsSrc . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N0 ) ; SDValue ShiftBy = SDValue ( CN1 , <NUM_LIT> ) ;

if ( ShiftBy . getValueType ( ) == <STR_LIT> ) ShiftBy = DCI . DAG . getConstant ( CN1 -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> enum m32r_model model ; rtx sym = gen_rtx_SYMBOL_REF ( Pmode , name ) ; if ( TARGET_MODEL_SMALL ) model = M32R_MODEL_SMALL ; else if ( TARGET_MODEL_MEDIUM ) model = M32R_MODEL_MEDIUM ; else if ( TARGET_MODEL_LARGE ) model = M32R_MODEL_LARGE ;


<s> IRPromoter ( Module * M ) : M ( M ) , Ctx ( M -> getContext ( ) ) , ExtTy ( Type :: getInt32Ty ( Ctx ) ) {


<s> Shift = true ; break ; } EVT VT = Op . getValueType ( ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , VT ) ; if ( Convert ) { SDValue SR = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , <STR_LIT> , Flag ) ; if ( Shift ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; if ( Invert ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; return SR ; } else { SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ;

SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> return ( uint64_t ) __builtin_neon_vget_lanev2di ( ( int64x2_t ) __a , __b ) ;


<s> if ( ! ( Enabled == ReciprocalEstimate :: Enabled || ( Enabled == ReciprocalEstimate :: Unspecified && ! usePrecSqrtF32 ( ) ) ) ) return SDValue ( ) ; if ( ExtraSteps == ReciprocalEstimate :: Unspecified ) ExtraSteps = <NUM_LIT> ; SDLoc DL ( Operand ) ; EVT VT = Operand . getValueType ( ) ; bool Ftz = useF32FTZ ( DAG . getMachineFunction ( ) ) ;

auto MakeIntrinsicCall = [ & ] ( <STR_LIT> IID ) {


<s> Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } RegisterSDNode * LHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; RegisterSDNode * RHSR = dyn_cast < RegisterSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ( LHSR && LHSR -> getReg ( ) == <STR_LIT> ) || ( RHSR && RHSR -> getReg ( ) == <STR_LIT> ) ) { Base = N ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( ( RHSC & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> ) { RHSC /= Scale ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ;


<s> if ( code >= AARCH64_BUILTIN_MAX ) return error_mark_node ; return aarch64_builtin_decls [ code ] ;


<s> Reg = <STR_LIT> ; break ; } MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Opc ) ) ; MIB -> findRegisterUseOperand ( Reg ) -> setIsUndef ( ) ; if ( Reg == <STR_LIT> ) { MIB . addReg ( Reg , RegState :: Undef ) ;


<s> return ( std :: max ) ( Lead [ <NUM_LIT> ] , Lead [ <NUM_LIT> ] ) ;


<s> if ( dest ) pattern = gen_maddsi3r ( lo , dest , copy_rtx ( dest ) , mep_mulr_source ( insn , dest , src1 , src2 ) , copy_rtx ( lo ) ) ; else pattern = gen_maddsi3_lo ( lo , src1 , src2 , copy_rtx ( lo ) ) ;


<s> for ( MachineInstr & MI : llvm :: make_range ( MachineBasicBlock :: iterator ( SCCDefInst ) , SCCDefInst . getParent ( ) -> end ( ) ) ) { if ( MI . findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ) return ; if ( MI . findRegisterUseOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ) Worklist . insert ( & MI ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase * PassManager ) : TargetPassConfig ( TM , * PassManager ) {


<s> Function * F = getParentFunction ( v ) ; if ( ! F ) return ;

for ( Function :: iterator it = F -> begin ( ) , ie = F -> end ( ) ; it != ie ; ++ it ) {


<s> MDR = & getAnalysis < MemoryDependenceWrapperPass > ( ) . getMemDep ( ) ;

LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ;


<s> std :: string ToYamlString ; if ( Metadata :: toYamlString ( FromYamlString , ToYamlString ) ) { errs ( ) << <STR_LIT> ; return ; } errs ( ) << ( YamlString == ToYamlString ? <STR_LIT> : <STR_LIT> ) << '\n' ; if ( YamlString != ToYamlString ) {

errs ( ) << <STR_LIT> << YamlString << '\n' << <STR_LIT> << ToYamlString << '\n' ;


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> LCC = cast < CondCodeSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; <STR_LIT> RCC = cast < CondCodeSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue X = LHS . getOperand ( <NUM_LIT> ) ; SDValue Y = RHS . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) != <STR_LIT> || Y . getOperand ( <NUM_LIT> ) != X ) return SDValue ( ) ; if ( LCC == <STR_LIT> ) { if ( X != LHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; if ( RCC == <STR_LIT> ) { const ConstantFPSDNode * C1 = dyn_cast < ConstantFPSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C1 || ! C1 -> isInfinity ( ) || C1 -> isNegative ( ) ) return SDValue ( ) ; const uint32_t Mask = <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ;

static_assert ( ( ( ~ ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) & <NUM_LIT> ) == Mask , <STR_LIT> ) ;


<s> if ( RM == Reloc :: Static ) return true ;

return GV -> hasLocalLinkage ( ) || ! GV -> hasDefaultVisibility ( ) ;


<s> if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) return true ; if ( selectImpl ( I , * CoverageInfo ) ) return true ; return false ;


<s> offset = const0_rtx ; base = eliminate_constant_term ( XEXP ( SET_SRC ( set ) , <NUM_LIT> ) , & offset ) ; off = INTVAL ( offset ) ; if ( GET_CODE ( base ) != REG || off < <NUM_LIT> ) continue ; if ( cfun_frame_layout . first_restore_gpr != - <NUM_LIT> && ( cfun_frame_layout . first_restore_gpr < first || cfun_frame_layout . last_restore_gpr > last ) ) continue ; if ( REGNO ( base ) != STACK_POINTER_REGNUM && REGNO ( base ) != HARD_FRAME_POINTER_REGNUM ) continue ; if ( first > BASE_REGNUM || last < BASE_REGNUM ) continue ; if ( cfun_frame_layout . first_restore_gpr != - <NUM_LIT> ) { rtx rpat = restore_gprs ( base , off + ( cfun_frame_layout . first_restore_gpr - first ) * UNITS_PER_LONG , cfun_frame_layout . first_restore_gpr , cfun_frame_layout . last_restore_gpr ) ; REG_NOTES ( rpat ) = REG_NOTES ( insn ) ; for ( rtx * ptr = & REG_NOTES ( rpat ) ; * ptr ; ) if ( REG_NOTE_KIND ( * ptr ) == REG_CFA_RESTORE && ( ( int ) REGNO ( XEXP ( * ptr , <NUM_LIT> ) ) < cfun_frame_layout . first_restore_gpr ) ) * ptr = XEXP ( * ptr , <NUM_LIT> ) ; else ptr = & XEXP ( * ptr , <NUM_LIT> ) ; new_insn = emit_insn_before ( rpat , insn ) ; RTX_FRAME_RELATED_P ( new_insn ) = <NUM_LIT> ; INSN_ADDRESSES_NEW ( new_insn , - <NUM_LIT> ) ; } remove_insn ( insn ) ; continue ; } if ( cfun_frame_layout . first_restore_gpr == - <NUM_LIT> && GET_CODE ( pat ) == SET && GENERAL_REG_P ( SET_DEST ( pat ) ) && GET_CODE ( SET_SRC ( pat ) ) == MEM ) { set = pat ; first = REGNO ( SET_DEST ( set ) ) ; offset = const0_rtx ; base = eliminate_constant_term ( XEXP ( SET_SRC ( set ) , <NUM_LIT> ) , & offset ) ; off = INTVAL ( offset ) ; if ( GET_CODE ( base ) != REG || off < <NUM_LIT> ) continue ; if ( REGNO ( base ) != STACK_POINTER_REGNUM && REGNO ( base ) != HARD_FRAME_POINTER_REGNUM ) continue ; remove_insn ( insn ) ; continue ; }


<s> StringRef FPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( FPU ) ; std :: vector < const char * > Features ; if ( ! <STR_LIT> ( ID , Features ) ) { Error ( FPUNameLoc , <STR_LIT> ) ;


<s> if ( ! <ISA_LIT>FI -> getLOHRelated ( ) . empty ( ) ) EmitLOHs ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> case llvm :: ELF :: EF_MIPS_ARCH_2 : return <STR_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_3 : return <STR_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_4 : return <STR_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_5 : return <STR_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_32 : return <STR_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_64 : return <STR_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_32R2 : return <STR_LIT> ;


<s> if ( SrcVT == <STR_LIT> && Subtarget . is64Bit ( ) ) { Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { DstVT , <STR_LIT> } , { Chain , Src } ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , Src ) ; } if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i64 ( Op , DAG , Subtarget ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i32 ( Op , DAG , Subtarget ) ; if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , dl ) ; SDValue Store1 = DAG . getStore ( Chain , dl , Src , StackSlot , MachinePointerInfo ( ) ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp . first ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Src ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) { ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; } SDValue Store = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; Chain = Fild . getValue ( <NUM_LIT> ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPop ( ) {


<s> if ( CALL_P ( insn ) || ( TARGET_MIPS16 ? simplejump_p ( insn ) : JUMP_P ( insn ) ) ) length += TARGET_MIPS16 ? <NUM_LIT> : <NUM_LIT> ; if ( ! cfun -> machine -> ignore_hazard_length_p && INSN_P ( insn ) && INSN_CODE ( insn ) >= <NUM_LIT> ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_DELAY : length += NOP_INSN_LENGTH ;


<s> static const std :: map < unsigned , unsigned > SRF2ZRF = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ; unsigned Register = RegisterTableSPU [ RegNo ] ; if ( Register == ~ <NUM_LIT> ) return MCDisassembler :: Fail ;

auto Ptr = SRF2ZRF . find ( Register ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) {


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; UserMI -> setDesc ( TII -> get ( U . getLongFormOpcode ( ) ) ) ; U . setMaxDisp ( U . getLongFormMaxDisp ( ) ) ; return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getLongFormMaxDisp ( ) , U . NegOk ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ;


<s> if ( ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) || ScalarTy -> isIntegerTy ( <NUM_LIT> ) ) return true ; if ( ScalarTy -> isHalfTy ( ) ) return Subtarget . hasStdExtZfh ( ) ; if ( ScalarTy -> isFloatTy ( ) ) return Subtarget . hasStdExtF ( ) ; if ( ScalarTy -> isDoubleTy ( ) ) return Subtarget . hasStdExtD ( ) ;


<s> SDValue Vec ; SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; MVT TVT ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { Ops . assign ( <NUM_LIT> , Cst ) ; TVT = <STR_LIT> ; } else { Ops . assign ( <NUM_LIT> , Cst ) ; TVT = <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printBitfieldInvMaskImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ;

int32_t width = ( <NUM_LIT> - countLeadingZeros ( v ) ) - lsb ;


<s> if ( loadImmediate ( OffsetValue , ATReg , <STR_LIT> , ! ABI . ArePtrs64bit ( ) , IDLoc , Instructions ) ) return true ; if ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> ) createAddu ( ATReg , ATReg , SrcReg , ABI . ArePtrs64bit ( ) , Instructions ) ; } unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg ; int64_t LeftLoadOffset = <NUM_LIT> , RightLoadOffset = <NUM_LIT> ; if ( isLittle ( ) ) { LeftLoadOffset = LoadedOffsetInAT ? <NUM_LIT> : ( OffsetValue + <NUM_LIT> ) ; RightLoadOffset = LoadedOffsetInAT ? <NUM_LIT> : OffsetValue ; } else { LeftLoadOffset = LoadedOffsetInAT ? <NUM_LIT> : OffsetValue ; RightLoadOffset = LoadedOffsetInAT ? <NUM_LIT> : ( OffsetValue + <NUM_LIT> ) ; } MCInst LeftLoadInst ; LeftLoadInst . setOpcode ( <STR_LIT> ) ; LeftLoadInst . addOperand ( DstRegOp ) ; LeftLoadInst . addOperand ( MCOperand :: createReg ( FinalSrcReg ) ) ; LeftLoadInst . addOperand ( MCOperand :: createImm ( LeftLoadOffset ) ) ; Instructions . push_back ( LeftLoadInst ) ; MCInst RightLoadInst ;

RightLoadInst . setOpcode ( <STR_LIT> ) ;


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , LHS , RHS , Flags ) ; } if ( LHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS ) && ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getVTList ( ) , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , BorrowIn ) ;


<s> int MaskSplitCost = getScalarizationOverhead ( MaskTy , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr ) ; int BranchCost = getCFInstrCost ( Instruction :: Br ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ;

auto VT = TLI -> getValueType ( DL , SrcVTy ) ;


<s> bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool isSVE = MFI . getStackID ( FI ) == TargetStackID :: ScalableVector ;

return resolveFrameOffsetReference ( MF , ObjectOffset , isFixed , isSVE , FrameReg , PreferFP , ForSimm ) ;


<s> free_bundle_state_chain = result -> next ; } else { result = XNEW ( struct bundle_state ) ;

result -> dfa_state = xmalloc ( dfa_state_size ) ;


<s> switch ( MCI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> return STI . getFeatureBits ( ) & <STR_LIT> ;


<s> do { LaneBitmask M = TRI . getSubRegIndexLaneMask ( S . getSubRegIndex ( ) ) ; if ( ( M & I . LaneMask ) . any ( ) ) LV . set ( S . getSubReg ( ) ) ; ++ S ; } while ( S . isValid ( ) ) ; } } ; BitVector LiveIn ( TRI . getNumRegs ( ) ) , Live ( TRI . getNumRegs ( ) ) ; CopyLiveIns ( B , LiveIn ) ; for ( auto SI : B -> successors ( ) ) CopyLiveIns ( SI , Live ) ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; if ( MI -> isDebugInstr ( ) ) continue ; MI -> clearKillInfo ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( R ) ) continue ; for ( MCSubRegIterator SR ( R , & TRI , true ) ; SR . isValid ( ) ; ++ SR ) Live . reset ( * SR ) ; }


<s> RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; default : return false ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( i ) ; updateValueMap ( & Arg , ResultReg ) ; ++ i ; } MRI . addLiveIn ( <STR_LIT> ) ; auto * MFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ;

for ( auto const & Arg : F -> args ( ) ) MFI -> addParam ( getLegalType ( getSimpleType ( Arg . getType ( ) ) ) ) ;


<s> const DataLayout * getDataLayout ( ) const override {

return getSubtargetImpl ( ) -> getDataLayout ( ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , RM . getValueOr ( Reloc :: Static ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) { initAsmInfo ( ) ;


<s> if ( hasFP ( MF ) ) { assert ( ( TailCallReturnAddrDelta <= <NUM_LIT> ) && <STR_LIT> ) ; int FrameIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , ( int ) SlotSize * - <NUM_LIT> + TailCallReturnAddrDelta ) ; assert ( FrameIdx == MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) && <STR_LIT> ) ; FrameIdx = <NUM_LIT> ; }


<s> else AlignedOffset = alignTo ( Offset , Alignment ) ; BlockInfo [ MBB . getNumber ( ) ] = AlignedOffset ; Offset = AlignedOffset + computeBlockSize ( MBB ) ; }


<s> MachineBasicBlock :: iterator I = MI ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: SHADER_TYPE : BB -> getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> ShaderType = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MI -> eraseFromParent ( ) ; break ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return BrOffset >= - <NUM_LIT> && BrOffset <= <NUM_LIT> ; }


<s> static tree mep_validate_io_cb ( tree * node , tree name , tree args , int flags ATTRIBUTE_UNUSED , bool * no_add ) { if ( TREE_CODE ( * node ) != VAR_DECL ) {

warning ( <NUM_LIT> , <STR_LIT> , name ) ;


<s> <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool isImmutable = ! ( getTargetMachine ( ) . Options . GuaranteedTailCallOpt && ( CallConv == CallingConv :: Fast ) ) ; unsigned PtrByteSize = <NUM_LIT> ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; unsigned LinkageSize = <ISA_LIT>FrameLowering :: getLinkageSize ( false , false , false ) ; CCInfo . AllocateStack ( LinkageSize , PtrByteSize ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_SVR4 ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * RC ; EVT ValVT = VA . getValVT ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasVSX ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , ValVT == <STR_LIT> ? <STR_LIT> : ValVT ) ; if ( ValVT == <STR_LIT> ) ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned ArgSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI -> CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ) ; }


<s> if ( Reg != - <NUM_LIT> ) { ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; return true ; } auto PMapper = <STR_LIT> ( RegString -> getString ( ) ) ; if ( PMapper ) { assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; unsigned Reg = PMapper -> Encoding ; uint64_t Immed = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned State ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) { assert ( Immed < <NUM_LIT> && <STR_LIT> ) ; State = <STR_LIT> ; } else { assert ( Immed < <NUM_LIT> && <STR_LIT> ) ; State = <STR_LIT> ;


<s> AMDGPU770Device :: AMDGPU770Device ( AMDGPUSubtarget * ST ) : AMDGPU7XXDevice ( ST ) {


<s> virtual void releaseBottomNode ( SUnit * SU ) {


<s> unsigned IndexReg = SM . getIndexReg ( ) ; unsigned Scale = SM . getScale ( ) ; if ( Scale == <NUM_LIT> && BaseReg != <STR_LIT> && BaseReg != <STR_LIT> && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale == <NUM_LIT> && ! ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) && ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) || <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) ) std :: swap ( BaseReg , IndexReg ) ; if ( Scale != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) return Error ( Start , <STR_LIT> ) ; if ( Scale == <NUM_LIT> ) Scale = <NUM_LIT> ; if ( ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) && ( IndexReg == <STR_LIT> || IndexReg == <STR_LIT> ) ) std :: swap ( BaseReg , IndexReg ) ; if ( ( BaseReg || IndexReg ) && CheckBaseRegAndIndexRegAndScale ( BaseReg , IndexReg , Scale , is64BitMode ( ) , ErrMsg ) ) return Error ( Start , ErrMsg ) ; if ( isParsingMSInlineAsm ( ) ) return CreateMemForMSInlineAsm ( RegNo , Disp , BaseReg , IndexReg , Scale , Start , End , Size , SM . getSymName ( ) , SM . getIdentifierInfo ( ) , Operands ) ;

if ( Parser . isParsingMasm ( ) && is64BitMode ( ) ) {


<s> SDValue AMDGPUTargetLowering :: LowerUDIVREM ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Num = Op . getOperand ( <NUM_LIT> ) ; SDValue Den = Op . getOperand ( <NUM_LIT> ) ; SDValue RCP = DAG . getNode ( <STR_LIT> , DL , VT , Den ) ; SDValue RCP_LO = DAG . getNode ( <STR_LIT> , DL , VT , RCP , Den ) ; SDValue RCP_HI = DAG . getNode ( <STR_LIT> , DL , VT , RCP , Den ) ; SDValue NEG_RCP_LO = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , VT ) , RCP_LO ) ; SDValue ABS_RCP_LO = DAG . getSelectCC ( DL , RCP_HI , DAG . getConstant ( <NUM_LIT> , VT ) , NEG_RCP_LO , RCP_LO , <STR_LIT> ) ; SDValue E = DAG . getNode ( <STR_LIT> , DL , VT , ABS_RCP_LO , RCP ) ; SDValue RCP_A_E = DAG . getNode ( <STR_LIT> , DL , VT , RCP , E ) ;

SDValue RCP_S_E = DAG . getNode ( <STR_LIT> , DL , VT , RCP , E ) ;


<s> case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : { if ( ! NeedTruncation && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { SDValue EFLAGS = LowerVectorAllZeroTest ( Op , Subtarget , DAG ) ; if ( EFLAGS . getNode ( ) ) return EFLAGS ; } Opcode = <STR_LIT> ; break ; } } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( NeedTruncation ) { EVT VT = Op . getValueType ( ) ; SDValue WideVal = Op -> getOperand ( <NUM_LIT> ) ; EVT WideVT = WideVal . getValueType ( ) ; unsigned ConvertedOp = <NUM_LIT> ; switch ( WideVal . getOpcode ( ) ) { default : break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; } if ( ConvertedOp ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isOperationLegal ( WideVal . getOpcode ( ) , WideVT ) ) { SDValue V0 = DAG . getNode ( <STR_LIT> , dl , VT , WideVal . getOperand ( <NUM_LIT> ) ) ; SDValue V1 = DAG . getNode ( <STR_LIT> , dl , VT , WideVal . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( ConvertedOp , dl , VT , V0 , V1 ) ; } } } if ( Opcode == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , Op . getValueType ( ) ) ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;

SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) , Op -> op_begin ( ) + NumOperands ) ;


<s> void <ISA_LIT>InstPrinter :: printMRSSystemRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Val == <STR_LIT> ) { O << <STR_LIT> ; return ; } if ( Val == <STR_LIT> ) { O << <STR_LIT> ; return ; } const <STR_LIT> * Reg = lookupSysReg ( Val , true , STI ) ; if ( isValidSysReg ( Reg , true , STI ) ) O << Reg -> Name ; else O << <STR_LIT> ( Val ) ;


<s> else emit_insn ( gen_move_gpsi ( dest , src ) ) ; return ; } if ( regno == HI_REGNUM ) { if ( REG_P ( dest ) ) { mips_emit_move ( temp , src ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthidi_ti ( gen_rtx_REG ( TImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( DImode , LO_REGNUM ) ) ) ; else emit_insn ( gen_mthisi_di ( gen_rtx_REG ( DImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( SImode , LO_REGNUM ) ) ) ; } else { if ( TARGET_64BIT ) emit_insn ( gen_mfhidi_ti ( temp , gen_rtx_REG ( TImode , MD_REG_FIRST ) ) ) ; else emit_insn ( gen_mfhisi_di ( temp , gen_rtx_REG ( DImode , MD_REG_FIRST ) ) ) ; mips_emit_move ( dest , temp ) ; } } else if ( mips_direct_save_slot_move_p ( regno , mem , mem == src ) ) mips_emit_move ( dest , src ) ; else {

gcc_assert ( ! reg_overlap_mentioned_p ( dest , temp ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasIntClamp ( false ) , HasVOP3PInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { AS = <STR_LIT> ( TT ) ;

initializeSubtargetDependencies ( TT , GPU , FS ) ;


<s> auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( MF -> getSubtarget ( ) ) ; switch ( HST . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 : case <ISA_LIT>Subtarget :: V60 : return CallerSavedRegsV4 ; } llvm_unreachable ( <STR_LIT> ) ;


<s> if ( TARGET_SPE && regno < <NUM_LIT> && ( SPE_VECTOR_MODE ( GET_MODE ( reg ) ) || ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SFmode && mode != SDmode && mode != SCmode ) ) ) ; else return NULL_RTX ; regno = REGNO ( reg ) ; words = ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_WORD - <NUM_LIT> ) / UNITS_PER_FP_WORD ; gcc_assert ( words <= <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < words ; i ++ , regno ++ ) { if ( BYTES_BIG_ENDIAN ) { parts [ <NUM_LIT> * i ] = gen_rtx_REG ( SImode , regno + FIRST_SPE_HIGH_REGNO ) ; parts [ <NUM_LIT> * i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno ) ; } else { parts [ <NUM_LIT> * i ] = gen_rtx_REG ( SImode , regno ) ;

parts [ <NUM_LIT> * i + <NUM_LIT> ] = gen_rtx_REG ( SImode , regno + FIRST_SPE_HIGH_REGNO ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; } switch ( FPInstClass ) { case <STR_LIT> : handleZeroArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFP ( I ) ; break ; case <STR_LIT> : handleOneArgFPRW ( I ) ; break ; case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI ( PrevMI ) ; if ( I == PrevI ) { dbgs ( ) << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && std :: prev ( Start ) != PrevI ) -- Start ;


<s> ScheduleHazardRecognizer :: HazardType <ISA_LIT>HazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { assert ( Stalls == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( LastMI && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) { MachineInstr * DefMI = LastMI ;

const MCInstrDesc & LastMCID = LastMI -> getDesc ( ) ;


<s> std :: string BTFTypeStruct :: getName ( ) { return std :: string ( STy -> getName ( ) ) ;


<s> bool invert ; if ( GET_CODE ( op1 ) == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( op1 ) ; switch ( code ) { case GTU : if ( val == <NUM_LIT> ) code = NE ; break ; case GT : case LE : if ( CONST_OK_FOR_J ( val + <NUM_LIT> ) ) { op1 = GEN_INT ( val + <NUM_LIT> ) ; code = code == LE ? LT : GE ; } break ; default : break ; } } if ( CONSTANT_P ( op1 ) && GET_CODE ( op1 ) != CONST_INT ) op1 = force_reg ( SImode , op1 ) ; invert = false ; switch ( code ) { case EQ : code = NE ; invert = true ; case NE : if ( GET_CODE ( op1 ) == CONST_INT && ! CONST_OK_FOR_K ( INTVAL ( op1 ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : code = GT ; invert = true ; case GT : if ( GET_CODE ( op1 ) == CONST_INT ) op1 = force_reg ( SImode , op1 ) ; break ; case GE : code = LT ; invert = true ; case LT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != <NUM_LIT> && ! CONST_OK_FOR_J ( INTVAL ( op1 ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case GTU : gcc_assert ( GET_CODE ( op1 ) != CONST_INT || INTVAL ( op1 ) != <NUM_LIT> ) ; code = LEU ; invert = true ; case LEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != <NUM_LIT> ) op1 = force_reg ( SImode , op1 ) ; break ; case LTU : code = GEU ; invert = true ;


<s> if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> || SrcPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; MVT AVT ; if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) AVT = <STR_LIT> ; else AVT = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ;


<s> for ( unsigned Idx = <NUM_LIT> ; Idx != NumOperands ; ++ Idx ) { LLT OpTy = MRI . getType ( MI . getOperand ( Idx ) . getReg ( ) ) ; assert ( <ISA_LIT>GenRegisterBankInfo :: getRegBankBaseIdxOffset ( RBIdx , OpTy . getSizeInBits ( ) ) == <ISA_LIT>GenRegisterBankInfo :: getRegBankBaseIdxOffset ( RBIdx , Size ) && <STR_LIT> ) ; bool OpIsFPR = OpTy . isVector ( ) || isPreISelGenericFloatingPointOpcode ( Opc ) ; ( void ) OpIsFPR ;

assert ( IsFPR == OpIsFPR && <STR_LIT> ) ;


<s> for ( insn = next_insn_to_bundle ( BB_HEAD ( bb ) , end ) ; insn ; insn = next ) { next = next_insn_to_bundle ( NEXT_INSN ( insn ) , end ) ; if ( GET_CODE ( PATTERN ( insn ) ) != ASM_INPUT ) { if ( next == NULL_RTX || GET_MODE ( next ) == TImode || CALL_P ( insn ) ) { PUT_MODE ( insn , QImode ) ; } else { PUT_MODE ( insn , SImode ) ; } }


<s> static bool isFPR64 ( unsigned Reg , unsigned SubReg , const MachineRegisterInfo * MRI ) {

if ( Register :: isVirtualRegister ( Reg ) ) return ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) && SubReg == <NUM_LIT> ) || ( MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & <STR_LIT> ) && SubReg == <STR_LIT> ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitEHSjLjLongJmp ( MachineInstr * MI , MachineBasicBlock * MBB ) const { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; } MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , SPOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; }


if ( findIndexForHandle ( Op , MF , Idx ) ) {


<s> bool <ISA_LIT>IfConversionTerm :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ) ;

if ( skipFunction ( MF . getFunction ( ) ) ) return false ;


<s> MachineInstr * MI = MRI -> getVRegDef ( SReg ) ; if ( ! MI ) return <STR_LIT> ; MachineOperand * MO = MI -> findRegisterDefOperand ( SReg ) ; assert ( MO -> isReg ( ) && <STR_LIT> ) ; if ( ! MO ) return <STR_LIT> ; if ( MI -> isCopy ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { SReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( Register :: isVirtualRegister ( SReg ) ) { if ( MO -> getSubReg ( ) == <STR_LIT> ) return <STR_LIT> ; return <STR_LIT> ; } return getDPRLaneFromSPR ( SReg ) ;


<s> int64_t Bytes , NumPredicateVectors , NumDataVectors ; Offset . getForFrameOffset ( Bytes , NumPredicateVectors , NumDataVectors ) ; if ( Bytes || ( ! Offset && SrcReg != DestReg ) ) { assert ( ( DestReg != <STR_LIT> || Bytes % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Opc = SetNZCV ? <STR_LIT> : <STR_LIT> ; if ( Bytes < <NUM_LIT> ) { Bytes = - Bytes ; Opc = SetNZCV ? <STR_LIT> : <STR_LIT> ; } emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , Bytes , Opc , TII , Flag , NeedsWinCFI , HasWinCFI ) ; SrcReg = DestReg ; } assert ( ! ( SetNZCV && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; assert ( ! ( NeedsWinCFI && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; if ( NumDataVectors ) { emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumDataVectors , <STR_LIT> , TII , Flag , NeedsWinCFI , nullptr ) ; SrcReg = DestReg ; } if ( NumPredicateVectors ) {

assert ( DestReg != <STR_LIT> && <STR_LIT> ) ;


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; }

<ISA_LIT>BaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ;


<s> break ; default : break ; } if ( IN_RANGE ( ival , - <NUM_LIT> , <NUM_LIT> ) ) return OP_TYPE_IMM_W ; return OP_TYPE_IMM_L ; } if ( GET_CODE ( op ) == CONST_DOUBLE ) { switch ( GET_MODE ( op ) ) { case SFmode : return OP_TYPE_IMM_W ; case VOIDmode : case DFmode : return OP_TYPE_IMM_L ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( op ) == CONST || symbolic_operand ( op , VOIDmode ) || LABEL_P ( op ) ) { switch ( GET_MODE ( op ) ) { case QImode : return OP_TYPE_IMM_Q ; case HImode : return OP_TYPE_IMM_W ; case SImode : return OP_TYPE_IMM_L ; default : if ( symbolic_operand ( m68k_unwrap_symbol ( op , false ) , VOIDmode ) ) return OP_TYPE_IMM_W ; return OP_TYPE_IMM_L ; } } gcc_assert ( ! reload_completed ) ;

if ( FLOAT_MODE_P ( GET_MODE ( op ) ) ) return OP_TYPE_FPN ;


<s> virtual ~ <ISA_LIT>SchedStrategy ( ) {


<s> bool isAligned = ! MMOs . empty ( ) && MMOs . front ( ) -> getAlignment ( ) >= Alignment ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , Subtarget ) ; DebugLoc DL ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . add ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState ( isKill ) ) ; MIB . setMemRefs ( MMOs ) ; NewMIs . push_back ( MIB ) ;


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ;

bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;


<s> } if ( Opcode == Instruction :: InsertElement ) { return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Store , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } } if ( Index != - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned SubNumElts = NumElts ; Index = Index % NumElts ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> ) { assert ( ( LT . second . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSubVecs = LT . second . getSizeInBits ( ) / <NUM_LIT> ; SubNumElts = NumElts / NumSubVecs ; if ( SubNumElts <= Index ) { RegisterFileMoveCost += ( Opcode == Instruction :: InsertElement ? <NUM_LIT> : <NUM_LIT> ) ; Index %= SubNumElts ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; N1 = peekThroughBitcasts ( N1 ) ; if ( N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; BuildVectorSDNode * Vector = cast < BuildVectorSDNode > ( N1 ) ; ShuffleVectorSDNode * Shuffle = cast < ShuffleVectorSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; EVT SrcType = Shuffle -> getValueType ( <NUM_LIT> ) ; if ( ! Shuffle -> getOperand ( <NUM_LIT> ) -> isUndef ( ) ) return SDValue ( ) ; unsigned SrcSize = SrcType . getScalarSizeInBits ( ) ;

unsigned NumElems = SrcType . getVectorNumElements ( ) ;


<s> bool <ISA_LIT>Subtarget :: IsLegalToCallImmediateAddr ( const TargetMachine & TM ) const {

if ( In64BitMode || isTargetWin32 ( ) ) return false ;


<s> switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new <ISA_LIT>DarwinTargetAsmInfo ( ) ; default :

return new <ISA_LIT>ELFTargetAsmInfo ( ) ;


<s> if ( isInlinableIntLiteral ( <ISA_LIT>mm ) ) { O << <ISA_LIT>mm ; } else { uint64_t Imm16 = static_cast < uint16_t > ( Imm ) ; O << formatHex ( Imm16 ) ; }


<s> if ( OddSPReg ) Value |= ( uint32_t ) <STR_LIT> ;


<s> EVT VecVT = N -> getValueType ( <NUM_LIT> ) ; EVT ElVT = VecVT . getVectorElementType ( ) ;

unsigned NumElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ;


<s> ++ I ; if ( ! CI ) continue ; Function * Callee = CI -> getCalledFunction ( ) ; if ( Callee == <NUM_LIT> ) continue ; if ( Simplifier . useNative ( CI ) ) Changed = true ; }


<s> const MCOperand & MO3 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << '[' << getRegisterName ( MO1 . getReg ( ) ) << ']' ; if ( <STR_LIT> ( MO3 . getImm ( ) ) ) { if ( MO2 . getReg ( ) == <NUM_LIT> ) O << '!' ;

else O << <STR_LIT> << getRegisterName ( MO2 . getReg ( ) ) ;


<s> bool isAISrcF16 ( ) const { return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) ;


<s> if ( INTVAL ( locality ) <= <NUM_LIT> ) return GEN_INT ( INTVAL ( write ) + <NUM_LIT> ) ;

if ( INTVAL ( locality ) <= <NUM_LIT> ) return write ;


<s> const TargetFrameInfo & TFI = * MF . getTarget ( ) . getFrameInfo ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) - TFI . getOffsetOfLocalArea ( ) + MFI -> getOffsetAdjustment ( ) ;


<s> return IsThumb && ( ThumbMode >= Thumb2 ) ;


<s> static const char * getRestoreLibCallName ( const MachineFunction & MF , const std :: vector < CalleeSavedInfo > & CSI ) { static const char * const RestoreLibCalls [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; int LibCallID = getLibCallID ( MF , CSI ) ;

if ( LibCallID == - <NUM_LIT> ) return nullptr ;


<s> SDValue Ptr = Opr . getOperand ( <NUM_LIT> ) ; return ! Ptr . getNode ( ) -> getFlags ( ) . hasIsAbsorptionCandidate ( ) ; }


<s> assert ( LHS . isReg ( ) && RHS . isReg ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; LLT Ty = MRI . getType ( LHS . getReg ( ) ) ; unsigned RegSize = Ty . getSizeInBits ( ) ; bool Is32Bit = ( RegSize == <NUM_LIT> ) ; const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; if ( auto ValAndVReg = getIConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI ) ) {

int64_t Imm = ValAndVReg -> Value . getSExtValue ( ) ;


<s> void <ISA_LIT>ELFMCAsmInfo :: anchor ( ) {


<s> static void m68hc11_init_libfuncs ( void ) { memcpy_libfunc = init_one_libfunc ( <STR_LIT> ) ;


<s> bool pru_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) {

bool in_memory = ( ! pru_arg_in_reg_bysize ( int_size_in_bytes ( type ) ) || int_size_in_bytes ( type ) == - <NUM_LIT> ) ;


<s> <ISA_LIT>DCFunction :: <ISA_LIT>DCFunction ( DCModule & DCM , const MCFunction & MCF ) : DCFunction ( DCM , MCF ) {


<s> { <STR_LIT> , rs6000_d_handle_target_float_abi } , { <STR_LIT> , rs6000_d_handle_target_object_format } , { NULL , NULL } , } ;

d_add_target_info_handlers ( handlers ) ;


<s> return __builtin_aarch64_cmeqhf_uss ( __a , __b ) ;


<s> case <STR_LIT> : case <STR_LIT> : ExpectedSourceType = <STR_LIT> ; break ; case <STR_LIT> : ExpectedSourceType = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( Conversion . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; auto Source = Conversion . getOperand ( <NUM_LIT> ) ; if ( Source . getValueType ( ) != ExpectedSourceType ) return SDValue ( ) ; auto IndexNode = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( IndexNode == nullptr || IndexNode -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; auto Op = GetWasmConversionOp ( ConversionOp ) ; return DAG . getNode ( Op , SDLoc ( N ) , ResVT , Source ) ; } auto ConversionOp = N -> getOpcode ( ) ; MVT ExpectedExtractType ; MVT ExpectedSourceType ; switch ( ConversionOp ) { case <STR_LIT> : case <STR_LIT> : ExpectedExtractType = <STR_LIT> ; ExpectedSourceType = <STR_LIT> ; break ; case <STR_LIT> : ExpectedExtractType = <STR_LIT> ; ExpectedSourceType = <STR_LIT> ;


<s> SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , B , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Ahi , B ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , AloBhi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;

AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , AhiBlo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> return __builtin_mve_vcvtq_m_from_f_sv4si ( __arm_vuninitializedq_s32 ( ) , __a , __p ) ;


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> if ( XFI -> isLargeFrame ( MF ) || hasFP ( MF ) ) RS -> addScavengingFrameIndex ( MFI . CreateStackObject ( Size , Align , false ) ) ; if ( XFI -> isLargeFrame ( MF ) && ! hasFP ( MF ) ) RS -> addScavengingFrameIndex ( MFI . CreateStackObject ( Size , Align , false ) ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> static bool second_ratio_invalid_for_first_lmul_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return calculate_sew ( info1 . get_vlmul ( ) , info2 . get_ratio ( ) ) == <NUM_LIT> ;


<s> fn_type = epiphany_compute_function_type ( current_function_decl ) ; interrupt_p = EPIPHANY_INTERRUPT_P ( fn_type ) ; if ( interrupt_p ) { addr = plus_constant ( Pmode , stack_pointer_rtx , - ( HOST_WIDE_INT ) <NUM_LIT> * UNITS_PER_WORD ) ; if ( ! lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) || ! epiphany_is_long_call_p ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) ) ) frame_move_insn ( gen_frame_mem ( DImode , addr ) , gen_rtx_REG ( DImode , GPR_0 ) ) ; frame_move_insn ( gen_rtx_REG ( SImode , GPR_0 ) , gen_rtx_REG ( word_mode , STATUS_REGNUM ) ) ; frame_move_insn ( gen_rtx_REG ( SImode , GPR_1 ) , gen_rtx_REG ( word_mode , IRET_REGNUM ) ) ; mem = gen_frame_mem ( BLKmode , stack_pointer_rtx ) ; off = GEN_INT ( - current_frame_info . first_slot_offset ) ; frame_insn ( gen_stack_adjust_add ( off , mem ) ) ; if ( ! epiphany_uninterruptible_p ( current_function_decl ) ) emit_insn ( gen_gie ( ) ) ; addr = plus_constant ( Pmode , stack_pointer_rtx , current_frame_info . first_slot_offset - ( HOST_WIDE_INT ) <NUM_LIT> * UNITS_PER_WORD ) ; } else { addr = plus_constant ( Pmode , stack_pointer_rtx , epiphany_stack_offset - ( HOST_WIDE_INT ) UNITS_PER_WORD ) ; epiphany_emit_save_restore ( <NUM_LIT> , current_frame_info . small_threshold , addr , <NUM_LIT> ) ; if ( current_frame_info . first_slot >= <NUM_LIT> ) { machine_mode mode = ( current_frame_info . first_slot_size == UNITS_PER_WORD ? word_mode : DImode ) ; off = GEN_INT ( - current_frame_info . first_slot_offset ) ; mem = gen_frame_mem ( BLKmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , off ) ) ; frame_insn ( gen_stack_adjust_str ( gen_frame_mem ( mode , stack_pointer_rtx ) , gen_rtx_REG ( mode , current_frame_info . first_slot ) , off , mem ) ) ;

addr = plus_constant ( Pmode , addr , current_frame_info . first_slot_offset ) ;


ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregciv2df ( __o , <NUM_LIT> ) ;


<s> static bool mips_near_type_p ( const_tree type ) {

return ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL || lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL ) ;


<s> bool <ISA_LIT>InstrInfo :: mayReadEXEC ( const MachineRegisterInfo & MRI , const MachineInstr & MI ) const { if ( MI . isMetaInstruction ( ) ) return false ; if ( MI . isCopyLike ( ) ) {

if ( ! RI . isSGPRReg ( MRI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return true ;


<s> if ( RLAmt [ i ] != VRI . RLAmt ) continue ; Mask |= ( <NUM_LIT> << i ) ; } unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; bool NeedsRotate = VRI . RLAmt != <NUM_LIT> ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) + ( unsigned ) ( bool ) Res ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << <STR_LIT> << <STR_LIT> << NumAndInsts << <STR_LIT> << VRI . NumGroups << <STR_LIT> ) ; if ( NumAndInsts >= VRI . NumGroups ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt ) { SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; VRot = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { VRot = VRI . V ; } SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , VRot , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; SDValue TotalVal ; if ( ! ANDIVal ) TotalVal = ANDISVal ; else if ( ! ANDISVal ) TotalVal = ANDIVal ; else TotalVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ANDIVal , ANDISVal ) , <NUM_LIT> ) ; if ( ! Res ) Res = TotalVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Res , TotalVal ) , <NUM_LIT> ) ; eraseMatchingBitGroups ( [ VRI ] ( const BitGroup & BG ) { return BG . V == VRI . V && BG . RLAmt == VRI . RLAmt ;


<s> FunctionPass * llvm :: create<ISA_LIT>SetflagAluCombinerPass ( ) { return new <ISA_LIT>SetflagAluCombiner ( ) ;


<s> static tree build_const_pointer ( tree t ) {

return build_pointer_type ( build_qualified_type ( t , TYPE_QUAL_CONST ) ) ;


<s> return ( uint16x4_t ) __builtin_neon_vget_highv8hi ( ( int16x8_t ) __a ) ;


<s> void printS10ImmOperand ( const MachineInstr * MI , unsigned OpNo ) {

short value = ( short ) ( ( ( int ) MI -> getOperand ( OpNo ) . getImm ( ) << <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> Value * Ptr = II . getOperand ( <NUM_LIT> ) ; Value * Mask = II . getOperand ( <NUM_LIT> ) ; Value * Vec = II . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantAggregateZero > ( Mask ) ) { IC . eraseInstFromFunction ( II ) ; return true ; } if ( II . getIntrinsicID ( ) == <STR_LIT> ) return false ; if ( Value * BoolMask = getBoolVecFromMask ( Mask ) ) { unsigned AddrSpace = cast < PointerType > ( Ptr -> getType ( ) ) -> getAddressSpace ( ) ; PointerType * VecPtrTy = PointerType :: get ( Vec -> getType ( ) , AddrSpace ) ; Value * PtrCast = IC . Builder . CreateBitCast ( Ptr , VecPtrTy , <STR_LIT> ) ;

IC . Builder . CreateMaskedStore ( Vec , PtrCast , Align ( <NUM_LIT> ) , BoolMask ) ;


<s> void tool_cleanup ( bool from_signal ATTRIBUTE_UNUSED ) {

for ( int i = <NUM_LIT> ; i < num_temps ; i ++ ) maybe_unlink ( temp_files [ i ] ) ;


<s> HOST_WIDE_INT size ; machine_mode ag_mode ; int count ; if ( ! AGGREGATE_TYPE_P ( type ) && TREE_CODE ( type ) != COMPLEX_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) return false ;

if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( type ) , type , & ag_mode , & count , NULL , false ) ) return false ;


<s> const MCExpr * ExtraImmOp = <NUM_LIT> ; if ( ( PatchedName . startswith ( <STR_LIT> ) || PatchedName . startswith ( <STR_LIT> ) ) && ( PatchedName . endswith ( <STR_LIT> ) || PatchedName . endswith ( <STR_LIT> ) || PatchedName . endswith ( <STR_LIT> ) || PatchedName . endswith ( <STR_LIT> ) ) ) { bool IsVCMP = PatchedName . startswith ( <STR_LIT> ) ; unsigned SSECCIdx = IsVCMP ? <NUM_LIT> : <NUM_LIT> ; unsigned SSEComparisonCode = StringSwitch < unsigned > ( PatchedName . slice ( SSECCIdx , PatchedName . size ( ) - <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( SSEComparisonCode != ~ <NUM_LIT> ) { ExtraImmOp = MCConstantExpr :: Create ( SSEComparisonCode , getParser ( ) . getContext ( ) ) ; if ( PatchedName . endswith ( <STR_LIT> ) ) { PatchedName = IsVCMP ? <STR_LIT> : <STR_LIT> ; } else if ( PatchedName . endswith ( <STR_LIT> ) ) { PatchedName = IsVCMP ? <STR_LIT> : <STR_LIT> ; } else if ( PatchedName . endswith ( <STR_LIT> ) ) { PatchedName = IsVCMP ? <STR_LIT> : <STR_LIT> ; } else { assert ( PatchedName . endswith ( <STR_LIT> ) && <STR_LIT> ) ; PatchedName = IsVCMP ? <STR_LIT> : <STR_LIT> ; } } }

if ( PatchedName . startswith ( <STR_LIT> ) ) {


<s> return ( uint16x4_t ) __builtin_aarch64_addpv4hi ( ( int16x4_t ) __a , ( int16x4_t ) __b ) ;


<s> const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; bool FoundDef = false ; bool FirstVSetVLI = false ; unsigned FirstSEW = <NUM_LIT> ; while ( MBBI != MBB . begin ( ) ) { -- MBBI ; if ( MBBI -> isMetaInstruction ( ) ) continue ; if ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) { if ( ! FoundDef ) { if ( ! FirstVSetVLI ) { FirstVSetVLI = true ; unsigned FirstVType = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> FirstLMul = <ISA_LIT>VType :: getVLMUL ( FirstVType ) ; FirstSEW = <ISA_LIT>VType :: getSEW ( FirstVType ) ; if ( FirstLMul != LMul ) return false ; } if ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; if ( MBBI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; if ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; continue ;


<s> getTargetStreamer ( ) . emitDirectiveCpreturn ( CpSaveLocation , CpSaveLocationIsRegister ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , ELFArch ( <NUM_LIT> ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , m_hasMemMappedGPR ( false ) , m_FeatureSetDummy ( false ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) {

ParseSubtargetFeatures ( CPU , CPU , FS ) ;


<s> name = get_identifier ( <STR_LIT> ) ; if ( name == NULL_TREE || TREE_CODE ( name ) != IDENTIFIER_NODE ) { warning ( <STR_LIT> ) ; return ; } decl_attributes ( & current_function_decl , tree_cons ( name , NULL_TREE , NULL_TREE ) , <NUM_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> int64_t WO = Width -> Value . getZExtValue ( ) << <NUM_LIT> | Offset -> Value . getZExtValue ( ) ; MachineInstr * MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( NewOpc ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( WO ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MI , TII , TRI , RBI ) ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) {


<s> assert ( <ISA_LIT>MCInstrInfo :: isBundle ( MCI ) && <STR_LIT> ) ; if ( MCI . size ( ) < <NUM_LIT> ) return ; bool StartedValid = llvm :: <ISA_LIT>MCShuffle ( false , MCII , STI , MCI ) ; MCInst CheckList ( MCI ) ; while ( lookForCompound ( MCII , Context , CheckList ) ) {


<s> int c = <NUM_LIT> ; v = v - ( ( v >> <NUM_LIT> ) & <NUM_LIT> ) ; v = ( v & <NUM_LIT> ) + ( ( v >> <NUM_LIT> ) & <NUM_LIT> ) ; c = ( ( ( v + ( v >> <NUM_LIT> ) ) & <NUM_LIT> ) * <NUM_LIT> ) >> <NUM_LIT> ;


<s> for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } unsigned StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ;

assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ;


<s> if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) { rtx elt ; gcc_assert ( const_vec_duplicate_p ( src , & elt ) && ( rtx_equal_p ( elt , const0_rtx ) || rtx_equal_p ( elt , const1_rtx ) ) ) ; emit_vlmax_op ( code_for_pred_mov ( mode ) , target , src , mask_mode ) ; return ;


<s> assert ( RegNo != <ISA_LIT>FunctionInfo :: UnusedReg ) ; OS << <STR_LIT> << RegNo << <STR_LIT> ;


<s> SDNode * InFP128 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Hi64 , SubRegEven ) ; InFP128 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , SDValue ( InFP128 , <NUM_LIT> ) , Lo64 , SubRegOdd ) ; SDValue OutChains [ <NUM_LIT> ] = { SDValue ( Hi64 . getNode ( ) , <NUM_LIT> ) , SDValue ( Lo64 . getNode ( ) , <NUM_LIT> ) } ;

SDValue OutChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ;


<s> if ( Work [ ThisW ] . size ( ) % <NUM_LIT> != <NUM_LIT> ) Work [ ThisW ] . push_back ( UndefValue :: get ( Ty ) ) ; for ( int i = <NUM_LIT> , e = Work [ ThisW ] . size ( ) ; i < e ; i += <NUM_LIT> ) { Value * Joined = Builder . CreateShuffleVector ( Work [ ThisW ] [ i ] , Work [ ThisW ] [ i + <NUM_LIT> ] , SMask ) ; Work [ OtherW ] . push_back ( Joined ) ; } std :: swap ( ThisW , OtherW ) ; } SMask . resize ( Vecs . size ( ) * getSizeOf ( Vecs . front ( ) -> getType ( ) ) ) ; std :: iota ( SMask . begin ( ) , SMask . end ( ) , <NUM_LIT> ) ; Value * Total = Work [ OtherW ] . front ( ) ; return Builder . CreateShuffleVector ( Total , SMask ) ;


<s> SelectionDAG & DAG = DCI . DAG ; if ( ! isS16 ( OpS16 , DAG ) && ! isSRA16 ( OpS16 ) ) { OpS16 = OpS32 ; OpS32 = SMULLOHI -> getOperand ( <NUM_LIT> ) ; } SDLoc dl ( OR ) ; unsigned Opcode = <NUM_LIT> ; if ( isS16 ( OpS16 , DAG ) ) Opcode = <STR_LIT> ; else if ( isSRA16 ( OpS16 ) ) { Opcode = <STR_LIT> ; OpS16 = OpS16 -> getOperand ( <NUM_LIT> ) ; } else return SDValue ( ) ; SDValue Res = DAG . getNode ( Opcode , dl , <STR_LIT> , OpS32 , OpS16 ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( OR , <NUM_LIT> ) , Res ) ;


<s> inline ConstantInt * cimm ( LLVMContext & C , unsigned value ) {

auto * Ty = IntegerType :: get ( C , <NUM_LIT> ) ;


<s> static bool LdStCopOpcode ( unsigned Opcode ) { if ( ( Opcode >= <STR_LIT> && Opcode <= <STR_LIT> ) || ( Opcode >= <STR_LIT> && Opcode <= <STR_LIT> ) ) return true ; return false ;


<s> static SDValue lowerFP_TO_SINT_STORE ( StoreSDNode * SD , SelectionDAG & DAG ) { SDValue Val = SD -> getValue ( ) ; if ( Val . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT FPTy = EVT :: getFloatingPointVT ( Val . getValueSizeInBits ( ) ) ;

SDValue Tr = DAG . getNode ( <STR_LIT> , SDLoc ( Val ) , FPTy , Val . getOperand ( <NUM_LIT> ) ) ;


<s> D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( Reg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( Reg , <STR_LIT> ) ;


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>RemoveExtendArgs ( TM ) ) ; addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; }


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( true , OSABI , ELF :: EM_<ISA_LIT> , false ) {


<s> Instruction * front ( ) const { return Chain . front ( ) ;


<s> rtx_insn * def_insn ; df_ref use , def ; struct df_link * defs ; newx = NULL_RTX ; if ( UNARY_P ( x ) ) { op0 = r10k_simplify_address ( XEXP ( x , <NUM_LIT> ) , insn ) ; if ( op0 != XEXP ( x , <NUM_LIT> ) ) newx = simplify_gen_unary ( GET_CODE ( x ) , GET_MODE ( x ) , op0 , GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) ; } else if ( BINARY_P ( x ) ) { op0 = r10k_simplify_address ( XEXP ( x , <NUM_LIT> ) , insn ) ; op1 = r10k_simplify_address ( XEXP ( x , <NUM_LIT> ) , insn ) ; if ( op0 != XEXP ( x , <NUM_LIT> ) || op1 != XEXP ( x , <NUM_LIT> ) ) newx = simplify_gen_binary ( GET_CODE ( x ) , GET_MODE ( x ) , op0 , op1 ) ; } else if ( GET_CODE ( x ) == LO_SUM ) { op0 = r10k_simplify_address ( XEXP ( x , <NUM_LIT> ) , insn ) ; if ( GET_CODE ( op0 ) == HIGH ) newx = XEXP ( x , <NUM_LIT> ) ; } else if ( REG_P ( x ) ) { use = df_find_use ( insn , regno_reg_rtx [ REGNO ( x ) ] ) ; gcc_assert ( use ) ; defs = DF_REF_CHAIN ( use ) ; if ( defs && defs -> next == NULL ) { def = defs -> ref ; if ( DF_REF_IS_ARTIFICIAL ( def ) ) { if ( x == stack_pointer_rtx && DF_REF_BB ( def ) == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) newx = virtual_incoming_args_rtx ; } else if ( dominated_by_p ( CDI_DOMINATORS , DF_REF_BB ( use ) , DF_REF_BB ( def ) ) ) { def_insn = DF_REF_INSN ( def ) ; if ( NONJUMP_INSN_P ( def_insn ) ) { set = single_set ( def_insn ) ; if ( set && rtx_equal_p ( SET_DEST ( set ) , x ) ) { note = find_reg_equal_equiv_note ( def_insn ) ; if ( note ) newx = XEXP ( note , <NUM_LIT> ) ; else newx = SET_SRC ( set ) ;

newx = r10k_simplify_address ( newx , def_insn ) ;


<s> if ( CC != - <NUM_LIT> ) return matchRegisterByNumber ( CC , is64BitReg ? <STR_LIT> : <STR_LIT> ) ;


<s> void llvm :: addUnpredicatedMveVpredROp ( MachineInstrBuilder & MIB , Register DestReg ) {


<s> bool <ISA_LIT>TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , unsigned , bool * Fast ) const { if ( Fast ) * Fast = Subtarget -> isUnalignedMemAccessFast ( ) ; return true ;


<s> LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , getKillRegState ( StatusDead ) ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; LivePhysRegs LiveRegs ; computeLiveIns ( LiveRegs , MRI , * DoneBB ) ; computeLiveIns ( LiveRegs , MRI , * StoreBB ) ; computeLiveIns ( LiveRegs , MRI , * LoadCmpBB ) ;


<s> void addVPredicateOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; PredicateOp Pred = getPredicate ( ) ; assert ( Pred . IsVector ) ; Inst . addOperand ( MCOperand :: createReg ( Pred . RegNum ) ) ; Inst . addOperand ( MCOperand :: createImm ( Pred . Polarity ) ) ;


<s> if ( icode == <NUM_LIT> ) internal_error ( <STR_LIT> ) ; nonvoid = TREE_TYPE ( TREE_TYPE ( fndecl ) ) != void_type_node ; opnum = nonvoid ; FOR_EACH_CALL_EXPR_ARG ( arg , iter , exp ) { const struct insn_operand_data * insn_op ; if ( arg == error_mark_node ) return NULL_RTX ; if ( opnum > MAX_BUILTIN_ARGS ) return NULL_RTX ; insn_op = & insn_data [ icode ] . operand [ opnum ] ; op [ opnum ] = expand_expr ( arg , NULL_RTX , insn_op -> mode , EXPAND_NORMAL ) ; if ( ! ( * insn_op -> predicate ) ( op [ opnum ] , insn_op -> mode ) ) op [ opnum ] = copy_to_mode_reg ( insn_op -> mode , op [ opnum ] ) ; if ( ! ( * insn_op -> predicate ) ( op [ opnum ] , insn_op -> mode ) ) { error_at ( EXPR_LOCATION ( exp ) , <STR_LIT> ) ; return const0_rtx ; } opnum ++ ; } if ( nonvoid ) { machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op [ <NUM_LIT> ] = target ; } fn = GEN_FCN ( icode ) ; switch ( opnum ) { case <NUM_LIT> : pat = fn ( NULL_RTX ) ; break ; case <NUM_LIT> : pat = fn ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = fn ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = fn ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = fn ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = fn ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ;


<s> MachineOperand & CallTarget = MI . getOperand ( <NUM_LIT> ) ; assert ( ( CallTarget . isGlobal ( ) || CallTarget . isReg ( ) ) && <STR_LIT> ) ; unsigned Opc = CallTarget . isGlobal ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstr * Call = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . getInstr ( ) ;


<s> static DecodeStatus DecodeT2BROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val ) ) ) ; return MCDisassembler :: Success ;


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isImm ( ) ) OS << MO . getImm ( ) ; else OS << regToString ( MO ) ; return false ; } return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , OS ) ;


<s> } if ( GET_CODE ( xinsn ) == REG && mt_reg_ok_for_base_p ( xinsn , strict ) ) return true ; if ( GET_CODE ( xinsn ) == PLUS && GET_CODE ( XEXP ( xinsn , <NUM_LIT> ) ) == REG && mt_reg_ok_for_base_p ( XEXP ( xinsn , <NUM_LIT> ) , strict ) && GET_CODE ( XEXP ( xinsn , <NUM_LIT> ) ) == CONST_INT && SMALL_INT ( XEXP ( xinsn , <NUM_LIT> ) ) ) return true ; return false ;


<s> unsigned int getOccupancy ( ) const { return Occupancy . first ;


return ( unsigned char ) __builtin_ia32_ktestcdi ( __A , __B ) ;


<s> if ( cfun -> machine -> interrupt_handler_p && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return ( regno == GLOBAL_POINTER_REGNUM ? TARGET_CALL_SAVED_GP : ! call_used_regs [ regno ] ) ;


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( <ISA_LIT>FI -> getUsesRedZone ( ) ) { MIB -> setDesc ( get ( MIB -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( get ( <STR_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( get<ISA_LIT>SubSuperRegister ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ) ; } else { assert ( MIB -> getOpcode ( ) == <STR_LIT> ) ; StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( get ( <STR_LIT> ) ) ; } MachineFunction & MF = * MBB . getParent ( ) ;

const <ISA_LIT>FrameLowering * TFL = Subtarget . getFrameLowering ( ) ;


<s> Pos = ( ( ( Pos ^ <NUM_LIT> ) + <NUM_LIT> ) ^ <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const { return MachineJumpTableInfo :: EK_BlockAddress ;


<s> unsigned <ISA_LIT>HazardRecognizer :: getNumDecoderSlots ( SUnit * SU ) const { const MCSchedClassDesc * SC = getSchedClass ( SU ) ;

if ( ! SC -> isValid ( ) ) return <NUM_LIT> ;


<s> unsigned <ISA_LIT>ConstantIslands :: GetOffsetOf ( MachineInstr * MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned Offset = BBInfo [ MBB -> getNumber ( ) ] . Offset ;

for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) ; ; ++ I ) {


<s> void <ISA_LIT>MCChecker :: reportErrorNewValue ( unsigned Register ) {

reportError ( <STR_LIT> + Twine ( RI . getName ( Register ) ) + <STR_LIT> <STR_LIT> ) ;


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override {


<s> if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) call_used_regs [ <NUM_LIT> ] = <NUM_LIT> ; if ( DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; if ( DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; if ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = call_used_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; if ( TARGET_TOC && TARGET_MINIMAL_TOC ) fixed_regs [ RS6000_PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; if ( ! TARGET_ALTIVEC && ! TARGET_VSX ) { for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; call_used_regs [ VRSAVE_REGNO ] = <NUM_LIT> ; } if ( TARGET_ALTIVEC || TARGET_VSX ) global_regs [ VSCR_REGNO ] = <NUM_LIT> ; if ( TARGET_ALTIVEC_ABI ) { for ( i = FIRST_ALTIVEC_REGNO ; i < FIRST_ALTIVEC_REGNO + <NUM_LIT> ; ++ i ) call_used_regs [ i ] = <NUM_LIT> ; if ( TARGET_XCOFF && ! rs6000_aix_extabi ) for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i < FIRST_ALTIVEC_REGNO + <NUM_LIT> ; ++ i ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ;


<s> bool CantUseFP = needsStackRealignment ( MF ) ;


<s> static void emitThumbRegPlusImmInReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned DestReg , unsigned BaseReg , int NumBytes , bool CanChangeCC , const TargetInstrInfo & TII , const <ISA_LIT>RegisterInfo & MRI , DebugLoc dl ) { bool isHigh = ! MRI . isLowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! MRI . isLowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) { assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; LdReg = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , false , false , true ) ; } if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addReg ( LdReg , false , false , true ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , LdReg , NumBytes , <STR_LIT> , <NUM_LIT> , & TII , true , dl ) ; int Opc = ( isSub ) ? <STR_LIT> : ( isHigh ? <STR_LIT> : <STR_LIT> ) ;

const MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ;


<s> EVT EltVT = Store -> getValue ( ) . getValueType ( ) . getVectorElementType ( ) ; EVT PtrVT = Store -> getBasePtr ( ) . getValueType ( ) ; unsigned NumElts = Store -> getMemoryVT ( ) . getVectorNumElements ( ) ; SDLoc SL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) {

SDValue Val = DAG . getNode ( <STR_LIT> , SL , EltVT , Store -> getValue ( ) , DAG . getConstant ( i , <STR_LIT> ) ) ;


<s> SDValue Trmp = Op . getOperand ( <NUM_LIT> ) ; SDValue FPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue Nest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; unsigned AS = <NUM_LIT> ; Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) , AS ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ;

Entry . Node = Nest ; Args . push_back ( Entry ) ;


<s> if ( isLittle ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ABI . IsO32 ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ! ABI . IsN64 ( ) ) Ret += <STR_LIT> ;


<s> if ( ! Strict ) return <NUM_LIT> <= OpId && isUInt < OP_WIDTH_ > ( OpId ) ; switch ( MsgId ) { case ID_GS : return ( OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_ ) && OpId != OP_GS_NOP ; case ID_GS_DONE : return OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_ ; case ID_SYSMSG :

return OP_SYS_FIRST_ <= OpId && OpId < OP_SYS_LAST_ ;


<s> return <STR_LIT> . contains ( RegNo ) ;


<s> assert ( RD . Sub == <NUM_LIT> ) ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( RS . Reg ) ) return false ; RegExtMap :: const_iterator F = VRX . find ( RD . Reg ) ; if ( F == VRX . end ( ) ) return false ; uint16_t EW = F -> second . Width ; putCell ( RD , getCell ( RS , Inputs ) , Outputs ) ; RegisterCell Res ; if ( F -> second . Type == ExtType :: SExt ) Res = eSXT ( getCell ( RD , Outputs ) , EW ) ; else if ( F -> second . Type == ExtType :: ZExt ) Res = eZXT ( getCell ( RD , Outputs ) , EW ) ; putCell ( RD , Res , Outputs ) ;


<s> bool Changed = false ; const <ISA_LIT>Subtarget & Subtarget = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MachineFunction :: iterator MBBI = MF . begin ( ) ; MachineFunction :: iterator EndMBB = MF . end ( ) ; for ( ; MBBI != EndMBB ; ++ MBBI ) { MachineBasicBlock * MBB = MBBI ; if ( ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator EndI = MBB -> end ( ) ; -- EndI ; if ( EndI -> getDesc ( ) . isReturn ( ) ) continue ; } bool ContainsFPCode = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; ! ContainsFPCode && I != E ; ++ I ) { if ( I -> getNumOperands ( ) != <NUM_LIT> && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { const TargetRegisterClass * clas ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) { if ( I -> getOperand ( op ) . isReg ( ) && I -> getOperand ( op ) . isDef ( ) && TargetRegisterInfo :: isVirtualRegister ( I -> getOperand ( op ) . getReg ( ) ) && ( ( clas = MRI . getRegClass ( I -> getOperand ( op ) . getReg ( ) ) ) == <STR_LIT> || clas == <STR_LIT> || clas == <STR_LIT> ) ) { ContainsFPCode = true ; break ; } } } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB -> getBasicBlock ( ) ; const PHINode * PN ; for ( succ_const_iterator SI = succ_begin ( LLVMBB ) , E = succ_end ( LLVMBB ) ;


<s> case AVX_U128 : if ( mode == AVX_U128_CLEAN ) emit_insn ( gen_avx_vzeroupper ( ) ) ; break ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ;


<s> case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , false , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , false , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , false , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , true , DAG ) ; case <STR_LIT> : return lowerMulDiv ( Op , <STR_LIT> , true , true , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; } return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG ) ;


<s> BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( UpdateMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CompareOpcode ) ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( KeepOldMask ) . addMBB ( UpdateMBB ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB -> addSuccessor ( UseAltMBB ) ; MBB = UseAltMBB ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedAltVal ) . addReg ( RotatedOldVal ) . addReg ( Src2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> + BitSize ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( UpdateMBB ) ; MBB = UpdateMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( RotatedOldVal ) . addMBB ( LoopMBB ) . addReg ( RotatedAltVal ) . addMBB ( UseAltMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( RotatedNewVal ) . addReg ( NegBitShift ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( CSOpcode ) , Dest ) . addReg ( OldVal ) . addReg ( NewVal ) . add ( Base ) . addImm ( Disp ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ;