<s> case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op , DAG ) ; case <STR_LIT> : return LowerVectorOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerMULH ( Op , DAG ) ; case <STR_LIT> :

return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , TargetOptions O , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level L ) : LLVMTargetMachine ( T , TT , CPU , FS , O , RM , CM , L ) , Subtarget ( TT , CPU , FS ) , DL ( <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { initAsmInfo ( ) ;


<s> ElemSize esize = Opcode == <STR_LIT> ? ESize8 : ( Opcode == <STR_LIT> ? ESize16 : ESize32 ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeNEONRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;

MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ;


<s> } else if ( SRVK == MCSymbolRefExpr :: VK_TLSLDM ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: createExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } EmitAndCountInstruction ( LEA ) ; if ( needsPadding ) {

EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ;


<s> AMDGPUInstrInfo :: AMDGPUInstrInfo ( TargetMachine & tm ) : AMDGPUGenInstrInfo ( <NUM_LIT> , <NUM_LIT> ) , RI ( tm ) , TM ( tm ) {


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = GPR32DecoderTable [ RegNo ] ;

if ( Register == <STR_LIT> ) Register = <STR_LIT> ;


<s> return isInlinableImm ( ) || isRegClass ( <STR_LIT> ) ;


<s> if ( LinkerConfig :: Object != config ( ) . codeGenType ( ) ) { ELFFileFormat * file_format = getOutputFormat ( ) ; LDSection & got = file_format -> getGOT ( ) ; m_pGOT = new <ISA_LIT>_64GOT ( got ) ; LDSection & gotplt = file_format -> getGOTPLT ( ) ; m_pGOTPLT = new <ISA_LIT>_64GOTPLT ( gotplt ) ; LDSection & plt = file_format -> getPLT ( ) ; plt . setAlign ( <NUM_LIT> ) ; m_pPLT = new <ISA_LIT>_64PLT ( plt , * m_pGOTPLT , config ( ) ) ;

LDSection & relplt = file_format -> getRelaPlt ( ) ;


<s> for ( i = <NUM_LIT> ; i < count ; ++ i , ++ p ) if ( ( target_flags & p -> target_mask ) == p -> target_mask ) alpha_builtin_function ( p -> name , ftype , p -> code , ( p -> is_const ? ECF_CONST : <NUM_LIT> ) | ECF_NOTHROW ) ;


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; MachineBasicBlock * PrologB = & MF . front ( ) , * EpilogB = nullptr ; if ( EnableShrinkWrapping ) findShrunkPrologEpilog ( MF , PrologB , EpilogB ) ; insertCSRSpillsInBlock ( * PrologB , CSI , HRI ) ; insertPrologueInBlock ( * PrologB ) ; if ( EpilogB ) {

insertCSRRestoresInBlock ( * EpilogB , CSI , HRI ) ;


<s> bool <ISA_LIT>InstrInfo :: isDotCurInst ( const MachineInstr & MI ) const {


<s> case <STR_LIT> : ShiftAmt = <NUM_LIT> ; break ; } Register TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( SrcReg ) . addImm ( ShiftAmt ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) . addImm ( ShiftAmt ) ; return true ;


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Lo = extract128BitVector ( Src , <NUM_LIT> , DAG , dl ) ; SDValue Hi = extract128BitVector ( Src , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) ; MVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , NewVT , Lo ) , DAG . getNode ( <STR_LIT> , dl , NewVT , Hi ) ) ;


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else {

const MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ;


<s> OS << getReg ( ) << <STR_LIT> ; break ; case Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ;


<s> uint64_t Index = Field >> <NUM_LIT> ; uint64_t Base = ( Field >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Disp = Field & <NUM_LIT> ; assert ( Index < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Disp ) ) ;

Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> [ Index ] ) ) ;


<s> SDValue Offset ; bool isPre = ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ; unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( SelectT2AddrModeImm8Offset ( N , LD -> getOffset ( ) , Offset ) ) { switch ( LoadedVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( isSExtLd ) Opcode = isPre ? <STR_LIT> : <STR_LIT> ; else Opcode = isPre ? <STR_LIT> : <STR_LIT> ; break ; default : return NULL ; } Match = true ; } if ( Match ) { SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ;

SDValue Ops [ ] = { Base , Offset , getAL ( CurDAG ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ;


<s> __rv . __o = __builtin_neon_vld2v8bf ( ( const __builtin_neon_bf * ) __ptr ) ;


<s> } else if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ) ; }


<s> static inline enum insn_code rs6000_htm_spr_icode ( bool nonvoid ) { if ( nonvoid ) return ( TARGET_POWERPC64 ) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si ; else return ( TARGET_POWERPC64 ) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si ;


<s> return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } <STR_LIT> CC ; SDValue LHS , RHS ; if ( CCVal . getOpcode ( ) == <STR_LIT> ) { LHS = CCVal . getOperand ( <NUM_LIT> ) ; RHS = CCVal . getOperand ( <NUM_LIT> ) ; CC = cast < CondCodeSDNode > ( CCVal . getOperand ( <NUM_LIT> ) ) -> get ( ) ; } else { LHS = CCVal ; RHS = DAG . getConstant ( <NUM_LIT> , DL , CCVal . getValueType ( ) ) ; CC = <STR_LIT> ; }

return LowerSELECT_CC ( CC , LHS , RHS , TVal , FVal , DL , DAG ) ;


<s> Tmp . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Tmp . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Tmp . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Out . EmitInstruction ( Tmp , STI ) ;


<s> auto IsHazardFn = [ ] ( const MachineInstr & I ) { if ( ! <ISA_LIT>InstrInfo :: isVMEM ( I ) && ! <ISA_LIT>InstrInfo :: isFLAT ( I ) ) return false ; return <ISA_LIT>InstrInfo :: isFPAtomic ( I ) ; } ; auto IsExpiredFn = [ ] ( const MachineInstr & MI , int WaitStates ) { if ( WaitStates >= <NUM_LIT> || <ISA_LIT>InstrInfo :: isVALU ( MI ) ) return true ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_PLT , <STR_LIT> } , { MO_PIC_FLAG , <STR_LIT> } , { MO_PCREL_FLAG , <STR_LIT> } , { MO_GOT_FLAG , <STR_LIT> } , { MO_PCREL_OPT_FLAG , <STR_LIT> } , { MO_TLSGD_FLAG , <STR_LIT> } , { MO_TLSLD_FLAG , <STR_LIT> } , { MO_TPREL_FLAG , <STR_LIT> } , { MO_GOT_TLSGD_PCREL_FLAG , <STR_LIT> } , { MO_GOT_TLSLD_PCREL_FLAG , <STR_LIT> } , { MO_GOT_TPREL_PCREL_FLAG , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MoveToFPReg ( MVT SrcVT , unsigned SrcReg , bool IsSigned ) { if ( SrcVT == <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( <STR_LIT> , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return <NUM_LIT> ; SrcReg = TmpReg ; } Address Addr ; Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = MFI . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ; if ( ! <ISA_LIT>EmitStore ( <STR_LIT> , SrcReg , Addr ) ) return <NUM_LIT> ; unsigned LoadOpc = <STR_LIT> ; if ( SrcVT == <STR_LIT> ) { if ( ! IsSigned ) { LoadOpc = <STR_LIT> ; Addr . Offset = ( Subtarget -> isLittleEndian ( ) ) ? <NUM_LIT> : <NUM_LIT> ; } else if ( Subtarget -> hasLFIWAX ( ) ) { LoadOpc = <STR_LIT> ; Addr . Offset = ( Subtarget -> isLittleEndian ( ) ) ? <NUM_LIT> : <NUM_LIT> ; }


<s> gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || SUBREG_P ( dest ) ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else {

if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ;


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MFI . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ( ) ; else FrameReg = <STR_LIT> ; Offset += MFI . getStackSize ( ) ; if ( FI < <NUM_LIT> ) Offset += RVFI -> getLibCallStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) { Offset += RVFI -> getVarArgsSaveSize ( ) ; if ( FI >= <NUM_LIT> ) Offset -= RVFI -> getLibCallStackSize ( ) ; } else { Offset += MFI . getStackSize ( ) ;


<s> getReadTimeStampCounter ( Op . getNode ( ) , DL , <STR_LIT> , DAG , Subtarget , Results ) ; return DAG . getMergeValues ( Results , DL ) ;


<s> MachineInstr * OpMI = MRI . getVRegDef ( Reg ) ; assert ( OpMI && <STR_LIT> ) ;

return get<ISA_LIT>VectorSplatScalar ( * OpMI , MRI ) ;


<s> return __builtin_ia32_movmskps ( ( __v4sf ) __A ) ;


<s> bool <ISA_LIT>CallLowering :: isTypeIsValidForThisReturn ( EVT Ty ) const {

return Ty . getSizeInBits ( ) == <NUM_LIT> ;


<s> getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( L , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ;


<s> } if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == HIGH ) { push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; }


<s> } MachineInstr * TrueCmpMI = findSuitableCompare ( TBB ) ; if ( ! TrueCmpMI ) { continue ; } <STR_LIT> HeadCmp ; if ( HeadCond . empty ( ) || ! parseCond ( HeadCond , HeadCmp ) ) { continue ; } <STR_LIT> TrueCmp ; if ( TrueCond . empty ( ) || ! parseCond ( TrueCond , TrueCmp ) ) { continue ; } const int HeadImm = ( int ) HeadCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int TrueImm = ( int ) TrueCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadImm << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ;

if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) {


<s> unsigned <ISA_LIT>16InstrInfo :: GetOppositeBranchOpc ( unsigned Opc ) const {


<s> bool mayNeedRelaxation ( const MCInst & , const MCSubtargetInfo & STI ) const override { return false ;


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , FK_PCRel_2 ) ) ; return <NUM_LIT> ;


<s> Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint16_t Flags = MI . getFlags ( ) ; LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; auto One = B . buildFConstant ( S64 , <NUM_LIT> ) ; auto DivScale0 = B . buildIntrinsic ( <STR_LIT> , { S64 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto NegDivScale0 = B . buildFNeg ( S64 , DivScale0 . getReg ( <NUM_LIT> ) , Flags ) ; auto Rcp = B . buildIntrinsic ( <STR_LIT> , { S64 } , false ) . addUse ( DivScale0 . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto Fma0 = B . buildFMA ( S64 , NegDivScale0 , Rcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S64 , Rcp , Fma0 , Rcp , Flags ) ; auto Fma2 = B . buildFMA ( S64 , NegDivScale0 , Fma1 , One , Flags ) ; auto DivScale1 = B . buildIntrinsic ( <STR_LIT> , { S64 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto Fma3 = B . buildFMA ( S64 , Fma1 , Fma2 , Fma1 , Flags ) ; auto Mul = B . buildFMul ( S64 , DivScale1 . getReg ( <NUM_LIT> ) , Fma3 , Flags ) ; auto Fma4 = B . buildFMA ( S64 , NegDivScale0 , Mul , DivScale1 . getReg ( <NUM_LIT> ) , Flags ) ; Register Scale ; if ( ! ST . hasUsableDivScaleConditionOutput ( ) ) { LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto NumUnmerge = B . buildUnmerge ( S32 , LHS ) ; auto DenUnmerge = B . buildUnmerge ( S32 , RHS ) ;

auto Scale0Unmerge = B . buildUnmerge ( S32 , DivScale0 ) ;


<s> if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ; if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ;


<s> if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { MachineInstr * Old = I ;

MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CalleeAmt ) ;


<s> for ( auto Ptr : Switches ) if ( Ptr != SwPtr && Ptr -> fitsTargetFeatures ( Features ) ) if ( Ptr -> Value == SwPtr -> Value && meetsDependencies ( SwSet , Ptr , Switches ) ) {

DISASM_DEBUG ( dbgs ( ) << <STR_LIT> << SwPtr -> Name << <STR_LIT> << Ptr -> Name << '\n' ) ;


<s> unsigned <ISA_LIT>TargetLowering :: combineRepeatedFPDivisors ( ) const { return <NUM_LIT> ;


<s> static void IfNeededLDAWSP ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc dl , const TargetInstrInfo & TII , int OffsetFromTop , int & RemainingAdj ) { while ( OffsetFromTop < RemainingAdj - MaxImmU16 ) { assert ( RemainingAdj && <STR_LIT> ) ;

int OpImm = ( RemainingAdj > MaxImmU16 ) ? MaxImmU16 : RemainingAdj ;


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ;

SDValue UnpckNode = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> void RetpolineThunkInserter :: populateThunk ( MachineFunction & MF ) { bool Is64Bit = MF . getTarget ( ) . getTargetTriple ( ) . getArch ( ) == Triple :: x86_64 ; Register ThunkReg ; if ( Is64Bit ) { assert ( MF . getName ( ) == <STR_LIT> && <STR_LIT> ) ; ThunkReg = <STR_LIT> ; } else { if ( MF . getName ( ) == EAXRetpolineName ) ThunkReg = <STR_LIT> ; else if ( MF . getName ( ) == ECXRetpolineName ) ThunkReg = <STR_LIT> ; else if ( MF . getName ( ) == EDXRetpolineName ) ThunkReg = <STR_LIT> ; else if ( MF . getName ( ) == EDIRetpolineName ) ThunkReg = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; } const TargetInstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineBasicBlock * Entry = & MF . front ( ) ; Entry -> clear ( ) ; while ( MF . size ( ) > <NUM_LIT> ) MF . erase ( std :: next ( MF . begin ( ) ) ) ; MachineBasicBlock * CaptureSpec = MF . CreateMachineBasicBlock ( Entry -> getBasicBlock ( ) ) ; MachineBasicBlock * CallTarget = MF . CreateMachineBasicBlock ( Entry -> getBasicBlock ( ) ) ; MCSymbol * TargetSym = MF . getContext ( ) . createTempSymbol ( ) ; MF . push_back ( CaptureSpec ) ; MF . push_back ( CallTarget ) ;

const unsigned CallOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ;


<s> LoadSDNode * LD = cast < LoadSDNode > ( N1 ) ; if ( ! isValidIndexedLoad ( LD ) ) return nullptr ; MVT VT = LD -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned Opc = ( VT == <STR_LIT> ? Opc16 : Opc8 ) ; MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N1 ) -> getMemOperand ( ) ; SDValue Ops0 [ ] = { N2 , LD -> getBasePtr ( ) , LD -> getChain ( ) } ; SDNode * ResNode = CurDAG -> SelectNodeTo ( Op , Opc , VT , <STR_LIT> , <STR_LIT> , Ops0 , <NUM_LIT> ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; ReplaceUses ( SDValue ( N1 . getNode ( ) , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N1 . getNode ( ) , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; return ResNode ;


<s> one = force_reg ( mode , const_double_from_real_value ( dconst1 , mode ) ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , xa , res , ! do_floor ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; tmp = expand_simple_binop ( mode , do_floor ? MINUS : PLUS , xa , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; if ( HONOR_SIGNED_ZEROS ( mode ) ) { if ( do_floor && flag_rounding_math ) tmp = ix86_expand_sse_fabs ( tmp , NULL ) ; ix86_sse_copysign_to_positive ( tmp , tmp , res , mask ) ; } emit_move_insn ( res , tmp ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> return isImm ( <NUM_LIT> , <NUM_LIT> ) ;


<s> output_addr_const ( file , op1 ) ; fputs ( <STR_LIT> , file ) ; } else fatal_insn ( <STR_LIT> , addr ) ; break ; } case MEM : case LABEL_REF : fatal_insn ( <STR_LIT> , addr ) ; break ; default : output_addr_const ( file , addr ) ;


<s> SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ;

Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ;


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FI , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> return __builtin_mve_vcreateq_uv8hi ( __a , __b ) ;


<s> if ( PredI != PredJ ) return false ; if ( SUJ -> isSucc ( SUI ) ) { for ( unsigned i = <NUM_LIT> , e = SUJ -> Succs . size ( ) ; i < e ; ++ i ) { const SDep & Dep = SUJ -> Succs [ i ] ; if ( Dep . getSUnit ( ) != SUI ) continue ; if ( Dep . getKind ( ) == SDep :: Anti ) continue ; if ( Dep . getKind ( ) == SDep :: Output ) if ( MII -> getOperand ( <NUM_LIT> ) . getReg ( ) != MIJ -> getOperand ( <NUM_LIT> ) . getReg ( ) ) continue ; return false ; } }

bool ARDef = TII -> definesAddressRegister ( * MII ) || TII -> definesAddressRegister ( * MIJ ) ;


<s> MCStreamer * ES = create<ISA_LIT>ELFStreamer ( Context , MAB , OS , Emitter , RelaxAll ) ; new MCTargetStreamer ( * ES ) ; return ES ;


<s> } else if ( PointerSize == <NUM_LIT> ? SelectADDRsi64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRsi ( N1 . getNode ( ) , N1 , Base , Offset ) ) { Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } else if ( PointerSize == <NUM_LIT> ? SelectADDRri64 ( N1 . getNode ( ) , N1 , Base , Offset ) : SelectADDRri ( N1 . getNode ( ) , N1 , Base , Offset ) ) { if ( PointerSize == <NUM_LIT> ) Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , Base , Offset , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } else { if ( PointerSize == <NUM_LIT> ) Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Opcode = pickOpcodeForVT ( TargetVT , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; if ( ! Opcode ) return false ; SDValue Ops [ ] = { getI32Imm ( isVolatile , dl ) , getI32Imm ( CodeAddrSpace , dl ) , getI32Imm ( vecType , dl ) , getI32Imm ( fromType , dl ) , getI32Imm ( fromTypeWidth , dl ) , N1 , Chain } ; <ISA_LIT>LD = CurDAG -> getMachineNode ( Opcode . getValue ( ) , dl , TargetVT , <STR_LIT> , Ops ) ; } if ( ! <ISA_LIT>LD ) return false ; MachineMemOperand * MemRef = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( <ISA_LIT>LD ) , { MemRef } ) ; ReplaceNode ( N , <ISA_LIT>LD ) ;


<s> auto & MF = DAG . getMachineFunction ( ) ; auto & TFL = * Subtarget . getFrameLowering ( ) ; const unsigned SPOffset = TFL . has128ByteRedZone ( MF ) ? - <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . is64Bit ( ) ) { SDValue Zero = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( SPOffset , DL , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ; SDNode * Res = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , Ops ) ; return SDValue ( Res , <NUM_LIT> ) ; }


<s> switch ( CM ) { default : break ; case CodeModel :: Default :

CM = RM == Reloc :: PIC_ ? CodeModel :: Small : CodeModel :: Medium ;


<s> assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , i , BaseReg , Off , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , i , BaseReg , Off , TII , this ) ; } assert ( Done && <STR_LIT> ) ; ( void ) Done ;


<s> bool <ISA_LIT>AsmPrinter :: UseReadOnlyJumpTables ( ) const {


<s> gmask = current_frame_info . gmask ; gcc_assert ( current_frame_info . total_size || ! gmask ) ; if ( current_frame_info . pretend_size != <NUM_LIT> ) { HOST_WIDE_INT pretend_size = current_frame_info . pretend_size ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - pretend_size ) ) ) ; } if ( current_frame_info . save_fp ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , frame_pointer_rtx ) ) ; gmask &= ~ ( FRAME_POINTER_MASK | RETURN_ADDR_MASK ) ; for ( regno = <NUM_LIT> ; regno <= M32R_MAX_INT_REGS ; ++ regno ) { if ( ( gmask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , regno ) ) ) ; } if ( current_frame_info . save_lr ) emit_insn ( gen_movsi_push ( stack_pointer_rtx , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ) ; frame_size = ( current_frame_info . total_size - ( current_frame_info . pretend_size + current_frame_info . reg_size ) ) ; if ( frame_size == <NUM_LIT> ) ; else if ( frame_size <= <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - frame_size ) ) ) ;


<s> } else if ( CTVal && CFVal && CTVal -> isOne ( ) && CFVal -> isZero ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } else if ( TVal . getOpcode ( ) == <STR_LIT> ) { if ( isAllOnesConstant ( TVal . getOperand ( <NUM_LIT> ) ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } } else if ( TVal . getOpcode ( ) == <STR_LIT> ) { if ( isNullConstant ( TVal . getOperand ( <NUM_LIT> ) ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } } else if ( CTVal && CFVal ) { const int64_t TrueVal = CTVal -> getSExtValue ( ) ; const int64_t FalseVal = CFVal -> getSExtValue ( ) ; bool Swap = false ; if ( TrueVal == ~ FalseVal ) { Opcode = <STR_LIT> ; } else if ( FalseVal > std :: numeric_limits < int64_t > :: min ( ) && TrueVal == - FalseVal ) { Opcode = <STR_LIT> ; } else if ( TVal . getValueType ( ) == <STR_LIT> ) { const uint32_t TrueVal32 = CTVal -> getZExtValue ( ) ; const uint32_t FalseVal32 = CFVal -> getZExtValue ( ) ; if ( ( TrueVal32 == FalseVal32 + <NUM_LIT> ) || ( TrueVal32 + <NUM_LIT> == FalseVal32 ) ) { Opcode = <STR_LIT> ; if ( TrueVal32 > FalseVal32 ) { Swap = true ; } } } else if ( ( TrueVal == FalseVal + <NUM_LIT> ) || ( TrueVal + <NUM_LIT> == FalseVal ) ) { Opcode = <STR_LIT> ; if ( TrueVal > FalseVal ) { Swap = true ; } } if ( Swap ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } if ( Opcode != <STR_LIT> ) { FVal = TVal ; } } ConstantSDNode * RHSVal = dyn_cast < ConstantSDNode > ( RHS ) ; if ( Opcode == <STR_LIT> && RHSVal && ! RHSVal -> isOne ( ) && ! RHSVal -> isZero ( ) && ! RHSVal -> isAllOnes ( ) ) { <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; if ( CTVal && CTVal == RHSVal && <ISA_LIT>CC == <STR_LIT> ) TVal = LHS ;

else if ( CFVal && CFVal == RHSVal && <ISA_LIT>CC == <STR_LIT> ) FVal = LHS ;


<s> return ( uint32x2_t ) __builtin_neon_vget_lowv4si ( ( int32x4_t ) __a ) ;


<s> if ( RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } if ( RegClass == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( Value ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RegClass ) ) { if ( RI . getRegSizeInBits ( * RegClass ) > <NUM_LIT> ) { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } else { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } } ArrayRef < int16_t > SubIndices = RI . getRegSplitParts ( RegClass , EltSize ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < SubIndices . size ( ) ; ++ Idx ) { int64_t IdxValue = Idx == <NUM_LIT> ? Value : <NUM_LIT> ; MachineInstrBuilder Builder = BuildMI ( MBB , MI , DL , get ( Opcode ) , RI . getSubReg ( DestReg , SubIndices [ Idx ] ) ) ;


<s> dbgprintf ( insn , <STR_LIT> ) ; if ( insn -> consumedOpcodeModifier ) return <NUM_LIT> ; insn -> consumedOpcodeModifier = TRUE ; switch ( insn -> spec -> modifierType ) { default : debug ( <STR_LIT> ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_GT ) != <NUM_LIT> ) ;


<s> if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return <NUM_LIT> ; if ( type && mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; return ( size + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;


<s> case 'h' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <NUM_LIT> , true ) ; break ; case 'w' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <NUM_LIT> ) ; break ; case 'k' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <NUM_LIT> ) ; break ; case 'V' : EmitPercent = false ; LLVM_FALLTHROUGH ; case 'q' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , P . getSubtarget ( ) . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LdrexOp ) , Dest . getReg ( ) ) ; MIB . addReg ( AddrReg ) ; if ( LdrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , TempReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ; MI . eraseFromParent ( ) ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; LivePhysRegs LiveRegs ; computeLiveIns ( LiveRegs , MRI , * DoneBB ) ; computeLiveIns ( LiveRegs , MRI , * StoreBB ) ; computeLiveIns ( LiveRegs , MRI , * LoadCmpBB ) ; StoreBB -> clearLiveIns ( ) ; computeLiveIns ( LiveRegs , MRI , * StoreBB ) ; LoadCmpBB -> clearLiveIns ( ) ;


<s> strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( dest ) . addReg ( oldval ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( newval ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loop1MBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop1MBB ) ;


<s> if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > Gathers ; SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ;

Changed |= optimiseAddress ( II -> getArgOperand ( <NUM_LIT> ) , II -> getParent ( ) , LI ) ;


<s> return __builtin_mve_vdupq_n_fv4sf ( __a ) ;


<s> return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ;


<s> unsigned SrcReg = Src . getReg ( ) ; if ( Opc != <STR_LIT> ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; MachineBasicBlock :: LivenessQueryResult LQR = MI -> getParent ( ) -> computeRegisterLiveness ( & getRegisterInfo ( ) , NewSrc , MI ) ;


<s> bool isRegisterReservedByUser ( Register R ) const {


<s> static bool readsLocalId ( const IntrinsicInst * II ) { switch ( II -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rdf ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x1_t ) { __builtin_aarch64_get_dregoidf ( __o , <NUM_LIT> ) } ;


<s> if ( ! REG_P ( target ) ) tmp = gen_reg_rtx ( mode ) ; if ( TARGET_P9_VECTOR ) { unspec = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op0 , op1 , sel ) , UNSPEC_VPERMR ) ; } else { notx = gen_rtx_NOT ( V16QImode , sel ) ; iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ;

emit_insn ( gen_rtx_SET ( norreg , iorx ) ) ;


<s> if ( call_used_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( fixed_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; comma = <STR_LIT> ; }

len += fprintf ( stderr , <STR_LIT> , comma , reg_class_names [ ( int ) rs6000_regno_regclass [ r ] ] ) ;


<s> case llvm :: ADDRESS_SPACE_SHARED : return <STR_LIT> :: SHARED ; case llvm :: ADDRESS_SPACE_GENERIC : return <STR_LIT> :: GENERIC ; case llvm :: ADDRESS_SPACE_PARAM : return <STR_LIT> :: PARAM ; case llvm :: ADDRESS_SPACE_CONST : return <STR_LIT> :: CONSTANT ; default : break ; } } return <STR_LIT> :: GENERIC ;


<s> if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) {


<s> EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } SDValue Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> rtx dst = destmem , src = * srcmem , tempreg ; enum insn_code code ; machine_mode move_mode ; int piece_size , i ; piece_size = <NUM_LIT> << floor_log2 ( size_to_move ) ; while ( ! int_mode_for_size ( piece_size * BITS_PER_UNIT , <NUM_LIT> ) . exists ( & move_mode ) || ( code = optab_handler ( mov_optab , move_mode ) ) == CODE_FOR_nothing ) { gcc_assert ( piece_size > <NUM_LIT> ) ; piece_size >>= <NUM_LIT> ; } if ( GET_MODE_SIZE ( move_mode ) > GET_MODE_SIZE ( word_mode ) ) { int nunits = GET_MODE_SIZE ( move_mode ) / GET_MODE_SIZE ( word_mode ) ; if ( ! mode_for_vector ( word_mode , nunits ) . exists ( & move_mode ) || ( code = optab_handler ( mov_optab , move_mode ) ) == CODE_FOR_nothing ) { move_mode = word_mode ; piece_size = GET_MODE_SIZE ( move_mode ) ; code = optab_handler ( mov_optab , move_mode ) ; }


<s> void <ISA_LIT>PostRASchedStrategy :: schedNode ( SUnit * SU , bool IsTopNode ) {

DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> ; ) ;


<s> bool IsVSSReg ( unsigned Reg , MachineRegisterInfo & MRI ) { return IsRegInClass ( Reg , & <STR_LIT> , MRI ) ;


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; O << Value ;

} else printOperand ( MI , OpNum , O ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; if ( Val == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ;


<s> bool runOnModule ( Module & M ) override { DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; if ( skipModule ( M ) ) return false ; bool Changed = false ; PromotionCacheTy PromotionCache ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF , PromotionCache ) ; }


<s> if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ( ToEltVT == <STR_LIT> || ToEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ToEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || FromVT . getVectorNumElements ( ) == NumElements || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> ) return SDValue ( ) ; auto isVMOVNOriginalMask = [ & ] ( ArrayRef < int > M , bool rev ) { unsigned NumElts = ToVT . getVectorNumElements ( ) ; if ( NumElts != M . size ( ) || ( ToVT != <STR_LIT> && ToVT != <STR_LIT> ) ) return false ; unsigned Off0 = rev ? NumElts : <NUM_LIT> ; unsigned Off1 = rev ? <NUM_LIT> : NumElts ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) ( Off0 + i / <NUM_LIT> ) ) return false ;

if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ] != ( int ) ( Off1 + i / <NUM_LIT> ) ) return false ;


<s> auto AlignVectors :: getAlignFromValue ( const Value * V ) const -> Align {

const auto * C = dyn_cast < ConstantInt > ( V ) ;


<s> if ( REG_P ( x ) && ( mode == TFmode || mode == TImode ) && mode == GET_MODE ( x ) && FP_REGNUM_P ( REGNO ( x ) ) && ! TARGET_SIMD && reg_class_subset_p ( rclass , FP_REGS ) ) { if ( mode == TFmode ) sri -> icode = CODE_FOR_aarch64_reload_movtf ;

else if ( mode == TImode ) sri -> icode = CODE_FOR_aarch64_reload_movti ;


<s> Type = ELF :: R_MIPS_CALL16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GOTTPREL ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_PC16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_DISP ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ;

Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ;


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasF16C = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRDRAND = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasCmpxchg16b = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; <ISA_LIT>_MC :: DetectFamilyModel ( EAX , Family , Model ) ; if ( IsAMD || ( Family == <NUM_LIT> && Model >= <NUM_LIT> ) ) { IsBTMemSlow = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) || ( Family == <NUM_LIT> && Model == <NUM_LIT> ) ) ) { IsUAMemFast = true ; ToggleFeature ( <STR_LIT> ) ; } if ( Family == <NUM_LIT> && ( Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> ) ) { <ISA_LIT>ProcFamily = IntelAtom ; UseLeaForSP = true ; ToggleFeature ( <STR_LIT> ) ; } else if ( Family == <NUM_LIT> && ( Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> ) ) { <ISA_LIT>ProcFamily = IntelSLM ; } unsigned MaxExtLevel ; <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & MaxExtLevel , & EBX , & ECX , & EDX ) ; if ( MaxExtLevel >= <NUM_LIT> ) { <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) { Has<ISA_LIT>_64 = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasLZCNT = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) {


<s> bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) MRI . setPhysRegUsed ( <STR_LIT> [ I ] ) ; if ( HasFP ) MRI . setPhysRegUsed ( <STR_LIT> ) ;

if ( MFFrame -> hasCalls ( ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ;


<s> case <NUM_LIT> : CanonicalVT = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } } else { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; switch ( Val . getValueType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : CanonicalVT = <STR_LIT> ; break ; case <NUM_LIT> : CanonicalVT = <STR_LIT> ; break ; case <NUM_LIT> : CanonicalVT = <STR_LIT> ; break ; case <NUM_LIT> : CanonicalVT = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( CanonicalVT . getVectorNumElements ( ) , Val ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ;


<s> static inline vec_float4 vec_min ( vec_float4 a , vec_float4 b ) {

return ( spu_sel ( a , b , spu_cmpgt ( a , b ) ) ) ;


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || isTargetAndroid ( ) ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> static bool isVREVMask ( const SmallVectorImpl < int > & M , EVT VT , unsigned BlockSize ) { assert ( ( BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned EltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ; if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) continue ;

if ( ( unsigned ) M [ i ] != ( i - i % BlockElts ) + ( BlockElts - <NUM_LIT> - i % BlockElts ) ) return false ;


<s> bool callsEhReturn ( ) const { return CallsEhReturn ;


<s> uint32_t encodeStackAdjustment ( uint32_t StackSize ) const {

return ( StackSize / <NUM_LIT> ) << <NUM_LIT> ;


<s> if ( TARGET_32BIT && mode == TImode ) return false ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ;

else if ( TARGET_FLOAT128_TYPE && ( mode == KFmode || mode == IFmode ) ) return true ;


<s> Function * I = <STR_LIT> ( II . getModule ( ) , NewIntr , ArgTys ) ; CallInst * NewCall = IC . Builder . CreateCall ( I , Args ) ; NewCall -> takeName ( & II ) ; NewCall -> copyMetadata ( II ) ; if ( isa < FPMathOperator > ( NewCall ) ) NewCall -> copyFastMathFlags ( & II ) ; if ( ! II . getType ( ) -> isVoidTy ( ) ) IC . replaceInstUsesWith ( II , NewCall ) ;

return IC . eraseInstFromFunction ( II ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx ) : MCII ( mcii ) , STI ( sti ) {


<s> case <STR_LIT> : Binary |= <NUM_LIT> << <STR_LIT> ; break ; case <STR_LIT> : Binary |= <NUM_LIT> << <STR_LIT> ; break ;


<s> if ( <ISA_LIT>FI -> getEmitNOAT ( ) ) OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ;


<s> return Size > <NUM_LIT> && Size <= SSThreshold ;


<s> TargetRegistry :: RegisterELFStreamer ( getThe<ISA_LIT>Target ( ) , createMCStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Target ( ) , createMCAsmTargetStreamer ) ;

TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ;


<s> return setInfoSVEStN < <NUM_LIT> > ( * this , DL , Info , I ) ; case <STR_LIT> : return setInfoSVEStN < <NUM_LIT> > ( * this , DL , Info , I ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = DL . getTypeSizeInBits ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ;


<s> static tree make_attribute ( const char * name , const char * arg_name , tree chain ) { tree attr_name ; tree attr_arg_name ; tree attr_args ; tree attr ; attr_name = get_identifier ( name ) ; attr_arg_name = build_string ( strlen ( arg_name ) , arg_name ) ;


<s> std :: pair < SDValue , int > BO = getBaseAndOffset ( L -> getBasePtr ( ) ) ; if ( BO . first . getOpcode ( ) == <STR_LIT> ) return false ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( BO . first ) ) {

auto & HTM = static_cast < const <ISA_LIT>TargetMachine & > ( getTargetMachine ( ) ) ;


<s> DebugLoc DL = MBBI -> getDebugLoc ( ) ; unsigned IssueWidth = TSM . getIssueWidth ( ) ;

for ( unsigned i = <NUM_LIT> , e = IssueWidth * NOOPsToAdd ; i != e ; ++ i ) BuildMI ( * MBB , MBBI , DL , TSM . getInstrInfo ( ) -> get ( <STR_LIT> ) ) ;


<s> MCInstLowering . Lower ( MI , TmpInst ) ; TmpInst . setOpcode ( <STR_LIT> ) ; OutStreamer -> EmitInstruction ( TmpInst , STI ) ; } else {

OutStreamer -> EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( LPCC :: ICC_T ) , STI ) ;


<s> Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ;


<s> if ( ! Src . getOperand ( Idx ) . isUndef ( ) && Src . getConstantOperandAPInt ( Idx ) . isNegative ( ) ) Imm . setBit ( Idx ) ; } return DAG . getConstant ( Imm , SDLoc ( N ) , VT ) ; } unsigned EltWidth = SrcVT . getScalarSizeInBits ( ) ; if ( Src . getOpcode ( ) == <STR_LIT> && Src . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == EltWidth ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) ) ; if ( SDValue NotSrc = IsNOT ( Src , DAG ) ) {


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo / <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> NumBytes = NumBits / <NUM_LIT> ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = <NUM_LIT> ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( Offset >= - ( <NUM_LIT> << <NUM_LIT> ) && Offset <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) return true ; unsigned shift = Log2_64 ( NumBytes ) ;

if ( NumBytes && Offset > <NUM_LIT> && ( Offset / NumBytes ) <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> && ( Offset >> shift ) << shift == Offset ) return true ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != AUIPCSymbol -> getOffset ( ) ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : return & F ; }


<s> if ( STI . isTargetWindowsCoreCLR ( ) ) { if ( InProlog ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; } else { emitStackProbeInline ( MF , MBB , MBBI , DL , false ) ; } } else { emitStackProbeCall ( MF , MBB , MBBI , DL , InProlog , InstrNum ) ;


<s> return new yaml :: <ISA_LIT>MachineFunctionInfo ( ) ;


<s> <ISA_LIT>64Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , bool bigEndian ) : <ISA_LIT>DisassemblerBase ( STI , Ctx , bigEndian ) {


<s> if ( Sym -> getType ( ) == <STR_LIT> ) { if ( Sym -> isUndefined ( ) ) getTargetStreamer ( ) -> emitGlobalType ( Sym ) ; } else if ( Sym -> getType ( ) == <STR_LIT> ) getTargetStreamer ( ) -> emitTagType ( Sym ) ; else if ( Sym -> getType ( ) == <STR_LIT> ) getTargetStreamer ( ) -> emitTableType ( Sym ) ; } DenseSet < MCSymbol * > InvokeSymbols ; for ( const auto & F : M ) { if ( F . isIntrinsic ( ) ) continue ; if ( F . isDeclarationForLinker ( ) ) { SmallVector < MVT , <NUM_LIT> > Results ; SmallVector < MVT , <NUM_LIT> > Params ; computeSignatureVTs ( F . getFunctionType ( ) , & F , F , TM , Params , Results ) ; auto Signature = signatureFromMVTs ( Results , Params ) ; bool InvokeDetected = false ; auto * Sym = getMCSymbolForFunction ( & F , <STR_LIT> || <STR_LIT> , Signature . get ( ) , InvokeDetected ) ; if ( InvokeDetected && ! InvokeSymbols . insert ( Sym ) . second ) continue ; Sym -> setType ( <STR_LIT> ) ; if ( ! Sym -> getSignature ( ) ) { Sym -> setSignature ( Signature . get ( ) ) ; addSignature ( std :: move ( Signature ) ) ; } else { Signature . reset ( ) ; } getTargetStreamer ( ) -> emitFunctionType ( Sym ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Name = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setImportModule ( storeName ( Name ) ) ; getTargetStreamer ( ) -> emitImportModule ( Sym , Name ) ; } if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Name = InvokeDetected ? Sym -> getName ( ) : F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setImportName ( storeName ( Name ) ) ; getTargetStreamer ( ) -> emitImportName ( Sym , Name ) ; } } if ( F . hasFnAttribute ( <STR_LIT> ) ) { auto * Sym = cast < MCSymbolWasm > ( getSymbol ( & F ) ) ; StringRef Name = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ;

Sym -> setExportName ( storeName ( Name ) ) ;


<s> assert ( Kind == Memory && <STR_LIT> ) ; return Mem . MaybeDirectBranchDest ;


<s> RS6000_OUTPUT_BASENAME ( file , name ) ; } else assemble_name ( file , name ) ;


<s> MachineInstr * DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; bool Invert = ! DefMI ; if ( ! DefMI ) DefMI = canFoldIntoMOVCC ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , this ) ; if ( ! DefMI ) return nullptr ; MachineOperand FalseReg = MI . getOperand ( Invert ? <NUM_LIT> : <NUM_LIT> ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * PreviousClass = MRI . getRegClass ( FalseReg . getReg ( ) ) ; if ( ! MRI . constrainRegClass ( DestReg , PreviousClass ) ) return nullptr ;

MachineInstrBuilder NewMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DefMI -> getDesc ( ) , DestReg ) ;


<s> if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ;


<s> for ( auto & I : MRI . use_nodbg_operands ( Reg ) ) { const auto & Result = LI . Query ( LIS . getInstructionIndex ( * I . getParent ( ) ) ) ; if ( Result . valueIn ( ) == DefVNI ) { if ( ! Result . isKill ( ) ) return false ; if ( HasOne ) return false ; HasOne = true ; }


<s> unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ; unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ;

if ( isSigned ) return ~ ( - <NUM_LIT> << ( bits - <NUM_LIT> ) ) ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , MII ( mii ) , InstInfo ( nullptr ) { setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ; Instrumentation . reset ( Create<ISA_LIT>AsmInstrumentation ( Options , Parser . getContext ( ) , STI ) ) ;


<s> EVT ValueVT = Val . getValueType ( ) ; if ( IsABIRegCopy && ValueVT == <STR_LIT> && PartVT == <STR_LIT> ) { Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ; Parts [ <NUM_LIT> ] = Val ; return true ; } if ( ValueVT . isScalableVector ( ) && PartVT . isScalableVector ( ) ) { LLVMContext & Context = * DAG . getContext ( ) ; EVT ValueEltVT = ValueVT . getVectorElementType ( ) ; EVT PartEltVT = PartVT . getVectorElementType ( ) ; unsigned ValueVTBitSize = ValueVT . getSizeInBits ( ) . getKnownMinSize ( ) ; unsigned PartVTBitSize = PartVT . getSizeInBits ( ) . getKnownMinSize ( ) ;

if ( PartVTBitSize % ValueVTBitSize == <NUM_LIT> ) {


<s> unsigned Opcode = MI . getOpcode ( ) ; MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; MCContext & Ctx = MF -> getContext ( ) ; assert ( <STR_LIT> ( Opcode , <STR_LIT> :: address ) == static_cast < int > ( FIOperandNum ) && <STR_LIT> ) ; MachineOperand & Base = MI . getOperand ( FIOperandNum ) ; int FrameIndex = Base . getIndex ( ) ; if ( Opcode == <STR_LIT> ) lowerSpillB1 ( II , FrameIndex ) ; else if ( Opcode == <STR_LIT> ) lowerRestoreB1 ( II , FrameIndex ) ; StringRef SymName = MFI -> isSpillSlotObjectIndex ( FrameIndex ) ? <STR_LIT> : <STR_LIT> ;

MCSymbol * Sym = Ctx . getOrCreateSymbol ( SymName ) ;


<s> int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( STI . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ;

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ;


* clear = build_call_expr ( set_fpsr , <NUM_LIT> , masked_fenv_sr ) ;


<s> MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg ) ;


<s> void visitCallBase ( CallBase & CB ) { if ( CB . getCalledFunction ( ) ) return ; auto * Callee = dyn_cast < Function > ( CB . getCalledOperand ( ) -> stripPointerCasts ( ) ) ; if ( Callee && isLegalToPromote ( CB , Callee ) ) { promoteCall ( CB , Callee ) ;


<s> const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; const std :: string FuncName = Func -> getName ( ) ; char * tmpName = new char [ strlen ( FuncName . c_str ( ) ) + <NUM_LIT> ] ; sprintf ( tmpName , <STR_LIT> , FuncName . c_str ( ) ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( FI ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ; }

else if ( RC == <STR_LIT> ) assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> if ( rl78_far_p ( operands [ <NUM_LIT> ] ) ) { rtx temp_reg = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; emit_move_insn ( temp_reg , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = temp_reg ; did = <NUM_LIT> ; } if ( rl78_far_p ( operands [ <NUM_LIT> ] ) ) { temp_reg = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; did = <NUM_LIT> ; } if ( ! did ) return <NUM_LIT> ; emit_insn ( gen ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( temp_reg ) emit_move_insn ( temp_reg , operands [ <NUM_LIT> ] ) ;


<s> SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { RC = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } const SDValue Ops [ ] = { RC , N -> getOperand ( <NUM_LIT> ) , SubReg0 , N -> getOperand ( <NUM_LIT> ) , SubReg1 } ; ReplaceNode ( N , CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , DL , N -> getValueType ( <NUM_LIT> ) , Ops ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) != <NUM_LIT> || isInlineImmediate ( N ) ) break ; uint64_t Imm ; if ( ConstantFPSDNode * FP = dyn_cast < ConstantFPSDNode > ( N ) ) Imm = FP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; else { ConstantSDNode * C = cast < ConstantSDNode > ( N ) ; Imm = C -> getZExtValue ( ) ; } SDLoc DL ( N ) ; ReplaceNode ( N , buildSMovImm64 ( DL , Imm , N -> getValueType ( <NUM_LIT> ) ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; bool Signed = Opc == <STR_LIT> ; uint32_t OffsetVal = Offset -> getZExtValue ( ) ; uint32_t WidthVal = Width -> getZExtValue ( ) ; ReplaceNode ( N , getBFE32 ( Signed , SDLoc ( N ) , N -> getOperand ( <NUM_LIT> ) , OffsetVal , WidthVal ) ) ; return ; } case <STR_LIT> : { SelectDIV_SCALE ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : { SelectMAD_64_32 ( N ) ; return ; } case <STR_LIT> : case <STR_LIT> : return SelectMUL_LOHI ( N ) ; case <STR_LIT> : { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; N = Lowering . legalizeTargetIndependentNode ( N , * CurDAG ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SelectS_BFE ( N ) ; return ; case <STR_LIT> : SelectBRCOND ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : SelectFMAD_FMA ( N ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void emitDefCFAOffsets ( MachineModuleInfo & MMI , MachineBasicBlock & MBB , DebugLoc dl , const <ISA_LIT>BaseInstrInfo & TII , bool HasFP ) { unsigned CFAOffset = <NUM_LIT> ; for ( auto & Info : Insts ) { if ( HasFP && ! Info . BeforeFPSet ) return ;


<s> lraddr = gen_frame_mem ( Pmode , plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ) ; MEM_VOLATILE_P ( lraddr ) = true ; emit_move_insn ( lraddr , eh_addr ) ;


<s> printDisp ( MI , opNum + <STR_LIT> , O ) ; O << ',' ; printOperand ( MI , opNum + <STR_LIT> , O ) ;


<s> else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ;


<s> rtx insn ; if ( low == high ) insn = emit_insn ( gen_stack_push ( gen_rtx_REG ( SImode , low ) ) ) ;

else insn = emit_insn ( gen_stack_pushm ( GEN_INT ( ( ( high - low ) + <NUM_LIT> ) * UNITS_PER_WORD ) , gen_rx_store_vector ( low , high ) ) ) ;


<s> else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( ) , OpFlag ) ; DebugLoc DL = JT -> getDebugLoc ( ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ;


<s> if ( is_microcoded_insn ( insn ) ) cached_can_issue_more = <NUM_LIT> ; else if ( is_cracked_insn ( insn ) ) cached_can_issue_more = more > <NUM_LIT> ? more - <NUM_LIT> : <NUM_LIT> ; else cached_can_issue_more = more - <NUM_LIT> ; return cached_can_issue_more ; } if ( rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn ( insn ) ) return <NUM_LIT> ; cached_can_issue_more = more - <NUM_LIT> ;


<s> return ( int64x1_t ) __builtin_neon_vpadalsv2si ( __a , __b ) ;


<s> static void sparc_output_deferred_case_vectors ( void ) { rtx t ; int align ; if ( sparc_addr_list == NULL_RTX && sparc_addr_diff_list == NULL_RTX ) return ; switch_to_section ( current_function_section ( ) ) ; align = floor_log2 ( FUNCTION_BOUNDARY / BITS_PER_UNIT ) ; if ( align > <NUM_LIT> ) ASM_OUTPUT_ALIGN ( asm_out_file , align ) ; for ( t = sparc_addr_list ; t ; t = XEXP ( t , <NUM_LIT> ) ) sparc_output_addr_vec ( XEXP ( t , <NUM_LIT> ) ) ;

for ( t = sparc_addr_diff_list ; t ; t = XEXP ( t , <NUM_LIT> ) ) sparc_output_addr_diff_vec ( XEXP ( t , <NUM_LIT> ) ) ;


<s> SmallVector < User * , <NUM_LIT> > LDSUsers ( GV -> users ( ) ) ; for ( auto * U : LDSUsers ) { auto FunctionToInsts = <STR_LIT> ( U , false ) ; for ( auto FI = FunctionToInsts . begin ( ) , FE = FunctionToInsts . end ( ) ; FI != FE ; ++ FI ) { Function * F = FI -> first ; auto & Insts = FI -> second ; for ( auto * I : Insts ) { SmallPtrSet < Instruction * , <NUM_LIT> > UserInsts ; if ( U == I ) { UserInsts . insert ( I ) ; } else { auto * CE = cast < ConstantExpr > ( U ) ; convertConstantExprsToInstructions ( I , CE , & UserInsts ) ; } for ( auto * II : UserInsts ) { auto * ReplaceInst = getReplacementInst ( F , GV , LDSPointer ) ; II -> replaceUsesOfWith ( GV , ReplaceInst ) ;


<s> inline int getProgramMemoryBank ( MemSDNode const * N ) { auto * V = N -> getMemOperand ( ) -> getValue ( ) ;

if ( V == nullptr || ! isProgramMemoryAddress ( V ) ) return - <NUM_LIT> ;


<s> R600InstrInfo :: R600InstrInfo ( AMDGPUTargetMachine & tm ) : AMDGPUInstrInfo ( tm ) , RI ( tm ) , ST ( tm . getSubtarget < AMDGPUSubtarget > ( ) ) {


<s> if ( NumVals != <NUM_LIT> ) { if ( Subtarget -> isGP64bit ( ) && NumVals == <NUM_LIT> && MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; O << '$' << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } return true ; } unsigned RegOp = OpNum ; if ( ! Subtarget -> isGP64bit ( ) ) { switch ( ExtraCode [ <NUM_LIT> ] ) { case 'M' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum + <NUM_LIT> : OpNum ; break ; case 'L' : RegOp = ( Subtarget -> isLittle ( ) ) ? OpNum : OpNum + <NUM_LIT> ; break ; case 'D' : RegOp = OpNum + <NUM_LIT> ; } if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << '$' << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } } case 'w' : break ;


<s> } const <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const GCNSubtarget & STM = MF -> getSubtarget < GCNSubtarget > ( ) ; if ( MFI -> isEntryFunction ( ) && STM . isAmdHsaOrMesa ( MF -> getFunction ( ) ) ) { SmallString < <NUM_LIT> > SymbolName ; getNameWithPrefix ( SymbolName , & MF -> getFunction ( ) ) , getTargetStreamer ( ) -> Emit<ISA_LIT>SymbolType ( SymbolName , ELF :: STT_<ISA_LIT>_HSA_KERNEL ) ; } if ( DumpCodeInstEmitter ) { DisasmLines . push_back ( MF -> getName ( ) . str ( ) + <STR_LIT> ) ; DisasmLineMaxLen = std :: max ( DisasmLineMaxLen , DisasmLines . back ( ) . size ( ) ) ; HexLines . push_back ( <STR_LIT> ) ; } AsmPrinter :: emitFunctionEntryLabel ( ) ;


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ;

dbgs ( ) << <STR_LIT> << Name << <STR_LIT> ;


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI , bool RelaxAll , bool NoExecStack ) { Triple TheTriple ( TT ) ; return create<ISA_LIT>ELFStreamer ( Ctx , MAB , OS , Emitter , RelaxAll , NoExecStack ) ;


<s> explicit <ISA_LIT>16DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>DAGToDAGISel ( TM ) {


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


<s> <ISA_LIT>ELFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > MOW , std :: unique_ptr < MCCodeEmitter > MCE ) : MCELFStreamer ( C , std :: move ( MAB ) , std :: move ( MOW ) , std :: move ( MCE ) ) {


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIdx ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIdx ) ; } else if ( RC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( FrameIdx ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> if ( Ext -> getType ( ) -> isVectorTy ( ) ) return false ; for ( const Use & U : Ext -> uses ( ) ) { const Instruction * Instr = cast < Instruction > ( U . getUser ( ) ) ; switch ( Instr -> getOpcode ( ) ) { case Instruction :: Shl : if ( ! isa < ConstantInt > ( Instr -> getOperand ( <NUM_LIT> ) ) ) return false ; break ; case Instruction :: GetElementPtr : { gep_type_iterator GTI = gep_type_begin ( Instr ) ; auto & DL = Ext -> getModule ( ) -> getDataLayout ( ) ; std :: advance ( GTI , U . getOperandNo ( ) ) ; Type * IdxTy = * GTI ; uint64_t ShiftAmt = countTrailingZeros ( DL . getTypeStoreSizeInBits ( IdxTy ) ) - <NUM_LIT> ; if ( ShiftAmt == <NUM_LIT> || ShiftAmt > <NUM_LIT> ) return false ; break ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMemOpBaseReg ( OperandVector & Operands ) { if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> for ( auto & MOP : MI . operands ( ) ) { if ( MOP . isReg ( ) && ! MOP . isDebug ( ) && MOP . getReg ( ) && ( ! SeenDef || ( MOP . isDef ( ) && MOP . isImplicit ( ) ) ) && TRI -> regsOverlap ( MOP . getReg ( ) , RegToRename ) ) { assert ( ( MOP . isImplicit ( ) || ( MOP . isRenamable ( ) && ! MOP . isEarlyClobber ( ) ) ) && <STR_LIT> ) ; MOP . setReg ( GetMatchingSubReg ( MOP . getReg ( ) ) ) ; SeenDef = true ; } } } else { for ( auto & MOP : MI . operands ( ) ) { if ( MOP . isReg ( ) && ! MOP . isDebug ( ) && MOP . getReg ( ) && TRI -> regsOverlap ( MOP . getReg ( ) , RegToRename ) ) { assert ( ( MOP . isImplicit ( ) || ( MOP . isRenamable ( ) && ! MOP . isEarlyClobber ( ) ) ) && <STR_LIT> ) ; MOP . setReg ( GetMatchingSubReg ( MOP . getReg ( ) ) ) ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return true ; } ; forAllMIsUntilDef ( * I , RegToRename , TRI , LdStLimit , UpdateMIs ) ; for ( auto & MI : iterator_range < MachineInstrBundleIterator < llvm :: MachineInstr >> ( std :: next ( I ) , std :: next ( Paired ) ) ) assert ( all_of ( MI . operands ( ) , [ this , & RenameReg ] ( const MachineOperand & MOP ) { return ! MOP . isReg ( ) || MOP . isDebug ( ) || ! MOP . getReg ( ) || ! TRI -> regsOverlap ( MOP . getReg ( ) , * RenameReg ) ; } ) && <STR_LIT> <STR_LIT> ) ; } MachineBasicBlock :: iterator InsertionPoint = MergeForward ? Paired : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( * Paired ) : getLdStBaseOp ( * I ) ; int Offset = getLdStOffsetOp ( * I ) . getImm ( ) ; int PairedOffset = getLdStOffsetOp ( * Paired ) . getImm ( ) ; bool PairedIsUnscaled = TII -> isUnscaledLdSt ( Paired -> getOpcode ( ) ) ; if ( IsUnscaled != PairedIsUnscaled ) { int MemSize = TII -> getMemScale ( * Paired ) ; if ( PairedIsUnscaled ) { assert ( ! ( PairedOffset % TII -> getMemScale ( * Paired ) ) && <STR_LIT> ) ; PairedOffset /= MemSize ; } else { PairedOffset *= MemSize ; } } MachineInstr * RtMI , * Rt2MI ; if ( Offset == PairedOffset + OffsetStride ) {


<s> static rtx move_to_de ( int opno , rtx_insn * before ) { rtx src = OP ( opno ) ; machine_mode mode = GET_MODE ( src ) ; rtx reg ;

if ( mode == VOIDmode ) mode = recog_data . operand_mode [ opno ] ;


<s> else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; return <NUM_LIT> ; } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ;

BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> return ( insn >> pos ) & ( ( <NUM_LIT> << l ) - <NUM_LIT> ) ;


<s> case CCValAssign :: AExt : case CCValAssign :: ZExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , true ) ) return false ; SrcReg = TmpReg ; break ; } case CCValAssign :: SExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , false ) ) return false ; SrcReg = TmpReg ; break ; } } } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetRegs [ i ] ) . addReg ( SrcReg ) ; } } } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RetRegs [ i ] , RegState :: Implicit ) ; return true ;


<s> bool forceScalarizeMaskedScatter ( VectorType * VTy , Align Alignment ) {

return forceScalarizeMaskedGather ( VTy , Alignment ) ;


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitCOPY_FD ( MachineInstr & MI , MachineBasicBlock * BB ) const { assert ( Subtarget . isFP64bit ( ) ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Fd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ws = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ;


<s> SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI . getShiftAmountTy ( SrcOp . getValueType ( ) ) ) ) ) ;


<s> Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasSSE2 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasInt256 ( ) ) || ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasBWI ( ) ) ) { if ( matchVectorShuffleWithPACK ( MaskVT , SrcVT , V1 , V2 , Shuffle , Mask , DAG , Subtarget ) ) { DstVT = MaskVT ; return true ; } } if ( ( MaskVT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && <NUM_LIT> <= EltSizeInBits && Subtarget . hasAVX ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) { if ( matchVectorShuffleWithUNPCK ( MaskVT , V1 , V2 , Shuffle , IsUnary , Mask , DL , DAG , Subtarget ) ) { SrcVT = DstVT = MaskVT ;

if ( MaskVT . is256BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) SrcVT = DstVT = ( <NUM_LIT> == EltSizeInBits ? <STR_LIT> : <STR_LIT> ) ;


<s> static machine_mode m68k_promote_function_mode ( const_tree type , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree fntype ATTRIBUTE_UNUSED , int for_return ) { if ( type == NULL_TREE && ! for_return && ( mode == QImode || mode == HImode ) ) return SImode ;


<s> op0 = gen_reg_rtx ( GET_MODE ( x ) ) ; emit_move_insn ( op0 , x ) ; } emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , <NUM_LIT> ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ;


<s> LoopRep -> getExitingBlocks ( ExitingMBBs ) ; if ( ExitingMBBs . size ( ) == <NUM_LIT> ) { MachineBasicBlock * DummyExitBlk = normalizeInfiniteLoopExit ( LoopRep ) ; if ( DummyExitBlk ) RetBlks . push_back ( DummyExitBlk ) ; } } for ( SmallVectorImpl < MachineBasicBlock * > :: const_iterator It = OrderedBlks . begin ( ) , E = OrderedBlks . end ( ) ; It != E ; ++ It ) { MachineBasicBlock * MBB = * It ; removeUnconditionalBranch ( MBB ) ;

removeRedundantConditionalBranch ( MBB ) ;


<s> HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = ( IsNonTemporal && HasSSE1 ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; if ( Aligned ) { if ( IsNonTemporal ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; } else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX512 ) ; if ( Aligned ) Opc = IsNonTemporal ? <STR_LIT> : <STR_LIT> ;


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , & GA , <NUM_LIT> ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( N , Ty , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( N , Ty , DAG , Has<ISA_LIT>64 ) ;

if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( ) ) ;


<s> bool <ISA_LIT>TTIImpl :: isRegisterRich ( ) { return true ;


return isInlineImm ( ) || ( isReg ( ) && isRegClass ( AMDGPU :: SReg_32RegClassID ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Idx = ISDOpc - <STR_LIT> ; Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } if ( ! <STR_LIT> ( Imm , RegSize ) ) return <NUM_LIT> ; unsigned ResultReg = fastEmitInst_ri ( Opc , RC , LHSReg , LHSIsKill , <STR_LIT> ( Imm , RegSize ) ) ;

if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> && ISDOpc != <STR_LIT> ) {


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE && <STR_LIT> ) ; int Imm = CE -> getValue ( ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( TLI . verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue RetAddr ; if ( depth == <NUM_LIT> ) { auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned RetReg = MF . addLiveIn ( <STR_LIT> , TLI . getRegClassFor ( PtrVT ) ) ;

RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RetReg , VT ) ;


<s> if ( TII -> isSMRD ( I -> getOpcode ( ) ) ) LastOpcodeType = SMEM ; else if ( Increment . Named . VM ) LastOpcodeType = VMEM ; } if ( Increment . Named . EXP ) { ExpInstrTypesSeen |= I -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = I -> getOperand ( i ) ; if ( ! isOpRelevant ( Op ) ) continue ; const TargetRegisterClass * RC = TII -> getOpRegClass ( * I , i ) ; RegInterval Interval = getRegInterval ( RC , Op ) ; for ( unsigned j = Interval . first ; j < Interval . second ; ++ j ) { if ( Op . isDef ( ) ) DefinedRegs [ j ] = Limit ; if ( Op . isUse ( ) ) UsedRegs [ j ] = Limit ;


<s> bool Changed = false ; for ( auto * DTN : children < MachineDomTreeNode * > ( N ) ) Changed |= removeDeadCode ( DTN ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto I = Instrs . begin ( ) , E = Instrs . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) || ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! R . isVirtual ( ) || ! MRI -> use_nodbg_empty ( R ) ) { AllDead = false ; break ; }


<s> return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ; O << <STR_LIT> ; return ; }

O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << getRegisterName ( MO2 . getReg ( ) ) ;


<s> void addLoc ( const CCValAssign & V ) { Locs . push_back ( V ) ;


<s> break ; } } } if ( ! SDST ) return false ; const Register SDSTReg = SDST -> getReg ( ) ; auto IsHazardFn = [ SDSTReg , TRI ] ( MachineInstr * I ) { return <ISA_LIT>InstrInfo :: isSMRD ( * I ) && I -> readsRegister ( SDSTReg , TRI ) ; } ; auto IsExpiredFn = [ TII , IV ] ( MachineInstr * MI , int ) { if ( MI ) { if ( TII -> isSALU ( * MI ) ) { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : return ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) && ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : { const int64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Decoded = <STR_LIT> ( IV , Imm ) ; return ( Decoded . LgkmCnt == <NUM_LIT> ) ; } default : if ( TII -> isSOPP ( * MI ) ) return false ; return true ; } }


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned Opc = N -> getOpcode ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! VT . isVector ( ) && VT != <STR_LIT> && ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || Subtarget -> hasMin3Max3_16 ( ) ) ) { if ( Op0 . getOpcode ( ) == Opc && Op0 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op1 ) ; } if ( Op1 . getOpcode ( ) == Opc && Op1 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; } } if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , true ) ) return Med3 ; }


<s> if ( isIntrinsicWithCCAndChain ( Op , Opcode , CCValid ) ) { assert ( Op -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; SDNode * Node = emitIntrinsicWithCCAndChain ( DAG , Op , Opcode ) ; SDValue CC = getCCResult ( DAG , SDValue ( Node , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Op . getNode ( ) , <NUM_LIT> ) , CC ) ; return SDValue ( ) ; } return SDValue ( ) ;


<s> gimple * g = gimple_build_assign ( lhs , cmp ) ; gimple_set_location ( g , gimple_location ( stmt ) ) ;


<s> assert ( ( isExtendable ( MI ) || isConstExtended ( MI ) ) && <STR_LIT> ) ; short ExtOpNum = getCExtOpNum ( MI ) ; MachineOperand & MO = MI . getOperand ( ExtOpNum ) ;

assert ( ( MO . isMBB ( ) || MO . isImm ( ) ) && <STR_LIT> ) ;


<s> state_transition ( curr_state , insn ) ; state -> insns_left = targetm . sched . variable_issue ( <NUM_LIT> , false , insn , state -> insns_left ) ; mips_sim_insn = insn ; note_stores ( PATTERN ( insn ) , mips_sim_record_set , state ) ;


<s> unsigned Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ;

return <ISA_LIT>SelectFPExtOrFPTrunc ( I , Opc , & <STR_LIT> ) ;


<s> static DecodeStatus decodeBranch ( MCInst & MI , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { if ( ! tryAddingSymbolicOperand ( Insn + Address , false , Address , <NUM_LIT> , <NUM_LIT> , MI , Decoder ) ) MI . addOperand ( MCOperand :: createImm ( Insn ) ) ;


<s> MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ int64_t ( RequiredAlign - <NUM_LIT> ) ; if ( StartOffset ) { SDLoc DL ( Ptr ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , DL , Ptr . getValueType ( ) ) ) ; } int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PVT , NumElems ) ; SDValue V1 = DAG . getLoad ( NVT , dl , Chain , Ptr , LD -> getPointerInfo ( ) . getWithOffset ( StartOffset ) , false , false , false , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ( NumElems , EltNo ) ;

return DAG . getVectorShuffle ( NVT , dl , V1 , DAG . getUNDEF ( NVT ) , Mask ) ;


<s> CallReturnHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder MIB ) : <ISA_LIT>IncomingValueHandler ( MIRBuilder , MRI ) , MIB ( MIB ) {


<s> static const std :: pair < unsigned , const char * > TargetFlags [ ] = {

{ MO_ABS_HI , <STR_LIT> } , { MO_ABS_LO , <STR_LIT> } , { MO_NO_FLAG , <STR_LIT> } } ;


<s> } else if ( ! SE -> isLoopInvariant ( EC , L ) ) continue ; if ( SE -> getTypeSizeInBits ( EC -> getType ( ) ) > ( TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) ) continue ; bool NotAlways = false ; for ( pred_iterator PI = pred_begin ( L -> getHeader ( ) ) , PIE = pred_end ( L -> getHeader ( ) ) ; PI != PIE ; ++ PI ) { if ( ! L -> contains ( * PI ) ) continue ; if ( ! DT -> dominates ( * I , * PI ) ) { NotAlways = true ; break ; } } if ( NotAlways ) continue ; Instruction * TI = ( * I ) -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { if ( ! BI -> isConditional ( ) ) continue ; CountedExitBranch = BI ; } else continue ; CountedExitBlock = * I ; ExitCount = EC ; break ; } if ( ! CountedExitBlock ) return MadeChange ; BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader || mightUseCTR ( TT , Preheader ) ) Preheader = InsertPreheaderForLoop ( L , this ) ; if ( ! Preheader ) return MadeChange ; DEBUG ( dbgs ( ) << <STR_LIT> << Preheader -> getName ( ) << <STR_LIT> ) ; MadeChange = true ; SCEVExpander SCEVE ( * SE , <STR_LIT> ) ; LLVMContext & C = SE -> getContext ( ) ; Type * CountType = TT . isArch64Bit ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; if ( ! ExitCount -> getType ( ) -> isPointerTy ( ) && ExitCount -> getType ( ) != CountType ) ExitCount = SE -> getZeroExtendExpr ( ExitCount , CountType ) ; ExitCount = SE -> getAddExpr ( ExitCount , SE -> getConstant ( CountType , <NUM_LIT> ) ) ; Value * ECValue = SCEVE . expandCodeFor ( ExitCount , CountType , Preheader -> getTerminator ( ) ) ; IRBuilder < > CountBuilder ( Preheader -> getTerminator ( ) ) ;

Module * M = Preheader -> getParent ( ) -> getParent ( ) ;


<s> checkNeonReplicateArgs ( FromW , ToW ) ;

if ( ToW == <NUM_LIT> && isNEONi64splat ( ) ) return false ;


<s> bool isValidFrameIdx = ( FrameIdx < <ISA_LIT>FrameInfo :: maxFrameOffset ( ) ) ; if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ) ? <STR_LIT> : <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; abort ( ) ; } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( opc ) , DestReg ) , FrameIdx ) ;


if ( HST . isTypeForHVX ( Ty ) ) return Size == static_cast < int > ( HST . getVectorLength ( ) ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & ) const { if ( RC == & <STR_LIT> ) return & <STR_LIT> ; return RC ;


<s> InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } AttributesSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> ) ;


<s> case FrameHelperType :: Epilog : for ( auto NextMI = NextMBBI ; NextMI != MBB . end ( ) ; NextMI ++ ) { if ( NextMI -> readsRegister ( <STR_LIT> , TRI ) ) return false ; } for ( const MachineBasicBlock * SuccMBB : MBB . successors ( ) ) { if ( SuccMBB -> isLiveIn ( <STR_LIT> ) || SuccMBB -> isLiveIn ( <STR_LIT> ) ) return false ; } break ; case FrameHelperType :: EpilogTail : {

if ( NextMBBI == MBB . end ( ) ) return false ;


<s> std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; std :: string Key = CPU + FS ; if ( F . hasMinSize ( ) ) Key += <STR_LIT> ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle , F . hasMinSize ( ) ) ; if ( ! I -> isThumb ( ) && ! I -> has<ISA_LIT>Ops ( ) ) F . getContext ( ) . emitError ( <STR_LIT> + F . getName ( ) + <STR_LIT> <STR_LIT> ) ; } return I . get ( ) ;


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO . getReg ( ) ) << <STR_LIT> ; return false ;


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const {

if ( Subtarget . isABI_N64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ;


<s> O << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> static DecodeStatus DecodeBankedReg ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned R = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned SysM = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ;

if ( ! <STR_LIT> ( ( R << <NUM_LIT> ) | SysM ) ) return MCDisassembler :: Fail ;


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> optForMinSize ( ) || ! BaseKill ) return false ;


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'a' : if ( MI -> getOperand ( OpNum ) . isReg ( ) ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> ; return false ; } case 'c' : if ( ! MI -> getOperand ( OpNum ) . isImm ( ) ) return true ; printNoHashImmediate ( MI , OpNum , O ) ; return false ; case 'P' : case 'q' : printOperand ( MI , OpNum , O ) ;


<s> const MCSubtargetInfo * STI = TM . getMCSubtargetInfo ( ) ; <STR_LIT> ISA = <STR_LIT> ( STI -> getFeatureBits ( ) ) ; TS -> EmitDirectiveHSACodeObjectISA ( ISA . Major , ISA . Minor , ISA . Stepping , <STR_LIT> , <STR_LIT> ) ; TS -> EmitRuntimeMetadata ( M ) ;