<s> assert ( ! BytesAdded && <STR_LIT> ) ; <ISA_LIT>FunctionInfo * AFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; int BccOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; bool isThumb = AFI -> isThumbFunction ( ) || AFI -> isThumb2Function ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! FBB ) { if ( Cond . empty ( ) ) { if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . add ( predOps ( <STR_LIT> ) ) ;

else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getRegBinaryCode ( unsigned reg ) const { switch ( reg ) {


<s> return new <ISA_LIT>TextureIntrinsicsReplacer ( ) ;


<s> case OPT_m33 : c4x_cpu_version = <NUM_LIT> ; return true ; case OPT_m40 : c4x_cpu_version = <NUM_LIT> ; return true ; case OPT_m44 : c4x_cpu_version = <NUM_LIT> ; return true ; case OPT_mcpu_ : if ( arg [ <NUM_LIT> ] == 'c' || arg [ <NUM_LIT> ] == 'C' ) arg ++ ; value = atoi ( arg ) ; switch ( value ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : c4x_cpu_version = value ; return true ; } return false ;


<s> case <STR_LIT> : return expandAtomicRMW128 ( MBB , MI , NMBBI ) ; case <STR_LIT> : return expandAtomicCmpSwap128 ( MBB , MI , NMBBI ) ; case <STR_LIT> : { Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstHi = TRI -> getSubReg ( Dst , <STR_LIT> ) ; Register DstLo = TRI -> getSubReg ( Dst , <STR_LIT> ) ; Register Lo = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Hi = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

PairedCopy ( TII , MBB , MI , MI . getDebugLoc ( ) , DstHi , DstLo , Hi , Lo ) ;


<s> static SDValue performUnpackCombine ( SDNode * N , SelectionDAG & DAG ) { assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return DAG . getUNDEF ( N -> getValueType ( <NUM_LIT> ) ) ;


<s> CCInfo . AnalyzeCallOperands ( Outs , getCCAssignFn ( CalleeCC ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ;

if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> void printT2SOOperand ( const MCInst * MI , unsigned OpNum ) {


<s> for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) ;


<s> } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;

BuildMI ( MBB , MBBI , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> static bool IsChild ( const MachineInstr & MI , const <ISA_LIT>FunctionInfo & MFI ) { if ( MI . getNumOperands ( ) == <NUM_LIT> ) return false ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) || ! MO . isDef ( ) ) return false ; unsigned Reg = MO . getReg ( ) ; return TargetRegisterInfo :: isVirtualRegister ( Reg ) && MFI . isVRegStackified ( Reg ) ;


<s> virtual void emit<ISA_LIT>RegisterIgnore ( unsigned reg ) {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3OpSel0 ( SDValue In , SDValue & Src , SDValue & SrcMods , SDValue & Clamp ) const { SDLoc SL ( In ) ; Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;

return SelectVOP3OpSel ( In , Src , SrcMods ) ;


<s> if ( test_hard_reg_class ( ADDW_REGS , SET_SRC ( PATTERN ( insn ) ) ) ) { if ( l ) * l = <NUM_LIT> ; return AS2 ( sbiw , % <NUM_LIT> , <NUM_LIT> ) ; } if ( l ) * l = <NUM_LIT> ; return ( AS2 ( cp , % A0 , __zero_reg__ ) CR_TAB AS2 ( cpc , % B0 , __zero_reg__ ) ) ;


<s> for ( MCAssembler :: iterator I = Asm . begin ( ) , E = Asm . end ( ) ; I != E ; ++ I ) { Asm . writeSectionData ( & * I , Layout ) ; }


<s> assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( canWidenShuffleElements ( Mask , WidenedMask ) ) return lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { if ( isSingleInputShuffleMask ( Mask ) ) { int PSHUFDMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) {

PSHUFDMask [ <NUM_LIT> * i ] = <NUM_LIT> * RepeatedMask [ i ] ;


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned Value = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ; Value -= Offset ;


<s> unsigned VGPRLimit = getNumVGPRsAllowed ( STI . getMaxWavesPerCU ( ) ) ; unsigned VSLimit = SGPRLimit + VGPRLimit ; for ( regclass_iterator I = regclass_begin ( ) , E = regclass_end ( ) ; I != E ; ++ I ) { const TargetRegisterClass * RC = * I ; unsigned NumSubRegs = std :: max ( ( int ) RC -> getSize ( ) / <NUM_LIT> , <NUM_LIT> ) ; unsigned Limit ;


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups ) ; unsigned InvBit = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups ) ;

return ( InvBit << <NUM_LIT> ) | RegBits ;


<s> return std :: pair < unsigned , unsigned > ( ( ( Sel >> <NUM_LIT> ) - <NUM_LIT> ) >> <NUM_LIT> , ( ( ( ( Sel >> <NUM_LIT> ) - <NUM_LIT> ) & <NUM_LIT> ) >> <NUM_LIT> ) << <NUM_LIT> ) ;


<s> bool <ISA_LIT>FastISel :: SelectFPExt ( const Instruction * I ) { Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ;


<s> getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { s32 , p0 } , { s1 } ) ; auto & LoadStoreBuilder = getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemDesc ( { { s1 , p0 , <NUM_LIT> , <NUM_LIT> } , { s8 , p0 , <NUM_LIT> , <NUM_LIT> } , { s16 , p0 , <NUM_LIT> , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> , <NUM_LIT> } , { p0 , p0 , <NUM_LIT> , <NUM_LIT> } } ) ; auto & PhiBuilder = getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { s32 , p0 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_BRCOND ) . legalFor ( { s1 } ) ; if ( ST . isThumb ( ) ) { computeTables ( ) ; verify ( * ST . getInstrInfo ( ) ) ; return ; } getActionDefinitionsBuilder ( G_GLOBAL_VALUE ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; if ( ST . hasV5TOps ( ) ) { getActionDefinitionsBuilder ( G_CTLZ ) . legalFor ( { s32 , s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_CTLZ_ZERO_UNDEF ) . lowerFor ( { s32 , s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; } else { getActionDefinitionsBuilder ( G_CTLZ_ZERO_UNDEF ) . libcallFor ( { s32 , s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_CTLZ ) . lowerFor ( { s32 , s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; } if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FCONSTANT , G_FNEG } ) . legalFor ( { s32 , s64 } ) ; LoadStoreBuilder . legalFor ( { { s64 , p0 } } ) ; PhiBuilder . legalFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalForCartesianProduct ( { s1 } , { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_MERGE_VALUES ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_UNMERGE_VALUES ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( { G_FPTOSI , G_FPTOUI } ) . legalForCartesianProduct ( { s32 } , { s32 , s64 } ) ;

getActionDefinitionsBuilder ( { G_SITOFP , G_UITOFP } ) . legalForCartesianProduct ( { s32 , s64 } , { s32 } ) ;


for ( const <ISA_LIT>Exception * CurException = ParentException ;


initialize<ISA_LIT>LowerAggrCopiesPass ( PR ) ;


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override {


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target32 ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>Target64 ( ) ) ;


<s> return isPredicateSetter ( MI -> getOpcode ( ) ) ;


if ( ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) ) {


<s> unsigned <ISA_LIT>MCCodeEmitter :: getHWydeOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const {

return getLabelOpValue ( Inst , OpNo , Fixups , SubtargetInfo , static_cast < MCFixupKind > ( <STR_LIT> ) ) ;


<s> if ( CONST_INT_P ( op [ opc ] ) ) { machine_mode vmode = insn_data [ icode ] . operand [ opc - <NUM_LIT> ] . mode ; unsigned int nunits = GET_MODE_NUNITS ( vmode ) . to_constant ( ) ; aarch64_simd_lane_bounds ( op [ opc ] , <NUM_LIT> , nunits , exp ) ; op [ opc ] = aarch64_endian_lane_rtx ( vmode , INTVAL ( op [ opc ] ) ) ; } case SIMD_ARG_CONSTANT : constant_arg : if ( ! ( * insn_data [ icode ] . operand [ opc ] . predicate ) ( op [ opc ] , mode ) ) { error ( <STR_LIT> , exp , opc + <NUM_LIT> - have_retval ) ; return const0_rtx ; } break ; case SIMD_ARG_STOP : gcc_unreachable ( ) ; } opc ++ ; } } switch ( opc ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> :

pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ;


<s> if ( <ISA_LIT>MCInstrInfo :: isVector ( MCII , Inst ) ) { ++ VOffset ; } if ( <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , Inst ) ) DefReg1 = <ISA_LIT>MCInstrInfo :: getNewValueOperand ( MCII , Inst ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , Inst ) ) DefReg2 = <ISA_LIT>MCInstrInfo :: getNewValueOperand2 ( MCII , Inst ) . getReg ( ) ; if ( ! RegisterMatches ( UseReg , DefReg1 , DefReg2 ) ) { continue ; } if ( ! <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , Inst ) ) { break ; } assert ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MI ) && <STR_LIT> ) ; if ( <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , Inst ) == <ISA_LIT>MCInstrInfo :: isPredicatedTrue ( MCII , MI ) ) break ; } unsigned Offset = <ISA_LIT>MCInstrInfo :: isVector ( MCII , MI ) ? VOffset : SOffset ; Offset <<= <NUM_LIT> ; Offset |= <ISA_LIT>MCInstrInfo :: SubregisterBit ( UseReg , DefReg1 , DefReg2 ) ; return Offset ;


<s> static bool isLdOffsetInRangeOfSt ( MachineInstr * LoadInst , MachineInstr * StoreInst ) { assert ( isMatchingStore ( LoadInst , StoreInst ) && <STR_LIT> ) ; int LoadSize = getMemScale ( LoadInst ) ; int StoreSize = getMemScale ( StoreInst ) ; int UnscaledStOffset = isUnscaledLdSt ( StoreInst ) ? getLdStOffsetOp ( StoreInst ) . getImm ( ) : getLdStOffsetOp ( StoreInst ) . getImm ( ) * StoreSize ; int UnscaledLdOffset = isUnscaledLdSt ( LoadInst ) ? getLdStOffsetOp ( LoadInst ) . getImm ( ) : getLdStOffsetOp ( LoadInst ) . getImm ( ) * LoadSize ;

return ( UnscaledStOffset <= UnscaledLdOffset ) && ( UnscaledLdOffset + LoadSize <= ( UnscaledStOffset + StoreSize ) ) ;


<s> SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * FBB = nullptr , * TBB = nullptr ; if ( analyzeBranch ( MBB , TBB , FBB , Cond , AllowModify ) ) return true ;


<s> any = true ; break ; } if ( ! any ) return ; dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i < SchedModel -> getNumProcResourceKinds ( ) ; ++ i ) if ( ProcResourceCounters [ i ] > <NUM_LIT> ) { dbgs ( ) << <STR_LIT> << SchedModel -> getProcResource ( i ) -> Name << <STR_LIT> << ProcResourceCounters [ i ] << <STR_LIT> ; any = true ;


<s> } else if ( GET_CODE ( op ) == MEM ) { output_address ( XEXP ( op , <NUM_LIT> ) ) ; if ( letter == 'd' && ! TARGET_68020 && CONSTANT_ADDRESS_P ( XEXP ( op , <NUM_LIT> ) ) && ! ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( op , <NUM_LIT> ) ) < <NUM_LIT> && INTVAL ( XEXP ( op , <NUM_LIT> ) ) >= - <NUM_LIT> ) ) fprintf ( file , MOTOROLA ? <STR_LIT> : <STR_LIT> ) ; } else if ( GET_CODE ( op ) == CONST_DOUBLE && GET_MODE ( op ) == SFmode ) { REAL_VALUE_TYPE r ; long l ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , l ) ; asm_fprintf ( file , <STR_LIT> , l & <NUM_LIT> ) ; } else if ( GET_CODE ( op ) == CONST_DOUBLE && GET_MODE ( op ) == XFmode ) { REAL_VALUE_TYPE r ; long l [ <NUM_LIT> ] ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_LONG_DOUBLE ( r , l ) ; asm_fprintf ( file , <STR_LIT> , l [ <NUM_LIT> ] & <NUM_LIT> , l [ <NUM_LIT> ] & <NUM_LIT> , l [ <NUM_LIT> ] & <NUM_LIT> ) ; } else if ( GET_CODE ( op ) == CONST_DOUBLE && GET_MODE ( op ) == DFmode ) {


<s> return ( MI -> getDesc ( ) . TSFlags & is_bside ) >> side_shift ;


<s> if ( len == <NUM_LIT> ) return AARCH64_PARSE_MISSING_ARG ; for ( cpu = all_cores ; cpu -> name != NULL ; cpu ++ ) { if ( strlen ( cpu -> name ) == len && strncmp ( cpu -> name , str , len ) == <NUM_LIT> ) { unsigned long isa_temp = cpu -> flags ; if ( ext != NULL ) { enum aarch64_parse_opt_result ext_res = aarch64_parse_extension ( ext , & isa_temp ) ; if ( ext_res != AARCH64_PARSE_OK ) return ext_res ; } * res = cpu ; * isa_flags = isa_temp ; return AARCH64_PARSE_OK ;


<s> O << '#' << FP -> getValueAPF ( ) . convertToDouble ( ) ; if ( isVerbose ( ) ) {

O
<<
<STR_LIT>
<<
MAI
->
getCommentString
(
)
<<
' '
;


<s> Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success ;


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> const bool HasVIndex = MI . getNumOperands ( ) == NumVIndexOps ; Register VIndex ; if ( HasVIndex ) { VIndex = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; ++ OpOffset ; } Register VOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; Register SOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; unsigned AuxiliaryData = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) ; MachineMemOperand * MMO = * MI . memoperands_begin ( ) ; unsigned ImmOffset ; unsigned TotalOffset ; std :: tie ( VOffset , ImmOffset , TotalOffset ) = splitBufferOffsets ( B , VOffset ) ; if ( TotalOffset != <NUM_LIT> ) MMO = B . getMF ( ) . getMachineMemOperand ( MMO , TotalOffset , MMO -> getSize ( ) ) ; if ( ! VIndex ) VIndex = B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; auto MIB = B . buildInstr ( getBufferAtomicPseudo ( IID ) ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> return __builtin_mve_vhcaddq_rot270_m_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a , __b , __p ) ;


<s> bool isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const override { return true ;


<s> AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = nullptr ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; UseDataRegionDirectives = MarkedJTDataRegions ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( T . isMacOSX ( ) && T . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) HasWeakDefCanBeHiddenDirective = false ; DwarfFDESymbolsUseAbsDiff = true ; UseIntegratedAssembler = true ;


<s> expand_float ( xa , xi , <NUM_LIT> ) ; if ( HONOR_SIGNED_ZEROS ( mode ) ) ix86_sse_copysign_to_positive ( xa , xa , res , mask ) ; emit_move_insn ( res , xa ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ;


<s> <ISA_LIT>MCAsmInfoCOFF :: <ISA_LIT>MCAsmInfoCOFF ( const Triple & Triple ) {


<s> Parser . Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( Val == <NUM_LIT> ) { if ( ! hasThumb ( ) ) return Error ( L , <STR_LIT> ) ; if ( ! isThumb ( ) ) SwitchMode ( ) ; getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code16 ) ; } else { if ( ! has<ISA_LIT> ( ) ) return Error ( L , <STR_LIT> ) ;


<s> EVT VT = Op . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; bool CanFoldLoad = false ; if ( MayFoldVectorLoad ( V2 ) ) CanFoldLoad = true ; if ( MayFoldVectorLoad ( V1 ) && MayFoldIntoStore ( Op ) ) CanFoldLoad = true ; if ( MayFoldVectorLoad ( V1 ) && MayFoldVectorLoad ( V2 ) ) CanFoldLoad = false ; if ( CanFoldLoad ) {

if ( HasXMMInt && NumElems == <NUM_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ;


<s> <ISA_LIT>TargetLowering :: ~ <ISA_LIT>TargetLowering ( ) {


<s> NewMBB -> transferSuccessors ( ThisMBB ) ; ThisMBB -> addSuccessor ( NewBRTarget , ProbToNewTarget ) ; ThisMBB -> addSuccessor ( NewMBB , ProbToNewTarget . getCompl ( ) ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( NewBROpcode ) ) . addReg ( BSI . SplitCond -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NewBRTarget ) ; BuildMI ( * ThisMBB , ThisMBB -> end ( ) , BSI . SplitBefore -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewMBB ) ; if ( BSI . MIToDelete ) BSI . MIToDelete -> eraseFromParent ( ) ; auto FirstTerminator = NewMBB -> getFirstTerminator ( ) ; if ( BSI . NewCond ) { assert ( FirstTerminator -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; FirstTerminator -> getOperand ( <NUM_LIT> ) . setReg ( BSI . NewCond -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( BSI . InvertOrigBranch ) FirstTerminator -> setDesc ( TII -> get ( InvertedOpcode ) ) ; for ( auto * Succ : NewMBB -> successors ( ) ) { updatePHIs ( Succ , ThisMBB , NewMBB , MRI ) ; } addIncomingValuesToPHIs ( NewBRTarget , ThisMBB , NewMBB , MRI ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ThisMBB -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; NewMBB -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; NewBRTarget -> dump ( ) ) ;


<s> CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ i ] . Flags . isByVal ( ) ) { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; int Size = Ins [ i ] . Flags . getByValSize ( ) ; unsigned NumRegs = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned FrameIdx = MFI -> CreateFixedObject ( <NUM_LIT> * NumRegs , VA . getLocMemOffset ( ) , false ) ; SDValue FrameIdxN = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; InVals . push_back ( FrameIdxN ) ; continue ; } if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; SDValue ArgValue ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> || RegVT . is64BitVector ( ) ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> || RegVT . is128BitVector ( ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: AExt : case CCValAssign :: SExt : case CCValAssign :: ZExt : assert ( RegVT == Ins [ i ] . VT && <STR_LIT> ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ArgOffset = VA . getLocMemOffset ( ) ; unsigned ArgSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; uint32_t BEAlign = <NUM_LIT> ; if ( ! Subtarget -> isLittleEndian ( ) && ArgSize < <NUM_LIT> && ! Ins [ i ] . Flags . isInConsecutiveRegs ( ) ) BEAlign = <NUM_LIT> - ArgSize ; int FI = MFI -> CreateFixedObject ( ArgSize , ArgOffset + BEAlign , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue ArgValue ; <STR_LIT> ExtType = <STR_LIT> ; MVT MemVT = VA . getValVT ( ) ; switch ( VA . getLocInfo ( ) ) { default : break ; case CCValAssign :: BCvt : MemVT = VA . getLocVT ( ) ; break ; case CCValAssign :: SExt : ExtType = <STR_LIT> ; break ; case CCValAssign :: ZExt :


<s> other_roots = other_forest -> m_roots ; for ( other_root_iter = other_roots -> begin ( ) ; other_root_iter != other_roots -> end ( ) ; other_root_iter ++ ) ( * other_root_iter ) -> set_forest ( this ) ; this -> m_globals -> remove_forest ( other_forest ) ; this -> m_roots -> splice ( this -> m_roots -> begin ( ) , * other_roots ) ;


if ( Opc == Instruction :: Shl || Opc == Instruction :: LShr ) return Op != I -> getOperand ( <NUM_LIT> ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Immediate ) ;


<s> if ( RS && ! FrameIndexVirtualScavenging ) RS -> enterBasicBlock ( BB ) ; bool InsideCallSequence = false ; for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ) { if ( I -> getOpcode ( ) == FrameSetupOpcode || I -> getOpcode ( ) == FrameDestroyOpcode ) { InsideCallSequence = ( I -> getOpcode ( ) == FrameSetupOpcode ) ; SPAdj += TII . getSPAdjust ( I ) ; MachineBasicBlock :: iterator PrevI = BB -> end ( ) ; if ( I != BB -> begin ( ) ) PrevI = std :: prev ( I ) ; TFI -> eliminateCallFramePseudoInstr ( Fn , * BB , I ) ; if ( PrevI == BB -> end ( ) ) I = BB -> begin ( ) ; else I = std :: next ( PrevI ) ; continue ; } MachineInstr * MI = I ; bool DoIncr = true ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ; if ( MI -> isDebugValue ( ) ) { assert ( i == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; unsigned Reg ; MachineOperand & Offset = MI -> getOperand ( <NUM_LIT> ) ; Offset . setImm ( Offset . getImm ( ) + TFI -> getFrameIndexReference ( Fn , MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) , Reg ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToRegister ( Reg , false ) ; continue ; } if ( MI -> getOpcode ( ) == TargetOpcode :: STATEPOINT ) { assert ( ( ! MI -> isDebugValue ( ) || i == <NUM_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned Reg ; MachineOperand & Offset = MI -> getOperand ( i + <NUM_LIT> ) ; const unsigned refOffset = TFI -> getFrameIndexReferenceFromSP ( Fn , MI -> getOperand ( i ) . getIndex ( ) , Reg ) ; Offset . setImm ( Offset . getImm ( ) + refOffset ) ; MI -> getOperand ( i ) . ChangeToRegister ( Reg , false ) ; continue ; } bool AtBeginning = ( I == BB -> begin ( ) ) ; if ( ! AtBeginning ) -- I ; TRI . eliminateFrameIndex ( MI , SPAdj , i , FrameIndexVirtualScavenging ? nullptr : RS ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const {


<s> } else BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BalTgtMBB -> rbegin ( ) -> bundleWithPred ( ) ; } else { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . has<ISA_LIT>64r6 ( ) ) BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> case <STR_LIT> : CC = <STR_LIT> ; std :: swap ( LHS , RHS ) ; return true ; case <STR_LIT> : CC = <STR_LIT> ; std :: swap ( LHS , RHS ) ; return true ; case <STR_LIT> : CC = <STR_LIT> ; std :: swap ( LHS , RHS ) ; return true ; case <STR_LIT> : CC = <STR_LIT> ; return true ; }


<s> MCAsmParser & Parser = getParser ( ) ; if ( ! Parser . getTok ( ) . getString ( ) . equals_lower ( <STR_LIT> ) || ! Parser . getLexer ( ) . peekTok ( ) . getString ( ) . equals_lower ( <STR_LIT> ) ) return true ; SMLoc S = getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; Parser . Lex ( ) ; S = getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , S , getContext ( ) ) ) ; Parser . Lex ( ) ; return false ;


<s> <ISA_LIT>CollectLOH ( ) : MachineFunctionPass ( ID ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default :


<s> bool <ISA_LIT>InstrInfo :: unfoldMemoryOperand ( SelectionDAG & DAG , SDNode * N , SmallVectorImpl < SDNode * > & NewNodes ) const {


<s> x = XVECEXP ( vals , <NUM_LIT> , i ) ; if ( ! CONSTANT_P ( x ) ) ++ n_var , one_var = i ; if ( i > <NUM_LIT> && ! rtx_equal_p ( x , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) all_same = false ; } if ( n_var == <NUM_LIT> ) { rtx constant = neon_make_constant ( vals ) ; if ( constant != NULL_RTX ) { emit_move_insn ( target , constant ) ; return ; } } if ( all_same && GET_MODE_SIZE ( inner_mode ) <= <NUM_LIT> ) { x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( target , gen_vec_duplicate ( mode , x ) ) ) ; return ; } if ( n_var == <NUM_LIT> ) { rtx copy = copy_rtx ( vals ) ; rtx index = GEN_INT ( one_var ) ; XVECEXP ( copy , <NUM_LIT> , one_var ) = XVECEXP ( vals , <NUM_LIT> , ( one_var + <NUM_LIT> ) % n_elts ) ; neon_expand_vector_init ( target , copy ) ; x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , <NUM_LIT> , one_var ) ) ; switch ( mode ) { case E_V8QImode : emit_insn ( gen_neon_vset_lanev8qi ( target , x , target , index ) ) ; break ; case E_V16QImode : emit_insn ( gen_neon_vset_lanev16qi ( target , x , target , index ) ) ; break ; case E_V4HImode : emit_insn ( gen_neon_vset_lanev4hi ( target , x , target , index ) ) ; break ; case E_V8HImode : emit_insn ( gen_neon_vset_lanev8hi ( target , x , target , index ) ) ; break ; case E_V2SImode : emit_insn ( gen_neon_vset_lanev2si ( target , x , target , index ) ) ; break ; case E_V4SImode : emit_insn ( gen_neon_vset_lanev4si ( target , x , target , index ) ) ; break ; case E_V2SFmode : emit_insn ( gen_neon_vset_lanev2sf ( target , x , target , index ) ) ; break ; case E_V4SFmode : emit_insn ( gen_neon_vset_lanev4sf ( target , x , target , index ) ) ; break ; case E_V2DImode : emit_insn ( gen_neon_vset_lanev2di ( target , x , target , index ) ) ; break ;


<s> bool First = true ; for ( MVT Type : Types ) { if ( First ) First = false ;


<s> getBufferStoreOpcode ( Ty , MemSize , Offen ) ; if ( Opc == - <NUM_LIT> ) return false ; MachineInstrBuilder MIB = B . buildInstr ( Opc ) . addUse ( VData ) ; if ( Offen ) MIB . addUse ( VOffset ) ;

MIB . addUse ( RSrc ) . addUse ( SOffset ) . addImm ( ImmOffset ) . addImm ( extractGLC ( AuxiliaryData ) ) . addImm ( extractSLC ( AuxiliaryData ) ) . addImm ( <NUM_LIT> ) . addImm ( extractDLC ( AuxiliaryData ) ) . addImm ( extractSWZ ( AuxiliaryData ) ) . addMemOperand ( MMO ) ;


<s> return ( uint8x8_t ) ( __a < __b ) ;


<s> if ( TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p ( x ) ) return false ; if ( TARGET_CMODEL_LARGE && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; if ( TARGET_CMODEL_MEDIUM && ( NDS32_SYMBOL_REF_RODATA_P ( x ) || CONSTANT_POOL_ADDRESS_P ( x ) ) && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; return true ; case CONST : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) { rtx plus_op = XEXP ( x , <NUM_LIT> ) ; rtx op0 = XEXP ( plus_op , <NUM_LIT> ) ; rtx op1 = XEXP ( plus_op , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == SYMBOL_REF && CONST_INT_P ( op1 ) ) { if ( flag_pic || SYMBOL_REF_TLS_MODEL ( op0 ) ) return false ; if ( TARGET_CMODEL_LARGE && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; if ( TARGET_CMODEL_MEDIUM && NDS32_SYMBOL_REF_RODATA_P ( op0 ) && ( reload_completed || reload_in_progress || lra_in_progress ) ) return false ; return true ; } } return false ; case POST_MODIFY : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) { rtx plus_op = XEXP ( x , <NUM_LIT> ) ; rtx op0 = XEXP ( plus_op , <NUM_LIT> ) ; rtx op1 = XEXP ( plus_op , <NUM_LIT> ) ; if ( nds32_address_register_rtx_p ( op0 , strict ) && nds32_legitimate_index_p ( mode , op1 , strict ) ) return true ; else return false ; } return false ; case POST_INC : case POST_DEC : if ( nds32_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; else return false ; case PLUS : if ( nds32_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict ) && nds32_legitimate_index_p ( mode , XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; else if ( nds32_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict ) && nds32_legitimate_index_p ( mode , XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; else return false ; case LO_SUM : { rtx sym = NULL_RTX ;


<s> bool isMOVNMovAlias ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue ( ) ;

for ( int MOVZShift = <NUM_LIT> ; MOVZShift <= <NUM_LIT> ; MOVZShift += <NUM_LIT> ) if ( ( Value & ~ ( <NUM_LIT> << MOVZShift ) ) == <NUM_LIT> ) return false ;


<s> static rtx ia64_function_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { return ia64_function_arg_1 ( cum , mode , type , named , false ) ;


<s> <ISA_LIT>MulMulBugFix ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>MulMulBugFixPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> const auto & MFI = MF . getFrameInfo ( ) ; return ObjectOffset + MFI . getStackSize ( ) ;


<s> return ( __m64 ) __builtin_ia32_pabsw ( ( __v4hi ) __X ) ;


<s> assert ( GV -> getVisibility ( ) == GlobalValue :: DefaultVisibility && <STR_LIT> ) ; LinkageAttr = MCSA_LGlobal ; break ; case GlobalValue :: AppendingLinkage : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: CommonLinkage : llvm_unreachable ( <STR_LIT> ) ; } assert ( LinkageAttr != MCSA_Invalid && <STR_LIT> ) ; MCSymbolAttr VisibilityAttr = MCSA_Invalid ; if ( ! TM . getIgnoreXCOFFVisibility ( ) ) { switch ( GV -> getVisibility ( ) ) { case GlobalValue :: DefaultVisibility : break ;


<s> static rtx_insn * emit_frame_insn ( rtx x ) {


<s> bool i386_pe_type_dllexport_p ( tree decl ) { gcc_assert ( TREE_CODE ( decl ) == VAR_DECL || TREE_CODE ( decl ) == FUNCTION_DECL ) ;

if ( TREE_CODE ( TREE_TYPE ( decl ) ) == METHOD_TYPE && DECL_ARTIFICIAL ( decl ) && ! DECL_THUNK_P ( decl ) ) return false ;


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; if ( <STR_LIT> -> contains ( Reg ) ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; }

if ( TFI -> hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo ::


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module & M ) {

OutStreamer . SwitchSection ( OutContext . getObjectFileInfo ( ) -> getTextSection ( ) ) ;


<s> arg_count ++ ; idx = arg_count - ! nonvoid ; insn_op = & insn_data [ icode ] . operand [ idx ] ; op [ arg_count ] = expand_normal ( arg ) ; if ( code == SPARC_BUILTIN_LDFSR || code == SPARC_BUILTIN_STFSR ) { if ( ! address_operand ( op [ arg_count ] , SImode ) ) { op [ arg_count ] = convert_memory_address ( Pmode , op [ arg_count ] ) ; op [ arg_count ] = copy_addr_to_reg ( op [ arg_count ] ) ;


<s> int argc ; __splimit = d0 ; argc = fp [ <NUM_LIT> ] ; argv = ( char * * ) & fp [ <NUM_LIT> ] ; environ = & argv [ argc + <NUM_LIT> ] ;


<s> enum arc_function_type arc_compute_function_type ( struct function * fun ) { tree decl = fun -> decl ; tree a ; enum arc_function_type fn_type = fun -> machine -> fn_type ; if ( fn_type != ARC_FUNCTION_UNKNOWN ) return fn_type ; fn_type = ARC_FUNCTION_NORMAL ; for ( a = DECL_ATTRIBUTES ( decl ) ; a ; a = TREE_CHAIN ( a ) ) { tree name = TREE_PURPOSE ( a ) , args = TREE_VALUE ( a ) ; if ( name == get_identifier ( <STR_LIT> ) && list_length ( args ) == <NUM_LIT> && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST ) { tree value = TREE_VALUE ( args ) ; if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) || ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type = ARC_FUNCTION_ILINK1 ; else if ( ! strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) fn_type = ARC_FUNCTION_ILINK2 ; else gcc_unreachable ( ) ; break ; } } return fun -> machine -> fn_type = fn_type ;


<s> gcc_assert ( DECL_P ( * node ) ) ; if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ;


<s> if ( ! ( ( __eax ^ __ebx ) & <NUM_LIT> ) ) return <NUM_LIT> ; __cpuid ( __ext , __eax , __ebx , __ecx , __edx ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {


<s> const char * fnname ; long fsiz = current_frame_info . total_size ; fnname = XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ! flag_inhibit_size_directive ) { fputs ( <STR_LIT> , file ) ; if ( interrupt_handler && strcmp ( INTERRUPT_HANDLER_NAME , fnname ) ) fputs ( <STR_LIT> , file ) ; else if ( break_handler && strcmp ( BREAK_HANDLER_NAME , fnname ) ) fputs ( <STR_LIT> , file ) ; else if ( fast_interrupt && strcmp ( FAST_INTERRUPT_NAME , fnname ) ) fputs ( <STR_LIT> , file ) ; else assemble_name ( file , fnname ) ; fputs ( <STR_LIT> , file ) ; if ( ! microblaze_is_interrupt_variant ( ) ) ASM_OUTPUT_TYPE_DIRECTIVE ( file , fnname , <STR_LIT> ) ;


<s> if ( op == <STR_LIT> || op == <STR_LIT> || op == <STR_LIT> || op == <STR_LIT> || op == <STR_LIT> || op == <STR_LIT> || op == <STR_LIT> || op == <STR_LIT> || op == <STR_LIT> || op == <STR_LIT> || op == <STR_LIT> || op == <STR_LIT> ) return false ; return true ;


<s> else if ( reg_unused_after ( insn , op [ <NUM_LIT> ] ) && compare_eq_p ( insn ) ) { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ;


<s> MachineFunction & MF = B . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; unsigned TypeSize = DL . getTypeStoreSize ( ParamTy ) ; Register PtrReg = lowerParameterPtr ( B , ParamTy , Offset ) ;

MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , TypeSize , Align ) ;


<s> return ( int64x2_t ) __builtin_aarch64_ssubwv2si ( __a , __b ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> SGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & <STR_LIT> ) ; VGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & <STR_LIT> ) ; <ISA_LIT>MachineFunctionInfo & MFI = * MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; TargetOccupancy = MFI . getOccupancy ( ) ; SGPRCriticalLimit = std :: min ( ST . getMaxNumSGPRs ( TargetOccupancy , true ) , SGPRExcessLimit ) ; VGPRCriticalLimit = std :: min ( ST . getMaxNumVGPRs ( TargetOccupancy ) , VGPRExcessLimit ) ;

SGPRCriticalLimit = std :: min ( SGPRCriticalLimit - ErrorMargin , SGPRCriticalLimit ) ;


<s> pandn_sb ( int8x8_t s , int8x8_t t ) { return __builtin_loongson_pandn_sb ( s , t ) ;


<s> if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( pos ) ) ; Inst . addOperand ( MCOperand :: createImm ( width ) ) ; Inst . addOperand ( MCOperand :: createImm ( const4 ) ) ; status = DecodeOperandRegister ( Inst , s1 , Address , Decoder ) ;


<s> if ( VT == <STR_LIT> ) { RefinementSteps = <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ; }


<s> unsigned <ISA_LIT>FrameLowering :: getInitialCFARegister ( const MachineFunction & MF ) const {

return TRI -> getDwarfRegNum ( StackPtr , true ) ;


<s> } RTLIB :: Libcall LC ; LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ;


<s> switch ( code ) { case REG : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; break ; case MEM : if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ; else output_address ( mode , XEXP ( op , <NUM_LIT> ) ) ; break ; default : if ( letter == 'z' && op == CONST0_RTX ( GET_MODE ( op ) ) ) fputs ( reg_names [ GP_REG_FIRST ] , file ) ; else if ( letter && letter != 'z' ) output_operand_lossage ( <STR_LIT> , letter ) ;

else output_addr_const ( file , riscv_strip_unspec_address ( op ) ) ;


<s> AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ;


<s> return _mm_set_epi64 ( __A , __A ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> static bool isSafeTruncation ( int64_t Val , unsigned Size ) { return isUIntN ( Size , Val ) || isIntN ( Size , Val ) ;


<s> auto * Symbols = static_cast < SectionSymbolsTy * > ( DisInfo ) ; if ( ! Symbols ) return false ; auto Result = std :: find_if ( Symbols -> begin ( ) , Symbols -> end ( ) , [ Value ] ( const SymbolInfoTy & Val ) { return Val . Addr == static_cast < uint64_t > ( Value ) && Val . Type == ELF :: STT_NOTYPE ; } ) ; if ( Result != Symbols -> end ( ) ) { auto * Sym = Ctx . getOrCreateSymbol ( Result -> Name ) ; const auto * Add = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Inst . addOperand ( MCOperand :: createExpr ( Add ) ) ; return true ; }


<s> rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; int form_int ; enum rtx_code code ; if ( TREE_CODE ( form ) != INTEGER_CST ) { error ( <STR_LIT> ) ; return const0_rtx ; } else form_int = TREE_INT_CST_LOW ( form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , SImode ) ) target = gen_reg_rtx ( SImode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> const Register Reg = Register :: index2VirtReg ( I ) ; const TargetRegisterClass * RC = MRI . getRegClassOrNull ( Reg ) ; if ( RC && <ISA_LIT>RegisterInfo :: isAGPRClass ( RC ) ) { UsesAGPRs = true ; return true ; } else if ( ! RC && ! MRI . use_empty ( Reg ) && MRI . getType ( Reg ) . isValid ( ) ) { return true ; } } for ( MCRegister Reg : <STR_LIT> ) {


<s> MachineBasicBlock :: iterator Pre = MBB -> begin ( ) ; MachineBasicBlock :: iterator E = MBB -> end ( ) ; MachineBasicBlock :: iterator It = Pre ; while ( It != E ) { if ( Pre -> getOpcode ( ) == AMDGPU :: CONTINUE && It -> getOpcode ( ) == AMDGPU :: ENDLOOP ) ContInstr . push_back ( Pre ) ; Pre = It ; ++ It ; }

for ( unsigned i = <NUM_LIT> ; i < ContInstr . size ( ) ; ++ i ) ContInstr [ i ] -> eraseFromParent ( ) ;


<s> auto * C1 = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ; Instruction * I = AI -> user_back ( ) ; if ( ! C1 || ! AI -> hasOneUse ( ) || I -> getOpcode ( ) != Instruction :: And || AI -> getParent ( ) != I -> getParent ( ) ) return AtomicExpansionKind :: CmpXChg ; auto * C2 = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Bits = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( ! C2 || Bits == <NUM_LIT> || ! isPowerOf2_64 ( C2 -> getZExtValue ( ) ) ) return AtomicExpansionKind :: CmpXChg ; if ( AI -> getOperation ( ) == AtomicRMWInst :: And ) return ~ C1 -> getValue ( ) == C2 -> getValue ( ) ? AtomicExpansionKind :: BitTestIntrinsic : AtomicExpansionKind :: CmpXChg ;

return C1 == C2 ? AtomicExpansionKind :: BitTestIntrinsic : AtomicExpansionKind :: CmpXChg ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: Token ) ; Op -> Tok = Str ; Op -> StartLoc = S ; Op -> EndLoc = S ; Op -> IsRV64 = IsRV64 ;


<s> continue ; } if ( ! isUnconditionalBranch ( * I ) && ! isConditionalBranch ( * I ) ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass != & <STR_LIT> ) { unsigned Offset = RegSpillOffsets [ Reg ] ; CalleeFrameSize += <NUM_LIT> ; if ( StartOffset > Offset ) { LowReg = Reg ; StartOffset = Offset ; } if ( EndOffset < Offset ) { HighReg = Reg ; EndOffset = RegSpillOffsets [ Reg ] ; } } } MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; MFI -> setLowReg ( LowReg ) ; MFI -> setHighReg ( HighReg ) ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? <STR_LIT> : <STR_LIT> ) ) ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; if ( LowReg == HighReg ) MIB . addReg ( <NUM_LIT> ) ; MIB . addReg ( LowReg , RegState :: Kill ) ; if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Kill ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg != LowReg && Reg != HighReg ) MIB . addReg ( Reg , RegState :: ImplicitKill ) ; } } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & <STR_LIT> ) { MBB . addLiveIn ( Reg ) ;

storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RegClass ) ;


<s> bool isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const override { const MCInstrDesc & TMCID = std :: prev ( TMBB . end ( ) ) -> getDesc ( ) ; if ( TMCID . isReturn ( ) || TMCID . isCall ( ) ) return false ; const MCInstrDesc & FMCID = std :: prev ( FMBB . end ( ) ) -> getDesc ( ) ; if ( FMCID . isReturn ( ) || FMCID . isCall ( ) ) return false ; if ( ( NumTCycles + NumFCycles ) > <NUM_LIT> ) return false ; return ! mayStall ( TMBB ) && ! mayStall ( FMBB ) ;


<s> operands [ <NUM_LIT> ] = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; } if ( action [ <NUM_LIT> ] == dec_before ) { operands [ <NUM_LIT> ] = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; } for ( i = <NUM_LIT> ; i < words ; i ++ ) output_asm_insn ( singlemove_string ( exops [ i ] ) , exops [ i ] ) ; if ( action [ <NUM_LIT> ] == inc_after ) { operands [ <NUM_LIT> ] = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; } if ( action [ <NUM_LIT> ] == inc_after ) { operands [ <NUM_LIT> ] = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_ECLAIR , true ) {


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( AFI -> getLocalStackSize ( ) == <NUM_LIT> ) return false ; if ( StackBumpBytes >= <NUM_LIT> ) return false ; if ( MFI -> hasVarSizedObjects ( ) ) return false ; if ( RegInfo -> needsStackRealignment ( MF ) ) return false ;

if ( canUseRedZone ( MF ) ) return false ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; std :: vector < std :: pair < Function * , Function * >> Replacements ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) || ! F . hasFnAttribute ( <STR_LIT> ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; if ( ! F . isVarArg ( ) ) report_fatal_error ( <STR_LIT> + F . getName ( ) ) ; if ( F . getFunctionType ( ) -> getNumParams ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> + F . getName ( ) ) ; FunctionType * NewType = nullptr ; Function * NewF = nullptr ; for ( Use & U : F . uses ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; if ( BitCastOperator * BC = dyn_cast < BitCastOperator > ( U . getUser ( ) ) ) { FunctionType * DestType = cast < FunctionType > ( BC -> getDestTy ( ) -> getPointerElementType ( ) ) ; NewType = DestType ; NewF = Function :: Create ( NewType , F . getLinkage ( ) , F . getName ( ) ) ; NewF -> setAttributes ( F . getAttributes ( ) ) ; NewF -> removeFnAttr ( <STR_LIT> ) ;


<s> void AMDGPUInstPrinter :: printUpdateExecMask ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {

printIfSet ( MI , OpNo , O , <STR_LIT> ) ;


<s> static bool arc_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case E_V2HImode : return TARGET_PLUS_DMPY ; case E_V4HImode : case E_V2SImode : return TARGET_PLUS_QMACW ; case E_V4SImode :


<s> if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != <NUM_LIT> ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsPairwise , IsUnsigned , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getHalfRateInstrCost ( ) ;


<s> case <STR_LIT> : HOpcode = <STR_LIT> ; break ; case <STR_LIT> : HOpcode = <STR_LIT> ; break ; case <STR_LIT> : HOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned LExtIndex = LHS . getConstantOperandVal ( <NUM_LIT> ) ; unsigned RExtIndex = RHS . getConstantOperandVal ( <NUM_LIT> ) ; if ( LExtIndex == <NUM_LIT> && RExtIndex == <NUM_LIT> && ( HOpcode == <STR_LIT> || HOpcode == <STR_LIT> ) ) std :: swap ( LExtIndex , RExtIndex ) ; if ( LExtIndex != <NUM_LIT> || RExtIndex != <NUM_LIT> ) return Op ; SDValue X = LHS . getOperand ( <NUM_LIT> ) ; EVT VecVT = X . getValueType ( ) ; unsigned BitWidth = VecVT . getSizeInBits ( ) ; assert ( ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; if ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) X = extract128BitVector ( X , <NUM_LIT> , DAG , DL ) ; SDValue HOp = DAG . getNode ( HOpcode , DL , X . getValueType ( ) , X , X ) ;

return DAG . getNode ( <STR_LIT> , DL , Op . getSimpleValueType ( ) , HOp , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> unsigned int save_reg_mask = <NUM_LIT> ; unsigned long func_type = arm_current_func_type ( ) ; if ( IS_NAKED ( func_type ) ) return <NUM_LIT> ; if ( frame_pointer_needed ) save_reg_mask |= ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) | ( <NUM_LIT> << IP_REGNUM ) | ( <NUM_LIT> << LR_REGNUM ) | ( <NUM_LIT> << PC_REGNUM ) ; if ( IS_VOLATILE ( func_type ) ) return save_reg_mask ;

save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ;


<s> if ( SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P ) { rtx base , offset ; split_const ( x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && ! offset_within_block_p ( base , INTVAL ( offset ) ) ) return false ;


<s> if ( Value == <NUM_LIT> ) return ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= ( Rn << <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default :


<s> auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto & DbgLoc = MIB -> getDebugLoc ( ) ; auto CondReg = MIB . getReg ( <NUM_LIT> ) ; assert ( validReg ( MRI , CondReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto CmpI = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . TSTri ) ) . addUse ( CondReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * CmpI , TII , TRI , RBI ) ) return false ; auto ResReg = MIB . getReg ( <NUM_LIT> ) ; auto TrueReg = MIB . getReg ( <NUM_LIT> ) ; auto FalseReg = MIB . getReg ( <NUM_LIT> ) ; assert ( validOpRegPair ( MRI , ResReg , TrueReg , <NUM_LIT> , <STR_LIT> ) && validOpRegPair ( MRI , TrueReg , FalseReg , <NUM_LIT> , <STR_LIT> ) && <STR_LIT> ) ; auto Mov1I = BuildMI ( MBB , InsertBefore , DbgLoc , TII . get ( Opcodes . MOVCCr ) ) . addDef ( ResReg ) . addUse ( TrueReg ) . addUse ( FalseReg ) . add ( predOps ( <STR_LIT> , <STR_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Mov1I , TII , TRI , RBI ) ) return false ;


<s> bool isUImm12Offset ( ) const { if ( ! isImm ( ) ) return false ;

const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; switch ( Align & <NUM_LIT> ) { case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; break ; case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget . is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } break ; default : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; break ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes , dl ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , dl , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal , dl ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } bool Use64BitRegs = Subtarget . isTarget64BitLP64 ( ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; EVT AddrVT = Dst . getValueType ( ) ; EVT SizeVT = Size . getValueType ( ) ; Chain = DAG . getMemset ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , AddrVT , Dst , DAG . getConstant ( Offset , dl , AddrVT ) ) , Val , DAG . getConstant ( BytesLeft , dl , SizeVT ) , Align , isVolatile , false , DstPtrInfo . getWithOffset ( Offset ) ) ;


<s> GCNPassConfig ( TargetMachine * TM , PassManagerBase & PM ) : <ISA_LIT>PassConfig ( TM , PM ) {


<s> const char * <ISA_LIT>Subtarget :: getBZeroEntry ( ) const {

if ( getTargetTriple ( ) . isMacOSX ( ) && ! getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) return <STR_LIT> ;


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , MCInstLowering ( OutContext , * Mang , * this ) , SM ( * this ) , <ISA_LIT>FI ( nullptr ) , LOHLabelCounter ( <NUM_LIT> ) {


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize ( ) ) && ! MFI -> hasVarSizedObjects ( ) ;


<s> if ( ! TARGET_AM33_2 ) { for ( i = FIRST_FP_REGNUM ; i <= LAST_FP_REGNUM ; i ++ ) fixed_regs [ i ] = <NUM_LIT> ;


<s> bool isArgPassedInSGPR ( const Argument * A ) { const Function * F = A -> getParent ( ) ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { case CallingConv :: <ISA_LIT>_KERNEL : case CallingConv :: SPIR_KERNEL : return true ; case CallingConv :: <ISA_LIT>_VS :


<s> <ISA_LIT>IncomingValueHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI ) : CallLowering :: IncomingValueHandler ( MIRBuilder , MRI ) {


<s> if ( Op . isImmTy ( <ISA_LIT>Operand :: ImmTyDppBoundCtrl ) ) { Operands . pop_back ( ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( <NUM_LIT> , S , <ISA_LIT>Operand :: ImmTyDppBoundCtrl ) ) ;


MCRegisterInfo * X = new MCRegisterInfo ( ) ;


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; if ( DAG . isVerifiedDebugInfoDesc ( Op ) ) return GA ;

return getGlobalAddressWrapper ( GA , GV , DAG ) ;


<s> int Offset = <NUM_LIT> ; const MCSymbolRefExpr * SRE ; if ( const auto * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { SRE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; const auto * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ;


<s> arm_elf_asm_cdtor ( symbol , priority , true ) ;


<s> unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; const TargetRegisterClass * InRC = MRI . getRegClass ( SrcReg ) ; if ( InRC == & <STR_LIT> ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY_TO_REGCLASS ) , TmpReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; SrcReg = TmpReg ; } unsigned DestReg = createResultReg ( & <STR_LIT> ) ;


<s> else if ( code == 'R' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , <NUM_LIT> - INTVAL ( x ) ) ; else if ( code == 'H' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> , ( int ) ( <NUM_LIT> & ~ INTVAL ( x ) ) ) ; else if ( code == 'h' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> , ( short ) - INTVAL ( x ) ) ; else if ( code == 'B' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> , ( int ) ( <NUM_LIT> & ~ INTVAL ( x ) ) ) ; else if ( code == 'b' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> , ( int ) ( <NUM_LIT> & - INTVAL ( x ) ) ) ; else if ( code == 'M' && CONST_INT_P ( x ) ) fprintf ( file , <STR_LIT> , ~ ( ( <NUM_LIT> << INTVAL ( x ) ) - <NUM_LIT> ) ) ; else if ( code == 'x' && CONST_INT_P ( x ) ) fprintf ( file , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ;

else if ( REG_P ( x ) ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ;


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI . getOperand ( i ) ; if ( Op . isReg ( ) ) { if ( ( Op . getReg ( ) != SGPRUsed . Reg || Op . getSubReg ( ) != SGPRUsed . SubReg ) && usesConstantBus ( MRI , Op , InstDesc . OpInfo [ i ] ) ) { return false ; } } else if ( InstDesc . OpInfo [ i ] . OperandType == <STR_LIT> ) { return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; return isLegalRegOperand ( MRI , OpInfo , * MO ) ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) ) ; if ( ! DefinedRC ) {


<s> static const TargetRegisterClass * const CalleeSavedRC [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ; return CalleeSavedRC ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( Triple ( TT ) ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , Options . StackAlignmentOverride ) { if ( Subtarget . isTargetWin64 ( ) ) this -> Options . TrapUnreachable = true ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , false , <NUM_LIT> ) ;


<s> explicit PolynomialMultiplyRecognize ( Loop * loop , const DataLayout & dl , const DominatorTree & dt , const TargetLibraryInfo & tli , ScalarEvolution & se ) : CurLoop ( loop ) , DL ( dl ) , DT ( dt ) , TLI ( tli ) , SE ( se ) {


<s> ModulePass * llvm :: create<ISA_LIT>GenScalarMASSEntriesPass ( ) {

return new <ISA_LIT>GenScalarMASSEntries ( ) ;


<s> CCValAssign & VA = ArgLocs [ i ] ; MVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; InVals . push_back ( ArgValue ) ; }


<s> static DecodeStatus DecodeDDDDRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success ;


<s> assert ( MI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Location . set ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; else { DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; }

return Ctx . GetOrCreateSymbol ( Name . str ( ) ) ;


<s> unsigned getReg ( ) const override {


<s> bool <ISA_LIT>ElimCompare :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const <ISA_LIT>InstrInfo * > ( F . getTarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ;

for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ;


<s> unsigned maximum_regs , maximum_bytes , start_regno , regno ; rtx value4word ; rtx dst_base_reg , new_base_reg ; unsigned HOST_WIDE_INT remain_bytes , remain_words , prepare_regs , fill_per_smw ; unsigned HOST_WIDE_INT real_size ; if ( TARGET_REDUCED_REGS ) { maximum_regs = <NUM_LIT> ; maximum_bytes = <NUM_LIT> ; start_regno = <NUM_LIT> ; } else { maximum_regs = <NUM_LIT> ; maximum_bytes = <NUM_LIT> ; start_regno = <NUM_LIT> ; } real_size = UINTVAL ( size ) & GET_MODE_MASK ( SImode ) ; if ( ! ( CONST_INT_P ( size ) && real_size <= maximum_bytes ) ) return false ; remain_bytes = real_size ; gcc_assert ( GET_MODE ( value ) == QImode || CONST_INT_P ( value ) ) ; value4word = nds32_gen_dup_4_byte_to_word_value ( value ) ; prepare_regs = remain_bytes / UNITS_PER_WORD ; dst_base_reg = copy_to_mode_reg ( SImode , XEXP ( dstmem , <NUM_LIT> ) ) ; if ( prepare_regs > maximum_regs ) prepare_regs = maximum_regs ; fill_per_smw = prepare_regs * UNITS_PER_WORD ; regno = start_regno ; switch ( prepare_regs ) { case <NUM_LIT> : default : { rtx reg0 = gen_rtx_REG ( SImode , regno ) ; rtx reg1 = gen_rtx_REG ( SImode , regno + <NUM_LIT> ) ; unsigned last_regno = start_regno + prepare_regs - <NUM_LIT> ; emit_move_insn ( reg0 , value4word ) ; emit_move_insn ( reg1 , value4word ) ; rtx regd = gen_rtx_REG ( DImode , regno ) ; regno += <NUM_LIT> ; while ( regno <= last_regno ) { if ( ( regno + <NUM_LIT> ) <= last_regno ) { rtx reg = gen_rtx_REG ( DImode , regno ) ; emit_move_insn ( reg , regd ) ; regno += <NUM_LIT> ; } else { rtx reg = gen_rtx_REG ( SImode , regno ) ; emit_move_insn ( reg , reg0 ) ; regno += <NUM_LIT> ; } } break ; } case <NUM_LIT> : { rtx reg = gen_rtx_REG ( SImode , regno ++ ) ; emit_move_insn ( reg , value4word ) ; } break ; case <NUM_LIT> : break ; } if ( fill_per_smw ) for ( ; remain_bytes >= fill_per_smw ; remain_bytes -= fill_per_smw ) { emit_insn ( nds32_expand_store_multiple ( start_regno , prepare_regs , dst_base_reg , dstmem , true , & new_base_reg ) ) ; dst_base_reg = new_base_reg ; dstmem = gen_rtx_MEM ( SImode , dst_base_reg ) ; } remain_words = remain_bytes / UNITS_PER_WORD ; if ( remain_words ) { emit_insn ( nds32_expand_store_multiple ( start_regno , remain_words , dst_base_reg , dstmem , true , & new_base_reg ) ) ; dst_base_reg = new_base_reg ;


<s> if ( TYPE_ALIGN ( type ) > BITS_PER_WORD ) { int align = TYPE_ALIGN ( type ) / BITS_PER_UNIT ; t = build ( PLUS_EXPR , integer_type_node , orig_ndx , build_int_cst ( NULL_TREE , align - <NUM_LIT> ) ) ; t = build ( BIT_AND_EXPR , integer_type_node , t , build_int_cst ( NULL_TREE , - align ) ) ; t = build ( MODIFY_EXPR , integer_type_node , orig_ndx , t ) ; gimplify_and_add ( t , pre_p ) ; } t = fold_convert ( integer_type_node , va_size ) ; t = build ( PLUS_EXPR , integer_type_node , orig_ndx , t ) ; t = build ( MODIFY_EXPR , integer_type_node , ndx , t ) ; gimplify_and_add ( t , pre_p ) ; array = create_tmp_var ( ptr_type_node , NULL ) ; lab_over = NULL ; if ( ! targetm . calls . must_pass_in_stack ( TYPE_MODE ( type ) , type ) ) { lab_false = create_artificial_label ( ) ; lab_over = create_artificial_label ( ) ; t = build_int_cst ( NULL_TREE , MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD ) ; t = build ( GT_EXPR , boolean_type_node , ndx , t ) ; t = build ( COND_EXPR , void_type_node , t , build ( GOTO_EXPR , void_type_node , lab_false ) , NULL ) ; gimplify_and_add ( t , pre_p ) ; t = build ( MODIFY_EXPR , void_type_node , array , reg ) ; gimplify_and_add ( t , pre_p ) ; t = build ( GOTO_EXPR , void_type_node , lab_over ) ; gimplify_and_add ( t , pre_p ) ; t = build ( LABEL_EXPR , void_type_node , lab_false ) ; gimplify_and_add ( t , pre_p ) ; } lab_false2 = create_artificial_label ( ) ; t = build_int_cst ( NULL_TREE , MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD ) ;

t = build ( GT_EXPR , boolean_type_node , orig_ndx , t ) ;


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const override { return <STR_LIT> ;


<s> const MachineOperand & MO = Br . getOperand ( I ) ; if ( MO . isMBB ( ) ) return MO . getMBB ( ) ; }


if ( MO . isReg ( ) ) for ( unsigned IndexReg : <STR_LIT> ) if ( RI . isSubRegisterEq ( IndexReg , MO . getReg ( ) ) ) return true ;


<s> bool AMDGPUDAGToDAGISel :: SelectVOP3Mods0 ( SDValue In , SDValue & Src , SDValue & SrcMods , SDValue & Clamp , SDValue & Omod ) const {


<s> } Next = Simple -> Next ; } else { for ( const auto & iter : Simple -> Inner -> ProcessedBranchesOut ) { Block * Target = iter . first ; Branch * Details = iter . second . get ( ) ; if ( Details -> Type != Branch :: Direct && contains ( NaturalBlocks , Target ) ) { Details -> Type = Branch :: Direct ; if ( MultipleShape * Multiple = dyn_cast < MultipleShape > ( Details -> Ancestor ) ) Multiple -> Breaks -- ; } else if ( Details -> Type == Branch :: Break && LastLoop && LastLoop -> Natural == Details -> Ancestor -> Natural ) { Details -> Labeled = false ; if ( MultipleShape * Multiple = dyn_cast < MultipleShape > ( Details -> Ancestor ) ) Multiple -> Breaks -- ; } } } } , [ & ] ( MultipleShape * Multiple ) { for ( const auto & iter : Multiple -> InnerMap ) { RemoveUnneededFlows ( iter . second , Multiple -> Next , Multiple -> Breaks ? nullptr : LastLoop , Depth + <NUM_LIT> ) ; } Next = Multiple -> Next ; } , [ & ] ( LoopShape * Loop ) { RemoveUnneededFlows ( Loop -> Inner , Loop -> Inner , Loop , Depth + <NUM_LIT> ) ; Next = Loop -> Next ;


<s> bool <ISA_LIT>DAGToDAGISel :: hasNoSignFlagUses ( SDValue Flags ) const { for ( SDNode :: use_iterator UI = Flags -> use_begin ( ) , UE = Flags -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != Flags . getResNo ( ) ) continue ; if ( UI -> getOpcode ( ) != <STR_LIT> || cast < RegisterSDNode > ( UI -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; for ( SDNode :: use_iterator FlagUI = UI -> use_begin ( ) , FlagUE = UI -> use_end ( ) ; FlagUI != FlagUE ; ++ FlagUI ) { if ( FlagUI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( ! FlagUI -> isMachineOpcode ( ) ) return false ; <STR_LIT> CC = getCondFromNode ( * FlagUI ) ; switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : continue ; default : return false ;


<s> if ( align > UNITS_PER_WORD ) { align = UNITS_PER_WORD ; } else if ( align < UNITS_PER_WORD ) { if ( INTVAL ( length ) <= MAX_MOVE_BYTES ) { move_by_pieces ( dest , src , bytes , align , <NUM_LIT> ) ; return true ; } else return false ; } if ( INTVAL ( length ) <= <NUM_LIT> * MAX_MOVE_BYTES ) { microblaze_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ;


<s> if ( Subtarget -> hasApertureRegs ( ) ) { unsigned Offset = AS == <ISA_LIT>AS :: LOCAL_ADDRESS ? <STR_LIT> :: OFFSET_SRC_SHARED_BASE : <STR_LIT> :: OFFSET_SRC_PRIVATE_BASE ; unsigned WidthM1 = AS == <ISA_LIT>AS :: LOCAL_ADDRESS ? <STR_LIT> :: WIDTH_M1_SRC_SHARED_BASE : <STR_LIT> :: WIDTH_M1_SRC_PRIVATE_BASE ; unsigned Encoding = <STR_LIT> :: ID_MEM_BASES << <STR_LIT> :: ID_SHIFT_ | Offset << <STR_LIT> :: OFFSET_SHIFT_ | WidthM1 << <STR_LIT> :: WIDTH_M1_SHIFT_ ; SDValue EncodingImm = DAG . getTargetConstant ( Encoding , DL , <STR_LIT> ) ; SDValue ApertureReg = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , EncodingImm ) , <NUM_LIT> ) ; SDValue ShiftAmount = DAG . getTargetConstant ( WidthM1 + <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ApertureReg , ShiftAmount ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register UserSGPR = Info -> getQueuePtrUserSGPR ( ) ; assert ( UserSGPR != <STR_LIT> ) ; SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR , <STR_LIT> ) ;


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: ParseOperand ( StringRef Mnemonic ) {

if ( isParsingIntelSyntax ( ) ) return ParseIntelOperand ( ) ;


<s> static void mips_emit_move_or_split ( rtx dest , rtx src , enum mips_split_type split_type ) { if ( mips_split_move_p ( dest , src , split_type ) ) mips_split_move ( dest , src , split_type , NULL ) ;


<s> unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , TempReg ) ; unsigned Flags = getKillRegState ( New . isDead ( ) ) ; addExclusiveRegPair ( MIB , New , Flags , IsThumb , TRI ) ; MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoadCmpBB ) ;


<s> unsigned SubIdx = ( IsI64 ? <STR_LIT> : <STR_LIT> ) ; bool DstIsLarger , SrcIsLarger ; tie ( DstIsLarger , SrcIsLarger ) = compareOpndSize ( CvtOpc , * MBB . getParent ( ) ) ; if ( DstIsLarger ) TmpReg = getRegisterInfo ( ) . getSubReg ( DstReg , SubIdx ) ; if ( SrcIsLarger ) DstReg = getRegisterInfo ( ) . getSubReg ( DstReg , SubIdx ) ;

BuildMI ( MBB , I , DL , MovDesc , TmpReg ) . addReg ( SrcReg , KillSrc ) ;


<s> <ISA_LIT>_64TargetMachine :: <ISA_LIT>_64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) , DL ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , JITInfo ( * this ) {


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : ForceFramePointer ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) , BytesToPopOnReturn ( <NUM_LIT> ) , DecorationStyle ( None ) , ReturnAddrIndex ( <NUM_LIT> ) , TailCallReturnAddrDelta ( <NUM_LIT> ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> label = gen_rtx_LABEL_REF ( DImode , label ) ; if ( before == NULL ) before = scratch ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) { x = gen_rtx_AND ( mode , before , val ) ; emit_insn ( gen_rtx_SET ( VOIDmode , val , x ) ) ; x = gen_rtx_NOT ( mode , val ) ; } else x = gen_rtx_fmt_ee ( code , mode , before , val ) ; if ( after ) emit_insn ( gen_rtx_SET ( VOIDmode , after , copy_rtx ( x ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ; emit_store_conditional ( mode , cond , mem , scratch ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label ) ;


<s> bool llvm :: checkConvertToNonDenormSingle ( APFloat & ArgAPFloat ) { APFloat APFloatToConvert = ArgAPFloat ; bool LosesInfo = true ;

APFloatToConvert . convert ( APFloat :: IEEEsingle ( ) , APFloat :: rmNearestTiesToEven , & LosesInfo ) ;


<s> void <ISA_LIT>MCCodeEmitter :: EmitRegModRMByte ( const MCOperand & ModRMReg , unsigned RegOpcodeFld , unsigned & CurByte , raw_ostream & OS ) const {


<s> return ( insn >> <STR_LIT> ) & <NUM_LIT> ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

unsigned Align = MFI . getObjectAlignment ( FI ) ;


<s> <ISA_LIT>GenPreLegalizerCombinerHelper Generated ( GeneratedRuleCfg , Helper ) ; if ( Generated . tryCombineAll ( Observer , MI , B ) ) return true ;


<s> SDValue <ISA_LIT>TargetLowering :: getGlobalReg ( SelectionDAG & DAG , EVT Ty ) const { <ISA_LIT>FunctionInfo * FI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return DAG . getRegister ( FI -> getGlobalBaseReg ( ) , Ty ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> MCValue Res ; bool IsReloc = getMemOff ( ) -> evaluateAsRelocatable ( Res , nullptr , nullptr ) ; return IsReloc && isShiftedInt < Bits , ShiftAmount > ( Res . getConstant ( ) ) ;


<s> if ( isa < BranchInst > ( V ) || isa < SwitchInst > ( V ) || isa < BasicBlock > ( V ) ) return true ; if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) ) return true ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; else if ( auto * Cast = dyn_cast < CastInst > ( V ) ) { if ( isa < ZExtInst > ( Cast ) ) return Cast -> getDestTy ( ) -> getScalarSizeInBits ( ) <= <NUM_LIT> ; else if ( auto * Trunc = dyn_cast < TruncInst > ( V ) ) return Trunc -> getDestTy ( ) -> getScalarSizeInBits ( ) <= TypeSize ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else if ( ! isa < BinaryOperator > ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> void <ISA_LIT>Cloner :: remapAllSites ( Function * Caller , Function * OrgF , Function * Clone ) { cloned_map_iterator cm_it = ClonedFunctionMap . find ( Caller ) ; if ( cm_it != ClonedFunctionMap . end ( ) ) Caller = cm_it -> second ; for ( Function :: iterator BI = Caller -> begin ( ) ; BI != Caller -> end ( ) ; ++ BI ) { BasicBlock & BB = * BI ; for ( BasicBlock :: iterator II = BB . begin ( ) ; II != BB . end ( ) ; ++ II ) { if ( II -> getNumOperands ( ) > <NUM_LIT> && II -> getOperand ( <NUM_LIT> ) == OrgF ) II -> setOperand ( <NUM_LIT> , Clone ) ; } }


<s> if ( ! emitExtractSubreg ( DstReg , SrcReg , I , MRI , MF ) ) return false ; I . eraseFromParent ( ) ; return true ; } bool HasAVX = STI . hasAVX ( ) ; bool HasAVX512 = STI . hasAVX512 ( ) ; bool HasVLX = STI . hasVLX ( ) ; if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> && DstTy . getSizeInBits ( ) == <NUM_LIT> ) { if ( HasVLX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( HasAVX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else return false ; } else if ( SrcTy . getSizeInBits ( ) == <NUM_LIT> && HasAVX512 ) { if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) I . setDesc ( TII . get ( <STR_LIT> ) ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , dl , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , dl , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , dl , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; uint64_t nextOffset = FPROffset ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op . getOperand ( <NUM_LIT> ) , ConstFPROffset ) ; SDValue secondStore = DAG . getTruncStore ( firstStore , dl , ArgFPR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , <STR_LIT> , false , false , <NUM_LIT> ) ; nextOffset += StackOffset ;

nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr , ConstStackOffset ) ;


<s> DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , isLittleEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { Result = decodeInstruction ( DecoderTable<ISA_LIT>V932 , Instr , Insn , Address , this , STI ) ;


<s> if ( Op . isReg ( ) ) { unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm ( ) ) { O << '#' << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op . getExpr ( ) ; }


<s> assert ( Fixup . Offset + Size <= DF . getContents ( ) . size ( ) && <STR_LIT> ) ;

for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) DF . getContents ( ) [ Fixup . Offset + i ] = uint8_t ( Value >> ( i * <NUM_LIT> ) ) ;


<s> StoreInst * <ISA_LIT> = dyn_cast < StoreInst > ( U . getUser ( ) ) ; if ( UseCount > MaxUses ) return false ; if ( ! <ISA_LIT> ) { auto * BCI = dyn_cast < BitCastInst > ( U . getUser ( ) ) ; if ( ! BCI || ! BCI -> hasOneUse ( ) ) return false ; Type * DestEltTy = BCI -> getType ( ) -> getPointerElementType ( ) ; if ( DestEltTy -> isAggregateType ( ) ) return false ; Type * SrcEltTy = Arg . getType ( ) -> getPointerElementType ( ) ; if ( SrcEltTy -> isArrayTy ( ) ) return false ; if ( ( SrcEltTy -> isStructTy ( ) && ( SrcEltTy -> getStructNumElements ( ) != <NUM_LIT> ) ) ) return false ; if ( DL -> getTypeAllocSize ( SrcEltTy ) != DL -> getTypeAllocSize ( DestEltTy ) ) return false ;


<s> void <ISA_LIT>AsmInstrumentation :: InstrumentAndEmitInstruction ( const MCInst & Inst , OperandVector & Operands , MCContext & Ctx , const MCInstrInfo & MII , MCStreamer & Out , bool PrintSchedInfoEnabled ) { EmitInstruction ( Out , Inst , PrintSchedInfoEnabled ) ;


<s> void <ISA_LIT>beTargetMachine :: anchor ( ) {


<s> void <ISA_LIT>InstrInfo :: replaceInstrOperandWithImm ( MachineInstr & MI , unsigned OpNo , int64_t Imm ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; Register InUseReg = MI . getOperand ( OpNo ) . getReg ( ) ;

MI . getOperand ( OpNo ) . ChangeToImmediate ( Imm ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) return std :: max ( ( VT . getSizeInBits ( ) / ( Subtarget . isABI_O32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ) , <NUM_LIT> ) ;

return <ISA_LIT>TargetLowering :: getNumRegisters ( Context , VT ) ;


return ( int64x1_t ) { __builtin_aarch64_sqshl_ndi ( __a [ <NUM_LIT> ] , __b ) } ;


<s> static MCTargetStreamer * create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetAsmStreamer ( S ) ;


<s> virtual void releaseTopNode ( SUnit * SU ) {


<s> std :: vector < std :: string > retidc ( ) { return D ( <STR_LIT> ) ;


<s> static inline machine_mode get_mode_wider_vector ( machine_mode o ) { machine_mode n = GET_MODE_WIDER_MODE ( o ) ;

gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n ) * <NUM_LIT> ) ;


<s> <ISA_LIT>65816RegisterInfo :: <ISA_LIT>65816RegisterInfo ( <ISA_LIT>65816Subtarget & st ) : <ISA_LIT>65816GenRegisterInfo ( <STR_LIT> ) , Subtarget ( st ) {


<s> if ( tmp == NULL_RTX ) return false ; operands [ <NUM_LIT> ] = tmp ; } else { CLEAR_HARD_REG_SET ( regset ) ; tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DImode , & regset ) ; if ( tmp != NULL_RTX ) { operands [ <NUM_LIT> ] = simplify_gen_subreg ( SImode , tmp , DImode , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = simplify_gen_subreg ( SImode , tmp , DImode , <NUM_LIT> ) ; } else { SET_HARD_REG_SET ( regset ) ; CLEAR_HARD_REG_BIT ( regset , regno % <NUM_LIT> == <NUM_LIT> ? regno + <NUM_LIT> : regno - <NUM_LIT> ) ; tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , SImode , & regset ) ; if ( tmp == NULL_RTX ) return false ; operands [ regno % <NUM_LIT> == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ] = tmp ; } } gcc_assert ( operands [ <NUM_LIT> ] != NULL_RTX ) ; gcc_assert ( operands [ <NUM_LIT> ] != NULL_RTX ) ; gcc_assert ( REGNO ( operands [ <NUM_LIT> ] ) % <NUM_LIT> == <NUM_LIT> ) ; gcc_assert ( REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; } } if ( offsets [ <NUM_LIT> ] > offsets [ <NUM_LIT> ] ) { gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; std :: swap ( align [ <NUM_LIT> ] , align [ <NUM_LIT> ] ) ; if ( const_store ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; } if ( gap != <NUM_LIT> ) return false ; if ( ! align_ok_ldrd_strd ( align [ <NUM_LIT> ] , offset ) ) return false ; if ( operands_ok_ldrd_strd ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , base , offset , false , load ) ) return true ; if ( TARGET_THUMB2 ) return false ; if ( load && commute ) { std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( operands_ok_ldrd_strd ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , base , offset , false , load ) ) return true ;


<s> init_adjust_machine_modes ( ) ; init_derived_machine_modes ( ) ; reinit_regs ( ) ;


<s> void setBasePtrStackAdjustment ( int64_t adj ) { BPAdj = adj ;


<s> ~ <ISA_LIT>Disassembler ( ) override {


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T , MRI ) ; assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , OSABI , true ) ;


<s> case AtomicRMWInst :: FSub : return AtomicExpansionKind :: CmpXChg ; default :


<s> Inst . addOperand ( MCOperand :: createImm ( - ( int64_t ) Val ) ) ; return MCDisassembler :: Success ;


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( LHS . getOpcode ( ) == <STR_LIT> || RHS . getOpcode ( ) == <STR_LIT> ) && Subtarget -> hasMad64_32 ( ) && ! VT . isVector ( ) && VT . getScalarSizeInBits ( ) > <NUM_LIT> && VT . getScalarSizeInBits ( ) <= <NUM_LIT> ) { if ( LHS . getOpcode ( ) != <STR_LIT> ) std :: swap ( LHS , RHS ) ; SDValue MulLHS = LHS . getOperand ( <NUM_LIT> ) ; SDValue MulRHS = LHS . getOperand ( <NUM_LIT> ) ; SDValue AddRHS = RHS ; if ( numBitsUnsigned ( MulLHS , DAG ) <= <NUM_LIT> && numBitsUnsigned ( MulRHS , DAG ) <= <NUM_LIT> ) { MulLHS = DAG . getZExtOrTrunc ( MulLHS , SL , <STR_LIT> ) ; MulRHS = DAG . getZExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getZExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , false ) ;


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; Offset += <NUM_LIT> ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) . getStackSize ( ) ;


<s> if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , false , Operands ) ; const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , false , true , Log2SEW , static_cast < unsigned > ( LMUL ) ) ; MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Operands ) ; SDNode * ReadVL = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDValue ( Load , <NUM_LIT> ) ) ; if ( auto * MemOp = dyn_cast < MemSDNode > ( Node ) ) CurDAG -> setNodeMemRefs ( Load , { MemOp -> getMemOperand ( ) } ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ;

for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) {


<s> MEM_VOLATILE_P ( mem ) = <NUM_LIT> ;


<s> case MachineOperand :: MO_Register : { unsigned Reg = <ISA_LIT>InstrInfo :: getRegNumForOperand ( MI -> getDesc ( ) , MO . getReg ( ) , OpNo ) ; const char * RegName = <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; if ( ! Subtarget -> isDarwin ( ) ) RegName = <ISA_LIT>RegisterInfo :: stripRegisterPrefix ( RegName ) ; O << RegName ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( Subtarget -> hasLazyResolverStub ( GV ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else { SymToPrint = getSymbol ( GV ) ;


<s> BranchInst . addOperand ( MCOperand :: createExpr ( OffsetExpr ) ) ; Instructions . push_back ( BranchInst ) ; Warning ( IDLoc , <STR_LIT> ) ; return false ; } return false ; } if ( IsSrcRegZero || IsTrgRegZero ) { if ( ( IsSrcRegZero && PseudoOpcode == <STR_LIT> ) || ( IsTrgRegZero && PseudoOpcode == <STR_LIT> ) ) { return false ; } if ( ( IsSrcRegZero && PseudoOpcode == <STR_LIT> ) || ( IsTrgRegZero && PseudoOpcode == <STR_LIT> ) ) { BranchInst . setOpcode ( <STR_LIT> ) ; BranchInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; BranchInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; BranchInst . addOperand ( MCOperand :: createExpr ( OffsetExpr ) ) ; Instructions . push_back ( BranchInst ) ; Warning ( IDLoc , <STR_LIT> ) ; return false ; } if ( IsUnsigned ) { BranchInst . setOpcode ( AcceptsEquality ? <STR_LIT> : <STR_LIT> ) ; BranchInst . addOperand ( MCOperand :: createReg ( IsSrcRegZero ? TrgReg : SrcReg ) ) ; BranchInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; BranchInst . addOperand ( MCOperand :: createExpr ( OffsetExpr ) ) ; Instructions . push_back ( BranchInst ) ; return false ; } BranchInst . setOpcode ( IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode ) ; BranchInst . addOperand ( MCOperand :: createReg ( IsSrcRegZero ? TrgReg : SrcReg ) ) ; BranchInst . addOperand ( MCOperand :: createExpr ( OffsetExpr ) ) ; Instructions . push_back ( BranchInst ) ; return false ; } unsigned ATRegNum = getATReg ( IDLoc ) ; if ( ! ATRegNum ) return true ; warnIfNoMacro ( IDLoc ) ; MCInst SetInst ; SetInst . setOpcode ( IsUnsigned ? <STR_LIT> : <STR_LIT> ) ; SetInst . addOperand ( MCOperand :: createReg ( ATRegNum ) ) ; SetInst . addOperand ( MCOperand :: createReg ( ReverseOrderSLT ? TrgReg : SrcReg ) ) ; SetInst . addOperand ( MCOperand :: createReg ( ReverseOrderSLT ? SrcReg : TrgReg ) ) ; Instructions . push_back ( SetInst ) ; if ( ! IsLikely ) BranchInst . setOpcode ( AcceptsEquality ? <STR_LIT> : <STR_LIT> ) ; else BranchInst . setOpcode ( AcceptsEquality ? <STR_LIT> : <STR_LIT> ) ; BranchInst . addOperand ( MCOperand :: createReg ( ATRegNum ) ) ; BranchInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> isThumb ( false ) , hasThumb2 ( false ) , ArgRegsSaveSize ( <NUM_LIT> ) , ReturnRegsCount ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSAlignGapSize ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , NumAlignedDPRCS2Regs ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) , IsSplitCSR ( false ) , PromotedGlobalsIncrease ( <NUM_LIT> ) {


<s> RelooperRecursor ( RelooperAlgorithm * ParentInit ) : Parent ( ParentInit ) {


<s> bool isGPR64Offset ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses [ RegClassID ] . contains ( Reg . RegNum ) ;


<s> } else if ( MI -> isCopy ( ) ) { TileReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return getShape ( MRI , TileReg ) ; }

assert ( MI -> isPHI ( ) && <STR_LIT> ) ;


<s> bool hasFPUv2DoubleFloat ( ) const {


<s> <ISA_LIT>IncomingValueHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI ) : IncomingValueHandler ( MIRBuilder , MRI ) {


<s> void printMemOffs32 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; EVT InVT = In . getValueType ( ) ; unsigned NumElems = OutVT . getVectorNumElements ( ) ; if ( ! Subtarget . hasSSE2 ( ) || Subtarget . hasAVX2 ( ) ) return SDValue ( ) ; EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 ( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; if ( Subtarget . hasSSSE3 ( ) && NumElems == <NUM_LIT> && ( ( OutSVT == <STR_LIT> && InSVT != <STR_LIT> ) || ( InSVT == <STR_LIT> && OutSVT == <STR_LIT> ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( Subtarget . hasSSE41 ( ) || OutSVT == <STR_LIT> ) return combineVectorTruncationWithPACKUS ( N , DL , Subtarget , DAG ) ; if ( InSVT == <STR_LIT> ) return combineVectorTruncationWithPACKSS ( N , DL , Subtarget , DAG ) ; return SDValue ( ) ;


<s> if ( SrcTy . isVector ( ) ) return ; assert ( ! ShiftTy . isVector ( ) && <STR_LIT> ) ; if ( SrcTy . getSizeInBits ( ) != <NUM_LIT> || ShiftTy . getSizeInBits ( ) != <NUM_LIT> ) return ; auto * AmtMI = MRI . getVRegDef ( ShiftReg ) ; assert ( AmtMI && <STR_LIT> ) ; if ( AmtMI -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) { MachineIRBuilder MIB ( I ) ; auto Trunc = MIB . buildInstr ( TargetOpcode :: COPY , { SrcTy } , { } ) . addReg ( ShiftReg , <NUM_LIT> , <STR_LIT> ) ; MRI . setRegBank ( Trunc . getReg ( <NUM_LIT> ) , RBI . getRegBank ( <STR_LIT> ) ) ; I . getOperand ( <NUM_LIT> ) . setReg ( Trunc . getReg ( <NUM_LIT> ) ) ; } return ; }


<s> bool <ISA_LIT>Disassembler :: isGFX11 ( ) const {

return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo ) ; <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getValVT ( ) , Val ) ;


<s> if ( IsPIC && Subtarget . isSVR4ABI ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ; return getTOCEntry ( DAG , SDLoc ( GA ) , GA ) ; } SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOHiFlag ) ; SDValue JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOLoFlag ) ;

return LowerLabelRef ( JTIHi , JTILo , IsPIC , DAG ) ;


<s> bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ; SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ; auto * Load = cast < MemIntrinsicSDNode > ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Ops { Load -> getChain ( ) , IntID } ; if ( IsUnmasked ) Ops . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; else Ops . push_back ( PassThru ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Op . getOperand ( <NUM_LIT> ) ) ;

if ( ! IsUnmasked ) Ops . push_back ( Mask ) ;


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } DebugLoc dl = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; unsigned NumArgs = MI . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } if ( MI . hasOneMemOperand ( ) ) MIB -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ;


<s> ValueVect BO ; BO . push_back ( & Fn -> front ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < BO . size ( ) ; ++ i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i ] ) ;

for ( auto DTN : children < DomTreeNode * > ( DT -> getNode ( B ) ) ) BO . push_back ( DTN -> getBlock ( ) ) ;


<s> AMDGPUGenSubtargetInfo ( TT , CPU , FS ) , DumpCode ( false ) { InstrItins = getInstrItineraryForCPU ( CPU ) ; StringRef GPU = CPU ; Is64bit = false ; HasVertexCache = false ; TexVTXClauseSize = <NUM_LIT> ; Gen = AMDGPUSubtarget :: R600 ; FP64 = false ; CaymanISA = false ; EnableIRStructurizer = true ; EnableIfCvt = true ; WavefrontSize = <NUM_LIT> ; CFALUBug = false ; ParseSubtargetFeatures ( GPU , FS ) ; DevName = GPU ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl , VT , V1 , V2 ) ; }


<s> if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return cost ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return cost ; return cost + <NUM_LIT> ; }

if ( insn_type == TYPE_SHIFT ) return cost + <NUM_LIT> ;


<s> bool has3E7 ( ) const { return Has3E7 ;


<s> return Kind == k_Barrier && ! getBarriernXSModifier ( ) ;


<s> BlockISELList SubISELList ; SubISELList . push_back ( * I ++ ) ; while ( I != E && canMerge ( SubISELList . back ( ) , * I ) ) SubISELList . push_back ( * I ++ ) ; expandMergeableISELs ( SubISELList ) ; } }


<s> if ( B -> pred_size ( ) < <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; MachineBasicBlock :: const_iterator I , E = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != E ; ++ I ) { const MachineOperand & RO1 = I -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RO3 = I -> getOperand ( <NUM_LIT> ) ; assert ( RO1 . isReg ( ) && RO3 . isReg ( ) ) ; if ( RO1 . getSubReg ( ) != <NUM_LIT> || RO3 . getSubReg ( ) != <NUM_LIT> ) { Cost ++ ; continue ; } MachineInstr * Def1 = MRI -> getVRegDef ( RO1 . getReg ( ) ) ; MachineInstr * Def3 = MRI -> getVRegDef ( RO3 . getReg ( ) ) ; if ( ! TII -> isPredicable ( * Def1 ) || ! TII -> isPredicable ( * Def3 ) ) Cost ++ ; } return Cost ;


<s> else fputs ( <STR_LIT> , file ) ; if ( align > <NUM_LIT> ) fprintf ( file , <STR_LIT> , ( size & <NUM_LIT> ) / <NUM_LIT> ) ; else fprintf ( file , <STR_LIT> , size & <NUM_LIT> ) ; } else { if ( global ) { fprintf ( file , <STR_LIT> ) ; assemble_name ( file , name ) ;


<s> static void note_np_check_stores ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ATTRIBUTE_UNUSED ) {

if ( REG_P ( x ) && ( REGNO ( x ) == REG_CC || ( int ) REGNO ( x ) == np_check_regno ) ) np_check_regno = - <NUM_LIT> ;


<s> if ( TARGET_A24 ) ofs = ( ofs + <NUM_LIT> ) & ~ <NUM_LIT> ; fprintf ( stderr , <STR_LIT> , from , to , ofs ) ;