<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> <STR_LIT> <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) {


<s> return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ;


<s> if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH ) return <NUM_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && ! ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || ( GET_RTX_CLASS ( code ) == RTX_COMM_ARITH && rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ) ) return <NUM_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH && ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <NUM_LIT> ;


<s> NVVMIntrRangePass :: NVVMIntrRangePass ( ) : NVVMIntrRangePass ( NVVMIntrRangeSM ) {


<s> return TARGET_PLUS_QMACW ? V4HImode : V2HImode ; case SImode : return V2SImode ; default : return word_mode ; }


<s> switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : case FK_PCRel_4 : return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RELAX ;


<s> bool isSVEVectorReg ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: SVEVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> <ISA_LIT>CollectLOH ( ) : MachineFunctionPass ( ID ) {


<s> Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ; if ( Opc == <STR_LIT> ) { SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits + NumBits - <NUM_LIT> , dl , OpVT ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Ops ) ; } Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , dl , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ; return Op ;


<s> MVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && VT == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; MVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue OutOps [ ] = { OutLo , OutHi } ;

return DAG . getMergeValues ( OutOps , <NUM_LIT> , dl ) ;


<s> explicit <ISA_LIT>ompactFrameLowering ( const <ISA_LIT>ompactSubtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ; } if ( VT . getSizeInBits ( ) > InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; MVT ExtVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( ) ) , VT . getVectorNumElements ( ) ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( Op . getOpcode ( ) , dl , VT , Ext ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , Br , DL , NewDesc ) ; for ( unsigned I = <NUM_LIT> , E = Br -> getDesc ( ) . getNumOperands ( ) ; I < E ; ++ I ) { MachineOperand & MO = Br -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) { assert ( MO . isMBB ( ) && <STR_LIT> ) ; break ; } MIB . addReg ( MO . getReg ( ) ) ; } MIB . addMBB ( MBBOpnd ) ; if ( Br -> hasDelaySlot ( ) ) { assert ( Br -> isBundledWithSucc ( ) ) ; MachineBasicBlock :: instr_iterator II ( Br ) ; MIBundleBuilder ( & * MIB ) . append ( ( ++ II ) -> removeFromBundle ( ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != Stages ; ++ i ) { const auto * BO = dyn_cast < BinaryOperator > ( Op ) ; if ( ! BO || BO -> getOpcode ( ) != Instruction :: Add ) return nullptr ; if ( i != <NUM_LIT> && ! BO -> hasNUses ( <NUM_LIT> ) ) return nullptr ; Value * LHS = BO -> getOperand ( <NUM_LIT> ) ; Value * RHS = BO -> getOperand ( <NUM_LIT> ) ; auto * Shuffle = dyn_cast < ShuffleVectorInst > ( LHS ) ; if ( Shuffle ) { Op = RHS ; } else { Shuffle = dyn_cast < ShuffleVectorInst > ( RHS ) ; Op = LHS ; } if ( ! Shuffle || Shuffle -> getOperand ( <NUM_LIT> ) != Op ) return nullptr ; unsigned MaskEnd = <NUM_LIT> << i ; for ( unsigned Index = <NUM_LIT> ; Index < MaskEnd ; ++ Index ) if ( Shuffle -> getMaskValue ( Index ) != ( int ) ( MaskEnd + Index ) ) return nullptr ; }


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineInstr * LoadMI ) const {


<s> void <ISA_LIT>AsmPrinter :: PrintDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) {


<s> nop = gen_nop ( ) ; } else if ( TARGET_FP && ! ( in_use & EV4_IB1 ) ) { in_use |= EV4_IB1 ; nop = gen_fnop ( ) ; } else nop = gen_unop ( ) ; * pin_use = in_use ; return nop ;


<s> const char * output_in_line_mul ( ) { static char insns [ <NUM_LIT> ] ; int i ;


<s> else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } SmallPtrSet < MachineInstr * , <NUM_LIT> > Visited ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { LoLoop . End } ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Remove ;

if ( ! IsSafeToRemove ( LoLoop . Dec , RDA , Visited , Remove , Ignore ) ) {


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) {

PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( true , OSABI , ELF :: EM_<ISA_LIT> , false ) {


<s> bool isImm7Shift0 ( ) const { return isImmediate < - <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> bool isAISrc_1024F16 ( ) const { return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; rtx op2 ; machine_mode tmode = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; if ( optimize || target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op0 = safe_vector_operand ( op0 , mode0 ) ; op1 = safe_vector_operand ( op1 , mode1 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ;


<s> if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) { Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , Val , <STR_LIT> ) , SDLoc ( Op ) , <STR_LIT> ) ; return true ; }


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> return :: isAllActivePredicate ( DAG , N ) ;


<s> LRegion -> replaceLiveOut ( Register , NewRegister ) ; for ( auto & CI : Children ) { if ( CI -> isRegion ( ) ) { CI -> getRegionMRT ( ) -> replaceLiveOutReg ( Register , NewRegister ) ; }


<s> <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStandardEncoding ( ) ) addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool IsLittleEndian , bool Is64Bit ) {

MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI , Is64Bit , IsLittleEndian ) ;


<s> case PLUS : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : case IOR : return <NUM_LIT> ;


<s> MIRBuilder . setInstrAndDebugLoc ( MI ) ; unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast ( NewTy , ValReg ) ; MIRBuilder . buildStore ( Bitcast . getReg ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , MMO ) ; } else { auto NewLoad = MIRBuilder . buildLoad ( NewTy , MI . getOperand ( <NUM_LIT> ) , MMO ) ; MIRBuilder . buildBitcast ( ValReg , NewLoad ) ; } MI . eraseFromParent ( ) ; return true ;


<s> <ISA_LIT>_32TargetMachine :: <ISA_LIT>_32TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>TargetMachine ( T , TT , FS , false ) , DataLayout ( getSubtargetImpl ( ) -> isTargetDarwin ( ) ? <STR_LIT> : ( getSubtargetImpl ( ) -> isTargetCygMing ( ) || getSubtargetImpl ( ) -> isTargetWindows ( ) ) ? <STR_LIT> :

<STR_LIT> ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this ) , JITInfo ( * this ) {


<s> case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom : return ST . get<ISA_LIT>AS ( ) . CONSTANT_ADDRESS ; }

return ST . get<ISA_LIT>AS ( ) . FLAT_ADDRESS ;


<s> if ( inse ) { o01 = inse -> getOperand ( <NUM_LIT> ) ; } else if ( auto nextshuff = dyn_cast < ShuffleVectorInst > ( shufop ) ) { o01 = consider_shuffle ( nextshuff ) ; }


<s> void <ISA_LIT>InstPrinter :: printV4 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O << <STR_LIT> ;


<s> bool applyShiftAndToMak ( MachineInstr & MI , MachineRegisterInfo & MRI , std :: tuple < Register , uint32_t , uint32_t > & MatchInfo ) { assert ( MI . getOpcode ( ) == TargetOpcode :: G_SHL ) ; replaceMI ( <STR_LIT> , MI , MRI , MatchInfo ) ; return true ;


<s> if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return false ; if ( Subtarget . hasAVX512 ( ) ) return true ; bool LShift = VT . is128BitVector ( ) || VT . is256BitVector ( ) ; bool AShift = LShift && VT != <STR_LIT> && VT != <STR_LIT> ; return ( Opcode == <STR_LIT> ) ? AShift : LShift ;


<s> static void emitThumbConstant ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned DestReg , int Imm , const TargetInstrInfo & TII , const <ISA_LIT>RegisterInfo & MRI , DebugLoc dl ) { bool isSub = Imm < <NUM_LIT> ; if ( isSub ) Imm = - Imm ;

int Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ;


<s> <ISA_LIT>HazardRecognizer ( const MachineSchedContext * C ) : DAG ( nullptr ) , SchedModel ( nullptr ) {


<s> bool isArithmeticShifter ( ) const { if ( ! isShifter ( ) ) return false ; <STR_LIT> ST = <STR_LIT> ( Shifter . Val ) ; return ST == <STR_LIT> || ST == <STR_LIT> || ST == <STR_LIT> ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOLoad ) ; unsigned Opc = <NUM_LIT> ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; bool ReqIndirectLoad = Func -> hasFnAttribute ( <STR_LIT> ) && ( DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> || DestReg == <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) || TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ;


<s> decl_callee = TREE_TYPE ( decl_callee ) ; } else { decl_callee = fntype_callee ; while ( FUNCTION_TYPE != TREE_CODE ( decl_callee ) && METHOD_TYPE != TREE_CODE ( decl_callee ) ) { decl_callee = TREE_TYPE ( decl_callee ) ; } } if ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal || cfun -> machine -> is_naked || avr_naked_function_p ( decl_callee ) || ( avr_OS_task_function_p ( decl_callee ) != cfun -> machine -> is_OS_task ) || ( avr_OS_main_function_p ( decl_callee ) != cfun -> machine -> is_OS_main ) ) {


<s> case fixup_<ISA_LIT>_7_X : case fixup_<ISA_LIT>_6_X : case fixup_<ISA_LIT>_COPY : case fixup_<ISA_LIT>_GLOB_DAT : case fixup_<ISA_LIT>_JMP_SLOT : case fixup_<ISA_LIT>_RELATIVE : case fixup_<ISA_LIT>_PLT_B22_PCREL : case fixup_<ISA_LIT>_GOTREL_LO16 : case fixup_<ISA_LIT>_GOTREL_HI16 : case fixup_<ISA_LIT>_GOTREL_32 : case fixup_<ISA_LIT>_GOT_LO16 : case fixup_<ISA_LIT>_GOT_HI16 : case fixup_<ISA_LIT>_GOT_32 : case fixup_<ISA_LIT>_GOT_16 : case fixup_<ISA_LIT>_DTPMOD_32 : case fixup_<ISA_LIT>_DTPREL_LO16 : case fixup_<ISA_LIT>_DTPREL_HI16 : case fixup_<ISA_LIT>_DTPREL_32 : case fixup_<ISA_LIT>_DTPREL_16 : case fixup_<ISA_LIT>_GD_PLT_B22_PCREL : case fixup_<ISA_LIT>_LD_PLT_B22_PCREL : case fixup_<ISA_LIT>_GD_GOT_LO16 : case fixup_<ISA_LIT>_GD_GOT_HI16 : case fixup_<ISA_LIT>_GD_GOT_32 : case fixup_<ISA_LIT>_GD_GOT_16 : case fixup_<ISA_LIT>_LD_GOT_LO16 : case fixup_<ISA_LIT>_LD_GOT_HI16 : case fixup_<ISA_LIT>_LD_GOT_32 : case fixup_<ISA_LIT>_LD_GOT_16 : case fixup_<ISA_LIT>_IE_LO16 : case fixup_<ISA_LIT>_IE_HI16 : case fixup_<ISA_LIT>_IE_32 : case fixup_<ISA_LIT>_IE_16 : case fixup_<ISA_LIT>_IE_GOT_LO16 : case fixup_<ISA_LIT>_IE_GOT_HI16 : case fixup_<ISA_LIT>_IE_GOT_32 : case fixup_<ISA_LIT>_IE_GOT_16 : case fixup_<ISA_LIT>_TPREL_LO16 : case fixup_<ISA_LIT>_TPREL_HI16 : case fixup_<ISA_LIT>_TPREL_32 : case fixup_<ISA_LIT>_TPREL_16 : case fixup_<ISA_LIT>_GOTREL_32_6_X : case fixup_<ISA_LIT>_GOTREL_16_X : case fixup_<ISA_LIT>_GOTREL_11_X : case fixup_<ISA_LIT>_GOT_32_6_X : case fixup_<ISA_LIT>_GOT_16_X : case fixup_<ISA_LIT>_GOT_11_X : case fixup_<ISA_LIT>_DTPREL_32_6_X : case fixup_<ISA_LIT>_DTPREL_16_X : case fixup_<ISA_LIT>_DTPREL_11_X : case fixup_<ISA_LIT>_GD_GOT_32_6_X : case fixup_<ISA_LIT>_GD_GOT_16_X : case fixup_<ISA_LIT>_GD_GOT_11_X : case fixup_<ISA_LIT>_LD_GOT_32_6_X : case fixup_<ISA_LIT>_LD_GOT_16_X : case fixup_<ISA_LIT>_LD_GOT_11_X : case fixup_<ISA_LIT>_IE_32_6_X : case fixup_<ISA_LIT>_IE_16_X :


<s> gcc_assert ( MEM_P ( mem ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , get_frame_alias_set ( ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - size_int ) ) ) ) ; if ( flag_stack_clash_protection ) { add_reg_note ( insn , REG_STACK_CHECK , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; }


<s> DebugLoc DL = Inst -> getDebugLoc ( ) ; MachineOperand & Dest = Inst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst -> getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( AMDGPU :: V_BCNT_U32_B32_e64 ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & AMDGPU :: SGPR_32RegClass ; unsigned MidReg = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; unsigned ResultReg = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , AMDGPU :: sub0 ) ; MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , AMDGPU :: sub0 , SrcSubRC ) ; MachineOperand SrcRegSub1 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , AMDGPU :: sub1 , SrcSubRC ) ; MachineInstr * First = BuildMI ( MBB , MII , DL , InstDesc , MidReg ) . addOperand ( SrcRegSub0 ) . addImm ( <NUM_LIT> ) ;

MachineInstr * Second = BuildMI ( MBB , MII , DL , InstDesc , ResultReg ) . addOperand ( SrcRegSub1 ) . addReg ( MidReg ) ;


<s> explicit CountValue ( int64_t i ) : Kind ( CV_Immediate ) , Contents ( i ) , isNegative ( i < <NUM_LIT> ) {


<s> const MCGNodes * SCC = & i -> first ; MCGNodeSet preds ; for ( MCGNodes :: const_iterator j ( SCC -> begin ( ) ) , je ( SCC -> end ( ) ) ; j != je ; j ++ ) { for ( MCGSites :: const_iterator k ( ( * j ) -> getCallingSites ( ) . begin ( ) ) , ke ( ( * j ) -> getCallingSites ( ) . end ( ) ) ; k != ke ; k ++ ) { if ( & SCCMap [ ( * k ) -> getCaller ( ) ] -> first != SCC ) { preds . insert ( ( * k ) -> getCaller ( ) ) ; } } } for ( MCGNodes :: const_iterator j ( SCC -> begin ( ) ) , je ( SCC -> end ( ) ) ; j != je ; j ++ ) { if ( preds . size ( ) == <NUM_LIT> ) WL . push_back ( * j ) ; else predCount [ * j ] = preds . size ( ) ; } } while ( ! WL . empty ( ) ) { MCGNode * tmp = WL . back ( ) ;


<s> if ( * RM == Reloc :: DynamicNoPIC && ! TT . isOSDarwin ( ) ) return Reloc :: Static ;


<s> default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case MachineOperand :: MO_Register : assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ;

case MachineOperand :: MO_GlobalAddress :


<s> switch ( classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) ) { case EHPersonality :: MSVC_<ISA_LIT>SEH : return <NUM_LIT> ; case EHPersonality :: MSVC_CXX : return <NUM_LIT> ; default : break ; }


<s> void <ISA_LIT>AsmParser :: createCpRestoreMemOp ( bool IsLoad , int StackOffset , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI ) { <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; if ( IsLoad ) {

TOut . emitLoadWithImmOffset ( <STR_LIT> , <STR_LIT> , <STR_LIT> , StackOffset , <STR_LIT> , IDLoc , STI ) ;


<s> rtl_opt_pass * make_pass_arc_predicate_delay_insns ( gcc :: context * ctxt ) { return new pass_arc_predicate_delay_insns ( ctxt ) ;


<s> const <STR_LIT> * Reg = lookupSysReg ( Val , false , STI ) ; if ( isValidSysReg ( Reg , false , STI ) ) O << Reg -> Name ; else O << <STR_LIT> ( Val ) ;


<s> switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> int Scale = <NUM_LIT> ; unsigned ImmOp ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : ImmOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : ImmOp = <NUM_LIT> ;


<s> unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) - <STR_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << Reg << '\n' ) ; BuildMI ( * MBB , Inst , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; pushReg ( Reg ) ; break ; } case TargetOpcode :: INLINEASM : { unsigned STUses = <NUM_LIT> , STDefs = <NUM_LIT> , STClobbers = <NUM_LIT> , STDeadDefs = <NUM_LIT> ; unsigned NumOps = <NUM_LIT> ; SmallSet < unsigned , <NUM_LIT> > FRegIdx ; unsigned RCID ; for ( unsigned i = InlineAsm :: MIOp_FirstOperand , e = MI . getNumOperands ( ) ; i != e && MI . getOperand ( i ) . isImm ( ) ; i += <NUM_LIT> + NumOps ) { unsigned Flags = MI . getOperand ( i ) . getImm ( ) ; NumOps = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumOps != <NUM_LIT> ) continue ; const MachineOperand & MO = MI . getOperand ( i + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) continue ; unsigned STReg = MO . getReg ( ) - <STR_LIT> ; if ( STReg >= <NUM_LIT> ) continue ; if ( InlineAsm :: hasRegClassConstraint ( Flags , RCID ) ) { FRegIdx . insert ( i + <NUM_LIT> ) ; continue ; } switch ( InlineAsm :: getKind ( Flags ) ) { case InlineAsm :: Kind_RegUse : STUses |= ( <NUM_LIT> << STReg ) ; break ; case InlineAsm :: Kind_RegDef : case InlineAsm :: Kind_RegDefEarlyClobber : STDefs |= ( <NUM_LIT> << STReg ) ; if ( MO . isDead ( ) ) STDeadDefs |= ( <NUM_LIT> << STReg ) ; break ; case InlineAsm :: Kind_Clobber : STClobbers |= ( <NUM_LIT> << STReg ) ; break ; default : break ; } } if ( STUses && ! isMask_32 ( STUses ) ) MI . emitError ( <STR_LIT> ) ; unsigned NumSTUses = countTrailingOnes ( STUses ) ; if ( STDefs && ! isMask_32 ( STDefs ) ) { MI . emitError ( <STR_LIT> ) ; STDefs = NextPowerOf2 ( STDefs ) - <NUM_LIT> ; } unsigned NumSTDefs = countTrailingOnes ( STDefs ) ; if ( STClobbers && ! isMask_32 ( STDefs | STClobbers ) ) MI . emitError ( <STR_LIT> ) ; unsigned STPopped = STUses & ( STDefs | STClobbers ) ; if ( STPopped && ! isMask_32 ( STPopped ) ) MI . emitError ( <STR_LIT> ) ; unsigned NumSTPopped = countTrailingOnes ( STPopped ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NumSTUses << <STR_LIT> << NumSTPopped << <STR_LIT> << NumSTDefs << <STR_LIT> ) ;

for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I < E ; ++ I ) if ( FRegIdx . count ( I ) ) {


<s> MachineInstr * MI1 = Arguments -> MI ; MachineInstr * MI2 = & * NextMII ; Register RegDstMI1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RegSrcMI1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! IsMovepSrcRegister ( RegSrcMI1 ) ) return false ; if ( ! IsMovepDestinationReg ( RegDstMI1 ) ) return false ;

if ( MI2 -> getOpcode ( ) != Entry . WideOpc ( ) ) return false ;


<s> MVT VecTy = ty ( Vec ) ; if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy , true ) ) return LowerHvxExtractElement ( Op , DAG ) ; MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ;

return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ElemTy , ty ( Op ) , DAG ) ;


<s> return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV :

if ( CallsEHReturn ) return CSR_64EHRet_SaveList ;


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ;


<s> static poly_int64 ix86_return_pops_args ( tree fundecl , tree funtype , poly_int64 size ) { unsigned int ccvt ; if ( TARGET_64BIT ) return <NUM_LIT> ; ccvt = ix86_get_callcvt ( funtype ) ; if ( ( ccvt & ( IX86_CALLCVT_STDCALL | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL ) ) != <NUM_LIT> && ! stdarg_p ( funtype ) ) return size ; if ( aggregate_value_p ( TREE_TYPE ( funtype ) , fundecl ) && ! ix86_keep_aggregate_return_pointer ( funtype ) ) { int nregs = ix86_function_regparm ( funtype , fundecl ) ; if ( nregs == <NUM_LIT> ) return GET_MODE_SIZE ( Pmode ) ; }


<s> return AtomicRMWExpansionKind :: LLSC ;


<s> if ( Info0 -> BitsPerComp != <NUM_LIT> ) return false ; if ( getBufferFormatWithCompCount ( CI . Format , CI . Width + Paired . Width , STI ) == <NUM_LIT> ) return false ; } unsigned EltOffset0 = CI . Offset / CI . EltSize ; unsigned EltOffset1 = Paired . Offset / CI . EltSize ; CI . UseST64 = false ; CI . BaseOff = <NUM_LIT> ; if ( ( CI . InstClass != DS_READ ) && ( CI . InstClass != DS_WRITE ) ) { return ( EltOffset0 + CI . Width == EltOffset1 || EltOffset1 + Paired . Width == EltOffset0 ) && CI . GLC == Paired . GLC && CI . DLC == Paired . DLC && ( CI . InstClass == S_BUFFER_LOAD_IMM || CI . SLC == Paired . SLC ) ; } if ( ( EltOffset0 % <NUM_LIT> == <NUM_LIT> ) && ( EltOffset1 % <NUM_LIT> ) == <NUM_LIT> && isUInt < <NUM_LIT> > ( EltOffset0 / <NUM_LIT> ) && isUInt < <NUM_LIT> > ( EltOffset1 / <NUM_LIT> ) ) {


<s> int64_t Value = CE -> getValue ( ) ;

return Value >= <NUM_LIT> && Value < <NUM_LIT> ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


<s> unsigned BitWidth = KnownZero . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , <NUM_LIT> ) ; APInt KnownZero2 ; APInt KnownOne2 ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { KnownZero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CWidth ) return ; uint32_t Width = CWidth -> getZExtValue ( ) & <NUM_LIT> ; if ( Opc == <STR_LIT> ) KnownZero = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> - Width ) ; break ;


<s> arg_words = & cum -> arg_words ; regbase = ( incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST ) ; max = MAX_ARGS_IN_REGISTERS ; words = ( ( arg . promoted_size_in_bytes ( ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; if ( arg . type && ( TYPE_ALIGN ( arg . type ) > BITS_PER_WORD ) ) { int align = MIN ( TYPE_ALIGN ( arg . type ) , STACK_BOUNDARY ) / BITS_PER_WORD ; * arg_words = ( * arg_words + align - <NUM_LIT> ) & - align ; } if ( * arg_words + words > max ) return ( rtx ) <NUM_LIT> ; regno = regbase + * arg_words ; if ( cum -> incoming && regno <= A7_REG && regno + words > A7_REG ) cfun -> machine -> need_a7_copy = TARGET_WINDOWED_ABI ; return gen_rtx_REG ( arg . mode , regno ) ;


<s> if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) return <STR_LIT> ; for ( bs0 = <NUM_LIT> ; bs0 < HOST_BITS_PER_WIDE_INT ; bs0 ++ ) if ( ( mask & ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << bs0 ) ) != <NUM_LIT> ) break ; for ( bs1 = bs0 ; bs1 < HOST_BITS_PER_WIDE_INT ; bs1 ++ ) if ( ( mask & ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << bs1 ) ) == <NUM_LIT> ) break ; gcc_assert ( bs1 == HOST_BITS_PER_WIDE_INT || ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << bs1 ) > mask ) ; p = <NUM_LIT> - bs0 ; len = bs1 - bs0 ; operands [ <NUM_LIT> ] = GEN_INT ( p ) ; operands [ <NUM_LIT> ] = GEN_INT ( len ) ; return <STR_LIT> ;


<s> bool <ISA_LIT>ExpandPseudo :: expandASRB7Rd ( Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ;

bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ;


<s> static void riscv_restore_reg ( rtx reg , rtx mem ) { rtx insn = riscv_emit_move ( reg , mem ) ; rtx dwarf = NULL_RTX ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; REG_NOTES ( insn ) = dwarf ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; const SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) ; const SDValue One = DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Lt0 = DAG . getSetCC ( SL , SetCCVT , Src , Zero , <STR_LIT> ) ; SDValue NeTrunc = DAG . getSetCC ( SL , SetCCVT , Src , Trunc , <STR_LIT> ) ; SDValue And = DAG . getNode ( <STR_LIT> , SL , SetCCVT , Lt0 , NeTrunc ) ;

SDValue Add = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , And , One , Zero ) ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: commuteInstructionImpl ( MachineInstr & MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { <ISA_LIT>FunctionInfo & MFI = * MI . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ;

if ( MFI . isVRegStackified ( MI . getOperand ( OpIdx1 ) . getReg ( ) ) || MFI . isVRegStackified ( MI . getOperand ( OpIdx2 ) . getReg ( ) ) ) return nullptr ;


<s> if ( Op . isReg ( ) ) return makeRegRef ( Op . getReg ( ) , Op . getSubReg ( ) ) ;

return RegisterRef ( PRI . getRegMaskId ( Op . getRegMask ( ) ) , LaneBitmask :: getAll ( ) ) ;


<s> if ( TARGET_VECTOR ) return riscv_v_ext_vector_mode_p ( mode ) ;


<s> if ( ! IsVerboseAsm ) { OS << '\n' ; return ; }


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ;


<s> MachineInstr & MI = * I ; Next = std :: next ( I ) ; if ( TII -> isSGPRSpill ( MI ) ) { int FI = TII -> getNamedOperand ( MI , <STR_LIT> :: addr ) -> getIndex ( ) ; assert ( MFI . getStackID ( FI ) == <STR_LIT> ) ; if ( FuncInfo -> allocateSGPRSpillToVGPR ( MF , FI ) ) { bool Spilled = TRI . eliminateSGPRToVGPRSpillFrameIndex ( MI , FI , RS ) ; ( void ) Spilled ; assert ( Spilled && <STR_LIT> ) ; } else AllSGPRSpilledToVGPRs = false ; } } } FuncInfo -> removeSGPRToVGPRFrameIndices ( MFI ) ; } if ( FuncInfo -> hasNonSpillStackObjects ( ) || FuncInfo -> hasSpilledVGPRs ( ) || ! AllSGPRSpilledToVGPRs || ! allStackObjectsAreDead ( MFI ) ) { assert ( RS && <STR_LIT> ) ; int ScavengeFI = MFI . CreateFixedObject ( TRI . getSpillSize ( <STR_LIT> ) , <NUM_LIT> , false ) ; RS -> addScavengingFrameIndex ( ScavengeFI ) ;


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto DL = MIRBuilder . getMF ( ) . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . getArgumentList ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + <NUM_LIT> , DL , F ) ; ArgInfos . push_back ( AInfo ) ; Idx ++ ; }

FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , CC_<ISA_LIT> , DL ) ;


<s> int BaseCost = ST -> hasMVEIntegerOps ( ) ? ST -> getMVEVectorCostFactor ( ) : <NUM_LIT> ; if ( NumElts % Factor == <NUM_LIT> && TLI -> isLegalInterleavedAccessType ( Factor , SubVecTy , DL ) ) return Factor * BaseCost * TLI -> getNumInterleavedAccesses ( SubVecTy , DL ) ; if ( ST -> hasMVEIntegerOps ( ) && Factor == <NUM_LIT> && NumElts / Factor > <NUM_LIT> && VecTy -> isIntOrIntVectorTy ( ) && DL . getTypeSizeInBits ( SubVecTy ) <= <NUM_LIT> ) return <NUM_LIT> * BaseCost ;


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return & FrameLowering ;


<s> void toFeatureVector ( std :: vector < std :: string > & FeatureVector , const FeatureBitset & FeatureBits ) { for ( auto Feature : <ISA_LIT>FeatureKV ) { if ( FeatureBits [ Feature . Value ] && llvm :: <STR_LIT> ( Feature . Key ) ) FeatureVector . push_back ( std :: string ( <STR_LIT> ) + Feature . Key ) ;


<s> STI -> getFeatureBits ( ) . test ( FeatureWavefrontSize32 ) ;


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const TargetMachine & TM = DAG . getTarget ( ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , JTI , Zero ) ;

if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) {


<s> else if ( II && II -> getIntrinsicID ( ) == <STR_LIT> ) Scatters . push_back ( II ) ; } } bool Changed = false ; for ( unsigned i = <NUM_LIT> ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; if ( isa < GetElementPtrInst > ( I -> getArgOperand ( <NUM_LIT> ) ) ) optimiseOffsets ( cast < Instruction > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) , I -> getParent ( ) , & LI ) ; Value * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( L ) -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = <NUM_LIT> ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; if ( isa < GetElementPtrInst > ( I -> getArgOperand ( <NUM_LIT> ) ) ) optimiseOffsets ( cast < Instruction > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) , I -> getParent ( ) , & LI ) ; Value * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( cast < Instruction > ( S ) -> getParent ( ) ) ;


<s> static PredicateKind getPredicateSense ( const MachineInstr * MI , const <ISA_LIT>InstrInfo * HII ) { if ( ! HII -> isPredicated ( MI ) ) return PK_Unknown ; if ( HII -> isPredicatedTrue ( MI ) ) return PK_True ;


<s> if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( DefInfo . hasSameAVL ( CurInfo ) && DefInfo . hasSameVTYPE ( CurInfo ) ) return false ; } }


<s> SDValue RL = Op . getOperand ( <NUM_LIT> ) ; SDValue LH = DAG . getNode ( <STR_LIT> , DL , VT , LL , C63 ) ; SDValue RH = DAG . getNode ( <STR_LIT> , DL , VT , RL , C63 ) ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , <STR_LIT> , LL , RL , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SDValue NegLLTimesRH = DAG . getNode ( <STR_LIT> , DL , VT , LL , RH ) ; SDValue NegLHTimesRL = DAG . getNode ( <STR_LIT> , DL , VT , LH , RL ) ; SDValue NegSum = DAG . getNode ( <STR_LIT> , DL , VT , NegLLTimesRH , NegLHTimesRL ) ; Ops [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Ops [ <NUM_LIT> ] , NegSum ) ; }

return DAG . getMergeValues ( Ops , DL ) ;


<s> switch ( <ISA_LIT>CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return true ; case <STR_LIT> : return false ; case <STR_LIT> : return false ; case <STR_LIT> : return false ; case <STR_LIT> : return false ; case <STR_LIT> : return true ;


<s> unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s3 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ;

Inst . addOperand ( MCOperand :: createImm ( n ) ) ;


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return Opcode == Instruction :: PHI ? <NUM_LIT> : <NUM_LIT> ;

return CostKind == TTI :: TCK_RecipThroughput ? <NUM_LIT> : <NUM_LIT> ;


<s> int MCOpcode = AMDGPU :: getMCOpcode ( MIOpcode , AMDGPUSubtargetTo<ISA_LIT>Subtarget ( ST . getGeneration ( ) ) ) ;

if ( MCOpcode == - <NUM_LIT> ) MCOpcode = MIOpcode ;


<s> if ( Subtarget . hasCMov ( ) ) if ( SDValue RV = combineIntegerAbs ( N , DAG ) ) return RV ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ;

if ( isFNEG ( N ) ) return combineFneg ( N , DAG , Subtarget ) ;


<s> Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Constant * Idx = ConstantInt :: get ( Ty , Offset ) ; Constant * GAI = ConstantExpr :: getGetElementPtr ( Type :: getInt8Ty ( * DAG . getContext ( ) ) , GA , Idx ) ; SDValue CP = DAG . getConstantPool ( GAI , <STR_LIT> ) ;

return DAG . getLoad ( getPointerTy ( ) , DL , DAG . getEntryNode ( ) , CP , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> lastCheck = CI -> getParent ( ) ; DebugLoc DL3 = CI -> getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , cmpInst ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( reg ) ;

lastCheck -> insert ( CI , copyMoveM ) ;


<s> return EnableUnsafeDSOffsetFolding ;


<s> bool <ISA_LIT>AsmParser :: ParseLiteralValues ( unsigned Size , SMLoc L ) { auto parseOne = [ & ] ( ) -> bool {


<s> bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * CopySCC , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } if ( Size > <NUM_LIT> ) return false ; MachineInstr * Select = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; bool Ret = constrainSelectedInstRegOperands ( * Select , TII , TRI , RBI ) ;


<s> IRPromoter ( Module * M ) : M ( M ) , Ctx ( M -> getContext ( ) ) {


<s> MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_FPImmediate : { assert ( MO . getFPImm ( ) -> isZero ( ) && <STR_LIT> ) ; MCOp = MCOperand :: CreateFPImm ( <NUM_LIT> ) ; break ; } case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ;


<s> static bool mmix_pass_by_reference ( const CUMULATIVE_ARGS * argsp , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return true ;

if ( MMIX_FUNCTION_ARG_SIZE ( mode , type ) > <NUM_LIT> && ! TARGET_LIBFUNC && ( ! argsp || ! argsp -> lib ) ) return true ;


<s> if ( ! I -> pred_empty ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) {


<s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useLVIControlFlowIntegrity ( ) ;


<s> const <ISA_LIT>FunctionInfo * FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ;

Optional < std :: string > OutlinerString = FI -> getOutliningStyle ( ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler :: Success ;


<s> SMLoc Loc = Parser . getLexer ( ) . getLoc ( ) ; std :: unique_ptr < <ISA_LIT>Operand > Expr = <ISA_LIT>Operand :: CreateImm ( nullptr , Loc , Loc ) ;

MCExpr const * & Val = Expr -> Imm . Val ;


<s> FunctionPass * llvm :: create<ISA_LIT>LowerBrUnless ( ) { return new <ISA_LIT>LowerBrUnless ( ) ;


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; }


<s> O << <STR_LIT> << emitCurrentABIString ( ) << '\n' ;

if ( Subtarget -> isABI_EABI ( ) ) O << <STR_LIT> << ( Subtarget -> isGP32bit ( ) ? <STR_LIT> : <STR_LIT> ) << '\n' ;


<s> Ld = BaseLd ; ByteOffset = <NUM_LIT> ; return true ; } switch ( Elt . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findEltLoadSrc ( Elt . getOperand ( <NUM_LIT> ) , Ld , ByteOffset ) ; case <STR_LIT> : if ( auto * IdxC = dyn_cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) { uint64_t Idx = IdxC -> getZExtValue ( ) ; if ( ( Idx % <NUM_LIT> ) == <NUM_LIT> && findEltLoadSrc ( Elt . getOperand ( <NUM_LIT> ) , Ld , ByteOffset ) ) { ByteOffset += Idx / <NUM_LIT> ; return true ; } }


<s> return ( uint8x8_t ) __builtin_neon_vpaddv8qi ( ( int8x8_t ) __a , ( int8x8_t ) __b ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( Memory . OffsetRegNum ) ) ; if ( ! Memory . OffsetRegNum ) { if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val , <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ;

} else Inst . addOperand ( MCOperand :: createExpr ( Memory . OffsetImm ) ) ;


<s> if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ; return Val > - <NUM_LIT> && Val < <NUM_LIT> ;


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;

SDValue Res = DAG . getTargetBlockAddress ( Node -> getBlockAddress ( ) , PtrVT ) ;


<s> if ( ( TREE_CODE ( decl_op1 ) == VAR_DECL || TREE_CODE ( decl_op1 ) == CONST_DECL ) && ( TREE_CODE ( decl_op0 ) == VAR_DECL || TREE_CODE ( decl_op0 ) == CONST_DECL ) ) return ( get_variable_section ( decl_op1 , false ) != get_variable_section ( decl_op0 , false ) ) ; if ( TREE_CODE ( decl_op1 ) == LABEL_DECL && TREE_CODE ( decl_op0 ) == LABEL_DECL ) return ( DECL_CONTEXT ( decl_op1 ) != DECL_CONTEXT ( decl_op0 ) ) ; }


<s> CCMask = CCMaskForCondCode ( Cond ) ; if ( CmpOp0 . getValueType ( ) . isFloatingPoint ( ) ) CCValid = <STR_LIT> ; else { IsUnsigned = CCMask & <STR_LIT> ; CCValid = <STR_LIT> ; CCMask &= CCValid ; adjustZeroCmp ( DAG , IsUnsigned , CmpOp0 , CmpOp1 , CCMask ) ; adjustSubwordCmp ( DAG , IsUnsigned , CmpOp0 , CmpOp1 , CCMask ) ; if ( preferUnsignedComparison ( DAG , CmpOp0 , CmpOp1 , CCMask ) ) IsUnsigned = true ; }


<s> MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is32Bit = ( MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ) ; auto ImmFns = selectArithImmed ( RHS ) ; unsigned Opc = OpcTable [ Is32Bit ] [ ImmFns . hasValue ( ) ] ; Register ZReg = Is32Bit ? <STR_LIT> : <STR_LIT> ; auto CmpMI = MIRBuilder . buildInstr ( Opc , { ZReg } , { LHS } ) ; if ( ImmFns ) { for ( auto & RenderFn : * ImmFns ) RenderFn ( CmpMI ) ; } else { CmpMI . addUse ( RHS . getReg ( ) ) ; } constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ;


<s> CurrentProgramInfo = <ISA_LIT>ProgramInfo ( ) ; const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; MF . setAlignment ( MFI -> isEntryFunction ( ) ? <NUM_LIT> : <NUM_LIT> ) ; SetupMachineFunction ( MF ) ; const <ISA_LIT>Subtarget & STM = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCContext & Context = getObjFileLowering ( ) . getContext ( ) ; if ( ! STM . isAmdHsaOS ( ) && ! STM . isAmdPalOS ( ) ) { MCSectionELF * ConfigSection = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; OutStreamer -> SwitchSection ( ConfigSection ) ; } if ( MFI -> isEntryFunction ( ) ) { get<ISA_LIT>ProgramInfo ( CurrentProgramInfo , MF ) ; } else { auto I = CallGraphResourceInfo . insert ( std :: make_pair ( & MF . getFunction ( ) , <ISA_LIT>FunctionResourceInfo ( ) ) ) ; <ISA_LIT>FunctionResourceInfo & Info = I . first -> second ; assert ( I . second && <STR_LIT> ) ; Info = analyzeResourceUsage ( MF ) ; } if ( STM . isAmdPalOS ( ) ) EmitPALMetadata ( MF , CurrentProgramInfo ) ; else if ( ! STM . isAmdHsaOS ( ) ) { EmitProgramInfo<ISA_LIT> ( MF , CurrentProgramInfo ) ; } DisasmLines . clear ( ) ; HexLines . clear ( ) ; DisasmLineMaxLen = <NUM_LIT> ; EmitFunctionBody ( ) ; if ( isVerbose ( ) ) { MCSectionELF * CommentSection = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; OutStreamer -> SwitchSection ( CommentSection ) ; if ( ! MFI -> isEntryFunction ( ) ) { OutStreamer -> emitRawComment ( <STR_LIT> , false ) ; <ISA_LIT>FunctionResourceInfo & Info = CallGraphResourceInfo [ & MF . getFunction ( ) ] ; emitCommonFunctionComments ( Info . NumVGPR , Info . getTotalNumSGPRs ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , Info . PrivateSegmentSize , getFunctionCodeSize ( MF ) , MFI ) ; return false ; } OutStreamer -> emitRawComment ( <STR_LIT> , false ) ;

emitCommonFunctionComments ( CurrentProgramInfo . NumVGPR , CurrentProgramInfo . NumSGPR , CurrentProgramInfo . ScratchSize , getFunctionCodeSize ( MF ) , MFI ) ;


<s> Ops . append ( Split ? <NUM_LIT> : <NUM_LIT> , DAG . getUNDEF ( EltVT ) ) ; continue ; } const APInt & V = Bits [ i ] ; assert ( V . getBitWidth ( ) == VT . getScalarSizeInBits ( ) && <STR_LIT> ) ; if ( Split ) { Ops . push_back ( DAG . getConstant ( V . trunc ( <NUM_LIT> ) , dl , EltVT ) ) ; Ops . push_back ( DAG . getConstant ( V . lshr ( <NUM_LIT> ) . trunc ( <NUM_LIT> ) , dl , EltVT ) ) ; } else if ( EltVT == <STR_LIT> ) { APFloat FV ( APFloat :: IEEEsingle ( ) , V ) ; Ops . push_back ( DAG . getConstantFP ( FV , dl , EltVT ) ) ; } else if ( EltVT == <STR_LIT> ) { APFloat FV ( APFloat :: IEEEdouble ( ) , V ) ; Ops . push_back ( DAG . getConstantFP ( FV , dl , EltVT ) ) ; } else { Ops . push_back ( DAG . getConstant ( V , dl , EltVT ) ) ; } } SDValue ConstsNode = DAG . getBuildVector ( ConstVecVT , dl , Ops ) ; return DAG . getBitcast ( VT , ConstsNode ) ;


<s> if ( AsmParser -> isVI ( ) ) return isVReg32 ( ) ; else if ( AsmParser -> isGFX9Plus ( ) ) return isRegClass ( <STR_LIT> ) || isInlinableImm ( type ) ; else return false ;


<s> Op -> Cop . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> static void getPrePostIndexedMemOpInfo ( const MachineInstr & MI , int & Scale , int & MinOffset , int & MaxOffset ) {


<s> assert ( ( isShiftedUInt < Width , Shift > ( Value ) ) ) ; return Value >> Shift ;


<s> <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , true ) {


<s> break ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset & <NUM_LIT> ) return <STR_LIT> ; else if ( Offset > <NUM_LIT> || Offset < <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : { int64_t Offset = ( Value & ~ <NUM_LIT> ) ; if ( Offset == <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : return checkPCRelOffset ( Value , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT> :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;

bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;


<s> if ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return false ; x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_ELF || TARGET_MACHO ) { bool large_toc_ok ; if ( DEFAULT_ABI == ABI_V4 && flag_pic ) return false ;

large_toc_ok = ( lra_in_progress && TARGET_CMODEL != CMODEL_SMALL && small_toc_ref ( x , VOIDmode ) ) ;


<s> case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( hasAGPRs ( RC ) ) { switch ( Count ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : default : llvm_unreachable ( <STR_LIT> ) ; }


<s> void <ISA_LIT>65816TargetAsmStreamer :: EmitSegEndDirective ( void ) { OS << indent ; OS << <STR_LIT> ;


<s> if ( sym ) { fprintf ( asm_out_file , <STR_LIT> ) ; output_address ( VOIDmode , sym ) ; fprintf ( asm_out_file , val ? <STR_LIT> : <STR_LIT> ) ;


<s> if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SPCopy , RegState :: Kill ) ; } } return true ;


<s> if ( Ins . empty ( ) ) return NotStructReturn ; const <STR_LIT> & Flags = Ins [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) ) return RegStructReturn ;


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) , Lowering ( * TM . getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


<s> MCObjectWriter * create<ISA_LIT>WinCOFFObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit ) { MCWinCOFFObjectTargetWriter * MOTW = new <ISA_LIT>WinCOFFObjectWriter ( Is64Bit ) ; return createWinCOFFObjectWriter ( MOTW , OS ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> for ( i = <NUM_LIT> ; i != <NUM_LIT> && SVOp -> getMaskElt ( i ) < <NUM_LIT> ; ++ i ) ; if ( i == <NUM_LIT> ) return - <NUM_LIT> ; unsigned ShiftAmt = SVOp -> getMaskElt ( i ) ; if ( ShiftAmt < i ) return - <NUM_LIT> ; ShiftAmt -= i ; for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i ) ) return - <NUM_LIT> ; return ShiftAmt ;


<s> switch ( N . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> return & InstrInfo . getRegisterInfo ( ) ;


<s> } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ;


<s> else if ( ValVT . isVector ( ) ) return LowerSTOREVector ( Op , DAG ) ;


<s> rtx ops [ <NUM_LIT> ] = { XEXP ( op , <NUM_LIT> ) , XEXP ( op , <NUM_LIT> ) } ; int op_is_t_count = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( t_reg_operand ( ops [ i ] , VOIDmode ) || negt_reg_operand ( ops [ i ] , VOIDmode ) ) op_is_t_count ++ ; else { set_of_reg op_set = sh_find_set_of_reg ( ops [ i ] , insn , prev_nonnote_nondebug_insn_bb ) ; if ( op_set . set_src == NULL_RTX ) continue ; if ( t_reg_operand ( op_set . set_src , VOIDmode ) || negt_reg_operand ( op_set . set_src , VOIDmode ) || sh_is_logical_t_store_expr ( op_set . set_src , op_set . insn ) ) op_is_t_count ++ ; } } return op_is_t_count == <NUM_LIT> ;


<s> static const char * const externs [ ] = { <STR_LIT> } ; int i ; int n ; n = ARRAY_SIZE ( externs ) ;

for ( i = <NUM_LIT> ; i < n ; i ++ ) fprintf ( file , <STR_LIT> , externs [ i ] ) ;


<s> static SDValue LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) { SDValue VecOp = Op . getOperand ( <NUM_LIT> ) ; SDValue ValOp = Op . getOperand ( <NUM_LIT> ) ; SDValue IdxOp = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; ConstantSDNode * CN = cast < ConstantSDNode > ( IdxOp ) ; assert ( CN != <NUM_LIT> && <STR_LIT> ) ;

EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;


<s> bool aarch64_move_imm ( HOST_WIDE_INT val , machine_mode mode ) { if ( aarch64_movw_imm ( val , mode ) || aarch64_movw_imm ( ~ val , mode ) ) return <NUM_LIT> ;

return aarch64_bitmask_imm ( val , mode ) ;


<s> int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ;

RS -> addScavengingFrameIndex ( RegScavFI ) ;


<s> DebugLoc dl = I == MBB -> end ( ) ? DebugLoc ( ) : I -> getDebugLoc ( ) ; if ( isAtTop ( RegNo ) ) return ; unsigned STReg = getSTReg ( RegNo ) ; unsigned RegOnTop = getStackEntry ( <NUM_LIT> ) ; std :: swap ( RegMap [ RegNo ] , RegMap [ RegOnTop ] ) ; if ( RegMap [ RegOnTop ] >= StackTop ) report_fatal_error ( <STR_LIT> ) ; std :: swap ( Stack [ RegMap [ RegOnTop ] ] , Stack [ StackTop - <NUM_LIT> ] ) ;

BuildMI ( * MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addReg ( STReg ) ;


<s> tag_insn_info ( rtx_insn * i , rtx d , rtx b , rtx o , bool w , bool p ) : insn ( i ) , dest ( d ) , base ( b ) , offset ( o ) , writeback ( w ) , ldp ( p ) {


<s> static inline __ev64_opaque__ __ev_set_u16_internal ( __ev64_opaque__ a , uint16_t b , uint32_t pos ) { union { __ev64_opaque__ v ; uint16_t i [ <NUM_LIT> ] ; } u ; u . v = a ; u . i [ pos ] = b ; return u . v ;


<s> switch ( code ) { case LE : case LEU : case GT : case GTU : std :: swap ( lo [ <NUM_LIT> ] , lo [ <NUM_LIT> ] ) ; std :: swap ( hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ) ; code = swap_condition ( code ) ; case LT : case LTU : case GE : case GEU : { bool uns = ( code == LTU || code == GEU ) ; rtx ( * sbb_insn ) ( machine_mode , rtx , rtx , rtx ) = uns ? gen_sub3_carry_ccc : gen_sub3_carry_ccgz ; if ( ! nonimmediate_operand ( lo [ <NUM_LIT> ] , submode ) ) lo [ <NUM_LIT> ] = force_reg ( submode , lo [ <NUM_LIT> ] ) ; if ( ! x86_64_general_operand ( lo [ <NUM_LIT> ] , submode ) ) lo [ <NUM_LIT> ] = force_reg ( submode , lo [ <NUM_LIT> ] ) ; if ( ! register_operand ( hi [ <NUM_LIT> ] , submode ) ) hi [ <NUM_LIT> ] = force_reg ( submode , hi [ <NUM_LIT> ] ) ; if ( ( uns && ! nonimmediate_operand ( hi [ <NUM_LIT> ] , submode ) ) || ( ! uns && ! x86_64_general_operand ( hi [ <NUM_LIT> ] , submode ) ) ) hi [ <NUM_LIT> ] = force_reg ( submode , hi [ <NUM_LIT> ] ) ; emit_insn ( gen_cmp_1 ( submode , lo [ <NUM_LIT> ] , lo [ <NUM_LIT> ] ) ) ; tmp = gen_rtx_SCRATCH ( submode ) ; emit_insn ( sbb_insn ( submode , tmp , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ) ) ; tmp = gen_rtx_REG ( uns ? CCCmode : CCGZmode , FLAGS_REG ) ; ix86_expand_branch ( code , tmp , const0_rtx , label ) ; return ; } default : break ; } label2 = gen_label_rtx ( ) ; code1 = code ; code2 = swap_condition ( code ) ; code3 = unsigned_condition ( code ) ; switch ( code ) { case LT : case GT : case LTU : case GTU : break ; case LE : code1 = LT ; code2 = GT ; break ; case GE : code1 = GT ; code2 = LT ; break ; case LEU : code1 = LTU ; code2 = GTU ; break ; case GEU : code1 = GTU ; code2 = LTU ; break ; case EQ : code1 = UNKNOWN ; code2 = NE ; break ; case NE : code2 = UNKNOWN ; break ; default : gcc_unreachable ( ) ; } if ( code1 != UNKNOWN ) ix86_expand_branch ( code1 , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] , label ) ; if ( code2 != UNKNOWN ) ix86_expand_branch ( code2 , hi [ <NUM_LIT> ] , hi [ <NUM_LIT> ] , label2 ) ;

ix86_expand_branch ( code3 , lo [ <NUM_LIT> ] , lo [ <NUM_LIT> ] , label ) ;


<s> } if ( VT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getSINTTOFP ( SrcVT , VT ) ) ; SDValue ValueToStore = Src ; if ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getStoreSize ( ) ; Align Alignment ( Size ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Alignment , false ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; Chain = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MPI , Alignment ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( VT , SrcVT , dl , Chain , StackSlot , MPI , Alignment , DAG ) ;

if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ;


<s> unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPEMI -> eraseFromParent ( ) ; BBInfo [ CPEBB -> getNumber ( ) ] . Size -= Size ; if ( CPEBB -> empty ( ) ) {

BBInfo [ CPEBB -> getNumber ( ) ] . Size = <NUM_LIT> ;


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const {

return & InstrInfo . getRegisterInfo ( ) ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; return splitAndLowerVectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ;


<s> MachineMemOperand * MMO = cast < MemSDNode > ( N ) -> getMemOperand ( ) ;

return DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } , N -> getSimpleValueType ( <NUM_LIT> ) , MMO ) ;


<s> void setPersonality ( const MCSymbol * Per ) { HasPersonality = <NUM_LIT> ;


<s> break ; case E_BLKmode : cum -> gp_reg_found = <NUM_LIT> ; cum -> arg_words += ( ( int_size_in_bytes ( arg . type ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; break ; case E_SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DFmode : cum -> arg_words += <NUM_LIT> ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DImode : cum -> gp_reg_found = <NUM_LIT> ; cum -> arg_words += <NUM_LIT> ; break ;


<s> const MachineOperand * <ISA_LIT>InstrInfo :: getNamedOperand ( const MachineInstr & MI , unsigned OperandName ) const { int Idx = AMDGPU :: getNamedOperandIdx ( MI . getOpcode ( ) , OperandName ) ; if ( Idx == - <NUM_LIT> ) return nullptr ;


<s> const ConstantFP * FV = cast < ConstantFPSDNode > ( Node ) -> getConstantFPValue ( ) ; EVT DestType = Node -> getValueType ( <NUM_LIT> ) ;

unsigned Alignment = TLI . getDataLayout ( ) -> getABITypeAlignment ( FV -> getType ( ) ) ;


<s> updateDefinedRegisters ( * MBBI , DefinedInBB , TRI ) ; if ( TII -> isPairableLdStInst ( * MBBI ) && tryToPairLdStInst ( MBBI ) ) Modified = true ; else ++ MBBI ; } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { if ( isMergeableLdStUpdate ( * MBBI ) && tryToMergeLdStUpdate ( MBBI ) ) Modified = true ; else ++ MBBI ; } return Modified ;


<s> assert ( IsValidLdStrOpc && <STR_LIT> ) ; if ( NonSExtOpc == getMatchingNonSExtOpcode ( OpcB , & PairIsValidLdStrOpc ) ) { Flags . setSExtIdx ( NonSExtOpc == ( unsigned ) OpcA ? <NUM_LIT> : <NUM_LIT> ) ; return true ; } if ( ! PairIsValidLdStrOpc ) return false ;

if ( isNarrowStore ( OpcA ) || isNarrowStore ( OpcB ) ) return false ;


<s> static tree c6x_build_builtin_va_list ( void ) {

return build_pointer_type ( char_type_node ) ;


<s> Optional < <ISA_LIT>MemOpInfo > <ISA_LIT>MemOpInfo :: getAtomicCmpxchgInfo ( const MachineBasicBlock :: iterator & MI ) { assert ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) ; if ( ! ( MI -> mayLoad ( ) && MI -> mayStore ( ) ) ) return None ; if ( MI -> getNumMemOperands ( ) == <NUM_LIT> ) return <ISA_LIT>MemOpInfo ( SyncScope :: System , AtomicOrdering :: SequentiallyConsistent , AtomicOrdering :: SequentiallyConsistent ) ;

return <ISA_LIT>MemOpInfo :: constructFromMIWithMMO ( MI ) ;


<s> return __builtin_shuffle ( a , ( uint32x2_t ) { <NUM_LIT> , <NUM_LIT> } ) ;


<s> bool hasSHA2 ( ) const { return HasSHA2 ;


<s> BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ;


<s> AddDefaultPred ( MIB ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo , getKillRegState ( Desired . isDead ( ) ) ) ) ; unsigned SBCrr = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( SBCrr ) ) . addReg ( StatusReg , RegState :: Define | RegState :: Dead ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi , getKillRegState ( Desired . isDead ( ) ) ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; StoreBB -> addLiveIn ( Addr . getReg ( ) ) ; StoreBB -> addLiveIn ( New . getReg ( ) ) ; addPostLoopLiveIns ( StoreBB , LiveRegs ) ; unsigned STREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( StoreBB , DL , TII -> get ( STREXD ) , StatusReg ) ; addExclusiveRegPair ( MIB , New , <NUM_LIT> , IsThumb , TRI ) ; MIB . addOperand ( Addr ) ; AddDefaultPred ( MIB ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( StatusReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ; StoreBB -> addSuccessor ( DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; addPostLoopLiveIns ( DoneBB , LiveRegs ) ; MBB . addSuccessor ( LoadCmpBB ) ; NextMBBI = MBB . end ( ) ;


<s> if ( ! NeedsStackRealignment && MFI -> getMaxAlignment ( ) > getStackAlignment ( ) ) report_fatal_error ( <STR_LIT> + Twine ( MF . getName ( ) ) + <STR_LIT> <STR_LIT> <STR_LIT> ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) NumBytes += MFI -> getMaxCallFrameSize ( ) ; NumBytes = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; if ( MFI -> getMaxAlignment ( ) > <NUM_LIT> ) { NumBytes = RoundUpToAlignment ( NumBytes , MFI -> getMaxAlignment ( ) ) ; } MFI -> setStackSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ;

unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ;


<s> case Instruction :: GetElementPtr : { const DataLayout & TD = * AP . TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; APInt OffsetAI ( TD . getPointerSizeInBits ( ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( TD , OffsetAI ) ; const MCExpr * Base = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: CreateAdd ( Base , MCConstantExpr :: Create ( Offset , Ctx ) , Ctx ) ; } case Instruction :: Trunc : case Instruction :: BitCast : return LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; case Instruction :: IntToPtr : { const DataLayout & TD = * AP . TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Op = ConstantExpr :: getIntegerCast ( Op , TD . getIntPtrType ( CV -> getContext ( ) ) , false ) ; return LowerConstant ( Op , AP ) ; } case Instruction :: PtrToInt : { const DataLayout & TD = * AP . TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; Constant * Op = CE -> getOperand ( <NUM_LIT> ) ; Type * Ty = CE -> getType ( ) ; const MCExpr * OpExpr = LowerConstant ( Op , AP ) ; if ( TD . getTypeAllocSize ( Ty ) == TD . getTypeAllocSize ( Op -> getType ( ) ) ) return OpExpr ; unsigned InBits = TD . getTypeAllocSizeInBits ( Op -> getType ( ) ) ; const MCExpr * MaskExpr = MCConstantExpr :: Create ( ~ <NUM_LIT> >> ( <NUM_LIT> - InBits ) , Ctx ) ; return MCBinaryExpr :: CreateAnd ( OpExpr , MaskExpr , Ctx ) ; } case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: SDiv : case Instruction :: SRem : case Instruction :: Shl : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : { const MCExpr * LHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; const MCExpr * RHS = LowerConstant ( CE -> getOperand ( <NUM_LIT> ) , AP ) ; switch ( CE -> getOpcode ( ) ) { default :


<s> MCAsmParser & Parser = getParser ( ) ; const MCExpr * Value ;

if ( getParser ( ) . parseExpression ( Value ) ) return true ;


<s> TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ;

TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , create<ISA_LIT>ELFStreamer ) ;


<s> if ( MEM_P ( src ) && ! matching_memory ) src = force_reg ( mode , src ) ; op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_e ( code , mode , src ) ) ; if ( reload_in_progress || code == NOT ) { gcc_assert ( code == NOT ) ; emit_insn ( op ) ; } else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , op , clob ) ) ) ; } if ( dst != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [ <NUM_LIT> ] , dst ) ;


<s> RegBegin = TRI -> getSubReg ( RegBegin , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( RegBegin ) ; unsigned RegOps = OpNum + <NUM_LIT> ; while ( MI -> getOperand ( RegOps ) . isReg ( ) ) { O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( RegOps ) . getReg ( ) ) ; RegOps ++ ; } O << <STR_LIT> ; return false ; } case 'R' : case 'Q' : { if ( OpNum == <NUM_LIT> ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNum - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; unsigned RC ; InlineAsm :: hasRegClassConstraint ( Flags , RC ) ; if ( RC == <STR_LIT> ) { if ( NumVals != <NUM_LIT> ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! MO . isReg ( ) ) return true ; const TargetRegisterInfo * TRI = MF -> getTarget ( ) . getRegisterInfo ( ) ; unsigned Reg = TRI -> getSubReg ( MO . getReg ( ) , ExtraCode [ <NUM_LIT> ] == 'Q' ? <STR_LIT> : <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } if ( NumVals != <NUM_LIT> ) return true ; unsigned RegOp = ExtraCode [ <NUM_LIT> ] == 'Q' ? OpNum : OpNum + <NUM_LIT> ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; } case 'e' : case 'f' : { if ( ! MI -> getOperand ( OpNum ) . isReg ( ) ) return true ; unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) ) return true ; const TargetRegisterInfo * TRI = MF -> getTarget ( ) . getRegisterInfo ( ) ; unsigned SubReg = TRI -> getSubReg ( Reg , ExtraCode [ <NUM_LIT> ] == 'e' ? <STR_LIT> : <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( SubReg ) ; return false ; } case 'h' : return true ;


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier = true ; break ; } } if ( isFastMultiplier ) { APInt Diff = TrueC -> getAPIntValue ( ) - FalseC -> getAPIntValue ( ) ; Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; if ( Diff != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( Diff , Cond . getValueType ( ) ) ) ; if ( FalseC -> getAPIntValue ( ) != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) return DCI . CombineTo ( N , Cond , SDValue ( ) ) ; return Cond ; } } } } if ( ! DCI . isBeforeLegalize ( ) && ! DCI . isBeforeLegalizeOps ( ) ) { ConstantSDNode * CmpAgainst = nullptr ; if ( ( Cond . getOpcode ( ) == <STR_LIT> || Cond . getOpcode ( ) == <STR_LIT> ) && ( CmpAgainst = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) && ! isa < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) { if ( CC == <STR_LIT> && CmpAgainst == dyn_cast < ConstantSDNode > ( FalseOp ) ) { CC = <STR_LIT> ( CC ) ; std :: swap ( TrueOp , FalseOp ) ; } if ( CC == <STR_LIT> && CmpAgainst == dyn_cast < ConstantSDNode > ( TrueOp ) ) { SDValue Ops [ ] = { FalseOp , Cond . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CC , <STR_LIT> ) , Cond } ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , Ops ) ; } } } return SDValue ( ) ;


<s> } for ( auto subscope : Subscopes ) { subscope -> Priv -> replaceUseOfBlockWith ( oldBlock , newBlock ) ; }


<s> } int Opcode = isImmU6 ( Value ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , dl , TII . get ( Opcode ) , DstReg ) . addImm ( Value ) ;


<s> if ( ( DataWidth < <NUM_LIT> ) || ( Consecutive == <NUM_LIT> ) ) return false ;

if ( ST -> hasAVX512 ( ) || ST -> hasAVX2 ( ) ) return true ;


<s> subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) return true ;

if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ;


<s> EdgeExec . clear ( ) ; InstrExec . clear ( ) ; assert ( FlowQ . empty ( ) ) ; propagate ( MF ) ; bool Changed = rewrite ( MF ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << Changed << <STR_LIT> ; if ( Changed ) MF . print ( dbgs ( ) , nullptr ) ;


<s> stringbuf buf ; char kind [ ] = { '-' , 'u' , 'd' , 'x' } ; for ( unsigned long i = <NUM_LIT> ; i < uses . size ( ) ; i ++ ) { int x = <NUM_LIT> ; if ( uses . test ( i ) ) x += <NUM_LIT> ; if ( defs . test ( i ) ) x += <NUM_LIT> ;


<s> rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( negate_p ) val = - val ; val &= GET_MODE_MASK ( GET_MODE_INNER ( GET_MODE ( x ) ) ) ;

if ( val & <NUM_LIT> ) return IN_RANGE ( val , <NUM_LIT> , <NUM_LIT> ) ;


<s> SDValue NewCond = LowerSETCC ( Cond , DAG ) ; if ( NewCond . getNode ( ) ) Cond = NewCond ; } SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op2 = Op . getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <STR_LIT> ) { SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) ; if ( Cmp . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( Op1 ) ; ConstantSDNode * N2C = dyn_cast < ConstantSDNode > ( Op2 ) ; ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( Cmp . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( N1C && N1C -> isAllOnesValue ( ) && N2C && N2C -> isNullValue ( ) && RHSC && RHSC -> isNullValue ( ) ) { SDValue CmpOp0 = Cmp . getOperand ( <NUM_LIT> ) ; Cmp = DAG . getNode ( <STR_LIT> , dl , CmpOp0 . getValueType ( ) , CmpOp0 , DAG . getConstant ( <NUM_LIT> , CmpOp0 . getValueType ( ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Cmp ) ; } } } if ( Cond . getOpcode ( ) == <STR_LIT> && Cond . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getAPIntValue ( ) == <NUM_LIT> ) Cond = Cond . getOperand ( <NUM_LIT> ) ; } if ( Cond . getOpcode ( ) == <STR_LIT> || Cond . getOpcode ( ) == <STR_LIT> ) { CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) ; unsigned Opc = Cmp . getOpcode ( ) ; EVT VT = Op . getValueType ( ) ; bool IllegalFPCMov = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && ! isScalarFPTypeInSSEReg ( VT ) ) IllegalFPCMov = ! hasFPCMov ( cast < ConstantSDNode > ( CC ) -> getSExtValue ( ) ) ; if ( ( is<ISA_LIT>LogicalCmp ( Cmp ) && ! IllegalFPCMov ) || Opc == <STR_LIT> ) { Cond = Cmp ; addTest = false ; }


<s> FlagsTy ( ) : IsFunc ( <NUM_LIT> ) , IsGV ( <NUM_LIT> ) {


<s> AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ; CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling :: WinEH ;

WinEHEncodingType = WinEH :: EncodingType :: Itanium ;


<s> unsigned Opc = MI -> getOpcode ( ) ; return <ISA_LIT>InstrInfo :: isVALU ( * MI ) && Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ; } ; if ( :: getWaitStatesSince ( IsHazardFn , MI , IsExpiredFn ) == std :: numeric_limits < int > :: max ( ) ) return false ; auto * Src0 = TII -> getNamedOperand ( * MI , <STR_LIT> :: src0 ) ; unsigned Reg = Src0 -> getReg ( ) ; bool IsUndef = Src0 -> isUndef ( ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define | ( IsUndef ? RegState :: Dead : <NUM_LIT> ) ) . addReg ( Reg , IsUndef ? RegState :: Undef : RegState :: Kill ) ;


<s> n += ss . jump_cycle_index ; if ( n >= <NUM_LIT> ) n -= <NUM_LIT> ;


<s> return ( __m256i ) __builtin_ia32_cvttps2dq256 ( ( __v8sf ) __A ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> MachineBasicBlock :: iterator <ISA_LIT>LoadStoreOptimizer :: mergeBufferStorePair ( CombineInfo & CI , CombineInfo & Paired ) { MachineBasicBlock * MBB = CI . I -> getParent ( ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; const unsigned Opcode = getNewOpcode ( CI , Paired ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI , Paired ) ; Register SrcReg = MRI -> createVirtualRegister ( SuperRC ) ; const auto * Src0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Src1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , Paired . I , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; const unsigned Regs = getRegs ( Opcode , * TII ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * Paired . I -> memoperands_begin ( ) ; MachineInstr * New = MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( std :: min ( CI . Offset , Paired . Offset ) ) . addImm ( CI . GLC ) . addImm ( CI . SLC ) . addImm ( <NUM_LIT> ) . addImm ( CI . DLC ) . addImm ( <NUM_LIT> ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ;

moveInstsAfter ( MIB , CI . InstsToMove ) ;


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;

return Infos [ Kind - FirstTargetFixupKind ] ;


<s> static DecodeStatus DecodeT2BROperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val ) ) ) ;


<s> SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LO , HI ; SDValue Chain = DAG . getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue rd = DAG . getNode ( <STR_LIT> , DL , Tys , Chain ) ; if ( Subtarget -> is64Bit ( ) ) { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } else { LO = DAG . getCopyFromReg ( rd , DL , <STR_LIT> , <STR_LIT> , rd . getValue ( <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } Chain = HI . getValue ( <NUM_LIT> ) ; if ( Subtarget -> is64Bit ( ) ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , HI , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;

Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LO , Tmp ) ) ;


<s> if ( INSN_P ( seq ) ) { insn = seq ; while ( insn != NULL_RTX ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = NEXT_INSN ( insn ) ; } seq = emit_insn ( seq ) ; } else { seq = emit_insn ( seq ) ; RTX_FRAME_RELATED_P ( seq ) = <NUM_LIT> ; } return seq ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasCalls ( ) && ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isEntryFunction ( ) ) { return MFI . getStackSize ( ) != <NUM_LIT> ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMOA ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( HasAlloca ) SlotAlign = HFI . getStackAlignment ( ) ; unsigned Opc = SlotAlign < RegAlign ? <STR_LIT> : <STR_LIT> ; MachineMemOperand * MMOA = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , SlotAlign ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMOA ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> return ( __m128i ) __builtin_ia32_pmovqd128_mask ( ( __v2di ) __A , ( __v4si ) _mm_setzero_si128 ( ) , __M ) ;


<s> if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ;


return HasAtomicFaddRtnInsts || HasAtomicFaddNoRtnInsts ;


<s> void PrintSwitchToSection ( const MCAsmInfo & MAI , raw_ostream & OS , const MCExpr * Subsection ) const override {


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const {

return SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ? AtomicExpansionKind :: Expand : AtomicExpansionKind :: None ;


<s> if ( regno >= CSKY_FIRST_VFP_REGNUM && ! CSKY_TARGET_ARCH ( CK803 ) ) return <NUM_LIT> ;


<s> AMDGPUInstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_LO : return ELF :: R_<ISA_LIT>_GOTPCREL32_LO ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_HI : return ELF :: R_<ISA_LIT>_GOTPCREL32_HI ; case MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_LO : return ELF :: R_<ISA_LIT>_REL32_LO ; case MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_HI : return ELF :: R_<ISA_LIT>_REL32_HI ; } switch ( Fixup . getKind ( ) ) { default : break ; case FK_PCRel_4 :


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const {


<s> <ISA_LIT>Operand :: Ptr <ISA_LIT>AsmParser :: defaultMubufOffset ( ) const {

return <ISA_LIT>Operand :: CreateImm ( <NUM_LIT> , SMLoc ( ) , <ISA_LIT>Operand :: ImmTyOffset ) ;


<s> unsigned EltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != j + WhichResult ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != j + WhichResult ) ) return false ; } }

if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ;


<s> while ( CurrVT != VT ) { int CurrScalarSizeInBits = CurrVT . getScalarSizeInBits ( ) ; int CurrNumElts = CurrVT . getVectorNumElements ( ) ; MVT NextSVT = <STR_LIT> ( CurrScalarSizeInBits * <NUM_LIT> ) ; MVT NextVT = <STR_LIT> ( NextSVT , CurrNumElts / <NUM_LIT> ) ; SDValue Shift = DAG . getConstant ( CurrScalarSizeInBits , DL , NextVT ) ; SDValue HiZ = DAG . getSetCC ( DL , CurrVT , DAG . getBitcast ( CurrVT , Op0 ) , DAG . getBitcast ( CurrVT , Zero ) , <STR_LIT> ) ; HiZ = DAG . getBitcast ( NextVT , HiZ ) ; SDValue ResNext = Res = DAG . getBitcast ( NextVT , Res ) ; SDValue R0 = DAG . getNode ( <STR_LIT> , DL , NextVT , ResNext , Shift ) ; SDValue R1 = DAG . getNode ( <STR_LIT> , DL , NextVT , HiZ , Shift ) ; R1 = DAG . getNode ( <STR_LIT> , DL , NextVT , ResNext , R1 ) ;

Res = DAG . getNode ( <STR_LIT> , DL , NextVT , R0 , R1 ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ;


<s> void <ISA_LIT>SEInstrInfo :: expandRetRA ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ;


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; ; MachineInstrBuilder Inst32 = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( Op32 ) ) ; int Op32DstIdx = <STR_LIT> ( Op32 , <STR_LIT> :: vdst ) ; if ( Op32DstIdx != - <NUM_LIT> ) { Inst32 . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else { assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; } Inst32 . add ( * getNamedOperand ( MI , <STR_LIT> :: src0 ) ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) Inst32 . add ( * Src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { int Op32Src2Idx = <STR_LIT> ( Op32 , <STR_LIT> :: src2 ) ; if ( Op32Src2Idx != - <NUM_LIT> ) { Inst32 . add ( * Src2 ) ; } else { copyFlagsToImplicitVCC ( * Inst32 , * Src2 ) ; }


return lowerVectorShuffleAsSplitOrBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ;


<s> if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Op . getImm ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Op . getImm ( ) ) ) { const <ISA_LIT>MCExpr * LHSSymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ;

return ( LHSSymbolRefExpr && LHSSymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) ;


<s> void mips_final_prescan_insn ( rtx_insn * insn , rtx * opvec , int noperands ) { if ( mips_need_noat_wrapper_p ( insn , opvec , noperands ) ) mips_push_asm_switch ( & mips_noat ) ;


<s> return __builtin_mve_vmaxq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __b , __p ) ;


<s> uint16_t Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm != <NUM_LIT> ) { O << ( ( OpNo == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; printS16ImmDecOperand ( MI , OpNo , O ) ;


<s> } if ( code == GTU ) { cop0 = force_reg ( mode , cop0 ) ; switch ( mode ) { case V16SImode : case V8DImode : case V8SImode : case V4DImode : case V4SImode : case V2DImode : { rtx t1 , t2 , mask ; rtx ( * gen_sub3 ) ( rtx , rtx , rtx ) ; switch ( mode ) { case V16SImode : gen_sub3 = gen_subv16si3 ; break ; case V8DImode : gen_sub3 = gen_subv8di3 ; break ; case V8SImode : gen_sub3 = gen_subv8si3 ; break ; case V4DImode : gen_sub3 = gen_subv4di3 ; break ; case V4SImode : gen_sub3 = gen_subv4si3 ; break ; case V2DImode : gen_sub3 = gen_subv2di3 ; break ; default : gcc_unreachable ( ) ; } mask = ix86_build_signbit_mask ( mode , true , false ) ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_sub3 ( t1 , cop0 , mask ) ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_sub3 ( t2 , cop1 , mask ) ) ; cop0 = t1 ; cop1 = t2 ; code = GT ; } break ; case V64QImode : case V32HImode : case V32QImode : case V16HImode : case V16QImode : case V8HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_US_MINUS ( mode , cop0 , cop1 ) ) ) ; cop0 = x ; cop1 = CONST0_RTX ( mode ) ; code = EQ ;


<s> extra = <NUM_LIT> ; break ; default : break ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( ( unsigned HOST_WIDE_INT ) ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) + <NUM_LIT> ) >= <NUM_LIT> - extra ) && ! ( SPE_VECTOR_MODE ( mode ) || ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) ) { HOST_WIDE_INT high_int , low_int ; rtx sum ; low_int = ( ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( low_int >= <NUM_LIT> - extra ) low_int = <NUM_LIT> ; high_int = INTVAL ( XEXP ( x , <NUM_LIT> ) ) - low_int ; sum = force_operand ( gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , GEN_INT ( high_int ) ) , <NUM_LIT> ) ; return plus_constant ( Pmode , sum , low_int ) ; } else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT && GET_MODE_NUNITS ( mode ) == <NUM_LIT> && ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD || ( ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ) && ( mode == DFmode || mode == DDmode ) ) ) && ! avoiding_indexed_address_p ( mode ) ) { return gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , force_reg ( Pmode , force_operand ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; } else if ( SPE_VECTOR_MODE ( mode ) || ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) { if ( mode == DImode ) return x ; if ( GET_CODE ( x ) == PLUS ) { rtx op1 = XEXP ( x , <NUM_LIT> ) ; rtx op2 = XEXP ( x , <NUM_LIT> ) ; rtx y ; op1 = force_reg ( Pmode , op1 ) ; if ( GET_CODE ( op2 ) != REG && ( GET_CODE ( op2 ) != CONST_INT || ! SPE_CONST_OFFSET_OK ( INTVAL ( op2 ) ) || ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && ! SPE_CONST_OFFSET_OK ( INTVAL ( op2 ) + <NUM_LIT> ) ) ) ) op2 = force_reg ( Pmode , op2 ) ; y = gen_rtx_PLUS ( Pmode , op1 , op2 ) ; if ( ( GET_MODE_SIZE ( mode ) > <NUM_LIT> || mode == DDmode ) && REG_P ( op2 ) ) return force_reg ( Pmode , y ) ;


<s> inline SDValue getImm ( const SDNode * Node , unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , Node -> getValueType ( <NUM_LIT> ) ) ;


if ( ! BB -> isLiveIn ( BasePtr ) ) BB -> addLiveIn ( BasePtr ) ;


<s> unsigned CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto IsMoveLR = [ & CountReg ] ( MachineInstr * MI ) { return MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == CountReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ; } ; MachineBasicBlock * MBB = Start -> getParent ( ) ; if ( auto * LRDef = RDA . getUniqueReachingMIDef ( Start , <STR_LIT> ) ) if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) return LRDef ; if ( auto * LRDef = RDA . getLocalLiveOutMIDef ( MBB , <STR_LIT> ) ) if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) return LRDef ; return RDA . isSafeToDefRegAt ( Start , <STR_LIT> ) ? Start : nullptr ;


<s> Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cvt ) ) ; } return ; } } break ; } case <STR_LIT> : { if ( SDValue Res = LowerINTRIN<ISA_LIT>C_W_CHAIN ( SDValue ( N , <NUM_LIT> ) , DAG ) ) { Results . push_back ( Res ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; } break ; } case <STR_LIT> : { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ; EVT SelectVT = NewVT ; if ( NewVT . bitsLT ( <STR_LIT> ) ) { LHS = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS ) ; SelectVT = <STR_LIT> ; } SDValue NewSelect = DAG . getNode ( <STR_LIT> , SL , SelectVT , N -> getOperand ( <NUM_LIT> ) , LHS , RHS ) ; if ( NewVT != SelectVT ) NewSelect = DAG . getNode ( <STR_LIT> , SL , NewVT , NewSelect ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , VT , NewSelect ) ) ; return ; } case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SDLoc SL ( N ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ) ; return ; } case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) break ; SDLoc SL ( N ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Op ) ) ; return ; } default : break ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( <STR_LIT> ) ;


<s> unsigned Opc ; if ( VT == XLenVT ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( N ) ; SDValue FpToInt = DAG . getNode ( Opc , DL , XLenVT , Src . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( FRM , DL , XLenVT ) ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , FpToInt ) ;


<s> } ; auto processPredecessors = [ & ] ( MachineBasicBlock * CurBB ) { auto beginRoad = BBInfo [ CurBB ] . roadBegin ( ) ; assert ( beginRoad && <STR_LIT> ) ; for ( auto Pred : CurBB -> predecessors ( ) ) { auto & CurInfo = BBInfo [ Pred ] ; auto endRoad = CurInfo . roadEnd ( ) ; assert ( ( beginRoad == endRoad || ! endRoad ) && <STR_LIT> ) ; if ( ! endRoad ) { CurInfo . setRoadEnd ( beginRoad ) ; queueThisRoad . push_back ( Pred ) ; if ( ! CurInfo . roadBegin ( ) ) queueNextRoads . push_back ( Pred ) ; } } } ; do { while ( ! queueThisRoad . empty ( ) ) { auto CurBB = queueThisRoad . front ( ) ; queueThisRoad . pop_front ( ) ; auto & CurInfo = BBInfo [ CurBB ] ; if ( CurInfo . roadBegin ( ) == curRoad ) processPredecessors ( CurBB ) ; if ( CurInfo . roadEnd ( ) == curRoad ) processSuccessors ( CurBB ) ; }


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) != <STR_LIT> ) { return false ; } Base = Addr . getOperand ( <NUM_LIT> ) ;

Offset = Addr . getOperand ( <NUM_LIT> ) ;


<s> Entry . Node = Argument ; Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getInt32Ty ( * DAG . getContext ( ) ) , DAG . getExternalFunctionSymbol ( <STR_LIT> ) , std :: move ( Args ) ) ;

std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ;


<s> return <STR_LIT> ; } if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) {