raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { while ( ( Count -- ) > <NUM_LIT> ) {


<s> else if ( Type == ( unsigned ) <STR_LIT> ) return getRegisterPairOdd ( Reg , MF ) ;

else if ( Type == ( unsigned ) <STR_LIT> ) return getRegisterPairEven ( Reg , MF ) ;


<s> Op -> FPImm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op ;


<s> bool single_dest_per_chain ( const rtx & t ATTRIBUTE_UNUSED , insn_info_list_t * v , void * arg ATTRIBUTE_UNUSED ) { for ( int i = v -> length ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { tag_insn_info * insn_info = ( * v ) [ i ] ; for ( int j = v -> length ( ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) { if ( in_same_chain ( insn_info -> insn , ( * v ) [ j ] -> insn , REGNO ( insn_info -> dest ) ) ) { v -> ordered_remove ( j ) ; i = v -> length ( ) ; break ; } } }


<s> ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; AscizDirective = <STR_LIT> ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ;


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; const TargetMachine & TM = DAG . getTarget ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) { return DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; }

if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> return Kind == k_Register && Reg . isVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> const unsigned Opcode = getNewOpcode ( CI ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI ) ; unsigned SrcReg = MRI -> createVirtualRegister ( SuperRC ) ; const auto * Src0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Src1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; const unsigned Regs = getRegs ( Opcode ) ;

if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReplaceableInstrs ) ; i != e ; ++ i ) if ( ReplaceableInstrs [ i ] [ domain - <NUM_LIT> ] == opcode ) return ReplaceableInstrs [ i ] ;


<s> assert ( ( Kind == k_Memory ) && <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3Mods0Clamp0OMod ( SDValue In , SDValue & Src , SDValue & SrcMods , SDValue & Clamp , SDValue & Omod ) const {

Clamp = Omod = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( In ) , <STR_LIT> ) ;


<s> const DataLayout TD = getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; OutStreamer -> EmitSymbolValue ( Stubs [ i ] . second . getPointer ( ) , TD . getPointerSize ( <NUM_LIT> ) , <NUM_LIT> ) ; } Stubs . clear ( ) ; }


<s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) , TailAgnostic ( false ) , MaskAgnostic ( false ) , MaskRegOp ( false ) , SEWLMULRatioOnly ( false ) {


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetGlobalAddressSymbol ( const MachineOperand & MO ) const { const GlobalValue * Global = MO . getGlobal ( ) ; if ( ! isa < Function > ( Global ) ) { auto * WasmSym = cast < MCSymbolWasm > ( Printer . getSymbol ( Global ) ) ; if ( <STR_LIT> ( Global -> getAddressSpace ( ) ) && ! WasmSym -> getType ( ) ) { const MachineFunction & MF = * MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const Function & CurrentFunc = MF . getFunction ( ) ; Type * GlobalVT = Global -> getValueType ( ) ;


<s> bool AMDGPUDAGToDAGISel :: SelectMUBUFAddr64 ( SDValue Addr , SDValue & SRsrc , SDValue & VAddr , SDValue & Offset , SDValue & SLC ) const { SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;

return SelectMUBUFAddr64 ( Addr , SRsrc , VAddr , Offset ) ;


<s> ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregciv2di_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x2_t ) __builtin_aarch64_get_qregciv2di_pss ( __o , <NUM_LIT> ) ;


<s> assert ( MI . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ;

MIB . addImm ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ) ) ;


<s> const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) -> getParent ( ) ; unsigned char OpFlag = Subtarget . classifyGlobalReference ( nullptr , * Mod ) ; unsigned WrapperKind = <STR_LIT> ; CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) WrapperKind = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( isPositionIndependent ( ) && ! Subtarget . is64Bit ( ) ) {

Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Result ) ;


<s> assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; unsigned B = Value & <NUM_LIT> ;


<s> if ( XTL . getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) return true ;

Type * ObjType = GV -> getValueType ( ) ;


<s> } } switch ( <ISA_LIT>16Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : if ( ! isTargetMachO ( STI ) && EvaluateAsPCRel ( E ) ) Kind = MCFixupKind ( isThumb2 ( STI ) ? <STR_LIT> : <STR_LIT> ) ; else Kind = MCFixupKind ( isThumb2 ( STI ) ? <STR_LIT> : <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : if ( ! isTargetMachO ( STI ) && EvaluateAsPCRel ( E ) ) Kind = MCFixupKind ( isThumb2 ( STI ) ? <STR_LIT> : <STR_LIT> ) ; else Kind = MCFixupKind ( isThumb2 ( STI ) ? <STR_LIT> : <STR_LIT> ) ; break ; } Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , E , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ;


<s> MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , MachineInstr * LoadMI ) const override { return nullptr ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ;


<s> int nb , ne ; if ( ! rs6000_is_valid_mask ( operands [ <NUM_LIT> ] , & nb , & ne , mode ) ) gcc_unreachable ( ) ; if ( mode == DImode && ne == <NUM_LIT> ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LSHIFTRT && INTVAL ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - INTVAL ( operands [ <NUM_LIT> ] ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( mode == DImode && nb == <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - ne ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ;


<s> return decodeRegisterClass ( Inst , RegNo , CRRegs ) ;


<s> static Target The<ISA_LIT>32Target ; return The<ISA_LIT>32Target ;


<s> DiagnosticPredicate isSVEPreferredLogicalImm ( ) const { if ( isLogicalImm < T > ( ) && ! isSVECpyImm < T > ( ) ) return DiagnosticPredicateTy :: Match ;

return DiagnosticPredicateTy :: NoMatch ;


<s> static tree gcn_reduction_update ( location_t loc , gimple_stmt_iterator * gsi , tree ptr , tree var , tree_code op ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;

return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {


<s> bool <ISA_LIT>PassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return IsCPSRDead ( Instr ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; }


<s> AccessKind AccessToCheck = AK_Write ; if ( sForm ( MI ) != MI . getOpcode ( ) ) AccessToCheck = AK_All ; return ! areCFlagsAccessedBetweenInstrs ( & MI , & CmpInstr , & TRI , AccessToCheck ) ;


<s> auto Fn = MI . getParent ( ) -> getParent ( ) -> getFunction ( ) ;

auto Attr = Fn -> getFnAttribute ( <STR_LIT> ) ;


<s> int check_use_sfunc_addr ( rtx insn , rtx reg ) { while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( GET_CODE ( insn ) == CODE_LABEL || GET_CODE ( insn ) == JUMP_INSN ) break ; if ( ! INSN_P ( insn ) ) continue ; if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) insn = XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ;

if ( GET_CODE ( PATTERN ( insn ) ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) continue ;


<s> if ( FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( FixupKind == MCFixupKind ( <STR_LIT> ) ) ImmOffset -= <NUM_LIT> ; if ( ImmOffset ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( ImmOffset , Ctx ) , Ctx ) ; Fixups . push_back ( MCFixup :: Create ( CurByte , Expr , FixupKind ) ) ; EmitConstant ( <NUM_LIT> , Size , CurByte , OS ) ;


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ;


<s> static int sh_mode_entry ( int entity ATTRIBUTE_UNUSED ) { return NORMAL_MODE ( entity ) ;


<s> static SDValue NormalizeBuildVector ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT EltTy = VT . getVectorElementType ( ) ; if ( EltTy . isFloatingPoint ( ) || EltTy . getSizeInBits ( ) > <NUM_LIT> ) return Op ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( SDValue Lane : Op -> ops ( ) ) { if ( auto * CstLane = dyn_cast < ConstantSDNode > ( Lane ) ) { APInt LowBits ( EltTy . getSizeInBits ( ) , CstLane -> getZExtValue ( ) ) ; Lane = DAG . getConstant ( LowBits . getZExtValue ( ) , dl , <STR_LIT> ) ; } Ops . push_back ( Lane ) ; } return DAG . getBuildVector ( VT , dl , Ops ) ;


<s> } else if ( TREE_NAME_EQ ( name , ATTR_INTR ) ) { if ( TREE_CODE ( TREE_TYPE ( * node ) ) == FUNCTION_TYPE && ! VOID_TYPE_P ( TREE_TYPE ( TREE_TYPE ( * node ) ) ) ) message = <STR_LIT> ; else { TREE_USED ( * node ) = <NUM_LIT> ; DECL_PRESERVE_P ( * node ) = <NUM_LIT> ; } if ( is_critical_func ( * node ) ) { warning ( OPT_Wattributes , <STR_LIT> ) ; DECL_ATTRIBUTES ( * node ) = remove_attribute ( ATTR_CRIT , DECL_ATTRIBUTES ( * node ) ) ; } } else if ( TREE_NAME_EQ ( name , ATTR_REENT ) ) { if ( is_naked_func ( * node ) ) message = <STR_LIT> ; else if ( is_critical_func ( * node ) ) message = <STR_LIT> ; } else if ( TREE_NAME_EQ ( name , ATTR_CRIT ) ) {


<s> case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> :

case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , Op . getDebugLoc ( ) ) ;


<s> return C_RegisterClass ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : return C_Immediate ; case 'C' : if ( Constraint . size ( ) == <NUM_LIT> ) switch ( Constraint [ <NUM_LIT> ] ) { case '0' : case 'i' : case 'j' : return C_Immediate ; default : break ; } break ; default : break ;


<s> if ( GET_CODE ( imm ) == CONST_INT ) return true ; gcc_assert ( CONST_WIDE_INT_NUNITS ( imm ) == <NUM_LIT> ) ;

rtx lo = GEN_INT ( CONST_WIDE_INT_ELT ( imm , <NUM_LIT> ) ) ;


<s> } emit_insn ( gen_rtx_SET ( reg , mem ) ) ; } emit_use ( reg ) ; } else { if ( SPR_P ( REGNO ( reg ) ) ) { rtx temp = gen_rtx_REG ( mode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( temp , reg ) ) ; frv_frame_insn ( gen_rtx_SET ( mem , temp ) , frv_dwarf_store ( reg , stack_offset ) ) ; } else if ( mode == DImode ) { rtx reg1 = gen_rtx_REG ( SImode , REGNO ( reg ) ) ; rtx reg2 = gen_rtx_REG ( SImode , REGNO ( reg ) + <NUM_LIT> ) ; rtx set1 = frv_dwarf_store ( reg1 , stack_offset ) ; rtx set2 = frv_dwarf_store ( reg2 , stack_offset + <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( mem , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( XEXP ( mem , <NUM_LIT> ) , <NUM_LIT> ) ) == REG ) { rtx temp = gen_rtx_REG ( SImode , TEMP_REGNO ) ; emit_move_insn ( temp , gen_rtx_PLUS ( SImode , XEXP ( XEXP ( mem , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( XEXP ( mem , <NUM_LIT> ) , <NUM_LIT> ) ) ) ;


<s> bool <ISA_LIT>AsmParser :: expandLoadImm ( MCInst & Inst , bool Is32BitImm , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI ) { const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ImmOp . isImm ( ) && <STR_LIT> ) ; const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , false , IDLoc , Out , STI ) ) return true ;


<s>
const
MCOperand
&
MO2
=
MI
->
getOperand
(
OpNum
+
<NUM_LIT>
)
;
const
MCOperand
&
MO3
=
MI
->
getOperand
(
OpNum
+
<NUM_LIT>
)
;
printRegName
(
O
,
MO1
.
getReg
(
)
)
;
<STR_LIT>
ShOpc
=
<STR_LIT>
(
MO3
.
getImm
(
)
)
;
O
<<
<STR_LIT>
<<
<STR_LIT>
(
ShOpc
)
;
if
(
ShOpc
==
<STR_LIT>
)
return
;
O
<<
' '
;


<s> return ( __m64 ) __builtin_ia32_pmulhuw ( ( __v4hi ) __A , ( __v4hi ) __B ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue r1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , RHS ) ; const APFloat K0Val ( BitsToFloat ( <NUM_LIT> ) ) ; const SDValue K0 = DAG . getConstantFP ( K0Val , <STR_LIT> ) ; const APFloat K1Val ( BitsToFloat ( <NUM_LIT> ) ) ; const SDValue K1 = DAG . getConstantFP ( K1Val , <STR_LIT> ) ; const SDValue One = DAG . getTargetConstantFP ( <NUM_LIT> , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) ;

SDValue r2 = DAG . getSetCC ( SL , SetCCVT , r1 , K0 , <STR_LIT> ) ;


<s> bool Is32 = ( VT == <STR_LIT> ) ; SDLoc SL ( N ) ; MachineSDNode * CmpSwap = nullptr ; if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SelectCode ( N ) ; return ; } MachineMemOperand * MMO = Mem -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( CmpSwap , { MMO } ) ; unsigned SubReg = Is32 ? <STR_LIT> : <STR_LIT> ;

SDValue Extract = CurDAG -> getTargetExtractSubreg ( SubReg , SL , VT , SDValue ( CmpSwap , <NUM_LIT> ) ) ;


<s> result = arm_rtx_costs_internal ( x , ( enum rtx_code ) code , ( enum rtx_code ) outer_code , current_tune -> insn_extra_cost , total , speed ) ;


<s> static SDValue LowerVectorCTLZ_AVX512CDI ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems > <NUM_LIT> || ( NumElems == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) ) return LowerVectorIntUnary ( Op , DAG ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ;

assert ( ( NewVT . is256BitVector ( ) || NewVT . is512BitVector ( ) ) && <STR_LIT> ) ;


<s> unsigned RegNo = MO . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( RegNo ) ) return <ISA_LIT>InstPrinter :: getRegisterName ( RegNo ) ; return utostr ( TargetRegisterInfo :: virtReg2Index ( RegNo ) + NumArgs ) ;


<s> bool isAddr32 ( ) const { return isAddrN < <NUM_LIT> > ( ) ;


<s> if ( ! Callee || Callee -> isDeclaration ( ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; if ( CS . isNoInline ( ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; TargetTransformInfo & TTI = TTIWP -> getTTI ( * Callee ) ; if ( ! TTI . areInlineCompatible ( Caller , Callee ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; if ( CS . hasFnAttr ( Attribute :: AlwaysInline ) ) { auto IsViable = isInlineViable ( * Callee ) ; if ( IsViable ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ; return llvm :: InlineCost :: getNever ( IsViable . message ) ;


<s> void <ISA_LIT>SchedStrategy :: releaseTopNode ( SUnit * SU ) {

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; SU -> dump ( DAG ) ; ) ;


<s> if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ;

return ( Cnt >= <NUM_LIT> && Cnt <= ElementBits ) ;


<s> -- StackTop ; pushReg ( getFPReg ( MI . getOperand ( <NUM_LIT> ) ) ) ; } else { duplicateToTop ( Reg , getFPReg ( MI . getOperand ( <NUM_LIT> ) ) , I ) ; } MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( getConcreteOpcode ( MI . getOpcode ( ) ) ) ) ; MI . dropDebugNumber ( ) ;


<s> return pru_regno_ok_for_base_p ( regno , strict_p ) ;


<s> comp_reg = cmp_op0 ; condition = gen_rtx_fmt_ee ( signed_condition ( code ) , SImode , comp_reg , const0_rtx ) ; emit_jump_insn ( gen_condjump ( condition , label1 ) ) ; } else if ( code == EQ || code == NE ) { emit_insn ( gen_xorsi3 ( comp_reg , cmp_op0 , cmp_op1 ) ) ; condition = gen_rtx_fmt_ee ( signed_condition ( code ) , SImode , comp_reg , const0_rtx ) ;


<s> GepNode ( ) : Flags ( <NUM_LIT> ) , Parent ( nullptr ) , Idx ( nullptr ) , PTy ( nullptr ) {