<s> SmallVector < unsigned , <NUM_LIT> > toDel ; if ( regJustKilledBefore ( LIs , r , MI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( r , TRI ) << <STR_LIT> ; MI . print ( dbgs ( ) ) ; ) ; toDel . push_back ( r ) ; } while ( ! toDel . empty ( ) ) { Chains . remove ( toDel . back ( ) ) ; toDel . pop_back ( ) ; } } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( addIntraChainConstraint ( G , Rd , Ra ) ) addInterChainConstraint ( G , Rd , Ra ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned Rd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; addInterChainConstraint ( G , Rd , Rd ) ; break ; } default : break ; } } }


<s> bool IsPCRel = ( MO . getTargetFlags ( ) & ~ access ) == <STR_LIT> ; RefKind = IsPCRel ? MCSymbolRefExpr :: VK_<ISA_LIT>_TLS_PCREL : MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PCREL ; else if ( MO . getTargetFlags ( ) == ( <STR_LIT> | <STR_LIT> ) ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PCREL ; else if ( MO . getTargetFlags ( ) == ( <STR_LIT> | <STR_LIT> ) ) RefKind = MCSymbolRefExpr :: VK_TPREL ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSGD_PCREL ; else if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TPREL_PCREL ; const MachineInstr * MI = MO . getParent ( ) ; const MachineFunction * MF = MI -> getMF ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; unsigned MIOpcode = MI -> getOpcode ( ) ; assert ( ( Subtarget -> isUsingPCRelativeCalls ( ) || MIOpcode != <STR_LIT> ) && <STR_LIT> ) ; if ( Subtarget -> isUsingPCRelativeCalls ( ) ) { if ( MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> || MIOpcode == <STR_LIT> ) { RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_NOTOC ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_OPT ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ;

Expr = MCBinaryExpr :: createSub ( Expr , PB , Ctx ) ;


if ( width_source == SVE_SCALABLE ) return default_estimated_poly_value ( val ) ;


<s> static DecodeStatus DecodeBlezGroupBranchMMR6 ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> ; bool HasRs = false ; if ( Rt == <NUM_LIT> ) return MCDisassembler :: Fail ; else if ( Rs == <NUM_LIT> ) MI . setOpcode ( <STR_LIT> ) ; else if ( Rs == Rt ) MI . setOpcode ( <STR_LIT> ) ; else { HasRs = true ; MI . setOpcode ( <STR_LIT> ) ; } if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> FunctionPass * llvm :: createAMDGPUCFGStructurizerPass ( TargetMachine & tm ) {


<s> Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain ;


<s> return new DigitalPassConfig ( this , PM ) ;


<s> CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getBytesToPopOnReturn ( ) , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) {


<s> case MCSymbolRefExpr :: VK_GOT : assert ( Type == RT32_32 ) ; return IsPCRel ? ELF :: R_386_GOTPC : ELF :: R_386_GOT32 ; case MCSymbolRefExpr :: VK_GOTOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_GOTOFF ; case MCSymbolRefExpr :: VK_TPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LE_32 ; case MCSymbolRefExpr :: VK_DTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LDO_32 ; case MCSymbolRefExpr :: VK_TLSGD : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GD ; case MCSymbolRefExpr :: VK_GOTTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_IE_32 ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: cpu0 , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> MF -> insert ( MBBIter , mallocMBB ) ; MF -> insert ( MBBIter , continueMBB ) ; continueMBB -> splice ( continueMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; continueMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BuildMI ( BB , DL , TII -> get ( TargetOpcode :: COPY ) , tmpSPVReg ) . addReg ( physSPReg ) ; BuildMI ( BB , DL , TII -> get ( IsLP64 ? <STR_LIT> : <STR_LIT> ) , SPLimitVReg ) . addReg ( tmpSPVReg ) . addReg ( sizeVReg ) ; BuildMI ( BB , DL , TII -> get ( IsLP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( TlsOffset ) . addReg ( TlsReg ) . addReg ( SPLimitVReg ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( mallocMBB ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , physSPReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( TargetOpcode :: COPY ) , bumpSPPtrVReg ) . addReg ( SPLimitVReg ) ; BuildMI ( bumpMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( continueMBB ) ; const uint32_t * RegMask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( * MF , CallingConv :: C ) ; if ( IsLP64 ) { BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( sizeVReg ) ; BuildMI ( mallocMBB , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ;


<s> R600VectorRegMerger ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TII ( <NUM_LIT> ) {


<s> <ISA_LIT>_32ExecPLT0 :: <ISA_LIT>_32ExecPLT0 ( SectionData & pParent ) : PLT :: Entry < sizeof ( x86_32_exec_plt0 ) > ( pParent ) {


<s> bool Use32BitInsts = isUInt < <NUM_LIT> > ( Mask ) ; unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = ( Mask >> <NUM_LIT> ) & UINT16_MAX ; if ( Use32BitInsts ) { assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; if ( InstCnt ) * InstCnt += ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) ; SDValue ANDIVal , ANDISVal ; if ( ANDIMask != <NUM_LIT> ) ANDIVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( Res , dl ) , getI32Imm ( ANDIMask , dl ) ) , <NUM_LIT> ) ; if ( ANDISMask != <NUM_LIT> ) ANDISVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( Res , dl ) , getI32Imm ( ANDISMask , dl ) ) , <NUM_LIT> ) ; if ( ! ANDIVal ) Res = ANDISVal ; else if ( ! ANDISVal ) Res = ANDIVal ; else Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( ANDIVal , dl ) , ANDISVal ) , <NUM_LIT> ) ; } else { if ( InstCnt ) * InstCnt += selectI64ImmInstrCount ( Mask ) + <NUM_LIT> ; SDValue MaskVal = SDValue ( selectI64Imm ( CurDAG , dl , Mask ) , <NUM_LIT> ) ;

Res = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , ExtendToInt64 ( Res , dl ) , MaskVal ) , <NUM_LIT> ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) , Subtarget ( & tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , OptForSize ( false ) {


<s> Op -> PostIdxReg . isAdd = isAdd ; Op -> PostIdxReg . ShiftTy = ShiftTy ; Op -> PostIdxReg . ShiftImm = ShiftImm ;


return ( __m64 ) __builtin_ia32_psllq ( ( long long ) __m , ( long long ) __count ) ;


<s> assert ( Resources -> canReserveResources ( * NewMI ) ) ; Resources -> reserveResources ( * NewMI ) ; MF -> DeleteMachineInstr ( NewMI ) ; } else Resources -> reserveResources ( * MI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; if ( TII -> mayBeCurLoad ( * MI ) ) for ( auto & S : SU -> Succs ) if ( S . isAssignedRegDep ( ) && S . getLatency ( ) == <NUM_LIT> && S . getSUnit ( ) -> NumPredsLeft == <NUM_LIT> ) { UsesDotCur = S . getSUnit ( ) ; DotCurPNum = PacketNum ; break ; }


<s> void <ISA_LIT>ConstantIslands :: scanFunctionJumpTables ( ) { for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & I : MBB ) if ( I . isBranch ( ) && ( I . getOpcode ( ) == <STR_LIT> || I . getOpcode ( ) == <STR_LIT> ) ) T2JumpTables . push_back ( & I ) ; }


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;

addPass ( create<ISA_LIT>FrameAnalyzerPass ( ) ) ;


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MI . getOpcode ( ) == <STR_LIT> ? MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ;

Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ;


<s> for ( MachineBasicBlock :: reverse_iterator It = MBB -> rbegin ( ) , E = MBB -> rend ( ) ; It != E ; ++ It ) { MachineInstr * MI = & * It ; if ( MI ) { if ( isCondBranch ( MI ) || isUncondBranch ( MI ) ) return MI ; else if ( ! TII -> isMov ( MI -> getOpcode ( ) ) ) break ;


<s> void <ISA_LIT>InstPrinter :: printNoNull ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O << <STR_LIT> ;


<s> UsedRegs . insert ( Reg ) ; if ( IsLoad ) { for ( const MachineOperand & MO : MI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || MO . isDead ( ) ) continue ; assert ( MO . isImplicit ( ) ) ; unsigned DefReg = MO . getReg ( ) ; if ( std :: find ( ImpDefs . begin ( ) , ImpDefs . end ( ) , DefReg ) != ImpDefs . end ( ) ) continue ; if ( MI -> readsRegister ( DefReg ) ) continue ; ImpDefs . push_back ( DefReg ) ; } } } typedef MachineBasicBlock :: iterator iterator ; MachineInstr * LatestMI = Cand . Instrs [ Cand . LatestMIIdx ] ; iterator InsertBefore = std :: next ( iterator ( LatestMI ) ) ; MachineBasicBlock & MBB = * LatestMI -> getParent ( ) ; unsigned Offset = getMemoryOpOffset ( * First ) ; unsigned Base = getLoadStoreBaseOp ( * First ) . getReg ( ) ; bool BaseKill = LatestMI -> killsRegister ( Base ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * First , PredReg ) ; DebugLoc DL = First -> getDebugLoc ( ) ; MachineInstr * Merged = nullptr ; if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged ) return nullptr ;

iterator EarliestI ( Cand . Instrs [ Cand . EarliestMIIdx ] ) ;


<s> bool SelectAddrModeIndexed16 ( SDValue N , SDValue & Base , SDValue & OffImm ) {

return SelectAddrModeIndexed ( N , <NUM_LIT> , Base , OffImm ) ;


<s> else if ( MBB == Latch ) IVReg = IV_Phi -> getOperand ( i ) . getReg ( ) ; } if ( ! InitialValue ) return nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * TB = nullptr , * FB = nullptr ; bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; if ( NotAnalyzed ) return nullptr ; MachineBasicBlock * Header = L -> getHeader ( ) ; assert ( TB && <STR_LIT> ) ; if ( ExitingBlock != Latch && ( TB == Latch || FB == Latch ) ) { MachineBasicBlock * LTB = nullptr , * LFB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > LCond ; bool NotAnalyzed = TII -> analyzeBranch ( * Latch , LTB , LFB , LCond , false ) ; if ( NotAnalyzed ) return nullptr ; if ( TB == Latch ) TB = ( LTB == Header ) ? LTB : LFB ; else FB = ( LTB == Header ) ? LTB : LFB ; } assert ( ( ! FB || TB == Header || FB == Header ) && <STR_LIT> ) ; if ( ! TB || ( FB && TB != Header && FB != Header ) ) return nullptr ; bool Negated = TII -> predOpcodeHasNot ( Cond ) ^ ( TB != Header ) ; unsigned PredReg , PredPos , PredRegFlags ; if ( ! TII -> getPredReg ( Cond , PredReg , PredPos , PredRegFlags ) ) return nullptr ; MachineInstr * CondI = MRI -> getVRegDef ( PredReg ) ; unsigned CondOpc = CondI -> getOpcode ( ) ; unsigned CmpReg1 = <NUM_LIT> , CmpReg2 = <NUM_LIT> ; int Mask = <NUM_LIT> , ImmValue = <NUM_LIT> ;

bool AnalyzedCmp = TII -> analyzeCompare ( * CondI , CmpReg1 , CmpReg2 , Mask , ImmValue ) ;


<s> VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( RegSizeInBytes * ( ArgRegs . size ( ) - Idx ) ) ; } int FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSizeInBytes ) { unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSizeInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;

cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ;


<s> EVT VT = <STR_LIT> ; EVT WideVT = <STR_LIT> ; SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != VT ) return Op ; SDValue ShiftAmt = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue HiLHS = DAG . getNode ( <STR_LIT> , dl , VT , LHS , ShiftAmt ) ; SDValue HiRHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS , ShiftAmt ) ;

SDValue Args [ ] = { HiLHS , LHS , HiRHS , RHS } ;


<s> <ISA_LIT>MemOp ( Kind Op ) : Op ( Op ) {


<s> void <ISA_LIT>InstPrinter :: printS16X4ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {

if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( short ) ( MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getNumAddressableSGPRs ( const <ISA_LIT>Subtarget & ST ) const { if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> uint64_t Mask = <STR_LIT> ( DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) , Is32Bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! isPowerOf2_64 ( Mask ) ) return false ; MachineOperand & MO = DefMI -> getOperand ( <NUM_LIT> ) ; unsigned NewReg = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( NewReg ) ) return false ; assert ( ! MRI -> def_empty ( NewReg ) && <STR_LIT> ) ; MachineBasicBlock & RefToMBB = * MBB ; MachineBasicBlock * TBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Imm = Log2_64 ( Mask ) ; unsigned Opc = ( Imm < <NUM_LIT> ) ? ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) : ( IsNegativeBranch ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * NewMI = BuildMI ( RefToMBB , MI , DL , get ( Opc ) ) . addReg ( NewReg ) . addImm ( Imm ) . addMBB ( TBB ) ; MO . setIsKill ( false ) ; if ( ! Is32Bit && Imm < <NUM_LIT> ) NewMI -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { if ( ! ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ! ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ; if ( DefMI -> findRegisterDefOperandIdx ( <STR_LIT> , true ) != - <NUM_LIT> ) return false ; <STR_LIT> CC = ( <STR_LIT> ) DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( areCFlagsAccessedBetweenInstrs ( DefMI , MI , & getRegisterInfo ( ) , AK_Write ) ) return false ; MachineBasicBlock & RefToMBB = * MBB ;

MachineBasicBlock * TBB = MI . getOperand ( TargetBBInMI ) . getMBB ( ) ;


<s> V0 = Elt . getOperand ( <NUM_LIT> ) ; V0NumElts = V0 . getValueType ( ) . getVectorNumElements ( ) ; } if ( Elt . getOperand ( <NUM_LIT> ) == V0 ) { Mask [ i ] = ( cast < ConstantSDNode > ( Elt -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; continue ; } else if ( ! V1 . getNode ( ) ) { V1 = Elt . getOperand ( <NUM_LIT> ) ; } if ( Elt . getOperand ( <NUM_LIT> ) == V1 ) { unsigned Lane = cast < ConstantSDNode > ( Elt -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Mask [ i ] = ( Lane + V0NumElts ) ; continue ; } else { return false ; } } return true ;


<s> return __builtin_c6x_clrr ( src1 , src2 ) ;


<s> const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;

return new <ISA_LIT>AsmBackend ( STI , OSABI , TT . isArch64Bit ( ) ) ;


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O << <STR_LIT> ;


<s> unsigned HiSR = subreg_hireg ; if ( S == <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( A2_or ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) ; BuildMI ( B , MI , DL , TII -> get ( A2_or ) , HiR ) . addReg ( Op1 . getReg ( ) , RS1 , HiSR ) . addReg ( Op2 . getReg ( ) , RS2 , HiSR ) ; } else if ( S < <NUM_LIT> ) { BuildMI ( B , MI , DL , TII -> get ( S2_asl_i_r_or ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) . addImm ( S ) ; unsigned TmpR1 = MRI -> createVirtualRegister ( IntRC ) ; BuildMI ( B , MI , DL , TII -> get ( S2_extractu ) , TmpR1 ) . addReg ( Op2 . getReg ( ) , RS2 & ~ RegState :: Kill , LoSR ) . addImm ( S ) . addImm ( <NUM_LIT> - S ) ; unsigned TmpR2 = MRI -> createVirtualRegister ( IntRC ) ; BuildMI ( B , MI , DL , TII -> get ( A2_or ) , TmpR2 ) . addReg ( Op1 . getReg ( ) , RS1 , HiSR ) . addReg ( TmpR1 ) ; BuildMI ( B , MI , DL , TII -> get ( S2_asl_i_r_or ) , HiR ) . addReg ( TmpR2 ) . addReg ( Op2 . getReg ( ) , RS2 , HiSR ) . addImm ( S ) ; } else if ( S == <NUM_LIT> ) {

BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: COPY ) , LoR ) . addReg ( Op1 . getReg ( ) , RS1 & ~ RegState :: Kill , LoSR ) ;


<s> UsesELFSectionDirectiveForBSS = true ; AllowAtInName = true ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ;

ProtectedVisibilityAttr = MCSA_Invalid ;


<s> if ( Op . getValueType ( ) == <STR_LIT> && Vec . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) < <NUM_LIT> ) { SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Lane ) ; } return Op ;


<s> MachineInstr & NvjMI = * ++ MII ; ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI ) Good = tryAllocateResourcesForConstExt ( true ) ; bool ExtNvjMI = HII -> isExtended ( NvjMI ) || HII -> isConstExtended ( NvjMI ) ; if ( Good ) { if ( ResourceTracker -> canReserveResources ( NvjMI ) ) ResourceTracker -> reserveResources ( NvjMI ) ; else Good = false ; } if ( Good && ExtNvjMI ) Good = tryAllocateResourcesForConstExt ( true ) ; if ( ! Good ) { endPacket ( MBB , MI ) ; assert ( ResourceTracker -> canReserveResources ( MI ) ) ; ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI ) { assert ( canReserveResourcesForConstExt ( ) ) ; tryAllocateResourcesForConstExt ( true ) ; } assert ( ResourceTracker -> canReserveResources ( NvjMI ) ) ; ResourceTracker -> reserveResources ( NvjMI ) ; if ( ExtNvjMI ) { assert ( canReserveResourcesForConstExt ( ) ) ; reserveResourcesForConstExt ( ) ; } } CurrentPacketMIs . push_back ( & MI ) ; CurrentPacketMIs . push_back ( & NvjMI ) ; return MII ; } ResourceTracker -> reserveResources ( MI ) ; if ( ExtMI && ! tryAllocateResourcesForConstExt ( true ) ) { endPacket ( MBB , MI ) ; if ( PromotedToDotNew ) demoteToDotOld ( MI ) ; if ( GlueAllocframeStore ) { useCalleesSP ( MI ) ; GlueAllocframeStore = false ; } ResourceTracker -> reserveResources ( MI ) ; reserveResourcesForConstExt ( ) ; } CurrentPacketMIs . push_back ( & MI ) ; return MII ;


<s> Op . addRegOrImmWithFPInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isDPPCtrl ( ) ) { Op . addImmOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { llvm_unreachable ( <STR_LIT> ) ; } } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDppRowMask , <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDppBankMask , <NUM_LIT> ) ;

addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDppBoundCtrl ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: shrinkAndImmediate ( SDNode * And ) { MVT VT = And -> getSimpleValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; auto * And1C = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! And1C ) return false ; APInt MaskVal = And1C -> getAPIntValue ( ) ; unsigned MaskLZ = MaskVal . countLeadingZeros ( ) ; if ( ! MaskLZ ) return false ; SDValue And0 = And -> getOperand ( <NUM_LIT> ) ; APInt HighZeros = APInt :: getHighBitsSet ( VT . getSizeInBits ( ) , MaskLZ ) ; APInt NegMaskVal = MaskVal | HighZeros ; unsigned MinWidth = NegMaskVal . getMinSignedBits ( ) ;

if ( MinWidth > <NUM_LIT> || ( MinWidth > <NUM_LIT> && MaskVal . getMinSignedBits ( ) <= <NUM_LIT> ) ) return false ;


<s> LLVM_DUMP_METHOD void <ISA_LIT>ConstantIslands :: dumpBBs ( ) { for ( unsigned J = <NUM_LIT> , E = BBInfo . size ( ) ; J != E ; ++ J ) { const BasicBlockInfo & BBI = BBInfo [ J ] ;

dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << format ( <STR_LIT> , BBInfo [ J ] . Size ) ;


<s> auto & Context = getContext ( ) ; auto * DescBegin = Context . createTempSymbol ( ) ; auto * DescEnd = Context . createTempSymbol ( ) ; auto * DescSZ = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( DescEnd , Context ) , MCSymbolRefExpr :: create ( DescBegin , Context ) , Context ) ; Emit<ISA_LIT>Note ( DescSZ , ElfNote :: NT_<ISA_LIT>_HSA_CODE_OBJECT_METADATA , [ & ] ( MCELFStreamer & OS ) { OS . EmitLabel ( DescBegin ) ; OS . EmitBytes ( VerifiedYamlString . get ( ) ) ; OS . EmitLabel ( DescEnd ) ;


<s> return __builtin_mve_vhsubq_m_n_sv4si ( __arm_vuninitializedq_s32 ( ) , __a , __b , __p ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; Type * t = DAG . getMachineFunction ( ) . getFunction ( ) -> getReturnType ( ) ; t -> dump ( ) ; outs ( ) << <STR_LIT> << t -> isPointerTy ( ) << <STR_LIT> ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( auto & Loc : RVLocs ) { if ( t -> isPointerTy ( ) ) Loc . convertToReg ( <STR_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( <NUM_LIT> ) ; InGlue = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain ;


<s> if ( next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ;

MachineBasicBlock * NextBB = next ( MBBI ) ;


<s> } if ( isSymbol ) { if ( SM . getSym ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getBaseReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getIndexReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size ) ; } StringRef ErrMsg ; if ( CheckBaseRegAndIndexReg ( BaseReg , IndexReg , ErrMsg ) ) { Error ( StartInBrac , ErrMsg ) ; return nullptr ; }

return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , BaseReg , IndexReg , Scale , Start , End , Size ) ;


<s> HOST_WIDE_INT offset = INTVAL ( addend ) ; return ! ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; } if ( ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && CONSTANT_P ( x ) ) { return arc_legitimate_constant_p ( mode , x ) ; } if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == POST_INC ) && RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ;

if ( ( GET_CODE ( x ) == PRE_MODIFY || GET_CODE ( x ) == POST_MODIFY ) && GET_CODE ( XEXP ( ( x ) , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( ( x ) , <NUM_LIT> ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && legitimate_offset_address_p ( QImode , XEXP ( x , <NUM_LIT> ) , TARGET_AUTO_MODIFY_REG , strict ) ) return true ;


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue ( ) ) ) ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override {


<s> int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) { return DAG . getCommutedVectorShuffle ( * SVOp ) ; } else if ( LowV2Elements == LowV1Elements ) { int SumV1Indices = <NUM_LIT> , SumV2Indices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = SVOp -> getMask ( ) . size ( ) ; i < Size ; ++ i ) if ( SVOp -> getMask ( ) [ i ] >= NumElements ) SumV2Indices += i ; else if ( SVOp -> getMask ( ) [ i ] >= <NUM_LIT> ) SumV1Indices += i ; if ( SumV2Indices < SumV1Indices ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; }


<s> auto curfunc = MF . getFunction ( ) . getName ( ) ; if ( isConverting ( MF ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << curfunc << <STR_LIT> ) ; analyzeFunction ( MF ) ; } return false ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) {


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler :: Success ;


<s> if ( TT . getArch ( ) == Triple :: x86_64 ) return llvm :: make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ; return llvm :: make_unique < TargetLoweringObjectFileMachO > ( ) ; } if ( TT . isOSFreeBSD ( ) ) return llvm :: make_unique < <ISA_LIT>FreeBSDTargetObjectFile > ( ) ; if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) ) return llvm :: make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ;

if ( TT . isOSFuchsia ( ) ) return llvm :: make_unique < <ISA_LIT>FuchsiaTargetObjectFile > ( ) ;


<s> assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ;

SelectVOP3BMods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> void EmitARM64WinCFISaveRegP ( unsigned Reg , int Offset ) override {

OS << <STR_LIT> << Reg << <STR_LIT> << Offset << <STR_LIT> ;


<s> ST = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) ;

GR = ST -> get<ISA_LIT>GlobalRegistry ( ) ;


<s> return Ty . isSimple ( ) && Subtarget . isHVXVectorType ( Ty . getSimpleVT ( ) , true ) ; } ; auto IsHvxOp = [ this ] ( SDValue Op ) { return Subtarget . isHVXVectorType ( ty ( Op ) , true ) ; } ;

return llvm :: any_of ( N -> values ( ) , IsHvxTy ) || llvm :: any_of ( N -> ops ( ) , IsHvxOp ) ;


<s> bool <ISA_LIT>FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * RegInfo , std :: vector < CalleeSavedInfo > & CSI , unsigned & MinCSFrameIndex , unsigned & MaxCSFrameIndex ) const { if ( CSI . empty ( ) ) return true ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( auto & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ; int FrameIdx ; unsigned Size = RegInfo -> getSpillSize ( * RC ) ; Align Alignment ( RegInfo -> getSpillAlignment ( * RC ) ) ; FrameIdx = MFI . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ; if ( hasFP ( MF ) && AFI -> hasSwiftAsyncContext ( ) && Reg == <STR_LIT> ) { FrameIdx = MFI . CreateStackObject ( <NUM_LIT> , Alignment , true ) ; AFI -> setSwiftAsyncContextFrameIdx ( FrameIdx ) ; if ( ( unsigned ) FrameIdx < MinCSFrameIndex ) MinCSFrameIndex = FrameIdx ; if ( ( unsigned ) FrameIdx > MaxCSFrameIndex ) MaxCSFrameIndex = FrameIdx ;


<s> if ( ( TargetTriple . isOSFreeBSD ( ) && TargetTriple . getOSMajorVersion ( ) >= <NUM_LIT> ) || TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ;


<s> Value * <ISA_LIT>IREmitter :: visitLCMPXCHG16_DAG ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> return ; } switch ( mode ) { case SFmode : case DFmode : case XFmode : case QImode : case HImode : case SImode : simple : tmp = ix86_expand_compare ( code , op0 , op1 ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; return ; case DImode : if ( TARGET_64BIT ) goto simple ; if ( ! optimize_insn_for_size_p ( ) && TARGET_STV && ( code == EQ || code == NE ) ) { op0 = force_reg ( mode , gen_rtx_XOR ( mode , op0 , op1 ) ) ; op1 = const0_rtx ; } case TImode : { rtx lo [ <NUM_LIT> ] , hi [ <NUM_LIT> ] ; rtx_code_label * label2 ; enum rtx_code code1 , code2 , code3 ; machine_mode submode ; if ( CONSTANT_P ( op0 ) && ! CONSTANT_P ( op1 ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } split_double_mode ( mode , & op0 , <NUM_LIT> , lo + <NUM_LIT> , hi + <NUM_LIT> ) ; split_double_mode ( mode , & op1 , <NUM_LIT> , lo + <NUM_LIT> , hi + <NUM_LIT> ) ; submode = mode == DImode ? SImode : DImode ; if ( ( code == EQ || code == NE ) && ( ! optimize_insn_for_size_p ( ) || hi [ <NUM_LIT> ] == const0_rtx || lo [ <NUM_LIT> ] == const0_rtx ) ) { rtx xor0 , xor1 ; xor1 = hi [ <NUM_LIT> ] ; if ( hi [ <NUM_LIT> ] != const0_rtx ) xor1 = expand_binop ( submode , xor_optab , xor1 , hi [ <NUM_LIT> ] , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; xor0 = lo [ <NUM_LIT> ] ; if ( lo [ <NUM_LIT> ] != const0_rtx ) xor0 = expand_binop ( submode , xor_optab , xor0 , lo [ <NUM_LIT> ] , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; tmp = expand_binop ( submode , ior_optab , xor1 , xor0 , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; ix86_expand_branch ( code , tmp , const0_rtx , label ) ; return ; } if ( CONST_INT_P ( hi [ <NUM_LIT> ] ) ) switch ( code ) {

case LT : case LTU : case GE : case GEU :


<s> case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> :


<s> if ( ! Subtarget . hasDSP ( ) ) return SDValue ( ) ; if ( ! BV || ! BV -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , EltSize , ! Subtarget . isLittle ( ) ) || ( SplatBitSize != EltSize ) || ( SplatValue . getZExtValue ( ) >= EltSize ) ) return SDValue ( ) ; SDLoc DL ( N ) ;

return DAG . getNode ( Opc , DL , Ty , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( SplatValue . getZExtValue ( ) , DL , <STR_LIT> ) ) ;


<s> if ( MBB != nullptr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBBI . getNumber ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ) ; } FallthroughMap [ & MBBI ] = MBB ;


<s> SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ahi = DAG . getNode ( <STR_LIT> , dl , VT , A , ShAmt ) ; SDValue Bhi = DAG . getNode ( <STR_LIT> , dl , VT , B , ShAmt ) ; EVT MulVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; A = DAG . getNode ( <STR_LIT> , dl , MulVT , A ) ; B = DAG . getNode ( <STR_LIT> , dl , MulVT , B ) ; Ahi = DAG . getNode ( <STR_LIT> , dl , MulVT , Ahi ) ; Bhi = DAG . getNode ( <STR_LIT> , dl , MulVT , Bhi ) ; SDValue AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , A , B ) ; SDValue AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , A , Bhi ) ; SDValue AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , Ahi , B ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , AloBhi , ShAmt ) ; AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , AhiBlo , ShAmt ) ;

SDValue Res = DAG . getNode ( <STR_LIT> , dl , VT , AloBlo , AloBhi ) ;


<s> bool isHiImm16 ( ) { if ( ! isImm ( ) ) return false ; if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Value ) ) { int64_t Value = ConstExpr -> getValue ( ) ; return Value != <NUM_LIT> && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Value ) ; } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ;

if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ;


<s> return II -> getArgOperand ( <NUM_LIT> ) ; case <STR_LIT> : return II -> getArgOperand ( <NUM_LIT> ) ; } } Type * ValTy = getPayload ( Val ) -> getType ( ) ;

if ( auto * VecTy = dyn_cast < VectorType > ( ValTy ) ) {


<s> uint64_t <ISA_LIT>InstrInfo :: getDefaultRsrcDataFormat ( ) const { if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { return ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; } uint64_t RsrcDataFormat = <STR_LIT> ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , RA , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , false ) , <ISA_LIT>_MC :: getDwarfRegFlavour ( TT , true ) , RA ) ; <ISA_LIT>_MC :: initLLVMToSEHAndCVRegMapping ( X ) ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; NumOpsAdded = <NUM_LIT> ;


<s> } else if ( getEMachine ( ) == ELF :: EM_386 ) { if ( IsPCRel ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_386_GOTPC ; break ; case FK_PCRel_1 : case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC8 ; break ; } break ; case FK_PCRel_2 : case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC16 ; break ; } break ; case <STR_LIT> : case FK_PCRel_4 : case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_PC32 ; break ; case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_386_PLT32 ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_386_GOTPC ; break ; case <STR_LIT> : case FK_PCRel_4 : case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_386_32 ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_386_GOT32 ; break ; case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_386_PLT32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_386_GOTOFF ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_386_TLS_GD ; break ; case MCSymbolRefExpr :: VK_TPOFF :


<s> GlobalBaseReg = <NUM_LIT> ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> if ( VT . is256BitVector ( ) || VT . is512BitVector ( ) ) { if ( VT . is256BitVector ( ) && IdxVal == <NUM_LIT> ) { if ( ( Subtarget . hasAVX ( ) && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) ) || ( Subtarget . hasAVX2 ( ) && EltVT == <STR_LIT> ) ) { SDValue N1Vec = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1Vec , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } unsigned NumEltsIn128 = <NUM_LIT> / EltSizeInBits ; assert ( isPowerOf2_32 ( NumEltsIn128 ) && <STR_LIT> ) ; if ( ! VT . is128BitVector ( ) && IdxVal >= NumEltsIn128 && ( ( Subtarget . hasAVX2 ( ) && EltSizeInBits != <NUM_LIT> ) || ( Subtarget . hasAVX ( ) && ( EltSizeInBits >= <NUM_LIT> ) && MayFoldLoad ( N1 ) ) ) ) { SDValue N1SplatVec = DAG . getSplatBuildVector ( VT , dl , N1 ) ; SmallVector < int , <NUM_LIT> > BlendMask ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) BlendMask . push_back ( i == IdxVal ? i + NumElts : i ) ; return DAG . getVectorShuffle ( VT , dl , N0 , N1SplatVec , BlendMask ) ; } SDValue V = extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned IdxIn128 = IdxVal & ( NumEltsIn128 - <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getIntPtrConstant ( IdxIn128 , dl ) ) ; return insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; if ( IdxVal == <NUM_LIT> && <STR_LIT> ( N0 . getNode ( ) ) ) { if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { N1 = DAG . getNode ( <STR_LIT> , dl , VT , N1 ) ; return getShuffleVectorZeroOrUndef ( N1 , <NUM_LIT> , true , Subtarget , DAG ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; MVT ShufVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , ShufVT , N1 ) ; N1 = getShuffleVectorZeroOrUndef ( N1 , <NUM_LIT> , true , Subtarget , DAG ) ; return DAG . getBitcast ( VT , N1 ) ;


<s> else if ( const_ok_for_mcore ( val ) ) return <NUM_LIT> ; else if ( TARGET_HARDLIT && mcore_const_ok_for_inline ( val ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , Cnt ) ) { SDValue RHS = DAG . getNode ( <STR_LIT> , SDLoc ( N -> getOperand ( <NUM_LIT> ) ) , VT , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , RHS ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , Cnt ) ) { SDValue RHS = DAG . getNode ( <STR_LIT> , SDLoc ( N -> getOperand ( <NUM_LIT> ) ) , VT , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; return DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , RHS ) ; }


<s> STI . getInstrInfo ( ) -> storeRegToStack ( MBB , MBBI , <STR_LIT> , false , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) , <NUM_LIT> ) ; unsigned InsPosition = <NUM_LIT> ; unsigned InsSize = <NUM_LIT> ; unsigned SrcReg = <STR_LIT> ; if ( IntKind == <STR_LIT> ) { SrcReg = <STR_LIT> ; InsPosition = <NUM_LIT> ; InsSize = <NUM_LIT> ; } else InsSize = StringSwitch < unsigned > ( IntKind ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ; assert ( InsSize != <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg ) . addImm ( InsPosition ) . addImm ( InsSize ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

if ( ! STI . useSoftFloat ( ) ) BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) operands [ <NUM_LIT> ] = force_reg ( Pmode , operands [ <NUM_LIT> ] ) ; else if ( TLS_SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = legitimize_tls_address ( operands [ <NUM_LIT> ] , temp ) ;

else if ( flag_pic ) operands [ <NUM_LIT> ] = legitimize_pic_address ( operands [ <NUM_LIT> ] , temp ) ;


<s> const MCExpr * getImm ( ) const { assert ( ( Kind == k_Immediate || Kind == k_LSAImm ) && <STR_LIT> ) ; return Imm . Val ;


<s> SDValue Op0 = N -> getOperand ( I ^ <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && ( RxSBG [ I ] . Mask & <NUM_LIT> ) == <NUM_LIT> ) if ( auto * Load = dyn_cast < LoadSDNode > ( Op0 . getNode ( ) ) ) if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return nullptr ; if ( Opcode == <STR_LIT> && detectOrAndInsertion ( Op0 , RxSBG [ I ] . Mask ) ) { Opcode = <STR_LIT> ; if ( Subtarget -> hasMiscellaneousExtensions ( ) ) Opcode = <STR_LIT> ; } SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { convertTo ( DL , <STR_LIT> , Op0 ) , convertTo ( DL , <STR_LIT> , RxSBG [ I ] . Input ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Start , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . End , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Rotate , DL , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ; return convertTo ( DL , VT , SDValue ( N , <NUM_LIT> ) ) . getNode ( ) ;


<s> Register RegA = A . getOperand ( i ) . getReg ( ) ; Register RegB = B -> getOperand ( i ) . getReg ( ) ; AllOpsMatch = MAI . getRegisterAlias ( A . getMF ( ) , RegA ) == MAI . getRegisterAlias ( B -> getMF ( ) , RegB ) ; } else { AllOpsMatch = A . getOperand ( i ) . isIdenticalTo ( B -> getOperand ( i ) ) ; } }


<s> showImproveSimpleJumpintoIf ( HeadMBB , TrueMBB , FalseMBB , LandBlk , <NUM_LIT> ) ; ) ; const TargetRegisterClass * I32RC = TRI -> getCFGStructurizerRegClass ( <STR_LIT> ) ; if ( ! MigrateTrue || ! MigrateFalse ) { return <NUM_LIT> ; } int NumNewBlk = <NUM_LIT> ; bool LandBlkHasOtherPred = ( LandBlk -> pred_size ( ) > <NUM_LIT> ) ; MachineBasicBlock :: iterator I = insertInstrBefore ( LandBlk , <STR_LIT> ) ; if ( LandBlkHasOtherPred ) { report_fatal_error ( <STR_LIT> ) ; unsigned CmpResReg = HeadMBB -> getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( I32RC ) ; report_fatal_error ( <STR_LIT> ) ; insertCondBranchBefore ( LandBlk , I , <STR_LIT> , CmpResReg , DebugLoc ( ) ) ; } unsigned InitReg = HeadMBB -> getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( I32RC ) ; insertCondBranchBefore ( LandBlk , I , <STR_LIT> , InitReg , DebugLoc ( ) ) ; if ( MigrateTrue ) { migrateInstruction ( TrueMBB , LandBlk , I ) ; report_fatal_error ( <STR_LIT> ) ; } insertInstrBefore ( I , <STR_LIT> ) ; if ( MigrateFalse ) { migrateInstruction ( FalseMBB , LandBlk , I ) ;


<s> switch ( Opcode ) { default : break ; case <STR_LIT> : return true ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT> : case <STR_LIT> :


<s> static bool isExtendedBUILD_VECTOR ( SDNode * N , SelectionDAG & DAG , bool isSigned ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> ) { SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( BVN -> getValueType ( <NUM_LIT> ) != <STR_LIT> || BVN -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned LoElt = DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned HiElt = <NUM_LIT> - LoElt ; ConstantSDNode * Lo0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt ) ) ; ConstantSDNode * Hi0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt ) ) ; ConstantSDNode * Lo1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt + <NUM_LIT> ) ) ; ConstantSDNode * Hi1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt + <NUM_LIT> ) ) ;

if ( ! Lo0 || ! Hi0 || ! Lo1 || ! Hi1 ) return false ;


<s> return op . isImm ( ) && op . getImm ( ) == <NUM_LIT> ;


<s> key . m_Addend = <NUM_LIT> ; m_GotTLSGdEntriesMap [ key ] = pEntry ; } else if ( pType == llvm :: ELF :: R_MIPS_TLS_GOTTPREL ) { GotEntryKey key ; key . m_GOTPage = m_CurrentGOTPart ; key . m_pInfo = pInfo ; key . m_Addend = <NUM_LIT> ; m_GotTLSGotEntriesMap [ key ] = pEntry ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal = Incr ; }

BuildMI ( BB , DL , TII -> get ( SC ) , Success ) . addReg ( StoreVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ;


<s> return PhysReg == <STR_LIT> || PhysReg == <STR_LIT> || PhysReg == <STR_LIT> || PhysReg == <STR_LIT> || PhysReg == <STR_LIT> ;


<s> return tilegx_emit_setcc_internal ( operands [ <NUM_LIT> ] , GET_CODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , cmp_mode ) ;


<s> void <ISA_LIT>FunctionInfo :: initializeBaseYamlFields ( const yaml :: <ISA_LIT>FunctionInfo & YamlMFI ) {

if ( YamlMFI . HasRedZone . hasValue ( ) ) HasRedZone = YamlMFI . HasRedZone ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ;


<s> arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_NOMPY_SET ) arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case ARC_TUNE_ARC700_4_2_XMAC : arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_NOMPY_SET ) arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case ARC_TUNE_ARC600 : if ( TARGET_MUL64_SET ) { arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } default : arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } if ( TARGET_NOMPY_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ! TARGET_DPFP && TARGET_DPFP_DISABLE_LRSR ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET && TARGET_DPFP_COMPACT_SET ) || ( TARGET_SPFP_FAST_SET && TARGET_SPFP_COMPACT_SET ) ) error ( <STR_LIT> ) ; if ( TARGET_SPFP_FAST_SET && TARGET_ARC600_FAMILY ) error ( <STR_LIT> ) ; if ( ( TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET || TARGET_SPFP ) && TARGET_HARD_FLOAT ) error ( <STR_LIT> ) ; if ( flag_pic && TARGET_ARC600_FAMILY ) { warning ( <NUM_LIT> , <STR_LIT> , arc_cpu_string ) ; flag_pic = <NUM_LIT> ; } arc_init_reg_tables ( ) ; memset ( arc_punct_chars , <NUM_LIT> , sizeof ( arc_punct_chars ) ) ; arc_punct_chars [ '#' ] = <NUM_LIT> ; arc_punct_chars [ '*' ] = <NUM_LIT> ; arc_punct_chars [ '?' ] = <NUM_LIT> ; arc_punct_chars [ '!' ] = <NUM_LIT> ; arc_punct_chars [ '^' ] = <NUM_LIT> ; arc_punct_chars [ '&' ] = <NUM_LIT> ; arc_punct_chars [ '+' ] = <NUM_LIT> ; arc_punct_chars [ '_' ] = <NUM_LIT> ;

if ( optimize > <NUM_LIT> && ! TARGET_NO_COND_EXEC ) {


<s> int AMDGPUCFGStructurizer :: getContinueZeroOpcode ( int OldOpcode ) { switch ( OldOpcode ) { case AMDGPU :: JUMP_COND :

case AMDGPU :: JUMP : return AMDGPU :: CONTINUE_LOGICALZ_i32 ;


<s> high_in2 = force_reg ( DImode , high_in2 ) ; if ( unsigned_p ) emit_insn ( gen_subdi3_compare1 ( high_dest , high_in1 , high_in2 ) ) ; else emit_insn ( gen_subvdi_insn ( high_dest , high_in1 , high_in2 ) ) ; } else { if ( CONST_INT_P ( low_in2 ) ) { high_in2 = force_reg ( DImode , high_in2 ) ;


<s> RegStrictDom |= mergeScore ( M , VgprScores [ T ] [ J ] , Other . VgprScores [ T ] [ J ] ) ; } if ( T == VM_CNT ) { for ( int J = <NUM_LIT> ; J <= VgprUB ; J ++ ) { unsigned char NewVmemTypes = VgprVmemTypes [ J ] | Other . VgprVmemTypes [ J ] ; RegStrictDom |= NewVmemTypes != VgprVmemTypes [ J ] ; VgprVmemTypes [ J ] = NewVmemTypes ; } } if ( T == LGKM_CNT ) { for ( int J = <NUM_LIT> ; J <= SgprUB ; J ++ ) { RegStrictDom |= mergeScore ( M , SgprScores [ J ] , Other . SgprScores [ J ] ) ;


<s> <STR_LIT> ( uint32_t SizeInBits , StringRef TypeName ) : Name ( TypeName ) { Kind = <STR_LIT> ; BTFType . Info = Kind << <NUM_LIT> ;

BTFType . Size = roundupToBytes ( SizeInBits ) ;


<s> TargetLowering :: CallLoweringInfo CLI ( DAG ) ;

CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , IntPtrTy , DAG . getTargetExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , std :: move ( Args ) , <NUM_LIT> ) ;


<s> bool isSCSrcB16 ( ) const { return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( MB ) . addImm ( <NUM_LIT> ) ; } else { unsigned MB ; if ( SrcVT == <STR_LIT> ) MB = <NUM_LIT> ; else if ( SrcVT == <STR_LIT> ) MB = <NUM_LIT> ; else MB = <NUM_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) . addImm ( MB ) ; }


<s> int body = ( code & <NUM_LIT> ) != <NUM_LIT> ; unw_word rlen ;


<s> if ( sibcall ) tmp = ret_rtx ; else tmp = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNUM ) ) ; gcc_assert ( CONST_INT_P ( callee_abi ) ) ; callee_abi = gen_rtx_UNSPEC ( DImode , gen_rtvec ( <NUM_LIT> , callee_abi ) , UNSPEC_CALLEE_ABI ) ; vec = gen_rtvec ( <NUM_LIT> , call , callee_abi , tmp ) ; call = gen_rtx_PARALLEL ( VOIDmode , vec ) ; aarch64_emit_call_insn ( call ) ;


<s> case AMDGPU :: V_MOV_B64_PSEUDO : case AMDGPU :: S_MOV_B32 : case AMDGPU :: S_MOV_B64 :


<s> if ( GET_MODE ( insn ) == SImode ) {

while ( GET_MODE ( insn ) != QImode ) insn = NEXT_INSN ( insn ) ;


<s> if ( I == MBB . end ( ) ) return false ; if ( I -> getOpcode ( ) == <STR_LIT> ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } BranchPredicate Pred = getBranchPredicate ( I -> getOpcode ( ) ) ;


<s> CooperTargetMachine :: CooperTargetMachine ( const Module & M , const std :: string & FS ) : <ISA_LIT>TargetMachine ( M , FS , true ) {


<s> <ISA_LIT>_64TargetMachine :: <ISA_LIT>_64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) , DL ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this ) , JITInfo ( * this ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> if ( MRI -> getRegClass ( PR . R ) != PredRC ) return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( const MachineOperand & MO : DefI -> operands ( ) ) if ( MO . isReg ( ) && MO . isUse ( ) ) WorkQ . push ( Register ( MO . getReg ( ) ) ) ; break ;


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ;

BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> static void rs6000_eliminate_indexed_memrefs ( rtx operands [ <NUM_LIT> ] ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , GET_MODE ( operands [ <NUM_LIT> ] ) , false ) ) operands [ <NUM_LIT> ] = replace_equiv_address ( operands [ <NUM_LIT> ] , copy_addr_to_reg ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , GET_MODE ( operands [ <NUM_LIT> ] ) , false ) ) operands [ <NUM_LIT> ] = replace_equiv_address ( operands [ <NUM_LIT> ] , copy_addr_to_reg ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ;


OutStreamer . EmitDataRegion ( MCDR_DataRegionEnd ) ;


<s> return pred ? pred : pred = gen_reg_rtx ( BImode ) ;


return get<ISA_LIT>ArchVersion ( ) == <STR_LIT> :: V69 ;


<s> return COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( ( outer == PLUS || outer == COMPARE ) && INTVAL ( x ) < <NUM_LIT> && INTVAL ( x ) > - <NUM_LIT> ) return <NUM_LIT> ; else if ( ( outer == IOR || outer == XOR || outer == AND ) && INTVAL ( x ) < <NUM_LIT> && INTVAL ( x ) >= - <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( outer == AND ) { int i ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) if ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == INTVAL ( x ) || ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == ~ INTVAL ( x ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer == ASHIFT || outer == ASHIFTRT || outer == LSHIFTRT ) return <NUM_LIT> ; return COSTS_N_INSNS ( <NUM_LIT> ) ; case CONST : case CONST_DOUBLE : case LABEL_REF : case SYMBOL_REF : return COSTS_N_INSNS ( <NUM_LIT> ) ; case UDIV : case UMOD : case DIV : case MOD : return <NUM_LIT> ; case TRUNCATE : return <NUM_LIT> ; case AND : case XOR : case IOR : return COSTS_N_INSNS ( <NUM_LIT> ) ; case MEM : return ( COSTS_N_INSNS ( <NUM_LIT> ) + COSTS_N_INSNS ( <NUM_LIT> ) * ( ( GET_MODE_SIZE ( mode ) - <NUM_LIT> ) / UNITS_PER_WORD ) + ( ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) ? COSTS_N_INSNS ( <NUM_LIT> ) : <NUM_LIT> ) ) ; case IF_THEN_ELSE :

if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PC || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PC ) return <NUM_LIT> ;


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ;


<s> uint64_t Count = CountNode -> getZExtValue ( ) ; unsigned BitSize = N . getValueType ( ) . getSizeInBits ( ) ; if ( Count < <NUM_LIT> || Count >= BitSize ) return false ; if ( RxSBG . Opcode == <STR_LIT> ) { if ( shiftedInBitsMatter ( RxSBG , Count , true ) ) return false ; } else { if ( ! refineRxSBGMask ( RxSBG , allOnes ( BitSize - Count ) << Count ) ) return false ; } RxSBG . Rotate = ( RxSBG . Rotate + Count ) & <NUM_LIT> ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * CountNode = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! CountNode ) return false ; uint64_t Count = CountNode -> getZExtValue ( ) ; unsigned BitSize = N . getValueType ( ) . getSizeInBits ( ) ; if ( Count < <NUM_LIT> || Count >= BitSize ) return false ; if ( RxSBG . Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { if ( shiftedInBitsMatter ( RxSBG , Count , false ) ) return false ; } else { if ( ! refineRxSBGMask ( RxSBG , allOnes ( BitSize - Count ) ) ) return false ; } RxSBG . Rotate = ( RxSBG . Rotate - Count ) & <NUM_LIT> ; RxSBG . Input = N . getOperand ( <NUM_LIT> ) ; return true ;


<s> uint64_t TruncMask = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ! isMask_64 ( TruncMask ) ) return SDValue ( ) ; uint64_t Width = CountPopulation_64 ( TruncMask ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; if ( Shift . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ;

if ( ! isa < ConstantSDNode > ( Shift -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> AMDGPUA<ISA_LIT> = <STR_LIT> ( * TM ) ; EnableLateStructurizeCFG = <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ;


<s> <ISA_LIT>PreAMXConfig ( Function & Func ) : F ( Func ) {


<s> if ( ! isVectorInstr ( Instr ) ) continue ; copies . clear ( ) ; createCopies ( F , Instr , copies ) ; for ( unsigned i = <NUM_LIT> , e = copies . size ( ) ; i != e ; ++ i ) BB -> insert ( II , copies [ i ] ) ;

assert ( ( copies . size ( ) > <NUM_LIT> ) && <STR_LIT> ) ;


<s> COFF<ISA_LIT>AsmBackend ( const Target & T , const Triple & TheTriple ) : <ISA_LIT>AsmBackend ( T , true ) {


<s> if ( ! Is32BitAddress && ! has<ISA_LIT>3 ( ) ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } if ( ! Offset . isImm ( ) ) return loadAndAddSymbolAddress ( Offset . getExpr ( ) , DstReg , BaseReg , Is32BitAddress , IDLoc , Out , STI ) ; if ( ! ABI . ArePtrs64bit ( ) ) { Is32BitAddress = true ;


<s> offset = ( cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size + cfun -> machine -> eh_return_data_regs_size + cfun -> machine -> local_size + cfun -> machine -> out_args_size ) ; } else if ( from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM ) { offset = <NUM_LIT> ; } else if ( from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM ) { offset = ( cfun -> machine -> local_size + cfun -> machine -> out_args_size ) ; } else if ( from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM ) { offset = ( - <NUM_LIT> ) * ( cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size + cfun -> machine -> eh_return_data_regs_size ) ; } else { gcc_unreachable ( ) ; } return offset ;


<s> if ( TARGET_CPU_ZARCH ) return get_hard_reg_initial_val ( Pmode , RETURN_REGNUM ) ; else { cfun_frame_layout . save_return_addr_p = true ; return gen_rtx_MEM ( Pmode , return_address_pointer_rtx ) ; } } if ( TARGET_PACKED_STACK ) offset = - <NUM_LIT> * UNITS_PER_WORD ; else offset = RETURN_REGNUM * UNITS_PER_WORD ;

addr = plus_constant ( frame , offset ) ;


<s> rtx mt_function_arg ( const CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named , int incoming_p ) { int slotno , regno ; rtx reg ;

slotno = mt_function_arg_slotno ( cum , mode , type , named , incoming_p , & regno ) ;


<s> Register Arg = getRegForValue ( * i ) ; if ( ! Arg . isValid ( ) ) return false ; Flags . setOrigAlign ( Align ( DL . getABITypeAlignment ( ArgTy ) ) ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < Register , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Subtarget -> genLongCalls ( ) ) UseReg = true ; Register CalleeReg ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ; else CalleeReg = getRegForValue ( Callee ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( UseReg ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( UseReg ) MIB . addReg ( CalleeReg ) ; else if ( ! IntrMemName ) MIB . addGlobalAddress ( GV , <NUM_LIT> , <NUM_LIT> ) ; else MIB . addExternalSymbol ( IntrMemName , <NUM_LIT> ) ; for ( Register R : RegArgs ) MIB . addReg ( R , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; SmallVector < Register , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes , isVarArg ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept ( UsedRegs , TRI ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ;


<s> rtx expand_builtin ( unsigned int code , tree exp , rtx target ) {

registered_function & rfn = * ( * registered_functions ) [ code ] ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) , IsGraphicsShader ( <STR_LIT> ( F . getCallingConv ( ) ) ) {


<s> void <ISA_LIT>InstPrinter :: printRegisterList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != OpNum ) O << <STR_LIT> ;

printRegName ( O , MI -> getOperand ( i ) . getReg ( ) ) ;


<s> pdp11_gen_int_label ( buf , <STR_LIT> , value ) ;

if ( ! TARGET_UNIX_ASM ) fprintf ( file , <STR_LIT> ) ;


<s> MDNode * Operand = N -> getOperand ( i ) ; MDNode * NewOperand = remapMDNode ( M , Operand ) ; OperandChanged |= Operand != NewOperand ; NewOperands . push_back ( NewOperand ) ; } if ( ! OperandChanged ) { return ; } N -> dropAllReferences ( ) ;

for ( SmallVectorImpl < MDNode * > :: iterator I = NewOperands . begin ( ) , E = NewOperands . end ( ) ;


<s> static DecodeStatus decodeRVCInstrRdRs1Rs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rs2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ;

Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>InstPrinter :: printCRxOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & CRx = MI -> getOperand ( OpNum ) ; O << 'c' << CRx . getImm ( ) ;


<s> case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ;


<s> exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Incr2 ) . addReg ( Incr ) . addReg ( ShiftAmt ) ; BB = loopMBB ; unsigned LL = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( AlignedAddr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , BinOpRes ) . addReg ( <STR_LIT> ) . addReg ( AndRes ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , NewVal ) . addReg ( BinOpRes ) . addReg ( Mask ) ; } else if ( BinOpcode ) {

BuildMI ( BB , DL , TII -> get ( BinOpcode ) , BinOpRes ) . addReg ( OldVal ) . addReg ( Incr2 ) ;


<s> inline int vec_any_ge ( vector float a1 , vector float a2 ) {


<s> return <STR_LIT> ; } else if ( INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) >= - <NUM_LIT> ) return <STR_LIT> ; } else if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ) != PLUS ) { rtx labelref = XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ; if ( MOTOROLA ) asm_fprintf ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( XEXP ( labelref , <NUM_LIT> ) ) ) ; else ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( XEXP ( labelref , <NUM_LIT> ) ) ) ; } return <STR_LIT> ;


<s> LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; TLI = TLIP ? & TLIP -> getTLI ( * L -> getHeader ( ) -> getParent ( ) ) : nullptr ; DL = & L -> getHeader ( ) -> getModule ( ) -> getDataLayout ( ) ; this -> L = L ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ST -> hasV8_1MMainlineOps ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ;

auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * {


<s> DT . buildDepsGraph ( Graph , MMI ) ;


<s> } if ( State . RecursiveCall ) return false ; unsigned Opc = Inst . getOpcode ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; if ( ( State . I == <NUM_LIT> ) && ( State . SaveCount == <NUM_LIT> ) ) { switch ( Opc ) { default : State . SaveCount = <NUM_LIT> ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; } } if ( State . I < State . SaveCount ) { State . Saved [ State . I ++ ] = Inst ; if ( State . I < State . SaveCount ) return true ; } if ( State . SaveCount > <NUM_LIT> ) { assert ( State . I == State . SaveCount && <STR_LIT> ) ; State . SaveCount = <NUM_LIT> ; State . RecursiveCall = true ; switch ( State . Saved [ <NUM_LIT> ] . getOpcode ( ) ) { default : break ; case <STR_LIT> : EmitDataMask ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> :

EmitDirectGuardCall ( State . I , State . Saved , Out ) ;


<s> switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_lds : return Operand . isLDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_glc : return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcB32 : return Operand . isSSrcB32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrcF32 : return Operand . isSSrcF32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; case MCK_VReg32OrOff : return Operand . isVReg32OrOff ( ) ? Match_Success : Match_InvalidOperand ;


<s> unsigned CC = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; PredicationCode = CC ; } } if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) {

unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ;


<s> assert ( index < <ISA_LIT>ImageArgs . size ( ) && <STR_LIT> ) ;


<s> int64_t Sels [ <NUM_LIT> ] ; if ( ! trySkipToken ( AsmToken :: LBrac ) ) return MatchOperand_ParseFail ; if ( getParser ( ) . parseAbsoluteExpression ( Sels [ <NUM_LIT> ] ) ) return MatchOperand_ParseFail ; if ( <NUM_LIT> > Sels [ <NUM_LIT> ] || <NUM_LIT> < Sels [ <NUM_LIT> ] ) return MatchOperand_ParseFail ; for ( size_t i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! trySkipToken ( AsmToken :: Comma ) ) return MatchOperand_ParseFail ; if ( getParser ( ) . parseAbsoluteExpression ( Sels [ i ] ) ) return MatchOperand_ParseFail ; if ( <NUM_LIT> > Sels [ i ] || <NUM_LIT> < Sels [ i ] ) return MatchOperand_ParseFail ; } if ( ! trySkipToken ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; unsigned DPP8 = <NUM_LIT> ;

for ( size_t i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) DPP8 |= ( Sels [ i ] << ( i * <NUM_LIT> ) ) ;


<s> bool IsByte = std :: is_same < int8_t , std :: make_signed_t < T >> :: value || std :: is_same < int8_t , T > :: value ; if ( auto ShiftedImm = getShiftedVal < <NUM_LIT> > ( ) ) if ( ! ( IsByte && ShiftedImm -> second ) && <STR_LIT> < T > ( ShiftedImm -> first << ShiftedImm -> second ) ) return DiagnosticPredicateTy :: Match ; return DiagnosticPredicateTy :: NearMatch ;


<s> return __builtin_mve_vcmulq_rot90v8hf ( __a , __b ) ;


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT ElemVT = VT . getScalarType ( ) ; SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; switch ( ElemVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> :


<s> DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = <NUM_LIT> ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = <NUM_LIT> ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } else TREE_PUBLIC ( ifunc_alias_decl ) = <NUM_LIT> ; t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_CONTEXT ( t ) = decl ; DECL_ARTIFICIAL ( t ) = <NUM_LIT> ; DECL_IGNORED_P ( t ) = <NUM_LIT> ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( ifunc_alias_decl != NULL ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {


<s> void <ISA_LIT>GOT :: initGOTList ( ) { m_SymbolOrderMap . clear ( ) ; m_MultipartList . clear ( ) ; m_MultipartList . push_back ( GOTMultipart ( ) ) ; m_MultipartList . back ( ) . m_Inputs . insert ( m_pInput ) ; m_MergedGlobalSymbols . clear ( ) ; m_InputGlobalSymbols . clear ( ) ; m_MergedLocalSymbols . clear ( ) ; m_InputLocalSymbols . clear ( ) ;


<s> SDNode * N = Op . getNode ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; EVT NewVT = getTypeToTransformTo ( * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , dl , NewVT , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;

Hi = DAG . getNode ( <STR_LIT> , dl , NewVT , Op , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> inline unsigned M1 ( unsigned Val ) {


<s> static int riscv_flatten_aggregate_argument ( const_tree type , riscv_aggregate_field fields [ <NUM_LIT> ] , bool ignore_zero_width_bit_field_p ) { if ( ! type || TREE_CODE ( type ) != RECORD_TYPE ) return - <NUM_LIT> ;

return riscv_flatten_aggregate_field ( type , fields , <NUM_LIT> , <NUM_LIT> , ignore_zero_width_bit_field_p ) ;


<s> mips_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named ) ; if ( ! info . fpr_p ) cum -> gp_reg_found = true ; if ( cum -> arg_number < <NUM_LIT> && info . fpr_p ) cum -> fp_code += ( arg . mode == SFmode ? <NUM_LIT> : <NUM_LIT> ) << ( cum -> arg_number * <NUM_LIT> ) ; if ( mips_abi != ABI_EABI || ! info . fpr_p ) cum -> num_gprs = info . reg_offset + info . reg_words ; else if ( info . reg_words > <NUM_LIT> ) cum -> num_fprs += MAX_FPRS_PER_FMT ; if ( info . stack_words > <NUM_LIT> ) cum -> stack_words = info . stack_offset + info . stack_words ; cum -> arg_number ++ ;


<s> <ISA_LIT>ebTargetMachine :: <ISA_LIT>ebTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> SDValue And = Src . getOperand ( <NUM_LIT> ) ; if ( And . hasOneUse ( ) && <STR_LIT> ( And . getOperand ( <NUM_LIT> ) . getNode ( ) , SplatVal ) && SplatVal . isPowerOf2 ( ) ) { MVT VT = Src . getSimpleValueType ( ) ; unsigned BitWidth = VT . getScalarSizeInBits ( ) ; unsigned ShAmt = BitWidth - SplatVal . logBase2 ( ) - <NUM_LIT> ; SDLoc DL ( And ) ; SDValue X = And . getOperand ( <NUM_LIT> ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) { VT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; X = DAG . getBitcast ( VT , X ) ; } SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( ShAmt , DL , VT ) ) ; SDValue Cast = DAG . getBitcast ( SrcVT , Shl ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Cast ) ; } } return SDValue ( ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { if ( ! OutStreamer . hasRawTextSupport ( ) ) return ; emitFrameDirective ( ) ;


<s> Op -> PSBHint . Data = Str . data ( ) ; Op -> PSBHint . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op ;


<s> static bool isIRF ( unsigned Field , bool IsSPU ) { if ( IsSPU ) return Field >= <NUM_LIT> && Field <= <NUM_LIT> ;

else return Field >= <NUM_LIT> && Field <= <NUM_LIT> ;


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return false ; const MachineInstr * MI = MRI . getUniqueVRegDef ( Reg ) ; return MI && MI -> isImplicitDef ( ) ;


<s> case 'b' : case 'h' : case 's' : case 'd' : case 'q' : break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; O << getRegisterName ( Reg ) ; if ( suffix != <NUM_LIT> ) O << '.' << suffix ;


<s> if ( is32Bit ( VT ) ) lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;

else lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> else ISARevision = <NUM_LIT> ; } else { ISARevision = <NUM_LIT> ; if ( P . has<ISA_LIT>5 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>4 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>3 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>2 ( ) ) ISALevel = <NUM_LIT> ; else if ( P . has<ISA_LIT>1 ( ) ) ISALevel = <NUM_LIT> ;


<s> * lhs = SET_DEST ( pat ) ; * rhs1 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; if ( GET_RTX_CLASS ( GET_CODE ( SET_SRC ( pat ) ) ) != RTX_UNARY ) * rhs2 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ;


<s> constant_to_array ( mode , op , arr ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) for ( j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) if ( arr [ j ] != arr [ i + j ] ) return <NUM_LIT> ;

val = ( arr [ <NUM_LIT> ] << <NUM_LIT> ) | ( arr [ <NUM_LIT> ] << <NUM_LIT> ) | ( arr [ <NUM_LIT> ] << <NUM_LIT> ) | arr [ <NUM_LIT> ] ;


<s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {


<s> Incr = - <NUM_LIT> ; } for ( ; SubReg != End ; SubReg += Incr ) { const MachineInstrBuilder & MIB = BuildMI ( MBB , I , DL , get ( Opcode ) ) ; AddSubReg ( MIB , DestReg , Indices [ SubReg ] , RegState :: Define , TRI ) ; AddSubReg ( MIB , SrcReg , Indices [ SubReg ] , <NUM_LIT> , TRI ) ; AddSubReg ( MIB , SrcReg , Indices [ SubReg ] , getKillRegState ( KillSrc ) , TRI ) ; }


<s> bool SplitStack = MF . shouldSplitStack ( ) ; bool Lower = ( Subtarget -> isOSWindows ( ) && ! Subtarget -> isTargetMacho ( ) ) || SplitStack ; SDLoc dl ( Op ) ; if ( ! Lower ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDNode * Node = Op . getNode ( ) ; unsigned SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue Tmp1 = SDValue ( Node , <NUM_LIT> ) ; SDValue Tmp2 = SDValue ( Node , <NUM_LIT> ) ; SDValue Tmp3 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Chain = Tmp1 . getOperand ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDLoc ( Node ) ) ; SDValue Size = Tmp2 . getOperand ( <NUM_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Tmp3 ) -> getZExtValue ( ) ; const TargetFrameLowering & TFI = * getTargetMachine ( ) . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , dl ) ; }

SDValue Chain = Op . getOperand ( <NUM_LIT> ) ;


<s> unsigned oc = MI . getOpcode ( ) ; if ( oc == <STR_LIT> || oc == <STR_LIT> || oc == <STR_LIT> || oc == <STR_LIT> || oc == <STR_LIT> ) { assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { sourceReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; destReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } } else if ( oc == <STR_LIT> ) { assert ( MI . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { sourceReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> BasicBlock * Dest ; if ( To -> isZero ( ) ) Dest = BI -> getSuccessor ( <NUM_LIT> ) ; else Dest = BI -> getSuccessor ( <NUM_LIT> ) ; BranchInst :: Create ( Dest , BI ) ;


<s> bool IsBufferSMRD = TII . isBufferSMRD ( * SMRD ) ; for ( const MachineOperand & Use : SMRD -> uses ( ) ) { if ( ! Use . isReg ( ) ) continue ; int WaitStatesNeededForUse = SmrdSgprWaitStates - getWaitStatesSinceDef ( Use . getReg ( ) , IsHazardDefFn , SmrdSgprWaitStates ) ; WaitStatesNeeded = std :: max ( WaitStatesNeeded , WaitStatesNeededForUse ) ; if ( IsBufferSMRD ) { int WaitStatesNeededForUse = SmrdSgprWaitStates - getWaitStatesSinceDef ( Use . getReg ( ) , IsBufferHazardDefFn , SmrdSgprWaitStates ) ; WaitStatesNeeded = std :: max ( WaitStatesNeeded , WaitStatesNeededForUse ) ; } }


<s> void <ISA_LIT>MCInstLower :: Initialize ( Mangler * M , MCContext * C ) { Mang = M ;


<s> ret = simplify_const_unary_operation ( FLOAT_EXTEND , SFmode , val , BFmode ) ; if ( ret ) return ret ; ret = gen_reg_rtx ( SImode ) ;

emit_move_insn ( ret , GEN_INT ( INTVAL ( op ) & <NUM_LIT> ) ) ;


<s> if ( mode == SFmode ) return ( CURR_REGMODE_PRESSURE ( SFmode ) > SFMODE_MAX_WEIGHT ) ; else return ( CURR_REGMODE_PRESSURE ( SImode ) > SIMODE_MAX_WEIGHT ) ;


<s> unsigned Reg = DefMI -> getOperand ( DefIdx ) . getReg ( ) ; if ( DepMI -> readsRegister ( Reg , & getRegisterInfo ( ) ) || ! isPredicated ( DepMI ) ) return <NUM_LIT> ;

return getInstrLatency ( ItinData , DefMI ) ;


<s> bool isPICStyleGOT ( ) const { return PICStyle == PICStyles :: Style :: GOT ;


<s> explicit RedundantLdStEliminator ( MachineFunction & mf , const <ISA_LIT>RegisterInfo * tri , unsigned int tgtreg , const <ISA_LIT>MachineFunctionInfo & PMFI ) : MF ( mf ) , TRI ( tri ) , TgtReg ( tgtreg ) , NumFIs ( PMFI . getSinglePathFICnt ( ) ) , OffsetFIs ( PMFI . getSinglePathLoopCntFI ( <NUM_LIT> ) ) {


<s> static bool aarch64_mode_valid_for_sched_fusion_p ( machine_mode mode ) { return mode == SImode || mode == DImode || mode == SFmode || mode == DFmode || ( aarch64_vector_mode_supported_p ( mode ) && ( known_eq ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) || ( known_eq ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS ) == <NUM_LIT> ) ) ) ;


<s> static bool find_mem_ref ( rtx pat , rtx * mem_ref ) { const char * fmt ; int i , j ; if ( tie_operand ( pat , VOIDmode ) ) return false ; if ( GET_CODE ( pat ) == MEM ) { * mem_ref = pat ; return true ;


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ;


<s> Value * Joined = Builder . CreateShuffleVector ( Work [ ThisW ] [ i ] , Work [ ThisW ] [ i + <NUM_LIT> ] , SMask ) ; Work [ OtherW ] . push_back ( Joined ) ; } std :: swap ( ThisW , OtherW ) ; } SMask . resize ( Vecs . size ( ) * getSizeOf ( Vecs . front ( ) -> getType ( ) ) ) ; std :: iota ( SMask . begin ( ) , SMask . end ( ) , <NUM_LIT> ) ; Value * Total = Work [ OtherW ] . front ( ) ; return Builder . CreateShuffleVector ( Total , SMask ) ;


<s> assert ( ( Size & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * CPEMI = BuildMI ( BB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; std :: vector < CPEntry > CPEs ; CPEs . push_back ( CPEntry ( CPEMI , i ) ) ;


<s> FunctionInfoMap [ F ] = calculateFunctionInfo ( F , TM . getTargetData ( ) ) ; Info = & FunctionInfoMap [ F ] ; } else { Info = & info_item -> second ; } const FunctionType * FT = F -> getFunctionType ( ) ; switch ( Info -> getDecorationStyle ( ) ) { case None : break ; case StdCall : if ( ! FT -> isVarArg ( ) || ( FT -> getNumParams ( ) == <NUM_LIT> ) || ( FT -> getNumParams ( ) == <NUM_LIT> && F -> hasStructRetAttr ( ) ) ) Name += '@' + utostr_32 ( Info -> getBytesToPopOnReturn ( ) ) ; break ; case FastCall : if ( ! FT -> isVarArg ( ) || ( FT -> getNumParams ( ) == <NUM_LIT> ) || ( FT -> getNumParams ( ) == <NUM_LIT> && F -> hasStructRetAttr ( ) ) ) Name += '@' + utostr_32 ( Info -> getBytesToPopOnReturn ( ) ) ; if ( Name [ <NUM_LIT> ] == '_' ) Name [ <NUM_LIT> ] = '@' ; else Name = '@' + Name ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> MCOperand lowerSymbolOperandDarwin ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCOperand lowerSymbolOperandELF ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCOperand lowerSymbolOperandCOFF ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ;

MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ;


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ; } uint64_t NegatedImm = ( ~ SplatBits ) . getZExtValue ( ) ; Val = isNEONModifiedImm ( NegatedImm , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VmovVT , VT . is128BitVector ( ) , VMVNModImm ) ; if ( Val . getNode ( ) ) { SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; bool isOnlyLowElement = true ; bool usesOnlyOneValue = true ; bool isConstant = true ; SDValue Value ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . getOpcode ( ) == <STR_LIT> ) continue ; if ( i > <NUM_LIT> ) isOnlyLowElement = false ; if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ; if ( ! Value . getNode ( ) ) Value = V ; else if ( V != Value ) usesOnlyOneValue = false ; } if ( ! Value . getNode ( ) ) return DAG . getUNDEF ( VT ) ; if ( isOnlyLowElement ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( usesOnlyOneValue && EltSize <= <NUM_LIT> ) { if ( ! isConstant ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; if ( VT . getVectorElementType ( ) . isFloatingPoint ( ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , & Ops [ <NUM_LIT> ] , NumElts ) ;

Val = LowerBUILD_VECTOR ( Val , DAG , ST ) ;


<s> else if ( OpVal != N -> getOperand ( i ) ) return <NUM_LIT> ; } if ( OpVal . getNode ( ) != <NUM_LIT> ) {

if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( OpVal ) ) {


<s> if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; return Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) : DAG . getZeroExtendVectorInReg ( ExOp , DL , VT ) ; } if ( ! Subtarget . hasInt256 ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) ) { unsigned NumVecs = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumSubElts = <NUM_LIT> / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ;

for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i != NumVecs ; ++ i , Offset += NumSubElts ) {


<s> static __inline vec_ullong2 spu_cmpabsgt ( vec_double2 a , vec_double2 b ) { return ( ( vec_ullong2 ) ( si_dfcmgt ( ( qword ) ( a ) , ( qword ) ( b ) ) ) ) ;


<s> NewMI = BuildMI ( B , MI , DL , get ( insn ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << getName ( NewMI -> getOpcode ( ) ) << <STR_LIT> << NewMI -> getDesc ( ) . getSchedClass ( ) ) ; NewMI -> eraseFromParent ( ) ;


<s> if ( reg == stack_pointer_rtx || reg == frame_pointer_rtx || reg == hard_frame_pointer_rtx ) { offset -= cfun -> machine -> frame . total_size ; if ( reg == hard_frame_pointer_rtx ) offset += cfun -> machine -> frame . hard_frame_pointer_offset ;


<s> OutMI . setOpcode ( RVV -> BaseInstr ) ; const MachineBasicBlock * MBB = MI -> getParent ( ) ; assert ( MBB && <STR_LIT> ) ; const MachineFunction * MF = MBB -> getParent ( ) ; assert ( MF && <STR_LIT> ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; assert ( TRI && <STR_LIT> ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { int OpNo = ( int ) MI -> getOperandNo ( & MO ) ; assert ( OpNo >= <NUM_LIT> && <STR_LIT> ) ; if ( OpNo == RVV -> getVLIndex ( ) || OpNo == RVV -> getSEWIndex ( ) || OpNo == RVV -> getMergeOpIndex ( ) ) continue ; MCOperand MCOp ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) {

Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ;


<s> LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getLoad ( VT , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getPointerInfo ( ) , LN0 -> isVolatile ( ) , LN0 -> isNonTemporal ( ) , LN0 -> isInvariant ( ) , LN0 -> getAlignment ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN0 , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( Opcode , SDLoc ( N ) , VT , Load ) ;


<s> unsigned Lgkmcnt = getBitMask ( getLgkmcntBitShift ( ) , getLgkmcntBitWidth ( ) ) ;


<s> uint32_t MaskVal = Mask -> getZExtValue ( ) ; if ( isMask_32 ( MaskVal ) ) { uint32_t WidthVal = countPopulation ( MaskVal ) ; ReplaceNode ( N , getS_BFE ( <STR_LIT> , SDLoc ( N ) , Srl . getOperand ( <NUM_LIT> ) , ShiftVal , WidthVal ) ) ; return ; } } } break ; case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { const SDValue & And = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * Shift = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( Shift && Mask ) { uint32_t ShiftVal = Shift -> getZExtValue ( ) ; uint32_t MaskVal = Mask -> getZExtValue ( ) >> ShiftVal ; if ( isMask_32 ( MaskVal ) ) { uint32_t WidthVal = countPopulation ( MaskVal ) ; ReplaceNode ( N , getS_BFE ( <STR_LIT> , SDLoc ( N ) , And . getOperand ( <NUM_LIT> ) , ShiftVal , WidthVal ) ) ; return ; } } } else if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SelectS_BFEFromShifts ( N ) ; return ; } break ; case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SelectS_BFEFromShifts ( N ) ; return ; } break ;


<s> buildBlockRefs ( EA , RefM ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineBasicBlock & EntryB = * EA . Addr -> getCode ( ) ; assert ( EntryB . pred_empty ( ) && <STR_LIT> ) ; for ( auto I = MRI . livein_begin ( ) , E = MRI . livein_end ( ) ; I != E ; ++ I ) LiveIns . insert ( RegisterRef ( I -> first ) ) ; for ( auto I : EntryB . liveins ( ) ) LiveIns . insert ( RegisterRef ( I . PhysReg , I . LaneMask ) ) ; for ( std :: pair < RegisterId , LaneBitmask > P : LiveIns ) { NodeAddr < PhiNode * > PA = newPhi ( EA ) ; uint16_t PhiFlags = NodeAttrs :: PhiRef | NodeAttrs :: Preserving ; RegisterRef RR ( P . first , P . second ) ; NodeAddr < DefNode * > DA = newDef ( PA , RR , PhiFlags ) ; PA . Addr -> addMember ( DA , * this ) ; } RegisterSet EHRegs = getLandingPadLiveIns ( ) ; if ( ! EHRegs . empty ( ) ) { for ( NodeAddr < BlockNode * > BA : Blocks ) { const MachineBasicBlock & B = * BA . Addr -> getCode ( ) ; if ( ! B . isEHPad ( ) ) continue ; NodeList Preds ; for ( MachineBasicBlock * PB : B . predecessors ( ) ) Preds . push_back ( findBlock ( PB ) ) ; for ( RegisterRef RR : EHRegs ) { NodeAddr < PhiNode * > PA = newPhi ( BA ) ; uint16_t PhiFlags = NodeAttrs :: PhiRef | NodeAttrs :: Preserving ;