<s> } int MitigatedGadgets = <NUM_LIT> , RemainingGadgets = <NUM_LIT> ; NodeSet ReachableNodes { G } ; for ( const Node & RootN : G . nodes ( ) ) { if ( llvm :: none_of ( RootN . edges ( ) , MachineGadgetGraph :: isGadgetEdge ) ) continue ; ReachableNodes . clear ( ) ; std :: function < void ( const Node * , bool ) > FindReachableNodes = [ & ] ( const Node * N , bool FirstNode ) { if ( ! FirstNode ) ReachableNodes . insert ( * N ) ; for ( const Edge & E : N -> edges ( ) ) { const Node * Dest = E . getDest ( ) ; if ( MachineGadgetGraph :: isCFGEdge ( E ) && ! ElimEdges . contains ( E ) && ! ReachableNodes . contains ( * Dest ) ) FindReachableNodes ( Dest , false ) ; } } ; FindReachableNodes ( & RootN , true ) ; for ( const Edge & E : RootN . edges ( ) ) { if ( MachineGadgetGraph :: isGadgetEdge ( E ) ) { if ( ReachableNodes . contains ( * E . getDest ( ) ) ) { ++ RemainingGadgets ; } else { ++ MitigatedGadgets ; ElimEdges . insert ( E ) ; } }


<s> SmallString < <NUM_LIT> > SymbolName ; getNameWithPrefix ( SymbolName , MF -> getFunction ( ) ) , getTargetStreamer ( ) . Emit<ISA_LIT>SymbolType ( SymbolName , ELF :: STT_<ISA_LIT>_HSA_KERNEL ) ; }

AsmPrinter :: EmitFunctionEntryLabel ( ) ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; }


<s> void mep_function_profiler ( FILE * file ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ;


<s> if ( ! isShiftedImm ( ) && ! isImm ( ) ) return false ; const MCExpr * Expr ; if ( isShiftedImm ( ) ) { unsigned Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != <NUM_LIT> ) return false ; } else Expr = getImm ( ) ;

const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ;


<s> } if ( ( I -> mayLoad ( ) ) && std :: next ( I ) == E && I != MBB -> begin ( ) ) { MachineBasicBlock * newBB = MF . CreateMachineBasicBlock ( ( I -> getParent ( ) ) -> getBasicBlock ( ) ) ; MachineFunction :: iterator It = MBB -> getIterator ( ) ; MF . insert ( It , newBB ) ; newBB -> splice ( newBB -> end ( ) , I -> getParent ( ) , I ) ; MBB -> addSuccessor ( newBB ) ; newBB -> setHasAddressTaken ( ) ; break ; } } } return completed ;


<s> if ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset & <NUM_LIT> ) return <STR_LIT> ; else if ( Offset > <NUM_LIT> || Offset < <NUM_LIT> ) return <STR_LIT> ; break ; }


<s> static bool isLegalMUBUFImmOffset ( const ConstantSDNode * Imm ) {

return isUInt < <NUM_LIT> > ( Imm -> getZExtValue ( ) ) ;


<s> cum -> words = GET_MODE_SIZE ( mode ) ; } else { cum -> words += GET_MODE_SIZE ( mode ) ;

if ( cum -> words <= HARD_REG_SIZE ) cum -> nregs = <NUM_LIT> ;


<s> rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( tmp , vperm ) ) ; emit_insn ( par ) ;


<s> if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; if ( isNegative ) RealVal . changeSign ( ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; int Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> && ! RealVal . isPosZero ( ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) ) { int64_t Val ; if ( ! isNegative && Tok . getString ( ) . startswith ( <STR_LIT> ) ) { Val = Tok . getIntVal ( ) ; if ( Val > <NUM_LIT> || Val < <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; }


<s> if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ) return false ; return MCInstrAnalysis :: isConditionalBranch ( Inst ) ;


<s> if ( HasExtender || <ISA_LIT>MCInstrInfo :: isConstExtended ( MII , * MI ) ) if ( <ISA_LIT>MCInstrInfo :: getExtendableOp ( MII , * MI ) == OpNo ) O << <STR_LIT> ;


<s> Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; }


<s> switch ( Kind ) { default : break ; case <STR_LIT> : Value >>= <NUM_LIT> ;


<s> virtual const char * getPassName ( ) const {


<s> const bool CanUseBFC = AST . hasV6T2Ops ( ) || AST . hasV7Ops ( ) ; const unsigned AlignMask = Alignment - <NUM_LIT> ; const unsigned NrBitsToZero = countTrailingZeros ( Alignment ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; if ( ! AFI -> isThumbFunction ( ) ) { if ( CanUseBFC ) { AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( ~ AlignMask ) ) ; } else if ( AlignMask <= <NUM_LIT> ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( AlignMask ) ) ) ; } else { assert ( ! MustBeSingleInstruction && <STR_LIT> <STR_LIT> <STR_LIT> ) ;

AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) ) ) ;


<s> const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GO ) ; XSym -> setStorageClass ( SC ) ; MCSectionXCOFF * Csect = OutStreamer -> getContext ( ) . getXCOFFSection ( XSym -> getName ( ) , isa < Function > ( GO ) ? XCOFF :: XMC_DS : XCOFF :: XMC_UA , XCOFF :: XTY_ER , SC , SectionKind :: getMetadata ( ) ) ; XSym -> setContainingCsect ( Csect ) ; } return XSym -> getContainingCsect ( ) -> getQualNameSymbol ( ) ; } if ( GV ) { SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; return Csect -> getQualNameSymbol ( ) ; } return getSymbol ( GV ) ;


<s> LLT Ty = B . getMRI ( ) -> getType ( DstReg ) ; if ( Ty == S32 ) { B . buildInstr ( <STR_LIT> , { DstReg } , { MI . getOperand ( <NUM_LIT> ) } , MI . getFlags ( ) ) ; } else { auto Cvt0 = B . buildInstr ( <STR_LIT> , { S32 } , { MI . getOperand ( <NUM_LIT> ) } , MI . getFlags ( ) ) ; B . buildFPTrunc ( DstReg , Cvt0 , MI . getFlags ( ) ) ; }


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset - <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ;


<s> if ( IsConstantInSmallSection ( DL , C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align , GO ) ;


const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> rtx insn ; int i ; if ( link_size > <NUM_LIT> ) link_size = <NUM_LIT> ; insn = emit_insn ( gen_link ( GEN_INT ( - <NUM_LIT> - link_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < XVECLEN ( PATTERN ( insn ) , <NUM_LIT> ) ; i ++ ) { rtx set = XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , i ) ; gcc_assert ( GET_CODE ( set ) == SET ) ;

RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ;


<s> if ( CModel == CodeModel :: Large || ! GVar || ! GVar -> hasInitializer ( ) || GVar -> hasCommonLinkage ( ) || GVar -> hasAvailableExternallyLinkage ( ) ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( HighPartReg ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( HighPartReg ) . addGlobalAddress ( GV ) ; }


<s> bool <ISA_LIT>InstrInfo :: isVecAcc ( const MachineInstr & MI ) const {

return isHVXVec ( MI ) && isAccumulator ( MI ) ;


<s> if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return nregs_table [ regno ] . hi_regs ; if ( regno == A0_REGNO && mode == SImode && TARGET_A16 ) return <NUM_LIT> ; if ( ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> || mode == PSImode ) && TARGET_A24 ) return nregs_table [ regno ] . pi_regs ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return nregs_table [ regno ] . si_regs ;

if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return nregs_table [ regno ] . di_regs ;


<s> if ( TheTriple . getArch ( ) == Triple :: mips || TheTriple . getArch ( ) == Triple :: mipsel ) CPU = <STR_LIT> ; else CPU = <STR_LIT> ; } return CPU ;


<s> SDValue TCChain = InChain ; bool isTailCall = isInTailCallPosition ( DAG , Op . getNode ( ) , TCChain ) ; if ( isTailCall ) InChain = TCChain ; TargetLowering :: CallLoweringInfo CLI ( InChain , RetTy , false , false , false , false , <NUM_LIT> , getLibcallCallingConv ( Call ) , isTailCall , false , true , Callee , Args , DAG , SDLoc ( Op ) ) ;

std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ;


<s> case AMDGPU :: sub2 : return <NUM_LIT> ; case AMDGPU :: sub3 : return <NUM_LIT> ; }


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _m_empty ( void ) { _mm_empty ( ) ;


<s> switch ( rs6000_cpu_attr ) { case CPU_PPC8540 : case CPU_PPC8548 : return <NUM_LIT> ;


<s> default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerMSAStoreIntr ( Op , DAG , Intr ) ;


<s> DiagnosticInfoUnsupported :: DiagnosticInfoUnsupported ( const Function & Fn , const Twine & Desc , DiagnosticSeverity Severity ) : DiagnosticInfo ( getKindID ( ) , Severity ) , Description ( Desc ) , Fn ( Fn ) {


<s> int ResTyNumElts = ResTy . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Indices ; for ( int i = <NUM_LIT> ; i < ResTyNumElts ; ++ i ) Indices . push_back ( Node -> getMaskElt ( i ) ) ; if ( isVECTOR_SHUFFLE_SPLATI ( Op , ResTy , Indices , DAG ) ) return lowerVECTOR_SHUFFLE_VSHF ( Op , ResTy , Indices , DAG ) ; SDValue Result ; if ( ( Result = lowerVECTOR_SHUFFLE_ILVEV ( Op , ResTy , Indices , DAG ) ) ) return Result ; if ( ( Result = lowerVECTOR_SHUFFLE_ILVOD ( Op , ResTy , Indices , DAG ) ) ) return Result ; if ( ( Result = lowerVECTOR_SHUFFLE_ILVL ( Op , ResTy , Indices , DAG ) ) ) return Result ; if ( ( Result = lowerVECTOR_SHUFFLE_ILVR ( Op , ResTy , Indices , DAG ) ) ) return Result ; if ( ( Result = lowerVECTOR_SHUFFLE_PCKEV ( Op , ResTy , Indices , DAG ) ) ) return Result ; if ( ( Result = lowerVECTOR_SHUFFLE_PCKOD ( Op , ResTy , Indices , DAG ) ) ) return Result ; if ( ( Result = lowerVECTOR_SHUFFLE_SHF ( Op , ResTy , Indices , DAG ) ) ) return Result ; return lowerVECTOR_SHUFFLE_VSHF ( Op , ResTy , Indices , DAG ) ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( new TestMFP ( ) ) ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( formatted_raw_ostream & OS , MCInstPrinter & InstPrinter ) : OS ( OS ) , InstPrinter ( InstPrinter ) {


<s> const char * <ISA_LIT>MCExpr :: getName ( ) const { const auto & Modifier = std :: find_if ( std :: begin ( ModifierNames ) , std :: end ( ModifierNames ) , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> Spelling ; }


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override {


<s> ShapeKind getKind ( ) const { return Kind ;


<s> if ( I -> isReg ( ) && ! I -> getReg ( ) . isVirtual ( ) && I -> isUse ( ) && RI . isPhysRegLiveAcrossClauses ( I -> getReg ( ) ) ) return false ;


return ( __m128i ) __builtin_ia32_pmovqb128_mask ( ( __v2di ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = Clause . second . size ( ) ; i < e ; ++ i ) { BB -> splice ( InsertPos , BB , Clause . second [ i ] ) ;


<s> return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDNode * Op0 = Node -> getOperand ( <NUM_LIT> ) . getNode ( ) ; uint64_t Mask ; if ( isa < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) && isConstantMask ( Op0 , Mask ) ) { uint64_t ShAmt = Node -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) { SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( Node ) , XLenVT ) ; CurDAG -> SelectNodeTo ( Node , <STR_LIT> , XLenVT , Op0 -> getOperand ( <NUM_LIT> ) , ShAmtVal ) ; return ; } } break ; } case <STR_LIT> : assert ( ! Subtarget -> is64Bit ( ) && <STR_LIT> ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) ) ) ; return ; case <STR_LIT> : { LoadSDNode * Load = cast < LoadSDNode > ( Node ) ; if ( Load -> getAddressingMode ( ) != <STR_LIT> ) break ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue Base = Node -> getOperand ( <NUM_LIT> ) ; SDValue Offset = Node -> getOperand ( <NUM_LIT> ) ; bool simm12 = false ; bool signExtend = Load -> getExtensionType ( ) == <STR_LIT> ; if ( auto ConstantOffset = dyn_cast < ConstantSDNode > ( Offset ) ) { int ConstantVal = ConstantOffset -> getSExtValue ( ) ; simm12 = isInt < <NUM_LIT> > ( ConstantVal ) ; if ( simm12 ) Offset = CurDAG -> getTargetConstant ( ConstantVal , SDLoc ( Offset ) , Offset . getValueType ( ) ) ; } unsigned Opcode = <NUM_LIT> ; switch ( Load -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : if ( simm12 && signExtend ) Opcode = <STR_LIT> ; else if ( simm12 && ! signExtend ) Opcode = <STR_LIT> ; else if ( ! simm12 && signExtend ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; break ; case <STR_LIT> : if ( simm12 && signExtend ) Opcode = <STR_LIT> ;


<s> switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> :

assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ;


<s> assert ( bss_sect_hdr != NULL ) ; SectionData * bss_section = NULL ; if ( bss_sect_hdr -> hasSectionData ( ) ) bss_section = bss_sect_hdr -> getSectionData ( ) ; else bss_section = IRBuilder :: CreateSectionData ( * bss_sect_hdr ) ; uint32_t addralign = config ( ) . targets ( ) . bitclass ( ) / <NUM_LIT> ; Fragment * frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , pSym . size ( ) ) ; uint64_t size = ObjectBuilder :: AppendFragment ( * frag , * bss_section , addralign ) ; bss_sect_hdr -> setSize ( bss_sect_hdr -> size ( ) + size ) ; ResolveInfo :: Binding binding = ( ResolveInfo :: Binding ) pSym . binding ( ) ; if ( binding == ResolveInfo :: Weak ) binding = ResolveInfo :: Global ;

LDSymbol * cpy_sym = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Resolve > ( pSym . name ( ) , ( ResolveInfo :: Type ) pSym . type ( ) , ResolveInfo :: Define , binding , pSym . size ( ) , <NUM_LIT> , FragmentRef :: Create ( * frag , <NUM_LIT> ) , ( ResolveInfo :: Visibility ) pSym . other ( ) ) ;


<s> case KindTy :: Imm : OS << <STR_LIT> << Imm ; break ; case KindTy :: MemOp : MemOp . print ( OS ) ;


<s> CCInfo . AllocateReg ( ImplicitBufferPtrReg ) ; } unsigned NumArgs = F . arg_size ( ) ; Function :: const_arg_iterator CurOrigArg = F . arg_begin ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; unsigned P<ISA_LIT>nputNum = <NUM_LIT> ; BitVector Skipped ( NumArgs ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i , ++ CurOrigArg ) { EVT ValEVT = TLI . getValueType ( DL , CurOrigArg -> getType ( ) ) ; <STR_LIT> Flags ; assert ( VRegs [ i ] . size ( ) == <NUM_LIT> && <STR_LIT> ) ; ArgInfo OrigArg { VRegs [ i ] [ <NUM_LIT> ] , CurOrigArg -> getType ( ) } ; setArgFlags ( OrigArg , i + <NUM_LIT> , DL , F ) ; Flags . setOrigAlign ( DL . getABITypeAlignment ( CurOrigArg -> getType ( ) ) ) ; if ( F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS && ! OrigArg . Flags . isInReg ( ) && ! OrigArg . Flags . isByVal ( ) && P<ISA_LIT>nputNum <= <NUM_LIT> ) { if ( CurOrigArg -> use_empty ( ) && ! Info -> isP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ) { Skipped . set ( i ) ; ++ P<ISA_LIT>nputNum ; continue ; } Info -> markP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( ! CurOrigArg -> use_empty ( ) ) Info -> markP<ISA_LIT>nputEnabled ( P<ISA_LIT>nputNum ) ; ++ P<ISA_LIT>nputNum ; } CCAssignFn * AssignFn = CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; if ( ValEVT . isVector ( ) ) { EVT ElemVT = ValEVT . getVectorElementType ( ) ; if ( ! ValEVT . isSimple ( ) ) return false ; MVT ValVT = ElemVT . getSimpleVT ( ) ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , OrigArg . Flags , CCInfo ) ; if ( ! Res ) return false ; } else { MVT ValVT = ValEVT . getSimpleVT ( ) ; if ( ! ValEVT . isSimple ( ) ) return false ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , OrigArg . Flags , CCInfo ) ; if ( Res ) return false ; } } Function :: const_arg_iterator Arg = F . arg_begin ( ) ;

if ( F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_VS || F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS ) {


__builtin_ia32_pmovusqw256mem_mask ( ( unsigned long long * ) __P , ( __v4di ) __A , __M ) ;


<s> if ( rs < <NUM_LIT> ) rs = <NUM_LIT> ;

return ( ( GET_MODE_SIZE ( mode ) + rs - <NUM_LIT> ) / rs ) ;


<s> } } } if ( ST . hasSwap ( ) && ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ) { if ( auto * NextMI = matchSwap ( MI , MRI , TII ) ) { Next = NextMI -> getIterator ( ) ; continue ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { const MachineOperand * Dest = & MI . getOperand ( <NUM_LIT> ) ; MachineOperand * Src0 = & MI . getOperand ( <NUM_LIT> ) ; MachineOperand * Src1 = & MI . getOperand ( <NUM_LIT> ) ; if ( ! Src0 -> isReg ( ) && Src1 -> isReg ( ) ) { if ( TII -> commuteInstruction ( MI , false , <NUM_LIT> , <NUM_LIT> ) ) std :: swap ( Src0 , Src1 ) ; } if ( Dest -> getReg ( ) . isVirtual ( ) && Src0 -> isReg ( ) ) { MRI . setRegAllocationHint ( Dest -> getReg ( ) , <NUM_LIT> , Src0 -> getReg ( ) ) ; MRI . setRegAllocationHint ( Src0 -> getReg ( ) , <NUM_LIT> , Dest -> getReg ( ) ) ; continue ; } if ( Src0 -> isReg ( ) && Src0 -> getReg ( ) == Dest -> getReg ( ) ) { if ( Src1 -> isImm ( ) && isKImmOperand ( TII , * Src1 ) ) { unsigned Opc = ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII -> get ( Opc ) ) ; MI . tieOperands ( <NUM_LIT> , <NUM_LIT> ) ; } } } if ( MI . isCompare ( ) && TII -> isSOPC ( MI ) ) { shrinkScalarCompare ( TII , MI ) ; continue ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( Src . isImm ( ) && Dst . getReg ( ) . isPhysical ( ) ) { int32_t ReverseImm ; if ( isKImmOperand ( TII , Src ) ) MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; else if ( isReverseInlineImm ( TII , Src , ReverseImm ) ) { MI . setDesc ( TII -> get ( <STR_LIT> ) ) ;


<s> static __inline qword si_mpyhhu ( qword a , qword b ) { return ( ( qword ) ( vec_mule ( ( vec_ushort8 ) ( a ) , ( vec_ushort8 ) ( b ) ) ) ) ;


<s> return isRegisterType ( Ty ) && isLoadStoreSizeLegal ( ST , Query , Opcode ) && ! loadStoreBitcastWorkaround ( Ty ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) {


<s> <ISA_LIT>AsmBackend ( const Target & T ) : MCAsmBackend ( ) {


<s> void <ISA_LIT>CallFrameOptimization :: collectCallInfo ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , CallContext & Context ) { const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( STI -> getRegisterInfo ( ) ) ; assert ( I -> getOpcode ( ) == TII -> getCallFrameSetupOpcode ( ) ) ; MachineBasicBlock :: iterator FrameSetup = I ++ ; Context . FrameSetup = FrameSetup ; unsigned int MaxAdjust = TII -> getFrameSize ( * FrameSetup ) >> Log2SlotSize ; if ( ! MaxAdjust ) { Context . NoStackParams = true ; return ; } while ( I -> getOpcode ( ) == <STR_LIT> || I -> isDebugInstr ( ) ) ++ I ; Register StackPtr = RegInfo . getStackRegister ( ) ; auto StackPtrCopyInst = MBB . end ( ) ; for ( auto J = I ; ! J -> isCall ( ) ; ++ J ) if ( J -> isCopy ( ) && J -> getOperand ( <NUM_LIT> ) . isReg ( ) && J -> getOperand ( <NUM_LIT> ) . isReg ( ) && J -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { StackPtrCopyInst = J ; Context . SPCopy = & * J ++ ; StackPtr = Context . SPCopy -> getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } if ( MaxAdjust > <NUM_LIT> ) Context . ArgStoreVector . resize ( MaxAdjust , nullptr ) ; DenseSet < unsigned int > UsedRegs ; for ( InstClassification Classification = Skip ; Classification != Exit ; ++ I ) { if ( I == StackPtrCopyInst ) continue ; Classification = classifyInstruction ( MBB , I , RegInfo , UsedRegs ) ; if ( Classification != Convert ) continue ; if ( ! I -> getOperand ( <STR_LIT> ) . isReg ( ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != StackPtr ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) || ( I -> getOperand ( <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ( I -> getOperand ( <STR_LIT> ) . getReg ( ) != <STR_LIT> ) || ! I -> getOperand ( <STR_LIT> ) . isImm ( ) ) return ; int64_t StackDisp = I -> getOperand ( <STR_LIT> ) . getImm ( ) ;

assert ( StackDisp >= <NUM_LIT> && <STR_LIT> ) ;


<s> static void nvptx_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & ) {

CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;


<s> if ( ! isFLAT ( MI ) ) return false ;

if ( MI . memoperands_empty ( ) ) return true ;


<s> } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Alignment >= <NUM_LIT> ) Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; else Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; } ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addFullAddress ( MIB , AM ) ; if ( MMO ) MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ;


<s> else func_addr = func ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = gen_rtx_USE ( VOIDmode , cookie ) ; n = <NUM_LIT> ; if ( TARGET_SECURE_PLT && flag_pic && GET_CODE ( func_addr ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( func_addr ) ) call [ n ++ ] = gen_rtx_USE ( VOIDmode , pic_offset_table_rtx ) ; call [ n ++ ] = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ;

insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( n , call ) ) ;


<s> bool hasReservedCallFrame ( const MachineFunction & MF ) const { return true ;


<s> unsigned CCValid = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > Selects ; SmallVector < MachineInstr * , <NUM_LIT> > DbgValues ; Selects . push_back ( & MI ) ; unsigned Count = <NUM_LIT> ; for ( MachineBasicBlock :: iterator NextMIIt = std :: next ( MachineBasicBlock :: iterator ( MI ) ) ; NextMIIt != MBB -> end ( ) ; ++ NextMIIt ) { if ( isSelectPseudo ( * NextMIIt ) ) { assert ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CCValid && <STR_LIT> ) ; if ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CCMask || NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) { Selects . push_back ( & * NextMIIt ) ; continue ; } break ; } if ( NextMIIt -> definesRegister ( <STR_LIT> ) || NextMIIt -> usesCustomInsertionHook ( ) ) break ; bool User = false ; for ( auto SelMI : Selects ) if ( NextMIIt -> readsVirtualRegister ( SelMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { User = true ; break ; } if ( NextMIIt -> isDebugInstr ( ) ) { if ( User ) { assert ( NextMIIt -> isDebugValue ( ) && <STR_LIT> ) ; DbgValues . push_back ( & * NextMIIt ) ; } } else if ( User || ++ Count > <NUM_LIT> ) break ; }

MachineInstr * LastMI = Selects . back ( ) ;


<s> std :: string Ret ; Ret += <STR_LIT> ; return Ret ;


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; return <NUM_LIT> ;


<s> SDValue Chain = Alloc . getValue ( <NUM_LIT> ) ; EVT DupVTs [ ] = { Alloc . getValueType ( ) , <STR_LIT> } ; SDValue DupOps [ ] = { Chain , Alloc } ; SDValue Dup = DAG . getNode ( <STR_LIT> , dl , DupVTs , DupOps ) ; Chain = Dup . getValue ( <NUM_LIT> ) ;

std :: string MethodDescStr = MFI -> getFromTypeNameMap ( AllocatedTy ) ;


<s> } Type * PtrTy = VecTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { VecTy , PtrTy } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * LdNFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ; for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) { if ( LoadCount > <NUM_LIT> ) BaseAddr = Builder . CreateConstGEP1_32 ( BaseAddr , VecTy -> getVectorNumElements ( ) * Factor ) ; CallInst * LdN = Builder . CreateCall ( LdNFunc , Builder . CreateBitCast ( BaseAddr , PtrTy ) , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Shuffles . size ( ) ; i ++ ) { ShuffleVectorInst * SVI = Shuffles [ i ] ; unsigned Index = Indices [ i ] ; Value * SubVec = Builder . CreateExtractValue ( LdN , Index ) ;

if ( EltTy -> isPointerTy ( ) ) SubVec = Builder . CreateIntToPtr ( SubVec , VectorType :: get ( SVI -> getType ( ) -> getVectorElementType ( ) , VecTy -> getVectorNumElements ( ) ) ) ;


<s> <ISA_LIT>SPClone ( ) : ModulePass ( ID ) {


<s> MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; } } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } unsigned RetOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( RetOpc ) ) ; AddOptionalDefs ( MIB ) ; for ( unsigned R : RetRegs ) MIB . addReg ( R , RegState :: Implicit ) ; return true ;


<s> if ( ! Uses . count ( MO . getReg ( ) ) ) continue ;


<s> continue ; } SDValue Val = DAG . getCopyFromReg ( Chain , DL , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ;


<s> if ( IdSymbolic [ Id ] && Name == IdSymbolic [ Id ] ) return Id ; } return ID_UNKNOWN_ ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimm2 ( SDValue N , SDValue & Imm ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ! first ) eatComma ( ) ; first = false ; auto MatchResult = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( MatchResult == MatchOperand_Success ) { continue ; } if ( MatchResult == MatchOperand_ParseFail ) {


<s> if ( ! <ISA_LIT>SelectAddress ( LI -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; const <ISA_LIT>InstrInfo & XII = ( const <ISA_LIT>InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ;

MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : GlobalBaseReg ( ) , VarArgsFrameOffset ( <NUM_LIT> ) , IsLeafProc ( false ) {


<s> bool <ISA_LIT>DAGToDAGISel :: usePrecSqrtF32 ( ) const { if ( UsePrecSqrtF32 . getNumOccurrences ( ) > <NUM_LIT> ) { return UsePrecSqrtF32 ; } else { if ( TM . Options . UnsafeFPMath ) return false ; else return true ;


<s> rtx_insn * insn ; if ( offset == <NUM_LIT> ) return ; if ( offset < - <NUM_LIT> || offset > <NUM_LIT> ) { rtx reg = gen_rtx_REG ( SImode , REG_A0 ) ; rtx low = GEN_INT ( trunc_int_for_mode ( offset , HImode ) ) ; insn = emit_insn ( gen_movsi_high ( reg , low ) ) ; if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_movsi_lo_sum ( reg , reg , to_add ) ) ;


<s> unsigned ArgOffset = <ISA_LIT>FrameInfo :: minStackSize ( ) ; unsigned ArgRegIdx = <NUM_LIT> ; std :: vector < std :: pair < unsigned , SDValue > > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( ; ArgRegIdx != NumOps ; ++ ArgRegIdx ) { SDValue Arg = OutVals [ ArgRegIdx ] ; CCValAssign & VA = ArgLocs [ ArgRegIdx ] ; SDValue PtrOff = DAG . getConstant ( ArgOffset , StackPtr . getValueType ( ) ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , PtrOff ) ; switch ( Arg . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ArgRegIdx != NumArgRegs ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; ArgOffset += StackSlotSize ; } break ; } } unsigned NumStackBytes = ArgOffset - <ISA_LIT>FrameInfo :: minStackSize ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumStackBytes , true ) ) ; if ( ! MemOpChains . empty ( ) ) { Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; } SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned CallOpc = <STR_LIT> ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; EVT CalleeVT = Callee . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , CalleeVT ) ; if ( ! ST -> usingLargeMem ( ) ) { if ( GV -> isDeclaration ( ) ) { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , GA , Zero ) ; } else { Callee = DAG . getNode ( <STR_LIT> , dl , CalleeVT , GA , Zero ) ; } } else { Callee = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; }

} else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) {


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res ;


<s> } SDValue Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ) ; } MVT EltVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ( <NUM_LIT> / NumElts ) ; MVT ExtVT = <STR_LIT> ( EltVT , NumElts ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , In ) ; InVT = ExtVT ; ShiftInx = InVT . getScalarSizeInBits ( ) - <NUM_LIT> ; } if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) {

In = DAG . getNode ( <STR_LIT> , DL , InVT , In , DAG . getConstant ( ShiftInx , DL , InVT ) ) ;


<s> emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , HImode , <NUM_LIT> ) ; emit_move_insn ( mem , GEN_INT ( <NUM_LIT> ) ) ; emit_move_insn ( mem , fnaddr ) ;


<s> void findRedundantStores ( void ) { std :: map < MachineInstr * , std :: pair < BitVector , BitVector > > collected_stores ; std :: queue < MachineBasicBlock * > worklist ; for ( po_iterator < MachineBasicBlock * > POI = po_begin ( & MF . front ( ) ) , POIe = po_end ( & MF . front ( ) ) ; POI != POIe ; ++ POI ) { worklist . push ( * POI ) ; } while ( ! worklist . empty ( ) ) { MachineBasicBlock * MBB = worklist . front ( ) ; worklist . pop ( ) ; Blockinfo & BI = this -> BlockInfos . at ( MBB ) ; BitVector subseqstores ( NumFIs , true ) ; BitVector futureloads ( NumFIs ) ; if ( MBB -> succ_size ( ) > <NUM_LIT> ) { for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) ; SI != MBB -> succ_end ( ) ; ++ SI ) { Blockinfo & BISucc = this -> BlockInfos . at ( * SI ) ; futureloads |= BISucc . FutureLoadsEntry ; subseqstores &= BISucc . SubseqStoresEntry ;


<s> const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return <NUM_LIT> ;


<s> } MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDValue NewValue = convertToScalableVector ( ContainerVT , StoreVal , DAG , Subtarget ) ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , { Store -> getChain ( ) , NewValue , Store -> getBasePtr ( ) , VL } , Store -> getMemoryVT ( ) , Store -> getMemOperand ( ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>BranchExpansion ( ) {

return new <ISA_LIT>BranchExpansion ( ) ;


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_<ISA_LIT> , true ) {


<s> InsertionPointsPerFunc InsertPtsPerFunc ;

computeInsertionPoints ( Val , InsertPtsPerFunc ) ;


<s> bool IsDefined = false ; for ( auto & MO : OrigMI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; assert ( ( MO . isDef ( ) || MO . isUse ( ) ) && <STR_LIT> ) ; for ( MCSuperRegIterator Supers ( OrigDestReg , TRI , true ) ; Supers . isValid ( ) ; ++ Supers ) { if ( * Supers == MO . getReg ( ) ) { if ( MO . isDef ( ) ) IsDefined = true ; else return false ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( StackDirection D , Align StackAl , int LAO , unsigned TransAl ) : TargetFrameLowering ( D , StackAl , LAO , TransAl ) {


<s> if ( NumElts % Factor == <NUM_LIT> && TLI -> isLegalInterleavedAccessType ( Factor , SubVecTy , DL ) ) return Factor * BaseCost * TLI -> getNumInterleavedAccesses ( SubVecTy , DL ) ; if ( ST -> hasMVEIntegerOps ( ) && Factor == <NUM_LIT> && NumElts / Factor > <NUM_LIT> && VecTy -> isIntOrIntVectorTy ( ) && DL . getTypeSizeInBits ( SubVecTy ) <= <NUM_LIT> ) return <NUM_LIT> * BaseCost ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue ( ) ) ) ;


<s> static rtx_insn * vax_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < machine_mode > & input_modes ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , VAX_PSL_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , VAX_PSL_REGNUM ) ; return NULL ;


<s> return __builtin_neon_vdup_lanev4hf ( __a , __b ) ;


<s> zero = SET_SRC ( elt ) ; if ( ! REG_P ( reg ) || GET_MODE ( reg ) != expected_mode || zero != CONST0_RTX ( SImode ) ) return false ; regno = REGNO ( reg ) ; if ( vfp ) { if ( i != first_set && regno != last_regno + <NUM_LIT> ) return false ; } else { if ( regno == SP_REGNUM || regno == PC_REGNUM ) return false ;

if ( i != first_set && regno <= last_regno ) return false ;


<s> const uint32_t Encoded_s_code_end = <NUM_LIT> ; MCStreamer & OS = getStreamer ( ) ; OS . PushSection ( ) ; OS . emitValueToAlignment ( <NUM_LIT> , Encoded_s_code_end , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) OS . emitInt32 ( Encoded_s_code_end ) ; OS . PopSection ( ) ; return true ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>64Target ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const {


<s> static int need_to_save ( int regno ) { if ( fixed_regs [ regno ] ) return <NUM_LIT> ; if ( crtl -> calls_eh_return ) return <NUM_LIT> ; if ( regno == FP_REGNO ) return <NUM_LIT> ;

if ( cfun -> machine -> is_interrupt && ( ! cfun -> machine -> is_leaf || ( regno == A0_REGNO && m32c_function_needs_enter ( ) ) ) ) return <NUM_LIT> ;


<s> rtx msp430_function_arg ( cumulative_args_t cap , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( cap ) ; msp430_evaluate_arg ( cap , mode , type , named ) ;

if ( ca -> reg_count ) return gen_rtx_REG ( mode , ca -> start_reg ) ;


<s> builder . quick_push ( base + i ) ; builder . quick_push ( base + i + nelts ) ; }


<s> void createdInstr ( MachineInstr & MI ) override {


<s> if ( a < b ) return ( struct quot_rem ) { <NUM_LIT> , a } ; if ( b <= a ) { quot_digits = LZ ( b ) - LZ ( a ) ; quot_digits += ( a >= ( b << quot_digits ) ) ; b <<= quot_digits ; } while ( b <= a ) { b <<= <NUM_LIT> ; quot_digits ++ ; } if ( a & <NUM_LIT> ) { b >>= <NUM_LIT> ; if ( a >= b ) { a -= b ; extra = <NUM_LIT> << ( quot_digits - <NUM_LIT> ) ; } else { a -= b >> <NUM_LIT> ; extra = <NUM_LIT> << quot_digits ; } quot_digits -- ; } b -- ; switch ( quot_digits ) { case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : DS ; case <NUM_LIT> : ; } { struct quot_rem ret ; ret . quot = ( a & ( ( <NUM_LIT> << quot_digits ) - <NUM_LIT> ) ) + extra ; ret . rem = a >> quot_digits ; return ret ;


<s> bool MVEVPTBlock :: InsertVPTBlocks ( MachineBasicBlock & Block ) { bool Modified = false ; MachineBasicBlock :: instr_iterator MBIter = Block . instr_begin ( ) ; MachineBasicBlock :: instr_iterator EndIter = Block . instr_end ( ) ; while ( MBIter != EndIter ) { MachineInstr * MI = & * MBIter ; unsigned PredReg = <NUM_LIT> ; DebugLoc dl = MI -> getDebugLoc ( ) ; <STR_LIT> Pred = getVPTInstrPredicate ( * MI , PredReg ) ; assert ( Pred != <STR_LIT> && <STR_LIT> ) ; if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI -> dump ( ) ) ; int VPTInstCnt = <NUM_LIT> ; <STR_LIT> NextPred ; ++ MBIter ; while ( MBIter != EndIter && VPTInstCnt < <NUM_LIT> ) { NextPred = getVPTInstrPredicate ( * MBIter , PredReg ) ; assert ( NextPred != <STR_LIT> && <STR_LIT> ) ; if ( NextPred != Pred ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MBIter -> dump ( ) ) ; ++ VPTInstCnt ; ++ MBIter ; } ; unsigned BlockMask = <NUM_LIT> ; switch ( VPTInstCnt ) { case <NUM_LIT> : BlockMask = VPTMaskValue :: T ; break ; case <NUM_LIT> : BlockMask = VPTMaskValue :: TT ; break ; case <NUM_LIT> : BlockMask = VPTMaskValue :: TTT ; break ; case <NUM_LIT> : BlockMask = VPTMaskValue :: TTTT ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI , TRI , NewOpcode ) ; if ( VCMP ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; VCMP -> dump ( ) ) ; MIBuilder = BuildMI ( Block , MI , dl , TII -> get ( NewOpcode ) ) ; MIBuilder . addImm ( BlockMask ) ;

MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ;


<s> int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { int byte = ( op1 >> ( <NUM_LIT> * ( <NUM_LIT> - i ) ) ) & <NUM_LIT> ; if ( byte ) { emit_set_insn ( op0 , mov_done_p ? gen_rtx_PLUS ( SImode , op0 , GEN_INT ( byte ) ) : GEN_INT ( byte ) ) ; mov_done_p = true ; } if ( mov_done_p ) emit_set_insn ( op0 , gen_rtx_ASHIFT ( SImode , op0 , GEN_INT ( <NUM_LIT> ) ) ) ; } if ( ! mov_done_p ) emit_set_insn ( op0 , GEN_INT ( op1 & <NUM_LIT> ) ) ;


<s> static inline uint8_t encodeAdvSIMDModImmType9 ( uint64_t Imm ) {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFScratchOffset ( SDNode * Root , SDValue Addr , SDValue & SRsrc , SDValue & SOffset , SDValue & Offset ) const { ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ; if ( ! CAddr || ! isLegalMUBUFImmOffset ( CAddr ) ) return false ; SDLoc DL ( Addr ) ;

MachineFunction & MF = CurDAG -> getMachineFunction ( ) ;


<s> EVT VT = Op . getValueType ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; MVT IntVT = <STR_LIT> ; MVT FltVT = <STR_LIT> ; unsigned LHSSignBits = DAG . ComputeNumSignBits ( LHS ) ; if ( LHSSignBits < <NUM_LIT> ) return SDValue ( ) ; unsigned RHSSignBits = DAG . ComputeNumSignBits ( RHS ) ; if ( RHSSignBits < <NUM_LIT> ) return SDValue ( ) ; unsigned BitSize = VT . getSizeInBits ( ) ; unsigned SignBits = std :: min ( LHSSignBits , RHSSignBits ) ; unsigned DivBits = BitSize - SignBits ; if ( Sign ) ++ DivBits ; <STR_LIT> ToFp = Sign ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ToInt = Sign ? <STR_LIT> : <STR_LIT> ; SDValue jq = DAG . getConstant ( <NUM_LIT> , DL , IntVT ) ; if ( Sign ) { jq = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( BitSize - <NUM_LIT> , DL , VT ) ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } SDValue ia = LHS ; SDValue ib = RHS ; SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; unsigned OpCode = MFI -> getMode ( ) . allFP32Denormals ( ) ? ( unsigned ) <STR_LIT> : ( unsigned ) <STR_LIT> ; SDValue fr = DAG . getNode ( OpCode , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ;

fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ;


<s> MachineLocation <ISA_LIT>AsmPrinter :: getDebugValueLocation ( const MachineInstr * MI ) const { MachineLocation Location ; assert ( MI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Location . set ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; else { DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; }


<s> int maximum_bytes ; if ( TARGET_REDUCED_REGS ) maximum_bytes = <NUM_LIT> ; else maximum_bytes = <NUM_LIT> ; if ( GET_CODE ( total_bytes ) != CONST_INT || GET_CODE ( alignment ) != CONST_INT || INTVAL ( total_bytes ) > maximum_bytes || INTVAL ( total_bytes ) & <NUM_LIT> || INTVAL ( alignment ) & <NUM_LIT> ) return <NUM_LIT> ; dst_base_reg = copy_to_mode_reg ( SImode , XEXP ( dstmem , <NUM_LIT> ) ) ; src_base_reg = copy_to_mode_reg ( SImode , XEXP ( srcmem , <NUM_LIT> ) ) ;


<s> if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; } else { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CondCode , CondCode2 ) ; if ( CondCode2 != <STR_LIT> ) return false ; if ( ! emitFPCompare ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg1 , MRI , TRI ) ;

auto ValAndVReg = getConstantVRegValWithLookThrough ( SrcReg2 , MRI ) ;


<s> static rtx m68hc11_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , HARD_D_REGNUM ) ;


<s> if ( flag_pic ) sprintf ( buf , <STR_LIT> , fname ) ; else sprintf ( buf , <STR_LIT> , fname ) ; }


<s> switch ( op ) { case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( mode1 ) ; default :


<s> if ( attr_length_indirect_call ( insn ) == <NUM_LIT> ) return <STR_LIT> ; xoperands [ <NUM_LIT> ] = NULL_RTX ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( TARGET_SOM || ! TARGET_GAS ) { xoperands [ <NUM_LIT> ] = gen_label_rtx ( ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( xoperands [ <NUM_LIT> ] ) ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ;


<s> auto SignBit64 = B . buildMerge ( S64 , { Zero32 , SignBit } ) ; auto Shr = B . buildAShr ( S64 , FractMask , Exp ) ; auto Not = B . buildNot ( S64 , Shr ) ; auto Tmp0 = B . buildAnd ( S64 , Src , Not ) ; auto FiftyOne = B . buildConstant ( S32 , FractBits - <NUM_LIT> ) ; auto ExpLt0 = B . buildICmp ( CmpInst :: ICMP_SLT , S1 , Exp , Zero32 ) ; auto ExpGt51 = B . buildICmp ( CmpInst :: ICMP_SGT , S1 , Exp , FiftyOne ) ; auto Tmp1 = B . buildSelect ( S64 , ExpLt0 , SignBit64 , Tmp0 ) ;

B . buildSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ExpGt51 , Src , Tmp1 ) ;


<s> public : <ISA_LIT>MCInstLower ( <ISA_LIT>AsmPrinter & asmPrinter ) ; void lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand lowerOperand ( const MachineOperand & MO ) const ;


<s> unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegLst == <NUM_LIT> ) return MCDisassembler :: Fail ; RegNum = RegLst & <NUM_LIT> ; if ( RegNum > <NUM_LIT> ) return MCDisassembler :: Fail ;

for ( unsigned i = <NUM_LIT> ; i < RegNum ; i ++ ) Inst . addOperand ( MCOperand :: createReg ( Regs [ i ] ) ) ;


<s> fprintf ( stderr , <STR_LIT> , subtree -> str ) ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> return llvm :: make_unique < <ISA_LIT>WinCOFFObjectWriter > ( Is64Bit ) ;


<s> } else if ( RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; } else if ( RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( JumpTarget . getImm ( ) ) ; } else if ( RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ;


<s> else if ( Inst -> isFullCopy ( ) ) NextReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( NextReg == SrcReg || ! Register :: isVirtualRegister ( NextReg ) ) break ; SrcReg = NextReg ; }


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ;

const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;


<s> AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ;

FunctionPass :: getAnalysisUsage ( AU ) ;


<s> bool IsFMA3 = ( ( TSFlags & <STR_LIT> ) == <STR_LIT> || ( TSFlags & <STR_LIT> ) == <STR_LIT> ) && ( TSFlags & <STR_LIT> ) == <STR_LIT> && ( TSFlags & <STR_LIT> ) == <STR_LIT> && ( ( BaseOpcode >= <NUM_LIT> && BaseOpcode <= <NUM_LIT> ) || ( BaseOpcode >= <NUM_LIT> && BaseOpcode <= <NUM_LIT> ) || ( BaseOpcode >= <NUM_LIT> && BaseOpcode <= <NUM_LIT> ) ) ; if ( ! IsFMA3 ) return nullptr ; verifyTables ( ) ; ArrayRef < <ISA_LIT>InstrFMA3Group > Table ; if ( TSFlags & <STR_LIT> ) Table = makeArrayRef ( RoundGroups ) ; else if ( TSFlags & <STR_LIT> ) Table = makeArrayRef ( BroadcastGroups ) ; else Table = makeArrayRef ( Groups ) ; unsigned FormIndex = ( ( BaseOpcode - <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; auto I = llvm :: bsearch ( Table , [ = ] ( const <ISA_LIT>InstrFMA3Group & Group ) { return Opcode <= Group . Opcodes [ FormIndex ] ; } ) ; assert ( I != Table . end ( ) && I -> Opcodes [ FormIndex ] == Opcode && <STR_LIT> ) ;


<s> static const int16_t Sub0_2 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const int16_t Sub0_1 [ ] = { <STR_LIT> , <STR_LIT> , } ; switch ( <STR_LIT> ( * RC -> MC ) ) { case <NUM_LIT> : return { } ; case <NUM_LIT> : return makeArrayRef ( Sub0_1 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_2 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_3 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_4 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_7 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_31 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( EltSize == <NUM_LIT> ) { static const int16_t Sub0_31_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_15_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_7_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_3_64 [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( <STR_LIT> ( * RC -> MC ) ) { case <NUM_LIT> : return { } ; case <NUM_LIT> : return makeArrayRef ( Sub0_3_64 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_7_64 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15_64 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_31_64 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( EltSize == <NUM_LIT> ) { static const int16_t Sub0_31_128 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_15_128 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const int16_t Sub0_7_128 [ ] = { <STR_LIT> , <STR_LIT> } ; switch ( <STR_LIT> ( * RC -> MC ) ) { case <NUM_LIT> : return { } ; case <NUM_LIT> : return makeArrayRef ( Sub0_7_128 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_15_128 ) ; case <NUM_LIT> : return makeArrayRef ( Sub0_31_128 ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } assert ( EltSize == <NUM_LIT> && <STR_LIT> ) ; static const int16_t Sub0_31_256 [ ] = {


<s> if ( ! IsTailPredicationLegal ( ) ) return IsDo ? <STR_LIT> : <STR_LIT> ;

return VCTPOpcodeToLSTP ( VCTPs . back ( ) -> getOpcode ( ) , IsDo ) ;


<s> bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ;


<s> level2 -> line = ecx & <NUM_LIT> ; assoc = ( ecx >> <NUM_LIT> ) & <NUM_LIT> ; if ( assoc == <NUM_LIT> ) assoc = <NUM_LIT> ; else if ( assoc == <NUM_LIT> ) assoc = <NUM_LIT> ;

else if ( assoc >= <NUM_LIT> && assoc <= <NUM_LIT> ) assoc = <NUM_LIT> + ( assoc - <NUM_LIT> ) * <NUM_LIT> ;


<s> static rtx_insn * emit_nop_after ( int cycles , rtx_insn * after ) { rtx_insn * insn ; if ( cycles == <NUM_LIT> ) cycles -- ;


<s> GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const { SmallString < <NUM_LIT> > Name ;

raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


<s> if ( ! matchMed < ICstRegMatch > ( MI , MRI , OpcodeTriple , Val , K0 , K1 ) ) return false ; const APInt & K0_Imm = getConstantIntVRegVal ( K0 , MRI ) -> getValue ( ) ; const APInt & K1_Imm = getConstantIntVRegVal ( K1 , MRI ) -> getValue ( ) ; if ( OpcodeTriple . Med == <STR_LIT> && K0_Imm . sgt ( K1_Imm ) ) return false ; if ( OpcodeTriple . Med == <STR_LIT> && K0_Imm . ugt ( K1_Imm ) ) return false ; MatchInfo = { OpcodeTriple . Med , Val , K0 , K1 } ; return true ;


<s> std :: pair < MachineBasicBlock * , MachineBasicBlock * > <ISA_LIT>LowerControlFlow :: splitBlock ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * LoopBB = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF -> CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ;


<s> RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HA ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , PB , Ctx ) ; } switch ( access ) { case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: createLo ( Expr , isDarwin , Ctx ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: createHa ( Expr , isDarwin , Ctx ) ; break ;


<s> uint64_t encoding = <STR_LIT> ( Val , sizeof ( T ) * <NUM_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( encoding ) ) ;


<s> else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ;


<s> return & getParentInst ( ) -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ;

case MachineOperand :: MO_GlobalAddress :


<s> Def -> setDesc ( TII . get ( GT_S_I32 ) ) ; Inverted = true ; break ; case GT_U_I32 : Def -> setDesc ( TII . get ( LE_U_I32 ) ) ; Inverted = true ; break ; case GE_U_I32 : Def -> setDesc ( TII . get ( LT_U_I32 ) ) ; Inverted = true ; break ; case LT_U_I32 : Def -> setDesc ( TII . get ( GE_U_I32 ) ) ; Inverted = true ; break ; case LE_U_I32 : Def -> setDesc ( TII . get ( GT_U_I32 ) ) ; Inverted = true ; break ; case EQ_I64 : Def -> setDesc ( TII . get ( NE_I64 ) ) ; Inverted = true ; break ; case NE_I64 : Def -> setDesc ( TII . get ( EQ_I64 ) ) ; Inverted = true ; break ; case GT_S_I64 : Def -> setDesc ( TII . get ( LE_S_I64 ) ) ; Inverted = true ; break ; case GE_S_I64 : Def -> setDesc ( TII . get ( LT_S_I64 ) ) ; Inverted = true ; break ; case LT_S_I64 : Def -> setDesc ( TII . get ( GE_S_I64 ) ) ; Inverted = true ; break ; case LE_S_I64 : Def -> setDesc ( TII . get ( GT_S_I64 ) ) ; Inverted = true ; break ; case GT_U_I64 : Def -> setDesc ( TII . get ( LE_U_I64 ) ) ; Inverted = true ; break ; case GE_U_I64 : Def -> setDesc ( TII . get ( LT_U_I64 ) ) ; Inverted = true ; break ; case LT_U_I64 : Def -> setDesc ( TII . get ( GE_U_I64 ) ) ; Inverted = true ; break ; case LE_U_I64 : Def -> setDesc ( TII . get ( GT_U_I64 ) ) ; Inverted = true ; break ; case EQ_F32 : Def -> setDesc ( TII . get ( NE_F32 ) ) ; Inverted = true ; break ; case NE_F32 :

Def -> setDesc ( TII . get ( EQ_F32 ) ) ;


<s> if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ;


<s> SDLoc DL ( Op ) ; if ( Op . getValueType ( ) != <STR_LIT> || S0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , S0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue FloatLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , S0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue FloatHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; FloatHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FloatHi , DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FloatLo , FloatHi ) ;


<s> if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; }


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; if ( MBB -> pred_empty ( ) || ( isBlockOnlyReachableByFallthrough ( & * MBB ) && ! ( MBB -> isEHFuncletEntry ( ) ) ) ) { MachineInstr * MI_subi = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> return ( __m128d ) __builtin_ia32_loadsd_mask ( __P , ( __v2df ) _mm_setzero_pd ( ) , __U ) ;


<s> MIB -> addOperand ( TailCall . getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; MIB -> addOperand ( BranchCond [ <NUM_LIT> ] ) ; MIB . copyImplicitOps ( TailCall ) ; LivePhysRegs LiveRegs ( getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; LiveRegs . stepForward ( * MIB , Clobbers ) ; for ( const auto & C : Clobbers ) { MIB . addReg ( C . first , RegState :: Implicit ) ; MIB . addReg ( C . first , RegState :: Implicit | RegState :: Define ) ;


<s> <ISA_LIT>Section * & Entry = SectionsByName [ Name ] ; if ( Entry ) return Entry ; Entry = <ISA_LIT>Section :: Create ( Name , Ty , Address , Color , getContext ( ) ) ; switch ( Ty ) { default : llvm_unreachable ( <STR_LIT> ) ; case UDATA : UDATASections_ . push_back ( Entry ) ; break ; case IDATA : IDATASections_ . push_back ( Entry ) ; break ; case ROMDATA : ROMDATASection_ = Entry ; break ; case UDATA_SHR : SHAREDUDATASection_ = Entry ; break ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = CE -> getValue ( ) ; Value = <STR_LIT> ( Value ) ;

Inst . addOperand ( MCOperand :: createImm ( Value ) ) ;


<s> SDLoc DL ( Addr ) ; if ( canBeRepresentedAsSls ( * CN ) ) { int32_t Imm = CN -> getSExtValue ( ) ; Offset = CurDAG -> getTargetConstant ( Imm , DL , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; }


<s> forwardITPosition ( ) ; forwardVPTPosition ( ) ; return true ; } { while ( processInstruction ( Inst , Operands , Out ) ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump_pretty ( dbgs ( ) , MII . getName ( Inst . getOpcode ( ) ) ) ; dbgs ( ) << <STR_LIT> ) ; } forwardITPosition ( ) ; forwardVPTPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; if ( PendConditionalInstruction ) { PendingConditionalInsts . push_back ( Inst ) ;

if ( isITBlockFull ( ) || isITBlockTerminator ( Inst ) ) flushPendingInstructions ( Out ) ;


<s> const DataLayout * TD = TM . getDataLayout ( ) ; int Bytes ; if ( isa < ConstantArray > ( CPV ) || isa < ConstantVector > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( const ConstantDataSequential * CDS = dyn_cast < ConstantDataSequential > ( CPV ) ) { if ( CDS -> getNumElements ( ) ) for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) bufferLEByte ( cast < Constant > ( CDS -> getElementAsConstant ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( isa < ConstantStruct > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) { StructType * ST = cast < StructType > ( CPV -> getType ( ) ) ;

for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; assert ( ( Subtarget -> isTargetLinux ( ) || Subtarget -> isTargetDarwin ( ) ) && <STR_LIT> ) ; assert ( Op . getNode ( ) -> getNumOperands ( ) == <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! DAG . getTarget ( ) . Options . UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SDValue InstOps [ ] = { Chain , SrcPtr , DAG . getConstant ( ArgSize , <STR_LIT> ) , DAG . getConstant ( ArgMode , <STR_LIT> ) , DAG . getConstant ( Align , <STR_LIT> ) } ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , InstOps , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ;

Chain = VAARG . getValue ( <NUM_LIT> ) ;


<s> if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; if ( ! isIntrinsic ) return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) ) ; if ( Cnt >= - ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) && Cnt <= - <NUM_LIT> ) { Cnt = - Cnt ; return true ; } return false ;


<s> if ( ( lsb & shift_mask ) == <NUM_LIT> ) return <NUM_LIT> ; return c == - lsb && lsb != <NUM_LIT> ; } else if ( GET_CODE ( andop ) == CONST_DOUBLE && ( GET_MODE ( andop ) == VOIDmode || GET_MODE ( andop ) == DImode ) ) { HOST_WIDE_INT low , lsb , shift_mask_low ; low = CONST_DOUBLE_LOW ( andop ) ; if ( HOST_BITS_PER_WIDE_INT < <NUM_LIT> ) { HOST_WIDE_INT high , shift_mask_high ; high = CONST_DOUBLE_HIGH ( andop ) ; if ( low == <NUM_LIT> ) { shift_mask_high = ~ <NUM_LIT> ; if ( INTVAL ( shiftop ) > <NUM_LIT> ) shift_mask_high <<= INTVAL ( shiftop ) - <NUM_LIT> ; lsb = high & - high ; if ( ( lsb & shift_mask_high ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( canWidenShuffleElements ( Mask , WidenedMask ) ) return lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) { unsigned VPERMILPMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getConstant ( VPERMILPMask , DL , <STR_LIT> ) ) ; } if ( Subtarget . hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; }

if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ;


<s> void arm_emit_eabi_attribute ( const char * name , int num , int val ) {

asm_fprintf ( asm_out_file , <STR_LIT> , num , val ) ;


<s> void <ISA_LIT>FastISel :: <ISA_LIT>SimplifyAddress ( Address & Addr , MVT VT , bool & UseOffset , unsigned & IndexReg ) { if ( ! isInt < <NUM_LIT> > ( Addr . Offset ) ) UseOffset = false ; if ( ! UseOffset && Addr . BaseType == Address :: FrameIndexBase ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( ! UseOffset ) { IntegerType * OffsetTy = ( ( VT == <STR_LIT> ) ? Type :: getInt32Ty ( * Context ) : Type :: getInt64Ty ( * Context ) ) ; const ConstantInt * Offset = ConstantInt :: getSigned ( OffsetTy , ( int64_t ) ( Addr . Offset ) ) ; IndexReg = <ISA_LIT>MaterializeInt ( Offset , <STR_LIT> ) ;


<s> explicit <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {


<s> SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ;

const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> return isImmTy ( ImmTyNone ) || isImmTy ( ImmTyOffset ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; i += <NUM_LIT> ) { if ( ( M [ i ] >= <NUM_LIT> && static_cast < unsigned > ( M [ i ] ) != Idx ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && static_cast < unsigned > ( M [ i + <NUM_LIT> ] ) != Idx + NumElts ) ) return false ; Idx += <NUM_LIT> ; } return true ;


<s> return new GCNPassConfig ( this , PM ) ;


<s> auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - FirstSPAdjustAmount ) ) ; BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { for ( auto & I = LastFrameDestroy ; I != MBBI ; ++ I ) { if ( I -> mayLoad ( ) && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register DestReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == FPReg ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( SPReg , true ) , - FPOffset ) ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; break ; } } } } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) {


<s> Value * <ISA_LIT>IREmitter :: visitCMN ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getType ( Src0 ) != S32 ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; MachineInstr * Src1Def = getDefIgnoringCopies ( Src1 , * MRI ) ; if ( Src1Def && Src1Def -> getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) && RBI . constrainGenericRegister ( Src0 , <STR_LIT> , * MRI ) ; } Register ShiftSrc0 ; Register ShiftSrc1 ; int64_t ShiftAmt ; bool Shift0 = mi_match ( Src0 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc0 ) , m_ICst ( ShiftAmt ) ) ) ) && ShiftAmt == <NUM_LIT> ; bool Shift1 = mi_match ( Src1 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc1 ) , m_ICst ( ShiftAmt ) ) ) ) && ShiftAmt == <NUM_LIT> ; unsigned Opc = <STR_LIT> ; if ( Shift0 && Shift1 ) { Opc = <STR_LIT> ;

MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc0 ) ;


<s> Register SrcReg = SMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MI -> modifiesRegister ( SrcReg , TRI ) ) { switch ( MI -> getOpcode ( ) ) { default : SI = Splats . erase ( SI ) ; continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( SplatReg != SrcReg ) { unsigned SubRegIndex = TRI -> getSubRegIndex ( SrcReg , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register SplatSubReg = TRI -> getSubReg ( SplatReg , SubRegIndex ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SplatSubReg ) ; MI -> substituteRegister ( SrcReg , SplatReg , <NUM_LIT> , * TRI ) ; } SI = Splats . erase ( SI ) ; ++ MBBI ; SMI -> eraseFromParent ( ) ; -- MBBI ; ++ NumSimplified ; MadeChange = true ; continue ; } } if ( MI -> modifiesRegister ( SplatReg , TRI ) || ( SrcReg != SplatReg && MI -> readsRegister ( SplatReg , TRI ) ) ) { SI = Splats . erase ( SI ) ; continue ; } ++ SI ; } if ( MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> ) continue ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ;

if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) continue ;


<s> TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>_64Target , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>_32Target , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>_64Target , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>_32Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>_64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_32Target , create<ISA_LIT>_32AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_64Target , create<ISA_LIT>_64AsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>_32Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>_64Target , createMCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>_32Target , create<ISA_LIT>MCInstPrinter ) ;

TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>_64Target , create<ISA_LIT>MCInstPrinter ) ;


<s> TypeSize getRegisterBitWidth ( TargetTransformInfo :: RegisterKind K ) const {

return TypeSize :: getFixed ( <NUM_LIT> ) ;


if ( EnableFalkorHWPFFix ) addPass ( createFalkorHWPFFixPass ( ) ) ;


<s> MachineInstr * MI = Br . MI ; MachineBasicBlock * MBB = MI -> getParent ( ) ; if ( ! isThumb1 ) llvm_unreachable ( <STR_LIT> ) ; Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBSizes [ MBB -> getNumber ( ) ] += <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , <NUM_LIT> ) ; HasFarJump = true ; NumUBrFixed ++ ;

DOUT ( llvm :: dbgs ( ) << <STR_LIT> << * MI ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getProcIFlags ( ) ) ) ) ;


<s> if ( ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) && isa < ConstantSDNode > ( N2 ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ;

} else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) {


<s> return ( Val == DoubleToBits ( <NUM_LIT> ) ) || ( Val == DoubleToBits ( <NUM_LIT> ) ) || ( Val == DoubleToBits ( - <NUM_LIT> ) ) || ( Val == DoubleToBits ( <NUM_LIT> ) ) || ( Val == DoubleToBits ( - <NUM_LIT> ) ) || ( Val == DoubleToBits ( <NUM_LIT> ) ) || ( Val == DoubleToBits ( - <NUM_LIT> ) ) || ( Val == DoubleToBits ( <NUM_LIT> ) ) || ( Val == DoubleToBits ( - <NUM_LIT> ) ) || ( Val == <NUM_LIT> && HasInv2Pi ) ;


<s> <ISA_LIT>PostLegalizerLoweringInfo ( bool OptSize , bool MinSize ) : CombinerInfo ( true , false , nullptr , true , OptSize , MinSize ) {

if ( ! GeneratedRuleCfg . parseCommandLineOption ( ) ) report_fatal_error ( <STR_LIT> ) ;


<s> offset = INTVAL ( XEXP ( op , <NUM_LIT> ) ) ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) return <NUM_LIT> ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) { if ( XEXP ( op , <NUM_LIT> ) == frame_pointer_rtx ) return offset < - <NUM_LIT> || offset > <NUM_LIT> ; return offset < <NUM_LIT> || offset > <NUM_LIT> ;


<s> case BRIG_COMPARE_LE : return BRIG_COMPARE_GT ; case BRIG_COMPARE_LT : return BRIG_COMPARE_GE ; case BRIG_COMPARE_NE : return BRIG_COMPARE_EQ ; default :


<s> if ( IsPIC && AttachToOperandIdx ) ErrMsg = <STR_LIT> ;


<s> <ISA_LIT>OptimizePICCall ( ) : MachineFunctionPass ( ID ) {


<s> t = get_attr_type ( seq -> insn ( <NUM_LIT> ) ) ; if ( t == TYPE_MCLD ) return t ; t = get_attr_type ( seq -> insn ( <NUM_LIT> ) ) ; if ( t == TYPE_MCLD ) return t ; return TYPE_MCST ; } else return get_attr_type ( insn ) ;


<s> SDValue CmpOp1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC ) ) ; SDValue Glue = emitCmp ( DAG , DL , C ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( C . CCValid , <STR_LIT> ) , DAG . getConstant ( C . CCMask , <STR_LIT> ) , Dest , Glue ) ;


<s> enum vlmul_type vlmul = get_vlmul ( vmode ) ; unsigned int ratio = calculate_ratio ( sew , vlmul ) ; if ( ! optimize ) emit_hard_vlmax_vsetvl ( vmode , vl ) ; else emit_insn ( gen_vlmax_avl ( Pmode , vl , gen_int_mode ( ratio , Pmode ) ) ) ;


<s> unsigned RInd = TargetRegisterInfo :: virtReg2Index ( VR ) ; if ( RInd >= CVect . size ( ) ) CVect . resize ( std :: max ( RInd + <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ; const BitTracker :: RegisterCell * CP = CVect [ RInd ] ; if ( CP == <NUM_LIT> ) CP = CVect [ RInd ] = & BT . lookup ( VR ) ; return * CP ;


<s> const unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( DstRB . getID ( ) != SrcRB . getID ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstRB . getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * DstRC = getRegClassForTypeOnBank ( DstTy , DstRB ) ; if ( ! DstRC ) return false ; const TargetRegisterClass * SrcRC = getRegClassForTypeOnBank ( SrcTy , SrcRB ) ; if ( ! SrcRC ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstRC == SrcRC ) { } else if ( DstRC == & <STR_LIT> ) { I . getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; } else if ( DstRC == & <STR_LIT> ) { I . getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; } else if ( DstRC == & <STR_LIT> ) { I . getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; } else { return false ; } I . setDesc ( TII . get ( <STR_LIT> ) ) ; return true ;


<s> bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; return ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( M , VT ) ) ) ;


<s> for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isRegMask ( ) ) continue ; for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) { if ( MO . clobbersPhysReg ( reg ) ) return true ;


<s> if ( ! cfun -> machine -> uses_anonymous_args && crtl -> args . size >= <NUM_LIT> && crtl -> args . size <= ( LAST_ARG_REGNUM * UNITS_PER_WORD ) && ( TARGET_AAPCS_BASED ? crtl -> args . info . aapcs_ncrn < <NUM_LIT> : crtl -> args . info . nregs < <NUM_LIT> ) ) return LAST_ARG_REGNUM ; for ( reg = LAST_LO_REGNUM ; reg > LAST_ARG_REGNUM ; reg -- ) if ( pushed_regs_mask & ( <NUM_LIT> << reg ) ) return reg ; if ( TARGET_THUMB2 ) { for ( reg = FIRST_HI_REGNUM ; reg < <NUM_LIT> ; reg ++ ) if ( pushed_regs_mask & ( <NUM_LIT> << reg ) ) return reg ; } gcc_unreachable ( ) ;


<s> SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; const <ISA_LIT>RegisterInfo * QRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; SDValue CopyChain = DAG . getCopyToReg ( Chain , dl , QRI -> getStackRegister ( ) , Sub ) ; SDValue Ops [ <NUM_LIT> ] = { ArgAdjust , CopyChain } ;

return DAG . getMergeValues ( Ops , dl ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : * AddrIdx = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : * AddrIdx = <NUM_LIT> ; if ( IsStore ) * IsStore = true ; return true ; case <STR_LIT> : case <STR_LIT> : * AddrIdx = <NUM_LIT> ; if ( IsStore ) * IsStore = true ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( CM == CodeModel :: JITDefault ) RM = Reloc :: Static ; else if ( RM == Reloc :: Default ) RM = Reloc :: PIC_ ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return X ;


<s> static const MCPhysReg IntraCallClobberedRegs [ ] = { <STR_LIT> } ; return ArrayRef < MCPhysReg > ( IntraCallClobberedRegs ) ;


<s> rtx src , dest ; if ( CONST_INT_P ( count ) ) { HOST_WIDE_INT countval = INTVAL ( count ) ; HOST_WIDE_INT epilogue_size = countval % max_size ; int i ; gcc_assert ( ( max_size & ( max_size - <NUM_LIT> ) ) == <NUM_LIT> ) ; for ( i = max_size ; i >= <NUM_LIT> ; i >>= <NUM_LIT> ) { if ( epilogue_size & i ) destmem = emit_memmov ( destmem , & srcmem , destptr , srcptr , i ) ; } return ; } if ( max_size > <NUM_LIT> ) { count = expand_simple_binop ( GET_MODE ( count ) , AND , count , GEN_INT ( max_size - <NUM_LIT> ) , count , <NUM_LIT> , OPTAB_DIRECT ) ; expand_set_or_cpymem_via_loop ( destmem , srcmem , destptr , srcptr , NULL , count , QImode , <NUM_LIT> , <NUM_LIT> , false ) ; return ; } if ( TARGET_SINGLE_STRINGOP ) { if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; src = change_address ( srcmem , SImode , srcptr ) ; dest = change_address ( destmem , SImode , destptr ) ; emit_insn ( gen_strmov ( destptr , dest , srcptr , src ) ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ; } if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; src = change_address ( srcmem , HImode , srcptr ) ; dest = change_address ( destmem , HImode , destptr ) ; emit_insn ( gen_strmov ( destptr , dest , srcptr , src ) ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ; } if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; src = change_address ( srcmem , QImode , srcptr ) ; dest = change_address ( destmem , QImode , destptr ) ; emit_insn ( gen_strmov ( destptr , dest , srcptr , src ) ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ; } } else { rtx offset = force_reg ( Pmode , const0_rtx ) ; rtx tmp ; if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; src = change_address ( srcmem , SImode , srcptr ) ; dest = change_address ( destmem , SImode , destptr ) ; emit_move_insn ( dest , src ) ; tmp = expand_simple_binop ( Pmode , PLUS , offset , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_LIB_WIDEN ) ; if ( tmp != offset ) emit_move_insn ( offset , tmp ) ; emit_label ( label ) ;


<s> Register Rt = TailAdd . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg = Rs == GAReg ? Rt : Rs ; if ( ! MRI -> hasOneUse ( Reg ) ) return false ; MachineInstr & OffsetTail = * MRI -> getVRegDef ( Reg ) ; if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { MachineOperand & AddiImmOp = OffsetTail . getOperand ( <NUM_LIT> ) ; if ( AddiImmOp . getTargetFlags ( ) != <STR_LIT> ) return false ; int64_t OffLo = AddiImmOp . getImm ( ) ; MachineInstr & OffsetLui = * MRI -> getVRegDef ( OffsetTail . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineOperand & LuiImmOp = OffsetLui . getOperand ( <NUM_LIT> ) ; if ( OffsetLui . getOpcode ( ) != <STR_LIT> || LuiImmOp . getTargetFlags ( ) != <STR_LIT> || ! MRI -> hasOneUse ( OffsetLui . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Offset = SignExtend64 < <NUM_LIT> > ( LuiImmOp . getImm ( ) << <NUM_LIT> ) ; Offset += OffLo ; if ( ! ST -> is64Bit ( ) ) Offset = SignExtend64 < <NUM_LIT> > ( Offset ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << OffsetTail << <STR_LIT> << OffsetLui ) ; DeadInstrs . insert ( & OffsetTail ) ; DeadInstrs . insert ( & OffsetLui ) ; return true ; } else if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << OffsetTail ) ; Offset = SignExtend64 < <NUM_LIT> > ( OffsetTail . getOperand ( <NUM_LIT> ) . getImm ( ) << <NUM_LIT> ) ; DeadInstrs . insert ( & OffsetTail ) ;


<s> bool <ISA_LIT>CFGStructurizer :: needMigrateBlock ( MachineBasicBlock * MBB ) const { unsigned BlockSizeThreshold = <NUM_LIT> ; unsigned CloneInstrThreshold = <NUM_LIT> ; bool MultiplePreds = MBB && ( MBB -> pred_size ( ) > <NUM_LIT> ) ; if ( ! MultiplePreds ) return false ;


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizeShlAshrLshr ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , GISelChangeObserver & Observer ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_ASHR || MI . getOpcode ( ) == TargetOpcode :: G_LSHR || MI . getOpcode ( ) == TargetOpcode :: G_SHL ) ; Register AmtReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto * CstMI = MRI . getVRegDef ( AmtReg ) ; assert ( CstMI && <STR_LIT> ) ; if ( CstMI -> getOpcode ( ) != TargetOpcode :: G_CONSTANT ) return true ; unsigned Amount = CstMI -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; if ( Amount > <NUM_LIT> ) return true ; assert ( MRI . getType ( AmtReg ) . getSizeInBits ( ) == <NUM_LIT> ) ; MIRBuilder . setInstrAndDebugLoc ( MI ) ; auto ExtCst = MIRBuilder . buildZExt ( LLT :: scalar ( <NUM_LIT> ) , AmtReg ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ExtCst . getReg ( <NUM_LIT> ) ) ; return true ;


<s> llvm :: RegisterAsmPrinter < llvm :: <ISA_LIT>Z80AsmPrinter > X ( llvm :: getThe<ISA_LIT>Z80Target ( ) ) ;


<s> unsigned getTotalNumVGPRs ( const MCSubtargetInfo * STI ) { if ( ! isGFX10 ( * STI ) ) return <NUM_LIT> ; return STI -> getFeatureBits ( ) . test ( FeatureWavefrontSize32 ) ? <NUM_LIT> : <NUM_LIT> ;


<s> ( void ) Analyzed ; if ( TBB && TBB != MBB ) { assert ( ( FBB == nullptr || FBB == MBB ) && <STR_LIT> ) ; assert ( Cond . size ( ) == <NUM_LIT> && Cond [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto * RangeCheck = MRI . getVRegDef ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; assert ( RangeCheck != nullptr ) ; if ( RangeCheck -> getOpcode ( ) != <STR_LIT> ) return nullptr ; MI . RemoveOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; MI . addOperand ( MF , MachineOperand :: CreateMBB ( TBB ) ) ; } TII . removeBranch ( * HeaderMBB , nullptr ) ; HeaderMBB -> splice ( HeaderMBB -> end ( ) , MBB , MBB -> begin ( ) , MBB -> end ( ) ) ; HeaderMBB -> removeSuccessor ( MBB ) ; for ( auto & Succ : MBB -> successors ( ) ) if ( HeaderMBB -> isSuccessor ( Succ ) ) HeaderMBB -> removeSuccessor ( Succ ) ; HeaderMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ;


<s> if ( num_mova ) si_limit -= GET_MODE_SIZE ( mode ) ; } } if ( mova_p ( from ) ) { switch ( untangle_mova ( & num_mova , & mova , from ) ) { case <NUM_LIT> : if ( flag_pic ) { rtx src = SET_SRC ( PATTERN ( from ) ) ; if ( GET_CODE ( src ) == CONST && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_SYMOFF ) last_symoff = from ; } break ; case <NUM_LIT> : return find_barrier ( <NUM_LIT> , <NUM_LIT> , mova ) ; case <NUM_LIT> : { leading_mova = <NUM_LIT> ; barrier_before_mova = good_barrier ? good_barrier : found_barrier ; } default : break ; } if ( found_si > count_si ) count_si = found_si ; } else if ( JUMP_TABLE_DATA_P ( from ) && GET_CODE ( PATTERN ( from ) ) == ADDR_DIFF_VEC ) { if ( ( num_mova > <NUM_LIT> && GET_MODE ( prev_nonnote_insn ( from ) ) == VOIDmode ) || ( num_mova && ( prev_nonnote_insn ( from ) == XEXP ( MOVA_LABELREF ( mova ) , <NUM_LIT> ) ) ) ) num_mova -- ; if ( barrier_align ( next_real_insn ( from ) ) == align_jumps_log ) { good_barrier = found_barrier ; break ; } else { rtx body = PATTERN ( from ) ; inc = XVECLEN ( body , <NUM_LIT> ) * GET_MODE_SIZE ( GET_MODE ( body ) ) ; } } else if ( JUMP_P ( from ) && ! TARGET_SH2 && ! optimize_size ) new_align = <NUM_LIT> ; if ( JUMP_P ( from ) && get_attr_type ( from ) == TYPE_CBRANCH && ! sequence_insn_p ( from ) ) inc += <NUM_LIT> ; if ( found_si ) { count_si += inc ; if ( new_align > si_align ) { si_limit -= ( count_si - <NUM_LIT> ) & ( new_align - si_align ) ; si_align = new_align ; } count_si = ( count_si + new_align - <NUM_LIT> ) & - new_align ; } if ( found_hi ) { count_hi += inc ; if ( new_align > hi_align ) { hi_limit -= ( count_hi - <NUM_LIT> ) & ( new_align - hi_align ) ; hi_align = new_align ; } count_hi = ( count_hi + new_align - <NUM_LIT> ) & - new_align ; } from = NEXT_INSN ( from ) ; } if ( num_mova ) { if ( leading_mova ) { fixup_mova ( mova ) ; return find_barrier ( <NUM_LIT> , <NUM_LIT> , mova ) ; } else { from = mova ; good_barrier = found_barrier = barrier_before_mova ; } } if ( found_barrier ) { if ( good_barrier && next_real_insn ( found_barrier ) ) found_barrier = good_barrier ; } else { rtx_code_label * label = gen_label_rtx ( ) ; if ( last_symoff ) from = last_symoff ; if ( PREV_INSN ( from ) != orig && ( count_hi > hi_limit || count_si > si_limit ) ) from = PREV_INSN ( PREV_INSN ( from ) ) ;


<s> static MCSubtargetInfo * createAMDGPUMCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ;

InitAMDGPUMCSubtargetInfo ( X , TT , CPU , FS ) ;


<s> static machine_mode nvptx_promote_function_mode ( const_tree type , machine_mode mode , int * ARG_UNUSED ( punsignedp ) , const_tree funtype , int for_return ) {

return promote_arg ( mode , for_return || ! type || TYPE_ARG_TYPES ( funtype ) ) ;


<s> void <ISA_LIT>AsmPrinter :: emitAsanReportError ( Module & M , unsigned Reg , const ASanAccessInfo & AccessInfo , MCSubtargetInfo & STI ) { std :: string Name = AccessInfo . IsWrite ? <STR_LIT> : <STR_LIT> ; MCSymbol * ReportError = OutContext . getOrCreateSymbol ( <STR_LIT> + Name + utostr ( <NUM_LIT> << AccessInfo . AccessSizeIndex ) ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> + Reg ) , STI ) ;

OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( ReportError , MCSymbolRefExpr :: VK_PLT , OutContext ) ) , STI ) ;


<s> return Parser . Error ( L , Msg , Ranges ) ;


<s> MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! DefInst ) continue ; bool IsCandidate = false ; if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar ) { if ( GVar -> hasAttribute ( <STR_LIT> ) ) { assert ( ImmVal == <NUM_LIT> ) ; IsCandidate = true ; } else if ( ! GVar -> hasInitializer ( ) && GVar -> hasExternalLinkage ( ) && GVar -> getSection ( ) == <STR_LIT> ) { if ( ImmVal == <NUM_LIT> ) IsCandidate = true ; else errs ( ) << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> << ImmVal << <STR_LIT> ; } } } } if ( ! IsCandidate ) continue ; auto Begin = MRI -> use_begin ( DstReg ) , End = MRI -> use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) { NextI = std :: next ( I ) ; I -> setReg ( SrcReg ) ; }


<s> bool existed ; bool * slot = & mflip_mips16_htab -> get_or_insert ( name , & existed ) ; if ( ! existed ) { mips16_flipper = ! mips16_flipper ; * slot = mips16_flipper ? ! base_is_mips16 : base_is_mips16 ; } return * slot ;


<s> return isImmTy ( ImmTyDppRowMask ) ;


<s> unsigned RegNo = ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) ? <STR_LIT> : <STR_LIT> ; return CreateLiveInRegister ( DAG , & <STR_LIT> , RegNo , <STR_LIT> ) ; } SDLoc SL ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned UserSGPR = Info -> getQueuePtrUserSGPR ( ) ; assert ( UserSGPR != <STR_LIT> ) ;

SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR , <STR_LIT> ) ;


<s> MachineBasicBlock * MBB1 = * MBB -> succ_begin ( ) ; MachineBasicBlock * MBB2 = * std :: next ( MBB -> succ_begin ( ) ) ; if ( MBB1 != MBB2 ) return ; MachineInstr * BranchMI = getNormalBlockBranchInstr ( MBB ) ; assert ( BranchMI && isCondBranch ( BranchMI ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * BranchMI ) ; BranchMI -> eraseFromParent ( ) ;


<s> return ! isTC1 ( MI ) && ! isTC2Early ( MI ) && ! MI . getDesc ( ) . mayLoad ( ) && ! MI . getDesc ( ) . mayStore ( ) && MI . getDesc ( ) . getOpcode ( ) != <STR_LIT> && MI . getDesc ( ) . getOpcode ( ) != <STR_LIT> && ! isMemOp ( MI ) && ! MI . isBranch ( ) && ! MI . isReturn ( ) && ! MI . isCall ( ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( ( Val & <NUM_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; return MCDisassembler :: Success ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + ( save_fp ? <NUM_LIT> : <NUM_LIT> ) + <NUM_LIT> ) ) ; indx = <NUM_LIT> ; reg = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - nregs * UNITS_PER_WORD ) ) ; RTX_FRAME_RELATED_P ( reg ) = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; save_blink = false ; } for ( regno = start_reg ; regno <= end_reg ; regno ++ , indx ++ , off -= UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; } if ( save_fp ) { mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , hard_frame_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( hard_frame_pointer_rtx , stack_pointer_rtx ) ;


<s> static void dumpBytes ( const SmallVectorImpl < int > & Bytes , std :: string Msg ) {

dbgs ( ) << Msg . c_str ( ) << <STR_LIT> ;


<s> return ( uint8x8_t ) __builtin_neon_vreinterpretv8qidi ( __a ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Target & T , StringRef TT ) {