<s> BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( Dest . getReg ( ) , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; LoadCmpBB -> addSuccessor ( DoneBB ) ; LoadCmpBB -> addSuccessor ( StoreBB ) ; MIB = BuildMI ( StoreBB , DL , TII -> get ( StrexOp ) , TempReg ) . addReg ( NewReg ) . addReg ( AddrReg ) ; if ( StrexOp == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPri = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( StoreBB , DL , TII -> get ( CMPri ) ) . addReg ( TempReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( StoreBB , DL , TII -> get ( Bcc ) ) . addMBB ( LoadCmpBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; StoreBB -> addSuccessor ( LoadCmpBB ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ;


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ;

buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ;


<s> Val = MO . getImm ( ) ; return true ; } if ( ! MO . isReg ( ) ) return false ; int64_t TV ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return false ; MachineInstr * DI = MRI -> getVRegDef ( R ) ; unsigned DOpc = DI -> getOpcode ( ) ; switch ( DOpc ) { case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! checkForImmediate ( DI -> getOperand ( <NUM_LIT> ) , TV ) ) return false ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & S1 = DI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & S2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V1 , V2 ; if ( ! checkForImmediate ( S1 , V1 ) || ! checkForImmediate ( S2 , V2 ) ) return false ; TV = V2 | ( V1 << <NUM_LIT> ) ; break ; } case TargetOpcode :: REG_SEQUENCE : { const MachineOperand & S1 = DI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & S3 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V1 , V3 ; if ( ! checkForImmediate ( S1 , V1 ) || ! checkForImmediate ( S3 , V3 ) ) return false ; unsigned Sub2 = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Sub4 = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Sub2 == <STR_LIT> && Sub4 == <STR_LIT> ) TV = V1 | ( V3 << <NUM_LIT> ) ; else if ( Sub2 == <STR_LIT> && Sub4 == <STR_LIT> ) TV = V3 | ( V1 << <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; } default : return false ; }


<s> switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isSLoad = true ; break ; } if ( ( isSLoad && ( RegNo % <NUM_LIT> ) ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; } else { DefCycle = RegNo + <NUM_LIT> ; }


<s> RegNum = matchRegisterName ( lowerCase ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) {

RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ;


<s> if ( MI . getOpcode ( ) != TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS || ! IntrsWConstsToFold . count ( MI . getIntrinsicID ( ) ) ) continue ; unsigned NumOp = MI . getNumExplicitDefs ( ) + IntrsWConstsToFold . at ( MI . getIntrinsicID ( ) ) ; while ( MI . getOperand ( NumOp ) . isReg ( ) ) { MachineOperand & MOp = MI . getOperand ( NumOp ) ; MachineInstr * ConstMI = MRI . getVRegDef ( MOp . getReg ( ) ) ; assert ( ConstMI -> getOpcode ( ) == TargetOpcode :: G_CONSTANT ) ; MI . RemoveOperand ( NumOp ) ; MI . addOperand ( MachineOperand :: CreateImm ( ConstMI -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ) ) ; if ( MRI . use_empty ( ConstMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ToErase . push_back ( ConstMI ) ; } } } for ( MachineInstr * MI : ToErase ) MI -> eraseFromParent ( ) ;


<s> void finish ( ) override { for ( auto * Sym : UpdateOther ) copyLocalEntry ( Sym , Sym -> getVariableValue ( ) ) ;


<s> bool hasNo<ISA_LIT>16Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; Attribute SFAttr = F . getFnAttribute ( <STR_LIT> ) ; bool softFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == <STR_LIT> : Options . UseSoftFloat ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS + ( softFloat ? <STR_LIT> : <STR_LIT> ) ] ; if ( ! I ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> virtual void EmitARM64WinCFISaveRegP ( unsigned Reg , int Offset ) {


<s> static bool nds32_expand_movmemsi_loop_unknown_size ( rtx dstmem , rtx srcmem , rtx size , rtx alignment ) { rtx dst_base_reg , src_base_reg ; rtx dst_itr , src_itr ; rtx dstmem_m , srcmem_m , dst_itr_m , src_itr_m ; rtx dst_end ; rtx size_least_3_bit ; rtx double_word_end ; rtx double_word_mode_loop , byte_mode_entry , byte_mode_loop , end_label ; rtx tmp ; rtx mask_least_3_bit ; int start_regno ; bool align_to_4_bytes = ( INTVAL ( alignment ) & <NUM_LIT> ) == <NUM_LIT> ; if ( TARGET_ISA_V3M && ! align_to_4_bytes ) return <NUM_LIT> ; if ( TARGET_REDUCED_REGS ) start_regno = <NUM_LIT> ; else start_regno = <NUM_LIT> ; dst_itr = gen_reg_rtx ( Pmode ) ; src_itr = gen_reg_rtx ( Pmode ) ; dst_end = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( QImode ) ; mask_least_3_bit = GEN_INT ( ~ <NUM_LIT> ) ; double_word_mode_loop = gen_label_rtx ( ) ; byte_mode_entry = gen_label_rtx ( ) ; byte_mode_loop = gen_label_rtx ( ) ; end_label = gen_label_rtx ( ) ; dst_base_reg = copy_to_mode_reg ( Pmode , XEXP ( dstmem , <NUM_LIT> ) ) ; src_base_reg = copy_to_mode_reg ( Pmode , XEXP ( srcmem , <NUM_LIT> ) ) ; size_least_3_bit = expand_binop ( SImode , and_optab , size , mask_least_3_bit , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; dst_end = expand_binop ( Pmode , add_optab , dst_base_reg , size , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( dst_itr , dst_base_reg ) ; emit_move_insn ( src_itr , src_base_reg ) ; emit_cmp_and_jump_insns ( size_least_3_bit , const0_rtx , EQ , NULL , SImode , <NUM_LIT> , byte_mode_entry ) ; double_word_end = expand_binop ( Pmode , add_optab , dst_base_reg , size_least_3_bit , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ;


<s> } else { const <ISA_LIT>Subtarget & STI = MI -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;

OutStreamer -> AddComment ( Twine ( <STR_LIT> ) + STI . getRegisterInfo ( ) -> getName ( RegNo ) ) ;


<s> std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; InstructionCost Cost = getMemoryOpCost ( Opcode , VecTy , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; Cost += Factor * ( LT . first - <NUM_LIT> ) ; return Cost ;


<s> const MachineInstr * BMI = BSU -> getInstr ( ) ; if ( ! BMI || BMI -> isPseudo ( ) || BMI -> isTransient ( ) || ( Preds && ! shouldScheduleAdjacent ( * TII , ST , BMI , AMI ) ) || ( ! Preds && ! shouldScheduleAdjacent ( * TII , ST , AMI , BMI ) ) ) continue ; if ( Preds ) DAG -> addEdge ( ASU , SDep ( BSU , SDep :: Cluster ) ) ; else DAG -> addEdge ( BSU , SDep ( ASU , SDep :: Cluster ) ) ; for ( SDep & Dep : APreds ) if ( Dep . getSUnit ( ) == BSU ) Dep . setLatency ( <NUM_LIT> ) ; auto & BSuccs = Preds ? BSU -> Succs : BSU -> Preds ; for ( SDep & Dep : BSuccs ) if ( Dep . getSUnit ( ) == ASU ) Dep . setLatency ( <NUM_LIT> ) ; ++ NumFused ; DEBUG ( { SUnit * LSU = Preds ? BSU : ASU ; SUnit * RSU = Preds ? ASU : BSU ; const MachineInstr * LMI = Preds ? BMI : AMI ; const MachineInstr * RMI = Preds ? AMI : BMI ; dbgs ( ) << DAG -> MF . getName ( ) << <STR_LIT> ; LSU -> print ( dbgs ( ) , DAG ) ; dbgs ( ) << <STR_LIT> ; RSU -> print ( dbgs ( ) , DAG ) ; dbgs ( ) << <STR_LIT> << TII -> getName ( LMI -> getOpcode ( ) ) << <STR_LIT> << TII -> getName ( RMI -> getOpcode ( ) ) << '\n' ;


<s> bool <ISA_LIT>RegisterInfo :: hasFP ( const MachineFunction & MF ) const { return DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> unsigned getT2AddrModeImm0_1020s4OpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT> ;


<s> BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; mainMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ;

BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ;


<s> V1Mask [ i ] = V2Mask [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else { const int ZeroMask = <NUM_LIT> ; int V1Idx = Mask [ i / Scale ] < Size ? Mask [ i / Scale ] * Scale + i % Scale : ZeroMask ; int V2Idx = Mask [ i / Scale ] < Size ? ZeroMask : ( Mask [ i / Scale ] - Size ) * Scale + i % Scale ; if ( Zeroable [ i / Scale ] ) V1Idx = V2Idx = ZeroMask ; V1Mask [ i ] = DAG . getConstant ( V1Idx , DL , <STR_LIT> ) ; V2Mask [ i ] = DAG . getConstant ( V2Idx , DL , <STR_LIT> ) ; V1InUse |= ( ZeroMask != V1Idx ) ; V2InUse |= ( ZeroMask != V2Idx ) ; } } if ( V1InUse ) V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , DAG . getBuildVector ( <STR_LIT> , DL , V1Mask ) ) ; if ( V2InUse ) V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V2 ) , DAG . getBuildVector ( <STR_LIT> , DL , V2Mask ) ) ;


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } unsigned FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; if ( isInt < <NUM_LIT> > ( Offset ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;

} else if ( isInt < <NUM_LIT> > ( Offset ) ) {


<s> const auto SavedBytes = Bytes ; if ( decodeInstruction ( Table , TmpInst , Inst , Address , this , STI ) ) { MI = TmpInst ; return MCDisassembler :: Success ;


<s> void <ISA_LIT>JITInfo :: replaceMachineCodeForFunction ( void * Old , void * New ) {


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const DebugLoc & DL = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; uint64_t CalleePopAmount = IsDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; if ( ! hasReservedCallFrame ( MF ) ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ; assert ( isUInt < <NUM_LIT> > ( Amount ) && <STR_LIT> ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register SPReg = MFI -> getStackPtrOffsetReg ( ) ; Amount *= getScratchScaleFactor ( ST ) ; if ( IsDestroy ) Amount = - Amount ; auto Add = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( Amount ) ; Add -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } else if ( CalleePopAmount != <NUM_LIT> ) {


<s> <ISA_LIT>PLT1 :: <ISA_LIT>PLT1 ( SectionData & pParent ) : PLT :: Entry < sizeof ( aarch64_plt1 ) > ( pParent ) {


<s> return ( __m128i ) __builtin_ia32_punpckhwd128_mask ( ( __v8hi ) __A , ( __v8hi ) __B , ( __v8hi ) _mm_setzero_si128 ( ) , ( __mmask8 ) __U ) ;


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm , JITCodeEmitter & mce ) : MachineFunctionPass ( ID ) , JTI ( <NUM_LIT> ) , II ( ( const <ISA_LIT>InstrInfo * ) tm . getInstrInfo ( ) ) , TD ( tm . getDataLayout ( ) ) , TM ( tm ) , MCE ( mce ) , MCPEs ( <NUM_LIT> ) , MJTEs ( <NUM_LIT> ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> else if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) == LABEL_REF ) label = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; else continue ; } else continue ; if ( get_attr_length ( insn ) == <NUM_LIT> ) continue ; if ( flag_pic ) { target = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , label ) , <NUM_LIT> ) ; target = gen_rtx_CONST ( SImode , target ) ; target = force_const_mem ( SImode , target ) ; jump = gen_rtx_REG ( Pmode , BASE_REGISTER ) ; jump = gen_rtx_PLUS ( Pmode , jump , temp_reg ) ; } else { target = force_const_mem ( Pmode , label ) ; jump = temp_reg ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) {


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> AU . addRequired < MachineLoopInfo > ( ) ; AU . addRequired < ReachingDefAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) {


<s> PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> } else { if ( XNACKUsed ) ExtraSGPRs = <NUM_LIT> ; if ( FlatScrUsed || STI -> getFeatureBits ( ) . test ( <STR_LIT> ) ) ExtraSGPRs = <NUM_LIT> ; } return ExtraSGPRs ;


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ;

bool isAdd = MO1 . getImm ( ) != <NUM_LIT> ;


<s> if ( N1 . getOpcode ( ) == <STR_LIT> ) N1 = N1 . getOperand ( <NUM_LIT> ) ; unsigned LoOpcode , HiOpcode ; if ( Subtarget -> hasMulU24 ( ) && isU24 ( N0 , DAG ) && isU24 ( N1 , DAG ) ) { N0 = DAG . getZExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getZExtOrTrunc ( N1 , DL , <STR_LIT> ) ; LoOpcode = <STR_LIT> ; HiOpcode = <STR_LIT> ; } else if ( Subtarget -> hasMulI24 ( ) && isI24 ( N0 , DAG ) && isI24 ( N1 , DAG ) ) {

N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ;


<s> FunctionPass * llvm :: createShadowCallStackPass ( ) {


<s> if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; if ( SDValue V = lowerVectorShuffleWithUndefHalf ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( VT . isInteger ( ) && ! Subtarget -> hasAVX2 ( ) ) { int ElementBits = VT . getScalarSizeInBits ( ) ; if ( ElementBits < <NUM_LIT> ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; MVT FpVT = <STR_LIT> ( <STR_LIT> ( ElementBits ) , VT . getVectorNumElements ( ) ) ; V1 = DAG . getBitcast ( FpVT , V1 ) ; V2 = DAG . getBitcast ( FpVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( FpVT , DL , V1 , V2 , Mask ) ) ; } switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV4F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> :

return lowerV8F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ;


assert ( FrameIdx == MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) && <STR_LIT> ) ;


<s> return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ;


<s> EVT Ty = Op . getValueType ( ) ; unsigned GOTFlag = <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( Op , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( Op , DAG , LoFlag ) ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load , Lo ) ;


<s> } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMsaDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMsaDirective ( ) ; } else { parseSetAssignment ( ) ; return false ;


<s> TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Is64Bit = Subtarget -> is64Bit ( ) ; assert ( Subtarget -> isTargetNaCl ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ;

for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ;


<s> if ( HiOperand . isBlockAddress ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addBlockAddress ( HiOperand . getBlockAddress ( ) , HiOperand . getOffset ( ) , HiOperand . getTargetFlags ( ) ) . addReg ( LoReg , LoRegKillFlag ) ; return ; } if ( HiOperand . isJTI ( ) ) { BuildMI ( * BB , InsertPt , DL , TII -> get ( <STR_LIT> ) , DoubleDestReg ) . addJumpTableIndex ( HiOperand . getIndex ( ) , HiOperand . getTargetFlags ( ) ) . addReg ( LoReg , LoRegKillFlag ) ; return ; }


<s> rtx_insn * insn ; if ( offset == <NUM_LIT> ) return ; if ( offset < - <NUM_LIT> || offset > <NUM_LIT> ) { rtx reg = gen_rtx_REG ( SImode , REG_A0 ) ; rtx low = GEN_INT ( trunc_int_for_mode ( offset , HImode ) ) ; insn = emit_insn ( gen_movsi_high ( reg , low ) ) ; if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_movsi_lo_sum ( reg , reg , to_add ) ) ; if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; to_add = reg ; }


<s> return std :: min ( STC . getStackCacheSize ( ) , getMinMaxDisplacement ( Node , true ) ) ;


<s> MDNode * Node = cast < MDNode > ( KernelMDNode -> getOperand ( i + <NUM_LIT> ) ) ; Res . push_back ( Node -> getOperand ( OpIdx ) ) ;


<s> } else { const unsigned * CSRegs = getCalleeSavedRegs ( ) ; if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; bool HasFP = hasFP ( MF ) ; if ( ( STI . isTargetDarwin ( ) && NumBytes ) || HasFP ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( HasFP || AFI -> getGPRCalleeSavedArea2Size ( ) || AFI -> getDPRCalleeSavedAreaSize ( ) || AFI -> getDPRCalleeSavedAreaOffset ( ) ) { if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedAreaSize ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getGPRCalleeSavedArea2Size ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getGPRCalleeSavedArea1Size ( ) ) ; }

if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , VARegSaveSize ) ;


<s> SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ;

SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ;


<s> Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) , Result ) ; }

if ( isGlobalStubReference ( OpFlags ) ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> ) ;


<s> switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: BUNDLE : case TargetOpcode :: CFI_INSTRUCTION : case TargetOpcode :: EH_LABEL :


<s> } else emit_move_insn ( target , GEN_INT ( d3 ) ) ; emit_move_insn ( target , gen_rtx_ASHIFT ( DImode , target , GEN_INT ( <NUM_LIT> ) ) ) ; if ( d2 ) emit_move_insn ( target , gen_rtx_PLUS ( DImode , target , GEN_INT ( d2 ) ) ) ;

if ( d1 ) emit_move_insn ( target , gen_rtx_PLUS ( DImode , target , GEN_INT ( d1 ) ) ) ;


<s> if ( ! isInt < <NUM_LIT> > ( Imm ) ) { Shift = countTrailingZeros < uint64_t > ( Imm ) ; int64_t ImmSh = static_cast < uint64_t > ( Imm ) >> Shift ; if ( isInt < <NUM_LIT> > ( ImmSh ) ) { Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned Result = <NUM_LIT> ; unsigned Lo = Imm & <NUM_LIT> ; unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) { ++ Result ; } else if ( Lo ) { Result += <NUM_LIT> ; } else { ++ Result ; } if ( ! Shift ) return Result ; if ( Imm ) ++ Result ; if ( ( Hi = ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ) ++ Result ; if ( ( Lo = Remainder & <NUM_LIT> ) ) ++ Result ;


<s> SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; APInt ShlConst = ( cast < ConstantSDNode > ( N01 ) ) -> getAPIntValue ( ) ; APInt SarConst = ( cast < ConstantSDNode > ( N1 ) ) -> getAPIntValue ( ) ; EVT CVT = N1 . getValueType ( ) ; if ( SarConst . isNegative ( ) ) return SDValue ( ) ; for ( MVT SVT : <STR_LIT> ( ) ) { unsigned ShiftSize = SVT . getSizeInBits ( ) ; if ( ShiftSize < <NUM_LIT> || ShiftSize > <NUM_LIT> || ShlConst != Size - ShiftSize ) continue ; SDLoc DL ( N ) ; SDValue NN = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getValueType ( SVT ) ) ; SarConst = SarConst - ( Size - ShiftSize ) ; if ( SarConst == <NUM_LIT> ) return NN ;

else if ( SarConst . isNegative ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , NN , DAG . getConstant ( - SarConst , DL , CVT ) ) ;


<s> Offset = CurDAG -> getIntPtrConstant ( <NUM_LIT> , SDLoc ( Addr ) , true ) ;


<s> void <ISA_LIT>LoopRescheduling :: moveGroup ( InstrGroup & G , MachineBasicBlock & LB , MachineBasicBlock & PB , MachineBasicBlock :: iterator At , unsigned OldPhiR , unsigned NewPredR ) { DenseMap < unsigned , unsigned > RegMap ; const TargetRegisterClass * PhiRC = MRI -> getRegClass ( NewPredR ) ; Register PhiR = MRI -> createVirtualRegister ( PhiRC ) ; BuildMI ( LB , At , At -> getDebugLoc ( ) , HII -> get ( TargetOpcode :: PHI ) , PhiR ) . addReg ( NewPredR ) . addMBB ( & PB ) . addReg ( G . Inp . Reg ) . addMBB ( & LB ) ; RegMap . insert ( std :: make_pair ( G . Inp . Reg , PhiR ) ) ; for ( unsigned i = G . Ins . size ( ) ; i > <NUM_LIT> ; -- i ) { const MachineInstr * SI = G . Ins [ i - <NUM_LIT> ] ; unsigned DR = getDefReg ( SI ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DR ) ; Register NewDR = MRI -> createVirtualRegister ( RC ) ; DebugLoc DL = SI -> getDebugLoc ( ) ; auto MIB = BuildMI ( LB , At , DL , HII -> get ( SI -> getOpcode ( ) ) , NewDR ) ; for ( unsigned j = <NUM_LIT> , m = SI -> getNumOperands ( ) ; j < m ; ++ j ) { const MachineOperand & Op = SI -> getOperand ( j ) ;


<s> static int out_adj_frame_ptr ( FILE * file , int adj ) { int size = <NUM_LIT> ; if ( adj ) { if ( TARGET_TINY_STACK ) { if ( adj < - <NUM_LIT> || adj > <NUM_LIT> ) warning ( <NUM_LIT> , <STR_LIT> , adj ) ; fprintf ( file , ( AS2 ( subi , r28 , % d ) CR_TAB ) , adj ) ; size ++ ; } else if ( adj < - <NUM_LIT> || adj > <NUM_LIT> ) { fprintf ( file , ( AS2 ( subi , r28 , lo8 ( % d ) ) CR_TAB AS2 ( sbci , r29 , hi8 ( % d ) ) CR_TAB ) , adj , adj ) ;


<s> mep_note_pragma_flag ( funcname , FUNC_DISINTERRUPT ) ;


<s> const MCOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; O << MO . getImm ( ) + <NUM_LIT> ;


<s> if ( Count % <NUM_LIT> != <NUM_LIT> ) return false ; uint64_t NumNops = Count / <NUM_LIT> ;

for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ;


<s> static inline void maybe_add_dllimport ( tree decl ) { if ( i386_pe_type_dllimport_p ( decl ) ) DECL_DLLIMPORT_P ( decl ) = <NUM_LIT> ;


<s> if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) {

IntPtr = CurDAG -> getIntPtrConstant ( Cst -> getZExtValue ( ) / <NUM_LIT> , SDLoc ( Addr ) , true ) ;


<s> Thumb2InstrInfo :: Thumb2InstrInfo ( const <ISA_LIT>Subtarget & STI ) : RI ( * this , STI ) {


<s> int FPOffset = Subtarget . getFrameLowering ( ) -> getFramePointerSaveOffset ( ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } return DAG . getFrameIndex ( FPSI , PtrVT ) ;


<s> case MCDisassembler :: SoftFail : Out = In ; return true ; case MCDisassembler :: Fail : Out = In ; return false ; }


<s> TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; const MCSection * LSPSection = TLOFMacho . getLazySymbolPointerSection ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { const MCSection * StubSection = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; const MCSymbol * Stub = Stubs [ i ] . first ; const MCSymbol * RawSym = Stubs [ i ] . second ; const MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; const MCSymbol * AnonSymbol = GetAnonSym ( Stub , OutContext ) ; O << * Stub << <STR_LIT> ;


<s> for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) { CPUser & U = CPUsers [ i ] ; unsigned UserOffset = getUserOffset ( U ) ; if ( isCPEntryInRange ( U . MI , UserOffset , U . CPEMI , U . getMaxDisp ( ) + <NUM_LIT> , U . NegOk , true ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; }


<s> cvtLdWriteBackRegAddrMode2 ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;

( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode2Operands ( Inst , <NUM_LIT> ) ;


<s> static const MCPhysReg CalleeSavedRegs [ ] = { <NUM_LIT> } ; return CalleeSavedRegs ;


<s> MCCodeEmitter * create<ISA_LIT>Z80MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>Z80MCCodeEmitter ( MCII , Ctx ) ;


<s> const RegClassWeight & <ISA_LIT>RegisterInfo :: getRegClassWeight ( const TargetRegisterClass * RC ) const {


<s> OS << <STR_LIT> << Sym -> getName ( ) << <STR_LIT> << <STR_LIT> ( static_cast < <STR_LIT> > ( Sym -> getGlobalType ( ) . Type ) ) << '\n' ;


<s> void setFunctionType ( FunctionType * FT ) { FuncTy = FT ;


<s> StringRef getPassName ( ) const override {


<s> case ORDERED : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_ABS ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case EQ : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , gen_rtx_ABS ( compare_mode , op0 ) ) ) ) ; op0 = temp ; break ; case UNGE : temp = gen_reg_rtx ( result_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ; false_cond = true_cond ; true_cond = temp ; temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; case GT : temp = gen_reg_rtx ( result_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ; true_cond = false_cond ; false_cond = temp ; temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode , gen_rtx_GE ( VOIDmode , op0 , op1 ) , true_cond , false_cond ) ) ) ;


<s> HOST_WIDE_INT mask = d -> mask ; unsigned attr = rs6000_builtin_info [ d -> code ] . attr ; bool void_func = ( attr & RS6000_BTC_VOID ) ; int attr_args = ( attr & RS6000_BTC_TYPE_MASK ) ; int nopnds = <NUM_LIT> ; tree argtype = ( attr & RS6000_BTC_SPR ) ? long_unsigned_type_node : unsigned_type_node ; if ( ( mask & builtin_mask ) != mask ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , d -> name ) ; continue ; } if ( d -> name == <NUM_LIT> ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , ( long unsigned ) i ) ; continue ; } op [ nopnds ++ ] = ( void_func ) ? void_type_node : argtype ; if ( attr_args == RS6000_BTC_UNARY ) op [ nopnds ++ ] = argtype ; else if ( attr_args == RS6000_BTC_BINARY ) { op [ nopnds ++ ] = argtype ; op [ nopnds ++ ] = argtype ; } else if ( attr_args == RS6000_BTC_TERNARY ) { op [ nopnds ++ ] = argtype ; op [ nopnds ++ ] = argtype ; op [ nopnds ++ ] = argtype ; } switch ( nopnds ) { case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; default : gcc_unreachable ( ) ; } def_builtin ( d -> name , type , d -> code ) ; }


<s> if ( Alignment == <NUM_LIT> ) { SDValue Loads [ <NUM_LIT> ] ; Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Base , LoadNode -> getPointerInfo ( ) , <STR_LIT> , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , Alignment ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Base . getValueType ( ) , Base , Increment ) ; Loads [ <NUM_LIT> ] = DAG . getExtLoad ( Ext , DL , <STR_LIT> , Chain , Ptr , LoadNode -> getPointerInfo ( ) , <STR_LIT> , LoadNode -> isVolatile ( ) , LoadNode -> isNonTemporal ( ) , LoadNode -> isInvariant ( ) , Alignment ) ; SDValue ShiftAmount = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Loads [ <NUM_LIT> ] , ShiftAmount ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Tmp1 , Loads [ <NUM_LIT> ] ) ; Increment = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> BasicBlock * <ISA_LIT>CommonGEP :: adjustForInvariance ( GepNode * Node , NodeChildrenMap & NCM , NodeToValueMap & Loc ) { ValueVect Bs ; if ( Node -> Flags & GepNode :: Root ) { if ( Instruction * PIn = dyn_cast < Instruction > ( Node -> BaseVal ) ) Bs . push_back ( PIn -> getParent ( ) ) ; } else { Bs . push_back ( Loc [ Node -> Parent ] ) ; } if ( Instruction * IIn = dyn_cast < Instruction > ( Node -> Idx ) ) Bs . push_back ( IIn -> getParent ( ) ) ; BasicBlock * TopB = nearest_common_dominatee ( DT , Bs ) ; BasicBlock * LocB = cast_or_null < BasicBlock > ( Loc [ Node ] ) ; if ( LocB ) { Loop * Lp = LI -> getLoopFor ( LocB ) ; while ( Lp ) { if ( ! isInvariantIn ( Node , Lp ) || ! isInMainPath ( LocB , Lp ) ) break ; BasicBlock * NewLoc = preheader ( DT , Lp ) ; if ( ! NewLoc || ! DT -> dominates ( TopB , NewLoc ) ) break ; Lp = Lp -> getParentLoop ( ) ; LocB = NewLoc ; } } Loc [ Node ] = LocB ; NodeChildrenMap :: iterator CF = NCM . find ( Node ) ; if ( CF != NCM . end ( ) ) { NodeVect & Cs = CF -> second ; for ( GepNode * C : Cs ) adjustForInvariance ( C , NCM , Loc ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ;

return ( DisableFramePointerElim ( MF ) || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ;


<s> if ( optimize_size && hard_regno < <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setLibCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( IsSigned ) . setZExtResult ( ! IsSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; return CallInfo . first ;


<s> bool isInlineImmediate32 ( int64_t Imm ) const { return <STR_LIT> ( Imm , Subtarget -> hasInv2PiInlineImm ( ) ) ;


<s> <ISA_LIT>ElimCompare ( const <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) {


<s> bool <ISA_LIT>InstrInfo :: readsLDSSrcReg ( const MachineInstr * MI ) const { if ( ! isALUInstr ( MI -> getOpcode ( ) ) ) { return false ; }

for ( MachineInstr :: const_mop_iterator I = MI -> operands_begin ( ) , E = MI -> operands_end ( ) ; I != E ; ++ I ) {


<s> HSACodeProps . mGroupSegmentFixedSize = ProgramInfo . LDSSize ; HSACodeProps . mPrivateSegmentFixedSize = ProgramInfo . ScratchSize ; HSACodeProps . mKernargSegmentAlign = std :: max ( uint32_t ( <NUM_LIT> ) , MFI . getMaxKernArgAlign ( ) ) ; HSACodeProps . mWavefrontSize = STM . getWavefrontSize ( ) ; HSACodeProps . mNumSGPRs = CurrentProgramInfo . NumSGPR ; HSACodeProps . mNumVGPRs = CurrentProgramInfo . NumVGPR ; HSACodeProps . mMaxFlatWorkGroupSize = MFI . getMaxFlatWorkGroupSize ( ) ; HSACodeProps . mIsDynamicCallStack = ProgramInfo . DynamicCallStack ; HSACodeProps . mIsXNACKEnabled = STM . isXNACKEnabled ( ) ;


<s> static bool frv_must_pass_in_stack ( enum machine_mode mode , tree type ) {


<s> unsigned PtrArgAS = PtrArg -> getType ( ) -> getPointerAddressSpace ( ) ; auto * PtrTy = llvm :: PointerType :: get ( PtrElemTy , PtrArgAS ) ; SmallVector < llvm :: Type * , <NUM_LIT> > ArgTys ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) ArgTys . push_back ( CI -> getArgOperand ( I ) -> getType ( ) ) ; ArgTys . push_back ( PtrTy ) ; Name = Name + <STR_LIT> + std :: to_string ( Size ) ; auto * FTy = FunctionType :: get ( Callee -> getReturnType ( ) , ArrayRef < Type * > ( ArgTys ) , false ) ; <ISA_LIT>LibFunc NewLibFunc ( Name , FTy ) ; FunctionCallee F = <ISA_LIT>LibFunc :: getOrInsertFunction ( M , NewLibFunc ) ; if ( ! F ) return false ; auto * BCast = B . CreatePointerCast ( PtrArg , PtrTy ) ; SmallVector < Value * , <NUM_LIT> > Args ;

for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) Args . push_back ( CI -> getArgOperand ( I ) ) ;


<s> __inline__ static void sh_media_STHI_L ( void * p , int s , unsigned int mw ) {

__asm__ ( <STR_LIT> : <STR_LIT> ( ( ( char * ) p ) [ s ] ) : <STR_LIT> ( mw ) ) ;


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , Register SwiftErrorVReg ) const { assert ( ( ( Val && ! VRegs . empty ( ) ) || ( ! Val && VRegs . empty ( ) ) ) && <STR_LIT> ) ; if ( VRegs . size ( ) > <NUM_LIT> ) return false ; MIRBuilder . buildInstr ( <STR_LIT> ) ; return true ;


<s> unsigned IsPCRel = <NUM_LIT> ; if ( auto * SymB = Target . getSymB ( ) ) { uint32_t FixupAddress = Writer -> getFragmentAddress ( Fragment , Layout ) + Fixup . getOffset ( ) ; IsPCRel = <NUM_LIT> ; FixedValue = FixupAddress - Writer -> getSymbolAddress ( SymB -> getSymbol ( ) , Layout ) + Target . getConstant ( ) ; FixedValue += <NUM_LIT> << Log2Size ; } else { FixedValue = <NUM_LIT> ;


<s> static DecodeStatus DecodeSPE4RCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {

return decodeRegisterClass ( Inst , RegNo , RRegs ) ;


<s> enum machine_mode mode = GET_MODE ( x ) == VOIDmode ? GET_MODE ( y ) : GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ? DFmode : DImode ; if ( ! mmix_valid_comparison ( code , mode , x ) ) return NULL_RTX ; cc_reg = gen_reg_rtx ( ccmode ) ; if ( ! REG_P ( x ) && ! REG_P ( y ) ) x = force_reg ( mode , x ) ;

if ( ! REG_P ( y ) && ( GET_CODE ( y ) != CONST_INT || ! CONST_OK_FOR_LETTER_P ( INTVAL ( y ) , 'I' ) ) ) y = force_reg ( mode , y ) ;


<s> SDValue rdx = DAG . getCopyFromReg ( rax . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , <STR_LIT> , rax . getValue ( <NUM_LIT> ) ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , rdx , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , rax , Tmp ) , rdx . getValue ( <NUM_LIT> ) } ;

return DAG . getMergeValues ( Ops , <NUM_LIT> , dl ) ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > Catches ; for ( auto & MBB : MF ) for ( auto & MI : MBB ) if ( <STR_LIT> ( MI . getOpcode ( ) ) ) Catches . push_back ( & MI ) ; for ( auto * Catch : Catches ) { MachineBasicBlock * EHPad = getMatchingEHPad ( Catch ) ; assert ( EHPad && <STR_LIT> ) ; auto InsertPos = EHPad -> begin ( ) ; while ( InsertPos != EHPad -> end ( ) && InsertPos -> isEHLabel ( ) ) InsertPos ++ ;


<s> case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None : break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM : return <STR_LIT> ; } unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> pminub ( uint8x8_t s , uint8x8_t t ) {

return __builtin_loongson_pminub ( s , t ) ;


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: EABI || TargetTriple . getEnvironment ( ) == Triple :: EABIHF ) && ! isTargetDarwin ( ) ;


<s> bool <ISA_LIT>AsmParser :: parseSSectionDirective ( StringRef Section , unsigned Type ) { if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ;


<s> const auto & F = MF . getFunction ( ) ; const auto & MFI = MF . getFrameInfo ( ) ; const auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; assert ( ! MFI . hasVarSizedObjects ( ) && ! HST . getRegisterInfo ( ) -> needsStackRealignment ( MF ) ) ;

return F . hasFnAttribute ( Attribute :: NoReturn ) && F . hasFnAttribute ( Attribute :: NoUnwind ) && ! F . hasFnAttribute ( Attribute :: UWTable ) && HST . noreturnStackElim ( ) && MFI . getStackSize ( ) == <NUM_LIT> ;


<s> } if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , PtrVT ) ; Disp = CurDAG -> getTargetConstant ( RHSC , dl , <STR_LIT> ) ; return true ; } MVT VT = cast < MemSDNode > ( Op ) -> getMemoryVT ( ) . getSimpleVT ( ) ; if ( isUInt < <NUM_LIT> > ( RHSC ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = CurDAG -> getTargetConstant ( RHSC , dl , <STR_LIT> ) ; return true ; } }


<s> State . PrefixSaved = <NUM_LIT> ; State . PrefixPass = false ;


<s> IRBuilder < > Builder ( & BB ) ; for ( auto & I : make_early_inc_range ( BB ) ) { if ( I . getOpcode ( ) == Instruction :: FNeg ) { Builder . SetInsertPoint ( & I ) ; Value * In = I . getOperand ( <NUM_LIT> ) ; Value * Zero = ConstantFP :: get ( In -> getType ( ) , - <NUM_LIT> ) ; I . replaceAllUsesWith ( Builder . CreateFSub ( Zero , In ) ) ; I . eraseFromParent ( ) ; continue ; } if ( ! M . getContext ( ) . hasSetOpaquePointersValue ( ) ) continue ; if ( auto LI = dyn_cast < LoadInst > ( & I ) ) { if ( Value * NoOpBitcast = maybeGenerateBitcast ( Builder , PointerTypes , I , LI -> getPointerOperand ( ) , LI -> getType ( ) ) ) { LI -> replaceAllUsesWith ( Builder . CreateLoad ( LI -> getType ( ) , NoOpBitcast ) ) ; LI -> eraseFromParent ( ) ; } continue ; } if ( auto SI = dyn_cast < StoreInst > ( & I ) ) { if ( Value * NoOpBitcast = maybeGenerateBitcast ( Builder , PointerTypes , I , SI -> getPointerOperand ( ) , SI -> getValueOperand ( ) -> getType ( ) ) ) { SI -> replaceAllUsesWith ( Builder . CreateStore ( SI -> getValueOperand ( ) , NoOpBitcast ) ) ; SI -> eraseFromParent ( ) ; } continue ;


<s> bool i386_pe_type_dllimport_p ( tree ) {


<s> unsigned stkSze = MF -> getFrameInfo ( ) -> getStackSize ( ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( <ISA_LIT>InstPrinter :: getRegisterName ( stkReg ) ) + <STR_LIT> + Twine ( stkSze ) + <STR_LIT> + Twine ( <ISA_LIT>InstPrinter :: getRegisterName ( retReg ) ) ) ;


<s> } unsigned TmpBasereg = Basereg ; if ( CSRs . size ( ) > <NUM_LIT> && ( ( ( AddedSize + Offset ) - Scale ) > ( uint64_t ) Scale * <NUM_LIT> ) ) { TmpBasereg = adjustRegBySVE ( MF , MBB , MBBI , DL , Basereg , <NUM_LIT> , false ) ; Offset = <NUM_LIT> ;


<s> static Register getFPReg ( const <ISA_LIT>Subtarget & STI ) { return <STR_LIT> ;


<s> Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : { SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , SetCC ) ; return Sum ; } } SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Cond , <STR_LIT> ) , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , SetCC ) ;


<s> if ( ! TARGET_TOC ) return false ; if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( strict && ! ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , <NUM_LIT> ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , <NUM_LIT> ) , strict ) ) ) return false ; if ( GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , <NUM_LIT> ) ; } tocrel_base = op ; tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , <NUM_LIT> ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , <NUM_LIT> ) ; tocrel_offset = XEXP ( op , <NUM_LIT> ) ; } return ( GET_CODE ( tocrel_base ) == UNSPEC && XINT ( tocrel_base , <NUM_LIT> ) == UNSPEC_TOCREL ) ;


<s> O << MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> static MCDisassembler * create<ISA_LIT>LEDisassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) {

return new <ISA_LIT>Disassembler ( STI , Ctx , true ) ;


<s> if ( ResTy != MatchOperand_NoMatch ) return ResTy ; ResTy = ParseAnyRegister ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; const MCExpr * Expr = nullptr ;

if ( Parser . parseExpression ( Expr ) ) {


<s> PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , Fast ) ) ;


<s> return decodeRegisterClass ( Inst , RegNo , CRRegs ) ;


<s> bool isSImm9Lsb0 ( ) const { return isBareSimmNLsb0 < <NUM_LIT> > ( ) ;


<s> if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Name ) ; getStreamer ( ) . emitSymbolAttribute ( Sym , MCSA_Global ) ; return false ;


<s> int <ISA_LIT>TTIImpl :: getInterleavedMemoryOpCostAVX512 ( unsigned Opcode , Type * VecTy , unsigned Factor , ArrayRef < unsigned > Indices , unsigned Alignment , unsigned AddressSpace , bool UseMaskForCond , bool UseMaskForGaps ) { if ( UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ; MVT LegalVT = getTLI ( ) -> getTypeLegalizationCost ( DL , VecTy ) . second ; unsigned VecTySize = DL . getTypeStoreSize ( VecTy ) ; unsigned LegalVTSize = LegalVT . getStoreSize ( ) ; unsigned NumOfMemOps = ( VecTySize + LegalVTSize - <NUM_LIT> ) / LegalVTSize ; auto * SingleMemOpTy = VectorType :: get ( cast < VectorType > ( VecTy ) -> getElementType ( ) , LegalVT . getVectorNumElements ( ) ) ; unsigned MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , MaybeAlign ( Alignment ) , AddressSpace ) ; unsigned VF = cast < VectorType > ( VecTy ) -> getNumElements ( ) / Factor ; MVT VT = <STR_LIT> ( <STR_LIT> ( VecTy -> getScalarType ( ) ) , VF ) ; if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; unsigned ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ;

Type * ResultTy = VectorType :: get ( cast < VectorType > ( VecTy ) -> getElementType ( ) , cast < VectorType > ( VecTy ) -> getNumElements ( ) / Factor ) ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> } } if ( needsRegArgSlots && TFI . hasReservedCallFrame ( MF ) ) MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , <NUM_LIT> , <NUM_LIT> ) ; else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; } if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag , dl ) ; if ( ! Ins . empty ( ) ) InFlag = Chain . getValue ( <NUM_LIT> ) ;

return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , dl , DAG , InVals ) ;


<s> CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; MadeChange |= RemoveUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= HandleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= FixUpImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= OptimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= UndoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) {

const CPEntry & CPE = CPEntries [ i ] [ j ] ;


<s> return Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ;


<s> invert_find_roots ( Nodes , NCM , Roots ) ; for ( NodeVect :: iterator I = Roots . begin ( ) , E = Roots . end ( ) ; I != E ; ++ I ) recalculatePlacementRec ( * I , NCM , Loc ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << LocationAsBlock ( Loc ) ) ;


<s> far = <NUM_LIT> ; jump = <STR_LIT> <STR_LIT> <STR_LIT> ; } else { far = <NUM_LIT> ; if ( flag_pic ) { if ( TARGET_SH2 ) jump = <STR_LIT> <STR_LIT> <STR_LIT> ; else jump = <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ; } else jump = <STR_LIT> <STR_LIT> <STR_LIT> ; } if ( NONJUMP_INSN_P ( ( prev = prev_nonnote_insn ( insn ) ) ) && INSN_CODE ( prev ) == CODE_FOR_indirect_jump_scratch ) { this_jmp . reg = SET_DEST ( XVECEXP ( PATTERN ( prev ) , <NUM_LIT> , <NUM_LIT> ) ) ; if ( REGNO ( this_jmp . reg ) == R0_REG && flag_pic && ! TARGET_SH2 ) jump = <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ; output_asm_insn ( jump , & this_jmp . lab ) ; if ( dbr_sequence_length ( ) ) print_slot ( final_sequence ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } else { if ( dbr_sequence_length ( ) ) print_slot ( final_sequence ) ; this_jmp . reg = gen_rtx_REG ( SImode , <NUM_LIT> ) ; if ( TARGET_SH5 ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( jump , & this_jmp . lab ) ; if ( TARGET_SH5 ) output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } if ( far && flag_pic && TARGET_SH2 ) { braf_base_lab = gen_label_rtx ( ) ;

( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( braf_base_lab ) ) ;


<s> if ( isVarArg && Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; int BytesCalleePops = ( CallConv == CallingConv :: Fast && getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) -> setHasTailCall ( ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( & BranchRelaxationPassID ) ;


<s> assert ( Op . getValueType ( ) . is128BitVector ( ) && Op . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Val = DAG . getUNDEF ( <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Val ) ;


<s> for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ;

const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , AB , CE , OS ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; S -> getAssembler ( ) . setIncrementalLinkerCompatible ( IncrementalLinkerCompatible ) ; return S ;


<s> if ( strlen ( Original -> Code ) * ( Original -> BranchesIn . size ( ) - <NUM_LIT> ) > TotalCodeSize / RelooperSplittingFactor ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << Original -> Code << <STR_LIT> ) ; for ( const auto & Prior : Original -> BranchesIn ) { Block * Split = new Block ( Original -> Code , Original -> BranchVar ) ; Parent -> AddBlock ( Split , Original -> Id ) ; Split -> BranchesIn . insert ( Prior ) ; std :: unique_ptr < Branch > Details ;

Details . swap ( Prior -> BranchesOut [ Original ] ) ;


<s> case <NUM_LIT> : break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; case <STR_LIT> : MCE . emitByte ( <NUM_LIT> ) ; break ; }


<s> OperandMatchResultTy parseAR32 ( OperandVector & Operands ) {

return parseRegister ( Operands , AR32Reg ) ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ;


<s> Operands . push_back ( <STR_LIT> ( Name , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( parseOperand ( Operands , Name ) != MatchOperand_Success ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) != MatchOperand_Success ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT> ) ;


<s> if ( ! MI . mayLoad ( ) ) return <STR_LIT> ; if ( isMUBUF ( MI ) || isVGPRSpill ( MI ) ) return isStackAccess ( MI , FrameIndex ) ; if ( isSGPRSpill ( MI ) ) return isSGPRStackAccess ( MI , FrameIndex ) ; return <STR_LIT> ;


<s> if ( ISA_HAS_SEB_SEH || GENERATE_MIPS16E ) return COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI . getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI . setObjectAlignment ( RPI . FrameIdx , <NUM_LIT> ) ;

AFI -> setCalleeSaveStackHasFreeSpace ( true ) ;


<s> for ( int Idx = <NUM_LIT> ; * CURegs ; ++ CURegs , ++ Idx ) if ( * CURegs == Reg ) return Idx ;


<s> } else { Insert = L -> getHeader ( ) -> getFirstNonPHIOrDbgOrLifetime ( ) ; } Value * Args [ ] = { Cond , Broken } ; return CallInst :: Create ( IfBreak , Args , <STR_LIT> , Insert ) ; }


<s> static std :: atomic < bool > FoldTablesChecked ( false ) ; if ( ! FoldTablesChecked . load ( std :: memory_order_relaxed ) ) { assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable2Addr ) , std :: end ( MemoryFoldTable2Addr ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable2Addr ) , std :: end ( MemoryFoldTable2Addr ) ) == std :: end ( MemoryFoldTable2Addr ) && <STR_LIT> ) ;

assert ( std :: is_sorted ( std :: begin ( MemoryFoldTable0 ) , std :: end ( MemoryFoldTable0 ) ) && std :: adjacent_find ( std :: begin ( MemoryFoldTable0 ) , std :: end ( MemoryFoldTable0 ) ) == std :: end ( MemoryFoldTable0 ) && <STR_LIT> ) ;


<s> iter = Next ; } } Multiple -> InnerMap [ CurrEntry -> Id ] = Process ( CurrBlocks , CurrEntries , nullptr ) ; if ( ! Fused ) CurrEntry -> IsCheckedMultipleEntry = true ; } for ( const auto & Entry : Entries ) if ( ! contains ( IndependentGroups , Entry ) ) NextEntries . insert ( Entry ) ; if ( Multiple -> InnerMap . size ( ) >= RelooperMultipleSwitchThreshold ) { Multiple -> UseSwitch = true ;


<s> static unsigned getDepthOfOptCmov ( unsigned TrueOpDepth , unsigned FalseOpDepth ) {

return std :: max ( divideCeil ( TrueOpDepth * <NUM_LIT> + FalseOpDepth , <NUM_LIT> ) , divideCeil ( FalseOpDepth * <NUM_LIT> + TrueOpDepth , <NUM_LIT> ) ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


Inst . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> static int epiphany_mode_entry_exit ( int entity , bool exit ) { int normal_mode = epiphany_normal_fp_mode ; MACHINE_FUNCTION ( cfun ) -> sw_entities_processed |= ( <NUM_LIT> << entity ) ; if ( epiphany_is_interrupt_p ( current_function_decl ) ) normal_mode = FP_MODE_CALLER ; switch ( entity ) { case EPIPHANY_MSW_ENTITY_AND : if ( exit ) return normal_mode != FP_MODE_INT ? <NUM_LIT> : <NUM_LIT> ;


<s> BBGen = make_unique < const MachineInstr * [ ] > ( NbReg ) ; std :: fill ( BBGen . get ( ) , BBGen . get ( ) + NbReg , nullptr ) ; BitVector & BBKillSet = Kill [ & MBB ] ; BBKillSet . resize ( NbReg ) ; for ( const MachineInstr & MI : MBB ) { bool IsADRP = MI . getOpcode ( ) == <STR_LIT> ; if ( IsADRP || ! ADRPMode ) for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ( ! ADRPMode && ! MO . isUse ( ) ) || ( ADRPMode && ( ! IsADRP || ! MO . isDef ( ) ) ) ) continue ; unsigned CurReg = MO . getReg ( ) ; MapRegToId :: const_iterator ItCurRegId = RegToId . find ( CurReg ) ; if ( ItCurRegId == RegToId . end ( ) ) continue ; CurReg = ItCurRegId -> second ; if ( ! BBGen [ CurReg ] && ! BBKillSet . test ( CurReg ) ) getSet ( ReachableUses , MBB , CurReg , NbReg ) . insert ( & MI ) ; if ( BBGen [ CurReg ] ) getUses ( ColorOpToReachedUses , CurReg , * BBGen [ CurReg ] ) . insert ( & MI ) ; } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isRegMask ( ) ) continue ; const uint32_t * PreservedRegs = MO . getRegMask ( ) ; for ( const auto Entry : RegToId ) { unsigned Reg = Entry . second ; if ( MachineOperand :: clobbersPhysReg ( PreservedRegs , Entry . first ) ) { BBGen [ Reg ] = ADRPMode ? & MI : nullptr ; BBKillSet . set ( Reg ) ; } } } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned CurReg = MO . getReg ( ) ; MapRegToId :: const_iterator ItCurRegId = RegToId . find ( CurReg ) ; if ( ItCurRegId == RegToId . end ( ) ) continue ; for ( MCRegAliasIterator AI ( CurReg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) { MapRegToId :: const_iterator ItRegId = RegToId . find ( * AI ) ; assert ( ItRegId != RegToId . end ( ) && <STR_LIT> <STR_LIT> ) ; BBKillSet . set ( ItRegId -> second ) ; BBGen [ ItRegId -> second ] = & MI ;


<s> PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>CTRLoopsVerifyPass ( PR ) ; initialize<ISA_LIT>LoopPreIncPrepPass ( PR ) ; initialize<ISA_LIT>TOCRegDepsPass ( PR ) ; initialize<ISA_LIT>EarlyReturnPass ( PR ) ; initialize<ISA_LIT>VSXCopyPass ( PR ) ; initialize<ISA_LIT>VSXFMAMutatePass ( PR ) ; initialize<ISA_LIT>VSXSwapRemovalPass ( PR ) ; initialize<ISA_LIT>ReduceCRLogicalsPass ( PR ) ; initialize<ISA_LIT>BSelPass ( PR ) ; initialize<ISA_LIT>BranchCoalescingPass ( PR ) ; initialize<ISA_LIT>QPXLoadSplatPass ( PR ) ; initialize<ISA_LIT>BoolRetToIntPass ( PR ) ; initialize<ISA_LIT>ExpandISELPass ( PR ) ; initialize<ISA_LIT>PreEmitPeepholePass ( PR ) ; initialize<ISA_LIT>TLSDynamicCallPass ( PR ) ;

initialize<ISA_LIT>MIPeepholePass ( PR ) ;


<s> bool isUnmovable [ <NUM_LIT> ] = { false , false , false , false } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { RemapSwizzle [ i ] = i ; if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) { unsigned Idx = dyn_cast < ConstantSDNode > ( NewBldVec [ i ] . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( i == Idx ) isUnmovable [ Idx ] = true ;


<s> unsigned CPIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPoolEntry & MCPE = ( * MCPEs ) [ CPIndex ] ; JTI -> addConstantPoolEntryAddr ( CPI , MCE . getCurrentPCValue ( ) ) ; if ( MCPE . isMachineConstantPoolEntry ( ) ) { <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE . Val . MachineCPVal ) ; DEBUG ( errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << * ACPV << '\n' ) ; assert ( ACPV -> isGlobalValue ( ) && <STR_LIT> ) ;

const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ;


<s> switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : if ( riscv_v_ext_vector_mode_p ( mode ) ) return false ; info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ;

info -> symbol_type = riscv_classify_symbolic_expression ( info -> offset ) ;


<s> bool epiphany_is_long_call_p ( rtx x ) { tree decl = SYMBOL_REF_DECL ( x ) ; bool ret_val = ! TARGET_SHORT_CALLS ; tree attrs ; if ( decl ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret_val = true ; else if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret_val = false ; } return ret_val ;


<s> if ( ! PrologueBB ) { PrologueBB = AI -> getParent ( ) ; continue ; } PrologueBB = DT -> findNearestCommonDominator ( PrologueBB , AI -> getParent ( ) ) ; } assert ( PrologueBB ) ; IRBuilder < > IRB ( & PrologueBB -> front ( ) ) ; Function * IRG_SP = <STR_LIT> ( F -> getParent ( ) , <STR_LIT> ) ; Instruction * Base = IRB . CreateCall ( IRG_SP , { Constant :: getNullValue ( IRB . getInt64Ty ( ) ) } ) ; Base -> setName ( <STR_LIT> ) ; return Base ;


<s> switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : case CCValAssign :: ZExt : case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;

RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


<s> addPass ( & PostRAHazardRecognizerID ) ; if ( Enable<ISA_LIT>InsertWaitcntsPass ) addPass ( create<ISA_LIT>InsertWaitcntsPass ( ) ) ; else addPass ( create<ISA_LIT>InsertWaitsPass ( ) ) ;

addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ;


<s> const EVT OpTy = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpTy == <STR_LIT> ) NewTy = <STR_LIT> ; else if ( OpTy == <STR_LIT> && HasFullFP16 ) NewTy = <STR_LIT> ; else if ( OpTy == <STR_LIT> && HasFullFP16 ) NewTy = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return DAG . UnrollVectorOp ( Op . getNode ( ) ) ;

Op = DAG . getNode ( Op . getOpcode ( ) , dl , NewTy , Op . getOperand ( <NUM_LIT> ) ) ;


<s> const Function & F = MF . getFunction ( ) ; unsigned StackProbeSize = <NUM_LIT> ;

if ( F . hasFnAttribute ( <STR_LIT> ) ) F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ;


<s> return ( CRIS_CONSTANT_P ( x ) && ( ! flag_pic || cris_valid_pic_const ( x , true ) ) ) ;


<s> SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OpHi ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget -> hasInt256 ( ) ) { In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; SmallVector < SDValue , <NUM_LIT> > pshufbMask ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue BV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & pshufbMask [ <NUM_LIT> ] , <NUM_LIT> ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , BV ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT> ) , & ShufMask [ <NUM_LIT> ] ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OpLo ) ;


<s> if ( ! Subtarget -> hasFPARMv8 ( ) ) break ; if ( VT . isScalableVector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } else { PredicateConstraint PC = parsePredicateConstraint ( Constraint ) ; if ( PC != PredicateConstraint :: Invalid ) { assert ( VT . isScalableVector ( ) ) ; bool restricted = ( PC == PredicateConstraint :: Upl ) ; return restricted ? std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) : std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && Constraint [ <NUM_LIT> ] == '{' && tolower ( Constraint [ <NUM_LIT> ] ) == 'v' && Constraint [ Size - <NUM_LIT> ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( <NUM_LIT> , Size - <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , RegNo ) ; if ( ! Failed && RegNo >= <NUM_LIT> && RegNo <= <NUM_LIT> ) { if ( VT != <STR_LIT> && VT . getSizeInBits ( ) == <NUM_LIT> ) { Res . first = <STR_LIT> . getRegister ( RegNo ) ; Res . second = & <STR_LIT> ; } else { Res . first = <STR_LIT> . getRegister ( RegNo ) ; Res . second = & <STR_LIT> ; } } } }

if ( Res . second && ! Subtarget -> hasFPARMv8 ( ) && ! <STR_LIT> . hasSubClassEq ( Res . second ) && ! <STR_LIT> . hasSubClassEq ( Res . second ) ) return std :: make_pair ( <NUM_LIT> , nullptr ) ;


<s> MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; InstrumentMOVSBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , AccessSize , Ctx , Out ) ; EmitLabel ( Out , DoneSym ) ;


<s> std :: set < Instruction * > worklist ; for ( inst_iterator I = inst_begin ( F ) , E = inst_end ( F ) ; I != E ; ++ I ) { PtrToIntInst * PTI = dyn_cast < PtrToIntInst > ( & * I ) ; IntToPtrInst * ITP = dyn_cast < IntToPtrInst > ( & * I ) ; if ( ! ( PTI && <STR_LIT> ( PTI -> getPointerOperand ( ) -> getType ( ) ) ) && ! ( ITP && <STR_LIT> ( ITP -> getDestTy ( ) ) ) ) continue ; UndefValue * U = UndefValue :: get ( I -> getType ( ) ) ; I -> replaceAllUsesWith ( U ) ; Function * TrapIntrin = <STR_LIT> ( F . getParent ( ) , <STR_LIT> ) ; CallInst :: Create ( TrapIntrin , { } , <STR_LIT> , & * I ) ; worklist . insert ( & * I ) ; } for ( Instruction * I : worklist ) I -> eraseFromParent ( ) ;


<s> if ( I . isExpr ( ) && cast < <ISA_LIT>MCExpr > ( I . getExpr ( ) ) -> signMismatch ( ) && WarnSignedMismatch ) Warning ( MCI . getLoc ( ) , <STR_LIT> ) ; NewInst . addOperand ( I ) ; }


return __builtin_mve_vcvtpq_m_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __p ) ;


return ( EncVal << <NUM_LIT> ) | ( EncVal << <NUM_LIT> ) ;


<s> getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { { s32 , s32 } } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalForCartesianProduct ( { s32 } , { s32 , p0 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_GEP , G_INTTOPTR } ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalFor ( { { s32 , p0 } } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( { G_GLOBAL_VALUE , G_JUMP_TABLE } ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV , G_FABS , G_FSQRT } ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FCMP ) . legalFor ( { { s32 , s32 } , { s32 , s64 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_FCEIL , G_FFLOOR } ) . libcallFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( G_FPEXT ) . legalFor ( { { s64 , s32 } } ) ; getActionDefinitionsBuilder ( G_FPTRUNC ) . legalFor ( { { s32 , s64 } } ) ; getActionDefinitionsBuilder ( G_FPTOSI ) . legalForCartesianProduct ( { s32 } , { s64 , s32 } ) . libcallForCartesianProduct ( { s64 } , { s64 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_FPTOUI ) . libcallForCartesianProduct ( { s64 } , { s64 , s32 } ) . lowerForCartesianProduct ( { s32 } , { s64 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SITOFP ) . legalForCartesianProduct ( { s64 , s32 } , { s32 } ) . libcallForCartesianProduct ( { s64 , s32 } , { s64 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_UITOFP ) . libcallForCartesianProduct ( { s64 , s32 } , { s64 } ) . customForCartesianProduct ( { s64 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) ;

getActionDefinitionsBuilder ( G_SEXT_INREG ) . lower ( ) ;


<s> return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


<s> if ( ! Parse<ISA_LIT>Register ( RegKind , Reg , RegNum , RegWidth , & DwordRegIndex ) ) { return nullptr ; } KernelScope . usesRegister ( RegKind , DwordRegIndex , RegWidth ) ; return <ISA_LIT>Operand :: CreateReg ( this , Reg , StartLoc , EndLoc , false ) ;


<s> switch ( CC ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( SPR_P ( REGNO ( reg ) ) ) { rtx temp = gen_rtx_REG ( mode , TEMP_REGNO ) ; emit_insn ( gen_rtx_SET ( VOIDmode , temp , reg ) ) ; frv_frame_insn ( gen_rtx_SET ( Pmode , mem , temp ) , frv_dwarf_store ( reg , stack_offset ) ) ; } else if ( GET_MODE ( reg ) == DImode ) { rtx reg1 = gen_rtx_REG ( SImode , REGNO ( reg ) ) ; rtx reg2 = gen_rtx_REG ( SImode , REGNO ( reg ) + <NUM_LIT> ) ; rtx set1 = frv_dwarf_store ( reg1 , stack_offset ) ; rtx set2 = frv_dwarf_store ( reg2 , stack_offset + <NUM_LIT> ) ; frv_frame_insn ( gen_rtx_SET ( Pmode , mem , reg ) , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set1 , set2 ) ) ) ; }

else frv_frame_insn ( gen_rtx_SET ( Pmode , mem , reg ) , frv_dwarf_store ( reg , stack_offset ) ) ;


<s> return ( GV -> getValueType ( ) -> isFunctionTy ( ) || ! isNonGlobalAddrSpace ( GV -> getAddressSpace ( ) ) ) && ! shouldEmitFixup ( GV ) && ! getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> auto * PromEltTy = IntegerType :: getIntNTy ( EltTy -> getContext ( ) , PromEltTyBits ) ; auto * SrcVecTy = FixedVectorType :: get ( EltTy , VF ) ; auto * PromSrcVecTy = FixedVectorType :: get ( PromEltTy , VF ) ; int NumDstElements = VF * ReplicationFactor ; auto * PromDstVecTy = FixedVectorType :: get ( PromEltTy , NumDstElements ) ; auto * DstVecTy = FixedVectorType :: get ( EltTy , NumDstElements ) ; MVT LegalSrcVecTy = TLI -> getTypeLegalizationCost ( DL , SrcVecTy ) . second ; MVT LegalPromSrcVecTy = TLI -> getTypeLegalizationCost ( DL , PromSrcVecTy ) . second ; MVT LegalPromDstVecTy = TLI -> getTypeLegalizationCost ( DL , PromDstVecTy ) . second ; MVT LegalDstVecTy = TLI -> getTypeLegalizationCost ( DL , DstVecTy ) . second ; if ( ! LegalSrcVecTy . isVector ( ) || ! LegalPromSrcVecTy . isVector ( ) || ! LegalPromDstVecTy . isVector ( ) || ! LegalDstVecTy . isVector ( ) ) return bailout ( ) ; if ( PromEltTyBits != EltTyBits ) { InstructionCost PromotionCost ; PromotionCost += getCastInstrCost ( Instruction :: SExt , PromSrcVecTy , SrcVecTy , TargetTransformInfo :: CastContextHint :: None , CostKind ) ; PromotionCost += getCastInstrCost ( Instruction :: Trunc , DstVecTy , PromDstVecTy , TargetTransformInfo :: CastContextHint :: None , CostKind ) ; return PromotionCost + getReplicationShuffleCost ( PromEltTy , ReplicationFactor , VF , DemandedDstElts , CostKind ) ;


<s> unsigned VF = SrcVecTy -> getNumElements ( ) ; unsigned NumDstVectors = getNumVectorRegs ( Dst ) ; unsigned NumSrcVectors = getNumVectorRegs ( Src ) ; if ( Opcode == Instruction :: Trunc ) { if ( Src -> getScalarSizeInBits ( ) == Dst -> getScalarSizeInBits ( ) ) return <NUM_LIT> ; return getVectorTruncCost ( Src , Dst ) ; } if ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) { if ( SrcScalarBits >= <NUM_LIT> ) { unsigned NumUnpacks = getElSizeLog2Diff ( Src , Dst ) ; unsigned NumSrcVectorOps = ( NumUnpacks > <NUM_LIT> ? ( NumDstVectors - NumSrcVectors ) : ( NumDstVectors / <NUM_LIT> ) ) ; return ( NumUnpacks * NumDstVectors ) + NumSrcVectorOps ; } else if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) ; } if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP || Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) { if ( DstScalarBits == <NUM_LIT> || ST -> hasVectorEnhancements2 ( ) ) { if ( SrcScalarBits == DstScalarBits ) return NumDstVectors ; if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) + NumDstVectors ; } InstructionCost ScalarCost = getCastInstrCost ( Opcode , Dst -> getScalarType ( ) , Src -> getScalarType ( ) , CCH , CostKind ) ; InstructionCost TotCost = VF * ScalarCost ; bool NeedsInserts = true , NeedsExtracts = true ; if ( DstScalarBits == <NUM_LIT> && ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP ) ) NeedsInserts = false ; if ( SrcScalarBits == <NUM_LIT> && ( Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) ) NeedsExtracts = false ; TotCost += getScalarizationOverhead ( SrcVecTy , false , NeedsExtracts ) ; TotCost += getScalarizationOverhead ( DstVecTy , NeedsInserts , false ) ; if ( VF == <NUM_LIT> && SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) TotCost *= <NUM_LIT> ; return TotCost ; } if ( Opcode == Instruction :: FPTrunc ) { if ( SrcScalarBits == <NUM_LIT> ) return VF + getScalarizationOverhead ( DstVecTy , true , false ) ; else return VF / <NUM_LIT> + std :: max ( <NUM_LIT> , VF / <NUM_LIT> ) ; } if ( Opcode == Instruction :: FPExt ) { if ( SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) { return VF * <NUM_LIT> ; }

return VF + getScalarizationOverhead ( SrcVecTy , false , true ) ;


<s> if ( ! TII -> getNamedOperand ( MI , <STR_LIT> :: clamp ) -> getImm ( ) ) return nullptr ; const MachineOperand * Src0 = TII -> getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src1 = TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( ! Src0 -> isReg ( ) || ! Src1 -> isReg ( ) || Src0 -> getSubReg ( ) != Src1 -> getSubReg ( ) || Src0 -> getSubReg ( ) != <STR_LIT> ) return nullptr ; if ( TII -> hasModifiersSet ( MI , <STR_LIT> :: omod ) ) return nullptr ; unsigned Src0Mods = TII -> getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) -> getImm ( ) ; unsigned Src1Mods = TII -> getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) -> getImm ( ) ; unsigned UnsetMods = ( Op == <STR_LIT> ) ? <STR_LIT> : <NUM_LIT> ; if ( Src0Mods != UnsetMods && Src1Mods != UnsetMods ) return nullptr ; return Src0 ;


<s> <ISA_LIT>AsmInstrumentation :: ~ <ISA_LIT>AsmInstrumentation ( ) {


<s> case ImmTyOffset1 : OS << <STR_LIT> ; break ; case ImmTyGLC : OS << <STR_LIT> ; break ; case ImmTySLC : OS << <STR_LIT> ; break ; case ImmTyTFE : OS << <STR_LIT> ; break ; case ImmTyD16 : OS << <STR_LIT> ; break ; case ImmTyFORMAT : OS << <STR_LIT> ; break ; case ImmTyClamp<ISA_LIT> : OS << <STR_LIT> ; break ; case ImmTyOMod<ISA_LIT> : OS << <STR_LIT> ; break ; case ImmTyDppCtrl : OS << <STR_LIT> ; break ; case ImmTyDppRowMask : OS << <STR_LIT> ; break ; case ImmTyDppBankMask : OS << <STR_LIT> ; break ; case ImmTyDppBoundCtrl : OS << <STR_LIT> ; break ; case ImmTySdwaDstSel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc0Sel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc1Sel : OS << <STR_LIT> ; break ; case ImmTySdwaDstUnused : OS << <STR_LIT> ; break ; case ImmTyDMask : OS << <STR_LIT> ; break ; case ImmTyUNorm : OS << <STR_LIT> ; break ; case ImmTyDA : OS << <STR_LIT> ; break ; case ImmTyR128 : OS << <STR_LIT> ; break ; case ImmTyLWE : OS << <STR_LIT> ; break ; case ImmTyOff : OS << <STR_LIT> ; break ; case ImmTyExpTgt : OS << <STR_LIT> ; break ; case ImmTyExpCompr : OS << <STR_LIT> ; break ; case ImmTyExpVM : OS << <STR_LIT> ; break ; case ImmTyHwreg : OS << <STR_LIT> ; break ; case ImmTySendMsg : OS << <STR_LIT> ; break ;

case ImmTyInterpSlot : OS << <STR_LIT> ; break ;


<s> else Params . push_back ( iPTR ) ; for ( Type * Ty : FuncTy -> params ( ) ) { SmallVector < MVT , <NUM_LIT> > ParamMVTs ; ComputeLegalValueVTs ( CurrentFunc , TM , Ty , ParamMVTs ) ; for ( MVT ParamMVT : ParamMVTs ) Params . push_back ( <STR_LIT> ( ParamMVT ) ) ; } if ( FuncTy -> isVarArg ( ) ) Params . push_back ( iPTR ) ; WasmSym -> setReturns ( std :: move ( Returns ) ) ; WasmSym -> setParams ( std :: move ( Params ) ) ; WasmSym -> setIsFunction ( true ) ; } return WasmSym ;


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II ) ; return ; } if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVESpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerVRSAVERestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool isIXAddr = usesIXAddr ( MI ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI -> getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI -> getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && ( ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) {

MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


<s> bool <ISA_LIT>HardwareLoops :: orderBumpCompare ( MachineInstr * BumpI , MachineInstr * CmpI ) { assert ( BumpI != CmpI && <STR_LIT> ) ; MachineBasicBlock * BB = BumpI -> getParent ( ) ; if ( CmpI -> getParent ( ) != BB ) return false ; typedef MachineBasicBlock :: instr_iterator instr_iterator ; for ( instr_iterator I ( BumpI ) , E = BB -> instr_end ( ) ; I != E ; ++ I ) if ( & * I == CmpI ) return true ; unsigned PredR = CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool FoundBump = false ; instr_iterator CmpIt = CmpI -> getIterator ( ) , NextIt = std :: next ( CmpIt ) ; for ( instr_iterator I = NextIt , E = BB -> instr_end ( ) ; I != E ; ++ I ) { MachineInstr * In = & * I ; for ( unsigned i = <NUM_LIT> , n = In -> getNumOperands ( ) ; i < n ; ++ i ) { MachineOperand & MO = In -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isUse ( ) ) { if ( MO . getReg ( ) == PredR ) return false ; } } if ( In == BumpI ) { BB -> splice ( ++ BumpI -> getIterator ( ) , BB , CmpI -> getIterator ( ) ) ; FoundBump = true ; break ; } } assert ( FoundBump && <STR_LIT> ) ; return FoundBump ;


<s> if ( reg -> where == UNW_WHERE_NONE ) reg -> where = UNW_WHERE_GR_SAVE ; reg -> when = sr -> region_start + MIN ( ( int ) t , sr -> region_len - <NUM_LIT> ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createImm ( const MCExpr * Val , SMLoc S , SMLoc E ) {

auto Op = std :: make_unique < <ISA_LIT>Operand > ( Immediate ) ;


<s> case <STR_LIT> : return true ; } return false ;


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! MFI . hasStackObjects ( ) ) return ; bool MayNeedScavengingEmergencySlot = MFI . hasStackObjects ( ) ;

assert ( ( RS || ! MayNeedScavengingEmergencySlot ) && <STR_LIT> ) ;


<s> return __builtin_aarch64_urshlv16qi_uus ( __a , __b ) ;


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ;

printSOImm ( O , MO . getImm ( ) , VerboseAsm , MAI ) ;


<s> if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { NewDiv = UndefValue :: get ( VT ) ; for ( unsigned N = <NUM_LIT> , E = VT -> getNumElements ( ) ; N != E ; ++ N ) { Value * NumEltN = Builder . CreateExtractElement ( Num , N ) ; Value * DenEltN = Builder . CreateExtractElement ( Den , N ) ; Value * NewElt ; if ( ScalarSize <= <NUM_LIT> ) { NewElt = expandDivRem32 ( Builder , I , NumEltN , DenEltN ) ; if ( ! NewElt ) NewElt = Builder . CreateBinOp ( Opc , NumEltN , DenEltN ) ; } else { NewElt = shrinkDivRem64 ( Builder , I , NumEltN , DenEltN ) ; if ( ! NewElt ) { NewElt = Builder . CreateBinOp ( Opc , NumEltN , DenEltN ) ; Div64ToExpand . push_back ( cast < BinaryOperator > ( NewElt ) ) ; } } NewDiv = Builder . CreateInsertElement ( NewDiv , NewElt , N ) ; } } else { if ( ScalarSize <= <NUM_LIT> ) NewDiv = expandDivRem32 ( Builder , I , Num , Den ) ; else { NewDiv = shrinkDivRem64 ( Builder , I , Num , Den ) ; if ( ! NewDiv ) Div64ToExpand . push_back ( & I ) ; } } if ( NewDiv ) {


<s> BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { MachineInstr * MI = BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } } else { if ( is64bit ) BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( MBB , MBBI , dl , tm . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> if ( ! EltsFromConsecutiveLoads ( SVN , NumElems , EVT , Base , DAG , MFI , TLI ) ) return SDValue ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( Base ) ; if ( isBaseAlignmentOfN ( <NUM_LIT> , Base -> getOperand ( <NUM_LIT> ) . getNode ( ) , TLI ) ) return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) ) ;

return DAG . getLoad ( VT , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) , LD -> getAlignment ( ) ) ;


<s> bitmap_set_bit ( regs , split_stack_prologue_scratch_regno ( ) ) ; }


<s> } } if ( ! Subtarget -> isThumb1Only ( ) ) { SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ; if ( Result . getNode ( ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; APInt SplatBits0 ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; APInt SplatBits1 ; if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ; } } } if ( Subtarget -> isThumb1Only ( ) || ! Subtarget -> hasV6T2Ops ( ) ) return SDValue ( ) ; DebugLoc DL = N -> getDebugLoc ( ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue MaskOp = N0 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( MaskOp ) ; if ( ! MaskC ) return SDValue ( ) ; unsigned Mask = MaskC -> getZExtValue ( ) ; if ( Mask == <NUM_LIT> ) return SDValue ( ) ;


<s> int <ISA_LIT>InstrInfo :: GetDotNewOp ( const MachineInstr * MI ) const { int NVOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( Op . getValueType ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; EVT VT = <STR_LIT> ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> :


<s> ~ NaCl<ISA_LIT>_64AsmBackend ( ) override {


<s> SmallString < <NUM_LIT> > SubtargetKey ( GPU ) ; SubtargetKey . append ( FS ) ; auto & I = SubtargetMap [ SubtargetKey ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , GPU , FS , * this ) ;


<s> unsigned getCumLocs ( void ) const { return NumLocs + ChildrenMaxCumLocs ;


<s> __arm_vldrbq_u8 ( uint8_t const * __base ) {

return __builtin_mve_vldrbq_uv16qi ( ( __builtin_neon_qi * ) __base ) ;


<s> bool IsPIC = isPositionIndependent ( ) ; getLabelAccessInfo ( IsPIC , Subtarget , MOHiFlag , MOLoFlag ) ; SDValue TgtBAHi = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOHiFlag ) ; SDValue TgtBALo = DAG . getTargetBlockAddress ( BA , PtrVT , <NUM_LIT> , MOLoFlag ) ; return LowerLabelRef ( TgtBAHi , TgtBALo , IsPIC , DAG ) ;


<s> if ( extra < <NUM_LIT> ) extra = <NUM_LIT> ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ;

return offset + <NUM_LIT> < <NUM_LIT> - extra ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZ , false ) ; break ; case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , RealTimeProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; setAttributeItem ( MPextension_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZVirtualization , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( WMMX_arch , AllowWMMXv1 , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( WMMX_arch , AllowWMMXv2 , false ) ;


<s> ProgInfo . NumSGPR = Info . NumExplicitSGPR ; ProgInfo . ScratchSize = Info . PrivateSegmentSize ; ProgInfo . VCCUsed = Info . UsesVCC ; ProgInfo . FlatUsed = Info . UsesFlatScratch ; ProgInfo . DynamicCallStack = Info . HasDynamicallySizedStack || Info . HasRecursion ; const uint64_t MaxScratchPerWorkitem = GCNSubtarget :: MaxWaveScratchSize / STM . getWavefrontSize ( ) ; if ( ProgInfo . ScratchSize > MaxScratchPerWorkitem ) { DiagnosticInfoStackSize DiagStackSize ( MF . getFunction ( ) , ProgInfo . ScratchSize , MaxScratchPerWorkitem , DS_Error ) ; MF . getFunction ( ) . getContext ( ) . diagnose ( DiagStackSize ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ExtraSGPRs = IsaInfo :: getNumExtraSGPRs ( & STM , ProgInfo . VCCUsed , ProgInfo . FlatUsed ) ; if ( STM . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS && ! STM . hasSGPRInitBug ( ) ) { unsigned MaxAddressableNumSGPRs = STM . getAddressableNumSGPRs ( ) ; if ( ProgInfo . NumSGPR > MaxAddressableNumSGPRs ) { LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; DiagnosticInfoResourceLimit Diag ( MF . getFunction ( ) , <STR_LIT> , ProgInfo . NumSGPR , MaxAddressableNumSGPRs , DS_Error , DK_ResourceLimit ) ; Ctx . diagnose ( Diag ) ; ProgInfo . NumSGPR = MaxAddressableNumSGPRs - <NUM_LIT> ; } } ProgInfo . NumSGPR += ExtraSGPRs ; const Function & F = MF . getFunction ( ) ; unsigned WaveDispatchNumSGPR = <NUM_LIT> , WaveDispatchNumVGPR = <NUM_LIT> ; if ( isShader ( F . getCallingConv ( ) ) ) { bool IsPixelShader = F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS && ! STM . isAmdHsaOS ( ) ; uint32_t InputEna = <NUM_LIT> ; uint32_t InputAddr = <NUM_LIT> ; unsigned LastEna = <NUM_LIT> ; if ( IsPixelShader ) { InputEna = MFI -> getP<ISA_LIT>nputEnable ( ) ; InputAddr = MFI -> getP<ISA_LIT>nputAddr ( ) ; assert ( ( InputEna || InputAddr ) && <STR_LIT> <STR_LIT> ) ; LastEna = InputEna ? findLastSet ( InputEna ) + <NUM_LIT> : <NUM_LIT> ; } const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; unsigned PSArgCount = <NUM_LIT> ; unsigned IntermediateVGPR = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { unsigned NumRegs = ( DL . getTypeSizeInBits ( Arg . getType ( ) ) + <NUM_LIT> ) / <NUM_LIT> ; if ( Arg . hasAttribute ( Attribute :: InReg ) ) { WaveDispatchNumSGPR += NumRegs ; } else {

if ( IsPixelShader && PSArgCount < <NUM_LIT> ) {


<s> if ( isa < StructType > ( Ty ) ) return <STR_LIT> ; else if ( isa < ArrayType > ( Ty ) ) { Type * ElmTy = cast < ArrayType > ( Ty ) -> getElementType ( ) ; if ( isa < CompositeType > ( ElmTy ) ) return <STR_LIT> ; return GetLoadString ( ElmTy ) ; } else { const DataLayout & DL = MF -> getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * MF -> getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( MF -> getFunction ( ) ) . getTargetLowering ( ) ;

EVT VT = TLI . getValueType ( DL , Ty ) ;


<s> assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ;


<s> if ( ! SC -> isValid ( ) ) return <NUM_LIT> ; if ( SC -> BeginGroup ) { if ( CurrGroupSize ) return <NUM_LIT> - CurrGroupSize ; return - <NUM_LIT> ; } if ( SC -> EndGroup ) {

unsigned resultingGroupSize = ( CurrGroupSize + getNumDecoderSlots ( SU ) ) ;


<s> return ( __m64 ) __builtin_arm_wmaxsw ( ( __v2si ) __A , ( __v2si ) __B ) ;


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) { VT = <STR_LIT> ; } return VT . getSizeInBits ( ) ; }


<s> unsigned Op = Inst . getOpcode ( ) ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . x , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . y , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . y + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x , Call ) ; break ;