<s> if ( MBB . getNumber ( ) > <NUM_LIT> ) { unsigned AlignExtra = GetAlignmentAdjustment ( MBB , FuncSize ) ; auto & BS = BlockSizes [ MBB . getNumber ( ) - <NUM_LIT> ] ; BS . first += AlignExtra ; BS . second = AlignExtra ; FuncSize += AlignExtra ; } unsigned BlockSize = <NUM_LIT> ; unsigned UnalignedBytesRemaining = <NUM_LIT> ; for ( MachineInstr & MI : MBB ) { unsigned MINumBytes = TII -> getInstSizeInBytes ( MI ) ; if ( MI . isInlineAsm ( ) && ( FirstImpreciseBlock < <NUM_LIT> ) ) FirstImpreciseBlock = MBB . getNumber ( ) ; if ( TII -> isPrefixed ( MI . getOpcode ( ) ) ) { NumPrefixed ++ ; if ( ! UnalignedBytesRemaining ) { BlockSize += <NUM_LIT> ; UnalignedBytesRemaining = <NUM_LIT> ; NumPrefixedAligned ++ ; } } UnalignedBytesRemaining -= std :: min ( UnalignedBytesRemaining , MINumBytes ) ;


<s> tree aarch64_general_builtin_decl ( unsigned code , bool ) { if ( code >= AARCH64_BUILTIN_MAX ) return error_mark_node ;


<s> if ( Group ) Flags |= ELF :: SHF_GROUP ;

MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , FnSection . getUniqueID ( ) , static_cast < const MCSymbolELF * > ( & Fn ) ) ;


<s> unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ;

GlobalBaseReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ;


<s> if ( to == STACK_POINTER_REGNUM ) return ! frame_pointer_needed ;


<s> CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * RC ; EVT ValVT = VA . getValVT ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>SubTarget . hasVSX ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , ValVT == <STR_LIT> ? <STR_LIT> : ValVT ) ; if ( ValVT == <STR_LIT> ) ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned ArgSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI -> CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ) ; } } SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_SVR4_ByVal ) ; unsigned MinReservedArea = CCByValInfo . getNextStackOffset ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MinReservedArea = std :: max ( MinReservedArea , <ISA_LIT>FrameLowering :: getMinCallFrameSize ( false , false ) ) ; unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; MinReservedArea = ( MinReservedArea + AlignMask ) & ~ AlignMask ; FI -> setMinReservedArea ( MinReservedArea ) ;

SmallVector < SDValue , <NUM_LIT> > MemOps ;


<s> cfun -> machine -> gasisr . yes = <NUM_LIT> ; treg = avr_hregs_split_reg ( & set ) ; if ( treg < <NUM_LIT> ) treg = AVR_TMP_REGNO ; cfun -> machine -> gasisr . regno = treg ; cfun -> machine -> stack_usage += <NUM_LIT> + ( treg != AVR_TMP_REGNO ) ; emit_insn ( gen_gasisr ( GEN_INT ( GASISR_Prologue ) , GEN_INT ( treg ) ) ) ; } else { emit_push_byte ( AVR_ZERO_REGNO , true ) ; emit_push_byte ( AVR_TMP_REGNO , true ) ; emit_push_sfr ( sreg_rtx , false , false , AVR_TMP_REGNO ) ; emit_move_insn ( zero_reg_rtx , const0_rtx ) ; emit_use ( zero_reg_rtx ) ; } if ( AVR_HAVE_RAMPD ) emit_push_sfr ( rampd_rtx , false , true , treg ) ; if ( AVR_HAVE_RAMPX && TEST_HARD_REG_BIT ( set , REG_X ) && TEST_HARD_REG_BIT ( set , REG_X + <NUM_LIT> ) ) { emit_push_sfr ( rampx_rtx , false , true , treg ) ; } if ( AVR_HAVE_RAMPY && ( frame_pointer_needed || ( TEST_HARD_REG_BIT ( set , REG_Y ) && TEST_HARD_REG_BIT ( set , REG_Y + <NUM_LIT> ) ) ) ) { emit_push_sfr ( rampy_rtx , false , true , treg ) ; } if ( AVR_HAVE_RAMPZ && TEST_HARD_REG_BIT ( set , REG_Z ) && TEST_HARD_REG_BIT ( set , REG_Z + <NUM_LIT> ) ) { emit_push_sfr ( rampz_rtx , false , AVR_HAVE_RAMPD , treg ) ; } } avr_prologue_setup_frame ( size , set ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> stack_usage + INCOMING_FRAME_SP_OFFSET ;


<s> printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ;


<s> if ( dwarf2out_do_frame ( ) ) { if ( flag_unwind_tables || flag_exceptions ) { if ( dwarf_debuginfo_p ( ) ) asm_fprintf ( f , <STR_LIT> ) ; else asm_fprintf ( f , <STR_LIT> ) ; } else asm_fprintf ( f , <STR_LIT> ) ; done_cfi_sections = true ;


return __arm_vreinterpretq_s32_f32 ( __a ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasV8_2aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasPerfMon ( false ) , HasFullFP16 ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , StrictAlign ( false ) , ReserveX18 ( TT . isOSDarwin ( ) ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) {


<s> unsigned getSRetReturnReg ( ) const {


<s> else d_add_builtin_version ( <STR_LIT> ) ;

if ( TARGET_HARD_FLOAT ) d_add_builtin_version ( <STR_LIT> ) ;


<s> temp . val [ <NUM_LIT> ] = vcombine_s32 ( val . val [ <NUM_LIT> ] , vcreate_s32 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ;

__o = __builtin_aarch64_set_qregoiv4si ( __o , ( int32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> :


<s> Type * BCTy = BitCast -> getType ( ) ; Type * BCSrcTy = BitCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ;

if ( BCTy -> getVectorNumElements ( ) == BCSrcTy -> getVectorNumElements ( ) ) {


<s> for ( auto I = BB -> begin ( ) , E = BB -> end ( ) ; I != E ; ++ I ) { switch ( I -> getOpcode ( ) ) { case <STR_LIT> : if ( TLSBaseAddrReg ) I = ReplaceTLSCall ( & * I , TLSBaseAddrReg ) ;

else I = SetRegister ( & * I , & TLSBaseAddrReg ) ;


<s> expandLoadStackGuard ( MI ) ; MI . getParent ( ) -> erase ( MI ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ;

int ImpDefIdx = MI . findRegisterDefOperandIdx ( DstRegD ) ;


<s> if ( mode != SFmode && mode != DFmode ) return <NUM_LIT> ; if ( ! ( mode == GET_MODE ( operands [ <NUM_LIT> ] ) && mode == GET_MODE ( operands [ <NUM_LIT> ] ) && mode == GET_MODE ( operands [ <NUM_LIT> ] ) && mode == GET_MODE ( operands [ <NUM_LIT> ] ) && mode == GET_MODE ( operands [ <NUM_LIT> ] ) ) ) return <NUM_LIT> ; if ( ! ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) ) return <NUM_LIT> ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <NUM_LIT> ; if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <NUM_LIT> ; if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return <NUM_LIT> ; if ( mode == SFmode && ( REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ <NUM_LIT> ] ) ) != FPUPPER_REGS ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> if ( popType ( ErrorLoc , <STR_LIT> :: I32 ) ) return true ; Stack . push_back ( Type ) ; } else if ( Name == <STR_LIT> ) { if ( getTable ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , Inst , Type ) ) return true ; if ( popType ( ErrorLoc , Type ) ) return true ; if ( popType ( ErrorLoc , <STR_LIT> :: I32 ) ) return true ; } else if ( Name == <STR_LIT> ) { if ( getTable ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , Inst , Type ) ) return true ; if ( popType ( ErrorLoc , <STR_LIT> :: I32 ) ) return true ; if ( popType ( ErrorLoc , Type ) ) return true ; if ( popType ( ErrorLoc , <STR_LIT> :: I32 ) ) return true ; } else if ( Name == <STR_LIT> ) { if ( popType ( ErrorLoc , { } ) ) return true ; } else if ( Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> ) { if ( checkEnd ( ErrorLoc , Name == <STR_LIT> ) ) return true ; if ( Name == <STR_LIT> ) Unreachable = false ; } else if ( Name == <STR_LIT> ) { if ( endOfFunction ( ErrorLoc ) ) return true ; } else if ( Name == <STR_LIT> || Name == <STR_LIT> ) { if ( popType ( ErrorLoc , <STR_LIT> :: I32 ) ) return true ; if ( checkSig ( ErrorLoc , LastSig ) ) return true ; if ( Name == <STR_LIT> && endOfFunction ( ErrorLoc ) ) return true ; } else if ( Name == <STR_LIT> || Name == <STR_LIT> ) { const MCSymbolRefExpr * SymRef ; if ( getSymRef ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , Inst , SymRef ) ) return true ; auto WasmSym = cast < MCSymbolWasm > ( & SymRef -> getSymbol ( ) ) ; auto Sig = WasmSym -> getSignature ( ) ; if ( ! Sig || WasmSym -> getType ( ) != <STR_LIT> ) return typeError ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , StringRef ( <STR_LIT> ) + WasmSym -> getName ( ) + <STR_LIT> ) ; if ( checkSig ( ErrorLoc , * Sig ) ) return true ; if ( Name == <STR_LIT> && endOfFunction ( ErrorLoc ) ) return true ; } else if ( Name == <STR_LIT> ) { const MCSymbolRefExpr * SymRef ; if ( getSymRef ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , Inst , SymRef ) ) return true ; const auto * WasmSym = cast < MCSymbolWasm > ( & SymRef -> getSymbol ( ) ) ;

const auto * Sig = WasmSym -> getSignature ( ) ;


<s> break ; case DFmode : reg = gen_rtx_REG ( DFmode , <NUM_LIT> ) ; break ; case DImode : reg = gen_rtx_REG ( DImode , <NUM_LIT> ) ; break ; default : gcc_unreachable ( ) ; } tmp = gen_rtx_MEM ( QImode , func ) ; tmp = emit_call_insn ( gen_call_value ( reg , tmp , const0_rtx , const0_rtx , const0_rtx ) ) ; CALL_INSN_FUNCTION_USAGE ( tmp ) = usage ; RTL_CONST_CALL_P ( tmp ) = <NUM_LIT> ; tmp = get_insns ( ) ;


<s> MachineInstr * New = MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( JoinedFormat ) . addImm ( CI . CPol ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( combineKnownAdjacentMMOs ( CI , Paired ) ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ;

const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ;


<s> BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; ++ Count ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> , - <NUM_LIT> , <STR_LIT> ) , RI ( ) {


<s> bool <ISA_LIT>Operand :: isPCI ( ) const {

return isMemOp ( ) && MemOp . Op == <STR_LIT> :: RegIndirectDisplacementIndex && MemOp . OuterReg == <STR_LIT> ;


<s> if ( TARGET_68040 || ! TARGET_68881 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; case EXCESS_PRECISION_TYPE_FLOAT16 : error ( <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ;


<s> static bool runOnUse ( Use & U , const PHINodeSet & PromotablePHINodes , B2IMap & BoolToIntMap ) { auto Defs = findAllDefs ( U ) ; if ( llvm :: none_of ( Defs , isa < Instruction , Value * > ) ) return false ; for ( Value * V : Defs ) if ( ! isa < PHINode > ( V ) && ! isa < Constant > ( V ) && ! isa < Argument > ( V ) && ! isa < CallInst > ( V ) ) return false ; for ( Value * V : Defs ) if ( const auto * P = dyn_cast < PHINode > ( V ) ) if ( ! PromotablePHINodes . count ( P ) ) return false ; if ( isa < ReturnInst > ( U . getUser ( ) ) ) ++ NumBoolRetPromotion ; if ( isa < CallInst > ( U . getUser ( ) ) ) ++ NumBoolCallPromotion ; ++ NumBoolToIntPromotion ; for ( Value * V : Defs ) if ( ! BoolToIntMap . count ( V ) ) BoolToIntMap [ V ] = translate ( V ) ; for ( auto & Pair : BoolToIntMap ) { auto * First = dyn_cast < User > ( Pair . first ) ; auto * Second = dyn_cast < User > ( Pair . second ) ; assert ( ( ! First || Second ) && <STR_LIT> ) ; if ( First && ! isa < CallInst > ( First ) ) for ( unsigned i = <NUM_LIT> ; i < First -> getNumOperands ( ) ; ++ i ) Second -> setOperand ( i , BoolToIntMap [ First -> getOperand ( i ) ] ) ; } Value * IntRetVal = BoolToIntMap [ U ] ; Type * Int1Ty = Type :: getInt1Ty ( U -> getContext ( ) ) ; auto * I = cast < Instruction > ( U . getUser ( ) ) ; Value * BackToBool = new TruncInst ( IntRetVal , Int1Ty , <STR_LIT> , I ) ; U . set ( BackToBool ) ; return true ;


<s> const char * x86DisassemblerGetInstrName ( unsigned Opcode , void * mii ) { const MCInstrInfo * MII = static_cast < const MCInstrInfo * > ( mii ) ;


<s> mode = mode_for_size ( GET_MODE_BITSIZE ( mode ) , MODE_INT , <NUM_LIT> ) ; for ( i = bytes ; i < <NUM_LIT> ; i += bytes ) for ( j = <NUM_LIT> ; j < bytes ; j ++ ) if ( arr [ j ] != arr [ i + j ] ) return <NUM_LIT> ; val = arr [ <NUM_LIT> ] ; for ( j = <NUM_LIT> ; j < bytes ; j ++ ) val = ( val << <NUM_LIT> ) | arr [ j ] ; val = trunc_int_for_mode ( val , mode ) ; return val >= low && val <= high ;


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == <STR_LIT> && ! Subtarget . hasStdExtZfh ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ;

if ( VT == <STR_LIT> && ! Subtarget . hasStdExtD ( ) ) return false ;


<s> unsigned LaneSelectReg = LaneSelectOp -> getReg ( ) ; auto IsHazardFn = [ TII ] ( MachineInstr * MI ) { return TII -> isVALU ( * MI ) ; } ; const int RWLaneWaitStates = <NUM_LIT> ; int WaitStatesSince = getWaitStatesSinceDef ( LaneSelectReg , IsHazardFn , RWLaneWaitStates ) ;

return RWLaneWaitStates - WaitStatesSince ;


<s> bool <ISA_LIT>FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; for ( const auto & Info : enumerate ( CSI ) ) { if ( Info . index ( ) < <NUM_LIT> ) Info . value ( ) . setTargetSpilled ( ) ; else Info . value ( ) . setFrameIdx ( MFI . CreateSpillStackObject ( <NUM_LIT> , Align ( ) ) ) ; } return true ;


<s> static std :: string <ISA_LIT>_ez_int2hex ( int64_t val ) { std :: stringstream stream ;


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasGoyaISA ( ) ) { Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; const Module * MM = MF . getMMI ( ) . getModule ( ) ; Metadata * PrintfModule = MM -> getModuleFlag ( <STR_LIT> ) ; if ( PrintfModule ) { Reserved . set ( <STR_LIT> ) ; MachineInstrBuilder MIB ;

const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ;


<s> uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ; int32_t width = ( <NUM_LIT> - countLeadingZeros ( v ) ) - lsb ; assert ( MO . isImm ( ) && <STR_LIT> ) ;

O << markup ( <STR_LIT> ) << '#' << lsb << markup ( <STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) << '#' << width << markup ( <STR_LIT> ) ;


<s> NodePreLegalizer ( ) : FunctionPass ( ID ) , FDivFunc ( nullptr ) , FRemFunc ( nullptr ) , UDivFunc ( nullptr ) , URemFunc ( nullptr ) , SDivFunc ( nullptr ) , SRemFunc ( nullptr ) {


<s> } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( Desc . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( i ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( i + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else {


<s> unsigned Opc = getLoadRegOpcode ( DstReg , RC , TRI , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; <STR_LIT> ( BuildMI ( MBB , MI , DL , get ( Opc ) , DstReg ) , FrameIndex ) ;


<s> break ; } const unsigned PtrIdx = <NUM_LIT> ; const unsigned ValIdx = <NUM_LIT> ; if ( DA -> isDivergentUse ( & I . getOperandUse ( PtrIdx ) ) ) { return ; } const bool ValDivergent = DA -> isDivergentUse ( & I . getOperandUse ( ValIdx ) ) ; if ( ValDivergent && ( ! ST -> hasDPP ( ) || DL -> getTypeSizeInBits ( I . getType ( ) ) != <NUM_LIT> ) ) { return ; } const ReplacementInfo Info = { & I , Op , ValIdx , ValDivergent } ;


<s> assert ( Inputs . has ( R1 . Reg ) && Inputs . has ( R2 . Reg ) ) ; const LatticeCell & L1 = Inputs . get ( R2 . Reg ) ; const LatticeCell & L2 = Inputs . get ( R2 . Reg ) ; if ( L2 . isBottom ( ) ) { if ( L1 . isBottom ( ) ) return false ; return evaluateORrr ( R2 , R1 , Inputs , Result ) ; } LatticeCell LS2 ; if ( ! evaluate ( R2 , L2 , LS2 ) ) return false ; if ( LS2 . isBottom ( ) || LS2 . isProperty ( ) ) return false ; APInt A ; for ( unsigned i = <NUM_LIT> ; i < LS2 . size ( ) ; ++ i ) { LatticeCell RC ; bool Eval = constToInt ( LS2 . Values [ i ] , A ) && evaluateORri ( R1 , A , Inputs , RC ) ; if ( ! Eval ) return false ; Result . meet ( RC ) ;


<s> unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getNode ( <STR_LIT> , dl , VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getNode ( <STR_LIT> , dl , VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true ) ; if ( LD . getNode ( ) ) return LD ; if ( isTargetShuffle ( N -> getOpcode ( ) ) ) { SDValue Shuffle = PerformTargetShuffleCombine ( SDValue ( N , <NUM_LIT> ) , DAG , DCI , Subtarget ) ; if ( Shuffle . getNode ( ) ) return Shuffle ;

SmallVector < int , <NUM_LIT> > NonceMask ;


<s> case EQ : msw_skip = NE ; lsw_taken = EQ ; if ( prob . initialized_p ( ) ) { msw_skip_prob = rev_prob ; lsw_taken_prob = prob > profile_probability :: never ( ) ? profile_probability :: guessed_always ( ) : profile_probability :: guessed_never ( ) ; } break ; case NE : msw_taken = NE ; msw_taken_prob = prob ; lsw_taken = NE ; lsw_taken_prob = profile_probability :: guessed_never ( ) ; break ; case GTU : case GT : msw_taken = comparison ; if ( CONST_INT_P ( op2l ) && INTVAL ( op2l ) == - <NUM_LIT> ) break ; if ( comparison != GTU || op2h != CONST0_RTX ( SImode ) ) msw_skip = swap_condition ( msw_taken ) ; lsw_taken = GTU ; break ; case GEU : case GE : if ( op2l == CONST0_RTX ( SImode ) ) msw_taken = comparison ; else { msw_taken = comparison == GE ? GT : GTU ; msw_skip = swap_condition ( msw_taken ) ; lsw_taken = GEU ; } break ; case LTU : case LT : msw_taken = comparison ; if ( op2l == CONST0_RTX ( SImode ) ) break ; msw_skip = swap_condition ( msw_taken ) ; lsw_taken = LTU ; break ; case LEU : case LE : if ( CONST_INT_P ( op2l ) && INTVAL ( op2l ) == - <NUM_LIT> ) msw_taken = comparison ; else { lsw_taken = LEU ; if ( comparison == LE ) msw_taken = LT ; else if ( op2h != CONST0_RTX ( SImode ) ) msw_taken = LTU ; else { msw_skip = swap_condition ( LTU ) ; break ; } msw_skip = swap_condition ( msw_taken ) ; } break ; default : return false ; } num_branches = ( ( msw_taken != LAST_AND_UNUSED_RTX_CODE ) + ( msw_skip != LAST_AND_UNUSED_RTX_CODE ) + ( lsw_taken != LAST_AND_UNUSED_RTX_CODE ) ) ; if ( comparison != EQ && comparison != NE && num_branches > <NUM_LIT> ) { if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) && prob . initialized_p ( ) && prob . to_reg_br_prob_base ( ) >= ( int ) ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) && prob . to_reg_br_prob_base ( ) <= ( int ) ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ) { msw_taken_prob = prob . apply_scale ( <NUM_LIT> , <NUM_LIT> ) ; msw_skip_prob = rev_prob . apply_scale ( REG_BR_PROB_BASE , rev_prob . to_reg_br_prob_base ( ) + REG_BR_PROB_BASE ) ; lsw_taken_prob = prob ; } else { msw_taken_prob = prob ; msw_skip_prob = profile_probability :: guessed_always ( ) ; lsw_taken_prob = prob ; } } operands [ <NUM_LIT> ] = op1h ;


<s> FuncInfo -> setVarArgsFrameIndex ( FrameInfo . CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; } assert ( ! ( Subtarget . useSoftFloat ( ) && TheFunction . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) && <STR_LIT> ) ; if ( is64Bit ( ) ) { ArrayRef < MCPhysReg > ArgGPRs = get64BitArgumentGPRs ( CallConv , Subtarget ) ; ArrayRef < MCPhysReg > ArgXMMs = get64BitArgumentXMMs ( TheMachineFunction , CallConv , Subtarget ) ; unsigned NumIntRegs = CCInfo . getFirstUnallocated ( ArgGPRs ) ; unsigned NumXMMRegs = CCInfo . getFirstUnallocated ( ArgXMMs ) ; assert ( ! ( NumXMMRegs && ! Subtarget . hasSSE1 ( ) ) && <STR_LIT> ) ; if ( isWin64 ( ) ) { int HomeOffset = FrameLowering . getOffsetOfLocalArea ( ) + <NUM_LIT> ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateFixedObject ( <NUM_LIT> , NumIntRegs * <NUM_LIT> + HomeOffset , false ) ) ; if ( NumIntRegs < <NUM_LIT> ) FuncInfo -> setVarArgsFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) ) ; } else { FuncInfo -> setVarArgsGPOffset ( NumIntRegs * <NUM_LIT> ) ; FuncInfo -> setVarArgsFPOffset ( ArgGPRs . size ( ) * <NUM_LIT> + NumXMMRegs * <NUM_LIT> ) ; FuncInfo -> setRegSaveFrameIndex ( FrameInfo . CreateStackObject ( ArgGPRs . size ( ) * <NUM_LIT> + ArgXMMs . size ( ) * <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ; } SmallVector < SDValue , <NUM_LIT> > LiveGPRs ; SmallVector < SDValue , <NUM_LIT> > LiveXMMRegs ; SDValue ALVal ; for ( MCPhysReg Reg : ArgGPRs . slice ( NumIntRegs ) ) { Register GPR = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveGPRs . push_back ( DAG . getCopyFromReg ( Chain , DL , GPR , <STR_LIT> ) ) ; } const auto & AvailableXmms = ArgXMMs . slice ( NumXMMRegs ) ; if ( ! AvailableXmms . empty ( ) ) { Register AL = TheMachineFunction . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ALVal = DAG . getCopyFromReg ( Chain , DL , AL , <STR_LIT> ) ; for ( MCPhysReg Reg : AvailableXmms ) {

Register XMMReg = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ;


<s> return __builtin_mve_vcmpeqq_n_fv8hf ( __a , __b ) ;


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ; return getAddrLocal ( N , Ty , DAG , Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ;


<s> if ( m_InsVec . size ( ) == <NUM_LIT> ) return nullptr ;


<s> GetInstSeqLs ( Imm & <NUM_LIT> , RemSize , SeqLs ) ;

AddInstr ( SeqLs , Inst ( ORi , Imm & <NUM_LIT> ) ) ;


<s> Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddPtr , InFlag ) ; Chain = LoadEnvPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadEnvPtr . getValue ( <NUM_LIT> ) ; SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , MTCTROps , <NUM_LIT> + ( InFlag . getNode ( ) != <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops . push_back ( Chain ) ; CallOpc = isSVR4ABI ? <STR_LIT> : <STR_LIT> ; Callee . setNode ( <NUM_LIT> ) ;

if ( isTailCall ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ;


<s> DebugLoc curLoc = MI . getDebugLoc ( ) ; if ( prevDebugLoc . isUnknown ( ) && curLoc . isUnknown ( ) ) return ; if ( prevDebugLoc == curLoc ) return ; prevDebugLoc = curLoc ; if ( curLoc . isUnknown ( ) ) return ; const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const LLVMContext & ctx = MF -> getFunction ( ) -> getContext ( ) ; DIScope Scope ( curLoc . getScope ( ctx ) ) ; assert ( ( ! Scope || Scope . isScope ( ) ) && <STR_LIT> ) ; if ( ! Scope ) return ; StringRef fileName ( Scope . getFilename ( ) ) ; StringRef dirName ( Scope . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) { sys :: path :: append ( FullPathName , fileName ) ;


<s> bool FixAllFDIVSQRT :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = DebugLoc ( ) ; bool Modified = false ; for ( auto MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( auto MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ;


<s> else if ( Subtarget -> isTargetDarwin ( ) ) return LowerDarwin_VASTART ( Op , DAG ) ;

else return LowerAAPCS_VASTART ( Op , DAG ) ;


<s> BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addReg ( FrameReg ) ; } BuildMI ( * MBB , MI , DL , TII -> get ( ScalarStoreOp ) ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( OffsetReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; continue ; } if ( SpillToVGPR ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; } else { if ( OnlyToVGPR ) return false ; unsigned TmpReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder Mov = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SubReg , SubKillState ) ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == e ) SuperKillState |= getKillRegState ( IsKill ) ; Mov . addReg ( SuperReg , RegState :: Implicit | SuperKillState ) ; } unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ;

MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , EltSize , MinAlign ( Align , EltSize * i ) ) ;


<s> unsigned Offset = Fixup . getOffset ( ) ;

for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { emitGRX32Move ( MBB , MBBI , DL , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , KillSrc , false ) ; return ; } unsigned Opcode ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = STI . hasVector ( ) ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;

BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( ! Subtarget -> hasBFE ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( ! Subtarget -> hasBFE ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( ! Subtarget -> hasBFE ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ;


<s> AsmAttributeEmitter ( MCStreamer & Streamer_ ) : Streamer ( Streamer_ ) {


<s> const unsigned char JMP64r = <NUM_LIT> ; const unsigned char MOV64ri = <NUM_LIT> ; const unsigned char N86R10 = TRI -> getEncodingValue ( <STR_LIT> ) & <NUM_LIT> ; const unsigned char N86R11 = TRI -> getEncodingValue ( <STR_LIT> ) & <NUM_LIT> ; const unsigned char REX_WB = <NUM_LIT> | <NUM_LIT> | <NUM_LIT> ; unsigned OpCode = ( ( MOV64ri | N86R11 ) << <NUM_LIT> ) | REX_WB ; SDValue Addr = Trmp ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( OpCode , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , FPtr , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; OpCode = ( ( MOV64ri | N86R10 ) << <NUM_LIT> ) | REX_WB ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( OpCode , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; OpCode = ( JMP64r << <NUM_LIT> ) | REX_WB ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( OpCode , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; unsigned char ModRM = N86R11 | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( ModRM , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ; } else {

const Function * Func = cast < Function > ( cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ) ;


<s> if ( ! CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) return false ; tmpaddend = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ; addr = XEXP ( addr , <NUM_LIT> ) ; } if ( GET_CODE ( addr ) == SYMBOL_REF || ( GET_CODE ( addr ) == UNSPEC && ( XINT ( addr , <NUM_LIT> ) == UNSPEC_GOTENT || XINT ( addr , <NUM_LIT> ) == UNSPEC_PLT31 ) ) ) {


<s> const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = * ( MBB -> getParent ( ) ) ; bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned FrameSize = determineFrameLayout ( MF ) ;


<s> unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * Copy = BuildMI ( * MI -> getParent ( ) , MI , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( LiveMaskReg ) ; LIS -> ReplaceMachineInstrInMaps ( * MI , * Copy ) ;


<s> bool isOnStack ( unsigned Reg ) const { for ( const RangeTy & Range : Worklist ) for ( const MachineOperand & MO : Range ) if ( MO . isReg ( ) && MO . getReg ( ) == Reg ) return true ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _xsaves ( void * __P , long long __M ) {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ;


<s> static DecodeStatus decodePCDBLOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) * <NUM_LIT> + Address ) ) ;


<s> } else if ( MEM_P ( src ) ) return out_movqi_r_mr ( insn , operands , plen ) ; } else if ( MEM_P ( dest ) ) { rtx xop [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = dest ; xop [ <NUM_LIT> ] = src == CONST0_RTX ( GET_MODE ( dest ) ) ? zero_reg_rtx : src ; return out_movqi_mr_r ( insn , xop , plen ) ; } return <STR_LIT> ;


<s> return isReg ( ) && checkRegisterClass ( getReg ( ) , true , false , false ) ;


<s> bool <ISA_LIT>DeadRegisterDefinitions :: runOnMachineFunction ( MachineFunction & MF ) { TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto & MBB : MF ) if ( processMachineBasicBlock ( MBB ) ) Changed = true ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ;

const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( * MF ) ;


<s> SDValue getGatherScatterIndex ( SDValue Op ) { if ( auto * N = dyn_cast < MaskedGatherScatterSDNode > ( Op . getNode ( ) ) ) return N -> getIndex ( ) ; if ( auto * N = dyn_cast < VPGatherScatterSDNode > ( Op . getNode ( ) ) ) return N -> getIndex ( ) ;


<s> get<ISA_LIT>ProgramInfo ( KernelInfo , * MF ) ; EmitAmdKernelCodeT ( * MF , KernelInfo ) ; }


<s> SDLoc DL ( Op ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> ) ;


<s> assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; Register StoreAddrReg = ( PtrVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;

SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) , dl ) ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ;

bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . canRealignStack ( MF ) ;


<s> return BB ; case <STR_LIT> : { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineFunction * MF = BB -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MFI -> LDSSize ) ; MI . eraseFromParent ( ) ; return BB ; } case <STR_LIT> : return splitKillBlock ( MI , BB ) ; default : return <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; }


<s> } else if ( Subtarget -> has<ISA_LIT>32r6 ( ) ) { TmpInst0 . setOpcode ( <STR_LIT> ) ; HasLinkReg = true ; } else if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) TmpInst0 . setOpcode ( <STR_LIT> ) ; else { TmpInst0 . setOpcode ( <STR_LIT> ) ; } MCOperand MCOp ;


<s> unsigned CommOpIdx2 = TargetInstrInfo :: CommuteAnyOperandIndex ; if ( ! TII -> findCommutedOpIndices ( * MI , CommOpIdx1 , CommOpIdx2 ) || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI , false , CommOpIdx1 , CommOpIdx2 ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ;

MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ;


<s> MIB . addImm ( ( MI . getOperand ( OpIdx ) . getImm ( ) >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> if ( ! VecTy -> isVectorTy ( ) || isa < ScalableVectorType > ( VecTy ) ) return false ; if ( ! cast < VectorType > ( VecTy ) -> getElementType ( ) -> isIntegerTy ( ) ) return false ; EVT Ty = EVT :: getEVT ( VecTy , false ) ; if ( ! Ty . isSimple ( ) || Ty . getSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( isHVXVectorType ( Ty . getSimpleVT ( ) , IncludeBool ) ) return true ; auto Action = getTargetLowering ( ) -> getPreferredVectorAction ( Ty . getSimpleVT ( ) ) ;

return Action == TargetLoweringBase :: TypeWidenVector ;


<s> if ( ! satisfies_constraint_j00 ( op ) && ! satisfies_constraint_jm1 ( op ) && ! satisfies_constraint_jKK ( op ) && ! satisfies_constraint_jxx ( op ) && ! satisfies_constraint_jyy ( op ) ) return <NUM_LIT> ; } if ( ! SYMBOLIC_CONST ( op ) ) return <NUM_LIT> ; if ( larl_operand ( op , mode ) ) return <NUM_LIT> ; if ( TLS_SYMBOLIC_CONST ( op ) ) return <NUM_LIT> ; if ( flag_pic ) return <NUM_LIT> ;


<s> if ( ! I . isPHI ( ) ) break ; unsigned HeadReg = <NUM_LIT> , CmpBBReg = <NUM_LIT> ; for ( unsigned oi = <NUM_LIT> , oe = I . getNumOperands ( ) ; oi != oe ; oi += <NUM_LIT> ) { MachineBasicBlock * MBB = I . getOperand ( oi + <NUM_LIT> ) . getMBB ( ) ; unsigned Reg = I . getOperand ( oi ) . getReg ( ) ; if ( MBB == Head ) { assert ( ( ! HeadReg || HeadReg == Reg ) && <STR_LIT> ) ; HeadReg = Reg ; }


<s> MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( ImmOp ) ; OpStart = <NUM_LIT> ; Changed = true ; } else if ( HII -> getAddrMode ( * OldMI ) == <STR_LIT> && OldMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { short NewOpCode = HII -> changeAddrMode_io_abs ( * OldMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; MIB = BuildMI ( * BB , InsertPt , OldMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) . add ( OldMI -> getOperand ( <NUM_LIT> ) ) ; const GlobalValue * GV = ImmOp . getGlobal ( ) ; int64_t Offset = ImmOp . getOffset ( ) + OldMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addGlobalAddress ( GV , Offset , ImmOp . getTargetFlags ( ) ) ; OpStart = <NUM_LIT> ; Changed = true ;


<s> if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> isTerminator ( ) ) ; return I == Pred -> end ( ) || ! I -> isBarrier ( ) ;


<s> for ( auto * MBB : ML -> getBlocks ( ) ) dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> ; ) ; std :: function < MachineInstr * ( MachineBasicBlock * ) > SearchForStart = [ & SearchForStart ] ( MachineBasicBlock * MBB ) -> MachineInstr * { for ( auto & MI : * MBB ) { if ( isLoopStart ( MI ) ) return & MI ; } if ( MBB -> pred_size ( ) == <NUM_LIT> ) return SearchForStart ( * MBB -> pred_begin ( ) ) ; return nullptr ; } ; LowOverheadLoop LoLoop ( * ML , * MLI , * RDA ) ; if ( auto * Preheader = ML -> getLoopPreheader ( ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else if ( auto * Preheader = MLI -> findLoopPreheader ( ML , true ) ) LoLoop . Start = SearchForStart ( Preheader ) ; else return false ; for ( auto * MBB : reverse ( ML -> getBlocks ( ) ) ) { for ( auto & MI : * MBB ) { if ( MI . isDebugValue ( ) ) continue ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) LoLoop . End = & MI ; else if ( isLoopStart ( MI ) ) LoLoop . Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) { LoLoop . Revert = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LoLoop . AnalyseMVEInst ( & MI ) ; } } } LLVM_DEBUG ( LoLoop . dump ( ) ) ; if ( ! LoLoop . FoundAllComponents ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA -> getReachingLocalUses ( LoLoop . Dec , <STR_LIT> , Uses ) ; if ( Uses . size ( ) > <NUM_LIT> || ! Uses . count ( LoLoop . End ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LoLoop . Revert = true ; }

LoLoop . CheckLegality ( BBUtils . get ( ) ) ;


<s> unsigned getMaxPrivateElementSize ( ) const { return MaxPrivateElementSize ;


<s> bool doFinalization ( Module & M ) override { return false ;


<s> case rint_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && ! TARGET_ROUND ) return opt_type == OPTIMIZE_FOR_SPEED ; return true ; case floor_optab : case ceil_optab : case btrunc_optab : if ( SSE_FLOAT_MODE_P ( mode1 ) && TARGET_SSE_MATH && ! flag_trapping_math && TARGET_ROUND ) return true ; return opt_type == OPTIMIZE_FOR_SPEED ; case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( ) ; default : return true ;


<s> const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; switch ( Opc ) { case G_ADD : case G_SEXT : case G_ZEXT : case G_GEP : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_LOAD : case G_STORE : OperandsMapping = Ty . getSizeInBits ( ) == <NUM_LIT> ? getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) : & <STR_LIT> [ <STR_LIT> ] ; break ; case G_FADD : assert ( ( Ty . getSizeInBits ( ) == <NUM_LIT> || Ty . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; OperandsMapping = Ty . getSizeInBits ( ) == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr } ) ; break ; case G_SEQUENCE : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LLT Ty2 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . getSizeInBits ( ) != <NUM_LIT> || Ty1 . getSizeInBits ( ) != <NUM_LIT> || Ty2 . getSizeInBits ( ) != <NUM_LIT> ) return InstructionMapping { } ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , nullptr , & <STR_LIT> [ <STR_LIT> ] , nullptr } ) ; break ; } case G_EXTRACT : { LLT Ty1 = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Ty . getSizeInBits ( ) != <NUM_LIT> || Ty1 . getSizeInBits ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) % <NUM_LIT> != <NUM_LIT> ) return InstructionMapping { } ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , nullptr , nullptr } ) ; break ; } default : return InstructionMapping { } ; } for ( unsigned i = <NUM_LIT> ; i < NumOperands ; i ++ ) {

for ( const auto & Mapping : OperandsMapping [ i ] ) {


<s> if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { int64_t Format = ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX11 ? <STR_LIT> :: UFMT_32_FLOAT : <STR_LIT> :: UFMT_32_FLOAT ; return ( Format << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; } uint64_t RsrcDataFormat = <STR_LIT> ; if ( ST . isAmdHsaOS ( ) ) { if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ;

if ( ST . getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ;


<s> return createTupleImpl ( CurDAG , Regs , RegClassIDs [ NF - <NUM_LIT> ] , <STR_LIT> ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( true , OSABI , ELF :: EM_<ISA_LIT> , true ) {


<s> if ( Subtarget . isDarwinABI ( ) ) return nullptr ; if ( ! TM . is<ISA_LIT>64 ( ) ) return nullptr ; if ( MF -> getFunction ( ) . getCallingConv ( ) != CallingConv :: CXX_FAST_TLS ) return nullptr ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return nullptr ; bool SaveR2 = ! getReservedRegs ( * MF ) . test ( <STR_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList : CSR_SVR464_Altivec_ViaCopy_SaveList ;


<s> static SDValue LowerSDIV ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; SDValue N2 , N3 ; if ( VT == <STR_LIT> ) { N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; N2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; N0 = LowerSDIV_v4i8 ( N0 , N1 , dl , DAG ) ; N2 = LowerSDIV_v4i8 ( N2 , N3 , dl , DAG ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , N2 ) ;


<s> if ( BytesRemoved ) * BytesRemoved = <NUM_LIT> ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ;

if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ;


<s> return <STR_LIT> ( Imm , STI . hasInv2PiInlineImm ( ) ) ;


<s> if ( Subtarget . isThumb ( ) ) MI . setOpcode ( <STR_LIT> ) ; else if ( Subtarget . useNaClTrap ( ) ) MI . setOpcode ( <STR_LIT> ) ; else MI . setOpcode ( <STR_LIT> ) ;


<s> TII = ( const <ISA_LIT>16InstrInfo * ) STI -> getInstrInfo ( ) ; MFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( ! PrescannedForConstants ) prescanForConstants ( ) ; HasFarJump = false ; MF -> getRegInfo ( ) . invalidateLiveness ( ) ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialPlacement ( CPEMIs ) ; initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; DEBUG ( dumpBBs ( ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; ( void ) NoBRIters ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ; ImmBranches . clear ( ) ; return MadeChange ;


<s> fprintf ( stream , <STR_LIT> , LOCAL_ASM_OP ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> ) ; ASM_OUTPUT_LABEL ( stream , name ) ; fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_UNSIGNED <STR_LIT> , size ) ;


<s> static bool mep_get_intrinsic_insn ( int intrinsic ATTRIBUTE_UNUSED , const struct cgen_insn * * insn_ptr ATTRIBUTE_UNUSED ) { int i ; i = mep_intrinsic_insn [ intrinsic ] ; while ( i >= <NUM_LIT> && ! CGEN_ENABLE_INSN_P ( i ) ) i = mep_intrinsic_chain [ i ] ; if ( i >= <NUM_LIT> ) { * insn_ptr = & cgen_insns [ i ] ; return true ; } return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isFPCmp = true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; if ( isFPCmp ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Opc = FPBranchCodeToOpc ( GetFPBranchCodeFromCond ( CC ) ) ; BuildMI ( BB , dl , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; } else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator i = BB -> succ_begin ( ) , e = BB -> succ_end ( ) ; i != e ; ++ i ) { EM -> insert ( std :: make_pair ( * i , sinkMBB ) ) ; sinkMBB -> addSuccessor ( * i ) ; } while ( ! BB -> succ_empty ( ) ) BB -> removeSuccessor ( BB -> succ_begin ( ) ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ;


<s> void add_chunk ( chunk ch ) { chunks . push_back ( ch ) ;


<s> rtx_insn * insn ; FOR_BB_INSNS ( bb , insn ) if ( INSN_P ( insn ) ) return insn ;


<s> bool <ISA_LIT>FastISel :: selectFPTrunc ( const Instruction * I ) { Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isFloatTy ( ) || ! V -> getType ( ) -> isDoubleTy ( ) ) return false ; Register Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ;

Register ResultReg = createResultReg ( & <STR_LIT> ) ;


return ( uint32x2_t ) ( __a <= <NUM_LIT> ) ;


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCContext & Ctx , MCStreamer & Streamer , const MCAsmInfo * T ) : AsmPrinter ( O , TM , Ctx , Streamer , T ) , Subtarget ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) != PLUS ) { gcc_assert ( REG_P ( op ) || GET_CODE ( op ) == POST_INC || GET_CODE ( op ) == PRE_DEC || GET_CODE ( op ) == POST_DEC ) ; return <NUM_LIT> ; } offset = INTVAL ( XEXP ( op , <NUM_LIT> ) ) ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) return <NUM_LIT> ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) { if ( XEXP ( op , <NUM_LIT> ) == frame_pointer_rtx ) return offset < - <NUM_LIT> || offset > <NUM_LIT> ; return offset < <NUM_LIT> || offset > <NUM_LIT> ; } return offset < <NUM_LIT> || offset > <NUM_LIT> ;


<s> if ( op_const & <NUM_LIT> ) return build_int_cst ( alpha_dimode_u , opint [ <NUM_LIT> ] & mask ) ; if ( op ) return fold_build2 ( BIT_AND_EXPR , alpha_dimode_u , op [ <NUM_LIT> ] , build_int_cst ( alpha_dimode_u , mask ) ) ; } else if ( ( op_const & <NUM_LIT> ) && opint [ <NUM_LIT> ] == <NUM_LIT> ) return build_int_cst ( alpha_dimode_u , <NUM_LIT> ) ;


<s> SDValue InFlag = SDValue ( Mul , <NUM_LIT> ) ; if ( HasLo ) { Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , Ty , <STR_LIT> , InFlag ) ; InFlag = SDValue ( Lo , <NUM_LIT> ) ; } if ( HasHi ) {

Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL , Ty , InFlag ) ;


<s> std :: stringstream SpillDirty ; MCGSiteUInt :: const_iterator it = WorstCaseSpillDirty . find ( j -> first ) ; assert ( it != WorstCaseSpillDirty . end ( ) ) ; if ( it == WorstCaseSpillDirty . end ( ) ) SpillDirty << <STR_LIT> ; else SpillDirty << it -> second ;

MachineFunction * MF = j -> first -> getCaller ( ) -> getMF ( ) ;


<s> static tree sparc_gimplify_va_arg ( tree valist , tree type , gimple_seq * pre_p , gimple_seq * post_p ) { HOST_WIDE_INT size , rsize , align ; tree addr , incr ; bool indirect ; tree ptrtype = build_pointer_type ( type ) ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { indirect = true ; size = rsize = UNITS_PER_WORD ; align = <NUM_LIT> ; } else { indirect = false ; size = int_size_in_bytes ( type ) ; rsize = ROUND_UP ( size , UNITS_PER_WORD ) ; align = <NUM_LIT> ; if ( TARGET_ARCH64 ) { if ( TYPE_ALIGN ( type ) >= <NUM_LIT> * ( unsigned ) BITS_PER_WORD ) align = <NUM_LIT> * UNITS_PER_WORD ; if ( AGGREGATE_TYPE_P ( type ) ) { if ( size == <NUM_LIT> ) size = rsize = UNITS_PER_WORD ; else size = rsize ; } } } incr = valist ; if ( align ) { incr = fold_build_pointer_plus_hwi ( incr , align - <NUM_LIT> ) ;

incr = fold_convert ( sizetype , incr ) ;


<s> bool isMemoryUnscaled ( ) const { if ( ! isMem ( ) ) return false ; if ( Mem . Mode != ImmediateOffset ) return false ; if ( ! Mem . OffsetImm ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Mem . OffsetImm ) ; if ( ! CE ) return false ;


<s> if ( grp == <NUM_LIT> || grp == <NUM_LIT> ) { wr = ( wr << <NUM_LIT> ) | ( wr & <NUM_LIT> ) ; } wr = ( wr << <NUM_LIT> ) | ( wr & <NUM_LIT> ) ;


<s> return isIntRegForSubInst ( HRI . getSubReg ( Reg , <STR_LIT> ) ) && isIntRegForSubInst ( HRI . getSubReg ( Reg , <STR_LIT> ) ) ;


<s> if ( rx_small_data_limit > <NUM_LIT> ) { switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_SDATA : return sdata_section ; case SECCAT_SBSS : return sbss_section ; case SECCAT_SRODATA : default :


<s> StoreSDNode * SN = cast < StoreSDNode > ( N ) ; if ( ! SN -> isSimple ( ) || ! <STR_LIT> ( SN ) ) return SDValue ( ) ; EVT VT = SN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; Align Alignment = SN -> getAlign ( ) ; if ( Alignment < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = SN -> getAddressSpace ( ) ;

if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Alignment , SN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) {


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> Subtarget -> isNaN2008 ( ) ? getTargetStreamer ( ) . emitDirectiveNaN2008 ( ) : getTargetStreamer ( ) . emitDirectiveNaNLegacy ( ) ; if ( Subtarget -> isABI_EABI ( ) ) { if ( Subtarget -> isGP32bit ( ) ) OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getDataRel ( ) ) ) ; else OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getDataRel ( ) ) ) ;


<s> if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ;

return MRI -> canReserveReg ( BasePtr ) ;


<s> case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return ExpandADDSUB ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ;


<s> bool <ISA_LIT>MCInstrInfo :: hasImmExt ( MCInst const & MCI ) {

if ( ! <ISA_LIT>MCInstrInfo :: isBundle ( MCI ) ) return false ;


<s> } } if ( Ops . size ( ) != <NUM_LIT> ) return false ; unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = <NUM_LIT> ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; }


<s> MachineBasicBlock * TSB = * FP . TrueB -> succ_begin ( ) ; MachineBasicBlock * FSB = * FP . FalseB -> succ_begin ( ) ; if ( TSB != FSB ) return false ; if ( TSB -> pred_size ( ) != <NUM_LIT> ) return false ; } unsigned TS = <NUM_LIT> , FS = <NUM_LIT> , Spare = <NUM_LIT> ; if ( FP . TrueB ) { TS = std :: distance ( FP . TrueB -> begin ( ) , FP . TrueB -> getFirstTerminator ( ) ) ; if ( TS < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - TS ; } if ( FP . FalseB ) { FS = std :: distance ( FP . FalseB -> begin ( ) , FP . FalseB -> getFirstTerminator ( ) ) ; if ( FS < HEXAGON_PACKET_SIZE ) Spare += HEXAGON_PACKET_SIZE - TS ; } unsigned TotalIn = TS + FS ; DEBUG ( dbgs ( ) << <STR_LIT> << TotalIn << <STR_LIT> << Spare << <STR_LIT> ) ; if ( TotalIn >= SizeLimit + Spare ) return false ; unsigned TotalPh = <NUM_LIT> ; unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB ) ;

PredDefs += countPredicateDefs ( FP . JoinB ) ;


<s> getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; } else { getSymbol ( GVar ) -> print ( O , MAI ) ; } return ; } if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( true ) ; PointerType * PTy = dyn_cast < PointerType > ( Cexpr -> getType ( ) ) ; bool IsNonGenericPointer = false ; if ( PTy && PTy -> getAddressSpace ( ) != <NUM_LIT> ) { IsNonGenericPointer = true ; } if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( v ) ) { if ( EmitGeneric && ! isa < Function > ( v ) && ! IsNonGenericPointer ) { O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; O << <STR_LIT> ; } else { getSymbol ( GVar ) -> print ( O , MAI ) ;


<s> bool DblSpaced = false ; if ( Name . find ( <STR_LIT> ) != std :: string :: npos ) { if ( Name . endswith ( <STR_LIT> ) || Name . endswith ( <STR_LIT> ) ) DblSpaced = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; if ( Name . endswith ( <STR_LIT> ) || Name . endswith ( <STR_LIT> ) ) DblSpaced = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; } else {

if ( Name . startswith ( <STR_LIT> ) || Name . startswith ( <STR_LIT> ) ) DblSpaced = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ;


<s> FunctionPass * create<ISA_LIT>InstrCompress ( ) {


<s> if ( REG_P ( addr_reg ) ) { reg = addr_reg ; } else if ( ( GET_CODE ( addr_reg ) == SUBREG && REG_P ( SUBREG_REG ( addr_reg ) ) && GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( addr_reg ) ) ) <= UNITS_PER_WORD ) ) { reg = SUBREG_REG ( addr_reg ) ; } else return FALSE ; if ( GET_MODE ( addr_reg ) != Pmode ) { return FALSE ; } return TRUE ;


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . add ( Src ) ;


<s> case <STR_LIT> : if ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( Val & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; } if ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && Val % <NUM_LIT> == <NUM_LIT> ) { Shift = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Imm = CurDAG -> getTargetConstant ( ( Val >> <NUM_LIT> ) & <NUM_LIT> , DL , <STR_LIT> ) ; return true ; }


<s> RegisterTarget < Triple :: xcore > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> ModulePass * llvm :: create<ISA_LIT>PromoteConstantPass ( ) { return new <ISA_LIT>PromoteConstant ( ) ;


<s> for ( unsigned i = <NUM_LIT> ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) { assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; } unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset = - Offset ; Offset += MFI -> getLocalFrameSize ( ) ; Offset += <NUM_LIT> ;

unsigned StackAlign = TFI -> getStackAlignment ( ) ;


<s> ) ; ContNextScc = true ; } else if ( sccRemainedNumBlk != <NUM_LIT> && sccRemainedNumBlk < SccNumBlk ) { SccNumBlk = sccRemainedNumBlk ; It = SccBeginIter ; ContNextScc = false ; DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( MBB ) << <STR_LIT> << SccNumIter << '\n' ; ) ; } else { ContNextScc = true ; } } else { ContNextScc = false ; } if ( ContNextScc ) SccBeginMBB = nullptr ; } MachineBasicBlock * EntryMBB = GraphTraits < MachineFunction * > :: nodes_begin ( FuncRep ) ; if ( EntryMBB -> succ_size ( ) == <NUM_LIT> ) { Finish = true ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; } else { int NewnumRemainedBlk = countActiveBlock ( OrderedBlks . begin ( ) , OrderedBlks . end ( ) ) ; if ( NewnumRemainedBlk == <NUM_LIT> || NewnumRemainedBlk < NumRemainedBlk ) { MakeProgress = true ; NumRemainedBlk = NewnumRemainedBlk ; } else { MakeProgress = false ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; } } } while ( ! Finish && MakeProgress ) ; wrapup ( GraphTraits < MachineFunction * > :: nodes_begin ( FuncRep ) ) ; for ( MBBInfoMap :: iterator It = BlockInfoMap . begin ( ) , E = BlockInfoMap . end ( ) ; It != E ; ++ It ) { if ( ( * It ) . second && ( * It ) . second -> IsRetired ) { assert ( ( ( * It ) . first ) -> getNumber ( ) != - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( ( * It ) . first ) -> getNumber ( ) << <STR_LIT> ; ) ; ( * It ) . first -> eraseFromParent ( ) ; } delete ( * It ) . second ; } BlockInfoMap . clear ( ) ; LLInfoMap . clear ( ) ;


<s> infp -> pad_reg = <NUM_LIT> ; infp -> pad_outbound = <NUM_LIT> ; if ( infp -> outbound_size % STACK_BYTES ) infp -> pad_outbound = STACK_BYTES - ( infp -> outbound_size % STACK_BYTES ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( infp -> growth ) ; i ++ ) infp -> growth [ i ] = <NUM_LIT> ; regarg = infp -> reg_size + infp -> arg_size ; localregarg = infp -> local_size + regarg ; localreg = infp -> local_size + infp -> reg_size ; outbounds = infp -> outbound_size + infp -> pad_outbound ; growths = <NUM_LIT> ; if ( localregarg <= ADDI_REACH && ( infp -> reg_size <= <NUM_LIT> || ( infp -> reg_mask & <NUM_LIT> ) != <NUM_LIT> ) ) { if ( localregarg % STACK_BYTES ) infp -> pad_reg = STACK_BYTES - ( localregarg % STACK_BYTES ) ; step = localregarg + infp -> pad_reg ; infp -> reg_offset = infp -> local_size ; if ( outbounds + step <= ADDI_REACH && ! frame_pointer_needed ) { step += outbounds ; infp -> reg_offset += outbounds ; outbounds = <NUM_LIT> ; } infp -> arg_offset = step - <NUM_LIT> ; infp -> growth [ growths ++ ] = step ; infp -> reg_growth = growths ; infp -> local_growth = growths ; if ( outbounds ) infp -> growth [ growths ++ ] = outbounds ; goto finish ; } if ( localregarg <= STORE_REACH && ( infp -> local_size > ADDI_REACH ) && ( infp -> reg_size <= <NUM_LIT> || ( infp -> reg_mask & <NUM_LIT> ) != <NUM_LIT> ) ) { int all ; if ( localregarg % STACK_BYTES ) infp -> pad_reg = STACK_BYTES - ( localregarg % STACK_BYTES ) ; all = localregarg + infp -> pad_reg + infp -> pad_local ; step = ADDI_REACH ; if ( step > all ) step = all ; infp -> arg_offset = step - <NUM_LIT> ; infp -> growth [ growths ++ ] = step ; infp -> reg_growth = growths ; infp -> reg_offset = step - infp -> pad_reg - infp -> reg_size ; all -= step ; if ( outbounds + all <= ADDI_REACH && ! frame_pointer_needed ) { all += outbounds ; outbounds = <NUM_LIT> ; }


<s> void setRegSaveFrameIndex ( int Idx ) { RegSaveFrameIndex = Idx ;


<s> unsigned NewOpcode = getInvertedPredicatedOpcode ( MI -> getOpcode ( ) ) ; int TargetPos = MI -> getNumOperands ( ) - <NUM_LIT> ; while ( ( TargetPos > - <NUM_LIT> ) && ! MI -> getOperand ( TargetPos ) . isMBB ( ) ) -- TargetPos ;

assert ( ( TargetPos >= <NUM_LIT> ) && MI -> getOperand ( TargetPos ) . isMBB ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op2 = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( Op2 . getImm ( ) == <NUM_LIT> ) return ;


<s> case 'x' : case 'w' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; case 'U' :

if ( constraint [ <NUM_LIT> ] == 'p' && ( constraint [ <NUM_LIT> ] == 'l' || constraint [ <NUM_LIT> ] == 'a' ) ) weight = CW_Register ;


<s> return isLegacy ( ) ? ElfNote :: NoteNameV2 : ElfNote :: NoteNameV3 ;


<s> unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Datasize = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm ; if ( Datasize ) { if ( Inst . getOpcode ( ) == <STR_LIT> ) DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; else DecodeGPR64spRegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) ; imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! <STR_LIT> ( imm , <NUM_LIT> ) ) return Fail ; } else {

if ( Inst . getOpcode ( ) == <STR_LIT> ) DecodeGPR32RegisterClass ( Inst , Rd , Addr , Decoder ) ;


<s> if ( QII -> isNewValueJump ( MI ) ) return true ;

if ( QII -> isNewValueStore ( MI ) ) return true ;


<s> if ( Ty . isVector ( ) && Ty . getVectorElementType ( ) . isFloatingPoint ( ) ) return true ;


<s> default : break ; case Match_Success : if ( validateInstruction ( Inst , Operands ) ) { forwardITPosition ( ) ; return true ; } while ( processInstruction ( Inst , Operands ) ) ; forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst ) ; return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) {

if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ;


<s> if ( Op . isReg ( ) ) { Op . addRegOperands ( Inst , <NUM_LIT> ) ; continue ; } if ( Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ) { GDSOnly = true ; continue ; } OptionalIdx [ Op . getImmTy ( ) ] = i ; } unsigned OffsetIdx = OptionalIdx [ <ISA_LIT>Operand :: ImmTyOffset ] ; ( ( <ISA_LIT>Operand & ) * Operands [ OffsetIdx ] ) . addImmOperands ( Inst , <NUM_LIT> ) ; if ( ! GDSOnly ) { unsigned GD<ISA_LIT>dx = OptionalIdx [ <ISA_LIT>Operand :: ImmTyGDS ] ;

( ( <ISA_LIT>Operand & ) * Operands [ GD<ISA_LIT>dx ] ) . addImmOperands ( Inst , <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>CodeEmitter :: getHA16Encoding ( const MachineInstr & MI , unsigned OpNo ) const { const MachineOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO ) ; MCE . addRelocation ( GetRelocation ( MO , <STR_LIT> ) ) ;


<s> const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> bool hasCodeObjectV3 ( const FeatureBitset & Features ) {

return Features . test ( FeatureCodeObjectV3 ) ;


<s> if ( ! GetLane ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ;

EVT NewToVT = EVT :: getIntegerVT ( C , VT . getSizeInBits ( ) ) ;


<s> explicit <ISA_LIT>Z80MCExpr ( VariantKind Kind , const MCExpr * Expr , bool Negated ) : Kind ( Kind ) , SubExpr ( Expr ) , Negated ( Negated ) {


<s> for ( Argument & Arg : F . args ( ) ) if ( Arg . getType ( ) -> isPointerTy ( ) && Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ;


<s> OS . EmitValueToAlignment ( <NUM_LIT> , Encoded_s_code_end , <NUM_LIT> ) ;

for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) OS . EmitIntValue ( Encoded_s_code_end , <NUM_LIT> ) ;


<s> void addMemPCRelImm12Operands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: tryParseNeonVectorRegister ( OperandVector & Operands ) { if ( getTok ( ) . isNot ( AsmToken :: Identifier ) ) return true ; SMLoc S = getLoc ( ) ; StringRef Kind ; unsigned Reg ; OperandMatchResultTy Res = tryParseVectorRegister ( Reg , Kind , RegKind :: NeonVector ) ;

if ( Res != MatchOperand_Success ) return true ;


<s> bool isSGPRClassID ( unsigned RCID ) const { if ( static_cast < int > ( RCID ) == - <NUM_LIT> ) return false ;

return isSGPRClass ( getRegClass ( RCID ) ) ;


<s> int64_t Reg = tryMatchVectorRegister ( Kind , false ) ; if ( Reg == - <NUM_LIT> ) { Reg = tryMatchSVEVectorRegister ( Parser . getTok ( ) , Kind , false ) ; if ( Reg == - <NUM_LIT> ) return true ; Parser . Lex ( ) ; RegisterKind = RegKind :: SVEVector ; } Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( Reg , RegisterKind , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , false , S , getContext ( ) ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = getLoc ( ) ;


<s> unsigned IntNo = Op . getConstantOperandVal ( <NUM_LIT> ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : { SDLoc DL ( Op ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; } SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ;

SDValue IntID = DAG . getTargetConstant ( IsUnmasked ? <STR_LIT> : <STR_LIT> , DL , XLenVT ) ;


<s> if ( MInfo . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ;


emit_insn ( fn ( dest , tmp2 , tmp3 ) ) ;


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinCFISaveFRegP ( unsigned Reg , int Offset ) { emitARM64WinUnwindCode ( Win64EH :: UOP_SaveFRegP , Reg , Offset ) ;


<s> NumOpsAdded = <NUM_LIT> ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; <STR_LIT> AddrOpcode = getUBit ( insn ) ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOp = getShiftOpcForBits ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned ShImm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; getImmShiftSE ( ShOp , ShImm ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( AddrOpcode , ShImm , ShOp ) ) ) ; NumOpsAdded = <NUM_LIT> ; } return true ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result ;


<s> assert ( ImmOffs && <STR_LIT> ) ; O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << ImmOffs ; return ; } O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << TRI -> getAsmName ( MO1 . getReg ( ) ) ;

if ( unsigned ShImm = <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << <STR_LIT> << ShImm ;


<s> if ( ! ( FeatureBits & <STR_LIT> ) ) return MCDisassembler :: Fail ; break ; default : return MCDisassembler :: Fail ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Mask = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! ( FeatureBits & <STR_LIT> ) ) { if ( Mask != <NUM_LIT> ) S = MCDisassembler :: SoftFail ; } else { if ( Mask == <NUM_LIT> || ( Mask != <NUM_LIT> && ValLow > <NUM_LIT> ) || ( ! ( FeatureBits & <STR_LIT> ) && ( Mask & <NUM_LIT> ) ) ) S = MCDisassembler :: SoftFail ; } } } else { if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ;


<s> Options . MaxNumLoads = TLI -> getMaxExpandSizeMemcmp ( OptSize ) ; Options . NumLoadsPerBlock = <NUM_LIT> ; Options . AllowOverlappingLoads = true ; if ( IsZeroCmp ) { const unsigned PreferredWidth = ST -> getPreferVectorWidth ( ) ; if ( PreferredWidth >= <NUM_LIT> && ST -> hasAVX512 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( PreferredWidth >= <NUM_LIT> && ST -> hasAVX ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( PreferredWidth >= <NUM_LIT> && ST -> hasSSE2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; }


<s> if ( m_pInput == NULL ) { m_pInput = & pInput ; initGOTList ( ) ; } else { m_pInput = & pInput ; changeInput ( ) ;


<s> static bool shouldSwapCmpOperands ( const Comparison & C ) { if ( C . Op0 . getValueType ( ) == <STR_LIT> ) return false ; if ( isa < ConstantFPSDNode > ( C . Op1 ) ) return false ; auto * ConstOp1 = dyn_cast < ConstantSDNode > ( C . Op1 ) ; if ( ConstOp1 && ConstOp1 -> getZExtValue ( ) == <NUM_LIT> ) return false ; if ( isNaturalMemoryOperand ( C . Op1 , C . ICmpType ) && C . Op1 . hasOneUse ( ) ) return false ; if ( isNaturalMemoryOperand ( C . Op0 , C . ICmpType ) && C . Op0 . hasOneUse ( ) ) { if ( ! ConstOp1 ) return true ; if ( C . ICmpType != <STR_LIT> && isUInt < <NUM_LIT> > ( ConstOp1 -> getZExtValue ( ) ) ) return false ;

if ( C . ICmpType != <STR_LIT> && isInt < <NUM_LIT> > ( ConstOp1 -> getSExtValue ( ) ) ) return false ;


<s> static inline bool isPCRELFixupKind ( unsigned FixupKind ) { return FixupKind == FK_<ISA_LIT>_PCrel ;


<s> putc ( 'd' , file ) ; break ; case <NUM_LIT> : break ; default : error ( <STR_LIT> ) ; break ; } return ; } reg = NULL ; switch ( code ) { case <NUM_LIT> : if ( STACK_TOP_P ( x ) ) { reg = <STR_LIT> ; break ; } case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ANY_FP_REG_P ( x ) && ! ANY_MASK_REG_P ( x ) && ! ANY_BND_REG_P ( x ) ) putc ( code == <NUM_LIT> && TARGET_64BIT ? 'r' : 'e' , file ) ; case <NUM_LIT> : case <NUM_LIT> : normal : reg = hi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_reg_name ) ) goto normal ; reg = qi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_high_reg_name ) ) goto normal ; reg = qi_high_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( SSE_REG_P ( x ) ) { gcc_assert ( ! duplicated ) ; putc ( 'y' , file ) ; fputs ( hi_reg_name [ regno ] + <NUM_LIT> , file ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isScalableVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ;

if ( V . getOpcode ( ) == <STR_LIT> ) if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , V . getOperand ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeImm5S4Operand ( const MCInst * MI , unsigned Op , const MCSubtargetInfo & STI , raw_ostream & O ) { printThumbAddrModeImm5SOperand ( MI , Op , STI , O , <NUM_LIT> ) ;


<s> splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= <NUM_LIT> || ( step == <NUM_LIT> && copies == <NUM_LIT> ) ) ) ; else return false ; for ( i = <NUM_LIT> ; i < nunits - <NUM_LIT> ; ++ i ) { HOST_WIDE_INT desired_val ; if ( ( ( i + <NUM_LIT> ) & ( step - <NUM_LIT> ) ) == <NUM_LIT> ) desired_val = val ;


<s> unsigned BBNum = BB -> getNumber ( ) ; for ( unsigned i = BBNum + <NUM_LIT> , e = MF -> getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned Offset = BBInfo [ i - <NUM_LIT> ] . Offset + BBInfo [ i - <NUM_LIT> ] . Size ;


<s> unsigned <ISA_LIT>CodeEmitter :: getLSAImmEncoding ( const MachineInstr & MI , unsigned OpNo ) const {


<s> return ( ( frame_pointer_needed && to == FRAME_POINTER_REGNUM ) || ! frame_pointer_needed ) ;


<s> int msp430_arg_partial_bytes ( cumulative_args_t cap , const function_arg_info & arg ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( cap ) ;

msp430_evaluate_arg ( cap , arg . mode , arg . type , arg . named ) ;


<s> } } TFI . emitPrologue ( MF , MF . front ( ) ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) TFI . emitEpilogue ( MF , * I ) ; }


<s> if ( MI . isEHLabel ( ) || MI . isCFIInstruction ( ) ) return true ; if ( MI . isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ;

if ( isSchedBarrier ( & MI ) ) return true ;


<s> if ( IsSplat ) { assert ( SplatV . getNode ( ) ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( SplatV . getNode ( ) ) ; if ( IdxN && IdxN -> isNullValue ( ) ) return getZero ( dl , VecTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , SplatV ) ; } SmallVector < ConstantInt * , <NUM_LIT> > Consts ( VecLen ) ; bool AllConst = getBuildVectorConstInts ( Values , VecTy , DAG , Consts ) ; if ( AllConst ) { ArrayRef < Constant * > Tmp ( ( Constant * * ) Consts . begin ( ) , ( Constant * * ) Consts . end ( ) ) ; Constant * CV = ConstantVector :: get ( Tmp ) ; unsigned Align = HwLen ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , VecTy , Align ) , DAG ) ; return DAG . getLoad ( VecTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Align ) ; } assert ( <NUM_LIT> * Words . size ( ) == Subtarget . getVectorLength ( ) ) ; SDValue HalfV0 = getInstr ( <STR_LIT> , dl , VecTy , { } , DAG ) ; SDValue HalfV1 = getInstr ( <STR_LIT> , dl , VecTy , { } , DAG ) ; SDValue S = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumWords / <NUM_LIT> ; ++ i ) {

SDValue N = DAG . getNode ( <STR_LIT> , dl , VecTy , { HalfV0 , Words [ i ] } ) ;


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) || ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i + <NUM_LIT> ) || ! isUndefOrEqual ( N -> getMaskElt ( i + <NUM_LIT> ) , i + <NUM_LIT> ) ) return false ; return true ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _xabort ( const unsigned int __imm ) { __builtin_ia32_xabort ( __imm ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = & <STR_LIT> ; else RC = & <STR_LIT> ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) {

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


<s> for ( Target * T : { & The<ISA_LIT>Target , & The<ISA_LIT>V9Target , & The<ISA_LIT>elTarget } ) { TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ;

TargetRegistry :: RegisterAsmTargetStreamer ( * T , createTargetAsmStreamer ) ;


<s> assert ( Old -> getType ( ) != New -> getType ( ) && <STR_LIT> ) ;

for ( auto * User : Old -> users ( ) ) for ( unsigned i = <NUM_LIT> ; i < User -> getNumOperands ( ) ; i ++ ) if ( User -> getOperand ( i ) == Old ) User -> setOperand ( i , New ) ;


<s> for ( unsigned i = <NUM_LIT> , e = DefDesc . getNumOperands ( ) ; i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI . getParent ( ) ) NewMI -> clearKillInfo ( ) ; DefMI -> eraseFromParent ( ) ;


<s> unsigned RelaxableOp = Inst . getNumOperands ( ) - <NUM_LIT> ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ;


<s> for ( auto I = B . livein_begin ( ) , E = B . livein_end ( ) ; I != E ; ++ I ) T . push_back ( I -> PhysReg ) ;

for ( auto I : T ) B . removeLiveIn ( I ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) {

if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) {


<s> case <STR_LIT> : case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Terminator . ExtraRelaxSize = <NUM_LIT> ;


<s> case <STR_LIT> : return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } Optional < MCFixupKind > getFixupKind ( StringRef Name ) const override ; const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override ; void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override ; bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override ; std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI ) ; } } ; } Optional < MCFixupKind > <ISA_LIT>MCAsmBackend :: getFixupKind ( StringRef Name ) const { unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_390_NONE ) . Case ( <STR_LIT> , ELF :: R_390_8 ) . Case ( <STR_LIT> , ELF :: R_390_16 ) . Case ( <STR_LIT> , ELF :: R_390_32 ) . Case ( <STR_LIT> , ELF :: R_390_64 ) . Default ( - <NUM_LIT> ) ; if ( Type != - <NUM_LIT> ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; return None ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ;

if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ;


if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP ) ) OutMI . addOperand ( MCOp ) ;


<s> auto FirstTerm = B . getFirstInstrTerminator ( ) ; if ( FirstTerm == B . instr_end ( ) ) return false ; if ( HII -> isExtended ( MI ) ) return false ; unsigned InstOffset = BlockToInstOffset [ & B ] ; unsigned Distance = <NUM_LIT> ; InstOffset += HII -> nonDbgBBSize ( & B ) * HEXAGON_INSTR_SIZE ; MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; if ( HII -> analyzeBranch ( B , TBB , FBB , Cond , false ) ) { if ( HII -> isNewValueJump ( * FirstTerm ) ) TBB = FirstTerm -> getOperand ( HII -> getCExtOpNum ( * FirstTerm ) ) . getMBB ( ) ; } if ( TBB && & MI == & * FirstTerm ) { Distance = std :: abs ( ( long long ) InstOffset - BlockToInstOffset [ TBB ] ) + BranchRelaxSafetyBuffer ; return ! HII -> isJumpWithinBranchRange ( * FirstTerm , Distance ) ; } if ( FBB ) { auto SecondTerm = std :: next ( FirstTerm ) ; assert ( SecondTerm != B . instr_end ( ) && ( SecondTerm -> isBranch ( ) || SecondTerm -> isCall ( ) ) && <STR_LIT> ) ; if ( & MI != & * SecondTerm ) return false ; Distance = std :: abs ( ( long long ) InstOffset - BlockToInstOffset [ FBB ] ) + BranchRelaxSafetyBuffer ; return ! HII -> isJumpWithinBranchRange ( * SecondTerm , Distance ) ;


<s> assert ( Size && <STR_LIT> ) ; const GlobalValue * GV = dyn_cast < GlobalValue > ( CV -> stripPointerCasts ( ) ) ; assert ( GV && <STR_LIT> ) ;

const MCExpr * E = MCSymbolRefExpr :: Create ( Mang -> getSymbol ( GV ) , ( Subtarget -> isTargetDarwin ( ) ? MCSymbolRefExpr :: VK_None : MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 ) , OutContext ) ;


<s> rtx align_rtx = operands [ <NUM_LIT> ] ; int constp = GET_CODE ( bytes_rtx ) == CONST_INT ; HOST_WIDE_INT bytes = constp ? INTVAL ( bytes_rtx ) : <NUM_LIT> ; int align = INTVAL ( align_rtx ) ; int leftover ; rtx src_reg ; rtx dst_reg ; if ( constp && bytes <= <NUM_LIT> ) return <NUM_LIT> ; dst_reg = copy_addr_to_reg ( XEXP ( orig_dst , <NUM_LIT> ) ) ; src_reg = copy_addr_to_reg ( XEXP ( orig_src , <NUM_LIT> ) ) ; if ( align > UNITS_PER_WORD ) align = UNITS_PER_WORD ; if ( optimize_size || ! constp || align != UNITS_PER_WORD ) { block_move_call ( dst_reg , src_reg , bytes_rtx ) ; return <NUM_LIT> ; }


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MustSaveTOC ) continue ; if ( IsCRField ) { <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ;

MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , StringRef TT ) {

if ( Triple ( TT ) . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ;


<s> tree lhs_type = TREE_TYPE ( gimple_assign_lhs ( assign ) ) ; tree rhs_type = TREE_TYPE ( gimple_assign_rhs1 ( assign ) ) ;


<s> Waitcnt = packBits ( Vmcnt , Waitcnt , getVmcntBitShiftLo ( Version . Major ) , getVmcntBitWidthLo ( Version . Major ) ) ;

return packBits ( Vmcnt >> getVmcntBitWidthLo ( Version . Major ) , Waitcnt , getVmcntBitShiftHi ( Version . Major ) , getVmcntBitWidthHi ( Version . Major ) ) ;


<s> int intregs , intoffset ; if ( cum -> floats_in_gpr == <NUM_LIT> && ( cum -> intoffset % <NUM_LIT> == <NUM_LIT> || ( cum -> intoffset == - <NUM_LIT> && final ) ) ) { cum -> words ++ ; cum -> floats_in_gpr = <NUM_LIT> ; } if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; cum -> floats_in_gpr = <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ;

if ( ! int_mode_for_size ( bits , <NUM_LIT> ) . exists ( ) ) {


<s> void recordFeatures ( Module & M , const FeatureBitset & Features , bool Stripped ) { for ( const SubtargetFeatureKV & KV : <ISA_LIT>FeatureKV ) { std :: string MDKey = ( StringRef ( <STR_LIT> ) + KV . Key ) . str ( ) ; if ( KV . Value == <STR_LIT> && Stripped ) { assert ( ! Features [ <STR_LIT> ] || ! Features [ <STR_LIT> ] ) ; M . addModuleFlag ( Module :: ModFlagBehavior :: Error , MDKey , <STR_LIT> ) ;


<s> SDValue V = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ;

} else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) {