<s> SmallDenseMap < const Constant * , unsigned , <NUM_LIT> > InsertionOrder ; for ( const auto & Record : Updates ) InsertionOrder . insert ( std :: make_pair ( Record . C , InsertionOrder . size ( ) ) ) ; std :: stable_sort ( Updates . begin ( ) , Updates . end ( ) , [ & InsertionOrder ] ( const UpdateRecord & L , const UpdateRecord & R ) { return InsertionOrder . lookup ( L . C ) < InsertionOrder . lookup ( R . C ) ;


<s> return __arm_vldrwq_z_u32 ( __base , __p ) ;


<s> auto Int8PtrTy = Type :: getInt8PtrTy ( Func . getContext ( ) , <ISA_LIT>AS :: GLOBAL_ADDRESS ) ; if ( HiddenArgNumBytes >= <NUM_LIT> ) { if ( Func . getParent ( ) -> getNamedMetadata ( <STR_LIT> ) ) emitKernelArg ( DL , Int8PtrTy , ValueKind :: HiddenPrintfBuffer ) ; else emitKernelArg ( DL , Int8PtrTy , ValueKind :: HiddenNone ) ; } if ( HiddenArgNumBytes >= <NUM_LIT> ) { if ( Func . hasFnAttribute ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , ValueKind :: HiddenDefaultQueue ) ;

emitKernelArg ( DL , Int8PtrTy , ValueKind :: HiddenCompletionAction ) ;


<s> return __arm_vldrwq_z_f32 ( __base , __p ) ;


<s> auto Pred = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; auto GetRegForProfit = [ & ] ( Register Reg ) { MachineInstr * Def = getDefIgnoringCopies ( Reg , MRI ) ; return isCMN ( Def , Pred , MRI ) ? Def -> getOperand ( <NUM_LIT> ) . getReg ( ) : Reg ;


<s> case Instruction :: Mul : return false ; case Instruction :: Add : return ScalarBits * cast < FixedVectorType > ( VTy ) -> getNumElements ( ) >= <NUM_LIT> ; case Instruction :: ICmp : return ( ScalarBits < <NUM_LIT> ) && ( ScalarBits * cast < FixedVectorType > ( VTy ) -> getNumElements ( ) >= <NUM_LIT> ) ; case Instruction :: FCmp : return Flags . NoNaN ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; InitDcpu16MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> if ( Ret -> getNumOperands ( ) == <NUM_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; return true ; } Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget -> hasSIMD128 ( ) && RV -> getType ( ) -> isVectorTy ( ) ) return false ; unsigned Opc ; switch ( getSimpleType ( RV -> getType ( ) ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> <ISA_LIT>ValueHandler ( bool IsIncoming , MachineIRBuilder & B , MachineRegisterInfo & MRI , CCAssignFn * AssignFn ) : ValueHandler ( IsIncoming , B , MRI , AssignFn ) {


<s> Register Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Register SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock * thisMBB = MBB ; if ( MF -> getMMI ( ) . getModule ( ) -> getModuleFlag ( <STR_LIT> ) ) { thisMBB = emitLongJmpShadowStackFix ( MI , thisMBB ) ; } MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) MIB . addReg ( MO . getReg ( ) ) ; else MIB . add ( MO ) ; } MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ;

if ( i == <STR_LIT> ) MIB . addDisp ( MO , LabelOffset ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>CodePrinterPass ( raw_ostream & o , <ISA_LIT>TargetMachine & tm , bool fast ) { return new <ISA_LIT>AsmPrinter ( o , tm , tm . getTargetAsmInfo ( ) , fast ) ;


<s> if ( ! Errata602117 && ! NonConsecutiveRegs ) return false ; bool isT2 = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isLd = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool EvenDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool EvenUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool OddDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OddUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool BaseKill = BaseOp . isKill ( ) ; bool BaseUndef = BaseOp . isUndef ( ) ; bool OffKill = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OffUndef = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; int OffImm = getMemoryOpOffset ( MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; unsigned NewOpc2 = ( isLd ) ? ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) ) ) {

assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) ) ;


<s> <ISA_LIT>Operand * Op = ( <ISA_LIT>Operand * ) CO . Operands [ <NUM_LIT> ] ; if ( ! IsVector && ! Op -> isRegList ( ) ) return Error ( L , <STR_LIT> ) ; if ( IsVector && ! Op -> isDPRRegList ( ) ) return Error ( L , <STR_LIT> ) ; getParser ( ) . getStreamer ( ) . EmitRegSave ( Op -> getRegList ( ) , IsVector ) ; return false ;


<s> assert ( ( ( Val && VReg ) || ( ! Val && ! VReg ) ) && <STR_LIT> ) ; if ( VReg ) { assert ( Val -> getType ( ) -> isIntegerTy ( ) && <STR_LIT> ) ; unsigned Size = Val -> getType ( ) -> getPrimitiveSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; unsigned ResReg = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIRBuilder . setInstr ( * Return , true ) ; MachineInstr * Copy = MIRBuilder . buildInstr ( TargetOpcode :: COPY , ResReg , VReg ) ; ( void ) Copy ;

assert ( Copy -> getNextNode ( ) == Return && <STR_LIT> ) ;


<s> return UseExperimentalZeroingPseudos ;


<s> int iter = spill_fill_data . next_iter ; rtx insn ; insn = emit_insn ( ( * move_fn ) ( reg , spill_restore_mem ( reg , cfa_off ) , GEN_INT ( cfa_off ) ) ) ; spill_fill_data . prev_insn [ iter ] = insn ;


<s> } else { if ( scratch ) emit_move_insn ( scratch , GEN_INT ( imm ) ) ; else scratch = force_reg ( SImode , GEN_INT ( imm ) ) ; retval = true ; insn = emit_insn ( gen_addsi3 ( dst , src , scratch ) ) ; } if ( need_note ) {

rtx note_rtx = gen_rtx_SET ( dst , plus_constant ( Pmode , src , imm ) ) ;


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_TAIL_CALL ( const MachineInstr & MI ) {

EmitSled ( MI , SledKind :: TAIL_CALL ) ;


<s> const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) && ! Disable<ISA_LIT>FastISel ) return new <ISA_LIT>FastISel ( funcInfo ) ;


<s> if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , L ) ; return false ;


<s> const TargetRegisterClass * RC = ( Width == <NUM_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned LoadOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned StoreOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , I , dl , TII . get ( <STR_LIT> ) , SCRATCH_REGISTER ) . addImm ( Subtarget . getIORegSREG ( ) ) ; BuildMI ( * BB , I , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , dl , TII . get ( LoadOpcode ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; Register Result = MRI . createVirtualRegister ( RC ) ; BuildMI ( * BB , I , dl , TII . get ( Opcode ) , Result ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;

BuildMI ( * BB , I , dl , TII . get ( StoreOpcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( Result ) ;


<s> return __builtin_loongson_psubd_s ( s , t ) ;


<s> case <STR_LIT> : return legalizeImplicitArgPtr ( MI , MRI , B ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> : return legalizeFDIVFastIntrin ( MI , MRI , B ) ; case <STR_LIT> : return legalizeIsAddrSpace ( MI , MRI , B , <ISA_LIT>AS :: LOCAL_ADDRESS ) ; case <STR_LIT> : return legalizeIsAddrSpace ( MI , MRI , B , <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; case <STR_LIT> : { B . setInstr ( MI ) ; B . buildConstant ( MI . getOperand ( <NUM_LIT> ) , ST . getWavefrontSize ( ) ) ; MI . eraseFromParent ( ) ;


<s> MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; SmallVector < MBBInfo , <NUM_LIT> > WorkList ( <NUM_LIT> , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ;


<s> <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ;

bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;


<s> if ( ( Encoding & DW_EH_PE_indirect ) && ( Encoding & DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ;

const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ;


if ( ! TARGET_ALTIVEC && ! TARGET_VSX ) {


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) {


<s> bool Changed = false ; MachineSSAUpdater SSAUpdater ( * MF ) ; LoopFinder LF ( * DT , * PDT ) ; SmallVector < MachineInstr * , <NUM_LIT> > DeadCopies ; for ( MachineBasicBlock & MBB : * MF ) { LF . initialize ( MBB ) ; for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isVreg1 ( DstReg ) ) continue ; Changed = true ; if ( MRI -> use_empty ( DstReg ) ) { DeadCopies . push_back ( & MI ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MRI -> setRegClass ( DstReg , IsWave32 ? & <STR_LIT> : & <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) continue ; DebugLoc DL = MI . getDebugLoc ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; if ( ! SrcReg . isVirtual ( ) || ( ! isLaneMaskReg ( SrcReg ) && ! isVreg1 ( SrcReg ) ) ) { assert ( TII -> getRegisterInfo ( ) . getRegSizeInBits ( SrcReg , * MRI ) == <NUM_LIT> ) ; unsigned TmpReg = createLaneMaskReg ( * MF ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( TmpReg ) ; SrcReg = TmpReg ; } std :: vector < MachineBasicBlock * > DomBlocks = { & MBB } ; for ( MachineInstr & Use : MRI -> use_instructions ( DstReg ) ) DomBlocks . push_back ( Use . getParent ( ) ) ; MachineBasicBlock * PostDomBound = PDT -> findNearestCommonDominator ( DomBlocks ) ; unsigned FoundLoopLevel = LF . findLoop ( PostDomBound ) ; if ( FoundLoopLevel ) { SSAUpdater . Initialize ( DstReg ) ; SSAUpdater . AddAvailableValue ( & MBB , DstReg ) ; LF . addLoopEntries ( FoundLoopLevel , SSAUpdater ) ; buildMergeLaneMasks ( MBB , MI , DL , DstReg , SSAUpdater . GetValueInMiddleOfBlock ( & MBB ) , SrcReg ) ; DeadCopies . push_back ( & MI ) ; } } for ( MachineInstr * MI : DeadCopies ) MI -> eraseFromParent ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : if ( ! isWQM ) { if ( ! ST -> hasCaymanISA ( ) && ! branchStackContains ( CFStack :: FIRST_NON_WQM_PUSH ) ) Item = CFStack :: FIRST_NON_WQM_PUSH ; else if ( CurrentEntries > <NUM_LIT> && ST -> getGeneration ( ) > <ISA_LIT>Subtarget :: EVERGREEN && ! ST -> hasCaymanISA ( ) && ! branchStackContains ( CFStack :: FIRST_NON_WQM_PUSH_W_FULL_ENTRY ) ) Item = CFStack :: FIRST_NON_WQM_PUSH_W_FULL_ENTRY ; else Item = CFStack :: SUB_ENTRY ; } else Item = CFStack :: ENTRY ; break ; } BranchStack . push_back ( Item ) ; if ( Item == CFStack :: ENTRY ) CurrentEntries ++ ;

else CurrentSubEntries += getSubEntrySize ( Item ) ;


<s> unsigned ResultReg = createResultReg ( DstRC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; TargetRegisterClass * DstRC = TLI . getRegClassFor ( CopyVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; }


<s> return ( __m256i ) __builtin_ia32_vpopcountw_v16hi ( ( __v16hi ) __A ) ;


<s> if ( Subtarget . isGP64bit ( ) ) BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ;

else BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ;


<s> } if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return <STR_LIT> ; } } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ;


<s> FOR_EACH_INSN_DEF ( def , insn ) if ( DF_REF_REG_DEF_P ( def ) && ! DF_REF_IS_ARTIFICIAL ( def ) && ( regno1 == DF_REF_REGNO ( def ) || regno2 == DF_REF_REGNO ( def ) ) ) return true ; return false ;


<s> <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; TS -> EmitDirectiveHSACodeObjectVersion ( <NUM_LIT> , <NUM_LIT> ) ; <STR_LIT> ISA = <STR_LIT> ( STI -> getFeatureBits ( ) ) ; TS -> EmitDirectiveHSACodeObjectISA ( ISA . Major , ISA . Minor , ISA . Stepping , <STR_LIT> , <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Data [ Offset + i ] += uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> void addMemVX64Operands ( MCInst & Inst , unsigned N ) const { addMemOperands ( Inst , N ) ;


<s> return ( __m128i ) __builtin_ia32_vpcomneqw ( ( __v8hi ) __A , ( __v8hi ) __B ) ;


<s> case <STR_LIT> : case <STR_LIT> : { unsigned OpOffset = <STR_LIT> ( Desc . TSFlags ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Imm = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> + OpOffset , <NUM_LIT> + OpOffset ) ; } return false ; } case <STR_LIT> : if ( Subtarget . hasSSE41 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSE2 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return findThreeSrcCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> <ISA_LIT>Z80MCInstLower ( MCContext & Ctx , AsmPrinter & Printer ) : Ctx ( Ctx ) , Printer ( Printer ) {


<s> static bool isZeroImm ( const MachineOperand & op ) { return op . isImm ( ) && op . getImm ( ) == <NUM_LIT> ;


<s> switch ( TheTriple . getOS ( ) ) { default :


<s> DAG . getConstant ( FuncInfo -> getVarArgsFirstGPR ( ) , PtrVT ) , DAG . getConstant ( FuncInfo -> getVarArgsFirstFPR ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) } ; SDValue MemOps [ NumFields ] ; unsigned Offset = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumFields ; ++ I ) { SDValue FieldAddr = Addr ; if ( Offset != <NUM_LIT> ) FieldAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , FieldAddr , DAG . getIntPtrConstant ( Offset ) ) ; MemOps [ I ] = DAG . getStore ( Chain , DL , Fields [ I ] , FieldAddr , MachinePointerInfo ( SV , Offset ) , false , false , <NUM_LIT> ) ; Offset += <NUM_LIT> ;


<s> else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ;


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Expr , Kind ) ;


<s> assert ( ! Val == VRegs . empty ( ) && <STR_LIT> ) ; CallingConv :: ID CC = B . getMF ( ) . getFunction ( ) . getCallingConv ( ) ; const bool IsShader = <STR_LIT> ( CC ) ; const bool IsWaveEnd = ( IsShader && MFI -> returnsVoid ( ) ) || <STR_LIT> ( CC ) ; if ( IsWaveEnd ) { B . buildInstr ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; return true ; } unsigned ReturnOpc = IsShader ? <STR_LIT> : <STR_LIT> ;

auto Ret = B . buildInstrNoInsert ( ReturnOpc ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ;

const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = <NUM_LIT> ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == <NUM_LIT> ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , <NUM_LIT> ) ; } else for ( i = <NUM_LIT> ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , GET_MODE_INNER ( mode ) , i == <NUM_LIT> ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; }

return default_assemble_integer ( x , size , aligned_p ) ;


<s> for ( const Use & RootInstUse : RootInst -> uses ( ) ) { User * RootInstUser = RootInstUse . getUser ( ) ; if ( auto * InsertUserCast = dyn_cast < InsertElementInst > ( RootInstUser ) ) { processInsertElementNode ( InsertUserCast , CurrLoop , PHI , TensorId ) ; RootInst = InsertUserCast ; Nested_Ins = true ; break ; } else if ( auto * Intrins = dyn_cast < IntrinsicInst > ( RootInstUser ) ) { <STR_LIT> Inid = Intrins -> getIntrinsicID ( ) ; int index = - <NUM_LIT> ; if ( Inid == <STR_LIT> || Inid == <STR_LIT> ) { if ( Inid == <STR_LIT> ) { int OperandIndex = <NUM_LIT> ; if ( dyn_cast < llvm :: ConstantInt > ( Intrins -> getOperand ( OperandIndex ) ) ) { if ( dyn_cast < Instruction > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) { if ( ! dyn_cast < ICmpInst > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) FallBackVec . insert ( TensorId ) ; else { if ( auto * Icmp = dyn_cast < ICmpInst > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) if ( ! dyn_cast < ConstantInt > ( Icmp -> getOperand ( <NUM_LIT> ) ) ) FallBackVec . insert ( TensorId ) ; } } index = dyn_cast < llvm :: ConstantInt > ( Intrins -> getOperand ( OperandIndex ) ) -> getZExtValue ( ) ; CurrLoop = compareStepValuesForAddMask ( PHI , CurrLoop ) ; int64_t AddMaskStep = getAddMaskStepVar ( Intrins ) ; if ( AddMaskStep != INVALID_STRIDE ) { unsigned Count = fetchIndexFromOperand ( index ) ; unsigned UnrollCount = <NUM_LIT> ; if ( getScevInfo ( CurrLoop ) ) { UnrollCount = getScevInfo ( CurrLoop ) -> getLoopUnrollCount ( CurrLoop ) ; } if ( UnrollCount ) AddMaskStep = AddMaskStep * UnrollCount ; UpdateDiffCoords ( TensorId , Count , AddMaskStep , <STR_LIT> , CurrLoop , PHI ) ; if ( ( <NUM_LIT> << Count ) < index ) { auto Remaining = fetchIndexFromOperand ( index - ( <NUM_LIT> << Count ) ) ; UpdateDiffCoords ( TensorId , Remaining , AddMaskStep , <STR_LIT> , CurrLoop , PHI ) ; } prepareLoopIvCoordMap ( TensorId , nullptr , Count ) ; RootInst = Intrins ; Nested_Ins = true ; break ; } } else { IncorrectIndexSpace = true ; return ; }

if ( dyn_cast < llvm :: ConstantInt > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) {


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override {


<s> static bool hasSMRDSignedImmOffset ( const MCSubtargetInfo & ST ) { return isGFX9Plus ( ST ) ;


<s> addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) ) ) ; const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) {

addPass ( createAMDGPUIndirectAddressingPass ( * TM ) ) ;


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ;


<s> rtx arm_load_function_descriptor ( rtx funcdesc ) { rtx fnaddr_reg = gen_reg_rtx ( Pmode ) ; rtx pic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ;

rtx fnaddr = gen_rtx_MEM ( Pmode , funcdesc ) ;


<s> for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { MachineInstr * DefMIToErase = nullptr ; if ( TII -> convertToImmediateForm ( MI , & DefMIToErase ) ) { Changed = true ; NumRRConvertedInPreEmit ++ ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { return false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getParent ( ) -> begin ( ) != MachineBasicBlock :: const_iterator ( MI ) ) return false ; return MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; } else if ( isVector ( MI ) ) { return false ; } else { return <ISA_LIT>InstrInfo :: isPredicable ( MI ) ;


<s> unsigned Reg = <NUM_LIT> ; int64_t Off ; if ( parseSEHRegisterNumber ( <STR_LIT> , Reg ) ) return true ;

if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitIndIdx ( const MCExpr * Value ) { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( isFrameStoreOpcode ( MI . getOpcode ( ) ) && ! MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) {

return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> for ( const CalleeSavedInfo & CSR : CSI ) { unsigned Reg = CSR . getReg ( ) ; assert ( Reg != <STR_LIT> && ! ( Reg == <STR_LIT> && hasFP ( * MF ) ) && <STR_LIT> ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSR . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; if ( AtStart ) MI = MBB . begin ( ) ; else { MI = BeforeI ;


<s> bool <ISA_LIT>AsmPrinter :: isLoop ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ;

return <ISA_LIT>II :: isLoopInst ( MI . getDesc ( ) ) && Opc != <STR_LIT> ;


<s> return ; } case 'K' : if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; return ; case 'L' : if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; return ; case 'M' : { if ( ! isUInt < <NUM_LIT> > ( CVal ) ) return ; if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; uint64_t NCVal = ~ ( uint32_t ) CVal ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; return ; } case 'N' : { if ( <STR_LIT> ( CVal , <NUM_LIT> ) ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; if ( ( CVal & <NUM_LIT> ) == CVal ) break ; uint64_t NCVal = ~ CVal ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; if ( ( NCVal & <NUM_LIT> ) == NCVal ) break ; return ; } default : return ; } Result = DAG . getTargetConstant ( CVal , SDLoc ( Op ) , <STR_LIT> ) ; break ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ;


<s> if ( VecTy . getVectorElementType ( ) != <STR_LIT> ) { assert ( ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned OpsPerWord = ( ElemSize == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MVT PartVT = <STR_LIT> ( VecTy . getVectorElementType ( ) , OpsPerWord ) ; for ( unsigned i = <NUM_LIT> ; i != VecLen ; i += OpsPerWord ) { SDValue W = buildVector32 ( Values . slice ( i , OpsPerWord ) , dl , PartVT , DAG ) ; Words . push_back ( DAG . getBitcast ( <STR_LIT> , W ) ) ; } } else { Words . assign ( Values . begin ( ) , Values . end ( ) ) ; } unsigned NumWords = Words . size ( ) ; bool IsSplat = true , IsUndef = true ; SDValue SplatV ; for ( unsigned i = <NUM_LIT> ; i != NumWords && IsSplat ; ++ i ) { if ( isUndef ( Words [ i ] ) ) continue ; IsUndef = false ; if ( ! SplatV . getNode ( ) ) SplatV = Words [ i ] ; else if ( SplatV != Words [ i ] ) IsSplat = false ; } if ( IsUndef ) return DAG . getUNDEF ( VecTy ) ; if ( IsSplat ) { assert ( SplatV . getNode ( ) ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( SplatV . getNode ( ) ) ; if ( IdxN && IdxN -> isNullValue ( ) ) return getZero ( dl , VecTy , DAG ) ; MVT WordTy = <STR_LIT> ( <STR_LIT> , HwLen / <NUM_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , WordTy , SplatV ) ; return DAG . getBitcast ( VecTy , S ) ; } SmallVector < ConstantInt * , <NUM_LIT> > Consts ( VecLen ) ; bool AllConst = getBuildVectorConstInts ( Values , VecTy , DAG , Consts ) ; if ( AllConst ) { ArrayRef < Constant * > Tmp ( ( Constant * * ) Consts . begin ( ) , ( Constant * * ) Consts . end ( ) ) ; Constant * CV = ConstantVector :: get ( Tmp ) ; Align Alignment ( HwLen ) ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , VecTy , Alignment ) , DAG ) ; return DAG . getLoad ( VecTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Alignment ) ; } auto IsBuildFromExtracts = [ this , & Values ] ( SDValue & SrcVec , SmallVectorImpl < int > & SrcIdx ) { SDValue Vec ; for ( SDValue V : Values ) { if ( isUndef ( V ) ) { SrcIdx . push_back ( - <NUM_LIT> ) ; continue ; } if ( V . getOpcode ( ) != <STR_LIT> ) return false ;

SDValue T = V . getOperand ( <NUM_LIT> ) ;


<s> PersonalityIndexLocs . push_back ( L ) ;


<s> SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ;

unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ;


<s> MRI . addLiveIn ( PreloadedPrivateBufferReg ) ; MBB . addLiveIn ( PreloadedPrivateBufferReg ) ; } for ( MachineBasicBlock & OtherBB : MF ) { if ( & OtherBB == & MBB ) continue ; if ( OffsetRegUsed ) OtherBB . addLiveIn ( ScratchWaveOffsetReg ) ; if ( ResourceRegUsed ) OtherBB . addLiveIn ( ScratchRsrcReg ) ; } DebugLoc DL ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; bool CopyBuffer = ResourceRegUsed && PreloadedPrivateBufferReg != <STR_LIT> && ST . isAmdCodeObjectV2 ( F ) && ScratchRsrcReg != PreloadedPrivateBufferReg ; bool CopyBufferFirst = TRI -> isSubRegisterEq ( PreloadedPrivateBufferReg , ScratchWaveOffsetReg ) ; if ( CopyBuffer && CopyBufferFirst ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchRsrcReg ) . addReg ( PreloadedPrivateBufferReg , RegState :: Kill ) ; } if ( OffsetRegUsed && PreloadedScratchWaveOffsetReg != ScratchWaveOffsetReg ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchWaveOffsetReg ) . addReg ( PreloadedScratchWaveOffsetReg , MRI . isPhysRegUsed ( ScratchWaveOffsetReg ) ? <NUM_LIT> : RegState :: Kill ) ; } if ( CopyBuffer && ! CopyBufferFirst ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchRsrcReg ) . addReg ( PreloadedPrivateBufferReg , RegState :: Kill ) ; }

if ( ResourceRegUsed ) emitEntryFunctionScratchSetup ( ST , MF , MBB , MFI , I , PreloadedPrivateBufferReg , ScratchRsrcReg ) ;


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src2Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( Src1Reg ) && isIntRegForSubInst ( Src2Reg ) ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DstReg ) && ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && isIntRegForSubInst ( SrcReg ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ( ( isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) || ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) && isIntRegForSubInst ( SrcReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ;

int Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace ) ;


<s> unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false ; } }


<s> const MCExpr * E = MCSymbolRefExpr :: create ( Get<ISA_LIT>GVSymbol ( GV , <STR_LIT> ) , ( Subtarget -> isTargetELF ( ) ? MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : MCSymbolRefExpr :: VK_None ) , OutContext ) ; OutStreamer -> emitValue ( E , Size ) ;


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ;

Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> bool KillsOp0 = MI -> killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI -> killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( KillsOp0 ) freeStackSlotAfter ( I , Op0 ) ; if ( KillsOp1 && Op0 != Op1 ) freeStackSlotAfter ( I , Op1 ) ;


<s> void EmitJal ( MCSymbol * Symbol ) ; void EmitInstrReg ( unsigned Opcode , unsigned Reg ) ; void EmitInstrRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 ) ; void EmitInstrRegRegReg ( unsigned Opcode , unsigned Reg1 , unsigned Reg2 , unsigned Reg3 ) ; void EmitMovFPIntPair ( unsigned MovOpc , unsigned Reg1 , unsigned Reg2 , unsigned FPReg1 , unsigned FPReg2 , bool LE ) ; void EmitSwapFPIntParams ( <STR_LIT> , bool LE , bool ToFP ) ; void EmitSwapFPIntRetval ( <STR_LIT> , bool LE ) ; void EmitFPCallStub ( const char * , const <STR_LIT> * ) ; void NaClAlignIndirectJumpTargets ( MachineFunction & MF ) ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( <NUM_LIT> ) , InConstantPool ( false ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; } virtual const char * getPassName ( ) const { return <STR_LIT> ; } virtual bool runOnMachineFunction ( MachineFunction & MF ) ; virtual void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; virtual void EmitFunctionEntryLabel ( ) ; virtual void EmitFunctionBodyStart ( ) ;


<s> case <NUM_LIT> : align = <NUM_LIT> ; break ; default : return MCDisassembler :: Fail ; } break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

} else Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> if ( MI != MBB . end ( ) && ! MI -> isDebugValue ( ) ) dl = MI -> getDebugLoc ( ) ; if ( isImmMskBitp ( Value ) ) { int N = Log2_32 ( Value ) + <NUM_LIT> ; return BuildMI ( MBB , MI , dl , get ( <STR_LIT> ) , Reg ) . addImm ( N ) ; } if ( isImmU16 ( Value ) ) {

int Opcode = isImmU6 ( Value ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( GVRHS -> isThreadLocal ( ) || GVRHS -> getName ( ) != <STR_LIT> || ! GVRHS -> hasExternalLinkage ( ) || GVRHS -> hasInitializer ( ) || GVRHS -> hasSection ( ) ) return nullptr ; if ( GOLHS -> isThreadLocal ( ) ) return nullptr ; return MCSymbolRefExpr :: create ( TM . getSymbol ( GOLHS , Mang ) , MCSymbolRefExpr :: VK_COFF_IMGREL32 , getContext ( ) ) ;


<s> <ISA_LIT>TargetMasks ( SDValue Mask = SDValue ( ) , SDValue AVL = SDValue ( ) ) : Mask ( Mask ) , AVL ( AVL ) {


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { OW -> WriteZeros ( Count ) ; return true ;


<s> int Cost = BaseT :: getCastInstrCost ( Opcode , Dst , Src , CostKind , I ) ; return vectorCostAdjustment ( Cost , Opcode , Dst , Src ) ;


<s> int hi_val = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < n_elts ; i ++ ) { rtx el = CONST_VECTOR_ELT ( const_vec , i ) ; unsigned HOST_WIDE_INT elpart ; gcc_assert ( CONST_INT_P ( el ) ) ; elpart = INTVAL ( el ) ; for ( int j = <NUM_LIT> ; j < repeat ; j ++ ) hi_val |= elpart << ( i * repeat + j ) ; }

return gen_int_mode ( hi_val , HImode ) ;


<s> static void emitLEAzzi ( MCStreamer & OutStreamer , MCOperand & Imm , MCOperand & RD , const MCSubtargetInfo & STI ) { MCInst LEAInst ; LEAInst . setOpcode ( <STR_LIT> ) ; LEAInst . addOperand ( RD ) ;


<s> else if ( aarch64_evpc_zip ( d ) ) return true ; else if ( aarch64_evpc_uzp ( d ) ) return true ; else if ( aarch64_evpc_trn ( d ) ) return true ; else if ( aarch64_evpc_sel ( d ) ) return true ; if ( d -> vec_flags == VEC_SVE_DATA ) return aarch64_evpc_sve_tbl ( d ) ;

else if ( d -> vec_flags == VEC_ADVSIMD ) return aarch64_evpc_tbl ( d ) ;


<s> } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { uint64_t Mask = V . getConstantOperandVal ( <NUM_LIT> ) ; const SmallVector < ValueBit , <NUM_LIT> > * LHSBits ; std :: tie ( Interesting , LHSBits ) = getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) if ( ( ( Mask >> i ) & <NUM_LIT> ) == <NUM_LIT> ) Bits [ i ] = ( * LHSBits ) [ i ] ; else Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; return std :: make_pair ( Interesting , & Bits ) ; } break ; case <STR_LIT> : { const auto & LHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; const auto & RHSBits = * getValueBits ( V . getOperand ( <NUM_LIT> ) , NumBits ) . second ; bool AllDisjoint = true ; for ( unsigned i = <NUM_LIT> ; i < NumBits ; ++ i ) if ( LHSBits [ i ] . isZero ( ) ) Bits [ i ] = RHSBits [ i ] ; else if ( RHSBits [ i ] . isZero ( ) ) Bits [ i ] = LHSBits [ i ] ; else { AllDisjoint = false ; break ; } if ( ! AllDisjoint ) break ; return std :: make_pair ( Interesting = true , & Bits ) ; } case <STR_LIT> : { if ( V . getValueType ( ) != <STR_LIT> || V . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) break ; const SmallVector < ValueBit , <NUM_LIT> > * LHSBits ; const unsigned NumOperandBits = <NUM_LIT> ; std :: tie ( Interesting , LHSBits ) = getValueBits ( V . getOperand ( <NUM_LIT> ) , NumOperandBits ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperandBits ; ++ i ) Bits [ i ] = ( * LHSBits ) [ i ] ;

for ( unsigned i = NumOperandBits ; i < NumBits ; ++ i ) Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ;


<s> unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; if ( BrOffset < DestOffset && ( DestOffset - BrOffset ) <= <NUM_LIT> ) { MachineBasicBlock :: iterator CmpMI = Br . MI ; if ( CmpMI != Br . MI -> getParent ( ) -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = getInstrPredicate ( * CmpMI , PredReg ) ; if ( Pred == <STR_LIT> && CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && is<ISA_LIT>LowRegister ( Reg ) ) { MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * CmpMI << <STR_LIT> << * Br . MI ) ;

MachineInstr * NewBR = BuildMI ( * MBB , CmpMI , Br . MI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( Reg ) . addMBB ( DestBB , Br . MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) ;


<s> void <ISA_LIT>PassConfig :: addPreRegBankSelect ( ) {

bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ;


<s> if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( isUnsupportedFloatingType ( VT ) ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getUINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; MakeLibCallOptions CallOptions ;

return makeLibCall ( DAG , LC , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , CallOptions , SDLoc ( Op ) ) . first ;


<s> for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( DstReg ) , E = MRI . use_end ( ) ; I != E ; ) { MachineInstr & UseMI = * I -> getParent ( ) ; if ( ! canReadVGPR ( UseMI , I . getOperandNo ( ) ) ) { Worklist . insert ( & UseMI ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! K0 ) return SDValue ( ) ; APFloat :: cmpResult Cmp = K0 -> getValueAPF ( ) . compare ( K1 -> getValueAPF ( ) ) ; if ( Cmp == APFloat :: cmpGreaterThan ) return SDValue ( ) ; EVT VT = Op0 . getValueType ( ) ; if ( Subtarget -> enableDX10Clamp ( ) ) { if ( K1 -> isExactlyValue ( <NUM_LIT> ) && K0 -> isExactlyValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; } if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasMed3_16 ( ) ) ) { SDValue Var = Op0 . getOperand ( <NUM_LIT> ) ; if ( ! isKnownNeverSNan ( DAG , Var ) ) return SDValue ( ) ;

return DAG . getNode ( <STR_LIT> , SL , K0 -> getValueType ( <NUM_LIT> ) , Var , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ;


<s> switch ( Ty . getScalarSizeInBits ( ) ) { case <NUM_LIT> : return isFMAFasterThanFMulAndFAdd ( MF , <STR_LIT> ) ; case <NUM_LIT> :


<s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> memset ( context , <NUM_LIT> , sizeof ( struct _Unwind_Context ) ) ; context -> bsp = context -> regstk_top = ( unsigned long ) bsp ; context -> psp = ( unsigned long ) psp ; context -> rp = ( unsigned long ) rp ; asm ( <STR_LIT> : <STR_LIT> ( context -> sp ) ) ; asm ( <STR_LIT> : <STR_LIT> ( context -> pr ) ) ; context -> pri_unat_loc = & context -> initial_unat ; if ( uw_frame_state_for ( context , & fs ) != _URC_NO_REASON ) abort ( ) ;


<s> const DataLayout * getDataLayout ( ) const override { return & DL ;


<s> if ( Op0 -> getNumOperands ( ) <= <NUM_LIT> ) return ; Kernel . mLanguage = <STR_LIT> ; Kernel . mLanguageVersion . push_back ( mdconst :: extract < ConstantInt > ( Op0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; Kernel . mLanguageVersion . push_back ( mdconst :: extract < ConstantInt > ( Op0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;


<s> auto Fma2 = B . buildFMA ( S64 , NegDivScale0 , Fma1 , One , Flags ) ; auto DivScale1 = B . buildIntrinsic ( <STR_LIT> , { S64 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto Fma3 = B . buildFMA ( S64 , Fma1 , Fma2 , Fma1 , Flags ) ; auto Mul = B . buildFMul ( S64 , DivScale1 . getReg ( <NUM_LIT> ) , Fma3 , Flags ) ; auto Fma4 = B . buildFMA ( S64 , NegDivScale0 , Mul , DivScale1 . getReg ( <NUM_LIT> ) , Flags ) ; Register Scale ; if ( ! ST . hasUsableDivScaleConditionOutput ( ) ) { LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto NumUnmerge = B . buildUnmerge ( S32 , LHS ) ; auto DenUnmerge = B . buildUnmerge ( S32 , RHS ) ; auto Scale0Unmerge = B . buildUnmerge ( S32 , DivScale0 ) ; auto Scale1Unmerge = B . buildUnmerge ( S32 , DivScale1 ) ; auto CmpNum = B . buildICmp ( ICmpInst :: ICMP_EQ , S1 , NumUnmerge . getReg ( <NUM_LIT> ) , Scale1Unmerge . getReg ( <NUM_LIT> ) ) ; auto CmpDen = B . buildICmp ( ICmpInst :: ICMP_EQ , S1 , DenUnmerge . getReg ( <NUM_LIT> ) , Scale0Unmerge . getReg ( <NUM_LIT> ) ) ; Scale = B . buildXor ( S1 , CmpNum , CmpDen ) . getReg ( <NUM_LIT> ) ; } else {

Scale = DivScale1 . getReg ( <NUM_LIT> ) ;


<s> switch ( Node -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , <STR_LIT> ) ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedLoad ( Node ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ;


<s> return ( cfun -> machine -> naked_p && ( cfun -> machine -> va_args_size == <NUM_LIT> ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> EVT TempValLoc = ValVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue ValToCopy = DAG . getBitcast ( TempValLoc , ValArg ) ; if ( ValLoc == <STR_LIT> ) ValToCopy = DAG . getNode ( <STR_LIT> , Dl , ValLoc , ValToCopy ) ; return ValToCopy ; } if ( ( ValVT == <STR_LIT> && ValLoc == <STR_LIT> ) || ( ValVT == <STR_LIT> && ValLoc == <STR_LIT> ) ) { return DAG . getBitcast ( ValLoc , ValArg ) ;


<s> static MachineInstr * LookThroughCOPY ( MachineInstr * MI , MachineRegisterInfo * MRI ) { while ( MI && MI -> getOpcode ( ) == TargetOpcode :: COPY && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ) MI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ;


<s> def_builtin ( <STR_LIT> , CODE_FOR_ldfsr , SPARC_BUILTIN_LDFSR , ftype ) ;


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ;


<s> case <NUM_LIT> : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case <NUM_LIT> : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ;


<s> if ( GET_MODE ( operands [ <NUM_LIT> ] ) == TFmode && ! TARGET_HARD_QUAD ) { operands [ <NUM_LIT> ] = sparc_emit_float_lib_cmp ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , GET_CODE ( operands [ <NUM_LIT> ] ) ) ; operands [ <NUM_LIT> ] = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; } code = GET_CODE ( operands [ <NUM_LIT> ] ) ; x = operands [ <NUM_LIT> ] ; y = operands [ <NUM_LIT> ] ; if ( code == EQ ) { if ( GET_MODE ( x ) == SImode ) { rtx pat ; if ( TARGET_ARCH64 ) pat = gen_seqsidi_special ( operands [ <NUM_LIT> ] , x , y ) ; else pat = gen_seqsisi_special ( operands [ <NUM_LIT> ] , x , y ) ; emit_insn ( pat ) ; return true ; } else if ( GET_MODE ( x ) == DImode ) { rtx pat = gen_seqdi_special ( operands [ <NUM_LIT> ] , x , y ) ; emit_insn ( pat ) ; return true ; } } if ( code == NE ) { if ( GET_MODE ( x ) == SImode ) { rtx pat ; if ( TARGET_ARCH64 ) pat = gen_snesidi_special ( operands [ <NUM_LIT> ] , x , y ) ; else pat = gen_snesisi_special ( operands [ <NUM_LIT> ] , x , y ) ; emit_insn ( pat ) ; return true ; } else if ( GET_MODE ( x ) == DImode ) { rtx pat ; if ( TARGET_VIS3 ) pat = gen_snedi_special_vis3 ( operands [ <NUM_LIT> ] , x , y ) ; else pat = gen_snedi_special ( operands [ <NUM_LIT> ] , x , y ) ; emit_insn ( pat ) ; return true ; } } if ( TARGET_V9 && TARGET_ARCH64 && GET_MODE ( x ) == DImode && ! ( TARGET_VIS3 && ( code == GTU || code == LTU ) ) && gen_v9_scc ( operands [ <NUM_LIT> ] , code , x , y ) ) return true ; if ( code == GTU || code == LEU ) { if ( ( GET_CODE ( x ) == REG || GET_CODE ( x ) == SUBREG ) && ( GET_CODE ( y ) == REG || GET_CODE ( y ) == SUBREG ) ) { tem = x ; x = y ; y = tem ; code = swap_condition ( code ) ; } } if ( code == LTU || ( ! TARGET_VIS3 && code == GEU ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , gen_rtx_fmt_ee ( code , GET_MODE ( operands [ <NUM_LIT> ] ) , gen_compare_reg_1 ( code , x , y ) , const0_rtx ) ) ) ; return true ; } if ( TARGET_V9 && gen_v9_scc ( operands [ <NUM_LIT> ] , code , x , y ) ) return true ; return false ;


<s> if ( cast < AtomicSDNode > ( Op ) -> getOrdering ( ) <= Monotonic ) return Op ; return SDValue ( ) ;


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; unsigned MaxAlign = calculateMaxStackAlignment ( FFI ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ;

RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) MaxAlign = std :: max ( MaxAlign , RI . getRegClass ( RegNum ) -> getAlignment ( ) ) ;


<s> static hashval_t hash ( tree t ) { return htab_hash_pointer ( t ) ;


<s> insn = gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( fp_offset ) ) ; insn = gen_rtx_SET ( SImode , ip_rtx , insn ) ; } else insn = gen_movsi ( ip_rtx , stack_pointer_rtx ) ; insn = emit_insn ( insn ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( args_to_push ) { if ( cfun -> machine -> uses_anonymous_args ) insn = emit_multi_reg_push ( ( <NUM_LIT> >> ( args_to_push / <NUM_LIT> ) ) & <NUM_LIT> ) ; else insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - args_to_push ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( ( func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ ) && ( live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ) != <NUM_LIT> && ! frame_pointer_needed ) emit_insn ( gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , LR_REGNUM ) , gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , LR_REGNUM ) , GEN_INT ( - <NUM_LIT> ) ) ) ) ; if ( live_regs_mask ) { insn = emit_multi_reg_push ( live_regs_mask ) ; saved_regs += bit_count ( live_regs_mask ) * <NUM_LIT> ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( TARGET_IWMMXT ) for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) { insn = gen_rtx_PRE_DEC ( V2SImode , stack_pointer_rtx ) ; insn = gen_frame_mem ( V2SImode , insn ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , insn , gen_rtx_REG ( V2SImode , reg ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; saved_regs += <NUM_LIT> ; } if ( ! IS_VOLATILE ( func_type ) ) { int start_reg ; if ( arm_fpu_arch == FPUTYPE_FPA_EMU2 ) { for ( reg = LAST_FPA_REGNUM ; reg >= FIRST_FPA_REGNUM ; reg -- ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) { insn = gen_rtx_PRE_DEC ( XFmode , stack_pointer_rtx ) ; insn = gen_frame_mem ( XFmode , insn ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , insn , gen_rtx_REG ( XFmode , reg ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; saved_regs += <NUM_LIT> ; } } else { start_reg = LAST_FPA_REGNUM ; for ( reg = LAST_FPA_REGNUM ; reg >= FIRST_FPA_REGNUM ; reg -- ) { if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) { if ( start_reg - reg == <NUM_LIT> ) { insn = emit_sfm ( reg , <NUM_LIT> ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; saved_regs += <NUM_LIT> ; start_reg = reg - <NUM_LIT> ;


<s> int NumV2Elements = count_if ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; const int UnpackLoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int UnpackHiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackLoMask ; else if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) Mask = UnpackHiMask ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( NumV2Elements == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( Subtarget . hasSSSE3 ( ) ) { if ( Subtarget . hasVLX ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; } if ( ! isSingleSHUFPSMask ( Mask ) ) {


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else {

assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ;


<s> return __builtin_mve_vcaddq_rot90_m_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __b , __p ) ;


<s> int AddrOffset = <STR_LIT> ( Desc . TSFlags ) ; if ( AddrOffset >= <NUM_LIT> ) { AddrOffset += <STR_LIT> ( Desc ) ; MachineOperand & p = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; if ( p . isReg ( ) && p . getReg ( ) != <STR_LIT> ) { seekLEAFixup ( p , I , MFI ) ;


<s> Amount /= <NUM_LIT> ; bool isU6 = isImmU6 ( Amount ) ; if ( ! isU6 && ! isImmU16 ( Amount ) ) { errs ( ) << <STR_LIT> << Amount << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } MachineInstr * New ; if ( Old -> getOpcode ( ) == <STR_LIT> ) { int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opcode ) ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == <STR_LIT> ) ; int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opcode ) , <STR_LIT> ) . addImm ( Amount ) ; } MBB . insert ( I , New ) ; } }


<s> else if ( X87_FLOAT_MODE_P ( mode ) && TARGET_FLOAT_RETURNS_IN_80387 ) regno = FIRST_FLOAT_REG ; else regno = AX_REG ; if ( ( fn || fntype ) && ( mode == SFmode || mode == DFmode ) ) { int sse_level = ix86_function_sseregparm ( fntype , fn , false ) ; if ( ( sse_level >= <NUM_LIT> && mode == SFmode ) || ( sse_level == <NUM_LIT> && mode == DFmode ) ) regno = FIRST_SSE_REG ;


<s> gcc_assert ( REG_P ( reg ) ) ; regno = REGNO ( reg ) ; nregs = REG_NREGS ( reg ) / <NUM_LIT> ; gcc_assert ( VFP_REGNO_OK_FOR_DOUBLE ( regno ) || NEON_REGNO_OK_FOR_QUAD ( regno ) ) ; gcc_assert ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) || VALID_NEON_STRUCT_MODE ( mode ) ) ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS ) addr = XEXP ( addr , <NUM_LIT> ) ; switch ( GET_CODE ( addr ) ) { case POST_INC : if ( nregs > <NUM_LIT> ) { templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; } else { templ = <STR_LIT> ; ops [ <NUM_LIT> ] = mem ; } ops [ <NUM_LIT> ] = reg ; break ; case PRE_DEC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; case POST_MODIFY : gcc_unreachable ( ) ; case REG : if ( nregs > <NUM_LIT> ) { if ( nregs > <NUM_LIT> ) templ = <STR_LIT> ;


VLIWPacketizerList :: endPacket ( MBB , MI ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & ) { return new <ISA_LIT>AsmBackend ( <STR_LIT> ) ;


<s> if ( ! reload_completed ) return <NUM_LIT> ; if ( regno == <NUM_LIT> ) return <NUM_LIT> ; for ( r = reg_save_b0 ; r <= reg_save_ar_lc ; r ++ ) if ( regno == current_frame_info . r [ r ] || regno == emitted_frame_related_regs [ r ] ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> unsigned Opcode = Op . getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= TruncSizeInBits ) return true ; return <STR_LIT> ( Op . getNode ( ) ) ; } ; auto TruncateArithmetic = [ & ] ( SDValue N0 , SDValue N1 ) { SDValue Trunc0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ; SDValue Trunc1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; return DAG . getNode ( SrcOpcode , DL , VT , Trunc0 , Trunc1 ) ; } ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; switch ( SrcOpcode ) { case <STR_LIT> : if ( SrcVT . getScalarType ( ) == <STR_LIT> && TLI . isOperationLegal ( SrcOpcode , VT ) && ! TLI . isOperationLegal ( SrcOpcode , SrcVT ) ) return TruncateArithmetic ( Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ;


<s> case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Value ) ; AddValueSymbolsImpl ( BE -> getLHS ( ) , Asm ) ; AddValueSymbolsImpl ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr :: SymbolRef :

Asm -> getOrCreateSymbolData ( cast < MCSymbolRefExpr > ( Value ) -> getSymbol ( ) ) ;


<s> } if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) { report_fatal_error ( <STR_LIT> ) ; }

X -> InitMCCodeGenInfo ( RM , CM , OL ) ;


<s> report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( Chain , dl , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = ( Subtarget -> is64Bit ( ) && ! Subtarget -> isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ;


<s> MachineInstr & MI = * I ; if ( ! isSafeToFold ( MI . getOpcode ( ) ) ) continue ; unsigned OpSize = TII -> getOpSize ( MI , <NUM_LIT> ) ; MachineOperand & OpToFold = MI . getOperand ( <NUM_LIT> ) ; bool FoldingImm = OpToFold . isImm ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( FoldingImm && ! TII -> isInlineConstant ( OpToFold , OpSize ) && ! MRI . hasOneUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; if ( Dst . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > CopiesToReplace ; std :: vector < FoldCandidate > FoldList ; for ( MachineRegisterInfo :: use_iterator Use = MRI . use_begin ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) , E = MRI . use_end ( ) ;


<s> EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ( ! Subtarget -> hasFMA ( ) && ! Subtarget -> hasFMA4 ( ) && ! Subtarget -> hasAVX512 ( ) ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ;

bool NegA = ( A . getOpcode ( ) == <STR_LIT> ) ;


<s> explicit <ISA_LIT>ImagePseudoSourceValue ( const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>PseudoSourceValue ( PSVImage , TM ) {


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MI . getOpcode ( ) == <STR_LIT> ? MCFixupKind ( <STR_LIT> ) : MCFixupKind ( <STR_LIT> ) ;

Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ;


<s> return __builtin_mve_vbrsrq_m_n_fv8hf ( __arm_vuninitializedq_f16 ( ) , __a , __b , __p ) ;


<s> } else if ( isa < MCSymbolRefExpr > ( getImm ( ) ) ) { const MCSymbolRefExpr * SymbolRefExpr = dyn_cast < MCSymbolRefExpr > ( getImm ( ) ) ; assert ( SymbolRefExpr && SymbolRefExpr -> getKind ( ) == MCSymbolRefExpr :: VK_None ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ;

const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ;


<s> if ( ! cfun -> stdarg || ! cfun -> va_list_gpr_size || crtl -> args . info . gprs >= GP_ARG_NUM_REG ) return ;


<s> VLIWMachineScheduler ( MachineSchedContext * C , MachineSchedStrategy * S ) : ScheduleDAGMILive ( C , S ) {


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Parser . Lex ( ) ; SmallVector < uint8_t , <NUM_LIT> > Opcodes ; for ( ; ; ) { const MCExpr * OE ; SMLoc OpcodeLoc = getLexer ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) || Parser . parseExpression ( OE ) ) { Error ( OpcodeLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } const MCConstantExpr * OC = dyn_cast < MCConstantExpr > ( OE ) ; if ( ! OC ) { Error ( OpcodeLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } const int64_t Opcode = OC -> getValue ( ) ; if ( Opcode & ~ <NUM_LIT> ) { Error ( OpcodeLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; }

Opcodes . push_back ( uint8_t ( Opcode ) ) ;


<s> MRI = & MF -> getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; const int InitialVectorSize ( <NUM_LIT> ) ; SwapVector . clear ( ) ; SwapVector . reserve ( InitialVectorSize ) ;


<s> Function * F = M -> getFunction ( Name ) ; assert ( F == nullptr && <STR_LIT> ) ; F = Function :: Create ( FunctionType :: get ( Type :: getVoidTy ( C ) , false ) , Function :: ExternalLinkage , Name , M ) ; assert ( F && <STR_LIT> ) ; F -> setLinkage ( GlobalValue :: LinkOnceODRLinkage ) ; F -> setUnnamedAddr ( GlobalValue :: UnnamedAddr :: Global ) ; F -> addFnAttr ( Attribute :: OptimizeNone ) ; F -> addFnAttr ( Attribute :: NoInline ) ; F -> addFnAttr ( Attribute :: MinSize ) ; F -> addFnAttr ( Attribute :: Naked ) ; MachineFunction & MF = MMI -> getOrCreateMachineFunction ( * F ) ; MF . getProperties ( ) . reset ( MachineFunctionProperties :: Property :: TracksLiveness ) ;

MF . getProperties ( ) . reset ( MachineFunctionProperties :: Property :: IsSSA ) ;


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ;


<s> case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return TT . isOSDarwin ( ) || ReserveX18 ; case <STR_LIT> : case <STR_LIT> :

return TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( Imm & <NUM_LIT> ) ) ; return Success ;


<s> Type * ArgTy = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; unsigned ArgSize = DAG . getDataLayout ( ) . getTypeAllocSize ( ArgTy ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) ) ArgSize = std :: max ( ArgSize , MinSlotSize ) ; bool NeedFPTrunc = false ; if ( VT . isFloatingPoint ( ) && ! VT . isVector ( ) && VT != <STR_LIT> ) { ArgSize = <NUM_LIT> ; NeedFPTrunc = true ; } SDValue VANext = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( ArgSize , DL , PtrVT ) ) ; VANext = DAG . getZExtOrTrunc ( VANext , DL , PtrMemVT ) ; SDValue APStore = DAG . getStore ( Chain , DL , VANext , Addr , MachinePointerInfo ( V ) ) ; if ( NeedFPTrunc ) { SDValue WideFP = DAG . getLoad ( <STR_LIT> , DL , APStore , VAList , MachinePointerInfo ( ) ) ; SDValue NarrowFP = DAG . getNode ( <STR_LIT> , DL , VT , WideFP . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;

SDValue Ops [ ] = { NarrowFP , WideFP . getValue ( <NUM_LIT> ) } ;


<s> return Info ? getMIMGBaseOpcodeInfo ( Info -> BaseOpcode ) : nullptr ;


<s> <ISA_LIT>ELFStreamer :: <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter ) : MCELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) , LastLabel ( nullptr ) {


<s> DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getParent ( ) -> getFunction ( ) -> getName ( ) << <STR_LIT> ) ; unsigned Last = determineLastCalleeSave ( CSI ) ; if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { return true ; }


<s> new <ISA_LIT>TargetELFStreamer ( * S ) ; S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ;

if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitFStart ( MCSymbol * SymStart , MCSymbol * SymEnd , unsigned Alignment ) { unsigned AlignBytes = std :: max ( <NUM_LIT> , <NUM_LIT> << Alignment ) ; const MCExpr * SizeExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( SymEnd , OutContext ) , MCSymbolRefExpr :: Create ( SymStart , OutContext ) , OutContext ) ; <ISA_LIT>TargetStreamer & PTS = static_cast < <ISA_LIT>TargetStreamer & > ( OutStreamer . getTargetStreamer ( ) ) ; PTS . EmitFStart ( SymStart , SizeExpr , AlignBytes ) ;


<s> if ( <STR_LIT> . contains ( Reg ) ) return false ; if ( <STR_LIT> . contains ( Reg ) ) { RegToUseForCFI = getSubReg ( Reg , <STR_LIT> ) ; for ( int I = <NUM_LIT> ; CSR_<ISA_LIT>_AAPCS_SaveList [ I ] ; ++ I ) {

if ( CSR_<ISA_LIT>_AAPCS_SaveList [ I ] == RegToUseForCFI ) return true ;


<s> static parse_codes parse_bif ( void ) { parse_codes result ; diag = & bif_diag ; if ( ! advance_line ( bif_file ) ) return PC_OK ; do result = parse_bif_stanza ( ) ; while ( result == PC_OK ) ;

if ( result == PC_EOFILE ) return PC_OK ;


<s> MCValue Val ; if ( ! E -> EvaluateAsRelocatable ( Val , nullptr , nullptr ) ) return false ;

if ( ! Val . getSymA ( ) || Val . getSymA ( ) -> getSymbol ( ) . isUndefined ( ) ) return false ;


<s> NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Chunk = ( ( <NUM_LIT> << NumBits ) - <NUM_LIT> ) * Scale ; } NumMIs += Bytes / Chunk ; if ( ( Bytes % Chunk ) != <NUM_LIT> ) NumMIs ++ ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; return Infos [ Kind - FirstTargetFixupKind ] ;


<s> MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( ! IsTruncatingStore && <STR_LIT> ) ; ( void ) IsTruncatingStore ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { if ( VT . bitsGE ( IndexVT ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; } else { IndexVT = getContainerForFixedLengthVector ( IndexVT ) ; ContainerVT = <STR_LIT> ( VT . getVectorElementType ( ) , IndexVT . getVectorElementCount ( ) ) ; } Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; Val = convertToScalableVector ( ContainerVT , Val , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ;

Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ;


<s> int sh_dwarf_calling_convention ( tree func ) { if ( sh_attr_renesas_p ( func ) ) return DW_CC_GNU_renesas_sh ; return DW_CC_normal ;


<s> unsigned Fd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ws = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Lane == <NUM_LIT> ) BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Ws , <NUM_LIT> , <STR_LIT> ) ; else { unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) . addImm ( Lane ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ;


<s> Counts . Array [ i ] = std :: min ( Value , WaitCounts . Array [ i ] ) ; } else Counts . Array [ i ] = <NUM_LIT> ; WaitedOn . Array [ i ] = LastIssued . Array [ i ] - Counts . Array [ i ] ; } if ( ! NeedWait ) return false ; if ( Counts . Named . EXP == <NUM_LIT> ) ExpInstrTypesSeen = <NUM_LIT> ; BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WAITCNT ) ) . addImm ( ( Counts . Named . VM & <NUM_LIT> ) | ( ( Counts . Named . EXP & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Counts . Named . LGKM & <NUM_LIT> ) << <NUM_LIT> ) ) ;


<s> for ( size = <NUM_LIT> ; size <= <NUM_LIT> ; size *= <NUM_LIT> ) { HOST_WIDE_INT bits = ( ( HOST_WIDE_INT ) <NUM_LIT> << size ) - <NUM_LIT> ; if ( mask == bits << shift ) return size ; } } return <NUM_LIT> ;


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;


<s> static NewSense Use ( unsigned PR , bool True ) { NewSense NS = { PR , false , false , True } ; return NS ;


<s> SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ;


<s> dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( ! LandMBB ) { dbgs ( ) << <STR_LIT> ; } else { dbgs ( ) << <STR_LIT> << LandMBB -> getNumber ( ) ; } dbgs ( ) << <STR_LIT> ; ) ; int OldOpcode = BranchMI -> getOpcode ( ) ; DebugLoc BranchDL = BranchMI -> getDebugLoc ( ) ; MachineBasicBlock :: iterator I = BranchMI ; insertCondBranchBefore ( I , getBranchNzeroOpcode ( OldOpcode ) , BranchDL ) ; if ( TrueMBB ) { MBB -> splice ( I , TrueMBB , TrueMBB -> begin ( ) , TrueMBB -> end ( ) ) ; MBB -> removeSuccessor ( TrueMBB ) ; if ( LandMBB && TrueMBB -> succ_size ( ) != <NUM_LIT> ) TrueMBB -> removeSuccessor ( LandMBB ) ; retireBlock ( TrueMBB ) ; MLI -> removeBlock ( TrueMBB ) ; } if ( FalseMBB ) { insertInstrBefore ( I , AMDGPU :: ELSE ) ; MBB -> splice ( I , FalseMBB , FalseMBB -> begin ( ) , FalseMBB -> end ( ) ) ; MBB -> removeSuccessor ( FalseMBB ) ; if ( LandMBB && FalseMBB -> succ_size ( ) != <NUM_LIT> ) FalseMBB -> removeSuccessor ( LandMBB ) ; retireBlock ( FalseMBB ) ;


<s> uint16_t validDomains = <NUM_LIT> ; if ( domain && lookup ( MI . getOpcode ( ) , domain ) ) validDomains = <NUM_LIT> ;

else if ( domain && lookupAVX2 ( MI . getOpcode ( ) , domain ) ) validDomains = Subtarget . hasAVX2 ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> virtual SUnit * pickNode ( bool & IsTopNode ) { return <NUM_LIT> ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _bzhi_u32 ( unsigned int __X , unsigned int __Y ) {


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const {


<s> } else { HighV = V2 ; } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else {

int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ;


<s> const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange0_32 ; return Match_Success ; } case <STR_LIT> : case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> >= ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange33_64 ; return Match_Success ; } case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeUImm6 ; return Match_Success ; } case <STR_LIT> : case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange33_64 ; return Match_Success ;


<s> void R600ExpandSpecialInstrsPass :: SetFlagInNewMI ( MachineInstr * NewMI , const MachineInstr * OldMI , unsigned Op ) { int OpIdx = TII -> getOperandIdx ( * OldMI , Op ) ;


<s> MachineInstr * instr = & ( * instr_iter ) ; assert ( InstrPred . find ( instr ) == InstrPred . end ( ) ) ; InstrPred . insert ( std :: make_pair ( instr , pred ) ) ; } for ( auto iter = Successors . begin ( ) , end = Successors . end ( ) ; iter != end ; iter ++ ) {


<s> void emitFunctionType ( const MCSymbolWasm * ) override {


<s> BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ;

BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> PostOrderLoopTraversal ( MachineLoop & ML , MachineLoopInfo & MLI ) : ML ( ML ) , MLI ( MLI ) {


<s> unsigned <ISA_LIT>InstrInfo :: getCExtOpNum ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ;


<s> explicit <ISA_LIT>FrameInfo ( const <ISA_LIT>Subtarget & sti ) : TargetFrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; break ; case <STR_LIT> :

if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ;


<s> Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; Type * RetTy = StructType :: get ( ArgTy , ArgTy , nullptr ) ; auto & DL = DAG . getDataLayout ( ) ; ArgListTy Args ; bool ShouldUseSRet = Subtarget -> isAPCS_ABI ( ) ; SDValue SRet ; if ( ShouldUseSRet ) { const uint64_t ByteSize = DL . getTypeAllocSize ( RetTy ) ; const unsigned StackAlign = DL . getPrefTypeAlignment ( RetTy ) ; int FrameIdx = MFI . CreateStackObject ( ByteSize , StackAlign , false ) ; SRet = DAG . getFrameIndex ( FrameIdx , TLI . getPointerTy ( DL ) ) ; ArgListEntry Entry ; Entry . Node = SRet ; Entry . Ty = RetTy -> getPointerTo ( ) ; Entry . IsSExt = false ; Entry . IsZExt = false ; Entry . IsSRet = true ; Args . push_back ( Entry ) ; RetTy = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } ArgListEntry Entry ;


<s> unsigned BytesPerElement = VT . getVectorElementType ( ) . getStoreSize ( ) ; EVT FromVT = Op . getNode ( ) ? Op . getValueType ( ) : VT ; unsigned FromBytesPerElement = FromVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( FromBytesPerElement < BytesPerElement ) return false ; unsigned Byte = ( ( Elem * FromBytesPerElement ) % <STR_LIT> + ( FromBytesPerElement - BytesPerElement ) ) ; while ( Op . getNode ( ) ) { if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; else if ( Op . getOpcode ( ) == <STR_LIT> && Op . hasOneUse ( ) ) { SmallVector < int , <STR_LIT> > OpBytes ; getVPermMask ( cast < ShuffleVectorSDNode > ( Op ) , OpBytes ) ; int NewByte ; if ( ! getShuffleInput ( OpBytes , Byte , BytesPerElement , NewByte ) ) break ; if ( NewByte < <NUM_LIT> ) { addUndef ( ) ; return true ; } Op = Op . getOperand ( unsigned ( NewByte ) / <STR_LIT> ) ; Byte = unsigned ( NewByte ) % <STR_LIT> ; } else if ( Op . isUndef ( ) ) { addUndef ( ) ; return true ;


<s> const MCExpr * getImm ( ) const { assert ( Kind == KindTy :: Immediate && <STR_LIT> ) ;


<s> return ( ( Opcode == TargetOpcode :: G_FMAD && Subtarget -> hasMadMixInsts ( ) ) || ( Opcode == TargetOpcode :: G_FMA && Subtarget -> hasFmaMixInsts ( ) ) ) && DestTy . getScalarSizeInBits ( ) == <NUM_LIT> && SrcTy . getScalarSizeInBits ( ) == <NUM_LIT> && ! hasFP32Denormals ( * MI . getMF ( ) ) ;


<s> void <ISA_LIT>AsmParser :: SetFrameRegister ( unsigned RegNo ) { Instrumentation -> SetFrameRegister ( RegNo ) ;


<s> Streamer . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; if ( ReadOnlySection . getAlignment ( ) < <NUM_LIT> ) ReadOnlySection . setAlignment ( Align ( <NUM_LIT> ) ) ; const MCSubtargetInfo & STI = MF -> getSubtarget ( ) ; SmallString < <NUM_LIT> > KernelName ; getNameWithPrefix ( KernelName , & MF -> getFunction ( ) ) ; getTargetStreamer ( ) -> EmitAmdhsaKernelDescriptor ( STI , KernelName , getAmdhsaKernelDescriptor ( * MF , CurrentProgramInfo ) , CurrentProgramInfo . NumVGPRsForWavesPerEU , CurrentProgramInfo . NumSGPRsForWavesPerEU - IsaInfo :: getNumExtraSGPRs ( & STI , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed ) , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed , hasXNACK ( STI ) ) ; Streamer . PopSection ( ) ;


<s> SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 , Shift32 ) ; SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , Out64 ) ; } if ( InVT == <STR_LIT> && ResVT == <STR_LIT> ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; SDValue In64 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In ) ; SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In64 ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Out64 , Shift32 ) ;

SDValue Out = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; if ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_64_SwiftError_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ;


return isBareImm ( isInt < <NUM_LIT> > ) ;


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ;


<s> if ( ! has_trailing_nott ( ) ) return false ; remove_insn ( trailing_nott ( ) ) ; return true ;


<s> bool <ISA_LIT>Subtarget :: isCall0ABI ( ) const { return TM . getABIInfo ( ) . getABIType ( ) == <STR_LIT> ;


<s> rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; rtx op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; if ( ! CONST_INT_P ( op1 ) ) { if ( optimize ) warning ( <NUM_LIT> , <STR_LIT> ) ; } else { HOST_WIDE_INT alignTest = INTVAL ( op1 ) ; if ( alignTest <= <NUM_LIT> || alignTest != ( alignTest & - alignTest ) ) { error ( <STR_LIT> ) ; return NULL_RTX ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } return false ;


<s> MachineOperand & opnd = CopyMI -> getOperand ( <NUM_LIT> ) ; if ( ! opnd . isReg ( ) ) return false ; Register Reg = opnd . getReg ( ) ; if ( ! Register :: isVirtualRegister ( Reg ) ) return false ; if ( MRI -> getRegClass ( Reg ) == & <STR_LIT> ) return false ; MachineInstr * DefInsn = MRI -> getVRegDef ( Reg ) ;

if ( ! isInsnFrom32Def ( DefInsn ) ) return false ;


<s> <ISA_LIT>IncomingArgHandler ( MachineIRBuilder & B , MachineRegisterInfo & MRI , CCAssignFn * AssignFn ) : <ISA_LIT>ValueHandler ( true , B , MRI , AssignFn ) {


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override {


<s> bool isMemVY64X ( ) const { return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) && getMemIndexReg ( ) >= <STR_LIT> && getMemIndexReg ( ) <= <STR_LIT> ;


<s> int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , APInt :: getAllOnesValue ( <NUM_LIT> ) , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue ( ) ;


<s> static void createPHIsForSelects ( MachineBasicBlock :: iterator MIItBegin , MachineBasicBlock :: iterator MIItEnd , MachineBasicBlock * TrueMBB , MachineBasicBlock * FalseMBB , MachineBasicBlock * SinkMBB ) { MachineFunction * MF = TrueMBB -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; unsigned CCValid = MIItBegin -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MIItBegin -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MIItBegin -> getDebugLoc ( ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; MIIt = skipDebugInstructionsForward ( ++ MIIt , MIItEnd ) ) { Register DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register TrueReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register FalseReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) std :: swap ( TrueReg , FalseReg ) ; if ( RegRewriteTable . find ( TrueReg ) != RegRewriteTable . end ( ) ) TrueReg = RegRewriteTable [ TrueReg ] . first ; if ( RegRewriteTable . find ( FalseReg ) != RegRewriteTable . end ( ) ) FalseReg = RegRewriteTable [ FalseReg ] . second ;

BuildMI ( * SinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( TrueReg ) . addMBB ( TrueMBB ) . addReg ( FalseReg ) . addMBB ( FalseMBB ) ;


<s> const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getTLSCallPreservedMask ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;

return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , Chain . getValue ( <NUM_LIT> ) ) ;


<s> virtual ~ MachineConstEvaluator ( ) {


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( & <ISA_LIT>MCInstrInfo :: getExpr ( * getImm ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) * <NUM_LIT> ) ) ;


<s> if ( ! getHasJmpExt ( ) ) NegateCC ( LHS , RHS , CC ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; if ( isa < ConstantSDNode > ( LHS . getNode ( ) ) ) std :: swap ( LHS , RHS ) ;

SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ;


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; }


<s> offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset . to_constant ( ) ; for ( unsigned int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ;

if ( bitmap_bit_p ( components , regno ) ) riscv_save_restore_reg ( mode , regno , offset , fn ) ;


<s> static SDValue LowerATOMIC_LOAD_STORE ( SDValue Op , SelectionDAG & DAG ) { if ( isStrongerThanMonotonic ( cast < AtomicSDNode > ( Op ) -> getSuccessOrdering ( ) ) ) { return SDValue ( ) ; } return Op ;


<s> CBucket . ChainSize = ( unsigned ) ( EleNum / ChainNum ) ; if ( CBucket . ChainSize * ChainNum != EleNum ) return false ; if ( SawChainSeparater ) { for ( unsigned i = <NUM_LIT> ; i < CBucket . ChainSize ; i ++ ) for ( unsigned j = <NUM_LIT> ; j < ChainNum ; j ++ ) if ( CBucket . Elements [ i ] . Offset != SE -> getMinusSCEV ( CBucket . Elements [ i + j * CBucket . ChainSize ] . Offset , CBucket . Elements [ j * CBucket . ChainSize ] . Offset ) ) return false ; } for ( unsigned i = <NUM_LIT> ; i < ChainNum ; i ++ ) CBucket . ChainBases . push_back ( CBucket . Elements [ i * CBucket . ChainSize ] ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ChainNum << <STR_LIT> ) ;


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; auto IsHazardFn = [ IsHazardDef , TRI , Reg ] ( MachineInstr * MI ) {

return IsHazardDef ( MI ) && MI -> modifiesRegister ( Reg , TRI ) ;


rewriteFrameIndex ( MachineInstr & MI , unsigned FrameRegIdx , unsigned FrameReg , int Offset , unsigned MOVOpc , unsigned ADDriOpc , unsigned SUBriOpc ) const {


<s> return getTargetMachine ( ) . Options . FloatABIType != FloatABI :: Hard ;


<s> for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( DstReg ) , E = MRI . use_end ( ) ; I != E ; ++ I ) { MachineInstr & UseMI = * I -> getParent ( ) ;

if ( ! canReadVGPR ( UseMI , I . getOperandNo ( ) ) ) {


<s> TieOps = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = <STR_LIT> ; if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> ; else if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> , CommuteIdx = <NUM_LIT> ; else return false ; break ; default : return false ; } if ( CommuteIdx != - <NUM_LIT> ) if ( ! commuteInstruction ( UseMI , false , CommuteIdx , UseIdx ) ) return false ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ;


<s> O << '(' ; printU32 ( MI , OpNo + <NUM_LIT> , O ) ; O << <STR_LIT> ; printU32 ( MI , OpNo + <NUM_LIT> , O ) ;


<s> return true ; } AM = Backup ; if ( matchAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && matchAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) { return true ; } AM = Backup ; if ( ! AM . hasBase ( ) && ! AM . hasIndexReg ( ) ) { N = Handle . getValue ( ) ; AM . BaseReg = N . getOperand ( <NUM_LIT> ) ; AM . IndexReg = N . getOperand ( <NUM_LIT> ) ; AM . Scale = <NUM_LIT> ;


<s> const SDLoc & dl ( N ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Address = N -> getOperand ( <NUM_LIT> ) ; SDValue Predicate = N -> getOperand ( <NUM_LIT> ) ; SDValue Base = N -> getOperand ( <NUM_LIT> ) ; SDValue Modifier = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode ; unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ;


return isMoveWideImm ( <NUM_LIT> , PermittedModifiers , NumModifiers ) ;


<s> static MCStreamer * create<ISA_LIT>NullStreamer ( MCContext & Ctx ) { MCStreamer * S = llvm :: createNullStreamer ( Ctx ) ; new <ISA_LIT>TargetStreamer ( * S ) ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> auto Abs = B . buildFAbs ( S32 , RHS , Flags ) ; const APFloat C0Val ( <NUM_LIT> ) ; auto C0 = B . buildConstant ( S32 , <NUM_LIT> ) ; auto C1 = B . buildConstant ( S32 , <NUM_LIT> ) ; auto C2 = B . buildConstant ( S32 , FloatToBits ( <NUM_LIT> ) ) ; auto CmpRes = B . buildFCmp ( CmpInst :: FCMP_OGT , S1 , Abs , C0 , Flags ) ; auto Sel = B . buildSelect ( S32 , CmpRes , C1 , C2 , Flags ) ; auto Mul0 = B . buildFMul ( S32 , RHS , Sel , Flags ) ; auto RCP = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( Mul0 . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto Mul1 = B . buildFMul ( S32 , LHS , RCP , Flags ) ; B . buildFMul ( Res , Sel , Mul1 , Flags ) ; MI . eraseFromParent ( ) ; return true ;