<s> } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; auto createLoadIntrinsic = [ & ] ( Value * BaseAddr ) { if ( Subtarget -> hasNEON ( ) ) { Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , VecEltTy } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , VecEltTy ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } } ; DenseMap < ShuffleVectorInst * , SmallVector < Value * , <NUM_LIT> >> SubVecs ;

for ( unsigned LoadCount = <NUM_LIT> ; LoadCount < NumLoads ; ++ LoadCount ) {


<s> if ( CurrentArgIndex == Args [ i ] . OrigArgIndex ) { Out . back ( ) ++ ; } else { Out . push_back ( <NUM_LIT> ) ;


<s> static int classify_argument ( machine_mode mode , const_tree type , enum x86_64_reg_class classes [ MAX_CLASSES ] , int bit_offset ) { int zero_width_bitfields = <NUM_LIT> ; static bool warned = false ; int n = classify_argument ( mode , type , classes , bit_offset , zero_width_bitfields ) ;

if ( ! zero_width_bitfields || warned || ! warn_psabi ) return n ;


<s> char symbol_name [ <NUM_LIT> ] ; total_n_vectors = nds32_isr_vectors [ <NUM_LIT> ] . total_n_vectors ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < total_n_vectors ; i ++ ) fprintf ( asm_out_file , <STR_LIT> , i ) ; fprintf ( asm_out_file , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < total_n_vectors ; i ++ ) fprintf ( asm_out_file , <STR_LIT> , i ) ; snprintf ( section_name , sizeof ( section_name ) , <STR_LIT> ) ; snprintf ( symbol_name , sizeof ( symbol_name ) , <STR_LIT> ) ;


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getELFSection ( <STR_LIT> , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getELFSection ( <STR_LIT> , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> FuncInfo ( ) : MemInstCost ( <NUM_LIT> ) , InstCost ( <NUM_LIT> ) , IAMInstCost ( <NUM_LIT> ) , LSMInstCost ( <NUM_LIT> ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> assert ( ! MFI . hasVarSizedObjects ( ) && ! HST . getRegisterInfo ( ) -> hasStackRealignment ( MF ) ) ;

return F . hasFnAttribute ( Attribute :: NoReturn ) && F . hasFnAttribute ( Attribute :: NoUnwind ) && ! F . hasFnAttribute ( Attribute :: UWTable ) && HST . noreturnStackElim ( ) && MFI . getStackSize ( ) == <NUM_LIT> ;


<s> return buildRSRC ( DAG , DL , Ptr , <NUM_LIT> , Rsrc ) ;


<s> reader = new LineReader ( filename ) ; } if ( reader -> fileName ( ) != filename ) { delete reader ; reader = new LineReader ( filename ) ; }


<s> const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; if ( getLexer ( ) . peekTok ( ) . getKind ( ) != AsmToken :: EndOfStatement ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ;

Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ;


<s> case Triple :: IOS : case Triple :: TvOS : return Major < <NUM_LIT> ; case Triple :: WatchOS : return Major < <NUM_LIT> ; case Triple :: MacOSX :


<s> data_section -> unnamed . callback = avr_output_data_section_asm_op ; bss_section -> unnamed . callback = avr_output_bss_section_asm_op ;


<s> if ( CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) return CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;

return JumpTableEntryIndices [ CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ] ;


<s> case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST ; break ; } switch ( MOTy ) { case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = Mang -> getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AsmPrinter . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ;


<s> if ( Group ) Flags |= ELF :: SHF_GROUP ; MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , FnSection . getUniqueID ( ) , & FnSection ) ; assert ( EHSection && <STR_LIT> ) ;


<s> unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( hasStoreToStackSlot ( MI , Accesses ) ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return <NUM_LIT> ;


<s> int mt_epilogue_uses ( int regno ) { if ( cfun -> machine && cfun -> machine -> interrupt_handler && reload_completed ) return <NUM_LIT> ; return regno == GPR_LINK ;


<s> MachineInstr * PopMI = MF . CreateMachineInstr ( get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ;


<s> } if ( StackSize || MFI -> hasCalls ( ) ) { assert ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; unsigned i = <NUM_LIT> ; MachineInstr & MI = * MBBI ; while ( ! MI . getOperand ( i ) . isImm ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } uint64_t Offset = NumBytes + MI . getOperand ( i ) . getImm ( ) ; if ( Offset > <NUM_LIT> ) { NumBytes = Offset - <NUM_LIT> ; Offset = <NUM_LIT> ; emitSPUpdate ( MBB , MBBI , NumBytes , TII ) ; } MI . getOperand ( i ) . ChangeToImmediate ( Offset ) ;


<s> bool IsIEEEMode = MFI -> getMode ( ) . IEEE ; bool HasNSZ = MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; MachineOperand * CurrentKnownM0Val = nullptr ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ( ! HasNSZ && ! MI . getFlag ( MachineInstr :: FmNsz ) ) || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; if ( CurrentKnownM0Val && MI . modifiesRegister ( <STR_LIT> , TRI ) ) CurrentKnownM0Val = nullptr ; continue ; } if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MachineOperand & NewM0Val = MI . getOperand ( <NUM_LIT> ) ; if ( CurrentKnownM0Val && CurrentKnownM0Val -> isIdenticalTo ( NewM0Val ) ) { MI . eraseFromParent ( ) ; continue ; } CurrentKnownM0Val = ( NewM0Val . isReg ( ) && NewM0Val . getReg ( ) . isPhysical ( ) ) ? nullptr : & NewM0Val ; continue ; } MachineOperand & OpToFold = MI . getOperand ( <NUM_LIT> ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) || OpToFold . isGlobal ( ) ;

if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <ISA_LIT>DataLayout , TT , getCPU ( CPU ) , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , SubTarget ( TT , getCPU ( CPU ) , FS , * this ) { this -> TLOF = make_unique < <ISA_LIT>TargetObjectFile > ( ) ; initAsmInfo ( ) ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ;

BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> CommentString = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; if ( TheTriple . getOS ( ) == llvm :: Triple :: Solaris ) UseIntegratedAssembler = true ;


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock * MBB = MII -> getParent ( ) ; DebugLoc DL = MII -> getDebugLoc ( ) ; unsigned Scratch = RS . scavengeRegister ( & <STR_LIT> , MII , <NUM_LIT> ) ; if ( MII -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( MII -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else {

BuildMI ( * MBB , MII , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addImm ( MII -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> int llvm :: getMatchingCondBranchOpcode ( int Opc ) { if ( Opc == <STR_LIT> ) return <STR_LIT> ;


<s> __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( ( ( char * ) mm ) [ s ] ) ) ;


<s> Init = createAString ( <STR_LIT> + std :: to_string ( index ) + <STR_LIT> + LoadStore + <STR_LIT> + printH ( p_SEL -> getAddExpr ( init , innerValueMin ) ) + <STR_LIT> , Int8Ty ) ; ATy = ArrayType :: get ( Int8Ty , Init . size ( ) ) ; llvm :: GlobalVariable * GV2 = new llvm :: GlobalVariable ( * p_M , ATy , false , GlobalValue :: ExternalLinkage , ConstantArray :: get ( ATy , Init ) , Name , GV1 ) ; Init = createAString ( <STR_LIT> + std :: to_string ( index ) + <STR_LIT> + LoadStore + <STR_LIT> + printH ( p_SEL -> getAddExpr ( init , innerValueMax ) ) + <STR_LIT> , Int8Ty ) ; ATy = ArrayType :: get ( Int8Ty , Init . size ( ) ) ; llvm :: GlobalVariable * GV3 = new llvm :: GlobalVariable ( * p_M , ATy , false , GlobalValue :: ExternalLinkage , ConstantArray :: get ( ATy , Init ) , Name , GV2 ) ; GV0 -> setSection ( <STR_LIT> ) ; GV1 -> setSection ( <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { OW -> WriteZeros ( Count ) ;


<s> SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DL ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , Chain . getValue ( <NUM_LIT> ) , DL ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , PtrVT , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget . isTargetKnownWindowsMSVC ( ) || Subtarget . isTargetWindowsItanium ( ) || Subtarget . isTargetWindowsGNU ( ) ) { SDLoc dl ( GA ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget . is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget . is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> , dl ) : ( Subtarget . isTargetWindowsGNU ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> , dl ) : DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ) ; SDValue ThreadPointer = DAG . getLoad ( PtrVT , dl , Chain , TlsArray , MachinePointerInfo ( Ptr ) ) ; SDValue res ; if ( GV -> getThreadLocalMode ( ) == GlobalVariable :: LocalExecTLSModel ) {


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> NumEntries = array_lengthof ( SpillOffsetTable ) ; return SpillOffsetTable ;


<s> return __builtin_aarch64_scvtfhi ( __a , __b ) ;


<s> opts -> x_ix86_force_drap = ptr -> x_ix86_force_drap ; opts -> x_ix86_incoming_stack_boundary_arg = ptr -> x_ix86_incoming_stack_boundary_arg ; opts -> x_ix86_pmode = ptr -> x_ix86_pmode ; opts -> x_ix86_preferred_stack_boundary_arg = ptr -> x_ix86_preferred_stack_boundary_arg ; opts -> x_ix86_recip_name = ptr -> x_ix86_recip_name ; opts -> x_ix86_regparm = ptr -> x_ix86_regparm ; opts -> x_ix86_section_threshold = ptr -> x_ix86_section_threshold ; opts -> x_ix86_sse2avx = ptr -> x_ix86_sse2avx ; opts -> x_ix86_stack_protector_guard = ptr -> x_ix86_stack_protector_guard ; opts -> x_ix86_stringop_alg = ptr -> x_ix86_stringop_alg ; opts -> x_ix86_tls_dialect = ptr -> x_ix86_tls_dialect ; opts -> x_ix86_tune_ctrl_string = ptr -> x_ix86_tune_ctrl_string ; opts -> x_ix86_tune_memcpy_strategy = ptr -> x_ix86_tune_memcpy_strategy ; opts -> x_ix86_tune_memset_strategy = ptr -> x_ix86_tune_memset_strategy ; opts -> x_ix86_tune_no_default = ptr -> x_ix86_tune_no_default ; opts -> x_ix86_veclibabi_type = ptr -> x_ix86_veclibabi_type ; ix86_tune_cost = processor_target_table [ ix86_tune ] . cost ; if ( opts -> x_optimize_size ) ix86_cost = & ix86_size_cost ; else ix86_cost = ix86_tune_cost ; if ( old_arch != ix86_arch ) {


<s> bool <ISA_LIT>ConstantIslands :: OffsetIsInRange ( unsigned UserOffset , unsigned TrialOffset , unsigned MaxDisp , bool NegativeOK , bool IsSoImm ) { if ( UserOffset <= TrialOffset ) { if ( TrialOffset - UserOffset <= MaxDisp ) return true ; } else if ( NegativeOK ) {

if ( UserOffset - TrialOffset <= MaxDisp ) return true ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , cpi ( <NUM_LIT> ) , instructionCount ( <NUM_LIT> ) {


<s> const TargetAsmInfo * <ISA_LIT>TargetMachine :: createTargetAsmInfo ( ) const { return new <ISA_LIT>TargetAsmInfo ( * this ) ;


<s> int64_t ThisVal = NumBytes ; if ( isInt < <NUM_LIT> > ( NumBytes ) ) Opcode = <STR_LIT> ; else { Opcode = <STR_LIT> ; int64_t MinVal = - uint64_t ( <NUM_LIT> ) << <NUM_LIT> ; int64_t MaxVal = ( int64_t ( <NUM_LIT> ) << <NUM_LIT> ) - <NUM_LIT> ; if ( ThisVal < MinVal ) ThisVal = MinVal ; else if ( ThisVal > MaxVal ) ThisVal = MaxVal ; } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) , Reg ) . addReg ( Reg ) . addImm ( ThisVal ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> for ( count = i = MIN_REGS ; i < MAX_REGS ; ++ i ) { regno = REG_ORDER [ i ] ; if ( regno == BP_REG && hfp ) continue ; if ( ! ix86_save_reg ( regno , false , false ) ) break ; ++ count ;


<s> O << <STR_LIT> ; printMemReference ( MI , OpNo , O ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> << <STR_LIT> << target -> getName ( ) << <STR_LIT> << target -> getNumber ( ) << <STR_LIT> ) ; MachineBasicBlock :: instr_iterator II ( BR ) ; while ( II -> isBundledWithPred ( ) ) II -- ; if ( PTM . getCodeModel ( ) == CodeModel :: Large ) { if ( opcode == <STR_LIT> || opcode == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , II , DebugLoc ( ) , PII . get ( <STR_LIT> ) , <STR_LIT> ) ) . add ( BR -> getOperand ( BR -> getNumExplicitOperands ( ) - <NUM_LIT> ) ) ; BR -> RemoveOperand ( BR -> getNumExplicitOperands ( ) - <NUM_LIT> ) ; BR -> addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , false , true ) ) ; opcode = opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } } BR -> setDesc ( PII . get ( opcode ) ) ; int delaySlots = PTM . getSubtargetImpl ( ) -> getCFLDelaySlotCycles ( false ) ; int cycles = delaySlots - PTM . getSubtargetImpl ( ) -> getCFLDelaySlotCycles ( true ) ; MachineBasicBlock :: iterator I = II ; if ( PTM . getSubtargetImpl ( ) -> getCFLType ( ) != <ISA_LIT>Subtarget :: CFL_NON_DELAYED && ! PII . hasRegUse ( & * I ) && PII . canRemoveFromSchedule ( MBB , I ) ) { cycles = PII . moveUp ( MBB , I , cycles ) ; } PII . advanceCycles ( MBB , I , delaySlots - cycles + <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < cycles ; i ++ ) {

AddDefaultPred ( BuildMI ( MBB , I , DebugLoc ( ) , PII . get ( <STR_LIT> ) ) ) ;


<s> const <ISA_LIT>Subtarget & STI = Subtarget ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = <STR_LIT> ; unsigned ADDiu = <STR_LIT> ; if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ;


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( Imm ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint32_t Trunc = static_cast < uint32_t > ( Imm ) ; return <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } default :


<s> } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOffset ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyFORMAT ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyGLC ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySLC ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyTFE ) ;

if ( isGFX10 ( ) ) addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDLC ) ;


<s> SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ;

return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops ) ;


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ;


<s> for ( i = <NUM_LIT> ; i < count ; i ++ ) if ( INTVAL ( CONST_VECTOR_ELT ( x , i ) ) != firstval ) return false ; return true ;


<s> } rtx_insn * xinsn = avr_parallel_insn_from_insns ( insns ) ; INSN_CODE ( xinsn ) = recog ( PATTERN ( xinsn ) , xinsn , NULL ) ; if ( INSN_CODE ( xinsn ) < <NUM_LIT> ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; return false ; } gcc_assert ( CODE_FOR_casesi_qi_sequence == INSN_CODE ( xinsn ) || CODE_FOR_casesi_hi_sequence == INSN_CODE ( xinsn ) ) ; extract_insn ( xinsn ) ; gcc_assert ( <NUM_LIT> == recog_data . n_operands ) ; gcc_assert ( <NUM_LIT> == recog_data . n_dups ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) avr_fdump ( dump_file , <STR_LIT> , i , recog_data . operand [ i ] ) ; fprintf ( dump_file , <STR_LIT> ) ; }


<s> return new <ISA_LIT>RewriteOutArguments ( ) ;


<s> DOTGraphTraits ( bool isSimple = false ) : DefaultDOTGraphTraits ( isSimple ) {


<s> auto top = Value & ( <NUM_LIT> << <NUM_LIT> ) ; auto middle = Value & ( <NUM_LIT> << <NUM_LIT> ) ; auto bottom = Value & <NUM_LIT> ; Value = ( top << <NUM_LIT> ) | ( middle << <NUM_LIT> ) | ( bottom << <NUM_LIT> ) ;


<s> return DecodeVecShiftRImm ( Inst , Imm | <NUM_LIT> , <NUM_LIT> ) ;


<s> EVT VT = Op . getValueType ( ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; unsigned Opc ; bool ExtraOp = false ; switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ;


<s> rtx gen_compare_reg ( rtx cmp ) { return gen_compare_reg_1 ( GET_CODE ( cmp ) , XEXP ( cmp , <NUM_LIT> ) , XEXP ( cmp , <NUM_LIT> ) ) ;


<s> else { Expr = MO . getExpr ( ) ; if ( Offset ) { const MCExpr * OffsetExpr = MCConstantExpr :: create ( Offset , Ctx ) ; Expr = MCBinaryExpr :: createAdd ( Expr , OffsetExpr , Ctx ) ; } } Fixups . push_back ( MCFixup :: create ( Offset , Expr , ( MCFixupKind ) Kind ) ) ; if ( AllowTLS && OpNum + <NUM_LIT> < MI . getNumOperands ( ) ) {

const MCOperand & MOTLS = MI . getOperand ( OpNum + <NUM_LIT> ) ;


<s> if ( ! isShiftOrExtend ( ) ) return false ; <STR_LIT> Ext = ShiftExtend . ShiftType ; if ( RmSize == <NUM_LIT> && ! ( Ext == <STR_LIT> || Ext == <STR_LIT> ) ) return false ; if ( RmSize == <NUM_LIT> && ! ( Ext == <STR_LIT> || Ext == <STR_LIT> ) ) return false ;

return ShiftExtend . Amount == Log2_32 ( MemSize ) || ShiftExtend . Amount == <NUM_LIT> ;


<s> DF -> getFixups ( ) . push_back ( MCFixup :: create ( DF -> getContents ( ) . size ( ) , PersonalityRef , MCFixup :: getKindForSize ( <NUM_LIT> , false ) ) ) ;


<s> if ( TT . isOSBinFormatMachO ( ) ) OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { if ( TT . getArch ( ) == Triple :: x86 ) {

MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int words = <NUM_LIT> ;

if ( sh_pass_in_reg_p ( * cum , mode , type ) && ! TARGET_FPU_DOUBLE && ( sh_round_reg ( * cum , mode ) + ( mode != BLKmode ? CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) : CEIL ( int_size_in_bytes ( type ) , UNITS_PER_WORD ) ) > NPARM_REGS ( mode ) ) ) words = NPARM_REGS ( mode ) - sh_round_reg ( * cum , mode ) ;


<s> bool IsAligned = Alignment == <NUM_LIT> || Alignment >= MemVT . getSizeInBits ( ) / <NUM_LIT> ; if ( RegVT . is256BitVector ( ) && Subtarget -> isUnalignedMem32Slow ( ) && ! DCI . isBeforeLegalizeOps ( ) && ! IsAligned && Ext == <STR_LIT> ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , std :: min ( <NUM_LIT> , Alignment ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getUNDEF ( RegVT ) ; NewVec = Insert128BitVector ( NewVec , Load1 , <NUM_LIT> , DAG , dl ) ; NewVec = Insert128BitVector ( NewVec , Load2 , NumElems / <NUM_LIT> , DAG , dl ) ;

return DCI . CombineTo ( N , NewVec , TF , true ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & Base = MI -> getOperand ( OpNo ) ; const MachineOperand & Offset = MI -> getOperand ( OpNo + <NUM_LIT> ) ; if ( Base . isReg ( ) ) printOperand ( MI , OpNo , O ) ; else assert ( <NUM_LIT> && <STR_LIT> ) ; if ( Offset . isImm ( ) ) {

if ( Offset . getImm ( ) ) O << <STR_LIT> << Offset . getImm ( ) ;


<s> rws_sum [ regno ] . written_by_fp |= flags . is_fp ; rws_sum [ regno ] . written_by_and = flags . is_and ; rws_sum [ regno ] . written_by_or = flags . is_or ;


<s> src_gpr_p = INT_REGNO_P ( src_regno ) ; src_fp_p = FP_REGNO_P ( src_regno ) ; src_vmx_p = ALTIVEC_REGNO_P ( src_regno ) ; src_vsx_p = src_fp_p | src_vmx_p ; } else { src_regno = - <NUM_LIT> ; src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false ; } if ( dest_regno >= <NUM_LIT> && src_regno >= <NUM_LIT> ) { if ( dest_gpr_p ) { if ( src_gpr_p ) return <STR_LIT> ; if ( TARGET_DIRECT_MOVE_128 && src_vsx_p ) return ( WORDS_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ; else if ( TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p ) return <STR_LIT> ; } else if ( TARGET_VSX && dest_vsx_p ) { if ( src_vsx_p ) return <STR_LIT> ; else if ( TARGET_DIRECT_MOVE_128 && src_gpr_p ) return ( WORDS_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ; else if ( TARGET_DIRECT_MOVE && src_gpr_p ) return <STR_LIT> ; } else if ( TARGET_ALTIVEC && dest_vmx_p && src_vmx_p ) return <STR_LIT> ; else if ( dest_fp_p && src_fp_p ) return <STR_LIT> ; } else if ( dest_regno >= <NUM_LIT> && MEM_P ( src ) ) { if ( dest_gpr_p ) { if ( TARGET_QUAD_MEMORY && quad_load_store_p ( dest , src ) ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( TARGET_ALTIVEC && dest_vmx_p && altivec_indexed_or_indirect_operand ( src , mode ) ) return <STR_LIT> ; else if ( TARGET_VSX && dest_vsx_p ) { if ( mode == V16QImode || mode == V8HImode || mode == V4SImode ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( TARGET_ALTIVEC && dest_vmx_p ) return <STR_LIT> ; else if ( dest_fp_p ) return <STR_LIT> ; } else if ( src_regno >= <NUM_LIT> && MEM_P ( dest ) ) { if ( src_gpr_p ) { if ( TARGET_QUAD_MEMORY && quad_load_store_p ( dest , src ) ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( TARGET_ALTIVEC && src_vmx_p && altivec_indexed_or_indirect_operand ( src , mode ) ) return <STR_LIT> ; else if ( TARGET_VSX && src_vsx_p ) { if ( mode == V16QImode || mode == V8HImode || mode == V4SImode ) return <STR_LIT> ; else return <STR_LIT> ;


<s> <ISA_LIT>RegAlloc ( ) : MachineFunctionPass ( ID ) {


<s> if ( TARGET_64BIT ) return gen_adddi3 ( rt , ra , GEN_INT ( c ) ) ; else return gen_addsi3 ( rt , ra , GEN_INT ( c ) ) ;


<s> void <ISA_LIT>MCCodeEmitter :: emitInstruction ( uint64_t Val , unsigned Size , const MCSubtargetInfo & STI , raw_ostream & OS ) const { if ( IsLittleEndian && Size == <NUM_LIT> && isMicro<ISA_LIT> ( STI ) ) { emitInstruction ( Val >> <NUM_LIT> , <NUM_LIT> , STI , OS ) ;

emitInstruction ( Val , <NUM_LIT> , STI , OS ) ;


<s> if ( BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( Amt ) ) { BaseShAmt = BV -> getSplatValue ( ) ; if ( BaseShAmt && BaseShAmt . isUndef ( ) ) BaseShAmt = SDValue ( ) ; } else { if ( Amt . getOpcode ( ) == <STR_LIT> ) Amt = Amt . getOperand ( <NUM_LIT> ) ; ShuffleVectorSDNode * SVN = dyn_cast < ShuffleVectorSDNode > ( Amt ) ; if ( SVN && SVN -> isSplat ( ) ) { unsigned SplatIdx = ( unsigned ) SVN -> getSplatIndex ( ) ; SDValue InVec = Amt . getOperand ( <NUM_LIT> ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { assert ( ( SplatIdx < InVec . getSimpleValueType ( ) . getVectorNumElements ( ) ) && <STR_LIT> ) ; BaseShAmt = InVec . getOperand ( SplatIdx ) ; } else if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( InVec . getOperand ( <NUM_LIT> ) ) ) { if ( C -> getZExtValue ( ) == SplatIdx ) BaseShAmt = InVec . getOperand ( <NUM_LIT> ) ; } } if ( ! BaseShAmt ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , EltVT , InVec , DAG . getIntPtrConstant ( SplatIdx , dl ) ) ; } } if ( BaseShAmt . getNode ( ) ) { assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ; if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; else if ( EltVT . bitsLT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ; return getTargetVShiftNode ( <ISA_LIT>OpcI , dl , VT , R , BaseShAmt , DAG ) ; } } if ( ! Subtarget . is64Bit ( ) && VT == <STR_LIT> && Amt . getOpcode ( ) == <STR_LIT> && Amt . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Amt = Amt . getOperand ( <NUM_LIT> ) ; unsigned Ratio = Amt . getSimpleValueType ( ) . getVectorNumElements ( ) / VT . getVectorNumElements ( ) ;

std :: vector < SDValue > Vals ( Ratio ) ;


<s> return & InstrInfo . getRegisterInfo ( ) ;


<s> return __builtin_mve_vrev32q_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a , __p ) ;


<s> static inline bool isIdenticalOp ( const MachineOperand & MO1 , const MachineOperand & MO2 ) { return MO1 . isIdenticalTo ( MO2 ) && ( ! MO1 . isReg ( ) || ! Register :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ;


<s> for ( ls = sr -> labeled_states ; ls ; ls = ls -> next ) { if ( ls -> label == label ) { free_state_stack ( & sr -> curr ) ;

memcpy ( & sr -> curr , & ls -> saved_state , sizeof ( sr -> curr ) ) ;


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ; assert ( <STR_LIT> . contains ( DestReg , SrcReg ) && <STR_LIT> ) ;


<s> bool IsCrossAddressSpaceOrdering = false ; if ( Ordering != AtomicOrdering :: NotAtomic ) { auto ScopeOrNone = to<ISA_LIT>AtomicScope ( S<ISA_LIT>D , InstrAddrSpace ) ; if ( ! ScopeOrNone ) { reportUnsupported ( MI , <STR_LIT> ) ; return None ; } std :: tie ( Scope , OrderingAddrSpace , IsCrossAddressSpaceOrdering ) = ScopeOrNone . getValue ( ) ; if ( ( OrderingAddrSpace == <STR_LIT> ) || ( ( OrderingAddrSpace & <STR_LIT> ) != OrderingAddrSpace ) || ( ( InstrAddrSpace & <STR_LIT> ) == <STR_LIT> ) ) { reportUnsupported ( MI , <STR_LIT> ) ; return None ; } }

return <ISA_LIT>MemOpInfo ( Ordering , Scope , OrderingAddrSpace , InstrAddrSpace , IsCrossAddressSpaceOrdering , FailureOrdering , IsVolatile , IsNonTemporal ) ;


<s> if ( MFI . hasVarSizedObjects ( ) ) { return - <NUM_LIT> ; } if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ;


<s> if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef ) for ( int M : Mask ) if ( M >= NumElements ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , NewMask ) ; } if ( VT . isInteger ( ) && VT . getScalarSizeInBits ( ) < <NUM_LIT> && canWidenShuffleElements ( Mask ) ) { SmallVector < int , <NUM_LIT> > NewMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; i += <NUM_LIT> ) NewMask . push_back ( Mask [ i ] != - <NUM_LIT> ? Mask [ i ] / <NUM_LIT> : ( Mask [ i + <NUM_LIT> ] != - <NUM_LIT> ? Mask [ i + <NUM_LIT> ] / <NUM_LIT> : - <NUM_LIT> ) ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; V1 = DAG . getNode ( <STR_LIT> , dl , NewVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , NewVT , V2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( NewVT , dl , V1 , V2 , NewMask ) ) ; } int NumV1Elements = <NUM_LIT> , NumUndefElements = <NUM_LIT> , NumV2Elements = <NUM_LIT> ; for ( int M : SVOp -> getMask ( ) ) if ( M < <NUM_LIT> ) ++ NumUndefElements ; else if ( M < NumElements ) ++ NumV1Elements ; else ++ NumV2Elements ; if ( NumV2Elements > NumV1Elements ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( NumV1Elements == NumV2Elements ) {


<s> assert ( Op . getNumOperands ( ) == <NUM_LIT> ) ;

assert ( ( ResVT . getSizeInBits ( ) == <NUM_LIT> || ResVT . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ;


<s> if ( config ( ) . targets ( ) . fixCA53Erratum835769 ( ) ) { factory -> addPrototype ( new <ISA_LIT>CA53Erratum835769Stub ( ) ) ; } if ( config ( ) . targets ( ) . fixCA53Erratum843419 ( ) ) { factory -> addPrototype ( new <ISA_LIT>CA53Erratum843419Stub ( ) ) ; factory -> addPrototype ( new <ISA_LIT>CA53Erratum843419Stub2 ( ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ;

NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ;


<s> for ( const auto & Ty : { v4s32 , v2s64 } ) { setAction ( { G_CONCAT_VECTORS , Ty } , Legal ) ; setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , Ty } , Legal ) ; } setAction ( { G_MERGE_VALUES , <NUM_LIT> , s64 } , Legal ) ; setAction ( { G_UNMERGE_VALUES , s64 } , Legal ) ;


<s> unsigned Dummy ; if ( isFrameStoreOpcode ( MI . getOpcode ( ) , Dummy ) ) { unsigned Reg ; if ( ( Reg = isStoreToStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ;

return hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ;


<s> SDValue V1_HI = extract128BitVector ( V1 , NumElts / <NUM_LIT> , DAG , DL ) ; MVT NewVT = V0_LO . getSimpleValueType ( ) ; SDValue LO = DAG . getUNDEF ( NewVT ) ; SDValue HI = DAG . getUNDEF ( NewVT ) ; if ( Mode ) { if ( ! isUndefLO && ! V0 -> isUndef ( ) ) LO = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V0_LO , V0_HI ) ; if ( ! isUndefHI && ! V1 -> isUndef ( ) ) HI = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V1_LO , V1_HI ) ; } else { if ( ! isUndefLO && ( ! V0_LO -> isUndef ( ) || ! V1_LO -> isUndef ( ) ) ) LO = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V0_LO , V1_LO ) ; if ( ! isUndefHI && ( ! V0_HI -> isUndef ( ) || ! V1_HI -> isUndef ( ) ) ) HI = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V0_HI , V1_HI ) ;


<s> return MVTToWasmReg ( Reg . Type ) ;


<s> { <STR_LIT> CR_TAB <STR_LIT> , <STR_LIT> } , { <STR_LIT> CR_TAB <STR_LIT> , <STR_LIT> } , { <STR_LIT> CR_TAB <STR_LIT> , <STR_LIT> } , { <STR_LIT> CR_TAB <STR_LIT> , <STR_LIT> } } ; xop [ <NUM_LIT> ] = xdest [ n ] ; xop [ <NUM_LIT> ] = src ; xop [ <NUM_LIT> ] = clobber_reg ; avr_asm_len ( asm_code [ n ] [ ldreg_p ] , xop , len , ldreg_p ? <NUM_LIT> : <NUM_LIT> ) ; continue ; } xval = simplify_gen_subreg ( QImode , src , mode , n ) ; ival [ n ] = INTVAL ( xval ) ; if ( n == <NUM_LIT> && n_bytes >= <NUM_LIT> && AVR_HAVE_MOVW ) { rtx lo16 = simplify_gen_subreg ( HImode , src , mode , <NUM_LIT> ) ; rtx hi16 = simplify_gen_subreg ( HImode , src , mode , <NUM_LIT> ) ; if ( INTVAL ( lo16 ) == INTVAL ( hi16 ) ) { if ( <NUM_LIT> != INTVAL ( lo16 ) || ! clear_p ) { avr_asm_len ( <STR_LIT> , & op [ <NUM_LIT> ] , len , <NUM_LIT> ) ; } break ; } } if ( ival [ n ] == <NUM_LIT> ) { if ( ! clear_p ) avr_asm_len ( ldreg_p ? <STR_LIT> : AVR_ZERO_REGNO == REGNO ( xdest [ n ] ) ? <STR_LIT> : <STR_LIT> , & xdest [ n ] , len , <NUM_LIT> ) ; continue ; } if ( clobber_val == ival [ n ] && REGNO ( clobber_reg ) == REGNO ( xdest [ n ] ) ) { continue ; } if ( ldreg_p ) { xop [ <NUM_LIT> ] = xdest [ n ] ; xop [ <NUM_LIT> ] = xval ; avr_asm_len ( <STR_LIT> , xop , len , <NUM_LIT> ) ; continue ; } for ( j = <NUM_LIT> ; j < n ; j ++ ) if ( ival [ j ] == ival [ n ] ) { xop [ <NUM_LIT> ] = xdest [ n ] ; xop [ <NUM_LIT> ] = xdest [ j ] ; avr_asm_len ( <STR_LIT> , xop , len , <NUM_LIT> ) ; done_byte = true ; break ; }


<s> if ( GET_CODE ( addr ) == PLUS && ( GET_CODE ( XEXP ( ( addr ) , <NUM_LIT> ) ) == MULT || ( CONST_INT_P ( XEXP ( ( addr ) , <NUM_LIT> ) ) && ! SMALL_INT ( INTVAL ( XEXP ( ( addr ) , <NUM_LIT> ) ) ) ) ) ) return true ; return false ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _tzcnt_u64 ( unsigned long long __X ) {


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue Addr = DAG . getFrameIndex ( XFI -> getVarArgsFrameIndex ( ) , <STR_LIT> ) ;

return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , Addr , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( ) ) ;


<s> bool isAISrc_512B16 ( ) const { return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; Readfirstlane -> getOperand ( <NUM_LIT> ) . setReg ( BaseOffset ) ; BaseOffset = Readfirstlane -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { if ( ! RBI . constrainGenericRegister ( BaseOffset , <STR_LIT> , * MRI ) ) return false ; } Register M0Base = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , M0Base ) . addReg ( BaseOffset ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Base ) ; } auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( gwsIntrinToOpcode ( IID ) ) ) ; if ( HasVSrc ) {

Register VSrc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( BYTES_BIG_ENDIAN && aarch64_composite_type_p ( type , mode ) ) {

HOST_WIDE_INT size = ( type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ;


<s> AttributeItem item = Contents [ i ] ; switch ( item . Type ) { case AttributeItem :: HiddenAttribute : break ; case AttributeItem :: NumericAttribute :


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ; return & * MIB ;


<s> Table . resize ( Order . size ( ) ) ; for ( RowType & Row : Table ) Row . resize ( Mult * Log , None ) ;


<s> return ( __m128 ) __builtin_ia32_cvtpd2ps ( ( __v2df ) __A ) ;


<s> SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , dl ) ;

SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getParser ( ) . Lex ( ) ; getTargetStreamer ( ) . emitDirectiveCpAdd ( RegOpnd . getGPR32Reg ( ) ) ;


<s> case <STR_LIT> : Success = populateDestinationSPU ( src , dest ) ; break ; case <STR_LIT> : Success = populateDestinationVPU ( src , dest ) ; break ; case <STR_LIT> : Success = populateDestinationLDSlot ( src , dest ) ; break ; case <STR_LIT> : Success = populateDestinationSTSlot ( src , dest ) ; break ; } if ( ! Success ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Success << <STR_LIT> ) ;


<s> void <ISA_LIT>GOT :: finalizeScan ( const Input & pInput ) {


<s> default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return Subtarget -> hasSSE1 ( ) ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : return Subtarget -> hasSSE2 ( ) ? <STR_LIT> : <NUM_LIT> ;


<s> return decodeRegisterClass ( Inst , RegNo , <ISA_LIT>Regs64 ) ;


<s> IsFixed . resize ( Ins . size ( ) , true ) ;

CCState :: AnalyzeFormalArguments ( Ins , Fn ) ;


<s> case TargetOpcode :: G_SHL : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_ASHR : return Helper . tryCombineShiftToUnmerge ( MI , <NUM_LIT> ) ; }


<s> void printf64mem ( const MachineInstr * MI , unsigned OpNo ) {


<s> SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> getOpcode ( ) == <STR_LIT> ) { Elts . push_back ( CurrentOp ) ; continue ; } ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . shl ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> getOpcode ( ) == <STR_LIT> ) { Elts . push_back ( CurrentOp ) ; continue ; } ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt ) , dl , ElementType ) ) ;


<s> unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( DstReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; unsigned SrcOpIdx = <NUM_LIT> ; if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc ) SrcOpIdx = OpIdx ++ ;


<s> unsigned OccupiedDwords ( MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { case AMDGPU :: INTERP_PAIR_XY : case AMDGPU :: INTERP_PAIR_ZW : case AMDGPU :: INTERP_VEC_LOAD : case AMDGPU :: DOT_4 : return <NUM_LIT> ; case AMDGPU :: KILL : return <NUM_LIT> ; default : break ;


<s> if ( OptionalIdx . find ( <ISA_LIT>Operand :: ImmTyExpCompr ) != OptionalIdx . end ( ) ) { Compr = true ; Inst . getOperand ( OperandIdx [ <NUM_LIT> ] ) = Inst . getOperand ( OperandIdx [ <NUM_LIT> ] ) ; Inst . getOperand ( OperandIdx [ <NUM_LIT> ] ) . setReg ( <STR_LIT> ) ; Inst . getOperand ( OperandIdx [ <NUM_LIT> ] ) . setReg ( <STR_LIT> ) ; } for ( auto i = <NUM_LIT> ; i < SrcIdx ; ++ i ) { if ( Inst . getOperand ( OperandIdx [ i ] ) . getReg ( ) != <STR_LIT> ) { EnMask |= Compr ? ( <NUM_LIT> << i * <NUM_LIT> ) : ( <NUM_LIT> << i ) ; } } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyExpVM ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyExpCompr ) ;

Inst . addOperand ( MCOperand :: createImm ( EnMask ) ) ;


<s> const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; if ( ! CN ) return false ; bool IsExact ; APSInt IntVal ( <NUM_LIT> , true ) ;

CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ;


<s> unsigned Align = MFI . getObjectAlignment ( FI ) ; return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , Flag , MFI . getObjectSize ( FI ) , Align ) ;


<s> return __builtin_mve_vaddq_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a , __b , __p ) ;


<s> bool <ISA_LIT>MemoryLegalizer :: insertVmem<ISA_LIT>MDCacheInvalidate ( MachineBasicBlock :: iterator & MI , bool Before ) const {

MachineBasicBlock & MBB = * MI -> getParent ( ) ;


<s> void <ISA_LIT>AsmPrinter :: printT2AddrModeImm12Operand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) { const MachineOperand & MO1 = MI -> getOperand ( OpNum ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; unsigned OffImm = MO2 . getImm ( ) ;

if ( OffImm ) O << <STR_LIT> << OffImm ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) {

assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ;


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> bool isSext ( ) const { llvm_unreachable ( <STR_LIT> ) ; return false ;


<s> if ( A_Base == B_Base && A_Base ) report_fatal_error ( <STR_LIT> , false ) ; if ( A -> isUndefined ( ) || B -> isUndefined ( ) ) { StringRef Name = A -> isUndefined ( ) ? A -> getName ( ) : B -> getName ( ) ; Asm . getContext ( ) . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> + Name + <STR_LIT> ) ; } Value += Writer -> getSymbolAddress ( * A , Layout ) - ( ! A_Base ? <NUM_LIT> : Writer -> getSymbolAddress ( * A_Base , Layout ) ) ; Value -= Writer -> getSymbolAddress ( * B , Layout ) - ( ! B_Base ? <NUM_LIT> : Writer -> getSymbolAddress ( * B_Base , Layout ) ) ; if ( ! A_Base ) Index = A -> getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Type = MachO :: <ISA_LIT>_64_RELOC_UNSIGNED ; MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ; Writer -> addRelocation ( A_Base , Fragment -> getParent ( ) , MRE ) ; if ( B_Base ) RelSymbol = B_Base ; else Index = B -> getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Type = MachO :: <ISA_LIT>_64_RELOC_SUBTRACTOR ; } else { const MCSymbol * Symbol = & Target . getSymA ( ) -> getSymbol ( ) ; if ( Symbol -> isTemporary ( ) && Value ) { const MCSection & Sec = Symbol -> getSection ( ) ; if ( ! Asm . getContext ( ) . getAsmInfo ( ) -> isSectionAtomizableBySymbols ( Sec ) ) Asm . addLocalUsedInReloc ( * Symbol ) ; } RelSymbol = Asm . getAtom ( * Symbol ) ; if ( Symbol -> isInSection ( ) ) { const MCSectionMachO & Section = static_cast < const MCSectionMachO & > ( * Fragment -> getParent ( ) ) ; if ( Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) ) RelSymbol = nullptr ; } if ( RelSymbol ) { if ( RelSymbol != Symbol ) Value += Layout . getSymbolOffset ( * Symbol ) - Layout . getSymbolOffset ( * RelSymbol ) ; } else if ( Symbol -> isInSection ( ) && ! Symbol -> isVariable ( ) ) {

Index = Symbol -> getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ;


<s> return * get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) ;


<s> if ( ! TARGET_SOM ) return <STR_LIT> ; if ( TARGET_GAS ) { if ( cfun && ! cfun -> machine -> in_nsubspa ) { cfun -> machine -> in_nsubspa = <NUM_LIT> ; if ( cfun -> decl && DECL_ONE_ONLY ( cfun -> decl ) && ! DECL_WEAK ( cfun -> decl ) ) return <STR_LIT> ; } else { forget_section ( ) ; }


<s> if ( ( InNumEltBits - NumPackedZeroBits ) <= Known . countMinLeadingZeros ( ) ) if ( SDValue V = truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ) return V ; if ( ( InNumEltBits - NumPackedSignBits ) < DAG . ComputeNumSignBits ( In ) ) if ( SDValue V = truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ) return V ; if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getBitcast ( <STR_LIT> , In ) ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ;

In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask1 ) ;


<s> return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> :


<s> const ArrayRef < MCPhysReg > <ISA_LIT>ABIInfo :: GetByValArgRegs ( ) const {

if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ;


<s> DecodeStatus <ISA_LIT>64Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint64_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } return MCDisassembler :: Fail ;


<s> if ( SET_DEST ( set ) != cc0_rtx ) { if ( GET_CODE ( SET_DEST ( set ) ) == STRICT_LOW_PART ) cc_status . value2 = XEXP ( SET_DEST ( set ) , <NUM_LIT> ) ; else cc_status . value2 = SET_DEST ( set ) ; } break ; case CC_COMPARE : CC_STATUS_INIT ; cc_status . value1 = SET_SRC ( body ) ; break ; case CC_CLOBBER : CC_STATUS_INIT ;


return Memory . OffsetRegNum == <NUM_LIT> && Memory . OffsetImm == nullptr && ( alignOK || Memory . Alignment == Alignment ) ;


<s> } for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; if ( MOP . isReg ( ) && ! MOP . isImplicit ( ) && ( MOP . getReg ( ) == <STR_LIT> || MOP . getReg ( ) == <STR_LIT> ) ) return outliner :: InstrType :: Illegal ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return outliner :: InstrType :: Legal ; if ( MI . isCall ( ) ) { const Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isGlobal ( ) ) { Callee = dyn_cast < Function > ( MOP . getGlobal ( ) ) ; break ; } } if ( Callee && Callee -> getName ( ) == <STR_LIT> ) return outliner :: InstrType :: Illegal ; auto UnknownCallOutlineType = outliner :: InstrType :: Illegal ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) UnknownCallOutlineType = outliner :: InstrType :: LegalTerminator ;

if ( ! Callee ) return UnknownCallOutlineType ;


<s> return ( uint32x4_t ) __builtin_neon_vaddwuv4hi ( ( int32x4_t ) __a , ( int16x4_t ) __b ) ;


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int OpNum , raw_ostream & O , const char * Modifier ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; unsigned TF = MO . getTargetFlags ( ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * Mang -> getSymbol ( GV ) ; printOffset ( MO . getOffset ( ) , O ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ;


<s> if ( GET_MODE ( SET_SRC ( op1 ) ) != flags_mode ) return false ; if ( GET_MODE_CLASS ( flags_mode ) != MODE_CC ) return false ; if ( flags_from_mode ( flags_mode ) & ~ flags_from_mode ( cc_mode ) ) return false ; return true ;


<s> DEBUG ( MDT -> print ( dbgs ( ) , ( const llvm :: Module * ) nullptr ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; DEBUG ( MF . dump ( ) ; ) ; return true ;


<s> uint64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;

uint64_t UImm = Imm << ( <NUM_LIT> - BitSize ) >> ( <NUM_LIT> - BitSize ) ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM , TM . getOptLevel ( ) ) , Lowering ( * TM . getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


<s> bool Modified = false ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = STI . getRegisterInfo ( ) ; TII = STI . getInstrInfo ( ) ; MF . getProperties ( ) . set ( MachineFunctionProperties :: Property :: TracksLiveness ) ; for ( Block & MBB : MF ) { bool ContinueExpanding = true ; unsigned ExpandCount = <NUM_LIT> ; do { assert ( ExpandCount < <NUM_LIT> && <STR_LIT> ) ; bool BlockModified = expandMBB ( MBB ) ; Modified |= BlockModified ; ExpandCount ++ ; ContinueExpanding = BlockModified ; } while ( ContinueExpanding ) ;


<s> DelJmp ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , TII ( tm . getInstrInfo ( ) ) {


<s> <ISA_LIT>AsmBackend ( uint8_t OSABI , bool Is64Bit ) : MCAsmBackend ( ) {


<s> if ( rtx n = find_regno_note ( i , REG_UNUSED , regno ) ) remove_note ( i , n ) ;


<s> int getTCReturnAddrDelta ( ) const {


<s> if ( Mask [ i ] > ( int ) NumElems ) { Mask [ i ] = NumElems ;


<s> setAvailableFeatures ( AssemblerOptions . front ( ) -> getFeatures ( ) ) ; AssemblerOptions . back ( ) -> setFeatures ( AssemblerOptions . front ( ) -> getFeatures ( ) ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>0 ( ) ; return false ;


<s> if ( const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( Expr ) ) { int16_t Val ; switch ( getVariantKind ( RelocStr ) ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : Val = MCE -> getValue ( ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Val = ( ( MCE -> getValue ( ) + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; default :


<s> setOperationAction ( <STR_LIT> , LegalVecVT , Custom ) ; setOperationAction ( <STR_LIT> , LegalVecVT , Custom ) ; } for ( MVT LegalPackedVT : AllPackedVTs ) { setOperationAction ( <STR_LIT> , LegalPackedVT , Custom ) ; setOperationAction ( <STR_LIT> , LegalPackedVT , Custom ) ; }


<s> bool <ISA_LIT>AtomicLower :: runOnFunction ( Function & F ) { SmallVector < AtomicRMWInst * > LocalMemoryAtomics ; for ( Instruction & I : instructions ( F ) ) if ( AtomicRMWInst * RMWI = dyn_cast < AtomicRMWInst > ( & I ) ) if ( RMWI -> getPointerAddressSpace ( ) == ADDRESS_SPACE_LOCAL ) LocalMemoryAtomics . push_back ( RMWI ) ;


<s> } else { DispVal = Op3 . getImm ( ) ; } const MachineOperand & Base = MI . getOperand ( Op ) ; const MachineOperand & Scale = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & IndexReg = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned BaseReg = Base . getReg ( ) ; if ( BaseReg == <STR_LIT> || ( Is64BitMode && DispForReloc ) ) { assert ( IndexReg . getReg ( ) == <NUM_LIT> && Is64BitMode && <STR_LIT> ) ; MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , true ) ; return ; } bool IsPCRel = MCE . earlyResolveAddresses ( ) ? true : false ; unsigned BaseRegNo = - <NUM_LIT> ; if ( BaseReg != <NUM_LIT> && BaseReg != <STR_LIT> ) BaseRegNo = get<ISA_LIT>RegNum ( BaseReg ) ; if ( IndexReg . getReg ( ) == <NUM_LIT> && BaseRegNo != N86 :: ESP && ( ! Is64BitMode || BaseReg != <NUM_LIT> ) ) { if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , true ) ; return ; } if ( ! DispForReloc && DispVal == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; return ; } if ( ! DispForReloc && isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitConstant ( DispVal , <NUM_LIT> ) ; return ; } MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , IsPCRel ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ;


<s> setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; for ( MVT FPVT : <STR_LIT> ( ) ) { for ( MVT OtherFPVT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , FPVT , OtherFPVT , Expand ) ; setTruncStoreAction ( FPVT , OtherFPVT , Expand ) ; } } for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setTruncStoreAction ( VT , <STR_LIT> , Expand ) ; } MVT PtrVT = <STR_LIT> ( TM . getPointerSizeInBits ( <NUM_LIT> ) ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , PtrVT , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT IntVT : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ; setOperationAction ( <STR_LIT> , IntVT , Expand ) ;


<s> DAG . getConstant ( FuncInfo -> getVarArgsFirstGPR ( ) , PtrVT ) , DAG . getConstant ( FuncInfo -> getVarArgsFirstFPR ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) } ; SDValue MemOps [ NumFields ] ; unsigned Offset = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumFields ; ++ I ) { SDValue FieldAddr = Addr ; if ( Offset != <NUM_LIT> ) FieldAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , FieldAddr , DAG . getIntPtrConstant ( Offset ) ) ; MemOps [ I ] = DAG . getStore ( Chain , DL , Fields [ I ] , FieldAddr , MachinePointerInfo ( SV , Offset ) , false , false , <NUM_LIT> ) ; Offset += <NUM_LIT> ; }

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOps , NumFields ) ;


<s> EndLoc = o . EndLoc ; switch ( Kind ) { case Register : Reg = o . Reg ; break ; case Immediate : Imm = o . Imm ; break ; case Token : Tok = o . Tok ; break ; case Memory : Mem = o . Mem ; break ; }


<s> int regno ; int offset_to_frame ; int align_mask ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( need_to_save_reg ( regno ) ) reg_save_size += UNITS_PER_WORD ;

offset_to_frame = crtl -> args . pretend_args_size + reg_save_size ;


<s> bool supportSplitCSR ( MachineFunction * MF ) const override {

return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) ;


<s> BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; unsigned OpNum = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MI -> getOperand ( OpNum ) . setMBB ( NewDest ) ; MI -> setDesc ( TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MI ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII -> AnalyzeBranch ( * MBB , TBB , FBB , Cond , false ) ; MachineBasicBlock * NewBB = splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> replaceSuccessor ( FBB , NewBB ) ; NewBB -> addSuccessor ( FBB ) ; } MachineBasicBlock * NextBB = & * std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , DebugLoc ( ) , TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MIB ) ; MIB . addMBB ( NextBB ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BlockInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( * MI ) ;


<s> } if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ;


<s> CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; break ; case NeoverseN2 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case NeoverseV1 : PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxBytesForLoopAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; break ; case Neoverse512TVB : PrefFunctionLogAlignment = <NUM_LIT> ; VScaleForTuning = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ;


<s> EVT VT = <STR_LIT> ; Opnds . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned Slot = <NUM_LIT> , e = Opnds . size ( ) ; Slot < e ; ++ Slot ) { SmallVectorImpl < SDValue > :: const_iterator I = Opnds . begin ( ) + Slot ; if ( I -> getOpcode ( ) == <STR_LIT> ) { Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; Opnds . push_back ( I -> getOperand ( <NUM_LIT> ) ) ; e += <NUM_LIT> ; continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Idx = I -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue ExtractedFromVec = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , unsigned > :: iterator M = VecInMap . find ( ExtractedFromVec ) ; if ( M == VecInMap . end ( ) ) { VT = ExtractedFromVec . getValueType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( VecInMap . begin ( ) != VecInMap . end ( ) && VT != VecInMap . begin ( ) -> first . getValueType ( ) ) return SDValue ( ) ; M = VecInMap . insert ( std :: make_pair ( ExtractedFromVec , <NUM_LIT> ) ) . first ; VecIns . push_back ( ExtractedFromVec ) ; } M -> second |= <NUM_LIT> << cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; } assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned FullMask = ( <NUM_LIT> << VT . getVectorNumElements ( ) ) - <NUM_LIT> ; for ( DenseMap < SDValue , unsigned > :: const_iterator I = VecInMap . begin ( ) , E = VecInMap . end ( ) ; I != E ; ++ I ) { if ( I -> second != FullMask ) return SDValue ( ) ; }

MVT TestVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ;


<s> <ISA_LIT>TargetAsmStreamer * S = new <ISA_LIT>TargetAsmStreamer ( ) ;

return llvm :: createAsmStreamer ( Ctx , S , OS , isVerboseAsm , useLoc , useCFI , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ;


<s> DiagnosticInfoMisalignedTrap ( StringRef M ) : DiagnosticInfo ( DK_MisalignedTrap , DS_Remark ) , Msg ( M ) {


<s> auto & Tok = Lexer . getTok ( ) ; switch ( Tok . getKind ( ) ) { case AsmToken :: Identifier : { auto & Id = Lexer . getTok ( ) ; const MCExpr * Val ; SMLoc End ; if ( Parser . parsePrimaryExpr ( Val , End ) ) return Error ( <STR_LIT> , Lexer . getTok ( ) ) ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Id . getLoc ( ) , Id . getEndLoc ( ) , <STR_LIT> { Val } ) ) ; break ; } case AsmToken :: Minus : Parser . Lex ( ) ; if ( Lexer . isNot ( AsmToken :: Integer ) ) return Error ( <STR_LIT> , Lexer . getTok ( ) ) ; if ( ParseOperandStartingWithInteger ( true , Operands , NamePair . second ) ) return true ; break ; case AsmToken :: Integer : if ( ParseOperandStartingWithInteger ( false , Operands , NamePair . second ) ) return true ; break ; case AsmToken :: Real : { double Val ;

if ( Tok . getString ( ) . getAsDouble ( Val , false ) ) return Error ( <STR_LIT> , Tok ) ;


<s> EVT VT = Operand . getValueType ( ) ; if ( ( VT == <STR_LIT> && Subtarget . hasFRSQRTES ( ) ) || ( VT == <STR_LIT> && Subtarget . hasFRSQRTE ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAltivec ( ) ) || ( VT == <STR_LIT> && Subtarget . hasVSX ( ) ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = getEstimateRefinementSteps ( VT , Subtarget ) ; UseOneConstNR = ! Subtarget . needsTwoConstNR ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ;


<s> Relocator :: Address S = pReloc . symValue ( ) ; if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) { S = helper_get_PLT_address ( * rsym , pParent ) ; } Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; Relocator :: DWord X = helper_get_page_address ( S + A ) - helper_get_page_address ( P ) ;

pReloc . target ( ) = helper_reencode_adr_imm ( pReloc . target ( ) , ( X >> <NUM_LIT> ) ) ;


<s> if ( volatile_refs_p ( a ) || volatile_refs_p ( b ) ) return <NUM_LIT> ; if ( ( REG_P ( XEXP ( a , <NUM_LIT> ) ) || ( GET_CODE ( XEXP ( a , <NUM_LIT> ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) && ( REG_P ( XEXP ( b , <NUM_LIT> ) ) || ( GET_CODE ( XEXP ( b , <NUM_LIT> ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) { HOST_WIDE_INT val0 = <NUM_LIT> , val1 = <NUM_LIT> ; rtx reg0 , reg1 ; int val_diff ; if ( GET_CODE ( XEXP ( a , <NUM_LIT> ) ) == PLUS ) { reg0 = XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ; val0 = INTVAL ( XEXP ( XEXP ( a , <NUM_LIT> ) , <NUM_LIT> ) ) ; } else reg0 = XEXP ( a , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( b , <NUM_LIT> ) ) == PLUS ) { reg1 = XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ; val1 = INTVAL ( XEXP ( XEXP ( b , <NUM_LIT> ) , <NUM_LIT> ) ) ; } else reg1 = XEXP ( b , <NUM_LIT> ) ; if ( ! const_ok_for_op ( val0 , PLUS ) || ! const_ok_for_op ( val1 , PLUS ) ) return <NUM_LIT> ; if ( arm_eliminable_register ( reg0 ) ) return <NUM_LIT> ; val_diff = val1 - val0 ;


<s> BitVector Candidates = TRI -> getAllocatableSet ( * MBB . getParent ( ) , & <STR_LIT> ) ; for ( MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! Register :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; }

BitVector Available = RS . getRegsAvailable ( & <STR_LIT> ) ;


<s> if ( NumOperands != <NUM_LIT> || ( Ty != MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Ty != MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) llvm_unreachable ( <STR_LIT> ) ; auto Mapping = getValueMapping ( getPartialMappingIdx ( Ty , isFP ) , <NUM_LIT> ) ;

return getInstructionMapping ( DefaultMappingID , <NUM_LIT> , Mapping , NumOperands ) ;


<s> bool <ISA_LIT>AsmParser :: ParseIntelDotOperator ( IntelExprStateMachine & SM , SMLoc & End ) { const AsmToken & Tok = getTok ( ) ; unsigned Offset ; StringRef DotDispStr = Tok . getString ( ) ; if ( DotDispStr . startswith ( <STR_LIT> ) ) DotDispStr = DotDispStr . drop_front ( <NUM_LIT> ) ; if ( Tok . is ( AsmToken :: Real ) ) { APInt DotDisp ; DotDispStr . getAsInteger ( <NUM_LIT> , DotDisp ) ; Offset = DotDisp . getZExtValue ( ) ; } else if ( isParsingMSInlineAsm ( ) && Tok . is ( AsmToken :: Identifier ) ) { std :: pair < StringRef , StringRef > BaseMember = DotDispStr . split ( '.' ) ; if ( SemaCallback -> LookupInlineAsmField ( BaseMember . first , BaseMember . second , Offset ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; } else return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; End = SMLoc :: getFromPointer ( DotDispStr . data ( ) ) ;

const char * DotExprEndLoc = DotDispStr . data ( ) + DotDispStr . size ( ) ;


<s> void ThumbRegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ;

const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> else { int br = <NUM_LIT> ; if ( crtl -> is_leaf ) for ( br = <NUM_LIT> ; br >= <NUM_LIT> && df_regs_ever_live_p ( br ) ; br -- ) ; cfun -> machine -> base_reg = gen_rtx_REG ( Pmode , ( br >= <NUM_LIT> ) ? br : BASE_REGNUM ) ; } s390_register_info ( ) ;


<s> void AMDGPUMCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { int MCOpcode = ST . getInstrInfo ( ) -> pseudoToMCOpcode ( MI -> getOpcode ( ) ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_Register : MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( StringRef ( GV -> getName ( ) ) ) ; MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( Sym , Ctx ) ) ; break ; } case MachineOperand :: MO_TargetIndex : { assert ( MO . getIndex ( ) == AMDGPU :: TI_CONSTDATA_START ) ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( StringRef ( END_OF_TEXT_LABEL_NAME ) ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; MCOp = MCOperand :: CreateExpr ( Expr ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { MCSymbol * Sym = Ctx . GetOrCreateSymbol ( StringRef ( MO . getSymbolName ( ) ) ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; MCOp = MCOperand :: CreateExpr ( Expr ) ; break ;


<s> if ( ParseOperand ( Operands , Mnemonic ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) break ; getLexer ( ) . Lex ( ) ;


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , MCAsmLayout const * Layout , MCFixup const * Fixup ) const { return Expr -> evaluateAsRelocatable ( Res , Layout , Fixup ) ;


<s> JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastMI ) ) ;

createPHIsForSelects ( MIItBegin , MIItEnd , StartMBB , FalseMBB , MBB ) ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> case <STR_LIT> : { Row = II -> getArgOperand ( <NUM_LIT> ) ; Col = II -> getArgOperand ( <NUM_LIT> ) ; break ; } } assert ( Count == <NUM_LIT> && <STR_LIT> ) ; IRBuilder < > Builder ( Inst ) ; LLVMContext & Ctx = Builder . getContext ( ) ; Value * Stride = Builder . getInt64 ( <NUM_LIT> ) ; Value * I8Ptr = Builder . CreateBitCast ( Inst -> getOperand ( <NUM_LIT> ) , Type :: getInt8PtrTy ( Ctx ) ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Inst -> replaceAllUsesWith ( NewInst ) ; } if ( ! NewInst ) splitLD ( Inst ) ; }


<s> static bool buildOpImageSampleExplicitLod ( MachineIRBuilder & MIRBuilder , Register resVReg , const StringRef typeStr , const SmallVectorImpl < Register > & args , <ISA_LIT>GlobalRegistry * GR ) { auto spvTy = GR -> getOrCreate<ISA_LIT>TypeByName ( typeStr , MIRBuilder ) ;


<s> static unsigned decodeLHU ( uint32_t insn ) { switch ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) { default : return UNSUPPORTED ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; }


<s> write_one_arg ( s , NULL_TREE , i + <NUM_LIT> , mode , false ) ; return i + <NUM_LIT> ; } if ( no_arg_types && ! AGGREGATE_TYPE_P ( type ) ) { if ( mode == SFmode ) mode = DFmode ; mode = arg_promotion ( mode ) ; } if ( i > <NUM_LIT> ) s << <STR_LIT> ; s << <STR_LIT> << nvptx_ptx_type_from_mode ( mode , false ) << <STR_LIT> << ( i + <NUM_LIT> ) << ( mode == QImode || mode == HImode ? <STR_LIT> : <STR_LIT> ) ;

if ( mode == BLKmode ) s << <STR_LIT> << int_size_in_bytes ( type ) << <STR_LIT> ;


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSType , IsLittle , Is64Bit ) ;


<s> if ( ! V ) { dbgs ( ) << <STR_LIT> ; return ; } dbgs ( ) << <STR_LIT> ; V -> dump ( ) ; dbgs ( ) << <STR_LIT> ; unsigned cnt = <NUM_LIT> ; for ( const Use & U : V -> uses ( ) ) { dbgs ( ) << <STR_LIT> << cnt << <STR_LIT> ;


<s> int <ISA_LIT>TTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) && <STR_LIT> ) ; if ( Imm == <NUM_LIT> ) return TTI :: TCC_Free ; const DataLayout & DL = getDataLayout ( ) ;

return <STR_LIT> ( Imm , DL . getTypeSizeInBits ( Ty ) , getST ( ) -> is64Bit ( ) ) ;


<s> static bool aarch64_vector_mode_p ( machine_mode mode ) {

return aarch64_vector_mode_supported_p ( mode ) || aarch64_vect_struct_mode_p ( mode ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {

FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; return Result ;


<s> if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7s : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v7 : if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6t2 : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6k : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6m : isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6 : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v5te : <ISA_LIT>ArchFeature = <STR_LIT> ; break ;


<s> if ( BYTES_BIG_ENDIAN ) { bool from_sve_p = aarch64_sve_data_mode_p ( from ) ; bool to_sve_p = aarch64_sve_data_mode_p ( to ) ;

if ( from_sve_p != to_sve_p ) return false ;


<s> SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; if ( ! Commute && MayFoldLoad ( N1 ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ! isa < ConstantSDNode > ( N1 ) || MayFoldIntoStore ( Op ) ) ) return false ; if ( MayFoldLoad ( N1 ) && ( ! isa < ConstantSDNode > ( N0 ) || MayFoldIntoStore ( Op ) ) ) return false ; Promote = true ; } } PVT = <STR_LIT> ; return Promote ;


<s> unsigned int <ISA_LIT>AsmBackend :: getNumFixupKinds ( ) const {

return <STR_LIT> :: NumTargetFixupKinds ;


<s> TargetFrameLowering :: DwarfFrameBase <ISA_LIT>FrameLowering :: getDwarfFrameBase ( const MachineFunction & MF ) const { DwarfFrameBase Loc ; Loc . Kind = DwarfFrameBase :: WasmFrameBase ; const <ISA_LIT>FunctionInfo & MFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( needsSP ( MF ) && MFI . isFrameBaseVirtual ( ) ) { unsigned LocalNum = MFI . getFrameBaseLocal ( ) ; Loc . Location . WasmLoc = { <STR_LIT> , LocalNum } ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - <NUM_LIT> ; std :: string upperCase = Tok . getString ( ) . str ( ) ; std :: string lowerCase = LowercaseString ( upperCase ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( ! RegNum ) return - <NUM_LIT> ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = Parser . getTok ( ) . getLoc ( ) ;


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . ClassifyGlobalReference ( GV , MF . getTarget ( ) ) != <STR_LIT> ) return false ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t MinOffset = - <NUM_LIT> ; for ( auto & UseInstr : MRI . use_nodbg_instructions ( Dst ) ) { if ( UseInstr . getOpcode ( ) != TargetOpcode :: G_PTR_ADD ) return false ;

auto Cst = getIConstantVRegValWithLookThrough ( UseInstr . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , isLittle ( isLittle ) , Subtarget ( nullptr ) , DefaultSubtarget ( TT , CPU , FS , isLittle , this ) , No<ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , this ) , <ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , this ) { Subtarget = & DefaultSubtarget ; initAsmInfo ( ) ;


<s> if ( Type == ELF :: R_NYUZI_GOT ) return true ; return false ;


<s> if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ;


<s> if ( reg == reg2 ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; if ( reg == rreg ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; real = copy_rtx ( PATTERN ( insn ) ) ; if ( reg2 != NULL_RTX ) real = replace_rtx ( real , reg2 , rreg ) ; if ( REGNO ( reg ) == STACK_POINTER_REGNUM ) gcc_checking_assert ( val == <NUM_LIT> ) ; else real = replace_rtx ( real , reg , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ) ; if ( GET_CODE ( real ) == SET ) { rtx set = real ; temp = simplify_rtx ( SET_SRC ( set ) ) ; if ( temp ) SET_SRC ( set ) = temp ; temp = simplify_rtx ( SET_DEST ( set ) ) ; if ( temp ) SET_DEST ( set ) = temp ; if ( GET_CODE ( SET_DEST ( set ) ) == MEM ) { temp = simplify_rtx ( XEXP ( SET_DEST ( set ) , <NUM_LIT> ) ) ; if ( temp ) XEXP ( SET_DEST ( set ) , <NUM_LIT> ) = temp ; } } else { int i ; gcc_assert ( GET_CODE ( real ) == PARALLEL ) ; for ( i = <NUM_LIT> ; i < XVECLEN ( real , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( real , <NUM_LIT> , i ) ) == SET ) { rtx set = XVECEXP ( real , <NUM_LIT> , i ) ; temp = simplify_rtx ( SET_SRC ( set ) ) ; if ( temp ) SET_SRC ( set ) = temp ; temp = simplify_rtx ( SET_DEST ( set ) ) ; if ( temp ) SET_DEST ( set ) = temp ; if ( GET_CODE ( SET_DEST ( set ) ) == MEM ) { temp = simplify_rtx ( XEXP ( SET_DEST ( set ) , <NUM_LIT> ) ) ; if ( temp ) XEXP ( SET_DEST ( set ) , <NUM_LIT> ) = temp ; } RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ;


<s> case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBH_OP1 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 :

case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 :


<s> ASM_GENERATE_INTERNAL_LABEL ( label , <STR_LIT> , labelno ) ; fprintf ( file , <STR_LIT> ) ; op [ <NUM_LIT> ] = gen_rtx_REG ( Pmode , RETURN_REGNUM ) ; op [ <NUM_LIT> ] = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; op [ <NUM_LIT> ] = gen_rtx_MEM ( Pmode , plus_constant ( op [ <NUM_LIT> ] , UNITS_PER_WORD ) ) ; op [ <NUM_LIT> ] = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; op [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , label ) ; SYMBOL_REF_FLAGS ( op [ <NUM_LIT> ] ) = SYMBOL_FLAG_LOCAL ; op [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; if ( flag_pic ) {

op [ <NUM_LIT> ] = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , op [ <NUM_LIT> ] ) , UNSPEC_PLT ) ;


<s> if ( ! mi -> isTerminator ( ) || mi -> isReturn ( ) || mi -> isBundle ( ) ) continue ; switch ( mi -> getOpcode ( ) ) { case <STR_LIT> : rewriteBranch ( mi , <STR_LIT> , dbb ) ; break ; case <STR_LIT> : rewriteBranch ( mi , <STR_LIT> , dbb ) ; break ; case <STR_LIT> : rewriteBranch ( mi , <STR_LIT> , dbb ) ; break ; case <STR_LIT> : rewriteBranch ( mi , <STR_LIT> , dbb ) ; break ; case <STR_LIT> : rewriteBranch ( mi , <STR_LIT> , dbb ) ; break ; case <STR_LIT> : rewriteBranch ( mi , <STR_LIT> , dbb ) ; break ;


<s> int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > ( SplatImm ) ) return false ;

SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc ( N ) , Subtarget -> getXLenVT ( ) ) ;


<s> <ISA_LIT>CCState CCInfo = static_cast < <ISA_LIT>CCState & > ( State ) ; static const MCPhysReg DataRegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg AddrRegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; auto I = CCInfo . F . arg_begin ( ) ; int No = ValNo ; while ( No > <NUM_LIT> ) { No -= I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; I ++ ; }

bool IsPtr = I != CCInfo . F . arg_end ( ) && I -> getType ( ) -> isPointerTy ( ) ;


<s> static inline vec_bint4 vec_unpackh ( vec_bshort8 a ) { return ( ( vec_bint4 ) ( vec_unpackh ( ( vec_short8 ) ( a ) ) ) ) ;


<s> static inline int vec_all_lt ( vec_float4 a , vec_float4 b ) { return ( ( int ) ( spu_extract ( spu_gather ( spu_cmpgt ( b , a ) ) , <NUM_LIT> ) == <NUM_LIT> ) ) ;


<s> TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ;

TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ;


<s> void <ISA_LIT>BaseInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? <NUM_LIT> : <NUM_LIT> ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? <STR_LIT> : <STR_LIT> : isThumb ? Subtarget . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) ; Call -> eraseFromParent ( ) ; } auto IsNonTailCall = [ ] ( MachineInstr & MI ) { return MI . isCall ( ) && ! MI . isReturn ( ) ;


<s> if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( TT . size ( ) == <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printOffset1 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) ) { O << <STR_LIT> ; printU8ImmDecOperand ( MI , OpNo , O ) ; }


<s> bool <ISA_LIT>BaseInstrInfo :: isPredicated ( const MachineInstr * MI ) const { if ( MI -> isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ;

if ( PIdx != - <NUM_LIT> && I -> getOperand ( PIdx ) . getImm ( ) != <STR_LIT> ) return true ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>leTarget ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( The<ISA_LIT>beTarget ) ;

RegisterTargetMachine < <ISA_LIT>TargetMachine > Z ( The<ISA_LIT>Target ) ;


<s> if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; y = x ; if ( TARGET_CMODEL != CMODEL_SMALL && GET_CODE ( y ) == LO_SUM ) y = XEXP ( y , <NUM_LIT> ) ; offset = NULL_RTX ; if ( GET_CODE ( y ) == PLUS && GET_MODE ( y ) == Pmode && CONST_INT_P ( XEXP ( y , <NUM_LIT> ) ) ) { offset = XEXP ( y , <NUM_LIT> ) ; y = XEXP ( y , <NUM_LIT> ) ; } if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_TOCREL ) { y = XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) ; if ( TARGET_XCOFF && GET_CODE ( y ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( y ) && rs6000_real_tls_symbol_ref_p ( get_pool_constant ( y ) ) ) return orig_x ; if ( offset != NULL_RTX ) y = gen_rtx_PLUS ( Pmode , y , offset ) ; if ( ! MEM_P ( orig_x ) ) return y ; else return replace_equiv_address_nv ( orig_x , y ) ; } if ( TARGET_MACHO && GET_CODE ( orig_x ) == LO_SUM && GET_CODE ( XEXP ( orig_x , <NUM_LIT> ) ) == CONST ) { y = XEXP ( XEXP ( orig_x , <NUM_LIT> ) , <NUM_LIT> ) ;

if ( GET_CODE ( y ) == UNSPEC && XINT ( y , <NUM_LIT> ) == UNSPEC_MACHOPIC_OFFSET ) return XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) ;


<s> force = is_costly_group ( group_insns , next_insn ) ; if ( ! force ) return can_issue_more ; if ( sched_verbose > <NUM_LIT> ) fprintf ( dump , <STR_LIT> , * group_count , can_issue_more ) ; if ( rs6000_sched_insert_nops == sched_finish_regroup_exact ) { if ( * group_end ) can_issue_more = <NUM_LIT> ; if ( can_issue_more && ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ; while ( can_issue_more > <NUM_LIT> ) { nop = gen_nop ( ) ; emit_insn_before ( nop , next_insn ) ; can_issue_more -- ; } * group_end = true ; return <NUM_LIT> ; } if ( rs6000_sched_insert_nops < sched_finish_regroup_exact ) { int n_nops = rs6000_sched_insert_nops ; if ( can_issue_more == <NUM_LIT> ) can_issue_more = issue_rate ; can_issue_more -- ; if ( can_issue_more == <NUM_LIT> ) { can_issue_more = issue_rate - <NUM_LIT> ; ( * group_count ) ++ ; end = true ; for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } } while ( n_nops > <NUM_LIT> ) { nop = gen_nop ( ) ;


<s> if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( Idx ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) {


<s> Blend1 &= ( M == ( Lane + Elt ) ) ; assert ( Lane <= M && M < ( Lane + NumEltsPerLane ) && <STR_LIT> ) ; M = M % NumEltsPerLane ; Range1 . first = std :: min ( Range1 . first , M ) ; Range1 . second = std :: max ( Range1 . second , M ) ; } else { M -= NumElts ; Blend2 &= ( M == ( Lane + Elt ) ) ; assert ( Lane <= M && M < ( Lane + NumEltsPerLane ) && <STR_LIT> ) ; M = M % NumEltsPerLane ; Range2 . first = std :: min ( Range2 . first , M ) ; Range2 . second = std :: max ( Range2 . second , M ) ; } } } if ( ! ( <NUM_LIT> <= Range1 . first && Range1 . second < NumEltsPerLane ) || ! ( <NUM_LIT> <= Range2 . first && Range2 . second < NumEltsPerLane ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) > <NUM_LIT> && ( Blend1 || Blend2 ) ) return SDValue ( ) ; auto RotateAndPermute = [ & ] ( SDValue Lo , SDValue Hi , int RotAmt , int Ofs ) { MVT ByteVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue Rotate = DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , DAG . getBitcast ( ByteVT , Hi ) , DAG . getBitcast ( ByteVT , Lo ) , DAG . getConstant ( Scale * RotAmt , DL , <STR_LIT> ) ) ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int Lane = <NUM_LIT> ; Lane != NumElts ; Lane += NumEltsPerLane ) { for ( int Elt = <NUM_LIT> ; Elt != NumEltsPerLane ; ++ Elt ) { int M = Mask [ Lane + Elt ] ;


<s> static void unicosmk_output_dex ( FILE * file ) { struct unicosmk_dex * dex ; int i ; if ( unicosmk_dex_list == NULL ) return ;


<s> IsEligibleForTailCallOptimization ( const <ISA_LIT>CC & <ISA_LIT>CCInfo , unsigned NextStackOffset , const <ISA_LIT>FunctionInfo & FI ) const { if ( ! Enable<ISA_LIT>TailCalls ) return false ;

if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return false ;