<s> void <ISA_LIT>InstPrinter :: printGDS ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O << <STR_LIT> ;


<s> <ISA_LIT>ConstantPoolValue :: ~ <ISA_LIT>ConstantPoolValue ( ) {


<s> void <ISA_LIT>InstructionSelector :: renderVFPF64Imm ( MachineInstrBuilder & NewInstBuilder , const MachineInstr & OldInst , int OpIdx ) const { assert ( OldInst . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ;

APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ;


<s> } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( SpillSize ) ;

BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getFrameOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> eltno ++ ; } src = replace_equiv_address ( src , srcreg ) ; RTVEC_ELT ( vec , nprefix ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , regno ) , src ) ; regno += regno_inc ; for ( i = <NUM_LIT> ; i < nregs ; i ++ , eltno ++ ) { RTVEC_ELT ( vec , nprefix + eltno ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , regno ) , adjust_address_nv ( src , SImode , i * <NUM_LIT> ) ) ;


<s> if ( CPU . empty ( ) || CPU == <STR_LIT> ) { if ( TT . getArch ( ) == Triple :: cpu0 || TT . getArch ( ) == Triple :: cpu0el ) { if ( CPU . empty ( ) || CPU == <STR_LIT> ) { <ISA_LIT>ArchFeature = <STR_LIT> ; }


<s> static void concatSubVector ( Value * * Vec , ArrayRef < Instruction * > InVec , unsigned VecElems , IRBuilder < > & Builder ) { if ( VecElems == <NUM_LIT> ) { for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = InVec [ i ] ; return ; } for ( unsigned j = <NUM_LIT> ; j < VecElems / <NUM_LIT> ; j ++ ) for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i + j * <NUM_LIT> ] = Builder . CreateShuffleVector ( InVec [ j * <NUM_LIT> + i ] , InVec [ j * <NUM_LIT> + i + <NUM_LIT> ] , makeArrayRef ( Concat , <NUM_LIT> ) ) ; if ( VecElems == <NUM_LIT> ) return ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( Vec [ i ] , Vec [ i + <NUM_LIT> ] , Concat ) ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasSGPRInitBug ( ) ) { unsigned NumSGPRs = <STR_LIT> . getNumRegs ( ) ; unsigned Limit = <ISA_LIT>Subtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - <NUM_LIT> ; for ( unsigned i = Limit ; i < NumSGPRs ; ++ i ) {

unsigned Reg = <STR_LIT> . getRegister ( i ) ;


if ( GET_CODE ( op ) != PLUS || GET_MODE ( op ) != Pmode || ! register_operand ( XEXP ( op , <NUM_LIT> ) , Pmode ) || ! ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT && SMALL_INT ( INTVAL ( XEXP ( op , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> unsigned NumRegs = Intervals . size ( ) ; for ( unsigned N = <NUM_LIT> ; N < NumRegs ; ++ N ) if ( VRM -> hasPhys ( Intervals [ N ] -> reg ) ) LRM -> unassign ( * Intervals [ N ] ) ; for ( unsigned N = <NUM_LIT> ; N < NumRegs ; ++ N ) if ( LRM -> checkInterference ( * Intervals [ N ] , StartReg + N ) ) return false ; for ( unsigned N = <NUM_LIT> ; N < NumRegs ; ++ N ) LRM -> assign ( * Intervals [ N ] , StartReg + N ) ; return true ;


<s> op1 = tmp ; } switch ( GET_CODE ( op1 ) ) { case CONST : tmp = XEXP ( op1 , <NUM_LIT> ) ; if ( GET_CODE ( tmp ) != PLUS || GET_CODE ( XEXP ( tmp , <NUM_LIT> ) ) != SYMBOL_REF ) break ; op1 = XEXP ( tmp , <NUM_LIT> ) ; addend = XEXP ( tmp , <NUM_LIT> ) ; case SYMBOL_REF : model = SYMBOL_REF_TLS_MODEL ( op1 ) ; if ( model ) op1 = legitimize_tls_address ( op1 , model , true ) ; else if ( ix86_force_load_from_GOT_p ( op1 ) ) { op1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , op1 ) , ( TARGET_64BIT ? UNSPEC_GOTPCREL : UNSPEC_GOT ) ) ; op1 = gen_rtx_CONST ( Pmode , op1 ) ; op1 = gen_const_mem ( Pmode , op1 ) ; set_mem_alias_set ( op1 , ix86_GOT_alias_set ( ) ) ; } else { tmp = legitimize_pe_coff_symbol ( op1 , addend != NULL_RTX ) ; if ( tmp ) { op1 = tmp ; if ( ! addend ) break ; } else { op1 = operands [ <NUM_LIT> ] ; break ; } } if ( addend ) { op1 = force_operand ( op1 , NULL_RTX ) ; op1 = expand_simple_binop ( Pmode , PLUS , op1 , addend , op0 , <NUM_LIT> , OPTAB_DIRECT ) ; } else op1 = force_operand ( op1 , op0 ) ; if ( op1 == op0 ) return ; op1 = convert_to_mode ( mode , op1 , <NUM_LIT> ) ; default : break ; } if ( ( flag_pic || MACHOPIC_INDIRECT ) && symbolic_operand ( op1 , mode ) ) { if ( TARGET_MACHO && ! TARGET_64BIT ) { if ( MACHOPIC_INDIRECT ) { rtx temp = ( op0 && REG_P ( op0 ) && mode == Pmode ) ? op0 : gen_reg_rtx ( Pmode ) ; op1 = machopic_indirect_data_reference ( op1 , temp ) ; if ( MACHOPIC_PURE ) op1 = machopic_legitimize_pic_address ( op1 , mode , temp == op1 ? <NUM_LIT> : temp ) ; } if ( op0 != op1 && GET_CODE ( op0 ) != MEM ) { rtx insn = gen_rtx_SET ( op0 , op1 ) ; emit_insn ( insn ) ; return ; } if ( GET_CODE ( op0 ) == MEM ) op1 = force_reg ( Pmode , op1 ) ;


<s> bool isLDMBaseRegInList ( const Inst & MI ) { auto BaseReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I < E ; ++ I ) { const auto & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . getReg ( ) == BaseReg ) return true ; } return false ;


<s> case <STR_LIT> : case <STR_LIT> : { int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( static_cast < int > ( OpNo ) == Src2Idx ) { bool IsFMA = Opc == <STR_LIT> ; bool IsF32 = Opc == <STR_LIT> ; unsigned Opc = IsFMA ? <STR_LIT> : ( IsF32 ? <STR_LIT> : <STR_LIT> ) ; const MCInstrDesc & MadDesc = TII -> get ( Opc ) ; return TII -> isInlineConstant ( OpToFold , MadDesc . OpInfo [ OpNo ] . OperandType ) ; }


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return isUInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI -> hasVarSizedObjects ( ) ;


<s> unsigned Opcode = <NUM_LIT> ; bool Match = false ; if ( LoadedVT == <STR_LIT> && isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Opcode = isPre ? <STR_LIT> : <STR_LIT> ; Match = true ; } else if ( LoadedVT == <STR_LIT> && SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = ( LD -> getExtensionType ( ) == <STR_LIT> ) ? ( isPre ? <STR_LIT> : <STR_LIT> ) : ( isPre ? <STR_LIT> : <STR_LIT> ) ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( LD -> getExtensionType ( ) == <STR_LIT> ) { if ( SelectAddrMode3Offset ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ; } } else { if ( isPre && SelectAddrMode2OffsetImmPre ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( ! isPre && SelectAddrMode2OffsetImm ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = <STR_LIT> ; } else if ( SelectAddrMode2OffsetReg ( N , LD -> getOffset ( ) , Offset , AMOpc ) ) { Match = true ; Opcode = isPre ? <STR_LIT> : <STR_LIT> ;


<s> } auto IsValidSub = [ ] ( MachineInstr * MI , int ExpectedVecWidth ) { return - getAddSubImmediate ( * MI ) == ExpectedVecWidth ; } ; MachineBasicBlock * MBB = VCTP -> getParent ( ) ; if ( auto * Def = RDA . getUniqueReachingMIDef ( & MBB -> back ( ) , VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) . asMCReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > ElementChain ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; unsigned ExpectedVectorWidth = getTailPredVectorWidth ( VCTP -> getOpcode ( ) ) ; Ignore . insert ( VCTPs . begin ( ) , VCTPs . end ( ) ) ; if ( TryRemove ( Def , RDA , ElementChain , Ignore ) ) { bool FoundSub = false ; for ( auto * MI : ElementChain ) { if ( isMovRegOpcode ( MI -> getOpcode ( ) ) ) continue ; if ( isSubImmOpcode ( MI -> getOpcode ( ) ) ) { if ( FoundSub || ! IsValidSub ( MI , ExpectedVectorWidth ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << * MI ) ; return false ; } FoundSub = true ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << * MI ) ; return false ; } } ToRemove . insert ( ElementChain . begin ( ) , ElementChain . end ( ) ) ; } } if ( ( Start -> getOpcode ( ) == <STR_LIT> || Start -> getOpcode ( ) == <STR_LIT> ) && Preheader && ! Preheader -> empty ( ) && ! RDA . hasLocalDefBefore ( VCTP , VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { if ( auto * Def = RDA . getUniqueReachingMIDef ( & Preheader -> back ( ) , VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) . asMCReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore ; Ignore . insert ( VCTPs . begin ( ) , VCTPs . end ( ) ) ; TryRemove ( Def , RDA , ToRemove , Ignore ) ; }


<s> static bool isLiteralsPair ( const MachineInstr * FirstMI , const MachineInstr & SecondMI ) { unsigned FirstOpcode = FirstMI ? FirstMI -> getOpcode ( ) : static_cast < unsigned > ( <STR_LIT> ) ;

unsigned SecondOpcode = SecondMI . getOpcode ( ) ;


<s> MachineInstr * DPRMI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * SPRMI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DPRMI && SPRMI ) { MachineInstr * ECDef = elideCopies ( DPRMI ) ; if ( ECDef && ECDef -> isImplicitDef ( ) ) { MachineInstr * EC = elideCopies ( SPRMI ) ; if ( EC && EC -> isCopy ( ) && EC -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SPRMI ) ; unsigned FullReg = SPRMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * TRC = MRI -> getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TRC -> hasSuperClassEq ( MRI -> getRegClass ( FullReg ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << printReg ( FullReg ) << <STR_LIT> ) ; eraseInstrWithNoUses ( MI ) ; return FullReg ; } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MI -> isRegSequence ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { unsigned NumImplicit = <NUM_LIT> , NumTotal = <NUM_LIT> ; unsigned NonImplicitReg = ~ <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumExplicitOperands ( ) ; ++ I ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) continue ; ++ NumTotal ; unsigned OpReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( OpReg ) ) break ; MachineInstr * Def = MRI -> getVRegDef ( OpReg ) ; if ( ! Def ) break ; if ( Def -> isImplicitDef ( ) ) ++ NumImplicit ; else NonImplicitReg = MI -> getOperand ( I ) . getReg ( ) ; }

if ( NumImplicit == NumTotal - <NUM_LIT> ) return optimizeAllLanesPattern ( MI , NonImplicitReg ) ;


<s> rtx tilegx_eh_return_handler_rtx ( void ) { rtx tmp = gen_frame_mem ( Pmode , hard_frame_pointer_rtx ) ; MEM_VOLATILE_P ( tmp ) = true ;


<s> Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } uint32_t CRNum ; bool BadNum = Tok . drop_front ( ) . getAsInteger ( <NUM_LIT> , CRNum ) ; if ( BadNum || CRNum > <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCExpr * CRImm = MCConstantExpr :: Create ( CRNum , getContext ( ) ) ; Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( CRImm , S , E ) ) ;


<s> bool writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const override {

if ( Count % <NUM_LIT> != <NUM_LIT> ) return false ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> Register = ( Insn >> <NUM_LIT> ) & <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Register ] ) ) ; return MCDisassembler :: Success ;


<s> static SDValue emitMemMemImm ( SelectionDAG & DAG , const SDLoc & DL , unsigned Op , SDValue Chain , SDValue Dst , SDValue Src , uint64_t Size , SDValue Byte = SDValue ( ) ) { unsigned Adj = getMemMemLenAdj ( Op ) ; assert ( Size >= Adj && <STR_LIT> ) ;

SDValue LenAdj = DAG . getConstant ( Size - Adj , DL , Dst . getValueType ( ) ) ;


<s> return ( __m64 ) __builtin_ia32_psllw ( ( __v4hi ) __m , ( long long ) __count ) ;


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrWithOffset . first ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PtrWithOffset . second ) ; } , } } ;


<s> MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( MPO . getAddrSpace ( ) , <NUM_LIT> ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ;


<s> static SDValue LowerTRUNCATE ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getValueType ( ) ; <STR_LIT> simpleVT = VT . getSimpleVT ( ) ; MVT VecVT = <STR_LIT> ( VT , ( <NUM_LIT> / VT . getSizeInBits ( ) ) ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; MVT Op0VT = Op0 . getValueType ( ) ; if ( Op0VT . getSimpleVT ( ) == <STR_LIT> && simpleVT == <STR_LIT> ) {


<s> static bool DisassembleThumbFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , BO Builder ) { uint16_t HalfWord = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( HalfWord == <NUM_LIT> ) { uint16_t op = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;

return DisassembleThumb1 ( op , MI , Opcode , insn , NumOps , NumOpsAdded , Builder ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ;


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T ) : <ISA_LIT>AsmBackend ( T , false ) {


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ;


<s> std :: iota ( SMask . begin ( ) , SMask . end ( ) , <NUM_LIT> ) ; Work [ OtherW ] . clear ( ) ; if ( Work [ ThisW ] . size ( ) % <NUM_LIT> != <NUM_LIT> ) Work [ ThisW ] . push_back ( UndefValue :: get ( Ty ) ) ; for ( int i = <NUM_LIT> , e = Work [ ThisW ] . size ( ) ; i < e ; i += <NUM_LIT> ) { Value * Joined = Builder . CreateShuffleVector ( Work [ ThisW ] [ i ] , Work [ ThisW ] [ i + <NUM_LIT> ] , SMask ) ; Work [ OtherW ] . push_back ( Joined ) ; } std :: swap ( ThisW , OtherW ) ; } SMask . resize ( Vecs . size ( ) * getSizeOf ( Vecs . front ( ) -> getType ( ) ) ) ; std :: iota ( SMask . begin ( ) , SMask . end ( ) , <NUM_LIT> ) ; Value * Total = Work [ OtherW ] . front ( ) ;

return Builder . CreateShuffleVector ( Total , UndefValue :: get ( Total -> getType ( ) ) , SMask ) ;


<s> static SDValue combineFMADDSUB ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool LegalOperations = ! DCI . isBeforeLegalizeOps ( ) ; SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; if ( TLI . getNegatibleCost ( N2 , DAG , LegalOperations , CodeSize ) != TargetLowering :: NegatibleCost :: Cheaper ) return SDValue ( ) ; SDValue NegN2 = TLI . getNegatedExpression ( N2 , DAG , LegalOperations , CodeSize ) ; unsigned NewOpcode = negateFMAOpcode ( N -> getOpcode ( ) , false , true , false ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegN2 , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegN2 ) ;


<s> bool hasNoInitSection ( ) const override {


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ;

OS << <STR_LIT> << toSymbol ( CurrentFnSym -> getName ( ) ) << '\n' ;


<s> bool sh2a_function_vector_p ( tree func ) { tree list ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; list = SH_ATTRIBUTES ( func ) ; while ( list ) { if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( list ) ) ) return true ;


<s> MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( * Update ) ) . addOperand ( getLdStRegOp ( * I ) ) . addOperand ( getLdStBaseOp ( * I ) ) . addImm ( Value ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } else { int Scale = getMemScale ( * I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( * Update ) ) . addOperand ( getLdStRegOp ( * I , <NUM_LIT> ) ) . addOperand ( getLdStRegOp ( * I , <NUM_LIT> ) ) . addOperand ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } ( void ) MIB ;

if ( IsPreIdx ) DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> StringRef getPassName ( ) const override {


<s> assert ( Addr && Addr -> isFI ( ) ) ; FrameIndex = Addr -> getIndex ( ) ;

return getNamedOperand ( MI , <STR_LIT> :: data ) -> getReg ( ) ;


<s> return ( __m64 ) __builtin_arm_wavg2h ( ( __v4hi ) __A , ( __v4hi ) __B ) ;


<s> NewVarInfo . AliveBlocks . set ( BBNum ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << '\n' ) ; OldVarInfo . AliveBlocks . reset ( BBNum ) ; } } auto I = OldVarInfo . Kills . begin ( ) ; while ( I != OldVarInfo . Kills . end ( ) ) { if ( ElseBlocks . contains ( ( * I ) -> getParent ( ) ) ) { NewVarInfo . Kills . push_back ( * I ) ; I = OldVarInfo . Kills . erase ( I ) ;


<s> unsigned StackAlign = TFL -> getStackAlignment ( ) ; int64_t Advantage = <NUM_LIT> ; for ( auto CC : CallSeqVector ) { if ( CC . NoStackParams ) continue ; if ( ! CC . UsePush ) { Advantage -= <NUM_LIT> ; } else { Advantage -= <NUM_LIT> ; if ( CC . ExpectedDist % StackAlign ) Advantage -= <NUM_LIT> ; Advantage += ( CC . ExpectedDist >> Log2SlotSize ) * <NUM_LIT> ;


<s> return __builtin_ia32_orps ( __A , __B ) ;


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> unsigned getIntrinsicInstrCost ( <STR_LIT> ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed = UINT_MAX ) { return <NUM_LIT> ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i ++ << <STR_LIT> << PV . getPointer ( ) -> getName ( ) << ( PV . getInt ( ) ? <STR_LIT> : <STR_LIT> ) ) ;


<s> } else { MCInst FMov ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FMov . setOpcode ( <STR_LIT> ) ; FMov . addOperand ( MCOperand :: createReg ( DestReg ) ) ; FMov . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : FMov . setOpcode ( <STR_LIT> ) ; FMov . addOperand ( MCOperand :: createReg ( DestReg ) ) ; FMov . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : FMov . setOpcode ( <STR_LIT> ) ; FMov . addOperand ( MCOperand :: createReg ( DestReg ) ) ;


<s> if ( parseOptionalToken ( AsmToken :: Comma ) ) { ControlLoc = getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Control ) ) return true ; } if ( getParser ( ) . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( NumBytes <= <NUM_LIT> ) { Error ( NumBytesLoc , <STR_LIT> ) ;


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( NamedMD && NamedMD -> getNumOperands ( ) ) { BlobType = ELF :: NT_<ISA_LIT>_METADATA ; auto MDN = dyn_cast < MDTuple > ( NamedMD -> getOperand ( <NUM_LIT> ) ) ; if ( MDN && MDN -> getNumOperands ( ) ) { if ( auto MDS = dyn_cast < MDString > ( MDN -> getOperand ( <NUM_LIT> ) ) ) setFromMsgPackBlob ( MDS -> getString ( ) ) ; } return ; } BlobType = ELF :: NT_AMD_<ISA_LIT>_PAL_METADATA ; NamedMD = M . getNamedMetadata ( <STR_LIT> ) ; if ( ! NamedMD || ! NamedMD -> getNumOperands ( ) ) return ; auto Tuple = dyn_cast < MDTuple > ( NamedMD -> getOperand ( <NUM_LIT> ) ) ; if ( ! Tuple ) return ; for ( unsigned I = <NUM_LIT> , E = Tuple -> getNumOperands ( ) & - <NUM_LIT> ; I != E ; I += <NUM_LIT> ) {

auto Key = mdconst :: dyn_extract < ConstantInt > ( Tuple -> getOperand ( I ) ) ;


<s> void printlea32mem ( const MCInst * MI , unsigned OpNo ) {


<s> if ( ! flag_non_call_exceptions || ! aarch64_could_trap_p ( d ) ) attrs = aarch64_add_attribute ( <STR_LIT> , attrs ) ;

return aarch64_add_attribute ( <STR_LIT> , attrs ) ;


<s> static void emit_store_conditional ( machine_mode mode , rtx res , rtx mem , rtx val ) { rtx ( * fn ) ( rtx , rtx , rtx ) = NULL ; if ( mode == SImode ) fn = gen_store_conditional_si ; else if ( mode == DImode ) fn = gen_store_conditional_di ;


<s> unsigned <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , Value * Ptr , bool VariableMask , unsigned Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ;


<s> MCStreamer * create<ISA_LIT>WinCOFFStreamer ( MCContext & Context , MCAsmBackend & MAB , MCCodeEmitter & Emitter , raw_ostream & OS ) {

return new <ISA_LIT>WinCOFFStreamer ( Context , MAB , Emitter , OS ) ;


<s> auto StatusOrErr = RealVal . convertFromString ( Desc -> Repr , APFloat :: rmTowardZero ) ; if ( ! StatusOrErr || * StatusOrErr != APFloat :: opOK ) llvm_unreachable ( <STR_LIT> ) ;

if ( getFPImm ( ) . bitwiseIsEqual ( RealVal ) ) return DiagnosticPredicateTy :: Match ;


<s> if ( ! HFI . needsAligna ( * MF ) ) return ; auto * AlignaI = const_cast < MachineInstr * > ( HFI . getAlignaInstr ( * MF ) ) ;


<s> PM . add ( create<ISA_LIT>BranchSelectionPass ( ) ) ; return false ;


<s> if ( CoaCounter >= CoaLimit ) return false ; CoaCounter ++ ; } unsigned BW1 , BW2 ; if ( ! isIntReg ( R1 , BW1 ) || ! isIntReg ( R2 , BW2 ) || BW1 != BW2 ) return false ; if ( MRI -> isLiveIn ( R1 . Reg ) ) return false ; if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; if ( L1 . hasSubRanges ( ) || L2 . hasSubRanges ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << printReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << printReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ;


<s> } else { const MCSymbol * Symbol = & Target . getSymA ( ) -> getSymbol ( ) ; if ( Symbol -> isTemporary ( ) && Value ) { const MCSection & Sec = Symbol -> getSection ( ) ; if ( ! Asm . getContext ( ) . getAsmInfo ( ) -> isSectionAtomizableBySymbols ( Sec ) ) Symbol -> setUsedInReloc ( ) ; } RelSymbol = Asm . getAtom ( * Symbol ) ; if ( Symbol -> isInSection ( ) ) { const MCSectionMachO & Section = static_cast < const MCSectionMachO & > ( * Fragment -> getParent ( ) ) ; if ( Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) ) RelSymbol = nullptr ; } if ( RelSymbol ) { if ( RelSymbol != Symbol ) Value += Layout . getSymbolOffset ( * Symbol ) - Layout . getSymbolOffset ( * RelSymbol ) ; } else if ( Symbol -> isInSection ( ) && ! Symbol -> isVariable ( ) ) { Index = Symbol -> getFragment ( ) -> getParent ( ) -> getOrdinal ( ) + <NUM_LIT> ; Value += Writer -> getSymbolAddress ( * Symbol , Layout ) ; if ( IsPCRel ) Value -= FixupAddress + ( <NUM_LIT> << Log2Size ) ; } else if ( Symbol -> isVariable ( ) ) { const MCExpr * Value = Symbol -> getVariableValue ( ) ; int64_t Res ; bool isAbs = Value -> evaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ; if ( isAbs ) { FixedValue = Res ; return ; } else { report_fatal_error ( <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> , false ) ; } } else { report_fatal_error ( <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> , false ) ; } MCSymbolRefExpr :: VariantKind Modifier = Target . getSymA ( ) -> getKind ( ) ; if ( IsPCRel ) { if ( IsRIPRel ) { if ( Modifier == MCSymbolRefExpr :: VK_GOTPCREL ) { if ( unsigned ( Fixup . getKind ( ) ) == <STR_LIT> ) Type = MachO :: <ISA_LIT>_64_RELOC_GOT_LOAD ; else Type = MachO :: <ISA_LIT>_64_RELOC_GOT ; } else if ( Modifier == MCSymbolRefExpr :: VK_TLVP ) { Type = MachO :: <ISA_LIT>_64_RELOC_TLV ; } else if ( Modifier != MCSymbolRefExpr :: VK_None ) { report_fatal_error ( <STR_LIT> , false ) ; } else { Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED ; switch ( - ( Target . getConstant ( ) + ( <NUM_LIT> << Log2Size ) ) ) { case <NUM_LIT> : Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED_1 ; break ; case <NUM_LIT> : Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED_2 ; break ; case <NUM_LIT> : Type = MachO :: <ISA_LIT>_64_RELOC_SIGNED_4 ; break ; } }


auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < <NUM_LIT> ; } ;


<s> if ( CPU . empty ( ) ) CPUName = <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName , FS ) ;


<s> const DebugLoc & dl = MI -> getDebugLoc ( ) ; if ( isInt < <NUM_LIT> > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } }


<s> LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , WidenScalar } , { <NUM_LIT> , Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ; auto Largest = result . back ( ) . first ; result . push_back ( { Largest + <NUM_LIT> , Unsupported } ) ;


<s> auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Builder . CreateCall ( MFence , { } ) ;

LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _m_empty ( void ) {


<s> if ( Subtarget -> hasAVX ( ) ) { DebugLoc dl = Op . getNode ( ) -> getDebugLoc ( ) ; SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> && Vec . getNode ( ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; return Extract128BitVector ( Vec , IdxVal , DAG , dl ) ; } } return SDValue ( ) ;


<s> if ( CONST_DOUBLE_P ( immediate ) && GET_MODE_CLASS ( mode ) == MODE_INT ) { unsigned HOST_WIDE_INT ival ; if ( ! aarch64_reinterpret_float_as_int ( immediate , & ival ) ) gcc_unreachable ( ) ; immediate = gen_int_mode ( ival , mode ) ; } machine_mode vmode ; int width = GET_MODE_BITSIZE ( mode ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;

vmode = aarch64_simd_container_mode ( mode , width ) ;


<s> if ( I -> isConditionalBranch ( ) ) return true ; if ( TII -> hasUnwantedEffectsWhenEXECEmpty ( * I ) ) return true ; if ( TII -> isSMRD ( * I ) || TII -> isVMEM ( * I ) || TII -> isFLAT ( * I ) || TII -> isDS ( * I ) || I -> getOpcode ( ) == <STR_LIT> ) return true ; ++ NumInstr ;

if ( NumInstr >= SkipThreshold ) return true ;


<s> MachineOperand & MO = MI . getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI . getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Size = RI . getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; const TargetRegisterClass * VRC64 = RI . getVGPR64Class ( ) ; if ( RI . getCommonSubClass ( VRC64 , VRC ) ) VRC = VRC64 ; else VRC = & <STR_LIT> ; Register Reg = MRI . createVirtualRegister ( VRC ) ;

DebugLoc DL = MBB -> findDebugLoc ( I ) ;


<s> SDLoc DL ( Node ) ; const GlobalValue * GV = Node -> getGlobal ( ) ; int64_t Offset = Node -> getOffset ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; CodeModel :: Model CM = TM . getCodeModel ( ) ; SDValue Result ; if ( Subtarget . isPC32DBLSymbol ( GV , RM , CM ) ) { uint64_t Anchor = Offset & ~ uint64_t ( <NUM_LIT> ) ; Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ;


<s> case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; }


<s> uint64_t SextImm = SignExtend64 ( Imm , MinSize ) ; SDValue SDImm = CurDAG -> getTargetConstant ( SextImm , dl , <STR_LIT> ) ;

if ( isInt < <NUM_LIT> > ( SextImm ) ) return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDImm ) ;


<s> const LLT Ty = MRI . getType ( Reg ) ; return Ty . isValid ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ; } const RegisterBank * RB = RegClassOrBank . get < const RegisterBank * > ( ) ;


<s> if ( Ty -> isVectorTy ( ) && SE ) { if ( ! BaseT :: isStridedAccess ( Ptr ) ) return NumVectorInstToHideOverhead ; if ( ! BaseT :: getConstantStrideStep ( SE , Ptr ) ) return <NUM_LIT> ; }

return BaseT :: getAddressComputationCost ( Ty , SE , Ptr ) ;


<s> if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx mem = XEXP ( pat , i ) ; if ( MEM_P ( mem ) ) { tree expr = MEM_EXPR ( mem ) ; if ( ! expr ) continue ; if ( TREE_CODE ( expr ) == MEM_REF && TREE_CODE ( TREE_OPERAND ( expr , <NUM_LIT> ) ) == SSA_NAME ) { gimple * def_stmt = SSA_NAME_DEF_STMT ( TREE_OPERAND ( expr , <NUM_LIT> ) ) ; if ( def_stmt && is_gimple_assign ( def_stmt ) ) expr = gimple_assign_rhs1 ( def_stmt ) ; } if ( is_attr_preserve_access ( expr ) ) maybe_make_core_relo ( expr , BPF_RELO_FIELD_BYTE_OFFSET ) ; } } rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_before ( seq , insn ) ; } }


<s> } } SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; SmallVector < unsigned , <NUM_LIT> > ImpDefs ; SmallVector < MachineOperand * , <NUM_LIT> > UsesOfImpDefs ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { unsigned Reg = memOps [ i ] . Reg ; bool isKill = memOps [ i ] . isKill || KilledRegs . count ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; for ( const MachineOperand & MO : memOps [ i ] . MBBI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! MO . isImplicit ( ) || MO . isDead ( ) ) continue ; unsigned DefReg = MO . getReg ( ) ; if ( std :: find ( ImpDefs . begin ( ) , ImpDefs . end ( ) , DefReg ) == ImpDefs . end ( ) ) ImpDefs . push_back ( DefReg ) ; findUsesOfImpDef ( UsesOfImpDefs , memOps , DefReg , memOps [ i ] . Position , insertPos ) ; } } MachineBasicBlock :: iterator Loc = memOps [ insertAfter ] . MBBI ; ++ Loc ; if ( ! MergeOps ( MBB , Loc , Offset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Regs , ImpDefs ) ) return ; Merges . push_back ( std :: prev ( Loc ) ) ; for ( SmallVectorImpl < MachineOperand * > :: iterator I = UsesOfImpDefs . begin ( ) , E = UsesOfImpDefs . end ( ) ; I != E ; ++ I ) ( * I ) -> setIsUndef ( ) ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { if ( Regs [ i - memOpsBegin ] . second ) { unsigned Reg = Regs [ i - memOpsBegin ] . first ; if ( KilledRegs . count ( Reg ) ) { unsigned j = Killer [ Reg ] ;

int Idx = memOps [ j ] . MBBI -> findRegisterUseOperandIdx ( Reg , true ) ;


<s> <ISA_LIT>Section * Entry = SectionsByName [ Name ] ; if ( Entry ) return Entry ;


<s> assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { AddDefaultPred ( BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) ) . addMBB ( TBB ) ; } else { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; } return <NUM_LIT> ; }


<s> if ( TARGET_AVX512VL && ( VALID_AVX256_REG_OR_OI_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) || VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ;


<s> switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI ) : MCDisassembler ( STI ) {


<s> static SDValue PerformShiftCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSHLCombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSRACombine ( N , DAG ) ) return V ; if ( N -> getOpcode ( ) != <STR_LIT> ) if ( SDValue V = performShiftToAllZeros ( N , DAG , Subtarget ) ) return V ;


<s> NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } else { LL = IsN64 ? <STR_LIT> : <STR_LIT> ; SC = IsN64 ? <STR_LIT> : <STR_LIT> ; AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal = Incr ; }

BuildMI ( BB , DL , TII -> get ( SC ) , Success ) . addReg ( StoreVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> if ( Rd == Rn || Rd == Rt || Rd == Rt + <NUM_LIT> ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt + <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S ;


<s> IC . pushOperator ( IC_PLUS ) ; break ; case IES_INIT : assert ( ! BracCount && <STR_LIT> ) ; State = IES_LBRAC ; break ; }


<s> switch ( MO . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : return AP . getSymbol ( MO . getGlobal ( ) ) ; case MachineOperand :: MO_ConstantPoolIndex : return AP . GetCPISymbol ( MO . getIndex ( ) ) ; case MachineOperand :: MO_JumpTableIndex : return AP . GetJTISymbol ( MO . getIndex ( ) ) ; case MachineOperand :: MO_BlockAddress :

return AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


<s> const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * CI . Paired -> memoperands_begin ( ) ; MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC0 ) . addImm ( CI . SLC0 ) . addImm ( <NUM_LIT> ) . addImm ( CI . DLC0 ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Dest1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , CI . InstsToMove ) ; MachineBasicBlock :: iterator Next = std :: next ( CI . I ) ; CI . I -> eraseFromParent ( ) ;


<s> const MachineFunction * MF = U . first ; Register Reg = U . second ; MAI . setRegisterAlias ( MF , Reg , GlobalReg ) ; if ( ! MF -> getRegInfo ( ) . getUniqueVRegDef ( Reg ) ) continue ; collectDefInstr ( Reg , MF , & MAI , MSType , IsFirst ) ; IsFirst = false ; if ( E -> getIsGV ( ) ) MAI . GlobalVarList . push_back ( MF -> getRegInfo ( ) . getUniqueVRegDef ( Reg ) ) ; }

if ( UsePreOrder ) for ( auto * S : E -> getDeps ( ) ) RecHoistUtil ( S ) ;


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ;

int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ;


<s> if ( II && ( II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> ) ) {

DEBUG ( dbgs ( ) << <STR_LIT> << * II << <STR_LIT> ) ;


if ( parseImmExpr ( Size ) ) return true ;


<s> SmallVector < Value * , <NUM_LIT> > Indices ( GEP -> idx_begin ( ) , GEP -> idx_end ( ) ) ; if ( Instruction * GEPI = dyn_cast < Instruction > ( GEP ) ) { GetElementPtrInst * NewGEP = GetElementPtrInst :: Create ( GEP -> getSourceElementType ( ) , Cast -> getOperand ( <NUM_LIT> ) , Indices , <STR_LIT> , GEPI ) ; NewGEP -> setIsInBounds ( GEP -> isInBounds ( ) ) ; Value * NewASC = new AddrSpaceCastInst ( NewGEP , GEP -> getType ( ) , <STR_LIT> , GEPI ) ; NewASC -> takeName ( GEP ) ; GEP -> replaceAllUsesWith ( NewASC ) ; } else { Constant * NewGEP = ConstantExpr :: getGetElementPtr ( GEP -> getSourceElementType ( ) , cast < Constant > ( Cast -> getOperand ( <NUM_LIT> ) ) , Indices , GEP -> isInBounds ( ) ) ; GEP -> replaceAllUsesWith ( ConstantExpr :: getAddrSpaceCast ( NewGEP , GEP -> getType ( ) ) ) ; } return true ;


<s> } for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UA = * I ; NodeAddr < InstrNode * > IA = UA . Addr -> getOwner ( * DFG ) ; if ( UA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) return false ; NodeAddr < RefNode * > AA = LV -> getNearestAliasedRef ( LRExtRR , IA ) ; if ( ( DFG -> IsDef ( AA ) && AA . Id != LRExtRegRD ) || AA . Addr -> getReachingDef ( ) != LRExtRegRD ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ;


<s> return createExternalAAWrapperPass ( [ ] ( Pass & P , Function & , AAResults & AAR ) { if ( auto * WrapperPass = P . getAnalysisIfAvailable < <ISA_LIT>AAWrapperPass > ( ) ) AAR . addAAResult ( WrapperPass -> getResult ( ) ) ;


<s> MVT SVT = N0 . getSimpleValueType ( ) ; SDLoc dl ( Op ) ;

assert ( ( SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> || SVT == <STR_LIT> ) && <STR_LIT> ) ;


<s> unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - ( int64_t ) SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; } return DAG . getFrameIndex ( ReturnAddrIndex , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ;


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> return __builtin_neon_vrndihf ( __a ) ;


<s> assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Modified = false ; SmallPtrSet < MachineInstr * , <NUM_LIT> > AnchorList ; MemInfoMap Visited ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator SectionEnd ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; I = SectionEnd ) { bool CollectModified ; std :: list < std :: list < CombineInfo >> MergeableInsts ; std :: tie ( SectionEnd , CollectModified ) = collectMergeableInsts ( I , E , Visited , AnchorList , MergeableInsts ) ; Modified |= CollectModified ; do { OptimizeAgain = false ; Modified |= optimizeBlock ( MergeableInsts ) ; } while ( OptimizeAgain ) ;


<s> SVOp -> getMask ( PermMask ) ; unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle = false ; break ; } if ( EltNo == <NUM_LIT> ) { EltNo = ByteSource / <NUM_LIT> ; } else if ( EltNo != ByteSource / <NUM_LIT> ) { isFourElementShuffle = false ; break ; } } PFIndexes [ i ] = EltNo ; } if ( isFourElementShuffle ) { unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost < <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ; EVT EltVT = V1 . getValueType ( ) . getVectorElementType ( ) ; unsigned BytesPerElement = EltVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > ResultMask ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { unsigned SrcElt = PermMask [ i ] < <NUM_LIT> ? <NUM_LIT> : PermMask [ i ] ; for ( unsigned j = <NUM_LIT> ; j != BytesPerElement ; ++ j ) ResultMask . push_back ( DAG . getConstant ( SrcElt * BytesPerElement + j , <STR_LIT> ) ) ; }

SDValue VPermMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ResultMask [ <NUM_LIT> ] , ResultMask . size ( ) ) ;


<s> name_ = PredefinedFuncs [ i ] . Name ;

if ( strcmp ( name , name_ ) == <NUM_LIT> ) return & PredefinedFuncs [ i ] . Signature ;


<s> builtin_decls_data bdda [ ] = { { double_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_DF } , { float_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_SF } , { V2DF_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_V2DF } , { V2SF_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_V2SF } , { V4SF_type_node , <STR_LIT> , AARCH64_BUILTIN_RSQRT_V4SF } } ; builtin_decls_data * bdd = bdda ; builtin_decls_data * bdd_end = bdd + ( sizeof ( bdda ) / sizeof ( builtin_decls_data ) ) ; for ( ; bdd < bdd_end ; bdd ++ ) { ftype = build_function_type_list ( bdd -> type_node , bdd -> type_node , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_FP , TYPE_MODE ( bdd -> type_node ) ) ; fndecl = aarch64_general_add_builtin ( bdd -> builtin_name , ftype , bdd -> function_code , attrs ) ;

aarch64_builtin_decls [ bdd -> function_code ] = fndecl ;


<s> OS . emitIntValue ( TypeLen , <NUM_LIT> ) ; OS . emitIntValue ( TypeLen , <NUM_LIT> ) ; OS . emitIntValue ( StrLen , <NUM_LIT> ) ; for ( const auto & TypeEntry : TypeEntries ) TypeEntry -> emitType ( OS ) ; uint32_t StringOffset = <NUM_LIT> ; for ( const auto & S : StringTable . getTable ( ) ) { OS . AddComment ( <STR_LIT> + std :: to_string ( StringOffset ) ) ;


<s> MCSymbol * Start = getContext ( ) . CreateTempSymbol ( ) ; EmitLabel ( Start ) ; MCSymbol * Symbol = getContext ( ) . GetOrCreateSymbol ( Name + <STR_LIT> + Twine ( MappingSymbolCounter ++ ) ) ; MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ;

MCELF :: SetType ( SD , ELF :: STT_NOTYPE ) ;


<s> if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace , CostKind ) ; int SplitCost = getScalarizationOverhead ( VTy , DemandedElts , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; return NumElem * Cost + SplitCost ; } } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = LT . first * <NUM_LIT> ; if ( LT . second . getStoreSize ( ) == <NUM_LIT> && ST -> isUnalignedMem32Slow ( ) ) Cost *= <NUM_LIT> ;


<s> } std :: sort ( Indexes . begin ( ) , Indexes . end ( ) ) ; auto & MRI = ( * R . begin ( ) ) -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; DenseMap < MachineInstr * , GCNRPTracker :: LiveRegSet > LiveRegMap ; SmallVector < SlotIndex , <NUM_LIT> > LiveIdxs , SRLiveIdxs ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I != E ; ++ I ) { auto Reg = Register :: index2VirtReg ( I ) ; if ( ! LIS . hasInterval ( Reg ) ) continue ; auto & LI = LIS . getInterval ( Reg ) ; LiveIdxs . clear ( ) ; if ( ! LI . findIndexesLiveAt ( Indexes , std :: back_inserter ( LiveIdxs ) ) ) continue ; if ( ! LI . hasSubRanges ( ) ) { for ( auto <ISA_LIT> : LiveIdxs ) LiveRegMap [ <ISA_LIT>I . getInstructionFromIndex ( <ISA_LIT> ) ] [ Reg ] = MRI . getMaxLaneMaskForVReg ( Reg ) ; } else for ( const auto & S : LI . subranges ( ) ) { SRLiveIdxs . clear ( ) ; S . findIndexesLiveAt ( LiveIdxs , std :: back_inserter ( SRLiveIdxs ) ) ; for ( auto <ISA_LIT> : SRLiveIdxs ) LiveRegMap [ <ISA_LIT>I . getInstructionFromIndex ( <ISA_LIT> ) ] [ Reg ] |= S . LaneMask ; } }


<s> static DecodeStatus DecodeAVLdSt_64RegisterClass ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) {

return decodeOperand_AVLdSt_Any ( Inst , Imm , <ISA_LIT>Disassembler :: OPW64 , Decoder ) ;


<s> unsigned regY = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * target = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addReg ( regY ) ;

BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( BtOpc ) ) . addMBB ( target ) ;


<s> assert ( FPPush . getOffset ( ) + <NUM_LIT> == LRPush . getOffset ( ) ) ; CurOffset = FPPush . getOffset ( ) ; unsigned LRReg = * MRI . getLLVMRegNum ( LRPush . getRegister ( ) , true ) ; unsigned FPReg = * MRI . getLLVMRegNum ( FPPush . getRegister ( ) , true ) ; LRReg = getXRegFromWReg ( LRReg ) ; FPReg = getXRegFromWReg ( FPReg ) ; assert ( LRReg == <STR_LIT> && FPReg == <STR_LIT> && <STR_LIT> ) ; CompactUnwindEncoding |= CU :: UNWIND_ARM64_MODE_FRAME ; HasFP = true ; break ; } case MCCFIInstruction :: OpDefCfaOffset : { if ( StackSize != <NUM_LIT> ) return CU :: UNWIND_ARM64_MODE_DWARF ; StackSize = std :: abs ( Inst . getOffset ( ) ) ; break ; } case MCCFIInstruction :: OpOffset : { unsigned Reg1 = * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; if ( i + <NUM_LIT> == e ) return CU :: UNWIND_ARM64_MODE_DWARF ; if ( CurOffset != <NUM_LIT> && Inst . getOffset ( ) != CurOffset - <NUM_LIT> ) return CU :: UNWIND_ARM64_MODE_DWARF ; CurOffset = Inst . getOffset ( ) ; const MCCFIInstruction & Inst2 = Instrs [ ++ i ] ; if ( Inst2 . getOperation ( ) != MCCFIInstruction :: OpOffset ) return CU :: UNWIND_ARM64_MODE_DWARF ; unsigned Reg2 = * MRI . getLLVMRegNum ( Inst2 . getRegister ( ) , true ) ; if ( Inst2 . getOffset ( ) != CurOffset - <NUM_LIT> ) return CU :: UNWIND_ARM64_MODE_DWARF ; CurOffset = Inst2 . getOffset ( ) ; Reg1 = getXRegFromWReg ( Reg1 ) ; Reg2 = getXRegFromWReg ( Reg2 ) ; if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X19_X20_PAIR ;

else if ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> && ( CompactUnwindEncoding & <NUM_LIT> ) == <NUM_LIT> ) CompactUnwindEncoding |= CU :: UNWIND_ARM64_FRAME_X21_X22_PAIR ;


<s> bool nios2_emit_move_sequence ( rtx * operands , machine_mode mode ) { rtx to = operands [ <NUM_LIT> ] ; rtx from = operands [ <NUM_LIT> ] ; if ( ! register_operand ( to , mode ) && ! reg_or_0_operand ( from , mode ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; from = copy_to_mode_reg ( mode , from ) ; } if ( CONSTANT_P ( from ) ) { if ( CONST_INT_P ( from ) ) { if ( ! SMALL_INT ( INTVAL ( from ) ) && ! SMALL_INT_UNSIGNED ( INTVAL ( from ) ) && ! UPPER16_INT ( INTVAL ( from ) ) ) {

HOST_WIDE_INT high = ( INTVAL ( from ) + <NUM_LIT> ) & ~ <NUM_LIT> ;


<s> bool <ISA_LIT>FrameLowering :: adjustStackWithPops ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , int Offset ) const { if ( Offset <= <NUM_LIT> ) return false ; if ( Offset % SlotSize ) return false ; int NumPops = Offset / SlotSize ; if ( NumPops != <NUM_LIT> && NumPops != <NUM_LIT> ) return false ; if ( MBBI == MBB . begin ( ) ) return false ; MachineBasicBlock :: iterator Prev = std :: prev ( MBBI ) ; if ( ! Prev -> isCall ( ) || ! Prev -> getOperand ( <NUM_LIT> ) . isRegMask ( ) ) return false ; unsigned Regs [ <NUM_LIT> ] ; unsigned FoundRegs = <NUM_LIT> ; auto & MRI = MBB . getParent ( ) -> getRegInfo ( ) ;

auto RegMask = Prev -> getOperand ( <NUM_LIT> ) ;


<s> static DecodeStatus DecodeF32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = F32RegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> virtual EVT getSetCCResultType ( EVT VT ) const { return <STR_LIT> ;


<s> Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const unsigned Option = MO . getTargetFlags ( ) & <STR_LIT> ; MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; switch ( Option ) { default : break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_Q1 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_Q2 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_Q3 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_Q4 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_CALL26 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_CALL19 ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_9BIT ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_6BIT ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_12BIT ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ;

<ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> bool IsRegFPR64 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegFPR64C = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool IsRegVR = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; if ( ( IsRegFPR64 && Kind == MCK_FPR32 ) || ( IsRegFPR64C && Kind == MCK_FPR32C ) ) { Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; return Match_Success ; } if ( IsRegFPR64 && Kind == MCK_FPR16 ) { Op . Reg . RegNum = convertFPR64ToFPR16 ( Reg ) ; return Match_Success ; } if ( IsRegVR && ( Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8 ) ) { Op . Reg . RegNum = convertVRToVRMx ( * getContext ( ) . getRegisterInfo ( ) , Reg , Kind ) ;

if ( Op . Reg . RegNum == <NUM_LIT> ) return Match_InvalidOperand ;


<s> return hasReservedCallFrame ( MF ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || ( hasFP ( MF ) && ! TRI -> needsStackRealignment ( MF ) ) || TRI -> hasBasePointer ( MF ) ;


<s> push2 ( unsigned i , unsigned j ) : doubleChange ( true , true , i , j ) {


<s> if ( msp430_check_env_var_for_devices ( & devices_csv_path ) ) return NULL ; return concat ( <STR_LIT> , msp430_dirname ( devices_csv_path ) , NULL ) ;


<s> } if ( Opc == <STR_LIT> && OpToFold -> isImm ( ) ) { MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; FoldList . push_back ( FoldCandidate ( MI , OpNo , OpToFold ) ) ; return true ; } if ( isUseMIInFoldList ( FoldList , MI ) ) return false ; unsigned CommuteIdx0 = TargetInstrInfo :: CommuteAnyOperandIndex ; unsigned CommuteIdx1 = TargetInstrInfo :: CommuteAnyOperandIndex ; bool CanCommute = TII -> findCommutedOpIndices ( * MI , CommuteIdx0 , CommuteIdx1 ) ; if ( CanCommute ) { if ( CommuteIdx0 == OpNo ) OpNo = CommuteIdx1 ; else if ( CommuteIdx1 == OpNo ) OpNo = CommuteIdx0 ; } if ( CanCommute && ( ! MI -> getOperand ( CommuteIdx0 ) . isReg ( ) || ! MI -> getOperand ( CommuteIdx1 ) . isReg ( ) ) ) return false ; if ( ! CanCommute || ! TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ) return false ; if ( ! TII -> isOperandLegal ( * MI , OpNo , OpToFold ) ) { TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ; return false ; } FoldList . push_back ( FoldCandidate ( MI , OpNo , OpToFold , true ) ) ; return true ; } FoldList . push_back ( FoldCandidate ( MI , OpNo , OpToFold ) ) ; return true ;


<s> switch ( AS ) { default : return false ; case <STR_LIT> : case <STR_LIT> :


<s> void GCNPassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ;

addPass ( create<ISA_LIT>PostLegalizeCombiner ( IsOptNone ) ) ;


<s> } else { rtx addr0 , addr1 , count , blocks , temp ; rtx_code_label * loop_start_label = gen_label_rtx ( ) ; rtx_code_label * loop_end_label = gen_label_rtx ( ) ; rtx_code_label * end_label = gen_label_rtx ( ) ; machine_mode mode ; mode = GET_MODE ( len ) ; if ( mode == VOIDmode ) mode = Pmode ; addr0 = gen_reg_rtx ( Pmode ) ; addr1 = gen_reg_rtx ( Pmode ) ; count = gen_reg_rtx ( mode ) ; blocks = gen_reg_rtx ( mode ) ; convert_move ( count , len , <NUM_LIT> ) ; emit_cmp_and_jump_insns ( count , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , end_label ) ; emit_move_insn ( addr0 , force_operand ( XEXP ( op0 , <NUM_LIT> ) , NULL_RTX ) ) ; emit_move_insn ( addr1 , force_operand ( XEXP ( op1 , <NUM_LIT> ) , NULL_RTX ) ) ; op0 = change_address ( op0 , VOIDmode , addr0 ) ; op1 = change_address ( op1 , VOIDmode , addr1 ) ; temp = expand_binop ( mode , add_optab , count , constm1_rtx , count , <NUM_LIT> , OPTAB_DIRECT ) ; if ( temp != count ) emit_move_insn ( count , temp ) ; temp = expand_binop ( mode , lshr_optab , count , GEN_INT ( <NUM_LIT> ) , blocks , <NUM_LIT> , OPTAB_DIRECT ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , loop_end_label ) ; emit_label ( loop_start_label ) ;

if ( TARGET_Z10 && ( GET_CODE ( len ) != CONST_INT || INTVAL ( len ) > <NUM_LIT> ) ) {


<s> void <ISA_LIT>TargetStreamer :: emitR ( unsigned Opcode , unsigned Reg0 , SMLoc IDLoc , const MCSubtargetInfo * STI ) { MCInst TmpInst ;


<s> if ( ! startswith ( ident , <STR_LIT> ) ) fprintf ( asm_out_file , <STR_LIT> , ident ) ; }


<s> static SDValue LowerADDC_ADDE_SUBC_SUBE ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; unsigned Opc ; bool ExtraOp = false ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;

case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> Br . MaxDisp = ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; BBInfoVector & BBInfo = BBUtils -> getBBInfo ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; BBUtils -> adjustBBOffsetsAfter ( MBB ) ; ++ NumUBrFixed ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ;


<s> unsigned ZextRatio = ResSize / SrcSize ; bool IsZext = true ; for ( unsigned i = <NUM_LIT> ; i < SrcType . getVectorNumElements ( ) ; ++ i ) { if ( i % ZextRatio ) { if ( Shuffle -> getMaskElt ( i ) > <NUM_LIT> ) { IsZext = false ; break ; } } else { if ( Shuffle -> getMaskElt ( i ) != ( int ) ( i / ZextRatio ) ) { IsZext = false ; break ; } } } if ( ! IsZext ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > Mask ; unsigned NumElems = SrcType . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) if ( i % ZextRatio ) Mask . push_back ( NumElems ) ; else Mask . push_back ( i / ZextRatio ) ; SDValue NewShuffle = DAG . getVectorShuffle ( Shuffle -> getValueType ( <NUM_LIT> ) , DL , Shuffle -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , SrcType ) , Mask ) ;

return DAG . getBitcast ( N0 . getValueType ( ) , NewShuffle ) ;


<s> CallContext ( ) : FrameSetup ( nullptr ) , ArgStoreVector ( <NUM_LIT> , nullptr ) {


<s> bool hardenSlsRetBr ( ) const { return HardenSlsRetBr ;


<s> SDValue Mul = DAG . getNode ( MultOpc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue InGlue = Mul ; if ( ! Op . getValue ( <NUM_LIT> ) . use_empty ( ) ) { SDValue CopyFromLo = DAG . getCopyFromReg ( InChain , dl , <STR_LIT> , Ty , InGlue ) ; DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , CopyFromLo ) ; InChain = CopyFromLo . getValue ( <NUM_LIT> ) ; InGlue = CopyFromLo . getValue ( <NUM_LIT> ) ; } if ( ! Op . getValue ( <NUM_LIT> ) . use_empty ( ) ) { SDValue CopyFromHi = DAG . getCopyFromReg ( InChain , dl , <STR_LIT> , Ty , InGlue ) ;

DAG . ReplaceAllUsesOfValueWith ( Op . getValue ( <NUM_LIT> ) , CopyFromHi ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SrcSubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const {

const TargetRegisterInfo & TRI = * MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) . getTargetRegisterInfo ( ) ;


<s> if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & * I2 ) ) continue ; unsigned I2DestReg = I2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsI1LowReg = ( I2DestReg - I1DestReg ) == <NUM_LIT> ; bool IsI2LowReg = ( I1DestReg - I2DestReg ) == <NUM_LIT> ; unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg ; if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , * I2 , AllowC64 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , * I2 , I1 , AllowC64 ) ) ) break ; if ( isSafeToMoveTogether ( I1 , * I2 , I1DestReg , I2DestReg , DoInsertAtI1 ) ) return & * I2 ; break ; } return nullptr ;


<s> return ( ( pLower16 & ~ <NUM_LIT> ) | ( ( ( ( pOffset >> <NUM_LIT> ) & <NUM_LIT> ) ^ ! sign ) << <NUM_LIT> ) | ( ( ( ( pOffset >> <NUM_LIT> ) & <NUM_LIT> ) ^ ! sign ) << <NUM_LIT> ) | ( ( pOffset >> <NUM_LIT> ) & <NUM_LIT> ) ) ;


<s> if ( arg . end_marker_p ( ) ) return alpha_arg_info_reg_val ( * cum ) ; num_args = cum -> num_args ; if ( num_args >= <NUM_LIT> || targetm . calls . must_pass_in_stack ( arg ) ) return NULL_RTX ; } { if ( * cum >= <NUM_LIT> ) return NULL_RTX ; num_args = * cum ; if ( arg . end_marker_p ( ) ) basereg = <NUM_LIT> ; else if ( targetm . calls . must_pass_in_stack ( arg ) ) return NULL_RTX ; }

return gen_rtx_REG ( arg . mode , num_args + basereg ) ;


<s> MachineInstr * MI = MO . getParent ( ) ; if ( MO . isReg ( ) ) { if ( MO . isKill ( ) && ActiveChains . find ( MO . getReg ( ) ) != ActiveChains . end ( ) ) {

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MO . getReg ( ) , TRI ) << <STR_LIT> ) ;


<s> case <STR_LIT> : return process_stvar < stvaruint16 > ( process ( Call -> getArgOperand ( <NUM_LIT> ) ) , process ( Call -> getArgOperand ( <NUM_LIT> ) ) ) ; case <STR_LIT> : return process_stvar < stvaruint32 > ( process ( Call -> getArgOperand ( <NUM_LIT> ) ) , process ( Call -> getArgOperand ( <NUM_LIT> ) ) ) ; case <STR_LIT> : return process_stdict ( process ( Call -> getArgOperand ( <NUM_LIT> ) ) , process ( Call -> getArgOperand ( <NUM_LIT> ) ) ) ; case <STR_LIT> : return process_endc ( process ( Call -> getArgOperand ( <NUM_LIT> ) ) ) ; case <STR_LIT> : return process_ctos ( process ( Call -> getArgOperand ( <NUM_LIT> ) ) ) ; case <STR_LIT> : return make < builder > ( ) ; case <STR_LIT> : return make < null > ( ) ; case <STR_LIT> : return process_global ( process ( Call -> getArgOperand ( <NUM_LIT> ) ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return process ( Call -> getArgOperand ( <NUM_LIT> ) ) ;


<s> assert ( isValidSEW ( SEW ) && <STR_LIT> ) ; unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ; unsigned VSEWBits = encodeSEW ( SEW ) ; unsigned VTypeI = ( VSEWBits << <NUM_LIT> ) | ( VLMULBits & <NUM_LIT> ) ; if ( TailAgnostic ) VTypeI |= <NUM_LIT> ;

if ( MaskAgnostic ) VTypeI |= <NUM_LIT> ;


<s> unsigned SubSizeInBits = SrcVT . getSizeInBits ( ) ; SDValue Lo = extractSubVector ( MinPos , <NUM_LIT> , DAG , DL , SubSizeInBits ) ; SDValue Hi = extractSubVector ( MinPos , NumSubElts , DAG , DL , SubSizeInBits ) ; MinPos = DAG . getNode ( BinOp , DL , SrcVT , Lo , Hi ) ; } assert ( ( ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Mask ; unsigned MaskEltsBits = ExtractVT . getSizeInBits ( ) ; if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMaxValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMinValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getAllOnesValue ( MaskEltsBits ) , DL , SrcVT ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; if ( ExtractVT == <STR_LIT> ) { SDValue Upper = DAG . getVectorShuffle ( SrcVT , DL , MinPos , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , MinPos , Upper ) ;


<s> SelectionDAG & DAG = CLI . DAG ; SDLoc & dl = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ;


<s> if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT && ! SMALL_INT ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> Base = N0 ; Offset0 = CurDAG -> getTargetConstant ( DWordOffset0 , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( DWordOffset1 , DL , <STR_LIT> ) ; return true ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { unsigned DWordOffset0 = C -> getZExtValue ( ) / <NUM_LIT> ; unsigned DWordOffset1 = DWordOffset0 + <NUM_LIT> ; if ( isUInt < <NUM_LIT> > ( DWordOffset0 ) ) { SDLoc DL ( Addr ) ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , DWordOffset1 , <NUM_LIT> ) ) { SmallVector < SDValue , <NUM_LIT> > Opnds ; Opnds . push_back ( Zero ) ; Opnds . push_back ( Addr . getOperand ( <NUM_LIT> ) ) ; unsigned SubOp = <STR_LIT> ; if ( Subtarget -> hasAddNoCarry ( ) ) { SubOp = <STR_LIT> ; Opnds . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) ) ; } MachineSDNode * MachineSub = CurDAG -> getMachineNode ( SubOp , DL , <STR_LIT> , Opnds ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset0 = CurDAG -> getTargetConstant ( DWordOffset0 , DL , <STR_LIT> ) ; Offset1 = CurDAG -> getTargetConstant ( DWordOffset1 , DL , <STR_LIT> ) ; return true ; }


<s> return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> rtx pset ; if ( ! live && ( pset = single_set ( insn ) ) && reg_overlap_mentioned_p ( r0_reg , SET_DEST ( pset ) ) && ! find_regno_note ( insn , REG_UNUSED , R0_REG ) ) { set ++ ; live = true ; } }


<s> unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ;

if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ;


<s> assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> , size ) ;


<s> static const MCPhysReg HvxVQRDecoderTable [ ] = {


<s> Forward ( unsigned VReg , MCPhysReg PReg , MVT VT ) : VReg ( VReg ) , PReg ( PReg ) , VT ( VT ) {


<s> if ( MO . isReg ( ) ) { unsigned reg = MI . getOperand ( opIdx ) . getReg ( ) ; if ( AMDGPUMCRegisterClasses [ AMDGPU :: VReg_32RegClassID ] . contains ( reg ) || AMDGPUMCRegisterClasses [ AMDGPU :: VReg_64RegClassID ] . contains ( reg ) ) { Value |= ( VGPR_BIT ( opIdx ) ) << vgprBitOffset ; } } else if ( MO . isFPImm ( ) ) { union { float f ; uint32_t i ; } Imm ; Imm . f = MO . getFPImm ( ) ; Value |= ( ( uint64_t ) Imm . i ) << <NUM_LIT> ; } }


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; if ( NumElems > <NUM_LIT> || ( NumElems == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) ) return LowerVectorIntUnary ( Op , DAG ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> , NumElems ) ; assert ( ( NewVT . is256BitVector ( ) || NewVT . is512BitVector ( ) ) && <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CtlzNode = DAG . getNode ( <STR_LIT> , dl , NewVT , Op ) ; SDValue TruncNode = DAG . getNode ( <STR_LIT> , dl , VT , CtlzNode ) ; SDValue Delta = DAG . getConstant ( <NUM_LIT> - EltVT . getSizeInBits ( ) , dl , VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , TruncNode , Delta ) ;


<s> int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ;

if ( Offset & <NUM_LIT> ) return <STR_LIT> ;


<s> <ISA_LIT>FrameLowering ( StackDirection D , unsigned StackAl , int LAO , unsigned TransAl = <NUM_LIT> ) : <ISA_LIT>FrameLowering ( D , StackAl , LAO , TransAl ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> return static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ;


<s> const <ISA_LIT>Subtarget * STI = & Fn . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ;


return TargetTriple . isWindowsGNUEnvironment ( ) ;


<s> EFlags = <STR_LIT> ( getFeatureBits ( ) ) ; return * this ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) {

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ;


<s> bool hasUsableDivScaleConditionOutput ( ) const { return getGeneration ( ) != SOUTHERN_ISLANDS ;


<s> } if ( ix86_cmodel == CM_LARGE_PIC && ! TARGET_PECOFF && MEM_P ( fnaddr ) && GET_CODE ( XEXP ( fnaddr , <NUM_LIT> ) ) == SYMBOL_REF && ! local_symbolic_operand ( XEXP ( fnaddr , <NUM_LIT> ) , VOIDmode ) ) fnaddr = gen_rtx_MEM ( QImode , construct_plt_address ( XEXP ( fnaddr , <NUM_LIT> ) ) ) ; else if ( sibcall ? ! sibcall_insn_operand ( XEXP ( fnaddr , <NUM_LIT> ) , word_mode ) : ! call_insn_operand ( XEXP ( fnaddr , <NUM_LIT> ) , word_mode ) ) { fnaddr = convert_to_mode ( word_mode , XEXP ( fnaddr , <NUM_LIT> ) , <NUM_LIT> ) ; fnaddr = gen_rtx_MEM ( QImode , copy_to_mode_reg ( word_mode , fnaddr ) ) ; } call = gen_rtx_CALL ( VOIDmode , fnaddr , callarg1 ) ; if ( retval ) { if ( TARGET_MPX && SCALAR_INT_MODE_P ( GET_MODE ( retval ) ) ) { rtx b0 = gen_rtx_REG ( BND64mode , FIRST_BND_REG ) ; rtx b1 = gen_rtx_REG ( BND64mode , FIRST_BND_REG + <NUM_LIT> ) ; if ( GET_CODE ( retval ) == PARALLEL ) { b0 = gen_rtx_EXPR_LIST ( VOIDmode , b0 , const0_rtx ) ; b1 = gen_rtx_EXPR_LIST ( VOIDmode , b1 , const0_rtx ) ; rtx par = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , b0 , b1 ) ) ; retval = chkp_join_splitted_slot ( retval , par ) ; } else { retval = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , retval , b0 , b1 ) ) ; chkp_put_regs_to_expr_list ( retval ) ; } } call = gen_rtx_SET ( VOIDmode , retval , call ) ; } vec [ vec_len ++ ] = call ; if ( pop ) { pop = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , pop ) ; pop = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , pop ) ;


<s> assert ( Value <= <NUM_LIT> && <STR_LIT> ) ;


<s> void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerOperand ( const MachineOperand & MO ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ;

MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ;


<s> bool isConstpoolSymbol ( ) const { int64_t Imm ; return isImm ( ) && ! evaluateConstantImm ( getImm ( ) , Imm ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) {


<s> Status ( unsigned Mask , unsigned Mode ) : Mask ( Mask ) , Mode ( Mode ) { Mode &= Mask ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( OverrideNEON && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) return Subtarget -> hasSVE ( ) ; if ( VT . getFixedSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( ! Subtarget -> useSVEForFixedLengthVectors ( ) ) return false ;

if ( VT . getFixedSizeInBits ( ) > Subtarget -> getMinSVEVectorSizeInBits ( ) ) return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ;


<s> APInt ShiftAmt = ShlRHS -> getAPIntValue ( ) ; unsigned BitWidth = MulType . getSizeInBits ( ) ; if ( ShiftAmt . sge ( <NUM_LIT> ) && ShiftAmt . slt ( BitWidth ) ) { APInt MulVal = APInt ( BitWidth , <NUM_LIT> ) << ShiftAmt ; RHS = DCI . DAG . getConstant ( MulVal , DL , MulType ) ; } else { return SDValue ( ) ; } } bool Signed ; if ( ! AreMulWideOperandsDemotable ( LHS , RHS , OptSize , Signed ) ) { return SDValue ( ) ; } EVT DemotedVT ; if ( MulType == <STR_LIT> ) { DemotedVT = <STR_LIT> ; } else { DemotedVT = <STR_LIT> ; } SDValue TruncLHS = DCI . DAG . getNode ( <STR_LIT> , DL , DemotedVT , LHS ) ; SDValue TruncRHS = DCI . DAG . getNode ( <STR_LIT> , DL , DemotedVT , RHS ) ; unsigned Opc ; if ( Signed ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } return DCI . DAG . getNode ( Opc , DL , MulType , TruncLHS , TruncRHS ) ;


<s> const Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned DstSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ;

assert ( ( DstSize == SrcSize || ( Register :: isPhysicalRegister ( SrcReg ) && DstSize <= SrcSize ) || ( ( ( DstSize + <NUM_LIT> ) / <NUM_LIT> == ( SrcSize + <NUM_LIT> ) / <NUM_LIT> ) && DstSize > SrcSize ) ) && <STR_LIT> ) ;


<s> case <STR_LIT> : handleTwoArgFP ( I ) ; break ; case <STR_LIT> : handleCompareFP ( I ) ; break ; case <STR_LIT> : handleCondMovFP ( I ) ; break ; case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( MachineBasicBlock :: iterator PrevI ( PrevMI ) ; if ( I == PrevI ) { dbgs ( ) << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && prior ( Start ) != PrevI ) -- Start ; dbgs ( ) << <STR_LIT> ; Start -> print ( dbgs ( ) , & MF . getTarget ( ) ) ;

while ( ++ Start != llvm :: next ( I ) ) {


<s> int i , j ; rtx tem ; if ( REG_P ( x ) && refers_to_regno_p ( regno , x ) ) return x ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( ( tem = regno_use_in ( regno , XEXP ( x , i ) ) ) ) return tem ; } else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( ( tem = regno_use_in ( regno , XVECEXP ( x , i , j ) ) ) ) return tem ; }


<s> unsigned LUi = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZEROReg = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; bool LastInstrIsADDiu = NewImm ; const <ISA_LIT>AnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; <ISA_LIT>AnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > <NUM_LIT> ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < <NUM_LIT> > ( Inst -> ImmOpnd ) ) ;

if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ;


<s> static inline vec_float4 vec_max ( vec_float4 a , vec_float4 b ) {

return ( spu_sel ( b , a , spu_cmpgt ( a , b ) ) ) ;


<s> <ISA_LIT>TargetObjectFile :: ~ <ISA_LIT>TargetObjectFile ( ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addRequired < MemoryDependenceWrapperPass > ( ) ;

AU . addRequired < LoopInfoWrapperPass > ( ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << Node << <STR_LIT> << * R << '\n' ) ; BasicBlock * PB = cast < Instruction > ( R ) -> getParent ( ) ; GepNode * N = Node ; GepNode * C = <NUM_LIT> , * NewNode = <NUM_LIT> ; while ( is_constant ( N ) && ! ( N -> Flags & GepNode :: Root ) ) { GepNode * NewN = new ( * Mem ) GepNode ( N ) ; Nodes . push_back ( NewN ) ; Loc [ NewN ] = PB ; if ( N == Node ) NewNode = NewN ; NewN -> Flags &= ~ GepNode :: Used ; if ( C ) C -> Parent = NewN ; C = NewN ; N = N -> Parent ; } if ( ! NewNode ) return ; NodeToUsesMap :: iterator UF = Uses . find ( Node ) ;


<s> std :: vector < std :: string > vtrshr ( ) { return D ( <STR_LIT> ) ;


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>_32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>_32Target ( ) , create<ISA_LIT>ExternalSymbolizer ) ; TargetRegistry :: RegisterMCDisassembler ( getTheARM64Target ( ) , create<ISA_LIT>Disassembler ) ;

TargetRegistry :: RegisterMCSymbolizer ( getTheARM64Target ( ) , create<ISA_LIT>ExternalSymbolizer ) ;


<s> Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;


<s> tmp2 = gen_reg_rtx ( Pmode ) ; mem = gen_const_mem ( Pmode , tmp1 ) ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( gsym , lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( tmp1 , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( tmp2 , mem ) ; rtx_insn * last = emit_insn ( gen_addsi3 ( got , tmp1 , tmp2 ) ) ; set_unique_reg_note ( last , REG_EQUAL , gsym ) ; } } } if ( model == TLS_MODEL_GLOBAL_DYNAMIC ) { tga = rs6000_tls_get_addr ( ) ; emit_library_call_value ( tga , dest , LCT_CONST , Pmode , <NUM_LIT> , const0_rtx , Pmode ) ; r3 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) { if ( TARGET_64BIT ) insn = gen_tls_gd_aix64 ( r3 , got , addr , tga , const0_rtx ) ; else insn = gen_tls_gd_aix32 ( r3 , got , addr , tga , const0_rtx ) ; } else if ( DEFAULT_ABI == ABI_V4 ) insn = gen_tls_gd_sysvsi ( r3 , got , addr , tga , const0_rtx ) ; else gcc_unreachable ( ) ; call_insn = last_call_insn ( ) ; PATTERN ( call_insn ) = insn ; if ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , pic_offset_table_rtx ) ; } else if ( model == TLS_MODEL_LOCAL_DYNAMIC ) { tga = rs6000_tls_get_addr ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; emit_library_call_value ( tga , tmp1 , LCT_CONST , Pmode , <NUM_LIT> , const0_rtx , Pmode ) ;


<s> static std :: pair < unsigned , unsigned > getMFHiLoOpc ( unsigned Src ) { return std :: make_pair ( <NUM_LIT> , <NUM_LIT> ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( GV -> isWeakForLinker ( ) && RelocM == Reloc :: Static ) { SDValue PoolAddr ; PoolAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , false , true , true , <NUM_LIT> ) ; } if ( Alignment == <NUM_LIT> ) { const PointerType * GVPtrTy = cast < PointerType > ( GV -> getType ( ) ) ; if ( GVPtrTy -> getElementType ( ) -> isSized ( ) ) { Alignment = getDataLayout ( ) -> getABITypeAlignment ( GVPtrTy -> getElementType ( ) ) ; } else { Alignment = <NUM_LIT> ; } } unsigned char HiFixup , LoFixup ; bool UseGOT = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; Alignment = <NUM_LIT> ; } else { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ;


<s> if ( OutStreamer . hasRawTextSupport ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask ( OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; if ( EmitCPLoad ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; if ( <ISA_LIT>FI -> getEmitNOAT ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } else if ( EmitCPLoad ) { SmallVector < MCInst , <NUM_LIT> > MCInsts ; MCInstLowering . LowerCPLOAD ( MCInsts ) ; for ( SmallVector < MCInst , <NUM_LIT> > :: iterator I = MCInsts . begin ( ) ;

I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ;


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerANDOR ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerANDOR ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;

for ( int x = Reserved . find_first ( ) ; x >= <NUM_LIT> ; x = Reserved . find_next ( x ) ) markSuperRegs ( Reserved , x ) ;


<s> <ISA_LIT>Operand * Op ; if ( Offset . isReg ( ) ) Op = <ISA_LIT>Operand :: CreateMem ( Base . getReg ( ) , Offset . getReg ( ) , S , E ) ; else Op = <ISA_LIT>Operand :: CreateMem ( Base . getReg ( ) , Offset . getImm ( ) , S , E ) ;


<s> } else if ( MEM_P ( dst ) && INT_REGNO_P ( reg ) ) { rtx breg ; if ( GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_INC || GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_DEC ) { rtx delta_rtx ; breg = XEXP ( XEXP ( dst , <NUM_LIT> ) , <NUM_LIT> ) ; delta_rtx = ( GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_INC ? GEN_INT ( GET_MODE_SIZE ( GET_MODE ( dst ) ) ) : GEN_INT ( - GET_MODE_SIZE ( GET_MODE ( dst ) ) ) ) ; if ( TARGET_UPDATE ) { rtx nsrc = simplify_gen_subreg ( reg_mode , src , mode , <NUM_LIT> ) ; emit_insn ( TARGET_32BIT ? ( TARGET_POWERPC64 ? gen_movdi_si_update ( breg , breg , delta_rtx , nsrc ) : gen_movsi_update ( breg , breg , delta_rtx , nsrc ) ) : gen_movdi_di_update ( breg , breg , delta_rtx , nsrc ) ) ; used_update = true ; } else emit_insn ( gen_add3_insn ( breg , breg , delta_rtx ) ) ; dst = replace_equiv_address ( dst , breg ) ; } else if ( ! rs6000_offsettable_memref_p ( dst , reg_mode ) && GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) != LO_SUM ) { if ( GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_MODIFY ) { rtx basereg = XEXP ( XEXP ( dst , <NUM_LIT> ) , <NUM_LIT> ) ; if ( TARGET_UPDATE ) { rtx nsrc = simplify_gen_subreg ( reg_mode , src , mode , <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( reg_mode , XEXP ( dst , <NUM_LIT> ) ) , nsrc ) ) ; used_update = true ; } else emit_insn ( gen_rtx_SET ( VOIDmode , basereg , XEXP ( XEXP ( dst , <NUM_LIT> ) , <NUM_LIT> ) ) ) ; dst = replace_equiv_address ( dst , basereg ) ; } else { rtx basereg = XEXP ( XEXP ( dst , <NUM_LIT> ) , <NUM_LIT> ) ; rtx offsetreg = XEXP ( XEXP ( dst , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PLUS && REG_P ( basereg ) && REG_P ( offsetreg ) && REGNO ( basereg ) != REGNO ( offsetreg ) ) ; if ( REGNO ( basereg ) == <NUM_LIT> ) { rtx tmp = offsetreg ; offsetreg = basereg ; basereg = tmp ; } emit_insn ( gen_add3_insn ( basereg , basereg , offsetreg ) ) ;

restore_basereg = gen_sub3_insn ( basereg , basereg , offsetreg ) ;


<s> if ( counters . failed_loads ) fprintf ( dump_file , <STR_LIT> , counters . failed_loads ) ; fprintf ( dump_file , <STR_LIT> , counters . stores , counters . adjacent_stores ) ; if ( counters . failed_stores ) fprintf ( dump_file , <STR_LIT> , counters . failed_stores ) ; fprintf ( dump_file , <STR_LIT> ) ; } df_remove_problem ( df_chain ) ; df_process_deferred_rescans ( ) ;


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return FrameLowering . get ( ) ;


<s> const uint16_t * <ISA_LIT>Z80RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getFunction ( ) . getFunctionType ( ) -> getNumParams ( ) <= <NUM_LIT> ) return CSR_0_1_SaveList ;


<s> unsigned DestBW = DestTy -> getBitWidth ( ) ; if ( PHINode * P = dyn_cast < PHINode > ( In ) ) { unsigned N = P -> getNumIncomingValues ( ) ; for ( unsigned i = <NUM_LIT> ; i != N ; ++ i ) { BasicBlock * InB = P -> getIncomingBlock ( i ) ; if ( InB == LoopB ) continue ; Value * InV = P -> getIncomingValue ( i ) ; IntegerType * Ty = cast < IntegerType > ( InV -> getType ( ) ) ; if ( Ty != P -> getType ( ) ) { assert ( Ty -> getBitWidth ( ) < DestBW ) ; InV = IRBuilder < > ( InB -> getTerminator ( ) ) . CreateZExt ( InV , DestTy ) ; P -> setIncomingValue ( i , InV ) ; } } } else if ( ZExtInst * Z = dyn_cast < ZExtInst > ( In ) ) { Value * Op = Z -> getOperand ( <NUM_LIT> ) ; if ( Op -> getType ( ) == Z -> getType ( ) ) Z -> replaceAllUsesWith ( Op ) ; Z -> eraseFromParent ( ) ; return ; } if ( TruncInst * T = dyn_cast < TruncInst > ( In ) ) { IntegerType * TruncTy = cast < IntegerType > ( OrigTy ) ; Value * Mask = ConstantInt :: get ( DestTy , ( <NUM_LIT> << TruncTy -> getBitWidth ( ) ) - <NUM_LIT> ) ; Value * And = IRBuilder < > ( In ) . CreateAnd ( T -> getOperand ( <NUM_LIT> ) , Mask ) ;


<s> return ( uint64x1_t ) ( __a <= ( float64x1_t ) { <NUM_LIT> } ) ;


<s> unsigned CmpOp = getFCmpOpcode ( I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ;

return selectCmp ( ResVReg , ResType , CmpOp , I ) ;


<s> auto UnmergeDefs = unmergeDefsSplitHigh ( Unmerge ) ; SmallVector < Register > RestParts ; for ( MachineOperand & Op : UnmergeDefs . Lows ) RestParts . push_back ( Op . getReg ( ) ) ; Register Rest = ( RestParts . size ( ) > <NUM_LIT> ) ? Builder . buildMerge ( LLT :: scalar ( RestParts . size ( ) * <NUM_LIT> ) , RestParts ) . getReg ( <NUM_LIT> ) : RestParts [ <NUM_LIT> ] ;

return { UnmergeDefs . High . getReg ( ) , Rest } ;


<s> * op = gen_rtx_SUBREG ( vmode , * op , <NUM_LIT> ) ; } else if ( CONST_INT_P ( * op ) ) { rtx vec_cst ; rtx tmp = gen_rtx_SUBREG ( vmode , gen_reg_rtx ( smode ) , <NUM_LIT> ) ; if ( constm1_operand ( * op , GET_MODE ( * op ) ) ) vec_cst = CONSTM1_RTX ( vmode ) ; else { unsigned n = GET_MODE_NUNITS ( vmode ) ; rtx * v = XALLOCAVEC ( rtx , n ) ; v [ <NUM_LIT> ] = * op ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) v [ i ] = const0_rtx ; vec_cst = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( n , v ) ) ; } if ( ! standard_sse_constant_p ( vec_cst , vmode ) ) { start_sequence ( ) ; vec_cst = validize_mem ( force_const_mem ( vmode , vec_cst ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_before ( seq , insn ) ; }

emit_insn_before ( gen_move_insn ( copy_rtx ( tmp ) , vec_cst ) , insn ) ;


<s> void <ISA_LIT>AsmPrinter :: emitGlobalVariable ( const GlobalVariable * GV ) {

if ( PromotedGlobals . count ( GV ) ) return ;


<s> void <ISA_LIT>CodeEmitter :: emitBasicBlock ( MachineBasicBlock & MBB ) { MCE . StartMachineBasicBlock ( & MBB ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ;


<s> if ( ( ST -> hasNEON ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( ST -> hasSVE ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) ) { if ( ExtraSteps == TargetLoweringBase :: ReciprocalEstimate :: Unspecified ) ExtraSteps = VT . getScalarType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( Opcode , SDLoc ( Operand ) , VT , Operand ) ; }


<s> } ; MachineInstr * LHSDef = getDefIgnoringCopies ( LHS . getReg ( ) , MRI ) ; MachineInstr * RHSDef = getDefIgnoringCopies ( RHS . getReg ( ) , MRI ) ; CmpInst :: Predicate P = ( CmpInst :: Predicate ) Predicate . getPredicate ( ) ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( P ) ; if ( IsCMN ( LHSDef , CC ) ) return emitCMN ( LHSDef -> getOperand ( <NUM_LIT> ) , RHS , MIRBuilder ) ; if ( IsCMN ( RHSDef , CC ) ) return emitCMN ( LHS , RHSDef -> getOperand ( <NUM_LIT> ) , MIRBuilder ) ; if ( ! isUnsignedICMPPred ( P ) && LHSDef && LHSDef -> getOpcode ( ) == TargetOpcode :: G_AND ) { auto ValAndVReg = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI ) ;

if ( ! ValAndVReg || ValAndVReg -> Value != <NUM_LIT> ) return nullptr ;


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> unsigned encoding ; const MCOperand op1 = MI . getOperand ( <NUM_LIT> ) ; assert ( op1 . isReg ( ) && <STR_LIT> ) ;

encoding = ( get<ISA_LIT>RegisterNumbering ( op1 . getReg ( ) ) << <NUM_LIT> ) ;


<s> if ( isNonZero ) { if ( First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , Op . getOperand ( i ) , DAG . getIntPtrConstant ( i , dl ) ) ; } }


<s> } else { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : New = BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addImm ( Offset ) ; break ; case <STR_LIT> : New = BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . addReg ( FramePtr ) . addImm ( Offset ) ; break ; case <STR_LIT> : New = BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addImm ( Offset ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } } } else { bool isU6 = isImmU6 ( Offset ) ; if ( ! isU6 && ! isImmU16 ( Offset ) ) { cerr << <STR_LIT> << Offset << <STR_LIT> ; abort ( ) ; } switch ( MI . getOpcode ( ) ) { int NewOpcode ; case <STR_LIT> : NewOpcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( NewOpcode ) , Reg ) . addImm ( Offset ) ; break ; case <STR_LIT> : NewOpcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( NewOpcode ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . addImm ( Offset ) ; break ; case <STR_LIT> : NewOpcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( NewOpcode ) , Reg ) . addImm ( Offset ) ;


<s> op1p = & XEXP ( x , <NUM_LIT> ) ; if ( ! REG_P ( op1 ) ) return false ; if ( GET_CODE ( op0 ) == SIGN_EXTEND && MEM_P ( XEXP ( op0 , <NUM_LIT> ) ) ) { rtx op00 = XEXP ( op0 , <NUM_LIT> ) ; rtx op000 = XEXP ( op00 , <NUM_LIT> ) ; rtx * op000p = & XEXP ( op00 , <NUM_LIT> ) ;

if ( ( GET_MODE ( op00 ) == HImode || GET_MODE ( op00 ) == QImode ) && ( REG_P ( op000 ) || ( GET_CODE ( op000 ) == POST_INC && REG_P ( XEXP ( op000 , <NUM_LIT> ) ) ) ) ) {


<s> return rs6000_darwin64_abi && ( ( mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > <NUM_LIT> ) || ( type && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) == <NUM_LIT> ) ) ? <NUM_LIT> : <NUM_LIT> ;


<s> return arg0 ( a ) && arg1 ( c ) && noArg ( b ) ;


<s> if ( ! CmpRhs || ! CmpRhs -> isZero ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue CmpLHS = Cond . getOperand ( <NUM_LIT> ) ; if ( CCOpcode == <STR_LIT> && ( isCtlzOpc ( RHS . getOpcode ( ) ) || isCttzOpc ( RHS . getOpcode ( ) ) ) && RHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( LHS ) ) { unsigned Opc = isCttzOpc ( RHS . getOpcode ( ) ) ? <STR_LIT> : <STR_LIT> ; return getFFBX_U32 ( DAG , CmpLHS , SL , Opc ) ; }

if ( CCOpcode == <STR_LIT> && ( isCtlzOpc ( LHS . getOpcode ( ) ) || isCttzOpc ( LHS . getOpcode ( ) ) ) && LHS . getOperand ( <NUM_LIT> ) == CmpLHS && isNegativeOne ( RHS ) ) {


<s> function_checker :: function_checker ( location_t location , const function_instance & instance , tree fndecl , tree fntype , unsigned int nargs , tree * args ) : function_call_info ( location , instance , fndecl ) , m_fntype ( fntype ) , m_nargs ( nargs ) , m_args ( args ) {


<s> unsigned getAddrMode6AddressOpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT> ;


<s> static SDValue PerformINTRINSIC_WO_CHAINCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { unsigned IntNo = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : return SDValue ( ) ; case <STR_LIT> : if ( ! Subtarget -> hasAVX2 ( ) ) return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasAVX ( ) ) return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; if ( Op0 == Op1 ) return Op0 ; if ( <STR_LIT> ( Mask . getNode ( ) ) ) return Op0 ; if ( <STR_LIT> ( Mask . getNode ( ) ) ) return Op1 ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Mask ) ) { if ( C -> isNullValue ( ) ) return Op0 ; if ( C -> isAllOnesValue ( ) ) return Op1 ; } return SDValue ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = Op0 . getValueType ( ) ;

assert ( VT . isVector ( ) && <STR_LIT> ) ;


<s> BasicBlock * BB = Term -> getParent ( ) ; llvm :: Loop * L = LI -> getLoopFor ( BB ) ; BasicBlock * Target = Term -> getSuccessor ( <NUM_LIT> ) ; PHINode * Broken = PHINode :: Create ( Int64 , <NUM_LIT> , <STR_LIT> , & Target -> front ( ) ) ;

Value * Cond = Term -> getCondition ( ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ;