<s> for ( unsigned i = Operands . size ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ i ] ) ; if ( Test ( Op ) ) return Op . getStartLoc ( ) ;


<s> if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; else if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> && ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) {


<s> unsigned Odd ; switch ( Hint . first ) { case <STR_LIT> : Odd = <NUM_LIT> ; break ; case <STR_LIT> : Odd = <NUM_LIT> ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return false ; } unsigned Paired = Hint . second ; if ( Paired == <NUM_LIT> ) return false ; unsigned PairedPhys = <NUM_LIT> ; if ( Register :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & <NUM_LIT> ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : shift = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Val % ( <NUM_LIT> << shift ) ) { * CommentStream << <STR_LIT> << getRegClassName ( SRegClassID ) << <STR_LIT> << Val ;


<s> if ( slotno == SPARC_INT_ARG_MAX - <NUM_LIT> ) nwords = <NUM_LIT> ; regs = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nwords ) ) ; for ( i = <NUM_LIT> ; i < nwords ; i ++ ) { XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( word_mode , regno ) , GEN_INT ( UNITS_PER_WORD * i ) ) ; regno ++ ; }


<s> break ; case VK_<ISA_LIT>_HA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HA ; break ; case VK_<ISA_LIT>_HIGH : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGH ; break ; case VK_<ISA_LIT>_HIGHA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHA ; break ; case VK_<ISA_LIT>_HIGHERA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA ; break ; case VK_<ISA_LIT>_HIGHER : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER ; break ; case VK_<ISA_LIT>_HIGHEST : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST ; break ; case VK_<ISA_LIT>_HIGHESTA : Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHESTA ; break ; } Sym = MCSymbolRefExpr :: create ( & Sym -> getSymbol ( ) , Modifier , Context ) ; Res = MCValue :: get ( Sym , Value . getSymB ( ) , Value . getConstant ( ) ) ; }


<s> bool iss4Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false , false ) ;


<s> void printJT2BlockOperand ( const MCInst * MI , unsigned OpNum ) {


<s> return ( __m128i ) __builtin_ia32_pmovsqd256_mask ( ( __v4di ) __A , ( __v4si ) _mm_setzero_si128 ( ) , __M ) ;


<s> unsigned MaxGPR = <NUM_LIT> ; bool killPixel = false ; const <ISA_LIT>Subtarget & STM = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RI = STM . getRegisterInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( const MachineBasicBlock & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) killPixel = true ; unsigned numOperands = MI . getNumOperands ( ) ; for ( unsigned op_idx = <NUM_LIT> ; op_idx < numOperands ; op_idx ++ ) { const MachineOperand & MO = MI . getOperand ( op_idx ) ; if ( ! MO . isReg ( ) ) continue ; unsigned HWReg = RI -> getEncodingValue ( MO . getReg ( ) ) & <NUM_LIT> ; if ( HWReg > <NUM_LIT> ) continue ; MaxGPR = std :: max ( MaxGPR , HWReg ) ; } } } unsigned RsrcReg ; if ( STM . getGeneration ( ) >= <ISA_LIT>Subtarget :: EVERGREEN ) { switch ( MF . getFunction ( ) -> getCallingConv ( ) ) { default : case CallingConv :: <ISA_LIT>_CS : RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS ; break ; case CallingConv :: <ISA_LIT>_GS : RsrcReg = R_028878_SQ_PGM_RESOURCES_GS ; break ; case CallingConv :: <ISA_LIT>_PS : RsrcReg = R_028844_SQ_PGM_RESOURCES_PS ; break ; case CallingConv :: <ISA_LIT>_VS : RsrcReg = R_028860_SQ_PGM_RESOURCES_VS ; break ; } } else { switch ( MF . getFunction ( ) -> getCallingConv ( ) ) { default : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_VS : RsrcReg = R_028868_SQ_PGM_RESOURCES_VS ; break ; case CallingConv :: <ISA_LIT>_PS : RsrcReg = R_028850_SQ_PGM_RESOURCES_PS ; break ; } } OutStreamer -> EmitIntValue ( RsrcReg , <NUM_LIT> ) ;

OutStreamer -> EmitIntValue ( S_NUM_GPRS ( MaxGPR + <NUM_LIT> ) | S_STACK_<ISA_LIT>ZE ( MFI -> CFStackSize ) , <NUM_LIT> ) ;


<s> return __aarch64_vset_lane_any ( * __src , __vec , __lane ) ;


<s> CanAcceptPredicationCode = false ; } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) { if ( hasV6MOps ( ) ) CanAcceptPredicationCode = Mnemonic != <STR_LIT> ;

else CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ;


<s> unsigned stackReg = RI . getFrameRegister ( MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; O << <STR_LIT> << '$' << LowercaseString ( RI . get ( stackReg ) . AsmName ) << ',' << stackSize << ',' << '$' << LowercaseString ( RI . get ( returnReg ) . AsmName ) << '\n' ;


<s> unsigned GCNTTIImpl :: getLoadVectorFactor ( unsigned VF , unsigned LoadSize , unsigned ChainSizeInBytes , VectorType * VecTy ) const { unsigned VecRegBitWidth = VF * LoadSize ; if ( VecRegBitWidth > <NUM_LIT> && VecTy -> getScalarSizeInBits ( ) < <NUM_LIT> ) return <NUM_LIT> / LoadSize ; return VF ;


<s> unsigned int cnt ; vec_uchar16 mask ; x . v = vec_sl ( vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) , vec_splat_u8 ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


return ( __m128d ) vec_splats ( * __P ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ;

TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;


<s> auto EM = Const -> getZExtValue ( ) ; Inst . addOperand ( MCOperand :: createImm ( EM ) ) ; } else if ( auto * CE = dyn_cast < Function > ( C ) ) { Register FuncReg = MAI -> getFuncReg ( CE -> getName ( ) . str ( ) ) ; assert ( FuncReg . isValid ( ) ) ; Inst . addOperand ( MCOperand :: createReg ( FuncReg ) ) ; } } }


<s> MCOperand <ISA_LIT>AsmPrinter :: lowerSymbolOperand ( const MachineOperand & MO , const MCSymbol * Sym ) const { const MCExpr * Expr = <NUM_LIT> ; Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , OutContext ) ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateGOT ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateGOTLo12 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateLo12 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateDTPREL_G1 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateDTPREL_G0_NC ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateGOTTPREL ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateGOTTPRELLo12 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateTLSDesc ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateTLSDescLo12 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateTPREL_G1 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateTPREL_G0_NC ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateABS_G3 ( Expr , OutContext ) ;


<s> unsigned Reg = <STR_LIT> [ FirstGPR ] ; int Offset = RegSpillOffsets [ Reg ] ; if ( StartSPOffset > Offset ) { LowGPR = Reg ; StartSPOffset = Offset ; } } } ZFI -> setSpillGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; CurrOffset = - <STR_LIT> ; } else { uint32_t LowGR64Num = UINT32_MAX ; for ( auto & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned GR64Num = <STR_LIT> ( Reg ) ; int Offset = - <NUM_LIT> * ( <NUM_LIT> - GR64Num + <NUM_LIT> ) ; if ( LowGR64Num > GR64Num ) { LowGR64Num = GR64Num ; StartSPOffset = <STR_LIT> + Offset ; } int FrameIdx = MFFrame . CreateFixedSpillStackObject ( <NUM_LIT> , Offset ) ; CS . setFrameIdx ( FrameIdx ) ; } else CS . setFrameIdx ( INT32_MAX ) ; } if ( LowGR64Num < UINT32_MAX ) LowGPR = <STR_LIT> [ LowGR64Num ] ; ZFI -> setRestoreGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; ZFI -> setSpillGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; CurrOffset = LowGPR ? - ( <STR_LIT> - StartSPOffset ) : <NUM_LIT> ; } for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; CurrOffset -= Size ;

assert ( CurrOffset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ;


<s> Terminator . Address = Position . Address ; Position . Address += Terminator . Size ; if ( AssumeRelaxed ) Position . Address += Terminator . ExtraRelaxSize ;


<s> if ( priority > <NUM_LIT> ) switch ( priority ) { case <NUM_LIT> : return FP_MODE_ROUND_UNKNOWN ; case <NUM_LIT> : return FP_MODE_NONE ; default : gcc_unreachable ( ) ; } switch ( ( enum attr_fp_mode ) epiphany_normal_fp_mode ) { case FP_MODE_INT : switch ( priority ) { case <NUM_LIT> : return FP_MODE_INT ; case <NUM_LIT> : return epiphany_normal_fp_rounding ; case <NUM_LIT> : return ( epiphany_normal_fp_rounding == FP_MODE_ROUND_NEAREST ? FP_MODE_ROUND_TRUNC : FP_MODE_ROUND_NEAREST ) ; case <NUM_LIT> : return FP_MODE_CALLER ; default : gcc_unreachable ( ) ; } case FP_MODE_ROUND_NEAREST : case FP_MODE_CALLER : switch ( priority ) { case <NUM_LIT> : return FP_MODE_ROUND_NEAREST ; case <NUM_LIT> : return FP_MODE_ROUND_TRUNC ; case <NUM_LIT> : return FP_MODE_INT ;


<s> MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , FIdx , MachinePointerInfo ( ) ) ; return DAG . getLoad ( Op . getValueType ( ) , dl , Store , FIdx , MachinePointerInfo ( ) ) ;


<s> const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; for ( Iter I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { const MachineInstr * MI = & * I ; if ( insertStall ( MBB , I , TII , MI -> getOpcode ( ) ) ) { FilledSlots ++ ; Changed = true ;


<s> const char * Spelling ; <ISA_LIT>MCExpr :: VariantKind VariantKind ; uint8_t SupportedFormats ; } PrefixEntries [ ] = { { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 , COFF | ELF | MACHO } , { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 , COFF | ELF | MACHO } , } ; StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; const auto & Prefix = std :: find_if ( std :: begin ( PrefixEntries ) , std :: end ( PrefixEntries ) , [ & IDVal ] ( const PrefixEntry & PE ) { return PE . Spelling == IDVal ; } ) ; if ( Prefix == std :: end ( PrefixEntries ) ) {

Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ;


<s> if ( Cexpr -> getOpcode ( ) == Instruction :: PtrToInt ) { Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr -> getOperand ( <NUM_LIT> ) ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; } case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : { const auto * CFP = cast < ConstantFP > ( CPV ) ; Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getHalfTy ( CPV -> getContext ( ) ) ) { APInt API = CFP -> getValueAPF ( ) . bitcastToAPInt ( ) ; uint16_t float16 = API . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ; ConvertIntToBytes < > ( ptr , float16 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ConvertFloatToBytes ( ptr , float32 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ; ConvertDoubleToBytes ( ptr , float64 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } break ; } case Type :: PointerTyID : { if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { aggBuffer -> addSymbol ( GVar , GVar ) ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr ) ;


<s> rtx_insn * queue = NULL ; bool in_bundle = false ; for ( insn = BB_HEAD ( bb ) ; insn != BB_END ( bb ) ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( INSN_P ( insn ) ) { if ( GET_MODE ( insn ) == QImode ) { while ( queue ) { rtx_insn * next_queue = PREV_INSN ( queue ) ; SET_PREV_INSN ( NEXT_INSN ( insn ) ) = queue ; SET_NEXT_INSN ( queue ) = NEXT_INSN ( insn ) ; SET_NEXT_INSN ( insn ) = queue ; SET_PREV_INSN ( queue ) = insn ; queue = next_queue ; } in_bundle = false ; } else if ( GET_MODE ( insn ) == SImode ) in_bundle = true ; }

else if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_VAR_LOCATION ) {


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ;

assert ( CE -> getValue ( ) >= <NUM_LIT> && CE -> getValue ( ) <= <NUM_LIT> && <STR_LIT> ) ;


<s> for ( t = <NUM_LIT> ; t < sr -> region_len ; ++ t ) { if ( ( t & <NUM_LIT> ) == <NUM_LIT> ) mask = * cp ++ ; kind = ( mask >> <NUM_LIT> * ( <NUM_LIT> - ( t & <NUM_LIT> ) ) ) & <NUM_LIT> ; if ( kind > <NUM_LIT> ) spill_next_when ( & regs [ kind - <NUM_LIT> ] , sr -> curr . reg + limit [ kind - <NUM_LIT> ] , sr -> region_start + t ) ; } } if ( sr -> any_spills ) { off = sr -> spill_offset ; alloc_spill_area ( & off , <NUM_LIT> , sr -> curr . reg + UNW_REG_F2 , sr -> curr . reg + UNW_REG_F31 ) ; alloc_spill_area ( & off , <NUM_LIT> , sr -> curr . reg + UNW_REG_B1 , sr -> curr . reg + UNW_REG_B5 ) ; alloc_spill_area ( & off , <NUM_LIT> , sr -> curr . reg + UNW_REG_R4 , sr -> curr . reg + UNW_REG_R7 ) ; }


<s> switch ( code ) { case OPT_m10 : target_flags &= ~ ( MASK_40 | MASK_45 ) ; return true ; default :


<s> <ISA_LIT>PreLegalizerCombinerHelper PreLegalizerHelper ( B , Helper ) ; <ISA_LIT>GenPreLegalizerCombinerHelper Generated ( GeneratedRuleCfg , Helper , PreLegalizerHelper ) ; if ( Generated . tryCombineAll ( Observer , MI , B , Helper ) ) return true ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_MEMCPY_INLINE : return Helper . tryEmitMemcpyInline ( MI ) ; case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector ( MI ) ; }


<s> static DecodeStatus DecodeCallTarget ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( BranchOffset ) ) ;


<s> return __arm_vqmovuntq_s32 ( __a , __b ) ;


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelaPLT ( ) const { assert ( m_pRelaPLT != NULL && <STR_LIT> ) ; return * m_pRelaPLT ;


<s> } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ;


<s> MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( Reg , getKillRegState ( RegDeadKill ) | getUndefRegState ( RegUndef ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) | getUndefRegState ( BaseUndef ) ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ;


<s> static SDValue performANDCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI ) { SelectionDAG & DAG = DCI . DAG ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( VT . isScalableVector ( ) ) return performSVEAndCombine ( N , DCI ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! BVN ) return SDValue ( ) ; APInt DefBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; APInt UndefBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; if ( resolveBuildVector ( BVN , DefBits , UndefBits ) ) { SDValue NewOp ; DefBits = ~ DefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , DefBits , & LHS ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , DefBits , & LHS ) ) ) return NewOp ; UndefBits = ~ UndefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , UndefBits , & LHS ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , UndefBits , & LHS ) ) ) return NewOp ; } return SDValue ( ) ;


if ( INTVAL ( ma ) == MASK_ANY ) return INVALID_ATTRIBUTE ;


<s> xcpuxc ( unsigned i , unsigned j , unsigned k ) : tripleChange ( false , true , false , i , j , k ) {


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override {

return getSubtargetImpl ( ) -> getSelectionDAGInfo ( ) ;


<s> assert ( isValidSEW ( SEW ) && <STR_LIT> ) ;


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM ) , DL ( isLittle ? ( <STR_LIT> ) :

( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) {


<s> static int iq2000_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( mode == DImode && cum -> arg_words == MAX_ARGS_IN_REGISTERS - <NUM_LIT> ) { if ( TARGET_DEBUG_D_MODE ) fprintf ( stderr , <STR_LIT> , UNITS_PER_WORD ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( FuncInfo -> getVarArgsFrameOffset ( ) , <STR_LIT> ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , Offset , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> AlignmentIsInBytes = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: WinEH ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ;


<s> cerr << <STR_LIT> ; cerr << <STR_LIT> << Opc << <STR_LIT> ; cerr << <STR_LIT> ; N -> dump ( ) ; abort ( ) ;


<s> if ( V -> isConstant ( ) ) return false ; for ( int i = <NUM_LIT> , e = V -> getNumOperands ( ) ; i < e ; ++ i ) { if ( V -> getOperand ( i ) . isUndef ( ) ) return false ; if ( V -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> || ( V -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> && V -> getOperand ( i ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) || ( V -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> && V -> getOperand ( i ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) || ( V -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> && V -> getOperand ( i ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) IsLoad = true ;

if ( V -> getOperand ( i ) != Op0 || ( ! IsLoad && ! V -> isOnlyUserOf ( V -> getOperand ( i ) . getNode ( ) ) ) ) IsSplat = false ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: COPY ) , NewSuperReg ) . addReg ( SuperReg . getReg ( ) , <NUM_LIT> , SuperReg . getSubReg ( ) ) ;

BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: COPY ) , SubReg ) . addReg ( NewSuperReg , <NUM_LIT> , SubIdx ) ;


<s> } else if ( isa < StoreInst > ( SingleUser ) ) return getLoadStoreAddrMode ( HasVector , I -> getType ( ) ) ; } } else if ( auto * StoreI = dyn_cast < StoreInst > ( I ) ) { if ( auto * LoadI = dyn_cast < LoadInst > ( StoreI -> getValueOperand ( ) ) ) if ( LoadI -> hasOneUse ( ) && LoadI -> getParent ( ) == I -> getParent ( ) ) return getLoadStoreAddrMode ( HasVector , LoadI -> getType ( ) ) ; } if ( HasVector && ( isa < LoadInst > ( I ) || isa < StoreInst > ( I ) ) ) { Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; bool IsFPAccess = MemAccessTy -> isFloatingPointTy ( ) ; bool IsVectorAccess = MemAccessTy -> isVectorTy ( ) ; if ( ! IsVectorAccess && isa < StoreInst > ( I ) ) { Value * DataOp = I -> getOperand ( <NUM_LIT> ) ; if ( isa < ExtractElementInst > ( DataOp ) ) IsVectorAccess = true ; } if ( ! IsVectorAccess && isa < LoadInst > ( I ) && I -> hasOneUse ( ) ) { User * LoadUser = * I -> user_begin ( ) ;

if ( isa < InsertElementInst > ( LoadUser ) ) IsVectorAccess = true ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ;

if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> static bool xtensa_lra_p ( void ) { return TARGET_LRA ;


<s> unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; } case <STR_LIT> : { if ( ! ShouldCombineAggressively ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) return false ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) ; } default :


<s> StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) { Error ( L , <STR_LIT> ) ; return false ; }


<s> case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ;

case MachineOperand :: MO_MachineBasicBlock :


<s> int size ; if ( TREE_CODE ( decl ) == STRING_CST || TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; if ( VAR_P ( decl ) && DECL_SECTION_NAME ( decl ) != <NUM_LIT> ) { const char * name ; name = DECL_SECTION_NAME ( decl ) ;

if ( strcmp ( name , <STR_LIT> ) != <NUM_LIT> && strcmp ( name , <STR_LIT> ) != <NUM_LIT> ) return false ;


<s> if ( ! register_operand ( operands [ <NUM_LIT> ] , mode ) && ! reg_or_0_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; if ( visium_flags_exposed && gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) && gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ;


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { const <ISA_LIT>Subtarget & ST = * get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) ; if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) return create<ISA_LIT>MachineScheduler ( C ) ; else if ( ST . enable<ISA_LIT>Scheduler ( ) ) return create<ISA_LIT>MachineScheduler ( C ) ;


<s> MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case <STR_LIT> : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_8 : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_4 : default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; bool micro<ISA_LIT>LEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? ( micro<ISA_LIT>LEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ;


<s> if ( Subtarget -> isCallingConvWin64 ( CallConv ) ) { return None ; } const Function * Fn = MF . getFunction ( ) ; bool NoImplicitFloatOps = Fn -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; assert ( ! ( MF . getTarget ( ) . Options . UseSoftFloat && NoImplicitFloatOps ) && <STR_LIT> ) ; if ( MF . getTarget ( ) . Options . UseSoftFloat || NoImplicitFloatOps || ! Subtarget -> hasSSE1 ( ) ) return None ; static const MCPhysReg XMMArgRegs64Bit [ ] = {


<s> bool Changed = false ; if ( OldReg == NewReg ) { Changed = true ; unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( OldReg ) ) ; MO . setReg ( NewReg ) ; MO . setIsDead ( ) ; MFI . stackifyVReg ( NewReg ) ; } return Changed ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { if ( Subtarget -> hasAVX ( ) ) { DebugLoc dl = Op . getNode ( ) -> getDebugLoc ( ) ; SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> && SubVec . getNode ( ) -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) == <NUM_LIT> ) {

return Insert128BitVector ( Vec , SubVec , Idx , DAG , dl ) ;


<s> const MachineOperand & MO = MI -> getOperand ( opNum ) ;

O << <STR_LIT> ( ( <STR_LIT> ) MO . getImm ( ) ) ;


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setLoadExtAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setLoadExtAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( unsigned InnerVT = ( unsigned ) <STR_LIT> ; InnerVT <= ( unsigned ) <STR_LIT> ; ++ InnerVT ) setTruncStoreAction ( VT . getSimpleVT ( ) , ( <STR_LIT> ) InnerVT , Expand ) ; } setLoadExtAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ;


<s> int ir0_mem_operand ( rtx op , enum machine_mode mode ) { return c4x_arn_mem_operand ( op , mode , IR0_REGNO ) ;


<s> return isMem ( ) && getMemBase ( ) -> isGPRAsmReg ( ) && ( isa < MCTargetExpr > ( getMemOff ( ) ) || ( isConstantMemOff ( ) && isShiftedInt < Bits , ShiftAmount > ( getConstantMemOff ( ) ) ) ) ;


<s> NewMBB -> splice ( NewMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ;


<s> static tree csky_floatHF_type_node = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( csky_floatHF_type_node ) = GET_MODE_PRECISION ( HFmode ) ; layout_type ( csky_floatHF_type_node ) ; ( * lang_hooks . types . register_builtin_type ) ( csky_floatHF_type_node , <STR_LIT> ) ;


<s> O << <STR_LIT> << formatImm ( Op . getImm ( ) * <NUM_LIT> ) ; return ; } const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( MI -> getOperand ( OpNum ) . getExpr ( ) ) ;


<s> static DecodeStatus DecodeGPR64x8ClassRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; if ( RegNo & <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> int32_t <ISA_LIT>TargetLowering :: analyzeImmediate ( const SDNode * N ) const { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; if ( const ConstantSDNode * Node = dyn_cast < ConstantSDNode > ( N ) ) { if ( TII -> isInlineConstant ( Node -> getAPIntValue ( ) ) ) return <NUM_LIT> ;

uint64_t Val = Node -> getZExtValue ( ) ;


<s> opNum = MI -> getNumOperands ( ) - <NUM_LIT> ; break ; } printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum , O ) ;


<s> unsigned getVmcntBitWidthLo ( unsigned VersionMajor ) {


<s> ++ OpIdx ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( <STR_LIT> ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ; MI . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; OpIdx += <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ( RegListBits >> i ) & <NUM_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , i ) ) ) ; ++ OpIdx ; } }


<s> const TargetRegisterInfo * <ISA_LIT>Subtarget :: getRegisterInfo ( ) const {

return & InstrInfo . getRegisterInfo ( ) ;


<s> for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ;

while ( pos < FIRST_PSEUDO_REGISTER ) reg_alloc_order [ pos ++ ] = <NUM_LIT> ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetHardFloat ( ) ; return false ;


<s> if ( Trunc -> getOperand ( <NUM_LIT> ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { Register Result = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result ) . addReg ( Reg ) ;


<s> else if ( isInt < <NUM_LIT> > ( Imm ) ) return longOp ; else llvm_unreachable ( <STR_LIT> ) ;


<s> if ( ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) && Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) return true ; auto * BV = dyn_cast < BuildVectorSDNode > ( Op ) ; return ( BV && BV -> isConstant ( ) ) ; } ; if ( ( IsFreeTruncation ( Op0 ) && DAG . computeKnownBits ( Op0 ) . countMaxActiveBits ( ) <= <NUM_LIT> ) && ( IsFreeTruncation ( Op1 ) && DAG . ComputeMaxSignificantBits ( Op1 ) <= <NUM_LIT> ) ) return true ;


<s> using namespace <ISA_LIT> ; static const MCPhysReg CtrlRegDecoderTable [ ] = { SA0 , LC0 , SA1 , LC1 , P3_0 , C5 , M0 , M1 , USR , PC , UGP , GP , CS0 , CS1 , UPCYCLELO , UPCYCLEHI , FRAMELIMIT , FRAMEKEY , PKTCOUNTLO , PKTCOUNTHI , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , UTIMERLO , UTIMERHI } ; if ( RegNo >= array_lengthof ( CtrlRegDecoderTable ) ) return MCDisassembler :: Fail ; static_assert ( NoRegister == <NUM_LIT> , <STR_LIT> ) ; if ( CtrlRegDecoderTable [ RegNo ] == NoRegister ) return MCDisassembler :: Fail ; unsigned Register = CtrlRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> const <ISA_LIT>InstrInfo * TII = getInstrInfo ( ) ;

if ( RxSBG . Rotate != <NUM_LIT> ) Mask = ( Mask << RxSBG . Rotate ) | ( Mask >> ( <NUM_LIT> - RxSBG . Rotate ) ) ;


<s> DeadCodeElimination ( MachineFunction & mf , MachineDominatorTree & mdt ) : MF ( mf ) , HII ( * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ) , MDT ( mdt ) , MRI ( mf . getRegInfo ( ) ) {


<s> bool MVEGatherScatterLowering :: isLegalTypeAndAlignment ( unsigned NumElements , unsigned ElemSize , unsigned Alignment ) {

if ( ( ( NumElements == <NUM_LIT> && ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) ) || ( NumElements == <NUM_LIT> && ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) ) || ( NumElements == <NUM_LIT> && ElemSize == <NUM_LIT> ) ) && ElemSize / <NUM_LIT> <= Alignment ) return true ;


<s> symb = ( * targetm . strip_name_encoding ) ( symb ) ; length = strlen ( symb ) ; symbol_name = alloca ( length + <NUM_LIT> ) ; GEN_SYMBOL_NAME_FOR_SYMBOL ( symbol_name , symb , length ) ; lazy_ptr_name = alloca ( length + <NUM_LIT> ) ; GEN_LAZY_PTR_NAME_FOR_SYMBOL ( lazy_ptr_name , symb , length ) ; if ( flag_pic == <NUM_LIT> ) machopic_picsymbol_stub1_section ( ) ; else machopic_symbol_stub1_section ( ) ; if ( flag_pic == <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , stub ) ; fprintf ( file , <STR_LIT> , symbol_name ) ; label ++ ; local_label_0 = alloca ( sizeof ( <STR_LIT> ) ) ; sprintf ( local_label_0 , <STR_LIT> , label ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , local_label_0 ) ; fprintf ( file , <STR_LIT> , local_label_0 ) ; fprintf ( file , <STR_LIT> , lazy_ptr_name , local_label_0 ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , ( TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) , lazy_ptr_name , local_label_0 ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } else { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , stub ) ; fprintf ( file , <STR_LIT> , symbol_name ) ; fprintf ( file , <STR_LIT> , lazy_ptr_name ) ;

fprintf ( file , <STR_LIT> , ( TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) , lazy_ptr_name ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS2 ( SDNode * Op , SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { return SelectThumbAddrModeRI5 ( Op , N , <NUM_LIT> , Base , OffImm , Offset ) ;


<s> void <ISA_LIT>MCCodeEmitter :: expandHalt ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { MCInst TmpInst = MCInstBuilder ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ;


<s> Candidate ( MachineInstr * mi , unsigned reg , unsigned subreg , unsigned freebanks , unsigned weight ) : MI ( mi ) , Reg ( reg ) , SubReg ( subreg ) , FreeBanks ( freebanks ) , Weight ( weight ) {


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _xsave ( void * __P , long long __M ) { return __builtin_ia32_xsave ( __P , __M ) ;


<s> const MachineOperand & MO = MI . getOperand ( OpNo ) ; assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ; return <NUM_LIT> >> TM . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


<s> PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getConstant ( ArgOffset , PtrVT ) ) ; } MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , NULL , <NUM_LIT> ) ) ; } else CalculateTailCallArgDest ( DAG , MF , is<ISA_LIT>64 , Arg , SPDiff , ArgOffset , TailCallArguments ) ;


<s> Target & llvm :: getThe<ISA_LIT>LogicalTarget ( ) { static Target The<ISA_LIT>LogicalTarget ; return The<ISA_LIT>LogicalTarget ;


<s> MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator I = MI ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: SHADER_TYPE : BB -> getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> ShaderType = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MI -> eraseFromParent ( ) ; break ; case AMDGPU :: <ISA_LIT>_INTERP : Lower<ISA_LIT>_INTERP ( MI , * BB , I , MRI ) ; break ; case AMDGPU :: <ISA_LIT>_WQM :

Lower<ISA_LIT>_WQM ( MI , * BB , I , MRI ) ;


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Rot = ( insn >> <STR_LIT> ) & <NUM_LIT> ; unsigned Imm = insn & <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Imm , <NUM_LIT> * Rot ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; <STR_LIT> SubMode = getAMSubModeForBits ( getPUBits ( insn ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( SubMode ) ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; else MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ;

assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Bias = DAG . getConstantFP ( BitsToDouble ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; MVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT ( <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( DestVT . bitsGT ( <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub ) ; }


<s> TargetLowering :: ConstraintWeight <ISA_LIT>TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'h' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' :

if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ;


<s> if ( Modifier && strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT> ) ) == <NUM_LIT> ) { <STR_LIT> VT = ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , VT ) ;


<s> PersonalityIndex = <STR_LIT> :: NUM_PERSONALITY_INDEX ; size_t TotalSize = Ops . size ( ) + <NUM_LIT> ; size_t RoundUpSize = ( TotalSize + <NUM_LIT> ) / <NUM_LIT> * <NUM_LIT> ; Result . resize ( RoundUpSize ) ; OpStreamer . EmitSize ( RoundUpSize ) ; } else { if ( PersonalityIndex == <STR_LIT> :: NUM_PERSONALITY_INDEX ) PersonalityIndex = ( Ops . size ( ) <= <NUM_LIT> ) ? <STR_LIT> :: AEABI_UNWIND_CPP_PR0 : <STR_LIT> :: AEABI_UNWIND_CPP_PR1 ;

if ( PersonalityIndex == <STR_LIT> :: AEABI_UNWIND_CPP_PR0 ) {


<s> MVT ResTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; if ( HST -> isHVXVectorType ( ResTy , true ) ) return SelectHvxVAlign ( N ) ; const SDLoc & dl ( N ) ; unsigned VecLen = ResTy . getSizeInBits ( ) ; if ( VecLen == <NUM_LIT> ) { SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ; SDNode * R = CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , Ops ) ; SDNode * C ; SDValue M0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue M1 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; if ( HST -> useCompound ( ) ) { C = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , M0 , N -> getOperand ( <NUM_LIT> ) , M1 ) ; } else { SDNode * T = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , M1 ) ; C = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( T , <NUM_LIT> ) , M0 ) ; } SDNode * S = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( R , <NUM_LIT> ) , SDValue ( C , <NUM_LIT> ) ) ; SDValue E = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , ResTy , SDValue ( S , <NUM_LIT> ) ) ; ReplaceNode ( N , E . getNode ( ) ) ; } else { assert ( VecLen == <NUM_LIT> ) ; SDNode * Pu = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDNode * VA = CurDAG -> getMachineNode ( <STR_LIT> , dl , ResTy , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , SDValue ( Pu , <NUM_LIT> ) ) ; ReplaceNode ( N , VA ) ; }


<s> return ( int16x4_t ) __builtin_neon_vrshrn_nv4si ( __a , __b ) ;


<s> if ( riscv_v_ext_vector_mode_p ( mode ) ) { scalar_mode inner_mode = GET_MODE_INNER ( mode ) ; REAL_VALUE_TYPE f = REAL_VALUE_ATOF ( <STR_LIT> , inner_mode ) ; rtx ele = const_double_from_real_value ( f , inner_mode ) ; start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; rtx dup = gen_const_vec_duplicate ( mode , ele ) ; emit_move_insn ( dest , dup ) ; rtx_insn * insn = get_last_insn ( ) ; rtx src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; ASSERT_TRUE ( rtx_equal_p ( src , gen_rtx_VEC_DUPLICATE ( mode , XEXP ( src , <NUM_LIT> ) ) ) ) ; end_sequence ( ) ; } } FOR_EACH_MODE_IN_CLASS ( mode , MODE_VECTOR_BOOL ) { if ( riscv_v_ext_vector_mode_p ( mode ) ) { start_sequence ( ) ; rtx dest = gen_reg_rtx ( mode ) ; emit_move_insn ( dest , CONSTM1_RTX ( mode ) ) ;


<s> return __arm_vhcaddq_rot90_s32 ( __a , __b ) ;


<s> case AsmToken :: Dot : break ; } const MCExpr * DestValue ; if ( getParser ( ) . parseExpression ( DestValue ) ) return MatchOperand_NoMatch ; bool IsPic = getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ; <ISA_LIT>MCExpr :: VariantKind Kind = IsPic ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_WPLT30 : <ISA_LIT>MCExpr :: VK_Sparc_WDI<ISA_LIT>30 ; const MCExpr * DestExpr = <ISA_LIT>MCExpr :: create ( Kind , DestValue , getContext ( ) ) ;

Operands . push_back ( <STR_LIT> ( DestExpr , S , E ) ) ;


<s> static const char * isa_str ( const struct loongarch_isa * isa , char separator ) { APPEND_STRING ( loongarch_isa_base_strings [ isa -> base ] ) APPEND1 ( separator ) if ( isa -> fpu == ISA_EXT_NOFPU ) { APPEND_STRING ( <STR_LIT> OPTSTR_ISA_EXT_FPU ) } else { APPEND_STRING ( OPTSTR_ISA_EXT_FPU ) APPEND_STRING ( loongarch_isa_ext_strings [ isa -> fpu ] ) }

APPEND1 ( '\0' ) return XOBFINISH ( & msg_obstack , const char * ) ;


<s> return Result ; } case <STR_LIT> : case <STR_LIT> : return LowerTrig ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerFDIV ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return LowerGlobalAddress ( MFI , Op , DAG ) ;


<s> void <ISA_LIT>InstPrinter :: printAbs ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {


<s> DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_RegMask : CSR_Win32_CFGuard_Check_NoSSE_RegMask ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: SwiftTail : if ( ! Is64Bit ) return CSR_32_RegMask ; return IsWin64 ? CSR_Win64_SwiftTail_RegMask : CSR_64_SwiftTail_RegMask ; case CallingConv :: <ISA_LIT>_64_SysV : return CSR_64_RegMask ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ;


<s> mco = GetSymbolRef ( mo , GetSymbolFromOperand ( mo , ap ) , ap ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : mco = GetSymbolRef ( mo , ap . GetCPISymbol ( mo . getIndex ( ) ) , ap ) ; break ; case MachineOperand :: MO_BlockAddress : mco = GetSymbolRef ( mo , ap . GetBlockAddressSymbol ( mo . getBlockAddress ( ) ) , ap ) ; break ; default : assert ( <NUM_LIT> ) ; break ; } mci . addOperand ( mco ) ; }


<s> Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RTLIB :: Libcall LC = ( ArgVT == <STR_LIT> ) ? RTLIB :: SINCOS_F64 : RTLIB :: SINCOS_F32 ; CallingConv :: ID CC = getLibcallCallingConv ( LC ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DL ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CC , RetTy , Callee , std :: move ( Args ) ) . setDiscardResult ( ShouldUseSRet ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; if ( ! ShouldUseSRet ) return CallResult . first ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) , dl ) ) ; SDValue LoadCos = DAG . getLoad ( ArgVT , dl , LoadSin . getValue ( <NUM_LIT> ) , Add , MachinePointerInfo ( ) ) ; SDVTList Tys = DAG . getVTList ( ArgVT , ArgVT ) ;

return DAG . getNode ( <STR_LIT> , dl , Tys , LoadSin . getValue ( <NUM_LIT> ) , LoadCos . getValue ( <NUM_LIT> ) ) ;


<s> SDValue Setcc = DAG . getNode ( <STR_LIT> , dl , VT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) ) ; bool ReplaceOtherUses = ! N0 . hasOneUse ( ) ; DCI . CombineTo ( N , Setcc ) ; if ( ReplaceOtherUses ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , Setcc ) ; DCI . CombineTo ( N0 . getNode ( ) , Trunc ) ; } return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) ) return R ;

if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; } setMinFunctionAlignment ( <NUM_LIT> ) ;

setPrefFunctionAlignment ( <NUM_LIT> ) ;


<s> return ( ( int ) ( spu_extract ( spu_gather ( spu_cmpeq ( a , b ) ) , <NUM_LIT> ) == <NUM_LIT> ) ) ;


<s> if ( CPU . empty ( ) || CPU == <STR_LIT> ) { if ( TT . getArch ( ) == Triple :: mips || TT . getArch ( ) == Triple :: mipsel ) CPU = <STR_LIT> ; else CPU = <STR_LIT> ; } return StringSwitch < <ISA_LIT>ABIInfo > ( CPU ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: O32 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Case ( <STR_LIT> , <ISA_LIT>ABIInfo :: N64 ( ) ) . Default ( <ISA_LIT>ABIInfo :: Unknown ( ) ) ;


<s> bool SchedulerBase :: hasSideEffects ( const MachineInstr * MI ) { const TargetInstrDesc & TID = MI -> getDesc ( ) ;

return ( TID . mayLoad ( ) || TID . mayStore ( ) || TID . hasUnmodeledSideEffects ( ) ) ;


<s> <ISA_LIT>PLT0 :: <ISA_LIT>PLT0 ( SectionData & pParent ) : PLT :: Entry < sizeof ( arm_plt0 ) > ( pParent ) {


<s> Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; bool UseAligned = ! NeedsAligna && ( NeedAlign <= HasAlign ) ; unsigned StoreOpc = UseAligned ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcR , getKillRegState ( IsKill ) ) . cloneMemRefs ( * MI ) ;


<s> rtx tmp = op1 ; op1 = op2 ; op2 = tmp ; } break ; default : gcc_unreachable ( ) ; } slt = gen_rtx_LT ( SImode , op1 , op2 ) ; if ( reverse ) { rtx tmp = copy_to_mode_reg ( SImode , gen_rtx_NEG ( SImode , slt ) ) ; emit_insn ( gen_add3_insn ( op0 , tmp , const1_rtx ) ) ;


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MBBI ) const { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : { MachineInstr * NewMI = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MI . setDesc ( get ( <STR_LIT> ) ) ;

llvm :: finalizeBundle ( MBB , NewMI , * ++ MBBI ) ;


<s> return getStandardCSEConfigForOpt ( TM -> getOptLevel ( ) ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) {


<s> OperandMatchResultTy parseADDR64 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegister ( Operands , RegGR , <STR_LIT> , ADDR64Reg ) ;


<s> unsigned RHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! getConstantVRegVal ( RHS , MRI ) ) std :: swap ( RHS , LHS ) ; const auto RHSImm = getConstantVRegVal ( RHS , MRI ) ; if ( ! RHSImm || * RHSImm != <NUM_LIT> ) return false ; const RegisterBank & RB = * RBI . getRegBank ( LHS , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) return false ; const auto Pred = ( CmpInst :: Predicate ) CCMI -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ; if ( Pred != CmpInst :: ICMP_NE && Pred != CmpInst :: ICMP_EQ ) return false ; const unsigned CmpWidth = MRI . getType ( LHS ) . getSizeInBits ( ) ; unsigned CBOpc = <NUM_LIT> ; if ( CmpWidth <= <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT> : <STR_LIT> ) ;

else if ( CmpWidth == <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT> : <STR_LIT> ) ;


<s> CCRetInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT VT = VA . getValVT ( ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ;

Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VT , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> AMDGPUAsmPrinter :: AMDGPUAsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> MatrixKind getMatrixKind ( ) const { assert ( Kind == k_MatrixRegister && <STR_LIT> ) ;


<s> if ( requiresRegisterScavenging ( MF ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } else { BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } if ( LP64 ) { if ( requiresRegisterScavenging ( MF ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; else BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: ImplicitKill ) ; } else {


<s> bool hasFP ( const MachineFunction & ) const override { return true ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue ShOps [ <NUM_LIT> ] ; ShOps [ <NUM_LIT> ] = ShAmt ; ShOps [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; ShOps [ <NUM_LIT> ] = ShOps [ <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ;

ShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ShOps [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> const CallLowering * <ISA_LIT>Subtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ;


<s> if ( ET -> isF8_152Ty ( ) || ET -> isF8_143Ty ( ) ) return Sz == <NUM_LIT> || Sz == <NUM_LIT> ; if ( const auto * IT = dyn_cast < IntegerType > ( ET ) ) { if ( IT -> getBitWidth ( ) == <NUM_LIT> ) return Sz == <NUM_LIT> || Sz == <NUM_LIT> || Sz == <NUM_LIT> ; if ( IT -> getBitWidth ( ) == <NUM_LIT> ) return Sz == <NUM_LIT> || Sz == <NUM_LIT> ; if ( IT -> getBitWidth ( ) == <NUM_LIT> ) return Sz == <NUM_LIT> || Sz == <NUM_LIT> ;

if ( IT -> getBitWidth ( ) == <NUM_LIT> ) return Sz == <NUM_LIT> ;


<s> virtual ~ <ISA_LIT>CommonSubtarget ( ) {


<s> virtual StringRef getPassName ( ) const override {


<s> bool nds32_n8_ex_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg ; switch ( get_attr_type ( producer ) ) { case TYPE_ALU : if ( movd44_insn_p ( producer ) ) def_reg = extract_movd44_odd_reg ( producer ) ; else def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_MUL : case TYPE_MAC : def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_DIV : if ( INSN_CODE ( producer ) == CODE_FOR_divmodsi4 || INSN_CODE ( producer ) == CODE_FOR_udivmodsi4 ) def_reg = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; else def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_LOAD : case TYPE_STORE : case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE :

if ( ! post_update_insn_p ( producer ) ) return false ;


<s> if ( ! isImm ( ) ) return false ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ) { int64_t Value = CE -> getValue ( ) ; return Value == ( int64_t ) ( int8_t ) Value ; } return true ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { unsigned NumArgVals = Ins . size ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; ResetTmpOffsetMap ( ) ; InitReservedFrameCount ( F ) ;

const char * tmpName = ESNames :: createESName ( PAN :: getArgsLabel ( FuncName ) ) ;


<s> bool <ISA_LIT>InstrInfo :: PredicateInstruction ( MachineInstr & MI , ArrayRef < MachineOperand > Pred ) const { if ( MI . getOpcode ( ) != <STR_LIT> || Pred . size ( ) != <NUM_LIT> ) { return false ; } assert ( isPredicable ( MI ) && <STR_LIT> ) ; assert ( Pred [ <NUM_LIT> ] . isImm ( ) && <STR_LIT> ) ; assert ( Pred [ <NUM_LIT> ] . isReg ( ) && <STR_LIT> ) ; bool Inverted = Pred [ <NUM_LIT> ] . getImm ( ) ; auto ErrCode = MI . getOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( Inverted ? <STR_LIT> : <STR_LIT> ) ) ;

MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) . add ( ErrCode ) ;


<s> else switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; EVT TheVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MachinePointerInfo :: getFixedStack ( SSFI ) , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( TheVT ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , MemSize , MemSize ) ; Value = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , array_lengthof ( Ops ) , DstTy , MMO ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , MemSize , MemSize ) ; if ( Opc != <STR_LIT> ) { SDValue Ops [ ] = { Chain , Value , StackSlot } ; SDValue FIST = DAG . getMemIntrinsicNode ( Opc , DL , DAG . getVTList ( <STR_LIT> ) , Ops , array_lengthof ( Ops ) , DstTy , MMO ) ; return std :: make_pair ( FIST , StackSlot ) ; } else { SDValue ftol = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , Value ) ;

SDValue eax = DAG . getCopyFromReg ( ftol , DL , <STR_LIT> , <STR_LIT> , ftol . getValue ( <NUM_LIT> ) ) ;


<s> const SCEVAddRecExpr * RH = dyn_cast < SCEVAddRecExpr > ( RHS ) ; if ( LH && RH ) { BasicBlock * LHB = LH -> getLoop ( ) -> getHeader ( ) ; BasicBlock * RHB = RH -> getLoop ( ) -> getHeader ( ) ; if ( ! DT . dominates ( LHB , RHB ) ) {

<ISA_LIT>_DEBUG ( LHB -> getName ( ) + <STR_LIT> + RHB -> getName ( ) + <STR_LIT> ) ;


<s> void llvm :: Lower<ISA_LIT>MachineInstrToMCInst ( const MachineInstr * MI , MCInst & OutMI , AsmPrinter & AP ) { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp = LowerOperand ( MI , MO , AP ) ;

if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ;


<s> if ( crtl -> is_leaf && ! df_regs_ever_live_p ( LAST_ARG_REGNUM ) ) cfun -> machine -> pic_reg = gen_rtx_REG ( SImode , LAST_ARG_REGNUM ) ; else cfun -> machine -> pic_reg = pic_offset_table_rtx ; } return cfun -> machine -> pic_reg ;


<s> if ( ! VT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) return false ; unsigned NumElts = Mask . size ( ) ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; unsigned MaxScale = <NUM_LIT> / EltSizeInBits ; for ( unsigned Scale = <NUM_LIT> ; Scale <= MaxScale ; Scale += Scale ) { unsigned SrcEltBits = EltSizeInBits * Scale ; if ( SrcEltBits < <NUM_LIT> && ! Subtarget . hasBWI ( ) ) continue ;


<s> MachineBasicBlock :: iterator E = I -> getParent ( ) -> end ( ) ; MachineInstr & MemMI = * I ; MachineBasicBlock :: iterator MBBI = I ; Register BaseReg = getLdStBaseOp ( MemMI ) . getReg ( ) ; int Offset = getLdStOffsetOp ( MemMI ) . getImm ( ) ; if ( MBBI == B || Offset != <NUM_LIT> ) return E ; if ( ! isTagStore ( MemMI ) ) { bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { Register DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } } ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; unsigned Count = <NUM_LIT> ; do { -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( isMatchingUpdateInsn ( * I , MI , BaseReg , Offset ) ) return MBBI ; LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; if ( ! ModifiedRegUnits . available ( BaseReg ) || ! UsedRegUnits . available ( BaseReg ) ) return E ;

} while ( MBBI != B && Count < Limit ) ;


<s> if ( MayFoldLoad && N2 -> getOpcode ( ) == <STR_LIT> && N2 -> hasOneUse ( ) && tryFoldVecLoad ( Node , N2 . getNode ( ) , N2 . getOperand ( <NUM_LIT> ) , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) { SDValue Load = N2 . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N0 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Imm , Load . getOperand ( <NUM_LIT> ) , InFlag } ; SDVTList VTs = CurDAG -> getVTList ( VT , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;

MachineSDNode * CNode = CurDAG -> getMachineNode ( MOpc , dl , VTs , Ops ) ;


<s> unsigned CallOpc = PrepareCall ( DAG , Callee , InFlag , Chain , CallSeqStart , dl , SPDiff , isTailCall , isPatchPoint , hasNest , RegsToPass , Ops , NodeTys , CS , Subtarget ) ; if ( isVarArg && Subtarget . isSVR4ABI ( ) && ! Subtarget . is<ISA_LIT>64 ( ) ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; int BytesCalleePops = ( CallConv == CallingConv :: Fast && getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ? NumBytes : <NUM_LIT> ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } if ( ! isTailCall && Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) && ! isPatchPoint ) { if ( CallOpc == <STR_LIT> ) { CallOpc = <STR_LIT> ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Ops . insert ( std :: next ( Ops . begin ( ) ) , AddTOC ) ; } else if ( ( CallOpc == <STR_LIT> ) && ( ! isLocalCall ( Callee ) || DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) CallOpc = <STR_LIT> ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( BytesCalleePops , dl , true ) , InFlag , dl ) ;


<s> if ( saved_regs & ( <NUM_LIT> << regno ) ) { if ( TARGET_H8300S ) { if ( ( TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) n_regs = <NUM_LIT> ; else if ( ( TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) n_regs = <NUM_LIT> ; else if ( ( TARGET_H8300SX || ( regno & <NUM_LIT> ) == <NUM_LIT> ) && ( ( saved_regs >> regno ) & <NUM_LIT> ) == <NUM_LIT> ) n_regs = <NUM_LIT> ; } h8300_push_pop ( regno , n_regs , false , false ) ; }


<s> <ISA_LIT>CombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize , GISelKnownBits * KB , MachineDominatorTree * MDT ) : CombinerInfo ( true , false , nullptr , EnableOpt , OptSize , MinSize ) , KB ( KB ) , MDT ( MDT ) {

if ( ! GeneratedRuleCfg . parseCommandLineOption ( ) ) report_fatal_error ( <STR_LIT> ) ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> if ( ARM_FUNC_TYPE ( cfun -> machine -> func_type ) == ARM_FT_UNKNOWN ) cfun -> machine -> func_type = arm_compute_func_type ( ) ;


<s> setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT FloatTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : FloatTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; if ( ! HasMVEFP ) setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ;


<s> return __builtin_mve_vcmpeqq_n_uv4si ( __a , __b ) ;


<s> assert ( TRI -> spillSGPRToVGPR ( ) && <STR_LIT> ) ; int NumLanes = Size / <NUM_LIT> ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( int I = <NUM_LIT> ; I < NumLanes ; ++ I , ++ NumVGPRSpillLanes ) { unsigned LaneVGPR ; unsigned VGPRIndex = ( NumVGPRSpillLanes % WaveSize ) ; if ( VGPRIndex == <NUM_LIT> ) { LaneVGPR = TRI -> findUnusedRegister ( MRI , & <STR_LIT> , MF ) ; if ( LaneVGPR == <STR_LIT> ) { SGPRToVGPRSpills . erase ( FI ) ; NumVGPRSpillLanes -= I ; return false ; } Optional < int > CSRSpillFI ; if ( FrameInfo . hasCalls ( ) && CSRegs && isCalleeSavedReg ( CSRegs , LaneVGPR ) ) { CSRSpillFI = FrameInfo . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; } SpillVGPRs . push_back ( SGPRSpillVGPRCSR ( LaneVGPR , CSRSpillFI ) ) ; for ( MachineBasicBlock & BB : MF ) BB . addLiveIn ( LaneVGPR ) ; } else { LaneVGPR = SpillVGPRs . back ( ) . VGPR ; } SpillLanes . push_back ( SpilledReg ( LaneVGPR , VGPRIndex ) ) ; }


isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * llscMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; for ( MachineBasicBlock :: succ_iterator I = BB -> succ_begin ( ) , E = BB -> succ_end ( ) ; I != E ; ++ I ) EM -> insert ( std :: make_pair ( * I , sinkMBB ) ) ; sinkMBB -> transferSuccessors ( thisMBB ) ; F -> insert ( It , llscMBB ) ; F -> insert ( It , sinkMBB ) ; BuildMI ( thisMBB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( llscMBB ) ; unsigned reg_res = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , reg_ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , reg_v2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , reg_store = F -> getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( llscMBB , dl , TII -> get ( is32 ? <STR_LIT> : <STR_LIT> ) , reg_res ) . addImm ( <NUM_LIT> ) . addReg ( reg_ptr ) ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { unsigned reg_cmp = F -> getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( llscMBB , dl , TII -> get ( <STR_LIT> ) , reg_cmp ) . addReg ( reg_v2 ) . addReg ( reg_res ) ; BuildMI ( llscMBB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( reg_cmp ) . addMBB ( sinkMBB ) ; BuildMI ( llscMBB , dl , TII -> get ( <STR_LIT> ) , reg_store ) . addReg ( <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v32s8 , v16s16 , v8s32 , v4s64 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( auto Ty : { v16s16 , v8s32 } ) setAction ( { G_MUL , Ty } , Legal ) ; for ( const auto & Ty : { v64s8 , v32s16 , v16s32 , v8s64 } ) { setAction ( { G_CONCAT_VECTORS , Ty } , Legal ) ; setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , Ty } , Legal ) ; } for ( const auto & Ty : { v32s8 , v16s16 , v8s32 , v4s64 } ) { setAction ( { G_CONCAT_VECTORS , <NUM_LIT> , Ty } , Legal ) ;

setAction ( { G_UNMERGE_VALUES , Ty } , Legal ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( <NUM_LIT> , Dot ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ;

StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( Mem . Reg ) ) ;


<s> for ( auto RegNo : getRegList ( ) ) Inst . addOperand ( MCOperand :: createReg ( RegNo ) ) ;


<s> assert ( ( MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Default || MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static ) && <STR_LIT> ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { MovePCtoLROffset = <NUM_LIT> ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) { const Triple & TheTriple = STI . getTargetTriple ( ) ;

Is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _pext_u32 ( unsigned int __X , unsigned int __Y ) {


<s> SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) ;


<s> MCE . addRelocation ( MachineRelocation :: getJumpTable ( MCE . getCurrentPCOffset ( ) , Reloc , JTIndex , <NUM_LIT> , false ) ) ;


<s> unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle = false ; break ; } if ( EltNo == <NUM_LIT> ) { EltNo = ByteSource / <NUM_LIT> ; } else if ( EltNo != ByteSource / <NUM_LIT> ) { isFourElementShuffle = false ; break ; } } PFIndexes [ i ] = EltNo ; } if ( isFourElementShuffle ) { unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost < <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; }

if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ;


<s> static void s390_default_align ( struct gcc_options * opts ) { if ( opts -> x_flag_align_functions && ! opts -> x_str_align_functions && opts -> x_s390_tune >= PROCESSOR_2964_Z13 ) opts -> x_str_align_functions = <STR_LIT> ;


<s> static tree sh_handle_interrupt_handler_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ;


<s> static bool ix86_function_ms_hook_prologue ( const_tree fn ) { if ( fn && lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fn ) ) ) { if ( decl_function_context ( fn ) != NULL_TREE ) error_at ( DECL_SOURCE_LOCATION ( fn ) , <STR_LIT> ) ; else return true ;


<s> if ( SDValue S = getVectorShiftByInt ( Op , DAG ) ) return S ;


<s> rtx op3 = expand_normal ( arg3 ) ; enum insn_code icode = d -> icode ; const struct insn_data_d * insn_p = & insn_data [ icode ] ; machine_mode mode0 = insn_p -> operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_p -> operand [ <NUM_LIT> ] . mode ; enum rtx_code comparison = UNEQ ; bool need_ucomi = false ; enum rtx_code comi_comparisons [ <NUM_LIT> ] = { UNEQ , GT , GE , UNORDERED , LTGT , UNLE , UNLT , ORDERED , UNEQ , UNLT , UNLE , LT , LTGT , GE , GT , LT , UNEQ , GT , GE , UNORDERED , LTGT , UNLE , UNLT , ORDERED , UNEQ , UNLT , UNLE , LT , LTGT , GE , GT , LT } ; bool need_ucomi_values [ <NUM_LIT> ] = { true , false , false , true , true , false , false , true , true , false , false , true , true , false , false , true , false , true , true , false , false , true , true , false , false , true , true , false , false , true , true , false } ; if ( ! CONST_INT_P ( op2 ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( INTVAL ( op2 ) < <NUM_LIT> || INTVAL ( op2 ) >= <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( ! insn_p -> operand [ <NUM_LIT> ] . predicate ( op3 , SImode ) ) { error ( <STR_LIT> ) ; return const0_rtx ; } comparison = comi_comparisons [ INTVAL ( op2 ) ] ; need_ucomi = need_ucomi_values [ INTVAL ( op2 ) ] ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , <NUM_LIT> ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_p -> operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_p -> operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( need_ucomi ) icode = icode == CODE_FOR_sse_comi_round ? CODE_FOR_sse_ucomi_round : CODE_FOR_sse2_ucomi_round ; pat = GEN_FCN ( icode ) ( op0 , op1 , op3 ) ; if ( ! pat ) return <NUM_LIT> ; if ( INTVAL ( op3 ) == NO_ROUND ) {

pat = ix86_erase_embedded_rounding ( pat ) ;


<s> bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; } return true ;


<s> return Decode2RUSInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode2RUSInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode2RUSInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode2RUSBitpInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode2RUSBitpInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode2RUSInstruction ( Inst , Insn , Address , Decoder ) ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return Decode3RImmInstruction ( Inst , Insn , Address , Decoder ) ;


<s> case <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_G1 : case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G1 : case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G1_NC : Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G2 : case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G2_NC : case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G2 : case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G2 : case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G2 : Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G3 : Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> Patterns . push_back ( Pattern ) ; Found = true ; } } ; typedef MachineCombinerPattern MCP ; switch ( Opc ) { default : break ; case <STR_LIT> : assert ( Root . getOperand ( <NUM_LIT> ) . isReg ( ) && Root . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDW_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDW_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDX_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDX_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBW_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBW_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBX_OP1 ) ; setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULSUBX_OP2 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDWI_OP1 ) ; break ; case <STR_LIT> : setFound ( <STR_LIT> , <NUM_LIT> , <STR_LIT> , MCP :: MULADDXI_OP1 ) ; break ;


<s> int src_regno ; if ( src == pc_rtx ) { if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_dbx_register_number ( dest_regno ) ) ; return ; } src_regno = REGNO ( src ) ; switch ( src_regno ) { case PR_REG ( <NUM_LIT> ) : gcc_assert ( dest_regno == current_frame_info . r [ reg_save_pr ] ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_dbx_register_number ( dest_regno ) ) ; break ; case AR_UNAT_REGNUM : gcc_assert ( dest_regno == current_frame_info . r [ reg_save_ar_unat ] ) ;


<s> Reserved . set ( AMDGPU :: FLAT_SCR ) ; Reserved . set ( AMDGPU :: VGPR255 ) ;


<s> return BRANCH_COST ( optimize_function_for_speed_p ( cfun ) , false ) >= <NUM_LIT> ;


<s> const char * name = lbasename ( main_input_filename ) ; unsigned len = strlen ( name ) ; char * clean_name = alloca ( len + <NUM_LIT> ) ;


<s> <STR_LIT> CC = ( <STR_LIT> ) Op . getImm ( ) ; const char * Str = <ISA_LIT>_condCodeToString ( CC ) ;


<s> return ( __m64 ) __builtin_ia32_psrlw ( ( __v4hi ) __m , __count ) ;


<s> if ( aarch64_float_const_zero_rtx_p ( value ) ) { * intval = <NUM_LIT> ; return true ; } scalar_float_mode mode ; if ( ! CONST_DOUBLE_P ( value ) || ! is_a < scalar_float_mode > ( GET_MODE ( value ) , & mode ) || GET_MODE_BITSIZE ( mode ) > HOST_BITS_PER_WIDE_INT || GET_MODE_BITSIZE ( mode ) > GET_MODE_BITSIZE ( DFmode ) ) return false ; unsigned HOST_WIDE_INT ival = <NUM_LIT> ; long res [ <NUM_LIT> ] ; real_to_target ( res , CONST_DOUBLE_REAL_VALUE ( value ) , REAL_MODE_FORMAT ( mode ) ) ; if ( mode == DFmode ) { int order = BYTES_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ; ival = zext_hwi ( res [ order ] , <NUM_LIT> ) ; ival |= ( zext_hwi ( res [ <NUM_LIT> - order ] , <NUM_LIT> ) << <NUM_LIT> ) ; } else ival = zext_hwi ( res [ <NUM_LIT> ] , <NUM_LIT> ) ; * intval = ival ; return true ;


<s> emit_move_insn ( A0 ( HImode , <NUM_LIT> ) , chainval ) ; emit_move_insn ( A0 ( QImode , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> - <NUM_LIT> ) ) ; emit_move_insn ( A0 ( HImode , <NUM_LIT> ) , function ) ; emit_move_insn ( A0 ( QImode , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ;


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool IsFakeVector = ! VT . isVector ( ) && ! IsF128 ; MVT LogicVT = VT ; if ( IsFakeVector ) LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignMask ( EltBits ) ; const fltSemantics & Sem = SelectionDAG :: EVTToAPFloatSemantics ( VT ) ; SDValue Mask = DAG . getConstantFP ( APFloat ( Sem , MaskElt ) , dl , LogicVT ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; unsigned LogicOp = IsFABS ? <STR_LIT> :


<s> const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const ArgDescriptor * Arg ; const TargetRegisterClass * ArgRC ; LLT ArgTy ; std :: tie ( Arg , ArgRC , ArgTy ) = MFI -> getPreloadedValue ( ArgType ) ; if ( ! Arg ) { assert ( ArgType == <STR_LIT> ) ;

B . buildConstant ( DstReg , <NUM_LIT> ) ;


emit_insn ( gen_rtx_SET ( res , gen_rtx_fmt_ee ( code , DImode , op0 , op1 ) ) ) ;


<s> O << <STR_LIT> ; if ( Count > <NUM_LIT> ) { bool IsVec64 = ( Layout < <STR_LIT> ) ; unsigned SubRegIdx = IsVec64 ? <STR_LIT> : <STR_LIT> ; for ( unsigned I = <NUM_LIT> ; I < Count ; I ++ ) { std :: string Name = getRegisterName ( MRI . getSubReg ( Reg , SubRegIdx ++ ) ) ; Name [ <NUM_LIT> ] = 'v' ; O << Name << LayoutStr ;

if ( I != Count - <NUM_LIT> ) O << <STR_LIT> ;


<s> void <ISA_LIT>AsmBackend :: processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t & Value , bool & IsResolved ) { IsResolved = true ;

( void ) adjustFixupValue ( Fixup , Value , & Asm . getContext ( ) ) ;


if ( Directive != <STR_LIT> && Directive != <STR_LIT> && Directive != <STR_LIT> && Directive != <STR_LIT> ) {


<s> auto End = MCSymbolRefExpr :: create ( TempSym , getContext ( ) ) ;

auto Expr = MCBinaryExpr :: create ( MCBinaryExpr :: Sub , End , Start , getContext ( ) ) ;


<s> case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL16_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_TLSLD16_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC16_LO ; break ; } } const MCExpr * Expr = MCSymbolRefExpr :: Create ( Symbol , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , PB , Ctx ) ; } if ( isDarwin ) { switch ( access ) { case <STR_LIT> : Expr = <ISA_LIT>MCExpr :: CreateHa16 ( Expr , Ctx ) ; break ; case <STR_LIT> :

Expr = <ISA_LIT>MCExpr :: CreateLo16 ( Expr , Ctx ) ;


<s> assert ( ( ( RootMask . size ( ) > OpMask . size ( ) && RootMask . size ( ) % OpMask . size ( ) == <NUM_LIT> ) || ( OpMask . size ( ) > RootMask . size ( ) && OpMask . size ( ) % RootMask . size ( ) == <NUM_LIT> ) || OpMask . size ( ) == RootMask . size ( ) ) && <STR_LIT> ) ; int MaskWidth = std :: max < int > ( OpMask . size ( ) , RootMask . size ( ) ) ; int RootRatio = std :: max < int > ( <NUM_LIT> , OpMask . size ( ) / RootMask . size ( ) ) ; int OpRatio = std :: max < int > ( <NUM_LIT> , RootMask . size ( ) / OpMask . size ( ) ) ; assert ( ( ( RootRatio == <NUM_LIT> && OpRatio == <NUM_LIT> ) || ( RootRatio == <NUM_LIT> ) != ( OpRatio == <NUM_LIT> ) ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Mask ; Mask . reserve ( MaskWidth ) ; for ( int i = <NUM_LIT> ; i < MaskWidth ; ++ i ) { int RootIdx = i / RootRatio ; if ( RootMask [ RootIdx ] < <NUM_LIT> ) { Mask . push_back ( RootMask [ RootIdx ] ) ; continue ; } int RootMaskedIdx = RootMask [ RootIdx ] * RootRatio + i % RootRatio ; int OpIdx = RootMaskedIdx / OpRatio ; if ( OpMask [ OpIdx ] < <NUM_LIT> ) {


<s> if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return true ; switch ( Fixup . getTargetKind ( ) ) { default : break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : if ( Target . isAbsolute ( ) ) return false ; break ;


<s> if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget -> hasInt256 ( ) ) if ( ! <STR_LIT> ( N00 . getNode ( ) ) ) return SDValue ( ) ;

if ( N00 . getValueType ( ) == <STR_LIT> && ExtraVT . getSizeInBits ( ) < <NUM_LIT> ) {


<s> if ( orig [ i ] != equiv [ i ] ) { if ( ( orig [ i ] == 'Q' || orig [ i ] == 'L' ) && equiv [ i ] == 'W' ) continue ; if ( ( orig [ i ] == '6' || orig [ i ] == '3' ) && equiv [ i ] == '1' ) continue ; if ( ( orig [ i ] == '4' || orig [ i ] == '2' ) && equiv [ i ] == '6' ) continue ; return false ;


<s> static_assert ( NoOverlap < u16 , expected , OperandAtT :: Mask ... > , <STR_LIT> ) ; Proxy < typename FilterOperand < OperandAtT ... > :: result > proxy { func } ; constexpr u16 mask = ( ~ OperandAtT :: Mask & ... & <NUM_LIT> ) ;

constexpr bool expanded = ( OperandAtT :: NeedExpansion || ... ) ;


<s> SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , V . getOperand ( <NUM_LIT> ) ) ; Res = DAG . getNode ( SrcOpc0 , DL , SrcVT0 , DAG . getBitcast ( SrcVT0 , Res ) ) ; return DAG . getBitcast ( VT , Res ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Src1 . isUndef ( ) || Src0 . getOperand ( <NUM_LIT> ) == Src1 . getOperand ( <NUM_LIT> ) ) { SDValue LHS = DAG . getBitcast ( VT , Src0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getBitcast ( VT , Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , V . getOperand ( <NUM_LIT> ) ) ; Res = DAG . getNode ( SrcOpc0 , DL , SrcVT0 , DAG . getBitcast ( SrcVT0 , Res ) , Src0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( VT , Res ) ; } break ; } return SDValue ( ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ;


<s> static int uses_ls_unit ( rtx_insn * insn ) { rtx set = single_set ( insn ) ;

if ( set != <NUM_LIT> && ( GET_CODE ( SET_DEST ( set ) ) == MEM || GET_CODE ( SET_SRC ( set ) ) == MEM ) ) return <NUM_LIT> ;


<s> unsigned Idx = isPairedLdSt ( MI ) || <ISA_LIT>InstrInfo :: isPreLdSt ( MI ) ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; OutStreamer -> EmitBinaryData ( <STR_LIT> ) ; unsigned DestRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; bool UsedMask [ ] = { false , false , false } ; unsigned SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) && <STR_LIT> ) ; SrcRegs [ I ] = Op -> getReg ( ) ; if ( SrcRegs [ I ] != DestRegs [ I ] ) { UsedMask [ I ] = true ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else { EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; }


<s> Item -> IntValue = IntValue ; Item -> StringValue = std :: string ( StringValue ) ; return ; }

Contents . push_back ( { AttributeType :: NumericAndText , Attribute , IntValue , std :: string ( StringValue ) } ) ;


<s> SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? AMDGPU :: V_DIV_SCALE_F64 : AMDGPU :: V_DIV_SCALE_F32 ; const SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; const SDValue False = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = {

Zero , N -> getOperand ( <NUM_LIT> ) , Zero , N -> getOperand ( <NUM_LIT> ) , Zero , N -> getOperand ( <NUM_LIT> ) , False , Zero } ;


<s> if ( SetjmpF ) { FunctionType * SetjmpFTy = SetjmpF -> getFunctionType ( ) ; FTy = FunctionType :: get ( Type :: getInt32PtrTy ( C ) , { SetjmpFTy -> getParamType ( <NUM_LIT> ) , IRB . getInt32Ty ( ) , Type :: getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } , false ) ; SaveSetjmpF = getEmscriptenFunction ( FTy , <STR_LIT> , & M ) ; FTy = FunctionType :: get ( IRB . getInt32Ty ( ) , { getAddrIntType ( & M ) , Type :: getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } , false ) ; TestSetjmpF = getEmscriptenFunction ( FTy , <STR_LIT> , & M ) ; for ( User * U : SetjmpF -> users ( ) ) { auto * UI = cast < Instruction > ( U ) ; SetjmpUsers . insert ( UI -> getFunction ( ) ) ; } } } if ( EnableEH ) { for ( Function & F : M ) { if ( F . isDeclaration ( ) ) continue ; Changed |= runEHOnFunction ( F ) ; } } if ( DoSjLj ) { Changed = true ; if ( LongjmpF ) replaceLongjmpWithEmscriptenLongjmp ( LongjmpF , EmLongjmpF ) ; if ( SetjmpF ) for ( Function * F : SetjmpUsers ) runSjLjOnFunction ( * F ) ; } if ( ! Changed ) {

if ( ResumeF ) ResumeF -> eraseFromParent ( ) ;