<s> } SparseBitVector < > Reachable ; for ( auto II = ++ MachineBasicBlock :: reverse_iterator ( WWM ) , IE = MBB -> rend ( ) ; II != IE ; ++ II ) { addDefs ( * II , Reachable ) ; } for ( idf_iterator < MachineBasicBlock * > I = ++ idf_begin ( MBB ) , E = idf_end ( MBB ) ; I != E ; ++ I ) { for ( const MachineInstr & MI : * * I ) { addDefs ( MI , Reachable ) ; } } LiveOut &= Reachable ; bool Modified = false ; for ( unsigned Reg : LiveOut ) { WWM . addOperand ( MachineOperand :: CreateReg ( Reg , false , true ) ) ; if ( LIS ) { LIS -> removeInterval ( Reg ) ; LIS -> createAndComputeVirtRegInterval ( Reg ) ;


<s> return create<ISA_LIT>ELFStreamer ( Ctx , MAB , OS , Emitter , false , T . getArch ( ) == Triple :: thumb ) ;


<s> Type * MaskTy = C -> getType ( ) ; unsigned MaskTySize = MaskTy -> getPrimitiveSizeInBits ( ) ; ( void ) MaskTySize ; assert ( ( MaskTySize == <NUM_LIT> || MaskTySize == <NUM_LIT> || MaskTySize == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( ElSize == <NUM_LIT> || ElSize == <NUM_LIT> || ElSize == <NUM_LIT> || ElSize == <NUM_LIT> ) && <STR_LIT> ) ; SmallBitVector UndefElts ; SmallVector < uint64_t , <NUM_LIT> > RawMask ; if ( ! extractConstantMask ( C , ElSize , UndefElts , RawMask ) ) return ; unsigned NumElts = RawMask . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( UndefElts [ i ] ) { ShuffleMask . push_back ( SM_SentinelUndef ) ;


<s> printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) {


<s> static int stackSlotSize ( ) { return <NUM_LIT> ;


<s> static MachineOperand copyRegOperandAsImplicit ( const MachineOperand & Orig ) { assert ( ! Orig . isImplicit ( ) ) ;

return MachineOperand :: CreateReg ( Orig . getReg ( ) , Orig . isDef ( ) , true , Orig . isKill ( ) , Orig . isDead ( ) , Orig . isUndef ( ) , Orig . isEarlyClobber ( ) , Orig . getSubReg ( ) , Orig . isDebug ( ) , Orig . isInternalRead ( ) ) ;


<s> StringRef getPassName ( ) const override {


<s> SequenceMBBI -> collectDebugValues ( SelectDebugValues ) ; SelectDests . insert ( SequenceMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else { if ( SequenceMBBI -> hasUnmodeledSideEffects ( ) || SequenceMBBI -> mayLoadOrStore ( ) ) break ; if ( llvm :: any_of ( SequenceMBBI -> operands ( ) , [ & ] ( MachineOperand & MO ) { return MO . isReg ( ) && MO . isUse ( ) && SelectDests . count ( MO . getReg ( ) ) ; } ) ) break ; } } const TargetInstrInfo & TII = * BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * HeadMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * TailMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , IfFalseMBB ) ; F -> insert ( I , TailMBB ) ; for ( MachineInstr * DebugInstr : SelectDebugValues ) { TailMBB -> push_back ( DebugInstr -> removeFromParent ( ) ) ; } TailMBB -> splice ( TailMBB -> end ( ) , HeadMBB , std :: next ( LastSelectPseudo -> getIterator ( ) ) , HeadMBB -> end ( ) ) ; TailMBB -> transferSuccessorsAndUpdatePHIs ( HeadMBB ) ; HeadMBB -> addSuccessor ( IfFalseMBB ) ; HeadMBB -> addSuccessor ( TailMBB ) ; unsigned Opcode = getBranchOpcodeForIntCondCode ( CC ) ; BuildMI ( HeadMBB , DL , TII . get ( Opcode ) ) . addReg ( LHS ) . addReg ( RHS ) . addMBB ( TailMBB ) ; IfFalseMBB -> addSuccessor ( TailMBB ) ; auto SelectMBBI = MI . getIterator ( ) ; auto SelectEnd = std :: next ( LastSelectPseudo -> getIterator ( ) ) ; auto InsertionPoint = TailMBB -> begin ( ) ; while ( SelectMBBI != SelectEnd ) { auto Next = std :: next ( SelectMBBI ) ; if ( isSelectPseudo ( * SelectMBBI ) ) { BuildMI ( * TailMBB , InsertionPoint , SelectMBBI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( HeadMBB ) . addReg ( SelectMBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( IfFalseMBB ) ;


<s> return true ; } ; auto MatchShift = [ & ] ( int Shift ) { for ( int i = <NUM_LIT> ; i != Size - Shift ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != Shift + i ) return false ; return true ; } ; for ( int Shift = <NUM_LIT> ; Shift != Size ; ++ Shift ) if ( CheckUndefs ( Shift ) && MatchShift ( Shift ) ) return Shift ;


<s> MIB . setMemRefs ( MI -> memoperands ( ) ) ; if ( unsigned OldInstrNum = MI -> peekDebugInstrNum ( ) ) { unsigned Subreg = TRI -> getSubRegIndex ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;

unsigned NewInstrNum = MIB -> getDebugInstrNum ( * MF ) ;


<s> int LaneSize = Mask . size ( ) / <NUM_LIT> ; bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; if ( isSingleInputShuffleMask ( Mask ) ) { SmallVector < int , <NUM_LIT> > FlippedBlendMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) FlippedBlendMask . push_back ( Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ) ; unsigned PERMMask = <NUM_LIT> | <NUM_LIT> << <NUM_LIT> ; SDValue Flipped = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , V1 , DAG . getConstant ( PERMMask , DL , <STR_LIT> ) ) ; return DAG . getVectorShuffle ( VT , DL , V1 , Flipped , FlippedBlendMask ) ; }


<s> switch ( VA . getLocInfo ( ) ) { default : break ; case CCValAssign :: AExtUpper : case CCValAssign :: SExtUpper : case CCValAssign :: ZExtUpper : { unsigned ValSizeInBits = ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; unsigned Opcode = VA . getLocInfo ( ) == CCValAssign :: ZExtUpper ? <STR_LIT> : <STR_LIT> ; Val = DAG . getNode ( Opcode , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , DL , VA . getLocVT ( ) ) ) ; break ; }


<s> assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , SDLoc ( X ) , VT , X ) ; InsertDAGNode ( DAG , N , NewX ) ; X = NewX ; } SDLoc DL ( N ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> , DL , VT , X , NewSRLAmt ) ; SDValue NewSHLAmt = DAG . getConstant ( AMShiftAmt , <STR_LIT> ) ; SDValue NewSHL = DAG . getNode ( <STR_LIT> , DL , VT , NewSRL , NewSHLAmt ) ; InsertDAGNode ( DAG , N , NewSRLAmt ) ; InsertDAGNode ( DAG , N , NewSRL ) ; InsertDAGNode ( DAG , N , NewSHLAmt ) ; InsertDAGNode ( DAG , N , NewSHL ) ; DAG . ReplaceAllUsesWith ( N , NewSHL ) ; AM . Scale = <NUM_LIT> << AMShiftAmt ; AM . IndexReg = NewSRL ; return false ;


<s> RegisterSubReg Reg ( MO ) ; if ( Reg . S && Reg . S != <STR_LIT> ) return false ; if ( ! PredGPRs . count ( Reg ) ) return false ; } MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewOpc = getPredForm ( Opc ) ; if ( NewOpc == <NUM_LIT> ) { switch ( Opc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = TargetOpcode :: COPY ; break ; default : return false ; } RegisterSubReg PR = getPredRegFor ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( ! isScalarPred ( PR ) ) return false ; NumOps = <NUM_LIT> ; } MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op0 . isDef ( ) ) ; RegisterSubReg OutR ( Op0 ) ; const TargetRegisterClass * PredRC = & <STR_LIT> ; RegisterSubReg NewPR = MRI -> createVirtualRegister ( PredRC ) ; MachineInstrBuilder MIB = BuildMI ( B , MI , DL , TII -> get ( NewOpc ) , NewPR . R ) ;

for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i ) {


<s> SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ;

this -> TM = & static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ;


<s> OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( STRICT_VFCMPE ) ; OPCODE ( STRICT_VFCMPES ) ; OPCODE ( VFCMPH ) ; OPCODE ( STRICT_VFCMPH ) ; OPCODE ( STRICT_VFCMPHS ) ; OPCODE ( VFCMPHE ) ; OPCODE ( STRICT_VFCMPHE ) ; OPCODE ( STRICT_VFCMPHES ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( STRICT_VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( STRICT_VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( VSTRS_CC ) ; OPCODE ( VSTRSZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ;


<s> std :: string MemARS ( ArRn reg , ArStep step ) { return <STR_LIT> + DsmArRn ( reg ) + DsmArStep ( step ) + <STR_LIT> ;


<s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( cfun_gpr_save_slot ( i ) == SAVE_SLOT_NONE ) continue ; while ( ( ! call_really_used_regs [ save_reg_slot ] || df_regs_ever_live_p ( save_reg_slot ) || cfun_fpr_save_p ( save_reg_slot ) ) && FP_REGNO_P ( save_reg_slot ) ) save_reg_slot ++ ; if ( ! FP_REGNO_P ( save_reg_slot ) ) { for ( j = <NUM_LIT> ; j <= <NUM_LIT> ; j ++ ) if ( FP_REGNO_P ( cfun_gpr_save_slot ( j ) ) ) cfun_gpr_save_slot ( j ) = SAVE_SLOT_STACK ; break ; } cfun_gpr_save_slot ( i ) = save_reg_slot ++ ;


<s> bool hasBaseOrIndexReg ( ) const { return IndexReg . getNode ( ) != <NUM_LIT> || Base . Reg . getNode ( ) != <NUM_LIT> ;


<s> virtual void EmitARM64WinCFIPrologEnd ( ) {


<s> tls [ <NUM_LIT> ] = <NUM_LIT> ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == UNSPEC ) { char off = which == RS6000_PLTSEQ_PLT_PCREL34 ? '8' : '4' ; if ( XINT ( operands [ <NUM_LIT> ] , <NUM_LIT> ) == UNSPEC_TLSGD ) sprintf ( tls , <STR_LIT> , off , rel64 ) ; else if ( XINT ( operands [ <NUM_LIT> ] , <NUM_LIT> ) == UNSPEC_TLSLD ) sprintf ( tls , <STR_LIT> , off , rel64 ) ; } gcc_assert ( DEFAULT_ABI == ABI_ELFv2 || DEFAULT_ABI == ABI_V4 ) ; static char str [ <NUM_LIT> ] ; char off = WORDS_BIG_ENDIAN ? '2' : '4' ; const char * addend = ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; switch ( which ) { case RS6000_PLTSEQ_TOCSAVE : sprintf ( str , <STR_LIT> <STR_LIT> , TARGET_64BIT ? <STR_LIT> : <STR_LIT> , tls , rel64 ) ; break ; case RS6000_PLTSEQ_PLT16_HA : if ( DEFAULT_ABI == ABI_V4 && ! flag_pic ) sprintf ( str , <STR_LIT> <STR_LIT> , tls , off , rel64 ) ; else sprintf ( str , <STR_LIT> <STR_LIT> , tls , off , rel64 , addend ) ; break ;


<s> break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : if ( Subtarget -> hasSSE1 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : if ( Subtarget -> hasSSE2 ( ) ) { Opc = <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ;


<s> <ISA_LIT>FrameLowering :: ~ <ISA_LIT>FrameLowering ( ) {


<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , IE = MBB . end ( ) ; I != IE ; ) { MachineInstr & MI = * I ; if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) { if ( MI . getOpcode ( ) == <STR_LIT> ) NeedFence = false ; else if ( MI . getOpcode ( ) == <STR_LIT> ) NeedFence = true ; ++ I ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; unsigned OutReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned InReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned GPR3 = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc1 , Opc2 ; const unsigned OrigRegs [ ] = { OutReg , InReg , GPR3 } ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ;

MachineBasicBlock :: iterator First = I ;


<s> for ( MachineLoopInfo :: iterator It = MLI -> begin ( ) , E = MLI -> end ( ) ; It != E ; ++ It ) for ( MachineLoop * ML : depth_first ( * It ) ) NestedLoops . push_back ( ML ) ; if ( NestedLoops . size ( ) == <NUM_LIT> ) return <NUM_LIT> ; int Num = <NUM_LIT> ; for ( std :: vector < MachineLoop * > :: reverse_iterator It = NestedLoops . rbegin ( ) , E = NestedLoops . rend ( ) ; It != E ; ++ It ) { MachineLoop * ExaminedLoop = * It ; if ( ExaminedLoop -> getNumBlocks ( ) == <NUM_LIT> || Visited [ ExaminedLoop ] ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ; ExaminedLoop -> dump ( ) ; ) ; int NumBreak = mergeLoop ( ExaminedLoop ) ; if ( NumBreak == - <NUM_LIT> ) break ; Num += NumBreak ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isVector ( ) ) return LowerVectorLoad ( Op , DAG ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; SDValue Chain = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; MachineMemOperand * MMO = LD -> getMemOperand ( ) ; SDValue NewLD = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , Chain , BasePtr , <STR_LIT> , MMO ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewLD ) ;

SDValue Ops [ ] = { Result , SDValue ( NewLD . getNode ( ) , <NUM_LIT> ) } ;


<s> for ( <ISA_LIT>Instr & ISJ : insts ( ) ) { const bool RequiresSlot = <ISA_LIT>MCInstrInfo :: requiresSlot ( STI , * ISJ . ID ) ; if ( ! RequiresSlot ) ISJ . Core . setAllUnits ( ) ; }


<s> return ST -> hasPOPCNT ( ) ? PSK_FastHardware : PSK_Software ;


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget ;


<s> return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , <NUM_LIT> , <NUM_LIT> ) ) ;


<s> const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; const TargetRegisterClass * DestRC = MRI . getRegClass ( Dest . getReg ( ) ) ; const TargetRegisterClass * NewDestRC = RI . getEquivalentVGPRClass ( DestRC ) ; const TargetRegisterClass * NewDestSubRC = RI . getSubRegClass ( NewDestRC , <STR_LIT> ) ; unsigned DestSub0 = MRI . createVirtualRegister ( NewDestSubRC ) ; BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ;

unsigned DestSub1 = MRI . createVirtualRegister ( NewDestSubRC ) ;


<s> static void pdp11_option_override ( void ) {


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


<s> return new <ISA_LIT>LowerI1Copies ( ) ;


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : if ( VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'v' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ;


<s> if ( RECORD_OR_UNION_TYPE_P ( type ) ) { msize = int_size_in_bytes ( type ) ; } } return msize != <NUM_LIT> && msize != <NUM_LIT> && msize != <NUM_LIT> && msize != <NUM_LIT> ; } else if ( arg . type && int_size_in_bytes ( arg . type ) == - <NUM_LIT> ) return true ; }


<s> if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ;


<s> getBranchTarget7OpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ;

const MCExpr * Expr = MO . getExpr ( ) ;


return isVSrcB16 ( ) || isLiteralImm ( <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const char * cpu ; int i ; if ( argc < <NUM_LIT> ) return NULL ; if ( strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) ) return NULL ; implver = __builtin_alpha_implver ( ) ; amask = __builtin_alpha_amask ( ~ <NUM_LIT> ) ; cpu = NULL ; for ( i = <NUM_LIT> ; cpu_types [ i ] . cpu != NULL ; i ++ ) if ( implver == cpu_types [ i ] . implver && ( ~ amask & cpu_types [ i ] . amask ) == cpu_types [ i ] . amask ) { cpu = cpu_types [ i ] . cpu ;


<s> SDValue Res = DAG . getNode ( Opc , dl , ResVT , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , TruncVT , Res ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget . hasDQI ( ) && Subtarget . hasVLX ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> && SrcVT == <STR_LIT> ) { return DAG . getNode ( IsSigned ? <STR_LIT> : <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ) ; } return SDValue ( ) ; } assert ( ! VT . isVector ( ) ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( SrcVT ) ; if ( ! IsSigned && Subtarget . hasAVX512 ( ) ) { if ( UseSSEReg ) return Op ; if ( VT == <STR_LIT> ) return SDValue ( ) ; } if ( VT == <STR_LIT> && UseSSEReg ) { assert ( IsSigned && <STR_LIT> ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } if ( UseSSEReg && IsSigned ) return Op ; if ( SDValue V = FP_TO_INTHelper ( Op , DAG , IsSigned ) ) return V ; llvm_unreachable ( <STR_LIT> ) ;


<s> rtx sh_get_pr_initial_val ( void ) { rtx val = get_hard_reg_initial_val ( Pmode , PR_REG ) ;

return gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , val ) , UNSPEC_RA ) ;


<s> llvm :: FastISel * <STR_LIT> ( FunctionLoweringInfo & funcInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) && ! Disable<ISA_LIT>FastISel ) return new <ISA_LIT>FastISel ( funcInfo ) ;


<s> unsigned Opc = <STR_LIT> ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , imm ) ; return CurDAG -> getMachineNode ( Opc , dl , VT , TFI , imm ) ; } case <STR_LIT> : { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue Callee = Node -> getOperand ( <NUM_LIT> ) ; SDValue R20Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; if ( ( isa < GlobalAddressSDNode > ( Callee ) ) || ( isa < ExternalSymbolSDNode > ( Callee ) ) ) { SDValue GPReg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Callee , GPReg , Chain } ; SDValue Load = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops ) , <NUM_LIT> ) ; Chain = Load . getValue ( <NUM_LIT> ) ; Chain = CurDAG -> getCopyToReg ( Chain , dl , R20Reg , Load , InFlag ) ; } else Chain = CurDAG -> getCopyToReg ( Chain , dl , R20Reg , Callee , InFlag ) ; SDNode * ResNode = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , R20Reg , Chain ) ; Chain = SDValue ( ResNode , <NUM_LIT> ) ; InFlag = SDValue ( ResNode , <NUM_LIT> ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , Chain ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , InFlag ) ; return ResNode ; } } } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == NULL || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ;


<s> unsigned int size = GET_MODE_SIZE ( GET_MODE ( dest ) ) ; if ( size == <NUM_LIT> && FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( size == <NUM_LIT> ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; }


<s> Ops [ <NUM_LIT> ] = SDNodeArg ; Ops [ <NUM_LIT> ] = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getTargetConstant ( switchType , DL , <STR_LIT> ) ;

Ops [ <NUM_LIT> ] = ( SDNodeArg2 == nullptr ) ? DAG . getUNDEF ( ResultVT ) : * SDNodeArg2 ;


<s> if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) { if ( ! TFI . hasFP ( MF ) ) report_fatal_error ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ; else { const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; Register FrameReg = RegInfo -> getPtrSizedFrameRegister ( MF ) ; assert ( ( FrameReg == <STR_LIT> || FrameReg == <STR_LIT> ) && <STR_LIT> ) ;


<s> new_addr = scratch ; } break ; case REG : case SUBREG : if ( ! base_reg_operand ( addr , GET_MODE ( addr ) ) ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } break ; case PLUS : op0 = XEXP ( addr , <NUM_LIT> ) ; op1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! base_reg_operand ( op0 , Pmode ) ) rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; else if ( int_reg_operand ( op1 , Pmode ) ) { if ( ( addr_mask & RELOAD_REG_INDEXED ) == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } } else if ( mode_supports_vsx_dform_quad ( mode ) && CONST_INT_P ( op1 ) ) { if ( ( ( addr_mask & RELOAD_REG_QUAD_OFFSET ) == <NUM_LIT> ) || ! quad_address_p ( addr , mode , false ) ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } } else if ( rs6000_legitimate_offset_address_p ( mode , addr , false , true ) ) { if ( ( addr_mask & RELOAD_REG_OFFSET ) == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } } else rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; break ; case LO_SUM : op0 = XEXP ( addr , <NUM_LIT> ) ; op1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! base_reg_operand ( op0 , Pmode ) ) rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; else if ( int_reg_operand ( op1 , Pmode ) ) { if ( ( addr_mask & RELOAD_REG_INDEXED ) == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } } else if ( mode_supports_vsx_dform_quad ( mode ) ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } else if ( legitimate_lo_sum_address_p ( mode , addr , false ) ) { if ( ( addr_mask & RELOAD_REG_OFFSET ) == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( scratch , addr ) ) ; new_addr = scratch ; } } else rs6000_secondary_reload_fail ( __LINE__ , reg , mem , scratch , store_p ) ; break ; case SYMBOL_REF : case CONST :


<s> unsigned match_load_op = <NUM_LIT> ; switch ( MaskN -> getZExtValue ( ) ) { default : return ; case <NUM_LIT> : match_load_op = <STR_LIT> ; break ; case <NUM_LIT> : match_load_op = <STR_LIT> ; break ; case <NUM_LIT> : match_load_op = <STR_LIT> ; break ; } const RegisterSDNode * RegN = dyn_cast < RegisterSDNode > ( BaseV . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( ! RegN || ! Register :: isVirtualRegister ( RegN -> getReg ( ) ) ) return ; unsigned AndOpReg = RegN -> getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( AndOpReg ) << '\n' ) ; MachineBasicBlock * MBB = FuncInfo -> MBB ; MachineInstr * MII = nullptr ; for ( auto & MI : * MBB ) { for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; ++ i ) { const MachineOperand & MOP = MI . getOperand ( i ) ; if ( ! MOP . isReg ( ) || ! MOP . isDef ( ) ) continue ; Register Reg = MOP . getReg ( ) ; if ( Register :: isVirtualRegister ( Reg ) && Reg == AndOpReg ) { MII = & MI ; break ; } } } if ( MII == nullptr ) { if ( ! checkLoadDef ( AndOpReg , match_load_op ) ) return ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MII -> dump ( ) ; dbgs ( ) << '\n' ) ; unsigned PrevReg = - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < MII -> getNumOperands ( ) ; ++ i ) { const MachineOperand & MOP = MII -> getOperand ( i ) ; if ( MOP . isReg ( ) ) { if ( MOP . isDef ( ) ) continue ; PrevReg = MOP . getReg ( ) ; if ( ! Register :: isVirtualRegister ( PrevReg ) ) return ;

if ( ! checkLoadDef ( PrevReg , match_load_op ) ) return ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>16 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , true ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( has<ISA_LIT>32r6 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>R632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( has<ISA_LIT>32r6 ( ) && isFP64 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32r6FP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } if ( hasCOP3 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCOP3_32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( has<ISA_LIT>32r6 ( ) && isGP64 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r6_GP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( has<ISA_LIT>32r6 ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( hasCn<ISA_LIT> ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCn<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ;


<s> return DAG . getStore ( N -> getChain ( ) , SDLoc ( Op ) , N -> getVal ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , N -> isVolatile ( ) , N -> isNonTemporal ( ) , N -> getAlignment ( ) , N -> getAAInfo ( ) ) ; } if ( N -> getMemoryVT ( ) == <STR_LIT> ) { if ( N -> getAlignment ( ) < <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return DAG . getTruncStore ( N -> getChain ( ) , SDLoc ( Op ) , N -> getVal ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> isVolatile ( ) , N -> isNonTemporal ( ) , N -> getAlignment ( ) , N -> getAAInfo ( ) ) ; } if ( N -> getMemoryVT ( ) == <STR_LIT> ) return DAG . getTruncStore ( N -> getChain ( ) , SDLoc ( Op ) , N -> getVal ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> isVolatile ( ) , N -> isNonTemporal ( ) , N -> getAlignment ( ) , N -> getAAInfo ( ) ) ;


<s> } for ( unsigned SUNum : DAG -> BottomUpIndex2SU ) { SUnit * SU = & DAG -> SUnits [ SUNum ] ; unsigned color = CurrentColoring [ SU -> NodeNum ] ; std :: set < unsigned > SUColors ; if ( CurrentColoring [ SU -> NodeNum ] <= ( int ) DAGSize ) continue ; if ( ColorCount [ color ] > <NUM_LIT> ) continue ; for ( SDep & SuccDep : SU -> Succs ) { SUnit * Succ = SuccDep . getSUnit ( ) ; if ( SuccDep . isWeak ( ) || Succ -> NodeNum >= DAGSize ) continue ; SUColors . insert ( CurrentColoring [ Succ -> NodeNum ] ) ; } if ( SUColors . size ( ) == <NUM_LIT> && * SUColors . begin ( ) != color ) { -- ColorCount [ color ] ;

CurrentColoring [ SU -> NodeNum ] = * SUColors . begin ( ) ;


<s> return ( Subtarget . getProcFamily ( ) == <ISA_LIT>Subtarget :: ExynosM1 || MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; return ( Subtarget . getProcFamily ( ) == <ISA_LIT>Subtarget :: ExynosM1 && <STR_LIT> ( Imm ) < <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm8Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; int32_t OffImm = ( int32_t ) MO2 . getImm ( ) ; bool isSub = OffImm < <NUM_LIT> ; if ( OffImm == INT32_MIN ) OffImm = <NUM_LIT> ; if ( isSub ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << - OffImm << markup ( <STR_LIT> ) ; } else if ( AlwaysPrintImm0 || OffImm > <NUM_LIT> ) {

O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << OffImm << markup ( <STR_LIT> ) ;


<s> return false ; case <STR_LIT> : if ( VT . getVectorNumElements ( ) > MinVLen ) return false ; MinVLen /= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget . hasStdExtZfh ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasStdExtF ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasStdExtD ( ) ) return false ; break ; } unsigned LMul = divideCeil ( VT . getSizeInBits ( ) , MinVLen ) ;

if ( LMul > Subtarget . getMaxLMULForFixedLengthVectors ( ) ) return false ;


<s> BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_OR_B64 ) , Dst ) . addReg ( Vcc ) . addReg ( Src ) ; MI . eraseFromParent ( ) ;


<s> SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget . hasSSE3 ( ) && shouldUseHorizontalOp ( true , DAG , Subtarget ) ) {

Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ;


<s> static bool needDataTypeAsOperand ( StringRef Mnemonic , SlotParser Slot , const FeatureBitset & Features ) {

if ( Mnemonic . startswith_lower ( <STR_LIT> ) ) return false ;


<s> unsigned Opcode = MI -> getOpcode ( ) ; return STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ;


<s> if ( ! TARGET_ZVECTOR ) return NULL ; if ( ! VECTOR_TYPE_P ( type1 ) || ! VECTOR_TYPE_P ( type2 ) ) return NULL ; bool1_p = s390_vector_bool_type_p ( type1 ) ; bool2_p = s390_vector_bool_type_p ( type2 ) ; if ( ! bool1_p && ! bool2_p && TYPE_UNSIGNED ( type1 ) != TYPE_UNSIGNED ( type2 ) ) return N_ ( <STR_LIT> ) ; plusminus_p = ( op == PLUS_EXPR || op == MINUS_EXPR ) ; muldiv_p = ( op == MULT_EXPR || op == RDIV_EXPR || op == TRUNC_DIV_EXPR || op == CEIL_DIV_EXPR || op == FLOOR_DIV_EXPR || op == ROUND_DIV_EXPR ) ;

compare_p = ( op == LT_EXPR || op == LE_EXPR || op == GT_EXPR || op == GE_EXPR || op == EQ_EXPR || op == NE_EXPR ) ;


<s> <ISA_LIT>PromoteAlloca ( ) : FunctionPass ( ID ) {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << '\n' ) ; ValueToValueMapTy dummy ; Function * NewF = CloneFunction ( & F , dummy ) ; setFeatures ( * NewF , NewFeatures ) ;


<s> EVT OldVT = N -> getValueType ( <NUM_LIT> ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ; MemSDNode * MN = cast < MemSDNode > ( N ) ; unsigned AS = MN -> getAddressSpace ( ) ;

if ( OldSize >= <NUM_LIT> && NewSize < <NUM_LIT> && MN -> getAlignment ( ) >= <NUM_LIT> && ( AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT || ( isa < LoadSDNode > ( N ) && AS == <ISA_LIT>AS :: GLOBAL_ADDRESS && MN -> isInvariant ( ) ) ) && <ISA_LIT>InstrInfo :: isUniformMMO ( MN -> getMemOperand ( ) ) ) return false ;


<s> unsigned Register = ( Insn >> <NUM_LIT> ) & <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Register ] ) ) ;

unsigned Offset = ( Insn & <NUM_LIT> ) ;


<s> static DecodeStatus DecodePPR_3bRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; return DecodePPRRegisterClass ( Inst , RegNo , Addr , Decoder ) ;


<s> } ScheduleQ . push ( & Fn . front ( ) ) ; while ( ! ScheduleQ . empty ( ) ) { MachineBasicBlock * MBB = ScheduleQ . front ( ) ; ScheduleQ . pop ( ) ; if ( Scheduled . count ( MBB ) ) continue ; MachineSuperBlock * MSB ; std :: auto_ptr < MachineSuperBlock > ownedMSB ; EntryMSBMap :: iterator it ; if ( ( it = Entries . find ( MBB ) ) != Entries . end ( ) ) { MSB = it -> second ; } else { if ( ! MBB -> size ( ) ) continue ; ownedMSB = std :: auto_ptr < MachineSuperBlock > ( new MachineSuperBlock ( Fn , * MBB ) ) ; MSB = ownedMSB . get ( ) ; } assignPHIs ( & State , MBB ) ; Scheduler -> Run ( MSB ) ; Scheduled . insert ( MSB -> begin ( ) , MSB -> end ( ) ) ; sumCycles += Scheduler -> getCycles ( ) ; for ( MachineSuperBlock :: iterator MBBI = MSB -> begin ( ) , MBBE = MSB -> end ( ) ; MBBI != MBBE ; ++ MBBI ) { for ( MachineBasicBlock :: succ_iterator SI = ( * MBBI ) -> succ_begin ( ) , SE = ( * MBBI ) -> succ_end ( ) ; SI != SE ; ++ SI ) { MachineBasicBlock * Succ = * SI ; ScheduleQ . push ( Succ ) ; } } } MFI -> setScheduledCyclesPre ( sumCycles ) ;


<s> if ( TT . isOSDarwin ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( Options . MCOptions . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>TargetMachine :: <ISA_LIT>_ABI_ELFv1 ; else if ( Options . MCOptions . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>TargetMachine :: <ISA_LIT>_ABI_ELFv2 ; assert ( Options . MCOptions . getABIName ( ) . empty ( ) && <STR_LIT> ) ; if ( TT . isMacOSX ( ) ) return <ISA_LIT>TargetMachine :: <ISA_LIT>_ABI_UNKNOWN ; switch ( TT . getArch ( ) ) { case Triple :: ppc64le :


<s> bool <ISA_LIT>DeadRegisterDefinitions :: usesFrameIndex ( const MachineInstr & MI ) { for ( const MachineOperand & Op : MI . uses ( ) ) if ( Op . isFI ( ) ) return true ;


<s> bool <ISA_LIT>InstrInfo :: isVectorOnly ( const MachineInstr & MI ) const {

return isVectorOnly ( MI . getOpcode ( ) ) ;


<s> <ISA_LIT>PLTA ( SectionData & pParent ) : PLT :: Entry < sizeof ( PLTA ) > ( pParent ) {


<s> while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> && I -> getOperand ( PIdx ) . getImm ( ) != <STR_LIT> ) return true ; } return false ; } int PIdx = MI . findFirstPredOperandIdx ( ) ; return PIdx != - <NUM_LIT> && MI . getOperand ( PIdx ) . getImm ( ) != <STR_LIT> ;


<s> Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; bool IsAllOnes = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const Constant * C = IsAllOnes ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; break ; } default : { unsigned NumOps = LoadMI -> getDesc ( ) . getNumOperands ( ) ;

for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) MOs . push_back ( LoadMI -> getOperand ( i ) ) ;


<s> <ISA_LIT>64GOT :: <ISA_LIT>64GOT ( LDSection & pSection ) : <ISA_LIT>GOT ( pSection ) {


<s> case EQ_I64 : Def -> setDesc ( TII . get ( NE_I64 ) ) ; Inverted = true ; break ; case NE_I64 : Def -> setDesc ( TII . get ( EQ_I64 ) ) ; Inverted = true ; break ; case GT_S_I64 : Def -> setDesc ( TII . get ( LE_S_I64 ) ) ; Inverted = true ; break ; case GE_S_I64 : Def -> setDesc ( TII . get ( LT_S_I64 ) ) ; Inverted = true ; break ; case LT_S_I64 : Def -> setDesc ( TII . get ( GE_S_I64 ) ) ; Inverted = true ; break ; case LE_S_I64 : Def -> setDesc ( TII . get ( GT_S_I64 ) ) ; Inverted = true ; break ; case GT_U_I64 : Def -> setDesc ( TII . get ( LE_U_I64 ) ) ; Inverted = true ; break ; case GE_U_I64 : Def -> setDesc ( TII . get ( LT_U_I64 ) ) ; Inverted = true ; break ; case LT_U_I64 : Def -> setDesc ( TII . get ( GE_U_I64 ) ) ; Inverted = true ; break ; case LE_U_I64 : Def -> setDesc ( TII . get ( GT_U_I64 ) ) ; Inverted = true ; break ; case EQ_F32 : Def -> setDesc ( TII . get ( NE_F32 ) ) ; Inverted = true ; break ; case NE_F32 : Def -> setDesc ( TII . get ( EQ_F32 ) ) ; Inverted = true ; break ; case EQ_F64 : Def -> setDesc ( TII . get ( NE_F64 ) ) ; Inverted = true ; break ; case NE_F64 : Def -> setDesc ( TII . get ( EQ_F64 ) ) ; Inverted = true ; break ; default : break ; } } if ( ! Inverted ) { unsigned ZeroReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MFI . stackifyVReg ( ZeroReg ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ZeroReg ) . addImm ( <NUM_LIT> ) ; unsigned Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; MFI . stackifyVReg ( Tmp ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Tmp ) . addReg ( Cond ) . addReg ( ZeroReg ) ; Cond = Tmp ; Inverted = true ; } assert ( Inverted ) ;

BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( Cond ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ;


<s> bool hasFMA4 ( ) const { return HasFMA4 && ! HasFMA ;


ParseInstruction ( StringRef Name , SMLoc NameLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands ) {


<s> tree s = build_string ( strlen ( reg_names [ CA_REGNO ] ) , reg_names [ CA_REGNO ] ) ;

return tree_cons ( NULL_TREE , s , clobbers ) ;


<s> break ; case fixup_<ISA_LIT>_B7_PCREL_X : case fixup_<ISA_LIT>_B9_PCREL_X : case fixup_<ISA_LIT>_B13_PCREL_X : case fixup_<ISA_LIT>_B15_PCREL_X : case fixup_<ISA_LIT>_B22_PCREL_X : Value &= <NUM_LIT> ; break ; case fixup_<ISA_LIT>_B32_PCREL_X : case fixup_<ISA_LIT>_GD_PLT_B32_PCREL_X : case fixup_<ISA_LIT>_LD_PLT_B32_PCREL_X : Value >>= <NUM_LIT> ; break ;


<s> U = I ; } } else if ( const auto * C = dyn_cast < ConstantExpr > ( V ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : return computeCallAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: IntToPtr : if ( TLI . getValueType ( U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( ) ) return computeCallAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return computeCallAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ;


<s> return DAG . getNode ( <STR_LIT> , dl , VT , V1 , DAG . getConstant ( Lane , <STR_LIT> ) ) ; } SmallVector < int , <NUM_LIT> > NV1Elt ; SmallVector < int , <NUM_LIT> > N1Index ; SmallVector < int , <NUM_LIT> > NV2Elt ; SmallVector < int , <NUM_LIT> > N2Index ; int Length = ShuffleMask . size ( ) ; int V1EltNum = V1 . getValueType ( ) . getVectorNumElements ( ) ; for ( int I = <NUM_LIT> ; I != Length ; ++ I ) { if ( ShuffleMask [ I ] != I ) { NV1Elt . push_back ( ShuffleMask [ I ] ) ; N1Index . push_back ( I ) ; } } for ( int I = <NUM_LIT> ; I != Length ; ++ I ) { if ( ShuffleMask [ I ] != ( I + V1EltNum ) ) { NV2Elt . push_back ( ShuffleMask [ I ] ) ; N2Index . push_back ( I ) ; } } SDValue InsV = V1 ; SmallVector < int , <NUM_LIT> > InsMasks = NV1Elt ; SmallVector < int , <NUM_LIT> > InsIndex = N1Index ; if ( ( int ) NV1Elt . size ( ) != Length || ( int ) NV2Elt . size ( ) != Length ) { if ( NV1Elt . size ( ) > NV2Elt . size ( ) ) { InsV = V2 ; InsMasks = NV2Elt ; InsIndex = N2Index ;


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Immed ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ShVal ) ; } , } } ;


<s> void EmitRawByte ( unsigned char C , unsigned & CurByte , raw_ostream & OS ) const { OS << ( char ) C ;


<s> explicit <ISA_LIT>BufferPseudoSourceValue ( const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>PseudoSourceValue ( PSVBuffer , TM ) {


<s> unsigned FrameSize = MFI . getStackSize ( ) ; if ( FrameSize & ~ <NUM_LIT> ) return true ; for ( unsigned i = <NUM_LIT> ; i < Info . size ( ) ; i ++ ) { int FrIdx = Info [ i ] . getFrameIdx ( ) ; unsigned Reg = Info [ i ] . getReg ( ) ; const TargetRegisterClass * RC = getMinimalPhysRegClass ( Reg ) ; unsigned Opcode = InstrInfo -> getStoreOpcodeForSpill ( RC ) ; if ( ! MFI . isFixedObjectIndex ( FrIdx ) ) { if ( offsetMinAlignForOpcode ( Opcode ) > <NUM_LIT> ) return true ; } if ( InstrInfo -> isXFormMemOp ( Opcode ) ) return true ; } return false ;


<s> else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . MCSym ) { assert ( ! AM . Disp && <STR_LIT> ) ; assert ( AM . SymbolFlags == <NUM_LIT> && <STR_LIT> ) ; Disp = CurDAG -> getMCSymbol ( AM . MCSym , <STR_LIT> ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ;

} else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ;


<s> case RIT_<ISA_LIT>_64_GOT : Expr = MCSymbolRefExpr :: Create ( Sym , isPCRel ? MCSymbolRefExpr :: VK_GOTPCREL : MCSymbolRefExpr :: VK_GOT , Ctx ) ; break ; case RIT_<ISA_LIT>_64_Subtractor : { RelocationRef RelNext ; Obj -> getRelocationNext ( Rel . getRawDataRefImpl ( ) , RelNext ) ; RelocationEntry RENext = Obj -> getRelocation ( RelNext . getRawDataRefImpl ( ) ) ; unsigned RType = Obj -> getAnyRelocationType ( RENext ) ; if ( RType != RIT_<ISA_LIT>_64_Unsigned ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; const MCExpr * LHS = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; symbol_iterator RSymI = RelNext . getSymbol ( ) ; uint64_t RSymAddr ; RSymI -> getAddress ( RSymAddr ) ; StringRef RSymName ; RSymI -> getName ( RSymName ) ; MCSymbol * RSym = Ctx . GetOrCreateSymbol ( RSymName ) ; if ( RSym -> isVariable ( ) == false ) RSym -> setVariableValue ( MCConstantExpr :: Create ( RSymAddr , Ctx ) ) ;

const MCExpr * RHS = MCSymbolRefExpr :: Create ( RSym , Ctx ) ;


<s> DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ;

Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) {


unsigned xMaxDisp = ConstantIslandsSmallOffset ? ConstantIslandsSmallOffset : MaxDisp ;


<s> SmallSet < unsigned , <NUM_LIT> > AddedRegPressure ; while ( ++ I != E ) { if ( I -> isDebugInstr ( ) || MemOps . count ( & * I ) ) continue ; if ( I -> isCall ( ) || I -> isTerminator ( ) || I -> hasUnmodeledSideEffects ( ) ) return false ;

if ( I -> mayStore ( ) || ( ! isLd && I -> mayLoad ( ) ) ) for ( MachineInstr * MemOp : MemOps ) if ( I -> mayAlias ( AA , * MemOp , false ) ) return false ;


<s> BSSSectionLarge = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; DataSection = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ; DataSectionLarge = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ;

DataRelROSection = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION ) ;


<s> if ( Imm == <NUM_LIT> || Imm == Mask || <STR_LIT> ( Imm & Mask , Size ) ) return false ; unsigned EltSize = Size ; uint64_t DemandedBits = Demanded . getZExtValue ( ) ; Imm &= DemandedBits ; while ( true ) { uint64_t NonDemandedBits = ~ DemandedBits ; uint64_t InvertedImm = ~ Imm & DemandedBits ; uint64_t RotatedImm = ( ( InvertedImm << <NUM_LIT> ) | ( InvertedImm >> ( EltSize - <NUM_LIT> ) & <NUM_LIT> ) ) & NonDemandedBits ; uint64_t Sum = RotatedImm + NonDemandedBits ; bool Carry = NonDemandedBits & ~ Sum & ( <NUM_LIT> << ( EltSize - <NUM_LIT> ) ) ; uint64_t Ones = ( Sum + Carry ) & NonDemandedBits ; NewImm = ( Imm | Ones ) & Mask ; if ( isShiftedMask_64 ( NewImm ) || isShiftedMask_64 ( ~ ( NewImm | ~ Mask ) ) ) break ; if ( EltSize == <NUM_LIT> ) return false ; EltSize /= <NUM_LIT> ; Mask >>= EltSize ; uint64_t Hi = Imm >> EltSize , DemandedBitsHi = DemandedBits >> EltSize ; if ( ( ( Imm ^ Hi ) & ( DemandedBits & DemandedBitsHi ) & Mask ) != <NUM_LIT> ) return false ; Imm |= Hi ; DemandedBits |= DemandedBitsHi ; } ++ NumOptimizedImms ; while ( EltSize < Size ) { NewImm |= NewImm << EltSize ; EltSize *= <NUM_LIT> ; } ( void ) OldImm ; assert ( ( ( OldImm ^ NewImm ) & Demanded . getZExtValue ( ) ) == <NUM_LIT> && <STR_LIT> ) ; assert ( OldImm != NewImm && <STR_LIT> ) ;


<s> DenseMap < unsigned , unsigned > :: const_iterator I = MLxEntryMap . find ( Opcode ) ; if ( I == MLxEntryMap . end ( ) ) return false ;

const <ISA_LIT>_MLxEntry & Entry = <ISA_LIT>_MLxTable [ I -> second ] ;


<s> bool single_dest_per_chain ( const rtx & t ATTRIBUTE_UNUSED , insn_info_list_t * v , void * arg ATTRIBUTE_UNUSED ) { for ( int i = v -> length ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { tag_insn_info * insn_info = ( * v ) [ i ] ; for ( int j = v -> length ( ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) { if ( in_same_chain ( insn_info -> insn , ( * v ) [ j ] -> insn , REGNO ( insn_info -> dest ) ) ) { v -> ordered_remove ( j ) ; i = v -> length ( ) ; break ; } }


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ;


<s> if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } return false ;


<s> return ( vector unsigned short ) __builtin_altivec_vadduhm ( ( vector signed short ) a1 , ( vector signed short ) a2 ) ;


<s> Register CopyReg = MRI -> createVirtualRegister ( BoolRC ) ; MachineInstr * CopyExec = BuildMI ( MBB , Start , DL , TII -> get ( <STR_LIT> ) , CopyReg ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; Register SaveReg = ExecModified ? MRI -> createVirtualRegister ( BoolRC ) : DstReg ; MachineInstr * OrSaveExec = BuildMI ( MBB , Start , DL , TII -> get ( OrSaveExecOpc ) , SaveReg ) . addReg ( CopyReg ) ; MachineBasicBlock * DestBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: iterator ElsePt ( MI ) ; if ( ExecModified ) {

MachineInstr * And = BuildMI ( MBB , ElsePt , DL , TII -> get ( AndOpc ) , DstReg ) . addReg ( Exec ) . addReg ( SaveReg ) ;


<s> const Value * MO = getMemoryInstrPtr ( Inst ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MO << '\n' ) ;


<s> bool iss6_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false , false ) ;


<s> unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , <STR_LIT> , DestReg , SrcReg ) ;

NewMI -> getOperand ( getOperandIdx ( * NewMI , <STR_LIT> :: src0 ) ) . setIsKill ( KillSrc ) ;


<s> assert ( ! ABI . IsCheriPureCap ( ) ) ; assert ( ! Ty . isFatPointer ( ) ) ; SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty , IsForTls ) , getTargetNode ( N , Ty , DAG , Flag ) ) ; return DAG . getLoad ( Ty , DL , Chain , Tgt , PtrInfo ) ;


<s> static inline struct bpf_sock * bpf_sk_lookup_tcp ( void * ctx , struct bpf_sock_tuple * tuple , int size , unsigned long long netns_id , unsigned long long flags ) {

return ( struct bpf_sock * ) __builtin_bpf_helper_sk_lookup_tcp ( ctx , ( void * ) tuple , size , netns_id , flags ) ;


<s> char * include_dir ; if ( msp430_devices_csv_loc ) include_dir = xstrdup ( msp430_devices_csv_loc ) ; else if ( msp430_check_env_var_for_devices ( & include_dir ) ) return ; include_dir = msp430_dirname ( include_dir ) ; include_dir = update_path ( include_dir , <STR_LIT> ) ; add_path ( include_dir , INC_SYSTEM , false , false ) ;


<s> OperandMatchResultTy ResTy = parseAnyRegister ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; const MCExpr * Expr = nullptr ; if ( Parser . parseExpression ( Expr ) ) { return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( Expr , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ;


<s> return ( __m256i ) __builtin_ia32_punpckhqdq256 ( ( __v4di ) __A , ( __v4di ) __B ) ;


<s> NextMBBI = std :: next ( MBBI ) ; if ( MI . isReturn ( ) || isIndirectBranchOpcode ( MI . getOpcode ( ) ) ) { assert ( MI . isTerminator ( ) ) ; insertSpeculationBarrier ( ST , MBB , std :: next ( MBBI ) , MI . getDebugLoc ( ) ) ; Modified = true ; } } return Modified ;


<s> insn -> threeByteEscape = <NUM_LIT> ; insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vexSize == <NUM_LIT> ) { insn -> twoByteEscape = <NUM_LIT> ; insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; insn -> twoByteEscape = current ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; insn -> threeByteEscape = current ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_38 ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; insn -> threeByteEscape = current ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_3A ; } else { dbgprintf ( insn , <STR_LIT> ) ; insn -> opcodeType = TWOBYTE ; }


<s> clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoVirt ( ) ; Parser . Lex ( ) ;


<s> SMLoc S = getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> unsigned OffsetOperandNo = getOffsetONFromFION ( * MI , FIOperandNum ) ; Offset += MI -> getOperand ( OffsetOperandNo ) . getImm ( ) ;

return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == TargetOpcode :: STACKMAP || MI -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || ( isInt < <NUM_LIT> > ( Offset ) && ( Offset % offsetMinAlign ( * MI ) ) == <NUM_LIT> ) ;


<s> MachineInstr * MI = & * MII ; LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; unsigned Opcode = MI -> getOpcode ( ) ; DenseMap < unsigned , unsigned > :: iterator OPI = ReduceOpcodeMap . find ( Opcode ) ; if ( OPI != ReduceOpcodeMap . end ( ) ) { const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) { if ( ReduceSpecial ( MBB , MI , Entry , LiveCPSR ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR ) ) {


<s> Is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ;


<s> assert ( getGeneration ( ) <= NORTHERN_ISLANDS ) ;


<s> unsigned getLgkmcntBitMask ( const IsaVersion & Version ) { return ( <NUM_LIT> << getLgkmcntBitWidth ( Version . Major ) ) - <NUM_LIT> ;


<s> int64_t getImm ( ) { return Imm + IC . execute ( ) ;


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { LLVM_DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ;

TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


<s> static __inline qword si_lqr ( unsigned int imm ) {

return ( ( qword ) ( vec_ld ( <NUM_LIT> , ( vector unsigned char * ) ( imm ) ) ) ) ;


if ( mayBeNewStore ( MI2 ) ) if ( MI2 -> getOpcode ( ) == <STR_LIT> ) if ( MI1 -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI2 -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return true ;


<s> } auto * A = dyn_cast < Argument > ( V ) ; auto * I = dyn_cast < Instruction > ( V ) ; assert ( ( A || I ) && <STR_LIT> ) ; auto InstPt = A ? & * A -> getParent ( ) -> getEntryBlock ( ) . begin ( ) : I -> getNextNode ( ) ; return new ZExtInst ( V , IntTy , <STR_LIT> , InstPt ) ;


<s> return new <ISA_LIT>InstPrinter ( TM , MAI , SyntaxVariant ) ;


<s> return __builtin_mve_vrndnq_fv4sf ( __a ) ;


<s> <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; SmallString < <NUM_LIT> > SymbolName ; getNameWithPrefix ( SymbolName , MF -> getFunction ( ) ) , TS -> Emit<ISA_LIT>SymbolType ( SymbolName , ELF :: STT_<ISA_LIT>_HSA_KERNEL ) ; } AsmPrinter :: EmitFunctionEntryLabel ( ) ;


<s> SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isInteger ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; RxSBGOperands RISBG ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) ) ; unsigned Count = <NUM_LIT> ; while ( expandRxSBG ( RISBG ) ) if ( RISBG . Input . getOpcode ( ) != <STR_LIT> && RISBG . Input . getOpcode ( ) != <STR_LIT> ) Count += <NUM_LIT> ; if ( Count == <NUM_LIT> ) return false ; if ( Count == <NUM_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ; if ( RISBG . Rotate == <NUM_LIT> ) { bool PreferAnd = false ; if ( VT == <STR_LIT> ) PreferAnd = true ; else if ( RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || RISBG . Mask == <NUM_LIT> || <STR_LIT> ( ~ RISBG . Mask ) || <STR_LIT> ( ~ RISBG . Mask ) ) PreferAnd = true ; else if ( auto * Load = dyn_cast < LoadSDNode > ( RISBG . Input ) ) { if ( Load -> getMemoryVT ( ) == <STR_LIT> && ( Load -> getExtensionType ( ) == <STR_LIT> || Load -> getExtensionType ( ) == <STR_LIT> ) && RISBG . Mask == <NUM_LIT> && Subtarget -> hasLoadAndZeroRightmostByte ( ) ) PreferAnd = true ; } if ( PreferAnd ) { SDValue In = convertTo ( DL , VT , RISBG . Input ) ; SDValue Mask = CurDAG -> getConstant ( RISBG . Mask , DL , VT ) ; SDValue New = CurDAG -> getNode ( <STR_LIT> , DL , VT , In , Mask ) ; if ( N != New . getNode ( ) ) { insertDAGNode ( CurDAG , N , Mask ) ; insertDAGNode ( CurDAG , N , New ) ; ReplaceNode ( N , New . getNode ( ) ) ; N = New . getNode ( ) ; } SelectCode ( N ) ; return true ; } } unsigned Opcode = <STR_LIT> ; if ( Subtarget -> hasMiscellaneousExtensions ( ) ) Opcode = <STR_LIT> ; EVT OpcodeVT = <STR_LIT> ; if ( VT == <STR_LIT> && Subtarget -> hasHighWord ( ) ) {


<s> emitAuipccInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI , <STR_LIT> , IDLoc , Out ) ;


<s> <ISA_LIT>AsmBackend ( Triple :: OSType OSType ) : MCAsmBackend ( ) , OSType ( OSType ) {


<s> default : return Op ; case <STR_LIT> : if ( ( C -> getZExtValue ( ) >> Bit ) & <NUM_LIT> ) return getTestBitOperand ( Op -> getOperand ( <NUM_LIT> ) , Bit , Invert , DAG ) ; return Op ; case <STR_LIT> : if ( C -> getZExtValue ( ) <= Bit && ( Bit - C -> getZExtValue ( ) ) < Op -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ) { Bit = Bit - C -> getZExtValue ( ) ; return getTestBitOperand ( Op -> getOperand ( <NUM_LIT> ) , Bit , Invert , DAG ) ; } return Op ; case <STR_LIT> :


<s> bool AMDGPUTargetLowering :: isFAbsFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ;


<s> SDValue <ISA_LIT>cc ; SDValue NewCmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; Res = DAG . getNode ( <STR_LIT> , dl , VT , LHS , FalseVal , <ISA_LIT>cc , N -> getOperand ( <NUM_LIT> ) , NewCmp ) ; } if ( CC == <STR_LIT> && LHS . getOpcode ( ) == <STR_LIT> && LHS -> hasOneUse ( ) ) { auto * LHS0C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * LHS1C = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ( LHS0C && LHS0C -> getZExtValue ( ) == <NUM_LIT> ) && ( LHS1C && LHS1C -> getZExtValue ( ) == <NUM_LIT> ) && ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) ) ; } } if ( Res . getNode ( ) ) { KnownBits Known ; DAG . computeKnownBits ( SDValue ( N , <NUM_LIT> ) , Known ) ; if ( Known . Zero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( Known . Zero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ; else if ( Known . Zero == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getValueType ( <STR_LIT> ) ) ;


<s> static DecodeStatus DecodeStoreInt ( MCInst & Inst , unsigned insn , uint64_t Address , const MCDisassembler * Decoder ) { return DecodeMem ( Inst , insn , Address , Decoder , false , DecodeIntRegsRegisterClass ) ;


<s> static unsigned ix86_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = <NUM_LIT> ; if ( ! TARGET_ADJUST_UNROLL ) return nunroll ; subrtx_iterator :: array_type array ; bbs = get_loop_body ( loop ) ; for ( i = <NUM_LIT> ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn ) ) FOR_EACH_SUBRTX ( iter , array , insn , NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) { machine_mode mode = GET_MODE ( x ) ; unsigned int n_words = GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ; if ( n_words > <NUM_LIT> ) mem_count += <NUM_LIT> ; else mem_count += <NUM_LIT> ; }


<s> bool function_arg_regno_p ( int n ) { int i ; for ( i = <NUM_LIT> ; arg_regs [ i ] != - <NUM_LIT> ; i ++ ) if ( n == arg_regs [ i ] ) return true ; return false ;


<s> static bool mips_truly_noop_truncation ( poly_uint64 outprec , poly_uint64 inprec ) {

return ! TARGET_64BIT || inprec <= <NUM_LIT> || outprec > <NUM_LIT> ;


<s> return ( GET_MODE_ALIGNMENT ( mode ) > PARM_BOUNDARY || ( type && TYPE_ALIGN ( type ) > PARM_BOUNDARY ) ) ;


<s> Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , <STR_LIT> ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; }

Type * Tys [ ] = { Addr -> getType ( ) } ;


<s> gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( LABEL_REF_P ( addr ) || GET_CODE ( addr ) == PLUS ) { int insns = REG_NREGS ( reg ) / <NUM_LIT> ; return insns * <NUM_LIT> ; } else return <NUM_LIT> ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( F64Val -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue From [ ] = { SDValue ( N , <NUM_LIT> ) , SDValue ( N , <NUM_LIT> ) } ; SDValue To [ ] = { F64Val . getOperand ( <NUM_LIT> ) , F64Val . getOperand ( <NUM_LIT> ) } ; CurDAG -> ReplaceAllUsesOfValuesWith ( From , To , <NUM_LIT> ) ; } }


<s> void <ISA_LIT>CodeEmitter :: emitExternalSymbolAddress ( const char * ES , unsigned Reloc ) const { MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , ES , <NUM_LIT> , <NUM_LIT> , false ) ) ;


<s> } for ( ablocks :: iterator i ( Blocks . begin ( ) ) , ie ( Blocks . end ( ) ) ; i != ie ; i ++ ) { delete * i ;


<s> getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } }


<s> NeedTruncation = true ; ArithOp = Arith ; } } } switch ( ArithOp . getOpcode ( ) ) { case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) goto default_case ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( ArithOp . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ) { if ( C -> isOne ( ) && ! Subtarget . slowIncDec ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> isAllOnesValue ( ) && ! Subtarget . slowIncDec ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) && Op -> hasOneUse ( ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) && ! hasNonFlagsUse ( Op ) ) { EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt >= BitWidth ) break ; APInt Mask = ArithOp . getOpcode ( ) == <STR_LIT> ? APInt :: getHighBitsSet ( BitWidth , BitWidth - ShAmt ) : APInt :: getLowBitsSet ( BitWidth , BitWidth - ShAmt ) ; if ( ! Mask . isSignedIntN ( <NUM_LIT> ) ) break ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , dl , VT ) ) ; DAG . ReplaceAllUsesWith ( Op , New ) ; Op = New ; } break ; case <STR_LIT> : if ( ! hasNonFlagsUse ( Op ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;


<s> unsigned <ISA_LIT>ELFObjectWriter :: getEFlags ( ) const {

return ELF :: EF_<ISA_LIT>_EABIMASK & DefaultEABIVersion ;


<s> SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; for ( const auto & OrigArg : OrigArgs ) { if ( OrigArg . Flags . isByVal ( ) ) return false ; if ( OrigArg . Regs . size ( ) > <NUM_LIT> ) return false ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildUnmerge ( Regs , OrigArg . Regs [ <NUM_LIT> ] ) ; } ) ) return false ; } OutgoingValueHandler Handler ( MIRBuilder , MRI , MIB , CC_<ISA_LIT> ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; bool IsFixed = OrigArgs . empty ( ) ? true : OrigArgs . back ( ) . IsFixed ; if ( STI . is64Bit ( ) && ! IsFixed && ! STI . isCallingConvWin64 ( CallConv ) ) { MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( <STR_LIT> ) . addImm ( Handler . getNumXmmRegs ( ) ) ; MIB . addUse ( <STR_LIT> , RegState :: Implicit ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee , <NUM_LIT> ) ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( OrigRet . Regs . size ( ) > <NUM_LIT> ) return false ; SplitArgs . clear ( ) ; SmallVector < Register , <NUM_LIT> > NewRegs ;

if ( ! splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) {


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count % <NUM_LIT> ) ; Count /= <NUM_LIT> ; const uint32_t Encoded_S_NOP_0 = <NUM_LIT> ;

for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) <STR_LIT> :: write < uint32_t > ( OS , Encoded_S_NOP_0 , Endian ) ;


<s> else return <STR_LIT> ; case LT : if ( cc_prev_status . flags & CC_OVERFLOW_UNUSABLE ) return <STR_LIT> ; else return <STR_LIT> ; case GEU : return <STR_LIT> ; case LTU : return <STR_LIT> ;


<s> unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; auto PState = <STR_LIT> ( Val ) ; if ( PState && PState -> haveFeatures ( STI . getFeatureBits ( ) ) ) O << PState -> Name ; else O << <STR_LIT> << formatImm ( Val ) ;


<s> const <ISA_LIT>ABIInfo & <ISA_LIT>Subtarget :: getABI ( ) const { return TM . getABI ( ) ;


<s> if ( G1 -> requiresFixup ( ) != G2 -> requiresFixup ( ) ) return G1 -> requiresFixup ( ) > G2 -> requiresFixup ( ) ; assert ( ( G1 == G2 || ( G1 -> startsBefore ( G2 ) ^ G2 -> startsBefore ( G1 ) ) ) && <STR_LIT> ) ; return G1 -> startsBefore ( G2 ) ; } ) ; Color PreferredColor = Parity < <NUM_LIT> ? Color :: Even : Color :: Odd ; while ( Chain * G = getAndEraseNext ( PreferredColor , GV ) ) { Color C = PreferredColor ;

if ( Parity == <NUM_LIT> ) C = G -> getPreferredColor ( ) ;


<s> Register ZReg = ZRegTable [ Idx ] ; unsigned Opc = OpcTable [ Idx ] ; auto CmpMI = MIB . buildInstr ( Opc , { ZReg } , { LHS . getReg ( ) } ) ; for ( auto & RenderFn : * ImmFns ) RenderFn ( CmpMI ) ; constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ;


<s> bool <ISA_LIT>Subtarget :: useDFAforSMS ( ) const {


<s> SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) {

if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return Op ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( StackDirection D , Align StackAl , int LAO , unsigned TransAl ) : TargetFrameLowering ( D , StackAl , LAO , TransAl ) {


<s> cur_tree = ( ( pop_target ) ? pop_target : target_option_default_node ) ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( cur_tree ) ) ; } else { cur_tree = nios2_valid_target_attribute_tree ( args ) ; if ( ! cur_tree ) return false ;


<s> unsigned Opc = <NUM_LIT> ; if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ;

for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ;


<s> unsigned SrcLo = HRI . getSubReg ( SrcR , <STR_LIT> ) ; unsigned SrcHi = HRI . getSubReg ( SrcR , <STR_LIT> ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = HRI . getSpillSize ( <STR_LIT> ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc ; if ( LPR . contains ( SrcLo ) ) { StoreOpc = NeedAlign <= HasAlign ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcLo , getKillRegState ( IsKill ) ) . cloneMemRefs ( * MI ) ; } if ( LPR . contains ( SrcHi ) ) { StoreOpc = NeedAlign <= MinAlign ( HasAlign , Size ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( Size ) . addReg ( SrcHi , getKillRegState ( IsKill ) ) . cloneMemRefs ( * MI ) ; }


<s> } else return false ; } else if ( ( ( runner ) -> getIntrinsicID ( ) == StoreId ) ) { if ( flag ) { flag = ! flag ; ptr2 = dyn_cast < Instruction > ( runner ) -> getOperand ( <NUM_LIT> ) ; StorePtrList . push_back ( runner ) ; if ( dyn_cast < Instruction > ( ptr ) == dyn_cast < Instruction > ( ptr2 ) ) Diagnostic = true ; } else return false ; } } if ( flag ) return false ; if ( ! createCopyInstruction ( ) ) return false ; UnrollSize = LoadPtrList . size ( ) ; if ( CycleSize > <NUM_LIT> || CycleSize == <NUM_LIT> || UnrollSize > <NUM_LIT> || UnrollSize == <NUM_LIT> ) return false ; BB = L -> getParentLoop ( ) -> block_begin ( ) ;

return extractIntrinFromList ( get_list_of < IntrinsicInst , <NUM_LIT> > ( BB ) , LoadId ) . empty ( ) ;


<s> if ( isShuffleEquivalent ( Mask , Unpckl , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; SmallVector < int , <NUM_LIT> > Unpckh ; createUnpackShuffleMask ( VT , Unpckh , false , false ) ;

if ( isShuffleEquivalent ( Mask , Unpckh , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ;


<s> <ISA_LIT>Disassembler :: <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> if ( Base . isReg ( ) ) { O << <STR_LIT> ; printRegName ( O , MRI . getSubReg ( Base . getReg ( ) , <STR_LIT> ) ) ; O << <STR_LIT> ; printRegName ( O , MRI . getSubReg ( Base . getReg ( ) , <STR_LIT> ) ) ; O << <STR_LIT> ;


if ( getOptLevel ( ) != CodeGenOpt :: None ) {


<s> if ( getParser ( ) . ParseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size , <NUM_LIT> ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ;

if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ;


<s> unsigned Opcode = I -> getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) return true ; <STR_LIT> BranchCode = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( Opcode ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ;


<s> switch ( e ) { CASE ( SamplerFilterMode , Nearest ) CASE ( SamplerFilterMode , Linear ) break ;


<s> } uint32_t AlignBits = RecordAlignment . value ( ) * <NUM_LIT> ; if ( MemberBitSize > AlignBits ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; StartBitOffset = MemberBitOffset & ~ ( AlignBits - <NUM_LIT> ) ;

if ( ( StartBitOffset + AlignBits ) < ( MemberBitOffset + MemberBitSize ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ;


<s> uint64_t <ISA_LIT>InstrInfo :: getInstImm ( const MachineInstr & MI ) const { const MCInstrDesc & MC = MI . getDesc ( ) ; if ( <ISA_LIT>II :: getHasImm ( MC ) ) { unsigned ImmPos = <ISA_LIT>II :: getImmFieldOpNum ( MC ) ; const MachineOperand & MOImm = MI . getOperand ( ImmPos ) ; assert ( MOImm . isImm ( ) || MOImm . isFPImm ( ) || MOImm . isMBB ( ) ) ;


<s> unsigned NewOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( <STR_LIT> ( <STR_LIT> ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) ) ; ++ NumSTRD2STM ; } } else { unsigned NewOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) || ( OffReg && TRI -> regsOverlap ( EvenReg , OffReg ) ) ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) && ( ! OffReg || ! TRI -> regsOverlap ( OddReg , OffReg ) ) ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , BaseReg , false , OffReg , false , Pred , PredReg , TII ) ; InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , BaseReg , BaseKill , OffReg , OffKill , Pred , PredReg , TII ) ; } else { InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , BaseReg , false , OffReg , false , Pred , PredReg , TII ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , BaseReg , BaseKill , OffReg , OffKill , Pred , PredReg , TII ) ; } if ( isLd ) ++ NumLDRD2LDR ; else ++ NumSTRD2STR ; }


<s> if ( MEM_P ( op ) ) return <NUM_LIT> ; if ( unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE ( op ) == SImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( TARGET_ZBB ) { if ( ! unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ;

if ( GET_MODE ( op ) == HImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; HasLEB128 = true ; AbsoluteDebugSectionOffsets = true ;


<s> GV -> eraseFromParent ( ) ; for ( Constant * C : ToRemove ) { C -> removeDeadConstantUsers ( ) ; } if ( ! Init . empty ( ) ) { ArrayType * ATy = ArrayType :: get ( Type :: getInt8PtrTy ( M . getContext ( ) ) , Init . size ( ) ) ; GV = new llvm :: GlobalVariable ( M , ATy , false , GlobalValue :: AppendingLinkage , ConstantArray :: get ( ATy , Init ) , Name ) ; GV -> setSection ( <STR_LIT> ) ; }


<s> static PredicateKind getPredicateSense ( const MachineInstr & MI , const <ISA_LIT>InstrInfo * HII ) { if ( ! HII -> isPredicated ( MI ) ) return PK_Unknown ; if ( HII -> isPredicatedTrue ( MI ) ) return PK_True ; return PK_False ;


<s> if ( MRI . livein_empty ( ) ) { return <NUM_LIT> ; } const TargetRegisterClass * IndirectRC = getIndirectAddrRegClass ( ) ; for ( MachineRegisterInfo :: livein_iterator LI = MRI . livein_begin ( ) , LE = MRI . livein_end ( ) ; LI != LE ; ++ LI ) { unsigned Reg = LI -> first ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) || ! IndirectRC -> contains ( Reg ) ) continue ; unsigned RegIndex ; unsigned RegEnd ; for ( RegIndex = <NUM_LIT> , RegEnd = IndirectRC -> getNumRegs ( ) ; RegIndex != RegEnd ; ++ RegIndex ) {

if ( IndirectRC -> getRegister ( RegIndex ) == Reg ) break ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const GCNSubtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI , const <ISA_LIT>TargetMachine & TM ) : TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , TM ( TM ) , STI ( STI ) , EnableLateStructurizeCFG ( <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ) , {


<s> EVT VT = Node -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = {

StoreVal , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ;


<s> if ( RestrictUseOfBaseReg ( ) ) { if ( AM . IndexReg . getNode ( ) == <NUM_LIT> ) { AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false ; } return true ; } if ( AM . BaseType != <ISA_LIT>ISelAddressMode :: RegBase || AM . Base_Reg . getNode ( ) ) { if ( ! AM . IndexReg . getNode ( ) ) { AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false ; } return true ; }

AM . BaseType = <ISA_LIT>ISelAddressMode :: RegBase ;


<s> return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCInstrInfo ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > A ( TheThumbLETarget ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > B ( TheThumbBETarget ) ;


<s> if ( ( M [ i ] >= <NUM_LIT> && ( unsigned ) M [ i ] != Idx ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + <NUM_LIT> ] != Idx + NumElts ) ) return false ; Idx += <NUM_LIT> ; } if ( VT . is64BitVector ( ) && EltSz == <NUM_LIT> ) return false ; return true ;


<s> MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ;


<s> MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; if ( Src0 . isReg ( ) && ( RI . isSGPRReg ( MRI , Src0 . getReg ( ) ) || isLiteralConstantLike ( Src0 , InstrDesc . OpInfo [ Src0Idx ] ) ) ) legalizeOpWithMove ( MI , Src0Idx ) ; } if ( Opc == <STR_LIT> ) { int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( Src0 . isReg ( ) && RI . isVGPR ( MRI , Src0 . getReg ( ) ) ) { unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src0 ) ; Src0 . ChangeToRegister ( Reg , false ) ; } if ( Src1 . isReg ( ) && RI . isVGPR ( MRI , Src1 . getReg ( ) ) ) { unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; } return ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . Opcode == <STR_LIT> || MCID . Opcode == <STR_LIT> ) { emitDataProcessingInstruction ( MI , <STR_LIT> ) ; unsigned JTIndex = ( MCID . Opcode == <STR_LIT> ) ? MI . getOperand ( <NUM_LIT> ) . getIndex ( ) : MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; emitInlineJumpTable ( JTIndex ) ; return ; } else if ( MCID . Opcode == <STR_LIT> ) { emitLoadStoreInstruction ( MI , <STR_LIT> ) ; emitInlineJumpTable ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ) ; return ;


<s> & <STR_LIT> ; case <NUM_LIT> : return RB -> getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB -> getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB -> getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB -> getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB -> getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; default :


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( PCLabelId ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) ) ; unsigned NewVReg4 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg4 ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( NewVReg2 , RegState :: Kill ) . addReg ( NewVReg3 , RegState :: Kill ) ) ; unsigned NewVReg5 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg5 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg4 , RegState :: Kill ) . addReg ( NewVReg5 , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ; } else { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addImm ( <NUM_LIT> ) . addMemOperand ( CPMMO ) ) ;


<s> TmpInst . addOperand ( MCOperand :: createReg ( Reg1 ) ) ; TmpInst . addOperand ( Op2 ) ; TmpInst . setLoc ( IDLoc ) ; getStreamer ( ) . EmitInstruction ( TmpInst , * STI ) ;


<s> static bool ix86_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_SSE && VALID_SSE_REG_MODE ( mode ) ) return true ; if ( TARGET_SSE2 && VALID_SSE2_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX && VALID_AVX256_REG_MODE ( mode ) ) return true ; if ( TARGET_AVX512F && VALID_AVX512F_REG_MODE ( mode ) ) return true ; if ( TARGET_MMX && VALID_MMX_REG_MODE ( mode ) ) return true ; if ( TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW ( mode ) ) return true ; return false ;


<s> void <ISA_LIT>XPLINKFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & Regs = Subtarget . getSpecialRegisters < <ISA_LIT>XPLINK64Registers > ( ) ;

MFFrame . setOffsetAdjustment ( Regs . getStackPointerBias ( ) ) ;


<s> if ( satisfies_constraint_L ( addis_value ) ) { fuse_ops [ <NUM_LIT> ] = addis_value ; addis_str = <STR_LIT> ; } else if ( GET_CODE ( addis_value ) == PLUS ) { rtx op0 = XEXP ( addis_value , <NUM_LIT> ) ; rtx op1 = XEXP ( addis_value , <NUM_LIT> ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) && satisfies_constraint_L ( op1 ) ) { fuse_ops [ <NUM_LIT> ] = op0 ; fuse_ops [ <NUM_LIT> ] = op1 ; addis_str = <STR_LIT> ; } } else if ( GET_CODE ( addis_value ) == HIGH ) { rtx value = XEXP ( addis_value , <NUM_LIT> ) ; if ( GET_CODE ( value ) == UNSPEC && XINT ( value , <NUM_LIT> ) == UNSPEC_TOCREL ) { fuse_ops [ <NUM_LIT> ] = XVECEXP ( value , <NUM_LIT> , <NUM_LIT> ) ;


<s> SDLoc DL ( Index ) ; if ( CurDAG -> isBaseWithConstantOffset ( Index ) ) { SDValue N0 = Index . getOperand ( <NUM_LIT> ) ; SDValue N1 = Index . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( C1 -> getSExtValue ( ) <= <NUM_LIT> || CurDAG -> SignBitIsZero ( N0 ) || ( Index -> getOpcode ( ) == <STR_LIT> && C1 -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = N0 ; Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } } if ( isa < ConstantSDNode > ( Index ) ) return false ;


<s> } HeadCond . clear ( ) ; MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; if ( TII -> analyzeBranch ( * Head , TBB , FBB , HeadCond ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumHeadBranchRejs ; return false ; } if ( ! TBB || HeadCond . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumHeadBranchRejs ; return false ; } if ( ! parseCond ( HeadCond , HeadCmpBBCC ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumHeadBranchRejs ; return false ; } if ( TBB != CmpBB ) { assert ( TBB == Tail && <STR_LIT> ) ; HeadCmpBBCC = <STR_LIT> ( HeadCmpBBCC ) ; } CmpBBCond . clear ( ) ; TBB = FBB = nullptr ; if ( TII -> analyzeBranch ( * CmpBB , TBB , FBB , CmpBBCond ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumCmpBranchRejs ; return false ; } if ( ! TBB || CmpBBCond . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumCmpBranchRejs ; return false ; } if ( ! parseCond ( CmpBBCond , CmpBBTailCC ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ++ NumCmpBranchRejs ; return false ; } if ( TBB != Tail ) CmpBBTailCC = <STR_LIT> ( CmpBBTailCC ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmpBBCC ) << <STR_LIT> << <STR_LIT> ( CmpBBTailCC ) << '\n' ) ; CmpMI = findConvertibleCompare ( CmpBB ) ; if ( ! CmpMI ) return false ; if ( ! canSpeculateInstrs ( CmpBB , CmpMI ) ) { ++ NumSpeculateRejs ;


<s> CopyPropagation CopyP ( HRI , MRI ) ; Changed |= visitBlock ( Entry , CopyP , ACP ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; BT . run ( ) ; RegisterSet ABS ; BitSimplification BitS ( BT , * MDT , HII , HRI , MRI , MF ) ; Changed |= visitBlock ( Entry , BitS , ABS ) ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) || Changed ; if ( Changed ) {

for ( auto & B : MF ) for ( auto & I : B ) I . clearKillInfo ( ) ;


<s> default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , dl , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ;

SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , dl , Reg , T , Result . getValue ( <NUM_LIT> ) ) ;


<s> else if ( Reg == <STR_LIT> ) Comment << <STR_LIT> ; else Comment << printReg ( Reg , & TRI ) ; SmallString < <NUM_LIT> > Expr ; unsigned DwarfReg = TRI . getDwarfRegNum ( Reg , true ) ; Expr . push_back ( ( uint8_t ) ( dwarf :: DW_OP_breg0 + DwarfReg ) ) ; Expr . push_back ( <NUM_LIT> ) ;

appendVGScaledOffsetExpr ( Expr , NumBytes , NumVGScaledBytes , TRI . getDwarfRegNum ( <STR_LIT> , true ) , Comment ) ;


<s> if ( Byte % BytesPerElement != <NUM_LIT> ) break ; Index = Byte / BytesPerElement ; Op = Op . getOperand ( unsigned ( First ) / Bytes . size ( ) ) ; Force = true ; } else if ( Opcode == <STR_LIT> && canTreatAsByteVector ( Op . getValueType ( ) ) ) { EVT OpVT = Op . getValueType ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( OpBytesPerElement < BytesPerElement ) break ; unsigned End = ( Index + <NUM_LIT> ) * BytesPerElement ; if ( End % OpBytesPerElement != <NUM_LIT> ) break ; Op = Op . getOperand ( End / OpBytesPerElement - <NUM_LIT> ) ; if ( ! Op . getValueType ( ) . isInteger ( ) ) { EVT VT = <STR_LIT> ( Op . getValueType ( ) . getSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; } EVT VT = <STR_LIT> ( ResVT . getSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; if ( VT != ResVT ) { DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , ResVT , Op ) ; } return Op ; } else if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && canTreatAsByteVector ( Op . getValueType ( ) ) && canTreatAsByteVector ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { EVT ExtVT = Op . getValueType ( ) ; EVT OpVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned ExtBytesPerElement = ExtVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned Byte = Index * BytesPerElement ; unsigned SubByte = Byte % ExtBytesPerElement ; unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement ; if ( SubByte < MinSubByte || SubByte + BytesPerElement > ExtBytesPerElement ) break ; Byte = Byte / ExtBytesPerElement * OpBytesPerElement ; Byte += SubByte - MinSubByte ; if ( Byte % BytesPerElement != <NUM_LIT> ) break ; Op = Op . getOperand ( <NUM_LIT> ) ; Index = Byte / BytesPerElement ; Force = true ; } else break ; } if ( Force ) { if ( Op . getValueType ( ) != VecVT ) { Op = DAG . getNode ( <STR_LIT> , DL , VecVT , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; } return DAG . getNode ( <STR_LIT> , DL , ResVT , Op , DAG . getConstant ( Index , DL , <STR_LIT> ) ) ; } return SDValue ( ) ;


<s> auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned AP = HMFI . getStackAlignBasePhysReg ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; bool UseFP = false , UseAP = false ; if ( NoOpt && ! HasExtraAlign ) UseFP = true ; if ( MFI . isFixedObjectIndex ( FI ) || MFI . isObjectPreAllocated ( FI ) ) { UseFP |= ( HasAlloca || HasExtraAlign ) ; } else { if ( HasAlloca ) { if ( HasExtraAlign ) UseAP = true ; else UseFP = true ; } } bool HasFP = hasFP ( MF ) ; assert ( ( HasFP || ! UseFP ) && <STR_LIT> ) ; if ( Offset > <NUM_LIT> && ! HasFP ) Offset -= <NUM_LIT> ; if ( UseFP ) FrameReg = FP ; else if ( UseAP ) FrameReg = AP ; else FrameReg = SP ;


<s> unsigned <ISA_LIT>SEInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { unsigned Opc = MI . getOpcode ( ) ; if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) , STI ( sti ) {