<s> I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( I -> getOpcode ( ) != BccOpc && I -> getOpcode ( ) != BccOpcNot ) return <NUM_LIT> ; I -> eraseFromParent ( ) ;


<s> if ( Ins [ i ] . Flags . isSRet ( ) ) { OriginalArgWasF128 . push_back ( false ) ; continue ; } assert ( Ins [ i ] . OrigArgIndex < MF . getFunction ( ) -> arg_size ( ) ) ; std :: advance ( FuncArg , Ins [ i ] . OrigArgIndex ) ; OriginalArgWasF128 . push_back ( originalTypeIsF128 ( FuncArg -> getType ( ) , nullptr ) ) ; }


<s> } if ( ISVECDEST ( Instr ) ) { createVecDest ( F , Instr , copies ) ; return ; } if ( ISVECBUILD ( Instr ) ) { createVecBuild ( F , Instr , copies ) ; return ; } unsigned numcopies = numCopiesNeeded ( Instr ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; ++ i ) copies . push_back ( F . CloneMachineInstr ( Instr ) ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; ++ i ) { MachineInstrBuilder copy ( F , copies [ i ] ) ; std :: vector < MachineOperand > allOperands ; std :: vector < bool > isDef ; for ( unsigned j = <NUM_LIT> , e = copy -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand oper = copy -> getOperand ( j ) ; allOperands . push_back ( oper ) ; if ( oper . isReg ( ) ) isDef . push_back ( oper . isDef ( ) ) ; else isDef . push_back ( false ) ; } for ( unsigned j = <NUM_LIT> , e = copy -> getNumOperands ( ) ; j != e ; ++ j ) copy -> RemoveOperand ( <NUM_LIT> ) ; copy -> setDesc ( InstrInfo -> get ( getScalarVersion ( Instr ) ) ) ; for ( unsigned j = <NUM_LIT> , e = allOperands . size ( ) ; j != e ; ++ j ) { MachineOperand oper = allOperands [ j ] ; if ( oper . isReg ( ) ) { unsigned regnum = oper . getReg ( ) ; if ( isVectorRegister ( regnum ) ) { SmallVector < unsigned , <NUM_LIT> > scalarRegs = getScalarRegisters ( regnum ) ; copy . addReg ( scalarRegs [ i ] , getDefRegState ( isDef [ j ] ) ) ; } else copy . addOperand ( oper ) ;


isThumb ( false ) , hasThumb2 ( false ) , VarArgsRegSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , GPRCS1Frames ( <NUM_LIT> ) , GPRCS2Frames ( <NUM_LIT> ) , DPRCSFrames ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) {


<s> for ( MachineBasicBlock * MBB = From ; MBB != To && ! MBB -> succ_empty ( ) ; MBB = * MBB -> succ_begin ( ) ) {

for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ;


<s> bool <ISA_LIT>GOT :: hasGOT1 ( ) const { return ( ( ! m_GOT . empty ( ) ) || ( ! m_GOTPLT . empty ( ) ) ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override {

return create<ISA_LIT>MachObjectWriter ( false , cantFail ( MachO :: getCPUType ( TT ) ) , Subtype ) ;


<s> static std :: string computeDataLayout ( const Triple & TT , StringRef CPU , StringRef FS ) { bool VectorABI = UsesVectorABI ( CPU , FS ) ; std :: string Ret = <STR_LIT> ; Ret += <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ;


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;

return IsConstantImm && isInt < <NUM_LIT> > ( Imm - <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> unsigned BitWidth = VT . getSizeInBits ( ) ; assert ( Op . getNumOperands ( ) == <NUM_LIT> && VT == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ;

SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ;


<s> if ( ! Subtarget . hasV4TOps ( ) ) return false ; const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) == OperandNum ;


<s> if ( ST . getTrapHandlerAbi ( ) != GCNSubtarget :: TrapHandlerAbiHsa || ! ST . isTrapHandlerEnabled ( ) ) { DiagnosticInfoUnsupported NoTrap ( B . getMF ( ) . getFunction ( ) , <STR_LIT> , MI . getDebugLoc ( ) , DS_Warning ) ; LLVMContext & Ctx = B . getMF ( ) . getFunction ( ) . getContext ( ) ;


<s> unsigned getMaxWorkGroupsPerCU ( unsigned FlatWorkGroupSize ) const override { return <STR_LIT> :: getMaxWorkGroupsPerCU ( this , FlatWorkGroupSize ) ;


<s> return MI . getDesc ( ) . isTerminator ( ) ;


<s> int lastpos = pos - <NUM_LIT> ; while ( lastpos < LINELEN - <NUM_LIT> && isdigit ( linebuf [ lastpos + <NUM_LIT> ] ) ) ++ lastpos ; if ( lastpos >= LINELEN - <NUM_LIT> ) { diag ( lastpos , <STR_LIT> ) ; exit ( <NUM_LIT> ) ; }


<s> SDValue Nest = Op . getOperand ( <NUM_LIT> ) ; const Value * TrmpAddr = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue OutChains [ <NUM_LIT> ] ; SDValue Addr = Trmp ; DebugLoc dl = Op . getDebugLoc ( ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Chain , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Chain , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Chain , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Chain , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Chain , dl , FPtr , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains , <NUM_LIT> ) ;


<s> ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign :: AExt : { bool Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; if ( ! Emitted ) Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; if ( ! Emitted ) Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; assert ( Emitted && <STR_LIT> ) ; Emitted = Emitted ; ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> ) return false ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; if ( ! ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) ) ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; Address Addr ; Addr . BaseType = Address :: RegBase ; Addr . Base . Reg = <STR_LIT> ; Addr . Offset = VA . getLocMemOffset ( ) ;

if ( ! <ISA_LIT>EmitStore ( ArgVT , Arg , Addr ) ) return false ;


<s> if ( ! REG_P ( x1 ) || ! MMIX_REG_OK ( x1 ) ) return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; if ( REG_P ( x2 ) && MMIX_REG_OK ( x2 ) ) return <NUM_LIT> ; if ( GET_CODE ( x2 ) == CONST_INT && CONST_OK_FOR_LETTER_P ( INTVAL ( x2 ) , 'I' ) ) return <NUM_LIT> ; return <NUM_LIT> ; }


<s> } unsigned DelayLimit = SchedModel . MispredictPenalty * <NUM_LIT> / <NUM_LIT> ; unsigned HeadDepth = Trace . getInstrCycles ( * CmpConv . Head -> getFirstTerminator ( ) ) . Depth ; unsigned CmpBBDepth = Trace . getInstrCycles ( * CmpConv . CmpBB -> getFirstTerminator ( ) ) . Depth ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadDepth << <STR_LIT> << CmpBBDepth << '\n' ) ; if ( CmpBBDepth > HeadDepth + DelayLimit ) {

DEBUG ( dbgs ( ) << <STR_LIT> << DelayLimit << <STR_LIT> ) ;


<s> std :: string Name = AccessInfo . IsWrite ? <STR_LIT> : <STR_LIT> ; MCSymbol * ReportError = OutContext . getOrCreateSymbol ( <STR_LIT> + Name + utostr ( <NUM_LIT> << AccessInfo . AccessSizeIndex ) ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> + Reg ) , STI ) ; OutStreamer -> emitInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( ReportError , OutContext ) ) , STI ) ;


<s> ensureEarlyExitBlock ( MBB , false ) ; MachineInstr * BranchMI = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EarlyExitBlock ) ; auto Next = std :: next ( BranchMI -> getIterator ( ) ) ; if ( Next != MBB . end ( ) && ! Next -> isTerminator ( ) ) splitBlock ( MBB , * BranchMI , MDT ) ; MBB . addSuccessor ( EarlyExitBlock ) ; MDT -> getBase ( ) . insertEdge ( & MBB , EarlyExitBlock ) ; }


<s> SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( Mask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ; SDValue Ops [ ] = { Chain , Src , Mask , Base , Index , Scale } ;

SDValue Res = DAG . getTargetMemSDNode < <ISA_LIT>MaskedGatherSDNode > ( VTs , Ops , dl , MemIntr -> getMemoryVT ( ) , MemIntr -> getMemOperand ( ) ) ;


<s> Imm = ( short ) cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return Imm == ( int32_t ) cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; else return Imm == ( int64_t ) cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ;


<s> return _mm_slli_epi32 ( __A , _mm_cvtsi128_si32 ( __B ) ) ;


<s> addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> uint32_t C = isC ? cast < ConstantSDNode > ( Size ) -> getZExtValue ( ) : ~ <NUM_LIT> ; if ( C <= <NUM_LIT> && ( ( C & <NUM_LIT> ) == <NUM_LIT> ) ) return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , SP , CurDAG -> getTargetConstant ( C / <NUM_LIT> , <STR_LIT> ) , Chain ) ; if ( Subtarget -> isThumb1Only ( ) ) { return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , SP , Size , Chain ) ; } else if ( Subtarget -> isThumb2 ( ) ) { if ( isC && Predicate_t2_so_imm ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else if ( isC && Predicate_imm0_4095 ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else {

SDValue Ops [ ] = { SP , Size , getI32Imm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) , Chain } ;


<s> SDValue Use = GetRefUse ( Op ) ; SDValue Aload = Obj ; if ( IS_START_OF_CHAIN ( InChainUseFlag ) ) { EVT VTs [ ] = { <STR_LIT> , <STR_LIT> } ; SDValue Ops [ ] = { Chain , Obj } ; Aload = DAG . getNode ( <STR_LIT> , DL , VTs , Ops ) ; SDNodeFlags Flags = Aload . getNode ( ) -> getFlags ( ) ; Flags . setIsComposite ( true ) ; Aload . getNode ( ) -> setFlags ( Flags ) ; Chain = Aload . getValue ( <NUM_LIT> ) ; } SDValue DescID = GetFieldSpecDescID ( DL , DAG , Obj , Idx ) ; SDNodeFlags Flags = Op . getNode ( ) -> getFlags ( ) ; Idx . getNode ( ) -> setFlags ( Flags ) ; SDValue FieldAcc ; if ( Use . getOpcode ( ) == <STR_LIT> ) { SDNode * AloadNode = Aload . getNode ( ) ; assert ( AloadNode -> getValueType ( AloadNode -> getNumValues ( ) - <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT VTs [ ] = { Use . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue StoreSrc [ ] = { Chain , Use . getOperand ( <NUM_LIT> ) } ; SDValue SrcLoad = LoadOperandWCh ( DAG , DL , VTs , StoreSrc ) ; TransferNodeFlags ( Use . getOperand ( <NUM_LIT> ) , SrcLoad ) ; SDValue Opr [ ] = { SrcLoad . getValue ( <NUM_LIT> ) , Aload , SrcLoad , DescID } ; FieldAcc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Opr ) ; TransferNodeFlags ( Op , FieldAcc ) ; } else { EVT VTs [ ] = { Op . getValueType ( ) , <STR_LIT> } ; SDValue Opr [ ] = { Chain , Aload , DescID } ; FieldAcc = DAG . getNode ( <STR_LIT> , DL , VTs , Opr ) ; Chain = FieldAcc . getValue ( <NUM_LIT> ) ; TransferNodeFlags ( Op , FieldAcc ) ; if ( Use . getOpcode ( ) == <STR_LIT> ) { EVT StoreVTs [ ] = { FieldAcc . getValueType ( ) , <STR_LIT> } ; SDValue StoreOps [ ] = { Chain , FieldAcc } ; FieldAcc = DAG . getNode ( <STR_LIT> , DL , StoreVTs , StoreOps ) ; Chain = FieldAcc . getValue ( <NUM_LIT> ) ; SDNodeFlags Flags ; Flags . setIsComposite ( Op . getNode ( ) -> getFlags ( ) . hasIsComposite ( ) ) ; FieldAcc . getNode ( ) -> setFlags ( Flags ) ; } }

if ( Use . getOpcode ( ) == <STR_LIT> || Use . getOpcode ( ) == <STR_LIT> ) ReplaceAllUsesOfValueAndChain ( false , DAG , Use , FieldAcc ) ;


<s> unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; bool NeedsRotate = VRI . RLAmt != <NUM_LIT> ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) + ( unsigned ) ( bool ) Res ; DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << <STR_LIT> << <STR_LIT> << NumAndInsts << <STR_LIT> << VRI . NumGroups << <STR_LIT> ) ; if ( NumAndInsts >= VRI . NumGroups ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt ) { SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt , dl ) , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( <NUM_LIT> , dl ) } ; VRot = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { VRot = VRI . V ; }


<s> if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; }


<s> return ( SSE_REG_P ( exp ) && ! EXT_REX_SSE_REG_P ( exp ) && GET_MODE_BITSIZE ( GET_MODE ( exp ) ) > <NUM_LIT> ) ;


<s> void startSinglePathS0Spill ( void ) { SPS0SpillOffset = SinglePathFIs . size ( ) ;


<s> unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; Register SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D3 , getUndefRegState ( SrcIsUndef ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcIsKill && ! SrcIsUndef ) MIB -> addRegisterKilled ( SrcReg , TRI , true ) ; else if ( ! SrcIsUndef ) MIB . addReg ( SrcReg , RegState :: Implicit ) ; TransferImpOps ( MI , MIB , MIB ) ; MIB . cloneMemRefs ( MI ) ; MI . eraseFromParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MIB . getInstr ( ) -> dump ( ) ; ) ;


<s> O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm ( ) << <STR_LIT> ;


<s> SmallVector < uint64_t , <NUM_LIT> > Record ; SmallVector < StringRef , <NUM_LIT> > Names ; M . getMDKindNames ( Names ) ; if ( Names . empty ( ) ) return ; Stream . EnterSubblock ( bitc :: METADATA_BLOCK_ID , <NUM_LIT> ) ; for ( unsigned MDKindID = <NUM_LIT> , e = Names . size ( ) ; MDKindID != e ; ++ MDKindID ) { Record . push_back ( MDKindID ) ; StringRef KName = Names [ MDKindID ] ; Record . append ( KName . begin ( ) , KName . end ( ) ) ; Stream . EmitRecord ( bitc :: METADATA_KIND , Record , <NUM_LIT> ) ; Record . clear ( ) ;


<s> MachineBasicBlock * PredMBB = nullptr ; if ( MBB -> pred_size ( ) == <NUM_LIT> ) PredMBB = * MBB -> pred_begin ( ) ; if ( MBB -> pred_size ( ) == <NUM_LIT> && Loop != nullptr && Loop -> getHeader ( ) == MBB ) { for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) if ( Loop -> contains ( Pred ) ) PredMBB = ( Pred == MBB ? nullptr : Pred ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalBase , HiLo ) ; } SDValue HiLo = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI32 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_LO32 , DAG ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , GlobalBase , HiLo ) ;

return DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , AbsAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; int CompareOpc ; bool isDot ; if ( ! getAltivecCompareInfo ( Op , CompareOpc , isDot ) ) return SDValue ( ) ; if ( ! isDot ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ; } SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( CompareOpc , <STR_LIT> ) } ; std :: vector < MVT > VTs ; VTs . push_back ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ; VTs . push_back ( <STR_LIT> ) ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) ;

SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ;


<s> if ( GET_CODE ( op1 ) == CONST_INT ) return INTVAL ( op1 ) >= <NUM_LIT> ; if ( GET_CODE ( op0 ) != REG ) return <NUM_LIT> ; if ( sparc_check_64 ( op0 , insn ) == <NUM_LIT> ) return <NUM_LIT> ; return ( GET_CODE ( op1 ) == REG && sparc_check_64 ( op1 , insn ) == <NUM_LIT> ) ; } case IOR : case XOR : { rtx op0 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; rtx op1 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) != REG || sparc_check_64 ( op0 , insn ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( GET_CODE ( op1 ) == CONST_INT ) return INTVAL ( op1 ) >= <NUM_LIT> ; return ( GET_CODE ( op1 ) == REG && sparc_check_64 ( op1 , insn ) == <NUM_LIT> ) ; } case LSHIFTRT : return GET_MODE ( SET_SRC ( pat ) ) == SImode ; case CONST_DOUBLE : return ! ( CONST_DOUBLE_LOW ( SET_SRC ( pat ) ) & <NUM_LIT> ) ; case CONST_INT : return ! ( INTVAL ( SET_SRC ( pat ) ) & <NUM_LIT> ) ; case ASHIFTRT : case SIGN_EXTEND : return - ( GET_MODE ( SET_SRC ( pat ) ) == SImode ) ; case REG : return sparc_check_64 ( SET_SRC ( pat ) , insn ) ; default : return <NUM_LIT> ;


<s> if ( isFullyRelaxed ( RF ) ) return false ; MCInst Relaxed ; relaxInstruction ( RF . getInst ( ) , * RF . getSubtargetInfo ( ) , Relaxed ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallString < <NUM_LIT> > Code ; raw_svector_ostream VecOS ( Code ) ; Emitter . encodeInstruction ( Relaxed , VecOS , Fixups , * RF . getSubtargetInfo ( ) ) ; const unsigned OldSize = RF . getContents ( ) . size ( ) ; const unsigned NewSize = Code . size ( ) ; assert ( NewSize >= OldSize && <STR_LIT> ) ; unsigned Delta = NewSize - OldSize ; if ( Delta > RemainingSize ) return false ; RF . setInst ( Relaxed ) ; RF . getContents ( ) = Code ;


<s> bool <ISA_LIT>FoldOperands :: tryFoldClamp ( MachineInstr & MI ) { const MachineOperand * ClampSrc = isClamp ( MI ) ; if ( ! ClampSrc || ! hasOneNonDBGUseInst ( * MRI , ClampSrc -> getReg ( ) ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( ClampSrc -> getReg ( ) ) ; if ( TII -> getClampMask ( * Def ) != TII -> getClampMask ( MI ) ) return false ; MachineOperand * DefClamp = TII -> getNamedOperand ( * Def , <STR_LIT> :: clamp ) ; if ( ! DefClamp ) return false ;

DEBUG ( dbgs ( ) << <STR_LIT> << * DefClamp << <STR_LIT> << * Def << '\n' ) ;


<s> return ( __a - ( __b * __aarch64_vget_lane_any ( __c , __lane ) ) ) ;


<s> static CUMULATIVE_ARGS zero_cum ; tree param ; tree next_param ; if ( TARGET_DEBUG_D_MODE ) { fprintf ( stderr , <STR_LIT> , ( long ) fntype ) ; if ( ! fntype ) fputc ( '\n' , stderr ) ; else { tree ret_type = TREE_TYPE ( fntype ) ; fprintf ( stderr , <STR_LIT> , get_tree_code_name ( TREE_CODE ( fntype ) ) , get_tree_code_name ( TREE_CODE ( ret_type ) ) ) ; } }


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) {


<s> if ( ST -> hasAVX ( ) && PreferVectorWidth >= <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> hasSSE1 ( ) && PreferVectorWidth >= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> <ISA_LIT>AlwaysInline ( ) : ModulePass ( ID ) {


<s> return true ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( C1 -> getZExtValue ( ) ) && ( ! Subtarget -> privateMemoryResourceIsRangeChecked ( ) || CurDAG -> SignBitIsZero ( N0 ) ) ) { std :: tie ( VAddr , SOffset ) = foldFrameIndex ( N0 ) ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_TTMP ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_SGPR ) {


<s> bool alpha_gimple_fold_builtin ( gimple_stmt_iterator * gsi ) { bool changed = false ; gimple * stmt = gsi_stmt ( * gsi ) ; tree call = gimple_call_fn ( stmt ) ; gimple * new_stmt = NULL ; if ( call ) { tree fndecl = gimple_call_fndecl ( stmt ) ; if ( fndecl ) { tree arg0 , arg1 ; switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case ALPHA_BUILTIN_UMULH : arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , MULT_HIGHPART_EXPR , arg0 , arg1 ) ; break ; default : break ; }


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) != <STR_LIT> || RHS . getOpcode ( ) != <STR_LIT> || LHS . getValueType ( ) != VT ) return SDValue ( ) ; auto * LHSN1 = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ; auto * RHSN1 = dyn_cast < ConstantSDNode > ( RHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! LHSN1 || LHSN1 != RHSN1 || ! RHSN1 -> isZero ( ) ) return SDValue ( ) ; SDValue Op1 = LHS -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = RHS -> getOperand ( <NUM_LIT> ) ; EVT OpVT1 = Op1 . getValueType ( ) ; EVT OpVT2 = Op2 . getValueType ( ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || OpVT1 != OpVT2 || Op2 . getOpcode ( ) != <STR_LIT> || OpVT1 . getVectorElementType ( ) != VT ) return SDValue ( ) ; SDValue Val1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Val2 = Op2 . getOperand ( <NUM_LIT> ) ;

EVT ValVT = Val1 -> getValueType ( <NUM_LIT> ) ;


<s> llvm :: BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( <STR_LIT> ) ;


<s> if ( MFI . hasCalls ( ) ) MaxAlign = ( StackAlign > MaxAlign ) ? StackAlign : MaxAlign ;

else if ( MaxAlign < SlotSize ) MaxAlign = SlotSize ;


<s> return CreateReg ( Index , RegKind_FGR , RegInfo , S , E , Parser ) ;


<s> static bool mustPreserveGV ( const GlobalValue & GV ) { if ( const Function * F = dyn_cast < Function > ( & GV ) ) return F -> isDeclaration ( ) || F -> getName ( ) . startswith ( <STR_LIT> ) || F -> getName ( ) . startswith ( <STR_LIT> ) || <STR_LIT> ( F -> getCallingConv ( ) ) ;


<s> return ( vector unsigned int ) __builtin_altivec_vmrghw ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> int next ; int offset_ld = <NUM_LIT> ; int offset_st = <NUM_LIT> ; rtx x ; if ( ! optimize || ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT ) ) return <NUM_LIT> ; bytes = INTVAL ( operands [ <NUM_LIT> ] ) ; align = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( align > MOVE_MAX ) align = MOVE_MAX ; move_ratio = <NUM_LIT> ; if ( optimize > <NUM_LIT> ) move_ratio = LARGEST_MOVE_RATIO ; num_pieces = ( bytes / align ) + ( bytes % align ) ; if ( num_pieces > move_ratio ) return <NUM_LIT> ; x = XEXP ( dst_mem , <NUM_LIT> ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; dst_mem = replace_equiv_address ( dst_mem , x ) ; } x = XEXP ( src_mem , <NUM_LIT> ) ; if ( ! REG_P ( x ) ) { x = force_reg ( Pmode , x ) ; src_mem = replace_equiv_address ( src_mem , x ) ; } active [ <NUM_LIT> ] = active [ <NUM_LIT> ] = false ; do { next = phase ; phase ^= <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { int next_amount ; next_amount = ( bytes >= <NUM_LIT> ? <NUM_LIT> : ( bytes >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; next_amount = MIN ( next_amount , align ) ; amount [ next ] = next_amount ; mode [ next ] = mode_from_align [ next_amount ] ; temp [ next ] = gen_reg_rtx ( mode [ next ] ) ; x = adjust_address ( src_mem , mode [ next ] , offset_ld ) ; emit_insn ( gen_rtx_SET ( temp [ next ] , x ) ) ; offset_ld += next_amount ; bytes -= next_amount ; active [ next ] = true ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ;


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( N ) , <STR_LIT> , AM . Disp , <NUM_LIT> ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , Align ( AM . Align ) , AM . Disp , <NUM_LIT> ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , <NUM_LIT> , <NUM_LIT> ) ; else Disp = CurDAG -> getTargetConstant ( AM . Disp , SDLoc ( N ) , <STR_LIT> ) ;


<s> if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ; else return TFI -> hasFP ( MF ) ? ( IsN64 ? <STR_LIT> : <STR_LIT> ) : ( IsN64 ? <STR_LIT> : <STR_LIT> ) ;


<s> MachineBasicBlock * <ISA_LIT>Z80TargetLowering :: insertMul ( MachineInstr & MI , MachineBasicBlock * BB ) const {


<s> if ( ! need_zero_all_mm ) return false ; rtx zero_mmx = NULL_RTX ; machine_mode mode = V4HImode ; for ( unsigned int regno = FIRST_MMX_REG ; regno <= LAST_MMX_REG ; regno ++ ) if ( regno != ret_mmx_regno ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( zero_mmx == NULL_RTX ) { zero_mmx = reg ; emit_insn ( gen_rtx_SET ( reg , CONST0_RTX ( mode ) ) ) ; } else emit_move_insn ( reg , zero_mmx ) ;


<s> SDVTList CompareVT = CurDAG -> getVTList ( CompareTys ) ; SDValue CompareOps [ ] = { LHS , RHS , Chain } ; SDNode * Compare = CurDAG -> getMachineNode ( <STR_LIT> , N , CompareVT , CompareOps ) ; CondCodeSDNode * CC = cast < CondCodeSDNode > ( Cond . getNode ( ) ) ; uint64_t TargetCCode ; switch ( CC -> get ( ) ) { case <STR_LIT> :: SETOEQ : case <STR_LIT> :: SETUEQ : case <STR_LIT> :: SETEQ : TargetCCode = <STR_LIT> ; break ; case <STR_LIT> :: SETONE : case <STR_LIT> :: SETUNE : case <STR_LIT> :: SETNE : TargetCCode = <STR_LIT> ; break ; case <STR_LIT> :: SETOLT : case <STR_LIT> :: SETULT : case <STR_LIT> :: SETLT : TargetCCode = <STR_LIT> ; break ; case <STR_LIT> :: SETOLE : case <STR_LIT> :: SETULE : case <STR_LIT> :: SETLE : TargetCCode = <STR_LIT> ; break ; case <STR_LIT> :: SETOGT : case <STR_LIT> :: SETUGT : case <STR_LIT> :: SETGT : TargetCCode = <STR_LIT> ; break ;

case <STR_LIT> :: SETOGE : case <STR_LIT> :: SETUGE : case <STR_LIT> :: SETGE : TargetCCode = <STR_LIT> ; break ;


<s> <ISA_LIT>MCInstPrinter ( const MCAsmInfo & mai , const MCInstrInfo & mii , const MCRegisterInfo & mri ) : MCInstPrinter ( mai , mii , mri ) {


<s> bool isVecListTwoDByteIndexed ( ) const {

if ( ! isSingleSpacedVectorIndexed ( ) ) return false ;


<s> if ( MapIt != FiTmpOffsetMap . end ( ) ) return MapIt -> second ; FiTmpOffsetMap [ FI ] = TmpSize ; TmpSize += size ;


<s> } unsigned Rotate = ( DestIsHigh != SrcIsHigh ? <NUM_LIT> : <NUM_LIT> ) ;

BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( DestReg , RegState :: Undef ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> - Size ) . addImm ( <NUM_LIT> + <NUM_LIT> ) . addImm ( Rotate ) ;


<s> tree node = get_identifier ( call_name ) ; call_ref = gen_rtx_SYMBOL_REF ( VOIDmode , IDENTIFIER_POINTER ( node ) ) ; } if ( TARGET_PLTSEQ ) { rtx base = const0_rtx ; int regno ; if ( DEFAULT_ABI == ABI_ELFv2 ) { base = gen_rtx_REG ( Pmode , TOC_REGISTER ) ; regno = <NUM_LIT> ; } else { if ( flag_pic ) base = gen_rtx_REG ( Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; regno = <NUM_LIT> ; } rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx hi = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , base , call_ref , arg ) , UNSPEC_PLT16_HA ) ; rtx lo = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , reg , call_ref , arg ) , UNSPEC_PLT16_LO ) ; emit_insn ( gen_rtx_SET ( reg , hi ) ) ; emit_insn ( gen_rtx_SET ( reg , lo ) ) ; return reg ; } return force_reg ( Pmode , call_ref ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredCatchRet ( MachineInstr & MI , MachineBasicBlock * BB ) const { MachineFunction * MF = BB -> getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; MachineBasicBlock * TargetMBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF -> getFunction ( ) . getPersonalityFn ( ) ) ) && <STR_LIT> ) ; if ( ! Subtarget . is32Bit ( ) ) return BB ; MachineBasicBlock * RestoreMBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; assert ( BB -> succ_size ( ) == <NUM_LIT> ) ; MF -> insert ( std :: next ( BB -> getIterator ( ) ) , RestoreMBB ) ; RestoreMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( RestoreMBB ) ; MI . getOperand ( <NUM_LIT> ) . setMBB ( RestoreMBB ) ; RestoreMBB -> setIsEHPad ( true ) ; auto RestoreMBBI = RestoreMBB -> begin ( ) ; BuildMI ( * RestoreMBB , RestoreMBBI , DL , TII . get ( <STR_LIT> ) ) . addMBB ( TargetMBB ) ; return BB ;


<s> bool ComplexPatternFuncMutatesDAG ( ) const override {


<s> if ( T . TopDown ) Changed = T . processBlock ( B , AVs ) ; RegisterSet Defs ; for ( auto & I : B ) getInstrDefs ( I , Defs ) ; RegisterSet NewAVs = AVs ; NewAVs . insert ( Defs ) ; for ( auto I = GTN :: child_begin ( N ) , E = GTN :: child_end ( N ) ; I != E ; ++ I ) {

MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ;


<s> rtx mem_push_rtx ; rtx mem_fake_push_rtx ; const int ifun = xstormy16_interrupt_function_p ( ) ; mem_push_rtx = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; mem_push_rtx = gen_rtx_MEM ( HImode , mem_push_rtx ) ; mem_fake_push_rtx = gen_rtx_PRE_INC ( Pmode , stack_pointer_rtx ) ; mem_fake_push_rtx = gen_rtx_MEM ( HImode , mem_fake_push_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . stdarg_save_size ) for ( regno = FIRST_ARGUMENT_REGISTER ; regno < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS ; regno ++ ) { rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem_fake_push_rtx , reg ) , REG_NOTES ( insn ) ) ; } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) { rtx reg = gen_rtx_REG ( HImode , regno ) ; insn = emit_move_insn ( mem_push_rtx , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem_fake_push_rtx , reg ) , REG_NOTES ( insn ) ) ; }

if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) {


<s> insn = next_real_insn ( insn ) ; last_call = prev = NULL ; prev_clock = - <NUM_LIT> ; earliest_bb_end = <NUM_LIT> ; prev_implicit_nops = <NUM_LIT> ; first = true ; while ( insn ) { int this_clock = - <NUM_LIT> ; rtx_insn * next ; int max_cycles = <NUM_LIT> ; next = next_real_insn ( insn ) ; if ( DEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER || shadow_or_blockage_p ( insn ) || JUMP_TABLE_DATA_P ( insn ) ) goto next_insn ; if ( ! c6x_flag_schedule_insns2 ) PUT_MODE ( insn , TImode ) ; else { int cycles ; this_clock = insn_get_clock ( insn ) ; if ( this_clock != prev_clock ) { PUT_MODE ( insn , TImode ) ; if ( ! first ) { cycles = this_clock - prev_clock ; cycles -= prev_implicit_nops ; if ( cycles > <NUM_LIT> ) { rtx nop = emit_nop_after ( cycles - <NUM_LIT> , prev ) ; insn_set_clock ( nop , prev_clock + prev_implicit_nops + <NUM_LIT> ) ; } } prev_clock = this_clock ; if ( last_call && insn_get_clock ( last_call ) + <NUM_LIT> <= this_clock ) { emit_label_before ( call_labels [ INSN_UID ( last_call ) ] , insn ) ; last_call = NULL_RTX ; } prev_implicit_nops = <NUM_LIT> ; } } if ( recog_memoized ( insn ) >= <NUM_LIT> && ( c6x_flag_schedule_insns2 || ! returning_call_p ( insn ) ) ) { max_cycles = get_attr_cycles ( insn ) ; if ( get_attr_type ( insn ) == TYPE_CALLP ) prev_implicit_nops = <NUM_LIT> ; } else max_cycles = <NUM_LIT> ; if ( returning_call_p ( insn ) ) last_call = insn ; if ( c6x_flag_schedule_insns2 ) { gcc_assert ( this_clock >= <NUM_LIT> ) ; if ( earliest_bb_end < this_clock + max_cycles ) earliest_bb_end = this_clock + max_cycles ; } else if ( max_cycles > <NUM_LIT> ) emit_nop_after ( max_cycles - <NUM_LIT> , insn ) ; prev = insn ; first = false ; next_insn : if ( c6x_flag_schedule_insns2 && ( next == NULL_RTX || ( GET_MODE ( next ) == TImode && INSN_INFO_ENTRY ( INSN_UID ( next ) ) . ebb_start ) ) && earliest_bb_end > <NUM_LIT> ) { int cycles = earliest_bb_end - prev_clock ; if ( cycles > <NUM_LIT> ) { prev = emit_nop_after ( cycles - <NUM_LIT> , prev ) ; insn_set_clock ( prev , prev_clock + prev_implicit_nops + <NUM_LIT> ) ; }


<s> void <ISA_LIT>MachineFunctionInfo :: anchor ( ) {


<s> const SDLoc & dl ( Op ) ; auto * LoadN = cast < LoadSDNode > ( Op . getNode ( ) ) ; assert ( LoadN -> isUnindexed ( ) && <STR_LIT> ) ; assert ( LoadN -> getMemoryVT ( ) . getVectorElementType ( ) != <STR_LIT> && <STR_LIT> ) ; SDValue Chain = LoadN -> getChain ( ) ; SDValue Base = LoadN -> getBasePtr ( ) ; SDValue Offset = DAG . getUNDEF ( <STR_LIT> ) ; MVT ResTy = ty ( Op ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; unsigned ResLen = ResTy . getStoreSize ( ) ; assert ( ResLen < HwLen && <STR_LIT> ) ; MVT BoolTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue Mask = getInstr ( <STR_LIT> , dl , BoolTy , { DAG . getConstant ( ResLen , dl , <STR_LIT> ) } , DAG ) ; MVT LoadTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto * MemOp = MF . getMachineMemOperand ( LoadN -> getMemOperand ( ) , <NUM_LIT> , HwLen ) ; SDValue Load = DAG . getMaskedLoad ( LoadTy , dl , Chain , Base , Offset , Mask , DAG . getUNDEF ( LoadTy ) , LoadTy , MemOp , <STR_LIT> , <STR_LIT> , false ) ;

SDValue Value = opCastElem ( Load , ResTy . getVectorElementType ( ) , DAG ) ;


<s> return __builtin_mve_vcmpneq_v16qi ( ( int8x16_t ) __a , ( int8x16_t ) __b ) ;


<s> putc ( '$' , file ) ; assemble_name ( file , fnname ) ; fputs ( <STR_LIT> , file ) ; } } if ( TARGET_ABI_OPEN_VMS && ! TREE_PUBLIC ( decl ) && DECL_CONTEXT ( decl ) && ! TYPE_P ( DECL_CONTEXT ( decl ) ) && TREE_CODE ( DECL_CONTEXT ( decl ) ) != TRANSLATION_UNIT_DECL ) { strcpy ( tramp_label , fnname ) ; strcat ( tramp_label , <STR_LIT> ) ; ASM_OUTPUT_LABEL ( file , tramp_label ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } strcpy ( entry_label , fnname ) ; if ( TARGET_ABI_OPEN_VMS ) strcat ( entry_label , <STR_LIT> ) ; ASM_OUTPUT_LABEL ( file , entry_label ) ; inside_function = TRUE ; if ( TARGET_ABI_OPEN_VMS ) fprintf ( file , <STR_LIT> , vms_base_regno ) ; if ( TARGET_ABI_OSF && TARGET_IEEE_CONFORMANT && ! flag_inhibit_size_directive ) { fputs ( <STR_LIT> , file ) ; } alpha_auto_offset = - frame_size + crtl -> args . pretend_args_size ; alpha_arg_offset = - frame_size + <NUM_LIT> ; if ( TARGET_ABI_OPEN_VMS ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , vms_unwind_regno , frame_size >= max_frame_size ? <NUM_LIT> : frame_size , reg_offset ) ; else if ( ! flag_inhibit_size_directive ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , ( frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) , frame_size >= max_frame_size ? <NUM_LIT> : frame_size , crtl -> args . pretend_args_size ) ; if ( TARGET_ABI_OPEN_VMS ) { if ( imask ) fprintf ( file , <STR_LIT> , imask & ~ ( <NUM_LIT> << REG_RA ) ) ; if ( fmask ) fprintf ( file , <STR_LIT> , fmask ) ; if ( alpha_procedure_type == PT_REGISTER ) fprintf ( file , <STR_LIT> , vms_save_fp_regno ) ; }

else if ( ! flag_inhibit_size_directive ) {


<s> emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , <NUM_LIT> ) , gen_raw_REG ( SImode , A7_REG ) ) ) ; break ; case SFmode : emit_insn ( gen_movsf_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case SImode : emit_insn ( gen_movsi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case HImode : emit_insn ( gen_movhi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case QImode : emit_insn ( gen_movqi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; default : gcc_unreachable ( ) ; } cfun -> machine -> set_frame_ptr_insn = emit_insn ( gen_set_frame_ptr ( ) ) ; if ( mode == DFmode || mode == DImode ) emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , <NUM_LIT> ) , gen_rtx_REG ( SImode , A7_REG - <NUM_LIT> ) ) ) ; entry_insns = get_insns ( ) ; end_sequence ( ) ; if ( cfun -> machine -> vararg_a7 ) { cfun -> machine -> vararg_a7_copy = entry_insns ; } else {


<s> int64_t Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm == <STR_LIT> ( MI -> getOpcode ( ) ) ) return ; O << <STR_LIT> << Imm ;


<s> void addMemNoOffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ;


<s> assert ( WaitingQueues . count ( MI ) && <STR_LIT> ) ;

WaitingQueues . find ( MI ) -> getSecond ( ) . push_back ( WaitingForMI ) ;


<s> auto ExtendVecSize = [ & DAG ] ( const SDLoc & DL , SDValue N , unsigned Size ) { EVT SrcVT = N . getValueType ( ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT . getScalarType ( ) , Size / SrcVT . getScalarSizeInBits ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ( Size / SrcVT . getSizeInBits ( ) , DAG . getUNDEF ( SrcVT ) ) ; Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , DstVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( VT . is512BitVector ( ) && Subtarget . useAVX512Regs ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; Opcode = getOpcode_EXTEND_VECTOR_INREG ( Opcode ) ; return DAG . getNode ( Opcode , DL , VT , ExOp ) ; } auto SplitAndExtendInReg = [ & ] ( unsigned SplitSize ) {

unsigned NumVecs = VT . getSizeInBits ( ) / SplitSize ;


<s> DW = getAnalysisIfAvailable < DwarfWriter > ( ) ;


<s> return Op . getNode ( ) -> getFlags ( ) . hasApproximateFuncs ( ) ;


<s> unsigned <ISA_LIT>64_ELFTargetObjectFile :: getTTypeEncoding ( ) const { CodeModel :: Model Model = TM . getCodeModel ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) return DW_EH_PE_indirect | DW_EH_PE_pcrel | ( Model == CodeModel :: Small || Model == CodeModel :: Medium ? DW_EH_PE_sdata4 : DW_EH_PE_sdata8 ) ;

if ( Model == CodeModel :: Small ) return DW_EH_PE_udata4 ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } }


<s> selected_tune = tmp_cpu ; explicit_tune_core = selected_tune -> ident ; selected_arch = & all_architectures [ tmp_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , pragma_or_attr ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str , pragma_or_attr ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> , str , pragma_or_attr ) ; break ; default :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> llvm_unreachable ( <STR_LIT> ) ; return isSSrcB32 ( ) ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( Is<ISA_LIT>64 ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( OptLevel >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ;


<s> if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , Load . getDebugLoc ( ) , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Ops . clear ( ) ; Ops . push_back ( NewChain ) ; } for ( unsigned i = <NUM_LIT> , e = OrigChain . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( OrigChain . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( OrigChain , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; CurDAG -> UpdateNodeOperands ( Load , Call . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ; Ops . clear ( ) ; Ops . push_back ( SDValue ( Load . getNode ( ) , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Call . getNode ( ) -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Call . getOperand ( i ) ) ;

CurDAG -> UpdateNodeOperands ( Call , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;


<s> case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : prefix = one_only ? <STR_LIT> : <STR_LIT> ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( prefix ) { const char * name , * linkonce ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = targetm . strip_name_encoding ( name ) ; linkonce = one_only ? <STR_LIT> : <STR_LIT> ; string = ACONCAT ( ( linkonce , prefix , <STR_LIT> , name , NULL ) ) ; set_decl_section_name ( decl , string ) ; return ; } }

default_unique_section ( decl , reloc ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( EltVT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { EltVT = <STR_LIT> ; EVT CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , VT . getVectorNumElements ( ) ) ; Value = DAG . getBitcast ( CastVT , Value ) ; } SDValue Extract = DAG . getNode ( <STR_LIT> , DL , EltVT , Value , VecIndex ) ;

return DAG . getStore ( MS -> getChain ( ) , DL , Extract , Addr , MS -> getPointerInfo ( ) . getWithOffset ( Offset ) , Alignment , MS -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) ) ; BaseReg = <STR_LIT> ; continue ; } bool HasCCOut = true ; if ( BaseReg == <STR_LIT> ) { if ( DestReg == <STR_LIT> && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) ) ; NumBytes = <NUM_LIT> ; continue ; } Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else { unsigned RotAmt = countLeadingZeros ( ThisVal ) ; ThisVal = ThisVal & <STR_LIT> ( <NUM_LIT> , RotAmt ) ; NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; } } else { assert ( DestReg != <STR_LIT> && BaseReg != <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> ( NumBytes ) != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ;


<s>
}
O
<<
TAI
->
getCOMMDirective
(
)
<<
name
<<
','
<<
Size
;
if
(
TAI
->
getCOMMDirectiveTakesAlignment
(
)
)
O
<<
','
<<
(
TAI
->
getAlignmentIsInBytes
(
)
(
<NUM_LIT>
<<
Align
)
:
Align
)
;
}
if
(
VerboseAsm
)
{
O
<<
<STR_LIT>
<<
TAI
->
getCommentString
(
)
<<
' '
;
PrintUnmangledNameSafely
(
GVar
,
O
)
;
}
O
<<
'\n'
;
return
;
}
}
switch
(
GVar
->
getLinkage
(
)
)
{
case
GlobalValue
::
CommonLinkage
:
case
GlobalValue
::
LinkOnceAnyLinkage
:
case
GlobalValue
::
LinkOnceODRLinkage
:
case
GlobalValue
::
WeakAnyLinkage
:
case
GlobalValue
::
WeakODRLinkage
:
if
(
Subtarget
->
isTargetDarwin
(
)
)
{
O
<<
<STR_LIT>
<<
name
<<
'\n'
<<
TAI
->
getWeakDefDirective
(
)
<<
name
<<
'\n'
;
}
else
if
(
Subtarget
->
isTargetCygMing
(
)
)
{
O
<<
<STR_LIT>
<<
name
<<
<STR_LIT>
<STR_LIT>
;
}
else
{
O
<<
<STR_LIT>
<<
name
<<
'\n'
;
}
break
;
case
GlobalValue
::
DLLExportLinkage
:
case
GlobalValue
::
AppendingLinkage
:
case
GlobalValue
::
ExternalLinkage
:
O
<<
<STR_LIT>
<<
name
<<
'\n'
;
case
GlobalValue
::
PrivateLinkage
:
case
GlobalValue
::
InternalLinkage
:
break
;
default
:
assert
(
<NUM_LIT>
&&
<STR_LIT>
)
;
}
EmitAlignment
(
Align
,
GVar
)
;
O
<<
name
<<
<STR_LIT>
;
if
(
VerboseAsm
)
{
O
<<
name
<<
<STR_LIT>
<<
TAI
->
getCommentString
(
)
<<
' '
;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CallConv ) const {


<s> Subtarget = & MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> return getModifiers ( ) . hasModifiers ( ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT SrcVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Src = convertToScalableVector ( SrcVT , Src , DAG , Subtarget ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ZeroSplat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Zero , VL ) ; SDValue SplatValue = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> , DL , XLenVT ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatValue , VL ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , Splat , ZeroSplat , VL ) ; if ( ! VT . isFixedLengthVector ( ) ) return Result ; return convertFromScalableVector ( VT , Result , DAG , Subtarget ) ;


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( VT , Mask , RepeatedMask ) ) { if ( isSingleInputShuffleMask ( Mask ) ) { unsigned Opc = VT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; } for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , VT , RepeatedMask , V1 , V2 , DAG ) ; } if ( SDValue Op = lowerVectorShuffleWithVALIGN ( DL , VT , Mask , V1 , V2 , DAG ) ) return Op ; return lowerVectorShuffleWithPERMV ( DL , VT , Mask , V1 , V2 , DAG ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo ) ; <ISA_LIT>CCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getValVT ( ) , Val ) ;


<s> static bool containsOnlyConstantData ( const Constant * C ) { if ( isa < ConstantData > ( C ) ) return true ; if ( isa < GlobalValue > ( C ) || isa < BlockAddress > ( C ) || isa < ConstantExpr > ( C ) ) return false ; return all_of ( C -> operands ( ) , [ ] ( const Use & U ) { return containsOnlyConstantData ( cast < Constant > ( & U ) ) ;


<s> OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; } if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; GlobalsEmitted = false ;


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true , true ) ;


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & C , MCAsmBackend & AB , raw_ostream & OS , MCCodeEmitter * CE , bool RelaxAll ) {

<ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , AB , CE , OS ) ;


<s> machine_mode inner_mode = GET_MODE ( inner_source ) ; if ( mode == SImode && inner_mode == SFmode ) { emit_insn ( gen_movsi_from_sf ( dest , inner_source ) ) ; return true ; } if ( mode == SFmode && inner_mode == SImode ) {

emit_insn ( gen_movsf_from_si ( dest , inner_source ) ) ;


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;

assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ;


<s> bool HasAnyUndefs ; if ( ! Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! IsLittleEndian ) ) return false ; Imm = SplatValue ; return true ;


<s> getRootMetadata ( <STR_LIT> ) = HSAMetadataDoc -> getNode ( TargetID . toString ( ) , true ) ;


<s> } } if ( ConstVec . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { BuildVectorSDNode * BCN = dyn_cast < BuildVectorSDNode > ( ConstVec . getNode ( ) ) ; assert ( BCN != <NUM_LIT> && <STR_LIT> ) ; APInt APSplatBits , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; unsigned minSplatBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) && minSplatBits <= SplatBitSize ) { uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; SDValue tc = DAG . getTargetConstant ( SplatBits & <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > tcVec ; tcVec . assign ( <NUM_LIT> , tc ) ;

return DAG . getNode ( Op . getNode ( ) -> getOpcode ( ) , dl , VT , Arg , DAG . getNode ( <STR_LIT> , dl , VT , & tcVec [ <NUM_LIT> ] , tcVec . size ( ) ) ) ;


<s> } emit_move_insn ( large , two31 ) ; emit_move_insn ( zero_or_two31 , MEM_P ( two31 ) ? large : two31 ) ; x = gen_rtx_fmt_ee ( LE , vecmode , large , value ) ; emit_insn ( gen_rtx_SET ( large , x ) ) ; x = gen_rtx_AND ( vecmode , zero_or_two31 , large ) ; emit_insn ( gen_rtx_SET ( zero_or_two31 , x ) ) ; x = gen_rtx_MINUS ( vecmode , value , zero_or_two31 ) ; emit_insn ( gen_rtx_SET ( value , x ) ) ; large = gen_rtx_REG ( V4SImode , REGNO ( large ) ) ; emit_insn ( gen_ashlv4si3 ( large , large , GEN_INT ( <NUM_LIT> ) ) ) ; x = gen_rtx_REG ( V4SImode , REGNO ( value ) ) ; if ( vecmode == V4SFmode ) emit_insn ( gen_fix_truncv4sfv4si2 ( x , value ) ) ;

else emit_insn ( gen_sse2_cvttpd2dq ( x , value ) ) ;


<s> Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ;

return MCOperand :: CreateExpr ( Expr ) ;


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo ;


<s> void <ISA_LIT>LowerControlFlowPass :: Skip ( MachineInstr & From , MachineOperand & To ) { if ( ! shouldSkip ( * From . getParent ( ) -> succ_begin ( ) , To . getMBB ( ) ) ) return ; DebugLoc DL = From . getDebugLoc ( ) ; BuildMI ( * From . getParent ( ) , & From , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( To ) . addReg ( <STR_LIT> ) ;


<s> break ; } } } } if ( ! Done && MatchAddress ( Addr , AM , false ) ) return false ; DOUT << <STR_LIT> ; DEBUG ( AM . dump ( ) ) ; EVT VT = Addr . getValueType ( ) ; if ( AM . BaseType == <STR_LIT> ) {

if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ;


<s> IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) ; STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( STI -> getInstrInfo ( ) ) ; if ( IsPIC && ABI . IsO32 ( ) && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( MF , TII ) ; MFp = & MF ; ForceLongBranchFirstPass = ForceLongBranch ; bool longBranchChanged = handlePossibleLongBranch ( ) ; bool forbiddenSlotChanged = handleForbiddenSlot ( ) ;

bool fpuDelaySlotChanged = handleFPUDelaySlot ( ) ;


<s> const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; for ( const MachineOperand & MO : MI -> defs ( ) ) Returns . push_back ( getType ( MRI . getRegClass ( MO . getReg ( ) ) ) ) ; for ( const MachineOperand & MO : MI -> explicit_uses ( ) ) if ( MO . isReg ( ) ) Params . push_back ( getType ( MRI . getRegClass ( MO . getReg ( ) ) ) ) ; if ( <STR_LIT> ( MI -> getOpcode ( ) ) ) Params . pop_back ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) getFunctionReturns ( MI , Returns ) ; MCOp = lowerTypeIndexOperand ( std :: move ( Returns ) , std :: move ( Params ) ) ; break ; } else if ( Info . OperandType == <STR_LIT> ) { auto BT = static_cast < <STR_LIT> > ( MO . getImm ( ) ) ; assert ( BT != <STR_LIT> :: Invalid ) ; if ( BT == <STR_LIT> :: Multivalue ) { SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; getFunctionReturns ( MI , Returns ) ; MCOp = lowerTypeIndexOperand ( std :: move ( Returns ) , SmallVector < <STR_LIT> , <NUM_LIT> > ( ) ) ; break ; } } else if ( Info . OperandType == <STR_LIT> ) { assert ( static_cast < <STR_LIT> > ( MO . getImm ( ) ) != <STR_LIT> :: Invalid ) ;


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( ) ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;

Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset ) ;


<s> unsigned BitsAboveLowBit = <NUM_LIT> & ( - LowBit << <NUM_LIT> ) ; mask ^= BitsAboveLowBit ; } Inst . addOperand ( MCOperand :: createImm ( pred ) ) ; Inst . addOperand ( MCOperand :: createImm ( mask ) ) ; return S ;


<s> unsigned <ISA_LIT>ConstantIslands :: GetOffsetOf ( MachineInstr * MI ) const { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned Offset = BBOffsets [ MBB -> getNumber ( ) ] ; if ( isThumb && MI -> getOpcode ( ) == <STR_LIT> && ( Offset % <NUM_LIT> != <NUM_LIT> || HasInlineAsm ) ) Offset += <NUM_LIT> ;

for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) ; ; ++ I ) {


<s> void <ISA_LIT>InstPrinter :: printJumpTable ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {

assert ( MI -> getOperand ( OpNo ) . isExpr ( ) && <STR_LIT> ) ;


<s> if ( ! imported [ ( int ) code ] ) { imported [ ( int ) code ] = <NUM_LIT> ;


<s> } if ( dump_file ) fprintf ( dump_file , <STR_LIT> , t [ <NUM_LIT> ] , t [ <NUM_LIT> ] , t [ <NUM_LIT> ] , t [ <NUM_LIT> ] ) ; return MAX ( ( t [ <NUM_LIT> ] + t [ <NUM_LIT> ] + t [ <NUM_LIT> ] + <NUM_LIT> ) / <NUM_LIT> , MAX ( t [ <NUM_LIT> ] , t [ <NUM_LIT> ] ) ) ;


<s> static DecodeStatus DecodeFPR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ;

unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ;


<s> if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; } if ( VTIsi1 && SrcReg != <STR_LIT> ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , SrcReg , false , <NUM_LIT> ) ; assert ( ANDReg && <STR_LIT> ) ; SrcReg = ANDReg ; } const MCInstrDesc & II = TII . get ( Opc ) ; SrcReg = constrainOperandRegClass ( II , SrcReg , II . getNumDefs ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg ) ;

addLoadStoreOperands ( Addr , MIB , MachineMemOperand :: MOStore , ScaleFactor , MMO ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) , true , false ) ;


return __builtin_mve_vrev16q_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a , __p ) ;


<s> static void v850_setup_incoming_varargs ( CUMULATIVE_ARGS * ca , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_arg_size ATTRIBUTE_UNUSED , int second_time ATTRIBUTE_UNUSED ) {

ca -> anonymous_args = ( ! TARGET_GHS ? <NUM_LIT> : <NUM_LIT> ) ;


<s> assert ( ( isa < LoadInst > ( VecInst ) || isa < ShuffleVectorInst > ( VecInst ) ) && <STR_LIT> ) ; Type * VecWidth = VecInst -> getType ( ) ; ( void ) VecWidth ; assert ( VecWidth -> isVectorTy ( ) && DL . getTypeSizeInBits ( VecWidth ) >= DL . getTypeSizeInBits ( SubVecTy ) * NumSubVectors && <STR_LIT> ) ; if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , Indices [ i ] , SubVecTy -> getVectorNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ; unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ; if ( VecLength == <NUM_LIT> || VecLength == <NUM_LIT> ) { VecBaseTy = VectorType :: get ( Type :: getInt8Ty ( LI -> getContext ( ) ) , <NUM_LIT> ) ; VecBasePtrTy = VecBaseTy -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ; VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; NumLoads = NumSubVectors * ( VecLength / <NUM_LIT> ) ; } else { VecBaseTy = SubVecTy ;


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cmpgt_pi16 ( __m64 __m1 , __m64 __m2 ) { __vector signed short a , b , c ; a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = ( __vector signed short ) vec_cmpgt ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> ) ) ; __m64_union m1 , m2 , res ;


<s> const bool Using<ISA_LIT>32 = RC == & <STR_LIT> ; unsigned Rt = RegInfo . createVirtualRegister ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) , Rt ) ;

for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) MIB . add ( MI . getOperand ( i ) ) ;


<s> unsigned SPReg ; int Offset = getFrameIndexReferenceFromSP ( MF , Info . PSPSymFrameIdx , SPReg ) ;


<s> <STR_LIT> AMDGPUEvergreenDevice ( ) {


<s> static unsigned getOpcodeForFMAIntrinsic ( unsigned IntNo ) { switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> :


<s> if ( MO . isImm ( ) ) return ( getMachineOpValue ( MI , MO , Fixups , STI ) & <NUM_LIT> ) | RegBits ; Fixups . push_back ( MCFixup :: create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return RegBits ;


<s> <ISA_LIT>ExpandPseudo ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , TII ( tm . getInstrInfo ( ) ) {


<s> static bool alpha_split_complex_arg ( tree type ) { return TYPE_MODE ( type ) != TCmode ;


<s> if ( ( INTVAL ( op ) >> <NUM_LIT> ) != <NUM_LIT> && ( INTVAL ( op ) >> <NUM_LIT> ) != - <NUM_LIT> && mask64_operand ( op , mode ) ) return <NUM_LIT> ; else return num_insns_constant_wide ( INTVAL ( op ) ) ; case CONST_WIDE_INT : { int i ; int ins = CONST_WIDE_INT_NUNITS ( op ) - <NUM_LIT> ; for ( i = <NUM_LIT> ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) ins += num_insns_constant_wide ( CONST_WIDE_INT_ELT ( op , i ) ) ; return ins ; } case CONST_DOUBLE : if ( mode == SFmode || mode == SDmode ) { long l ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL32 ( rv , l ) ; else REAL_VALUE_TO_TARGET_SINGLE ( rv , l ) ; return num_insns_constant_wide ( ( HOST_WIDE_INT ) l ) ; } long l [ <NUM_LIT> ] ; REAL_VALUE_TYPE rv ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , op ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL64 ( rv , l ) ; else REAL_VALUE_TO_TARGET_DOUBLE ( rv , l ) ; high = l [ WORDS_BIG_ENDIAN == <NUM_LIT> ] ; low = l [ WORDS_BIG_ENDIAN != <NUM_LIT> ] ; if ( TARGET_32BIT ) return ( num_insns_constant_wide ( low ) + num_insns_constant_wide ( high ) ) ; else { if ( ( high == <NUM_LIT> && low >= <NUM_LIT> ) || ( high == - <NUM_LIT> && low < <NUM_LIT> ) ) return num_insns_constant_wide ( low ) ; else if ( mask64_operand ( op , mode ) ) return <NUM_LIT> ; else if ( low == <NUM_LIT> ) return num_insns_constant_wide ( high ) + <NUM_LIT> ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + <NUM_LIT> ) ; }


<s> PreAnalyzeReturnForF128 ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ;


<s> std :: swap ( Idx1L , Idx1H ) ; } if ( Idx0L != <NUM_LIT> * i || Idx1L != <NUM_LIT> * i + <NUM_LIT> || Idx0H != <NUM_LIT> * i + <NUM_LIT> || Idx1H != <NUM_LIT> * i + <NUM_LIT> ) return SDValue ( ) ; if ( ! Mul ) { Mul = Op0L -> getOperand ( <NUM_LIT> ) ; if ( Mul -> getOpcode ( ) != <STR_LIT> || Mul . getValueType ( ) . getVectorNumElements ( ) != <NUM_LIT> * e ) return SDValue ( ) ; } if ( Mul != Op0L -> getOperand ( <NUM_LIT> ) || Mul != Op1L -> getOperand ( <NUM_LIT> ) || Mul != Op0H -> getOperand ( <NUM_LIT> ) || Mul != Op1H -> getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; } ShrinkMode Mode ; if ( ! canReduceVMulWidth ( Mul . getNode ( ) , DAG , Mode ) || Mode == ShrinkMode :: MULU16 ) return SDValue ( ) ; auto PMADDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { EVT InVT = Ops [ <NUM_LIT> ] . getValueType ( ) ; assert ( InVT . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( InVT == Ops [ <NUM_LIT> ] . getValueType ( ) && <STR_LIT> ) ; EVT ResVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) / <NUM_LIT> ) ;

EVT TruncVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ;


<s> bool isDPRRegList ( ) const { return Kind == k_DPRRegisterList ;


<s> assert ( ImpDefSCC . getReg ( ) == <STR_LIT> && ImpDefSCC . isDef ( ) ) ; unsigned CopyReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * CopyExec = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , CopyReg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; unsigned Tmp = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * And = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addReg ( CopyReg ) . addReg ( Cond . getReg ( ) ) ; setImpSCCDefDead ( * And , true ) ; MachineInstr * Xor = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , SaveExecReg ) . addReg ( Tmp ) . addReg ( CopyReg ) ; setImpSCCDefDead ( * Xor , ImpDefSCC . isDead ( ) ) ; MachineInstr * SetExec = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Tmp , RegState :: Kill ) ; MachineInstr * NewBr = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ;


<s> if ( imode == PSImode && mode == HImode && byte == <NUM_LIT> ) rv = gen_rtx_SUBREG ( mode , ireg , byte ) ; else rv = simplify_gen_subreg ( mode , ireg , imode , byte ) ; } else if ( GET_CODE ( r ) == MEM ) rv = adjust_address ( r , mode , byte ) ; else if ( GET_CODE ( r ) == SYMBOL_REF && ( byte == <NUM_LIT> || byte == <NUM_LIT> ) && mode == HImode ) { rv = gen_rtx_ZERO_EXTRACT ( HImode , r , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> * byte ) ) ; rv = gen_rtx_CONST ( HImode , r ) ;


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; return MAI ;


<s> return legalizeInsertVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return legalizeShuffleVector ( MI , MRI , B ) ; case TargetOpcode :: G_F<ISA_LIT>N : case TargetOpcode :: G_FCOS : return legalizeSinCos ( MI , MRI , B ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeGlobalValue ( MI , MRI , B ) ; case TargetOpcode :: G_LOAD : return legalizeLoad ( MI , MRI , B , Observer ) ; case TargetOpcode :: G_FMAD : return legalizeFMad ( MI , MRI , B ) ; case TargetOpcode :: G_FDIV : return legalizeFDIV ( MI , MRI , B ) ; case TargetOpcode :: G_UDIV : case TargetOpcode :: G_UREM : return legalizeUDIV_UREM ( MI , MRI , B ) ; case TargetOpcode :: G_SDIV : case TargetOpcode :: G_SREM : return legalizeSDIV_SREM ( MI , MRI , B ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpXChg ( MI , MRI , B ) ; case TargetOpcode :: G_FLOG : return legalizeFlog ( MI , B , <NUM_LIT> / numbers :: log2ef ) ; case TargetOpcode :: G_FLOG10 : return legalizeFlog ( MI , B , numbers :: ln2f / numbers :: ln10f ) ; case TargetOpcode :: G_FEXP : return legalizeFExp ( MI , B ) ; case TargetOpcode :: G_FPOW : return legalizeFPow ( MI , B ) ; case TargetOpcode :: G_FFLOOR :

return legalizeFFloor ( MI , MRI , B ) ;


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm ) ; return IsConstantImm && isShiftedInt < N , S > ( Imm ) ;


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & Regs = Subtarget . getSpecialRegisters < <ISA_LIT>XPLINK64Registers > ( ) ; unsigned LowGPR = <NUM_LIT> ; int LowOffset = INT32_MAX ; unsigned HighGPR = LowGPR ; int HighOffset = - <NUM_LIT> ; unsigned RegSP = Regs . getStackPointerRegister ( ) ; auto & GRRegClass = <STR_LIT> ; const unsigned RegSize = <NUM_LIT> ; auto ProcessCSI = [ & ] ( std :: vector < CalleeSavedInfo > & CSIList ) { for ( auto & CS : CSIList ) { unsigned Reg = CS . getReg ( ) ; int Offset = RegSpillOffsets [ Reg ] ; if ( Offset >= <NUM_LIT> ) { if ( GRRegClass . contains ( Reg ) ) { if ( LowOffset > Offset ) { LowOffset = Offset ; LowGPR = Reg ; } if ( Offset > HighOffset ) { HighOffset = Offset ; HighGPR = Reg ; } } int FrameIdx = MFFrame . CreateFixedSpillStackObject ( RegSize , Offset ) ;


<s> else type = build_vector_type ( eltype , GET_MODE_NUNITS ( mode ) ) ; type = build_distinct_type_copy ( type ) ; SET_TYPE_STRUCTURAL_EQUALITY ( type ) ; tree mangled_name = get_identifier ( arm_simd_types [ i ] . mangle ) ; tree value = tree_cons ( NULL_TREE , mangled_name , NULL_TREE ) ; TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , value , TYPE_ATTRIBUTES ( type ) ) ; arm_simd_types [ i ] . itype = type ; } tdecl = add_builtin_type ( arm_simd_types [ i ] . name , arm_simd_types [ i ] . itype ) ; TYPE_NAME ( arm_simd_types [ i ] . itype ) = tdecl ; SET_TYPE_STRUCTURAL_EQUALITY ( arm_simd_types [ i ] . itype ) ; } make_signed_type ( GET_MODE_PRECISION ( mode ) ) ; arm_simd_intOI_type_node = AARCH_BUILD_SIGNED_TYPE ( OImode ) ; arm_simd_intEI_type_node = AARCH_BUILD_SIGNED_TYPE ( EImode ) ; arm_simd_intCI_type_node = AARCH_BUILD_SIGNED_TYPE ( CImode ) ; arm_simd_intXI_type_node = AARCH_BUILD_SIGNED_TYPE ( XImode ) ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intEI_type_node ) ; TYPE_NAME ( arm_simd_intEI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intOI_type_node ) ; TYPE_NAME ( arm_simd_intOI_type_node ) = tdecl ; tdecl = add_builtin_type ( <STR_LIT> , arm_simd_intCI_type_node ) ;

TYPE_NAME ( arm_simd_intCI_type_node ) = tdecl ;


<s> unsigned AddrReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( AddrReg ) ) ; const IndirectBrInst * IB = cast < IndirectBrInst > ( I ) ; for ( const BasicBlock * SuccBB : IB -> successors ( ) ) FuncInfo . MBB -> addSuccessor ( FuncInfo . MBBMap [ SuccBB ] ) ; return true ;


<s> void <ISA_LIT>SpeculativeLoadHardeningPass :: getAnalysisUsage ( AnalysisUsage & AU ) const {

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> void <ISA_LIT>AsmPrinter :: emitPseudoIndirectBranch ( MCStreamer & OutStreamer , const MachineInstr * MI ) { bool HasLinkReg = false ; bool InMicro<ISA_LIT>Mode = Subtarget -> inMicro<ISA_LIT>Mode ( ) ; MCInst TmpInst0 ; if ( Subtarget -> has<ISA_LIT>64r6 ( ) ) { TmpInst0 . setOpcode ( <STR_LIT> ) ; HasLinkReg = true ; } else if ( Subtarget -> has<ISA_LIT>32r6 ( ) ) { if ( InMicro<ISA_LIT>Mode ) TmpInst0 . setOpcode ( <STR_LIT> ) ;


<s> if ( ! LaneC || LaneC -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ; } LoadSDNode * LoadSDN = cast < LoadSDNode > ( LD ) ; EVT MemVT = LoadSDN -> getMemoryVT ( ) ; if ( MemVT != VT . getVectorElementType ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) continue ; if ( * UI != N ) return SDValue ( ) ; } SDValue Addr = LD -> getOperand ( <NUM_LIT> ) ; SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) ) continue ;

SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ;


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) : FastISel ( FuncInfo , LibInfo ) , TM ( FuncInfo . MF -> getTarget ( ) ) , TII ( * TM . getInstrInfo ( ) ) , TLI ( * TM . getTargetLowering ( ) ) , <ISA_LIT>SubTarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , Context ( & FuncInfo . Fn -> getContext ( ) ) {


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , CTX ( ctx ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {

if ( Subtarget -> is64Bit ( ) ) return LowerFormalArguments_64 ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ;


<s> insn_length = get_attr_length ( insn ) ; long_jump_p = ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ? true : false ; r5_p = ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ? true : false ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; switch ( code ) {


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ; case AtomicRMWInst :: Max : return <STR_LIT> ; case AtomicRMWInst :: Min : return <STR_LIT> ; case AtomicRMWInst :: UMax : return <STR_LIT> ; case AtomicRMWInst :: UMin : return <STR_LIT> ; } } if ( XLen == <NUM_LIT> ) { switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Xchg : return <STR_LIT> ; case AtomicRMWInst :: Add : return <STR_LIT> ; case AtomicRMWInst :: Sub : return <STR_LIT> ; case AtomicRMWInst :: Nand : return <STR_LIT> ;


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override { if ( VT . getVectorElementType ( ) . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;


<s> bool <ISA_LIT>FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == <STR_LIT> ) return false ;


<s> using namespace TargetOpcode ; MIRBuilder . setInstr ( MI ) ;


<s> SmallVector < SDValue , <NUM_LIT> > LUTVec ; for ( int i = <NUM_LIT> ; i < NumByteElts ; ++ i ) LUTVec . push_back ( DAG . getConstant ( LUT [ i % <NUM_LIT> ] , DL , <STR_LIT> ) ) ; SDValue InRegLUT = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , LUTVec ) ; SmallVector < SDValue , <NUM_LIT> > Mask0F ( NumByteElts , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue M0F = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , Mask0F ) ; SmallVector < SDValue , <NUM_LIT> > Four ( NumByteElts , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FourV = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , Four ) ; SDValue HighNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , FourV ) ;

SDValue LowNibbles = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , In , M0F ) ;


<s> } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ; if ( isPositionIndependent ( ) ) TOp . setTargetFlags ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addOperand ( MCIL . LowerSymbolOperand ( TOp , TSym ) ) ) ; for ( unsigned I = sizeof UsedMask ; I -- > <NUM_LIT> ; ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; else EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> AddComment ( <STR_LIT> ) ;

recordSled ( CurSled , MI , SledKind :: TYPED_EVENT , <NUM_LIT> ) ;


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; int64_t Val = ~ MCE -> getValue ( ) & <NUM_LIT> ;

uint64_t encoding = <STR_LIT> ( Val , <NUM_LIT> ) ;


<s> if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > <NUM_LIT> ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] [ <NUM_LIT> ] , Regs ) ; } ) ) return false ;


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ;

TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ;


<s> return __builtin_ia32_vcvtph2psx256_mask ( __A , _mm256_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { assert ( false ) ; } } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOMod<ISA_LIT> ) ;


<s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName , CPUName , FS ) ;


<s> case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_SUB ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKSAVE ( Op , DAG ) ; case <STR_LIT> : return lowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return lowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return lowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerSIGN_EXTEND_VECTOR_INREG ( Op , DAG ) ;


<s> Register AddDefR = AddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UN = * I ; NodeAddr < StmtNode * > SN = UN . Addr -> getOwner ( * DFG ) ; MachineInstr * MI = SN . Addr -> getCode ( ) ; const MCInstrDesc & MID = MI -> getDesc ( ) ; if ( ( ! MID . mayLoad ( ) && ! MID . mayStore ( ) ) || HII -> getAddrMode ( * MI ) != <STR_LIT> || HII -> isHVXVec ( * MI ) ) return false ; MachineOperand BaseOp = MID . mayLoad ( ) ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; if ( ! BaseOp . isReg ( ) || BaseOp . getReg ( ) != AddDefR ) return false ; MachineOperand OffsetOp = MID . mayLoad ( ) ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; if ( ! OffsetOp . isImm ( ) ) return false ; int64_t newOffset = OffsetOp . getImm ( ) + AddMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isValidOffset ( MI , newOffset ) ) return false ; Register BaseReg = AddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isSafeToExtLR ( AddSN , AddMI , BaseReg , UNodeList ) ) return false ; } bool Changed = false ;


<s> return Kind == <STR_LIT> ? ELF :: R_386_GOT32X : ELF :: R_386_GOT32 ; case MCSymbolRefExpr :: VK_GOTOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_GOTOFF ; case MCSymbolRefExpr :: VK_TPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LE_32 ; case MCSymbolRefExpr :: VK_DTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LDO_32 ; case MCSymbolRefExpr :: VK_TLSGD : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GD ; case MCSymbolRefExpr :: VK_GOTTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_IE_32 ; case MCSymbolRefExpr :: VK_PLT : assert ( Type == RT32_32 ) ; return ELF :: R_386_PLT32 ; case MCSymbolRefExpr :: VK_INDNTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_IE ; case MCSymbolRefExpr :: VK_NTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LE ; case MCSymbolRefExpr :: VK_GOTNTPOFF : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_GOTIE ; case MCSymbolRefExpr :: VK_TLSLDM : assert ( Type == RT32_32 ) ; assert ( ! IsPCRel ) ; return ELF :: R_386_TLS_LDM ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; unsigned SP = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue StackPtr = DAG . getRegister ( SP , PtrVT ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ;

SDValue SaveSP = Op . getOperand ( <NUM_LIT> ) ;


<s> case EV4_IB1 : if ( in_use & EV4_IB1 ) goto done ; in_use |= EV4_IB1 ; break ; default : gcc_unreachable ( ) ; } len += <NUM_LIT> ; if ( GET_CODE ( insn ) == JUMP_INSN ) goto next_and_done ; next : insn = next_nonnote_insn ( insn ) ; if ( ! insn || ! INSN_P ( insn ) ) goto done ; if ( GET_MODE ( insn ) == TImode ) goto done ; if ( GET_CODE ( insn ) == CLOBBER || GET_CODE ( insn ) == USE ) goto next ; }


<s> static void aarch64_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , rtx model_rtx ) {

emit_insn ( gen_aarch64_load_exclusive ( mode , rval , mem , model_rtx ) ) ;


<s> } if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = <NUM_LIT> ; } if ( UNITS_PER_FP_ARG == <NUM_LIT> ) {

for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = <NUM_LIT> ;


<s> x = gen_rtx_VEC_MERGE ( mode , x , CONST0_RTX ( mode ) , const1_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; return true ; case V8HImode : case V16QImode : vsimode = V4SImode ; goto widen ; case V4HImode : case V8QImode : if ( ! mmx_ok ) return false ; vsimode = V2SImode ; goto widen ; widen :

var = convert_modes ( SImode , GET_MODE_INNER ( mode ) , var , true ) ;


<s> if ( ! Subtarget . hasAltivec ( ) ) return CSR_NoRegs_Altivec_RegMask ;

if ( Subtarget . isDarwin ( ) ) return CSR_NoRegs_Darwin_RegMask ;


<s> return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ? AtomicExpansionKind :: LLOnly : AtomicExpansionKind :: None ;


<s> const MachineInstr & mi = * miI ; if ( mi . readsRegister ( <STR_LIT> ) ) return false ; if ( mi . definesRegister ( <STR_LIT> ) ) break ; } if ( miI == BB -> end ( ) ) { for ( MachineBasicBlock :: succ_iterator sItr = BB -> succ_begin ( ) , sEnd = BB -> succ_end ( ) ; sItr != sEnd ; ++ sItr ) { MachineBasicBlock * succ = * sItr ; if ( succ -> isLiveIn ( <STR_LIT> ) ) return false ; } }

SelectItr -> addRegisterKilled ( <STR_LIT> , TRI ) ;


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 ; } else if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 ; } else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex ( ) ; return false ;


<s> RegisterTargetMachine < <ISA_LIT>LETargetMachine > X ( getThe<ISA_LIT>LETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>LETargetMachine > A ( getTheThumbLETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > B ( getTheThumbBETarget ( ) ) ; PassRegistry & Registry = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( Registry ) ;

initialize<ISA_LIT>LoadStoreOptPass ( Registry ) ;


<s> CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) {

unsigned Idx = ( FullSize - <NUM_LIT> - i ) ;


<s> if ( ! LIS -> hasInterval ( C . Reg ) ) return <NUM_LIT> ; LiveInterval & LI = LIS -> getInterval ( C . Reg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( C . Reg ) << <STR_LIT> ; C . MI -> dump ( ) ; LI . dump ( ) ) ; unsigned OrigStalls = computeStallCycles ( C . Reg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << OrigStalls << '\n' ) ; if ( ! OrigStalls ) return <NUM_LIT> ; struct BankStall { BankStall ( unsigned b , unsigned s ) : Bank ( b ) , Stalls ( s ) { } ; bool operator < ( const BankStall & RHS ) const { return Stalls > RHS . Stalls ; } unsigned Bank ; unsigned Stalls ; } ; SmallVector < BankStall , <NUM_LIT> > BankStalls ; for ( int Bank = <NUM_LIT> ; Bank < NUM_BANKS ; ++ Bank ) {

if ( C . FreeBanks & ( <NUM_LIT> << Bank ) ) {


<s> if ( offset > - <NUM_LIT> ) insn = emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( offset ) ) ) ; else { rtx tmpr = gen_rtx_REG ( DImode , <NUM_LIT> ) ; RTX_FRAME_RELATED_P ( emit_move_insn ( tmpr , GEN_INT ( offset ) ) ) = <NUM_LIT> ; insn = emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , tmpr ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else { if ( insn_const_int_ok_for_constraint ( offset , CONSTRAINT_L ) ) emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( offset ) ) ) ; else { rtx tmpr = gen_rtx_REG ( DImode , <NUM_LIT> ) ; emit_move_insn ( tmpr , GEN_INT ( offset ) ) ;


<s> int <ISA_LIT>FrameLowering :: getFrameIndexOffset ( const MachineFunction & MF , int FI ) const { const MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; int64_t Offset = ( MFFrame -> getObjectOffset ( FI ) + MFFrame -> getOffsetAdjustment ( ) ) ; Offset -= getOffsetOfLocalArea ( ) ; Offset += getAllocatedStackSize ( MF ) ;


<s> arg1 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST ) { tree inner_type = TREE_TYPE ( rtype ) ; tree_vector_builder n_elts ( rtype , VECTOR_CST_NELTS ( arg0 ) , <NUM_LIT> ) ; sparc_handle_vis_mul8x16 ( & n_elts , code , inner_type , arg0 , arg1 ) ; return n_elts . build ( ) ; } break ; case SPARC_BUILTIN_FPMERGE : arg0 = args [ <NUM_LIT> ] ; arg1 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST ) { tree_vector_builder n_elts ( rtype , <NUM_LIT> * VECTOR_CST_NELTS ( arg0 ) , <NUM_LIT> ) ; unsigned i ; for ( i = <NUM_LIT> ; i < VECTOR_CST_NELTS ( arg0 ) ; ++ i ) { n_elts . quick_push ( VECTOR_CST_ELT ( arg0 , i ) ) ; n_elts . quick_push ( VECTOR_CST_ELT ( arg1 , i ) ) ; } return n_elts . build ( ) ; } break ; case SPARC_BUILTIN_PDIST : case SPARC_BUILTIN_PDISTN : arg0 = args [ <NUM_LIT> ] ; arg1 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg0 ) ; STRIP_NOPS ( arg1 ) ; if ( code == SPARC_BUILTIN_PDIST ) { arg2 = args [ <NUM_LIT> ] ; STRIP_NOPS ( arg2 ) ; } else arg2 = integer_zero_node ; if ( TREE_CODE ( arg0 ) == VECTOR_CST && TREE_CODE ( arg1 ) == VECTOR_CST && TREE_CODE ( arg2 ) == INTEGER_CST ) { bool overflow = false ; widest_int result = wi :: to_widest ( arg2 ) ; widest_int tmp ; unsigned i ; for ( i = <NUM_LIT> ; i < VECTOR_CST_NELTS ( arg0 ) ; ++ i ) { tree e0 = VECTOR_CST_ELT ( arg0 , i ) ;


<s> void addRegPairOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned RegNo = getRegPair ( ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegNo ++ ) ) ;

Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ;


<s> return ( __m128i ) __builtin_ia32_psravq128_mask ( ( __v2di ) __X , ( __v2di ) __Y , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired ( ) ) { MIB . addReg ( Reg2 , getDefRegState ( true ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg2 ) , MachineMemOperand :: MOLoad , Size , Align ) ) ; } MIB . addReg ( Reg1 , getDefRegState ( true ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg1 ) , MachineMemOperand :: MOLoad , Size , Align ) ) ; if ( NeedsWinCFI ) InsertSEH ( MIB , TII , MachineInstr :: FrameDestroy ) ; } ; if ( ReverseCSRRestoreSeq ) for ( const RegPairInfo & RPI : reverse ( RegPairs ) ) EmitMI ( RPI ) ; else for ( const RegPairInfo & RPI : RegPairs ) EmitMI ( RPI ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ;


<s> DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ; if ( ! DF ) return nullptr ; Offset = <NUM_LIT> ; } for ( const MCFixup & F : DF -> getFixups ( ) ) { if ( F . getOffset ( ) != Offset ) continue ; switch ( ( unsigned ) F . getKind ( ) ) { default : continue ;


<s> qword q ; float f [ <NUM_LIT> ] ; } x ; x . f [ <NUM_LIT> ] = f ;


<s> auto III = Instructions . find ( & MI ) ; if ( III == Instructions . end ( ) ) continue ;

dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << PrintState ( III -> second . Needs ) << <STR_LIT> << PrintState ( III -> second . OutNeeds ) << '\n' ;


<s> bool <ISA_LIT>MCInstrInfo :: hasNewValue ( MCInstrInfo const & MCII , MCInst const & MCI ) {

const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ;


<s> if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; Destination = & MI . getOperand ( <NUM_LIT> ) ; Source = & MI . getOperand ( <NUM_LIT> ) ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ;


<s> return Op -> isLoad ( ) && Op -> getPseudoValue ( ) && Op -> getPseudoValue ( ) -> kind ( ) == PseudoSourceValue :: ConstantPool ;


<s> uint64_t Value = CE -> getValue ( ) ; return <STR_LIT> ( Value , Shift , RegWidth ) ;


<s> break ; case <STR_LIT> : NewCond = <STR_LIT> ; break ; case <STR_LIT> : NewCond = <STR_LIT> ; break ; case <STR_LIT> : NewCond = <STR_LIT> ; break ; case <STR_LIT> : NewCond = <STR_LIT> ; break ; case <STR_LIT> : NewCond = <STR_LIT> ; break ; case <STR_LIT> : NewCond = <STR_LIT> ; break ; case <STR_LIT> : NewCond = <STR_LIT> ;


<s> if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) < <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) + INTVAL ( XEXP ( x , <NUM_LIT> ) ) / <NUM_LIT> ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) + ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) - <NUM_LIT> ) / <NUM_LIT> ; } else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ! ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) > <NUM_LIT> && INTVAL ( XEXP ( x , <NUM_LIT> ) ) <= <NUM_LIT> ) ) { * total = COSTS_N_INSNS ( TARGET_COLDFIRE ? <NUM_LIT> : <NUM_LIT> ) ; return true ; } return false ; case MULT : if ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SIGN_EXTEND ) && GET_MODE ( x ) == SImode ) * total = COSTS_N_INSNS ( MULW_COST ) ; else if ( GET_MODE ( x ) == QImode || GET_MODE ( x ) == HImode ) * total = COSTS_N_INSNS ( MULW_COST ) ; else * total = COSTS_N_INSNS ( MULL_COST ) ; return true ; case DIV : case UDIV : case MOD : case UMOD : if ( GET_MODE ( x ) == QImode || GET_MODE ( x ) == HImode ) * total = COSTS_N_INSNS ( DIVW_COST ) ;

else if ( TARGET_CF_HWDIV ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder ) ; }


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>BaseRegisterInfo ( sti ) {


<s> return CreateReg ( Index , Str , RegKind_ACC , RegInfo , S , E , Parser ) ;


<s> return checkType ( N -> getSrcValue ( ) , <STR_LIT> ) ;


<s> auto CheckValueSize = [ TargetElemMaxSize ] ( Value * OffsetElem ) { ConstantInt * OConst = dyn_cast < ConstantInt > ( OffsetElem ) ; if ( ! OConst ) return false ; int SExtValue = OConst -> getSExtValue ( ) ; if ( SExtValue >= TargetElemMaxSize || SExtValue < <NUM_LIT> ) return false ; return true ; } ; if ( isa < FixedVectorType > ( ConstOff -> getType ( ) ) ) { for ( unsigned i = <NUM_LIT> ; i < TargetElemCount ; i ++ ) {

if ( ! CheckValueSize ( ConstOff -> getAggregateElement ( i ) ) ) return false ;


<s> assert ( StNode && StNode -> getOffset ( ) . isUndef ( ) && <STR_LIT> ) ; SDValue BasePtr = StNode -> getBasePtr ( ) ; if ( isa < FrameIndexSDNode > ( BasePtr . getNode ( ) ) ) { return Op ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; bool reseveCallFrame = TFI -> hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Opcode == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>CodePrinterPass ( raw_ostream & o , <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel , bool verbose ) { const <ISA_LIT>Subtarget * Subtarget = & tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isFlavorIntel ( ) ) {

return new <ISA_LIT>IntelAsmPrinter ( o , tm , tm . getTargetAsmInfo ( ) , OptLevel , verbose ) ;


<s> bool MachineConstEvaluator :: getCell ( const RegisterSubReg & R , const CellMap & Inputs , LatticeCell & RC ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( R . Reg ) ) return false ; const LatticeCell & L = Inputs . get ( R . Reg ) ; if ( ! R . SubReg ) { RC = L ;