<s> for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ) { MachineInstr * MI = & * I ; ++ I ; bool RemovedMI = false ; bool IsCopy = MI -> isCopy ( ) ; bool IsMoveImm = MI -> isMoveImmediate ( ) ; if ( IsCopy || IsMoveImm ) { MCPhysReg DefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MCPhysReg SrcReg = IsCopy ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ; int64_t SrcImm = IsMoveImm ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; if ( ! MRI -> isReserved ( DefReg ) && ( ( IsCopy && ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ) || IsMoveImm ) ) { for ( RegImm & KnownReg : KnownRegs ) { if ( KnownReg . Reg != DefReg && ! TRI -> isSuperRegister ( DefReg , KnownReg . Reg ) ) continue ; if ( IsCopy && KnownReg . Imm != <NUM_LIT> ) continue ; if ( IsMoveImm ) { if ( KnownReg . Imm != SrcImm ) continue ; MCPhysReg CmpReg = KnownReg . Reg ; if ( any_of ( MI -> implicit_operands ( ) , [ CmpReg ] ( MachineOperand & O ) { return ! O . isDead ( ) && O . isReg ( ) && O . isDef ( ) && O . getReg ( ) != CmpReg ; } ) ) continue ; } if ( IsCopy ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; else LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MI -> eraseFromParent ( ) ; Changed = true ; LastChange = I ; NumCopiesRemoved ++ ; UsedKnownRegs . insert ( KnownReg . Reg ) ; RemovedMI = true ; break ; } } } if ( RemovedMI ) continue ; for ( unsigned RI = <NUM_LIT> ; RI < KnownRegs . size ( ) ; ) if ( MI -> modifiesRegister ( KnownRegs [ RI ] . Reg , TRI ) ) { std :: swap ( KnownRegs [ RI ] , KnownRegs [ KnownRegs . size ( ) - <NUM_LIT> ] ) ;


<s> rtx function_expander :: get_fallback_value ( machine_mode mode , unsigned int nops , unsigned int merge_argno , unsigned int & argno ) { if ( pred == PRED_z ) return CONST0_RTX ( mode ) ;

gcc_assert ( pred == PRED_m || pred == PRED_x ) ;


<s> return <STR_LIT> ( MF . getFunction ( ) -> getCallingConv ( ) ) ;


<s> MD -> setRsrc2 ( CallingConv :: <ISA_LIT>_CS , CurrentProgramInfo . ComputePGMRSrc2 ) ; MD -> setFunctionLdsSize ( MF , CurrentProgramInfo . LDSSize ) ; MD -> setFunctionNumUsedVgprs ( MF , CurrentProgramInfo . NumVGPRsForWavesPerEU ) ; MD -> setFunctionNumUsedSgprs ( MF , CurrentProgramInfo . NumSGPRsForWavesPerEU ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>TargetMachine & tm ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) , TM ( tm ) {


<s> case ADDRESS_REG : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( info . regA ) ] ) ; output_addr_const ( file , info . offset ) ; break ; case ADDRESS_REG_INDEX : if ( REGNO ( info . regA ) == <NUM_LIT> ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( info . regB ) ] , reg_names [ REGNO ( info . regA ) ] ) ; else if ( REGNO ( info . regB ) != <NUM_LIT> ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( info . regB ) ] , reg_names [ REGNO ( info . regA ) ] ) ; break ; case ADDRESS_CONST_INT : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( info . regA ) ] ) ; output_addr_const ( file , info . offset ) ; break ; case ADDRESS_SYMBOLIC : case ADDRESS_SYMBOLIC_TXT_REL : case ADDRESS_GOTOFF : case ADDRESS_PLT : case ADDRESS_TLS : if ( info . regA ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( info . regA ) ] ) ; output_addr_const ( file , info . symbol ) ; if ( type == ADDRESS_GOTOFF ) { fputs ( <STR_LIT> , file ) ; } else if ( type == ADDRESS_PLT ) { fputs ( <STR_LIT> , file ) ; } else if ( type == ADDRESS_SYMBOLIC_TXT_REL ) { if ( info . offset != NULL && CONST_INT_P ( info . offset ) && INTVAL ( info . offset ) > <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , info . offset ) ; } fputs ( <STR_LIT> , file ) ;


<s> unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( TD ) ; assert ( EntrySize == <NUM_LIT> ) ; assert ( isPowerOf2_64 ( EntrySize ) ) ; auto PtrInfo = MachinePointerInfo :: getCapTable ( DAG . getMachineFunction ( ) ) ; SDValue Jumptable = getDataFromCapTable ( cast < JumpTableSDNode > ( Table . getNode ( ) ) , dl , PTy , DAG , Chain , PtrInfo ) ; Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index , DAG . getConstant ( Log2_32 ( EntrySize ) , dl , <STR_LIT> ) ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; auto LoadAddr = DAG . getPointerAdd ( dl , Jumptable , Index ) ; SDValue JTEntryValue = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadAddr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , MemVT ) ; Chain = JTEntryValue . getValue ( <NUM_LIT> ) ;


<s> AtomicSDNode * AN = cast < AtomicSDNode > ( N . getNode ( ) ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = N -> getOpcode ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { if ( Opc == <STR_LIT> ) { RHS = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RHS ) ; return DAG . getAtomic ( <STR_LIT> , DL , VT , Chain , LHS , RHS , AN -> getMemOperand ( ) ) ; } assert ( Opc == <STR_LIT> && <STR_LIT> ) ; return N ; } if ( Opc == <STR_LIT> && isNullConstant ( RHS ) ) { if ( AN -> getSuccessOrdering ( ) == AtomicOrdering :: SequentiallyConsistent && AN -> getSyncScopeID ( ) == SyncScope :: System ) { SDValue NewChain = emitLockedStackOp ( DAG , Subtarget , Chain , DL ) ; assert ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , DAG . getUNDEF ( VT ) , NewChain ) ;


<s> void <ISA_LIT>RegisterInfo :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned MaxAlign = std :: max ( MFI -> getMaxAlignment ( ) , calculateMaxStackAlignment ( MFI ) ) ; MFI -> setMaxAlignment ( MaxAlign ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int32_t TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , ( - <NUM_LIT> * SlotSize ) + TailCallReturnAddrDelta ) ; } if ( hasFP ( MF ) ) { assert ( ( TailCallReturnAddrDelta <= <NUM_LIT> ) && <STR_LIT> ) ; const TargetFrameInfo & TFI = * MF . getTarget ( ) . getFrameInfo ( ) ; int FrameIdx = MFI -> CreateFixedObject ( SlotSize , - ( int ) SlotSize + TFI . getOffsetOfLocalArea ( ) + TailCallReturnAddrDelta ) ; assert ( FrameIdx == MFI -> getObjectIndexBegin ( ) && <STR_LIT> ) ; FrameIdx = <NUM_LIT> ;


<s> unsigned NegSizeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( LP64 ) { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( G8RC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true ; } BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> ) . addReg ( NegSizeReg , getKillRegState ( KillNegSizeReg ) ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addImm ( maxCallFrameSize ) ; } else { if ( MaxAlign > TargetAlign ) { unsigned UnalNegSizeReg = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addImm ( ~ ( MaxAlign - <NUM_LIT> ) ) ; unsigned NegSizeReg1 = NegSizeReg ; NegSizeReg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , NegSizeReg ) . addReg ( UnalNegSizeReg , getKillRegState ( KillNegSizeReg ) ) . addReg ( NegSizeReg1 , RegState :: Kill ) ; KillNegSizeReg = true ;


<s> bool isR3LiveIn ( ) const { return R3IsLiveIn ;


<s> OptimizeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; MinimizeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; BlockInfo . clear ( ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; bool Modified = false ; for ( ReversePostOrderTraversal < MachineFunction * > :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) Modified |= ReduceMBB ( * * I ) ;


<s> unsigned MinRegOccupancy = std :: min ( ST . getOccupancyWithNumSGPRs ( SGPRs ) , ST . getOccupancyWithNumVGPRs ( VGPRs ) ) ;

return std :: min ( MinRegOccupancy , ST . getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) ) ) ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext * C , AsmPrinter & AsmPrinter ) : Ctx ( C ) , Printer ( AsmPrinter ) {


<s> return new <ISA_LIT>CtorDtorLowering ( ) ;


<s> unsigned Opcode = I . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opcode ) ) { if ( I . isCopy ( ) ) return selectCopy ( I , TII , MRI , TRI , RBI ) ; return true ; }

assert ( I . getNumOperands ( ) == I . getNumExplicitOperands ( ) && <STR_LIT> ) ;


<s> assert ( ! Is64Bit ) ; MCInst ADDInst ; unsigned ADDReg = <STR_LIT> ; ADDInst . setOpcode ( <STR_LIT> ) ; ADDInst . addOperand ( MCOperand :: CreateReg ( ADDReg ) ) ; ADDInst . addOperand ( MCOperand :: CreateReg ( ADDReg ) ) ; ADDInst . addOperand ( * AmtOp ) ; Out . EmitInstruction ( ADDInst , STI ) ; }

EmitIndirectBranch ( STI , MCOperand :: CreateReg ( RegTarget ) , Is64Bit , false , Out ) ;


<s> void StackFixup :: removeNElem ( Stack & stack , const StackVreg & vreg , size_t N ) { for ( unsigned i = <NUM_LIT> ; i < N ; ++ i ) removeElem ( stack , vreg ) ;


<s> bool CustomExpandInst ( const MCInst & Inst , MCStreamer & Out ) {

return CustomExpandInstNaCl<ISA_LIT> ( Inst , Out , State ) ;


<s> if ( ( GET_CODE ( op ) == ASHIFT || GET_CODE ( op ) == ASHIFTRT || GET_CODE ( op ) == LSHIFTRT || GET_CODE ( op ) == ROTATERT || GET_CODE ( op ) == ROTATE ) && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) return XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) == MULT && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) && ( ( unsigned ) exact_log2 ( INTVAL ( XEXP ( op , <NUM_LIT> ) ) ) ) < <NUM_LIT> ) return XEXP ( op , <NUM_LIT> ) ;


<s> Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ;


<s> bool AMDGPUInstrInfo :: hasStoreFromStackSlot ( const MachineInstr * MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { return false ;


<s> bool <ISA_LIT>MCExpr :: EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout ) const { return false ;


<s> assert ( LoVT . getVectorNumElements ( ) + ( HiVT . isVector ( ) ? HiVT . getVectorNumElements ( ) : <NUM_LIT> ) <= N . getValueType ( ) . getVectorNumElements ( ) && <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , LoVT , N , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ;

SDValue Hi = DAG . getNode ( HiVT . isVector ( ) ? <STR_LIT> : <STR_LIT> , DL , HiVT , N , DAG . getVectorIdxConstant ( LoVT . getVectorNumElements ( ) , DL ) ) ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ;


<s> if ( ( SignExtSrcVT != GLD1SrcMemVT ) || ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( DstVT , <STR_LIT> ) ; SDValue Ops [ ] = { Src -> getOperand ( <NUM_LIT> ) , Src -> getOperand ( <NUM_LIT> ) , Src -> getOperand ( <NUM_LIT> ) , Src -> getOperand ( <NUM_LIT> ) , Src -> getOperand ( <NUM_LIT> ) } ;

SDValue ExtLoad = DAG . getNode ( NewOpc , SDLoc ( N ) , VTs , Ops ) ;


<s> if ( RegVT == <STR_LIT> ) RC = Subtarget -> in<ISA_LIT>16Mode ( ) ? & <STR_LIT> : & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = Has<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = AddLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , dl , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , ValVT , ArgValue ) ; else if ( IsO32 && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = AddLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , dl , Reg2 , RegVT ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 ) ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( ValVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ;


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> bool c6x_long_call_p ( rtx op ) { tree decl ; if ( ! TARGET_LONG_CALLS ) return false ; decl = SYMBOL_REF_DECL ( op ) ; if ( decl != NULL_TREE && ! flag_reorder_blocks_and_partition && TREE_CODE ( decl ) == FUNCTION_DECL && c6x_function_in_section_p ( decl , current_function_section ( ) ) ) return false ; return true ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; int RegNum ; RegNum = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNum == - <NUM_LIT> ) return true ; Parser . Lex ( ) ; bool Writeback = false ; if ( ParseWriteBack ) { const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { Writeback = true ; Parser . Lex ( ) ;


<s> IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN :


<s> static SDValue LowerAndToBTST ( SDValue And , <STR_LIT> CC , const SDLoc & DL , SelectionDAG & DAG ) { SDValue Op0 = And . getOperand ( <NUM_LIT> ) ; SDValue Op1 = And . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( isOneConstant ( Op0 . getOperand ( <NUM_LIT> ) ) ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) {

auto Known = DAG . computeKnownBits ( Op0 ) ;


<s> Register <ISA_LIT>InstructionSelector :: widenGPRBankRegIfNeeded ( Register Reg , unsigned WideSize , MachineIRBuilder & MIB ) const { assert ( WideSize >= <NUM_LIT> && <STR_LIT> ) ; MachineRegisterInfo & MRI = * MIB . getMRI ( ) ; unsigned NarrowSize = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( WideSize >= NarrowSize && <STR_LIT> ) ; if ( NarrowSize == WideSize || NarrowSize == <NUM_LIT> ) return Reg ; const RegisterBank * RB = RBI . getRegBank ( Reg , MRI , TRI ) ; const TargetRegisterClass * OrigRC = getMinClassForRegBank ( * RB , NarrowSize ) ; const TargetRegisterClass * WideRC = getMinClassForRegBank ( * RB , WideSize ) ; assert ( OrigRC && <STR_LIT> ) ; assert ( WideRC && <STR_LIT> ) ; if ( OrigRC == WideRC ) return Reg ; unsigned SubReg = <NUM_LIT> ;

getSubRegForClass ( OrigRC , TRI , SubReg ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FeatureDummy ( false ) {

ParseSubtargetFeatures ( CPU , CPU , FS ) ;


<s> SDValue DivScale0 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , Y , Y , X ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Rcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Fma0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Rcp , One ) ; SDValue Fma1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Rcp , Fma0 , Rcp ) ; SDValue Fma2 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma1 , One ) ; SDValue DivScale1 = DAG . getNode ( <STR_LIT> , SL , ScaleVT , X , Y , X ) ; SDValue Fma3 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma1 , Fma2 , Fma1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 , Fma3 ) ; SDValue Fma4 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , DivScale1 ) ; SDValue Scale ; if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { const SDValue Hi = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue NumBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , X ) ; SDValue DenBC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Y ) ; SDValue Scale0BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale0 ) ; SDValue Scale1BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DivScale1 ) ; SDValue NumHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NumBC , Hi ) ; SDValue DenHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenBC , Hi ) ; SDValue Scale0Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale0BC , Hi ) ; SDValue Scale1Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Scale1BC , Hi ) ;

SDValue CmpDen = DAG . getSetCC ( SL , <STR_LIT> , DenHi , Scale0Hi , <STR_LIT> ) ;


<s> static const MCPhysReg XMMArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

if ( ! Info . IsFixed ) NumXMMRegs = State . getFirstUnallocated ( XMMArgRegs ) ;


<s>
for
(
unsigned
L
=
<NUM_LIT>
;
L
<
NUM_BANKS
;
++
L
)
if
(
FreeBanks
&
(
<NUM_LIT>
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L
)
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dbgs
(
)
<<
printBank
(
L
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' '
;


<s> if ( GET_CODE ( op ) == SYMBOL_REF ) { tree decl = SYMBOL_REF_DECL ( op ) ; return ! skip_local || ! decl || ! default_binds_local_p ( decl ) ; } fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( op , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( arc_raw_symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) , skip_local ) ) return true ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ;

if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ;


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , DebugLoc dl , const Thumb1RegisterInfo & MRI , int NumBytes ) { emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , NumBytes , TII , MRI ) ;


<s> if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ;

for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) {


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _rdseed32_step ( unsigned int * __p ) { return __builtin_ia32_rdseed_si_step ( __p ) ;


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; switch ( CC ) { default : break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , RHS , LHS , CC ) ; break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , LHS , RHS , CC ) ; break ; } if ( NegateFCC ( LHS , RHS , CC ) ) std :: swap ( TrueV , FalseV ) ; SDValue TargetCC = DAG . getConstant ( CC , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , TargetCC ) ;

SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> MachineFunction * F = BB -> getParent ( ) ; assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const uint32_t * RegMask = getTargetMachine ( ) . getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; if ( Subtarget -> is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ;


<s> if ( ! NoImplicitFloat && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) { if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE2 ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; if ( ( isSrcConst || isSrcStr ) && Subtarget -> hasSSE1 ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ; } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ;


<s> return isConstantImm ( ) && isInt < Bits > ( getConstantImm ( ) ) ;


<s> if ( ! Src ) return false ; if ( const PointerType * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) return ( PT -> getAddressSpace ( ) == spN ) ;


<s> MatImm = RImm ; MaskEnd = <NUM_LIT> ; } unsigned LS = findLastSet ( RImm ) ; if ( LS != r - <NUM_LIT> ) continue ; uint64_t OnesMask = - ( int64_t ) ( UINT64_C ( <NUM_LIT> ) << ( LS + <NUM_LIT> ) ) ; uint64_t RImmWithOnes = RImm | OnesMask ; RCount = getInt64CountDirect ( RImmWithOnes ) + <NUM_LIT> ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImmWithOnes ; MaskEnd = LS ;


<s> } while ( args ) ; return true ; } gcc_assert ( TREE_CODE ( args ) == STRING_CST ) ; size_t len = strlen ( TREE_STRING_POINTER ( args ) ) ; char * str_to_check = ( char * ) alloca ( len + <NUM_LIT> ) ; strcpy ( str_to_check , TREE_STRING_POINTER ( args ) ) ; if ( len == <NUM_LIT> ) { error ( <STR_LIT> , pragma_or_attr ) ; return false ; } unsigned int num_commas = num_occurences_in_str ( ',' , str_to_check ) ; char * token = strtok ( str_to_check , <STR_LIT> ) ; unsigned int num_attrs = <NUM_LIT> ; while ( token ) { num_attrs ++ ; if ( ! aarch64_process_one_target_attr ( token , pragma_or_attr ) ) { error ( <STR_LIT> , pragma_or_attr , token ) ; return false ;


<s> unsigned Reg = Op . getReg ( ) ; unsigned Size = TRI -> getMinimalPhysRegClass ( Reg ) -> getSize ( ) ; Result . Named . LGKM = Size > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } else { Result . Named . LGKM = <NUM_LIT> ; } } else { Result . Named . LGKM = <NUM_LIT> ;


<s> RemoveUnneededFlows ( Root ) ; FindLabeledLoops ( Root ) ;


<s> if ( AllVisited . count ( & I ) ) continue ; if ( isa < ICmpInst > ( I ) ) { auto & CI = cast < ICmpInst > ( I ) ; if ( CI . isSigned ( ) || ! isa < IntegerType > ( CI . getOperand ( <NUM_LIT> ) -> getType ( ) ) ) continue ; for ( auto & Op : CI . operands ( ) ) { if ( auto * I = dyn_cast < Instruction > ( Op ) ) MadeChange |= TryToPromote ( I ) ; } } } Promoter -> Cleanup ( ) ; LLVM_DEBUG ( if ( verifyFunction ( F , & dbgs ( ) ) ) { dbgs ( ) ;


<s> assert ( ( Count % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; OS . write_zeros ( Count ) ; return true ;


<s> const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ;

if ( STI . isTargetDarwin ( ) ) return true ;


<s> shmask . ll [ ( ( si_to_uint ( a ) + ( unsigned int ) ( imm ) ) >> <NUM_LIT> ) & <NUM_LIT> ] = <NUM_LIT> ; return ( ( qword ) ( shmask . v ) ) ;


<s> flags_valid = FLAGS_VALID_MOVE ; flags_operand1 = side_effects_p ( operands [ <NUM_LIT> ] ) ? NULL_RTX : operands [ <NUM_LIT> ] ; if ( side_effects_p ( operands [ <NUM_LIT> ] ) || modified_in_p ( operands [ <NUM_LIT> ] , current_output_insn ) ) flags_operand2 = NULL_RTX ; else flags_operand2 = operands [ <NUM_LIT> ] ; return ; } if ( flags_operand1 != NULL_RTX && modified_in_p ( flags_operand1 , current_output_insn ) ) flags_operand1 = NULL_RTX ;


<s> assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int ) Value ;


<s> switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumVectorElts = VT . getVectorNumElements ( ) ; unsigned RegClassID ; switch ( NumVectorElts ) { case <NUM_LIT> : RegClassID = <STR_LIT> ; break ; case <NUM_LIT> : if ( Opc == <STR_LIT> ) RegClassID = <STR_LIT> ; else RegClassID = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) return RR ; const TargetRegisterClass * RC = RegInfos [ RR . Reg ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( <NUM_LIT> ) ;

LaneBitmask Common = RR . Mask & RCMask ;


<s> unsigned Kind = Fixup . getKind ( ) ; int64_t SignedValue = static_cast < int64_t > ( Value ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return AdrImmBits ( Value & <NUM_LIT> ) ; case <STR_LIT> : assert ( ! IsResolved ) ; if ( TheTriple . isOSBinFormatCOFF ( ) ) return AdrImmBits ( Value & <NUM_LIT> ) ; return AdrImmBits ( ( Value & <NUM_LIT> ) >> <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ; if ( Value >= <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( TheTriple . isOSBinFormatCOFF ( ) && ! IsResolved ) Value &= <NUM_LIT> ;


<s> MachineOperand & Op = DBI -> getOperand ( <NUM_LIT> ) ; Op . ChangeToTargetIndex ( llvm :: <STR_LIT> , LocalId ) ;


<s> if ( frame . to_allocate > <NUM_LIT> ) gcc_assert ( initial_offset != <NUM_LIT> ) ; off = - initial_offset + <NUM_LIT> - frame . padding0 ; mem = gen_frame_mem ( Pmode , stack_pointer_rtx ) ; added_already = <NUM_LIT> ; if ( frame_pointer_needed ) { rtx fp_reg = gen_rtx_REG ( SImode , REG_A15 ) ; rtx addr = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ) ; insn = emit_move_insn ( gen_frame_mem ( Pmode , addr ) , fp_reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; nsaved ++ ; insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; off -= <NUM_LIT> ; added_already = - <NUM_LIT> ; } emit_add_sp_const ( initial_offset - added_already , true ) ; if ( nsaved < frame . nregs ) { unsigned i ; for ( i = <NUM_LIT> ; i < N_SAVE_ORDER ; i ++ ) { int idx = N_SAVE_ORDER - i - <NUM_LIT> ; unsigned regno = reg_save_order [ idx ] ; rtx reg ; machine_mode save_mode = SImode ; if ( regno == REG_A15 && frame_pointer_needed ) continue ; if ( ! c6x_save_reg ( regno ) ) continue ; if ( TARGET_STDW && ( off & <NUM_LIT> ) == <NUM_LIT> && off <= <NUM_LIT> && ( regno & <NUM_LIT> ) == <NUM_LIT> && i + <NUM_LIT> < N_SAVE_ORDER && reg_save_order [ idx - <NUM_LIT> ] == regno - <NUM_LIT> && c6x_save_reg ( regno - <NUM_LIT> ) ) { save_mode = DImode ; regno -- ; i ++ ; } reg = gen_rtx_REG ( save_mode , regno ) ; off -= GET_MODE_SIZE ( save_mode ) ; insn = emit_move_insn ( adjust_address ( mem , save_mode , off ) , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; nsaved += hard_regno_nregs ( regno , save_mode ) ; } } gcc_assert ( nsaved == frame . nregs ) ; emit_add_sp_const ( - frame . to_allocate - initial_offset , true ) ; if ( must_reload_pic_reg_p ( ) ) { if ( dsbt_decl == NULL ) { tree t ; t = build_index_type ( integer_one_node ) ; t = build_array_type ( integer_type_node , t ) ; t = build_decl ( BUILTINS_LOCATION , VAR_DECL , get_identifier ( <STR_LIT> ) , t ) ; DECL_ARTIFICIAL ( t ) = <NUM_LIT> ; DECL_IGNORED_P ( t ) = <NUM_LIT> ; DECL_EXTERNAL ( t ) = <NUM_LIT> ; TREE_STATIC ( t ) = <NUM_LIT> ; TREE_PUBLIC ( t ) = <NUM_LIT> ; TREE_USED ( t ) = <NUM_LIT> ; dsbt_decl = t ; }

emit_insn ( gen_setup_dsbt ( pic_offset_table_rtx , XEXP ( DECL_RTL ( dsbt_decl ) , <NUM_LIT> ) ) ) ;


<s> auto * ExtMI = MF . CreateMachineInstr ( HII -> get ( <STR_LIT> ) , DebugLoc ( ) ) ; bool Avail = ResourceTracker -> canReserveResources ( * ExtMI ) ;

if ( Reserve && Avail ) ResourceTracker -> reserveResources ( * ExtMI ) ;


<s> DebugLoc dl = Lower . getDebugLoc ( ) ; assert ( Lower . getValueType ( ) == Upper . getValueType ( ) && <STR_LIT> ) ; EVT VT = EVT :: getVectorVT ( * DAG . getContext ( ) , Lower . getValueType ( ) . getVectorElementType ( ) , Lower . getValueType ( ) . getVectorNumElements ( ) * <NUM_LIT> ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue Vec = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , VT ) , Upper , DAG . getConstant ( Lower . getValueType ( ) . getVectorNumElements ( ) , <STR_LIT> ) , DAG , dl ) ; Vec = Insert128BitVector ( Vec , Lower , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ;


<s> if ( in<ISA_LIT>16Mode ( ) ) { reportParseError ( <STR_LIT> ) ; return false ; } SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Reg ; OperandMatchResultTy ResTy = parseAnyRegister ( Reg ) ; if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & RegOpnd = static_cast < <ISA_LIT>Operand & > ( * Reg [ <NUM_LIT> ] ) ; if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( ) , <STR_LIT> ) ;


<s> if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'o' ; if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'r' ;

if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'w' ;


<s> AU . setPreservesAll ( ) ; AU . addRequired < MachineDominatorTree > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasVOP3PInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) {


<s> __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> insn_type = get_attr_type ( insn ) ; if ( REG_NOTE_KIND ( link ) == <NUM_LIT> ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD ) return cost + <NUM_LIT> ; if ( insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE ) { rtx pat = PATTERN ( insn ) ;


<s> static uint16_t getParityBitForEncoding ( uint16_t Enc ) {


<s> return gen_got_load_tls_ie ( Pmode , dest , sym ) ;


<s> return ! Subtarget . hasSSE2 ( ) || VT == <STR_LIT> ;


<s> rtx s390_get_thread_pointer ( void ) { rtx tp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( tp , gen_rtx_REG ( Pmode , TP_REGNUM ) ) ; mark_reg_pointer ( tp , BITS_PER_WORD ) ; return tp ;


<s> if ( ! TARGET_BOOLEANS && TARGET_HARD_FLOAT ) error ( <STR_LIT> ) ; for ( mode = VOIDmode ; mode != MAX_MACHINE_MODE ; mode = ( machine_mode ) ( ( int ) mode + <NUM_LIT> ) ) { int size = GET_MODE_SIZE ( mode ) ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { int temp ; if ( ACC_REG_P ( regno ) ) temp = ( TARGET_MAC16 && ( mclass == MODE_INT ) && ( size <= UNITS_PER_WORD ) ) ; else if ( GP_REG_P ( regno ) ) temp = ( ( regno & <NUM_LIT> ) == <NUM_LIT> || ( size <= UNITS_PER_WORD ) ) ; else if ( FP_REG_P ( regno ) ) temp = ( TARGET_HARD_FLOAT && ( mode == SFmode ) ) ; else if ( BR_REG_P ( regno ) ) temp = ( TARGET_BOOLEANS && ( mode == CCmode ) ) ; else temp = FALSE ; xtensa_hard_regno_mode_ok [ ( int ) mode ] [ regno ] = temp ; } } init_machine_status = xtensa_init_machine_status ; if ( flag_pic && TARGET_CONST16 ) error ( <STR_LIT> , ( flag_pic > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; else if ( TARGET_FORCE_NO_PIC ) flag_pic = <NUM_LIT> ; else if ( XTENSA_ALWAYS_PIC ) { if ( TARGET_CONST16 ) error ( <STR_LIT> ) ; flag_pic = <NUM_LIT> ; } if ( flag_pic > <NUM_LIT> ) flag_pic = <NUM_LIT> ; if ( flag_pic && ! flag_pie ) flag_shlib = <NUM_LIT> ;

if ( flag_reorder_blocks_and_partition ) {


<s> bool AMDGPUPeepholeOpt :: doFinalization ( Module & M ) { return false ;


<s> if ( TARGET_64BIT ) aputs ( <STR_LIT> ) ;

else if ( TARGET_PA_20 ) aputs ( <STR_LIT> ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) return parseLiteralValues ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) return parseLiteralValues ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirective<ISA_LIT> ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ;

else if ( IDVal == <STR_LIT> ) return parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ;


<s> if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; Mask = peekThroughBitcasts ( Mask ) ; X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned SraAmt = ~ <NUM_LIT> ; if ( Mask . getOpcode ( ) == <STR_LIT> ) { if ( auto * AmtBV = dyn_cast < BuildVectorSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ) if ( auto * AmtConst = AmtBV -> getConstantSplatNode ( ) ) SraAmt = AmtConst -> getZExtValue ( ) ; } else if ( Mask . getOpcode ( ) == <STR_LIT> ) { SDValue SraC = Mask . getOperand ( <NUM_LIT> ) ; SraAmt = cast < ConstantSDNode > ( SraC ) -> getZExtValue ( ) ; } if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V ) { assert ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) ; SDValue SubOp1 = DAG . getNode ( <STR_LIT> , DL , MaskVT , V , Mask ) ; SDValue SubOp2 = Mask ; if ( V == Y ) std :: swap ( SubOp1 , SubOp2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , SubOp1 , SubOp2 ) ) ; } } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; MVT BlendVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getBitcast ( BlendVT , X ) ;


<s> enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; } char const * FunctionNames [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , {


<s> bool UsedMask [ ] = { false , false , false } ; Register SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) && <STR_LIT> ) ; SrcRegs [ I ] = get<ISA_LIT>SubSuperRegister ( Op -> getReg ( ) , <NUM_LIT> ) ; if ( SrcRegs [ I ] != DestRegs [ I ] ) { UsedMask [ I ] = true ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else { emit<ISA_LIT>Nops ( * OutStreamer , <NUM_LIT> , Subtarget ) ; } } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( UsedMask [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ;

MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ;


<s> machine_mode memory_vector_mode ( const function_instance & fi ) const override {

poly_uint64 nunits = GET_MODE_NUNITS ( fi . vector_mode ( <NUM_LIT> ) ) ;


<s> virtual ~ <ISA_LIT>RI5CYIR ( ) { if ( dag != NULL ) { delete dag ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>BaseTargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; Value <<= Info . TargetOffset ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ;

unsigned Offset = Fixup . getOffset ( ) ;


<s> if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> && Desc . OpInfo [ I ] . isOptionalDef ( ) ) return true ;


<s> const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; unsigned WorkGroupSize = MFI -> getMaxFlatWorkGroupSize ( ) ; unsigned WavefrontSize = ST . getWavefrontSize ( ) ; unsigned TIDReg = MFI -> getTIDReg ( ) ; if ( ! MFI -> hasCalculatedTID ( ) ) { MachineBasicBlock & Entry = MBB . getParent ( ) -> front ( ) ; MachineBasicBlock :: iterator Insert = Entry . front ( ) ; DebugLoc DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> , * MF ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) . getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGYReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned TIDIGZReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned InputPtrReg = MFI -> getPreloadedReg ( <STR_LIT> ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ;

unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ;


<s> static void interruptFrameLayout ( MachineFunction & MF ) { const Function * F = MF . getFunction ( ) ; CallingConv :: ID CallConv = F -> getCallingConv ( ) ; if ( CallConv != CallingConv :: MBLAZE_INTR && CallConv != CallingConv :: MBLAZE_SVOL ) return ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; bool isIntr = CallConv == CallingConv :: MBLAZE_INTR ; MachineBasicBlock & MENT = MF . front ( ) ; MachineBasicBlock & MEXT = MF . back ( ) ; MachineBasicBlock :: iterator MENTI = MENT . begin ( ) ; MachineBasicBlock :: iterator MEXTI = prior ( MEXT . end ( ) ) ; DebugLoc ENTDL = MENTI != MENT . end ( ) ? MENTI -> getDebugLoc ( ) : DebugLoc ( ) ; DebugLoc EXTDL = MEXTI != MEXT . end ( ) ? MEXTI -> getDebugLoc ( ) : DebugLoc ( ) ; SmallVector < int , <NUM_LIT> > VFI ; for ( unsigned r = <STR_LIT> ; r <= <STR_LIT> ; ++ r ) { if ( ! MRI . isPhysRegUsed ( r ) && ! ( isIntr && r == <STR_LIT> ) ) continue ; int FI = MFI -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false , false ) ; VFI . push_back ( FI ) ; BuildMI ( MENT , MENTI , ENTDL , TII . get ( <STR_LIT> ) , r ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } int R17FI = MFI -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false , false ) ; int R18FI = MFI -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false , false ) ; BuildMI ( MENT , MENTI , ENTDL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( R17FI ) . addImm ( <NUM_LIT> ) ;

BuildMI ( MENT , MENTI , ENTDL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addFrameIndex ( R18FI ) . addImm ( <NUM_LIT> ) ;


<s> UP . OptSizeThreshold = <NUM_LIT> ; UP . PartialOptSizeThreshold = <NUM_LIT> ; if ( L -> getHeader ( ) -> getParent ( ) -> hasOptSize ( ) ) return ; if ( ! ST -> isThumb2 ( ) ) return ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << L -> getNumBlocks ( ) << <STR_LIT> << <STR_LIT> << ExitingBlocks . size ( ) << <STR_LIT> ) ; if ( ExitingBlocks . size ( ) > <NUM_LIT> ) return ; if ( ST -> hasBranchPredictor ( ) && L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; unsigned Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } SmallVector < const Value * , <NUM_LIT> > Operands ( I . operand_values ( ) ) ; Cost += getUserCost ( & I , Operands , TargetTransformInfo :: TCK_SizeAndLatency ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Cost << <STR_LIT> ) ; UP . Partial = true ; UP . Runtime = true ; UP . UpperBound = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = <NUM_LIT> ;


<s> const LLT SrcTy = MRI . getType ( SrcReg ) ; unsigned SubIdx = <STR_LIT> ; if ( ! DstTy . isVector ( ) || ! SrcTy . isVector ( ) ) return false ; assert ( SrcTy . getSizeInBits ( ) > DstTy . getSizeInBits ( ) && <STR_LIT> ) ; if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else if ( DstTy . getSizeInBits ( ) == <NUM_LIT> ) SubIdx = <STR_LIT> ; else return false ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstReg , MRI ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcReg , MRI ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubIdx ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubIdx ) ;


<s> unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg || ! Src1Reg ) return false ; emitInst ( DivOpc ) . addReg ( Src0Reg ) . addReg ( Src1Reg ) ; emitInst ( <STR_LIT> ) . addReg ( Src1Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; if ( ! ResultReg ) return false ;

unsigned MFOpc = ( ISDOpcode == <STR_LIT> || ISDOpcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> <ISA_LIT>ATTInstPrinter :: <ISA_LIT>ATTInstPrinter ( const MCAsmInfo & MAI ) : MCInstPrinter ( MAI ) {


<s> MVT ArgVT = Ins [ i ] . VT ; <STR_LIT> ArgFlags = Ins [ i ] . Flags ; Type * ArgTy = nullptr ; if ( IsRet ) ArgTy = FType -> getReturnType ( ) ; else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( Fn ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , true , IsRet , ArgTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << '\n' ) ; llvm_unreachable ( nullptr ) ; } }


<s> rtx_insn * rinsn ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { rinsn = insn -> rtl ( ) ; gcc_assert ( vsetvl_insn_p ( rinsn ) && <STR_LIT> ) ; } else { gcc_assert ( has_vtype_op ( insn -> rtl ( ) ) ) ;


<s> for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] == SM_SentinelUndef ) continue ;

else if ( Mask [ i ] < <NUM_LIT> && Mask [ i ] != SM_SentinelZero ) return false ;


<s> for ( SUnit * SU : SUnits ) { SU -> isScheduled = false ;


<s> const unsigned globalRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; globalRegs [ i ] != <NUM_LIT> ; ++ i ) {


<s> bool TreeSpoiled = IsLoopTreeSpoiled ( CurrTree ) ; if ( TreeSpoiled ) { MarkTreeAsSpoiled ( CurrTree ) ; } CurrTree = hwloops [ CurrTree ] . RightLoop ;


<s> void DecodeScalarMoveMask ( unsigned NumElts , bool IsLoad , SmallVectorImpl < int > & Mask ) { Mask . push_back ( NumElts ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) Mask . push_back ( IsLoad ? static_cast < int > ( SM_SentinelZero ) : i ) ;


<s> bool hasStackFrame ( ) const { return HasStackFrame ;


<s> SrcVT = <STR_LIT> ; DstVT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcVT = <STR_LIT> ; DstVT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SrcVT = <STR_LIT> ; DstVT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcVT = <STR_LIT> ; DstVT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SrcVT = <STR_LIT> ; DstVT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcVT = <STR_LIT> ; DstVT = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SrcVT = <STR_LIT> ; DstVT = <STR_LIT> ;


<s> for ( ; ; ) { const MCExpr * OE ; SMLoc OpcodeLoc = getLexer ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) || Parser . parseExpression ( OE ) ) { Error ( OpcodeLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } const MCConstantExpr * OC = dyn_cast < MCConstantExpr > ( OE ) ; if ( ! OC ) { Error ( OpcodeLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } const int64_t Opcode = OC -> getValue ( ) ; if ( Opcode & ~ <NUM_LIT> ) { Error ( OpcodeLoc , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Opcodes . push_back ( uint8_t ( Opcode ) ) ;

if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ;


copyRegToReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SrcReg , const TargetRegisterClass * DestRC , const TargetRegisterClass * SrcRC ) const {


<s> switch ( OpType ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> __inline__ static void sh_media_BRK ( void ) { __asm__ __volatile__ ( <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isTC1 ( const MachineInstr & MI ) const { unsigned SchedClass = MI . getDesc ( ) . getSchedClass ( ) ;


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { return <STR_LIT> ;


<s> SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FPStackOffset ( <NUM_LIT> ) , RAStackOffset ( <NUM_LIT> ) , CPUTopSavedRegOff ( <NUM_LIT> ) , FPUTopSavedRegOff ( <NUM_LIT> ) , GPHolder ( - <NUM_LIT> , - <NUM_LIT> ) , HasLoadArgs ( false ) , HasStoreVarArgs ( false ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> const char * getPassName ( ) const override {


<s> if ( MO . isImplicit ( ) ) { break ; } return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , MOTy , offset ) ; case MachineOperand :: MO_RegisterMask : break ; }


<s> if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + <STR_LIT> <= MI -> getNumOperands ( ) && MI -> getOperand ( Op + <STR_LIT> ) . isReg ( ) && isLeaMem ( MI , Op ) ;


<s> static void avr_option_override ( void ) { flag_delete_null_pointer_checks = <NUM_LIT> ; if ( avr_strict_X ) flag_caller_saves = <NUM_LIT> ; maybe_set_param_value ( PARAM_ALLOW_STORE_DATA_RACES , <NUM_LIT> , global_options . x_param_values , global_options_set . x_param_values ) ; if ( ( flag_unwind_tables || flag_non_call_exceptions || flag_asynchronous_unwind_tables ) && ! ACCUMULATE_OUTGOING_ARGS ) { flag_omit_frame_pointer = <NUM_LIT> ; } if ( flag_pic == <NUM_LIT> ) warning ( OPT_fpic , <STR_LIT> ) ; if ( flag_pic == <NUM_LIT> ) warning ( OPT_fPIC , <STR_LIT> ) ; if ( flag_pie == <NUM_LIT> ) warning ( OPT_fpie , <STR_LIT> ) ; if ( flag_pie == <NUM_LIT> ) warning ( OPT_fPIE , <STR_LIT> ) ; if ( ! avr_set_core_architecture ( ) ) return ; avr_addr . sreg = <NUM_LIT> + avr_arch -> sfr_offset ; avr_addr . rampz = <NUM_LIT> + avr_arch -> sfr_offset ; avr_addr . rampy = <NUM_LIT> + avr_arch -> sfr_offset ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; return Reserved ;


<s> DebugLoc dl = ES -> getDebugLoc ( ) ; SDValue TES = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TES ) ;

SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TES ) ;


<s> bool <ISA_LIT>InstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { SmallVector < MachineInstr * , <NUM_LIT> > CondBranches ; return AnalyzeBranchImpl ( MBB , TBB , FBB , Cond , CondBranches , AllowModify ) ;


<s> unsigned OReg64 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned TReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) , OReg ) . addReg ( BReg ) . addImm ( <NUM_LIT> ) . addReg ( IReg64 ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) , OReg64 ) . addReg ( OReg ) ; BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) , TReg ) . addReg ( OReg64 ) . addReg ( BReg ) ; BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( TReg ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } } else { BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( IReg ) . addJumpTableIndex ( MJTI ) . addReg ( <NUM_LIT> ) ; } SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > SeenMBBs ; for ( auto & LP : LPadList ) if ( SeenMBBs . insert ( LP ) . second ) DispContBB -> addSuccessor ( LP ) ; SmallVector < MachineBasicBlock * , <NUM_LIT> > MBBLPads ; const MCPhysReg * SavedRegs = MF -> getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( MachineBasicBlock * MBB : InvokeBBs ) { SmallVector < MachineBasicBlock * , <NUM_LIT> > Successors ( MBB -> succ_rbegin ( ) , MBB -> succ_rend ( ) ) ; for ( auto MBBS : Successors ) { if ( MBBS -> isEHPad ( ) ) { MBB -> removeSuccessor ( MBBS ) ; MBBLPads . push_back ( MBBS ) ; } } MBB -> addSuccessor ( DispatchBB ) ; for ( auto & II : reverse ( * MBB ) ) { if ( ! II . isCall ( ) ) continue ; DenseMap < unsigned , bool > DefRegs ; for ( auto & MOp : II . operands ( ) ) if ( MOp . isReg ( ) ) DefRegs [ MOp . getReg ( ) ] = true ; MachineInstrBuilder MIB ( * MF , & II ) ; for ( unsigned RI = <NUM_LIT> ; SavedRegs [ RI ] ; ++ RI ) { unsigned Reg = SavedRegs [ RI ] ; if ( ! DefRegs [ Reg ] ) MIB . addReg ( Reg , RegState :: ImplicitDefine | RegState :: Dead ) ; } break ; } }

for ( auto & LP : MBBLPads ) LP -> setIsEHPad ( false ) ;


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return true ;


<s> } if ( SDValue Shuf128 = lowerV4X128Shuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsVALIGN ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue V = lowerShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ;

return lowerShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> } Info -> P<ISA_LIT>nputAddr |= <NUM_LIT> << P<ISA_LIT>nputNum ++ ; } if ( Info -> getShaderType ( ) != ShaderType :: COMPUTE && Arg . VT . isVector ( ) ) { <STR_LIT> NewArg = Arg ; NewArg . Flags . setSplit ( ) ; NewArg . VT = Arg . VT . getVectorElementType ( ) ; Type * ParamType = FType -> getParamType ( Arg . getOrigArgIndex ( ) ) ; unsigned NumElements = ParamType -> getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j != NumElements ; ++ j ) { Splits . push_back ( NewArg ) ; NewArg . PartOffset += NewArg . VT . getStoreSize ( ) ; } } else if ( Info -> getShaderType ( ) != ShaderType :: COMPUTE ) { Splits . push_back ( Arg ) ; } } SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( Info -> getShaderType ( ) == ShaderType :: PIXEL && ( Info -> P<ISA_LIT>nputAddr & <NUM_LIT> ) == <NUM_LIT> ) { Info -> P<ISA_LIT>nputAddr |= <NUM_LIT> ; CCInfo . AllocateReg ( <STR_LIT> ) ; CCInfo . AllocateReg ( <STR_LIT> ) ; } if ( Info -> getShaderType ( ) == ShaderType :: COMPUTE ) { if ( Subtarget -> isAmdHsaOS ( ) ) Info -> NumUserSGPRs = <NUM_LIT> ; else Info -> NumUserSGPRs = <NUM_LIT> ; unsigned InputPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: INPUT_PTR ) ; unsigned InputPtrRegLo = TRI -> getPhysRegSubReg ( InputPtrReg , & <STR_LIT> , <NUM_LIT> ) ; unsigned InputPtrRegHi = TRI -> getPhysRegSubReg ( InputPtrReg , & <STR_LIT> , <NUM_LIT> ) ; unsigned ScratchPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: SCRATCH_PTR ) ; unsigned ScratchPtrRegLo = TRI -> getPhysRegSubReg ( ScratchPtrReg , & <STR_LIT> , <NUM_LIT> ) ; unsigned ScratchPtrRegHi = TRI -> getPhysRegSubReg ( ScratchPtrReg , & <STR_LIT> , <NUM_LIT> ) ; CCInfo . AllocateReg ( InputPtrRegLo ) ; CCInfo . AllocateReg ( InputPtrRegHi ) ; CCInfo . AllocateReg ( ScratchPtrRegLo ) ; CCInfo . AllocateReg ( ScratchPtrRegHi ) ; MF . addLiveIn ( InputPtrReg , & <STR_LIT> ) ; MF . addLiveIn ( ScratchPtrReg , & <STR_LIT> ) ; } if ( Info -> getShaderType ( ) == ShaderType :: COMPUTE ) {

getOriginalFunctionArgs ( DAG , DAG . getMachineFunction ( ) . getFunction ( ) , Ins , Splits ) ;


<s> static HOST_WIDE_INT iq2000_starting_frame_offset ( void ) { return crtl -> outgoing_args_size ;


<s> bool <ISA_LIT>TTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) {


<s> if ( Predicate_so_imm ( TrueVal . getNode ( ) ) ) { SDValue True = CurDAG -> getTargetConstant ( T -> getZExtValue ( ) , <STR_LIT> ) ; SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , True , CC , CCR , InFlag } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } return <NUM_LIT> ;


<s> static SDValue LowerF128_FPEXTEND ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPEXT_F64_F128 ) , <NUM_LIT> ) ;

if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPEXT_F32_F128 ) , <NUM_LIT> ) ;


<s> Reached . insert ( MI ) ; if ( MI -> isPHI ( ) ) { for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { Register Reg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( Reg ) ) { continue ; } MachineInstr * NewMI = MRI -> getVRegDef ( Reg ) ; if ( ! NewMI ) continue ; Front . push_back ( NewMI ) ; } } else if ( MI -> isFullCopy ( ) ) { if ( ! Register :: isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ;

MachineInstr * NewMI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> if ( Size == <NUM_LIT> ) return & <STR_LIT> ; assert ( Size == <NUM_LIT> ) ; return & <STR_LIT> ;


<s> ctors_section ( ) ; assemble_align ( POINTER_SIZE ) ; fputs ( <STR_LIT> , asm_out_file ) ;

output_addr_const ( asm_out_file , symbol ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; assert ( insn -> numImmediatesConsumed < <NUM_LIT> && <STR_LIT> ) ; insn -> immediateSize = size ; insn -> immediateOffset = insn -> readerCursor - insn -> startLocation ; switch ( size ) { case <NUM_LIT> : if ( consume ( insn , imm8 ) ) return - <NUM_LIT> ; insn -> immediates [ insn -> numImmediatesConsumed ] = imm8 ; break ; case <NUM_LIT> :

if ( consume ( insn , imm16 ) ) return - <NUM_LIT> ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { SubReg = <STR_LIT> ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isFPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) && isGPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) ) return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isGPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) && isFPR64 ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) , MRI ) ) { SubReg = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } }


<s> SDLoc DL ( Op ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT VecEVT = Vec . getValueType ( ) ; if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVVPReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } SDValue VL = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ResVT = ! VecVT . isInteger ( ) || VecEltVT . bitsGE ( XLenVT ) ? VecEltVT : XLenVT ; SDValue StartSplat = lowerScalarSplat ( SDValue ( ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , StartSplat , Vec , StartSplat , Mask , VL ) ;

SDValue Elt0 = DAG . getNode ( <STR_LIT> , DL , ResVT , Reduction , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;


<s> return BrOpc == <STR_LIT> || BrOpc == <STR_LIT> || BrOpc == <STR_LIT> || BrOpc == <STR_LIT> ;


<s> void <ISA_LIT>HazardRecognizer :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) ) { LastMI = MI ; FpMLxStalls = <NUM_LIT> ; }

ScoreboardHazardRecognizer :: EmitInstruction ( SU ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>InstrInfo ( ST ) , RI ( ) , ST ( ST ) {


<s> switch ( cc ) { case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_LS :


<s> Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ;


<s> if ( ! isCFProtectionSupported && ! IndirectBranchTracking ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) { auto MBB = MF . begin ( ) ; addENDBR ( * MBB ) ;


<s> unsigned Offset1 = Offset1Op -> getImm ( ) ; if ( Offset0 + <NUM_LIT> != Offset1 ) return false ; unsigned EltSize ; if ( LdSt . mayLoad ( ) ) EltSize = TRI -> getRegSizeInBits ( * getOpRegClass ( LdSt , <NUM_LIT> ) ) / <NUM_LIT> ; else { assert ( LdSt . mayStore ( ) ) ; int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = TRI -> getRegSizeInBits ( * getOpRegClass ( LdSt , Data0Idx ) ) / <NUM_LIT> ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; BaseOps . push_back ( BaseOp ) ; Offset = EltSize * Offset0 ; DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdst ) ; if ( DataOpIdx == - <NUM_LIT> ) { DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; Width = getOpSize ( LdSt , DataOpIdx ) ; DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: data1 ) ; Width += getOpSize ( LdSt , DataOpIdx ) ; } else { Width = getOpSize ( LdSt , DataOpIdx ) ; } } return true ; } if ( isMUBUF ( LdSt ) || isMTBUF ( LdSt ) ) { const MachineOperand * RSrc = getNamedOperand ( LdSt , <STR_LIT> :: srsrc ) ; if ( ! RSrc ) return false ; BaseOps . push_back ( RSrc ) ; BaseOp = getNamedOperand ( LdSt , <STR_LIT> :: vaddr ) ; if ( BaseOp && ! BaseOp -> isFI ( ) ) BaseOps . push_back ( BaseOp ) ; const MachineOperand * OffsetImm = getNamedOperand ( LdSt , <STR_LIT> :: offset ) ; Offset = OffsetImm -> getImm ( ) ; const MachineOperand * SOffset = getNamedOperand ( LdSt , <STR_LIT> :: soffset ) ; if ( SOffset ) { if ( SOffset -> isReg ( ) ) BaseOps . push_back ( SOffset ) ; else Offset += SOffset -> getImm ( ) ; } DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdst ) ; if ( DataOpIdx == - <NUM_LIT> ) DataOpIdx = <STR_LIT> ( Opc , <STR_LIT> :: vdata ) ; Width = getOpSize ( LdSt , DataOpIdx ) ; return true ; } if ( isMIMG ( LdSt ) ) { int SRsrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ;

BaseOps . push_back ( & LdSt . getOperand ( SRsrcIdx ) ) ;


<s> StringRef getPassName ( ) const override {


<s> void addLoc ( const CCValAssign & V ) {


<s> operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ;


<s> int need ; live_regs_mask = calc_live_regs ( & d ) ; if ( frame_pointer_needed ) { if ( TARGET_BIG ) emit_insn ( gen_movsi ( stack_pointer_rtx , frame_pointer_rtx ) ) ; else emit_insn ( gen_movhi ( stack_pointer_rtx , frame_pointer_rtx ) ) ; need = <NUM_LIT> ; } else { need = get_frame_size ( ) ;


<s> auto Children = Region -> getChildren ( ) ; for ( auto CI : * Children ) { if ( ! CI -> isRegion ( ) ) { if ( CI -> getMBBMRT ( ) -> getMBB ( ) -> succ_size ( ) > <NUM_LIT> ) {


<s> const DataLayout * getDataLayout ( ) const override {


<s> SpilledReg ( Register R , int L ) : VGPR ( R ) , Lane ( L ) {


<s> SDValue M0 = Lowering . copyToM0 ( * CurDAG , CurDAG -> getEntryNode ( ) , SDLoc ( N ) , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } Ops . push_back ( Glue ) ;

return CurDAG -> MorphNodeTo ( N , N -> getOpcode ( ) , N -> getVTList ( ) , Ops ) ;


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ;


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldReduceLoadWidth ( SDNode * N , <STR_LIT> , EVT NewVT ) const {

unsigned NewSize = NewVT . getStoreSizeInBits ( ) ;


<s> <STR_LIT> TargetFlags = <STR_LIT> ; if ( GV -> hasDLLImportStorageClass ( ) ) TargetFlags = <STR_LIT> ; else if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) TargetFlags = <STR_LIT> ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; SDLoc DL ( Op ) ; ++ NumMovwMovt ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , TargetFlags ) ) ; if ( TargetFlags & ( <STR_LIT> | <STR_LIT> ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result ;


LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Src1MBB -> getNumber ( ) << <STR_LIT> << Src2MBB -> getNumber ( ) << <STR_LIT> ; ) ;


<s> switch ( RegNo ) { case <NUM_LIT> : Register = <STR_LIT> ; break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; default : return MCDisassembler :: Fail ; }

Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> static SDValue lowerVectorShuffleAsElementInsertion ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT ExtVT = VT ; MVT EltVT = VT . getVectorElementType ( ) ; int V2Index = find_if ( Mask , [ & Mask ] ( int M ) { return M >= ( int ) Mask . size ( ) ; } ) - Mask . begin ( ) ; bool IsV1Zeroable = true ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( i != V2Index && ! Zeroable [ i ] ) { IsV1Zeroable = false ; break ; } SDValue V2S = getScalarValueForVectorElement ( V2 , Mask [ V2Index ] - Mask . size ( ) , DAG ) ; if ( V2S && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( V2S . getValueType ( ) ) ) { V2S = DAG . getBitcast ( EltVT , V2S ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) {


<s> StatepointOpers SOpers ( & MI ) ; if ( unsigned PatchBytes = SOpers . getNumPatchBytes ( ) ) { EmitNops ( * OutStreamer , PatchBytes , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; } else { const MachineOperand & CallTarget = SOpers . getCallTarget ( ) ; MCOperand CallTargetMCOp ; unsigned CallOpcode ; switch ( CallTarget . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : CallTargetMCOp = MCIL . LowerSymbolOperand ( CallTarget , MCIL . GetSymbolFromOperand ( CallTarget ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Immediate :

CallTargetMCOp = MCOperand :: createImm ( CallTarget . getImm ( ) ) ;


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm , JITCodeEmitter & mce ) : MachineFunctionPass ( ID ) , JTI ( nullptr ) , II ( nullptr ) , TD ( nullptr ) , TM ( tm ) , MCE ( mce ) , MCPEs ( nullptr ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & ST ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align ( <NUM_LIT> ) ) {


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <NUM_LIT> , <NUM_LIT> ) , RI ( ST , * this ) , Subtarget ( ST ) {


<s> handleSpecialCases ( BIL , MBB ) ; reorganizeBlockLayout ( BIL , MBB ) ; populateBlocks ( BIL ) ;


<s> unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Imm . getActiveBits ( ) >= <NUM_LIT> ) return <NUM_LIT> ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( Bits == <NUM_LIT> || ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) ) return <NUM_LIT> ; if ( ( ~ SImmVal < <NUM_LIT> ) || <STR_LIT> ( ZImmVal ) ) return <NUM_LIT> ;


<s> SDLoc DL ( Op ) ; SDValue Ops [ <NUM_LIT> ] ; if ( is32Bit ( VT ) ) lowerMUL_LOHI32 ( DAG , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; else { SDValue C63 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue LL = Op . getOperand ( <NUM_LIT> ) ;

SDValue RL = Op . getOperand ( <NUM_LIT> ) ;


<s> bool Error ( SMLoc L , const Twine & Msg ) {


<s> static SDValue getVShift ( bool isLeft , MVT VT , SDValue SrcOp , unsigned NumBits , SelectionDAG & DAG , const TargetLowering & TLI , DebugLoc dl ) { bool isMMX = VT . getSizeInBits ( ) == <NUM_LIT> ; MVT ShVT = isMMX ? <STR_LIT> : <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI . getShiftAmountTy ( ) ) ) ) ;


<s> if ( MI . getOpcode ( ) != <STR_LIT> && ( Offset >= <NUM_LIT> || Offset < - <NUM_LIT> ) ) { BaseReg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( ! BaseReg ) { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; BaseReg = RS -> scavengeRegister ( & <STR_LIT> , II , SPAdj ) ; assert ( BaseReg && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( BaseReg , TRI ) << <STR_LIT> << PrintReg ( FrameReg , TRI ) << <STR_LIT> << Offset << <STR_LIT> ) ; ( void ) TRI ; RS -> setRegUsed ( BaseReg ) ; } unsigned AddOpc = isUInt < <NUM_LIT> > ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( AddOpc ) ) . addReg ( BaseReg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; KillState = RegState :: Kill ; } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) , Reg ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; break ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ;

BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addReg ( BaseReg , KillState ) . addImm ( Offset ) . addMemOperand ( * MI . memoperands_begin ( ) ) ;


<s> assert ( nodeCost != WorstCaseGlobalEnsureFilling . end ( ) && ! Node -> isDead ( ) ) ; return nodeCost -> second ;


<s> void <ISA_LIT>InstPrinter :: printVectorIndex ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm ( ) << <STR_LIT> ;


<s> inline static unsigned get<ISA_LIT>ImmediateShift ( uint64_t TSFlags ) {

return ( TSFlags >> <NUM_LIT> ) & <NUM_LIT> ;


<s> SDValue ShiftRightLogicInByte ( SDValue A , int immInByte ) { MVT VT = A . getSimpleValueType ( ) ; assert ( ( VT . getSizeInBits ( ) == <NUM_LIT> || VT . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && VT != <STR_LIT> ) A = BITCAST ( A , <STR_LIT> ) ; SDValue B = DAG -> getNode ( <STR_LIT> , dl , <STR_LIT> , DAG -> getConstant ( <STR_LIT> , <STR_LIT> ) , A , Constant ( immInByte * <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( ! TargetLoweringBase :: shouldReduceLoadWidth ( N , ExtTy , NewVT ) ) return false ; unsigned NewSize = NewVT . getStoreSizeInBits ( ) ; if ( NewSize == <NUM_LIT> ) return true ; EVT OldVT = N -> getValueType ( <NUM_LIT> ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ; MemSDNode * MN = cast < MemSDNode > ( N ) ;

unsigned AS = MN -> getAddressSpace ( ) ;


<s> OutStreamer . EmitIntValue ( S_00B028_VGPRS ( KernelInfo . VGPRBlocks ) | S_00B028_SGPRS ( KernelInfo . SGPRBlocks ) , <NUM_LIT> ) ; if ( STM . isVGPRSpillingEnabled ( MFI ) ) { OutStreamer . EmitIntValue ( R_0286E8_SPI_TMPRING_<ISA_LIT>ZE , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( S_0286E8_WAVE<ISA_LIT>ZE ( KernelInfo . ScratchBlocks ) , <NUM_LIT> ) ; } } if ( MFI -> getShaderType ( ) == ShaderType :: PIXEL ) {

OutStreamer . EmitIntValue ( R_00B02C_SPI_SHADER_PGM_RSRC2_PS , <NUM_LIT> ) ;


<s> OptimizeReturned ( ) : FunctionPass ( ID ) {


<s> DEBUG ( dbgs ( ) << '\n' ) ; Instruction * InsertionPoint = findInsertionPoint ( UseIt ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( InsertionPoint -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << '\n' ) ; InsertionPoints & InsertPts = InsPtsPerFunc [ InsertionPoint -> getParent ( ) -> getParent ( ) ] ; if ( isDominated ( InsertionPoint , UseIt , InsertPts ) ) continue ; if ( tryAndMerge ( InsertionPoint , UseIt , InsertPts ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; InsertPts [ InsertionPoint ] . push_back ( UseIt ) ; }


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & C , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget . useCRBits ( ) ? <STR_LIT> : <STR_LIT> ;

if ( Subtarget . hasQPX ( ) ) return EVT :: getVectorVT ( C , <STR_LIT> , VT . getVectorNumElements ( ) ) ;


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const ScheduleDAG * DAG ) : ScoreboardHazardRecognizer ( ItinData , DAG , <STR_LIT> ) , LastMI ( nullptr ) {


<s> MCSymbol * RelocSymbol = <ISA_LIT>FI -> getPICOffsetSymbol ( ) ; MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer -> EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: create ( PICBase , OutContext ) , OutContext ) ; OutStreamer -> EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! MF -> getRegInfo ( ) . use_empty ( <STR_LIT> ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; MCSymbol * GlobalEPSymbol = <ISA_LIT>FI -> getGlobalEPSymbol ( ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , MCSymbolRefExpr :: create ( GlobalEPSymbol , OutContext ) , OutContext ) ; OutStreamer -> EmitLabel ( <ISA_LIT>FI -> getTOCOffsetSymbol ( ) ) ; OutStreamer -> EmitValue ( TOCDeltaExpr , <NUM_LIT> ) ; } return AsmPrinter :: EmitFunctionEntryLabel ( ) ; }

MCSectionSubPair Current = OutStreamer -> getCurrentSection ( ) ;


<s> OS . EmitIntValue ( GPRInfoSet ? GPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPRBitMask : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FPRInfoSet ? FPROffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameOffset : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? FrameReg : <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( FrameInfoSet ? ReturnReg : <NUM_LIT> , <NUM_LIT> ) ;

GPRInfoSet = FPRInfoSet = FrameInfoSet = false ;


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) {


<s> OptimizeReturned ( ) : FunctionPass ( ID ) , DT ( nullptr ) {


<s> for ( auto PDep : SDep . getSUnit ( ) -> Preds ) { auto PSU = PDep . getSUnit ( ) ; assert ( ! PSU -> isBoundaryNode ( ) ) ; if ( PSU != SU && ! isScheduled ( PSU ) ) { wouldBeScheduled = false ;


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ;

return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> if ( ! SVOp -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) ) return false ; if ( isVectorShiftLeft ( SVOp , DAG , isLeft , ShVal , ShAmt ) || isVectorShiftRight ( SVOp , DAG , isLeft , ShVal , ShAmt ) ) return true ; return false ;


<s> unsigned SSECC ; bool Swap = false ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( SSECC == <NUM_LIT> ) { unsigned CC0 , CC1 ; unsigned CombineOpc ; if ( SetCCOpcode == <STR_LIT> ) { CC0 = <NUM_LIT> ; CC1 = <NUM_LIT> ; CombineOpc = <STR_LIT> ; } else { assert ( SetCCOpcode == <STR_LIT> ) ; CC0 = <NUM_LIT> ; CC1 = <NUM_LIT> ; CombineOpc = <STR_LIT> ; } SDValue Cmp0 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( CC0 , <STR_LIT> ) ) ; SDValue Cmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( CC1 , <STR_LIT> ) ) ; return DAG . getNode ( CombineOpc , dl , VT , Cmp0 , Cmp1 ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_INT ( SDValue Op , SelectionDAG & DAG ) const { bool IsStrict = Op -> isStrictFPOpcode ( ) ; SDValue SrcVal = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; if ( SrcVal . getValueType ( ) . isVector ( ) ) return LowerVectorFP_TO_INT ( Op , DAG ) ; if ( SrcVal . getValueType ( ) == <STR_LIT> && ! Subtarget -> hasFullFP16 ( ) ) { assert ( ! IsStrict && <STR_LIT> ) ; SDLoc dl ( Op ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SrcVal ) ) ; } if ( SrcVal . getValueType ( ) != <STR_LIT> ) { return Op ; } return SDValue ( ) ;


<s> static DecodeStatus DecodeThumbAddrModeIS ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; return S ;


<s> static __inline unsigned long long sh_media_MSUB_L ( unsigned long long mm , unsigned long long mn ) { typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ; return ( unsigned long long ) __builtin_subv2si3 ( ( v2si ) mm , ( v2si ) mn ) ;


<s> const <ISA_LIT>RegisterInfo & QRI = getRegisterInfo ( ) ; const uint64_t F = MI -> getDesc ( ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> & QRI . Subtarget . hasV4TOps ( ) ) ;


<s> addRegOffset ( MIB , leaInReg , true , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned Src2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill2 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned leaInReg2 = <NUM_LIT> ; MachineInstr * InsMI2 = nullptr ; if ( Src == Src2 ) { addRegReg ( MIB , leaInReg , true , leaInReg , false ) ; } else { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; else leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , & * MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) ; InsMI2 = BuildMI ( * MFI , & * MIB , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( leaInReg2 , RegState :: Define , <STR_LIT> ) . addReg ( Src2 , getKillRegState ( isKill2 ) ) ; addRegReg ( MIB , leaInReg , true , leaInReg2 , true ) ; } if ( LV && isKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , InsMI2 ) ; break ; } } MachineInstr * NewMI = MIB ;

MachineInstr * ExtMI = BuildMI ( * MFI , MBBI , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( Dest , RegState :: Define | getDeadRegState ( isDead ) ) . addReg ( leaOutReg , RegState :: Kill , <STR_LIT> ) ;


<s> } MachineBasicBlock * TopBlock = L -> getTopBlock ( ) ; MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ; MachineBasicBlock * LoopStart = nullptr ; if ( ExitingBlock != L -> getLoopLatch ( ) ) { MachineBasicBlock * TB = nullptr , * FB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; if ( TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ) return false ; if ( L -> contains ( TB ) ) LoopStart = TB ; else if ( L -> contains ( FB ) ) LoopStart = FB ; else return false ; } else LoopStart = TopBlock ; DEBUG ( dbgs ( ) << <STR_LIT> ; L -> dump ( ) ) ; DebugLoc DL ; if ( InsertPos != Preheader -> end ( ) ) DL = InsertPos -> getDebugLoc ( ) ; if ( TripCount -> isReg ( ) ) { unsigned CountReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * Preheader , InsertPos , DL , TII -> get ( TargetOpcode :: COPY ) , CountReg ) . addReg ( TripCount -> getReg ( ) , <NUM_LIT> , TripCount -> getSubReg ( ) ) ; BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ; } else { assert ( TripCount -> isImm ( ) && <STR_LIT> ) ; int64_t CountImm = TripCount -> getImm ( ) ; if ( ! TII -> isValidOffset ( LOOP_i , CountImm ) ) { unsigned CountReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * Preheader , InsertPos , DL , TII -> get ( <STR_LIT> ) , CountReg ) . addImm ( CountImm ) ; BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ;

} else BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_i ) ) . addMBB ( LoopStart ) . addImm ( CountImm ) ;


<s> assert ( ( Count % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; OW -> WriteZeros ( Count ) ; return true ;


return ( __m128 ) __builtin_ia32_loadss ( & __F ) ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm ) , TM ( tm ) {


<s> } if ( Lexer . is ( AsmToken :: EndOfStatement ) && Name . startswith ( <STR_LIT> ) && Operands . size ( ) == <NUM_LIT> ) { Operands . erase ( Operands . begin ( ) , Operands . begin ( ) + <NUM_LIT> ) ; Operands . insert ( Operands . begin ( ) , <STR_LIT> ( <STR_LIT> , NameLoc ) ) ; } while ( Lexer . isNot ( AsmToken :: EndOfStatement ) && Lexer . is ( AsmToken :: Comma ) ) { Lexer . Lex ( ) ; if ( parseOperand ( & Operands , Mnemonic ) != MatchOperand_Success ) return true ; } if ( IsMemoryAssignmentError ( Operands ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; return true ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; const char * EndPtr = Tok . getLoc ( ) . getPointer ( ) + LineBuf . size ( ) ; while ( true ) { End = Tok . getEndLoc ( ) ; getLexer ( ) . Lex ( ) ; assert ( End . getPointer ( ) <= EndPtr && <STR_LIT> ) ; if ( End . getPointer ( ) == EndPtr ) break ; } Identifier = LineBuf ; if ( ! Result ) { StringRef InternalName = SemaCallback -> LookupInlineAsmLabel ( Identifier , getSourceManager ( ) , Loc , false ) ; assert ( InternalName . size ( ) && <STR_LIT> ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Label , Loc , Identifier . size ( ) , InternalName ) ) ; } MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Identifier ) ;

MCSymbolRefExpr :: VariantKind Variant = MCSymbolRefExpr :: VK_None ;


<s> unsigned TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned TfrOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( TfrOpc ) , TmpR ) . addReg ( SrcR , getKillRegState ( IsKill ) ) ;

BuildMI ( B , It , DL , HII . get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( TmpR , RegState :: Kill ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> case <STR_LIT> : { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( N0 ) && IsFoldableRMW ( N0 , Op ) ) return false ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Commute = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( N1 ) && ( ! Commute || ! isa < ConstantSDNode > ( N0 ) || ( Op . getOpcode ( ) != <STR_LIT> && IsFoldableRMW ( N1 , Op ) ) ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ( Commute && ! isa < ConstantSDNode > ( N1 ) ) || ( Op . getOpcode ( ) != <STR_LIT> && IsFoldableRMW ( N0 , Op ) ) ) ) return false ; if ( IsFoldableAtomicRMW ( N0 , Op ) || ( Commute && IsFoldableAtomicRMW ( N1 , Op ) ) ) return false ; }


<s> inline static bool isGlobalRelativeToPICBase ( unsigned char TargetFlag ) { switch ( TargetFlag ) { default : return false ; case <STR_LIT> : case <STR_LIT> : return true ;


<s> if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) { DCI . CombineTo ( N , Res ) ; return SDValue ( ) ; }


<s> for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) , EE = MBB -> end ( ) ; MBBI != EE ; ++ MBBI ) BlockSize += TII -> GetInstSizeInBytes ( MBBI ) ; BlockSizes [ MBB -> getNumber ( ) ] = BlockSize ; FuncSize += BlockSize ; } if ( FuncSize < ( <NUM_LIT> << <NUM_LIT> ) ) { BlockSizes . clear ( ) ; return false ; } bool MadeChange = true ; bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * Dest = nullptr ; if ( I -> getOpcode ( ) == <STR_LIT> && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; else if ( ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; else if ( ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) && ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! Dest ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) {


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && ( Imm != <NUM_LIT> ) && isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> return true ; } assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( LoADDI -> getOpcode ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getType ( ) != MachineOperand :: MO_GlobalAddress || LoADDI -> getOperand ( <NUM_LIT> ) . getOffset ( ) != <NUM_LIT> || ! MRI -> hasOneUse ( LoADDI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; return true ;


<s> virtual void EmitCFIEndProcImpl ( MCDwarfFrameInfo & Frame ) { RecordProcEnd ( Frame ) ;


<s> const TargetRegisterInfo * TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; int WaitStates = - <NUM_LIT> ; for ( MachineInstr * MI : EmittedInstrs ) {


<s> AlignBranchType . addKind ( <STR_LIT> ) ; AlignBranchType . addKind ( <STR_LIT> ) ; } if ( <ISA_LIT>AlignBranchBoundary . getNumOccurrences ( ) ) AlignBoundary = assumeAligned ( <ISA_LIT>AlignBranchBoundary ) ;

if ( <ISA_LIT>AlignBranch . getNumOccurrences ( ) ) AlignBranchType = <ISA_LIT>AlignBranchKindLoc ;


<s> if ( isRegOrImmWithInputMods ( Desc , Inst . getNumOperands ( ) ) ) { Op . addRegOrImmWithInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { llvm_unreachable ( <STR_LIT> ) ; } skippedVcc = false ; } if ( Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) { switch ( BasicInstType ) { case <STR_LIT> : addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> , <NUM_LIT> ) ; if ( <STR_LIT> ( Inst . getOpcode ( ) , <STR_LIT> :: omod ) != - <NUM_LIT> ) { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOMod<ISA_LIT> , <NUM_LIT> ) ; } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstSel , SdwaSel :: DWORD ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstUnused , DstUnused :: UNUSED_PRESERVE ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc0Sel , SdwaSel :: DWORD ) ; break ; case <STR_LIT> : addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> , <NUM_LIT> ) ; if ( <STR_LIT> ( Inst . getOpcode ( ) , <STR_LIT> :: omod ) != - <NUM_LIT> ) { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOMod<ISA_LIT> , <NUM_LIT> ) ; } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstSel , SdwaSel :: DWORD ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaDstUnused , DstUnused :: UNUSED_PRESERVE ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc0Sel , SdwaSel :: DWORD ) ;

addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySdwaSrc1Sel , SdwaSel :: DWORD ) ;


<s> resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle , F . optForMinSize ( ) ) ; if ( ! I -> isThumb ( ) && ! I -> has<ISA_LIT>Ops ( ) ) F . getContext ( ) . emitError ( <STR_LIT> + F . getName ( ) + <STR_LIT> <STR_LIT> ) ; } return I . get ( ) ;