<s> Offset = Addr ; return true ; } } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) && Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue LoVal = Addr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( LoVal . getOperand ( <NUM_LIT> ) ) || isa < GlobalAddressSDNode > ( LoVal . getOperand ( <NUM_LIT> ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = LoVal . getOperand ( <NUM_LIT> ) ; return true ; } }


<s> return __builtin_aarch64_lroundsfsi ( __a ) ;


<s> SDLoc DL ( CachePolicy ) ; if ( GLC ) { * GLC = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ; Value &= ~ ( uint64_t ) <NUM_LIT> ; } if ( SLC ) { * SLC = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ;


<s> byte_mode_size_tmp = expand_binop ( SImode , and_optab , size , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( byte_mode_size , byte_mode_size_tmp ) ; emit_label ( word_mode_label ) ; emit_insn ( gen_unaligned_store_update_base_dw ( itr , itr , value ) ) ; emit_cmp_and_jump_insns ( word_mode_end , itr , NE , NULL , Pmode , <NUM_LIT> , word_mode_label ) ; emit_label ( word_mode_end_label ) ; return byte_mode_size ;


<s> __inline__ static unsigned long long sh_media_MEXTR6 ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ;


addPass ( create<ISA_LIT>LowerBrUnless ( ) ) ;


<s> } ) != To -> getParent ( ) -> rend ( ) ) ; for ( -- To ; To != From ; -- To ) { const MachineInstr & Instr = * To ;

if ( ( ( AccessToCheck & AK_Write ) && Instr . modifiesRegister ( <STR_LIT> , TRI ) ) || ( ( AccessToCheck & AK_Read ) && Instr . readsRegister ( <STR_LIT> , TRI ) ) ) return true ;


<s> return MF . getContext ( ) . GetOrCreateSymbol ( Twine ( DL -> getPrivateGlobalPrefix ( ) ) + Twine ( MF . getFunctionNumber ( ) ) + <STR_LIT> ) ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . isTargetWindows ( ) ) return false ; const Function & F = MF . getFunction ( ) ; unsigned StackProbeSize = <NUM_LIT> ;

if ( F . hasFnAttribute ( <STR_LIT> ) ) F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ;


<s> case <ISA_LIT>Subtarget :: isELF : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return new <ISA_LIT>64_ELFTargetObjectFile ( TM ) ; return new <ISA_LIT>32_ELFTargetObjectFile ( TM ) ; case <ISA_LIT>Subtarget :: isMingw : case <ISA_LIT>Subtarget :: isCygwin :


<s> std :: make_unique < PostGenericScheduler > ( C ) , true ) ;

if ( ST . hasFusion ( ) ) DAG -> addMutation ( createPowerPCMacroFusionDAGMutation ( ) ) ;


<s> void Session :: UpdateIT ( ) { assert ( ITCounter ) ; -- ITCounter ;

if ( ITCounter == <NUM_LIT> ) ITState = <NUM_LIT> ;


<s> <ISA_LIT>GlobalRegistry :: <ISA_LIT>GlobalRegistry ( unsigned PointerSize ) : PointerSize ( PointerSize ) {


<s> return new AMDGPUPromoteAlloca ( ST ) ;


<s> const MCOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) << <NUM_LIT> ;


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Src -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { SDValue UnpkOp = Src -> getOperand ( <NUM_LIT> ) ; SDValue Dup = N -> getOperand ( <NUM_LIT> ) ; if ( Dup . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Dup -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; uint64_t ExtVal = C -> getZExtValue ( ) ; EVT EltTy = UnpkOp -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) ) return Src ;

APInt Mask = C -> getAPIntValue ( ) . trunc ( EltTy . getSizeInBits ( ) ) ;


<s> unsigned addr = <NUM_LIT> ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( DecodeGPR8RegisterClass ( Inst , reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( addr ) ) ; return MCDisassembler :: Success ;


<s> void <ISA_LIT>TargetLowering :: addDRTypeForNEON ( MVT VT ) { addRegisterClass ( VT , & <STR_LIT> ) ; addTypeForNEON ( VT , <STR_LIT> ) ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ; TII . storeRegToStackSlot ( * BB , MI , SrcReg , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , FI , SrcRC , RI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , LoReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) , HiReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ; return BB ;


<s> RegDefsUses :: RegDefsUses ( const TargetRegisterInfo & TRI ) : TRI ( TRI ) , Defs ( TRI . getNumRegs ( ) , false ) , Uses ( TRI . getNumRegs ( ) , false ) {


<s> assert ( isValid ( ) && ! isUnknown ( ) && <STR_LIT> ) ; return getSEWLMULRatio ( SEW , VLMul ) ;


<s> SMLoc ArchLoc = Parser . getTok ( ) . getLoc ( ) ; Lex ( ) ; <STR_LIT> ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> :: INVALID ) return Error ( ArchLoc , <STR_LIT> + Arch + <STR_LIT> ) ;

if ( parseToken ( AsmToken :: EndOfStatement ) ) return true ;


<s> if ( crtl -> profile ) return false ; return known_eq ( cfun -> machine -> frame . frame_size , <NUM_LIT> ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


<s> static void lowerGR128Binary ( SelectionDAG & DAG , const SDLoc & DL , EVT VT , unsigned Extend , unsigned Opcode , SDValue Op0 , SDValue Op1 , SDValue & Even , SDValue & Odd ) { SDNode * In128 = DAG . getMachineNode ( Extend , DL , <STR_LIT> , Op0 ) ; SDValue Result = DAG . getNode ( Opcode , DL , <STR_LIT> , SDValue ( In128 , <NUM_LIT> ) , Op1 ) ; bool Is32Bit = is32Bit ( VT ) ; Even = DAG . getTargetExtractSubreg ( <STR_LIT> ( Is32Bit ) , DL , VT , Result ) ; Odd = DAG . getTargetExtractSubreg ( <STR_LIT> ( Is32Bit ) , DL , VT , Result ) ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , const Triple & TT ) : <ISA_LIT>AsmBackend ( T ) , Is64Bit ( TT . getArch ( ) == Triple :: amdgcn ) , HasRelocationAddend ( TT . getOS ( ) == Triple :: AMDHSA ) {


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getNewValOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ;

if ( shouldInlineQuadwordAtomics ( ) && Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ;


<s> void relaxInstruction ( const MCInst & , llvm :: MCInst & ) const {


<s> static inline bool is_naked_func ( const_tree decl ) { return has_func_attr ( decl , <STR_LIT> ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , raw_ostream & O ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( O , MAI ) ;

if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>IntelInstPrinter ( O , MAI ) ;


<s> if ( arch == llvm :: ELF :: EF_MIPS_ARCH_1 || arch == llvm :: ELF :: EF_MIPS_ARCH_2 || arch == llvm :: ELF :: EF_MIPS_ARCH_32 || arch == llvm :: ELF :: EF_MIPS_ARCH_32R2 || arch == llvm :: ELF :: EF_MIPS_ARCH_32R6 ) return true ; uint64_t abi = flags & llvm :: ELF :: EF_MIPS_ABI ;

if ( abi == llvm :: ELF :: EF_MIPS_ABI_O32 || abi == llvm :: ELF :: EF_MIPS_ABI_EABI32 ) return true ;


<s> if ( ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; MVT AVT = <STR_LIT> ; if ( Subtarget -> is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) AVT = <STR_LIT> ; unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned CountVal = SizeVal / UBytes ; SDValue Count = DAG . getIntPtrConstant ( CountVal ) ; unsigned BytesLeft = SizeVal % UBytes ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getValueType ( AVT ) ) ; Ops . push_back ( InFlag ) ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( BytesLeft ) { unsigned Offset = SizeVal - BytesLeft ; MVT DstVT = Dst . getValueType ( ) ; MVT SrcVT = Src . getValueType ( ) ; MVT SizeVT = Size . getValueType ( ) ;

Results . push_back ( DAG . getMemcpy ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , DstVT , Dst , DAG . getConstant ( Offset , DstVT ) ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstant ( Offset , SrcVT ) ) , DAG . getConstant ( BytesLeft , SizeVT ) , Align , AlwaysInline , DstSV , DstSVOff + Offset , SrcSV , SrcSVOff + Offset ) ) ;


<s> KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Sel = CMask -> getZExtValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += <NUM_LIT> ) { unsigned SelBits = Sel & <NUM_LIT> ; if ( SelBits < <NUM_LIT> ) { SelBits *= <NUM_LIT> ; Known . One |= ( ( RHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( RHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits < <NUM_LIT> ) { SelBits = ( SelBits & <NUM_LIT> ) * <NUM_LIT> ; Known . One |= ( ( LHSKnown . One . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; Known . Zero |= ( ( LHSKnown . Zero . getZExtValue ( ) >> SelBits ) & <NUM_LIT> ) << I ; } else if ( SelBits == <NUM_LIT> ) { Known . Zero |= <NUM_LIT> << I ; } else if ( SelBits > <NUM_LIT> ) { Known . One |= <NUM_LIT> << I ; } Sel >>= <NUM_LIT> ; } break ; } case <STR_LIT> : { Known . Zero . setHighBits ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { Known . Zero . setHighBits ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { auto GA = cast < GlobalAddressSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; unsigned Align = GA -> getGlobal ( ) -> getAlignment ( ) ; Known . Zero . setHighBits ( <NUM_LIT> ) ; if ( Align ) Known . Zero . setLowBits ( Log2_32 ( Align ) ) ; break ; }


<s> <ISA_LIT>OptAddrMode ( ) : MachineFunctionPass ( ID ) {


<s> return ! ( STI . getFeatureBits ( ) & <STR_LIT> ) ;


<s> MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ;

for ( MachineFunction :: iterator MFI = MF . begin ( ) , MFE = MF . end ( ) ; MFI != MFE ;


<s> LLT VecTy = LLT :: vector ( <NUM_LIT> , ValTy ) ; Register PackedVal = B . buildBuildVector ( VecTy , { NewVal , CmpVal } ) . getReg ( <NUM_LIT> ) ;

B . buildInstr ( <STR_LIT> ) . addDef ( DstReg ) . addUse ( PtrReg ) . addUse ( PackedVal ) . setMemRefs ( MI . memoperands ( ) ) ;


<s> MachineBasicBlock :: iterator FirstEpilogSEH = std :: prev ( MBBI ) ; while ( FirstEpilogSEH -> getFlag ( MachineInstr :: FrameDestroy ) && FirstEpilogSEH != MBB . begin ( ) ) FirstEpilogSEH = std :: prev ( FirstEpilogSEH ) ; if ( FirstEpilogSEH != MBB . begin ( ) ) FirstEpilogSEH = std :: next ( FirstEpilogSEH ) ; BuildMI ( MBB , FirstEpilogSEH , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addMBB ( TargetMBB ) ; BuildMI ( MBB , FirstEpilogSEH , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addMBB ( TargetMBB ) . addImm ( <NUM_LIT> ) ; return true ; } Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI . memoperands_begin ( ) ) -> getValue ( ) ) ; const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; unsigned OpFlags = Subtarget . ClassifyGlobalReference ( GV , TM ) ; const unsigned char MO_NC = <STR_LIT> ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ;

if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ;


<s> if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( hasMovingSP && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumb2Function ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) {


<s> AllowAtInName = true ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ; ProtectedVisibilityAttr = MCSA_Invalid ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; if ( LHS . getValueType ( ) . isFatPointer ( ) ) { LHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , LHS ) ; RHS = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , XLenVT , RHS ) ; } SDValue TargetCC = DAG . getCondCode ( CCVal ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , LHS , RHS , TargetCC , Op . getOperand ( <NUM_LIT> ) ) ;


<s> return MF . getFunction ( ) . optForMinSize ( ) ;


<s> return <NUM_LIT> - mcore_num_ones ( mask ) ;


<s> return __builtin_aarch64_frecpev2sf ( __a ) ;


<s> rtx ndirty = GEN_INT ( GET_MODE_SIZE ( GET_MODE ( mem ) ) ) ; if ( ! cache_fetch_dirty ) cache_fetch_dirty = init_one_libfunc ( <STR_LIT> ) ; emit_library_call_value ( cache_fetch_dirty , data_addr , LCT_NORMAL , Pmode , <NUM_LIT> , ea_addr , EAmode , ndirty , SImode ) ;


<s> CASE ( LinkageType , Export ) CASE ( LinkageType , Import ) break ; }


<s> DA = & getAnalysis < DivergenceAnalysis > ( ) ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; bool MadeChange = false ; for ( BasicBlock & BB : F ) { BasicBlock :: iterator Next ;

for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; I = Next ) {


<s> if ( TARGET_SINGLE_PIC_BASE ) return false ; if ( cfun -> is_thunk ) return true ;

return cfun -> machine -> r2_setup_needed ;


<s> return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( Shift . ShiftTy , <NUM_LIT> ) ) ) ;


<s> const int ifun = xstormy16_interrupt_function_p ( ) ; mem_pop_rtx = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; mem_pop_rtx = gen_rtx_MEM ( HImode , mem_pop_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . locals_size ) { if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ;

else emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . locals_size ) ) ;


<s> if ( ! Scope ) return ; StringRef fileName ( Scope -> getFilename ( ) ) ; StringRef dirName ( Scope -> getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) { sys :: path :: append ( FullPathName , fileName ) ; fileName = FullPathName ; } if ( filenameMap . find ( fileName ) == filenameMap . end ( ) ) return ; if ( InterleaveSrc ) this -> emitSrcInText ( fileName , curLoc . getLine ( ) ) ; std :: stringstream temp ; temp << <STR_LIT> << filenameMap [ fileName ] << <STR_LIT> << curLoc . getLine ( ) << <STR_LIT> << curLoc . getCol ( ) ;

OutStreamer -> EmitRawText ( temp . str ( ) ) ;


<s> GPRInfoSet = true ; GPRBitMask = CPUBitmask ; GPROffset = CPUTopSavedRegOff ;


return ( __m128i ) __builtin_ia32_aesimc128 ( ( __v2di ) __X ) ;


<s> SDValue Reg = Is64Bit ? DAG . getRegister ( <STR_LIT> , VT ) : DAG . getNode ( <STR_LIT> , dl , VT ) ;


<s> initialize<ISA_LIT>ShortenInstPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> raw_ostream & printID ( raw_ostream & os ) const {

return os << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> << this << <STR_LIT> << MBB << <STR_LIT> ;


<s> MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , ES , RelocCST ) ) ; if ( Reloc == <STR_LIT> ) MCE . emitDWordLE ( <NUM_LIT> ) ;


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const {


<s> static Optional < MCPhysReg > tryToFindRegisterToRename ( const MachineFunction & MF , Register Reg , LiveRegUnits & DefinedInBB , LiveRegUnits & UsedInBetween , SmallPtrSetImpl < const TargetRegisterClass * > & RequiredClasses , const TargetRegisterInfo * TRI ) { const MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; auto AnySubOrSuperRegCalleePreserved = [ & MF , TRI ] ( MCPhysReg PR ) { return any_of ( TRI -> sub_and_superregs_inclusive ( PR ) , [ & MF , TRI ] ( MCPhysReg SubOrSuper ) { return TRI -> isCalleeSavedPhysReg ( SubOrSuper , MF ) ; } ) ; } ; auto CanBeUsedForAllClasses = [ & RequiredClasses , TRI ] ( MCPhysReg PR ) { return all_of ( RequiredClasses , [ PR , TRI ] ( const TargetRegisterClass * C ) { return any_of ( TRI -> sub_and_superregs_inclusive ( PR ) , [ C , TRI ] ( MCPhysReg SubOrSuper ) { return C == TRI -> getMinimalPhysRegClass ( SubOrSuper ) ; } ) ; } ) ; } ; auto * RegClass = TRI -> getMinimalPhysRegClass ( Reg ) ;

for ( const MCPhysReg & PR : * RegClass ) {


<s> if ( TREE_TYPE ( decl ) != error_mark_node && TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) == ADDR_SPACE_EA ) { if ( ! DECL_P ( decl ) ) return get_section ( <STR_LIT> , SECTION_WRITE | SECTION_DEBUG , NULL ) ; return get_named_section ( decl , <STR_LIT> , reloc ) ;


<s> if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) {


<s> int tertiary_reload_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { enum rtx_code code = GET_CODE ( op ) ; return code == MEM || ( TARGET_SH4 && code == CONST_DOUBLE ) ;


<s> void <ISA_LIT>TargetELFStreamer :: EmitDirectiveHSACodeObjectVersion ( uint32_t Major , uint32_t Minor ) {

EmitNote ( ElfNote :: NoteNameV2 , MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , ELF :: NT_AMD_HSA_CODE_OBJECT_VER<ISA_LIT>ON , [ & ] ( MCELFStreamer & OS ) {


<s> bool I2 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == S ; unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I2 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ;

return SignExtend32 < <NUM_LIT> > ( Imm25 ) ;


<s> SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; const unsigned NumFields = <NUM_LIT> ; SDValue Fields [ NumFields ] = {

DAG . getConstant ( FuncInfo -> getVarArgsFirstGPR ( ) , PtrVT ) , DAG . getConstant ( FuncInfo -> getVarArgsFirstFPR ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) , DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , PtrVT ) } ;


<s> unsigned Ra = ( MI . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = Func . getExpr ( ) ; const MCExpr * CallExpr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL , Ctx ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ;

if ( MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDLoc DL ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; if ( ! IsPositionIndependent ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ;


<s> if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , <NUM_LIT> ) ; if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - <NUM_LIT> ) ;

return TargetLowering :: getSafeStackPointerLocation ( IRB ) ;


<s> if ( Sym . getSection ( ) . getKind ( ) . isMergeableCString ( ) || Sym . getSection ( ) . getKind ( ) . isMergeableConst ( ) ) return & Sym ; return NULL ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3BMods0 ( SDValue In , SDValue & Src , SDValue & SrcMods , SDValue & Clamp , SDValue & Omod ) const { SDLoc DL ( In ) ; Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Omod = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return SelectVOP3BMods ( In , Src , SrcMods ) ;


<s> if ( pInst != nullptr ) { Out . EmitInstruction ( prevInst , STI ) ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> gcc_assert ( ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) || ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) || ( GET_CODE ( operands [ <NUM_LIT> ] ) == SUBREG ) ) ; if ( ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) && ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) ) return <NUM_LIT> ; if ( TARGET_BARREL_SHIFT ) return <NUM_LIT> ;

gcc_assert ( ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) || ( GET_CODE ( operands [ <NUM_LIT> ] ) == SUBREG ) || ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) || ( GET_CODE ( operands [ <NUM_LIT> ] ) == SUBREG ) ) ;


<s> <ISA_LIT>ConstantPoolValue :: <ISA_LIT>ConstantPoolValue ( const GlobalValue * gv , <STR_LIT> Modif ) : MachineConstantPoolValue ( ( const Type * ) Type :: getInt32Ty ( gv -> getContext ( ) ) ) , CVal ( gv ) , S ( NULL ) , LabelId ( <NUM_LIT> ) , Kind ( <STR_LIT> ) , PCAdjust ( <NUM_LIT> ) , Modifier ( Modif ) , AddCurrentAddress ( false ) {


<s> left . i [ <NUM_LIT> ] = count ; right . i [ <NUM_LIT> ] = <NUM_LIT> - count ; return ( ( qword ) ( vec_or ( vec_slo ( ( vec_uchar16 ) ( a ) , left . v ) , vec_sro ( ( vec_uchar16 ) ( a ) , right . v ) ) ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: EmitFlipSign ( const SDLoc & DL , SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op , DAG . getConstant ( APInt :: getSignMask ( VT . getSizeInBits ( ) ) , DL , VT ) ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) ) return true ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) { for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true ; } return false ;


<s> rtx_insn * insn ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; insn = mips_expand_call ( MIPS_CALL_NORMAL , v0 , mips_tls_symbol , const0_rtx , NULL_RTX , false ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return insn ;


<s> if ( ( OpSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( OpSize == <NUM_LIT> && Subtarget . hasAVX2 ( ) ) || ( OpSize == <NUM_LIT> && Subtarget . useAVX512Regs ( ) ) ) { auto BW = Subtarget . hasBWI ( ) ; EVT VecVT = OpSize == <NUM_LIT> ? ( BW ? <STR_LIT> : <STR_LIT> ) : OpSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; EVT CmpVT = OpSize == <NUM_LIT> ? ( BW ? <STR_LIT> : <STR_LIT> ) : VecVT ; SDValue Cmp ; if ( IsOrXorXorCCZero ) { SDValue A = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue B = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue C = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue D = DAG . getBitcast ( VecVT , X . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; SDValue Cmp1 = DAG . getSetCC ( DL , CmpVT , A , B , <STR_LIT> ) ; SDValue Cmp2 = DAG . getSetCC ( DL , CmpVT , C , D , <STR_LIT> ) ; Cmp = DAG . getNode ( <STR_LIT> , DL , CmpVT , Cmp1 , Cmp2 ) ; } else { SDValue VecX = DAG . getBitcast ( VecVT , X ) ; SDValue VecY = DAG . getBitcast ( VecVT , Y ) ; Cmp = DAG . getSetCC ( DL , CmpVT , VecX , VecY , <STR_LIT> ) ; } if ( OpSize == <NUM_LIT> && BW ) return DAG . getSetCC ( DL , VT , DAG . getBitcast ( <STR_LIT> , Cmp ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CC ) ; if ( OpSize == <NUM_LIT> ) return DAG . getSetCC ( DL , VT , DAG . getBitcast ( <STR_LIT> , Cmp ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CC ) ; SDValue MovMsk = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cmp ) ; SDValue FFFFs = DAG . getConstant ( OpSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ;

return DAG . getSetCC ( DL , VT , MovMsk , FFFFs , CC ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ; } return false ;


<s> if ( IRP . getPositionKind ( ) == IRPosition :: IRP_FUNCTION ) return * new ( A . Allocator ) AAAMDWorkGroupSizeFunction ( IRP , A ) ;


<s> const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return true ; } } if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && RegSize > <NUM_LIT> ) { switch ( UserOpc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return true ;


<s> assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( BB -> getParent ( ) -> getFunction ( ) . getPersonalityFn ( ) ) ) && <STR_LIT> ) ; return BB ;


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> if ( Data && Op . isIdenticalTo ( * Data ) ) return true ; MachineOperand * Data0 = TII -> getNamedOperand ( MI , <STR_LIT> :: data0 ) ; if ( Data0 && Op . isIdenticalTo ( * Data0 ) ) return true ; MachineOperand * Data1 = TII -> getNamedOperand ( MI , <STR_LIT> :: data1 ) ; if ( Data1 && Op . isIdenticalTo ( * Data1 ) ) return true ; return false ; } for ( MachineInstr :: mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( I -> isReg ( ) && I -> isUse ( ) ) return Op . isIdenticalTo ( * I ) ; }


<s> const <ISA_LIT>Subtarget & STI = MI . getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const unsigned Opcode = MI . getOpcode ( ) ;

return Opcode == <STR_LIT> || ( ! STI . is64Bit ( ) && Opcode == <STR_LIT> ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> SanityCheckImplicitOperands ( MCI ) ; std :: bitset < <NUM_LIT> > Bits ( MCI . getOperand ( MCI . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ) ; return Bits ;


<s> if ( TARGET_VXE2 && d . op0 == d . op1 && is_reverse_perm_mask ( d ) && d . vmode == V16QImode ) { if ( d . testing_p ) return true ; emit_insn ( gen_eltswapv16qi ( d . target , d . op0 ) ) ; return true ;


<s> const uint64_t F = MI -> getDesc ( ) . TSFlags ;

return ! ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; }


<s> } if ( ! table ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512 ) ; if ( table && Domain == <NUM_LIT> && table [ <NUM_LIT> ] == MI . getOpcode ( ) ) Domain = <NUM_LIT> ; } if ( ! table ) { assert ( ( Subtarget . hasDQI ( ) || Domain >= <NUM_LIT> ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512DQ ) ; if ( table && Domain == <NUM_LIT> && ( dom == <NUM_LIT> || table [ <NUM_LIT> ] == MI . getOpcode ( ) ) ) Domain = <NUM_LIT> ; } if ( ! table ) { assert ( ( Subtarget . hasDQI ( ) || Domain >= <NUM_LIT> ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512DQMasked ) ; if ( table && Domain == <NUM_LIT> && ( dom == <NUM_LIT> || table [ <NUM_LIT> ] == MI . getOpcode ( ) ) ) Domain = <NUM_LIT> ; } assert ( table && <STR_LIT> ) ;

MI . setDesc ( get ( table [ Domain - <NUM_LIT> ] ) ) ;


<s> SDLoc dl ( N ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ) ; } } if ( SDValue V = combineParity ( N , DAG , Subtarget ) ) return V ; if ( VT == <STR_LIT> ) { SmallVector < SDValue , <NUM_LIT> > SrcOps ; if ( matchScalarReduction ( SDValue ( N , <NUM_LIT> ) , <STR_LIT> , SrcOps ) && SrcOps . size ( ) == <NUM_LIT> ) { SDLoc dl ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { APInt AllBits = APInt :: getAllOnesValue ( NumElts ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , DAG . getConstant ( AllBits , dl , MaskVT ) , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ;

if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) {


<s> MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpc ) , ResultReg ) ; if ( Subtarget -> hasAVX ( ) ) MIB . addReg ( OpReg ) ; MIB . addReg ( OpReg ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) && <STR_LIT> ) ; MachineOperand & Imm = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; int64_t ImmVal = Imm . getImm ( ) ; Imm . setImm ( <NUM_LIT> | ( ( ImmVal & <NUM_LIT> ) << <NUM_LIT> ) | ( ImmVal & <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : const MachineOperand & Imm = MI . getOperand ( MI . getNumExplicitOperands ( ) - <NUM_LIT> ) ; int64_t ImmVal = Imm . getImm ( ) ; if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return false ; break ;


<s> vmovn_high_u32 ( uint16x4_t a , uint32x4_t b ) { uint16x8_t result = vcombine_u16 ( a , vcreate_u16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) : ) ;


<s> <ISA_LIT>Exception * getParentException ( ) const {


<s> if ( MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) ) Enc |= <NUM_LIT> ; return Enc ;


<s> checkUnsupportedInstruction ( Name , NameLoc ) ; if ( ! Parser . hasPendingError ( ) ) { StringRef Msg = ( Res == MatchOperand_ParseFail ) ? <STR_LIT> : <STR_LIT> ; Error ( getLoc ( ) , Msg ) ; } while ( ! trySkipToken ( AsmToken :: EndOfStatement ) ) {


<s> const auto PTruePattern = cast < ConstantInt > ( Pg -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( PTruePattern != <STR_LIT> ) return None ; auto * IdxTy = Type :: getInt64Ty ( II . getContext ( ) ) ; auto * Insert = InsertElementInst :: Create ( II . getArgOperand ( <NUM_LIT> ) , II . getArgOperand ( <NUM_LIT> ) , ConstantInt :: get ( IdxTy , <NUM_LIT> ) ) ; Insert -> insertBefore ( & II ) ; Insert -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , Insert ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> const OutputRelocSection & <ISA_LIT>LDBackend :: getRelaDyn ( ) const { assert ( m_pRelaDyn != NULL && <STR_LIT> ) ;


<s> return ( poly8x16_t ) __builtin_neon_vreinterpretv16qiti ( ( __builtin_neon_ti ) __a ) ;


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * <NUM_LIT> ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ;


<s> break ; case <STR_LIT> : case <STR_LIT> : <STR_LIT> ( TmpInst ) ; } uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ;

const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ;


<s> Op -> VType . Encoding = ( SewLog2 << <NUM_LIT> ) | Flmul ; } else { Op -> VType . Lmul = static_cast < VLMUL > ( LmulLog2 ) ; Op -> VType . Encoding = ( SewLog2 << <NUM_LIT> ) | LmulLog2 ; } if ( TailAgnostic ) { Op -> VType . Encoding |= <NUM_LIT> ; } if ( MaskedoffAgnostic ) {


<s> static DecodeStatus DecodeQQQRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) {


<s> bool <ISA_LIT>ExpandPseudo :: expandVSetVL ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { assert ( MBBI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ;

const MCInstrDesc & Desc = TII -> get ( <STR_LIT> ) ;


<s> EVT VT = Op -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue X = Op . getOperand ( <NUM_LIT> ) ; SDValue Y = Op . getOperand ( <NUM_LIT> ) ; unsigned Type ; if ( VT == <STR_LIT> ) Type = <ISA_LIT>II :: OpType :: FP32 ; else if ( VT == <STR_LIT> ) Type = <ISA_LIT>II :: OpType :: FP16 ; else Type = <ISA_LIT>II :: OpType :: BF16 ;

MachineSDNode * RecipNode = DAG . getMachineNode ( <STR_LIT> , DL , VT , { Y , DAG . getUNDEF ( VT ) , DAG . getTargetConstant ( Type , DL , <STR_LIT> ) , DAG . getTargetConstant ( <ISA_LIT>II :: SW_RECIP , DL , <STR_LIT> ) , DAG . getUNDEF ( VT ) , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ) ;


<s> void <ISA_LIT>InstPrinter :: printAbsAddrOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {


<s> e2 = gen_reg_rtx ( mode ) ; e3 = gen_reg_rtx ( mode ) ; real_from_integer ( & r , VOIDmode , - <NUM_LIT> , SIGNED ) ; mthree = CONST_DOUBLE_FROM_REAL_VALUE ( r , SFmode ) ; real_arithmetic ( & r , NEGATE_EXPR , & dconsthalf , NULL ) ; mhalf = CONST_DOUBLE_FROM_REAL_VALUE ( r , SFmode ) ; unspec = UNSPEC_RSQRT ; if ( VECTOR_MODE_P ( mode ) ) { mthree = ix86_build_const_vector ( mode , true , mthree ) ; mhalf = ix86_build_const_vector ( mode , true , mhalf ) ; if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) unspec = UNSPEC_RSQRT14 ; } a = force_reg ( mode , a ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , a ) , unspec ) ) ) ; if ( ! recip ) { rtx zero , mask ; zero = gen_reg_rtx ( mode ) ; mask = gen_reg_rtx ( mode ) ; zero = force_reg ( mode , CONST0_RTX ( mode ) ) ; if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) { mask = gen_reg_rtx ( HImode ) ; emit_insn ( gen_avx512f_cmpv16sf3 ( mask , zero , a , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_avx512f_blendmv16sf ( x0 , zero , x0 , mask ) ) ;


<s> const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; fputs ( GLOBAL_ASM_OP , stream ) ; RS6000_OUTPUT_BASENAME ( stream , name ) ;

fputs ( rs6000_xcoff_visibility ( decl ) , stream ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerELEMENT_COUNT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT VecVT = cast < VTSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; assert ( VecVT . isScalableVector ( ) && <STR_LIT> ) ; unsigned NumByteElts = <STR_LIT> / <NUM_LIT> ; EVT ElCntVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , { NumByteElts , true } ) ; SDValue EC = Op ; if ( ( VecVT != ElCntVT ) || ( VT != <STR_LIT> ) ) { SDValue Undef = DAG . getValueType ( ElCntVT ) ; EC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Undef ) ; unsigned NumElts = VecVT . getVectorNumElements ( ) ;


<s> else O << <STR_LIT> ; printReturnValStr ( F , O ) ; O << getSymbolName ( F ) << <STR_LIT> ; emitFunctionParamList ( F , O ) ; O << <STR_LIT> ;


<s> TII -> insertNoop ( MBB , llvm :: next ( I ) ) ; ++ InsertedLoadNOPs ; DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * J ) ; return true ; } else if ( J != MBB . end ( ) ) { ++ SkippedLoadNOPs ; return false ; } if ( J == MBB . end ( ) ) { if ( MBB . succ_empty ( ) ) return false ; bool inserted = false ; for ( MachineBasicBlock :: succ_iterator SMBB = MBB . succ_begin ( ) ; SMBB != MBB . succ_end ( ) ; ++ SMBB ) { MachineInstr * FirstMI = ( * SMBB ) -> begin ( ) ; if ( ( * SMBB ) -> empty ( ) || hasDefUseDep ( I , FirstMI ) ) { TII -> insertNoop ( * * SMBB , ( * SMBB ) -> begin ( ) ) ; ++ InsertedLoadNOPs ; if ( ! inserted ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; inserted = true ; } DEBUG ( dbgs ( ) << <STR_LIT> << * FirstMI ) ; } else { ++ SkippedLoadNOPs ; } } return inserted ; } return false ;


<s> const MachineInstr * FirstI = & Load , * SecondI = & Store ; if ( Load . isBundle ( ) && Store . isBundle ( ) ) { FirstI = nullptr ; SecondI = nullptr ; const MachineBasicBlock * MBB = Load . getParent ( ) ; auto MII = Load . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr * MI = & * MII ; if ( <ISA_LIT>II :: is_ld_l_v ( MI -> getDesc ( ) ) ) { FirstI = MI ; break ; } } MII = Store . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr * MI = & * MII ; if ( <ISA_LIT>II :: is_st_l_v ( MI -> getDesc ( ) ) ) { SecondI = MI ; break ; } } }

for ( auto & MO : FirstI -> operands ( ) ) {


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ;


<s> bool llvm :: useImmSlotForImm ( const MachineInstr & I , int64_t Val ) { const MCInstrDesc & IDesc = I . getDesc ( ) ; const MCOperandInfo & IInfo = IDesc . OpInfo [ <ISA_LIT>II :: getImmFieldOpNum ( IDesc ) ] ; bool isSigned = <ISA_LIT>MCInstrInfo :: isInstTypeSigned ( IDesc , I ) ;

return <ISA_LIT>MCInstrInfo :: useImmSlotForImm ( IInfo , Val , isSigned ) ;


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Offset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; default : Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; break ; } if ( DecodeRegListOperand16 ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ;

Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> else SpillOpc = IsPIC ? <STR_LIT> : <STR_LIT> ; } MachineInstr * SaveRegsCall = BuildMI ( MBB , MI , DL , HII . get ( SpillOpc ) ) . addExternalSymbol ( SpillFun ) ; addCalleeSaveRegistersAsImpOperand ( SaveRegsCall , CSI , false , true ) ; for ( unsigned I = <NUM_LIT> ; I < CSI . size ( ) ; ++ I ) MBB . addLiveIn ( CSI [ I ] . getReg ( ) ) ; return true ; } for ( unsigned i = <NUM_LIT> , n = CSI . size ( ) ; i < n ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsKill = ! HRI . isEHReturnCalleeSaveReg ( Reg ) ;


<s> if ( isOneConstant ( Op . getOperand ( <NUM_LIT> ) ) ) return Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ; return false ;


<s> if ( MBBI == MBB . end ( ) ) return false ; } unsigned PredReg = <NUM_LIT> ; return llvm :: getITInstrPredicate ( MBBI , PredReg ) == <STR_LIT> ;


<s> SDLoc DL ( & St ) ; SDValue BasePtr = St . getBasePtr ( ) ; uint64_t BaseOffset = <NUM_LIT> ; const MachinePointerInfo & PtrInfo = St . getPointerInfo ( ) ; SDValue NewST1 = DAG . getStore ( St . getChain ( ) , DL , SplatVal , BasePtr , PtrInfo , OrigAlignment , St . getMemOperand ( ) -> getFlags ( ) ) ; if ( BasePtr -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) ) { BaseOffset = cast < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; BasePtr = BasePtr -> getOperand ( <NUM_LIT> ) ; } unsigned Offset = EltOffset ; while ( -- NumVecElts ) { unsigned Alignment = MinAlign ( OrigAlignment , Offset ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( BaseOffset + Offset , DL , <STR_LIT> ) ) ;

NewST1 = DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SplatVal , OffsetPtr , PtrInfo . getWithOffset ( Offset ) , Alignment , St . getMemOperand ( ) -> getFlags ( ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressRecursively ( SDValue N , <ISA_LIT>ISelAddressMode & AM , <ISA_LIT>ISelListener & DeadNodes , unsigned Depth ) { bool is64Bit = Subtarget -> is64Bit ( ) ; DebugLoc dl = N . getDebugLoc ( ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; AM . dump ( ) ;


<s> Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: createLower16 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: createUpper16 ( Expr , OutContext ) ; break ; } break ; }


<s> InstrConverterBase ( unsigned SrcOpcode ) : SrcOpcode ( SrcOpcode ) {


<s> for ( int i = <NUM_LIT> ; i != ( int ) Index ; ++ i ) ShuffleMask . push_back ( i ) ; for ( int i = <NUM_LIT> ; i != ( int ) Length ; ++ i ) ShuffleMask . push_back ( i + <NUM_LIT> ) ; for ( int i = Index + Length ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( i ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( - <NUM_LIT> ) ; Value * SV = Builder . CreateShuffleVector ( Builder . CreateBitCast ( Op0 , ShufTy ) , Builder . CreateBitCast ( Op1 , ShufTy ) , ShuffleMask ) ; return Builder . CreateBitCast ( SV , II . getType ( ) ) ; } Constant * C0 = dyn_cast < Constant > ( Op0 ) ; Constant * C1 = dyn_cast < Constant > ( Op1 ) ; ConstantInt * CI00 = C0 ? dyn_cast_or_null < ConstantInt > ( C0 -> getAggregateElement ( ( unsigned ) <NUM_LIT> ) ) : nullptr ; ConstantInt * CI10 = C1 ? dyn_cast_or_null < ConstantInt > ( C1 -> getAggregateElement ( ( unsigned ) <NUM_LIT> ) ) : nullptr ; if ( CI00 && CI10 ) { APInt V00 = CI00 -> getValue ( ) ; APInt V10 = CI10 -> getValue ( ) ; APInt Mask = APInt :: getLowBitsSet ( <NUM_LIT> , Length ) . shl ( Index ) ; V00 = V00 & ~ Mask ; V10 = V10 . zextOrTrunc ( Length ) . zextOrTrunc ( <NUM_LIT> ) . shl ( Index ) ; APInt Val = V00 | V10 ; Type * IntTy64 = Type :: getInt64Ty ( II . getContext ( ) ) ; Constant * Args [ ] = { ConstantInt :: get ( IntTy64 , Val . getZExtValue ( ) ) , UndefValue :: get ( IntTy64 ) } ; return ConstantVector :: get ( Args ) ; } if ( II . getIntrinsicID ( ) == <STR_LIT> ) { Type * IntTy8 = Type :: getInt8Ty ( II . getContext ( ) ) ; Constant * CILength = ConstantInt :: get ( IntTy8 , Length , false ) ; Constant * CIIndex = ConstantInt :: get ( IntTy8 , Index , false ) ; Value * Args [ ] = { Op0 , Op1 , CILength , CIIndex } ;


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> <ISA_LIT>FixupHwLoops ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>FixupHwLoopsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Subtarget -> isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> , VT ) ;


if ( EnableFalkorHWPFFix ) addPass ( createFalkorHWPFFixPass ( ) ) ;


<s> for ( unsigned Reg : Edges ) { MRI -> setRegClass ( Reg , getDstRC ( MRI -> getRegClass ( Reg ) , Domain ) ) ; for ( auto & MO : MRI -> use_operands ( Reg ) ) { if ( MO . isReg ( ) ) MO . setSubReg ( <NUM_LIT> ) ;


<s> case MEK_CAPTABLE20 : case MEK_CAPTABLE_HI16 : case MEK_CAPTABLE_LO16 : if ( const <ISA_LIT>MCExpr * E = dyn_cast < const <ISA_LIT>MCExpr > ( getSubExpr ( ) ) ) E -> fixELFSymbolsInTLSFixups ( Asm ) ; break ; case MEK_DTPREL : case MEK_DTPREL_HI : case MEK_DTPREL_LO : case MEK_TLSLDM : case MEK_TLSGD : case MEK_GOTTPREL : case MEK_TPREL_HI : case MEK_TPREL_LO : case MEK_CAPTAB_TLSGD_HI16 :


<s> fputc ( '\t' , stream ) ; asm_fprintf ( stream , instr , reg ) ; fputs ( <STR_LIT> , stream ) ; for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( mask & ( <NUM_LIT> << i ) ) { if ( not_first ) fprintf ( stream , <STR_LIT> ) ; asm_fprintf ( stream , <STR_LIT> , i ) ; not_first = TRUE ;


<s> if ( isMemBound ( * Info ) ) { LLVM_DEBUG ( dbgs ( ) << F . getName ( ) << <STR_LIT> ) ; NumMemBound ++ ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; } if ( <STR_LIT> ( F . getCallingConv ( ) ) && needLimitWave ( * Info ) ) { LLVM_DEBUG ( dbgs ( ) << F . getName ( ) << <STR_LIT> ) ; NumLimitWave ++ ; F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ;


<s> bool sh_movsf_ie_ra_split_p ( rtx op0 , rtx op1 , rtx op2 ) { if ( rtx_equal_p ( op0 , op1 ) ) return true ; if ( GET_CODE ( op1 ) == CONST_DOUBLE && ! satisfies_constraint_G ( op1 ) && ! satisfies_constraint_H ( op1 ) && REG_P ( op0 ) && REG_P ( op2 ) ) return true ; if ( REG_P ( op0 ) && FP_REGISTER_P ( REGNO ( op0 ) ) && REG_P ( op1 ) && GENERAL_REGISTER_P ( REGNO ( op1 ) ) && REG_P ( op2 ) && ( REGNO ( op2 ) == FPUL_REG ) ) return true ;

if ( REG_P ( op1 ) && FP_REGISTER_P ( REGNO ( op1 ) ) && REG_P ( op0 ) && GENERAL_REGISTER_P ( REGNO ( op0 ) ) && REG_P ( op2 ) && ( REGNO ( op2 ) == FPUL_REG ) ) return true ;


<s> if ( TARGET_A16 ) emit_insn ( gen_movmemhi_whi_op ( desto , srco , counto , desta , srca , count ) ) ; else emit_insn ( gen_movmemhi_wpsi_op ( desto , srco , counto , desta , srca , count ) ) ; return <NUM_LIT> ; } if ( GET_CODE ( count ) != REG || REGNO ( count ) < FIRST_PSEUDO_REGISTER ) count = copy_to_mode_reg ( HImode , count ) ; if ( TARGET_A16 ) emit_insn ( gen_movmemhi_bhi_op ( desto , srco , counto , desta , srca , count ) ) ; else emit_insn ( gen_movmemhi_bpsi_op ( desto , srco , counto , desta , srca , count ) ) ; return <NUM_LIT> ;


<s> static inline uint8_t encodeAdvSIMDModImmType3 ( uint64_t Imm ) { return ( Imm & <NUM_LIT> ) >> <NUM_LIT> ;


<s> MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg ) , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned Align = DL . getABITypeAlignment ( Ty ) ; if ( VT != MemVT && VT . isFloatingPoint ( ) ) { assert ( VT . getScalarType ( ) == <STR_LIT> && MemVT . getScalarType ( ) == <STR_LIT> ) ; EVT IVT = toIntegerVT ( VT ) ; EVT MemIVT = toIntegerVT ( MemVT ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , <STR_LIT> , IVT , SL , Chain , Ptr , PtrOffset , PtrInfo , MemIVT , false , true , true , Align ) ;


<s> Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> return __builtin_neon_vcadd90v8hf ( __a , __b ) ;


<s> MachineInstr * instr = & * iter ; if ( instr && ( isCondBranch ( instr ) || isUncondBranch ( instr ) ) ) {


<s> RegisterTargetMachine < <ISA_LIT>ebTargetMachine > X ( The<ISA_LIT>Target ) ;


<s> bool writeback = ( W == <NUM_LIT> ) | ( P == <NUM_LIT> ) ; addr |= ( U << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> unsigned <ISA_LIT>InstrInfo :: getPartialRegUpdateClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { if ( OpNum != <NUM_LIT> || ! hasPartialRegUpdate ( MI . getOpcode ( ) , Subtarget ) ) return <NUM_LIT> ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; Register Reg = MO . getReg ( ) ; if ( Register :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI . readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else { if ( MI . readsRegister ( Reg , TRI ) ) return <NUM_LIT> ;


<s> return DisassembleNVdVnVmOptImm ( MI , Opcode , insn , NumOps , NumOpsAdded , N3V_VectorShift , B ) ;


<s> EVT MaskVT = Mask . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( Mask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ; SDValue Ops [ ] = { Chain , Src , Mask , Base , Index , Scale } ; SDValue Res = DAG . getTargetMemSDNode < <ISA_LIT>MaskedGatherSDNode > ( VTs , Ops , dl , MemIntr -> getMemoryVT ( ) , MemIntr -> getMemOperand ( ) ) ; return DAG . getMergeValues ( { Res , Res . getValue ( <NUM_LIT> ) } , dl ) ;


<s> VOffsetReg = B . buildConstant ( S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; B . getMRI ( ) -> setRegBank ( VOffsetReg , <STR_LIT> ) ; SOffsetReg = Base ; InstOffsetVal = ImmOffset ; return <NUM_LIT> ; } } if ( MachineInstr * Add = getOpcodeDef ( <STR_LIT> , CombinedOffset , * MRI ) ) { Register Src0 = getSrcRegIgnoringCopies ( * MRI , Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register Src1 = getSrcRegIgnoringCopies ( * MRI , Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const RegisterBank * Src0Bank = RBI . getRegBank ( Src0 , * MRI , * RBI . TRI ) ; const RegisterBank * Src1Bank = RBI . getRegBank ( Src1 , * MRI , * RBI . TRI ) ; if ( Src0Bank == & <STR_LIT> && Src1Bank == & <STR_LIT> ) { VOffsetReg = Src0 ; SOffsetReg = Src1 ; return <NUM_LIT> ; } if ( Src0Bank == & <STR_LIT> && Src1Bank == & <STR_LIT> ) { VOffsetReg = Src1 ; SOffsetReg = Src0 ; return <NUM_LIT> ; } } if ( RBI . getRegBank ( CombinedOffset , * MRI , * RBI . TRI ) == & <STR_LIT> ) { VOffsetReg = CombinedOffset ; } else { VOffsetReg = B . buildCopy ( S32 , CombinedOffset ) . getReg ( <NUM_LIT> ) ; B . getMRI ( ) -> setRegBank ( VOffsetReg , <STR_LIT> ) ; }

SOffsetReg = B . buildConstant ( S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ;


<s> } } if ( ! StopHere ) BI -> second . push_back ( MI ) ; } else { Base2StsMap [ Base ] . push_back ( MI ) ; StBases . push_back ( Base ) ; } } if ( StopHere ) { -- Loc ; break ; } } for ( unsigned i = <NUM_LIT> , e = LdBases . size ( ) ; i != e ; ++ i ) { unsigned Base = LdBases [ i ] ; SmallVectorImpl < MachineInstr * > & Lds = Base2LdsMap [ Base ] ; if ( Lds . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Lds , Base , true , MI2LocMap ) ; } for ( unsigned i = <NUM_LIT> , e = StBases . size ( ) ; i != e ; ++ i ) { unsigned Base = StBases [ i ] ; SmallVectorImpl < MachineInstr * > & Sts = Base2StsMap [ Base ] ; if ( Sts . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Sts , Base , false , MI2LocMap ) ; } if ( MBBI != E ) { Base2LdsMap . clear ( ) ; Base2StsMap . clear ( ) ; LdBases . clear ( ) ; StBases . clear ( ) ; } } return RetVal ;


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> void <ISA_LIT>InstPrinter :: printCCOperand ( const MCInst * MI , int opNum , const MCSubtargetInfo & STI , raw_ostream & O ) {

int CC = ( int ) MI -> getOperand ( opNum ) . getImm ( ) ;


<s> return <STR_LIT> . contains ( reg ) || <STR_LIT> . contains ( reg ) || <STR_LIT> . contains ( reg ) ;


<s> return const0_rtx ; } else internal_error ( <STR_LIT> ) ; if ( icode == <NUM_LIT> ) internal_error ( <STR_LIT> ) ; nonvoid = TREE_TYPE ( TREE_TYPE ( fndecl ) ) != void_type_node ; if ( nonvoid ) { machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( VECTOR_MODE_P ( insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ) ) last_vec_mode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; } arity = <NUM_LIT> ; FOR_EACH_CALL_EXPR_ARG ( arg , iter , exp ) { const struct insn_operand_data * insn_op ; unsigned int op_flags = all_op_flags & ( ( <NUM_LIT> << O_SHIFT ) - <NUM_LIT> ) ; all_op_flags = all_op_flags >> O_SHIFT ; if ( arg == error_mark_node ) return NULL_RTX ; if ( arity >= MAX_ARGS ) return NULL_RTX ; if ( O_IMM_P ( op_flags ) && TREE_CODE ( arg ) != INTEGER_CST ) { error ( <STR_LIT> , fndecl , arity + <NUM_LIT> ) ; return const0_rtx ; } if ( ! s390_const_operand_ok ( arg , arity + <NUM_LIT> , op_flags , fndecl ) ) return const0_rtx ; insn_op = & insn_data [ icode ] . operand [ arity + nonvoid ] ; op [ arity ] = expand_expr ( arg , NULL_RTX , insn_op -> mode , EXPAND_NORMAL ) ; if ( CONST_INT_P ( op [ arity ] ) && SCALAR_INT_MODE_P ( insn_op -> mode ) && GET_MODE ( op [ arity ] ) != insn_op -> mode ) op [ arity ] = GEN_INT ( trunc_int_for_mode ( INTVAL ( op [ arity ] ) , insn_op -> mode ) ) ; if ( POINTER_TYPE_P ( TREE_TYPE ( arg ) ) && insn_op -> predicate != address_operand ) op [ arity ] = gen_rtx_MEM ( insn_op -> mode , op [ arity ] ) ; if ( op_flags == O_ELEM ) { gcc_assert ( last_vec_mode != VOIDmode ) ; op [ arity ] = simplify_expand_binop ( SImode , code_to_optab ( AND ) , op [ arity ] , GEN_INT ( GET_MODE_NUNITS ( last_vec_mode ) - <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; } if ( VECTOR_MODE_P ( insn_op -> mode ) ) last_vec_mode = insn_op -> mode ; if ( insn_op -> predicate ( op [ arity ] , insn_op -> mode ) ) {


<s> if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & RegOpnd = static_cast < <ISA_LIT>Operand & > ( * Reg [ <NUM_LIT> ] ) ; if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ;


<s> unsigned s1_d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;

if ( is32Bit ) return MCDisassembler :: Fail ;


<s> if ( ! reload_completed ) return false ; if ( TARGET_WINDOWED_ABI ) return true ; if ( compute_frame_size ( get_frame_size ( ) ) == <NUM_LIT> ) return true ; return cfun -> machine -> epilogue_done ;


<s> case <STR_LIT> : if ( IsExtended ) return <STR_LIT> ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: isIntRegForSubInst ( DstReg ) && <ISA_LIT>MCInstrInfo :: isIntRegForSubInst ( SrcReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : if ( IsExtended ) return <STR_LIT> ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: minConstant ( MI , <NUM_LIT> ) <= <NUM_LIT> && <ISA_LIT>MCInstrInfo :: minConstant ( MI , <NUM_LIT> ) >= <NUM_LIT> && <ISA_LIT>MCInstrInfo :: isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : if ( IsExtended ) return <STR_LIT> ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && <ISA_LIT>MCInstrInfo :: isIntRegForSubInst ( Src1Reg ) && <ISA_LIT>MCInstrInfo :: minConstant ( MI , <NUM_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> == Src1Reg || <STR_LIT> == Src1Reg ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; break ; } return <STR_LIT> ;


<s> if ( ( Count & <NUM_LIT> ) != <NUM_LIT> ) { for ( uint64_t i = <NUM_LIT> , e = ( Count & <NUM_LIT> ) ; i != e ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_JT ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PTy = getPointerTy ( DAG . getDataLayout ( ) ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ; Table = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; Index = DAG . getNode ( <STR_LIT> , dl , PTy , Index , DAG . getConstant ( <NUM_LIT> , dl , PTy ) ) ;

SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Index , Table ) ;


<s> for ( unsigned i = NElts / <NUM_LIT> ; i != NElts ; ++ i ) ShuffleMask . push_back ( NElts + i ) ;

for ( unsigned i = NElts / <NUM_LIT> ; i != NElts ; ++ i ) ShuffleMask . push_back ( i ) ;


<s> const MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * F = MF . getFunction ( ) ; StringRef IntKind = F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; int64_t LROffset ; if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else if ( IntKind == <STR_LIT> || IntKind == <STR_LIT> ) LROffset = <NUM_LIT> ; else report_fatal_error ( <STR_LIT> <STR_LIT> ) ; RetOps . insert ( RetOps . begin ( ) + <NUM_LIT> , DAG . getConstant ( LROffset , DL , <STR_LIT> , false ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps ) ;


<s> assert ( isPowerOf2_32 ( ElemWidth ) && ElemWidth <= <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> / ElemWidth ; ++ i ) { Splat1 = ( Splat1 << ElemWidth ) | <NUM_LIT> ; SplatW = ( SplatW << ElemWidth ) | ElemWidth ; } SDValue Vec1 = DAG . getNode ( <STR_LIT> , dl , ResTy , DAG . getConstant ( uint32_t ( Splat1 ) , dl , <STR_LIT> ) ) ; SDValue VecW = DAG . getNode ( <STR_LIT> , dl , ResTy , DAG . getConstant ( uint32_t ( SplatW ) , dl , <STR_LIT> ) ) ; SDValue VecN1 = DAG . getNode ( <STR_LIT> , dl , ResTy , DAG . getConstant ( - <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue A = DAG . getNode ( <STR_LIT> , dl , ResTy , { DAG . getNode ( <STR_LIT> , dl , ResTy , { InpV , VecN1 } ) , DAG . getNode ( <STR_LIT> , dl , ResTy , { InpV , Vec1 } ) } ) ;

return DAG . getNode ( <STR_LIT> , dl , ResTy , { VecW , DAG . getNode ( <STR_LIT> , dl , ResTy , A ) } ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_RegList , Parser ) ;

Op -> RegList . List = new SmallVector < unsigned , <NUM_LIT> > ( Regs . begin ( ) , Regs . end ( ) ) ;


<s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return combineTRUNCATE ( N , DCI ) ;


<s> IndexType ( unsigned Idx ) : Index ( Idx ) {


<s> Branch ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_INDIRECT_SRC : IndirectSrc ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V1 : case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V2 : case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V4 : case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V8 : case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V16 : IndirectDst ( MI ) ; break ; case AMDGPU :: V_INTERP_P1_F32 : case AMDGPU :: V_INTERP_P2_F32 : case AMDGPU :: V_INTERP_MOV_F32 : NeedWQM = true ; break ; } } } if ( NeedWQM && MFI -> getShaderType ( ) == ShaderType :: PIXEL ) { MachineBasicBlock & MBB = MF . front ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; } if ( NeedFlat && MFI -> IsKernel ) { const MachineFrameInfo * FrameInfo = MF . getFrameInfo ( ) ; uint64_t StackSizeBytes = FrameInfo -> getStackSize ( ) ; int IndirectBegin = static_cast < const AMDGPUInstrInfo * > ( TII ) -> getIndirectIndexBegin ( MF ) ; uint64_t StackOffset = IndirectBegin < <NUM_LIT> ? <NUM_LIT> : ( <NUM_LIT> * IndirectBegin / <NUM_LIT> ) ; assert ( ( StackSizeBytes < <NUM_LIT> ) && StackOffset < <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock & MBB = MF . front ( ) ; DebugLoc NoDL ; MachineBasicBlock :: iterator Start = MBB . getFirstNonPHI ( ) ; const MCInstrDesc & SMovK = TII -> get ( AMDGPU :: S_MOVK_I32 ) ; assert ( isInt < <NUM_LIT> > ( StackOffset ) && isInt < <NUM_LIT> > ( StackSizeBytes ) ) ; BuildMI ( MBB , Start , NoDL , SMovK , AMDGPU :: FLAT_SCR_LO ) . addImm ( StackOffset ) ; BuildMI ( MBB , Start , NoDL , SMovK , AMDGPU :: FLAT_SCR_HI ) . addImm ( StackSizeBytes ) ; }


<s> AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ;


<s> struct __htm_tdb * tdb = ( struct __htm_tdb * ) tdb_ptr ; return ( tdb -> format == <NUM_LIT> && ( tdb -> abort_code == <NUM_LIT> || tdb -> abort_code == <NUM_LIT> ) ) ;


<s> SDValue V2Mask [ <NUM_LIT> ] ; V1InUse = false ; V2InUse = false ; int Size = Mask . size ( ) ; int Scale = <NUM_LIT> / Size ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Mask [ i / Scale ] == - <NUM_LIT> ) { V1Mask [ i ] = V2Mask [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else { const int ZeroMask = <NUM_LIT> ; int V1Idx = Mask [ i / Scale ] < Size ? Mask [ i / Scale ] * Scale + i % Scale : ZeroMask ; int V2Idx = Mask [ i / Scale ] < Size ? ZeroMask : ( Mask [ i / Scale ] - Size ) * Scale + i % Scale ; if ( Zeroable [ i / Scale ] ) V1Idx = V2Idx = ZeroMask ; V1Mask [ i ] = DAG . getConstant ( V1Idx , DL , <STR_LIT> ) ; V2Mask [ i ] = DAG . getConstant ( V2Idx , DL , <STR_LIT> ) ; V1InUse |= ( ZeroMask != V1Idx ) ; V2InUse |= ( ZeroMask != V2Idx ) ; } } if ( V1InUse ) V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1Mask ) ) ; if ( V2InUse ) V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V2 ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2Mask ) ) ; SDValue V ; if ( V1InUse && V2InUse ) V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; else V = V1InUse ? V1 : V2 ; return DAG . getBitcast ( VT , V ) ;


<s> static bool aarch64_evpc_sve_tbl ( struct expand_vec_perm_d * d ) { unsigned HOST_WIDE_INT nelt ;

if ( ! d -> one_vector_p && ! d -> perm . length ( ) . is_constant ( & nelt ) ) return false ;


<s> static SDValue splitIntVSETCC ( EVT VT , SDValue LHS , SDValue RHS , <STR_LIT> Cond , SelectionDAG & DAG , const SDLoc & dl ) { assert ( VT . isInteger ( ) && VT == LHS . getValueType ( ) && VT == RHS . getValueType ( ) && <STR_LIT> ) ; SDValue CC = DAG . getCondCode ( Cond ) ; SDValue LHS1 , LHS2 ; std :: tie ( LHS1 , LHS2 ) = splitVector ( LHS , DAG , dl ) ; SDValue RHS1 , RHS2 ; std :: tie ( RHS1 , RHS2 ) = splitVector ( RHS , DAG , dl ) ; EVT LoVT , HiVT ;

std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ;


<s> unsigned Opcode = MI . getOpcode ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool isCC = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( isCC ? <NUM_LIT> : <NUM_LIT> ) ; bool RequiresBundling = STI -> isTargetWindows ( ) && IsAnAddressOperand ( MO ) ; MachineInstrBuilder LO16 , HI16 ; if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ;

LO16 . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) , TM ( tm ) , Subtarget ( nullptr ) , ForCodeSize ( false ) {


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Vd = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; regs = regs >> <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs - <NUM_LIT> ) ; ++ i ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ++ Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> int tr0_used ; if ( ! current_function_is_leaf ) return - <NUM_LIT> ; tr0_used = flag_pic && regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] ;

for ( regno = FIRST_TARGET_REG + tr0_used ; regno <= LAST_TARGET_REG ; regno ++ ) if ( call_used_regs [ regno ] && ! regs_ever_live [ regno ] ) return regno ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> rtx hppa_pic_save_rtx ( void ) { return get_hard_reg_initial_val ( word_mode , PIC_OFFSET_TABLE_REGNUM ) ;


<s> lower_bound = <NUM_LIT> ; upper_bound = <NUM_LIT> ; if ( TREE_CODE ( id ) != INTEGER_CST || wi :: ltu_p ( wi :: to_wide ( id ) , lower_bound ) || wi :: gtu_p ( wi :: to_wide ( id ) , upper_bound ) ) error ( <STR_LIT> ) ; nmi = lookup_attribute ( <STR_LIT> , func_attrs ) ; warm = lookup_attribute ( <STR_LIT> , func_attrs ) ; if ( nmi != NULL_TREE ) { tree nmi_func_list ; tree nmi_func ; nmi_func_list = TREE_VALUE ( nmi ) ; nmi_func = TREE_VALUE ( nmi_func_list ) ; if ( TREE_CODE ( nmi_func ) != IDENTIFIER_NODE ) error ( <STR_LIT> ) ; } if ( warm != NULL_TREE ) { tree warm_func_list ; tree warm_func ; warm_func_list = TREE_VALUE ( warm ) ; warm_func = TREE_VALUE ( warm_func_list ) ; if ( TREE_CODE ( warm_func ) != IDENTIFIER_NODE ) error ( <STR_LIT> ) ; } } else { return ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ;


<s> rtl_opt_pass * make_pass_cc_fusion ( gcc :: context * ctxt ) { return new pass_cc_fusion ( ctxt ) ;


<s> Register HiLuiDestReg = HiLUI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LoADDI = MRI -> use_begin ( HiLuiDestReg ) -> getParent ( ) ; if ( LoADDI -> getOpcode ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> || LoADDI -> getOperand ( <NUM_LIT> ) . getType ( ) != MachineOperand :: MO_GlobalAddress || LoADDI -> getOperand ( <NUM_LIT> ) . getOffset ( ) != <NUM_LIT> || ! MRI -> hasOneUse ( LoADDI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ;


<s> static int mn10300_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t iclass , bool in ATTRIBUTE_UNUSED ) { enum reg_class rclass = ( enum reg_class ) iclass ; if ( rclass == FP_REGS ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> } std :: copy ( Ptr , Ptr + Size , Data . begin ( ) + Position ) ; Position += Size ; if ( Other ) {


<s> if ( mode != VOIDmode && mode != GET_MODE ( op ) ) return <NUM_LIT> ; if ( GET_CODE ( op ) == MEM ) { op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) == PLUS ) { rtx op0 = XEXP ( op , <NUM_LIT> ) ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT , const MCTargetOptions & Options ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ;


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const {


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo * TII = MF . getTarget ( ) . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } unsigned LowGPR = ZFI -> getLowSavedGPR ( ) ; unsigned HighGPR = ZFI -> getHighSavedGPR ( ) ; unsigned StartOffset = RegSpillOffsets [ LowGPR ] ; if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( LowGPR , RegState :: Define ) ; MIB . addReg ( HighGPR , RegState :: Define ) ; MIB . addReg ( HasFP ? <STR_LIT> : <STR_LIT> ) ; MIB . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) {


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> MachineInstr * IncomingDef = MRI -> getUniqueVRegDef ( IncomingReg ) ; if ( IncomingDef -> getOpcode ( ) == <STR_LIT> ) { IncomingReg = IncomingDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( isLaneMaskReg ( IncomingReg ) || isVreg1 ( IncomingReg ) ) ; assert ( ! IncomingDef -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; } else if ( IncomingDef -> getOpcode ( ) == <STR_LIT> ) { continue ; } else { assert ( IncomingDef -> isPHI ( ) || PhiRegisters . count ( IncomingReg ) ) ; } IncomingBlocks . push_back ( IncomingMBB ) ; IncomingRegs . push_back ( IncomingReg ) ; } PhiRegisters . insert ( DstReg ) ; std :: vector < MachineBasicBlock * > DomBlocks = { & MBB } ; for ( MachineInstr & Use : MRI -> use_instructions ( DstReg ) ) DomBlocks . push_back ( Use . getParent ( ) ) ; MachineBasicBlock * PostDomBound = PDT -> findNearestCommonDominator ( DomBlocks ) ; unsigned FoundLoopLevel = LF . findLoop ( PostDomBound ) ; SSAUpdater . Initialize ( DstReg ) ; if ( FoundLoopLevel ) { LF . addLoopEntries ( FoundLoopLevel , SSAUpdater , IncomingBlocks ) ; for ( unsigned i = <NUM_LIT> ; i < IncomingRegs . size ( ) ; ++ i ) { IncomingUpdated . push_back ( createLaneMaskReg ( * MF ) ) ; SSAUpdater . AddAvailableValue ( IncomingBlocks [ i ] , IncomingUpdated . back ( ) ) ; }


<s> assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; int Indexes [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { Constant * COp = V -> getAggregateElement ( I ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return nullptr ;


<s> if ( MD -> getNumOperands ( ) > NumOp ) { auto * CMeta = dyn_cast < ConstantAsMetadata > ( MD -> getOperand ( NumOp ) ) ; if ( CMeta ) return dyn_cast < ConstantInt > ( CMeta -> getValue ( ) ) ; } return nullptr ;


<s> assert ( Kind == k_Immediate && <STR_LIT> ) ;


<s> return true ; } if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { CInfo . Kind = <ISA_LIT>PreserveFieldInfoAI ; CInfo . Metadata = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; if ( ! CInfo . Metadata ) report_fatal_error ( <STR_LIT> ) ; uint64_t Flag = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ; if ( Flag >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Flag == <STR_LIT> ) CInfo . AccessIndex = <STR_LIT> ; else CInfo . AccessIndex = <STR_LIT> ; return true ; } if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { CInfo . Kind = <ISA_LIT>PreserveFieldInfoAI ; CInfo . Metadata = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; if ( ! CInfo . Metadata ) report_fatal_error ( <STR_LIT> ) ; uint64_t Flag = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ; if ( Flag >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Flag == <STR_LIT> ) CInfo . AccessIndex = <STR_LIT> ; else CInfo . AccessIndex = <STR_LIT> ; return true ; } return false ;


<s> bool LinearizedRegion :: contains ( MachineBasicBlock * MBB ) {


<s> emit_insn ( gen_atomic_compare_and_swapsi_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_DImode : emit_insn ( gen_atomic_compare_and_swapdi_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_TImode : emit_insn ( gen_atomic_compare_and_swapti_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_QImode : case E_HImode : default : gcc_unreachable ( ) ; } return s390_emit_compare ( code , cc , const0_rtx ) ;


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>GlobalRegistry * GR = ST . get<ISA_LIT>GlobalRegistry ( ) ; GR -> setCurrentFunc ( MF ) ; MachineIRBuilder MIB ( MF ) ; addConstantsToTrack ( MF , GR ) ; foldConstantsIntoIntrinsics ( MF ) ; insertBitcasts ( MF , GR , MIB ) ;

generateAssignInstrs ( MF , GR , MIB ) ;


<s> unsigned RetOpcode = MI -> getOpcode ( ) ; isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; isTrap = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; } SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { CalleeSavedInfo & Info = CSI [ i - <NUM_LIT> ] ; unsigned Reg = Info . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && ! isTrap && STI . hasV5TOps ( ) ) { if ( MBB . succ_empty ( ) ) { Reg = <STR_LIT> ; DeleteRet = true ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; Info . setRestored ( false ) ; } else LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( Reg ) ; } if ( Regs . empty ( ) ) continue ; std :: sort ( Regs . begin ( ) , Regs . end ( ) , [ & ] ( unsigned LHS , unsigned RHS ) { return TRI . getEncodingValue ( LHS ) < TRI . getEncodingValue ( RHS ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || LdrOpc == <NUM_LIT> ) {

MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> static SDValue getAllOnesMask ( MVT VecVT , SDValue VL , SDLoc DL , SelectionDAG & DAG ) {


<s> void <ISA_LIT>InstPrinter :: printRDOperand ( const MCInst * MI , int OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { int RD = ( int ) MI -> getOperand ( OpNum ) . getImm ( ) ; O << <ISA_LIT>RDToString ( ( <STR_LIT> ) RD ) ;


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , DebugLoc dl ) {

SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ;


<s> static DecodeStatus DecodeNamedImmOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { SomeNamedImmMapper Mapper ; bool ValidNamed ; Mapper . toString ( Val , ValidNamed ) ; if ( ValidNamed || Mapper . validImm ( Val ) ) { Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ; return MCDisassembler :: Success ; } return MCDisassembler :: Fail ;


<s> Result += ! isDuplexAGroup ( subInst1Opcode ) ;

} else Result += Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && ( Type != <STR_LIT> || <ISA_LIT>MCInstrInfo :: isFloat ( MCII , ID ) ) ;


<s> if ( b & <NUM_LIT> ) { vec_uint4 nan_mask = ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 a_inf = ( vec_uint4 ) vec_cmpeq ( aabs , nan_mask ) ; if ( b & <NUM_LIT> ) { vec_uint4 a_nan = ( vec_uint4 ) vec_cmpgt ( aabs , nan_mask ) ; a_nan = vec_or ( a_nan , vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_nan , x . v ) , a_inf ) ) ; a_nan = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) a_nan , ( vec_uchar16 ) a_nan , splat_hi ) ; result = vec_or ( result , a_nan ) ; } if ( b & <NUM_LIT> ) { a_inf = vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_inf , x . v ) , a_inf ) ; a_inf = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) a_inf , ( vec_uchar16 ) a_inf , splat_hi ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_andc ( a_inf , sign ) , result ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_and ( a_inf , sign ) , result ) ; } } if ( b & <NUM_LIT> ) { vec_uint4 iszero = ( vec_uint4 ) vec_cmpeq ( aabs , ( vec_uint4 ) vec_splat_u32 ( <NUM_LIT> ) ) ; iszero = vec_and ( iszero , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) iszero , x . v ) ) ; if ( b & <NUM_LIT> ) { vec_uint4 denorm_mask = ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 isdenorm = vec_nor ( ( vec_uint4 ) vec_cmpgt ( aabs , denorm_mask ) , iszero ) ; isdenorm = ( vec_uint4 ) vec_perm ( ( vec_uchar16 ) isdenorm , ( vec_uchar16 ) isdenorm , splat_hi ) ; if ( b & <NUM_LIT> ) result = vec_or ( vec_andc ( isdenorm , sign ) , result ) ;

if ( b & <NUM_LIT> ) result = vec_or ( vec_and ( isdenorm , sign ) , result ) ;


<s> if ( S == MCDisassembler :: Success ) { DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ;

DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder ) ;


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'c' : break ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ;


<s> const llvm :: <STR_LIT> * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ;

AsmPrinter :: runOnMachineFunction ( MF ) ;


<s> return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . enableSaveRestore ( ) && VarArgsSaveSize == <NUM_LIT> && ! MF . getFrameInfo ( ) . hasTailCall ( ) ;


<s> static void aarch64_def_or_undef ( bool def_p , const char * macro , cpp_reader * pfile ) { if ( def_p ) cpp_define ( pfile , macro ) ; else cpp_undef ( pfile , macro ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;

if ( get<ISA_LIT>Subtarget ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ;


<s> SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewReturnAddrFI , PtrVT ) ; Chain = DAG . getStore ( Chain , dl , RetAddrFrIdx , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , NewReturnAddrFI ) ) ;


<s> bool Changed = false ; std :: map < MachineBasicBlock * , unsigned > BB2OrderMap ; unsigned Order = <NUM_LIT> ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , MFE = MF . end ( ) ; MFI != MFE ; MFI ++ ) { MachineBasicBlock * BB = MFI ; BB2OrderMap [ BB ] = Order ; Order ++ ; } for ( MachineFunction :: iterator MBI = MF . begin ( ) ; MBI != MF . end ( ) ; MBI ++ ) { MachineBasicBlock * MBB = MBI ; MachineBasicBlock :: iterator I = MBI -> end ( ) ; if ( I == MBB -> begin ( ) ) continue ; I -- ; MachineInstr * LastInst = I ; if ( LastInst -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * Target = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB2OrderMap [ Target ] == BB2OrderMap [ MBB ] + <NUM_LIT> ) { LastInst -> eraseFromParent ( ) ; Changed = true ; }


<s> if ( DAG . getTarget ( ) . Options . UnsafeFPMath ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue V = Op -> getOperand ( <NUM_LIT> ) ; MVT VecIntVT = V . getSimpleValueType ( ) ; bool Is128 = VecIntVT == <STR_LIT> ; MVT VecFloatVT = Is128 ? <STR_LIT> : <STR_LIT> ; if ( VecFloatVT != Op -> getSimpleValueType ( <NUM_LIT> ) ) return SDValue ( ) ; assert ( ( VecIntVT == <STR_LIT> || VecIntVT == <STR_LIT> ) && <STR_LIT> ) ; SDValue VecCstLow = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstHigh = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstShift = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue HighShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstShift ) ; SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { MVT VecI16VT = Is128 ? <STR_LIT> : <STR_LIT> ; SDValue VecCstLowBitcast = DAG . getBitcast ( VecI16VT , VecCstLow ) ; SDValue VecBitcast = DAG . getBitcast ( VecI16VT , V ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecBitcast , VecCstLowBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue VecCstHighBitcast = DAG . getBitcast ( VecI16VT , VecCstHigh ) ; SDValue VecShiftBitcast = DAG . getBitcast ( VecI16VT , HighShift ) ; High = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecShiftBitcast , VecCstHighBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } else {

SDValue VecCstMask = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ;


for ( MachineLoop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) if ( L -> empty ( ) ) runOnLoop ( * * L , Fn ) ;


<s> unsigned <ISA_LIT>AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { return Match_Success ;


<s> if ( ! T . isOSBinFormatELF ( ) ) llvm_unreachable ( <STR_LIT> ) ;

return createELFStreamer ( Context , std :: move ( MAB ) , OS , std :: move ( Emitter ) , RelaxAll ) ;


<s> static DecodeStatus DecodeCacheOp ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Hint = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> const MachineOperand & AddrReg0 = I -> getOperand ( AddrIdx ) ; const MachineOperand & AddrReg1 = MBBI -> getOperand ( AddrIdx ) ; if ( AddrReg0 . getReg ( ) == AddrReg1 . getReg ( ) && AddrReg0 . getSubReg ( ) == AddrReg1 . getSubReg ( ) ) { int OffsetIdx = <STR_LIT> ( I -> getOpcode ( ) , <STR_LIT> :: offset ) ; unsigned Offset0 = I -> getOperand ( OffsetIdx ) . getImm ( ) & <NUM_LIT> ;

unsigned Offset1 = MBBI -> getOperand ( OffsetIdx ) . getImm ( ) & <NUM_LIT> ;


<s> if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> ) {

MI . setDesc ( TII -> get ( Opcode ) ) ;


<s> void <ISA_LIT>InstPrinter :: printRhaz ( const MCInst * , unsigned , raw_ostream & ) {


<s> int Offset = - LFS ; for ( int i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( ! MFI -> isSpillSlotObjectIndex ( i ) || MFI -> isDeadObjectIndex ( i ) ) continue ; int S = MFI -> getObjectSize ( i ) ; LFS += S ; Offset -= S ; MFI -> mapLocalFrameObject ( i , Offset ) ; } MFI -> setLocalFrameSize ( LFS ) ; unsigned A = MFI -> getLocalFrameMaxAlign ( ) ;

assert ( A <= <NUM_LIT> && <STR_LIT> ) ;


<s> Op -> VectorList . isDoubleSpaced = isDoubleSpaced ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else if ( ! ( SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) ) assert ( false && <STR_LIT> ) ; MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : OS << <STR_LIT> ; break ; }


<s> O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( MO . getImm ( ) ) << markup ( <STR_LIT> ) ;


<s> return decodeRegisterClass ( Inst , RegNo , VSSRegs ) ;


<s> while ( NumNOPBytes > <NUM_LIT> ) { if ( MII == MBB . end ( ) || MII -> isCall ( ) || MII -> getOpcode ( ) == <STR_LIT> || MII -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ; ++ MII ;


<s> } if ( ! ContainsWWM ) return false ; unsigned Reg = DefOpnd -> getReg ( ) ; for ( auto & Use : MRI -> use_operands ( Reg ) ) Use . setIsKill ( false ) ; SmallVector < MachineInstr * , <NUM_LIT> > Defs ; for ( auto & Def : MRI -> def_instructions ( Reg ) ) Defs . push_back ( & Def ) ; for ( auto Def : Defs ) { if ( DefOpnd -> getParent ( ) == Def ) continue ; Def -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true ) ) ; LLVM_DEBUG ( dbgs ( ) << * Def ) ; } return true ;


<s> return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr , Base , Disp , Index ) ;


<s> } else { ArgPtr = Builder . CreateConstInBoundsGEP1_64 ( Builder . getInt8Ty ( ) , KernArgSegment , EltOffset , Arg . getName ( ) + <STR_LIT> ) ; AdjustedArgTy = ArgTy ; } if ( IsV3 && Size >= <NUM_LIT> ) { V4Ty = VectorType :: get ( VT -> getVectorElementType ( ) , <NUM_LIT> ) ; AdjustedArgTy = V4Ty ; } ArgPtr = Builder . CreateBitCast ( ArgPtr , AdjustedArgTy -> getPointerTo ( AS ) , ArgPtr -> getName ( ) + <STR_LIT> ) ; LoadInst * Load = Builder . CreateAlignedLoad ( AdjustedArgTy , ArgPtr , AdjustedAlign ) ; Load -> setMetadata ( LLVMContext :: MD_invariant_load , MDNode :: get ( Ctx , { } ) ) ; MDBuilder MDB ( Ctx ) ; if ( isa < PointerType > ( ArgTy ) ) { if ( Arg . hasNonNullAttr ( ) ) Load -> setMetadata ( LLVMContext :: MD_nonnull , MDNode :: get ( Ctx , { } ) ) ; uint64_t DerefBytes = Arg . getDereferenceableBytes ( ) ; if ( DerefBytes != <NUM_LIT> ) { Load -> setMetadata ( LLVMContext :: MD_dereferenceable , MDNode :: get ( Ctx , MDB . createConstant ( ConstantInt :: get ( Builder . getInt64Ty ( ) , DerefBytes ) ) ) ) ; } uint64_t DerefOrNullBytes = Arg . getDereferenceableOrNullBytes ( ) ; if ( DerefOrNullBytes != <NUM_LIT> ) { Load -> setMetadata ( LLVMContext :: MD_dereferenceable_or_null , MDNode :: get ( Ctx , MDB . createConstant ( ConstantInt :: get ( Builder . getInt64Ty ( ) , DerefOrNullBytes ) ) ) ) ; } unsigned ParamAlign = Arg . getParamAlignment ( ) ; if ( ParamAlign != <NUM_LIT> ) { Load -> setMetadata ( LLVMContext :: MD_align , MDNode :: get ( Ctx , MDB . createConstant ( ConstantInt :: get ( Builder . getInt64Ty ( ) , ParamAlign ) ) ) ) ; } } if ( DoShiftOpt ) { Value * ExtractBits = OffsetDiff == <NUM_LIT> ? Load : Builder . CreateLShr ( Load , OffsetDiff * <NUM_LIT> ) ; IntegerType * ArgIntTy = Builder . getIntNTy ( Size ) ; Value * Trunc = Builder . CreateTrunc ( ExtractBits , ArgIntTy ) ; Value * NewVal = Builder . CreateBitCast ( Trunc , ArgTy , Arg . getName ( ) + <STR_LIT> ) ; Arg . replaceAllUsesWith ( NewVal ) ;


<s> void printARID8Mem ( const MCInst * MI , int opNum , raw_ostream & O ) {


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const {


<s> pass_cc_fusion ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_cc_fusion , ctxt ) {


<s> iterator_range < MCInst :: const_iterator > <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCInst const & MCI ) { assert ( isBundle ( MCI ) ) ; return drop_begin ( MCI , bundleInstructionsOffset ) ;


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const {


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; } } } <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <STR_LIT> CompareType ; switch ( CondCode ) { default : CompareType = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CompareType = <STR_LIT> ; break ; } <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; return DAG . getNode ( CompareType , dl , <STR_LIT> , LHS , RHS ) ;


<s> SDValue HiHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BCVec , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue LoVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoHalf ) ; SDValue HiVec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , HiHalf ) ; unsigned Idx = KIdx -> getZExtValue ( ) ; bool InsertLo = Idx < <NUM_LIT> ; SDValue InsHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , InsertLo ? LoVec : HiVec , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , InsVal ) , DAG . getConstant ( InsertLo ? Idx : ( Idx - <NUM_LIT> ) , SL , <STR_LIT> ) ) ; InsHalf = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , InsHalf ) ; SDValue Concat = InsertLo ? DAG . getBuildVector ( <STR_LIT> , SL , { InsHalf , HiHalf } ) : DAG . getBuildVector ( <STR_LIT> , SL , { LoHalf , InsHalf } ) ; return DAG . getNode ( <STR_LIT> , SL , VecVT , Concat ) ; } assert ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; EVT IntVT = NumElts == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;

SDValue Val = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , InsVal ) ;


<s> splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>ABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , <NUM_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ;

IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ;


<s> return __builtin_mve_vmulhq_uv16qi ( __a , __b ) ;


<s> unsigned getInlineAsmMemConstraint ( const std :: string & ConstraintCode ) const override { return InlineAsm :: Constraint_m ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine * TM , CodeGenOpt :: Level OptLevel ) : <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) {


<s> return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { return MatchOperand_ParseFail ; } Value = Parser . getTok ( ) . getString ( ) ;


<s> vld1q_dup_s32 ( const int32_t * __a ) { return ( int32x4_t ) __builtin_neon_vld1_dupv4si ( ( const __builtin_neon_si * ) __a ) ;