<s> <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { unsigned HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; if ( <ISA_LIT>SubTarget -> isGVIndirectSymbol ( GV ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( HighPartReg ) ; } else {

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( HighPartReg ) . addGlobalAddress ( GV ) ;


<s> bool runOnModule ( Module & M ) override { for ( auto & GV : M . globals ( ) ) GV . setThreadLocalMode ( GlobalValue :: ThreadLocalMode :: NotThreadLocal ) ;


<s> if ( ! isAddress || RegNo ) { RegNo = Regs [ RegNo ] ; if ( RegNo == <NUM_LIT> ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ;


<s> EVT VT = Value . getValueType ( ) ; EVT StVT = ( ! SN -> isTruncatingStore ( ) ? VT : SN -> getMemoryVT ( ) ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned alignment = SN -> getAlignment ( ) ; switch ( SN -> getAddressingMode ( ) ) { case <STR_LIT> : { EVT vecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT , ( <NUM_LIT> / VT . getSizeInBits ( ) ) ) ; SDValue alignLoadVec ; SDValue basePtr = SN -> getBasePtr ( ) ; SDValue the_chain = SN -> getChain ( ) ; SDValue insertEltOffs ; if ( alignment == <NUM_LIT> ) { ConstantSDNode * CN ; if ( basePtr . getOpcode ( ) == <STR_LIT> && ( CN = dyn_cast < ConstantSDNode > ( basePtr . getOperand ( <NUM_LIT> ) ) ) != <NUM_LIT> ) { int64_t offset = CN -> getSExtValue ( ) ; basePtr = basePtr . getOperand ( <NUM_LIT> ) ; insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & <NUM_LIT> ) , PtrVT ) ) ; if ( ( offset & ~ <NUM_LIT> ) > <NUM_LIT> ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & ~ <NUM_LIT> ) , PtrVT ) ) ; } } else { insertEltOffs = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ;


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;

else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i ) ) . second ) assert ( false && <STR_LIT> ) ;


<s> unsigned TwoXLenInBytes = ( <NUM_LIT> * XLen ) / <NUM_LIT> ; if ( ! IsFixed && ArgFlags . getOrigAlign ( ) == TwoXLenInBytes && DL . getTypeAllocSize ( OrigTy ) == TwoXLenInBytes ) { unsigned RegIdx = State . getFirstUnallocated ( ArgGPRs ) ; if ( RegIdx != array_lengthof ( ArgGPRs ) && RegIdx % <NUM_LIT> == <NUM_LIT> ) State . AllocateReg ( ArgGPRs ) ; } SmallVectorImpl < CCValAssign > & PendingLocs = State . getPendingLocs ( ) ; SmallVectorImpl < <STR_LIT> > & PendingArgFlags = State . getPendingArgFlags ( ) ; assert ( PendingLocs . size ( ) == PendingArgFlags . size ( ) && <STR_LIT> ) ; if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) { LocVT = XLenVT ; LocInfo = CCValAssign :: Indirect ; PendingLocs . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; PendingArgFlags . push_back ( ArgFlags ) ; if ( ! ArgFlags . isSplitEnd ( ) ) { return false ; } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; } PendingLocs . clear ( ) ;


<s> return ( ( ( TARGET_SHMEDIA ? <NUM_LIT> : TARGET_FMOVD ? <NUM_LIT> : <NUM_LIT> ) + addend ) * ( ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ) ) ; } if ( ( dstclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( srcclass ) ) || ( srcclass == FPUL_REGS && REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return <NUM_LIT> ; if ( ( dstclass == FPUL_REGS && ( srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS ) ) || ( srcclass == FPUL_REGS && ( dstclass == PR_REGS || dstclass == MAC_REGS ) ) ) return <NUM_LIT> ; if ( ( srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( ( dstclass ) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return <NUM_LIT> ; if ( TARGET_SHMEDIA && ( ( srcclass ) == TARGET_REGS || ( srcclass ) == SIBCALL_REGS ) ) { if ( sh_gettrcost >= <NUM_LIT> ) return sh_gettrcost ; else if ( ! TARGET_PT_FIXED ) return <NUM_LIT> ; } if ( ( srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) || ( dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) ) ) return <NUM_LIT> ;

if ( TARGET_SHMEDIA || ( TARGET_FMOVD && ! REGCLASS_HAS_GENERAL_REG ( srcclass ) && ! REGCLASS_HAS_GENERAL_REG ( dstclass ) ) ) return <NUM_LIT> * ( ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ) ;


<s> SDValue SysRegNo = DAG . getTargetConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; static const unsigned Table = ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToEven ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardZero ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardNegative ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: TowardPositive ) ) | ( <STR_LIT> << <NUM_LIT> * int ( RoundingMode :: NearestTiesToAway ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;

SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ;


<s> return ( uint8x8_t ) __builtin_neon_vrsubhnv8hi ( ( int16x8_t ) __a , ( int16x8_t ) __b ) ;


<s> mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - <NUM_LIT> * ptr_mode_size ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - ptr_mode_size ) ; emit_move_insn ( mem , chaddr ) ; begin_addr = force_reg ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ; end_addr = force_reg ( Pmode , plus_constant ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) , TRAMPOLINE_SIZE ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) , LCT_NORMAL , VOIDmode , <NUM_LIT> , begin_addr , Pmode , end_addr , Pmode ) ;


<s> if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad , useAM3 ) ; if ( needVMOV ) {

unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ;


<s> * __P = ( unsigned int ) ( __res >> <NUM_LIT> ) ; return ( unsigned int ) __res ;


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const {


<s> bitmap_clear ( to_clear_bitmap ) ; bitmap_set_range ( to_clear_bitmap , R0_REGNUM , NUM_ARG_REGS ) ; bitmap_set_bit ( to_clear_bitmap , IP_REGNUM ) ; if ( TARGET_HARD_FLOAT ) { int float_bits = D7_VFP_REGNUM - FIRST_VFP_REGNUM + <NUM_LIT> ; bitmap_set_range ( to_clear_bitmap , FIRST_VFP_REGNUM , float_bits ) ; emit_use ( gen_rtx_REG ( SImode , IP_REGNUM ) ) ; bitmap_clear_bit ( to_clear_bitmap , IP_REGNUM ) ; emit_use ( gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; bitmap_clear_bit ( to_clear_bitmap , <NUM_LIT> ) ; } for ( regno = NUM_ARG_REGS ; regno <= maxregno ; regno ++ ) { if ( IN_RANGE ( regno , FIRST_VFP_REGNUM , D7_VFP_REGNUM ) ) continue ; if ( IN_RANGE ( regno , IP_REGNUM , PC_REGNUM ) ) continue ; if ( call_used_regs [ regno ] ) bitmap_set_bit ( to_clear_bitmap , regno ) ; } result_type = TREE_TYPE ( DECL_RESULT ( current_function_decl ) ) ;


<s> const uint64_t F = MCID . TSFlags ; unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ; unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ;

if ( isSigned ) return ~ ( - <NUM_LIT> << ( bits - <NUM_LIT> ) ) ;


<s> static SDValue convertLocVTToValVT ( SelectionDAG & DAG , SDLoc DL , CCValAssign & VA , SDValue Chain , SDValue Value ) { if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ;

else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Value = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value , DAG . getValueType ( VA . getValVT ( ) ) ) ;


<s> return iterator_range < func_iterator > ( func_begin ( ) , func_end ( ) ) ;


<s> MBB -> addSuccessor ( TailTestMBB ) ; MBB = LoopBodyMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , IncReg ) . addReg ( PHIReg ) . addImm ( ProbeSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ProbeSize ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( ProbeSize - <NUM_LIT> ) . addReg ( <NUM_LIT> ) . setMemRefs ( VolLdMMO ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( LoopTestMBB ) ; MBB -> addSuccessor ( LoopTestMBB ) ; MBB = TailTestMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( PHIReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( DoneMBB ) ; MBB -> addSuccessor ( TailMBB ) ; MBB -> addSuccessor ( DoneMBB ) ; MBB = TailMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( PHIReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( PHIReg ) . setMemRefs ( VolLdMMO ) ; MBB -> addSuccessor ( DoneMBB ) ; MBB = DoneMBB ; BuildMI ( * MBB , MBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( <STR_LIT> ) ;


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ;

if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ;


<s> return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> tmp = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; } operands [ <NUM_LIT> ] = force_reg ( SImode , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_UNSPEC_VOLATILE ( VOIDmode , gen_rtvec ( <NUM_LIT> , operands [ <NUM_LIT> ] , tmp ) , VUNSPEC_ARC_SR ) ) ; return true ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) && arc_is_aux_reg_p ( operands [ <NUM_LIT> ] ) ) { if ( arc_get_aux_arg ( operands [ <NUM_LIT> ] , & auxr ) ) { tmp = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp , GEN_INT ( auxr ) ) ; } else { tmp = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( tmp ) == SYMBOL_REF ) ; } gcc_assert ( REG_P ( operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( <NUM_LIT> , tmp ) , VUNSPEC_ARC_LR ) ) ) ; return true ; } } if ( ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ <NUM_LIT> ] , Pmode ) ) operands [ <NUM_LIT> ] = arc_rewrite_small_data ( operands [ <NUM_LIT> ] ) ; if ( mode == SImode && SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) { prepare_pic_move ( operands , SImode ) ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) != MEM && ! TARGET_NO_SDATA_SET && small_data_pattern ( operands [ <NUM_LIT> ] , Pmode ) ) { operands [ <NUM_LIT> ] = arc_rewrite_small_data ( operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , operands [ <NUM_LIT> ] ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! ( reload_in_progress || reload_completed ) ) { operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; if ( ! move_dest_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; rtx pat = change_address ( operands [ <NUM_LIT> ] , mode , addr ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } if ( ! cse_not_expected ) { rtx pat = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; pat = arc_legitimize_address_0 ( pat , pat , mode ) ; if ( pat ) { pat = change_address ( operands [ <NUM_LIT> ] , mode , pat ) ; MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = pat ; } } } if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! cse_not_expected ) {


<s> struct m68k_address address ; reg = sched_get_reg_operand ( pro , true ) ; if ( reg == NULL ) return <NUM_LIT> ; mem = sched_get_mem_operand ( con , true , false ) ; gcc_assert ( mem != NULL && MEM_P ( mem ) ) ; if ( ! m68k_decompose_address ( GET_MODE ( mem ) , XEXP ( mem , <NUM_LIT> ) , reload_completed , & address ) ) gcc_unreachable ( ) ; if ( REGNO ( reg ) == REGNO ( address . index ) ) {

gcc_assert ( address . scale != <NUM_LIT> ) ;


<s> bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ;

addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> if ( ( Imm & ~ <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; return countTrailingZeros ( Imm ) ;


<s> if ( type == float128_type_node || type == float64x_type_node ) return NULL ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( type == vector_pair_type_node ) return <STR_LIT> ;

if ( type == vector_quad_type_node ) return <STR_LIT> ;


<s> unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) != <STR_LIT> ) continue ; int Opc = MI . getOpcode ( ) ; bool isLd = isLoadSingle ( Opc ) ; unsigned Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = getMemoryOpOffset ( MI ) ; bool StopHere = false ; if ( isLd ) { DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> >> :: iterator BI = Base2LdsMap . find ( Base ) ; if ( BI != Base2LdsMap . end ( ) ) { for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( * BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( & MI ) ; } else { Base2LdsMap [ Base ] . push_back ( & MI ) ; LdBases . push_back ( Base ) ; } } else { DenseMap < unsigned , SmallVector < MachineInstr * , <NUM_LIT> >> :: iterator BI = Base2StsMap . find ( Base ) ; if ( BI != Base2StsMap . end ( ) ) { for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( * BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( & MI ) ; } else { Base2StsMap [ Base ] . push_back ( & MI ) ; StBases . push_back ( Base ) ; } } if ( StopHere ) { -- Loc ; break ; } } for ( unsigned i = <NUM_LIT> , e = LdBases . size ( ) ; i != e ; ++ i ) { unsigned Base = LdBases [ i ] ; SmallVectorImpl < MachineInstr * > & Lds = Base2LdsMap [ Base ] ; if ( Lds . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Lds , Base , true , MI2LocMap ) ; } for ( unsigned i = <NUM_LIT> , e = StBases . size ( ) ; i != e ; ++ i ) { unsigned Base = StBases [ i ] ; SmallVectorImpl < MachineInstr * > & Sts = Base2StsMap [ Base ] ; if ( Sts . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Sts , Base , false , MI2LocMap ) ;


<s> output_quoted_string ( stream , name ) ; putc ( '\n' , stream ) ; } else if ( name != current_function_file && strcmp ( name , current_function_file ) != <NUM_LIT> ) { num_source_filenames += <NUM_LIT> ; current_function_file = name ;

fprintf ( stream , <STR_LIT> , num_source_filenames ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & sti ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( sti ) , STI ( sti ) {


<s> <ISA_LIT>WinCOFFStreamer ( MCContext & C , MCAsmBackend & AB , MCCodeEmitter & CE , raw_ostream & OS ) : MCWinCOFFStreamer ( C , AB , CE , OS ) {


<s> if ( ! emitCmp ( ResultReg , CI ) ) return false ; updateValueMap ( I , ResultReg ) ; return true ;


<s> LLVM_DEBUG ( llvm :: dbgs ( ) << <STR_LIT> ) ; if ( CPU . empty ( ) ) CPU = <STR_LIT> ; ParseSubtargetFeatures ( CPU , FS ) ;


<s> void setVarArgsStackIndex ( int Index ) { VarArgsStackIndex = Index ;


<s> LiveBundles . resize ( Bundles -> getNumBundles ( ) ) ; for ( MachineBasicBlock & MBB : MF ) { setKillFlags ( MBB ) ;

const unsigned Mask = calcLiveInMask ( & MBB , false ) ;


<s> M . MyShift = OtherPending > MyPending ? OtherPending - MyPending : <NUM_LIT> ; M . OtherShift = ScoreUBs [ T ] - Other . ScoreUBs [ T ] + M . MyShift ; const uint32_t NewUB = ScoreUBs [ T ] + M . MyShift ; if ( NewUB < ScoreUBs [ T ] ) report_fatal_error ( <STR_LIT> ) ; ScoreUBs [ T ] = NewUB ; ScoreLBs [ T ] = std :: min ( M . OldLB + M . MyShift , M . OtherLB + M . OtherShift ) ; StrictDom |= mergeScore ( M , LastFlat [ T ] , Other . LastFlat [ T ] ) ; bool RegStrictDom = false ; for ( int J = <NUM_LIT> , E = std :: max ( getMaxVGPR ( ) , Other . getMaxVGPR ( ) ) + <NUM_LIT> ; J != E ; J ++ ) { RegStrictDom |= mergeScore ( M , VgprScores [ T ] [ J ] , Other . VgprScores [ T ] [ J ] ) ; } if ( T == LGKM_CNT ) {

for ( int J = <NUM_LIT> , E = std :: max ( getMaxSGPR ( ) , Other . getMaxSGPR ( ) ) + <NUM_LIT> ;


<s> static bool IsAliasOfSX ( Register Reg ) { return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ;


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool Verbose , raw_ostream & Out ) { PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , OptLevel , Verbose ) ) ;


<s> if ( Ty . isVector ( ) ) return Ty . changeElementCount ( ElementCount :: getFixed ( PowerOf2Ceil ( Ty . getNumElements ( ) ) ) ) ;

return LLT :: scalar ( PowerOf2Ceil ( Ty . getSizeInBits ( ) ) ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT PTy = getPointerTy ( ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( * getDataLayout ( ) ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , MemVT , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; if ( ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) || ABI . IsN64 ( ) ) { Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Addr , getPICJumpTableRelocBase ( Table , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Addr ) ;


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_ACC ) && <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isSaveCalleeSavedRegsCall ( const MachineInstr & MI ) const { return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectVLOp ( SDValue N , SDValue & VL ) { auto * C = dyn_cast < ConstantSDNode > ( N ) ; if ( C && ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) || C -> getSExtValue ( ) == <STR_LIT> ) ) VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; else VL = N ;


<s> if ( ! GetImm ( MI2 , <NUM_LIT> , Offset2 ) ) return false ; Register Reg1 = MI1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg2 = MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

return ( ( Offset1 == ( Offset2 - <NUM_LIT> ) ) && ( ConsecutiveRegisters ( Reg1 , Reg2 ) ) ) ;


<s> enum class PPA1Flag3 : uint8_t { FPRMask = ( <NUM_LIT> >> <NUM_LIT> ) , LLVM_MARK_AS_BITMASK_ENUM ( FPRMask ) } ; enum class PPA1Flag4 : uint8_t { EPMOffsetPresent = ( <NUM_LIT> >> <NUM_LIT> ) , VRMask = ( <NUM_LIT> >> <NUM_LIT> ) , ProcedureNamePresent = ( <NUM_LIT> >> <NUM_LIT> ) , LLVM_MARK_AS_BITMASK_ENUM ( EPMOffsetPresent ) } ; auto Flags1 = PPA1Flag1 ( <NUM_LIT> ) ; auto Flags2 = PPA1Flag2 :: ExternalProcedure ; auto Flags3 = PPA1Flag3 ( <NUM_LIT> ) ; auto Flags4 = PPA1Flag4 :: EPMOffsetPresent | PPA1Flag4 :: ProcedureNamePresent ; Flags1 |= PPA1Flag1 :: DSA64Bit ; if ( VarArg ) Flags1 |= PPA1Flag1 :: VarArg ; if ( StackProtector ) Flags2 |= PPA1Flag2 :: STACKPROTECTOR ; if ( FPRMask ) Flags3 |= PPA1Flag3 :: FPRMask ; if ( VRMask ) Flags4 |= PPA1Flag4 :: VRMask ;

OutStreamer -> AddComment ( <STR_LIT> ) ;


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;

return Infos [ Kind - FirstTargetFixupKind ] ;


<s> MachineInstr * setRegister ( MachineInstr & I , unsigned * TLSBaseAddrReg ) { MachineFunction * MF = I . getParent ( ) -> getParent ( ) ; const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ;

MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ;


<s> if ( ! need_zero_all_mm ) return false ; machine_mode mode = V2SImode ; for ( unsigned int regno = FIRST_MMX_REG ; regno <= LAST_MMX_REG ; regno ++ ) if ( regno != ret_mmx_regno ) { rtx reg = gen_rtx_REG ( mode , regno ) ; emit_insn ( gen_rtx_SET ( reg , CONST0_RTX ( mode ) ) ) ;


<s> unsigned encodeLgkmcnt ( const IsaVersion & Version , unsigned Waitcnt , unsigned Lgkmcnt ) { return packBits ( Lgkmcnt , Waitcnt , getLgkmcntBitShift ( Version . Major ) , getLgkmcntBitWidth ( Version . Major ) ) ;


<s> gimple * stmt = gsi_stmt ( i ) ; if ( gimple_code ( stmt ) != GIMPLE_CALL ) continue ; tree callee = gimple_call_fndecl ( stmt ) ; if ( ! callee ) continue ; tree attrs = oacc_get_fn_attrib ( callee ) ; if ( attrs == NULL_TREE ) return false ; int partition_level = oacc_fn_attrib_level ( attrs ) ;


<s> static std :: vector < Constant * > createAString ( std :: string input , Type * & Int8Ty ) {


<s> unsigned Hint = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ;

Inst . addOperand ( MCOperand :: createImm ( Hint ) ) ;


<s> Ordered [ <NUM_LIT> ] = ExpInstrTypesSeen == <NUM_LIT> ; Ordered [ <NUM_LIT> ] = false ; Counters Counts = WaitCounts ; bool NeedWait = false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Required . Array [ i ] <= WaitedOn . Array [ i ] ) continue ; NeedWait = true ; if ( Ordered [ i ] ) { unsigned Value = LastIssued . Array [ i ] - Required . Array [ i ] ; Counts . Array [ i ] = std :: min ( Value , WaitCounts . Array [ i ] ) ; } else Counts . Array [ i ] = <NUM_LIT> ; WaitedOn . Array [ i ] = LastIssued . Array [ i ] - Counts . Array [ i ] ; } if ( ! NeedWait ) return false ; if ( Counts . Named . EXP == <NUM_LIT> ) ExpInstrTypesSeen = <NUM_LIT> ;

BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ( Counts . Named . VM & <NUM_LIT> ) | ( ( Counts . Named . EXP & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Counts . Named . LGKM & <NUM_LIT> ) << <NUM_LIT> ) ) ;


<s> static bool mayTailCallThisCC ( CallingConv :: ID CC ) {


<s> rtx sa ; sa = gen_reg_rtx ( Pmode ) ; cfun -> machine -> eh_stack_adjust = sa ; }

return cfun -> machine -> eh_stack_adjust ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( Memory . OffsetRegNum ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( Memory . ShiftImm ) ) ;


<s> bool hasPrefixInstrs ( ) const { return HasPrefixInstrs ;


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasVLX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; assert ( STI . hasAVX512 ( ) && <STR_LIT> ) ;

if ( isStackAligned ) return load ? <STR_LIT> : <STR_LIT> ;


<s> return EnableMacroFusion ? make_unique < <ISA_LIT>MacroFusion > ( ) : nullptr ;


<s> if ( TARGET_SVE && aarch64_cmp_autovec_modes ( VNx16QImode , V16QImode ) ) return aarch64_full_sve_mode ( mode ) . else_mode ( word_mode ) ;

if ( TARGET_SIMD ) return aarch64_vq_mode ( mode ) . else_mode ( word_mode ) ;


<s> if ( boundary > align && ! integer_zerop ( TYPE_SIZE ( type ) ) ) { if ( ! POINTER_TYPE_P ( type ) ) { t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build_pointer_plus_hwi ( valist_tmp , boundary - <NUM_LIT> ) ) ; gimplify_and_add ( t , pre_p ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist_tmp , fold_build2 ( BIT_AND_EXPR , TREE_TYPE ( valist ) , valist_tmp , build_int_cst ( TREE_TYPE ( valist ) , - boundary ) ) ) ; gimplify_and_add ( t , pre_p ) ; } } else boundary = align ; boundary *= BITS_PER_UNIT ; if ( boundary < TYPE_ALIGN ( type ) ) { type = build_variant_type_copy ( type ) ;


<s> if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && VT . getSizeInBits ( ) > <NUM_LIT> ) return TypeSplitVector ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) return TypePromoteInteger ; if ( VT . getScalarSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ) return TypeWidenVector ;

return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;


<s> return create<ISA_LIT>MachObjectWriter ( OS , true , object :: mach :: CTM_x86_64 , object :: mach :: CS<ISA_LIT>_ALL ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getBytesToPopOnReturn ( ) , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; assert ( VA . getLocInfo ( ) != CCValAssign :: FPExt && <STR_LIT> ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : VCCUsed = true ; continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FlatUsed = true ; continue ; default : break ; } if ( <STR_LIT> . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned hwReg = RI -> getEncodingValue ( reg ) & <NUM_LIT> ; unsigned maxUsed = hwReg + width - <NUM_LIT> ; if ( isSGPR ) { MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR ; } else { MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR ; } } } } unsigned ExtraSGPRs = <NUM_LIT> ; if ( VCCUsed ) ExtraSGPRs = <NUM_LIT> ; if ( STM . getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( FlatUsed ) ExtraSGPRs = <NUM_LIT> ;


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DL ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) {


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) {


<s> emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; }

if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ;


<s> insn = packet_group -> sorted [ i ] ; memcpy ( test_state , state , dfa_size ) ; if ( state_transition ( test_state , insn ) < <NUM_LIT> && cpu_unit_reservation_p ( test_state , NTH_UNIT ( group , upper_slot - <NUM_LIT> ) ) && frv_sort_insn_group_1 ( group , lower_slot , upper_slot - <NUM_LIT> , issued | ( <NUM_LIT> << i ) , num_insns , test_state ) ) { packet_group -> sorted [ upper_slot - <NUM_LIT> ] = insn ;


<s> } } if ( ! NewOpc ) { if ( VT == <STR_LIT> ) return SDValue ( ) ; else return Op ; } } DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Op0 ; SDValue Op1 = SkipExtension ( N1 , DAG ) ; if ( ! isMLA ) { Op0 = SkipExtension ( N0 , DAG ) ; assert ( Op0 . getValueType ( ) . is64BitVector ( ) && Op1 . getValueType ( ) . is64BitVector ( ) && <STR_LIT> ) ; return DAG . getNode ( NewOpc , DL , VT , Op0 , Op1 ) ; } SDValue N00 = SkipExtension ( N0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ; SDValue N01 = SkipExtension ( N0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ; EVT Op1VT = Op1 . getValueType ( ) ; return DAG . getNode ( N0 -> getOpcode ( ) , DL , VT , DAG . getNode ( NewOpc , DL , VT , DAG . getNode ( <STR_LIT> , DL , Op1VT , N00 ) , Op1 ) , DAG . getNode ( NewOpc , DL , VT , DAG . getNode ( <STR_LIT> , DL , Op1VT , N01 ) , Op1 ) ) ;


<s> return __builtin_shuffle ( __a , __b , ( uint32x2_t ) { <NUM_LIT> , <NUM_LIT> } ) ;


<s> } const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { switch ( Op . getReg ( ) ) { case <STR_LIT> : break ; default : O << getRegisterName ( Op . getReg ( ) ) ; break ; } } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else if ( Op . isDFPImm ( ) ) { if ( Op . getDFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { O << bit_cast < double > ( Op . getDFPImm ( ) ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else {


<s> uint64_t SlotSize = PtrVT . getStoreSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) . CreateFixedObject ( SlotSize , - SlotSize , true ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; } return DAG . getFrameIndex ( ReturnAddrIndex , PtrVT ) ;


<s> switch ( CC ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) {


<s> void <ISA_LIT>InstrInfo :: replaceInstrOperandWithImm ( MachineInstr & MI , unsigned OpNo , int64_t Imm ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; Register InUseReg = MI . getOperand ( OpNo ) . getReg ( ) ; MI . getOperand ( OpNo ) . ChangeToImmediate ( Imm ) ; if ( MI . implicit_operands ( ) . empty ( ) ) return ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; int UseOpIdx = MI . findRegisterUseOperandIdx ( InUseReg , false , TRI ) ; if ( UseOpIdx >= <NUM_LIT> ) {

MachineOperand & MO = MI . getOperand ( UseOpIdx ) ;


<s> if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> TransposedMatrix . resize ( <NUM_LIT> ) ; static constexpr int IntMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; ArrayRef < int > Mask = makeArrayRef ( IntMask1 , <NUM_LIT> ) ; Value * IntrVec1 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; Value * IntrVec2 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; static constexpr int IntMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Mask = makeArrayRef ( IntMask2 , <NUM_LIT> ) ; Value * IntrVec3 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; Value * IntrVec4 = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , Mask ) ; static constexpr int IntMask3 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Mask = makeArrayRef ( IntMask3 , <NUM_LIT> ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec1 , IntrVec2 , Mask ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec3 , IntrVec4 , Mask ) ; static constexpr int IntMask4 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Mask = makeArrayRef ( IntMask4 , <NUM_LIT> ) ; TransposedMatrix [ <NUM_LIT> ] = Builder . CreateShuffleVector ( IntrVec1 , IntrVec2 , Mask ) ;


<s> return ( __m256i ) __builtin_ia32_pmovuswb512_mask ( ( __v32hi ) __A , ( __v32qi ) _mm256_undefined_si256 ( ) , ( __mmask32 ) - <NUM_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ;

unsigned StackAlign = getStackAlignment ( ) ;


<s> int64_t Value = CE -> getValue ( ) ;

return Value > <NUM_LIT> && Value <= <NUM_LIT> ;


<s> insn = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insn , temp3 , o0 , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_TLSLD_BASE ) ) ; temp1 = gen_reg_rtx ( SImode ) ; temp2 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_tldo_hix22 ( temp1 , addr ) ) ; emit_insn ( gen_tldo_lox10 ( temp2 , temp1 , addr ) ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_tldo_add32 ( ret , temp3 , temp2 , addr ) ) ; else emit_insn ( gen_tldo_add64 ( ret , temp3 , temp2 , addr ) ) ; break ; case TLS_MODEL_INITIAL_EXEC : temp1 = gen_reg_rtx ( SImode ) ; temp2 = gen_reg_rtx ( SImode ) ; temp3 = gen_reg_rtx ( Pmode ) ; got = sparc_tls_got ( ) ; emit_insn ( gen_tie_hi22 ( temp1 , addr ) ) ; emit_insn ( gen_tie_lo10 ( temp2 , temp1 , addr ) ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_tie_ld32 ( temp3 , got , temp2 , addr ) ) ; else emit_insn ( gen_tie_ld64 ( temp3 , got , temp2 , addr ) ) ; if ( TARGET_SUN_TLS ) { ret = gen_reg_rtx ( Pmode ) ; if ( TARGET_ARCH32 ) emit_insn ( gen_tie_add32 ( ret , gen_rtx_REG ( Pmode , <NUM_LIT> ) , temp3 , addr ) ) ; else emit_insn ( gen_tie_add64 ( ret , gen_rtx_REG ( Pmode , <NUM_LIT> ) , temp3 , addr ) ) ; } else ret = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) , temp3 ) ; break ; case TLS_MODEL_LOCAL_EXEC : temp1 = gen_reg_rtx ( Pmode ) ; temp2 = gen_reg_rtx ( Pmode ) ; if ( TARGET_ARCH32 ) { emit_insn ( gen_tle_hix22_sp32 ( temp1 , addr ) ) ; emit_insn ( gen_tle_lox10_sp32 ( temp2 , temp1 , addr ) ) ; } else {

emit_insn ( gen_tle_hix22_sp64 ( temp1 , addr ) ) ;


<s> switch ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) { case ( <STR_LIT> ) : cond = loadZ ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; break ; case ( <STR_LIT> ) : cond = loadC ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadC , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; break ; case ( <STR_LIT> ) : cond = loadN ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadN , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; break ; case ( <STR_LIT> ) : cond = loadV ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadV , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> and_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadC , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> or_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadC , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> eq ( <NUM_LIT> , loadN , loadV ) ; break ; case ( <STR_LIT> ) : cond = ctx -> neq ( <NUM_LIT> , loadN , loadV ) ; break ; case ( <STR_LIT> ) : cond = ctx -> and_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> eq ( <NUM_LIT> , loadN , loadV ) ) ; break ; case ( <STR_LIT> ) : cond = ctx -> or_ ( <NUM_LIT> , ctx -> eq ( <NUM_LIT> , loadZ , ctx -> dec_unsigned ( <NUM_LIT> , <NUM_LIT> ) ) , ctx -> neq ( <NUM_LIT> , loadN , loadV ) ) ; break ;


<s> const auto & Op = MI . getOperand ( i ) ;

if ( Op . isReg ( ) && Op . getReg ( ) == BaseReg ) return true ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {


<s> assert ( VecVT . getSizeInBits ( ) < <NUM_LIT> && <STR_LIT> ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; unsigned WideNumElts = <NUM_LIT> / EltVT . getSizeInBits ( ) ; EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , WideNumElts ) ; unsigned NumConcat = WideNumElts / VecVT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ;


<s> assert ( T < NUM_INST_CNTS ) ; if ( T >= NUM_INST_CNTS ) return <NUM_LIT> ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = getRegTy ( SrcReg , MF ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , I , I -> getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; I -> getOperand ( <NUM_LIT> ) . setReg ( DstReg ) ;


<s> last2 = <NUM_LIT> ; aligned_p = true ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; for ( insn = get_insns ( ) ; insn != <NUM_LIT> ; insn = next ) { unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; length = get_attr_length ( insn ) ; if ( length > <NUM_LIT> && USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { gcc_assert ( last2 ) ; emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; } else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) { gcc_assert ( last ) ; emit_insn_after ( gen_nop ( ) , last ) ; aligned_p = true ; } } mips_sim_issue_insn ( & state , subinsn ) ; }

mips_sim_finish_insn ( & state , insn ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> unsigned getCalleeSavedFrameSize ( ) const { return CalleeSavedFrameSize ;


<s> static std :: vector < Value * > collectGenericAddressExpressions ( Function & F ) { std :: vector < std :: pair < Value * , bool >> PostorderStack ; DenseSet < Value * > Visited ; for ( Instruction & I : instructions ( F ) ) { if ( isa < LoadInst > ( I ) ) {


<s> return ret ; } else if ( TREE_CODE ( args ) != STRING_CST ) { error ( <STR_LIT> ) ; return false ; } char * argstr = ASTRDUP ( TREE_STRING_POINTER ( args ) ) ; char * q ; while ( ( q = strtok ( argstr , <STR_LIT> ) ) != NULL ) { argstr = NULL ; if ( ! strcmp ( q , <STR_LIT> ) ) opts -> x_target_flags |= MASK_THUMB ; else if ( ! strcmp ( q , <STR_LIT> ) ) opts -> x_target_flags &= ~ MASK_THUMB ; else if ( ! strcmp ( q , <STR_LIT> ) ) opts -> x_target_flags |= MASK_GENERAL_REGS_ONLY ; else if ( ! strncmp ( q , <STR_LIT> , <NUM_LIT> ) ) { int fpu_index ; if ( ! opt_enum_arg_to_value ( OPT_mfpu_ , q + <NUM_LIT> , & fpu_index , CL_TARGET ) ) { error ( <STR_LIT> , q ) ; return false ; } if ( fpu_index == TARGET_FPU_auto ) { sorry ( <STR_LIT> ) ; return false ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ;

if ( ! Subtarget . isThumb ( ) ) MIB . addReg ( <NUM_LIT> ) ;


<s> int arc_return_slot_offset ( ) { struct arc_frame_info * afi = & cfun -> machine -> frame_info ; return ( afi -> save_return_addr ? afi -> total_size - afi -> pretend_size - afi -> extra_size : - <NUM_LIT> ) ;


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI ) : MCELFStreamer ( Context , MAB , OS , Emitter ) { RegInfoRecord = new <ISA_LIT>RegInfoRecord ( this , Context ) ; <ISA_LIT>OptionRecords . push_back ( std :: unique_ptr < <ISA_LIT>RegInfoRecord > ( RegInfoRecord ) ) ;


<s> static __inline qword si_rotqby ( qword a , qword count ) { vec_uchar16 left , right ; left = vec_sl ( vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) , vec_splat_u8 ( <NUM_LIT> ) ) ; right = vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , left ) ;

return ( ( qword ) ( vec_or ( vec_slo ( ( vec_uchar16 ) ( a ) , left ) , vec_sro ( ( vec_uchar16 ) ( a ) , right ) ) ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVLD2DUP ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> MachineOperand & dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & src = MI -> getOperand ( <NUM_LIT> ) ; assert ( src . isReg ( ) && dst . isReg ( ) && dst . isDef ( ) ) ; int srcside = <STR_LIT> . contains ( src . getReg ( ) ) ? <NUM_LIT> : <NUM_LIT> ; int dstside = <STR_LIT> . contains ( dst . getReg ( ) ) ? <NUM_LIT> : <NUM_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; DEBUG ( dbgs ( ) << MI -> getDesc ( ) . getName ( ) << <STR_LIT> << ( <STR_LIT> . contains ( src . getReg ( ) ) ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( <STR_LIT> . contains ( dst . getReg ( ) ) ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ) ;


<s> return ( __m512i ) __builtin_ia32_broadcasti64x4_512 ( ( __v4di ) __A , ( __v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned UsedBanks = <NUM_LIT> ; if ( MI . isDebugValue ( ) ) return std :: make_pair ( StallCycles , UsedBanks ) ; RegsUsed . reset ( ) ; OperandMasks . clear ( ) ; for ( const auto & Op : MI . explicit_uses ( ) ) { if ( ! Op . isReg ( ) || Op . isUndef ( ) ) continue ; const Register R = Op . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getRegClassForReg ( * MRI , R ) ; if ( TRI -> hasAGPRs ( RC ) ) continue ; if ( Op . getSubReg ( ) ) { LaneBitmask LM = TRI -> getSubRegIndexLaneMask ( Op . getSubReg ( ) ) ; if ( TRI -> hasVGPRs ( RC ) ) { if ( TRI -> getNumCoveredRegs ( LM ) >= NUM_VGPR_BANKS ) continue ; } else { if ( TRI -> getNumCoveredRegs ( LM ) / <NUM_LIT> >= NUM_SGPR_BANKS ) continue ;


<s> static void mips_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx addr , end_addr , high , low , opcode , mem ; rtx trampoline [ <NUM_LIT> ] ; unsigned int i , j ; HOST_WIDE_INT end_addr_offset , static_chain_offset , target_function_offset ; end_addr_offset = mips_trampoline_code_size ( ) ; static_chain_offset = end_addr_offset ; target_function_offset = static_chain_offset + GET_MODE_SIZE ( ptr_mode ) ; addr = force_reg ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ; end_addr = mips_force_binary ( Pmode , PLUS , addr , GEN_INT ( end_addr_offset ) ) ; i = <NUM_LIT> ; if ( TARGET_USE_PIC_FN_ADDR_REG ) { trampoline [ i ++ ] = OP ( MIPS_LOAD_PTR ( AT_REGNUM , target_function_offset , PIC_FUNCTION_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_LOAD_PTR ( STATIC_CHAIN_REGNUM , static_chain_offset , PIC_FUNCTION_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_JR ( AT_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_MOVE ( PIC_FUNCTION_ADDR_REGNUM , AT_REGNUM ) ) ; } else if ( ptr_mode == DImode ) { trampoline [ i ++ ] = OP ( MIPS_MOVE ( AT_REGNUM , RETURN_ADDR_REGNUM ) ) ;

trampoline [ i ++ ] = OP ( MIPS_BAL ( <NUM_LIT> ) ) ;


<s> if ( ! Register :: isVirtualRegister ( Reg ) ) continue ; ( void ) LiveRegs . insert ( Reg ) ; }


<s> EVT InVT = <STR_LIT> ( <STR_LIT> ( InBits ) , <STR_LIT> / InBits ) ; SDValue PackedOp = DAG . getNode ( <STR_LIT> , DL , InVT , Op ) ;


<s> bool <ISA_LIT>InstrInfo :: isV60VectorInstruction ( const MachineInstr & MI ) const { const uint64_t V = getType ( MI ) ; return <STR_LIT> <= V && V <= <STR_LIT> ;


<s> if ( output_sdata ) fputs ( <STR_LIT> , file ) ; output_sdata = <NUM_LIT> ; break ; case PLUS : if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == MULT ) index = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , base = XEXP ( addr , <NUM_LIT> ) ; else if ( CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) index = XEXP ( addr , <NUM_LIT> ) , base = XEXP ( addr , <NUM_LIT> ) ; else base = XEXP ( addr , <NUM_LIT> ) , index = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( OBJECT_P ( base ) ) ; arc_print_operand_address ( file , base ) ; if ( CONSTANT_P ( base ) && CONST_INT_P ( index ) ) fputc ( '+' , file ) ; else fputc ( ',' , file ) ; gcc_assert ( OBJECT_P ( index ) ) ; arc_print_operand_address ( file , index ) ; break ;


<s> } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ;

else if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ;


<s> { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX2InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( Opcode == Instruction :: Load ) { if ( const auto * Entry = CostTableLookup ( AVX2InterleavedLoadTbl , Factor , ETy . getSimpleVT ( ) ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; } else { assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; if ( const auto * Entry = CostTableLookup ( AVX2InterleavedStoreTbl , Factor , ETy . getSimpleVT ( ) ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind ) ;


<s> bool isLROk = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; bool isSPOk = isPCOk || isLROk || ( Opc == <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) continue ; unsigned Reg = MO . getReg ( ) ;

if ( Reg == <NUM_LIT> || Reg == <STR_LIT> ) continue ;


<s> return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> reg1 = XEXP ( addr1 , <NUM_LIT> ) ; offset1 = INTVAL ( XEXP ( addr1 , <NUM_LIT> ) ) ; } else return <NUM_LIT> ; if ( REG_P ( addr2 ) ) { reg2 = addr2 ; offset2 = <NUM_LIT> ; } else if ( GET_CODE ( addr2 ) == PLUS && REG_P ( XEXP ( addr2 , <NUM_LIT> ) ) && GET_CODE ( XEXP ( addr2 , <NUM_LIT> ) ) == CONST_INT ) { reg2 = XEXP ( addr2 , <NUM_LIT> ) ;

offset2 = INTVAL ( XEXP ( addr2 , <NUM_LIT> ) ) ;


<s> } if ( MO . isFPImm ( ) ) { return MO . getFPImm ( ) -> isExactlyValue ( <NUM_LIT> ) || MO . getFPImm ( ) -> isExactlyValue ( <NUM_LIT> ) || MO . getFPImm ( ) -> isExactlyValue ( - <NUM_LIT> ) || MO . getFPImm ( ) -> isExactlyValue ( <NUM_LIT> ) || MO . getFPImm ( ) -> isExactlyValue ( - <NUM_LIT> ) || MO . getFPImm ( ) -> isExactlyValue ( <NUM_LIT> ) || MO . getFPImm ( ) -> isExactlyValue ( - <NUM_LIT> ) || MO . getFPImm ( ) -> isExactlyValue ( <NUM_LIT> ) || MO . getFPImm ( ) -> isExactlyValue ( - <NUM_LIT> ) ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( create<ISA_LIT>CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;


<s> static void normaliseSetCC ( SDValue & LHS , SDValue & RHS , <STR_LIT> & CC ) { switch ( CC ) {


<s> __attribute__ ( ( __always_inline__ ) ) vrsqrte_f32 ( float32x2_t a ) { float32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result ;


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( AddressRegI64 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( ShadowRegI64 ) . addImm ( <NUM_LIT> ) ) ; { MCInst Inst ; switch ( AccessSize ) { case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : assert ( false && <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> static DecodeStatus DecodeGR32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT> ) ;


<s> bool cris_output_addr_const_extra ( FILE * file , rtx xconst ) { switch ( GET_CODE ( xconst ) ) { rtx x ; case UNSPEC : x = XVECEXP ( xconst , <NUM_LIT> , <NUM_LIT> ) ; CRIS_ASSERT ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == CONST ) ; output_addr_const ( file , x ) ; switch ( XINT ( xconst , <NUM_LIT> ) ) { case CRIS_UNSPEC_PLT : fprintf ( file , <STR_LIT> ) ; break ; case CRIS_UNSPEC_GOTREL : fprintf ( file , <STR_LIT> ) ; break ; case CRIS_UNSPEC_GOTREAD : if ( flag_pic == <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; else fprintf ( file , <STR_LIT> ) ; break ; case CRIS_UNSPEC_PLTGOTREAD : if ( flag_pic == <NUM_LIT> ) fprintf ( file , CRIS_GOTPLT_SUFFIX <STR_LIT> ) ; else fprintf ( file , CRIS_GOTPLT_SUFFIX ) ; break ; default : gcc_unreachable ( ) ; } return true ;


<s> Ptr1Reg = ptrB ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Shift1Reg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , ShiftReg ) . addReg ( Shift1Reg ) . addImm ( is8bit ? <NUM_LIT> : <NUM_LIT> ) ; if ( is64bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , PtrReg ) . addReg ( Ptr1Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Incr2Reg ) . addReg ( incr ) . addReg ( ShiftReg ) ; if ( is8bit ) BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addImm ( <NUM_LIT> ) ; else { BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask3Reg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , Mask2Reg ) . addReg ( Mask3Reg ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , MaskReg ) . addReg ( Mask2Reg ) . addReg ( ShiftReg ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) , TmpDestReg ) . addReg ( ZeroReg ) . addReg ( PtrReg ) ; if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( Incr2Reg ) . addReg ( TmpDestReg ) ;

BuildMI ( BB , dl , TII -> get ( is64bit ? <STR_LIT> : <STR_LIT> ) , Tmp2Reg ) . addReg ( TmpDestReg ) . addReg ( MaskReg ) ;


<s> int64_t Val = ~ MCE -> getValue ( ) & <NUM_LIT> ;

uint64_t encoding = <STR_LIT> ( Val , <NUM_LIT> ) ;


<s> fprintf ( file , AS1 ( rjmp , __prologue_saves__ + % d ) <STR_LIT> , ( <NUM_LIT> - live_seq ) * <NUM_LIT> ) ; ++ prologue_size ; } fputs ( <STR_LIT> , file ) ; } else { HARD_REG_SET set ; prologue_size += avr_regs_to_save ( & set ) ; for ( reg = <NUM_LIT> ; reg < <NUM_LIT> ; ++ reg ) { if ( TEST_HARD_REG_BIT ( set , reg ) ) { fprintf ( file , <STR_LIT> AS1 ( push , % s ) <STR_LIT> , avr_regnames [ reg ] ) ; } } if ( frame_pointer_needed ) { fprintf ( file , <STR_LIT> AS1 ( push , r28 ) CR_TAB AS1 ( push , r29 ) CR_TAB AS2 ( in , r28 , __SP_L__ ) CR_TAB AS2 ( in , r29 , __SP_H__ ) <STR_LIT> ) ; prologue_size += <NUM_LIT> ; if ( size ) { fputs ( <STR_LIT> , file ) ; prologue_size += out_adj_frame_ptr ( file , size ) ; if ( interrupt_func_p ) { prologue_size += out_set_stack_ptr ( file , <NUM_LIT> , <NUM_LIT> ) ;


<s> case <STR_LIT> : { auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( LT . second == <STR_LIT> ) return LT . first * <NUM_LIT> ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : { static const auto ValidMinMaxTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { static const auto ValidSatTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; unsigned Instrs = LT . second . getScalarSizeInBits ( ) == RetTy -> getScalarSizeInBits ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( any_of ( ValidSatTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first * Instrs ; break ; } case <STR_LIT> : { static const auto ValidAbsTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidAbsTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ; } case <STR_LIT> : { InstructionCost Cost = <NUM_LIT> ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( LT . first > <NUM_LIT> ) { Type * LegalVTy = EVT ( LT . second ) . getTypeForEVT ( RetTy -> getContext ( ) ) ; InstructionCost AddCost = getArithmeticInstrCost ( Instruction :: Add , LegalVTy , CostKind ) ; Cost += AddCost * ( LT . first - <NUM_LIT> ) ; } return Cost ; } default : break ;


<s> if ( ! Exit ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool ClonedVCTPInExitBlock = false ; for ( auto & Pair : NewPredicates ) { Instruction * OldPred = Pair . first ; Instruction * NewPred = Pair . second ; for ( auto & I : * Exit ) { if ( I . isSameOperationAs ( OldPred ) ) { Instruction * PredClone = NewPred -> clone ( ) ; PredClone -> insertBefore ( & I ) ; I . replaceAllUsesWith ( PredClone ) ; MaybeDead . insert ( & I ) ; ClonedVCTPInExitBlock = true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I . dump ( ) ; dbgs ( ) << <STR_LIT> ; PredClone -> dump ( ) ) ;


<s> } else { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } return NULL_TREE ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> bool riscv_shamt_matches_mask_p ( int shamt , HOST_WIDE_INT mask ) {


<s> } } for ( offset = <NUM_LIT> , i = <NUM_LIT> ; offset + delta <= length ; offset += delta , i ++ ) if ( MEM_ALIGN ( dest ) >= bits ) mips_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; else { rtx part = adjust_address ( dest , BLKmode , offset ) ; set_mem_size ( part , delta ) ; if ( ! mips_expand_ins_as_unaligned_store ( part , regs [ i ] , bits , <NUM_LIT> ) ) gcc_unreachable ( ) ; } if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , RETURN_BEGIN ) ; }


<s> int getScatterOverhead ( ) const { return ScatterOverhead ;


<s> delim = false ; } else { if ( ! delim ) putc ( '"' , file ) ; delim = true ; putc ( c , file ) ; } } if ( delim ) putc ( '"' , file ) ; putc ( '\n' , file ) ; } else { fprintf ( file , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < size ; i ++ ) { fprintf ( file , <STR_LIT> , * p ++ & <NUM_LIT> ) ; if ( i < size - <NUM_LIT> ) putc ( ',' , file ) ; } putc ( '\n' , file ) ; }


<s> switch ( TSFlags & <STR_LIT> ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> :


<s> virtual unsigned getIEQOpcode ( ) const {

assert ( ! <STR_LIT> ) ; return <NUM_LIT> ;


<s> const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ;


<s> return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : { EVT EltTy = VT . getVectorElementType ( ) ; unsigned Opcode ; if ( EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( EltTy == <STR_LIT> || EltTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) OpLHS = WidenVector ( OpLHS , DAG ) ; SDValue Lane = DAG . getConstant ( OpNum - OP_VDUP0 , dl , <STR_LIT> ) ; return DAG . getNode ( Opcode , dl , VT , OpLHS , Lane ) ; } case OP_VEXT1 : case OP_VEXT2 : case OP_VEXT3 : { unsigned Imm = ( OpNum - OP_VEXT1 + <NUM_LIT> ) * getExtFactor ( OpLHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS , OpRHS , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; } case OP_VUZPL : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VUZPR : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VZIPL : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VZIPR : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ; case OP_VTRNL : return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , OpLHS , OpRHS ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerHvxStore ( SDValue Op , SelectionDAG & DAG ) const { auto * N = Op . getNode ( ) ; const SDLoc & dl ( Op ) ; SDValue Q0 = N -> getOperand ( <NUM_LIT> ) ; EVT VTOp = Q0 . getNode ( ) -> getValueType ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) != <STR_LIT> || VTOp != <STR_LIT> ) return Op ; SDValue Vor4 = HvxVecPredBitcastComputation ( Q0 , DAG ) ; SDValue C0 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C0 , DAG ) ; SDValue Vextract0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC0 } , DAG ) ; SDValue C32 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC32 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C32 , DAG ) ; SDValue Vextract1 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC32 } , DAG ) ; SDValue Combine0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vextract1 , Vextract0 } , DAG ) ; SDValue C64 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC64 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C64 , DAG ) ; SDValue Vextract2 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC64 } , DAG ) ; SDValue C96 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue InstrC96 = getInstr ( <STR_LIT> , dl , <STR_LIT> , C96 , DAG ) ; SDValue Vextract3 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vor4 , InstrC96 } , DAG ) ; SDValue Combine1 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vextract3 , Vextract2 } , DAG ) ; StoreSDNode * ST = cast < StoreSDNode > ( Op . getNode ( ) ) ;

SDValue C8 = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;


<s> MachineFrameInfo * MFI = & MF . getFrameInfo ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( StackAlign > <NUM_LIT> ) {


<s> unsigned getVType ( ) const { assert ( Kind == KindTy :: VType && <STR_LIT> ) ;


<s> bool hasFP ( const MachineFunction & MF ) const { return false ;


<s> static void visium_function_arg_advance ( cumulative_args_t pcum_v , const function_arg_info & arg ) { int size = ( GET_MODE_SIZE ( arg . mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; int stack_size = <NUM_LIT> ; CUMULATIVE_ARGS * ca = get_cumulative_args ( pcum_v ) ; if ( TARGET_FPU && ( ( GET_MODE_CLASS ( arg . mode ) == MODE_FLOAT && GET_MODE_SIZE ( arg . mode ) <= UNITS_PER_HWFPVALUE ) || ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( arg . mode ) <= UNITS_PER_HWFPVALUE * <NUM_LIT> ) ) ) { if ( ca -> frcount + size <= MAX_ARGS_IN_FP_REGISTERS ) ca -> frcount += size ; else { stack_size = size ; ca -> frcount = MAX_ARGS_IN_FP_REGISTERS ; } } else {

if ( ca -> grcount + size <= MAX_ARGS_IN_GP_REGISTERS ) ca -> grcount += size ;


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > Mask , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . getScalarType ( ) == <STR_LIT> ) return false ; if ( VT . getSimpleVT ( ) . getSizeInBits ( ) == <NUM_LIT> ) return false ; return isTypeLegal ( VT . getSimpleVT ( ) ) ;


<s> else Emit<ISA_LIT>MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst ) ;


<s> if ( Subtarget -> isGP64bit ( ) ) { Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , CurDAG -> getTargetConstant ( <NUM_LIT> , VT ) , SDValue ( Carry , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <STR_LIT> , VT ) ) ; } SDNode * AddCarry = CurDAG -> getMachineNode ( ADDuOp , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ;

return CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ;


<s> MachineFunction * MF = BB . getParent ( ) ; const bool ArePtrs64bit = STI -> getABI ( ) . ArePtrs64bit ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; unsigned LL , SC , ZERO , BNE , BEQ , MOVE ; if ( Size == <NUM_LIT> ) { if ( STI -> inMicro<ISA_LIT>Mode ( ) ) { LL = STI -> has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = STI -> has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ; BNE = STI -> has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ; BEQ = STI -> has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ; } else { LL = STI -> has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; SC = STI -> has<ISA_LIT>32r6 ( ) ? ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) : ( ArePtrs64bit ? <STR_LIT> : <STR_LIT> ) ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } ZERO = <STR_LIT> ; MOVE = <STR_LIT> ; } else { LL = STI -> has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = STI -> has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; MOVE = <STR_LIT> ; } Register Dest = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ptr = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OldVal = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewVal = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Scratch = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const BasicBlock * LLVM_BB = BB . getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB . getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , & BB , std :: next ( MachineBasicBlock :: iterator ( I ) ) , BB . end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( & BB ) ; BB . addSuccessor ( loop1MBB , BranchProbability :: getOne ( ) ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop1MBB -> normalizeSuccProbs ( ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; loop2MBB -> normalizeSuccProbs ( ) ; BuildMI ( loop1MBB , DL , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ;

BuildMI ( loop1MBB , DL , TII -> get ( BNE ) ) . addReg ( Dest , RegState :: Kill ) . addReg ( OldVal ) . addMBB ( exitMBB ) ;


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_VSrc16 ( unsigned Val ) const { return decodeSrcOp ( OPW16 , Val ) ;


<s> unsigned <ISA_LIT>SEInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> case IES_REGISTER : case IES_INIT : case IES_OFFSET : State = IES_MINUS ; if ( CurrState == IES_REGISTER || CurrState == IES_RPAREN || CurrState == IES_INTEGER || CurrState == IES_RBRAC || CurrState == IES_OFFSET ) IC . pushOperator ( IC_MINUS ) ; else if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { ErrMsg = <STR_LIT> ; return true ; } else IC . pushOperator ( IC_NEG ) ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg ; } else { if ( IndexReg ) { ErrMsg = <STR_LIT> ; return true ; } IndexReg = TmpReg ; Scale = <NUM_LIT> ; } } break ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) , Chain . getValue ( <NUM_LIT> ) ) ; } if ( Subtarget -> isTargetWindows ( ) || Subtarget -> isTargetMingw ( ) ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getEntryNode ( ) ; Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) :

( Subtarget -> isTargetMingw ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) :


<s> if ( Ops . size ( ) != <NUM_LIT> ) return ; unsigned UniqueOpndIdx ; if ( Ops [ <NUM_LIT> ] . isIdenticalTo ( Ops [ <NUM_LIT> ] ) ) UniqueOpndIdx = <NUM_LIT> ; else if ( Ops [ <NUM_LIT> ] . isIdenticalTo ( Ops [ <NUM_LIT> ] ) ) UniqueOpndIdx = <NUM_LIT> ; else if ( Ops [ <NUM_LIT> ] . isIdenticalTo ( Ops [ <NUM_LIT> ] ) ) UniqueOpndIdx = <NUM_LIT> ; else return ; unsigned Reg = MI . getOperand ( OpToReplace ) . getReg ( ) ;


<s> int <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , bool IsComplex ) { unsigned NumVectorInstToHideOverhead = <NUM_LIT> ;

if ( Ty -> isVectorTy ( ) && IsComplex ) return NumVectorInstToHideOverhead ;


<s> for ( const MachineOperand & Op : MRI -> use_operands ( Rd . Reg ) ) { if ( Rd != Register ( Op ) ) return OffsetRange :: zero ( ) ; Range . intersect ( getOffsetRange ( Rd , * Op . getParent ( ) ) ) ; }


<s> if ( Val == DoubleToBits ( <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return true ; } } for ( MCRegAliasIterator R ( <STR_LIT> , & MRI , true ) ; R . isValid ( ) ; ++ R ) { if ( * R == RegNo ) return false ; }


<s> static DecodeStatus DecodeBankedReg ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned R = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned SysM = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; if ( ! DisableHCP ) { addPass ( create<ISA_LIT>ConstPropagationPass ( ) ) ; addPass ( & UnreachableMachineBlockElimID ) ; } if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) ) ; if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) ) ; }


<s> return ( __m256d ) __builtin_ia32_loadupd256_mask ( ( __v4df * ) __P , ( __v4df ) _mm256_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> return __builtin_mve_vcvtbq_f16_f32v8hf ( __a , __b ) ;


<s> if ( label != <NUM_LIT> ) { targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( label ) ) ; asm_fprintf ( asm_out_file , <STR_LIT> , regno ) ; } }


<s> bool <ISA_LIT>RegisterInfo :: isAsmClobberable ( const MachineFunction & MF , unsigned PhysReg ) const {

return ! isReservedReg ( MF , PhysReg ) ;


<s> static inline void desc_abi ( unsigned char abi __attribute__ ( ( unused ) ) , unsigned char context __attribute__ ( ( unused ) ) , struct unw_state_record * sr __attribute__ ( ( unused ) ) ) {


<s> gcc_assert ( GET_CODE ( high ) == HIGH ) ; gcc_assert ( GET_CODE ( XEXP ( high , <NUM_LIT> ) ) == CONST ) ; unspec = XEXP ( XEXP ( high , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; gcc_assert ( XINT ( unspec , <NUM_LIT> ) == UNSPEC_PCREL_SYM ) ; opnds [ <NUM_LIT> ] = XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ; opnds [ <NUM_LIT> ] = XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( opnds [ <NUM_LIT> ] ) != SYMBOL_REF ) return ; first_insn_p = ( opnds [ <NUM_LIT> ] == tilepro_text_label_rtx ( ) ) ; replace_pc_relative_symbol_ref ( insn , opnds , first_insn_p ) ;


<s> SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;

SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedGPR64 ) ; ++ I ) Reserved . set ( ReservedGPR64 [ I ] ) ; if ( ! Subtarget . isABICalls ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isFP64bit ( ) ) { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( Subtarget . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( needsStackRealignment ( MF ) && MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) || <ISA_LIT>FI -> hasSaveS2 ( ) ) Reserved . set ( <STR_LIT> ) ;


<s> if ( GV ) { errs ( ) << <STR_LIT> ; GV -> dump ( ) ; } else if ( CP ) { errs ( ) << <STR_LIT> ; CP -> dump ( ) ; errs ( ) << <STR_LIT> << Align << '\n' ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } for ( auto Reg : <STR_LIT> ) { Reserved . set ( getSubReg ( Reg , <STR_LIT> ) ) ; Register Low = getSubReg ( Reg , <STR_LIT> ) ; if ( ! <STR_LIT> . contains ( Low ) ) Reserved . set ( Low ) ; } Register ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; } MCRegister StackPtrReg = MFI -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg ) { reserveRegisterTuples ( Reserved , StackPtrReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , StackPtrReg ) ) ; } MCRegister FrameReg = MFI -> getFrameOffsetReg ( ) ; if ( FrameReg ) { reserveRegisterTuples ( Reserved , FrameReg ) ;

assert ( ! isSubRegister ( ScratchRSrcReg , FrameReg ) ) ;


<s> const TargetFrameLowering * getFrameLowering ( ) const override {


<s> std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ;

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName , FS ) ;


<s> static bool cortexa7_younger ( FILE * file , int verbose , rtx_insn * insn ) { if ( recog_memoized ( insn ) < <NUM_LIT> ) { if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> , INSN_UID ( insn ) ) ; return false ; } switch ( get_attr_type ( insn ) ) { case TYPE_ALU_IMM : case TYPE_ALUS_IMM : case TYPE_LOGIC_IMM : case TYPE_LOGICS_IMM : case TYPE_EXTEND : case TYPE_MVN_IMM : case TYPE_MOV_IMM : case TYPE_MOV_REG : case TYPE_MOV_SHIFT : case TYPE_MOV_SHIFT_REG : case TYPE_BRANCH : case TYPE_CALL : return true ; default : return false ; }


<s> std :: pair < OutputIt1 , OutputIt2 > copy_if_else ( InputIt First , InputIt Last , OutputIt1 d1 , OutputIt2 d2 , UnaryPredicate Predicate ) { for ( InputIt I = First ; I != Last ; ++ I ) { if ( Predicate ( * I ) ) { * d1 = * I ; d1 ++ ; } else { * d2 = * I ; d2 ++ ; }


<s> return ( CONST_INT_P ( base_or_step ) && IN_RANGE ( INTVAL ( base_or_step ) , - <NUM_LIT> , <NUM_LIT> ) ) ;


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {

return LowerOperationWrapper ( N , Results , DAG ) ;


<s> assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt || VA . getLocInfo ( ) == CCValAssign :: ZExt ) { Size = <NUM_LIT> ; assert ( MRI . getType ( ValVReg ) . isScalar ( ) && <STR_LIT> ) ; MRI . setType ( ValVReg , LLT :: scalar ( <NUM_LIT> ) ) ; } auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , <NUM_LIT> ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ;


<s> EVT PtrVT = Op . getValueType ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , GSD -> getOffset ( ) + <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , GA ) ;


<s> return false ; } if ( ! Mem . WithPostInc ) { return false ; }


<s> InstructionCost getIntImmCostInst ( unsigned Opc , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst = nullptr ) { return getIntImmCost ( Imm , Ty , CostKind ) ;


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; const MachineFunction * MF = BB -> getParent ( ) ; const TargetRegisterInfo * TRI = MF -> getTarget ( ) . getRegisterInfo ( ) ; BitVector ReservedRegs = TRI -> getReservedRegs ( * MF ) ; for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) || MO . isKill ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != <STR_LIT> ) continue ; copy0MBB -> addLiveIn ( Reg ) ; sinkMBB -> addLiveIn ( Reg ) ;


<s> if ( DPP32 != - <NUM_LIT> ) return DPP32 ; auto E32 = <STR_LIT> ( Op ) ;


<s> bool <ISA_LIT>TargetLowering :: IsTailCallConvention ( CallingConv :: ID CallCC ) const { return CallCC == CallingConv :: Fast ;


<s> MBB . addLiveIn ( PreloadedScratchRsrcReg ) ; } } DebugLoc DL ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; Register ScratchWaveOffsetReg ; if ( TRI -> isSubRegisterEq ( ScratchRsrcReg , PreloadedScratchWaveOffsetReg ) ) { ArrayRef < MCPhysReg > AllSGPRs = TRI -> getAllSGPR32 ( MF ) ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) ; AllSGPRs = AllSGPRs . slice ( std :: min ( static_cast < unsigned > ( AllSGPRs . size ( ) ) , NumPreloaded ) ) ; Register GITPtrLoReg = MFI -> getGITPtrLoReg ( MF ) ; for ( MCPhysReg Reg : AllSGPRs ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) && ! TRI -> isSubRegisterEq ( ScratchRsrcReg , Reg ) && GITPtrLoReg != Reg ) { ScratchWaveOffsetReg = Reg ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchWaveOffsetReg ) . addReg ( PreloadedScratchWaveOffsetReg , RegState :: Kill ) ; break ; } } } else {

ScratchWaveOffsetReg = PreloadedScratchWaveOffsetReg ;


<s> void cvtMubufLds ( MCInst & Inst , const OperandVector & Operands ) { cvtMubufImpl ( Inst , Operands , false , false , true ) ;


<s> return Kind == KindTy :: SpecialCapRegister ;


<s> unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( NextReg ) . addReg ( SupReg , RegState :: ImplicitKill ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; MBB . addLiveIn ( SupReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } if ( NumAlignedDPRCS2Regs ) { MBB . addLiveIn ( NextReg ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( NextReg ) . addReg ( <STR_LIT> ) . addImm ( ( NextReg - R4BaseReg ) * <NUM_LIT> ) ) ;


<s> if ( GET_CODE ( x ) == HIGH && aarch64_valid_symref ( XEXP ( x , <NUM_LIT> ) , GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) ) return true ; if ( CONST_INT_P ( x ) ) return true ; if ( GET_CODE ( x ) == SYMBOL_REF && mode == DImode && CONSTANT_ADDRESS_P ( x ) ) return true ; return aarch64_classify_symbolic_expression ( x ) == SYMBOL_TINY_ABSOLUTE ;


<s> return AgentOneAddressSpaceS<ISA_LIT>D ;


<s> Arg . Kind = Kind ; Arg . ValueType = getRuntimeMDValueType ( T , BaseTypeName ) ; if ( ! AccQual . empty ( ) ) { Arg . AccQual = StringSwitch < KernelArg :: AccessQualifer > ( AccQual ) . Case ( <STR_LIT> , KernelArg :: ReadOnly ) . Case ( <STR_LIT> , KernelArg :: WriteOnly ) . Case ( <STR_LIT> , KernelArg :: ReadWrite ) . Default ( KernelArg :: AccNone ) ; } if ( auto * PT = dyn_cast < PointerType > ( T ) ) { Arg . AddrQual = getRuntimeAddrSpace ( static_cast < <ISA_LIT>AS :: AddressSpaces > ( PT -> getAddressSpace ( ) ) ) ;


<s> Node ( const OffsetRange & R ) : MaxEnd ( R . Max ) , Range ( R ) {


<s> FunctionPass * llvm :: create<ISA_LIT>ArgumentMove ( ) {


<s> const GlobalValue * GV = GN -> getGlobal ( ) ; SDLoc dl ( GN ) ; int64_t Offset = GN -> getOffset ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , Offset ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ;


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ;

assert ( MO . isExpr ( ) && <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex ( DAG ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , RetAddrFI , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> bool isMemThumbSPI ( ) const { if ( ! isMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . BaseRegNum != <STR_LIT> || Memory . Alignment != <NUM_LIT> ) return false ;

if ( ! Memory . OffsetImm ) return true ;


<s> Clusters . push_back ( lower ) ; Clusters . push_back ( higher ) ;


<s> if ( EnableA53Fix835769 ) addPass ( create<ISA_LIT>A53Fix835769 ( ) ) ;

if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ;


<s> branch [ ! inverted_p ] = MIPS_BRANCH_C ( <STR_LIT> , <STR_LIT> ) ; branch [ inverted_p ] = MIPS_BRANCH_C ( <STR_LIT> , <STR_LIT> ) ; } else if ( REGNO ( operands [ <NUM_LIT> ] ) != REGNO ( operands [ <NUM_LIT> ] ) ) { branch [ ! inverted_p ] = MIPS_BRANCH_C ( <STR_LIT> , <STR_LIT> ) ; branch [ inverted_p ] = MIPS_BRANCH_C ( <STR_LIT> , <STR_LIT> ) ; } else {

if ( GET_CODE ( operands [ <NUM_LIT> ] ) == NE ) inverted_p = ! inverted_p ;


<s> auto Const = cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ; auto * NewConst = ConstantInt :: get ( Ctx , Const -> getValue ( ) . abs ( ) ) ; Builder . SetInsertPoint ( I ) ; Value * NewVal = Builder . CreateSub ( I -> getOperand ( <NUM_LIT> ) , NewConst ) ; if ( auto * NewInst = dyn_cast < Instruction > ( NewVal ) ) { NewInst -> copyIRFlags ( I ) ; NewInsts . insert ( NewInst ) ; } InstsToRemove . insert ( I ) ;


<s> default : return None ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Sign *= - <NUM_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : {

if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ;


<s> t = __ev_mwhssf ( a , b ) ; return __ev_subfssiaaw ( t ) ;


<s> for ( MachineBasicBlock :: succ_iterator iter = srcBlk -> succ_begin ( ) , iterEnd = srcBlk -> succ_end ( ) ; iter != iterEnd ; ++ iter ) { dstBlk -> addSuccessor ( * iter ) ; }


<s> } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( N -> getNumOperands ( ) == <NUM_LIT> && N0Opc == N1Opc && ( N0Opc == <STR_LIT> || N0Opc == <STR_LIT> || N0Opc == <STR_LIT> || N0Opc == <STR_LIT> ) ) { SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue N11 = N1 -> getOperand ( <NUM_LIT> ) ; EVT N00VT = N00 . getValueType ( ) ; EVT N10VT = N10 . getValueType ( ) ; if ( N00 -> getOpcode ( ) == <STR_LIT> && N01 -> getOpcode ( ) == <STR_LIT> && N10 -> getOpcode ( ) == <STR_LIT> && N11 -> getOpcode ( ) == <STR_LIT> && N00VT == N10VT ) { SDValue N00Source = N00 -> getOperand ( <NUM_LIT> ) ; SDValue N01Source = N01 -> getOperand ( <NUM_LIT> ) ; SDValue N10Source = N10 -> getOperand ( <NUM_LIT> ) ; SDValue N11Source = N11 -> getOperand ( <NUM_LIT> ) ; if ( N00Source == N10Source && N01Source == N11Source && N00Source . getValueType ( ) == VT && N01Source . getValueType ( ) == VT ) { assert ( N0 . getValueType ( ) == N1 . getValueType ( ) ) ; uint64_t N00Index = N00 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N01Index = N01 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N10Index = N10 . getConstantOperandVal ( <NUM_LIT> ) ; uint64_t N11Index = N11 . getConstantOperandVal ( <NUM_LIT> ) ; if ( N00Index == N01Index && N10Index == N11Index && N00Index == <NUM_LIT> && N10Index == N00VT . getVectorNumElements ( ) ) return DAG . getNode ( N0Opc , dl , VT , N00Source , N01Source ) ; } } } if ( N -> getNumOperands ( ) == <NUM_LIT> && N0 == N1 && VT . getVectorNumElements ( ) == <NUM_LIT> ) { assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidenVector ( N0 , DAG ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } if ( N -> getNumOperands ( ) != <NUM_LIT> || N1Opc != <STR_LIT> ) return SDValue ( ) ; SDValue RHS = N1 -> getOperand ( <NUM_LIT> ) ; MVT RHSTy = RHS . getValueType ( ) . getSimpleVT ( ) ; if ( ! RHSTy . isVector ( ) ) return SDValue ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;

MVT ConcatTy = <STR_LIT> ( RHSTy . getVectorElementType ( ) , RHSTy . getVectorNumElements ( ) * <NUM_LIT> ) ;


<s> BB -> updateTerminator ( ) ; MF . RenumberBlocks ( ) ; ++ NumJTMoved ; return NULL ; } MachineBasicBlock * NewBB = MF . CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = JTBB ; ++ MBBI ; MF . insert ( MBBI , NewBB ) ; assert ( isThumb2 && <STR_LIT> ) ; BuildMI ( NewBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) ; MF . RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> removeSuccessor ( BB ) ; JTBB -> addSuccessor ( NewBB ) ;


<s> case VK_<ISA_LIT>_TPOFF_HI32 : case VK_<ISA_LIT>_TPOFF_LO32 : break ; }

fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved ( <STR_LIT> ) ; FunctionPass :: getAnalysisUsage ( AU ) ;


<s> AddedInstIter != Iter ; ++ AddedInstIter ) { dbgs ( ) << <STR_LIT> ;


<s> if ( mid == NULL ) { goto destroy ; } jbyteArray jBArr = ( * env ) -> NewByteArray ( env , <NUM_LIT> ) ; if ( jBArr != NULL ) { ( * env ) -> SetByteArrayRegion ( env , jBArr , <NUM_LIT> , <NUM_LIT> , ( jbyte * ) byteArray ) ; } ( * env ) -> CallStaticVoidMethod ( env , cls , mid , jBArr ) ; ( * env ) -> GetByteArrayRegion ( env , jBArr , <NUM_LIT> , <NUM_LIT> , ( jbyte * ) byteArray ) ; ( * env ) -> DeleteLocalRef ( env , jBArr ) ; destroy : if ( ( * env ) -> ExceptionOccurred ( env ) ) { ( * env ) -> ExceptionDescribe ( env ) ; }


<s> void <ISA_LIT>CFGStructurizer :: removeUnconditionalBranch ( MachineBasicBlock * MBB ) { MachineInstr * BranchMI ; while ( ( BranchMI = getLoopendBlockBranchInstr ( MBB ) ) && isUncondBranch ( BranchMI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BranchMI ) ;