<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32 ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) {

unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ;


<s> } else { rtx const_reg ; rtx insn ; int temp = epilogue_p ? <NUM_LIT> : <NUM_LIT> ; int i ; if ( epilogue_p < <NUM_LIT> || current_function_interrupt || ! call_really_used_regs [ temp ] || fixed_regs [ temp ] ) temp = - <NUM_LIT> ; if ( temp < <NUM_LIT> && ! current_function_interrupt && epilogue_p >= <NUM_LIT> ) { HARD_REG_SET temps ; COPY_HARD_REG_SET ( temps , call_used_reg_set ) ; AND_COMPL_HARD_REG_SET ( temps , call_fixed_reg_set ) ; if ( epilogue_p > <NUM_LIT> ) { int nreg = <NUM_LIT> ; if ( crtl -> return_rtx ) { machine_mode mode ; mode = GET_MODE ( crtl -> return_rtx ) ; if ( BASE_RETURN_VALUE_REG ( mode ) == FIRST_RET_REG ) nreg = HARD_REGNO_NREGS ( FIRST_RET_REG , mode ) ; } for ( i = <NUM_LIT> ; i < nreg ; i ++ ) CLEAR_HARD_REG_BIT ( temps , FIRST_RET_REG + i ) ; if ( crtl -> calls_eh_return ) { CLEAR_HARD_REG_BIT ( temps , EH_RETURN_STACKADJ_REGNO ) ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) CLEAR_HARD_REG_BIT ( temps , EH_RETURN_DATA_REGNO ( i ) ) ; } } if ( epilogue_p <= <NUM_LIT> ) { for ( i = FIRST_PARM_REG ; i < FIRST_PARM_REG + NPARM_REGS ( SImode ) ; i ++ ) CLEAR_HARD_REG_BIT ( temps , i ) ; if ( cfun -> static_chain_decl != NULL ) CLEAR_HARD_REG_BIT ( temps , STATIC_CHAIN_REGNUM ) ; } temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> && live_regs_mask ) { HARD_REG_SET temps ; COPY_HARD_REG_SET ( temps , * live_regs_mask ) ; CLEAR_HARD_REG_BIT ( temps , REGNO ( reg ) ) ; temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> ) { rtx adj_reg , tmp_reg , mem ; gcc_assert ( epilogue_p ) ; gcc_assert ( ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! global_regs [ <NUM_LIT> ] && ! global_regs [ <NUM_LIT> ] ) ; adj_reg = gen_rtx_REG ( GET_MODE ( reg ) , <NUM_LIT> ) ; tmp_reg = gen_rtx_REG ( GET_MODE ( reg ) , <NUM_LIT> ) ; emit_move_insn ( gen_tmp_stack_mem ( Pmode , reg ) , adj_reg ) ; emit_insn ( GEN_MOV ( adj_reg , GEN_INT ( size ) ) ) ; emit_insn ( GEN_ADD3 ( adj_reg , adj_reg , reg ) ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , adj_reg ) ) ;


<s> requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G2 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G2_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_ABS_G3 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G0 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G1 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_SABS_G2 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G2 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G1 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G1_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G0 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_DTPREL_G0_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_G1 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL_G0_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G2 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G1 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G1_NC : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G0 : requestedFixup = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_AARCH64_TPREL_G0_NC : requestedFixup = <STR_LIT> ; break ; } return Result | getAddressWithFixup ( UImm16MO , requestedFixup , Fixups , STI ) ;


<s> for ( ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) assert ( i + <NUM_LIT> < MI -> getNumOperands ( ) && <STR_LIT> ) ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return Offset == <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool isSigned = true ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = ( BaseReg == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += getFrameIndexInstrOffset ( MI , i ) ;

if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ;


<s> return MBB == A -> MBB && <ISA_LIT>ConstantPoolValue :: equals ( A ) ;


<s> loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Dest ) . addReg ( OldVal ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( exitMBB ) ; BB = loop2MBB ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NewVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( loop1MBB ) ;


<s> LiveGPRs . push_back ( DAG . getCopyFromReg ( Chain , DL , GPR , <STR_LIT> ) ) ; } const auto & AvailableXmms = ArgXMMs . slice ( NumXMMRegs ) ; if ( ! AvailableXmms . empty ( ) ) { unsigned AL = TheMachineFunction . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ALVal = DAG . getCopyFromReg ( Chain , DL , AL , <STR_LIT> ) ; for ( MCPhysReg Reg : AvailableXmms ) { unsigned XMMReg = TheMachineFunction . addLiveIn ( Reg , & <STR_LIT> ) ; LiveXMMRegs . push_back ( DAG . getCopyFromReg ( Chain , DL , XMMReg , <STR_LIT> ) ) ; } } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue RSFIN = DAG . getFrameIndex ( FuncInfo -> getRegSaveFrameIndex ( ) , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Offset = FuncInfo -> getVarArgsGPOffset ( ) ; for ( SDValue Val : LiveGPRs ) { SDValue FIN = DAG . getNode ( <STR_LIT> , DL , TargLowering . getPointerTy ( DAG . getDataLayout ( ) ) , RSFIN , DAG . getIntPtrConstant ( Offset , DL ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , DL , Val , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FuncInfo -> getRegSaveFrameIndex ( ) , Offset ) ) ; MemOps . push_back ( Store ) ; Offset += <NUM_LIT> ; } if ( ! LiveXMMRegs . empty ( ) ) { SmallVector < SDValue , <NUM_LIT> > SaveXMMOps ; SaveXMMOps . push_back ( Chain ) ; SaveXMMOps . push_back ( ALVal ) ; SaveXMMOps . push_back ( DAG . getIntPtrConstant ( FuncInfo -> getRegSaveFrameIndex ( ) , DL ) ) ; SaveXMMOps . push_back ( DAG . getIntPtrConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL ) ) ; SaveXMMOps . insert ( SaveXMMOps . end ( ) , LiveXMMRegs . begin ( ) , LiveXMMRegs . end ( ) ) ; MemOps . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SaveXMMOps ) ) ; } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOps ) ;


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( short ) ( MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ) ;


<s> MachineBasicBlock * <ISA_LIT>16TargetLowering :: emitFEXT_T8I816_ins ( unsigned BtOpc , unsigned CmpOpc , MachineInstr * MI , MachineBasicBlock * BB ) const { if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

unsigned regY = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * Mang -> getSymbol ( GV ) ; printOffset ( MO . getOffset ( ) , O ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ConstantPoolIndex : O << * GetCPISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << * GetJTISymbol ( MO . getIndex ( ) ) ; break ;


<s> std :: string Filename = llvm :: createGraphFilename ( file , FD ) ; raw_fd_ostream OS ( FD , true ) ; OS << <STR_LIT> << <STR_LIT> ; OS << <STR_LIT> ; OS << <STR_LIT> <STR_LIT> <STR_LIT> ; OS << CF . printTree ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; if ( DPRCSSize > <NUM_LIT> ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } NumBytes = DPRCSOffset ; if ( NumBytes ) { emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; if ( HasFP && is<ISA_LIT> ) AFI -> setShouldRestoreSPFromFP ( true ) ; } if ( STI . isTargetELF ( ) && hasFP ( MF ) ) MFI -> setOffsetAdjustment ( MFI -> getOffsetAdjustment ( ) - AFI -> getFramePtrSpillOffset ( ) ) ; AFI -> setGPRCalleeSavedArea1Size ( GPRCS1Size ) ; AFI -> setGPRCalleeSavedArea2Size ( GPRCS2Size ) ; AFI -> setDPRCalleeSavedAreaSize ( DPRCSSize ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) { unsigned MaxAlign = MFI -> getMaxAlignment ( ) ;

assert ( ! AFI -> isThumb1OnlyFunction ( ) ) ;


<s> cfun -> machine -> eh_stack_adjust = sa ; }

return cfun -> machine -> eh_stack_adjust ;


<s> if ( isALUInstr ( MI . getOpcode ( ) ) ) return true ; if ( isVector ( MI ) || isCubeOp ( MI . getOpcode ( ) ) ) return true ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; }


<s> return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { const auto & MF = DAG . getMachineFunction ( ) ; const auto * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned Reg = RegInfo -> getLocalAddressRegister ( MF ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , Op . getSimpleValueType ( ) ) ; } case <STR_LIT> : { SDValue FnOp = Op . getOperand ( <NUM_LIT> ) ; SDValue IncomingFPOp = Op . getOperand ( <NUM_LIT> ) ; GlobalAddressSDNode * GSD = dyn_cast < GlobalAddressSDNode > ( FnOp ) ; auto * Fn = dyn_cast_or_null < Function > ( GSD ? GSD -> getGlobal ( ) : nullptr ) ; if ( ! Fn ) report_fatal_error ( <STR_LIT> ) ; return IncomingFPOp ; }


<s> <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; }


<s> bool ret = rs6000_rtx_costs ( x , mode , outer_code , opno , total , speed ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( mode ) , GET_RTX_NAME ( outer_code ) , opno , * total , speed ? <STR_LIT> : <STR_LIT> ) ; debug_rtx ( x ) ;


<s> return __builtin_aarch64_urshlv4si_uus ( __a , __b ) ;


<s> static bool isVectorShift ( ShuffleVectorSDNode * SVOp , SelectionDAG & DAG , bool & isLeft , SDValue & ShVal , unsigned & ShAmt ) { if ( SVOp -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) > <NUM_LIT> ) return false ;

if ( isVectorShiftLeft ( SVOp , DAG , isLeft , ShVal , ShAmt ) || isVectorShiftRight ( SVOp , DAG , isLeft , ShVal , ShAmt ) ) return true ;


<s> case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformUINT_TO_FPCombine ( N , DAG ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFP_TO_SINTCombine ( N , DAG ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case GPRnopcRegClassID : case tGPR_and_tcGPRRegClassID : return getRegBank ( <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } llvm_unreachable ( <STR_LIT> ) ;


<s> if ( ! tryAddingSymbolicOperand ( Value , isBranch , Address , <NUM_LIT> , N / <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( Value ) ) ;


<s> if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } emitStackMaps ( SM ) ;


<s> rtl_opt_pass * make_pass_track_speculation ( gcc :: context * ctxt ) {

return new pass_track_speculation ( ctxt ) ;


<s> if ( ! isSysReg ( ) ) return false ; bool IsKnownRegister ; auto Mapper = <STR_LIT> ( getSysRegFeatureBits ( ) ) ;

Mapper . fromString ( getSysReg ( ) , IsKnownRegister ) ;


<s> return __builtin_ia32_mulph512_mask ( __B , __C , _mm512_setzero_ph ( ) , __A ) ;


<s> static rtx tilegx_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS cum = * get_cumulative_args ( cum_v ) ; int byte_size = ( ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ) ; bool doubleword_aligned_p ; if ( cum >= TILEGX_NUM_ARG_REGS ) return NULL_RTX ; doubleword_aligned_p = tilegx_function_arg_boundary ( mode , type ) > BITS_PER_WORD ;

if ( doubleword_aligned_p ) cum += cum & <NUM_LIT> ;


<s> bool <ISA_LIT>GOT :: isGOTFull ( ) const { uint64_t gotCount = <ISA_LIT>GOT0Num + m_MultipartList . back ( ) . m_LocalNum + m_MultipartList . back ( ) . m_GlobalNum ;


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = Op0 . getValueType ( ) ; if ( InVT . isVector ( ) && InVT . getScalarSizeInBits ( ) < <NUM_LIT> ) { SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; }

if ( DAG . SignBitIsZero ( Op0 ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 ) ;


<s> assert ( CE && <STR_LIT> ) ; int Imm = CE -> getValue ( ) ; bool isAdd = Imm >= <NUM_LIT> ; if ( Imm == INT32_MIN ) Imm = <NUM_LIT> ;

Imm = ( Imm < <NUM_LIT> ? - Imm : Imm ) | ( int ) isAdd << <NUM_LIT> ;


<s> Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_YB ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_YB ) ; } else { Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_BY ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_BY ) ; }


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> MachineBasicBlock :: iterator <ISA_LIT>InstrInfo :: loadImmediate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned Reg , uint64_t Value ) const { DebugLoc dl = MBB . findDebugLoc ( MI ) ;


<s> unsigned Opc = N -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return true ; if ( Opc == <STR_LIT> ) { if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return true ; } if ( Opc == <STR_LIT> ) { SDValue Addr = cast < LoadSDNode > ( N ) -> getBasePtr ( ) ; unsigned AddrOpc = Addr . getOpcode ( ) ; if ( AddrOpc == <STR_LIT> || AddrOpc == <STR_LIT> ) if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return true ; } return false ; } ; WorkQ . insert ( N ) ; for ( unsigned i = <NUM_LIT> ; i != WorkQ . size ( ) ; ++ i ) { SDNode * W = WorkQ [ i ] ; if ( IsNodeToSelect ( W ) ) Nodes . push_back ( W ) ; for ( unsigned j = <NUM_LIT> , f = W -> getNumOperands ( ) ; j != f ; ++ j ) WorkQ . insert ( W -> getOperand ( j ) . getNode ( ) ) ; }

for ( SDNode * L : Nodes ) ISel . Select ( L ) ;


<s> insn_op = & insn_data [ icode ] . operand [ arity + nonvoid ] ; op [ arity ] = expand_expr ( arg , NULL_RTX , insn_op -> mode , EXPAND_NORMAL ) ; if ( ! ( * insn_op -> predicate ) ( op [ arity ] , insn_op -> mode ) ) { if ( insn_op -> predicate == memory_operand ) { if ( op [ arity ] != const0_rtx ) op [ arity ] = copy_to_mode_reg ( Pmode , op [ arity ] ) ; op [ arity ] = gen_rtx_MEM ( insn_op -> mode , op [ arity ] ) ; } else op [ arity ] = copy_to_mode_reg ( insn_op -> mode , op [ arity ] ) ;


<s> uint64_t TruncMask = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( isMask_64 ( TruncMask ) && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) return false ; }


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( SaveLocation ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( SaveLocation ) ) ; }

getStreamer ( ) . EmitInstruction ( Inst , STI ) ;


<s> if ( startswith ( target_mcu , <STR_LIT> ) ) { snprintf ( mcu_name , sizeof ( mcu_name ) - <NUM_LIT> , <STR_LIT> , target_mcu + <NUM_LIT> ) ; start_upper = <NUM_LIT> ; } else { snprintf ( mcu_name , sizeof ( mcu_name ) - <NUM_LIT> , <STR_LIT> , target_mcu ) ; start_upper = <NUM_LIT> ; } end_upper = strlen ( mcu_name ) - <NUM_LIT> ;

for ( i = start_upper ; i < end_upper ; i ++ ) mcu_name [ i ] = TOUPPER ( mcu_name [ i ] ) ;


<s> clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ;

emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , op , clob ) ) ) ;


<s> return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCLUIImm : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm7Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb00 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm8Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm9Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm9Lsb000 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm10Lsb00NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm10Lsb0000NonZero : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm12 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm12Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidSImm13Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidUImm20LUI : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidUImm20AUIPC : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> ) ; case Match_InvalidSImm21Lsb0JAL : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ; case Match_InvalidCSRSystemRegister : { return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; } case Match_InvalidFenceArg : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ;


<s> MCSym = MBB -> getSymbol ( ) ; } else if ( CCPV -> isJT ( ) ) { signed JTI = cast < <ISA_LIT>ConstantPoolJT > ( CCPV ) -> getJTI ( ) ; MCSym = GetJTISymbol ( JTI ) ; } else { assert ( CCPV -> isExtSymbol ( ) && <STR_LIT> ) ; StringRef Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( CCPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( MCSym , MCSymbolRefExpr :: VK_None , OutContext ) ; if ( CCPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = OutContext . getOrCreateSymbol ( Twine ( MAI -> getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CCPV -> getLabelID ( ) ) ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: create ( PCLabel , OutContext ) ; if ( CCPV -> mustAddCurrentAddress ( ) ) {

MCSymbol * DotSym = OutContext . createTempSymbol ( ) ;


<s> int sval = ( int ) ( ( val << <NUM_LIT> ) >> <NUM_LIT> ) ; Imm = ( short ) val ; return val == sval ; }


<s> CONSTEXPR svmatch_svnmatch_impl ( int unspec ) : m_unspec ( unspec ) {


<s> assert ( F != Map . end ( ) ) ; return F - Map . begin ( ) ;


<s> for ( i = probe_interval ; i < size ; i += probe_interval ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { gcc_assert ( int_registers_saved ) ; HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , probe_interval ) ; emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ; last = first + rounded_size ; emit_insn ( gen_probe_stack_range ( Pmode , sr . reg , sr . reg , GEN_INT ( - last ) ) ) ;

if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) , rounded_size - size ) ) ;


<s> report_fatal_error ( <STR_LIT> ) ; return SDValue ( ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; LPCC :: CondCode CC = IntCondCCodeToICC ( Cond , DL , RHS , DAG ) ; SDValue TargetCC = DAG . getConstant ( CC , DL , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , TargetCC ) ;

SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> SignBit64 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , SignBit64 ) ; SDValue BcInt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; const SDValue FractMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << FractBits ) - <NUM_LIT> , <STR_LIT> ) ; SDValue Shr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , FractMask , Exp ) ; SDValue Not = DAG . getNOT ( SL , Shr , <STR_LIT> ) ; SDValue Tmp0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BcInt , Not ) ; EVT SetCCVT = getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) ; const SDValue FiftyOne = DAG . getConstant ( FractBits - <NUM_LIT> , <STR_LIT> ) ; SDValue ExpLt0 = DAG . getSetCC ( SL , SetCCVT , Exp , Zero , <STR_LIT> ) ;

SDValue ExpGt51 = DAG . getSetCC ( SL , SetCCVT , Exp , FiftyOne , <STR_LIT> ) ;


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ;

else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt ( CI , VT , VT != <STR_LIT> ) ;


<s> if ( F . hasFnAttribute ( <STR_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; } Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> if ( ! ATReg ) return true ; bool LoadedOffsetInAT = false ; if ( ! isInt < <NUM_LIT> > ( OffsetValue + <NUM_LIT> ) || ! isInt < <NUM_LIT> > ( OffsetValue ) ) { LoadedOffsetInAT = true ; if ( loadImmediate ( OffsetValue , ATReg , <STR_LIT> , ! ABI . ArePtrs64bit ( ) , true , IDLoc , Instructions ) ) return true ; if ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> ) createAddu ( ATReg , ATReg , SrcReg , ABI . ArePtrs64bit ( ) , Instructions ) ; } unsigned FirstLbuDstReg = LoadedOffsetInAT ? DstReg : ATReg ; unsigned SecondLbuDstReg = LoadedOffsetInAT ? ATReg : DstReg ; unsigned LbuSrcReg = LoadedOffsetInAT ? ATReg : SrcReg ;

int64_t FirstLbuOffset = <NUM_LIT> , SecondLbuOffset = <NUM_LIT> ;


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( IdVal ) ; assert ( MCE && <STR_LIT> ) ; int64_t Val = MCE -> getValue ( ) ;

SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( dg ) ) ;


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> TempTracker . getUpwardPressure ( SU -> getInstr ( ) , Pressure , MaxPressure ) ; } int NewSGPRPressure = Pressure [ SRI -> getSGPRPressureSet ( ) ] ; int NewVGPRPressure = Pressure [ SRI -> getVGPRPressureSet ( ) ] ; const int MaxVGPRPressureInc = <NUM_LIT> ; bool ShouldTrackVGPRs = VGPRPressure + MaxVGPRPressureInc >= VGPRExcessLimit ; bool ShouldTrackSGPRs = ! ShouldTrackVGPRs && SGPRPressure >= SGPRExcessLimit ; const int ErrorMargin = <NUM_LIT> ; VGPRExcessLimit -= ErrorMargin ; SGPRExcessLimit -= ErrorMargin ; if ( ShouldTrackVGPRs && NewVGPRPressure >= VGPRExcessLimit ) { Cand . RPDelta . Excess = PressureChange ( SRI -> getVGPRPressureSet ( ) ) ; Cand . RPDelta . Excess . setUnitInc ( NewVGPRPressure - VGPRExcessLimit ) ; }

if ( ShouldTrackSGPRs && NewSGPRPressure >= SGPRExcessLimit ) {


<s> return ( uint64x2_t ) __builtin_neon_vpaddluv4si ( ( int32x4_t ) __a ) ;


<s> if ( ResultReg == <NUM_LIT> ) return false ; ResultReg = FastEmitZExtFromI1 ( <STR_LIT> , ResultReg , false ) ; if ( ResultReg == <NUM_LIT> ) return false ; if ( DstVT != <STR_LIT> ) {

ResultReg = FastEmit_r ( <STR_LIT> , DstVT . getSimpleVT ( ) , <STR_LIT> , ResultReg , true ) ;


<s> float32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> if ( Subtarget . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_SaveList ; return CSR_Interrupt_SaveList ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ;


<s> MachineOperand & Dest = Inst . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst . getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( <STR_LIT> ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & <STR_LIT> ; unsigned MidReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , <STR_LIT> ) ;

MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , <STR_LIT> , SrcSubRC ) ;


<s> Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; isAdd = false ; MCFixupKind Kind ; if ( isThumb2 ( STI ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { Reg = <STR_LIT> ; int32_t Offset = MO . getImm ( ) ; if ( Offset == INT32_MIN ) { Offset = <NUM_LIT> ; isAdd = false ; } else if ( Offset < <NUM_LIT> ) { Offset *= - <NUM_LIT> ; isAdd = false ; } Imm12 = Offset ; } } else isAdd = EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm12 , Fixups , STI ) ; uint32_t Binary = Imm12 & <NUM_LIT> ; if ( isAdd ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ;


<s> thumb1_const_rtl ( rtx dst ) : dst ( dst ) {


<s> SmallVector < std :: pair < unsigned , MDNode * > , <NUM_LIT> > MD ; I . getAllMetadataOtherThanDebugLoc ( MD ) ; for ( unsigned i = <NUM_LIT> , e = MD . size ( ) ; i != e ; ++ i ) { Load -> setMetadata ( MD [ i ] . first , MD [ i ] . second ) ; }

Value * BitCastLoad = Builder . CreateBitCast ( Load , I . getType ( ) ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ;

SDValue Dest = Op . getOperand ( <NUM_LIT> ) ;


<s> return __builtin_loongson_pinsrh_1_u ( s , t ) ;


<s> SmallVectorImpl < ForwardedRegister > & getForwardedMustTailRegParms ( ) { return ForwardedMustTailRegParms ;


<s> EltTy = IntegerType :: getIntNTy ( EltTy -> getContext ( ) , EltTyBits ) ; auto bailout = [ & ] ( ) { return BaseT :: getReplicationShuffleCost ( EltTy , ReplicationFactor , VF , DemandedDstElts , CostKind ) ; } ; if ( ! ST -> hasAVX512 ( ) ) return bailout ( ) ; unsigned PromEltTyBits = EltTyBits ; switch ( EltTyBits ) { case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : if ( ! ST -> hasBWI ( ) ) PromEltTyBits = <NUM_LIT> ; break ; case <NUM_LIT> : if ( ! ST -> hasVBMI ( ) ) PromEltTyBits = <NUM_LIT> ; break ; case <NUM_LIT> : if ( ST -> hasBWI ( ) ) { if ( ST -> hasVBMI ( ) ) PromEltTyBits = <NUM_LIT> ; else PromEltTyBits = <NUM_LIT> ; break ; } return bailout ( ) ; default : return bailout ( ) ; } auto * PromEltTy = IntegerType :: getIntNTy ( EltTy -> getContext ( ) , PromEltTyBits ) ; auto * SrcVecTy = FixedVectorType :: get ( EltTy , VF ) ; auto * PromSrcVecTy = FixedVectorType :: get ( PromEltTy , VF ) ; int NumDstElements = VF * ReplicationFactor ; auto * PromDstVecTy = FixedVectorType :: get ( PromEltTy , NumDstElements ) ; auto * DstVecTy = FixedVectorType :: get ( EltTy , NumDstElements ) ; MVT LegalSrcVecTy = TLI -> getTypeLegalizationCost ( DL , SrcVecTy ) . second ; MVT LegalPromSrcVecTy = TLI -> getTypeLegalizationCost ( DL , PromSrcVecTy ) . second ; MVT LegalPromDstVecTy = TLI -> getTypeLegalizationCost ( DL , PromDstVecTy ) . second ; MVT LegalDstVecTy = TLI -> getTypeLegalizationCost ( DL , DstVecTy ) . second ; if ( ! LegalSrcVecTy . isVector ( ) || ! LegalPromSrcVecTy . isVector ( ) || ! LegalPromDstVecTy . isVector ( ) || ! LegalDstVecTy . isVector ( ) ) return bailout ( ) ; if ( PromEltTyBits != EltTyBits ) { InstructionCost PromotionCost ; PromotionCost += getCastInstrCost ( Instruction :: SExt , PromSrcVecTy , SrcVecTy , TargetTransformInfo :: CastContextHint :: None , CostKind ) ; PromotionCost += getCastInstrCost ( Instruction :: Trunc , DstVecTy , PromDstVecTy , TargetTransformInfo :: CastContextHint :: None , CostKind ) ; return PromotionCost + getReplicationShuffleCost ( PromEltTy , ReplicationFactor , VF , DemandedDstElts , CostKind ) ;


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , <NUM_LIT> ) ;

MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseMemBarrierOptOperand ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; unsigned Opt ; if ( Tok . is ( AsmToken :: Identifier ) ) { StringRef OptStr = Tok . getString ( ) ; Opt = StringSwitch < unsigned > ( OptStr . slice ( <NUM_LIT> , OptStr . size ( ) ) . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( ! hasV8Ops ( ) && ( Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> || Opt == <STR_LIT> ) ) Opt = ~ <NUM_LIT> ; if ( Opt == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * MemBarrierID ; if ( getParser ( ) . parseExpression ( MemBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( MemBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val & ~ <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; }


<s> inline void classify_registers ( const_tree , int bitpos , bool fp , classify_data_t * data ) { if ( fp ) { data -> fp_regs = true ;

if ( bitpos < BITS_PER_WORD ) data -> fp_regs_in_first_word = true ;


<s> bool spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const override {


<s> return MFI . isFrameAddressTaken ( ) || MFI . hasVarSizedObjects ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ;


<s> step = all ; infp -> growth [ growths ++ ] = step ; infp -> local_growth = growths ; all -= step ; gcc_assert ( all == <NUM_LIT> ) ; if ( outbounds ) infp -> growth [ growths ++ ] = outbounds ; goto finish ; } if ( ( regarg % STACK_BYTES ) == <NUM_LIT> ) { infp -> growth [ growths ++ ] = regarg ; infp -> reg_growth = growths ; infp -> arg_offset = regarg - <NUM_LIT> ; infp -> reg_offset = <NUM_LIT> ; if ( infp -> local_size % STACK_BYTES ) infp -> pad_local = STACK_BYTES - ( infp -> local_size % STACK_BYTES ) ; step = infp -> local_size + infp -> pad_local ; if ( ! frame_pointer_needed ) { step += outbounds ; outbounds = <NUM_LIT> ; } infp -> growth [ growths ++ ] = step ; infp -> local_growth = growths ; if ( outbounds ) infp -> growth [ growths ++ ] = outbounds ; goto finish ; } if ( regarg % STACK_BYTES != <NUM_LIT> ) infp -> pad_reg = STACK_BYTES - ( regarg % STACK_BYTES ) ; infp -> growth [ growths ++ ] = infp -> arg_size + infp -> reg_size + infp -> pad_reg ; infp -> reg_growth = growths ; infp -> arg_offset = infp -> growth [ <NUM_LIT> ] - <NUM_LIT> ; infp -> reg_offset = <NUM_LIT> ; if ( frame_pointer_needed ) { if ( infp -> local_size % STACK_BYTES != <NUM_LIT> ) infp -> pad_local = STACK_BYTES - ( infp -> local_size % STACK_BYTES ) ; infp -> growth [ growths ++ ] = infp -> local_size + infp -> pad_local ; infp -> local_growth = growths ; infp -> growth [ growths ++ ] = outbounds ; }


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> continue ; } } MachineInstr * MI = NULL ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; }


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { if ( getKind ( ) != VK_NONE ) OS << getVariantKindName ( ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseFGR64Regs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) {

if ( ! isFP64 ( ) ) return MatchOperand_NoMatch ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getGSVectorCost ( unsigned Opcode , Type * SrcVTy , const Value * Ptr , Align Alignment , unsigned AddressSpace ) { assert ( isa < VectorType > ( SrcVTy ) && <STR_LIT> ) ; unsigned VF = cast < FixedVectorType > ( SrcVTy ) -> getNumElements ( ) ; auto getIndexSizeInBits = [ ] ( const Value * Ptr , const DataLayout & DL ) { unsigned IndexSize = DL . getPointerSizeInBits ( ) ; const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; if ( IndexSize < <NUM_LIT> || ! GEP ) return IndexSize ; unsigned NumOfVarIndices = <NUM_LIT> ; const Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( auto * IndexVTy = dyn_cast < VectorType > ( IndxTy ) ) IndxTy = IndexVTy -> getElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( ST -> hasAVX512 ( ) && VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ; auto * IndexVTy = FixedVectorType :: get ( IntegerType :: get ( SrcVTy -> getContext ( ) , IndexSize ) , VF ) ;

std :: pair < InstructionCost , MVT > IdxsLT = TLI -> getTypeLegalizationCost ( DL , IndexVTy ) ;


<s> case GK_GFX700 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX700 ; case GK_GFX701 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX701 ; case GK_GFX702 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX702 ; case GK_GFX703 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX703 ; case GK_GFX704 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX704 ; case GK_GFX801 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX801 ; case GK_GFX802 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX802 ; case GK_GFX803 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX803 ; case GK_GFX810 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX810 ; case GK_GFX900 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX900 ; case GK_GFX902 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX902 ; case GK_GFX904 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX904 ; case GK_GFX906 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX906 ; case GK_GFX908 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX908 ; case GK_GFX909 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX909 ; case GK_GFX1010 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1010 ; case GK_GFX1011 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1011 ;

case GK_GFX1012 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1012 ;


<s> Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ;


<s> uint32_t v = CN -> getZExtValue ( ) ; if ( v && ! ( v & ( v - <NUM_LIT> ) ) ) { int bit = <NUM_LIT> - __builtin_clz ( v ) ; imm = CurDAG -> getTargetConstant ( bit , <STR_LIT> ) ; return true ; } }


<s> void arm_lang_object_attributes_init ( void ) {


<s> const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register FIReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( <STR_LIT> ) , FIReg ) . addFrameIndex ( FrameIdx ) ; TII -> getAddNoCarry ( * MBB , Ins , DL , BaseReg ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( FIReg ) . addImm ( <NUM_LIT> ) ;


<s> BuildMI ( MBB , Insert , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , Insert , DL , TII -> get ( <STR_LIT> ) ) ;


<s> static bool matchRegisterNameHelper ( MCRegister & RegNo , StringRef Name ) { RegNo = MatchRegisterName ( Name ) ; if ( RegNo == <STR_LIT> ) RegNo = MatchRegisterAltName ( Name ) ;


<s> return new <ISA_LIT>Disassembler ( STI , T . createMCRegInfo ( <STR_LIT> ) , true ) ;


<s> IncomingArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI ) : ValueHandler ( MIRBuilder , MRI ) {


<s> if ( TARGET_SVE && known_eq ( nbytes , BYTES_PER_SVE_VECTOR ) ) { unsigned int elem_nbytes = vector_element_size ( nbytes , nunits ) ;


<s> case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; default :


<s> static rtx tilegx_got_rtx ( void ) {


<s> const TargetRegisterClass * getRegClass ( const MCInstrDesc & TID , unsigned OpNum , const TargetRegisterInfo * TRI , const MachineFunction & MF ) const override { if ( OpNum >= TID . getNumOperands ( ) ) return nullptr ; return RI . getRegClass ( TID . OpInfo [ OpNum ] . RegClass ) ;


<s> if ( mSTM -> device ( ) -> getGeneration ( ) == <STR_LIT> && ( mSTM -> getDeviceName ( ) == <STR_LIT> ) ) { return false ; }

return CI -> getOperand ( CI -> getNumOperands ( ) - <NUM_LIT> ) -> getName ( ) . substr ( <NUM_LIT> , <NUM_LIT> ) == <STR_LIT> ;


<s> void <ISA_LIT>Relocator :: scanRelocation ( Relocation & pReloc , IRBuilder & pBuilder , Module & pModule , LDSection & pSection , Input & pInput ) { ResolveInfo * rsym = pReloc . symInfo ( ) ; assert ( rsym != NULL && <STR_LIT> ) ; assert ( pSection . getLink ( ) != NULL ) ; if ( ( pSection . getLink ( ) -> flag ( ) & llvm :: ELF :: SHF_ALLOC ) == <NUM_LIT> ) return ;

if ( rsym -> isLocal ( ) ) scanLocalReloc ( pReloc , pSection ) ;


<s> if ( EnableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ;


<s> void VarArgsLoweringHelper :: lowerVarArgsParameters ( SDValue & Chain , unsigned StackSize ) { FuncInfo -> setVarArgsFrameIndex ( <NUM_LIT> ) ; FuncInfo -> setRegSaveFrameIndex ( <NUM_LIT> ) ;

if ( FrameInfo . hasVAStart ( ) ) createVarArgAreaAndStoreRegisters ( Chain , StackSize ) ;


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> static const uint16_t Opc [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; assert ( CC < <NUM_LIT> && <STR_LIT> ) ; unsigned Idx = HasMemoryOperand ? <NUM_LIT> + CC : CC ; switch ( RegBytes ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return Opc [ Idx ] [ <NUM_LIT> ] ; case <NUM_LIT> : return Opc [ Idx ] [ <NUM_LIT> ] ; case <NUM_LIT> : return Opc [ Idx ] [ <NUM_LIT> ] ;


<s> unsigned regIdx = <NUM_LIT> ; switch ( Op -> Reg . Kind ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case rk_FloatReg : regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return nullptr ; Reg = QuadFPRegs [ regIdx / <NUM_LIT> ] ; break ; case rk_DoubleReg : regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return nullptr ; Reg = QuadFPRegs [ regIdx / <NUM_LIT> ] ; break ;


<s> SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDNode * OpNode = Op . getNode ( ) ;

EVT SVT = OpNode -> getValueType ( <NUM_LIT> ) ;


<s> InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; case <NUM_LIT> : EltLog2Size = <NUM_LIT> ; InsertOp = <STR_LIT> ; InsveOp = <STR_LIT> ; VecRC = & <STR_LIT> ; break ; } if ( IsFP ) { unsigned Wt = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( EltSizeInBytes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; SrcValReg = Wt ; } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg ) ; unsigned WdTmp2 = RegInfo . createVirtualRegister ( VecRC ) ; if ( IsFP ) { BuildMI ( * BB , MI , DL , TII -> get ( InsveOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ;


<s> DecodeStatus Result = decodeUImmOperand < <NUM_LIT> > ( Inst , UImm6 , Address , Decoder ) ; ( void ) Result ; assert ( Result == MCDisassembler :: Success && <STR_LIT> ) ; return MCDisassembler :: Success ;


<s> bool isReg ( ) const override { return Kind == k_Register && ! Reg . isVector ;


<s> MachineInstr * ConstMI = nullptr ; for ( MachineInstr & MI : MF . front ( ) ) { if ( MI . getOpcode ( ) == <STR_LIT> && SS == MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ) { ConstMI = & MI ; break ; } ++ ConstPos ; } assert ( ConstMI && <STR_LIT> ) ; unsigned AMXRegNum = TRI -> getRegClass ( <STR_LIT> ) -> getNumRegs ( ) ; SmallVector < Register , <NUM_LIT> > Phys2Virt ( AMXRegNum , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I != E ; ++ I ) { Register VirtReg = Register :: index2VirtReg ( I ) ; if ( MRI . reg_nodbg_empty ( VirtReg ) ) continue ; if ( MRI . getRegClass ( VirtReg ) -> getID ( ) != <STR_LIT> ) continue ; unsigned Index = VRM . getPhys ( VirtReg ) - <STR_LIT> ; if ( ! Phys2Virt [ Index ] ) Phys2Virt [ Index ] = VirtReg ; } for ( unsigned I = <NUM_LIT> ; I < AMXRegNum ; ++ I ) { if ( ! Phys2Virt [ I ] ) continue ; DebugLoc DL ; bool IsRow = true ; MachineInstr * NewMI = nullptr ; ShapeT Shape = VRM . getShape ( Phys2Virt [ I ] ) ; for ( auto & R : { Shape . getRow ( ) -> getReg ( ) , Shape . getCol ( ) -> getReg ( ) } ) { int64_t Imm = INT64_MAX ; int Offset = IsRow ? <NUM_LIT> + I : <NUM_LIT> + I * <NUM_LIT> ; for ( auto & DefMI : MRI . def_instructions ( R ) ) { MachineBasicBlock & MBB = * DefMI . getParent ( ) ; if ( DefMI . isMoveImmediate ( ) ) { if ( Imm != INT64_MAX ) { assert ( Imm == DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) && <STR_LIT> ) ; continue ;


<s> } Opc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { Opc = <STR_LIT> ; } else { assert ( RC == <STR_LIT> && <STR_LIT> ) ; Opc = <STR_LIT> ; } MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; AddDefaultPred ( MIB ) ;


<s> SDValue <ISA_LIT>TargetLowering :: buildVector32 ( ArrayRef < SDValue > Elem , const SDLoc & dl , MVT VecTy , SelectionDAG & DAG ) const { MVT ElemTy = VecTy . getVectorElementType ( ) ; assert ( VecTy . getVectorNumElements ( ) == Elem . size ( ) ) ; SmallVector < ConstantInt * , <NUM_LIT> > Consts ( Elem . size ( ) ) ; bool AllConst = getBuildVectorConstInts ( Elem , VecTy , DAG , Consts ) ; unsigned First , Num = Elem . size ( ) ; for ( First = <NUM_LIT> ; First != Num ; ++ First ) if ( ! isUndef ( Elem [ First ] ) ) break ; if ( First == Num ) return DAG . getUNDEF ( VecTy ) ; if ( AllConst && llvm :: all_of ( Consts , [ ] ( ConstantInt * CI ) { return CI -> isZero ( ) ; } ) ) return getZero ( dl , VecTy , DAG ) ; if ( ElemTy == <STR_LIT> ) { assert ( Elem . size ( ) == <NUM_LIT> ) ; if ( AllConst ) { uint32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; }

SDValue N = getInstr ( <STR_LIT> , dl , <STR_LIT> , { Elem [ <NUM_LIT> ] , Elem [ <NUM_LIT> ] } , DAG ) ;


<s> frag -> setOffset ( offset ) ; offset += frag -> size ( ) ; } if ( ! m_GOTPLT . empty ( ) ) { m_pGOTPLTFront = m_GOTPLT . front ( ) ; entry_iterator it , end = m_GOTPLT . end ( ) ; for ( it = m_GOTPLT . begin ( ) ; it != end ; ++ it ) { <ISA_LIT>GOTEntry * entry = * it ; frag_list . push_back ( entry ) ; entry -> setParent ( m_SectionData ) ; entry -> setOffset ( offset ) ; offset += entry -> size ( ) ; } } m_GOTPLT . clear ( ) ; if ( ! m_GOT . empty ( ) ) { m_pGOTFront = m_GOT . front ( ) ;

entry_iterator it , end = m_GOT . end ( ) ;


<s> RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> ) ;

RegisterTarget < Triple :: riscv64 > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> if ( LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( ( ! FullFP16 && LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) || LHS . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ;


<s> bool <ISA_LIT>ParallelDSP :: RecordSequentialLoads ( BasicBlock * BB ) { SmallVector < LoadInst * , <NUM_LIT> > Loads ; for ( auto & I : * BB ) { auto * Ld = dyn_cast < LoadInst > ( & I ) ; if ( ! Ld || ! Ld -> isSimple ( ) || ! Ld -> hasOneUse ( ) || ! isa < SExtInst > ( Ld -> user_back ( ) ) ) continue ; Loads . push_back ( Ld ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMImm ( const MCExpr * Val , bool Flag , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_MImmOp ) ;


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ;

TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBase ( ) ) ) ; const MCExpr * Expr = getMemOff ( ) ;


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>2 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>3 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( <ISA_LIT>ABI != UnknownABI ) ; assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ;

UseSmallSection = ! IsLinux && ( RM == Reloc :: Static ) ;


<s> if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; } if ( FP16 ) Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , SDLoc ( N ) , <STR_LIT> ) ; else Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } Base = N ; if ( FP16 ) Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; else Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg ) ; MIB . setMemRefs ( SetCCI . memoperands ( ) ) ;


<s> bool <ISA_LIT>AsmParser :: parseParenSuffix ( StringRef Name , OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) , * this ) ) ;


<s> if ( Size + sizeof ( T ) > Bytes . size ( ) ) return false ; T Val ; memcpy ( & Val , Bytes . data ( ) + Size , sizeof ( T ) ) ; <STR_LIT> :: byte_swap < T , <STR_LIT> :: little > ( Val ) ; Size += sizeof ( T ) ;

MI . addOperand ( MCOperand :: createFPImm ( static_cast < double > ( Val ) ) ) ;


<s> if ( TT . isArm64e ( ) ) CPU = <STR_LIT> ; } return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ;


<s> const <ISA_LIT>TargetMachine & getTargetMachine ( ) const {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> return true ; } const uint32_t nopEncoding = hasNOP ( ) ? <ISA_LIT>v6T2_NopEncoding : <ISA_LIT>v4_NopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % <NUM_LIT> ) { default : break ; case <NUM_LIT> : OW -> Write8 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; OW -> Write8 ( <NUM_LIT> ) ; break ; } return true ;


<s> if ( regno == FLG_REGNO ) fprintf ( s , <STR_LIT> ) ; else fprintf ( s , <STR_LIT> , <STR_LIT> [ reg_push_size ( regno ) ] , reg_names [ regno ] ) ;


<s> int live_regs_mask = <NUM_LIT> ; * count = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg < FIRST_PSEUDO_REGISTER ; reg ++ ) { if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) { ( * count ) ++ ;

live_regs_mask |= ( <NUM_LIT> << reg ) ;


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned PCAdj = IsPositionIndependent ? ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( IsPositionIndependent ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; }


<s> sgx_returnsite_magic_index_public ++ ; return <STR_LIT> + std :: to_string ( sgx_returnsite_magic_index_public - <NUM_LIT> ) ;


<s> static bool isReassocCandidate ( const MachineInstr & Inst , bool & Commuted ) { if ( isAssociativeAndCommutative ( Inst . getOpcode ( ) ) && hasVirtualRegDefsInBasicBlock ( Inst , Inst . getParent ( ) ) && hasReassocSibling ( Inst , Commuted ) ) return true ; return false ;


<s> for ( unsigned i = <NUM_LIT> ; i < bytes ; i ++ ) { OS . write ( ( uint8_t ) ( ( Encoding >> ( <NUM_LIT> * i ) ) & <NUM_LIT> ) ) ; }


<s> static struct register_pass_info f = { p , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_AFTER } ;


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ; int Cost = getMemoryOpCost ( Opcode , VecTy , MaybeAlign ( Alignment ) , AddressSpace ) ; Cost += Factor * ( LT . first - <NUM_LIT> ) ;


<s> Value * PassThru = ConstantAggregateZero :: get ( Ty ) ; Value * IndexBase ; if ( match ( Index , m_Intrinsic < <STR_LIT> > ( m_Value ( IndexBase ) , m_SpecificInt ( <NUM_LIT> ) ) ) ) { IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ; Align Alignment = BasePtr -> getPointerAlignment ( II . getModule ( ) -> getDataLayout ( ) ) ; Type * VecPtrTy = PointerType :: getUnqual ( Ty ) ; Value * Ptr = Builder . CreateGEP ( cast < VectorType > ( Ty ) -> getElementType ( ) , BasePtr , IndexBase ) ; Ptr = Builder . CreateBitCast ( Ptr , VecPtrTy ) ; CallInst * MaskedLoad = Builder . CreateMaskedLoad ( Ty , Ptr , Alignment , Mask , PassThru ) ; MaskedLoad -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , MaskedLoad ) ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override {

return & InstrInfo . getRegisterInfo ( ) ;


<s> fprintf ( stream , <STR_LIT> , reg_names [ MMIX_OUTPUT_REGNO ( regno ) ] , reg_names [ MMIX_STACK_POINTER_REGNUM ] , reg_names [ MMIX_STACK_POINTER_REGNUM ] ) ;


<s> if ( ! loongarch_canonicalize_int_order_test ( & inv_code , & cmp1 , mode ) ) { cmp1 = force_reg ( mode , cmp1 ) ; loongarch_emit_int_order_test ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == <NUM_LIT> ) { rtx inv_target ;


<s> unsigned getNumVGPRBlocks ( const MCSubtargetInfo * STI , unsigned NumVGPRs ) { NumVGPRs = alignTo ( std :: max ( <NUM_LIT> , NumVGPRs ) , getVGPREncodingGranule ( STI ) ) ; return NumVGPRs / getVGPREncodingGranule ( STI ) - <NUM_LIT> ;


<s> return ( int32x2_t ) __builtin_neon_vrsubhnv2di ( __a , __b ) ;


<s> reg = gen_reg_rtx ( CCmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , gen_rtx_fmt_ee ( test_code == NE ? EQ : test_code , CCmode , cmp0 , cmp1 ) ) ) ; test_code = test_code == NE ? EQ : NE ; mode = CCmode ; cmp0 = reg ; cmp1 = const0_rtx ; invert = <NUM_LIT> ; break ; default : abort_with_insn ( gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0 , cmp1 ) , <STR_LIT> ) ; } label1 = gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) ; label2 = pc_rtx ; if ( invert ) { label2 = label1 ; label1 = pc_rtx ; }

emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( test_code , mode , cmp0 , cmp1 ) , label1 , label2 ) ) ) ;


<s> unsigned Alignment = std :: min ( ByValAlign , ( unsigned ) <NUM_LIT> ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; if ( ! isLittle ) LoadVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadVal , DAG . getConstant ( <NUM_LIT> - LoadSize * <NUM_LIT> , <STR_LIT> ) ) ; Offset += LoadSize ; RemainingSize -= LoadSize ; if ( RemainingSize != <NUM_LIT> ) { assert ( RemainingSize == <NUM_LIT> && <STR_LIT> ) ; LoadPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( Offset , <STR_LIT> ) ) ; unsigned Alignment = std :: min ( ByValAlign , ( unsigned ) <NUM_LIT> ) ; SDValue Subword = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> , false , false , Alignment ) ; MemOpChains . push_back ( Subword . getValue ( <NUM_LIT> ) ) ; unsigned ShiftAmt = isLittle ? <NUM_LIT> : <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Subword , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ; LoadVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadVal , Shift ) ; } unsigned DstReg = O32IntRegs [ LocMemOffset / <NUM_LIT> ] ; RegsToPass . push_back ( std :: make_pair ( DstReg , LoadVal ) ) ; return ; } SDValue Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( Offset , <STR_LIT> ) ) ; LastFI = MFI -> CreateFixedObject ( RemainingSize , LocMemOffset , true ) ;

SDValue Dst = DAG . getFrameIndex ( LastFI , PtrType ) ;


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . OffsetRegNum ) return false ;

if ( ! Memory . OffsetImm ) return true ;


<s> switch ( Kind ) { case Immediate : getImm ( ) -> print ( OS ) ; break ; case Register : OS << <STR_LIT> ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( getReg ( ) ) << <STR_LIT> ; break ;


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , false , true , true ) ;


<s> if ( info -> first_fp_reg_save < <NUM_LIT> && ! TARGET_MACHO && ! TARGET_ELF ) { char * name ; int regno = info -> first_fp_reg_save - <NUM_LIT> ; if ( ( info -> savres_strategy & SAVE_INLINE_FPRS ) == <NUM_LIT> ) { bool lr = ( info -> savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR ) != <NUM_LIT> ; int sel = SAVRES_SAVE | SAVRES_FPR | ( lr ? SAVRES_LR : <NUM_LIT> ) ; name = rs6000_savres_routine_name ( info , regno , sel ) ; fprintf ( file , <STR_LIT> , name ) ;


<s> mask = rs6000_emit_vector_compare_inner ( rcode , op0 , op1 ) ; if ( mask ) return mask ; switch ( rcode ) { case LT : rcode = GT ; swap_operands = true ; try_again = true ; break ; case LTU : rcode = GTU ; swap_operands = true ; try_again = true ; break ; case NE : case UNLE : case UNLT : case UNGE : case UNGT : { enum rtx_code rev_code ; enum insn_code nor_code ; rtx mask2 ; rev_code = reverse_condition_maybe_unordered ( rcode ) ; if ( rev_code == UNKNOWN ) return NULL_RTX ; nor_code = optab_handler ( one_cmpl_optab , dmode ) ; if ( nor_code == CODE_FOR_nothing ) return NULL_RTX ; mask2 = rs6000_emit_vector_compare ( rev_code , op0 , op1 , dmode ) ; if ( ! mask2 ) return NULL_RTX ; mask = gen_reg_rtx ( dmode ) ; emit_insn ( GEN_FCN ( nor_code ) ( mask , mask2 ) ) ; return mask ; } break ; case GE : case GEU : case LE : case LEU : { rtx c_rtx , eq_rtx ; enum insn_code ior_code ; enum rtx_code new_code ; switch ( rcode ) { case GE : new_code = GT ; break ; case GEU : new_code = GTU ; break ; case LE : new_code = LT ; break ; case LEU : new_code = LTU ; break ; default : gcc_unreachable ( ) ; } ior_code = optab_handler ( ior_optab , dmode ) ; if ( ior_code == CODE_FOR_nothing ) return NULL_RTX ; c_rtx = rs6000_emit_vector_compare ( new_code , op0 , op1 , dmode ) ;


<s> } for ( unsigned j = <NUM_LIT> ; j < VecElems / <NUM_LIT> ; j ++ ) for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i + j * <NUM_LIT> ] = Builder . CreateShuffleVector ( InVec [ j * <NUM_LIT> + i ] , InVec [ j * <NUM_LIT> + i + <NUM_LIT> ] , makeArrayRef ( Concat , <NUM_LIT> ) ) ; if ( VecElems == <NUM_LIT> ) return ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = Builder . CreateShuffleVector ( Vec [ i ] , Vec [ i + <NUM_LIT> ] , Concat ) ; return ;


<s> return MO . getReg ( ) == <STR_LIT> && MO . isImplicit ( ) && isVALU ( * MO . getParent ( ) ) && ! readsExecAsData ( * MO . getParent ( ) ) ;


<s> DebugLoc DL = CI . I -> getDebugLoc ( ) ; const unsigned Opcode = getNewOpcode ( CI ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI ) ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; unsigned MergedOffset = std :: min ( CI . Offset0 , CI . Offset1 ) ; auto MIB = BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) , DestReg ) ; const unsigned Regs = getRegs ( Opcode ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC0 ) . addImm ( CI . SLC0 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Dest1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: vdata ) ;

BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ;


<s> if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) , * this , OptLevel , true ) ) ; } return false ;


<s> StringRef getDimName ( Dim dim ) { switch ( dim ) {

CASE_SUF ( Dim , DIM , <NUM_LIT> ) CASE_SUF ( Dim , DIM , <NUM_LIT> ) CASE_SUF ( Dim , DIM , <NUM_LIT> ) CASE_SUF ( Dim , DIM , Cube ) CASE_SUF ( Dim , DIM , Rect ) CASE_SUF ( Dim , DIM , Buffer ) CASE_SUF ( Dim , DIM , SubpassData ) break ;


<s> static bool matchShuffleWithSHUFPD ( MVT VT , SDValue & V1 , SDValue & V2 , unsigned & ShuffleImm , ArrayRef < int > Mask ) { int NumElts = VT . getVectorNumElements ( ) ; assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; ShuffleImm = <NUM_LIT> ; bool ShufpdMask = true ; bool CommutableMask = true ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( Mask [ i ] == SM_SentinelUndef ) continue ; if ( Mask [ i ] < <NUM_LIT> ) return false ; int Val = ( i & <NUM_LIT> ) + NumElts * ( i & <NUM_LIT> ) ; int CommutVal = ( i & <NUM_LIT> ) + NumElts * ( ( i & <NUM_LIT> ) ^ <NUM_LIT> ) ; if ( Mask [ i ] < Val || Mask [ i ] > Val + <NUM_LIT> ) ShufpdMask = false ;

if ( Mask [ i ] < CommutVal || Mask [ i ] > CommutVal + <NUM_LIT> ) CommutableMask = false ;


<s> if ( mode == BLKmode ) return true ; if ( AGGREGATE_TYPE_P ( type ) && TYPE_ALIGN ( type ) < GET_MODE_ALIGNMENT ( mode ) ) return true ; return false ;


<s> unsigned int getRemainingOccupancy ( ) const { return RemainingOccupancy ;


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( TargetMachine & TM , CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; auto & ABI = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;

else return TFI -> hasFP ( MF ) ? ABI . GetFramePtr ( ) : ABI . GetStackPtr ( ) ;


<s> mips_start_function_definition ( name , false ) ; stub -> output_body ( ) ; mips_end_function_definition ( name ) ; delete stub ;


<s> for ( unsigned I = <NUM_LIT> , E = Sig -> Params . size ( ) ; I < E ; I ++ ) Ret += getInvokeSig ( Sig -> Params [ I ] ) ;


<s> enum machine_mode mode = insn_data [ icode ] . operand [ opnum ] . mode ; if ( ( * insn_data [ icode ] . operand [ opnum ] . predicate ) ( arg , mode ) ) return arg ;

else return copy_to_mode_reg ( mode , arg ) ;


<s> if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) assert ( hasV8MBaselineOps ( ) && ! NoMovt && <STR_LIT> ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ;


<s> assert ( isFrameInstr ( I ) && <STR_LIT> ) ; assert ( I . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> && <STR_LIT> ) ;

return I . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> StringRef getPassName ( ) const override {


<s> static bool isImplicitlyDef ( MachineRegisterInfo & MRI , unsigned Reg ) { for ( MachineRegisterInfo :: def_instr_iterator It = MRI . def_instr_begin ( Reg ) , E = MRI . def_instr_end ( ) ; It != E ; ++ It ) { return ( * It ) . isImplicitDef ( ) ; } if ( MRI . isReserved ( Reg ) ) { return false ; }


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( ( Value & <NUM_LIT> ) != <NUM_LIT> && ( Value & <NUM_LIT> ) != <NUM_LIT> ) return false ;


frame -> hard_frame_pointer_offset += ( diff & <NUM_LIT> ) ;


<s> bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; int64_t CfaAdjustment = - StackAdjustment ; if ( StackAdjustment ) {

StackAdjustment += mergeSPUpdates ( MBB , I , true ) ;


<s> unsigned OpIdx = RootMaskedIdx >> OpRatioLog2 ; if ( OpMask [ OpIdx ] < <NUM_LIT> ) { Mask [ i ] = OpMask [ OpIdx ] ; continue ; } unsigned OpMaskedIdx = OpRatio == <NUM_LIT> ? OpMask [ OpIdx ] : ( OpMask [ OpIdx ] << OpRatioLog2 ) + ( RootMaskedIdx & ( OpRatio - <NUM_LIT> ) ) ; OpMaskedIdx = OpMaskedIdx & ( MaskWidth - <NUM_LIT> ) ; int InputIdx = OpMask [ OpIdx ] / ( int ) OpMask . size ( ) ; assert ( <NUM_LIT> <= OpInputIdx [ InputIdx ] && <STR_LIT> ) ; OpMaskedIdx += OpInputIdx [ InputIdx ] * MaskWidth ; Mask [ i ] = OpMaskedIdx ; } if ( all_of ( Mask , [ ] ( int Idx ) { return Idx == SM_SentinelUndef ; } ) ) return DAG . getUNDEF ( Root . getValueType ( ) ) ; if ( all_of ( Mask , [ ] ( int Idx ) { return Idx < <NUM_LIT> ; } ) ) return getZeroVector ( Root . getSimpleValueType ( ) , Subtarget , DAG , SDLoc ( Root ) ) ; resolveTargetShuffleInputsAndMask ( Ops , Mask ) ; assert ( ! Ops . empty ( ) && <STR_LIT> ) ; HasVariableMask |= isTargetShuffleVariableMask ( Op . getOpcode ( ) ) ; SmallVector < const SDNode * , <NUM_LIT> > CombinedNodes ( SrcNodes . begin ( ) , SrcNodes . end ( ) ) ; CombinedNodes . push_back ( Op . getNode ( ) ) ; if ( Ops . size ( ) < ( MaxRecursionDepth - Depth ) ) { for ( int i = <NUM_LIT> , e = Ops . size ( ) ; i < e ; ++ i ) { bool AllowVar = false ; if ( Ops [ i ] . getNode ( ) -> hasOneUse ( ) || SDNode :: areOnlyUsersOf ( CombinedNodes , Ops [ i ] . getNode ( ) ) ) AllowVar = AllowVariableMask ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Ops , i , Root , Mask , CombinedNodes , Depth + <NUM_LIT> , HasVariableMask , AllowVar , DAG , Subtarget ) ) return Res ; } } if ( SDValue Cst = combine<ISA_LIT>ShufflesConstants ( Ops , Mask , Root , HasVariableMask , DAG , Subtarget ) ) return Cst ;


<s> if ( isLegalMUBUFImmOffset ( C1 ) ) { Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } else if ( isUInt < <NUM_LIT> > ( C1 -> getZExtValue ( ) ) ) { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; VAddr = N1 ;


<s> void <ISA_LIT>RegisterInfo :: getInitialFrameState ( std :: vector < MachineMove > & Moves ) const { MachineLocation Dst ( MachineLocation :: VirtualFP ) ;

MachineLocation Src ( <STR_LIT> , <NUM_LIT> ) ;


<s> int SplatValue = * FirstDefinedIdx ; if ( any_of ( make_range ( std :: next ( FirstDefinedIdx ) , Mask . end ( ) ) , [ & SplatValue ] ( int Elt ) { return Elt >= <NUM_LIT> && Elt != SplatValue ; } ) ) return None ;


<s> bool <ISA_LIT>Z80FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return false ;


<s> static SDValue CombineVMOVDRRCandidateWithVecOp ( const SDNode * BC , SelectionDAG & DAG ) { SDValue Op = BC -> getOperand ( <NUM_LIT> ) ; EVT DstVT = BC -> getValueType ( <NUM_LIT> ) ; if ( ! DstVT . isVector ( ) || Op . getOpcode ( ) != <STR_LIT> || ! Op . hasOneUse ( ) ) return SDValue ( ) ;

ConstantSDNode * Index = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ;


if ( auto * WrapperPass = P . getAnalysisIfAvailable < <ISA_LIT>AAWrapperPass > ( ) ) AAR . addAAResult ( WrapperPass -> getResult ( ) ) ;


<s> PointerType * PtrTy = PointerType :: get ( Type :: getInt64Ty ( MF . getFunction ( ) . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; const MCInstrDesc & LoadDwordX4 = TII -> get ( <STR_LIT> ) ; auto MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , LoadDwordX4 , ScratchRsrcReg ) . addReg ( Rsrc01 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) . addMemOperand ( MMO ) ; return ; } if ( ST . isMesaGfxShader ( MF ) || ( PreloadedPrivateBufferReg == <STR_LIT> ) ) { assert ( ! ST . isAmdCodeObjectV2 ( MF ) ) ; const MCInstrDesc & SMovB32 = TII -> get ( <STR_LIT> ) ; unsigned Rsrc2 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; unsigned Rsrc3 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; uint64_t Rsrc23 = TII -> getScratchRsrcWords23 ( ) ; if ( MFI -> hasImplicitBufferPtr ( ) ) { unsigned Rsrc01 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; if ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) { const MCInstrDesc & Mov64 = TII -> get ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , Mov64 , Rsrc01 ) . addReg ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ;


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { if ( MO . getReg ( ) == <STR_LIT> ) O << DEPOTNAME << getFunctionNumber ( ) ; else O << getRegisterName ( MO . getReg ( ) ) ; } else { if ( ! Modifier ) emitVirtualRegister ( MO . getReg ( ) , false , O ) ; else { if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) emitVirtualRegister ( MO . getReg ( ) , true , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } return ; case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : { const char * symbname = MO . getSymbolName ( ) ; if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ; sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ; printParamName ( index , O ) ; } else if ( strstr ( symbname , <STR_LIT> ) == symbname ) { unsigned index ;


<s> static void emit_frame_store ( unsigned int regno , rtx base_reg , HOST_WIDE_INT frame_bias , HOST_WIDE_INT base_ofs ) { rtx reg = gen_rtx_REG ( DImode , regno ) ; emit_frame_store_1 ( reg , base_reg , frame_bias , base_ofs , reg ) ;


<s> if ( ! Mst -> isTruncatingStore ( ) ) return reduceMaskedStoreToScalarStore ( Mst , DAG ) ; EVT VT = Mst -> getValue ( ) . getValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT StVT = Mst -> getMemoryVT ( ) ; SDLoc dl ( Mst ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ToSz = StVT . getVectorElementType ( ) . getSizeInBits ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTruncStoreLegal ( VT , StVT ) ) return SDValue ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; assert ( ( ( NumElems * FromSz ) % ToSz ) == <NUM_LIT> && <STR_LIT> ) ; unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ;

SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ;


<s> bool AllAnalyzable = true ; for ( const MachineInstr & Term : MBB -> terminators ( ) ) { AnyBarrier |= Term . isBarrier ( ) ; AllAnalyzable &= Term . isBranch ( ) && ! Term . isIndirectBranch ( ) ;


<s> { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned Opc ; bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; break ; } if ( VTIsi1 && SrcReg != <STR_LIT> ) { unsigned ANDReg = emitAnd_ri ( <STR_LIT> , SrcReg , false , <NUM_LIT> ) ; assert ( ANDReg && <STR_LIT> ) ; SrcReg = ANDReg ; } const MCInstrDesc & II = TII . get ( Opc ) ; SrcReg = constrainOperandRegClass ( II , SrcReg , II . getNumDefs ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg ) ;

addLoadStoreOperands ( Addr , MIB , MachineMemOperand :: MOStore , ScaleFactor , MMO ) ;


<s> <STR_LIT> <ISA_LIT>Z80MCExpr :: getFixupKind ( ) const { <STR_LIT> Kind = <STR_LIT> :: LastTargetFixupKind ; switch ( getKind ( ) ) { case VK_<ISA_LIT>Z80_LO8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_HH8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_HHI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_PM_LO8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_PM_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_PM_HH8 :


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const {


<s> AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ;


<s> if ( IsCheriPureCap ( ) ) return makeArrayRef ( CheriCapArgRegs ) ; if ( IsO32 ( ) ) return makeArrayRef ( O32IntRegs ) ; if ( IsN32 ( ) || IsN64 ( ) ) return makeArrayRef ( <ISA_LIT>64IntRegs ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C - <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C - <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C - <NUM_LIT> ) : C - <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != INT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != INT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != UINT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != UINT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; } } } if ( ! isa < ConstantSDNode > ( RHS ) || ! isLegalArithImmed ( cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ) ) { SDValue TheLHS = isCMN ( LHS , CC ) ? LHS . getOperand ( <NUM_LIT> ) : LHS ; if ( getCmpOperandFoldingProfit ( TheLHS ) > getCmpOperandFoldingProfit ( RHS ) ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; } } SDValue Cmp ;


<s> if ( ! getLdStOffsetOp ( MI ) . isImm ( ) ) return false ; MachineBasicBlock :: iterator StoreI ; if ( findMatchingStore ( MBBI , LdStLimit , StoreI ) ) {


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , STI ) ; return nullptr ;


<s> break ; case <STR_LIT> : { <ISA_LIT>ISelAddressMode Backup = AM ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ; break ; } case <STR_LIT> : if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; uint64_t Offset = CN -> getSExtValue ( ) ; if ( ! MatchAddress ( N . getOperand ( <NUM_LIT> ) , AM ) && AM . GV == nullptr && CurDAG -> MaskedValueIsZero ( N . getOperand ( <NUM_LIT> ) , CN -> getAPIntValue ( ) ) ) { AM . Disp += Offset ; return false ; } AM = Backup ; } break ; }


<s> case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO : if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else if ( MIFrm == <STR_LIT> ) FixupKind = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ;


<s> if ( Add . first == nullptr ) return nullptr ; Value * OffsetsIncoming = Add . first ; int64_t Immediate = Add . second ; if ( OffsetsIncoming != Phi ) return nullptr ; Builder . SetInsertPoint ( & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; unsigned NumElems = cast < FixedVectorType > ( OffsetsIncoming -> getType ( ) ) -> getNumElements ( ) ; Instruction * ScaledOffsets = BinaryOperator :: Create ( Instruction :: Shl , Phi -> getIncomingValue ( <NUM_LIT> - IncrementIndex ) , Builder . CreateVectorSplat ( NumElems , Builder . getInt32 ( TypeScale ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; OffsetsIncoming = BinaryOperator :: Create ( Instruction :: Add , ScaledOffsets , Builder . CreateVectorSplat ( NumElems , Builder . CreatePtrToInt ( BasePtr , cast < VectorType > ( ScaledOffsets -> getType ( ) ) -> getElementType ( ) ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; OffsetsIncoming = BinaryOperator :: Create ( Instruction :: Sub , OffsetsIncoming , Builder . CreateVectorSplat ( NumElems , Builder . getInt32 ( Immediate ) ) , <STR_LIT> , & Phi -> getIncomingBlock ( <NUM_LIT> - IncrementIndex ) -> back ( ) ) ; Phi -> setIncomingValue ( <NUM_LIT> - IncrementIndex , OffsetsIncoming ) ; Builder . SetInsertPoint ( I ) ; Value * EndResult ; Value * NewInduction ; if ( I -> getIntrinsicID ( ) == <STR_LIT> ) { Value * Load = tryCreateMaskedGatherBaseWB ( I , Phi , Builder , Immediate ) ; EndResult = Builder . CreateExtractValue ( Load , <NUM_LIT> , <STR_LIT> ) ; NewInduction = Builder . CreateExtractValue ( Load , <NUM_LIT> , <STR_LIT> ) ; } else { NewInduction = tryCreateMaskedScatterBaseWB ( I , Phi , Builder , Immediate ) ; EndResult = NewInduction ; } Instruction * AddInst = cast < Instruction > ( Offsets ) ; AddInst -> replaceAllUsesWith ( NewInduction ) ;


<s> if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) llvm_unreachable ( <STR_LIT> ) ; return MCOperand :: createExpr ( Expr ) ;


<s> TargetLoweringBase :: LegalizeTypeAction <ISA_LIT>TargetLowering :: getPreferredVectorAction ( EVT VT ) const { if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getScalarType ( ) . bitsLE ( <STR_LIT> ) ) return TypeSplitVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;


<s> __o = __builtin_aarch64_ld4rdi ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ;


<s> return new <ISA_LIT>CallFrameOptimization ( ) ;


SplitArgs . back ( ) . Flags [ <NUM_LIT> ] . setInConsecutiveRegsLast ( ) ;


<s> Gen = AMDGPUSubtarget :: R600 ; FP64 = false ; CaymanISA = false ; EnableIRStructurizer = true ; EnableIfCvt = true ; WavefrontSize = <NUM_LIT> ; CFALUBug = false ; ParseSubtargetFeatures ( GPU , FS ) ; DevName = GPU ;


<s> Node = emitIntrinsicWithCCAndChain ( DAG , C . Op0 , C . Opcode ) ; return SDValue ( Node , <NUM_LIT> ) ; case <STR_LIT> : Node = emitIntrinsicWithCC ( DAG , C . Op0 , C . Opcode ) ; return SDValue ( Node , Node -> getNumValues ( ) - <NUM_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( C . Opcode == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , C . Op0 , C . Op1 , DAG . getTargetConstant ( C . ICmpType , DL , <STR_LIT> ) ) ;


<s> virtual EVT getSetCCResultType ( LLVMContext & , EVT ) const LLVM_OVERRIDE { return <STR_LIT> ;


<s> return ( __mmask16 ) __builtin_ia32_kshiftrihi ( ( __mmask16 ) __A , ( __mmask8 ) __B ) ;


<s> MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; if ( isFPCmp ) BuildMI ( BB , dl , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; else BuildMI ( BB , dl , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ;


<s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;


<s> virtual const char * getPassName ( ) const {