<s> if ( ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) && Src -> isIntegerTy ( <NUM_LIT> ) ) { if ( ST -> hasLoadStoreOnCond2 ( ) ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( Opcode == Instruction :: SExt ) Cost = ( DstScalarBits < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: ZExt ) Cost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I ) : nullptr ) ; if ( CmpOpTy != nullptr && CmpOpTy -> isFloatingPointTy ( ) ) Cost ++ ; return Cost ; } } else if ( ST -> hasVector ( ) ) { assert ( Dst -> isVectorTy ( ) ) ; unsigned VF = cast < VectorType > ( Src ) -> getNumElements ( ) ; unsigned NumDstVectors = getNumVectorRegs ( Dst ) ; unsigned NumSrcVectors = getNumVectorRegs ( Src ) ; if ( Opcode == Instruction :: Trunc ) { if ( Src -> getScalarSizeInBits ( ) == Dst -> getScalarSizeInBits ( ) ) return <NUM_LIT> ; return getVectorTruncCost ( Src , Dst ) ; } if ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) { if ( SrcScalarBits >= <NUM_LIT> ) { unsigned NumUnpacks = getElSizeLog2Diff ( Src , Dst ) ; unsigned NumSrcVectorOps = ( NumUnpacks > <NUM_LIT> ? ( NumDstVectors - NumSrcVectors ) : ( NumDstVectors / <NUM_LIT> ) ) ; return ( NumUnpacks * NumDstVectors ) + NumSrcVectorOps ; } else if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) ; } if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP || Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) { if ( DstScalarBits == <NUM_LIT> || ST -> hasVectorEnhancements2 ( ) ) { if ( SrcScalarBits == DstScalarBits ) return NumDstVectors ; if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) + NumDstVectors ; } unsigned ScalarCost = getCastInstrCost ( Opcode , Dst -> getScalarType ( ) , Src -> getScalarType ( ) ) ; unsigned TotCost = VF * ScalarCost ; bool NeedsInserts = true , NeedsExtracts = true ; if ( DstScalarBits == <NUM_LIT> && ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP ) ) NeedsInserts = false ; if ( SrcScalarBits == <NUM_LIT> && ( Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) ) NeedsExtracts = false ; TotCost += getScalarizationOverhead ( Src , false , NeedsExtracts ) ; TotCost += getScalarizationOverhead ( Dst , NeedsInserts , false ) ; if ( VF == <NUM_LIT> && SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) TotCost *= <NUM_LIT> ; return TotCost ; } if ( Opcode == Instruction :: FPTrunc ) { if ( SrcScalarBits == <NUM_LIT> ) return VF + getScalarizationOverhead ( Dst , true , false ) ;

else return VF / <NUM_LIT> + std :: max ( <NUM_LIT> , VF / <NUM_LIT> ) ;


<s> addPass ( create<ISA_LIT>WholeQuadModePass ( ) ) ;


<s> if ( ST . isAmdHsaOS ( ) ) { if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ; if ( ST . getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) RsrcDataFormat |= ( <NUM_LIT> << <NUM_LIT> ) ;


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } else { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> return { LHS , Addr , Idx , Flag , Load , AA } ;


<s> while ( AGGREGATE_TYPE_P ( type ) ) { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return computed ; type = TREE_TYPE ( field ) ;

while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ;


<s> LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isLittle ) , DataLayout ( isLittle ? std :: string ( <STR_LIT> ) : std :: string ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) { if ( getRelocationModel ( ) == Reloc :: Default ) { if ( Subtarget . isABI_O32 ( ) ) setRelocationModel ( Reloc :: PIC_ ) ;

else setRelocationModel ( Reloc :: Static ) ;


<s> return ST . needsAlignedVGPRs ( ) ? & <STR_LIT> : & <STR_LIT> ;


<s> if ( ! no_rtl ) { if ( gr_saved > <NUM_LIT> ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - gr_saved * UNITS_PER_WORD ) ; mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . aapcs_ncrn + R0_REGNUM , mem , gr_saved ) ; } if ( vr_saved > <NUM_LIT> ) { machine_mode mode = TImode ; int off , i , vr_start ; off = - ROUND_UP ( gr_saved * UNITS_PER_WORD , STACK_BOUNDARY / BITS_PER_UNIT ) ; off -= vr_saved * UNITS_PER_VREG ; vr_start = V0_REGNUM + local_cum . aapcs_nvrn ; for ( i = <NUM_LIT> ; i < vr_saved ; ++ i ) { rtx ptr , mem ; ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , off ) ; mem = gen_frame_mem ( mode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; aarch64_emit_move ( mem , gen_rtx_REG ( mode , vr_start + i ) ) ; off += UNITS_PER_VREG ; } }


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPIC ( ) {


<s> } else if ( str == <STR_LIT> ) { operands . push_back ( <ISA_LIT>Operand :: CreateBrCC ( <ISA_LIT>Operand :: BrCC :: C , tok . getLoc ( ) , tok . getEndLoc ( ) ) ) ; } else if ( str == <STR_LIT> ) { operands . push_back ( <ISA_LIT>Operand :: CreateBrCC ( <ISA_LIT>Operand :: BrCC :: PO , tok . getLoc ( ) , tok . getEndLoc ( ) ) ) ; } else if ( str == <STR_LIT> ) { operands . push_back ( <ISA_LIT>Operand :: CreateBrCC ( <ISA_LIT>Operand :: BrCC :: PE , tok . getLoc ( ) , tok . getEndLoc ( ) ) ) ; } else if ( str == <STR_LIT> ) {

operands . push_back ( <ISA_LIT>Operand :: CreateBrCC ( <ISA_LIT>Operand :: BrCC :: P , tok . getLoc ( ) , tok . getEndLoc ( ) ) ) ;


<s> return pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu ;


<s> return isExtImm < <NUM_LIT> > ( false , <NUM_LIT> ) ;


<s> void <ISA_LIT>LatencyQueue :: clear ( ) {


<s> MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) } ; int64_t Offsets [ <NUM_LIT> ] = { MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> } ; uint64_t Word01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t Word2 = Sampler << <NUM_LIT> | SrcSelect [ ELEMENT_X ] << <NUM_LIT> | SrcSelect [ ELEMENT_Y ] << <NUM_LIT> | SrcSelect [ ELEMENT_Z ] << <NUM_LIT> | SrcSelect [ ELEMENT_W ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> ;


<s> <ISA_LIT>TargetStreamer :: ~ <ISA_LIT>TargetStreamer ( ) {


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; StackSize -= <ISA_LIT>MFI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = StackSize - TFI . getOffsetOfLocalArea ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( StackSize || MFI -> hasCalls ( ) ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitSPUpdate ( MBB , MBBI , - ( int64_t ) NumBytes , TII ) ;


<s> ca -> mem_count = <NUM_LIT> ; if ( ! named ) return ; if ( mode == PSImode ) nregs = <NUM_LIT> ; else nregs = ( nregs + <NUM_LIT> ) / <NUM_LIT> ; if ( ca -> special_p ) { ca -> start_reg = <NUM_LIT> ; ca -> reg_count = <NUM_LIT> ; return ; } switch ( nregs ) { case <NUM_LIT> : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ! ca -> reg_used [ i ] ) { ca -> reg_count = <NUM_LIT> ; ca -> start_reg = CA_FIRST_REG + i ; return ; } break ; case <NUM_LIT> : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ! ca -> reg_used [ i ] && ! ca -> reg_used [ i + <NUM_LIT> ] ) { ca -> reg_count = <NUM_LIT> ; ca -> start_reg = CA_FIRST_REG + i ; return ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


<s> save_regs [ regno ] = <NUM_LIT> ; continue ; } if ( crx_interrupt_function_p ( ) ) { if ( ! current_function_is_leaf && call_used_regs [ regno ] ) save_regs [ regno ] = <NUM_LIT> ; else if ( regs_ever_live [ regno ] ) save_regs [ regno ] = <NUM_LIT> ; else save_regs [ regno ] = <NUM_LIT> ; } else { if ( regs_ever_live [ regno ] && ( ! call_used_regs [ regno ] || regno == RETURN_ADDRESS_REGNUM ) ) save_regs [ regno ] = <NUM_LIT> ; else save_regs [ regno ] = <NUM_LIT> ; } } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( save_regs [ regno ] == <NUM_LIT> ) { last_reg_to_save = regno ; sum_regs += UNITS_PER_WORD ; }


<s> if ( mode != V4SFmode && all_const_zero ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_XOR ( mode , target , target ) ) ) ; return ; } else if ( mode != V4SFmode && easy_vector_constant ( vals , mode ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , vals ) ) ; return ; } else if ( all_same ) ; else { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ) ; return ; } } if ( all_same ) { mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) , <NUM_LIT> ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , <NUM_LIT> ) , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , target , mem ) , x ) ) ) ; x = gen_rtx_VEC_SELECT ( inner_mode , target , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_VEC_DUPLICATE ( mode , x ) ) ) ; return ; } if ( n_var == <NUM_LIT> ) { rtx copy = copy_rtx ( vals ) ; XVECEXP ( copy , <NUM_LIT> , one_var ) = XVECEXP ( vals , <NUM_LIT> , ( one_var + <NUM_LIT> ) % n_elts ) ; rs6000_expand_vector_init ( target , copy ) ; rs6000_expand_vector_set ( target , XVECEXP ( vals , <NUM_LIT> , one_var ) , one_var ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ;

for ( i = <NUM_LIT> ; i < n_elts ; i ++ ) emit_move_insn ( adjust_address_nv ( mem , inner_mode , i * GET_MODE_SIZE ( inner_mode ) ) , XVECEXP ( vals , <NUM_LIT> , i ) ) ;


return __builtin_neon_vcvtahssi ( __a ) ;


<s> int RegNo = tryParseRegister ( ) ; if ( RegNo == - <NUM_LIT> ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExclaimTok . getString ( ) , ExclaimTok . getLoc ( ) ) ) ; Parser . Lex ( ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; SMLoc ExprLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) {


<s> void mips_emit_binary ( enum rtx_code code , rtx target , rtx op0 , rtx op1 ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_ee ( code , GET_MODE ( target ) , op0 , op1 ) ) ) ;


<s> p1 = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( p1 ) == CONST_INT ) { if ( ( GET_CODE ( p0 ) == UNSPEC ) ) return false ;

if ( ( GET_CODE ( p0 ) == SYMBOL_REF || GET_CODE ( p0 ) == LABEL_REF ) && ( microblaze_tls_symbol_p ( p0 ) || ! SMALL_INT ( p1 ) ) ) return false ;


<s> case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; default : assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> void <ISA_LIT>TargetLowering :: bundleInstWithWaitcnt ( MachineInstr & MI ) const { MachineBasicBlock * MBB = MI . getParent ( ) ; const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; auto I = MI . getIterator ( ) ; auto E = std :: next ( I ) ; BuildMI ( * MBB , E , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder Bundler ( * MBB , I , E ) ; finalizeBundle ( * MBB , Bundler . begin ( ) ) ;


<s> <ISA_LIT>SPMark ( <ISA_LIT>TargetMachine & tm ) : MachineModulePass ( ID ) , TM ( tm ) { ( void ) TM ;


<s> return <ISA_LIT>ABIInfo ( <STR_LIT> ) ;


<s> if ( EmitUniquedSection ) { Name . append ( <STR_LIT> ) ; Name . append ( GO -> getName ( ) ) ; } TRACE ( <STR_LIT> << Name << <STR_LIT> ) ; return getContext ( ) . getELFSection ( Name . str ( ) , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; } if ( Kind . isCommon ( ) ) { if ( NoSmallDataSorting ) return BSSSection ; Twine Name = Twine ( <STR_LIT> ) + getSectionSuffixForSize ( Size ) ; TRACE ( <STR_LIT> << Name << <STR_LIT> ) ; return getContext ( ) . getELFSection ( Name . str ( ) , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_HEX_GPREL ) ; } if ( Kind . isMergeableConst ( ) ) { TRACE ( <STR_LIT> ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GO ) ; if ( GVar -> hasSection ( ) && isSmallDataSection ( GVar -> getSection ( ) ) ) Kind = SectionKind :: getData ( ) ; } if ( Kind . isData ( ) ) { if ( NoSmallDataSorting ) { TRACE ( <STR_LIT> ) ; return SmallDataSection ; } StringRef Prefix ( <STR_LIT> ) ; SmallString < <NUM_LIT> > Name ( Prefix ) ; Name . append ( getSectionSuffixForSize ( Size ) ) ; if ( EmitUniquedSection ) { Name . append ( <STR_LIT> ) ; Name . append ( GO -> getName ( ) ) ;


<s> if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;

return Infos [ Kind - FirstTargetFixupKind ] ;


<s> } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned KnownBits = UserBBI . internalKnownBits ( ) ; unsigned UPad = UnknownPadding ( LogAlign , KnownBits ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) - UPad ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = std :: max ( UserBBI . postOffset ( ) - UPad - <NUM_LIT> , UserOffset + TII -> GetInstSizeInBytes ( UserMI ) + <NUM_LIT> ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + UPad + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = nullptr ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = std :: next ( MI ) ) { assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ; if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset += U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = MI ; } -- MI ; if ( LastIT ) { unsigned PredReg = <NUM_LIT> ;

<STR_LIT> CC = getITInstrPredicate ( MI , PredReg ) ;


<s> assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; Offset /= <NUM_LIT> ; bool isU6 = isImmU6 ( Offset ) ; if ( ! isU6 && ! isImmU16 ( Offset ) ) report_fatal_error ( <STR_LIT> + Twine ( Offset ) ) ; int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ;

BuildMI ( MBB , I , dl , TII . get ( Opcode ) , DstReg ) . addImm ( Offset ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseMSA128HRegs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) {

return parseMSARegs ( Operands , ( int ) <STR_LIT> ) ;


<s> } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || In64BitMode ) stackAlignment = <NUM_LIT> ;


<s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> rtx tmp ; tmp = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , src1 , src2 ) ) ;

if ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( SImode ) && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) {


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , VT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result ; if ( SingleOp . getNode ( ) ) { switch ( Opc ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , SingleOp ) ; break ;


<s> if ( Op == ADD ) { if ( ( CNVal == <NUM_LIT> ) || ( CNVal == - <NUM_LIT> ) ) { Op = ( CNVal == <NUM_LIT> ) ? INC : DEC ; return SDValue ( ) ; } if ( CNVal < <NUM_LIT> ) { Op = SUB ; CNVal = - CNVal ; } } return CurDAG -> getTargetConstant ( CNVal , NVT ) ; } if ( Op == ADD && Val . hasOneUse ( ) ) { if ( Val . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Val . getOperand ( <NUM_LIT> ) ) ) { Op = SUB ; return Val . getOperand ( <NUM_LIT> ) ; } if ( Val . getOpcode ( ) == <STR_LIT> && NVT == <STR_LIT> && Val . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( Val . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { Op = SUB ; Val = Val . getOperand ( <NUM_LIT> ) ; return CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , NVT , Val . getOperand ( <NUM_LIT> ) ) ; } }


<s> static bool isPromotableZeroStoreInst ( MachineInstr & MI ) { return ( isPromotableZeroStoreOpcode ( MI ) ) && getLdStRegOp ( MI ) . getReg ( ) == <STR_LIT> ;


<s> bool aarch64_split_128bit_move_p ( rtx dst , rtx src ) { return ( ! REG_P ( src ) || ! ( FP_REGNUM_P ( REGNO ( dst ) ) && FP_REGNUM_P ( REGNO ( src ) ) ) ) ;


<s> __arm_cdp ( const unsigned int __coproc , const unsigned int __opc1 , const unsigned int __CRd , const unsigned int __CRn , const unsigned int __CRm , const unsigned int __opc2 ) {


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; AddressingMode SupportedAM ( true , true ) ; if ( I != nullptr ) SupportedAM = supportedAddressingMode ( I , Subtarget . hasVector ( ) ) ; if ( ! SupportedAM . LongDisplacement && ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; if ( ! SupportedAM . IndexReg ) return AM . Scale == <NUM_LIT> ; else return AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> ;


<s> DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLocSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfARangesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfRangesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , leaInReg , true , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned Src2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill2 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned leaInReg2 = <NUM_LIT> ; MachineInstr * InsMI2 = <NUM_LIT> ; if ( Src == Src2 ) { addRegReg ( MIB , leaInReg , true , leaInReg , false ) ; } else { leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) ; InsMI2 = BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( leaInReg2 , RegState :: Define , <STR_LIT> ) . addReg ( Src2 , getKillRegState ( isKill2 ) ) ; addRegReg ( MIB , leaInReg , true , leaInReg2 , true ) ; } if ( LV && isKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , InsMI2 ) ; break ; } } MachineInstr * NewMI = MIB ; MachineInstr * ExtMI = BuildMI ( * MFI , MBBI , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( Dest , RegState :: Define | getDeadRegState ( isDead ) ) . addReg ( leaOutReg , RegState :: Kill , <STR_LIT> ) ; if ( LV ) { LV -> getVarInfo ( leaInReg ) . Kills . push_back ( NewMI ) ; LV -> getVarInfo ( leaOutReg ) . Kills . push_back ( ExtMI ) ; if ( isKill ) LV -> replaceKillInstruction ( Src , MI , InsMI ) ; if ( isDead ) LV -> replaceKillInstruction ( Dest , MI , ExtMI ) ; } return ExtMI ;


<s> bool popFeatureBits ( ) { assert ( FeatureBitStack . size ( ) == ParserOptionsStack . size ( ) && <STR_LIT> ) ; if ( FeatureBitStack . empty ( ) ) return true ; FeatureBitset FeatureBits = FeatureBitStack . pop_back_val ( ) ; copySTI ( ) . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( FeatureBits ) ) ; ParserOptions = ParserOptionsStack . pop_back_val ( ) ;


<s> DebugLoc DL ; AddDefaultPred ( BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } }


<s> static inline ShiftOpc getAM2ShiftOpc ( unsigned AM2Opc ) { return ( ShiftOpc ) ( ( AM2Opc >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> if ( ! I . isPHI ( ) ) break ; for ( unsigned oi = I . getNumOperands ( ) ; oi > <NUM_LIT> ; oi -= <NUM_LIT> ) { if ( I . getOperand ( oi - <NUM_LIT> ) . getMBB ( ) == CmpBB ) { I . RemoveOperand ( oi - <NUM_LIT> ) ; I . RemoveOperand ( oi - <NUM_LIT> ) ; } } }


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ;


<s> Offset = StackOffset :: getFixed ( MFI . getObjectOffset ( FrameIndex ) + AFI -> getTaggedBasePointerOffset ( ) ) ; } else if ( Tagged ) { StackOffset SPOffset = StackOffset :: getFixed ( MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) ) ; if ( MFI . hasVarSizedObjects ( ) || is<ISA_LIT>FrameOffsetLegal ( MI , SPOffset , nullptr , nullptr , nullptr ) != ( <ISA_LIT>FrameOffsetCanUpdate | <ISA_LIT>FrameOffsetIsLegal ) ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; return ; } FrameReg = <STR_LIT> ;


<s> static void sparc_file_end ( void ) { if ( pic_helper_symbol_name [ <NUM_LIT> ] && ! pic_helper_emitted_p ) emit_pic_helper ( ) ; if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack ( ) ;


<s> if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , NumSubElts ) ; } static <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VstNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , SubVecTy ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( ) ) ; Ops . push_back ( Builder . CreateBitCast ( SI -> getPointerOperand ( ) , Int8Ptr ) ) ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , getSequentialMask ( Builder , NumSubElts * i , NumSubElts ) ) ) ;

Ops . push_back ( Builder . getInt32 ( SI -> getAlignment ( ) ) ) ;


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; N = N . getOperand ( <NUM_LIT> ) ;

if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return false ;


<s> BasicBlock * NewBlk = OldTI -> getParent ( ) ; BasicBlock * TrueBlk = BasicBlock :: Create ( Cxt , NewBlk -> getName ( ) + <STR_LIT> , Func ) ; TrueBlk -> moveAfter ( NewBlk ) ; BasicBlock * FalseBlk = BasicBlock :: Create ( Cxt , NewBlk -> getName ( ) + <STR_LIT> , Func ) ; FalseBlk -> moveAfter ( TrueBlk ) ; IRB . SetInsertPoint ( OldTI ) ; IRB . CreateCondBr ( Cond , TrueBlk , FalseBlk ) ; OldTI -> eraseFromParent ( ) ; IRB . SetInsertPoint ( TrueBlk ) ; IRB . CreateBr ( EndBlk ) ; IRB . SetInsertPoint ( FalseBlk ) ; IRB . CreateBr ( EndBlk ) ; IRB . SetInsertPoint ( EndBlk -> getFirstNonPHI ( ) ) ; PHINode * PHI = IRB . CreatePHI ( Select -> getType ( ) , <NUM_LIT> ) ; PHI -> addIncoming ( TrueVal , TrueBlk ) ; PHI -> addIncoming ( FalseVal , FalseBlk ) ;


<s> llvm :: MachineBasicBlock :: iterator cmpInst = NULL ; for ( llvm :: MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == <STR_LIT> ) { errs ( ) << <STR_LIT> ; I -> dump ( ) ; MBB -> dump ( ) ; errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> ; } if ( I -> getOpcode ( ) == <STR_LIT> && ! ( I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ) { errs ( ) << <STR_LIT> ; I -> dump ( ) ; I -> getOperand ( <NUM_LIT> ) . print ( errs ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>Z80TargetMC ( ) {


<s> MachineBasicBlock & SrcMBB = * block -> getMBB ( ) ; if ( predType == RAInfo :: Register ) { RAInfo & RI = S -> isSubheader ( block ) ? RAInfos . at ( S -> findScopeOf ( block ) ) : RAInfos . at ( S ) ; if ( ! S -> isSubheader ( block ) || ! RI . needsScopeSpill ( ) ) { assert ( ! S -> isSubheader ( block ) || ( RI . Scope -> getParent ( ) == S ) ) ;

insertDefToRegLoc ( SrcMBB , predLoc , guardLoc , cond , ! first_def || S -> isSubheader ( block ) ) ;


<s> initializeEnvironment ( ) ; initSubtargetFeatures ( CPU , FS ) ; ParseSubtargetFeatures ( CPU , FS ) ;


<s> NodeAddr < UseNode * > UA = newNode ( NodeAttrs :: Ref | NodeAttrs :: Use | Flags ) ; UA . Addr -> setRegRef ( & Op , * this ) ; return UA ;


<s> if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec , true ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart ( LoLoop ) ; RemoveDeadBranch ( LoLoop . Start ) ;

LoLoop . End = ExpandLoopEnd ( LoLoop ) ;


<s> static int spu_naked_function_p ( tree func ) { tree a ;

if ( TREE_CODE ( func ) != FUNCTION_DECL ) abort ( ) ;


<s> case AddrModeT1_s : return <STR_LIT> ; case AddrModeT2_i12 : return <STR_LIT> ; case AddrModeT2_i8 : return <STR_LIT> ; case AddrModeT2_so : return <STR_LIT> ; case AddrModeT2_pc : return <STR_LIT> ; case AddrModeT2_i8s4 : return <STR_LIT> ; case AddrMode_i12 : return <STR_LIT> ; case AddrModeT2_ldrex : return <STR_LIT> ; case AddrModeT2_i7s4 : return <STR_LIT> ; case AddrModeT2_i7s2 : return <STR_LIT> ; case AddrModeT2_i7 : return <STR_LIT> ;


<s> else if ( insn_is_store_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_stvx_pattern ( insn , to_delete ) ;


<s> if ( cast < FixedVectorType > ( VecTy ) -> getNumElements ( ) < <NUM_LIT> ) return false ; if ( ElSize != <NUM_LIT> && ElSize != <NUM_LIT> && ElSize != <NUM_LIT> && ElSize != <NUM_LIT> ) return false ; return VecSize == <NUM_LIT> || VecSize % <NUM_LIT> == <NUM_LIT> ;


<s> return new <ISA_LIT>InstructionSelector ( TM , Subtarget , RBI ) ;


<s> <ISA_LIT>SEInstrInfo :: <ISA_LIT>SEInstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>InstrInfo ( STI , STI . getRelocationModel ( ) == Reloc :: PIC_ ? <STR_LIT> : <STR_LIT> ) , RI ( STI ) {


<s>
}
OutStreamer
->
emitRawComment
(
<STR_LIT>
,
false
)
;
emitCommonFunctionComments
(
CurrentProgramInfo
.
NumVGPR
,
CurrentProgramInfo
.
NumSGPR
,
CurrentProgramInfo
.
ScratchSize
,
getFunctionCodeSize
(
MF
)
,
MFI
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
CurrentProgramInfo
.
FloatMode
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
CurrentProgramInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
CurrentProgramInfo
.
LDSSize
)
+
<STR_LIT>
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
CurrentProgramInfo
.
SGPRBlocks
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
CurrentProgramInfo
.
VGPRBlocks
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
CurrentProgramInfo
.
NumSGPRsForWavesPerEU
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
CurrentProgramInfo
.
NumVGPRsForWavesPerEU
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
MFI
->
needsWaveLimiter
(
)
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
G_00B84C_USER_SGPR
(
CurrentProgramInfo
.
ComputePGMRSrc2
)
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
G_00B84C_TRAP_HANDLER
(
CurrentProgramInfo
.
ComputePGMRSrc2
)
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
G_00B84C_TGID_X_EN
(
CurrentProgramInfo
.
ComputePGMRSrc2
)
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
G_00B84C_TGID_Y_EN
(
CurrentProgramInfo
.
ComputePGMRSrc2
)
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
G_00B84C_TGID_Z_EN
(
CurrentProgramInfo
.
ComputePGMRSrc2
)
)
,
false
)
;
OutStreamer
->
emitRawComment
(
<STR_LIT>
+
Twine
(
G_00B84C_TIDIG_COMP_CNT
(
CurrentProgramInfo
.
ComputePGMRSrc2
)
)
,
false
)
;
}
if
(
DumpCodeInstEmitter
)
{
OutStreamer
->
SwitchSection
(
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_NOTE
,
<NUM_LIT>
)
)
;
for
(
size_t
i
=
<NUM_LIT>
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
=
<STR_LIT>
;
if
(
!
HexLines
[
i
]
.
empty
(
)
)
{
Comment
=
std
::
string
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;

Comment += <STR_LIT> + HexLines [ i ] + <STR_LIT> ;


<s> assert ( Op0 . isReg ( ) && Op1 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; unsigned SrcReg = Op1 . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ; } case <STR_LIT> : { const MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Op1 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op0 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ;

return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || NotExt ) ;


<s> EVT VT = LN -> getMemoryVT ( ) ; unsigned Size = VT . getStoreSize ( ) ; unsigned Align = LN -> getAlignment ( ) ; if ( Align < Size && isTypeLegal ( VT ) ) { bool IsFast ; unsigned AS = LN -> getAddressSpace ( ) ; if ( ! allowsMisalignedMemoryAccesses ( VT , AS , Align , LN -> getMemOperand ( ) -> getFlags ( ) , & IsFast ) ) { if ( VT . isVector ( ) ) return scalarizeVectorLoad ( LN , DAG ) ; SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( LN , DAG ) ; return DAG . getMergeValues ( Ops , SDLoc ( N ) ) ; } if ( ! IsFast ) return SDValue ( ) ; } if ( ! shouldCombineMemoryType ( VT ) ) return SDValue ( ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ; SDValue NewLoad = DAG . getLoad ( NewVT , SL , LN -> getChain ( ) , LN -> getBasePtr ( ) , LN -> getMemOperand ( ) ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , VT , NewLoad ) ; DCI . CombineTo ( N , BC , NewLoad . getValue ( <NUM_LIT> ) ) ;


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value >= <NUM_LIT> && Value < <NUM_LIT> ;


<s> if ( ! CallingConvSupported ( CallConv ) ) fail ( DL , DAG , <STR_LIT> <STR_LIT> ) ; if ( CLI . IsPatchPoint ) fail ( DL , DAG , <STR_LIT> ) ; if ( ( CallConv == CallingConv :: Fast && CLI . IsTailCall && MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) || ( CLI . CS && CLI . CS -> isMustTailCall ( ) ) ) fail ( DL , DAG , <STR_LIT> ) ; CLI . IsTailCall = false ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; if ( Ins . size ( ) > <NUM_LIT> ) fail ( DL , DAG , <STR_LIT> ) ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; for ( unsigned i = <NUM_LIT> ; i < Outs . size ( ) ; ++ i ) { const <STR_LIT> & Out = Outs [ i ] ; SDValue & OutVal = OutVals [ i ] ; if ( Out . Flags . isNest ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInAlloca ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInConsecutiveRegs ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInConsecutiveRegsLast ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isByVal ( ) && Out . Flags . getByValSize ( ) != <NUM_LIT> ) { auto * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateStackObject ( Out . Flags . getByValSize ( ) , Out . Flags . getByValAlign ( ) , false ) ; SDValue SizeNode = DAG . getConstant ( Out . Flags . getByValSize ( ) , DL , <STR_LIT> ) ; SDValue FINode = DAG . getFrameIndex ( FI , getPointerTy ( Layout ) ) ; Chain = DAG . getMemcpy ( Chain , DL , FINode , OutVal , SizeNode , Out . Flags . getByValAlign ( ) , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ; OutVal = FINode ; } } bool IsVarArg = CLI . IsVarArg ; unsigned NumFixedArgs = CLI . NumFixedArgs ; auto PtrVT = getPointerTy ( Layout ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; if ( IsVarArg ) { for ( SDValue Arg :

make_range ( OutVals . begin ( ) + NumFixedArgs , OutVals . end ( ) ) ) {


<s> if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return false ; return <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MF ) ;


<s> Offset = MO . getImm ( ) - WordOffset * getImmScale ( Opc ) ; unsigned InstrSrcReg = getLoadStoreRegOp ( * MBBI ) . getReg ( ) ; if ( Offset >= <NUM_LIT> && ! ( IsStore && InstrSrcReg == Base ) ) MO . setImm ( Offset ) ; else InsertSub = true ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! definesCPSR ( * MBBI ) ) { MachineOperand & MO = MBBI -> getOperand ( MBBI -> getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) ; Offset = ( Opc == <STR_LIT> ) ? MO . getImm ( ) + WordOffset * <NUM_LIT> : MO . getImm ( ) - WordOffset * <NUM_LIT> ; if ( Offset >= <NUM_LIT> && TL -> isLegalAddImmediate ( Offset ) ) { MO . setImm ( Offset ) ; return ; } else { InsertSub = true ; }


<s> unsigned DestReg = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DestRC = TargetRegisterInfo :: isVirtualRegister ( DestReg ) ? MRI . getRegClass ( DestReg ) : TRI . getPhysRegClass ( DestReg ) ; unsigned MovOp = TII -> getMovOpcode ( DestRC ) ; if ( MovOp == AMDGPU :: COPY ) continue ; UseMI -> setDesc ( TII -> get ( MovOp ) ) ; } } const MCInstrDesc & UseDesc = UseMI -> getDesc ( ) ; if ( UseDesc . isVariadic ( ) || UseDesc . OpInfo [ Use . getOperandNo ( ) ] . RegClass == - <NUM_LIT> ) continue ; if ( FoldingImm ) { MachineOperand ImmOp = MachineOperand :: CreateImm ( Imm . getSExtValue ( ) ) ; tryAddToFoldList ( FoldList , UseMI , Use . getOperandNo ( ) , & ImmOp , TII ) ; continue ; } tryAddToFoldList ( FoldList , UseMI , Use . getOperandNo ( ) , & OpToFold , TII ) ; } for ( FoldCandidate & Fold : FoldList ) { if ( updateOperand ( Fold , TRI ) ) { if ( ! Fold . isImm ( ) ) { assert ( Fold . OpToFold && Fold . OpToFold -> isReg ( ) ) ; Fold . OpToFold -> setIsKill ( false ) ; } DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << Fold . UseOpNo << <STR_LIT> << * Fold . UseMI << '\n' ) ; } }


<s> Opc = <ISA_LIT>SubTarget -> hasSPE ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = FP64LoadOpc ; break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , UseOffset , IndexReg ) ; bool IsVSSRC = isVSSRCRegClass ( UseRC ) ; bool IsVSFRC = isVSFRCRegClass ( UseRC ) ; bool Is32VSXLoad = IsVSSRC && Opc == <STR_LIT> ; bool Is64VSXLoad = IsVSFRC && Opc == <STR_LIT> ; if ( ( Is32VSXLoad || Is64VSXLoad ) && ( Addr . BaseType != Address :: FrameIndexBase ) && UseOffset && ( Addr . Offset == <NUM_LIT> ) ) { UseOffset = false ; } if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = IsVSSRC ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = IsVSFRC ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } auto MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; if ( IndexReg ) MIB . addReg ( Addr . Base . Reg ) . addReg ( IndexReg ) ;

else MIB . addReg ( <STR_LIT> ) . addReg ( Addr . Base . Reg ) ;


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= InsertITInstructions ( MBB ) ;

if ( Modified ) AFI -> setHasITBlocks ( true ) ;


<s> AU . addRequired < MemorySSAWrapperPass > ( ) ;


<s> else { for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { EVT RegVT = Ins [ i ] . VT ; TargetRegisterClass * TRC = getRegClassFor ( RegVT ) ; unsigned RegType ; if ( RegVT == <STR_LIT> ) { RegType = <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RegType = <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RegType = <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RegType = <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RegType = <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RegType = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue Index = DAG . getTargetConstant ( i , <STR_LIT> ) ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( TRC ) ; SDValue ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , Chain , Index ) ; InVals . push_back ( ArgValue ) ; MFI -> addRegister ( Reg , RegType , <STR_LIT> ) ; } } return Chain ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti , MII ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( Triple ( sti . getTargetTriple ( ) ) , sti . getCPU ( ) , Options ) ) { MCAsmParserExtension :: Initialize ( parser ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ;

setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsHvxMemoryAccess ( MVT VecTy , MachineMemOperand :: Flags Flags , bool * Fast ) const { if ( VecTy . getSizeInBits ( ) > <NUM_LIT> * Subtarget . getVectorLength ( ) ) return false ; if ( ! Subtarget . isHVXVectorType ( VecTy , false ) ) return false ;


<s> if ( CE -> getOpcode ( ) == Instruction :: AddrSpaceCast ) { unsigned SrcAS = CE -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getPointerAddressSpace ( ) ; return castRequiresQueuePtr ( SrcAS ) ;


<s> lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) ) return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ;


<s> unsigned KnownBits = BBInfo [ i - <NUM_LIT> ] . postKnownBits ( LogAlign ) ;

if ( i > BBNum + <NUM_LIT> && BBInfo [ i ] . Offset == Offset && BBInfo [ i ] . KnownBits == KnownBits ) break ;


<s> SDValue XformMskToBitPosU3Imm ( uint8_t Imm ) {


<s> if ( SU == UsesDotCur ) { UsesDotCur = nullptr ; DotCurPNum = - <NUM_LIT> ; } UsesLoad = MI -> mayLoad ( ) ; if ( TII -> isHVXVec ( * MI ) && ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) for ( auto & S : SU -> Succs ) if ( S . isAssignedRegDep ( ) && S . getLatency ( ) == <NUM_LIT> && TII -> mayBeNewStore ( * S . getSUnit ( ) -> getInstr ( ) ) && Resources -> canReserveResources ( * S . getSUnit ( ) -> getInstr ( ) ) ) { PrefVectorStoreNew = S . getSUnit ( ) ; break ;


<s> void <ISA_LIT>InstPrinter :: printUnsignedImm ( const MCInst * MI , int opNum , raw_ostream & O ) { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( RB0 == - <NUM_LIT> ) return RB1 ;


<s> int64_t getImmU16Context ( ) const {

assert ( ( Kind == Immediate || Kind == ContextImmediate ) && <STR_LIT> ) ;


<s> if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) ) return false ; } unsigned MIaG = <ISA_LIT>MCInstrInfo :: getDuplexCandidateGroup ( MIa ) , MIbG = <ISA_LIT>MCInstrInfo :: getDuplexCandidateGroup ( MIb ) ; static std :: map < unsigned , unsigned > subinstOpcodeMap ( std :: begin ( opcodeData ) , std :: end ( opcodeData ) ) ; if ( ( MIaG != <STR_LIT> ) && ( MIaG == MIbG ) && bisReversable ) { MCInst SubInst0 = <ISA_LIT>MCInstrInfo :: deriveSubInst ( MIa ) ; MCInst SubInst1 = <ISA_LIT>MCInstrInfo :: deriveSubInst ( MIb ) ; unsigned zeroedSubInstS0 = subinstOpcodeMap . find ( SubInst0 . getOpcode ( ) ) -> second ; unsigned zeroedSubInstS1 = subinstOpcodeMap . find ( SubInst1 . getOpcode ( ) ) -> second ; if ( zeroedSubInstS0 < zeroedSubInstS1 ) return false ; } if ( MIb . getOpcode ( ) == <STR_LIT> ) return false ; if ( ( MIaG != <STR_LIT> ) && ( MIbG != <STR_LIT> ) ) { if ( subInstWouldBeExtended ( MIa ) ) return false ; if ( subInstWouldBeExtended ( MIb ) && ! ExtendedB ) return false ; } if ( MIbG == <STR_LIT> ) { if ( ( MIb . getNumOperands ( ) > <NUM_LIT> ) && MIb . getOperand ( <NUM_LIT> ) . isReg ( ) && ( MIb . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ; FpFormatTy Format = getFpFormat ( ) ; if ( Format == FP_FORMAT_S || Format == FP_FORMAT_W ) return getReg ( <STR_LIT> , IntVal ) ; if ( Format == FP_FORMAT_D ) { if ( isFP64 ( ) ) { return getReg ( <STR_LIT> , IntVal ) ; } if ( ( IntVal > <NUM_LIT> ) || ( IntVal % <NUM_LIT> != <NUM_LIT> ) ) return - <NUM_LIT> ; return getReg ( <STR_LIT> , IntVal / <NUM_LIT> ) ; } }


<s> return ( vector signed short ) __builtin_altivec_vpkswss ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> if ( ToVT != <STR_LIT> && ToVT != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( FromVT != <STR_LIT> && FromVT != <STR_LIT> ) return SDValue ( ) ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = DAG . SplitVectorOperand ( N , <NUM_LIT> ) ;


<s> MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> bool <ISA_LIT>PacketizerList :: restrictingDepExistInPacket ( MachineInstr & MI , unsigned DepReg ) { SUnit * PacketSUDep = MIToSUnit . find ( & MI ) -> second ; for ( auto I : CurrentPacketMIs ) { if ( ! HII -> isPredicated ( * I ) ) continue ; SUnit * PacketSU = MIToSUnit . find ( I ) -> second ; if ( PacketSU -> isSucc ( PacketSUDep ) ) { for ( unsigned i = <NUM_LIT> ; i < PacketSU -> Succs . size ( ) ; ++ i ) { auto & Dep = PacketSU -> Succs [ i ] ; if ( Dep . getSUnit ( ) == PacketSUDep && Dep . getKind ( ) == SDep :: Anti && Dep . getReg ( ) == DepReg ) return true ; } } } return false ;


<s> unsigned getInstSizeInBytes ( const MachineInstr & MI ) const override {


<s> MVT <ISA_LIT>TargetLowering :: getScalarShiftAmountTy ( EVT LHSTy ) const {


<s> const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ;

if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ;


<s> void addTableEntry ( const <ISA_LIT>MemoryFoldTableEntry & Entry , uint16_t ExtraFlags ) { if ( ( Entry . Flags & TB_NO_REVERSE ) == <NUM_LIT> ) Table . push_back ( { Entry . DstOp , Entry . KeyOp , static_cast < uint16_t > ( Entry . Flags | ExtraFlags ) } ) ;


<s> SDValue BasePtr = getMemoryPtr ( Op ) ; SDValue Mask = getNodeMask ( Op ) ; SDValue Chain = getNodeChain ( Op ) ; SDValue AVL = getNodeAVL ( Op ) ; SDValue Data = getStoredValue ( Op ) ; SDValue PassThru = getNodePassthru ( Op ) ; SDValue StrideV = getLoadStoreStride ( Op , CDAG ) ; auto DataVT = * getIdiomaticVectorType ( Op . getNode ( ) ) ; auto Packing = getTypePacking ( DataVT ) ; if ( ! AVL ) AVL = CDAG . getConstant ( DataVT . getVectorNumElements ( ) , <STR_LIT> ) ; if ( ! Mask ) Mask = CDAG . getConstantMask ( Packing , true ) ; if ( IsLoad ) { MVT LegalDataVT = getLegalVectorType ( Packing , DataVT . getVectorElementType ( ) . getSimpleVT ( ) ) ; auto NewLoadV = CDAG . getNode ( <STR_LIT> , { LegalDataVT , <STR_LIT> } , { Chain , BasePtr , StrideV , Mask , AVL } ) ;

if ( ! PassThru || PassThru -> isUndef ( ) ) return NewLoadV ;


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvttsd_si32 ( __m128d __A ) { int result = ( ( __v2df ) __A ) [ <NUM_LIT> ] ;


<s> MinInstAlignment = <NUM_LIT> ; MaxInstLength = ( TT . getArch ( ) == Triple :: amdgcn ) ? <NUM_LIT> : <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes = false ; HasNoDeadStrip = true ; WeakRefDirective = <STR_LIT> ; SupportsDebugInformation = true ;


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; EVT ResVT = N -> getValueType ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) { EVT BCVT = <STR_LIT> , HalfVT = <STR_LIT> ; switch ( ResVT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : BCVT = <STR_LIT> ; HalfVT = <STR_LIT> ; break ; case <STR_LIT> : BCVT = <STR_LIT> ; HalfVT = <STR_LIT> ; break ; case <STR_LIT> : BCVT = <STR_LIT> ; HalfVT = <STR_LIT> ; break ; } if ( BCVT != <STR_LIT> ) { SDValue BC = DAG . getBitcast ( BCVT , Op0 ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , HalfVT , BC ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , Trunc , DAG . getUNDEF ( HalfVT ) ) ; } } if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue X = Op0 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , X , Op1 ) ; } }


<s> EVT EltVT = VT ; if ( VT . isVector ( ) ) EltVT = VT . getVectorElementType ( ) ; std :: vector < Constant * > CV ; if ( EltVT == <STR_LIT> ) { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } else { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ;


<s> if ( isa < FixedVectorType > ( DataType ) && ! ST -> useSVEForFixedLengthVectors ( ) ) return false ;

return isLegalElementTypeForSVE ( DataType -> getScalarType ( ) ) ;


<s> createUnpackShuffleMask ( VT , Unpckh , false , false ) ; if ( isShuffleEquivalent ( Mask , Unpckh , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckl ) ; if ( isShuffleEquivalent ( Mask , Unpckl , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckh ) ; if ( isShuffleEquivalent ( Mask , Unpckh , V1 , V2 ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 ) ;


<s> const <ISA_LIT>Z80RegisterInfo * getRegisterInfo ( ) const override {

return & InstrInfo . getRegisterInfo ( ) ;


<s> var_size = M32R_STACK_ALIGN ( size ) ; args_size = M32R_STACK_ALIGN ( crtl -> outgoing_args_size ) ; pretend_size = crtl -> args . pretend_args_size ; extra_size = FIRST_PARM_OFFSET ( <NUM_LIT> ) ; total_size = extra_size + pretend_size + args_size + var_size ; reg_size = <NUM_LIT> ; gmask = <NUM_LIT> ; fn_type = m32r_compute_function_type ( current_function_decl ) ; interrupt_p = M32R_INTERRUPT_P ( fn_type ) ; for ( regno = <NUM_LIT> ; regno < M32R_MAX_INT_REGS ; regno ++ ) { if ( MUST_SAVE_REGISTER ( regno , interrupt_p ) || ( regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used ) ) { reg_size += UNITS_PER_WORD ; gmask |= <NUM_LIT> << regno ; } } current_frame_info . save_fp = MUST_SAVE_FRAME_POINTER ; current_frame_info . save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used ; reg_size += ( ( current_frame_info . save_fp + current_frame_info . save_lr ) * UNITS_PER_WORD ) ;


<s> if ( ! FLOAT128_2REG_P ( mode ) && ( TARGET_HARD_FLOAT || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , <NUM_LIT> ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( reg_offset_p && ! quad_offset_p && legitimate_lo_sum_address_p ( mode , x , reg_ok_strict ) ) return <NUM_LIT> ;


<s> if ( AsmParser -> isVI ( ) ) return isVReg ( ) ;

else if ( AsmParser -> isGFX9 ( ) ) return isRegKind ( ) || isInlinableImm ( type ) ;


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < <STR_LIT> . getNumRegs ( ) ; ++ i ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( i ) ) markSuperRegs ( Reserved , <STR_LIT> . getRegister ( i ) ) ; } if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( PACStack :: hasPACStackAttribute ( MF ) ) markSuperRegs ( Reserved , PACStack :: CRSub ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;


<s> if ( VA . getLocVT ( ) . getSizeInBits ( ) < <NUM_LIT> ) { return MIRBuilder . buildAnyExt ( LLT :: scalar ( <NUM_LIT> ) , ValVReg ) . getReg ( <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getFunctionAlignment ( const Function * F ) const {

return F -> hasFnAttr ( Attribute :: OptimizeForSize ) ? <NUM_LIT> : <NUM_LIT> ;


<s> unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) + MI . getDesc ( ) . getNumImplicitUses ( ) ; return MI . getNumOperands ( ) == NumOps ;


<s> switch ( Kind ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : Value -= <NUM_LIT> ;


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) return <NUM_LIT> ; unsigned SignBits = <NUM_LIT> - Width -> getZExtValue ( ) + <NUM_LIT> ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Offset || ! Offset -> isNullValue ( ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: max ( SignBits , Op0SignBits ) ; } case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; return Width ? <NUM_LIT> - ( Width -> getZExtValue ( ) & <NUM_LIT> ) : <NUM_LIT> ; } case <STR_LIT> :


<s> SMLoc getStartLoc ( ) const { return StartLoc ;


<s> return nonDbgMICount ( ++ MII , getBundleEnd ( * BundleHead ) ) ;


<s> if ( Width == <NUM_LIT> || Width > <NUM_LIT> ) break ; AttributeSet Attrs = F . getAttributes ( ) ; if ( Attrs . hasAttribute ( AttrIdx , Attribute :: ByVal ) ) continue ; InPhysReg = getNextPhysReg ( InPhysReg , Width ) ; if ( ! InPhysReg ) break ; InVirtReg = getVirtRegFor ( InPhysReg ) ; if ( ! InVirtReg ) continue ;

if ( Attrs . hasAttribute ( AttrIdx , Attribute :: SExt ) ) VRX . insert ( std :: make_pair ( InVirtReg , ExtType ( ExtType :: SExt , Width ) ) ) ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } if ( ! ST . hasMAIInsts ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MaxNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) {

reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ;


<s> static bool isCommutedMOVL ( SDNode * N , bool V2IsSplat = false , bool V2IsUndef = false ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ;

return isCommutedMOVL ( N -> op_begin ( ) , N -> getNumOperands ( ) , V2IsSplat , V2IsUndef ) ;


<s> if ( TARGET_SSE_MATH && ! TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P ( mode ) ) return SSE_CLASS_P ( regclass ) ? regclass : NO_REGS ; if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) != VOIDmode ) { if ( reg_class_subset_p ( regclass , GENERAL_REGS ) ) return regclass ; if ( TARGET_80387 && standard_80387_constant_p ( x ) > <NUM_LIT> ) { if ( regclass == FLOAT_SSE_REGS ) return FLOAT_REGS ;

if ( regclass == FP_TOP_SSE_REGS ) return FP_TOP_REG ;


<s> if ( GET_CODE ( r ) == SUBREG && SUBREG_BYTE ( r ) == <NUM_LIT> ) { rtx ireg = SUBREG_REG ( r ) ; machine_mode imode = GET_MODE ( ireg ) ; if ( imode == PSImode && mode == HImode && byte == <NUM_LIT> ) rv = gen_rtx_SUBREG ( mode , ireg , byte ) ; else rv = simplify_gen_subreg ( mode , ireg , imode , byte ) ; } else if ( GET_CODE ( r ) == MEM ) rv = adjust_address ( r , mode , byte ) ; else if ( GET_CODE ( r ) == SYMBOL_REF && ( byte == <NUM_LIT> || byte == <NUM_LIT> ) && mode == HImode ) { rv = gen_rtx_ZERO_EXTRACT ( HImode , r , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> * byte ) ) ; rv = gen_rtx_CONST ( HImode , r ) ;


<s> return D ( <STR_LIT> , <STR_LIT> , R ( b ) ) ;


<s> static const char * arm_mangle_builtin_scalar_type ( const_tree type ) { int i = <NUM_LIT> ; while ( arm_scalar_builtin_types [ i ] != NULL ) { const char * name = arm_scalar_builtin_types [ i ] ; if ( TREE_CODE ( TYPE_NAME ( type ) ) == TYPE_DECL && DECL_NAME ( TYPE_NAME ( type ) ) && ! strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( TYPE_NAME ( type ) ) ) , name ) ) return arm_scalar_builtin_types [ i ] ; i ++ ;


<s> ref ; ref = DF_REF_NEXT_REG ( ref ) ) { if ( NONDEBUG_INSN_P ( DF_REF_INSN ( ref ) ) && ! bitmap_bit_p ( candidates , DF_REF_INSN_UID ( ref ) ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , regno , DF_REF_INSN_UID ( ref ) ) ; bitmap_set_bit ( regs , regno ) ; break ;


<s> if ( LDepth != RDepth ) { DEBUG ( dbgs ( ) << <STR_LIT> << left -> NodeNum << <STR_LIT> << LDepth << <STR_LIT> << right -> NodeNum << <STR_LIT> << RDepth << <STR_LIT> ) ;

return LDepth < RDepth ? <NUM_LIT> : - <NUM_LIT> ;


<s> if ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( ( addr ) , <NUM_LIT> ) ) == MULT ) return true ; return false ;


<s> case <STR_LIT> : { unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MBB . erase ( MI ) ; return true ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1SubHi = TRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src1SubLo = TRI . getSubReg ( Src1Reg , <STR_LIT> ) ; unsigned Src2SubHi = TRI . getSubReg ( Src2Reg , <STR_LIT> ) ; unsigned Src2SubLo = TRI . getSubReg ( Src2Reg , <STR_LIT> ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubHi ) . addReg ( Src2SubHi ) ;

BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( Src1SubLo ) . addReg ( Src2SubLo ) ;


<s> void <ISA_LIT>AsmPrinter :: printPICLabel ( const MachineInstr * MI , unsigned Op , raw_ostream & O ) { PrintPICBaseSymbol ( O ) ; O << '\n' ;


<s> Chain = Result . getValue ( <NUM_LIT> ) ; InFlag = Result . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Result , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops1 [ ] = { Chain , DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) , DAG . getRegister ( <STR_LIT> , PtrVT ) , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops1 , <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

return DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , PtrVT , InFlag ) ;


<s> bool IsShortVector ( unsigned ValNo ) {


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( ! DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasBulkMemory ( ) ) return SDValue ( ) ; SDValue MemIdx = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Chain , MemIdx , MemIdx , Dst , Src , DAG . getZExtOrTrunc ( Size , DL , <STR_LIT> ) } ) ;


<s> unsigned getNumFixupKinds ( ) const { return <NUM_LIT> ;


<s> if ( mode == PSImode ) return <NUM_LIT> ; if ( mode == CPSImode ) return <NUM_LIT> ; return msp430_hard_regno_nregs ( regno , mode ) ;


<s> if ( Addr . isRegBase ( ) ) { unsigned Reg = Addr . getReg ( ) ; if ( Reg == <NUM_LIT> ) { Reg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; unsigned Opc = Subtarget -> hasAddr64 ( ) ? <STR_LIT> : <STR_LIT> ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , Reg ) . addImm ( <NUM_LIT> ) ;


<s> static inline unsigned getUBit ( uint32_t insn ) { return ( insn >> <STR_LIT> ) & <NUM_LIT> ;


<s> MachineInstr * VCMP = VCMPOpcodeToVPT ( Divergent -> getOpcode ( ) ) != <NUM_LIT> ? Divergent : nullptr ; if ( DivergentNextIsPredicated ) { if ( ! VCMP ) { MachineInstrBuilder MIB = BuildMI ( * Divergent -> getParent ( ) , Divergent , Divergent -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addImm ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . BlockMasksToRecompute . insert ( MIB . getInstr ( ) ) ; } else { ReplaceVCMPWithVPT ( VCMP , VCMP ) ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST ) ; LoLoop . ToRemove . insert ( VPST ) ; } else if ( Block . containsVCTP ( ) ) { MachineInstr * VPST = Insts . front ( ) ; if ( Block . size ( ) == <NUM_LIT> ) { assert ( VPST -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; LoLoop . ToRemove . insert ( VPST ) ; } else LoLoop . BlockMasksToRecompute . insert ( VPST ) ; } else if ( Insts . front ( ) -> getOpcode ( ) == <STR_LIT> ) { MachineInstr * VPST = Insts . front ( ) ; auto Next = ++ MachineBasicBlock :: iterator ( VPST ) ; assert ( getVPTInstrPredicate ( * Next ) != <STR_LIT> && <STR_LIT> ) ; ( void ) Next ; MachineInstr * VprDef = RDA -> getUniqueReachingMIDef ( VPST , <STR_LIT> ) ; if ( VprDef && VCMPOpcodeToVPT ( VprDef -> getOpcode ( ) ) && ! LoLoop . ToRemove . contains ( VprDef ) ) { MachineInstr * VCMP = VprDef ; if ( ! std :: any_of ( ++ MachineBasicBlock :: iterator ( VCMP ) , MachineBasicBlock :: iterator ( VPST ) , hasVPRUse ) && RDA -> hasSameReachingDef ( VCMP , VPST , VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) && RDA -> hasSameReachingDef ( VCMP , VPST , VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { ReplaceVCMPWithVPT ( VCMP , VPST ) ;


<s> SDValue PICLabel = DAG . getTargetConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ; auto * LRWGRS = DAG . getMachineNode ( <STR_LIT> , DL , { Ty , Ty } , { CAddr , PICLabel } ) ; auto LRWADDGRS = DAG . getNode ( <STR_LIT> , DL , Ty , SDValue ( LRWGRS , <NUM_LIT> ) , SDValue ( LRWGRS , <NUM_LIT> ) ) ;

Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , LRWADDGRS , MachinePointerInfo ( N -> getGlobal ( ) ) ) ;


<s> case cortexr4f : case cortexr5 : case genericv7a : case cortexa5 : case cortexa7 : case cortexa8 : case cortexa9 : case cortexa12 : case cortexa17 : case cortexa53 : case fa726te : case marvell_pj4 : return <NUM_LIT> ; default : return <NUM_LIT> ; }


<s> if ( rest == NULL ) return - <NUM_LIT> ; char * after ; unsigned fint = strtol ( rest + <NUM_LIT> , & after , <NUM_LIT> ) ;

if ( after == rest + <NUM_LIT> ) return - <NUM_LIT> ;


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . isVector = isVector ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;

return Infos [ Kind - FirstTargetFixupKind ] ;


<s> bool Changed = false ; auto Children = Region -> getChildren ( ) ; for ( auto CI : * Children ) {


<s> static __inline__ double __fnmsub ( double x , double y , double z ) { double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r ;


<s> assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget -> is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned Opc ; if ( ! IsSigned && isIntegerTypeFTOL ( DstTy ) ) Opc = <STR_LIT> ; else switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; EVT TheVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( isScalarFPTypeInSSEReg ( TheVT ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , DL , Value , StackSlot , MachinePointerInfo :: getFixedStack ( SSFI ) , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( TheVT ) } ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , MemSize , MemSize ) ; Value = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , DstTy , MMO ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOStore , MemSize , MemSize ) ;


<s> getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget -> isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ;

return MCSymbolRefExpr :: Create ( MF -> getPICBaseSymbol ( ) , Ctx ) ;


<s> while ( ++ I != E && I -> isInsideBundle ( ) ) { assert ( ! I -> isBundle ( ) && <STR_LIT> ) ; Size += GetInstSizeInBytes ( & * I ) ;


<s> rtx cmp0 = operands [ <NUM_LIT> ] ; rtx cmp1 = operands [ <NUM_LIT> ] ; rtx cmp ; int invert ; rtx label1 , label2 ; switch ( mode ) { case DFmode : default : fatal_insn ( <STR_LIT> , gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0 , cmp1 ) ) ; case SImode : invert = FALSE ; cmp = gen_int_relational ( test_code , cmp0 , cmp1 , & invert ) ; break ; case SFmode : if ( ! TARGET_HARD_FLOAT ) fatal_insn ( <STR_LIT> , gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0 , cmp1 ) ) ; invert = FALSE ; cmp = gen_float_relational ( test_code , cmp0 , cmp1 ) ; break ;


<s> xor_constant = <NUM_LIT> << ( <NUM_LIT> - shift_amount - <NUM_LIT> ) ; and_constant = ( code == ASHIFT ? <NUM_LIT> - ( <NUM_LIT> << shift_amount ) : ( <NUM_LIT> << ( <NUM_LIT> - shift_amount ) ) - <NUM_LIT> ) ; switch ( qimode ) { case V16QImode : himode = V8HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv8hi3 : ( code == ASHIFTRT ) ? gen_ashrv8hi3 : gen_lshrv8hi3 ) ; gen_and = gen_andv16qi3 ; gen_xor = gen_xorv16qi3 ; gen_sub = gen_subv16qi3 ; break ; case V32QImode : himode = V16HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv16hi3 : ( code == ASHIFTRT ) ? gen_ashrv16hi3 : gen_lshrv16hi3 ) ; gen_and = gen_andv32qi3 ; gen_xor = gen_xorv32qi3 ; gen_sub = gen_subv32qi3 ; break ; case V64QImode : himode = V32HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv32hi3 : ( code == ASHIFTRT ) ? gen_ashrv32hi3 : gen_lshrv32hi3 ) ; gen_and = gen_andv64qi3 ; gen_xor = gen_xorv64qi3 ; gen_sub = gen_subv64qi3 ; break ; default : gcc_unreachable ( ) ; } tmp = gen_reg_rtx ( himode ) ; vec_const_and = gen_reg_rtx ( qimode ) ; op1_subreg = lowpart_subreg ( himode , op1 , qimode ) ; emit_insn ( gen_shift ( tmp , op1_subreg , op2 ) ) ; emit_move_insn ( dest , simplify_gen_subreg ( qimode , tmp , himode , <NUM_LIT> ) ) ; emit_move_insn ( vec_const_and , ix86_build_const_vector ( qimode , true , gen_int_mode ( and_constant , QImode ) ) ) ; emit_insn ( gen_and ( dest , dest , vec_const_and ) ) ; if ( code == ASHIFTRT ) { vec_const_xor = gen_reg_rtx ( qimode ) ;

emit_move_insn ( vec_const_xor , ix86_build_const_vector ( qimode , true , gen_int_mode ( xor_constant , QImode ) ) ) ;


<s> if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ;

return TargetLoweringBase :: getMaxSupportedInterleaveFactor ( ) ;


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const {

if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> Val = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; } InVals . push_back ( Val ) ;


<s> virtual unsigned int execute ( function * ) { return arc_predicate_delay_insns ( ) ;


<s> if ( ! m_vector_manager -> all_same_ratio_p ( m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ) return false ; if ( ! m_vector_manager -> all_same_avl_p ( cfg_bb , m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ) return false ; size_t expr_id = bitmap_first_set_bit ( m_vector_manager -> vector_avin [ cfg_bb -> index ] ) ; if ( ! m_vector_manager -> vector_exprs [ expr_id ] -> same_vlmax_p ( info ) ) return false ; if ( ! m_vector_manager -> vector_exprs [ expr_id ] -> compatible_avl_p ( info ) ) return false ; edge e ; edge_iterator ei ; bool all_valid_p = true ; FOR_EACH_EDGE ( e , ei , cfg_bb -> preds ) { if ( bitmap_empty_p ( m_vector_manager -> vector_avout [ e -> src -> index ] ) ) { all_valid_p = false ; break ; }


<s> EVT VT = Store -> getMemoryVT ( ) ; if ( VT == <STR_LIT> ) { return DAG . getTruncStore ( Store -> getChain ( ) , DL , DAG . getSExtOrTrunc ( Store -> getValue ( ) , DL , <STR_LIT> ) , Store -> getBasePtr ( ) , <STR_LIT> , Store -> getMemOperand ( ) ) ; } assert ( VT . isVector ( ) && Store -> getValue ( ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; unsigned AS = Store -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , AS , Store -> getAlignment ( ) ) ) { return expandUnalignedStore ( Store , DAG ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS : AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( AS == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; } else if ( AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorStore ( Store , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ;


<s> void addImmThumbSROperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> if ( ! MO . isImplicit ( ) && MO . getReg ( ) == AMDGPU :: EXEC ) ++ ConstantBusCount ; if ( MO . getReg ( ) == AMDGPU :: M0 || MO . getReg ( ) == AMDGPU :: VCC || ( ! MO . isImplicit ( ) && ( AMDGPU :: SGPR_32RegClass . contains ( MO . getReg ( ) ) || AMDGPU :: SGPR_64RegClass . contains ( MO . getReg ( ) ) ) ) ) { if ( SGPRUsed != MO . getReg ( ) ) { ++ ConstantBusCount ; SGPRUsed = MO . getReg ( ) ; } } } if ( isLiteralConstant ( MO ) ) ++ ConstantBusCount ; } if ( ConstantBusCount > <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } if ( Src1Idx != - <NUM_LIT> && ( isVOP2 ( Opcode ) || isVOPC ( Opcode ) ) ) { const MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( Src1 . isImm ( ) || Src1 . isFPImm ( ) ) { ErrInfo = <STR_LIT> ; return false ; } } if ( isVOP3 ( Opcode ) ) { if ( Src0Idx != - <NUM_LIT> && isLiteralConstant ( MI -> getOperand ( Src0Idx ) ) ) { ErrInfo = <STR_LIT> ; return false ;


<s> int avr_accumulate_outgoing_args ( void ) { if ( ! cfun ) return TARGET_ACCUMULATE_OUTGOING_ARGS ; return ( TARGET_ACCUMULATE_OUTGOING_ARGS && ! ( cfun -> calls_setjmp || cfun -> has_nonlocal_label ) ) ;


<s> static bool arm_macro_fusion_p ( void ) {


<s> return __builtin_shuffle ( __a , __b , ( uint32x2_t ) { <NUM_LIT> , <NUM_LIT> } ) ;


<s> return <NUM_LIT> ; } else { rtx temp = subtargets ? gen_reg_rtx ( mode ) : target ; if ( TARGET_USE_MOVT ) arm_emit_movpair ( temp , GEN_INT ( val ) ) ; else emit_set_insn ( temp , GEN_INT ( val ) ) ; if ( code == MINUS ) emit_set_insn ( target , gen_rtx_MINUS ( mode , temp , source ) ) ; else emit_set_insn ( target , gen_rtx_fmt_ee ( code , mode , source , temp ) ) ; return <NUM_LIT> ; } }


<s> FnStartLoc = L ; getParser ( ) . getStreamer ( ) . EmitFnStart ( ) ;


<s> Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; BaseReg = & LdSt . getOperand ( <NUM_LIT> ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ;


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerREM ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> :

if ( Subtarget -> isTargetWindows ( ) && ! Op . getValueType ( ) . isVector ( ) ) return LowerDIV_Windows ( Op , DAG , true ) ;


<s> unsigned CommOpIdx1 = <NUM_LIT> ; unsigned CommOpIdx2 = TargetInstrInfo :: CommuteAnyOperandIndex ; if ( ! TII -> findCommutedOpIndices ( * MI , CommOpIdx1 , CommOpIdx2 ) || MI -> getOperand ( CommOpIdx2 ) . getReg ( ) != Reg0 ) return false ; MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI , false , CommOpIdx1 , CommOpIdx2 ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { Register Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; Register PredReg ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ;

HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ;


<s> static SDValue LowerMSCATTER ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { assert ( Subtarget -> hasAVX512 ( ) && <STR_LIT> ) ; MaskedScatterSDNode * N = cast < MaskedScatterSDNode > ( Op . getNode ( ) ) ; EVT VT = N -> getValue ( ) . getValueType ( ) ; assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) {


<s> bool isSSrc32 ( ) const { return isImm ( ) || ( isReg ( ) && isRegClass ( AMDGPU :: SReg_32RegClassID ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { std :: cout << <STR_LIT> << std :: endl ;


<s> static MCOperand GetSymbolRef ( const MachineOperand & MO , const MCSymbol * Symbol , <ISA_LIT>AsmPrinter & Printer ) { MCContext & MC = Printer . OutContext ; const MCExpr * ME ; ME = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , MC ) ;

if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: CreateAdd ( ME , MCConstantExpr :: Create ( MO . getOffset ( ) , MC ) , MC ) ;


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ;

Function * ThreadPointerFunc = <STR_LIT> ( M , <STR_LIT> ) ;


<s> if ( Node -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; }


<s> progname = <STR_LIT> ; gcc_init_libintl ( ) ; diagnostic_initialize ( global_dc , <NUM_LIT> ) ; if ( atexit ( mkoffload_cleanup ) != <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> ) ; const char * host_compiler = getenv ( <STR_LIT> ) ; if ( ! host_compiler ) fatal_error ( input_location , <STR_LIT> ) ; const char * target_driver_name = GCC_INSTALL_NAME ; char * target_compiler = find_target_compiler ( target_driver_name ) ; if ( target_compiler == NULL ) fatal_error ( input_location , <STR_LIT> , target_driver_name ) ; expandargv ( & argc , & argv ) ; for ( int i = <NUM_LIT> ; i < argc ; i ++ ) { if ( startswith ( argv [ i ] , STR ) ) { if ( strcmp ( argv [ i ] + strlen ( STR ) , <STR_LIT> ) == <NUM_LIT> ) offload_abi = OFFLOAD_ABI_LP64 ; else if ( strcmp ( argv [ i ] + strlen ( STR ) , <STR_LIT> ) == <NUM_LIT> ) offload_abi = OFFLOAD_ABI_ILP32 ; else fatal_error ( input_location , <STR_LIT> STR ) ; } else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) save_temps = true ; else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) verbose = true ; else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> && i + <NUM_LIT> < argc ) dumppfx = argv [ ++ i ] ; else if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> && i + <NUM_LIT> < argc ) out_obj_filename = argv [ ++ i ] ; } if ( ! out_obj_filename ) fatal_error ( input_location , <STR_LIT> ) ; if ( ! dumppfx ) dumppfx = out_obj_filename ; const char * target_so_filename = prepare_target_image ( target_compiler , argc , argv ) ; const char * host_descr_filename = generate_host_descr_file ( host_compiler ) ; struct obstack argv_obstack ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , host_descr_filename ) ; obstack_ptr_grow ( & argv_obstack , target_so_filename ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , out_obj_filename ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; char * * new_argv = XOBFINISH ( & argv_obstack , char * * ) ; fork_execute ( new_argv [ <NUM_LIT> ] , new_argv , false , NULL ) ; obstack_free ( & argv_obstack , NULL ) ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , symbols [ <NUM_LIT> ] ) ;


<s> int first_reg_to_save ( void ) { int first_reg ;

for ( first_reg = <NUM_LIT> ; first_reg <= <NUM_LIT> ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ;


<s> } } else { unsigned NewOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) || ( OffReg && TRI -> regsOverlap ( EvenReg , OffReg ) ) ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) && ( ! OffReg || ! TRI -> regsOverlap ( OddReg , OffReg ) ) ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , BaseReg , false , OffReg , false , Pred , PredReg , TII ) ; InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , BaseReg , BaseKill , OffReg , OffKill , Pred , PredReg , TII ) ; } else { InsertLDR_STR ( MBB , MBBI , OffImm , isLd , dl , NewOpc , EvenReg , EvenDeadKill , BaseReg , false , OffReg , false , Pred , PredReg , TII ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , dl , NewOpc , OddReg , OddDeadKill , BaseReg , BaseKill , OffReg , OffKill , Pred , PredReg , TII ) ; } if ( isLd ) ++ NumLDRD2LDR ; else ++ NumSTRD2STR ; } MBBI = prior ( MBBI ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>leTarget ( ) ) ;

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>beTarget ( ) ) ;


<s> PostOptimizer ( RelooperAlgorithm * ParentInit ) : Parent ( ParentInit ) {


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>FrameLowering * TFI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getSubtarget ( ) . getFrameLowering ( ) ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( TFI -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } assert ( ! MI . isDebugValue ( ) && <STR_LIT> ) ; bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ;

<STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ;


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ;

SDValue NegSize = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getConstant ( <NUM_LIT> , dl , PtrVT ) , Size ) ;


<s> if ( <ISA_LIT>SinglePathInfo :: isEnabled ( ) ) { addPass ( create<ISA_LIT>SPMarkPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>SinglePathInfoPass ( get<ISA_LIT>TargetMachine ( ) ) ) ;

addPass ( create<ISA_LIT>SPPreparePass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> SDLoc DL ( N ) ; EVT ValVT = Val . getValueType ( ) ; if ( ValVT . isVector ( ) ) { if ( ! ValVT . isSimple ( ) ) return SDValue ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } MemSDNode * MemSD = cast < MemSDNode > ( N ) ; const DataLayout * TD = getDataLayout ( ) ; unsigned Align = MemSD -> getAlignment ( ) ; unsigned PrefAlign = TD -> getPrefTypeAlignment ( ValVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return SDValue ( ) ; } unsigned Opcode = <NUM_LIT> ; EVT EltVT = ValVT . getVectorElementType ( ) ; unsigned NumElts = ValVT . getVectorNumElements ( ) ; bool NeedExt = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) NeedExt = true ; switch ( NumElts ) { default : return SDValue ( ) ; case <NUM_LIT> : Opcode = <STR_LIT> ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; break ; } } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue ExtVal = DAG . getNode ( <STR_LIT> , DL , EltVT , Val , DAG . getIntPtrConstant ( i ) ) ; if ( NeedExt ) ExtVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ExtVal ) ; Ops . push_back ( ExtVal ) ; } Ops . append ( N -> op_begin ( ) + <NUM_LIT> , N -> op_end ( ) ) ; SDValue NewSt = DAG . getMemIntrinsicNode ( Opcode , DL , DAG . getVTList ( <STR_LIT> ) , Ops , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ; return NewSt ; }


<s> bool isVISrc_256V2INT32 ( ) const { return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> <ISA_LIT>StoreResults ( ) : MachineFunctionPass ( ID ) {


<s> unsigned int has_highgprs = <NUM_LIT> ; unsigned int has_dfp = <NUM_LIT> ; unsigned int has_te = <NUM_LIT> ; unsigned int has_vx = <NUM_LIT> ; unsigned int has_opt_esa_zarch = <NUM_LIT> ; int i ; if ( argc < <NUM_LIT> ) return NULL ; arch = strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ; if ( ! arch && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) ) return NULL ; for ( i = <NUM_LIT> ; i < argc ; i ++ ) if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) has_opt_esa_zarch = <NUM_LIT> ; f = fopen ( <STR_LIT> , <STR_LIT> ) ; if ( f == NULL ) return NULL ; for ( has_features = <NUM_LIT> , has_processor = <NUM_LIT> ; ( has_features == <NUM_LIT> || has_processor == <NUM_LIT> ) && fgets ( buf , sizeof ( buf ) , f ) != NULL ; ) { if ( has_processor == <NUM_LIT> && strncmp ( buf , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { const char * p ; long machine_id ; p = strstr ( buf , <STR_LIT> ) ; if ( p == NULL ) continue ; p += <NUM_LIT> ; has_processor = <NUM_LIT> ; machine_id = strtol ( p , NULL , <NUM_LIT> ) ; switch ( machine_id ) { case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; is_cpu_z9_109 = <NUM_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { auto & MBB = * MI . getParent ( ) ; auto DL = MI . getDebugLoc ( ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: LOAD_STACK_GUARD : { assert ( Subtarget . isTargetLinux ( ) && <STR_LIT> ) ; const int64_t Offset = Subtarget . is<ISA_LIT>64 ( ) ? - <NUM_LIT> : - <NUM_LIT> ; const unsigned Reg = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( get ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Offset ) . addReg ( Reg ) ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasP9Vector ( ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && isAnImmediateOperand ( MI . getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ; return expandVSXMemPseudo ( MI ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasP8Vector ( ) && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; return expandVSXMemPseudo ( MI ) ; } case <STR_LIT> : case <STR_LIT> : {

assert ( Subtarget . hasVSX ( ) && <STR_LIT> ) ;


<s> if ( ChangeTo<ISA_LIT>16 ) { if ( PreviousIn<ISA_LIT>16Mode ) return ; OverrideMode = <ISA_LIT>16Override ; PreviousIn<ISA_LIT>16Mode = true ; setHelperClasses<ISA_LIT>16 ( ) ; return ; } else if ( ChangeToNo<ISA_LIT>16 ) { if ( ! PreviousIn<ISA_LIT>16Mode ) return ; OverrideMode = No<ISA_LIT>16Override ; PreviousIn<ISA_LIT>16Mode = false ; setHelperClasses<ISA_LIT>SE ( ) ; return ; } else { if ( OverrideMode == NoOverride ) return ; OverrideMode = NoOverride ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( in<ISA_LIT>16Mode ( ) && ! PreviousIn<ISA_LIT>16Mode ) { setHelperClasses<ISA_LIT>16 ( ) ; PreviousIn<ISA_LIT>16Mode = true ;

} else if ( ! in<ISA_LIT>16Mode ( ) && PreviousIn<ISA_LIT>16Mode ) {


<s> static rtx F ( rtx x ) { RTX_FRAME_RELATED_P ( x ) = <NUM_LIT> ;