<s> } return ( ( val & ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << <NUM_LIT> ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << <NUM_LIT> ) ) == val ) ;


<s> static void avr_option_override ( void ) { if ( avr_strict_X ) flag_caller_saves = <NUM_LIT> ; maybe_set_param_value ( PARAM_ALLOW_STORE_DATA_RACES , <NUM_LIT> , global_options . x_param_values , global_options_set . x_param_values ) ; if ( ( flag_unwind_tables || flag_non_call_exceptions || flag_asynchronous_unwind_tables ) && ! ACCUMULATE_OUTGOING_ARGS ) { flag_omit_frame_pointer = <NUM_LIT> ; } if ( flag_pic == <NUM_LIT> ) warning ( OPT_fpic , <STR_LIT> ) ; if ( flag_pic == <NUM_LIT> ) warning ( OPT_fPIC , <STR_LIT> ) ; if ( flag_pie == <NUM_LIT> ) warning ( OPT_fpie , <STR_LIT> ) ; if ( flag_pie == <NUM_LIT> ) warning ( OPT_fPIE , <STR_LIT> ) ; avr_gasisr_prologues = <NUM_LIT> ; if ( ! avr_set_core_architecture ( ) ) return ; avr_addr . sreg = <NUM_LIT> + avr_arch -> sfr_offset ; avr_addr . rampz = <NUM_LIT> + avr_arch -> sfr_offset ; avr_addr . rampy = <NUM_LIT> + avr_arch -> sfr_offset ;


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitVectorConcat ( Optional < unsigned > Dst , unsigned Op1 , unsigned Op2 , MachineIRBuilder & MIRBuilder ) const { MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; const LLT Op1Ty = MRI . getType ( Op1 ) ; const LLT Op2Ty = MRI . getType ( Op2 ) ; if ( Op1Ty != Op2Ty ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } assert ( Op1Ty . isVector ( ) && <STR_LIT> ) ; if ( Op1Ty . getSizeInBits ( ) >= <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Op1Ty . getSizeInBits ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } const LLT ScalarTy = LLT :: scalar ( Op1Ty . getSizeInBits ( ) ) ; const RegisterBank & FPRBank = * RBI . getRegBank ( Op1 , MRI , TRI ) ; const TargetRegisterClass * DstRC = getMinClassForRegBank ( FPRBank , Op1Ty . getSizeInBits ( ) * <NUM_LIT> ) ; MachineInstr * WidenedOp1 = emitScalarToVector ( ScalarTy . getSizeInBits ( ) , DstRC , Op1 , MIRBuilder ) ; MachineInstr * WidenedOp2 = emitScalarToVector ( ScalarTy . getSizeInBits ( ) , DstRC , Op2 , MIRBuilder ) ; if ( ! WidenedOp1 || ! WidenedOp2 ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } unsigned InsertOpc , InsSubRegIdx ; std :: tie ( InsertOpc , InsSubRegIdx ) = getInsertVecEltOpInfo ( FPRBank , ScalarTy . getSizeInBits ( ) ) ; if ( ! Dst ) Dst = MRI . createVirtualRegister ( DstRC ) ; auto InsElt = MIRBuilder . buildInstr ( InsertOpc , { * Dst } , { WidenedOp1 -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) . addImm ( <NUM_LIT> ) . addUse ( WidenedOp2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) ;

constrainSelectedInstRegOperands ( * InsElt , TII , TRI , RBI ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( nullptr ) , DefaultSubtarget ( TT , CPU , FS , isLittle , this ) , No<ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , this ) , <ISA_LIT>16Subtarget ( TT , CPU , FS . empty ( ) ? <STR_LIT> : FS . str ( ) + <STR_LIT> , isLittle , this ) { Subtarget = & DefaultSubtarget ;


<s> bool SawLoad = false ; bool SawStore = false ; for ( ReverseIter I ( Slot ) ; I != MBB . rend ( ) ; ++ I ) { if ( I -> isDebugValue ( ) ) continue ; if ( terminateSearch ( * I ) ) break ; if ( delayHasHazard ( * I , SawLoad , SawStore , RegDefs , RegUses ) ) continue ; Filler = llvm :: next ( I ) . base ( ) ; return true ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI , StringRef C ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_HEXAGON , true ) , CPU ( C ) {


<s> puxc2 ( unsigned i , unsigned j , unsigned k ) : tripleChange ( true , false , false , i , j , k ) {


<s> x = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( x ) = <NUM_LIT> ; return x ;


<s> const char * * new_link_args = ( const char * * ) xcalloc ( link_arg_max + <NUM_LIT> , sizeof ( char * ) ) ; for ( i = <NUM_LIT> ; i <= link_arg_max ; i ++ ) new_link_args [ i ] = link_args [ i ] ; if ( link_args ) free ( link_args ) ;


<s> if ( isLoopInstr ( instr ) ) { nop = <NUM_LIT> ; } for ( unsigned int i = <NUM_LIT> ; i < nop ; i ++ ) { if ( MOPIsLoopRegUse ( & instr -> getOperand ( i ) ) ) { return true ; } }


<s> return __builtin_mve_vcvtq_to_f_sv8hf ( __a ) ;


<s> return ( __m256i ) __builtin_ia32_pternlogq256_mask ( ( __v4di ) __A , ( __v4di ) __B , ( __v4di ) __C , ( unsigned char ) __imm , ( __mmask8 ) - <NUM_LIT> ) ;


<s> Desc . Regs . push_back ( op . getReg ( ) ) ; break ; } if ( MI -> modifiesRegister ( <STR_LIT> , TRI ) ) return Optional < BlockBRNZ > ( ) ; } if ( Desc . Regs . size ( ) != <NUM_LIT> ) { return Optional < BlockBRNZ > ( ) ; } const Register & Reg0 = Desc . Regs [ <NUM_LIT> ] ; while ( ++ MI != MBB . instr_rend ( ) ) { if ( MI -> isPHI ( ) ) { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg0 ) { unsigned NumOperands = MI -> getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOperands ; I += <NUM_LIT> ) {

Desc . Regs . push_back ( MI -> getOperand ( I ) . getReg ( ) ) ;


<s> for ( ; flag -> name != NULL ; flag ++ ) { if ( length == strlen ( flag -> name ) && ! strncmp ( flag -> name , token , length ) ) return flag -> flag ; } error ( <STR_LIT> , option_name , token ) ; return <NUM_LIT> ;


<s> if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; for ( auto & CS : reverse ( CSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; }


<s> std :: string T = PAN :: getFrameSectionName ( FnName ) ;

return get<ISA_LIT>Section ( T . c_str ( ) , SectionKind :: getDataRel ( ) ) ;


<s> std :: string cloneVarName = Var ; std :: string cloneFnName = getCloneFnName ( Fn ) ;

cloneVarName . replace ( cloneVarName . find ( Fn ) , Fn . length ( ) , cloneFnName ) ;


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; addPass ( createSinkingPass ( ) ) ; addPass ( create<ISA_LIT>TypeRewriter ( ) ) ; addPass ( create<ISA_LIT>AnnotateControlFlowPass ( ) ) ; return false ;


<s> Reg = o . Reg ; break ; case Immediate : Imm = o . Imm ; break ; case Token : Tok = o . Tok ; break ; }


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } ) ;


<s> bool isSystemRegister ( ) const { return Kind == KindTy :: SystemRegister ;


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , <STR_LIT> Flags ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ;

const bool IsImmutable = ! Flags . isByVal ( ) ;


<s> MCOperand <ISA_LIT>MCInstLower :: LowerSymbolOperand ( const MachineOperand & MO , MachineOperandType MOTy , unsigned Offset ) const {


<s> TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp0 , TmpOp1 ) ; break ; case <STR_LIT> : Invert = true ; case <STR_LIT> : TmpOp0 = Op0 ; TmpOp1 = Op1 ; Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp1 , TmpOp0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , TmpOp0 , TmpOp1 ) ; break ; } } else { switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( Opc == <STR_LIT> ) { SDValue AndOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) AndOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) AndOp = Op1 ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) AndOp = AndOp . getOperand ( <NUM_LIT> ) ; if ( AndOp . getNode ( ) && AndOp . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , AndOp . getOperand ( <NUM_LIT> ) ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , AndOp . getOperand ( <NUM_LIT> ) ) ; Invert = ! Invert ; } } } if ( Swap ) std :: swap ( Op0 , Op1 ) ; SDValue SingleOp ; if ( <STR_LIT> ( Op1 . getNode ( ) ) ) SingleOp = Op0 ; else if ( <STR_LIT> ( Op0 . getNode ( ) ) ) { if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) Opc = <STR_LIT> ; SingleOp = Op1 ; } SDValue Result ; if ( SingleOp . getNode ( ) ) { switch ( Opc ) { case <STR_LIT> :

Result = DAG . getNode ( <STR_LIT> , dl , CmpVT , SingleOp ) ; break ;


<s> continue ; } int RootMaskedIdx = RootMask [ RootIdx ] * RootRatio + i % RootRatio ; int OpIdx = RootMaskedIdx / OpRatio ; if ( OpMask [ OpIdx ] < <NUM_LIT> ) { Mask . push_back ( OpMask [ OpIdx ] ) ; continue ; } Mask . push_back ( OpMask [ OpIdx ] * OpRatio + RootMaskedIdx % OpRatio ) ; } if ( llvm :: all_of ( Mask , [ ] ( int Idx ) { return Idx == SM_SentinelUndef ; } ) ) { DCI . CombineTo ( Root . getNode ( ) , DAG . getUNDEF ( Root . getValueType ( ) ) ) ; return true ; } if ( llvm :: all_of ( Mask , [ ] ( int Idx ) { return Idx < <NUM_LIT> ; } ) ) { DCI . CombineTo ( Root . getNode ( ) , getZeroVector ( Root . getSimpleValueType ( ) , Subtarget , DAG , SDLoc ( Root ) ) ) ; return true ; } int MaskSize = Mask . size ( ) ; bool UseInput0 = std :: any_of ( Mask . begin ( ) , Mask . end ( ) , [ MaskSize ] ( int Idx ) { return <NUM_LIT> <= Idx && Idx < MaskSize ; } ) ; bool UseInput1 = std :: any_of ( Mask . begin ( ) , Mask . end ( ) , [ MaskSize ] ( int Idx ) { return MaskSize <= Idx ; } ) ; if ( UseInput0 && UseInput1 ) return false ; else if ( UseInput1 ) { std :: swap ( Input0 , Input1 ) ; ShuffleVectorSDNode :: commuteMask ( Mask ) ; } assert ( Input0 && <STR_LIT> ) ; HasVariableMask |= isTargetShuffleVariableMask ( Op . getOpcode ( ) ) ; if ( Op -> isOnlyUserOf ( Input0 . getNode ( ) ) && combine<ISA_LIT>ShufflesRecursively ( Input0 , Root , Mask , Depth + <NUM_LIT> , HasVariableMask , DAG , DCI , Subtarget ) ) return true ; SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > <NUM_LIT> && canWidenShuffleElements ( Mask , WidenedMask ) ) { Mask = std :: move ( WidenedMask ) ;


<s> } else { if ( bundleSize == HEXAGON_PACKET_SIZE - <NUM_LIT> && fixupCount ) return false ; } if ( DisableShuffle ) return false ; <ISA_LIT>MCShuffler MCS ( MCII , STI , MCB , AddMI ) ; if ( ! MCS . reshuffleTo ( MCB ) ) { unsigned shuffleError = MCS . getError ( ) ; switch ( shuffleError ) { default : return false ;


<s> MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( Off ) . addImm ( <NUM_LIT> ) ; } BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskUpper ) . addReg ( <STR_LIT> ) . addImm ( MaskImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask ) . addReg ( MaskUpper ) . addReg ( ShiftAmt ) ;

BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Mask2 ) . addReg ( <STR_LIT> ) . addReg ( Mask ) ;


<s> memset ( rws_sum , <NUM_LIT> , sizeof ( rws_sum ) ) ; first_instruction = <NUM_LIT> ;


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS << Offset ; }

if ( ( Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ) || ( Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ) ) OS << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printPCRelTLSOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printPCRelOperand ( MI , OpNum , O ) ; if ( ( unsigned ) OpNum + <NUM_LIT> < MI -> getNumOperands ( ) ) {

const MCOperand & MO = MI -> getOperand ( OpNum + <NUM_LIT> ) ;


<s> I . setLatency ( Lat ) ; T . setSUnit ( Src ) ; auto F = find ( Dst -> Preds , T ) ;

assert ( F != Dst -> Preds . end ( ) ) ;


<s> } auto VarEntry = std :: make_unique < BTFKindVar > ( Global . getName ( ) , GVTypeId , GVarInfo ) ; uint32_t VarId = addType ( std :: move ( VarEntry ) ) ; assert ( ! SecName . empty ( ) ) ; if ( DataSecEntries . find ( std :: string ( SecName ) ) == DataSecEntries . end ( ) ) { DataSecEntries [ std :: string ( SecName ) ] = std :: make_unique < BTFKindDataSec > ( Asm , std :: string ( SecName ) ) ; } const DataLayout & DL = Global . getParent ( ) -> getDataLayout ( ) ; uint32_t Size = DL . getTypeAllocSize ( Global . getType ( ) -> getElementType ( ) ) ; DataSecEntries [ std :: string ( SecName ) ] -> addVar ( VarId , Asm -> getSymbol ( & Global ) , Size ) ; }


<s> } ; static const StringRef HSAIntrinsicToAttr [ ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA || TT . getOS ( ) == Triple :: Mesa3D ) { Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; for ( Function & F : M ) { if ( F . hasFnAttribute ( <STR_LIT> ) ) continue ; bool HasApertureRegs = TM && TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . hasApertureRegs ( ) ; if ( ! HasApertureRegs && hasAddrSpaceCast ( F , AS ) ) F . addFnAttr ( <STR_LIT> ) ;


<s> qword q ; long long l [ <NUM_LIT> ] ; } x ; x . q = q ;


<s> char * newsym ; char * p ; tree formal_type ; if ( * asmname == '*' || strchr ( asmname , '@' ) ) return DECL_ASSEMBLER_NAME ( decl ) ; formal_type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( formal_type != NULL_TREE ) { if ( TREE_VALUE ( tree_last ( formal_type ) ) != void_type_node ) return DECL_ASSEMBLER_NAME ( decl ) ; while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { int parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - <NUM_LIT> ) / PARM_BOUNDARY * PARM_BOUNDARY ) ;


<s> static llvm :: once_flag InitializeRegisterBankFlag ; static auto InitializeRegisterBankOnce = [ & ] ( ) { const RegisterBank & RBGPR = getRegBank ( <STR_LIT> ) ; ( void ) RBGPR ; assert ( & <STR_LIT> == & RBGPR && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ; assert ( RBGPR . covers ( * TRI . getRegClass ( <STR_LIT> ) ) && <STR_LIT> ) ;


<s> return ( __m128i ) __builtin_ia32_vpcomeqq ( ( __v2di ) __A , ( __v2di ) __B ) ;


<s> if ( ( R == Match_Success ) || ( R == Match_PreferE32 ) || ( R == Match_MissingFeature && Result != Match_PreferE32 ) || ( R == Match_InvalidOperand && Result != Match_MissingFeature && Result != Match_PreferE32 ) || ( R == Match_MnemonicFail && Result != Match_InvalidOperand && Result != Match_MissingFeature && Result != Match_PreferE32 ) ) { Result = R ; ErrorInfo = EI ; } if ( R == Match_Success ) break ; } switch ( Result ) { default : break ; case Match_Success : if ( ! validateInstruction ( Inst , IDLoc ) ) { return true ; } Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS ) ; return Error ( IDLoc , <STR_LIT> + Suggestion , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; }


<s> bool isCortexA9 ( ) const { return <ISA_LIT>ProcFamily == CortexA9 ;


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> << d_field << <STR_LIT> << d_is_imm << <STR_LIT> ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << s_field << <STR_LIT> << s_is_imm << <STR_LIT> ) ; if ( d_is_imm ) { Inst . addOperand ( MCOperand :: createImm ( d_field ) ) ; } else { Inst . addOperand ( MCOperand :: createReg ( getRegForField ( d_field ) ) ) ; }


<s> if ( ! TARGET_OPT_AGU || optimize_function_for_size_p ( cfun ) ) return false ; if ( ! REG_P ( operands [ <NUM_LIT> ] ) || ! REG_P ( operands [ <NUM_LIT> ] ) ) return false ; regno0 = true_regnum ( operands [ <NUM_LIT> ] ) ; regno1 = true_regnum ( operands [ <NUM_LIT> ] ) ; return ix86_lea_outperforms ( insn , regno0 , regno1 , INVALID_REGNUM , <NUM_LIT> , false ) ;


<s> return getIntegerAttribute ( F , <STR_LIT> , F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ;


<s> if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI , AllOnes ) ) return Result ;


<s> emit_move_insn ( ptr_reg , XEXP ( XEXP ( xinsn , <NUM_LIT> ) , <NUM_LIT> ) ) ; result = gen_rtx_PLUS ( Pmode , ptr_reg , constant ) ; if ( SMALL_INT ( constant ) ) return result ; xinsn = result ; } if ( GET_CODE ( xinsn ) == PLUS ) { rtx xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; rtx xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; enum rtx_code code0 = GET_CODE ( xplus0 ) ; enum rtx_code code1 = GET_CODE ( xplus1 ) ; if ( code0 != REG && code1 == REG ) { xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; code0 = GET_CODE ( xplus0 ) ; code1 = GET_CODE ( xplus1 ) ; } if ( code0 == REG && REG_OK_FOR_BASE_P ( xplus0 ) && code1 == CONST_INT && ! SMALL_INT ( xplus1 ) ) { rtx int_reg = gen_reg_rtx ( Pmode ) ; rtx ptr_reg = gen_reg_rtx ( Pmode ) ; emit_move_insn ( int_reg , GEN_INT ( INTVAL ( xplus1 ) & ~ <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( ptr_reg , gen_rtx_PLUS ( Pmode , xplus0 , int_reg ) ) ) ; result = gen_rtx_PLUS ( Pmode , ptr_reg , GEN_INT ( INTVAL ( xplus1 ) & <NUM_LIT> ) ) ; return result ; } if ( code0 == REG && REG_OK_FOR_BASE_P ( xplus0 ) ) { if ( reload_in_progress ) df_set_regs_ever_live ( PIC_OFFSET_TABLE_REGNUM , true ) ; if ( code1 == CONST ) { xplus1 = XEXP ( xplus1 , <NUM_LIT> ) ; code1 = GET_CODE ( xplus1 ) ; } if ( code1 == SYMBOL_REF ) { if ( microblaze_tls_symbol_p ( xplus1 ) ) { rtx tls_ref , reg ; reg = gen_reg_rtx ( Pmode ) ; tls_ref = microblaze_legitimize_tls_address ( xplus1 , NULL_RTX ) ; emit_move_insn ( reg , tls_ref ) ; result = gen_rtx_PLUS ( Pmode , xplus0 , reg ) ; return result ; } else if ( flag_pic == <NUM_LIT> ) { if ( ! TARGET_PIC_DATA_TEXT_REL ) { rtx pic_ref , reg ; reg = gen_reg_rtx ( Pmode ) ; pic_ref = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , xplus1 ) , UNSPEC_GOTOFF ) ; pic_ref = gen_rtx_CONST ( Pmode , pic_ref ) ; pic_ref = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , pic_ref ) ; pic_ref = gen_const_mem ( Pmode , pic_ref ) ; emit_move_insn ( reg , pic_ref ) ; result = gen_rtx_PLUS ( Pmode , xplus0 , reg ) ; return result ; } else { rtx pic_ref , reg ; reg = gen_reg_rtx ( Pmode ) ; pic_ref = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , xplus1 ) , UNSPEC_TEXT ) ; pic_ref = gen_rtx_CONST ( Pmode , pic_ref ) ; emit_insn ( gen_addsi3 ( reg , pic_offset_table_rtx , xplus0 ) ) ; result = gen_rtx_PLUS ( Pmode , reg , pic_ref ) ; return result ; } }


<s> return Result ; } case <STR_LIT> : case <STR_LIT> : return LowerTrig ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerFDIV ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_CMP_SWAP ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ;

<ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> return ( int64x1_t ) __builtin_neon_vshrs_ndi ( __a , __b ) ;


<s> MachineBasicBlock :: iterator InsertPt = std :: next ( OpDef -> getIterator ( ) ) ; if ( InsertPt != OpDefBB . end ( ) && InsertPt -> isPHI ( ) ) InsertPt = OpDefBB . getFirstNonPHI ( ) ; MIB . setInsertPt ( * OpDef -> getParent ( ) , InsertPt ) ; auto Copy = MIB . buildCopy ( Ty , OpReg ) ; MRI . setRegBank ( Copy . getReg ( <NUM_LIT> ) , * DstRB ) ; MO . setReg ( Copy . getReg ( <NUM_LIT> ) ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredSelect ( MachineInstr * MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineInstr * CascadedCMOV = nullptr ; MachineInstr * LastCMOV = MI ; <STR_LIT> CC = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; <STR_LIT> OppCC = <STR_LIT> ( CC ) ; MachineBasicBlock :: iterator NextMIIt = std :: next ( MachineBasicBlock :: iterator ( MI ) ) ; if ( isCMOVPseudo ( MI ) ) { while ( NextMIIt != BB -> end ( ) && isCMOVPseudo ( NextMIIt ) && ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CC || NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) ) { LastCMOV = & * NextMIIt ; ++ NextMIIt ; } } if ( LastCMOV == MI && NextMIIt != BB -> end ( ) && NextMIIt -> getOpcode ( ) == MI -> getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { CascadedCMOV = & * NextMIIt ; } MachineBasicBlock * jcc1MBB = nullptr ; if ( CascadedCMOV ) { jcc1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , jcc1MBB ) ; jcc1MBB -> addLiveIn ( <STR_LIT> ) ; } MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ;

MachineInstr * LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV ;


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ;

if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_crc32_u8 ( unsigned int __C , unsigned char __V ) {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; Value * Ptr = I -> getArgOperand ( <NUM_LIT> ) ; unsigned Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Type * Ty = Input -> getType ( ) ;

if ( ! isLegalTypeAndAlignment ( Ty -> getVectorNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ;


<s> static SDValue GetGlobalReg ( SelectionDAG & DAG , EVT Ty ) { <ISA_LIT>FunctionInfo * FI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ;

return DAG . getRegister ( FI -> getGlobalBaseReg ( ) , Ty ) ;


<s> return ( uint16x8_t ) __builtin_neon_vcltv8hf ( __a , __b ) ;


<s> case CallingConv :: <ISA_LIT>_CS : return R_00B848_COMPUTE_PGM_RSRC1 ; case CallingConv :: <ISA_LIT>_GS : return R_00B228_SPI_SHADER_PGM_RSRC1_GS ; case CallingConv :: <ISA_LIT>_PS : return R_00B028_SPI_SHADER_PGM_RSRC1_PS ; case CallingConv :: <ISA_LIT>_VS : return R_00B128_SPI_SHADER_PGM_RSRC1_VS ; }


<s> return __builtin_loongson_pmaxsh ( s , t ) ;


<s> bool <ISA_LIT>InstrInfo :: shouldScheduleLoadsNear ( SDNode * Load0 , SDNode * Load1 , int64_t Offset0 , int64_t Offset1 , unsigned NumLoads ) const { assert ( Offset1 > Offset0 && <STR_LIT> ) ;

return ( NumLoads <= <NUM_LIT> && ( Offset1 - Offset0 ) < <NUM_LIT> ) ;


<s> bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ;


<s> unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) llvm_unreachable ( <STR_LIT> ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ;


<s> if ( ! BT . has ( RD . Reg ) ) continue ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; const BitTracker :: RegisterCell & RC = BT . lookup ( RD . Reg ) ; if ( FRC -> getID ( ) == <STR_LIT> ) { bool T = genPackhl ( MI , RD , RC ) ; Changed |= T ; continue ; } if ( FRC -> getID ( ) == <STR_LIT> ) { bool T = genExtractHalf ( MI , RD , RC ) ;

T = T || genCombineHalf ( MI , RD , RC ) ;


<s> Chain = LD -> getChain ( ) ; Base = LD -> getBasePtr ( ) ; MMO = LD -> getMemOperand ( ) ; if ( MMO -> getSize ( ) < <NUM_LIT> ) return SDValue ( ) ; break ; } case <STR_LIT> : { MemIntrinsicSDNode * Intrin = cast < MemIntrinsicSDNode > ( N ) ; Chain = Intrin -> getChain ( ) ; Base = Intrin -> getOperand ( <NUM_LIT> ) ; MMO = Intrin -> getMemOperand ( ) ; break ; } } MVT VecTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; SDValue LoadOps [ ] = { Chain , Base } ; SDValue Load = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VecTy , <STR_LIT> ) , LoadOps , VecTy , MMO ) ; DCI . AddToWorklist ( Load . getNode ( ) ) ; Chain = Load . getValue ( <NUM_LIT> ) ; SDValue Swap = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VecTy , <STR_LIT> ) , Chain , Load ) ;

DCI . AddToWorklist ( Swap . getNode ( ) ) ;


<s> static MachineBasicBlock * getTargetMBB ( const MachineInstr & Br ) {

for ( unsigned I = <NUM_LIT> , E = Br . getDesc ( ) . getNumOperands ( ) ; I < E ; ++ I ) {


<s> srcBlk = * srcBlk -> succ_begin ( ) ; if ( srcBlk == NULL ) { return preBlk ; } if ( ! allowSideEntry && srcBlk -> pred_size ( ) > <NUM_LIT> ) { return NULL ; } } if ( srcBlk && srcBlk -> succ_size ( ) == <NUM_LIT> ) { return srcBlk ; }


<s> } break ; } case <STR_LIT> : { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRClass ( MRI . getRegClass ( Reg ) ) ) break ; bool SGPRBranch = false ; bool HasBreakDef = false ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i += <NUM_LIT> ) { unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( TRI -> hasVGPRs ( MRI . getRegClass ( Reg ) ) ) { TII -> moveToVALU ( MI ) ; break ; } MachineInstr * DefInstr = MRI . getUniqueVRegDef ( Reg ) ; assert ( DefInstr ) ; switch ( DefInstr -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasBreakDef = true ; break ; } }

if ( ! SGPRBranch && ! HasBreakDef ) TII -> moveToVALU ( MI ) ;


<s> int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ;

<ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ;


<s> int ImmValue = ImmOp . getImm ( ) ; if ( - <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else { tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue & <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; }


<s> static HOST_WIDE_INT rs6000_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST && ( STRICT_ALIGNMENT || ! optimize_size ) ) return MAX ( align , BITS_PER_WORD ) ; return align ;


<s> void WinEHStatePass :: linkExceptionRegistration ( IRBuilder < > & Builder , Function * Handler ) { Handler -> addFnAttr ( <STR_LIT> ) ; Type * LinkTy = getEHLinkRegistrationType ( ) ; Value * HandlerI8 = Builder . CreateBitCast ( Handler , Builder . getInt8PtrTy ( ) ) ; Builder . CreateStore ( HandlerI8 , Builder . CreateStructGEP ( LinkTy , Link , <NUM_LIT> ) ) ;

Constant * FSZero = Constant :: getNullValue ( LinkTy -> getPointerTo ( ) -> getPointerTo ( <NUM_LIT> ) ) ;


<s> unsigned <ISA_LIT>CallingConvHook :: getNextExtRegs ( StringRef fName ) { std :: vector < unsigned > regList ; for ( auto & rec : regRecord ) { if ( rec . fName == fName && rec . reg >= <STR_LIT> && rec . reg <= <STR_LIT> ) regList . push_back ( rec . reg ) ; }

if ( regList . size ( ) == <NUM_LIT> ) return <STR_LIT> ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) {


<s> if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } ShiftedVal &= maskTrailingZeros < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t NewVal ; unsigned Opc ; if ( Val < <NUM_LIT> ) { Opc = <STR_LIT> ; NewVal = Val | <NUM_LIT> ; } else { Opc = <STR_LIT> ; NewVal = Val & ~ <NUM_LIT> ; } if ( isInt < <NUM_LIT> > ( NewVal ) ) { <STR_LIT> TmpSeq ; generateInstSeqImpl ( NewVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } int32_t Lo = Val ; uint32_t Hi = Val >> <NUM_LIT> ; Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ; generateInstSeqImpl ( Lo , ActiveFeatures , TmpSeq ) ; if ( Lo > <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; } else if ( Lo < <NUM_LIT> && TmpSeq . size ( ) + countPopulation ( ~ Hi ) < Res . size ( ) ) { Opc = <STR_LIT> ; Hi = ~ Hi ; } if ( Opc > <NUM_LIT> ) { while ( Hi != <NUM_LIT> ) { unsigned Bit = countTrailingZeros ( Hi ) ; TmpSeq . push_back ( <STR_LIT> ( Opc , Bit + <NUM_LIT> ) ) ; Hi &= ~ ( <NUM_LIT> << Bit ) ; } if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } } if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { assert ( ActiveFeatures [ <STR_LIT> ] && <STR_LIT> ) ; int64_t Div = <NUM_LIT> ; unsigned Opc = <NUM_LIT> ; <STR_LIT> TmpSeq ;

if ( ( Val % <NUM_LIT> ) == <NUM_LIT> && isInt < <NUM_LIT> > ( Val / <NUM_LIT> ) ) {


<s> void <ISA_LIT>InstPrinter :: printClamp ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {

<ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo , O , <STR_LIT> ) ;


<s> const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> } EmitLoad ( STI , false , Reg32 , SandboxedInst . getOperand ( <NUM_LIT> ) . getReg ( ) , SandboxedInst . getOperand ( <NUM_LIT> ) . getImm ( ) , SandboxedInst . getOperand ( <NUM_LIT> ) . getReg ( ) , SandboxedInst . getOperand ( <NUM_LIT> ) . getImm ( ) , SandboxedInst . getOperand ( <NUM_LIT> ) . getReg ( ) , Out ) ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ;

return MI -> mayStore ( ) && hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ;


<s> } MCValue Res ; bool Relocatable = Expr -> evaluateAsRelocatable ( Res , nullptr , nullptr ) ; if ( ! Relocatable || Res . getSymB ( ) ) return false ; if ( ! Res . getSymA ( ) && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) return false ; if ( Res . getSymA ( ) ) DarwinRefKind = Res . getSymA ( ) -> getKind ( ) ;


<s> bool <ISA_LIT>InstrInfo :: isNonUniformBranchInstr ( MachineInstr & Branch ) const { return Branch . getOpcode ( ) == <STR_LIT> ;


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module & ) {


<s> APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignBit ( EltBits ) ; Constant * C = ConstantInt :: get ( * Context , MaskElt ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( LogicVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , Alignment ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; unsigned LogicOp = IsFABS ? <STR_LIT> : IsFNABS ? <STR_LIT> : <STR_LIT> ; SDValue Operand = IsFNABS ? Op0 . getOperand ( <NUM_LIT> ) : Op0 ; if ( VT . isVector ( ) || IsF128 ) return DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ; Operand = DAG . getNode ( <STR_LIT> , dl , LogicVT , Operand ) ; SDValue LogicNode = DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LogicNode , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> DataSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getDataRel ( ) ) ; BSSSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;

EHFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;


<s> return ( gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) || gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const {

return create<ISA_LIT>ELFObjectWriter ( TheTriple ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> static void loongarch_va_start ( tree valist , rtx nextarg ) { nextarg = plus_constant ( Pmode , nextarg , - cfun -> machine -> varargs_size ) ;

std_expand_builtin_va_start ( valist , nextarg ) ;


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) ) { Register R = MO . getReg ( ) ; assert ( MO . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( R . isVirtual ( ) ) RO . insert ( std :: make_pair ( R , Index ++ ) ) ; }


<s> } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; }

unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;


<s> LoadChains . push_back ( Load . getValue ( <NUM_LIT> ) ) ; BasePtr = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( Stride , dl , BasePtr . getValueType ( ) ) ) ; } SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadChains ) ; SDValue Value = DAG . getBuildVector ( Op . getValueType ( ) , dl , Vals ) ; if ( LN -> isIndexed ( ) ) { SDValue RetOps [ ] = { Value , Vals [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) , TF } ; return DAG . getMergeValues ( RetOps , dl ) ; } SDValue RetOps [ ] = { Value , TF } ; return DAG . getMergeValues ( RetOps , dl ) ; } assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( LN -> isUnindexed ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > VectElmts , VectElmtChains ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Idx = DAG . getConstant ( i , dl , BasePtr . getValueType ( ) ) ;

Idx = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , Idx ) ;


<s> if ( ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath || ( N0 -> getFlags ( ) . hasAllowContract ( ) && N1 -> getFlags ( ) . hasAllowContract ( ) ) ) && isFMAFasterThanFMulAndFAdd ( VT ) ) { return <STR_LIT> ;


<s> BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( LoReg ) ; if ( FP64 ) {

BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( HiReg ) . addReg ( DstReg , RegState :: Implicit ) ;


<s> machine_mode cmpmode ; rtx tmp , flags ; cmpmode = SELECT_CC_MODE ( code , op0 , op1 ) ; flags = gen_rtx_REG ( cmpmode , FLAGS_REG ) ; tmp = gen_rtx_COMPARE ( cmpmode , op0 , op1 ) ;

emit_insn ( gen_rtx_SET ( VOIDmode , flags , tmp ) ) ;


<s> unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> getDesc ( ) . isTerminator ( ) ) break ; -- MBBI ; } DL = MBBI -> getDebugLoc ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } else { if ( NumBytes ) {

MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ;


<s> } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addUse ( Gep -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; MIB . addImm ( <NUM_LIT> ) ;


<s> if ( IsStackReg ( Op . getMemBaseReg ( ) ) ) Displacement -= OrigSPOffset ; if ( IsStackReg ( Op . getMemIndexReg ( ) ) ) Displacement -= OrigSPOffset * Op . getMemScale ( ) ; assert ( Displacement >= <NUM_LIT> ) ; if ( Displacement == <NUM_LIT> ) { EmitLEA ( Op , Size , Reg , Out ) ; return ; }


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtsi64_si64x ( __m64 __i ) { return ( long long ) __i ;


<s> const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= <NUM_LIT> && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) return <STR_LIT> ;


<s> Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ; case <STR_LIT> : if ( STI . getTargetTriple ( ) . isArch64Bit ( ) ) Ok = isUInt < <NUM_LIT> > ( Imm ) ; else Ok = isUInt < <NUM_LIT> > ( Imm ) ;


<s> } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; if ( ( predRegNumDst != predRegNumSrc ) || QII -> isDotNewInst ( PacketMI ) != QII -> isDotNewInst ( MI ) || getPredicateSense ( MI , QII ) != getPredicateSense ( PacketMI , QII ) ) { return false ; } } std :: vector < MachineInstr * > :: iterator VI ; std :: vector < MachineInstr * > :: iterator VE ; unsigned StartCheck = <NUM_LIT> ; for ( VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE ) ; ++ VI ) { SUnit * TempSU = MIToSUnit . find ( * VI ) -> second ; MachineInstr * TempMI = TempSU -> getInstr ( ) ; if ( TempMI != PacketMI && ! StartCheck ) continue ; StartCheck = <NUM_LIT> ; if ( TempMI == PacketMI ) continue ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) && TempSU -> getInstr ( ) -> modifiesRegister ( MI -> getOperand ( opNum ) . getReg ( ) , QRI ) ) return false ; } } if ( ! QII -> isPostIncrement ( MI ) && GetStoreValueOperand ( MI ) . isReg ( ) && GetStoreValueOperand ( MI ) . getReg ( ) == DepReg ) { for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) - <NUM_LIT> ; opNum ++ ) { if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . getReg ( ) == DepReg ) { return false ; } }

for ( unsigned opNum = <NUM_LIT> ; opNum < PacketMI -> getNumOperands ( ) ; opNum ++ ) {


<s> Inst . addOperand ( MCOperand :: CreateReg ( Register + <NUM_LIT> ) ) ; unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Offset ) ) ) ;


<s> insns = get_insns ( ) ; for ( insn = NEXT_INSN ( insns ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx i ; i = PATTERN ( insn ) ; if ( GET_CODE ( i ) == SET ) { machine_mode mode = GET_MODE ( SET_SRC ( i ) ) ; if ( SPE_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || FLOAT128_2REG_P ( mode ) ) ) return true ; } } }


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> static bool isUnalignedLoadStore ( unsigned Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


if ( extracted_mcu_data . name != NULL ) return cached_result = extracted_mcu_data . hwmpy != <NUM_LIT> ;


<s> NodeAddr < DefNode * > PDA = Rel . front ( ) ; RegisterRef RR = PDA . Addr -> getRegRef ( * this ) ; DefM [ RR . Reg ] . push ( DA ) ; Defined . insert ( RR . Reg ) ; for ( RegisterId A : PRI . getAliasSet ( RR . Reg ) ) { assert ( A != RR . Reg ) ; if ( ! Defined . count ( A ) ) DefM [ A ] . push ( DA ) ; } for ( NodeAddr < NodeBase * > T : Rel ) Visited . insert ( T . Id ) ;


<s> case Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: get<ISA_LIT>RegEncoding ( const MCInst & MI , unsigned OpNum ) const { return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MI . getOperand ( OpNum ) . getReg ( ) ) ;


<s> <ISA_LIT>PassConfig :: addPreISel ( ) ; addPass ( create<ISA_LIT>LateCodeGenPreparePass ( ) ) ; if ( EnableAtomicOptimizations ) { addPass ( create<ISA_LIT>AtomicOptimizerPass ( ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( & <ISA_LIT>UnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { if ( EnableStructurizerWorkarounds ) { addPass ( createFixIrreduciblePass ( ) ) ; addPass ( createUnifyLoopExitsPass ( ) ) ; } addPass ( createStructurizeCFGPass ( false ) ) ; } addPass ( create<ISA_LIT>AnnotateUniformValues ( ) ) ;


<s> size_t THMToTHMStub :: size ( ) const { return m_Size ;


<s> VectorComponents = <NUM_LIT> ; } else if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } if ( VectorComponents > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , <STR_LIT> , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , <STR_LIT> , DestReg , SrcReg ) ;

NewMI -> getOperand ( getOperandIdx ( * NewMI , <STR_LIT> :: src0 ) ) . setIsKill ( KillSrc ) ;


<s> unsigned getMemOpcode ( ) const { unsigned Opcode = I -> first ; const <ISA_LIT>InstrFMA3Group * Group = I -> second ; return Group -> getMemOpcode ( Opcode ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , ArrayRef < int > Mask , int Index , Type * SubTp ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; return vectorCostAdjustment ( LT . first , Instruction :: ShuffleVector , Tp , nullptr ) ;


<s> reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & RegOpnd = static_cast < <ISA_LIT>Operand & > ( * Reg [ <NUM_LIT> ] ) ; if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ;


<s> if ( ! shouldConvertUse ( Val , User , Use . getOperandNo ( ) ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << Use . getOperandNo ( ) << <STR_LIT> ) ; DEBUG ( User -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << '\n' ) ; Instruction * InsertionPoint = findInsertionPoint ( Use ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( InsertionPoint -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << '\n' ) ; InsertionPoints & InsertPts = InsPtsPerFunc [ InsertionPoint -> getParent ( ) -> getParent ( ) ] ; if ( isDominated ( InsertionPoint , Use , InsertPts ) ) continue ; if ( tryAndMerge ( InsertionPoint , Use , InsertPts ) ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; InsertPts [ InsertionPoint ] . push_back ( & Use ) ;


<s> ELF<ISA_LIT>_64AsmBackend ( const Target & T , uint8_t OSABI ) : ELF<ISA_LIT>AsmBackend ( T , OSABI ) {


<s> Register ScratchReg = MI . getOperand ( Opers . getNextScratchIdx ( ) ) . getReg ( ) ; EncodedBytes = <NUM_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = Opers . getNumPatchBytes ( ) ; assert ( NumBytes >= EncodedBytes && <STR_LIT> ) ;

assert ( ( NumBytes - EncodedBytes ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSet<ISA_LIT>0 ( ) { OS << <STR_LIT> ;

<ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>0 ( ) ;


<s> if ( ! Subtarget . hasSSE2 ( ) && VT . is128BitVector ( ) ) { Vec = DAG . getConstantFP ( + <NUM_LIT> , dl , <STR_LIT> ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget . hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget . hasVLX ( ) || VT . getVectorNumElements ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; Vec = DAG . getConstant ( <NUM_LIT> , dl , VT ) ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) , UC ( Parser ) { MCAsmParserExtension :: Initialize ( Parser ) ;

MRI = getContext ( ) . getRegisterInfo ( ) ;


<s> Chain = CWD . getValue ( <NUM_LIT> ) ; } SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) ; RetVal = DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , dl , VT , RetVal ) ;

return DAG . getMergeValues ( { RetVal , Chain } , dl ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getRpt2ImmOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Op ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int64_t Imm = MO . getImm ( ) ; assert ( ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) && <STR_LIT> ) ; return Imm - <NUM_LIT> ;


<s> if ( & Ty != & Returns [ <NUM_LIT> ] ) OS << <STR_LIT> ; OS << <STR_LIT> ( Ty ) ; }


<s> Register PredReg ; NumInstrsSteppedOver = <NUM_LIT> ; while ( Iter != EndIter ) { if ( Iter -> isDebugInstr ( ) ) { ++ Iter ; continue ; } NextPred = getVPTInstrPredicate ( * Iter , PredReg ) ; assert ( NextPred != <STR_LIT> && <STR_LIT> ) ; if ( NextPred == <STR_LIT> || MaxSteps == <NUM_LIT> ) break ;


<s> void <ISA_LIT>InstPrinter :: printAddrMode5Operand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , OpNum , STI , O ) ; return ; } O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; <STR_LIT> Op = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( AlwaysPrintImm0 || ImmOffs || Op == <STR_LIT> ) { O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( Op ) << ImmOffs * <NUM_LIT> << markup ( <STR_LIT> ) ;


if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && GET_MODE_SIZE ( mode ) < <NUM_LIT> && ! COMPLEX_MODE_P ( mode ) && ! VECTOR_TYPE_P ( ret_type ) && ! VECTOR_MODE_P ( mode ) ) return gen_rtx_REG ( SImode , FUNC_RETURN_REGNUM ) ;


<s> emit_insn ( gen_rtx_SET ( target , x ) ) ; return true ; } return false ; case E_V8QImode : case E_V4QImode : if ( ! mmx_ok ) return false ; goto widen ; case E_V8HImode : case E_V8HFmode : case E_V8BFmode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; if ( TARGET_SSE2 ) { struct expand_vec_perm_d dperm ; rtx tmp1 , tmp2 ; permute : memset ( & dperm , <NUM_LIT> , sizeof ( dperm ) ) ; dperm . target = target ; dperm . vmode = mode ; dperm . nelt = GET_MODE_NUNITS ( mode ) ; dperm . op0 = dperm . op1 = gen_reg_rtx ( mode ) ; dperm . one_operand_p = true ; if ( mode == V8HFmode || mode == V8BFmode ) { tmp1 = force_reg ( GET_MODE_INNER ( mode ) , val ) ; tmp2 = gen_reg_rtx ( mode ) ; emit_insn ( maybe_gen_vec_set_0 ( mode , tmp2 , CONST0_RTX ( mode ) , tmp1 ) ) ; tmp1 = gen_lowpart ( mode , tmp2 ) ; } else { tmp1 = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp1 , gen_lowpart ( SImode , val ) ) ; tmp2 = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_vec_setv4si_0 ( tmp2 , CONST0_RTX ( V4SImode ) , tmp1 ) ) ; tmp1 = gen_lowpart ( mode , tmp2 ) ; } emit_move_insn ( dperm . op0 , tmp1 ) ; ok = ( expand_vec_perm_1 ( & dperm ) || expand_vec_perm_broadcast_1 ( & dperm ) ) ; gcc_assert ( ok ) ; return ok ; } goto widen ; case E_V16QImode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; if ( TARGET_SSE2 ) goto permute ; goto widen ; widen : { machine_mode smode , wsmode , wvmode ; rtx x ; smode = GET_MODE_INNER ( mode ) ; wvmode = get_mode_wider_vector ( mode ) ; wsmode = GET_MODE_INNER ( wvmode ) ; val = convert_modes ( wsmode , smode , val , true ) ; if ( smode == QImode && ! TARGET_PARTIAL_REG_STALL ) emit_insn ( gen_insv_1 ( wsmode , val , val ) ) ; else { x = expand_simple_binop ( wsmode , ASHIFT , val , GEN_INT ( GET_MODE_BITSIZE ( smode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; val = expand_simple_binop ( wsmode , IOR , val , x , x , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } x = gen_reg_rtx ( wvmode ) ; ok = ix86_expand_vector_init_duplicate ( mmx_ok , wvmode , x , val ) ; gcc_assert ( ok ) ; emit_move_insn ( target , gen_lowpart ( GET_MODE ( target ) , x ) ) ; return ok ; } case E_V16HImode : case E_V16HFmode :


<s> if ( ! RBI . constrainGenericRegister ( SrcReg , <STR_LIT> , MRI ) ) return false ; if ( Signed && DstSize == <NUM_LIT> && ( SrcSize == <NUM_LIT> || SrcSize == <NUM_LIT> ) ) { const unsigned SextOpc = SrcSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , TII . get ( SextOpc ) , DstReg ) . addReg ( SrcReg ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; } const unsigned BFE64 = Signed ? <STR_LIT> : <STR_LIT> ; const unsigned BFE32 = Signed ? <STR_LIT> : <STR_LIT> ; if ( DstSize > <NUM_LIT> && SrcSize <= <NUM_LIT> ) { unsigned ExtReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned UndefReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , ExtReg ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) . addReg ( UndefReg ) . addImm ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( BFE64 ) , DstReg ) . addReg ( ExtReg ) . addImm ( SrcSize << <NUM_LIT> ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; } unsigned Mask ; if ( ! Signed && shouldUseAndMask ( SrcSize , Mask ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( Mask ) ; } else { BuildMI ( MBB , I , DL , TII . get ( BFE32 ) , DstReg ) . addReg ( SrcReg ) . addImm ( SrcSize << <NUM_LIT> ) ; } return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; } return false ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) {

MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;


<s> if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ; }

return new <ISA_LIT>GNULDBackend ( pConfig , new <ISA_LIT>GNUInfo ( pConfig . targets ( ) . triple ( ) ) ) ;


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , Align ( <NUM_LIT> ) , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } } return <STR_LIT> ;


<s> bool <ISA_LIT>FastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; unsigned i = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { const AttributeSet & Attrs = F -> getAttributes ( ) ; if ( Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: ByVal ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: SwiftSelf ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: SwiftError ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: InAlloca ) || Attrs . hasAttribute ( i + <NUM_LIT> , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ;

if ( ! Subtarget -> hasSIMD128 ( ) && ArgTy -> isVectorTy ( ) ) return false ;


<s> MIRBuilder . setInstr ( MI ) ; auto FMFlags = getFastMathFlags ( MI ) ; if ( FMFlags != FPFastMathMode :: None ) { Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . hasOneUse ( DstReg ) && <STR_LIT> ) ; Register NewReg = MRI . use_instr_begin ( DstReg ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addUse ( NewReg ) . addImm ( Decoration :: FPFastMathMode ) . addImm ( FMFlags ) ; } } }


<s> if ( VecRegBitWidth > <NUM_LIT> && VecTy -> getScalarSizeInBits ( ) < <NUM_LIT> ) return <NUM_LIT> / LoadSize ;


<s> res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; res . as_char [ <NUM_LIT> ] = __b ; return ( res . as_m64 ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getNumArgRegs ( const MachineFunction * MF ) {

return array_lengthof ( <ISA_LIT>_ArgRegs ) ;


<s> static bool CallIsStructReturn ( CallSDNode * TheCall ) {

unsigned NumOps = TheCall -> getNumArgs ( ) ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { Register Tmp = createVReg ( Builder , <STR_LIT> ) ; Builder . buildInstr ( <STR_LIT> ) . addDef ( Tmp ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; Builder . buildInstr ( <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addUse ( Tmp ) ; MI . eraseFromParent ( ) ; return ; } unsigned Opcode ; switch ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> :


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ;

if ( ! isInt < <NUM_LIT> > ( Offset ) ) {


<s> assert ( MIb . mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ; int64_t OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ;

int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ;


<s> Kind = VK_<ISA_LIT>_HI ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : Kind = VK_<ISA_LIT>_HIGHER ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Kind = VK_<ISA_LIT>_HIGHEST ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr ) ;


<s> std :: string ClassDef = EmitClassDefinition ( TyNmPair . first , ClassName ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ClassDef ; ) ; std :: error_code EC ; sys :: fs :: OpenFlags OpenFlags = sys :: fs :: F_None ; raw_fd_ostream ClassFile ( ClassName + <STR_LIT> , EC , OpenFlags ) ;


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ;

MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , <NUM_LIT> , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ;


return __builtin_ia32_movmskps ( ( __v4sf ) __A ) ;


<s> return ( CC == CallingConv :: Fast || CC == CallingConv :: GHC ) ;


<s> uint64_t evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size ) const { if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType != MCOI :: OPERAND_PCREL ) return - <NUM_LIT> ;

int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> if ( Counter >= CTRLoopLimit ) return false ; Counter ++ ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( TT , * I ) ) return MadeChange ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; BasicBlock * CountedExitBlock = nullptr ; const SCEV * ExitCount = nullptr ; BranchInst * CountedExitBranch = nullptr ; for ( SmallVectorImpl < BasicBlock * > :: iterator I = ExitingBlocks . begin ( ) , IE = ExitingBlocks . end ( ) ; I != IE ; ++ I ) { const SCEV * EC = SE -> getExitCount ( L , * I ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * L << <STR_LIT> << ( * I ) -> getName ( ) << <STR_LIT> << * EC << <STR_LIT> ) ; if ( isa < SCEVCouldNotCompute > ( EC ) ) continue ; if ( const SCEVConstant * ConstEC = dyn_cast < SCEVConstant > ( EC ) ) { if ( ConstEC -> getValue ( ) -> isZero ( ) ) continue ; } else if ( ! SE -> isLoopInvariant ( EC , L ) ) continue ; if ( SE -> getTypeSizeInBits ( EC -> getType ( ) ) > ( TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) ) continue ; bool NotAlways = false ; for ( pred_iterator PI = pred_begin ( L -> getHeader ( ) ) , PIE = pred_end ( L -> getHeader ( ) ) ; PI != PIE ; ++ PI ) { if ( ! L -> contains ( * PI ) ) continue ; if ( ! DT -> dominates ( * I , * PI ) ) { NotAlways = true ; break ; } }


<s> <ISA_LIT>ELFAttributeData ( ) : ELFAttributeData ( <STR_LIT> ) , m_CurrentCPUArch ( - <NUM_LIT> ) , m_DIVUseInitialized ( false ) , m_HardFPUseInitialized ( false ) {


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ;


<s> for ( auto * D : Dependences ) { if ( D -> front ( ) == I1 && D -> back ( ) == I2 ) return D ; }


initializeGCNRegBankReassignPass ( * PR ) ;


<s> int general_scalar_chain :: vector_const_cost ( rtx exp ) { gcc_assert ( CONST_INT_P ( exp ) ) ; if ( standard_sse_constant_p ( exp , vmode ) ) return ix86_cost -> sse_op ;

return ix86_cost -> sse_load [ smode == DImode ? <NUM_LIT> : <NUM_LIT> ] ;


<s> bool <ISA_LIT>AsmBackend :: needAlign ( MCObjectStreamer & OS ) const { if ( ! OS . getAllowAutoPadding ( ) ) return false ; assert ( allowAutoPadding ( ) && <STR_LIT> ) ; MCAssembler & Assembler = OS . getAssembler ( ) ; MCSection * Sec = OS . getCurrentSectionOnly ( ) ; if ( Assembler . isBundlingEnabled ( ) && Sec -> isBundleLocked ( ) ) return false ; if ( ! ( STI . hasFeature ( <STR_LIT> ) || STI . hasFeature ( <STR_LIT> ) ) ) return false ;


<s> void <ISA_LIT>AsmPrinter :: PrinterDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) { OS << <STR_LIT> ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter & InstPrinter , bool VerboseAsm ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) , InstPrinter ( InstPrinter ) , IsVerboseAsm ( VerboseAsm ) {


<s> static AddrMode DecodeSrcAddrModeII ( unsigned Insn ) { unsigned Rs = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;

unsigned As = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> } else if ( TREE_CODE ( type ) == UNION_TYPE ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_union_value ( size , mode , <NUM_LIT> , regbase ) ; } else if ( VECTOR_TYPE_P ( type ) && mode == BLKmode ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_vector_value ( size , <NUM_LIT> , true , SPARC_FP_ARG_FIRST ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { const int size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; mode = int_mode_for_size ( size * BITS_PER_UNIT , <NUM_LIT> ) . else_blk ( ) ;

if ( mode == BLKmode ) return function_arg_union_value ( size , mode , <NUM_LIT> , regbase ) ;


<s> if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ; if ( PredCost && MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) * PredCost = <NUM_LIT> ;

if ( UOps ) return ItinData -> getStageLatency ( Class ) ;


<s> return align_flags ( rx_align_log_for_label ( lab , uses_threshold ) , rx_max_skip_for_label ( lab ) ) ;


<s> const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( MCID . mayStore ( ) ) return true ; unsigned Opcode = MCID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TII -> isFpMLxInstruction ( Opcode ) ; } return false ;


<s> return <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> ) ;


<s> void <ISA_LIT>ConditionalCompares :: invalidateTraces ( ) {

Traces -> invalidate ( CmpConv . Head ) ;


<s> SDValue Addr = From . getOperand ( <NUM_LIT> ) ; SDValue NewAddr = DAG . getNode ( <STR_LIT> , dl , Addr . getSimpleValueType ( ) , Addr , DAG . getConstant ( DestIndex * EVT . getStoreSize ( ) , Addr . getSimpleValueType ( ) ) ) ; LoadSDNode * Load = cast < LoadSDNode > ( From ) ; SDValue NewLoad = DAG . getLoad ( EVT , dl , Load -> getChain ( ) , NewAddr , DAG . getMachineFunction ( ) . getMachineMemOperand ( Load -> getMemOperand ( ) , <NUM_LIT> , EVT . getStoreSize ( ) ) ) ; if ( EVT == <STR_LIT> ) { SDValue LoadScalarToVector = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad ) ; SDValue InsertpsMask = DAG . getIntPtrConstant ( DestIndex << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , To , LoadScalarToVector , InsertpsMask ) ; } else { return DAG . getNode ( <STR_LIT> , dl , VT , To , NewLoad , DAG . getConstant ( DestIndex , <STR_LIT> ) ) ;


<s> const int align_mask = mov_insn_alignment_mask ( mode , consider_sh2a ) ; if ( ! allow_zero && max_disp < <NUM_LIT> ) return false ; return offset >= <NUM_LIT> && offset <= max_disp && ( offset & align_mask ) == <NUM_LIT> ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CC_Save_RegMask ;


<s> static HOST_WIDE_INT aarch64_simd_vector_alignment ( const_tree type ) { if ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_VECTOR_BOOL ? <NUM_LIT> : <NUM_LIT> ; HOST_WIDE_INT align = tree_to_shwi ( TYPE_SIZE ( type ) ) ;


<s> TargetIRAnalysis <ISA_LIT>TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ) ) ; } ) ;


<s> if ( STI -> has<ISA_LIT>2 ( ) ) return false ; return handleSlot ( [ this ] ( auto & I ) -> bool { return TII -> HasLoadDelaySlot ( I ) ; } , [ this ] ( auto & IInSlot , auto & I ) -> bool { return TII -> SafeInLoadDelaySlot ( IInSlot , I ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; bool isHigh = ! is<ISA_LIT>LowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = AddDefaultT1CC ( MIB ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , RegState :: Kill ) ;


<s> ScheduleDAGInstrs :: finalizeSchedule ( ) ; finalizeBundles ( MF ) ;


<s> <ISA_LIT>FrameAnalyzer ( ) : MachineFunctionPass ( ID ) {


<s> const char * maybe_suffix_2 = <STR_LIT> ; if ( ALL_FIXED_POINT_MODE_P ( from ) && ALL_FIXED_POINT_MODE_P ( to ) && UNSIGNED_FIXED_POINT_MODE_P ( from ) == UNSIGNED_FIXED_POINT_MODE_P ( to ) && ALL_FRACT_MODE_P ( from ) == ALL_FRACT_MODE_P ( to ) ) maybe_suffix_2 = <STR_LIT> ; sprintf ( buffer , <STR_LIT> , funcname , fromname , toname , maybe_suffix_2 ) ;

set_conv_libfunc ( optable , to , from , buffer ) ;


<s> assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; MachineOperand * MOSrc0 = getSrcFromCopy ( & * Def , MRI , SubReg0 ) ; if ( MOSrc0 ) -- NumNewCopies ; if ( MOSrc0 && MRI -> hasOneNonDBGUse ( OrigSrc0 ) ) ++ NumRemovableCopies ; } if ( ! MRI -> def_empty ( OrigSrc1 ) ) { MachineRegisterInfo :: def_instr_iterator Def = MRI -> def_instr_begin ( OrigSrc1 ) ; assert ( std :: next ( Def ) == MRI -> def_instr_end ( ) && <STR_LIT> ) ; MachineOperand * MOSrc1 = getSrcFromCopy ( & * Def , MRI , SubReg1 ) ; if ( MOSrc1 ) -- NumNewCopies ; if ( MOSrc1 && MRI -> hasOneNonDBGUse ( OrigSrc1 ) ) ++ NumRemovableCopies ; } unsigned Dst = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool AllUsesAreCopies = true ; for ( MachineRegisterInfo :: use_instr_nodbg_iterator Use = MRI -> use_instr_nodbg_begin ( Dst ) , E = MRI -> use_instr_nodbg_end ( ) ; Use != E ; ++ Use ) { unsigned SubReg ; if ( getSrcFromCopy ( & * Use , MRI , SubReg ) || isTransformable ( & * Use ) ) ++ NumRemovableCopies ; else if ( Use -> getOpcode ( ) == <STR_LIT> || Use -> getOpcode ( ) == <STR_LIT> ) ;


<s> for ( Structor & S : Structors ) { if ( const ConstantExpr * CE = dyn_cast < ConstantExpr > ( S . Func ) ) S . Func = CE -> getOperand ( <NUM_LIT> ) ; llvm :: GlobalAlias :: create ( GlobalValue :: ExternalLinkage , ( IsCtor ? llvm :: Twine ( <STR_LIT> ) : llvm :: Twine ( <STR_LIT> ) ) + llvm :: Twine ( convertToSinitPriority ( S . Priority ) ) + llvm :: Twine ( <STR_LIT> , FormatIndicatorAndUniqueModId ) + llvm :: Twine ( <STR_LIT> , llvm :: utostr ( Index ++ ) ) , cast < Function > ( S . Func ) ) ; }


<s> unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFramePointer ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , <NUM_LIT> , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( IsCastIntrinsicWithRoundMode ) { InputSwitch = Op . getConstantOperandVal ( NumOp - <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << InputSwitch << <STR_LIT> ) ; } EVT OpType = ( IsCastIntrinsicWithRoundMode ) ? Op . getValueType ( ) : Op -> getValueType ( <NUM_LIT> ) ;

const SDValue & Src = ( IsCastIntrinsicWithRoundMode ) ? Op . getOperand ( <NUM_LIT> ) : Op . getOperand ( <NUM_LIT> ) ;


<s> default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; } printOperand ( MI , OpNo , O ) ;


<s> return ELF :: R_<ISA_LIT>_GOTPCREL ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_LO : return ELF :: R_<ISA_LIT>_GOTPCREL32_LO ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_HI : return ELF :: R_<ISA_LIT>_GOTPCREL32_HI ; case MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_LO : return ELF :: R_<ISA_LIT>_REL32_LO ; case MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_HI : return ELF :: R_<ISA_LIT>_REL32_HI ; case MCSymbolRefExpr :: VK_<ISA_LIT>_REL64 : return ELF :: R_<ISA_LIT>_REL64 ; } switch ( Fixup . getKind ( ) ) { default : break ; case FK_PCRel_4 : return ELF :: R_<ISA_LIT>_REL32 ; case FK_Data_4 : case FK_SecRel_4 :


<s> for ( i = <NUM_LIT> ; i < issue_rate ; i ++ ) { group_insns [ i ] = <NUM_LIT> ; } can_issue_more = issue_rate ; slot = <NUM_LIT> ; insn = get_next_active_insn ( prev_head_insn , tail ) ; group_end = false ; while ( insn != NULL_RTX ) { slot = ( issue_rate - can_issue_more ) ; group_insns [ slot ] = insn ; can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; if ( insn_terminates_group_p ( insn , current_group ) ) can_issue_more = <NUM_LIT> ; next_insn = get_next_active_insn ( insn , tail ) ; if ( next_insn == NULL_RTX ) return group_count + <NUM_LIT> ; group_end = ( can_issue_more == <NUM_LIT> || ( can_issue_more == <NUM_LIT> && ! is_branch_slot_insn ( next_insn ) ) || ( can_issue_more <= <NUM_LIT> && is_cracked_insn ( next_insn ) ) || ( can_issue_more < issue_rate && insn_terminates_group_p ( next_insn , previous_group ) ) ) ;


<s> if ( MachineInstr * Def = MRI . getUniqueVRegDef ( MO . getReg ( ) ) ) if ( Def -> getParent ( ) == & MBB ) MFI . unstackifyVReg ( MO . getReg ( ) ) ; } } for ( auto I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ) { MachineInstr & MI = * I ++ ; if ( ! <STR_LIT> ( MI . getOpcode ( ) ) ) continue ; Register TeeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DefReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MFI . isVRegStackified ( TeeReg ) ) { MFI . unstackifyVReg ( DefReg ) ; unsigned CopyOpc = getCopyOpcode ( MRI . getRegClass ( DefReg ) ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII . get ( CopyOpc ) , TeeReg ) . addReg ( DefReg ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII . get ( CopyOpc ) , Reg ) . addReg ( DefReg ) ; MI . eraseFromParent ( ) ; }


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectAddrSpaceCast ( SDNode * N ) { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; AddrSpaceCastSDNode * CastN = cast < AddrSpaceCastSDNode > ( N ) ; unsigned SrcAddrSpace = CastN -> getSrcAddressSpace ( ) ; unsigned DstAddrSpace = CastN -> getDestAddressSpace ( ) ; assert ( SrcAddrSpace != DstAddrSpace && <STR_LIT> ) ; if ( DstAddrSpace == ADDRESS_SPACE_GENERIC ) { unsigned Opc ; switch ( SrcAddrSpace ) { default : report_fatal_error ( <STR_LIT> ) ; case ADDRESS_SPACE_GLOBAL : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_LOCAL : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; } return CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Src ) ; } else { if ( SrcAddrSpace != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; unsigned Opc ; switch ( DstAddrSpace ) { default : report_fatal_error ( <STR_LIT> ) ; case ADDRESS_SPACE_GLOBAL : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ;


<s> assert ( ! ( UseUN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && <STR_LIT> ) ; NodeAddr < StmtNode * > UseIA = UseUN . Addr -> getOwner ( * DFG ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Print < NodeAddr < InstrNode * >> ( UseIA , * DFG ) << <STR_LIT> ) ; MachineInstr * UseMI = UseIA . Addr -> getCode ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * UseMI -> getParent ( ) ) << <STR_LIT> << * UseMI << <STR_LIT> ) ; const MCInstrDesc & UseMID = UseMI -> getDesc ( ) ; assert ( HII -> getAddrMode ( * UseMI ) == <STR_LIT> ) ; auto UsePos = MachineBasicBlock :: iterator ( UseMI ) ; MachineBasicBlock :: instr_iterator InsertPt = UsePos . getInstrIterator ( ) ; short NewOpCode = getBaseWithLongOffset ( * UseMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; unsigned OpStart ; unsigned OpEnd = UseMI -> getNumOperands ( ) ; MachineBasicBlock * BB = UseMI -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , InsertPt , UseMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; if ( UseMID . mayLoad ( ) ) { MIB . add ( UseMI -> getOperand ( <NUM_LIT> ) ) ;

MIB . add ( AddAslMI -> getOperand ( <NUM_LIT> ) ) ;


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;


<s> SDValue RHS = VecIns [ Slot + <NUM_LIT> ] ; VecIns . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ) ; } <STR_LIT> CCode ; if ( SDValue V = LowerVectorAllZero ( DL , VecIns . back ( ) , CC , Mask , Subtarget , DAG , CCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( CCode , DL , <STR_LIT> ) ; return V ; } } if ( Op . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> BinOp ; if ( SDValue Match = DAG . matchBinOpReduction ( Op . getNode ( ) , BinOp , { <STR_LIT> } ) ) { <STR_LIT> CCode ; if ( SDValue V = LowerVectorAllZero ( DL , Match , CC , Mask , Subtarget , DAG , CCode ) ) { <ISA_LIT>CC = DAG . getTargetConstant ( CCode , DL , <STR_LIT> ) ;


<s> if ( findChainOperand ( Load0 ) != findChainOperand ( Load1 ) ) return false ; Offset0 = Load0Offset -> getZExtValue ( ) ; Offset1 = Load1Offset -> getZExtValue ( ) ; return true ; } if ( ( isMUBUF ( Opc0 ) || isMTBUF ( Opc0 ) ) && ( isMUBUF ( Opc1 ) || isMTBUF ( Opc1 ) ) ) { if ( ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: soffset ) || findChainOperand ( Load0 ) != findChainOperand ( Load1 ) || ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: vaddr ) || ! nodesHaveSameOperandValue ( Load0 , Load1 , <STR_LIT> :: srsrc ) ) return false ; int OffIdx0 = <STR_LIT> ( Opc0 , <STR_LIT> :: offset ) ; int OffIdx1 = <STR_LIT> ( Opc1 , <STR_LIT> :: offset ) ; if ( OffIdx0 == - <NUM_LIT> || OffIdx1 == - <NUM_LIT> ) return false ; -- OffIdx0 ; -- OffIdx1 ; SDValue Off0 = Load0 -> getOperand ( OffIdx0 ) ; SDValue Off1 = Load1 -> getOperand ( OffIdx1 ) ;

if ( ! isa < ConstantSDNode > ( Off0 ) || ! isa < ConstantSDNode > ( Off1 ) ) return false ;


<s> } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - <NUM_LIT> - i ) ;

Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> const auto * DAsm = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; return addOperand ( Inst , DAsm -> decodeMandatoryLiteralConstant ( Imm ) ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; if ( TLI . verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue RetAddr ; if ( depth == <NUM_LIT> ) { auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned RetReg = MF . addLiveIn ( <STR_LIT> , TLI . getRegClassFor ( PtrVT ) ) ; RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RetReg , VT ) ; return RetAddr ; } SDValue FrameAddr = getFRAMEADDR ( depth - <NUM_LIT> , Op , DAG , Subtarget ) ; unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , dl ) ) ; RetAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return RetAddr ;


<s> const MCSymbol * Sym = Ctx -> GetOrCreateSymbol ( SymName ) ; const MCSymbolRefExpr * MCSym ; MCSym = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , * Ctx ) ; MCOperand SymHi = MCOperand :: CreateExpr ( MCSym ) ; MCSym = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , * Ctx ) ; MCOperand SymLo = MCOperand :: CreateExpr ( MCSym ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; int RegNum ; RegNum = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNum == - <NUM_LIT> ) return true ; Parser . Lex ( ) ; bool Writeback = false ; if ( ParseWriteBack ) { const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { Writeback = true ; Parser . Lex ( ) ; }


<s> DECL_ARTIFICIAL ( space ) = <NUM_LIT> ; DECL_IGNORED_P ( space ) = <NUM_LIT> ; ofs = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , integer_type_node ) ; DECL_FIELD_CONTEXT ( ofs ) = record ; TREE_CHAIN ( ofs ) = space ; base = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , ptr_type_node ) ; DECL_FIELD_CONTEXT ( base ) = record ; TREE_CHAIN ( base ) = ofs ; TYPE_FIELDS ( record ) = base ; layout_type ( record ) ; va_list_gpr_counter_field = ofs ;


<s> if ( TARGET_32BIT && DEFAULT_ABI == ABI_V4 ) { if ( rs6000_passes_vector ) fprintf ( asm_out_file , <STR_LIT> , ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) ; if ( rs6000_returns_struct ) fprintf ( asm_out_file , <STR_LIT> , aix_struct_return ? <NUM_LIT> : <NUM_LIT> ) ; } if ( TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2 ) file_end_indicate_exec_stack ( ) ; if ( flag_split_stack ) file_end_indicate_split_stack ( ) ; if ( cpu_builtin_p ) { switch_to_section ( data_section ) ;


<s> unsigned ParamRegs = <NUM_LIT> ; if ( auto * M = MF -> getFunction ( ) -> getParent ( ) ) ParamRegs = M -> getNumberRegisterParameters ( ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < Args . size ( ) ; Idx ++ ) { Type * T = Args [ Idx ] . Ty ;

if ( T -> isPointerTy ( ) || T -> isIntegerTy ( ) ) if ( MF -> getDataLayout ( ) . getTypeAllocSize ( T ) <= <NUM_LIT> ) {


<s> bool <ISA_LIT>InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { const MCInstrDesc & Desc = MI . getDesc ( ) ; if ( ! Desc . isCommutable ( ) ) return false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ; switch ( Imm ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Subtarget . hasSSE41 ( ) ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return false ; } case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>InstPrinter :: printS13ImmDecOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { if ( <STR_LIT> ( STI ) ) {

O << formatDec ( SignExtend32 < <NUM_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ) ;


<s> ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( hasQPX ( ) || isBGQ ( ) ) StackAlignment = <NUM_LIT> ; IsLittleEndian = ( TargetTriple . getArch ( ) == Triple :: ppc64le ) ; if ( IsLittleEndian ) { HasVSX = false ; HasP8Vector = false ; } if ( TargetABI == <ISA_LIT>_ABI_UNKNOWN ) { if ( ! isDarwin ( ) && Is<ISA_LIT>64 ) { if ( IsLittleEndian ) TargetABI = <ISA_LIT>_ABI_ELFv2 ; else TargetABI = <ISA_LIT>_ABI_ELFv1 ;


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( EVT VT1 , EVT VT2 ) const {


<s> if ( mode == SImode ) return <NUM_LIT> ;


<s> assert ( MOOMap . size ( ) && MOOMap . find ( Reg ) != MOOMap . end ( ) && <STR_LIT> ) ; return MOOMap [ Reg ] ;


<s> unsigned Reg = Op . getReg ( ) ; unsigned regIdx = Reg - <STR_LIT> ; if ( regIdx > <NUM_LIT> ) return false ;

Op . Reg . RegNum = F32Regs [ regIdx ] ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ MBB -> getIterator ( ) ; MachineBasicBlock * thisMBB = MBB ; MachineFunction * MF = MBB -> getParent ( ) ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; mainMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ;


<s> if ( ! MaskVT . isInteger ( ) || DAG . ComputeNumSignBits ( Mask ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT && DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , MaskVT ) ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ;


<s> if ( ! REG_P ( x1 ) ) { rtx tem = x1 ; x1 = x2 ; x2 = tem ; } if ( ! REG_P ( x1 ) || ! MMIX_REG_OK ( x1 ) ) return TARGET_BASE_ADDRESSES && mmix_constant_address_p ( x ) ; if ( REG_P ( x2 ) && MMIX_REG_OK ( x2 ) ) return <NUM_LIT> ; if ( satisfies_constraint_I ( x2 ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> return parseAddress ( Operands , BDXMem , <STR_LIT> , ADDR64Reg ) ;


<s> return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_LOCAL_P ( x ) && ! SYMBOL_REF_EXTERNAL_P ( x ) && ( mips_get_compress_mode ( SYMBOL_REF_DECL ( x ) ) & MASK_MIPS16 ) ) ;


<s> if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII , MachineInstr :: FrameDestroy ) ; else { assert ( ! MFI . getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII , MachineInstr :: FrameDestroy ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . add ( predOps ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes , MachineInstr :: FrameDestroy ) ; if ( MBBI != MBB . end ( ) && AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getDPRCalleeSavedGapSize ( ) ) { assert ( AFI -> getDPRCalleeSavedGapSize ( ) == <NUM_LIT> && <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedGapSize ( ) , MachineInstr :: FrameDestroy ) ; }

if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ;


case D15 : case D14 : case D13 : case D12 :


<s> const TargetAsmInfo * <ISA_LIT>TargetMachine :: createTargetAsmInfo ( ) const { return new <ISA_LIT>TargetAsmInfo ( * this ) ;


<s> if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame -> getObjectSize ( FI ) , MFFrame -> getObjectAlignment ( FI ) ) ; return MIB . addImm ( Offset ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ;


<s> set_optab_libfunc ( ne_optab , TFmode , <STR_LIT> ) ; set_optab_libfunc ( gt_optab , TFmode , <STR_LIT> ) ;

set_optab_libfunc ( ge_optab , TFmode , <STR_LIT> ) ;


<s> V1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , SingleTy , VecV ) ; SDValue HalfV = DAG . getConstant ( SingleTy . getVectorNumElements ( ) , dl , <STR_LIT> ) ; PickHi = DAG . getSetCC ( dl , <STR_LIT> , IdxV , HalfV , <STR_LIT> ) ; if ( isHvxSingleTy ( SubTy ) ) { if ( const auto * CN = dyn_cast < const ConstantSDNode > ( IdxV . getNode ( ) ) ) { unsigned Idx = CN -> getZExtValue ( ) ; assert ( Idx == <NUM_LIT> || Idx == VecTy . getVectorNumElements ( ) / <NUM_LIT> ) ; unsigned SubIdx = ( Idx == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getTargetInsertSubreg ( SubIdx , dl , VecTy , VecV , SubV ) ; } SDValue InLo = DAG . getNode ( <STR_LIT> , dl , VecTy , { SubV , V1 } ) ; SDValue InHi = DAG . getNode ( <STR_LIT> , dl , VecTy , { V0 , SubV } ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , PickHi , InHi , InLo ) ; } SDValue S = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , HalfV ) ; IdxV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , PickHi , S , IdxV ) ; SingleV = DAG . getNode ( <STR_LIT> , dl , SingleTy , PickHi , V1 , V0 ) ; } assert ( SubTy . getSizeInBits ( ) == <NUM_LIT> || SubTy . getSizeInBits ( ) == <NUM_LIT> ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV . getNode ( ) ) ; if ( ! IdxN || ! IdxN -> isZero ( ) ) { IdxV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( ElemWidth / <NUM_LIT> , dl , <STR_LIT> ) ) ; SingleV = DAG . getNode ( <STR_LIT> , dl , SingleTy , SingleV , IdxV ) ; } unsigned RolBase = HwLen ; if ( VecTy . getSizeInBits ( ) == <NUM_LIT> ) { SDValue V = DAG . getBitcast ( <STR_LIT> , SubV ) ; SingleV = DAG . getNode ( <STR_LIT> , dl , SingleTy , V ) ; } else { SDValue V = DAG . getBitcast ( <STR_LIT> , SubV ) ; SDValue R0 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , V ) ; SDValue R1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , V ) ; SingleV = DAG . getNode ( <STR_LIT> , dl , SingleTy , SingleV , R0 ) ; SingleV = DAG . getNode ( <STR_LIT> , dl , SingleTy , SingleV , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;

SingleV = DAG . getNode ( <STR_LIT> , dl , SingleTy , SingleV , R1 ) ;


<s> int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ;

if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ;

MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ;


<s> if ( ! I -> start . isBlock ( ) || I -> valno != OldVN ) continue ; if ( ! NewVN ) NewVN = LI . getNextValue ( I -> start , LIS -> getVNInfoAllocator ( ) ) ; I -> valno = NewVN ;