<s> else if ( ST . is64Bit ( ) || ST . isTargetDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . is64Bit ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ;

if ( ! ST . is64Bit ( ) && ST . isOSWindows ( ) ) Ret += <STR_LIT> ;


<s> dest = adjust_address ( dest , V2DImode , <NUM_LIT> ) ; source = gen_lowpart ( V2DImode , source ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( source ) : source ; permute_src = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_tmp = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( tmp , permute_src ) ) ; emit_insn ( gen_rtx_SET ( dest , permute_tmp ) ) ;


<s> static void mep_rewrite_mult ( rtx_insn * insn , rtx pattern ) { rtx hi_clobber ; hi_clobber = XVECEXP ( pattern , <NUM_LIT> , XVECLEN ( pattern , <NUM_LIT> ) - <NUM_LIT> ) ; XEXP ( hi_clobber , <NUM_LIT> ) = gen_rtx_REG ( SImode , HI_REGNO ) ;


<s> wi . want_locations = true ; walk_gimple_seq ( body , NULL , check_op_callback , & wi ) ; chk_function_decl ( fntype , fun -> function_start_locus ) ;


<s> if ( Optional < int64_t > Imm = getConstantVRegSExtVal ( CombinedOffset , * MRI ) ) { uint32_t SOffset , ImmOffset ; if ( <STR_LIT> ( * Imm , SOffset , ImmOffset , & RBI . Subtarget , Alignment ) ) { VOffsetReg = B . buildConstant ( S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; SOffsetReg = B . buildConstant ( S32 , SOffset ) . getReg ( <NUM_LIT> ) ; InstOffsetVal = ImmOffset ; B . getMRI ( ) -> setRegBank ( VOffsetReg , <STR_LIT> ) ; B . getMRI ( ) -> setRegBank ( SOffsetReg , <STR_LIT> ) ; return SOffset + ImmOffset ; } } Register Base ; unsigned Offset ; std :: tie ( Base , Offset ) = <STR_LIT> ( * MRI , CombinedOffset ) ; uint32_t SOffset , ImmOffset ; if ( Offset > <NUM_LIT> && <STR_LIT> ( Offset , SOffset , ImmOffset , & RBI . Subtarget , Alignment ) ) { if ( RBI . getRegBank ( Base , * MRI , * RBI . TRI ) == & <STR_LIT> ) { VOffsetReg = Base ; SOffsetReg = B . buildConstant ( S32 , SOffset ) . getReg ( <NUM_LIT> ) ; B . getMRI ( ) -> setRegBank ( SOffsetReg , <STR_LIT> ) ; InstOffsetVal = ImmOffset ; return <NUM_LIT> ; } if ( SOffset == <NUM_LIT> ) { VOffsetReg = B . buildConstant ( S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; B . getMRI ( ) -> setRegBank ( VOffsetReg , <STR_LIT> ) ; SOffsetReg = Base ; InstOffsetVal = ImmOffset ; return <NUM_LIT> ; } } if ( MachineInstr * Add = getOpcodeDef ( <STR_LIT> , CombinedOffset , * MRI ) ) { Register Src0 = getSrcRegIgnoringCopies ( * MRI , Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register Src1 = getSrcRegIgnoringCopies ( * MRI , Add -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;

const RegisterBank * Src0Bank = RBI . getRegBank ( Src0 , * MRI , * RBI . TRI ) ;


<s> for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { MachineInstr * MI = & * I ; NextI = std :: next ( I ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: COPY : Changed |= expandCopy ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandStoreInt ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandLoadInt ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandStoreVecPred ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandLoadVecPred ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> :

Changed |= expandLoadVec2 ( B , I , MRI , HII , NewRegs ) ;


<s> assert ( MF . getFrameInfo ( ) -> getObjectSize ( FrameIdx ) >= ( RC -> getSize ( ) / <NUM_LIT> ) && <STR_LIT> ) ; unsigned Alignment = ( RC -> getSize ( ) / <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;

bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ;


<s> const MCExpr * ME ; ME = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , MC ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: CreateAdd ( ME , MCConstantExpr :: Create ( MO . getOffset ( ) , MC ) , MC ) ; return ( MCOperand :: CreateExpr ( ME ) ) ;


<s> if ( RemainderOffsetInfo . find ( Remainder ) == RemainderOffsetInfo . end ( ) ) RemainderOffsetInfo [ Remainder ] = std :: make_pair ( j , <NUM_LIT> ) ; else RemainderOffsetInfo [ Remainder ] . second ++ ; } } unsigned MaxCountRemainder = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < ( unsigned ) Form ; j ++ ) if ( ( RemainderOffsetInfo . find ( j ) != RemainderOffsetInfo . end ( ) ) && RemainderOffsetInfo [ j ] . second > RemainderOffsetInfo [ MaxCountRemainder ] . second ) MaxCountRemainder = j ; if ( RemainderOffsetInfo [ MaxCountRemainder ] . second < DispFormPrepMinThreshold ) return false ; if ( MaxCountRemainder == <NUM_LIT> ) return true ; const SCEV * Offset = BucketChain . Elements [ RemainderOffsetInfo [ MaxCountRemainder ] . first ] . Offset ; BucketChain . BaseSCEV = SE -> getAddExpr ( BucketChain . BaseSCEV , Offset ) ; for ( auto & E : BucketChain . Elements ) { if ( E . Offset ) E . Offset = cast < SCEVConstant > ( SE -> getMinusSCEV ( E . Offset , Offset ) ) ; else E . Offset = cast < SCEVConstant > ( SE -> getNegativeSCEV ( Offset ) ) ; } std :: swap ( BucketChain . Elements [ RemainderOffsetInfo [ MaxCountRemainder ] . first ] , BucketChain . Elements [ <NUM_LIT> ] ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> const MCRegisterClass & XRegClass = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; bool isXReg = XRegClass . contains ( FirstReg ) , isWReg = WRegClass . contains ( FirstReg ) ; if ( ! isXReg && ! isWReg ) { Error ( S , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCRegisterInfo * RI = getContext ( ) . getRegisterInfo ( ) ; unsigned FirstEncoding = RI -> getEncodingValue ( FirstReg ) ; if ( FirstEncoding & <NUM_LIT> ) { Error ( S , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc M = getLoc ( ) ; if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( M , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; SMLoc E = getLoc ( ) ; int SecondReg = tryParseRegister ( ) ; if ( SecondReg == - <NUM_LIT> ) { return MatchOperand_ParseFail ; } if ( RI -> getEncodingValue ( SecondReg ) != FirstEncoding + <NUM_LIT> || ( isXReg && ! XRegClass . contains ( SecondReg ) ) || ( isWReg && ! WRegClass . contains ( SecondReg ) ) ) { Error ( E , <STR_LIT> <STR_LIT> ) ;


<s> unsigned LiteralSize ; if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) { if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) { ++ NumLiterals ; LiteralSize = <NUM_LIT> ; } SmallDenseSet < unsigned > SGPRsUsed ; unsigned SGPRUsed = findImplicitSGPRReadInVOP ( Inst ) ; if ( SGPRUsed != <STR_LIT> ) { SGPRsUsed . insert ( SGPRUsed ) ; ++ ConstantBusUseCount ; } const int Src0Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src0 ) ; const int Src1Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src1 ) ; const int Src2Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src2 ) ; const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MCOperand & MO = Inst . getOperand ( OpIdx ) ; if ( usesConstantBus ( Inst , OpIdx ) ) { if ( MO . isReg ( ) ) { LastSGPR = mc2PseudoReg ( MO . getReg ( ) ) ; if ( ! SGPRsUsed . count ( LastSGPR ) ) { SGPRsUsed . insert ( LastSGPR ) ; ++ ConstantBusUseCount ; } } else { if ( Desc . OpInfo [ OpIdx ] . OperandType == MCOI :: OPERAND_IMMEDIATE ) continue ; unsigned Size = <STR_LIT> ( Desc , OpIdx ) ; if ( Size < <NUM_LIT> ) Size = <NUM_LIT> ; if ( NumLiterals == <NUM_LIT> ) {


<s> DirectXSubtarget :: DirectXSubtarget ( const Triple & TT , StringRef CPU , StringRef FS , const DirectXTargetMachine & TM ) : DirectXGenSubtargetInfo ( TT , CPU , CPU , FS ) , TL ( TM , * this ) {


<s> Function * Callee = CS . getCalledFunction ( ) ; if ( ! Callee || Callee -> size ( ) != <NUM_LIT> ) return false ; const BasicBlock & BB = Callee -> getEntryBlock ( ) ; if ( const Instruction * I = BB . getFirstNonPHI ( ) ) { if ( ! isa < CallInst > ( I ) ) { return false ; } if ( isa < ReturnInst > ( * std :: next ( I -> getIterator ( ) ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Callee -> getName ( ) << '\n' ) ; return true ; }


<s> bool AMDGPUInstrInfo :: canFoldMemoryOperand ( const MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops ) const { return false ;


<s> void <ISA_LIT>AsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) {


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; return false ;


<s> return size > <NUM_LIT> * <NUM_LIT> ? <NUM_LIT> : ( HOST_WIDE_INT ) size ;


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( ! isUndefOrEqual ( Mask [ <NUM_LIT> ] , NumElts ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; return true ;


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> FOOffset = ( Reg - <ISA_LIT>64IntRegs ) * <NUM_LIT> - <NUM_LIT> * <NUM_LIT> ; } else FOOffset = VA . getLocMemOffset ( ) ; unsigned NumRegs = ( Flags . getByValSize ( ) + <NUM_LIT> ) / <NUM_LIT> ; unsigned LastFI = MFI -> CreateFixedObject ( NumRegs * <NUM_LIT> , FOOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( LastFI , PtrTy ) ; InVals . push_back ( FIN ) ; for ( unsigned I = <NUM_LIT> ; ( Reg != <ISA_LIT>64IntRegs + <NUM_LIT> ) && ( I < NumRegs ) ; ++ Reg , ++ I ) { unsigned VReg = AddLiveIn ( MF , * Reg , <STR_LIT> ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , FIN , DAG . getConstant ( I * <NUM_LIT> , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , dl , DAG . getRegister ( VReg , <STR_LIT> ) , StorePtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; OutChains . push_back ( Store ) ;


<s> if ( regno == ARG_REGISTER ( <NUM_LIT> ) || ( TARGET_32BIT && TARGET_AAPCS_BASED && TARGET_HARD_FLOAT && regno == FIRST_VFP_REGNUM ) || ( TARGET_IWMMXT_ABI && regno == FIRST_IWMMXT_REGNUM ) ) return true ;


<s> mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ; emit_move_insn ( mem , chain_value ) ;


<s> Register IdxReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const RegisterBank * IdxRB = RBI . getRegBank ( IdxReg , * MRI , TRI ) ; if ( IdxRB -> getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( SrcTy , * SrcRB ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( DstTy , * DstRB ) ; if ( ! SrcRC || ! DstRC ) return false ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; const bool Is64 = DstTy . getSizeInBits ( ) == <NUM_LIT> ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , SrcRC , IdxReg , DstTy . getSizeInBits ( ) / <NUM_LIT> ) ; if ( SrcRB -> getID ( ) == <STR_LIT> ) { if ( DstTy . getSizeInBits ( ) != <NUM_LIT> && ! Is64 ) return false ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; unsigned Opc = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( Opc ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ; return true ; } if ( SrcRB -> getID ( ) != <STR_LIT> || DstTy . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! STI . useVGPRIndexMode ( ) ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; MI . eraseFromParent ( ) ;


<s> if ( UseMI -> isCopy ( ) && UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) . isPhysical ( ) && ! TRI -> isSGPRReg ( * MRI , UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { numVGPRUses ++ ; } if ( Visited . insert ( UseMI ) . second ) worklist . insert ( UseMI ) ; continue ; } if ( UseMI -> isPHI ( ) ) { const TargetRegisterClass * UseRC = MRI -> getRegClass ( Use . getReg ( ) ) ; if ( ! TRI -> isSGPRReg ( * MRI , Use . getReg ( ) ) && UseRC != & <STR_LIT> ) numVGPRUses ++ ; continue ; } const TargetRegisterClass * OpRC = TII -> getOpRegClass ( * UseMI , UseMI -> getOperandNo ( & Use ) ) ; if ( ! TRI -> isSGPRClass ( OpRC ) && OpRC != & <STR_LIT> && OpRC != & <STR_LIT> ) { numVGPRUses ++ ; } } } Register PHIRes = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

const TargetRegisterClass * RC0 = MRI -> getRegClass ( PHIRes ) ;


<s> bool hasBitPreservingFPLogic ( EVT VT ) const override {

return VT == <STR_LIT> || VT == <STR_LIT> || VT . isVector ( ) ;


<s> const DataLayout & DL = SI -> getModule ( ) -> getDataLayout ( ) ; unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; bool EltIs64Bits = DL . getTypeSizeInBits ( EltTy ) == <NUM_LIT> ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize != <NUM_LIT> ) || EltIs64Bits ) return false ; if ( EltTy -> isHalfTy ( ) ) return false ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; Type * IntVecTy = VectorType :: get ( IntTy , Op0 -> getType ( ) -> getVectorNumElements ( ) ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; SmallVector < Value * , <NUM_LIT> > Ops ;

Type * Int8Ptr = Builder . getInt8PtrTy ( SI -> getPointerAddressSpace ( ) ) ;


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI , DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ) ;

SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI , Hi ) ;


<s> static inline bool getPreviousInstr ( MachineBasicBlock :: iterator & I , MachineBasicBlock & MBB ) {


<s> parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn = nullptr ; IsPicEnabled = ( getContext ( ) . getObjectFileInfo ( ) -> getRelocM ( ) == Reloc :: PIC_ ) ; IsCpRestoreSet = false ; CpRestoreOffset = - <NUM_LIT> ; Triple TheTriple ( sti . getTargetTriple ( ) ) ;

if ( ( TheTriple . getArch ( ) == Triple :: mips ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) IsLittleEndian = false ;


<s> default : break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned RotAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < ValueBit , <NUM_LIT> > LHSBits ( Bits . size ( ) ) ; getValueBits ( V . getOperand ( <NUM_LIT> ) , LHSBits ) ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) Bits [ i ] = LHSBits [ i < RotAmt ? i + ( Bits . size ( ) - RotAmt ) : i - RotAmt ] ; return true ; } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned ShiftAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < ValueBit , <NUM_LIT> > LHSBits ( Bits . size ( ) ) ; getValueBits ( V . getOperand ( <NUM_LIT> ) , LHSBits ) ; for ( unsigned i = ShiftAmt ; i < Bits . size ( ) ; ++ i ) Bits [ i ] = LHSBits [ i - ShiftAmt ] ; for ( unsigned i = <NUM_LIT> ; i < ShiftAmt ; ++ i ) Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; return true ; } break ; case <STR_LIT> :


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCSubtargetInfo & STI , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx ) ;


<s> SDNode * Shift = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { bytes = <NUM_LIT> - bytes ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperLowerSelect , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; } if ( bits > <NUM_LIT> ) { bits = <NUM_LIT> - bits ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( ( Shift != <NUM_LIT> ? Shift : UpperLowerSelect ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bits , ShiftAmtVT ) ) ; } } else { SDNode * NegShift = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperLowerSelect , <NUM_LIT> ) , SDValue ( NegShift , <NUM_LIT> ) ) ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( Shift , <NUM_LIT> ) , SDValue ( NegShift , <NUM_LIT> ) ) ;


<s> Loc . Location . WasmLoc = { <STR_LIT> , LocalNum } ; } else { Loc . Location . WasmLoc = { <STR_LIT> , <NUM_LIT> } ; }


<s> Inst . addOperand ( MCOperand :: createImm ( static_cast < unsigned > ( MAI -> SrcLang ) ) ) ;

Inst . addOperand ( MCOperand :: createImm ( static_cast < unsigned > ( MAI -> SrcLangVersion ) ) ) ;


<s> assert ( static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . hasMSA ( ) && <STR_LIT> ) ; return & <STR_LIT> [ <STR_LIT> ] ;


<s> vld2_dup_p8 ( const poly8_t * __a ) {


<s> SDNode * M0 = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , <STR_LIT> , V , Chain ) ;


<s> const size_t TagHeaderSize = <NUM_LIT> + <NUM_LIT> ; Streamer . EmitIntValue ( VendorHeaderSize + TagHeaderSize + ContentsSize , <NUM_LIT> ) ; Streamer . EmitBytes ( CurrentVendor ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; for ( unsigned int i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItemType item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag ) ; switch ( item . Type ) { default : llvm_unreachable ( <STR_LIT> ) ; case AttributeItemType :: NumericAttribute : Streamer . EmitULEB128IntValue ( item . IntValue ) ;


<s> const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset , Width ) ;


<s> const auto * CmpRHSC = dyn_cast < ConstantFP > ( CmpRHS ) ; if ( CmpRHSC && CmpRHSC -> isNullValue ( ) ) CmpRHS = CmpLHS ; } unsigned CC ; bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>SSEConditionCode ( Predicate ) ; if ( CC > <NUM_LIT> ) return false ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; static unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned * Opc = nullptr ; switch ( RetVT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ; bool CmpLHSIsKill = hasTrivialKill ( CmpLHS ) ; unsigned CmpRHSReg = getRegForValue ( CmpRHS ) ; bool CmpRHSIsKill = hasTrivialKill ( CmpRHS ) ; if ( ! LHSReg || ! RHSReg || ! CmpLHS || ! CmpRHS ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg ; if ( Subtarget -> hasAVX ( ) ) { const TargetRegisterClass * FR32 = & <STR_LIT> ; const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT . SimpleTy == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BlendOpcode = ( RetVT . SimpleTy == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , FR32 , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned VBlendReg = fastEmitInst_rrr ( BlendOpcode , VR128 , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CmpReg , true ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( VBlendReg ) ; } else { unsigned CmpReg = fastEmitInst_rri ( Opc [ <NUM_LIT> ] , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ;

unsigned AndReg = fastEmitInst_rr ( Opc [ <NUM_LIT> ] , RC , CmpReg , false , LHSReg , LHSIsKill ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned RegisterPair = CPPairDecoderTable [ RegNo / <NUM_LIT> ] ;

Inst . addOperand ( MCOperand :: createReg ( RegisterPair ) ) ;


<s> if ( <STR_LIT> ( STI ) && ( STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA || STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; getTargetStreamer ( ) -> EmitCodeEnd ( ) ; } return AsmPrinter :: doFinalization ( M ) ;


<s> int64_t TripCount = LoopCount -> getOperand ( <NUM_LIT> ) . getImm ( ) + TripCountAdjust ; LoopCount -> getOperand ( <NUM_LIT> ) . setImm ( TripCount ) ; return ;


<s> return GET_CODE ( x ) == REG && INT_REG_OK_FOR_BASE_P ( x , strict ) ;


<s> static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { if ( RM . hasValue ( ) ) return * RM ; if ( TT . isOSDarwin ( ) ) return Reloc :: DynamicNoPIC ; if ( TT . getArch ( ) == Triple :: ppc64 ) return Reloc :: PIC_ ; return Reloc :: Static ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx , true ) ;


<s> auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VReg , Ret ) ) return false ; MIRBuilder . insertInstr ( Ret ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> int32x4_t result = vcombine_s32 ( a , vcreate_s32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) : ) ; return result ;


<s> static bool DecodeSymbolicOperand ( MCInst & Inst , uint64_t Address , uint64_t Value , const void * Decoder ) { static const uint64_t atLeast = <NUM_LIT> ; auto Disassembler = static_cast < const MCDisassembler * > ( Decoder ) ; return ( nullptr != Disassembler && Disassembler -> tryAddingSymbolicOperand ( Inst , Value , Address , true , <NUM_LIT> , atLeast ) ) ;


<s> rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( CONSTANT_P ( xop0 ) && ! symbol_mentioned_p ( xop0 ) ) xop0 = force_reg ( SImode , xop0 ) ; if ( CONSTANT_P ( xop1 ) && ! CONST_INT_P ( xop1 ) && ! symbol_mentioned_p ( xop1 ) ) xop1 = force_reg ( SImode , xop1 ) ; if ( ARM_BASE_REGISTER_RTX_P ( xop0 ) && CONST_INT_P ( xop1 ) ) { HOST_WIDE_INT n , low_n ; rtx base_reg , val ; n = INTVAL ( xop1 ) ; if ( mode == DImode || mode == DFmode ) { low_n = n & <NUM_LIT> ; n &= ~ <NUM_LIT> ; if ( low_n > <NUM_LIT> ) { n += <NUM_LIT> ; low_n -= <NUM_LIT> ; } } else { low_n = ( ( mode ) == TImode ? <NUM_LIT> : n >= <NUM_LIT> ? ( n & <NUM_LIT> ) : - ( ( - n ) & <NUM_LIT> ) ) ; n -= low_n ; } base_reg = gen_reg_rtx ( SImode ) ; val = force_operand ( plus_constant ( Pmode , xop0 , n ) , NULL_RTX ) ;


<s> case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : assert ( MI -> getNumOperands ( ) >= <NUM_LIT> ) ; const MachineOperand & Reg = MI -> getOperand ( <NUM_LIT> ) ; assert ( Reg . isReg ( ) && <STR_LIT> ) ; assert ( Reg . isUse ( ) && <STR_LIT> ) ; RegUses . insert ( Reg . getReg ( ) ) ; const MachineOperand & RegOrImm = MI -> getOperand ( <NUM_LIT> ) ; if ( RegOrImm . isImm ( ) ) break ; assert ( RegOrImm . isReg ( ) && <STR_LIT> ) ; assert ( RegOrImm . isUse ( ) && <STR_LIT> ) ;

RegUses . insert ( RegOrImm . getReg ( ) ) ;


<s> <ISA_LIT>Cloner ( ) : ModulePass ( & ID ) {


<s> if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= <NUM_LIT> ) || ( TARGET_ARCH64 && size <= <NUM_LIT> ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST + <NUM_LIT> * slotno ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH32 ) return gen_rtx_REG ( mode , regno ) ; if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { rtx reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) { if ( ( regno - SPARC_FP_ARG_FIRST ) >= SPARC_INT_ARG_MAX * <NUM_LIT> ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ) ) ; else return reg ; } else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * <NUM_LIT> ) { int intreg ; if ( incoming_p ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / <NUM_LIT> ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , v0 , v1 ) ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , CPI , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } }


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredCmp0 ( MachineInstr & MI , MachineBasicBlock * BB ) const { bool Is24Bit = MI . getOpcode ( ) == <STR_LIT> ; assert ( ( Is24Bit || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * BB , MI , DL , TII -> get ( Is24Bit ? <STR_LIT> : <STR_LIT> ) , Is24Bit ? <STR_LIT> : <STR_LIT> ) . addReg ( Is24Bit ? <STR_LIT> : <STR_LIT> ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;

BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ;


<s> static inline const MachineInstrBuilder & addFrameReference ( const MachineInstrBuilder & MIB , int FI , int Offset = <NUM_LIT> ) { MachineInstr * MI = MIB ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; auto Flags = MachineMemOperand :: MONone ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; return addOffset ( MIB . addFrameIndex ( FI ) , Offset ) . addMemOperand ( MMO ) ;


<s> if ( cum >= TILEGX_NUM_ARG_REGS ) return NULL_RTX ; doubleword_aligned_p = tilegx_function_arg_boundary ( mode , type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) cum += cum & <NUM_LIT> ; if ( ( cum + ( byte_size + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) > TILEGX_NUM_ARG_REGS ) return NULL_RTX ; return gen_rtx_REG ( mode , cum ) ;


<s> static void CreateMCInst ( MCInst & Inst , unsigned Opc , const MCOperand & Opnd0 , const MCOperand & Opnd1 , const MCOperand & Opnd2 = MCOperand ( ) ) { Inst . setOpcode ( Opc ) ; Inst . addOperand ( Opnd0 ) ; Inst . addOperand ( Opnd1 ) ; if ( Opnd2 . isValid ( ) ) Inst . addOperand ( Opnd2 ) ;


return __builtin_aarch64_frecpev2df ( __a ) ;


<s> static bool getMCRDeprecationInfo ( MCInst & MI , MCSubtargetInfo & STI , std :: string & Info ) { if ( STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { if ( ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { Info = <STR_LIT> ; return true ; } if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { Info = <STR_LIT> ; return true ; } } if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) {


<s> for ( MCSymbol * Sym : ExtSymSDNodeSymbols ) OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Extern ) ; return <ISA_LIT>AsmPrinter :: doFinalization ( M ) ;


<s> return ArgInfo . PrivateSegmentWaveByteOffset . getRegister ( ) ;


<s> return hasVInstructionsI64 ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> mode = V2DImode ; dest = adjust_address ( dest , V2DImode , <NUM_LIT> ) ; source = gen_lowpart ( V2DImode , source ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( source ) : source ;

permute_src = rs6000_gen_le_vsx_permute ( source , mode ) ;


<s> if ( MO . isImplicit ( ) ) continue ; const <ISA_LIT>FunctionInfo & MFI = * MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned WAReg = MFI . getWAReg ( MO . getReg ( ) ) ; MCOp = MCOperand :: createReg ( WAReg ) ; break ; } case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_FPImmediate : { const ConstantFP * Imm = MO . getFPImm ( ) ; if ( Imm -> getType ( ) -> isFloatTy ( ) ) MCOp = MCOperand :: createFPImm ( Imm -> getValueAPF ( ) . convertToFloat ( ) ) ; else if ( Imm -> getType ( ) -> isDoubleTy ( ) ) MCOp = MCOperand :: createFPImm ( Imm -> getValueAPF ( ) . convertToDouble ( ) ) ; else llvm_unreachable ( <STR_LIT> ) ; break ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createConstpoolOp ( const MCExpr * Val , SMLoc S , SMLoc E ) {

auto Op = std :: make_unique < <ISA_LIT>Operand > ( CPOP ) ;


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> explicit SuccessorList ( MachineLoop * Loop ) : MetaBlock ( Loop ) , Index ( <NUM_LIT> ) , Num ( successors ( ) . size ( ) ) {


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; if ( Val != nullptr ) { if ( ! isSupportedType ( Val -> getType ( ) ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > RetInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; ArgInfo ArgRetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( ArgRetInfo , <NUM_LIT> , RetInfos , OrigArgIndices ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , RetInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } }


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , uint8_t _OSABI ) : <ISA_LIT>AsmBackend ( T ) , OSABI ( _OSABI ) { HasReliableSymbolDifference = true ;


<s> SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT SrcVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Src = convertToScalableVector ( SrcVT , Src , DAG , Subtarget ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ZeroSplat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Zero , VL ) ; SDValue SplatValue = DAG . getConstant ( Op . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> , DL , XLenVT ) ; SDValue Splat = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatValue , VL ) ;

SDValue Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , Splat , ZeroSplat , VL ) ;


<s> switch ( I -> getDesc ( ) . TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : if ( TFI -> hasFP ( MF ) && AFI -> hasStackFrame ( ) ) Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> :


<s> if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return <NUM_LIT> ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ? <NUM_LIT> : <NUM_LIT> ; else if ( mode == V2DImode ) { if ( ! CONST_INT_P ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) || ! CONST_INT_P ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ;

if ( zero_constant ( op , mode ) ) return <NUM_LIT> ;


<s> if ( Sym . find ( getTagName ( LIBCALL ) ) != std :: string :: npos ) return LIBCALL ; if ( Sym . find ( <STR_LIT> ) == std :: string :: npos ) return GLOBAL ; if ( Sym . find ( <STR_LIT> ) != std :: string :: npos ) return STATIC_LOCAL ;


for ( i = <NUM_LIT> ; isSymbolChar ( FixupNameStart [ i ] ) ; i ++ ) ;


<s> if ( flag_check_pointer_bounds ) warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ; return VOIDmode ; }


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM ) , TSInfo ( ) , ELFArch ( false ) , m_FeatureSetDummy ( false ) { ParseSubtargetFeatures ( CPU , FS ) ;


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ;


<s> return createASMStreamer ( Ctx , OS , isVerboeASM , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ;


<s> if ( optimize_bb_for_speed_p ( bb ) ) continue ;


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const {


<s> if ( ! InsideFrameSequence ) return false ; InsideFrameSequence = false ; } } if ( InsideFrameSequence ) return false ; } bool CannotReserveFrame = MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; if ( CannotReserveFrame ) return true ; AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ;

bool OptForSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) || FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ;


<s> if ( SIBLING_CALL_P ( insn ) ) { if ( direct_p ) { if ( ix86_nopic_noplt_attribute_p ( call_op ) ) { if ( TARGET_64BIT ) xasm = <STR_LIT> ; else xasm = <STR_LIT> ; } else xasm = <STR_LIT> ; } else if ( TARGET_SEH ) xasm = <STR_LIT> ; else xasm = <STR_LIT> ; output_asm_insn ( xasm , & call_op ) ; return <STR_LIT> ; } if ( TARGET_SEH ) { rtx_insn * i ; for ( i = NEXT_INSN ( insn ) ; i ; i = NEXT_INSN ( i ) ) { if ( INSN_P ( i ) ) break ; if ( NOTE_P ( i ) && NOTE_KIND ( i ) == NOTE_INSN_EPILOGUE_BEG && ! flag_non_call_exceptions && ! can_throw_internal ( insn ) ) { seh_nop_p = true ; break ; } } if ( i == NULL ) seh_nop_p = true ; } if ( direct_p ) { if ( ix86_nopic_noplt_attribute_p ( call_op ) ) { if ( TARGET_64BIT ) xasm = <STR_LIT> ;


<s> Opcode = I -> getOpcode ( ) ; U = I ; InMBB = I -> getParent ( ) == FuncInfo . MBB -> getBasicBlock ( ) ; } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( V ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ;

if ( GV -> hasDLLImportStorageClass ( ) ) return false ;


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> fpr_reg_base = <NUM_LIT> + cum -> words ; if ( arg_size > <NUM_LIT> || mode == BLKmode || ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { rtx loc [ <NUM_LIT> ] ; int i , offset = <NUM_LIT> , ub = arg_size ; gpr_reg_base -= alignment ; ub = MIN ( ub , max_arg_words - cum -> words - alignment ) ; for ( i = <NUM_LIT> ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , gpr_reg_base ) , GEN_INT ( offset ) ) ; gpr_reg_base -= <NUM_LIT> ; offset += <NUM_LIT> ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( ub , loc ) ) ; } } else { if ( arg_size > <NUM_LIT> ) { if ( cum -> words ) { gpr_reg_base = <NUM_LIT> ; fpr_reg_base = <NUM_LIT> ; } else { gpr_reg_base = <NUM_LIT> ; fpr_reg_base = <NUM_LIT> ; } if ( mode == BLKmode || ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , gpr_reg_base ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( <NUM_LIT> , loc ) ) ; } } else { gpr_reg_base = <NUM_LIT> - cum -> words ; fpr_reg_base = <NUM_LIT> + <NUM_LIT> * cum -> words ; } } if ( ( ( TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32 ) && ! TARGET_SOFT_FLOAT && GET_MODE_CLASS ( mode ) == MODE_FLOAT && cum -> nargs_prototype <= <NUM_LIT> && type != NULL_TREE && ! cum -> incoming ) || ( ! TARGET_64BIT && ! TARGET_GAS && ! cum -> incoming && cum -> indirect && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) { retval = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , fpr_reg_base ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , gpr_reg_base ) , const0_rtx ) ) ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { EVT Ty = Op . getValueType ( ) ; if ( Ty == <STR_LIT> ) { SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; } else if ( Ty . isVector ( ) && Ty . isInteger ( ) && isTypeLegal ( Ty ) ) { return DAG . getNode ( <STR_LIT> , dl , Ty , Op . getOperand ( <NUM_LIT> ) ) ; } else { report_fatal_error ( <STR_LIT> ) ; } } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> :


<s> } } else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) Val = DAG . getBitcast ( LocVT , Val ) ; else assert ( VA . getLocInfo ( ) == CCValAssign :: Full && <STR_LIT> ) ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( Reg , Val ) ) ; } else if ( ! IsTailCall ) { assert ( VA . isMemLoc ( ) ) ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , { Chain , Val , DAG . getConstant ( VA . getLocMemOffset ( ) , DL , PtrVT ) } , LocVT , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , VA . getLocMemOffset ( ) ) , <NUM_LIT> , false , false ) ; Chain = DAG . getStore ( Chain , DL , Val , DAG . getTargetIndex ( VA . getLocMemOffset ( ) / PtrBits , PtrVT , VA . getLocMemOffset ( ) % PtrBits ) , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , VA . getLocMemOffset ( ) ) ) ; } } SDValue InFlag ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( IsTailCall ) InFlag = SDValue ( ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , PtrVT ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , PtrVT ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) Ops . push_back ( DAG . getRegister ( RegsToPass [ I ] . first , RegsToPass [ I ] . second . getValueType ( ) ) ) ;

const uint32_t * Mask = RegInfo -> getCallPreservedMask ( MF , CallConv ) ;


<s> if ( CSI . empty ( ) ) return false ; return FrameIdx >= CSI . front ( ) . getFrameIdx ( ) && FrameIdx <= CSI . back ( ) . getFrameIdx ( ) ;


<s> bool ia64_expand_vecint_minmax ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx xops [ <NUM_LIT> ] ; if ( mode == V8QImode && ( code == UMIN || code == UMAX ) ) return false ; if ( mode == V4HImode && ( code == SMIN || code == SMAX ) ) return false ; if ( mode == V4HImode && code == UMAX ) { rtx x , tmp = gen_reg_rtx ( mode ) ; x = gen_rtx_US_MINUS ( mode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( tmp , x ) ) ; emit_insn ( gen_addv4hi3 ( operands [ <NUM_LIT> ] , tmp , operands [ <NUM_LIT> ] ) ) ;


<s> using LoopVector = std :: vector < MachineLoop * > ; LoopVector WorkQ ; append_range ( WorkQ , * MLI ) ; for ( unsigned i = <NUM_LIT> ; i < WorkQ . size ( ) ; ++ i ) append_range ( WorkQ , * WorkQ [ i ] ) ; USet Rs ; for ( unsigned i = <NUM_LIT> , n = WorkQ . size ( ) ; i < n ; ++ i ) { MachineLoop * L = WorkQ [ i ] ; Rs . clear ( ) ;


<s> bool <ISA_LIT>InstrInfo :: isExtendLikelyToBeFolded ( MachineInstr & ExtMI , MachineRegisterInfo & MRI ) const { assert ( ExtMI . getOpcode ( ) == TargetOpcode :: G_SEXT || ExtMI . getOpcode ( ) == TargetOpcode :: G_ZEXT || ExtMI . getOpcode ( ) == TargetOpcode :: G_ANYEXT ) ; if ( ExtMI . getOpcode ( ) == TargetOpcode :: G_ANYEXT ) return true ; Register DefReg = ExtMI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneNonDBGUse ( DefReg ) ) return false ; auto * UserMI = & * MRI . use_instr_nodbg_begin ( DefReg ) ; return UserMI -> getOpcode ( ) == TargetOpcode :: G_PTR_ADD ;


<s> auto * Node = cast < MemIntrinsicSDNode > ( Op . getNode ( ) ) ; SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Code , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ;

return DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( Op ) , Node -> getVTList ( ) , Ops , Node -> getMemoryVT ( ) , Node -> getMemOperand ( ) ) ;


<s> if ( Best != Dst ) return false ; if ( ( Src == SrcBest && Dst == DstBest ) || ( SrcBest == nullptr && Dst == DstBest ) || ( Src == SrcBest && Dst == nullptr ) ) return true ; if ( SrcBest != nullptr ) { if ( ! hasV60Ops ( ) ) changeLatency ( SrcBest , Dst , <NUM_LIT> ) ; else restoreLatency ( SrcBest , Dst ) ; } if ( DstBest != nullptr ) { if ( ! hasV60Ops ( ) ) changeLatency ( Src , DstBest , <NUM_LIT> ) ; else restoreLatency ( Src , DstBest ) ; } if ( SrcBest && DstBest ) changeLatency ( SrcBest , DstBest , <NUM_LIT> ) ; else if ( DstBest ) { ExclSrc . insert ( Src ) ; for ( auto & I : DstBest -> Preds ) if ( ExclSrc . count ( I . getSUnit ( ) ) == <NUM_LIT> && isBestZeroLatency ( I . getSUnit ( ) , DstBest , TII , ExclSrc , ExclDst ) ) changeLatency ( I . getSUnit ( ) , DstBest , <NUM_LIT> ) ; } else if ( SrcBest ) {


<s> Type * CPTy = CPVal -> getType ( ) ; Align Alignment = MF . getDataLayout ( ) . getPrefTypeAlign ( CPTy ) ; MachineConstantPool * MCP = MF . getConstantPool ( ) ; return MCP -> getConstantPoolIndex ( CPVal , Alignment ) ;


<s> unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ;


<s> if ( ! MaskedImm ) return ; if ( RemSize <= <NUM_LIT> ) { AddInstr ( SeqLs , Inst ( ADDiu , MaskedImm ) ) ; return ; } if ( ! ( Imm & <NUM_LIT> ) ) { GetInstSeqLsSHL ( Imm , RemSize , SeqLs ) ; return ; } GetInstSeqLsADDiu ( Imm , RemSize , SeqLs ) ; if ( Imm & <NUM_LIT> ) { InstSeqLs SeqLsORi ;

GetInstSeqLsORi ( Imm , RemSize , SeqLsORi ) ;


<s> SDValue In2H = Node -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ; if ( ! SelectAddr ( Node , In1 , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) return NULL ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ;

MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ;


<s> EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetThreadLocalGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getThreadLocalPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const auto & TLOF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream OS ( Flags ) ; for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function ) ;

for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Global ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>EmitLoad ( EVT VT , unsigned & ResultReg , Address & Addr , unsigned Alignment , bool isZExt , bool allocReg ) { assert ( VT . isSimple ( ) && <STR_LIT> ) ; unsigned Opc ; bool useAM3 = false ; bool needVMOV = false ; TargetRegisterClass * RC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { if ( isZExt ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; useAM3 = true ; } } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; }

<ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ;


<s> uint64_t TSFlags = MII . get ( Inst . getOpcode ( ) ) . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == <NUM_LIT> ) return true ; auto Opcode = Inst . getOpcode ( ) ; auto OpNum = <STR_LIT> ( Opcode , <STR_LIT> :: offset ) ; assert ( OpNum != - <NUM_LIT> ) ; const auto & Op = Inst . getOperand ( OpNum ) ; if ( ! hasFlatOffsets ( ) && Op . getImm ( ) != <NUM_LIT> ) { Error ( getFlatOffsetLoc ( Operands ) , <STR_LIT> ) ; return false ; } unsigned OffsetSize = isGFX9 ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( TSFlags & ( <STR_LIT> | <STR_LIT> ) ) { if ( ! isIntN ( OffsetSize , Op . getImm ( ) ) ) { Error ( getFlatOffsetLoc ( Operands ) , isGFX9 ( ) ? <STR_LIT> : <STR_LIT> ) ; return false ; } } else {

if ( ! isUIntN ( OffsetSize - <NUM_LIT> , Op . getImm ( ) ) ) {


<s> static bool isVREVMask ( ArrayRef < int > M , EVT VT , unsigned BlockSize ) { assert ( ( BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> || BlockSize == <NUM_LIT> ) && <STR_LIT> ) ; unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ;

if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ;


<s> <STR_LIT> BlockMask = CreateVPTBlock ( MBIter , EndIter , DeadInstructions ) ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( unsigned ) BlockMask << <STR_LIT> ) ; if ( MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI , TRI , NewOpcode ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; VCMP -> dump ( ) ) ; MIBuilder = BuildMI ( Block , MI , DL , TII -> get ( NewOpcode ) ) ; MIBuilder . addImm ( ( uint64_t ) BlockMask ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; for ( MachineInstr & MII : make_range ( VCMP -> getIterator ( ) , MI -> getIterator ( ) ) ) { MII . clearRegisterKills ( VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRI ) ; MII . clearRegisterKills ( VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRI ) ; } VCMP -> eraseFromParent ( ) ; } else { MIBuilder = BuildMI ( Block , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIBuilder . addImm ( ( uint64_t ) BlockMask ) ; }

for ( MachineInstr * DeadMI : DeadInstructions ) DeadMI -> eraseFromParent ( ) ;


<s> case CONST : case LABEL_REF : case SYMBOL_REF : case CONST_DOUBLE : if ( src != const0_rtx ) base_cost += pdp11_addr_cost ( src , mode , ADDR_SPACE_GENERIC , speed ) ; return base_cost ; default : break ; } if ( FLOAT_MODE_P ( mode ) && ( op == FLOAT_TRUNCATE || op == FLOAT_EXTEND || op == FIX || op == FLOAT ) ) { src2 = XEXP ( src , <NUM_LIT> ) ; base_cost += pdp11_addr_cost ( src2 , mode , ADDR_SPACE_GENERIC , speed ) ; } else if ( op != SUBREG && op != UNSPEC && GET_RTX_LENGTH ( op ) > <NUM_LIT> ) {


<s> for ( set_info * set : sets ) { if ( read_vl_insn_p ( set -> insn ( ) -> rtl ( ) ) ) { const insn_info * insn = get_backward_fault_first_load_insn ( set -> insn ( ) ) ; if ( insn == info1 . get_insn ( ) ) return info2 . compatible_vtype_p ( info1 ) ; } } } return false ;


<s> assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) ) ; return ( Base << <NUM_LIT> ) | Disp ;


<s> MCAsmBackend * llvm :: createThumbLEAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU ) {

return create<ISA_LIT>AsmBackend ( T , MRI , TT , CPU , true ) ;


<s> machine_mode mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; rtx dest = operands [ <NUM_LIT> ] ; rtx src = operands [ <NUM_LIT> ] ; rtx addr ; if ( GET_CODE ( src ) == MEM ) addr = XEXP ( src , <NUM_LIT> ) ; else if ( GET_CODE ( dest ) == MEM ) addr = XEXP ( dest , <NUM_LIT> ) ; else addr = NULL_RTX ; unsigned int base_length ; switch ( mode ) { case E_QImode : if ( addr == NULL_RTX ) return <NUM_LIT> ; if ( h8300_eightbit_constant_address_p ( addr ) ) return <NUM_LIT> ; base_length = <NUM_LIT> ; break ; case E_HImode : if ( addr == NULL_RTX ) { if ( REG_P ( src ) ) return <NUM_LIT> ; if ( src == const0_rtx ) return <NUM_LIT> ; return <NUM_LIT> ; } base_length = <NUM_LIT> ; break ; case E_SImode : if ( addr == NULL_RTX ) { if ( REG_P ( src ) ) { if ( REGNO ( src ) == MAC_REG || REGNO ( dest ) == MAC_REG ) return <NUM_LIT> ; else return <NUM_LIT> ; } if ( GET_CODE ( src ) == CONST_INT ) { int val = INTVAL ( src ) ; if ( val == <NUM_LIT> ) return <NUM_LIT> ; if ( val == ( val & <NUM_LIT> ) || val == ( val & <NUM_LIT> ) ) return <NUM_LIT> ; switch ( val & <NUM_LIT> ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; } } return <NUM_LIT> ;


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( ) ;

MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ;


<s> else if ( Op . readsReg ( ) && Op . getReg ( ) . isPhysical ( ) ) PhysRegUses . insert ( Op . getReg ( ) ) ; } }


<s> unsigned getVmcntBitMask ( const IsaVersion & Version ) { unsigned VmcntLo = ( <NUM_LIT> << getVmcntBitWidthLo ( ) ) - <NUM_LIT> ;

if ( Version . Major < <NUM_LIT> ) return VmcntLo ;


<s> if ( RelocM == Reloc :: PIC_ || RelocM == Reloc :: DynamicNoPIC ) { const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getConstTextCoalSection ( ) ) ; if ( RelocM == Reloc :: DynamicNoPIC ) { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } else { const MCSection * sect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } const MCSection * StaticInitSect = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_REGULAR | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( StaticInitSect ) ; } } OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; if ( Subtarget -> isTargetELF ( ) ) { std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString != <STR_LIT> ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CPUString ) ) ; if ( Subtarget -> hasVFP2 ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( <STR_LIT> ) + <STR_LIT> ) ; if ( ! UnsafeFPMath ) { OutStreamer . EmitRawText ( <STR_LIT> + Twine ( <STR_LIT> ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( <STR_LIT> ) + <STR_LIT> ) ; } if ( NoInfsFPMath && NoNaNsFPMath ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( <STR_LIT> ) + <STR_LIT> ) ; else OutStreamer . EmitRawText ( <STR_LIT> + Twine ( <STR_LIT> ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( <STR_LIT> ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( <STR_LIT> ) + <STR_LIT> ) ; if ( Subtarget -> isAAPCS_ABI ( ) && FloatABIType == FloatABI :: Hard ) { OutStreamer . EmitRawText ( <STR_LIT> + Twine ( <STR_LIT> ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( <STR_LIT> ) + <STR_LIT> ) ; } }


<s> for ( MachineBasicBlock * Succ : BB -> successors ( ) ) { for ( MachineInstr & MI : * Succ ) { if ( ! MI . isPHI ( ) ) break ; for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { unsigned IncomingReg = MI . getOperand ( I ) . getReg ( ) ; MachineOperand & FromBB = MI . getOperand ( I + <NUM_LIT> ) ; if ( BB == FromBB . getMBB ( ) ) { if ( SplitDefRegs . count ( IncomingReg ) ) FromBB . setMBB ( SplitBB ) ; break ; } } } } MF -> insert ( ++ MachineFunction :: iterator ( BB ) , SplitBB ) ; SplitBB -> splice ( SplitBB -> begin ( ) , BB , SplitPoint , BB -> end ( ) ) ; SplitBB -> transferSuccessors ( BB ) ;


<s> case POST_MODIFY : o = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; post_modify : code = POST_MODIFY ; swap = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } r = XEXP ( addr , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , gen_rtx_fmt_ee ( code , Pmode , r , gen_rtx_PLUS ( Pmode , r , o ) ) , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , plus_constant ( Pmode , r , <NUM_LIT> ) , <NUM_LIT> ) ; } else { xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ; xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ; } } if ( reg_overlap_mentioned_p ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ) { swap = <NUM_LIT> ; gcc_assert ( ! reg_overlap_mentioned_p ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ) ; } operands [ <NUM_LIT> + swap ] = xop [ <NUM_LIT> ] ; operands [ <NUM_LIT> + swap ] = xop [ <NUM_LIT> ] ; operands [ <NUM_LIT> - swap ] = xop [ <NUM_LIT> ] ; operands [ <NUM_LIT> - swap ] = xop [ <NUM_LIT> ] ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ;


<s> } else { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; }


<s> bool <ISA_LIT>FrameLowering :: hasBP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;

return MFI -> hasVarSizedObjects ( ) && TRI -> needsStackRealignment ( MF ) ;


<s> } if ( SrcRC == <STR_LIT> && SrcReg == <STR_LIT> && DestRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) ; return true ; } if ( DestRC == <STR_LIT> && DestReg == <STR_LIT> && SrcRC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg ) ; return true ; }


<s> StackOffset = <NUM_LIT> ; UsedRegs . resize ( ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) -> getNumRegs ( ) + <NUM_LIT> ) / <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: findCommutedOpIndices ( const MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { assert ( ! MI . isBundle ( ) && <STR_LIT> ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ;

if ( ! MCID . isCommutable ( ) ) return false ;


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , DL , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , DL , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , true , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const TargetRegisterClass & RC = <STR_LIT> ; const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FPSpillSlot = MFI . CreateStackObject ( TRI . getSpillSize ( RC ) , TRI . getSpillAlignment ( RC ) , true ) ; FPSpillSlotSet = true ; return FPSpillSlot ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! TM . is<ISA_LIT>64 ( ) ) return false ; if ( ! Subtarget . isSVR4ABI ( ) ) return false ;

if ( PhysReg == <STR_LIT> ) return ( getReservedRegs ( MF ) . test ( <STR_LIT> ) ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; }


<s> typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ;

return ( unsigned long long ) __builtin_sh_media_MSHALDS_W ( ( v4hi ) mm , mn ) ;


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; if ( ! isTailCall ) { if ( isVector ) { SDValue StackPtr ; if ( is<ISA_LIT>64 ) StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; else StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getConstant ( ArgOffset , PtrVT ) ) ;


<s> static scalar_int_mode s390_unwind_word_mode ( void ) {


<s> if ( ! ( ( OpcodeN == <STR_LIT> && OpcodeN0 == <STR_LIT> ) || ( OpcodeN == <STR_LIT> && OpcodeN0 == <STR_LIT> ) ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT InVT = N0 . getValueType ( ) ; if ( N0 . getResNo ( ) != <NUM_LIT> || InVT != <STR_LIT> || ! ( VT == <STR_LIT> || VT == <STR_LIT> ) ) return SDValue ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; auto DivRemOpcode = OpcodeN0 == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;

SDValue R = DAG . getNode ( DivRemOpcode , SDLoc ( N ) , NodeTys , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ;


<s> return * ( getContext ( ) . getRegisterInfo ( ) . getRegClass ( RC ) . begin ( ) + RegNo ) ;


<s> int64_t ConstAddr = <NUM_LIT> ; Register PtrBase ; int64_t Offset ; std :: tie ( PtrBase , Offset ) = getPtrBaseWithConstantOffset ( Root . getReg ( ) , * MRI ) ; if ( Offset ) { if ( isDSOffsetLegal ( PtrBase , Offset , <NUM_LIT> ) ) { return std :: make_pair ( PtrBase , Offset ) ; } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) {

} else if ( mi_match ( Root . getReg ( ) , * MRI , m_ICst ( ConstAddr ) ) ) {


return __builtin_mve_vdupq_m_n_sv4si ( __arm_vuninitializedq_s32 ( ) , __a , __p ) ;


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; }

AttributesSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> ) ;


<s> const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ; Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ConvertFloatToBytes ( ptr , float32 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ; ConvertDoubleToBytes ( ptr , float64 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } break ; } case Type :: PointerTyID : { if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { aggBuffer -> addSymbol ( GVar , GVar ) ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr ) ; } unsigned int s = DL . getTypeAllocSize ( CPV -> getType ( ) ) ; aggBuffer -> addZeros ( s ) ; break ; } case Type :: ArrayTyID : case Type :: VectorTyID : case Type :: StructTyID : { if ( isa < ConstantAggregate > ( CPV ) || isa < ConstantDataSequential > ( CPV ) ) { int ElementSize = DL . getTypeAllocSize ( CPV -> getType ( ) ) ; bufferAggregateConstant ( CPV , aggBuffer ) ; if ( Bytes > ElementSize ) aggBuffer -> addZeros ( Bytes - ElementSize ) ; } else if ( isa < ConstantAggregateZero > ( CPV ) ) aggBuffer -> addZeros ( Bytes ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ;


<s> Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ;

const unsigned DstSz = VT . getScalarSizeInBits ( ) ;


<s> static bool isExtended ( uint64_t TSFlags ) { return ( TSFlags >> <STR_LIT> ) & <STR_LIT> ;


<s> if ( ST -> hasAVX ( ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> return isSignOrZeroExtended ( MI , true , depth ) ;


<s> static bool isPackLowMask ( ShuffleVectorSDNode * SVOp ) { EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; i ++ ) { if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , i * <NUM_LIT> ) ) return false ;


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlignment ( * RC ) , false ) ;

RS -> addScavengingFrameIndex ( RegScavFI ) ;


BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , x ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; }


<s> if ( CondCodes ) { unsigned TmpReg1 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg1 ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( TmpReg1 , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( CondCodes [ <NUM_LIT> ] ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC = getCompareCC ( Predicate ) ; assert ( ( CC != <STR_LIT> ) && <STR_LIT> ) ; <STR_LIT> invertedCC = getInvertedCondCode ( CC ) ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) . addImm ( invertedCC ) ;


<s> void setGlobalBaseReg ( unsigned Reg ) { GlobalBaseReg = Reg ;


<s> auto SectionsOr = ELF . sections ( ) ; if ( ! SectionsOr ) return SectionsOr . takeError ( ) ; for ( const auto & Sec : * SectionsOr ) { auto SecNameOr = ELF . getSectionName ( Sec ) ; if ( ! SecNameOr ) { return SecNameOr . takeError ( ) ; } else if ( * SecNameOr == Name ) { return Idx ; } ++ Idx ;


<s> sprintf ( buf , <STR_LIT> , is_ctor ? <STR_LIT> : <STR_LIT> , MAX_INIT_PRIORITY - priority ) ; sec = get_section ( buf , <NUM_LIT> , NULL ) ; } else sec = is_ctor ? ctors_section : dtors_section ; assemble_addr_to_section ( symbol , sec ) ;


<s> OutlinerCosts ( const <ISA_LIT>Subtarget & target ) : CallTailCall ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameTailCall ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallThunk ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameThunk ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallNoLRSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameNoLRSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallRegSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameRegSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallDefault ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameDefault ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , SaveRestoreLROnStack ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) {


<s> rtx_insn * and_insn ; rtx and_operation = find_alignment_op ( insn , base_reg , & and_insn ) ; if ( and_operation != <NUM_LIT> ) { rtx src_reg = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; df_ref src_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_USE ( src_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( src_use ) , src_reg ) ) continue ; struct df_link * link = DF_REF_CHAIN ( src_use ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ;

if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ;


<s> const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ; return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ;


<s> DEF ( SHUFFLELL , <STR_LIT> , ( LLUINT , LLUINT , UINT , UINT , NULL_TREE ) ) ; DEF ( WORKER_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( VECTOR_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ; DEF ( CMP_SWAP , <STR_LIT> , ( UINT , PTRVOID , UINT , UINT , NULL_TREE ) ) ;

DEF ( CMP_SWAPLL , <STR_LIT> , ( LLUINT , PTRVOID , LLUINT , LLUINT , NULL_TREE ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = DAGSize ; i != e ; ++ i ) { <ISA_LIT>ScheduleBlock * Block = CurrentBlocks [ i ] ; Block -> fastSchedule ( ) ; } MachineBasicBlock :: iterator CurrentTopFastSched = DAG -> getCurrentTop ( ) ; std :: vector < MachineBasicBlock :: iterator > PosOld ; std :: vector < MachineBasicBlock :: iterator > PosNew ; PosOld . reserve ( DAG -> SUnits . size ( ) ) ; PosNew . reserve ( DAG -> SUnits . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = DAGSize ; i != e ; ++ i ) { int BlockIndice = TopDownIndex2Block [ i ] ; <ISA_LIT>ScheduleBlock * Block = CurrentBlocks [ BlockIndice ] ; std :: vector < SUnit * > SUs = Block -> getScheduledUnits ( ) ; for ( SUnit * SU : SUs ) { MachineInstr * MI = SU -> getInstr ( ) ; MachineBasicBlock :: iterator Pos = MI ; PosOld . push_back ( Pos ) ; if ( & * CurrentTopFastSched == MI ) { PosNew . push_back ( Pos ) ; CurrentTopFastSched = nextIfDebug ( ++ CurrentTopFastSched , DAG -> getCurrentBottom ( ) ) ; } else { DAG -> getBB ( ) -> splice ( CurrentTopFastSched , DAG -> getBB ( ) , MI ) ; DAG -> getLIS ( ) -> handleMove ( * MI , true ) ; PosNew . push_back ( CurrentTopFastSched ) ; } } } for ( unsigned i = <NUM_LIT> , e = DAGSize ; i != e ; ++ i ) { <ISA_LIT>ScheduleBlock * Block = CurrentBlocks [ i ] ; std :: vector < SUnit * > SUs = Block -> getScheduledUnits ( ) ; Block -> schedule ( ( * SUs . begin ( ) ) -> getInstr ( ) , ( * SUs . rbegin ( ) ) -> getInstr ( ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( unsigned i = PosOld . size ( ) , e = <NUM_LIT> ; i != e ; -- i ) {

MachineBasicBlock :: iterator POld = PosOld [ i - <NUM_LIT> ] ;


<s> } if ( canIssueInSlot ( SU , Bundle . size ( ) ) ) { Bundle . push_back ( SU ) ; CurrWidth += Width ; return true ; } assert ( ! Bundle . empty ( ) && <STR_LIT> ) ;

if ( canIssueInSlot ( SU , <NUM_LIT> ) && canIssueInSlot ( Bundle [ <NUM_LIT> ] , Bundle . size ( ) ) ) {


<s> TotalPackets ++ ; return false ; } if ( ! isResourceAvailable ( SU ) ) { ResourcesModel -> clearResources ( ) ; savePacket ( ) ; Packet . clear ( ) ; TotalPackets ++ ; startNewCycle = true ; } if ( ! SU -> getInstr ( ) -> isPseudo ( ) ) { ResourcesModel -> reserveResources ( * SU -> getInstr ( ) ) ; Packet . push_back ( SU ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TotalPackets << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> ) ;

LLVM_DEBUG ( dbgs ( ) << Packet [ i ] -> NodeNum << <STR_LIT> ) ;


<s> CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; CommentString = <STR_LIT> ;


<s> int modrm = ix86_get_modrm_for_rop ( insn , recog_data . operand , recog_data . n_operands , & opno0 , & opno1 ) ; if ( modrm < <NUM_LIT> || ! ix86_rop_should_change_byte_p ( modrm ) || opno0 == opno1 ) continue ; rtx oldreg = recog_data . operand [ opno1 ] ; preprocess_constraints ( insn ) ; const operand_alternative * alt = which_op_alt ( ) ; int i ; for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) if ( i != opno1 && alt [ i ] . earlyclobber && reg_overlap_mentioned_p ( recog_data . operand [ i ] , oldreg ) ) break ; if ( i < recog_data . n_operands ) continue ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) , REGNO ( oldreg ) , reg_class_names [ alt [ opno1 ] . cl ] ) ; HARD_REG_SET unavailable ; REG_SET_TO_HARD_REG_SET ( unavailable , & live ) ; SET_HARD_REG_BIT ( unavailable , REGNO ( oldreg ) ) ; IOR_COMPL_HARD_REG_SET ( unavailable , call_used_reg_set ) ; IOR_HARD_REG_SET ( unavailable , fixed_reg_set ) ; IOR_HARD_REG_SET ( unavailable , output_risky ) ; IOR_COMPL_HARD_REG_SET ( unavailable , reg_class_contents [ alt [ opno1 ] . cl ] ) ;

for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( ! TEST_HARD_REG_BIT ( unavailable , i ) ) break ;


return CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DebugLoc :: getUnknownLoc ( ) , RA , <STR_LIT> ) ;


<s> if ( isa < ScalableVectorType > ( Arg . getType ( ) ) ) return false ; if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , <NUM_LIT> ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ;

handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ;


<s> __inline__ static void sh_media_FPUTSCR ( float fg ) {

__asm__ ( <STR_LIT> : : <STR_LIT> ( fg ) ) ;


<s> <ISA_LIT>MCELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter ) : MCELFStreamer ( Context , TAB , OS , Emitter ) , MCII ( create<ISA_LIT>MCInstrInfo ( ) ) {


<s> if ( ! IsMemcpy ) return true ; if ( ! ConstantSize && Alignment >= Align ( <NUM_LIT> ) ) return true ;

if ( ConstantSize && ConstantSize -> getZExtValue ( ) > Subtarget . getMaxInlineSizeThreshold ( ) && ConstantSize -> getZExtValue ( ) < Subtarget . getMaxMemcpyTPInlineSizeThreshold ( ) ) return true ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> vec_uint4 neg_b ; vec_uint4 mask ; neg_b = vec_splat ( ( vec_uint4 ) ( si_from_int ( - b ) ) , <NUM_LIT> ) ;

mask = vec_sra ( vec_sl ( neg_b , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ;


<s> else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , false , false , isKill ) ;


<s> for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DR , TRI ) << <STR_LIT> << printReg ( HiR , TRI ) << ':' << printReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } }


<s> case CONST_INT : if ( satisfies_constraint_I ( x ) ) { * total = <NUM_LIT> ; return true ; } else if ( outer_code == PLUS && add_operand ( x , VOIDmode ) ) { * total = <NUM_LIT> ; return true ; } else if ( move_operand ( x , SImode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } return false ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case CONST_DOUBLE : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case HIGH : * total = <NUM_LIT> ; return true ; case MEM : if ( outer_code == ZERO_EXTEND || outer_code == SIGN_EXTEND ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && cint_248_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , VOIDmode ) ) { * total = ( rtx_cost ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , mode , ( enum rtx_code ) outer_code , opno , speed ) + rtx_cost ( XEXP ( x , <NUM_LIT> ) , mode , ( enum rtx_code ) outer_code , opno , speed ) + COSTS_N_INSNS ( <NUM_LIT> ) ) ; return true ; } return false ; case MULT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> return ( uint64x1_t ) { __builtin_aarch64_ushldi_uus ( __a [ <NUM_LIT> ] , __b [ <NUM_LIT> ] ) } ;


<s> if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; moveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ;


<s> unsigned ShiftAmt = RHS -> getZExtValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { if ( auto * Mask = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ) { if ( Mask -> getAPIntValue ( ) . isShiftedMask ( ) && Mask -> getAPIntValue ( ) . countTrailingZeros ( ) == ShiftAmt ) { return DAG . getNode ( <STR_LIT> , SL , VT , DAG . getNode ( <STR_LIT> , SL , VT , LHS . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , SL , VT , LHS . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ; } } } if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( ShiftAmt < <NUM_LIT> ) return SDValue ( ) ;

SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : return <STR_LIT> ; case VK_<ISA_LIT>_HI : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_LO : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_GOT_HI : return <STR_LIT> ; }


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _readfsbase_u32 ( void ) { return __builtin_ia32_rdfsbase32 ( ) ;


<s> BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; const unsigned Regs = getRegs ( Opcode ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; assert ( CI . I -> hasOneMemOperand ( ) && CI . Paired -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ;

const MachineMemOperand * MMOb = * CI . Paired -> memoperands_begin ( ) ;


<s> void adds3_0ImmOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst , N ) ;


<s> return TARGET_64BIT && ix86_cfun_abi ( ) != MS_ABI ; case ST0_REG : case ST1_REG : if ( TARGET_64BIT && ix86_cfun_abi ( ) == MS_ABI ) return false ; return TARGET_FLOAT_RETURNS_IN_80387 ; case XMM0_REG : case XMM1_REG : return TARGET_SSE ; case MM0_REG : if ( TARGET_MACHO || TARGET_64BIT ) return false ; return TARGET_MMX ;


<s> tmp1 = simplify_gen_subreg ( HImode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; tmp2 = simplify_gen_subreg ( QImode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; emit_insn ( gen_udivmodhiqi3 ( tmp0 , tmp1 , tmp2 ) ) ; if ( signed_p ) { div = gen_rtx_DIV ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; mod = gen_rtx_MOD ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { div = gen_rtx_UDIV ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; mod = gen_rtx_UMOD ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } tmp1 = gen_rtx_ZERO_EXTRACT ( mode , tmp0 , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; if ( REG_P ( operands [ <NUM_LIT> ] ) ) insn = emit_move_insn ( operands [ <NUM_LIT> ] , tmp1 ) ; else { scratch = gen_reg_rtx ( mode ) ;


<s> default_file_start ( ) ; if ( X86_FILE_START_VERSION_DIRECTIVE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( X86_FILE_START_FLTUSED ) fputs ( <STR_LIT> , asm_out_file ) ; if ( ix86_asm_dialect == ASM_INTEL ) fputs ( <STR_LIT> , asm_out_file ) ;


<s> return DAG . ComputeMaxSignificantBits ( Op ) ;


<s> int ft32_is_mem_pm ( rtx o ) { return ( MEM_P ( o ) && ! ADDR_SPACE_GENERIC_P ( MEM_ADDR_SPACE ( o ) ) ) ;


<s> void <ISA_LIT>StackTagging :: untagAlloca ( AllocaInst * AI , Instruction * InsertBefore , uint64_t Size ) { IRBuilder < > IRB ( InsertBefore ) ; IRB . CreateCall ( SetTagFunc , { IRB . CreatePointerCast ( AI , IRB . getInt8PtrTy ( ) ) , ConstantInt :: get ( IRB . getInt64Ty ( ) , Size ) } ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_GPR ) && <STR_LIT> ) ;

AsmParser . warnIfAssemblerTemporary ( RegIdx . Index , StartLoc ) ;


<s> return ( int8x16_t ) __builtin_neon_vshrs_nv16qi ( __a , __b ) ;


<s> Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_TLVP , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; if ( MO . isJTI ( ) && MAI . hasSetDirective ( ) ) { MCSymbol * Label = Ctx . CreateTempSymbol ( ) ; AsmPrinter . OutStreamer . EmitAssignment ( Label , Expr ) ; Expr = MCSymbolRefExpr :: Create ( Label , Ctx ) ; } break ; } if ( Expr == <NUM_LIT> ) Expr = MCSymbolRefExpr :: Create ( Sym , RefKind , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: CreateExpr ( Expr ) ;


<s> if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; TII . restoreFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ;


<s> bool Changed = false ; InstrsToRemove . clear ( ) ; for ( MachineBasicBlock & MBB : MF ) for ( MachineInstr & MI : MBB ) Changed |= processInstr ( MI ) ; for ( MachineInstr * MI : InstrsToRemove ) MI -> eraseFromParent ( ) ;


<s> void printMemRegImmShifted ( const MachineInstr * MI , unsigned OpNo ) { if ( MI -> getOperand ( OpNo ) . isImm ( ) ) printS16X4ImmOperand ( MI , OpNo ) ; else printSymbolLo ( MI , OpNo ) ; O << '(' ; if ( MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else printOperand ( MI , OpNo + <NUM_LIT> ) ; O << ')' ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> uint64_t MulAmt2 = <NUM_LIT> ; if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } SDLoc DL ( N ) ; SDValue NewMul ; if ( MulAmt2 && ( isPowerOf2_64 ( MulAmt2 ) || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> ) ) { if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , DL , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , DL , <STR_LIT> ) ) ;

else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( MulAmt2 , DL , VT ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isWhileOpcode ( unsigned Opc ) const {

return get ( Opc ) . TSFlags & <STR_LIT> ;


<s> __builtin_ia32_directstoreu_u64 ( ( unsigned long long * ) __P , __A ) ;


<s> MCSymbol * OffsetSym = MF . getMMI ( ) . getContext ( ) . getOrCreateParentFrameOffsetSymbol ( GlobalValue :: dropLLVMManglingEscape ( Fn -> getName ( ) ) ) ; SDValue OffsetSymVal = DAG . getMCSymbol ( OffsetSym , PtrVT ) ; SDValue ParentFrameOffset = DAG . getNode ( <STR_LIT> , dl , PtrVT , OffsetSymVal ) ; const <ISA_LIT>Subtarget & Subtarget = DAG . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , EntryEBP , ParentFrameOffset ) ;

int RegNodeSize = getSEHRegistrationNodeSize ( Fn ) ;


<s> if ( lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP ) ) OutMI . addOperand ( MCOp ) ; } switch ( OutMI . getOpcode ( ) ) { case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : { const Function & F = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return false ; AP . emitNops ( Num ) ; return true ; } break ; } case <STR_LIT> : OutMI . setOpcode ( <STR_LIT> ) ;

OutMI . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) ) ;