<s> SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) {

default : llvm_unreachable ( <STR_LIT> ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) {

return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCRegInfo ( <STR_LIT> ) ) ;


<s> if ( isImm ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( a . getReg ( ) ) . addImm ( b . getImm ( ) ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( a . getReg ( ) ) . addReg ( b . getReg ( ) ) ; } bytesAdded += <NUM_LIT> ; switch ( ConditionCode ) { case <STR_LIT> :: SETEQ : case <STR_LIT> :: SETUEQ : JmpOpcode = <STR_LIT> ; break ; case <STR_LIT> :: SETGT : JmpOpcode = <STR_LIT> ; break ; case <STR_LIT> :: SETUGT : JmpOpcode = <STR_LIT> ; break ; case <STR_LIT> :: SETUGE : JmpOpcode = <STR_LIT> ; break ; case <STR_LIT> :: SETGE : JmpOpcode = <STR_LIT> ; break ; case <STR_LIT> :: SETLT : JmpOpcode = <STR_LIT> ; break ; case <STR_LIT> :: SETULT : JmpOpcode = <STR_LIT> ; break ; case <STR_LIT> :: SETLE : JmpOpcode = <STR_LIT> ; break ; case <STR_LIT> :: SETULE : JmpOpcode = <STR_LIT> ; break ;


<s> if ( flags . R4 ( ) ) s . push_back ( <STR_LIT> ) ; if ( flags . Cfgi ( ) ) s . push_back ( <STR_LIT> ) ; if ( flags . R7 ( ) ) s . push_back ( <STR_LIT> ) ; if ( flags . Cfgj ( ) ) s . push_back ( <STR_LIT> ) ;


<s>
void
<ISA_LIT>AsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
*
MI
<<
'\n'
)
;
SmallString
<
<NUM_LIT>
>
Str
;
raw_svector_ostream
OS
(
Str
)
;
unsigned
NumDefs
=
MI
->
getDesc
(
)
.
getNumDefs
(
)
;
assert
(
NumDefs
<=
<NUM_LIT>
&&
<STR_LIT>
)
;
OS
<<
'\t'
;
switch
(
MI
->
getOpcode
(
)
)
{
case
TargetOpcode
::
COPY
:
OS
<<
regToString
(
MI
->
getOperand
(
<NUM_LIT>
)
.
getReg
(
)
)
;
break
;
case
<STR_LIT>
:
OS
<<
<STR_LIT>
<<
toSymbol
(
MI
->
getOperand
(
<NUM_LIT>
)
.
getGlobal
(
)
->
getName
(
)
)
;
break
;
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
OS
<<
argToString
(
MI
->
getOperand
(
<NUM_LIT>
)
.
getImm
(
)
)
;
break
;
case
<STR_LIT>
:
OS
<<
<STR_LIT>
<<
MI
->
getOperand
(
<NUM_LIT>
)
.
getImm
(
)
;
break
;
case
<STR_LIT>
:
OS
<<
<STR_LIT>
<<
MI
->
getOperand
(
<NUM_LIT>
)
.
getImm
(
)
;
break
;
case
<STR_LIT>
:
OS
<<
<STR_LIT>
<<
toString
(
MI
->
getOperand
(
<NUM_LIT>
)
.
getFPImm
(
)
->
getValueAPF
(
)
)
;
break
;
case
<STR_LIT>
:
OS
<<
<STR_LIT>
<<
toString
(
MI
->
getOperand
(
<NUM_LIT>
)
.
getFPImm
(
)
->
getValueAPF
(
)
)
;
break
;
default
:
{
OS
<<
OpcodeName
(
TII
,
MI
)
;
bool
NeedComma
=
false
;
for
(
const
MachineOperand
&
MO
:
MI
->
uses
(
)
)
{
if
(
MO
.
isReg
(
)
&&
MO
.
isImplicit
(
)
)
continue
;
if
(
NeedComma
)
OS
<<
','
;
NeedComma
=
true
;
OS
<<
' '
;
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
<STR_LIT>
)
;
case
MachineOperand
::
MO_Register
:
OS
<<
regToString
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
OS
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
OS
<<
toString
(
MO
.
getFPImm
(
)
->
getValueAPF
(
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
OS
<<
toSymbol
(
MO
.
getGlobal
(
)
->
getName
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
OS
<<
toSymbol
(
MO
.
getMBB
(
)
->
getSymbol
(
)
->
getName
(
)
)
;
break
;
}
}


<s> bool ok ; if ( d -> one_operand_p ) return false ; if ( TARGET_AVX2 && GET_MODE_SIZE ( vmode ) == <NUM_LIT> ) ; else if ( TARGET_AVX && ( vmode == V4DFmode || vmode == V8SFmode ) ) ; else if ( TARGET_SSE4_1 && ( GET_MODE_SIZE ( vmode ) == <NUM_LIT> || GET_MODE_SIZE ( vmode ) == <NUM_LIT> || GET_MODE_SIZE ( vmode ) == <NUM_LIT> ) ) ; else return false ; for ( i = <NUM_LIT> , which = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned e = d -> perm [ i ] ; if ( e != i ) which |= ( e < nelt ? <NUM_LIT> : <NUM_LIT> ) ; } if ( which != <NUM_LIT> && which != <NUM_LIT> ) return false ; if ( d -> testing_p && GET_MODE_SIZE ( vmode ) == <NUM_LIT> ) return true ; dcopy = * d ; if ( which == <NUM_LIT> ) dcopy . op0 = dcopy . op1 = d -> op1 ; else dcopy . op0 = dcopy . op1 = d -> op0 ; if ( ! d -> testing_p ) dcopy . target = gen_reg_rtx ( vmode ) ; dcopy . one_operand_p = true ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) dcopy . perm [ i ] = d -> perm [ i ] & ( nelt - <NUM_LIT> ) ; ok = expand_vec_perm_1 ( & dcopy ) ; if ( GET_MODE_SIZE ( vmode ) != <NUM_LIT> && ! ok ) return false ; else gcc_assert ( ok ) ; if ( d -> testing_p ) return true ; dcopy1 = * d ; if ( which == <NUM_LIT> ) dcopy1 . op1 = dcopy . target ; else dcopy1 . op0 = dcopy . target ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) dcopy1 . perm [ i ] = ( ( d -> perm [ i ] >= nelt ) ? ( nelt + i ) : i ) ; ok = expand_vec_perm_blend ( & dcopy1 ) ;


<s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case Register : Reg = o . Reg ; break ; case RegisterSeq : RegSeq = o . RegSeq ; break ; case CPOP : CPool = o . CPool ; break ; case Immediate :


<s> bits = real_to_target ( NULL , & r , HFmode ) ; if ( WORDS_BIG_ENDIAN ) assemble_zeros ( <NUM_LIT> ) ;


<s> else if ( Subtarget -> isPICStyleStubPIC ( ) ) OpFlag = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) , CP -> getOffset ( ) , OpFlag ) ; Result . getNode ( ) -> setTrapInfo ( Op -> getTrapInfo ( ) ) ; SDLoc DL ( CP ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( OpFlag ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Result ) ; }


<s> <ISA_LIT>DCModule :: <ISA_LIT>DCModule ( DCTranslator & DCT , Module & M ) : DCModule ( DCT , M ) {


<s> return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ;


<s> void neg ( uint64_t & Value ) { Value *= - <NUM_LIT> ;


<s> rtx mem = plus_constant ( Pmode , stack_pointer_rtx , adjustment ) ; mem = gen_rtx_POST_MODIFY ( Pmode , stack_pointer_rtx , mem ) ; emit_move_insn ( reg1 , gen_frame_mem ( mode , mem ) ) ; } else {

rtx reg2 = gen_rtx_REG ( mode , regno2 ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { SDValue S0 = Op . getOperand ( <NUM_LIT> ) ; if ( S0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT == <STR_LIT> ) return LowerINT_TO_FP64 ( Op , DAG , false ) ; assert ( DestVT == <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , S0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FloatLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , S0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue FloatHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ;

FloatHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FloatHi , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> Optional < int64_t > Op0 = getIfConst ( I -> getOperand ( <NUM_LIT> ) ) ; Optional < int64_t > Op1 = getIfConst ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0 || ! Op1 ) return Optional < int64_t > { } ; if ( I -> getOpcode ( ) == Instruction :: Add ) return Optional < int64_t > { Op0 . getValue ( ) + Op1 . getValue ( ) } ; if ( I -> getOpcode ( ) == Instruction :: Mul ) return Optional < int64_t > { Op0 . getValue ( ) * Op1 . getValue ( ) } ; } return Optional < int64_t > { } ;


<s> return ; } if ( ! ca -> reg_used [ <NUM_LIT> ] && ca -> can_split ) { ca -> reg_count = <NUM_LIT> ; ca -> mem_count = <NUM_LIT> ; ca -> start_reg = CA_FIRST_REG + <NUM_LIT> ; return ; } break ; case <NUM_LIT> : case <NUM_LIT> : ca -> can_split = <NUM_LIT> ; if ( ! ca -> reg_used [ <NUM_LIT> ] && ! ca -> reg_used [ <NUM_LIT> ] && ! ca -> reg_used [ <NUM_LIT> ] && ! ca -> reg_used [ <NUM_LIT> ] ) { ca -> reg_count = <NUM_LIT> ; ca -> start_reg = CA_FIRST_REG ; return ;


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : { if ( AsmVariant == <NUM_LIT> ) O << '%' ; unsigned Reg = MO . getReg ( ) ; if ( Modifier && strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT> ) ) == <NUM_LIT> ) { <STR_LIT> VT = ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : ( ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; Reg = get<ISA_LIT>SubSuperRegister ( Reg , VT ) ; } O << <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ; return ; } case MachineOperand :: MO_Immediate : O << '$' << MO . getImm ( ) ; return ; case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : { O << '$' ; printSymbolOperand ( MO , O ) ; break ;


<s> add_vector_labels ( file , <STR_LIT> ) ; if ( is_fast_interrupt_func ( NULL_TREE ) ) asm_fprintf ( file , <STR_LIT> ) ;

if ( is_interrupt_func ( NULL_TREE ) ) asm_fprintf ( file , <STR_LIT> ) ;


<s> ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( dest ) . addReg ( oldval ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( newval ) . addReg ( ptr ) ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loop1MBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loop1MBB ) ;


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ;

GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * I -> getTargetLowering ( ) ) ) ;


<s> SDValue Chain = DAG . getEntryNode ( ) ; SDValue Glue ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) report_fatal_error ( <STR_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , GOT , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , GOTOffset , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getTargetGlobalAddress ( Node -> getGlobal ( ) , DL , Node -> getValueType ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ;

const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ;


<s> if ( TARGET_ALTIVEC ) return altivec_builtin_mask_for_load ; else return <NUM_LIT> ;


<s> return ( uint8x8_t ) __builtin_neon_vcgtv8qi ( __b , __a ) ;


<s> parseAccessReg ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Percent ) ) return MatchOperand_NoMatch ; Register Reg ; if ( parseRegister ( Reg , RegAccess , nullptr ) ) return MatchOperand_ParseFail ;

Operands . push_back ( <ISA_LIT>Operand :: createAccessReg ( Reg . Num , Reg . StartLoc , Reg . EndLoc ) ) ;


<s> int fpr_reg_base ; int gpr_reg_base ; rtx retval ; if ( mode == VOIDmode ) return NULL_RTX ; arg_size = FUNCTION_ARG_SIZE ( mode , type ) ; if ( ! TARGET_64BIT ) { if ( cum -> words + arg_size > max_arg_words ) return NULL_RTX ; } else { if ( arg_size > <NUM_LIT> ) alignment = cum -> words & <NUM_LIT> ; if ( cum -> words + alignment >= max_arg_words ) return NULL_RTX ; } if ( TARGET_64BIT ) { gpr_reg_base = <NUM_LIT> - cum -> words ; fpr_reg_base = <NUM_LIT> + cum -> words ; if ( arg_size > <NUM_LIT> || mode == BLKmode || ( type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { rtx loc [ <NUM_LIT> ] ; int i , offset = <NUM_LIT> , ub = arg_size ; gpr_reg_base -= alignment ; ub = MIN ( ub , max_arg_words - cum -> words - alignment ) ; for ( i = <NUM_LIT> ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , gpr_reg_base ) , GEN_INT ( offset ) ) ; gpr_reg_base -= <NUM_LIT> ; offset += <NUM_LIT> ; } return gen_rtx_PARALLEL ( mode , gen_rtvec_v ( ub , loc ) ) ; } } else { if ( arg_size > <NUM_LIT> ) {


<s> if ( ! isTypeLegal ( EVT :: getEVT ( Ty1 ) ) ) return false ;

assert ( Ty1 -> getPrimitiveSizeInBits ( ) <= <NUM_LIT> && <STR_LIT> ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> using namespace <ISA_LIT>PACKey ; switch ( K ) { case IA : case IB : return <STR_LIT> ;


<s> int <ISA_LIT>TTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * ValTy , bool IsPairwiseForm , TTI :: TargetCostKind CostKind ) { if ( IsPairwiseForm ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ;


<s> switch ( <STR_LIT> ( Opc ) ) { default : return UNKNOWN ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return BUFFER_LOAD ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return BUFFER_STORE ; } } if ( TII . isMIMG ( Opc ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: vaddr ) == - <NUM_LIT> && <STR_LIT> ( Opc , <STR_LIT> :: vaddr0 ) == - <NUM_LIT> ) return UNKNOWN ; if ( <STR_LIT> ( Opc ) -> BVH ) return UNKNOWN ; if ( TII . get ( Opc ) . mayStore ( ) || ! TII . get ( Opc ) . mayLoad ( ) || TII . isGather4 ( Opc ) ) return UNKNOWN ; return MIMG ; } if ( TII . isMTBUF ( Opc ) ) { switch ( <STR_LIT> ( Opc ) ) { default : return UNKNOWN ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBUFFER_LOAD ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBUFFER_STORE ; } } return UNKNOWN ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return S_BUFFER_LOAD_IMM ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DS_READ ; case <STR_LIT> :


<s> static bool canWidenShuffleElements ( ArrayRef < int > Mask ) {

for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; i += <NUM_LIT> ) if ( ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] % <NUM_LIT> != <NUM_LIT> ) || ( Mask [ i + <NUM_LIT> ] != - <NUM_LIT> && ( Mask [ i + <NUM_LIT> ] % <NUM_LIT> != <NUM_LIT> || ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] + <NUM_LIT> != Mask [ i + <NUM_LIT> ] ) ) ) ) return false ;


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( Vec . getOpcode ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == VecVT ) { SDLoc DL ( ExtElt ) ; SDValue Ext0 = DAG . getNode ( <STR_LIT> , DL , Vec . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) , Vec . getOperand ( <NUM_LIT> ) , Index ) ; SDValue Ext1 = DAG . getNode ( <STR_LIT> , DL , VT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; SDValue Ext2 = DAG . getNode ( <STR_LIT> , DL , VT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ext0 , Ext1 , Ext2 ) ; } switch ( Vec . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDLoc DL ( ExtElt ) ; SmallVector < SDValue , <NUM_LIT> > ExtOps ; for ( SDValue Op : Vec -> ops ( ) ) ExtOps . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , Op , Index ) ) ; return DAG . getNode ( Vec . getOpcode ( ) , DL , VT , ExtOps ) ; } default :


<s> for ( User * AllocaUser : Alloca -> users ( ) ) { GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( AllocaUser ) ; if ( ! GEP ) { if ( ! canVectorizeInst ( cast < Instruction > ( AllocaUser ) , Alloca ) ) return false ; WorkList . push_back ( AllocaUser ) ; continue ; } Value * Index = GEPToVectorIndex ( GEP ) ; if ( ! Index ) { DEBUG ( dbgs ( ) << <STR_LIT> << * GEP << '\n' ) ; return false ; } GEPVectorIdx [ GEP ] = Index ; for ( User * GEPUser : AllocaUser -> users ( ) ) { if ( ! canVectorizeInst ( cast < Instruction > ( GEPUser ) , AllocaUser ) ) return false ; WorkList . push_back ( GEPUser ) ; } } VectorType * VectorTy = arrayTypeToVecType ( AllocaTy ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * AllocaTy << <STR_LIT> << * VectorTy << '\n' ) ; for ( Value * V : WorkList ) {

Instruction * Inst = cast < Instruction > ( V ) ;


<s> return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> :

return performSUBCombine ( N , DAG , DCI , Subtarget ) ;


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue PSHUFB = lowerVectorShuffleWithPSHUFB ( DL , <STR_LIT> , Mask , V1 , V2 , Zeroable , Subtarget , DAG ) ) return PSHUFB ; if ( Subtarget . hasVBMI ( ) ) return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG , true ) ;


<s> if ( MCPE . isMachineConstantPoolEntry ( ) ) { <ISA_LIT>ConstantPoolValue * ACPV = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE . Val . MachineCPVal ) ; DOUT << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << * ACPV << '\n' ; GlobalValue * GV = ACPV -> getGV ( ) ; if ( GV ) { Reloc :: Model RelocM = TM . getRelocationModel ( ) ; emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) , ( intptr_t ) ACPV ) ; } else { emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ;

} else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) {


<s> bool RanOutOfSGPRs = false ; unsigned SOffset = ScratchOffset ; unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; unsigned Size = NumSubRegs * <NUM_LIT> ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size ) ) { SOffset = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; if ( SOffset == <STR_LIT> ) { RanOutOfSGPRs = true ; SOffset = <STR_LIT> ; } BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SOffset ) . addReg ( ScratchOffset ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; } if ( RanOutOfSGPRs ) Ctx . emitError ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i != e ; ++ i , Offset += <NUM_LIT> ) { unsigned SubReg = NumSubRegs > <NUM_LIT> ? getPhysRegSubReg ( Value , & <STR_LIT> , i ) : Value ; BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . addReg ( SubReg , getDefRegState ( IsLoad ) ) . addReg ( ScratchRsrcReg ) . addReg ( SOffset ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( Value , RegState :: Implicit | getDefRegState ( IsLoad ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; }


<s> type_suffix_index suffix = find_type_suffix ( tclass , element_bits ) ; return scalar_types [ type_suffixes [ suffix ] . vector_type ] ;


<s> bool Result = AsmPrinter :: runOnMachineFunction ( F ) ; OutStreamer -> emitRawText ( StringRef ( <STR_LIT> ) ) ; return Result ;


<s> if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( TFI -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } assert ( ! MI . isDebugValue ( ) && <STR_LIT> ) ; bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ; unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ; if ( Offset == <NUM_LIT> ) MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , false ) ;


<s> SelectRoot ( * CurDAG ) ; DOUT ( llvm :: dbgs ( ) << <STR_LIT> ; CurDAG -> RemoveDeadNodes ( ) ;


<s> if ( JumpMI -> getParent ( ) != LEAMI -> getParent ( ) ) return false ; unsigned EntryReg = JumpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = LEAMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CanDeleteLEA = true ; BaseRegKill = false ; MachineInstr * RemovableAdd = nullptr ; MachineBasicBlock :: iterator I ( LEAMI ) ; for ( ++ I ; & * I != JumpMI ; ++ I ) { if ( isSimpleIndexCalc ( * I , EntryReg , BaseReg ) ) { RemovableAdd = & * I ; break ; } for ( unsigned K = <NUM_LIT> , E = I -> getNumOperands ( ) ; K != E ; ++ K ) { const MachineOperand & MO = I -> getOperand ( K ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) == BaseReg ) return false ; if ( MO . isUse ( ) && MO . getReg ( ) == BaseReg ) { BaseRegKill = BaseRegKill || MO . isKill ( ) ; CanDeleteLEA = false ; } }


<s> assert ( N . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( N ) ; SmallVector < SDValue , <NUM_LIT> > Chain ; SDValue V = N . getOperand ( <NUM_LIT> ) ; for ( ; V . hasOneUse ( ) ; V = V . getOperand ( <NUM_LIT> ) ) { switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : continue ; case <STR_LIT> : break ; case <STR_LIT> : if ( Mask [ <NUM_LIT> ] != <NUM_LIT> || Mask [ <NUM_LIT> ] != <NUM_LIT> || ! ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) return SDValue ( ) ; Chain . push_back ( V ) ; continue ; case <STR_LIT> : if ( Mask [ <NUM_LIT> ] != <NUM_LIT> || Mask [ <NUM_LIT> ] != <NUM_LIT> || ! ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) return SDValue ( ) ; Chain . push_back ( V ) ; continue ; case <STR_LIT> : case <STR_LIT> : if ( V . getSimpleValueType ( ) . getScalarType ( ) != <STR_LIT> && V . getSimpleValueType ( ) . getScalarType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned CombineOp = V . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( V . getOperand ( <NUM_LIT> ) != V . getOperand ( <NUM_LIT> ) || ! V -> isOnlyUserOf ( V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return SDValue ( ) ; Chain . push_back ( V ) ; V = V . getOperand ( <NUM_LIT> ) ; do { switch ( V . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> :

if ( V . getOpcode ( ) == CombineOp ) break ;


<s> OutStreamer -> GetOS ( ) << <STR_LIT> ; static_cast < formatted_raw_ostream & > ( OutStreamer -> GetOS ( ) ) . PadToColumn ( <NUM_LIT> + depth ) ; EmitToStreamer ( * OutStreamer , curInst ) ; if ( curInst . getOpcode ( ) == <STR_LIT> ) EmitSubBlockForPushcont ( lower , curInst , depth + <NUM_LIT> ) ; } } if ( isVerbose ( ) ) { auto MIit = Mapping . find ( & Inst ) ; if ( MIit != Mapping . end ( ) ) for ( auto & Comment : MFI -> getStackModelComments ( MIit -> second ) ) OutStreamer -> AddComment ( Comment ) ; }

OutStreamer
->
EmitRawText
(
<STR_LIT>
+
std
::
string
(
depth
,
' '
)
+
<STR_LIT>
)
;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ;


<s> if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != <NUM_LIT> ) tmp_regno = AX_REG ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != <NUM_LIT> ) tmp_regno = DX_REG ; else tmp_regno = CX_REG ; } emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( REG_P ( this_param ) ) this_reg = this_param ; else if ( vcall_offset ) { this_reg = gen_rtx_REG ( Pmode , AX_REG ) ; emit_move_insn ( this_reg , this_param ) ; } else this_reg = NULL_RTX ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; rtx delta_dst = this_reg ? this_reg : this_param ; if ( TARGET_64BIT ) { if ( ! x86_64_general_operand ( delta_rtx , Pmode ) ) { tmp = gen_rtx_REG ( Pmode , tmp_regno ) ; emit_move_insn ( tmp , delta_rtx ) ; delta_rtx = tmp ; } } ix86_emit_binop ( PLUS , Pmode , delta_dst , delta_rtx ) ; } if ( vcall_offset ) { rtx vcall_addr , vcall_mem , this_mem ; tmp = gen_rtx_REG ( Pmode , tmp_regno ) ; this_mem = gen_rtx_MEM ( ptr_mode , this_reg ) ; if ( Pmode != ptr_mode ) this_mem = gen_rtx_ZERO_EXTEND ( Pmode , this_mem ) ; emit_move_insn ( tmp , this_mem ) ; vcall_addr = plus_constant ( Pmode , tmp , vcall_offset ) ; if ( TARGET_64BIT && ! ix86_legitimate_address_p ( ptr_mode , vcall_addr , true ) ) { rtx tmp2 = gen_rtx_REG ( Pmode , R11_REG ) ; emit_move_insn ( tmp2 , GEN_INT ( vcall_offset ) ) ; vcall_addr = gen_rtx_PLUS ( Pmode , tmp , tmp2 ) ; } vcall_mem = gen_rtx_MEM ( ptr_mode , vcall_addr ) ; if ( Pmode != ptr_mode ) emit_insn ( gen_addsi_1_zext ( this_reg , gen_rtx_REG ( ptr_mode , REGNO ( this_reg ) ) , vcall_mem ) ) ; else ix86_emit_binop ( PLUS , Pmode , this_reg , vcall_mem ) ; } if ( this_reg && this_reg != this_param ) emit_move_insn ( this_param , this_reg ) ; fnaddr = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( TARGET_64BIT ) { if ( ! flag_pic || targetm . binds_local_p ( function ) || TARGET_PECOFF ) ; else { tmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , fnaddr ) , UNSPEC_GOTPCREL ) ; tmp = gen_rtx_CONST ( Pmode , tmp ) ; fnaddr = gen_const_mem ( Pmode , tmp ) ; } } else {

if ( ! flag_pic || targetm . binds_local_p ( function ) ) ;


<s> return <ISA_LIT>_EXPAND_PSEUDO_NAME ;


<s> if ( ( fnmask & RS6000_BTM_CELL ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_VSX ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_HTM ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_ALTIVEC ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) == ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_DFP ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P9_MISC ) == RS6000_BTM_P9_MISC ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_P10 ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_MMA ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_LDBL128 ) == RS6000_BTM_LDBL128 ) { if ( ! TARGET_HARD_FLOAT ) error ( <STR_LIT> , name , <STR_LIT> ) ; else error ( <STR_LIT> , name , TARGET_IEEEQUAD ? <STR_LIT> : <STR_LIT> ) ; }

else if ( ( fnmask & RS6000_BTM_HARD_FLOAT ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ;


<s> return ( vcall_offset >= - <NUM_LIT> || ! fixed_regs [ <NUM_LIT> ] ) ;


<s> MachineBasicBlock * <ISA_LIT>16TargetLowering :: emitFEXT_CCRXI16_ins ( unsigned SltiOpc , unsigned SltiXOpc , MachineInstr * MI , MachineBasicBlock * BB ) const { if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned CC = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SltOpc = <ISA_LIT>16WhichOp8uOr16simm ( SltiOpc , SltiXOpc , Imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addImm ( Imm ) ;

BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printPCRelImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ;

if ( Op . isImm ( ) ) O << Op . getImm ( ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> } if ( interrupt ) { if ( crtl -> is_leaf ) { if ( df_regs_ever_live_p ( regno ) ) return <NUM_LIT> ; } else if ( call_used_regs [ regno ] ) return <NUM_LIT> ; if ( regno == PROLOGUE_TMP_REGNUM ) { if ( df_regs_ever_live_p ( MDB_REGNUM ) || df_regs_ever_live_p ( MDC_REGNUM ) ) return <NUM_LIT> ;

for ( int i = FP_FIRST_REGNUM ; i <= FP_LAST_REGNUM ; i ++ ) if ( df_regs_ever_live_p ( i ) ) return <NUM_LIT> ;


<s> } else { while ( ! MDT . dominates ( OneUseInst , UseInst ) ) { if ( UseInst -> getDesc ( ) . getNumDefs ( ) == <NUM_LIT> ) return false ; const MachineOperand & MO = UseInst -> getOperand ( <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) return false ; unsigned DefReg = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( DefReg ) || ! MFI . isVRegStackified ( DefReg ) ) return false ; assert ( MRI . hasOneUse ( DefReg ) ) ; const MachineOperand & NewUse = * MRI . use_begin ( DefReg ) ; const MachineInstr * NewUseInst = NewUse . getParent ( ) ; if ( NewUseInst == OneUseInst ) { if ( & OneUse > & NewUse ) return false ; break ;


<s> MCSymbol * Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Major , Ctx ) ) ; Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Minor , Ctx ) ) ; Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Stepping , Ctx ) ) ; } if ( ISA . Major >= <NUM_LIT> && isHsaAbiVersion3AndAbove ( & getSTI ( ) ) ) { initializeGprCountSymbol ( IS_VGPR ) ; initializeGprCountSymbol ( IS_SGPR ) ; } else KernelScope . initialize ( getContext ( ) ) ; }


<s> Path [ BN ] = true ; bool ReachedExit = false ; for ( auto & SB : MBB . successors ( ) ) ReachedExit |= updateExitPaths ( * SB , RestoreB , DoneT , DoneF , Path ) ; if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MachineInstr & RetI = MBB . back ( ) ; if ( ! isRestoreCall ( RetI . getOpcode ( ) ) ) for ( auto & R : CSI ) RetI . addOperand ( MachineOperand :: CreateReg ( R . getReg ( ) , false , true ) ) ; ReachedExit = true ;


<s> rtx simple ( enum machine_mode mode , rtx operand ) { if ( mode == DFmode && GET_CODE ( operand ) == MEM && GET_CODE ( XEXP ( operand , <NUM_LIT> ) ) == PLUS ) { rtx x = XEXP ( operand , <NUM_LIT> ) ; rtx t1 = XEXP ( x , <NUM_LIT> ) ; rtx t2 = copy_to_mode_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t2 , gen_rtx_PLUS ( Pmode , t2 , t1 ) ) ) ; return gen_rtx_MEM ( mode , t2 ) ; } return operand ;


<s> } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ;

EVT CmpVT = TLI . getValueType ( CmpLHS -> getType ( ) ) ;


<s> } if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Offsets = GEP -> getOperand ( <NUM_LIT> ) ; assert ( cast < FixedVectorType > ( Ty ) -> getNumElements ( ) == cast < FixedVectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) ) ; if ( Offsets -> getType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; if ( ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; else if ( ! ( cast < FixedVectorType > ( Offsets -> getType ( ) ) -> getNumElements ( ) == <NUM_LIT> && Offsets -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) return nullptr ;


<s> while ( InsertPos != MBB . end ( ) && InsertPos -> getOpcode ( ) == <STR_LIT> ) ++ InsertPos ; MachineInstr * Begin = BuildMI ( MBB , InsertPos , MBB . findDebugLoc ( InsertPos ) , TII . get ( <STR_LIT> ) ) . addImm ( int64_t ( <STR_LIT> :: Void ) ) ; DebugLoc EndDL = ( * AfterLoop -> pred_rbegin ( ) ) -> findBranchDebugLoc ( ) ; MachineInstr * End = BuildMI ( * AfterLoop , AfterLoop -> begin ( ) , EndDL , TII . get ( <STR_LIT> ) ) ; LoopTops [ End ] = Begin ; assert ( ( ! ScopeTops [ AfterLoop -> getNumber ( ) ] || ScopeTops [ AfterLoop -> getNumber ( ) ] -> getNumber ( ) < MBB . getNumber ( ) ) && <STR_LIT> ) ; if ( ! ScopeTops [ AfterLoop -> getNumber ( ) ] ) ScopeTops [ AfterLoop -> getNumber ( ) ] = & MBB ;


<s> return SDValue ( DAG -> getMachineNode ( AMDGPU :: <ISA_LIT>_ADDR64_RSRC , DL , <STR_LIT> , Ptr ) , <NUM_LIT> ) ;


<s> <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ;

Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ;


<s> OS << <STR_LIT> << GetArchName ( Arch ) << '\n' ;


<s> static bool msp430_legitimate_constant ( machine_mode mode , rtx x ) {

return ! CONST_INT_P ( x ) || mode != PSImode || ( INTVAL ( x ) < ( <NUM_LIT> << <NUM_LIT> ) && INTVAL ( x ) >= ( HOST_WIDE_INT ) ( HOST_WIDE_INT_M1U << <NUM_LIT> ) ) ;


<s> unsigned ADDI = STI . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDI ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg ; loadImmediate ( MBB , I , & Reg , Amount ) ; BuildMI ( MBB , I , DL , get ( ADD ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ;


<s> <ISA_LIT>SplitDoubleRegs ( ) : MachineFunctionPass ( ID ) , TRI ( nullptr ) , TII ( nullptr ) { initialize<ISA_LIT>SplitDoubleRegsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( Subtarget . useOddSPReg ( ) ? & <STR_LIT> : & <STR_LIT> ) ;

BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ;


<s> const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = MI -> mayStore ( ) ; unsigned Opc = MI -> getOpcode ( ) ; int LoadStoreOp = IsStore ? getOffsetMUBUFStore ( Opc ) : getOffsetMUBUFLoad ( Opc ) ; if ( LoadStoreOp == - <NUM_LIT> ) return false ;

unsigned Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) -> getReg ( ) ;


<s> void emitULEB128Value ( const MCExpr * Value ) override {


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getLitEncoding ( const MCOperand & MO , unsigned OpSize ) const { int64_t Imm ; if ( MO . isExpr ( ) ) { const MCConstantExpr * C = dyn_cast < MCConstantExpr > ( MO . getExpr ( ) ) ; if ( ! C ) return <NUM_LIT> ; Imm = C -> getValue ( ) ; } else { assert ( ! MO . isFPImm ( ) ) ; if ( ! MO . isImm ( ) ) return ~ <NUM_LIT> ; Imm = MO . getImm ( ) ; } if ( OpSize == <NUM_LIT> ) return getLit32Encoding ( static_cast < uint32_t > ( Imm ) ) ; assert ( OpSize == <NUM_LIT> ) ;

return getLit64Encoding ( static_cast < uint64_t > ( Imm ) ) ;


<s> if ( ! F || ! canReuseBoundaryAlignFragment ( * F ) ) { F = new MCBoundaryAlignFragment ( AlignBoundary ) ;


<s> return lowerV2F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I16VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ;


<s> return ( ( Size == <NUM_LIT> ) && ! Subtarget -> isMClass ( ) ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ;


<s> std :: string * SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( Sym ) ;

MCOp = GetSymbolRef ( OutContext . getOrCreateSymbol ( StringRef ( SymNamePtr -> c_str ( ) ) ) ) ;


<s> if ( type == TYPE_LOAD_EXT_U || type == TYPE_LOAD_EXT_UX || type == TYPE_LOAD_UX || type == TYPE_STORE_UX || type == TYPE_MFCR ) return true ; }


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> asm_fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; assemble_name ( file , XSTR ( XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ;


<s> int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> + <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ;


<s> UDItype v = ( USItype ) b ; v <<= ( sizeof ( SItype ) * <NUM_LIT> ) ; a -= ( TFtype ) v ; if ( a < <NUM_LIT> ) v -= ( USItype ) ( - a ) ;


<s> void addInst ( MachineInstr * MI , SetVector < MachineInstr * > & Preds ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; if ( ! Divergent && ! set_difference ( Preds , PredicateThen -> Predicates ) . empty ( ) ) { Divergent = & Insts . back ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Divergent -> MI ) ; }


<s> if ( ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ;

if ( LocVT == <STR_LIT> && ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State , false ) ) return false ;


<s> unsigned imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) DecodeFPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; else DecodeVectorRegisterClass ( Inst , Rd , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; switch ( Inst . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: CreateImm ( ( cmode & <NUM_LIT> ) << <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: CreateImm ( cmode & <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; break ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) , Op -> op_end ( ) ) ;

return makeLibCall ( DAG , LC , Op . getValueType ( ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) , false , SDLoc ( Op ) ) . first ;


<s> return MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_DTPOFF , getContext ( ) ) ;


<s> SDValue NewXor = DAG . getNode ( <STR_LIT> , Op1 . getDebugLoc ( ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , VT ) ) ; return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) + <NUM_LIT> , VT ) ) ;


<s> virtual const TargetData * getTargetData ( ) const {


<s> MI1 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI2 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI2 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI3 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg ) ; if ( ImpIsDead ) MI3 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


regno -- ) if ( ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) || ( regno == MMIX_FRAME_POINTER_REGNUM && frame_pointer_needed ) ) break ;


<s> if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) {

uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; assert ( ! MFI -> hasVarSizedObjects ( ) ) ; if ( MFI -> getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } unsigned IgnoredFrameReg ; Offset = MF . getSubtarget ( ) . getFrameLowering ( ) -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) ;

return getIndirectIndexBegin ( MF ) + Offset ;


<s> if ( ! isMul4 ) { Bytes &= ~ <NUM_LIT> ; ExtraOpc = <STR_LIT> ; } NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Opc = <STR_LIT> ; } else { if ( DestReg != BaseReg ) DstNotEqBase = true ; NumBits = <NUM_LIT> ; if ( DestReg == <STR_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; assert ( isMul4 && <STR_LIT> ) ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; } else { Opc = isSub ? <STR_LIT> : <STR_LIT> ; NumBits = <NUM_LIT> ; NeedPred = NeedCC = true ; } isTwoAddr = true ; } unsigned NumMIs = calcNumMI ( Opc , ExtraOpc , Bytes , NumBits , Scale ) ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( NumMIs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , DestReg , BaseReg , NumBytes , true , TII , MRI , dl ) ; return ; } if ( DstNotEqBase ) { if ( is<ISA_LIT>LowRegister ( DestReg ) && is<ISA_LIT>LowRegister ( BaseReg ) ) { unsigned Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; const TargetInstrDesc & TID = TII . get ( isSub ? <STR_LIT> : <STR_LIT> ) ; const MachineInstrBuilder MIB = AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TID , DestReg ) ) ; AddDefaultPred ( MIB . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) ; }


<s> void addConstPoolAsmImmOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> SelectionDAG & DAG = DCI . DAG ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( ST -> hasMVEIntegerOps ( ) && Src . getOpcode ( ) == <STR_LIT> ) { EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT . getScalarSizeInBits ( ) == DstVT . getScalarSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DstVT , Src . getOperand ( <NUM_LIT> ) ) ; } while ( Src . getOpcode ( ) == <STR_LIT> ) Src = Src . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) && SrcVT . getScalarSizeInBits ( ) <= DstVT . getScalarSizeInBits ( ) && DAG . getDataLayout ( ) . isBigEndian ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DstVT , Src ) ; if ( SDValue R = PerformExtractEltToVMOVRRD ( N , DCI ) ) return R ; return SDValue ( ) ;


<s> if ( getLexer ( ) . is ( AsmToken :: LBrac ) && parseBracketSuffix ( Name , Operands ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { if ( parseBracketSuffix ( Name , Operands ) ) return true ; } else if ( getLexer ( ) . is ( AsmToken :: LParen ) && parseParenSuffix ( Name , Operands ) ) return true ; }


<s> unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( <STR_LIT> , ELF :: R_AARCH64_NONE ) . Case ( <STR_LIT> , ELF :: R_AARCH64_ABS16 ) . Case ( <STR_LIT> , ELF :: R_AARCH64_ABS32 ) . Case ( <STR_LIT> , ELF :: R_AARCH64_ABS64 ) . Default ( - <NUM_LIT> ) ;

if ( Type == - <NUM_LIT> ) return None ;


<s> static bool isVZIP_v_undef_Mask ( ArrayRef < int > M , EVT VT , unsigned & WhichResult ) { unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = i / NumElts ; else WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != Idx ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != Idx ) ) return false ; Idx += <NUM_LIT> ; } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ;

if ( VT . is64BitVector ( ) && EltSz == <NUM_LIT> ) return false ;


<s> BuildMI ( MBB , MI . getIterator ( ) , DL , TII -> get ( <STR_LIT> ) , Reg ) . addOperand ( * Val ) ; MI . eraseFromParent ( ) ; return false ; }

MachineInstr * MovRel = BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( Val -> getReg ( ) , getUndefRegState ( Val -> isUndef ( ) ) ) . addReg ( Dst , RegState :: Implicit ) ;


<s> if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv2sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V2SF ] ;

if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv4sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V4SF ] ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = MI -> mayStore ( ) ; unsigned Opc = MI -> getOpcode ( ) ; int LoadStoreOp = IsStore ? getOffsetMUBUFStore ( Opc ) : getOffsetMUBUFLoad ( Opc ) ; if ( LoadStoreOp == - <NUM_LIT> ) return false ;


<s> function_builder :: ~ function_builder ( ) { obstack_free ( & m_string_obstack , NULL ) ;


<s> SDLoc DL ( Op ) ; SDValue DescAddr = LowerGlobalAddressDarwin ( Op , DAG ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ;


<s> void <ISA_LIT>InstPrinter :: printAdrpLabel ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

const MCOperand & Op = MI -> getOperand ( OpNum ) ;


<s> if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; if ( isInt < <NUM_LIT> > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( - StackSize ) ; else { assert ( <STR_LIT> ) ; } MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ;

SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize ) ;


<s> case SImode : if ( unsigned_p ) { cvt = ufloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_si_uns ; } else { cvt = sfloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_si_sign ; } break ; case DImode : if ( unsigned_p ) { cvt = ufloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_di_uns ; } else { cvt = sfloat_optab ; hw_convert = hw_conversions [ kf_or_tf ] . from_di_sign ; } break ; default : gcc_unreachable ( ) ; } } else if ( FLOAT128_IEEE_P ( src_mode ) ) { if ( src_mode == KFmode ) kf_or_tf = <NUM_LIT> ; else if ( src_mode == TFmode ) kf_or_tf = <NUM_LIT> ; else gcc_unreachable ( ) ; switch ( dest_mode ) { case DFmode : cvt = trunc_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_df ; break ; case SFmode : cvt = trunc_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_sf ; break ; case KFmode : case IFmode : case TFmode : if ( FLOAT128_IBM_P ( dest_mode ) ) cvt = trunc_optab ; else do_move = true ; break ; case SImode : if ( unsigned_p ) { cvt = ufix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_si_uns ; } else { cvt = sfix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_si_sign ; } break ; case DImode : if ( unsigned_p ) { cvt = ufix_optab ; hw_convert = hw_conversions [ kf_or_tf ] . to_di_uns ; }


<s> assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; if ( TREE_PUBLIC ( decl ) && ! DECL_WEAK ( decl ) ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; putc ( '\n' , file ) ; } } else ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; rs6000_output_function_entry ( file , name ) ; fputs ( <STR_LIT> , file ) ; return ; } if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) && ! TARGET_SECURE_PLT && ( ! constant_pool_empty_p ( ) || crtl -> profile ) && uses_TOC ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; putc ( '-' , file ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ; ASM_DECLARE_RESULT ( file , DECL_RESULT ( decl ) ) ; if ( TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ( ) ) { char buf [ <NUM_LIT> ] ; ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , rs6000_pic_labelno ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; putc ( '\n' , file ) ; } if ( DEFAULT_ABI == ABI_AIX ) { const char * desc_name , * orig_name ; orig_name = ( * targetm . strip_name_encoding ) ( name ) ; desc_name = orig_name ; while ( * desc_name == '.' ) desc_name ++ ; if ( TREE_PUBLIC ( decl ) ) fprintf ( file , <STR_LIT> , desc_name ) ; fprintf ( file , <STR_LIT> , MINIMAL_TOC_SECTION_ASM_OP ) ; fprintf ( file , <STR_LIT> , desc_name ) ;

fprintf ( file , <STR_LIT> , orig_name ) ;


<s> return __builtin_neon_vcvthuhf ( __a ) ;


<s> } DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ;

MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( isSub ? - ThisVal : ThisVal ) ;


<s> break ; case 'y' : if ( type -> is<ISA_LIT>_MMXTy ( ) && Subtarget . hasMMX ( ) ) weight = CW_SpecificReg ; break ; case 'Y' : if ( StringRef ( constraint ) . size ( ) != <NUM_LIT> ) break ; switch ( constraint [ <NUM_LIT> ] ) { default : return CW_Invalid ; case 'z' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) ) return CW_SpecificReg ; return CW_Invalid ; case 'k' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) return CW_Register ; return CW_Invalid ; case 'm' : if ( type -> is<ISA_LIT>_MMXTy ( ) && Subtarget . hasMMX ( ) ) return weight ; return CW_Invalid ; case 'i' : case 't' : case '2' : if ( ! Subtarget . hasSSE2 ( ) ) return CW_Invalid ; break ; } break ; case 'v' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) weight = CW_Register ; LLVM_FALLTHROUGH ; case 'x' : if ( ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasSSE1 ( ) ) || ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX ( ) ) ) weight = CW_Register ; break ; case 'k' : if ( ( type -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) && Subtarget . hasAVX512 ( ) ) weight = CW_Register ; break ; case 'I' : if ( auto * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( auto * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ;


<s> RegisterTargetMachine < <ISA_LIT>elTargetMachine > Z ( getThe<ISA_LIT>elTarget ( ) ) ;


<s> ValueBit ( Kind K = Variable ) : Idx ( UINT32_MAX ) , K ( K ) {


<s> return ( ( qword ) ( vec_sub ( vec_splat ( ( vec_short8 ) ( si_from_short ( b ) ) , <NUM_LIT> ) , ( vec_short8 ) ( a ) ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemBytes = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemBytes = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return new <ISA_LIT>MCAsmInfo ( TT ) ;


<s> return true ; } if ( MI . mayLoadOrStore ( ) && ! isStoreImmediate ( ExtOpc ) ) { unsigned RegOpc , Shift ; unsigned AM = HII -> getAddrMode ( MI ) ; if ( AM == <STR_LIT> ) { RegOpc = HII -> changeAddrMode_io_rr ( ExtOpc ) ; Shift = <NUM_LIT> ; } else if ( AM == <STR_LIT> ) { RegOpc = HII -> changeAddrMode_ur_rr ( ExtOpc ) ; Shift = MI . getOperand ( MI . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( RegOpc == - <NUM_LIT> ) { dbgs ( ) << <STR_LIT> << HII -> getName ( ExtOpc ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; } unsigned BaseP , OffP ; HII -> getBaseAndOffsetPosition ( MI , BaseP , OffP ) ; MachineInstrBuilder MIB = BuildMI ( MBB , At , dl , HII -> get ( RegOpc ) ) ; if ( MI . mayLoad ( ) ) MIB . add ( getLoadResultOp ( MI ) ) ; if ( HII -> isPredicated ( MI ) ) MIB . add ( getPredicateOp ( MI ) ) ;


<s> Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isAtLeastRelease ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Function * Strex = <STR_LIT> ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , <STR_LIT> ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Strex , Lo , Hi , Addr ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = <STR_LIT> ( M , Int , Tys ) ; return Builder . CreateCall2 ( Strex , Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( <NUM_LIT> ) ) , Addr ) ;


<s> MI -> getOperand ( Operand + <NUM_LIT> ) . setReg ( <NUM_LIT> ) ; MI -> getOperand ( Operand + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; MI -> getOperand ( Operand + <NUM_LIT> ) . setReg ( <NUM_LIT> ) ;


<s> byte_mode_size = emit_setmem_word_loop ( dst , size , value4word ) ; value4byte = simplify_gen_subreg ( QImode , value4word , SImode , subreg_lowpart_offset ( QImode , SImode ) ) ; emit_setmem_byte_loop ( dst , byte_mode_size , value4byte , false ) ;


<s> void <ISA_LIT>ELFStreamer :: EmitPersonality ( const MCSymbol * Per ) {


<s> static void HandleMemoryRefTruncation ( MCInst * Inst , unsigned IndexOpPosition , MCStreamer & Out ) { const bool UseZeroBasedSandbox = FlagUseZeroBasedSandbox ; unsigned IndexReg = Inst -> getOperand ( IndexOpPosition ) . getReg ( ) ; if ( UseZeroBasedSandbox ) { Inst -> getOperand ( IndexOpPosition ) . setReg ( DemoteRegTo32_ ( IndexReg ) ) ; } else { EmitRegTruncate ( IndexReg , Out ) ; }


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) : MCII ( MCII ) , Ctx ( Ctx ) {


<s> const_iterator begin ( ) const { return Map . begin ( ) ;


<s> static inline bool isImmLH ( uint64_t Val ) { return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;


<s> Res -> Tok . Data = Str . data ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , DL ( computeDataLayout ( TargetTriple ) ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , TSInfo ( DL ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - <NUM_LIT> : - <NUM_LIT> ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { setPICStyle ( PICStyles :: None ) ; } else if ( is64Bit ( ) ) { setPICStyle ( PICStyles :: RIPRel ) ;


<s> tree io_low_attr = lookup_attribute ( <STR_LIT> , attr ) ; tree io_attr = lookup_attribute ( <STR_LIT> , attr ) ; tree addr_attr ; if ( io_low_attr && TREE_VALUE ( io_low_attr ) && TREE_VALUE ( TREE_VALUE ( io_low_attr ) ) ) addr_attr = io_attr ; else if ( io_attr && TREE_VALUE ( io_attr ) && TREE_VALUE ( TREE_VALUE ( io_attr ) ) ) addr_attr = io_attr ; else addr_attr = lookup_attribute ( <STR_LIT> , attr ) ; if ( io_low_attr || ( io_attr && addr_attr && low_io_address_operand ( GEN_INT ( TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( addr_attr ) ) ) ) , QImode ) ) ) SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_IO_LOW ; if ( io_attr || io_low_attr ) SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_IO ;

if ( addr_attr && ! DECL_EXTERNAL ( decl ) ) SYMBOL_REF_FLAGS ( sym ) |= SYMBOL_FLAG_ADDRESS ;


<s> Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord T = getThumbBit ( pReloc ) ; Relocator :: DWord P = pReloc . place ( ) ; if ( T != <NUM_LIT> ) helper_clear_thumb_bit ( S ) ; uint16_t upper_inst = * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) ) ; uint16_t lower_inst = * ( reinterpret_cast < uint16_t * > ( & pReloc . target ( ) ) + <NUM_LIT> ) ; Relocator :: DWord val = ( ( upper_inst ) << <NUM_LIT> ) | ( lower_inst ) ;

Relocator :: DWord A = helper_extract_thumb_movw_movt_addend ( val ) + pReloc . addend ( ) ;


<s> static __inline qword si_mpy ( qword a , qword b ) { return ( ( qword ) ( vec_mulo ( ( vec_short8 ) ( a ) , ( vec_short8 ) ( b ) ) ) ) ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ;


<s> if ( <ISA_LIT>MCInstrInfo :: isExtentSigned ( MCII , MCI ) ) return ( <NUM_LIT> << ( <ISA_LIT>MCInstrInfo :: getExtentBits ( MCII , MCI ) - <NUM_LIT> ) ) - <NUM_LIT> ;

return ( <NUM_LIT> << <ISA_LIT>MCInstrInfo :: getExtentBits ( MCII , MCI ) ) - <NUM_LIT> ;


<s> assert ( ( MIa . mayLoad ( ) || MIa . mayStore ( ) ) && <STR_LIT> ) ; assert ( ( MIb . mayLoad ( ) || MIb . mayStore ( ) ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) ) return false ; if ( MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( AA && MIa . hasOneMemOperand ( ) && MIb . hasOneMemOperand ( ) ) { const MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ;

const MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ;


<s> MaskCV [ i ] = Builder . getInt32 ( NumElts ) ; } else if ( Mask [ i ] == SM_SentinelUndef ) MaskCV [ i ] = UndefValue :: get ( EltTy ) ; else MaskCV [ i ] = Builder . getInt32 ( Mask [ i ] ) ; }

assert ( ( ! V1IsZero || ! V1 ) && <STR_LIT> ) ;


<s> const char * directive = ASM_LONG ; if ( TARGET_LP64 ) directive = ASM_QUAD ; gcc_assert ( ! TARGET_64BIT ) ; fprintf ( file , <STR_LIT> , directive , LPREFIX , value ) ;


<s> const <ISA_LIT>TargetLowering & TLI = * TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) . getTargetLowering ( ) ; SmallVector < EVT , <NUM_LIT> > VTs ; ComputeValueVTs ( TLI , DL , Ty , VTs ) ;


<s> if ( M == i ) continue ; if ( M == i + Size ) { BlendMask |= <NUM_LIT> << i ; continue ; } if ( Zeroable [ i ] ) { if ( V1IsZeroOrUndef ) { ForceV1Zero = true ; Mask [ i ] = i ; continue ; } if ( V2IsZeroOrUndef ) { ForceV2Zero = true ; BlendMask |= <NUM_LIT> << i ; Mask [ i ] = i + Size ; continue ; } } return false ; }


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { flag_aligned_memcpy = false ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ConstantSize ) { uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ( SizeVal > <NUM_LIT> ) && ( ( SizeVal % <NUM_LIT> ) == <NUM_LIT> ) ) flag_aligned_memcpy = true ;


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ;

<ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) { HOST_WIDE_INT n = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( ( n & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ( n & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ( n & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; } return <NUM_LIT> ; } else { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && register_operand ( operands [ <NUM_LIT> ] , VOIDmode ) ) { HOST_WIDE_INT intval = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( TARGET_H8300SX && ( intval >= <NUM_LIT> && intval <= <NUM_LIT> ) ) return <NUM_LIT> ; if ( TARGET_H8300SX && ( intval >= - <NUM_LIT> && intval <= - <NUM_LIT> ) ) return <NUM_LIT> ; switch ( ( unsigned int ) intval & <NUM_LIT> ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; }

if ( ( intval & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> for ( SDNode * U : DAG . getEntryNode ( ) . getNode ( ) -> uses ( ) ) { if ( LoadSDNode * L = dyn_cast < LoadSDNode > ( U ) ) { if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( L -> getBasePtr ( ) ) ) { if ( FI -> getIndex ( ) < <NUM_LIT> ) { int64_t InFirstByte = MFI . getObjectOffset ( FI -> getIndex ( ) ) ; int64_t InLastByte = InFirstByte ;

InLastByte += MFI . getObjectSize ( FI -> getIndex ( ) ) - <NUM_LIT> ;


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetFrameLowering * TFI = Subtarget . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> CurDAG -> computeKnownBits ( Op , KnownZero , KnownOne ) ; uint64_t NonZeroBits = ( ~ KnownZero ) . getZExtValue ( ) ; uint64_t AndImm ; if ( isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , AndImm ) ) { assert ( ( ~ APInt ( BitWidth , AndImm ) & ~ KnownZero ) == <NUM_LIT> ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } uint64_t ShlImm ; if ( ! isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , ShlImm ) ) return false ;


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit ) ; return createELFObjectWriter ( MOTW , OS , true ) ;


<s> if ( isPICStyleStubPIC ( ) ) return <STR_LIT> ; return <STR_LIT> ;


<s> for ( unsigned i = <NUM_LIT> , e = Values . size ( ) ; i != e ; ++ i ) { SDValue V = Values [ i ] ; if ( V . isUndef ( ) ) { Consts [ i ] = ConstantInt :: get ( IntTy , <NUM_LIT> ) ; continue ; } if ( auto * CN = dyn_cast < ConstantSDNode > ( V . getNode ( ) ) ) { const ConstantInt * CI = CN -> getConstantIntValue ( ) ; Consts [ i ] = ConstantInt :: get ( IntTy , CI -> getValue ( ) . getSExtValue ( ) ) ;

} else if ( auto * CN = dyn_cast < ConstantFPSDNode > ( V . getNode ( ) ) ) {


<s> if ( ! computeAddress ( Store -> getPointerOperand ( ) , Addr ) ) return false ; unsigned Opc ; bool VTIsi1 = false ; bool A64 = Subtarget -> hasAddr64 ( ) ; switch ( getSimpleType ( Store -> getValueOperand ( ) -> getType ( ) ) ) { case <STR_LIT> : VTIsi1 = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = A64 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = A64 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = A64 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> :


<s> void <ISA_LIT>InstructionSelector :: putConstant ( InsertInfo I , unsigned DestReg , unsigned Constant ) const { ( void ) BuildMI ( I . MBB , I . InsertBefore , I . DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( DestReg ) . addImm ( Constant ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> gcc_assert ( mask > <NUM_LIT> && mask < <NUM_LIT> ) ; temp = gen_rtx_fmt_ee ( comparison , VOIDmode , gen_rtx_REG ( CCRAWmode , CC_REGNUM ) , GEN_INT ( mask ) ) ; temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; temp = gen_rtx_SET ( pc_rtx , temp ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isVerbose ( ) ) { OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> AddBlankLine ( ) ; } break ; } case <STR_LIT> : case <STR_LIT> : if ( isVerbose ( ) ) { OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> AddBlankLine ( ) ; } break ; default : {

<ISA_LIT>MCInstLower MCInstLowering ( OutContext , * this ) ;


<s> if ( delta < <NUM_LIT> ) emit_insn ( gen_rtx_SET ( Pmode , this_rtx , gen_rtx_MINUS ( Pmode , this_rtx , shift ) ) ) ; else emit_insn ( gen_rtx_SET ( Pmode , this_rtx , gen_rtx_PLUS ( Pmode , this_rtx , shift ) ) ) ; } if ( mdelta % <NUM_LIT> != <NUM_LIT> ) {

scratch_rtx = GEN_INT ( ( delta < <NUM_LIT> ? - <NUM_LIT> : <NUM_LIT> ) * ( mdelta % <NUM_LIT> ) ) ;


<s> SaveBlocks . push_back ( & MF . front ( ) ) ; for ( MachineBasicBlock & MBB : MF ) { if ( MBB . isEHFuncletEntry ( ) ) SaveBlocks . push_back ( & MBB ) ;

if ( MBB . isReturnBlock ( ) ) RestoreBlocks . push_back ( & MBB ) ;


<s> getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> uint64_t MOVZEquivalent = RegWidth == <NUM_LIT> ? ~ Value & <NUM_LIT> : ~ Value ; return isMOVZImm ( RegWidth , MOVZEquivalent , UImm16 , Shift ) ;


<s> MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ;

MIB . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> <ISA_LIT>BaseTargetMachine :: ~ <ISA_LIT>BaseTargetMachine ( ) {


<s> return new <ISA_LIT>CFGOptimizer ( ) ;


<s> while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( ! isAnalyzableBranchOpc ( I -> getOpcode ( ) ) || ( NumTerminators == <NUM_LIT> && ! isAnalyzableBranchOpc ( std :: prev ( I ) -> getOpcode ( ) ) ) ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ;


<s> printOperand ( MI , OpNo + <NUM_LIT> , STI , O ) ;


<s> unsigned LoadOpcode , StoreOpcode ; TII . getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; BuildMI ( MBB , SaveMBBI , DL , TII . get ( StoreOpcode ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( Base ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ;

BuildMI ( MBB , UseMBBI , DL , TII . get ( LoadOpcode ) , Reg ) . addReg ( Base ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ;


<s> case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs == <NUM_LIT> || NumVecs == <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs != <NUM_LIT> && NumVecs != <NUM_LIT> && Opc != <STR_LIT> ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , Ops . size ( ) ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA , <NUM_LIT> ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) {


<s> bool <ISA_LIT>PrologEpilogPass :: runOnMachineFunction ( MachineFunction & MF ) { const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ; TRI . eliminateFrameIndex ( MI , <NUM_LIT> , i , nullptr ) ; Modified = true ; }


<s> rtx dest , vdest , op0 , op1 , mask , op2 , op3 ; mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; if ( mode == HFmode ) vmode = V8HFmode ; else if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else if ( mode == TFmode ) vmode = mode ; else gcc_unreachable ( ) ; if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } dest = operands [ <NUM_LIT> ] ; vdest = lowpart_subreg ( vmode , dest , mode ) ;

if ( vdest == NULL_RTX ) vdest = gen_reg_rtx ( vmode ) ;


<s> if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . OffsetRegNum ) ) return false ; if ( shift == <NUM_LIT> && Memory . ShiftType != <STR_LIT> ) return false ; if ( shift > <NUM_LIT> && ( Memory . ShiftType != <STR_LIT> || Memory . ShiftImm != shift ) ) return false ;


<s> unsigned int prev_regno = CONDITION_CODE_REGNUM ; while ( num_operands -- ) { if ( GET_CODE ( operands [ num_operands ] ) != REG ) return <NUM_LIT> ; if ( REGNO ( operands [ num_operands ] ) > prev_regno ) return <NUM_LIT> ;

prev_regno = REGNO ( operands [ num_operands ] ) ;


<s> rtx test ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; test = gen_rtx_GE ( VOIDmode , tmp , const_double_from_real_value ( REAL_VALUE_ATOF ( <STR_LIT> , XFmode ) , XFmode ) ) ; emit_jump_insn ( gen_cbranchxf4 ( test , XEXP ( test , <NUM_LIT> ) , XEXP ( test , <NUM_LIT> ) , label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( <NUM_LIT> ) ) ; emit_insn ( gen_fyl2xp1xf3_i387 ( op0 , op1 , tmp2 ) ) ; emit_jump ( label2 ) ; emit_label ( label1 ) ; emit_move_insn ( tmp , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( tmp , op1 , tmp ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : if ( coproc == <NUM_LIT> || coproc == <NUM_LIT> ) return MCDisassembler :: Fail ; break ; default : break ; } uint64_t featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( ( featureBits & <STR_LIT> ) && ( coproc != <NUM_LIT> ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( coproc ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( CRd ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : imm = <STR_LIT> ( U ? <STR_LIT> : <STR_LIT> , imm ) ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : imm |= U << <NUM_LIT> ; default : Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ;


<s> static bool isPromotableZeroStoreInst ( MachineInstr * MI ) { return ( isPromotableZeroStoreOpcode ( MI ) ) && getLdStRegOp ( MI ) . getReg ( ) == <STR_LIT> ;


<s> case <STR_LIT> : { Info . opc = <STR_LIT> ; uint64_t NumElts = DL . getTypeSizeInBits ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlign ( PtrTy -> getElementType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = DL . getABITypeAlign ( PtrTy -> getElementType ( ) ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> :


<s> for ( int i = Num ; i < Bytes ; ++ i ) { buffer [ curpos ] = <NUM_LIT> ; curpos ++ ; }


<s> CCAssignFn * <ISA_LIT>FastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: WebKit_JS ) return CC_<ISA_LIT>_WebKit_JS ; if ( CC == CallingConv :: GHC ) return CC_<ISA_LIT>_GHC ;

return Subtarget -> isTargetDarwin ( ) ? CC_<ISA_LIT>_DarwinPCS : CC_<ISA_LIT>_AAPCS ;


<s> LongBrMBB -> addSuccessor ( BalTgtMBB ) ; BalTgtMBB -> addSuccessor ( TgtMBB ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned BalOp = <STR_LIT> ; if ( ! ABI . IsN64 ( ) ) { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addMBB ( TgtMBB ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) ; } else { BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; TgtMBB -> setAlignment ( MIPS_NACL_BUNDLE_ALIGN ) ; } } assert ( LongBrMBB -> size ( ) + BalTgtMBB -> size ( ) == LongBranchSeqSize ) ; } else { Pos = LongBrMBB -> begin ( ) ; LongBrMBB -> addSuccessor ( TgtMBB ) ;

BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TgtMBB ) ;


<s> static rtx frv_legitimize_argument ( enum insn_code icode , int opnum , rtx arg ) { machine_mode mode = insn_data [ icode ] . operand [ opnum ] . mode ;

if ( ( * insn_data [ icode ] . operand [ opnum ] . predicate ) ( arg , mode ) ) return arg ;


<s> unsigned Opc = Inst . getOpcode ( ) ; unsigned I = <NUM_LIT> ; const MCInstrDesc & Desc = MII . get ( Inst . getOpcode ( ) ) ; for ( unsigned J = <NUM_LIT> ; J < Desc . getNumDefs ( ) ; ++ J ) { ( ( <ISA_LIT>Operand & ) * Operands [ I ++ ] ) . addRegOperands ( Inst , <NUM_LIT> ) ; } for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( isRegOrImmWithInputMods ( Desc , Inst . getNumOperands ( ) ) ) { Op . addRegOrImmWithFPInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImmModifier ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { llvm_unreachable ( <STR_LIT> ) ; } } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> ) ; int OpSelIdx = <STR_LIT> ( Opc , <STR_LIT> :: op_sel ) ; if ( OpSelIdx != - <NUM_LIT> ) addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOpSel ) ;

addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyWaitEXP ) ;


<s> tree list = M32C_ATTRIBUTES ( node ) ; while ( list ) { if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( list ) ) ) return <NUM_LIT> ; list = TREE_CHAIN ( list ) ;


<s> if ( ! isSingleSpacedVectorIndexed ( ) ) return false ;

return VectorList . Count == <NUM_LIT> && VectorList . LaneIndex <= <NUM_LIT> ;


<s> FunctionPass * llvm :: create<ISA_LIT>MemorySize ( ) { return new <ISA_LIT>MemorySize ( ) ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) {


<s> case DFmode : return <NUM_LIT> ; case XFmode : return <NUM_LIT> ; case TImode : return SPEC_MODE_INVALID ; default : return SPEC_MODE_INVALID ; }


<s> if ( auto FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ;


<s> return ; case SYMBOL_REF : assemble_name ( stream , XSTR ( x , <NUM_LIT> ) ) ; return ; case LABEL_REF : case CONST : output_addr_const ( stream , x ) ; return ; case PLUS : frv_print_operand_memory_reference ( stream , x , <NUM_LIT> ) ;


<s> StoreOperands . push_back ( Chain ) ; StoreOperands . push_back ( DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) ) ; } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size ( ) - <NUM_LIT> ; switch ( NumElts ) { case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } EVT TheStoreType = ExtendIntegerRetVal ? <STR_LIT> : VTs [ i ] ; Chain = DAG . getMemIntrinsicNode ( Op , dl , DAG . getVTList ( <STR_LIT> ) , StoreOperands , TheStoreType , MachinePointerInfo ( ) , Align ( <NUM_LIT> ) , MachineMemOperand :: MOStore ) ; StoreOperands . clear ( ) ; }


<s> return __builtin_aarch64_sshlv2di ( __a , __b ) ;


<s> break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( Opc ) { case <STR_LIT> : ED . Rd = MI . getOperand ( <NUM_LIT> ) ; ED . IsDef = true ; break ; case <STR_LIT> : case <STR_LIT> : ED . Rd = { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> } ; ED . IsDef = true ; break ; case <STR_LIT> : ED . Rd = { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> } ; ED . IsDef = true ; break ; case <STR_LIT> : ED . Rd = MI . getOperand ( <NUM_LIT> ) ; ED . Expr . Rs = MI . getOperand ( OpNum - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ED . Expr . Rs = MI . getOperand ( OpNum - <NUM_LIT> ) ;


<s> std_expand_builtin_va_start ( valist , nextarg ) ;


<s> default : O << <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( DL , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { unsigned align = PAL . getParamAlignment ( paramIndex ) ; if ( align == <NUM_LIT> ) align = DL . getABITypeAlignment ( ETy ) ; if ( ! isKernelFunc && align < <NUM_LIT> ) align = <NUM_LIT> ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ;


<s> BB -> addSuccessor ( copy0MBB ) ; } BB -> addSuccessor ( sinkMBB ) ; unsigned Opc = <STR_LIT> ( CC ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; if ( CascadedCMOV ) { unsigned Opc2 = <STR_LIT> ( ( <STR_LIT> ) CascadedCMOV -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( jcc1MBB , DL , TII -> get ( Opc2 ) ) . addMBB ( sinkMBB ) ; } copy0MBB -> addSuccessor ( sinkMBB ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = sinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; if ( RegRewriteTable . find ( Op1Reg ) != RegRewriteTable . end ( ) ) Op1Reg = RegRewriteTable [ Op1Reg ] . first ; if ( RegRewriteTable . find ( Op2Reg ) != RegRewriteTable . end ( ) ) Op2Reg = RegRewriteTable [ Op2Reg ] . second ; MIB = BuildMI ( * sinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( Op1Reg ) . addMBB ( copy0MBB ) . addReg ( Op2Reg ) . addMBB ( thisMBB ) ; RegRewriteTable [ DestReg ] = std :: make_pair ( Op1Reg , Op2Reg ) ; } if ( CascadedCMOV ) { MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( jcc1MBB ) ; BuildMI ( * sinkMBB , std :: next ( MachineBasicBlock :: iterator ( MIB . getInstr ( ) ) ) , DL , TII -> get ( TargetOpcode :: COPY ) , CascadedCMOV -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; CascadedCMOV -> eraseFromParent ( ) ; } for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ) ( MIIt ++ ) -> eraseFromParent ( ) ;


<s>
const
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_PROGBITS
,
<NUM_LIT>
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
ConfigSection
)
;
const
AMDGPUSubtarget
&
STM
=
TM
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
if
(
STM
.
getGeneration
(
)
>
AMDGPUSubtarget
::
NORTHERN_ISLANDS
)
{
EmitProgramInfo<ISA_LIT>
(
MF
)
;
}
else
{
EmitProgramInfoR600
(
MF
)
;
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
<NUM_LIT>
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
EmitFunctionBody
(
)
;
if
(
STM
.
dumpCode
(
)
)
{
MF
.
dump
(
)
;
if
(
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_NOTE
,
<NUM_LIT>
,
SectionKind
::
getReadOnly
(
)
)
)
;
for
(
size_t
i
=
<NUM_LIT>
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;

Comment += <STR_LIT> + HexLines [ i ] + <STR_LIT> ;


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> return __arm_vcmulq_rot90_f32 ( __a , __b ) ;


<s> BaseReg = Addr ; Offset = CurDAG -> getIntPtrConstant ( <NUM_LIT> , true ) ; return true ; } return false ;


<s> BaseRegFlags = RegState :: Kill ; TII -> getAddNoCarry ( * MBB , InsertBefore , DL , BaseReg ) . addReg ( ImmReg ) . addReg ( AddrReg -> getReg ( ) , <NUM_LIT> , BaseSubReg ) . addImm ( <NUM_LIT> ) ; BaseSubReg = <NUM_LIT> ; } MachineInstrBuilder Write2 = BuildMI ( * MBB , InsertBefore , DL , Write2Desc ) . addReg ( BaseReg , BaseRegFlags , BaseSubReg ) . add ( * Data0 ) . add ( * Data1 ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * Paired . I } ) ; CI . I -> eraseFromParent ( ) ; Paired . I -> eraseFromParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Write2 << '\n' ) ;


<s> } return DAG . getConstant ( Imm , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; } if ( Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && SrcVT . isFloatingPoint ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == EVT ( SrcVT ) . changeVectorElementTypeToInteger ( ) ) Src = Src . getOperand ( <NUM_LIT> ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getSignMask ( SrcVT . getScalarSizeInBits ( ) ) ) ; if ( TLI . SimplifyDemandedBits ( Src , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; APInt SplatVal ; if ( Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) == Src . getValueType ( ) && cast < CondCodeSDNode > ( Src . getOperand ( <NUM_LIT> ) ) -> get ( ) == <STR_LIT> && <STR_LIT> ( Src . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Src . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue And = Src . getOperand ( <NUM_LIT> ) ; if ( And . hasOneUse ( ) && <STR_LIT> ( And . getOperand ( <NUM_LIT> ) . getNode ( ) , SplatVal ) && SplatVal . isPowerOf2 ( ) ) { MVT VT = Src . getSimpleValueType ( ) ; unsigned BitWidth = VT . getScalarSizeInBits ( ) ; unsigned ShAmt = BitWidth - SplatVal . logBase2 ( ) - <NUM_LIT> ; SDLoc DL ( And ) ; SDValue X = And . getOperand ( <NUM_LIT> ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) { VT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; X = DAG . getBitcast ( VT , X ) ;