<s> case <STR_LIT> : { BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } case <STR_LIT> : return selectStoreIntrinsic ( I , false ) ; case <STR_LIT> : return selectStoreIntrinsic ( I , true ) ; case <STR_LIT> : case <STR_LIT> : return selectDSOrderedIntrinsic ( I , IntrinsicID ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> size_t <ISA_LIT>CA53ErratumStub :: alignment ( ) const { return <NUM_LIT> ;


<s> std :: vector < std :: string > mov_y1 ( Abl a ) {

return D ( <STR_LIT> , R ( a ) , <STR_LIT> ) ;


<s> static uint16_t type ( uint16_t T ) {


<s> <ISA_LIT>JITInfo * getJITInfo ( ) override {


<s> if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = alignTo ( maxCallFrameSize , StackAlign ) ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ;

if ( ! ( hasReservedCallFrame ( MF ) && MFI -> adjustsStack ( ) ) ) FrameSize += maxCallFrameSize ;


<s> static <ISA_LIT>MCExpr :: VariantKind Variants [ ] = { <ISA_LIT>MCExpr :: VK_ABS_G3 } ; return isMovWSymbol ( Variants ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;


<s> void <ISA_LIT>FunctionInfo :: anchor ( ) {


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; case MachineOperand :: MO_Immediate : if ( ! Modifier || strcmp ( Modifier , <STR_LIT> ) ) O << '#' ; O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isMemOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; uint64_t Offset = MO . getOffset ( ) ; if ( ! Modifier || strcmp ( Modifier , <STR_LIT> ) ) O << ( isMemOp ? '&' : '#' ) ; if ( Offset ) O << '(' << Offset << '+' ; O << * getSymbol ( MO . getGlobal ( ) ) ; if ( Offset ) O << ')' ; return ;


<s> SDValue NewLoad = DAG . getMaskedLoad ( WideDataVT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , Src0 , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) ) ; SDValue Exract = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue RetOps [ ] = { Exract , NewLoad . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , dl ) ;


<s> return isMemOp ( ) && MemOp . Op == <STR_LIT> :: Addr ;


<s> static rtx gen_add3_const ( rtx rt , rtx ra , long c ) { if ( TARGET_64BIT ) return gen_adddi3 ( rt , ra , GEN_INT ( c ) ) ; else return gen_addsi3 ( rt , ra , GEN_INT ( c ) ) ;


<s> static void avr_expand_nops ( rtx operands0 ) { unsigned HOST_WIDE_INT n_nops = UINTVAL ( operands0 ) & GET_MODE_MASK ( HImode ) ; while ( n_nops -- ) {


<s> int NegIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) } ; int AbsIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) } ; std :: vector < unsigned > Consts ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { int SrcIdx = OperandIdx [ j ] ; if ( SrcIdx < <NUM_LIT> ) break ; if ( RegisterSDNode * Reg = dyn_cast < RegisterSDNode > ( Ops [ SrcIdx - <NUM_LIT> ] ) ) {

if ( Reg -> getReg ( ) == AMDGPU :: ALU_CONST ) {


<s> <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; <STR_LIT> IID = ICA . getID ( ) ; Type * RetTy = ICA . getReturnType ( ) ; const SmallVectorImpl < const Value * > & Args = ICA . getArgs ( ) ; unsigned ISD = <STR_LIT> ; switch ( IID ) { default : break ; case <STR_LIT> : ISD = <STR_LIT> ; if ( Args [ <NUM_LIT> ] == Args [ <NUM_LIT> ] ) ISD = <STR_LIT> ; break ; case <STR_LIT> : ISD = <STR_LIT> ; if ( Args [ <NUM_LIT> ] == Args [ <NUM_LIT> ] ) ISD = <STR_LIT> ; break ; } if ( ISD != <STR_LIT> ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; MVT MTy = LT . second ; if ( ST -> hasAVX512 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasXOP ( ) ) if ( const auto * Entry = CostTableLookup ( XOPCostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> is64Bit ( ) ) if ( const auto * Entry = CostTableLookup ( X64CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( const auto * Entry = CostTableLookup ( <ISA_LIT>CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ;


<s> ReversePostOrderTraversal < MachineFunction * > RPOT ( & MF ) ; for ( MachineBasicBlock * MBB : RPOT ) { bool InWWM = false ; for ( MachineInstr & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) RegsAssigned |= processDef ( MI . getOperand ( <NUM_LIT> ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; InWWM = true ; continue ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; InWWM = false ; } if ( ! InWWM ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; for ( MachineOperand & DefOpnd : MI . defs ( ) ) { RegsAssigned |= processDef ( DefOpnd ) ; } } } if ( ! RegsAssigned ) return false ; rewriteRegs ( MF ) ; return true ;


<s> static bool already_contains ( rtx loc , rtx value ) { unsigned char index ; unsigned char val ; if ( ( index = get_content_index ( loc ) ) == NOT_KNOWN ) return false ; if ( ( val = get_content_index ( value ) ) == NOT_KNOWN ) return false ;

if ( content_memory [ index ] != val ) return false ;


<s> default : State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN : case IES_REGISTER : State = IES_NE ; IC . pushOperator ( IC_NE ) ; break ; }


<s> enum machine_mode mode ; if ( regs_inited == <NUM_LIT> ) create_regs_rtx ( ) ; mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; if ( A_REG_P ( operands [ <NUM_LIT> ] ) && memory_reload_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx big_offset = XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ; rtx base = XEXP ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( base ) != REG ) { rtx tmp = base ; base = big_offset ; big_offset = tmp ; } if ( ! VALID_CONSTANT_OFFSET_P ( big_offset , mode ) ) { int vh , vl ; rtx reg = operands [ <NUM_LIT> ] ; rtx offset ; int val = INTVAL ( big_offset ) ; if ( ! rtx_equal_p ( base , operands [ <NUM_LIT> ] ) ) { emit_move_insn ( reg , base ) ; } if ( val > <NUM_LIT> ) { vh = val >> <NUM_LIT> ; vl = val & <NUM_LIT> ; } else { vh = ( val >> <NUM_LIT> ) & <NUM_LIT> ; vl = val & <NUM_LIT> ; } offset = GEN_INT ( vl ) ; if ( ! VALID_CONSTANT_OFFSET_P ( offset , mode ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , reg , gen_rtx_PLUS ( HImode , reg , big_offset ) ) ) ; offset = const0_rtx ; } else { emit_insn ( gen_rtx_SET ( VOIDmode , reg , gen_rtx_PLUS ( HImode , reg , GEN_INT ( vh << <NUM_LIT> ) ) ) ) ;


<s> } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && ( ( isInt < <NUM_LIT> > ( Offset ) && ( ( Offset % offsetMinAlign ( MI ) ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ;

if ( isInt < <NUM_LIT> > ( Offset ) ) BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( Offset ) ;


<s> if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FIST ;


<s> unsigned LoLHS = MRI -> createGenericVirtualRegister ( HalfTy ) ; unsigned HiLHS = MRI -> createGenericVirtualRegister ( HalfTy ) ; const RegisterBank * Bank = getRegBank ( Reg , * MRI , * TRI ) ; MRI -> setRegBank ( LoLHS , * Bank ) ;


<s> return __builtin_mve_vrev16q_m_uv16qi ( __arm_vuninitializedq_u8 ( ) , __a , __p ) ;


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , <NUM_LIT> , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createHardwareLoopsPass ( ) ) ;

addPass ( createMVETailPredicationPass ( ) ) ;


<s> void Thumb1FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; assert ( ( unsigned ) NumBytes >= ArgRegsSaveSize && <STR_LIT> ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes - ArgRegsSaveSize ) ;


<s> StringRef Name ; if ( getParser ( ) . parseIdentifier ( Name ) ) return Error ( L , <STR_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , getContext ( ) ) ; Expr = <ISA_LIT>MCExpr :: Create ( Expr , <ISA_LIT>MCExpr :: VK_TLSDESC , getContext ( ) ) ; MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; getParser ( ) . getStreamer ( ) . EmitInstruction ( Inst , STI ) ;


<s> MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; }


<s> CopyBits = <NUM_LIT> ; CopyScale = <NUM_LIT> ; } else if ( DestReg == BaseReg ) { } else if ( is<ISA_LIT>LowRegister ( BaseReg ) ) { CopyOpc = isSub ? <STR_LIT> : <STR_LIT> ; CopyBits = <NUM_LIT> ; CopyNeedsCC = true ; } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = isSub ? <STR_LIT> : <STR_LIT> ; ExtraBits = <NUM_LIT> ; ExtraNeedsCC = true ; } else { if ( DestReg == BaseReg ) { } else { CopyOpc = <STR_LIT> ; CopyBits = <NUM_LIT> ; } ExtraOpc = <NUM_LIT> ; } assert ( ( ( Bytes & <NUM_LIT> ) == <NUM_LIT> || ExtraScale == <NUM_LIT> ) && <STR_LIT> ) ; unsigned CopyRange = ( ( <NUM_LIT> << CopyBits ) - <NUM_LIT> ) * CopyScale ; if ( CopyOpc && Bytes < CopyScale ) { CopyOpc = <STR_LIT> ; CopyScale = <NUM_LIT> ; CopyNeedsCC = false ; CopyRange = <NUM_LIT> ; } unsigned ExtraRange = ( ( <NUM_LIT> << ExtraBits ) - <NUM_LIT> ) * ExtraScale ; unsigned RequiredCopyInstrs = CopyOpc ? <NUM_LIT> : <NUM_LIT> ; unsigned RangeAfterCopy = ( CopyRange > Bytes ) ? <NUM_LIT> : ( Bytes - CopyRange ) ; assert ( RangeAfterCopy % ExtraScale == <NUM_LIT> && <STR_LIT> ) ; unsigned RequiredExtraInstrs ; if ( ExtraRange ) RequiredExtraInstrs = alignTo ( RangeAfterCopy , ExtraRange ) / ExtraRange ; else if ( RangeAfterCopy > <NUM_LIT> ) RequiredExtraInstrs = <NUM_LIT> ; else RequiredExtraInstrs = <NUM_LIT> ; unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( RequiredInstrs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , dl , DestReg , BaseReg , NumBytes , true , TII , MRI , MIFlags ) ; return ; } if ( CopyOpc ) { unsigned CopyImm = std :: min ( Bytes , CopyRange ) / CopyScale ; Bytes -= CopyImm * CopyScale ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( CopyOpc ) , DestReg ) ; if ( CopyNeedsCC ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; MIB . addReg ( BaseReg , RegState :: Kill ) ; if ( CopyOpc != <STR_LIT> ) { MIB . addImm ( CopyImm ) ; } MIB . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ;


<s> emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF ) ) . addSym ( Sym , <STR_LIT> ) ;


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ;


<s> } ) ; assert ( ReservedVGPRInfoItr != FuncInfo -> getSGPRSpillVGPRs ( ) . end ( ) ) ; auto Index = std :: distance ( FuncInfo -> getSGPRSpillVGPRs ( ) . begin ( ) , ReservedVGPRInfoItr ) ; FuncInfo -> setSGPRSpillVGPRs ( LowestAvailableVGPR , FI , Index ) ; for ( MachineBasicBlock & MBB : MF ) { assert ( LowestAvailableVGPR . isValid ( ) && <STR_LIT> ) ; MBB . addLiveIn ( LowestAvailableVGPR ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; auto * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( const <STR_LIT> & In : Ins ) { if ( In . Flags . isInAlloca ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( In . Flags . isNest ( ) ) fail ( DL , DAG , <STR_LIT> ) ;

if ( In . Flags . isInConsecutiveRegs ( ) ) fail ( DL , DAG , <STR_LIT> ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> if ( isDarwinABI || is<ISA_LIT>64 ) return <NUM_LIT> * ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ;


<s> uint64_t Offset = MFI -> allocateKernArg ( ValVT . getStoreSize ( ) , ArgFlags . getOrigAlign ( ) ) ; State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> if ( CondReg == <NUM_LIT> ) return false ; unsigned Opc = <STR_LIT> ; if ( Not ) Opc = <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addMBB ( TBB ) . addReg ( CondReg ) ; finishCondBranch ( Br -> getParent ( ) , TBB , FBB ) ; return true ;


<s> <ISA_LIT>MCNaClExpander ( const MCContext & Ctx , std :: unique_ptr < MCRegisterInfo > && RI , std :: unique_ptr < MCInstrInfo > && II , bool Is64Bit ) : MCNaClExpander ( Ctx , std :: move ( RI ) , std :: move ( II ) ) , Is64Bit ( Is64Bit ) {


<s> SDValue <ISA_LIT>TargetLowering :: lowerSTACKSAVE ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setManipulatesSP ( true ) ;

return DAG . getCopyFromReg ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , <STR_LIT> , Op . getValueType ( ) ) ;


<s> static DecodeStatus DecodeStoreF32 ( MCInst & Inst , uint64_t insn , uint64_t Address , const void * Decoder ) { return DecodeMem ( Inst , insn , Address , Decoder , false , DecodeF32RegisterClass ) ;


<s> return calculateCost ( C , Domain ) < <NUM_LIT> ;


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( create<ISA_LIT>PromoteConstantPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>AddressTypePromotionPass ( ) ) ; return false ;


<s> a = ( __vector signed int ) vec_splats ( __m1 ) ; b = ( __vector signed int ) vec_splats ( __m2 ) ; c = ( __vector signed int ) vec_cmpeq ( a , b ) ; return ( __m64 ) ( ( __vector long long ) c ) [ <NUM_LIT> ] ; __m64_union m1 , m2 , res ; m1 . as_m64 = __m1 ; m2 . as_m64 = __m2 ; res . as_int [ <NUM_LIT> ] = ( m1 . as_int [ <NUM_LIT> ] == m2 . as_int [ <NUM_LIT> ] ) ? - <NUM_LIT> : <NUM_LIT> ; res . as_int [ <NUM_LIT> ] = ( m1 . as_int [ <NUM_LIT> ] == m2 . as_int [ <NUM_LIT> ] ) ? - <NUM_LIT> : <NUM_LIT> ; return ( __m64 ) res . as_m64 ;


<s> if ( ! TFI . hasFP ( MF ) ) report_fatal_error ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ; else { const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; Register FrameReg = RegInfo -> getPtrSizedFrameRegister ( MF ) ; assert ( ( FrameReg == <STR_LIT> || FrameReg == <STR_LIT> ) && <STR_LIT> ) ; } } if ( Reg ) return Reg ;


<s> unsigned add = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! add ) imm *= - <NUM_LIT> ; if ( imm == <NUM_LIT> && ! add ) imm = INT32_MIN ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; if ( Rn == <NUM_LIT> ) tryAddingPcLoadReferenceComment ( Address , Address + imm + <NUM_LIT> , Decoder ) ; return S ;


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> unsigned NumOperands = MI . getNumOperands ( ) ; auto GetBlendDomains = [ & ] ( unsigned ImmWidth , bool Is256 ) { uint16_t validDomains = <NUM_LIT> ; if ( MI . getOperand ( NumOperands - <NUM_LIT> ) . isImm ( ) ) { unsigned Imm = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( ! Is256 || Subtarget . hasAVX2 ( ) ) validDomains |= <NUM_LIT> ; } return validDomains ; } ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> :


<s> Register VDstIn = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto MIB = BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , VDst ) ; Optional < ValueAndVReg > ConstSelect = getConstantVRegValWithLookThrough ( LaneSelect , * MRI , true , true ) ; if ( ConstSelect ) { MIB . addReg ( Val ) ; MIB . addImm ( ConstSelect -> Value . getSExtValue ( ) & maskTrailingOnes < uint64_t > ( STI . getWavefrontSizeLog2 ( ) ) ) ; } else { Optional < ValueAndVReg > ConstVal = getConstantVRegValWithLookThrough ( Val , * MRI , true , true ) ; if ( ConstVal && <STR_LIT> ( ConstVal -> Value . getSExtValue ( ) , STI . hasInv2PiInlineImm ( ) ) ) { MIB . addImm ( ConstVal -> Value . getSExtValue ( ) ) ; MIB . addReg ( LaneSelect ) ; } else { MIB . addReg ( Val ) ; RBI . constrainGenericRegister ( LaneSelect , <STR_LIT> , * MRI ) ; BuildMI ( * MBB , * MIB , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LaneSelect ) ; MIB . addReg ( <STR_LIT> ) ; } } MIB . addReg ( VDstIn ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ;


<s> return nonDbgMICount ( ++ MII , getBundleEnd ( BundleHead . getInstrIterator ( ) ) ) ;


<s> ++ NumIter ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NumIter << <STR_LIT> << NumRemainedBlk << <STR_LIT> ; ) ; SmallVectorImpl < MachineBasicBlock * > :: const_iterator It = OrderedBlks . begin ( ) ; SmallVectorImpl < MachineBasicBlock * > :: const_iterator E = OrderedBlks . end ( ) ; SmallVectorImpl < MachineBasicBlock * > :: const_iterator SccBeginIter = It ; MachineBasicBlock * SccBeginMBB = nullptr ; int SccNumBlk = <NUM_LIT> ; int SccNumIter ; while ( It != E ) { MBB = * It ; if ( ! SccBeginMBB ) { SccBeginIter = It ; SccBeginMBB = MBB ; SccNumIter = <NUM_LIT> ; SccNumBlk = NumRemainedBlk ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( SccBeginMBB ) ; dbgs ( ) << <STR_LIT> ; ) ; } if ( ! isRetiredBlock ( MBB ) ) patternMatch ( MBB ) ; ++ It ; bool ContNextScc = true ; if ( It == E || getSCCNum ( SccBeginMBB ) != getSCCNum ( * It ) ) { ++ SccNumIter ; int sccRemainedNumBlk = countActiveBlock ( SccBeginIter , It ) ; if ( sccRemainedNumBlk != <NUM_LIT> && sccRemainedNumBlk >= SccNumBlk ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( MBB ) << <STR_LIT> << SccNumIter ; dbgs ( ) << <STR_LIT> ; ) ; ContNextScc = true ; } else if ( sccRemainedNumBlk != <NUM_LIT> && sccRemainedNumBlk < SccNumBlk ) { SccNumBlk = sccRemainedNumBlk ; It = SccBeginIter ; ContNextScc = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( MBB ) << <STR_LIT> << SccNumIter << '\n' ; ) ; } else { ContNextScc = true ; } } else {


<s> bool <ISA_LIT>TargetLowering :: shouldExpandGetActiveLaneMask ( EVT ResVT , EVT OpVT ) const { if ( ! Subtarget -> hasSVE ( ) ) return true ;

if ( ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT != <STR_LIT> && ResVT != <STR_LIT> ) return true ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; }


OS << <STR_LIT> << Sym -> getName ( ) << <STR_LIT> ;


<s> return isNewValue ( MI ) && MI . isBranch ( ) ;


<s> for ( auto Elem : Registers ) { errs ( ) << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( Elem ) << <STR_LIT> ; } errs ( ) << <STR_LIT> ;


<s> } EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ;

return combineAddOrSubToADCOrSBB ( N , DAG ) ;


<s> MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ; if ( MJTI == <NUM_LIT> ) return false ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; for ( unsigned i = <NUM_LIT> , e = T2JumpTables . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = T2JumpTables [ i ] ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned NumOps = MCID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( MCID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; bool ByteOk = true ; bool HalfWordOk = true ; unsigned JTOffset = GetOffsetOf ( MI ) + <NUM_LIT> ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; unsigned DstOffset = BBOffsets [ MBB -> getNumber ( ) ] ; if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI = PrevI ; bool OptOk = true ; for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) {


<s> Value * <ISA_LIT>IREmitter :: visitUMAX ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI , Register SwiftErrorVReg ) const {

if ( VRegs . size ( ) > <NUM_LIT> ) return false ;


<s> for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) , & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) } ) TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; for ( Target * T : { & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) TargetRegistry :: RegisterMCInstrAnalysis ( * T , createThumbMCInstrAnalysis ) ; for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getTheThumbLETarget ( ) } ) { TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>LEAsmBackend ) ; } for ( Target * T : { & getThe<ISA_LIT>BETarget ( ) , & getTheThumbBETarget ( ) } ) { TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>BEAsmBackend ) ; }


<s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = { <NUM_LIT> } ; return CalleeSavedRegClasses ;


<s> Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: createImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( imod ) ) ; Inst . addOperand ( MCOperand :: createImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ;


<s> NodeList Refs ; NodeId Start = RA . Id ; do { Refs . push_back ( RA ) ; RA = getNextRelated ( IA , RA ) ;

} while ( RA . Id != <NUM_LIT> && RA . Id != Start ) ;


<s> if ( isNeg ) return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ;

if ( ( V & <NUM_LIT> ) != <NUM_LIT> ) return false ;


<s> LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) . addImm ( <STR_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg ) . addImm ( <NUM_LIT> ) ;

BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( LoopBB ) . addImm ( <STR_LIT> ) ;


<s> assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( InVT == <STR_LIT> ) { if ( VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = VT . getHalfNumVectorElementsVT ( ) ;

SDValue OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , In ) ;


<s> if ( N . getOpcode ( ) == <STR_LIT> ) N = N . getOperand ( <NUM_LIT> ) ; LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ; if ( ! LD || LD -> isVolatile ( ) ) return false ; if ( LD -> getAddressingMode ( ) != <STR_LIT> ) return false ;

<STR_LIT> ExtType = LD -> getExtensionType ( ) ;


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { PM . add ( create<ISA_LIT>BranchSelectionPass ( ) ) ; return false ;


<s> static bool isFMA3 ( unsigned Opcode ) {

return getFMA3Group ( Opcode ) != nullptr ;


<s> if ( ! HasAlloca || ! NeedsAlign ) return ; unsigned LFS = MFI . getLocalFrameSize ( ) ; for ( int i = <NUM_LIT> , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( ! MFI . isSpillSlotObjectIndex ( i ) || MFI . isDeadObjectIndex ( i ) ) continue ; unsigned S = MFI . getObjectSize ( i ) ; unsigned A = std :: max ( MFI . getObjectAlignment ( i ) , <NUM_LIT> ) ; MFI . setObjectAlignment ( i , <NUM_LIT> ) ;


<s> Register EntryReg = JumpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: iterator I ( LEAMI ) ; for ( ++ I ; & * I != JumpMI ; ++ I ) { if ( I -> getOpcode ( ) == <STR_LIT> && I -> getOperand ( <NUM_LIT> ) . getReg ( ) == EntryReg ) RemovableAdd = & * I ; } if ( ! RemovableAdd ) return ; MachineBasicBlock :: iterator J ( RemovableAdd ) ; for ( ++ J ; & * J != JumpMI ; ++ J ) { for ( unsigned K = <NUM_LIT> , E = J -> getNumOperands ( ) ; K != E ; ++ K ) { const MachineOperand & MO = J -> getOperand ( K ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) == EntryReg ) return ;

if ( MO . isUse ( ) && MO . getReg ( ) == EntryReg ) return ;


<s> else if ( nparts == <NUM_LIT> ) { emit_move_insn ( part [ <NUM_LIT> ] [ <NUM_LIT> ] , part [ <NUM_LIT> ] [ <NUM_LIT> ] ) ; emit_move_insn ( part [ <NUM_LIT> ] [ <NUM_LIT> ] , part [ <NUM_LIT> ] [ <NUM_LIT> ] ) ; } } else { if ( GET_MODE ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) == SImode ) { switch ( GET_CODE ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) ) { case MEM : part [ <NUM_LIT> ] [ <NUM_LIT> ] = adjust_address ( part [ <NUM_LIT> ] [ <NUM_LIT> ] , DImode , <NUM_LIT> ) ; break ; case REG : part [ <NUM_LIT> ] [ <NUM_LIT> ] = gen_rtx_REG ( DImode , REGNO ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) ) ; break ; default : gcc_unreachable ( ) ; } if ( GET_MODE ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) == SImode ) part [ <NUM_LIT> ] [ <NUM_LIT> ] = part [ <NUM_LIT> ] [ <NUM_LIT> ] ; } } emit_move_insn ( part [ <NUM_LIT> ] [ <NUM_LIT> ] , part [ <NUM_LIT> ] [ <NUM_LIT> ] ) ; emit_move_insn ( part [ <NUM_LIT> ] [ <NUM_LIT> ] , part [ <NUM_LIT> ] [ <NUM_LIT> ] ) ; return ; } if ( ( REG_P ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) && REG_P ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) && ( REGNO ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) == REGNO ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) || ( nparts == <NUM_LIT> && REGNO ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) == REGNO ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) ) || ( nparts == <NUM_LIT> && REGNO ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) == REGNO ( part [ <NUM_LIT> ] [ <NUM_LIT> ] ) ) ) ) || ( collisions > <NUM_LIT> && reg_overlap_mentioned_p ( part [ <NUM_LIT> ] [ <NUM_LIT> ] , XEXP ( part [ <NUM_LIT> ] [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ) { for ( i = <NUM_LIT> , j = nparts - <NUM_LIT> ; i < nparts ; i ++ , j -- ) { operands [ <NUM_LIT> + i ] = part [ <NUM_LIT> ] [ j ] ; operands [ <NUM_LIT> + i ] = part [ <NUM_LIT> ] [ j ] ; } } else { for ( i = <NUM_LIT> ; i < nparts ; i ++ ) { operands [ <NUM_LIT> + i ] = part [ <NUM_LIT> ] [ i ] ; operands [ <NUM_LIT> + i ] = part [ <NUM_LIT> ] [ i ] ;


<s> const auto * MME = dyn_cast < <ISA_LIT>MCExpr > ( getImm ( ) ) ; if ( MME ) { const <STR_LIT> Kind = MME -> getFixupKind ( ) ; if ( Kind == <STR_LIT> && High < <NUM_LIT> - <NUM_LIT> ) return false ; const MCFixupKindInfo & Info = <STR_LIT> ( Kind , nullptr ) ; int64_t MaxValue = ( <NUM_LIT> << Info . TargetSize ) - <NUM_LIT> ; bool Evaluated = false ; int64_t Constant = <NUM_LIT> ; Evaluated = MME -> evaluateAsConstant ( Constant ) ; if ( Evaluated && Constant > <NUM_LIT> ) { return ( Constant <= MaxValue ) ; } return ( MaxValue <= High ) ; } const auto * SRE = dyn_cast < MCSymbolRefExpr > ( getImm ( ) ) ; if ( SRE ) { return true ; } const auto * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) {


<s> int64_t IntVal ; if ( getParser ( ) . parseAbsoluteExpression ( IntVal ) ) return MatchOperand_ParseFail ; APFloat F ( BitsToDouble ( IntVal ) ) ; if ( Minus ) F . changeSign ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , F . bitcastToAPInt ( ) . getZExtValue ( ) , S , <ISA_LIT>Operand :: ImmTyNone , true ) ) ; return MatchOperand_Success ;


<s> if ( Position == Parent -> end ( ) ) { MachineBasicBlock * Succ = Parent -> getNextNode ( ) ; if ( Succ != nullptr && Parent -> isSuccessor ( Succ ) ) { Position = Succ -> begin ( ) ; Parent = Succ ; } else { llvm_unreachable ( <STR_LIT> ) ; } } Iter Instr = getNextMachineInstrInBB ( Position ) ; if ( Instr == Parent -> end ( ) ) {

return getNextMachineInstr ( Instr , Parent ) ;


<s> C &= ( ( uint64_t ) - <NUM_LIT> ) >> ( <NUM_LIT> - VT . getSizeInBits ( ) ) ; if ( C == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( C == <NUM_LIT> ) return X ; if ( isPowerOf2_64 ( C ) ) return DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( Log2_64 ( C ) , DL , ShiftTy ) ) ; unsigned Log2Ceil = Log2_64_Ceil ( C ) ; uint64_t Floor = <NUM_LIT> << Log2_64 ( C ) ; uint64_t Ceil = Log2Ceil == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << Log2Ceil ; if ( C - Floor <= Ceil - C ) {

SDValue Op0 = genConstMult ( X , Floor , DL , VT , ShiftTy , DAG ) ;


<s> BBInfo . resize ( MF -> getNumBlockIDs ( ) ) ; for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ++ I ) computeBlockSize ( & * I ) ; adjustBBOffsetsAfter ( & MF -> front ( ) ) ; for ( MachineBasicBlock & MBB : * MF ) { if ( ! BBHasFallthrough ( & MBB ) ) WaterList . push_back ( & MBB ) ; for ( MachineInstr & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; int Opc = MI . getOpcode ( ) ; if ( MI . isBranch ( ) ) { bool isCond = false ; unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; int UOpc = Opc ; switch ( Opc ) { default : continue ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = false ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = false ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ;


<s> snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE , NULL ) ;


<s> bool SVEIntrinsicOpts :: optimizeFunctions ( SmallSetVector < Function * , <NUM_LIT> > & Functions ) { bool Changed = false ; Changed |= optimizePTrueIntrinsicCalls ( Functions ) ; Changed |= optimizeIntrinsicCalls ( Functions ) ;


<s> b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B ) ; c = ( __vector unsigned int ) vec_cmpgt ( a , float_exp_mask ) ; d = ( __vector unsigned int ) vec_cmpgt ( b , float_exp_mask ) ;

return ( ( __m128 ) vec_or ( c , d ) ) ;


<s> if ( global_regs [ regno ] ) return false ; if ( cfun -> machine -> interrupt_handler_p && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ;

return ( regno == GLOBAL_POINTER_REGNUM ? TARGET_CALL_SAVED_GP : ! call_used_regs [ regno ] ) ;


<s> inline SDValue getI32Imm ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


<s> gimple stmt = gsi_stmt ( * gsi ) ; tree call = gimple_call_fn ( stmt ) ; gimple new_stmt = NULL ; if ( call ) { tree fndecl = gimple_call_fndecl ( stmt ) ; if ( fndecl ) { tree arg0 , arg1 ; switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case ALPHA_BUILTIN_UMULH : arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , MULT_HIGHPART_EXPR , arg0 , arg1 ) ; break ; default : break ; } } } if ( new_stmt ) {


<s> if ( Val == <NUM_LIT> || Val == <NUM_LIT> ) return MCDisassembler :: Fail ; const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ;

if ( ! isValidCoprocessorNumber ( Val , featureBits ) ) return MCDisassembler :: Fail ;


<s> } unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , IsVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; StackArgsSize = CCInfo . getNextStackOffset ( ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII , VA ) ) return false ; } } } bool PositionIndependent = isPositionIndependent ( ) ; if ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || PositionIndependent ) { unsigned NumInRegs = <NUM_LIT> ; unsigned MaxInRegs = PositionIndependent ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ;


<s> if ( Pattern == MachineCombinerPattern :: REASSOC_XMM_AMM_BMM ) { NewVRD = MRI . createVirtualRegister ( RC ) ; InstrIdxForVirtReg . insert ( std :: make_pair ( NewVRD , <NUM_LIT> ) ) ; } auto AdjustOperandOrder = [ & ] ( MachineInstr * MI , Register RegAdd , bool KillAdd , Register RegMul1 , bool KillRegMul1 , Register RegMul2 , bool KillRegMul2 ) { MI -> getOperand ( AddOpIdx ) . setReg ( RegAdd ) ; MI -> getOperand ( AddOpIdx ) . setIsKill ( KillAdd ) ; MI -> getOperand ( FirstMulOpIdx ) . setReg ( RegMul1 ) ; MI -> getOperand ( FirstMulOpIdx ) . setIsKill ( KillRegMul1 ) ; MI -> getOperand ( FirstMulOpIdx + <NUM_LIT> ) . setReg ( RegMul2 ) ; MI -> getOperand ( FirstMulOpIdx + <NUM_LIT> ) . setIsKill ( KillRegMul2 ) ; } ; if ( Pattern == MachineCombinerPattern :: REASSOC_XY_AMM_BMM ) { MachineInstrBuilder MINewB = BuildMI ( * MF , Prev -> getDebugLoc ( ) , get ( FmaOp ) , NewVRB ) . addReg ( RegX , getKillRegState ( KillX ) ) . addReg ( RegM21 , getKillRegState ( KillM21 ) ) . addReg ( RegM22 , getKillRegState ( KillM22 ) ) ; MachineInstrBuilder MINewA = BuildMI ( * MF , Root . getDebugLoc ( ) , get ( FmaOp ) , NewVRA ) . addReg ( RegY , getKillRegState ( KillY ) ) . addReg ( RegM31 , getKillRegState ( KillM31 ) ) . addReg ( RegM32 , getKillRegState ( KillM32 ) ) ; if ( AddOpIdx != <NUM_LIT> ) { AdjustOperandOrder ( MINewB , RegX , KillX , RegM21 , KillM21 , RegM22 , KillM22 ) ; AdjustOperandOrder ( MINewA , RegY , KillY , RegM31 , KillM31 , RegM32 , KillM32 ) ; } MachineInstrBuilder MINewC = BuildMI ( * MF , Root . getDebugLoc ( ) , get ( FMAOpIdxInfo [ Idx ] [ InfoArrayIdxFAddInst ] ) , RegC ) . addReg ( NewVRB , getKillRegState ( true ) ) . addReg ( NewVRA , getKillRegState ( true ) ) ; setSpecialOperandAttr ( * MINewA , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewB , IntersectedFlags ) ; setSpecialOperandAttr ( * MINewC , IntersectedFlags ) ; InsInstrs . push_back ( MINewA ) ;


<s> const char * RegName = <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; if ( ! Subtarget -> isDarwin ( ) ) RegName = stripRegisterPrefix ( RegName ) ; O << RegName ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ! GV -> isStrongDefinitionForLinker ( ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ;

} else if ( GV -> isDeclaration ( ) || GV -> hasCommonLinkage ( ) || GV -> hasAvailableExternallyLinkage ( ) ) {


<s> while ( v -> length ( ) > <NUM_LIT> ) delete v -> pop ( ) ;


<s> if ( ! Alloca || ! Alloca -> isStaticAlloca ( ) ) continue ; Type * Ty = Alloca -> getAllocatedType ( ) ; unsigned AllocaSize = Ty -> isSized ( ) ? DL . getTypeAllocSize ( Ty ) : <NUM_LIT> ; if ( AllocaSize > MaxAlloca ) continue ; } else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) { LocalGEPsSeen ++ ; if ( LocalGEPsSeen > <NUM_LIT> || L -> getLoopDepth ( ) > <NUM_LIT> || ( ! isa < GlobalVariable > ( GEP -> getPointerOperand ( ) ) && ! isa < Argument > ( GEP -> getPointerOperand ( ) ) ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * L << <STR_LIT> ) ; UP . Runtime = UnrollRuntimeLocal ; } bool HasLoopDef = false ; for ( const Value * Op : GEP -> operands ( ) ) { const Instruction * Inst = dyn_cast < Instruction > ( Op ) ; if ( ! Inst || L -> isLoopInvariant ( Op ) ) continue ; if ( llvm :: any_of ( L -> getSubLoops ( ) , [ Inst ] ( const Loop * SubLoop ) { return SubLoop -> contains ( Inst ) ; } ) ) continue ; HasLoopDef = true ; break ; } if ( ! HasLoopDef ) continue ; UP . Threshold = Threshold ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Threshold << <STR_LIT> << * L << <STR_LIT> << * GEP << '\n' ) ; if ( UP . Threshold >= MaxBoost ) return ; } if ( L -> isInnermost ( ) && BB -> size ( ) < UnrollMaxBlockToAnalyze ) UP . MaxIterationsCountToAnalyze = <NUM_LIT> ; }


<s> double r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ;


<s> EVT ViaVecTy = ResVecTy ; SDLoc DL ( Op ) ; SDValue LaneA ; SDValue LaneB = Op -> getOperand ( <NUM_LIT> ) ; if ( ResVecTy == <STR_LIT> ) { LaneA = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ViaVecTy = <STR_LIT> ; } else LaneA = LaneB ; SDValue Ops [ <NUM_LIT> ] = { LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB , LaneA , LaneB } ;

SDValue Result = DAG . getNode ( <STR_LIT> , DL , ViaVecTy , makeArrayRef ( Ops , ViaVecTy . getVectorNumElements ( ) ) ) ;


<s> want_long = <NUM_LIT> ; } if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( insn ) && ( get_attr_cond ( insn ) != COND_USE || ! reg_set_p ( gen_rtx_REG ( CCmode , CC_REG ) , XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ) ) { prev = as_a < rtx_insn * > ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ; gcc_assert ( ! prev_real_insn ( insn ) || ! arc_hazard ( prev_real_insn ( insn ) , prev ) ) ; cfun -> machine -> force_short_suffix = ! want_long ; rtx save_pred = current_insn_predicate ; final_scan_insn ( prev , asm_out_file , optimize , <NUM_LIT> , NULL ) ; cfun -> machine -> force_short_suffix = - <NUM_LIT> ; prev -> set_deleted ( ) ; current_output_insn = insn ; current_insn_predicate = save_pred ; }

else if ( want_long ) fputs ( <STR_LIT> , asm_out_file ) ;


<s> default : break ; case <STR_LIT> : { uint64_t TopLabel = ControlFlowCounter ++ ; ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter ++ , false ) ) ; printAnnotation ( OS , <STR_LIT> + utostr ( TopLabel ) + ':' ) ; ControlFlowStack . push_back ( std :: make_pair ( TopLabel , true ) ) ; break ; } case <STR_LIT> : ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter ++ , false ) ) ; break ; case <STR_LIT> : ControlFlowStack . pop_back ( ) ; printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowStack . pop_back_val ( ) . first ) + ':' ) ; break ; case <STR_LIT> :


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> ExceptionsType = ExceptionHandling :: WinEH ;


<s> T Val ; memcpy ( & Val , Bytes . data ( ) + Size , sizeof ( T ) ) ; <STR_LIT> :: byte_swap < T , <STR_LIT> :: little > ( Val ) ; Size += sizeof ( T ) ; if ( std :: is_floating_point < T > :: value ) { MI . addOperand ( MCOperand :: createFPImm ( static_cast < double > ( Val ) ) ) ; } else { MI . addOperand ( MCOperand :: createImm ( static_cast < int64_t > ( Val ) ) ) ;


<s> bool hasC910 ( ) const { return HasC910 ;


<s> if ( <ISA_LIT>SubTarget -> isTargetELF ( ) ) GlobalBaseReg = <STR_LIT> ; else GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; if ( <ISA_LIT>SubTarget -> isTargetELF ( ) ) { unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , TempReg ) . addReg ( GlobalBaseReg ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( GlobalBaseReg ) . addReg ( TempReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ;


<s> if ( ret ) { int64_t c = dyn_cast < ConstantSDNode > ( O ) -> getSExtValue ( ) ; if ( <STR_LIT> ( c ) ) { Base = B ; Offset = O ; return true ; }


<s> return __builtin_arm_qadd8 ( __a , __b ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & S1 = DI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & S2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V1 , V2 ; if ( ! checkForImmediate ( S1 , V1 ) || ! checkForImmediate ( S2 , V2 ) ) return false ; TV = V2 | ( static_cast < uint64_t > ( V1 ) << <NUM_LIT> ) ; break ; } case TargetOpcode :: REG_SEQUENCE : { const MachineOperand & S1 = DI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & S3 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V1 , V3 ; if ( ! checkForImmediate ( S1 , V1 ) || ! checkForImmediate ( S3 , V3 ) ) return false ; unsigned Sub2 = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Sub4 = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Sub2 == <STR_LIT> && Sub4 == <STR_LIT> ) TV = V1 | ( V3 << <NUM_LIT> ) ; else if ( Sub2 == <STR_LIT> && Sub4 == <STR_LIT> ) TV = V3 | ( V1 << <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; } default : return false ; } switch ( MO . getSubReg ( ) ) { case <STR_LIT> : Val = TV & <NUM_LIT> ; break ; case <STR_LIT> : Val = ( TV >> <NUM_LIT> ) & <NUM_LIT> ;


<s> int i = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( ( unsigned ) ( ~ i ) < <NUM_LIT> ) return <STR_LIT> ; if ( ( unsigned ) i < <NUM_LIT> ) return <STR_LIT> ; if ( i >= - <NUM_LIT> && i < <NUM_LIT> ) return <STR_LIT> ; if ( ( unsigned ) i < <NUM_LIT> ) return <STR_LIT> ; if ( i >= - <NUM_LIT> && i < <NUM_LIT> ) return <STR_LIT> ; } if ( push_operand ( operands [ <NUM_LIT> ] , SImode ) ) return <STR_LIT> ; return <STR_LIT> ; case HImode : if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) { int i = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( i == <NUM_LIT> ) return <STR_LIT> ; else if ( ( unsigned int ) i < <NUM_LIT> ) return <STR_LIT> ; else if ( ( unsigned int ) ~ i < <NUM_LIT> ) return <STR_LIT> ; else if ( ( unsigned int ) i < <NUM_LIT> ) return <STR_LIT> ; } return <STR_LIT> ; case QImode : if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) {


<s> if ( got == registersMsrToSlvMap . end ( ) ) { return regNUM ; } else { return got -> second ;


<s> assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , getT1tRn ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; assert ( OpIdx < NumOps && <STR_LIT> ) ;

if ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) {


<s> if ( ( uint64_t ) Mask [ i ] == ( ( ( uint64_t ) i << N ) & ModMask ) ) IsAnyViable = true ; else ViableForN [ j ] = false ; } if ( ! IsAnyViable ) break ; } for ( unsigned j = <NUM_LIT> ; j != array_lengthof ( ViableForN ) ; ++ j ) if ( ViableForN [ j ] ) return j + <NUM_LIT> ; return <NUM_LIT> ;


<s> SDValue OutChains [ <NUM_LIT> ] ; OutChains [ <NUM_LIT> ] = DAG . getStore ( StNode -> getChain ( ) , dl , SDValue ( Hi64 , <NUM_LIT> ) , StNode -> getBasePtr ( ) , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; EVT addrVT = StNode -> getBasePtr ( ) . getValueType ( ) ;

SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , StNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , addrVT ) ) ;


<s> if ( MO2 . getReg ( ) ) { O << <STR_LIT> << getAddrOpcStr ( <STR_LIT> ( MO3 . getImm ( ) ) ) ; printRegName ( O , MO2 . getReg ( ) ) ; O << ']' << markup ( <STR_LIT> ) ; return ; } unsigned ImmOffs = <STR_LIT> ( MO3 . getImm ( ) ) ; <STR_LIT> op = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( ImmOffs || ( op == <STR_LIT> ) ) {

O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << <STR_LIT> ( op ) << ImmOffs << markup ( <STR_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> else if ( ! TARGET_80387 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! ( TARGET_SSE && TARGET_SSE_MATH ) ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; } return ( type == EXCESS_PRECISION_TYPE_STANDARD ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT : FLT_EVAL_METHOD_UNPREDICTABLE ) ; case EXCESS_PRECISION_TYPE_FLOAT16 : if ( TARGET_80387 && ! ( TARGET_SSE_MATH && TARGET_SSE ) ) error ( <STR_LIT> ) ;


<s> void <ISA_LIT>MCCodeEmitter :: EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Opcode = MI . getOpcode ( ) ; MCNumEmitted ++ ;

EmitInstruction ( getBinaryCodeForInstr ( MI ) , OS ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) {


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { O << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> assert ( Kind == k_Tok && <STR_LIT> ) ;


<s> } MachineFunctionProperties getRequiredProperties ( ) const override { return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ; } StringRef getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override { const std :: vector < MachineConstantPoolEntry > & CPs = MF . getConstantPool ( ) -> getConstants ( ) ; if ( CPs . empty ( ) ) return false ; auto * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; auto * BB = MF . CreateMachineBasicBlock ( ) ; BB -> setAlignment ( <NUM_LIT> ) ; MF . ensureAlignment ( <NUM_LIT> ) ; MF . push_back ( BB ) ; for ( size_t i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { auto Size = MF . getDataLayout ( ) . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; BuildMI ( * BB , BB -> end ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; } return true ; } } ; char <STR_LIT> = <NUM_LIT> ; } FunctionPass * llvm :: create<ISA_LIT>ConstantIslandPass ( ) { return new <ISA_LIT>ConstantIslands ( ) ;


<s> return create<ISA_LIT>WinCOFFObjectWriter ( ) ;


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const ScheduleDAG * DAG ) : ScoreboardHazardRecognizer ( ItinData , DAG , <STR_LIT> ) {


<s> DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ;

if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ;


<s> SDLoc dl ( Op ) ; if ( ( InVTElt == <STR_LIT> ) && ( ( ( Subtarget . hasBWI ( ) && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget . hasDQI ( ) && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) && InVTElt != <STR_LIT> && ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || Subtarget . hasBWI ( ) ) ) { if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return getExtendInVec ( In . getOpcode ( ) , dl , VT , In . getOperand ( <NUM_LIT> ) , DAG ) ; return getExtendInVec ( <STR_LIT> , dl , VT , In , DAG ) ; } if ( InVTElt != <STR_LIT> ) return SDValue ( ) ; MVT ExtVT = VT ; if ( ! VT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) { ExtVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / NumElts ) , NumElts ) ; } else if ( VTElt == <STR_LIT> || VTElt == <STR_LIT> ) { ExtVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; } SDValue V ; if ( Subtarget . hasDQI ( ) ) {

V = getExtendInVec ( <STR_LIT> , dl , ExtVT , In , DAG ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = getOpcForTextureInstr ( Intrinsic ) ; Info . memVT = <STR_LIT> ; Info . ptrVal = nullptr ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = false ; Info . align = <NUM_LIT> ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = getOpcForTextureInstr ( Intrinsic ) ; Info . memVT = <STR_LIT> ; Info . ptrVal = nullptr ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = false ; Info . align = <NUM_LIT> ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = getOpcForSurfaceInstr ( Intrinsic ) ; Info . memVT = <STR_LIT> ; Info . ptrVal = nullptr ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = false ; Info . align = <NUM_LIT> ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( STI . in<ISA_LIT>16Mode ( ) ) return create<ISA_LIT>16TargetLowering ( TM , STI ) ; return create<ISA_LIT>SETargetLowering ( TM , STI ) ;


<s> vmlal_high_s8 ( int16x8_t a , int8x16_t b , int8x16_t c ) { int16x8_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> return ( vector float ) __builtin_altivec_vrfin ( ( vector float ) a1 ) ;


<s> } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 : if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ; return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RELAX ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ALIGN ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB8 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SET32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_SUB32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ADD64 ;


<s> const MCOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & SegReg = MI -> getOperand ( Op + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << DispVal ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > Z ( getThe<ISA_LIT>Target ( ) ) ;


<s> if ( is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) || is_attribute_p ( <STR_LIT> , TREE_PURPOSE ( attrs ) ) ) warning ( OPT_Wattributes , <STR_LIT> , TREE_PURPOSE ( attrs ) ) ; else { * tail = tree_cons ( TREE_PURPOSE ( attrs ) , NULL_TREE , NULL_TREE ) ; tail = & TREE_CHAIN ( * tail ) ; } } attrs = * attributes ; }


<s> unsigned NumElements = cast < FixedVectorType > ( DataTypeVTy ) -> getNumElements ( ) ; unsigned EltSize = DataTypeVTy -> getElementType ( ) -> getScalarSizeInBits ( ) ; return NumElements > <NUM_LIT> && isPowerOf2_64 ( NumElements ) && EltSize >= <NUM_LIT> && EltSize <= <NUM_LIT> && isPowerOf2_64 ( EltSize ) ;


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return X ;


<s> return ( reg_class_size [ ( int ) regclass ] == <NUM_LIT> ) ;


<s> nregs = XVECLEN ( p , <NUM_LIT> ) - <NUM_LIT> ; reg = REGNO ( XEXP ( XVECEXP ( p , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( reg < <NUM_LIT> ) { if ( nregs * <NUM_LIT> == offset - <NUM_LIT> ) { fprintf ( asm_out_file , <STR_LIT> ) ; offset -= <NUM_LIT> ; } reg_size = <NUM_LIT> ; } else if ( IS_VFP_REGNUM ( reg ) ) { offset -= <NUM_LIT> ; reg_size = <NUM_LIT> ; } else if ( reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM ) { asm_fprintf ( asm_out_file , <STR_LIT> , reg , nregs ) ; return ; } else abort ( ) ; if ( offset != nregs * reg_size ) abort ( ) ; fprintf ( asm_out_file , <STR_LIT> ) ; offset = <NUM_LIT> ; lastreg = <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= nregs ; i ++ ) { e = XVECEXP ( p , <NUM_LIT> , i ) ; if ( GET_CODE ( e ) != SET || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != MEM || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != REG ) abort ( ) ; reg = REGNO ( XEXP ( e , <NUM_LIT> ) ) ; if ( reg < lastreg ) abort ( ) ; if ( i != <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( IS_VFP_REGNUM ( reg ) ) asm_fprintf ( asm_out_file , <STR_LIT> , ( reg - FIRST_VFP_REGNUM ) / <NUM_LIT> ) ; else asm_fprintf ( asm_out_file , <STR_LIT> , reg ) ; e = XEXP ( XEXP ( e , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( e ) == PLUS ) { offset += reg_size ; if ( GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != REG || REGNO ( XEXP ( e , <NUM_LIT> ) ) != SP_REGNUM || GET_CODE ( XEXP ( e , <NUM_LIT> ) ) != CONST_INT || offset != INTVAL ( XEXP ( e , <NUM_LIT> ) ) ) abort ( ) ; }

else if ( i != <NUM_LIT> || GET_CODE ( e ) != REG || REGNO ( e ) != SP_REGNUM ) abort ( ) ;


<s> unsigned getSGPREncodingGranule ( ) const {

return <STR_LIT> :: getSGPREncodingGranule ( MCSubtargetInfo :: getFeatureBits ( ) ) ;


<s> ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; Disp += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) . first ; if ( IndexReg == <NUM_LIT> ) return false ; break ; } goto unsupported_gep ; } } if ( ! isInt < <NUM_LIT> > ( Disp ) ) break ; AM . IndexReg = IndexReg ; AM . Scale = Scale ; AM . Disp = ( uint32_t ) Disp ; if ( <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ) return true ; AM = SavedAM ; break ; unsupported_gep : break ; } } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) if ( const GlobalVariable * GVar = dyn_cast_or_null < GlobalVariable > ( GA -> resolveAliasedGlobal ( false ) ) ) if ( GVar -> isThreadLocal ( ) ) return false ; if ( ! Subtarget -> isPICStyleRIPRel ( ) || ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ) { AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) { if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } AM . GVOpFlags = GVFlags ; return true ; } DenseMap < const Value * , unsigned > :: iterator I = LocalValueMap . find ( V ) ; unsigned LoadReg ; if ( I != LocalValueMap . end ( ) && I -> second != <NUM_LIT> ) { LoadReg = I -> second ;


<s> return true ; } auto * BO = dyn_cast < BinaryOperator > ( Index ) ; if ( ! BO ) return false ; if ( BO -> getOpcode ( ) != Instruction :: Add && BO -> getOpcode ( ) != Instruction :: Or && BO -> getOpcode ( ) != Instruction :: Mul && BO -> getOpcode ( ) != Instruction :: Shl ) return false ; if ( BO -> getOpcode ( ) == Instruction :: Shl && ! isa < Constant > ( BO -> getOperand ( <NUM_LIT> ) ) ) return false ; if ( BO -> getOpcode ( ) == Instruction :: Or && ! haveNoCommonBitsSet ( BO -> getOperand ( <NUM_LIT> ) , BO -> getOperand ( <NUM_LIT> ) , * DL ) ) return false ; Value * OtherOp ; if ( isa < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) && L -> contains ( cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ) ) { Index = cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ; OtherOp = BO -> getOperand ( <NUM_LIT> ) ; } else if ( isa < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) && L -> contains ( cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ) ) { Index = cast < Instruction > ( BO -> getOperand ( <NUM_LIT> ) ) ; OtherOp = BO -> getOperand ( <NUM_LIT> ) ; } else { return false ; } if ( ! L -> isLoopInvariant ( OtherOp ) ) return false ; Value * SplatOp = getSplatValue ( OtherOp ) ; if ( ! SplatOp ) return false ; if ( ! matchStridedRecurrence ( Index , L , Stride , BasePtr , Inc , Builder ) ) return false ; unsigned StepIndex = Inc -> getOperand ( <NUM_LIT> ) == BasePtr ? <NUM_LIT> : <NUM_LIT> ; unsigned StartBlock = BasePtr -> getOperand ( <NUM_LIT> ) == Inc ? <NUM_LIT> : <NUM_LIT> ; Value * Step = Inc -> getOperand ( StepIndex ) ;

Value * Start = BasePtr -> getOperand ( StartBlock ) ;


<s> static DecodeStatus decodeOperand_VGPR_32 ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { auto DAsm = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; return addOperand ( Inst , DAsm -> decodeSrcOp ( <ISA_LIT>Disassembler :: OPW32 , Imm ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > LoOps , HiOps ; for ( unsigned I = <NUM_LIT> , E = VT . getVectorNumElements ( ) / <NUM_LIT> ; I != E ; ++ I ) { LoOps . push_back ( Op . getOperand ( I ) ) ; HiOps . push_back ( Op . getOperand ( I + E ) ) ; } SDValue Lo = DAG . getBuildVector ( HalfVT , SL , LoOps ) ; SDValue Hi = DAG . getBuildVector ( HalfVT , SL , HiOps ) ; SDValue CastLo = DAG . getNode ( <STR_LIT> , SL , HalfIntVT , Lo ) ; SDValue CastHi = DAG . getNode ( <STR_LIT> , SL , HalfIntVT , Hi ) ; SDValue Blend = DAG . getBuildVector ( <STR_LIT> ( HalfIntVT , <NUM_LIT> ) , SL , { CastLo , CastHi } ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Blend ) ; } assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; assert ( ! Subtarget -> hasVOP3PInsts ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; if ( Hi . isUndef ( ) ) { Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ; SDValue ExtLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , ExtLo ) ;


<s> int getTCReturnAddrDelta ( ) const { return TailCallReturnAddrDelta ;


<s> if ( Op . getReg ( ) == <NUM_LIT> ) { MI -> dump ( ) ; } printRegName ( O , Op . getReg ( ) ) ; return ; } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ;


<s> return ( uint64x1_t ) { __builtin_aarch64_ursra_ndi_uuus ( __a [ <NUM_LIT> ] , __b [ <NUM_LIT> ] , __c ) } ;


<s> ptr = to_host_file_spec ( argv [ i ] ) ; exefilename = xstrdup ( ptr ) ; out_len = strlen ( ptr ) ; buff = xmalloc ( out_len + <NUM_LIT> ) ; if ( share ) strcpy ( buff , <STR_LIT> ) ; else strcpy ( buff , <STR_LIT> ) ; strcat ( buff , ptr ) ; addarg ( buff ) ; if ( share ) { sharefilename = xmalloc ( out_len + <NUM_LIT> ) ; if ( ptr == strchr ( argv [ i ] , ']' ) ) strcpy ( sharefilename , ++ ptr ) ; else if ( ptr == strchr ( argv [ i ] , ':' ) ) strcpy ( sharefilename , ++ ptr ) ; else if ( ptr == strrchr ( argv [ i ] , '/' ) ) strcpy ( sharefilename , ++ ptr ) ;

else strcpy ( sharefilename , argv [ i ] ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; SDValue Flag ; EVT SPTy = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ;


<s> MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; unsigned Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , false ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . addDef ( TRI -> getReturnAddressReg ( MF ) ) ; if ( ! addCallTargetOperands ( MIB , MIRBuilder , Info ) ) return false ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , Info . CallConv ) ; MIB . addRegMask ( Mask ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( Info . CallConv , Info . IsVarArg , MF , ArgLocs , F . getContext ( ) ) ; SmallVector < std :: pair < MCRegister , Register > , <NUM_LIT> > ImplicitArgRegs ; if ( <ISA_LIT>TargetMachine :: EnableFixedFunctionABI && Info . CallConv != CallingConv :: <ISA_LIT>_Gfx ) { if ( ! passSpecialInputs ( MIRBuilder , CCInfo , ImplicitArgRegs , Info ) ) return false ; } SmallVector < Register , <NUM_LIT> > PhysRegs ; OutgoingValueAssigner Assigner ( AssignFnFixed , AssignFnVarArg ) ; if ( ! determineAssignments ( Assigner , OutArgs , CCInfo ) ) return false ; <ISA_LIT>OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , false ) ; if ( ! handleAssignments ( Handler , OutArgs , CCInfo , ArgLocs , MIRBuilder ) ) return false ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; handleImplicitCallArguments ( MIRBuilder , MIB , ST , * MFI , ImplicitArgRegs ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; if ( MIB -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * ST . getInstrInfo ( ) , * ST . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , MIB -> getOperand ( <NUM_LIT> ) , <NUM_LIT> ) ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Info . CanLowerReturn && ! Info . OrigRet . Ty -> isVoidTy ( ) ) {

CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( Info . CallConv , Info . IsVarArg ) ;


<s> return FP32InputDenormals && FP32OutputDenormals ;


<s> getShiftRight16Imm ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {

return <NUM_LIT> - MI . getOperand ( Op ) . getImm ( ) ;


<s> const TargetSchedModel & getSchedModel ( ) const { return SchedModel ;


<s> UsedFP = true ; FPReg = NewFPReg ; if ( NewSPReg == <STR_LIT> ) FPOffset = SPOffset + Offset ; else FPOffset += Offset ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , TargetOptions Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OptLevel ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , getGPUOrDefault ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( RM ) , CM , OptLevel ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , getTargetCPU ( ) , FS , * this ) , IntrinsicInfo ( ) { setRequiresStructuredCFG ( true ) ;


<s> void <ISA_LIT>16InstrInfo :: loadRegFromStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI , int64_t Offset ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;

MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOLoad ) ;


<s> case ImmTyGLC : OS << <STR_LIT> ; break ; case ImmTySLC : OS << <STR_LIT> ; break ; case ImmTyTFE : OS << <STR_LIT> ; break ; case ImmTyClamp<ISA_LIT> : OS << <STR_LIT> ; break ; case ImmTyOMod<ISA_LIT> : OS << <STR_LIT> ; break ; case ImmTyDppCtrl : OS << <STR_LIT> ; break ; case ImmTyDppRowMask : OS << <STR_LIT> ; break ; case ImmTyDppBankMask : OS << <STR_LIT> ; break ; case ImmTyDppBoundCtrl : OS << <STR_LIT> ; break ; case ImmTySdwaSel : OS << <STR_LIT> ; break ; case ImmTySdwaDstUnused : OS << <STR_LIT> ; break ; case ImmTyDMask : OS << <STR_LIT> ; break ; case ImmTyUNorm : OS << <STR_LIT> ; break ; case ImmTyDA : OS << <STR_LIT> ; break ; case ImmTyR128 : OS << <STR_LIT> ; break ; case ImmTyLWE : OS << <STR_LIT> ; break ; case ImmTyHwreg : OS << <STR_LIT> ; break ; case ImmTySendMsg : OS << <STR_LIT> ; break ;


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; uint64_t Value = SignExtend64 < N > ( Imm ) * <NUM_LIT> + Address ;

if ( ! tryAddingSymbolicOperand ( Value , isBranch , Address , <NUM_LIT> , N / <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( Value ) ) ;


<s> <STR_LIT> CC = StringSwitch < <STR_LIT> > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;

if ( CC == <STR_LIT> && getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) CC = StringSwitch < <STR_LIT> > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> if ( ArgOffset > LinkageSize + ParamAreaSize ) UseMemory = true ; if ( ! Flags . isByVal ( ) ) { if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ( HasQPX && ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) ) ) if ( AvailableFPRs > <NUM_LIT> ) { -- AvailableFPRs ; return false ; } if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) if ( AvailableVRs > <NUM_LIT> ) { -- AvailableVRs ;


<s> unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz != <NUM_LIT> && EltSz != <NUM_LIT> && EltSz != <NUM_LIT> ) return false ; unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ;

if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz ) return false ;


<s> if ( unsigned SubReg = MO . getSubReg ( ) ) {

assert ( RI . getRegSizeInBits ( * RI . getSubClassWithSubReg ( MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) . getRegClass ( MO . getReg ( ) ) , SubReg ) ) >= <NUM_LIT> && <STR_LIT> ) ;


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ;

State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;

else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;


<s> Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = getPointerTy ( ) ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( getPointerTy ( ) ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , dl ) ; } else { SDValue Flag ; const unsigned Reg = ( Subtarget -> isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ;

unsigned SPReg = RegInfo -> getStackRegister ( ) ;


<s> static bool isPSHUFHWMask ( ArrayRef < int > Mask , MVT VT , bool HasInt256 ) { if ( VT != <STR_LIT> && ( ! HasInt256 || VT != <STR_LIT> ) ) return false ; if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> ) { if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ;


<s> bool is ( unsigned T ) const { assert ( T == <NUM_LIT> || T == <NUM_LIT> ) ;

return T == <NUM_LIT> ? Type == Zero : ( T == <NUM_LIT> ? Type == One : false ) ;


<s> Register FactorRegister = TII -> getVLENFactoredAmount ( MF , MBB , MBBI , DL , Amount , Flag ) ;

BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , SPReg ) . addReg ( SPReg ) . addReg ( FactorRegister , RegState :: Kill ) . setMIFlag ( Flag ) ;


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ;

return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ) ;


<s> const FeatureBitset & FeatureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> && ! FeatureBits [ <STR_LIT> ] ) S = MCDisassembler :: SoftFail ;

if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> if ( of == CONST0_RTX ( mode ) ) { emit_move_insn ( operands [ <NUM_LIT> ] , ot ) ; return ; } x = gen_rtx_NOT ( mode , cmp ) ; x = gen_rtx_AND ( mode , x , of ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , x ) ) ; } else if ( of == CONST0_RTX ( mode ) ) { x = gen_rtx_AND ( mode , cmp , ot ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , x ) ) ;


<s> if ( SetCC . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , Ty , SetCC . getOperand ( <NUM_LIT> ) , SetCC . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , SetCC . getOperand ( <NUM_LIT> ) ) ;


<s> ismatch = true ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned answer = i * <NUM_LIT> + <NUM_LIT> ; if ( isV2undef && answer >= NumElts ) answer -= NumElts ; if ( M [ i ] != - <NUM_LIT> && ( unsigned ) M [ i ] != answer ) { ismatch = false ; break ; } } if ( ismatch ) return <STR_LIT> ; ismatch = true ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned answer = i / <NUM_LIT> + NumElts * ( i % <NUM_LIT> ) ; if ( isV2undef && answer >= NumElts ) answer -= NumElts ; if ( M [ i ] != - <NUM_LIT> && ( unsigned ) M [ i ] != answer ) { ismatch = false ; break ; } } if ( ismatch ) return <STR_LIT> ; ismatch = true ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { unsigned answer = ( NumElts + i ) / <NUM_LIT> + NumElts * ( i % <NUM_LIT> ) ; if ( isV2undef && answer >= NumElts ) answer -= NumElts ; if ( M [ i ] != - <NUM_LIT> && ( unsigned ) M [ i ] != answer ) { ismatch = false ; break ; } } if ( ismatch ) return <STR_LIT> ; ismatch = true ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; auto setBitVector = [ & Reserved , this ] ( unsigned Reg ) { for ( MCRegAliasIterator I ( Reg , this , true ) ; I . isValid ( ) ; ++ I ) { Reserved . set ( * I ) ; } for ( MCSubRegIterator I ( Reg , this , true ) ; I . isValid ( ) ; ++ I ) { Reserved . set ( * I ) ; } } ; setBitVector ( <STR_LIT> ) ; setBitVector ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { setBitVector ( FramePtr ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> <STR_LIT> ) ; setBitVector ( getBaseRegister ( ) ) ; } return Reserved ;


<s> [ [ noreturn ] ] static void raise_relocation_error ( unsigned Width , unsigned Kind ) { std :: string Text ; raw_string_ostream Stream ( Text ) ; Stream << <STR_LIT> << Width << <STR_LIT> << Kind ; report_fatal_error ( Twine ( Stream . str ( ) ) ) ;


<s> int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT ; int padding_locals ; int regno ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; padding_locals = cfun -> machine -> local_vars_size % stack_alignment ; if ( padding_locals ) padding_locals = stack_alignment - padding_locals ; cfun -> machine -> local_vars_size += padding_locals ; cfun -> machine -> callee_saved_reg_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] ) ) cfun -> machine -> callee_saved_reg_size += <NUM_LIT> ;

cfun -> machine -> size_for_adjusting_sp = crtl -> args . pretend_args_size + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? ( HOST_WIDE_INT ) crtl -> outgoing_args_size : <NUM_LIT> ) ;


<s> case <STR_LIT> : return & * I ; } ++ NumCmpTermRejs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; return nullptr ; } for ( MachineBasicBlock :: iterator B = MBB -> begin ( ) ; I != B ; ) { -- I ; assert ( ! I -> isTerminator ( ) && <STR_LIT> ) ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) || ! isUInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumImmRangeRejs ; return nullptr ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isDeadDef ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return & * I ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumLiveDstRejs ; return nullptr ; case <STR_LIT> : case <STR_LIT> :


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( STI ) , RI ( STI . getTargetTriple ( ) ) {


<s> SDLoc DL ( N ) ; int FI = cast < FrameIndexSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; SDValue FiOp = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; int TagOffset = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDNode * Out = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { FiOp , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( TagOffset , DL , <STR_LIT> ) } ) ; ReplaceNode ( N , Out ) ;


return ( ( qword ) ( vec_perm ( vec_perm ( a , b , pattern ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) , pat ) ) ) ;


<s> void LinearizedRegion :: replaceRegisterInsideRegion ( unsigned Register , unsigned NewRegister , bool IncludeLoopPHIs , MachineRegisterInfo * MRI ) {

replaceRegister ( Register , NewRegister , MRI , true , false , IncludeLoopPHIs ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) {


<s> int64_t Value = CE -> getValue ( ) ; return ( ( Value & <NUM_LIT> ) == <NUM_LIT> && Value <= <NUM_LIT> && Value >= - <NUM_LIT> ) ;


<s> MVT VT = N . getSimpleValueType ( ) ; unsigned Complexity = <NUM_LIT> ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) if ( AM . Base_Reg . getNode ( ) ) Complexity = <NUM_LIT> ; else AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity ++ ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Scale > <NUM_LIT> ) Complexity ++ ; if ( AM . hasSymbolicDisplacement ( ) ) { if ( Subtarget -> is64Bit ( ) ) Complexity = <NUM_LIT> ; else Complexity += <NUM_LIT> ; } if ( AM . Disp && ( AM . Base_Reg . getNode ( ) || AM . IndexReg . getNode ( ) ) ) Complexity ++ ; if ( Complexity <= <NUM_LIT> ) return false ; getAddressOperands ( AM , SDLoc ( N ) , Base , Scale , Index , Disp , Segment ) ;


<s> switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) { case E_SFmode : func = <STR_LIT> ; break ; case E_DFmode : func = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } break ; case FLOAT_TRUNCATE : switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) { case E_SFmode : func = <STR_LIT> ; break ; case E_DFmode : func = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } break ; case FLOAT : switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) { case E_SImode : func = <STR_LIT> ; if ( TARGET_ARCH64 ) operands [ <NUM_LIT> ] = gen_rtx_SIGN_EXTEND ( DImode , operands [ <NUM_LIT> ] ) ; break ; case E_DImode : func = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } break ; case UNSIGNED_FLOAT : switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) { case E_SImode : func = <STR_LIT> ; if ( TARGET_ARCH64 ) operands [ <NUM_LIT> ] = gen_rtx_ZERO_EXTEND ( DImode , operands [ <NUM_LIT> ] ) ; break ; case E_DImode : func = <STR_LIT> ;


<s> bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( TARGET_ALTIVEC && ( align >= <NUM_LIT> || TARGET_EFFICIENT_UNALIGNED_VSX ) ) clear_step = <NUM_LIT> ; else if ( TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) clear_step = <NUM_LIT> ; else clear_step = <NUM_LIT> ; if ( optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; if ( ! optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; for ( offset = <NUM_LIT> ; bytes > <NUM_LIT> ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= <NUM_LIT> && TARGET_ALTIVEC && ( align >= <NUM_LIT> || TARGET_EFFICIENT_UNALIGNED_VSX ) ) { clear_bytes = <NUM_LIT> ; mode = V4SImode ; } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes = <NUM_LIT> ; mode = DImode ; if ( offset == <NUM_LIT> && align < <NUM_LIT> ) { rtx addr ; addr = XEXP ( orig_dest , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes = <NUM_LIT> ;


<s> OperandMatchResultTy parseGR64 ( OperandVector & Operands ) {

return parseRegister ( Operands , GR64Reg ) ;


<s> case CallingConv :: Tail : case CallingConv :: Swift : case CallingConv :: SwiftTail : case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_StdCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: <ISA_LIT>_VectorCall : case CallingConv :: Intel_OCL_BI : return isTargetWin64 ( ) ; case CallingConv :: Win64 : return true ;


<s> MachineBasicBlock * NextB = ( NextBI != MFN -> end ( ) ) ? & * NextBI : nullptr ; MachineBasicBlock * T1B = T1I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock :: const_iterator T2I = std :: next ( T1I ) ; assert ( T2I == B -> end ( ) || T2I -> getOpcode ( ) == <STR_LIT> ) ; MachineBasicBlock * T2B = ( T2I == B -> end ( ) ) ? NextB : T2I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( T1B == T2B ) { return false ; } if ( MLI -> getLoopFor ( T1B ) != L || MLI -> getLoopFor ( T2B ) != L ) return false ; if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> ) && ( TNS == <NUM_LIT> ) ; bool FOk = ( FNP == <NUM_LIT> ) && ( FNS == <NUM_LIT> ) ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) { JB = FB ; FB = nullptr ; }


<s> if ( FPVT == <STR_LIT> && ! Subtarget -> hasFullFP16 ( ) ) return false ; return TargetLowering :: shouldConvertFpToSat ( Op , FPVT , VT ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> if ( regno < <NUM_LIT> ) return <NUM_LIT> ; if ( TEST_HARD_REG_CLASS ( rclass , regno ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> getTargetStreamer ( ) -> emitIndirectFunctionType ( getSymbol ( & F ) , Params , Results ) ; } } for ( const auto & G : M . globals ( ) ) { if ( ! G . hasInitializer ( ) && G . hasExternalLinkage ( ) ) { if ( G . getValueType ( ) -> isSized ( ) ) {

uint16_t Size = M . getDataLayout ( ) . getTypeAllocSize ( G . getValueType ( ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitXOR ( const SDNode * N ) { return IREmitter :: visitXOR ( N ) ;


if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) {


<s> MVT ArgVT = ArgIdx . value ( ) . VT ; if ( ArgVT . isVector ( ) && ArgVT . getVectorElementType ( ) == <STR_LIT> ) return ArgIdx . index ( ) ; } return None ;


<s> df_insn_rescan ( slot [ <NUM_LIT> ] ) ; } if ( slot [ <NUM_LIT> ] == NULL_RTX ) { slot [ <NUM_LIT> ] = emit_insn_after ( gen_forced_nop ( ) , slot [ <NUM_LIT> ] ) ; df_insn_rescan ( slot [ <NUM_LIT> ] ) ; } if ( INSN_LOCATION ( slot [ <NUM_LIT> ] ) && INSN_LOCATION ( slot [ <NUM_LIT> ] ) != INSN_LOCATION ( slot [ <NUM_LIT> ] ) ) INSN_LOCATION ( slot [ <NUM_LIT> ] ) = INSN_LOCATION ( slot [ <NUM_LIT> ] ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto * EHInfo = MF . getWasmEHFuncInfo ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > ExtractInstrs ; SmallVector < MachineInstr * , <NUM_LIT> > ToDelete ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) ToDelete . push_back ( & MI ) ; else ExtractInstrs . push_back ( & MI ) ; } } } bool Changed = ! ToDelete . empty ( ) || ! ExtractInstrs . empty ( ) ; for ( auto * MI : ToDelete ) MI -> eraseFromParent ( ) ; if ( ExtractInstrs . empty ( ) ) return Changed ; SmallSet < MachineBasicBlock * , <NUM_LIT> > TerminatePads ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isCall ( ) ) { const MachineOperand & CalleeOp = MI . getOperand ( <NUM_LIT> ) ;

if ( CalleeOp . isGlobal ( ) && CalleeOp . getGlobal ( ) -> getName ( ) == <STR_LIT> ) TerminatePads . insert ( getMatchingEHPad ( & MI ) ) ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( create<ISA_LIT>SetSpillBase ( ) , false ) ;


<s> bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; if ( ! IsOptNone ) addPass ( create<ISA_LIT>PostLegalizeCombiner ( IsOptNone ) ) ;


<s> Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; } if ( VA . isMemLoc ( ) ) { HasStackArgs = true ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } if ( HasStackArgs ) { SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( ; AI != AE ; AI ++ ) { CCValAssign & VA = ArgLocs [ AI ] ; SDValue Arg = OutVals [ AI ] ; assert ( VA . isMemLoc ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + <NUM_LIT> , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; } SDValue InFlag ; for ( auto Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ;


<s> yaml :: MachineFunctionInfo * GCNTargetMachine :: createDefaultFuncInfoYAML ( ) const { return new yaml :: <ISA_LIT>MachineFunctionInfo ( ) ;


<s> CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ;


<s> fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( mode ) , GET_RTX_NAME ( outer_code ) , opno , * total , speed ? <STR_LIT> : <STR_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; } if ( ! ExtraOp ) return DAG . getNode ( Opc , SDLoc ( Op ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( Opc , SDLoc ( Op ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;