<s> PreBuilder . SetInsertPoint ( TileDP ) ; Value * NDWord = PreBuilder . CreateLShr ( N , PreBuilder . getInt16 ( <NUM_LIT> ) ) ; Value * KDWord = PreBuilder . CreateLShr ( K , PreBuilder . getInt16 ( <NUM_LIT> ) ) ; BasicBlock * Start = InsertI -> getParent ( ) ; BasicBlock * End = SplitBlock ( InsertI -> getParent ( ) , InsertI , & DTU , LI , nullptr , <STR_LIT> ) ; IRBuilder < > Builder ( TileDP ) ; Value * ResVec = createTileDPLoops < IntrID > ( Start , End , Builder , M , NDWord , KDWord , C , A , B ) ; Builder . SetInsertPoint ( End -> getFirstNonPHI ( ) ) ; Value * ResAMX = Builder . CreateBitCast ( ResVec , Type :: get<ISA_LIT>_AMXTy ( Builder . getContext ( ) ) ) ; for ( auto UI = TileDP -> use_begin ( ) , UE = TileDP -> use_end ( ) ; UI != UE ; ) { Instruction * I = cast < Instruction > ( ( UI ++ ) -> getUser ( ) ) ; Value * Vec ; if ( match ( I , m_BitCast ( m_Value ( Vec ) ) ) ) { I -> replaceAllUsesWith ( ResVec ) ; I -> eraseFromParent ( ) ; } } TileDP -> replaceAllUsesWith ( ResAMX ) ; TileDP -> eraseFromParent ( ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>FrameOffsetCannotUpdate ; } unsigned Scale , Width ; int64_t MinOff , MaxOff ; if ( ! <ISA_LIT>InstrInfo :: getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; const MachineOperand & ImmOpnd = MI . getOperand ( <ISA_LIT>InstrInfo :: getLoadStoreImmIdx ( MI . getOpcode ( ) ) ) ; Offset += ImmOpnd . getImm ( ) * Scale ; Optional < unsigned > UnscaledOp = <ISA_LIT>InstrInfo :: getUnscaledLdSt ( MI . getOpcode ( ) ) ; bool useUnscaledOp = UnscaledOp && ( Offset % Scale || Offset < <NUM_LIT> ) ; if ( useUnscaledOp && ! <ISA_LIT>InstrInfo :: getMemOpInfo ( * UnscaledOp , Scale , Width , MinOff , MaxOff ) ) llvm_unreachable ( <STR_LIT> ) ; int64_t Remainder = Offset % Scale ;

assert ( ! ( Remainder && useUnscaledOp ) && <STR_LIT> ) ;


<s> auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; unsigned BP = <NUM_LIT> ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) ; int RealOffset = Offset + MI . getOperand ( FIOp + <NUM_LIT> ) . getImm ( ) ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( HII . isValidOffset ( Opc , RealOffset ) ) { MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( RealOffset ) ; return ; } const Function * F = MF . getFunction ( ) ; dbgs ( ) << <STR_LIT> ; if ( F ) dbgs ( ) << F -> getName ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> << MB . getNumber ( ) << <STR_LIT> << MI ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const {

return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> if ( ( isLD_TNSR ( SU1 ) && isLD_TNSR ( SU2 ) ) || ( isLD_TNSR ( SU1 ) && isST_TNSR ( SU2 ) ) || ( isLD_TNSR ( SU2 ) && isST_TNSR ( SU1 ) ) ) { return true ;


<s> OS << <STR_LIT> << <STR_LIT> ( FPU ) << <STR_LIT> ;


c = ( __vector unsigned short ) vec_perm ( w0 , w1 , xform1 ) ;


<s> MI = II -> getIterator ( ) ; } if ( ! ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) ) continue ; if ( const auto & MOI = MOA . getLoadInfo ( MI ) ) Changed |= expandLoad ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getStoreInfo ( MI ) ) Changed |= expandStore ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicFenceInfo ( MI ) ) Changed |= expandAtomicFence ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicCmpxchgOrRmwInfo ( MI ) ) Changed |= expandAtomicCmpxchgOrRmw ( MOI . getValue ( ) , MI ) ;


<s> unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; if ( NumElts % Factor == <NUM_LIT> && ( SubVecSize == <NUM_LIT> || SubVecSize % <NUM_LIT> == <NUM_LIT> ) ) return Factor * ( ( SubVecSize + <NUM_LIT> ) / <NUM_LIT> ) ; }

return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) {

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> SDValue helperANDvipNodeCreate ( const SDValue & SDNodeArg , SDLoc & DL , SelectionDAG & DAG , unsigned opType , unsigned mask , EVT ResultVT ) { SmallVector < SDValue , <NUM_LIT> > Ops ( <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = SDNodeArg ; Ops [ <NUM_LIT> ] = DAG . getTargetConstant ( mask , DL , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getTargetConstant ( opType , DL , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getUNDEF ( ResultVT ) ; Ops [ <NUM_LIT> ] = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;


<s> for ( i = GET_RTX_LENGTH ( code ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'e' && reg_used_in_mem_p ( regno , XEXP ( x , i ) ) ) return true ;

else if ( fmt [ i ] == 'E' ) for ( j = <NUM_LIT> ; j < XVECLEN ( x , i ) ; j ++ ) if ( reg_used_in_mem_p ( regno , XVECEXP ( x , i , j ) ) ) return true ;


<s> bool isO32 ( ) const { return STI . getFeatureBits ( ) & <STR_LIT> ;


<s> } if ( RtReg == <STR_LIT> || RtReg == <STR_LIT> ) { Warning ( IDLoc , <STR_LIT> ) ; if ( Signed ) { if ( UseTraps ) { emitRRI ( <STR_LIT> , RtReg , ZeroReg , <NUM_LIT> , IDLoc , Instructions ) ; return false ; } emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , Instructions ) ; return false ; } } unsigned BranchTargetNoTraps ; unsigned BranchTarget ; if ( UseTraps ) { BranchTarget = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; emitRRI ( <STR_LIT> , RtReg , ZeroReg , <NUM_LIT> , IDLoc , Instructions ) ; } else { BranchTarget = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; BranchTargetNoTraps = <NUM_LIT> ; emitRRI ( <STR_LIT> , RtReg , ZeroReg , BranchTargetNoTraps , IDLoc , Instructions ) ; } emitRR ( DivOp , RsReg , RtReg , IDLoc , Instructions ) ; if ( ! UseTraps ) emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , Instructions ) ; if ( ! Signed ) { emitR ( <STR_LIT> , RsReg , IDLoc , Instructions ) ; return false ; } unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; emitRRI ( <STR_LIT> , ATReg , ZeroReg , - <NUM_LIT> , IDLoc , Instructions ) ;


<s> assert ( CI . InstClass == Paired . InstClass ) ;

if ( ( CI . InstClass == FLAT_LOAD || CI . InstClass == FLAT_STORE ) && <ISA_LIT>InstrInfo :: isFLATGlobal ( * CI . I ) && <ISA_LIT>InstrInfo :: isFLATGlobal ( * Paired . I ) ) return ( CI . InstClass == FLAT_STORE ) ? GLOBAL_STORE : GLOBAL_LOAD ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : noImmForm = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) Offset += MFI -> getStackSize ( ) ; if ( OpC == <STR_LIT> || ( ! noImmForm && isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned SReg = MF . getRegInfo ( ) . createVirtualRegister ( is64Bit ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addReg ( SReg , RegState :: Kill ) . addImm ( Offset ) ; unsigned OperandBase ; if ( noImmForm ) OperandBase = <NUM_LIT> ; else if ( OpC != TargetOpcode :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ; MI . setDesc ( TII . get ( NewOpcode ) ) ; OperandBase = <NUM_LIT> ; } else { OperandBase = OffsetOperandNo ;


<s> for ( auto Ptr : Switches ) if ( Ptr != SwPtr && Ptr -> fitsTargetFeatures ( Features ) ) if ( Ptr -> Value == SwPtr -> Value && meetsDependencies ( SwSet , Ptr , Switches ) ) { DISASM_DEBUG ( dbgs ( ) << <STR_LIT> << SwPtr -> Name << <STR_LIT> << Ptr -> Name << '\n' ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectIndexedLoadZeroExtend64 ( LoadSDNode * LD , unsigned Opcode , SDLoc dl ) { SDValue Chain = LD -> getChain ( ) ; EVT LoadedVT = LD -> getMemoryVT ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Offset = LD -> getOffset ( ) ; SDNode * OffsetNode = Offset . getNode ( ) ; int32_t Val = cast < ConstantSDNode > ( OffsetNode ) -> getSExtValue ( ) ; if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) { SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , <STR_LIT> , Base , TargetConstVal , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , TargetConst0 , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ;

const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ;


<s> } else { MachineInstrBuilder InvertedMI ; int InvertedOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; case <STR_LIT> : InvertedOpcode = <STR_LIT> ; break ; } InvertedMI = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( InvertedOpcode ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { InvertedMI . addOperand ( MI -> getOperand ( i ) ) ; if ( MI -> getOperand ( i ) . isMBB ( ) ) CondBrMBBOperand = i ; } MI -> eraseFromParent ( ) ; MI = Br . MI = InvertedMI ; } MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . OffsetBits ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; MachineBasicBlock * DestBB = MI -> getOperand ( CondBrMBBOperand ) . getMBB ( ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( CondBrMBBOperand ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock :: iterator MBBI = MI ; ++ MBBI ; splitBlockBeforeInstr ( MBBI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( MBB ) ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << MI -> getOperand ( CondBrMBBOperand ) . getMBB ( ) -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ;


<s> MachineInstr * Def = MRI . getUniqueVRegDef ( CFMask ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock :: iterator InsPt = Def && Def -> getParent ( ) == & MBB ? std :: next ( MachineBasicBlock :: iterator ( Def ) ) : MBB . begin ( ) ; MachineInstr * NewMI = BuildMI ( MBB , InsPt , DL , TII -> get ( OrOpc ) , Exec ) . addReg ( Exec ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; LoweredEndCf . insert ( NewMI ) ; MachineInstr * CleanUpMI = nullptr ; if ( NeedsKillCleanup . count ( & MI ) ) CleanUpMI = BuildMI ( MBB , InsPt , DL , TII -> get ( <STR_LIT> ) ) ; if ( LIS ) {

LIS -> ReplaceMachineInstrInMaps ( MI , * NewMI ) ;


<s> if ( this -> <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT> ;


<s> StringRef getPassName ( ) const override { return <ISA_LIT>_CLEANUP_VSETVLI_NAME ;


<s> assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; } } unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; } unsigned RetOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( RetOpc ) ) ; AddOptionalDefs ( MIB ) ; for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RetRegs [ i ] , RegState :: Implicit ) ;


<s> insertDAGNode ( DAG , N , NewX ) ; X = NewX ; } SDValue NewMask = DAG . getConstant ( Mask >> ShiftAmt , DL , VT ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , X , NewMask ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; insertDAGNode ( DAG , N , NewMask ) ; insertDAGNode ( DAG , N , NewAnd ) ; insertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith ( N , NewShift ) ; DAG . RemoveDeadNode ( N . getNode ( ) ) ;


<s> asm volatile ( <STR_LIT> : <STR_LIT> ( eax ) , <STR_LIT> ( ebx ) , <STR_LIT> ( ecx ) , <STR_LIT> ( edx ) : <STR_LIT> ( <NUM_LIT> ) ) ; if ( eax == <NUM_LIT> ) return ; asm volatile ( <STR_LIT> : <STR_LIT> ( eax ) , <STR_LIT> ( ebx ) , <STR_LIT> ( ecx ) , <STR_LIT> ( edx ) : <STR_LIT> ( <NUM_LIT> ) ) ; if ( edx & SSE ) { unsigned int mxcsr = __builtin_ia32_stmxcsr ( ) ; mxcsr |= MXCSR_FTZ ;


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , I . getReg ( ) ) ;


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; EVT ValVT = VA . getValVT ( ) ; SDValue Val ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ;

Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ;


<s> const MachineInstr * MI = MRI . getUniqueVRegDef ( Reg ) ;


<s> else { HOST_WIDE_INT rounded_size ; rtx r3 = MIPS_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = MIPS_PROLOGUE_TEMP2 ( Pmode ) ; gcc_assert ( first <= <NUM_LIT> ) ; rounded_size = size & - PROBE_INTERVAL ; emit_insn ( gen_rtx_SET ( VOIDmode , r3 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ) ; if ( rounded_size > <NUM_LIT> ) { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , r12 , gen_rtx_MINUS ( Pmode , r3 , r12 ) ) ) ;


<s> Value * <ISA_LIT>AtomicOptimizer :: buildScan ( IRBuilder < > & B , AtomicRMWInst :: BinOp Op , Value * V , Value * const Identity ) const { Type * const Ty = V -> getType ( ) ; Module * M = B . GetInsertBlock ( ) -> getModule ( ) ; Function * UpdateDPP = <STR_LIT> ( M , <STR_LIT> , Ty ) ; Function * PermLaneX16 = <STR_LIT> ( M , <STR_LIT> , { } ) ; Function * ReadLane = <STR_LIT> ( M , <STR_LIT> , { } ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; Idx ++ ) { V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: ROW_SHR0 | <NUM_LIT> << Idx ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; } if ( ST -> hasDPPBroadcasts ( ) ) { V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: BCAST15 ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: BCAST31 ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; } else { Value * const PermX = B . CreateCall ( PermLaneX16 , { V , V , B . getInt32 ( - <NUM_LIT> ) , B . getInt32 ( - <NUM_LIT> ) , B . getFalse ( ) , B . getFalse ( ) } ) ; V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , PermX , B . getInt32 ( DPP :: QUAD_PERM_ID ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; if ( ! ST -> isWave32 ( ) ) { Value * const Lane31 = B . CreateCall ( ReadLane , { V , B . getInt32 ( <NUM_LIT> ) } ) ;

V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , Lane31 , B . getInt32 ( DPP :: QUAD_PERM_ID ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ;


<s> } auto E = BB -> end ( ) ; for ( auto I = std :: next ( DefI -> getIterator ( ) ) ; I != E ; ++ I ) { Uses . erase ( & * I ) ; if ( Uses . empty ( ) || I -> modifiesRegister ( <STR_LIT> , TRI ) ) break ; } return Uses . empty ( ) ;


<s> return ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) ;


<s> int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return false ; int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand * Src0 = getImmOrMaterializedImm ( MRI , MI -> getOperand ( Src0Idx ) ) ; MachineOperand * Src1 = getImmOrMaterializedImm ( MRI , MI -> getOperand ( Src1Idx ) ) ; if ( ! Src0 -> isImm ( ) && ! Src1 -> isImm ( ) ) return false ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( Src0 -> isImm ( ) && Src0 -> getImm ( ) == <NUM_LIT> ) { bool UseCopy = TII -> getNamedOperand ( * MI , <STR_LIT> :: src2 ) -> isReg ( ) ; MI -> RemoveOperand ( Src1Idx ) ; MI -> RemoveOperand ( Src0Idx ) ; MI -> setDesc ( TII -> get ( UseCopy ? <STR_LIT> : <STR_LIT> ) ) ; return true ; } } if ( Src0 -> isImm ( ) && Src1 -> isImm ( ) ) { int32_t NewImm ; if ( ! evalBinaryInstruction ( Opc , NewImm , Src0 -> getImm ( ) , Src1 -> getImm ( ) ) ) return false ; const <ISA_LIT>RegisterInfo & TRI = TII -> getRegisterInfo ( ) ; bool IsSGPR = TRI . isSGPRReg ( MRI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI -> getOperand ( Src0Idx ) . ChangeToImmediate ( NewImm ) ; MI -> RemoveOperand ( Src1Idx ) ; mutateCopyOp ( * MI , TII -> get ( getMovOpc ( IsSGPR ) ) ) ; return true ; } if ( ! MI -> isCommutable ( ) ) return false ; if ( Src0 -> isImm ( ) && ! Src1 -> isImm ( ) ) {


<s> return get<ISA_LIT>ArchVersion ( ) >= <STR_LIT> :: V55 ;


<s> void StackVreg :: print ( const Stack & S ) const { S . printElement ( dbgs ( ) , * this ) ;


<s> Value = ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ;


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { unsigned Opcode = getSGPRSpillRestoreOpcode ( RC -> getSize ( ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && RC -> getSize ( ) == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) ; return ; }

if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) {


<s> static rtx mips_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) {

return mips_function_value_1 ( valtype , fn_decl_or_type , VOIDmode ) ;


<s> unsigned <ISA_LIT>FastISel :: getRegForPromotedValue ( const Value * V , bool IsSigned ) {

return IsSigned ? getRegForSignedValue ( V ) : getRegForUnsignedValue ( V ) ;


<s> static TargetLowering :: ArgListTy getDivRemArgList ( const SDNode * N , LLVMContext * Context , const <ISA_LIT>Subtarget * Subtarget ) { assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = N -> getOperand ( i ) . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * Context ) ; Entry . Node = N -> getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } if ( Subtarget -> isTargetWindows ( ) && Args . size ( ) >= <NUM_LIT> ) std :: swap ( Args [ <NUM_LIT> ] , Args [ <NUM_LIT> ] ) ;


<s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ;

emitDemotedVars ( & MF -> getFunction ( ) , O ) ;


<s> const LLT s1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_UADDE ) . lowerFor ( { { s32 , s1 } } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForCartesianProduct ( { p0 , s32 } , { p0 } ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 } ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ;

getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ;


<s> UP . Partial = UP . Runtime = true ; }

TargetTransformInfo :: getUnrollingPreferences ( F , L , UP ) ;


<s> static bool HasNestArgument ( const MachineFunction * MF ) {

const Function * F = MF -> getFunction ( ) ;


<s> static inline vec_int4 vec_adds ( vec_int4 a , vec_bint4 b ) { return ( vec_adds ( a , ( vec_int4 ) ( b ) ) ) ;


<s> static SDValue getVShift ( bool isLeft , EVT VT , SDValue SrcOp , unsigned NumBits , SelectionDAG & DAG , const TargetLowering & TLI , DebugLoc dl ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; EVT ShVT = <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ;

SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ;


<s> if ( ! Val ) return true ; auto & MF = MIRBuilder . getMF ( ) ; const auto & F = * MF . getFunction ( ) ; auto DL = MF . getDataLayout ( ) ; auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeSet :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , DL , MF . getRegInfo ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret , AssignFn ) ; return handleAssignments ( MIRBuilder , SplitVTs , RetHandler ) ;


<s> __vector signed int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return ( __m128i ) vec_vmsumshm ( ( __v8hi ) __A , ( __v8hi ) __B , zero ) ;


<s> Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; } if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res ) ; SDValue LowX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LowX , Res ) ;


<s> SDValue Offset = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result , Offset ) ;


<s> if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) && hasUndefRegUpdate ( MI . getOpcode ( ) , OpNum ) ) return UndefRegClearance ; return <NUM_LIT> ;


<s> void arm_poke_function_name ( FILE * stream , const char * name ) { unsigned long alignlength ; unsigned long length ; rtx x ; length = strlen ( name ) + <NUM_LIT> ; alignlength = ROUND_UP_WORD ( length ) ; ASM_OUTPUT_ASCII ( stream , name , length ) ; ASM_OUTPUT_ALIGN ( stream , <NUM_LIT> ) ; x = GEN_INT ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> + alignlength ) ; assemble_aligned_integer ( UNITS_PER_WORD , x ) ;


<s> emitRRI ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> , IDLoc , STI ) ;


<s> int out_args_size ; int save_reg_size ; int callee_save_reg_size ; if ( cfun -> machine -> initialized ) return cfun -> machine -> total_size ; save_reg_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno <= LAST_GP_REG ; regno ++ ) if ( prologue_saved_reg_p ( regno ) ) { save_mask |= <NUM_LIT> << regno ; save_reg_size += <NUM_LIT> ; } if ( TARGET_HAS_CDX && save_reg_size != <NUM_LIT> ) { if ( ( save_mask & ( <NUM_LIT> << RA_REGNO ) ) == <NUM_LIT> ) { save_mask |= <NUM_LIT> << RA_REGNO ; save_reg_size += <NUM_LIT> ; } for ( regno = <NUM_LIT> ; regno >= <NUM_LIT> ; regno -- ) if ( ( save_mask & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ) { unsigned int i ; for ( i = regno - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( ( save_mask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) {


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; if ( isSeveralBitsExtractOpFromShr ( N , Opc , Opd0 , Immr , Imms ) ) return true ; uint64_t ShlImm = <NUM_LIT> ; uint64_t TruncBits = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , ShlImm ) ) { Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else if ( VT == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; TruncBits = Opd0 -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) - VT . getSizeInBits ( ) ; VT = Opd0 . getValueType ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ; } else return false ; if ( ShlImm >= VT . getSizeInBits ( ) ) { DEBUG ( ( dbgs ( ) << N << <STR_LIT> ) ) ;


<s> if ( ! <STR_LIT> ( N . getNode ( ) ) || ! IsProfitableToFold ( N , P , P ) || ! IsLegalToFold ( N , P , P , OptLevel ) ) return false ;

return selectAddr ( N . getNode ( ) , N . getOperand ( <NUM_LIT> ) , Base , Scale , Index , Disp , Segment ) ;


<s> void get_aligned_mem ( rtx ref , rtx * paligned_mem , rtx * pbitnum ) { rtx base ; HOST_WIDE_INT disp , offset ; gcc_assert ( GET_CODE ( ref ) == MEM ) ; if ( reload_in_progress && ! memory_address_p ( GET_MODE ( ref ) , XEXP ( ref , <NUM_LIT> ) ) ) { base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; gcc_assert ( memory_address_p ( GET_MODE ( ref ) , base ) ) ; } else base = XEXP ( ref , <NUM_LIT> ) ; if ( GET_CODE ( base ) == PLUS ) disp = INTVAL ( XEXP ( base , <NUM_LIT> ) ) , base = XEXP ( base , <NUM_LIT> ) ; else disp = <NUM_LIT> ; if ( MEM_ALIGN ( ref ) >= <NUM_LIT> ) offset = <NUM_LIT> ; else offset = disp & <NUM_LIT> ;

* paligned_mem = widen_memory_access ( ref , SImode , - offset ) ;


<s> auto firstInst = MF -> getBlockNumbered ( <NUM_LIT> ) -> instr_begin ( ) ; MachineInstr * cacheIns = MF -> CreateMachineInstr ( TII -> get ( <STR_LIT> ) , firstInst -> getDebugLoc ( ) , true ) ; cacheIns -> addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; cacheIns -> addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; cacheIns -> addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MachineBasicBlock * MBB = firstInst -> getParent ( ) ; MBB -> insert ( firstInst , cacheIns ) ; return true ; } return false ;


<s> delete static_cast < <ISA_LIT>Section * > ( DwarfFrameSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfPubTypesSection ) ; delete static_cast < const <ISA_LIT>Section * > ( DwarfDebugInlineSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfStrSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfLocSection ) ;

delete static_cast < <ISA_LIT>Section * > ( DwarfARangesSection ) ;


<s> return __builtin_mve_vrshlq_uv16qi ( __a , __b ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>StoreResults ( ) { return new <ISA_LIT>StoreResults ( ) ;


<s> return ELF :: R_<ISA_LIT>_REFLONG ; case FK_PCRel_8 : return ELF :: R_<ISA_LIT>_REFQUAD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PC_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PC_LO32 ; } } switch ( Fixup . getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_2 : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_REFLONG ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_REFQUAD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_REFLONG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO32 ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_LO32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOTOFF_HI32 ;


<s> SDValue Op0 = DAG . getBitcast ( IntVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getBitcast ( IntVT , N -> getOperand ( <NUM_LIT> ) ) ; unsigned IntOpcode ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ;


<s> <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; fastEmitBranch ( Target , DbgLoc ) ; return true ; } return false ;


<s> if ( ! Subtarget . prefers32BitThumb ( ) ) PM . add ( createThumb2SizeReductionPass ( ) ) ; PM . add ( createUnpackMachineBundlesPass ( ) ) ;


<s> static CodeModel :: Model getEffectiveCodeModel ( Optional < CodeModel :: Model > CM , Reloc :: Model RM , bool JIT ) {


<s> bool isVCSrcB32 ( ) const { return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> struct __htm_tdb * tdb = ( struct __htm_tdb * ) tdb_ptr ;


<s> emit_insn ( gen_addsi3 ( this_rtx , this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; rtx temp2 = gen_rtx_REG ( Pmode , MB_ABI_TEMP2_REGNUM ) ; if ( flag_pic ) emit_move_insn ( temp2 , expand_pic_symbol_ref ( Pmode , funexp ) ) ; else emit_move_insn ( temp2 , funexp ) ; emit_insn ( gen_indirect_jump ( temp2 ) ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ;

final_start_function ( insn , file , <NUM_LIT> ) ;


<s> } if ( ! INSN_P ( insn ) ) continue ; if ( CALL_P ( insn ) ) ++ call_count ; else if ( insn == prologue_matched ) ; else { df_ref use ; FOR_EACH_INSN_USE ( use , insn ) { if ( ! call_used_regs [ DF_REF_REGNO ( use ) ] ) {

if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , INSN_UID ( insn ) ) ;


<s> MVT getVectorIdxTy ( const DataLayout & DL ) const override {


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateSysCR ( unsigned Val , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_SysCR , Ctx ) ; Op -> SysCRImm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> } if ( Tok . getString ( ) . find ( '.' ) != StringRef :: npos ) { const MCExpr * NewDisp ; if ( ParseIntelDotOperator ( Disp , NewDisp ) ) return nullptr ; End = Tok . getEndLoc ( ) ; Parser . Lex ( ) ; Disp = NewDisp ; } int BaseReg = SM . getBaseReg ( ) ; int IndexReg = SM . getIndexReg ( ) ; int Scale = SM . getScale ( ) ; if ( ! isParsingInlineAsm ( ) ) { if ( ! BaseReg && ! IndexReg ) { if ( ! SegReg ) return <STR_LIT> ( getPointerWidth ( ) , Disp , Start , End , Size ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size ) ; }


<s> RegionFragment * getExIdxFragment ( ) const {


<s> KMaskOp = <NUM_LIT> ; if ( <STR_LIT> ( TSFlags ) ) FirstCommutableVecOp = <NUM_LIT> ; LastCommutableVecOp ++ ; } else if ( IsIntrinsic ) { FirstCommutableVecOp = <NUM_LIT> ; } if ( isMem ( MI , LastCommutableVecOp ) ) LastCommutableVecOp -- ; if ( SrcOpIdx1 != CommuteAnyOperandIndex && ( SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp || SrcOpIdx1 == KMaskOp ) ) return false ; if ( SrcOpIdx2 != CommuteAnyOperandIndex && ( SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp || SrcOpIdx2 == KMaskOp ) ) return false ; if ( SrcOpIdx1 == CommuteAnyOperandIndex || SrcOpIdx2 == CommuteAnyOperandIndex ) { unsigned CommutableOpIdx2 = SrcOpIdx2 ; if ( SrcOpIdx1 == SrcOpIdx2 ) CommutableOpIdx2 = LastCommutableVecOp ;

else if ( SrcOpIdx2 == CommuteAnyOperandIndex ) CommutableOpIdx2 = SrcOpIdx1 ;


<s> inline static AluCode stringTo<ISA_LIT>AluCode ( StringRef S ) { return StringSwitch < AluCode > ( S ) . Case ( <STR_LIT> , ADD ) . Case ( <STR_LIT> , ADDC ) . Case ( <STR_LIT> , SUB ) . Case ( <STR_LIT> , SUBB ) . Case ( <STR_LIT> , AND ) . Case ( <STR_LIT> , OR ) . Case ( <STR_LIT> , XOR ) . Case ( <STR_LIT> , SHL ) . Case ( <STR_LIT> , SRL ) . Case ( <STR_LIT> , SRA ) . Default ( UNKNOWN ) ;


<s> if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) | ( <NUM_LIT> << IP_REGNUM ) | ( <NUM_LIT> << LR_REGNUM ) | ( <NUM_LIT> << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= <NUM_LIT> << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % <NUM_LIT> ) != <NUM_LIT> ) { for ( reg = <NUM_LIT> ; reg <= <NUM_LIT> ; reg ++ ) if ( ( save_reg_mask & ( <NUM_LIT> << reg ) ) == <NUM_LIT> ) break ; if ( reg <= <NUM_LIT> ) save_reg_mask |= ( <NUM_LIT> << reg ) ; else { cfun -> machine -> sibcall_blocked = <NUM_LIT> ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned ExtOff = isExt ; unsigned Vec0Off = ExtOff + <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + Vec0Off , N -> op_begin ( ) + Vec0Off + NumVecs ) ; SDValue RegSeq = createQTuple ( Regs ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( isExt ) Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( NumVecs + ExtOff + <NUM_LIT> ) ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( Opc , dl , VT , Ops ) ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = CTX . getRegisterInfo ( ) . getEncodingValue ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ; isAdd = false ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ;

if ( isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ;


<s> while ( true ) { if ( ! Parser . getTok ( ) . is ( AsmToken :: Colon ) ) return false ; Lex ( ) ; StringRef Option = Parser . getTok ( ) . getString ( ) ; if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ;

else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ;


<s> addPass ( & <ISA_LIT>LateBranchLoweringPassID ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & <ISA_LIT>PreEmitPeepholeID ) ;

addPass ( & PostRAHazardRecognizerID ) ;


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> :


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_monitor ( void const * __P , unsigned int __E , unsigned int __H ) { __builtin_ia32_monitor ( __P , __E , __H ) ;


<s> if ( align_labels . levels [ <NUM_LIT> ] . log < <NUM_LIT> ) { rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( INSN_P ( next ) && recog_memoized ( next ) >= <NUM_LIT> ) return <NUM_LIT> ; }

return align_labels . levels [ <NUM_LIT> ] . log ;


<s> if ( Shift . getOpcode ( ) != <STR_LIT> || ! Shift . hasOneUse ( ) || ! isa < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) ) return true ; unsigned ShiftAmt = Shift . getConstantOperandVal ( <NUM_LIT> ) ; unsigned MaskLZ = countLeadingZeros ( Mask ) ; unsigned MaskTZ = countTrailingZeros ( Mask ) ; unsigned AMShiftAmt = MaskTZ ; if ( AMShiftAmt == <NUM_LIT> || AMShiftAmt > <NUM_LIT> ) return true ; if ( countTrailingOnes ( Mask >> MaskTZ ) + MaskTZ + MaskLZ != <NUM_LIT> ) return true ; unsigned ScaleDown = ( <NUM_LIT> - X . getSimpleValueType ( ) . getSizeInBits ( ) ) + ShiftAmt ; if ( MaskLZ < ScaleDown ) return true ; MaskLZ -= ScaleDown ; bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getSimpleValueType ( ) . getSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getSimpleValueType ( ) . getSizeInBits ( ) , MaskLZ ) ; KnownBits Known = DAG . computeKnownBits ( X ) ; if ( MaskedHighBits != Known . Zero ) return true ; MVT VT = N . getSimpleValueType ( ) ; if ( ReplacingAnyExtend ) {


<s> for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , getKillRegState ( isKill ) ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd ) ; NewMIs . push_back ( MIB ) ;


<s> Parser . Lex ( ) ; const MCExpr * Val ; InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelInlineAsmIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; void * Decl = nullptr ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_EnumVal ) ) return ErrorOperand ( Start , <STR_LIT> ) ; else if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) Decl = Info . Var . Decl ; InstInfo -> AsmRewrites -> emplace_back ( AOK_Skip , OffsetOfLoc , <NUM_LIT> ) ; bool Parse32 = is32BitMode ( ) || Code16GCC ;

unsigned RegNo = is64BitMode ( ) ? <STR_LIT> : ( Parse32 ? <STR_LIT> : <STR_LIT> ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine * TM = nullptr , CodeGenOpt :: Level OptLevel = CodeGenOpt :: Default ) : SelectionDAGISel ( * TM , OptLevel ) { EnableLateStructurizeCFG = <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ;


<s> static bool compare_sign_p ( rtx_insn * insn ) { RTX_CODE cond = compare_condition ( insn ) ; return ( cond == GE || cond == LT ) ;


<s> if ( isConsecutiveAccess ( MemOp0 , MemOp1 , DL , SE ) ) { VecMem . clear ( ) ; VecMem . push_back ( MemOp0 ) ; VecMem . push_back ( MemOp1 ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ;


<s> <ISA_LIT>ConstantIslands ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , ABI ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ) , STI ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , MF ( <NUM_LIT> ) , MCP ( <NUM_LIT> ) , PrescannedForConstants ( false ) {


<s> tree ap_field = TYPE_FIELDS ( TREE_TYPE ( valist ) ) ; valist = build3 ( COMPONENT_REF , TREE_TYPE ( ap_field ) , valist , ap_field , NULL_TREE ) ; } return valist ;


<s> } if ( Kind == TTI :: SK_Alternate ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ; if ( ST -> hasAVX2 ( ) && LT . second == <STR_LIT> ) return LT . first ; static const CostTblEntry < <STR_LIT> > AVXAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasAVX ( ) ) if ( const auto * Entry = CostTableLookup ( AVXAltShuffleTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost ; static const CostTblEntry < <STR_LIT> > SSE41AltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasSSE41 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE41AltShuffleTbl , <STR_LIT> , LT . second ) ) return LT . first * Entry -> Cost ; static const CostTblEntry < <STR_LIT> > SSSE3AltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> }


assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ;


<s> break ; case CONST : operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; break ; case PLUS : arg1 = XEXP ( addr , <NUM_LIT> ) ; arg2 = XEXP ( addr , <NUM_LIT> ) ; if ( CONSTANT_P ( arg1 ) ) base = arg2 , offset = arg1 ; else base = arg1 , offset = arg2 ; gcc_assert ( REG_P ( base ) ) ; if ( REG_P ( offset ) ) { int reg_offset = REGNO ( offset ) ; int reg_base = REGNO ( base ) ; int reg_dest = REGNO ( operands [ <NUM_LIT> ] ) ; asm_fprintf ( asm_out_file , <STR_LIT> , reg_dest + <NUM_LIT> , reg_base , reg_offset ) ; asm_fprintf ( asm_out_file , <STR_LIT> , reg_dest , reg_dest + <NUM_LIT> ) ; asm_fprintf ( asm_out_file , <STR_LIT> , reg_dest + <NUM_LIT> , reg_dest + <NUM_LIT> ) ; } else { operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; if ( REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( base ) ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ;


<s> GCNPassConfig ( LLVMTargetMachine & TM , PassManagerBase & PM ) : <ISA_LIT>PassConfig ( TM , PM ) {


<s> else report_fatal_error ( <STR_LIT> <STR_LIT> ) ; RetOps . insert ( RetOps . begin ( ) + <NUM_LIT> , DAG . getConstant ( LROffset , <STR_LIT> , false ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps ) ;


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const {


<s> Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; } assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; if ( DestReg ) MIB . addReg ( DestReg , RegState :: Define ) ; if ( SrcReg ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( ZeroReg ) MIB . addReg ( ZeroReg ) ;


<s> emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , FPOffset , TII , MachineInstr :: FrameSetup ) ; } if ( NumBytes ) { const bool NeedsRealignment = RegInfo -> needsStackRealignment ( MF ) ; unsigned scratchSPReg = <STR_LIT> ; if ( NeedsRealignment ) { scratchSPReg = findScratchNonCalleeSaveRegister ( & MBB ) ; assert ( scratchSPReg != <STR_LIT> ) ; } if ( ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , MBBI , DL , scratchSPReg , <STR_LIT> , - NumBytes , TII , MachineInstr :: FrameSetup ) ; if ( NeedsRealignment ) { const unsigned Alignment = MFI . getMaxAlignment ( ) ; const unsigned NrBitsToZero = countTrailingZeros ( Alignment ) ; assert ( NrBitsToZero > <NUM_LIT> ) ; assert ( scratchSPReg != <STR_LIT> ) ; uint32_t andMaskEncoded = ( <NUM_LIT> << <NUM_LIT> ) | ( ( <NUM_LIT> - NrBitsToZero ) << <NUM_LIT> ) | ( ( <NUM_LIT> - NrBitsToZero - <NUM_LIT> ) << <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( scratchSPReg , RegState :: Kill ) . addImm ( andMaskEncoded ) ; AFI -> setStackRealigned ( true ) ; } } if ( RegInfo -> hasBasePointer ( MF ) ) { TII -> copyPhysReg ( MBB , MBBI , DL , RegInfo -> getBaseRegister ( ) , <STR_LIT> , false ) ; } if ( needsFrameMoves ) { const DataLayout & TD = MF . getDataLayout ( ) ; const int StackGrowth = - TD . getPointerSize ( <NUM_LIT> ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( HasFP ) {

unsigned Reg = RegInfo -> getDwarfRegNum ( FramePtr , true ) ;


<s> static tree alpha_fold_builtin_extxx ( tree op [ ] , unsigned HOST_WIDE_INT opint [ ] , long op_const , unsigned HOST_WIDE_INT bytemask , bool is_high ) { long zap_const = <NUM_LIT> ; tree * zap_op = NULL ; if ( op_const & <NUM_LIT> ) { unsigned HOST_WIDE_INT loc ; loc = opint [ <NUM_LIT> ] & <NUM_LIT> ; loc *= BITS_PER_UNIT ; if ( loc != <NUM_LIT> ) {


<s> return true ; } if ( ! register_operand ( dest , mode ) && ! register_operand ( src , mode ) && ! const_0_operand ( src , mode ) ) { loongarch_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { loongarch_legitimize_const_move ( mode , dest , src ) ;

set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ;


<s> return __arm_vld1q_z_f32 ( __base , __p ) ;


<s> if ( N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( N -> getMaskElt ( i ) > <NUM_LIT> ) return false ; bool HasHi = false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Elt = N -> getMaskElt ( i ) ; if ( Elt >= <NUM_LIT> && Elt != <NUM_LIT> ) return false ; if ( Elt == <NUM_LIT> ) HasHi = true ;


<s> static void rs6000_emit_msub ( rtx target , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( target ) ; rtx dst ; if ( optab_handler ( fms_optab , mode ) != CODE_FOR_nothing ) dst = expand_ternary_op ( mode , fms_optab , m1 , m2 , a , target , <NUM_LIT> ) ; else {

a = expand_unop ( mode , neg_optab , a , NULL_RTX , <NUM_LIT> ) ;


<s> SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ;

SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ;


<s> unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < <NUM_LIT> ) continue ; if ( ConstCount > <NUM_LIT> && Cycle == <NUM_LIT> ) return false ; if ( ConstCount > <NUM_LIT> && Cycle == <NUM_LIT> ) return false ;


<s> SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT StVT = St -> getMemoryVT ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromEltSz = VT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ToEltSz = StVT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! isPowerOf2_32 ( NumElems * FromEltSz * ToEltSz ) ) return SDValue ( ) ; if ( <NUM_LIT> != ( NumElems * FromEltSz ) % ToEltSz ) return SDValue ( ) ; unsigned SizeRatio = FromEltSz / ToEltSz ; assert ( SizeRatio * NumElems * ToEltSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDLoc DL ( St ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = TLI . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec . data ( ) ) ; MVT StoreType = <STR_LIT> ; for ( MVT Tp : <STR_LIT> ( ) ) { if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ; assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , DL , TLI . getPointerTy ( ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) {

SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I , DL ) ) ;


<s> static DecodeStatus DecodeMemBarrierOption ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) { if ( Val & ~ <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler :: Success ;


<s> SmallVector < GlobalValue * , <NUM_LIT> > TmpVec ; collectUsedGlobalVariables ( M , TmpVec , true ) ; UsedList . insert ( TmpVec . begin ( ) , TmpVec . end ( ) ) ; TmpVec . clear ( ) ; collectUsedGlobalVariables ( M , TmpVec , false ) ; UsedList . insert ( TmpVec . begin ( ) , TmpVec . end ( ) ) ;


<s> if ( Src0 . isImm ( ) && TII -> isLiteralConstant ( Src0 , TII -> getOpSize ( MI , Src0Idx ) ) ) return ; if ( Src0 . isReg ( ) && ! isVGPR ( & Src0 , TRI , MRI ) ) return ; if ( Src0 . isReg ( ) && MRI . hasOneUse ( Src0 . getReg ( ) ) ) { unsigned Reg = Src0 . getReg ( ) ; MachineInstr * Def = MRI . getUniqueVRegDef ( Reg ) ; if ( Def && Def -> isMoveImmediate ( ) ) { MachineOperand & MovSrc = Def -> getOperand ( <NUM_LIT> ) ; bool ConstantFolded = false ; if ( MovSrc . isImm ( ) && isUInt < <NUM_LIT> > ( MovSrc . getImm ( ) ) ) { Src0 . ChangeToImmediate ( MovSrc . getImm ( ) ) ; ConstantFolded = true ; } if ( ConstantFolded ) { if ( MRI . use_empty ( Reg ) ) Def -> eraseFromParent ( ) ; ++ NumLiteralConstantsFolded ; return ; } } } if ( TryToCommute && MI . isCommutable ( ) && TII -> commuteInstruction ( MI ) ) foldImmediates ( MI , TII , MRI , false ) ;


<s> __arm_vuninitializedq_s64 ( void ) {


<s> GA = cast < GlobalAddressSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getGlobal ( ) ; Offset = cast < GlobalAddressSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getOffset ( ) ; return true ; } } return TargetLowering :: isGAPlusOffset ( N , GA , Offset ) ;


<s> BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; if ( SrcReg != <STR_LIT> ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = prior ( MBBI ) ; emitSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes ) ; } else emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ;


<s> Error ( Tok . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = StringSwitch < int > ( Tok . getString ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> ) { Error ( Tok . getLoc ( ) , <STR_LIT> ) ;


<s> int stackGrowth = - <NUM_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( llvm :: <STR_LIT> , true ) , - stackGrowth ) ; MAI -> addInitialFrameState ( Inst ) ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ;


<s> const AsmToken & RegTok = Parser . getTok ( ) ; int RegNo = tryParseRegister ( ) ; if ( RegNo == - <NUM_LIT> ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNo , RegTok . getLoc ( ) , RegTok . getEndLoc ( ) ) ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExclaimTok . getString ( ) , ExclaimTok . getLoc ( ) ) ) ; Parser . Lex ( ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return TokError ( <STR_LIT> ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateVectorIndex ( MCE -> getValue ( ) , SIdx , E , getContext ( ) ) ) ;


<s> virtual void emitARM64WinCFIClearUnwoundToCall ( ) {


<s> } if ( update_base_reg_p ) { offset = count * <NUM_LIT> ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; * update_base_reg = gen_reg_rtx ( SImode ) ; XVECEXP ( result , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( * update_base_reg , new_addr ) ; } for ( par_index = <NUM_LIT> ; par_index < count ; par_index ++ ) { offset = par_index * <NUM_LIT> ; new_addr = plus_constant ( Pmode , base_addr , offset ) ; mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ; XVECEXP ( result , <NUM_LIT> , par_index + start_idx ) = gen_rtx_SET ( mem , reg ) ; } return result ;


<s> void EmitALUClause ( MachineBasicBlock :: iterator InsertPos , ClauseFile & Clause , unsigned & CfCount ) { CounterPropagateAddr ( Clause . first , CfCount ) ; MachineBasicBlock * BB = Clause . first -> getParent ( ) ; BuildMI ( BB , InsertPos -> getDebugLoc ( ) , TII -> get ( AMDGPU :: ALU_CLAUSE ) ) . addImm ( CfCount ) ; for ( unsigned i = <NUM_LIT> , e = Clause . second . size ( ) ; i < e ; ++ i ) { BB -> splice ( InsertPos , BB , Clause . second [ i ] ) ; } CfCount += Clause . second . size ( ) ;


<s> FormalArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , CCAssignFn * AssignFn ) : IncomingValueHandler ( MIRBuilder , MRI , AssignFn ) {


<s> const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : Opc = HasAVX512 ? <STR_LIT> : HasSSE1 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = HasAVX512 ? <STR_LIT> : HasSSE2 ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ;


<s> explicit StackVreg ( unsigned VirtReg , const DILocalVariable * DbgVar = nullptr ) : VirtReg ( VirtReg ) , DbgVar ( DbgVar ) {


update_base = XVECEXP ( op , <NUM_LIT> , update_base_elt_idx ) ;


<s> Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( MI . isMoveReg ( ) || isORCopyInst ( MI ) ) { Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT> ) ; return true ; } return false ;


<s> switch ( Opc ) { default : return CSEConfigFull :: shouldCSEOpc ( Opc ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> SDValue HighShift = DAG . getConstant ( ( HighOffset - Offset ) * <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Low = DAG . getLoad ( getPointerTy ( ) , DL , Chain , LowAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue High = DAG . getLoad ( getPointerTy ( ) , DL , Chain , HighAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue LowShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low , LowShift ) ; SDValue HighShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High , HighShift ) ;

SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LowShifted , HighShifted ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << ( Cond ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << * TfrI ) ; MachineOperand & MD = TfrI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MP = TfrI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MS = TfrI -> getOperand ( <NUM_LIT> ) ; if ( ! MS . isKill ( ) ) return false ; if ( MD . getSubReg ( ) ) return false ; RegisterRef RT ( MS ) ; unsigned PredR = MP . getReg ( ) ; MachineInstr * DefI = getReachingDefForPred ( RT , TfrI , PredR , Cond ) ; if ( ! DefI || ! isPredicable ( DefI ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * DefI ) ; ReferenceMap Uses , Defs ; MachineBasicBlock :: iterator DefIt = DefI , TfrIt = TfrI ; bool PredValid = true ; for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { if ( ! I -> modifiesRegister ( PredR , <NUM_LIT> ) ) continue ; PredValid = false ; break ; } for ( MachineBasicBlock :: iterator I = std :: next ( DefIt ) ; I != TfrIt ; ++ I ) { MachineInstr * MI = & * I ; unsigned Exec = Exec_Then | Exec_Else ; if ( PredValid && HII -> isPredicated ( * MI ) && MI -> readsRegister ( PredR ) ) Exec = ( Cond == HII -> isPredicatedTrue ( * MI ) ) ? Exec_Then : Exec_Else ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ;

if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return false ;


<s> y = ( vec_uchar16 ) ( vec_sr ( ( vec_uint4 ) vec_sro ( ( vec_uchar16 ) ( a ) , ( ( vec_uchar16 ) ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) , ( vec_uint4 ) vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , x ) ) ) ;

result = vec_or ( vec_sll ( ( qword ) ( a ) , x ) , y ) ;


<s> attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ;

return lookup_attribute ( <STR_LIT> , attributes ) != NULL_TREE ;


<s> HOST_WIDE_INT locals_size = get_frame_size ( ) ; int regno ; HOST_WIDE_INT stack_space_to_deallocate = ( current_function_outgoing_args_size + current_function_pretend_args_size + locals_size + <NUM_LIT> ) & ~ <NUM_LIT> ; HOST_WIDE_INT offset = current_function_outgoing_args_size ; for ( regno = <NUM_LIT> ; regno >= MMIX_FIRST_GLOBAL_REGNUM ; regno -- ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) stack_space_to_deallocate += <NUM_LIT> ; if ( MMIX_CFUN_HAS_LANDING_PAD ) stack_space_to_deallocate += <NUM_LIT> ; else if ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ) stack_space_to_deallocate += <NUM_LIT> ; if ( frame_pointer_needed ) stack_space_to_deallocate += <NUM_LIT> ; if ( ( stack_space_to_deallocate % <NUM_LIT> ) != <NUM_LIT> ) internal_error ( <STR_LIT> , stack_space_to_deallocate ) ; for ( regno = MMIX_FIRST_GLOBAL_REGNUM ; regno <= <NUM_LIT> ; regno ++ ) if ( ( ( regno != MMIX_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) {


<s> bool isMachineVerifierClean ( ) const override { return false ;


<s> Value * <ISA_LIT>IREmitter :: visitVLD2_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> case VK_<ISA_LIT>_LO12 : return <STR_LIT> ; case VK_<ISA_LIT>_HI20 : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL_LO12 : return <STR_LIT> ;

case VK_<ISA_LIT>_PCREL_HI20 : return <STR_LIT> ;


<s> BuildMI ( MBB , MBB . end ( ) , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; NumInserted ++ ; } if ( Cond . empty ( ) || FBB ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( <STR_LIT> ) ) . addMBB ( Cond . empty ( ) ? TBB : FBB ) ; NumInserted ++ ;


<s> int <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) { assert ( Tp -> isVectorTy ( ) ) ; assert ( ST -> hasVector ( ) && <STR_LIT> ) ; unsigned NumVectors = getNumVectorRegs ( Tp ) ; if ( Tp -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Kind == TargetTransformInfo :: SK_Broadcast ? NumVectors - <NUM_LIT> : <NUM_LIT> ) ; switch ( Kind ) { case TargetTransformInfo :: SK_ExtractSubvector : return ( Index == <NUM_LIT> ? <NUM_LIT> : NumVectors ) ; case TargetTransformInfo :: SK_Broadcast : return NumVectors - <NUM_LIT> ;


<s> const MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FI = cast < FrameIndexSDNode > ( Loc ) -> getIndex ( ) ; int BFI = cast < FrameIndexSDNode > ( BaseLoc ) -> getIndex ( ) ; int FS = MFI -> getObjectSize ( FI ) ; int BFS = MFI -> getObjectSize ( BFI ) ; if ( FS != BFS || FS != ( int ) Bytes ) return false ; return MFI -> getObjectOffset ( FI ) == ( MFI -> getObjectOffset ( BFI ) + Dist * Bytes ) ; } if ( DAG . isBaseWithConstantOffset ( Loc ) && Loc . getOperand ( <NUM_LIT> ) == BaseLoc && cast < ConstantSDNode > ( Loc . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) == Dist * Bytes ) return true ;

const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


<s> const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI -> canReserveReg ( BasePtr ) ; return true ;


<s> } else { const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getTarget ( ) . getRegisterInfo ( ) ; const unsigned * SubSet = TRI -> getSubRegisters ( DestReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SubSet [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SubSet [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ;


<s> static SDValue lowerV16F32VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue UnpckNode = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ; if ( UnpckNode ) return UnpckNode ;

return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> static int c4x_leaf_function_p ( ) {

if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ) ) return <NUM_LIT> ;


<s> if ( AM . BaseOffs <= - ( <NUM_LIT> << <NUM_LIT> ) || AM . BaseOffs >= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) {


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _pdep_u32 ( unsigned int __X , unsigned int __Y ) {


<s> bool hasRTC ( ) const { return m_RTC ;


<s> emit_insn ( gen_insql_be ( ins_tmps [ i ] , data_regs [ i ] , dreg ) ) ; emit_insn ( gen_insxh ( data_regs [ i ] , data_regs [ i ] , i64 , dreg ) ) ; } else { emit_insn ( gen_insxh ( ins_tmps [ i ] , data_regs [ i ] , i64 , dreg ) ) ; emit_insn ( gen_insql_le ( data_regs [ i ] , data_regs [ i ] , dreg ) ) ; } } for ( i = words - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { ins_tmps [ i - <NUM_LIT> ] = expand_binop ( DImode , ior_optab , data_regs [ i ] , ins_tmps [ i - <NUM_LIT> ] , ins_tmps [ i - <NUM_LIT> ] , <NUM_LIT> , OPTAB_WIDEN ) ; } } if ( WORDS_BIG_ENDIAN ) { emit_insn ( gen_mskxl_be ( st_tmp_2 , st_tmp_2 , constm1_rtx , dreg ) ) ; emit_insn ( gen_mskxh ( st_tmp_1 , st_tmp_1 , i64 , dreg ) ) ; } else { emit_insn ( gen_mskxh ( st_tmp_2 , st_tmp_2 , i64 , dreg ) ) ; emit_insn ( gen_mskxl_le ( st_tmp_1 , st_tmp_1 , constm1_rtx , dreg ) ) ; } if ( data_regs != NULL ) { st_tmp_2 = expand_binop ( DImode , ior_optab , st_tmp_2 , ins_tmps [ words - <NUM_LIT> ] , st_tmp_2 , <NUM_LIT> , OPTAB_WIDEN ) ; st_tmp_1 = expand_binop ( DImode , ior_optab , st_tmp_1 , data_regs [ <NUM_LIT> ] , st_tmp_1 , <NUM_LIT> , OPTAB_WIDEN ) ; } if ( WORDS_BIG_ENDIAN ) emit_move_insn ( st_addr_1 , st_tmp_1 ) ; else emit_move_insn ( st_addr_2 , st_tmp_2 ) ;


<s> unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( Reg ) ) ; TII -> reMaterialize ( MBB , Insert , NewReg , <NUM_LIT> , Def , * TRI ) ; Op . setReg ( NewReg ) ; MachineInstr * Clone = & * std :: prev ( Insert ) ; LIS . InsertMachineInstrInMaps ( * Clone ) ; LIS . createAndComputeVirtRegInterval ( NewReg ) ; MFI . stackifyVReg ( NewReg ) ; ImposeStackOrdering ( Clone ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Clone -> dump ( ) ) ; bool IsDead = MRI . use_empty ( Reg ) ; if ( ! IsDead ) { LiveInterval & LI = LIS . getInterval ( Reg ) ; ShrinkToUses ( LI , LIS ) ; IsDead = ! LI . liveAt ( LIS . getInstructionIndex ( Def ) . getDeadSlot ( ) ) ; } if ( IsDead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SlotIndex Idx = LIS . getInstructionIndex ( Def ) . getRegSlot ( ) ;

LIS . removePhysRegDefAt ( <STR_LIT> , Idx ) ;


<s> if ( MI -> isCall ( ) ) return true ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( MO . isFI ( ) ) return true ; if ( ! MO . isReg ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( R ) ) return true ; for ( MCSubRegIterator S ( R , & HRI , true ) ; S . isValid ( ) ; ++ S ) if ( CSR [ * S ] ) return true ; }


<s> assert ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Lo , Hi ; SDValue ArgValueLo , ArgValueHi ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( nullptr == InFlag ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValueLo = DAG . getCopyFromReg ( Root , Dl , Reg , <STR_LIT> ) ; Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ; ArgValueHi = DAG . getCopyFromReg ( Root , Dl , Reg , <STR_LIT> ) ; } else {

ArgValueLo = DAG . getCopyFromReg ( Root , Dl , VA . getLocReg ( ) , <STR_LIT> , * InFlag ) ;


<s> if ( Splat . getOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * Mask = dyn_cast < ConstantSDNode > ( Splat . getOperand ( <NUM_LIT> ) ) ; if ( ! Mask || Mask -> getZExtValue ( ) != <NUM_LIT> ) return false ;


<s> } } if ( VT . is256BitVector ( ) ) { SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ; if ( R . getNode ( ) ) return R ; } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getResNo ( ) == <NUM_LIT> && N0 . getValueType ( ) == <STR_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) { SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , VT ) ; SDValue R = DAG . getNode ( <STR_LIT> , dl , NodeTys , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , R . getValue ( <NUM_LIT> ) ) ; return R . getValue ( <NUM_LIT> ) ; } return SDValue ( ) ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> if ( ! Skipped && MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM3Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM3Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( MO2 . getReg ( ) ) { Binary |= get<ISA_LIT>RegisterNumbering ( MO2 . getReg ( ) ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; if ( unsigned ImmOffs = <STR_LIT> ( AM3Opc ) ) { Binary |= ( ImmOffs >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ImmOffs & <NUM_LIT> ) ;


<s> bool inMicro<ISA_LIT>Mode ( ) const { return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> return ; } TOut . emitStoreWithImmOffset ( <STR_LIT> , <STR_LIT> , <STR_LIT> , StackOffset , [ & ] ( ) { return getATReg ( IDLoc ) ; } , IDLoc , STI ) ;


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> for ( Module :: iterator F = M . begin ( ) , E = M . end ( ) ; F != E ; ++ F ) { if ( F -> isDeclaration ( ) || F -> hasFnAttribute ( <STR_LIT> ) || F -> hasFnAttribute ( <STR_LIT> ) ) continue ; Modified |= fixupFPReturnAndCall ( * F , & M , Subtarget ) ; FPParamVariant V = whichFPParamVariantNeeded ( * F ) ; if ( V != NoSig ) { Modified = true ; createFPFnStub ( F , & M , V , Subtarget ) ; } }


<s> MCAsmParserExtension :: Initialize ( Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ;

setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isLdstSoMinusReg ( const MachineInstr & MI , unsigned Op ) const { unsigned OffImm = MI . getOperand ( Op + <NUM_LIT> ) . getImm ( ) ;

return <STR_LIT> ( OffImm ) == <STR_LIT> ;


<s> unsigned * cost = XNEWVEC ( unsigned , <NUM_LIT> ) ;

cost [ vect_prologue ] = cost [ vect_body ] = cost [ vect_epilogue ] = <NUM_LIT> ;


<s> if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) {


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> if ( ForCodeSize || V . hasOneUse ( ) ) return true ; return false ;


<s> case GT : case LT : case LE : if ( op1 == CONST0_RTX ( mode ) && ( CSKY_ISA_FEATURE_GET ( fpv2_sf ) || CSKY_ISA_FEATURE_GET ( fpv2_df ) || CSKY_ISA_FEATURE_GET ( fpv2_divd ) ) ) op1 = force_reg ( mode , op1 ) ; break ; case ORDERED : code = UNORDERED ; invert = true ; break ; default : break ;


<s> if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decode<ISA_LIT>64Instruction32 ( instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } Result = decode<ISA_LIT>Instruction32 ( instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } return MCDisassembler :: Fail ;


<s> } if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( SrcReg ) ) return <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) ) return <STR_LIT> ; } if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) return HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> :


<s> X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getScalarSizeInBits ( ) ; if ( ! MaskVT . isInteger ( ) || DAG . ComputeNumSignBits ( Mask ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( SDValue Res = combineLogicBlendIntoConditionalNegate ( VT , Mask , X , Y , DL , DAG , Subtarget ) ) return Res ; if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ;

MVT BlendVT = VT . is256BitVector ( ) ? <STR_LIT> : <STR_LIT> ;


<s> unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char L = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { assert ( ! Val == VRegs . empty ( ) && <STR_LIT> ) ; auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned Opcode = ST . getReturnOpcode ( ) ; auto Ret = MIRBuilder . buildInstrNoInsert ( Opcode ) . add ( predOps ( <STR_LIT> ) ) ; if ( ! lowerReturnVal ( MIRBuilder , Val , VRegs , Ret ) ) return false ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI , unsigned Alignment ) : TargetFrameLowering ( StackGrowsDown , Alignment , - <NUM_LIT> ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( STI . getRegisterInfo ( ) ) {


<s> printAddress ( MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) , O ) ;


<s> static std :: string GetTypeName ( Type & Ty ) { if ( auto * IntTy = dyn_cast < IntegerType > ( & Ty ) ) { return std :: string ( <STR_LIT> ) + std :: to_string ( IntTy -> getBitWidth ( ) ) ;


<s> unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( InVT . isScalableVector ( ) ) { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ! isTypeLegal ( VT ) || ! VT . isInteger ( ) ) return SDValue ( ) ; SDValue Vec0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; if ( VT . getVectorElementCount ( ) != ( InVT . getVectorElementCount ( ) * <NUM_LIT> ) ) return SDValue ( ) ; EVT WideVT = InVT . widenIntegerVectorElementType ( * ( DAG . getContext ( ) ) ) ; SDValue ExtVec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec1 ) ; if ( Idx == <NUM_LIT> ) { SDValue HiVec0 = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec0 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ExtVec , HiVec0 ) ; } else if ( Idx == InVT . getVectorMinNumElements ( ) ) { SDValue LoVec0 = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec0 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoVec0 , ExtVec ) ;


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI , ( Is64Bit ) ? true : false ) ;

return createELFObjectWriter ( MOTW , OS , IsLittleEndian ) ;


if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) x = XEXP ( x , <NUM_LIT> ) ;


<s> case XOPA_MAP : decision = & XOPA_MAP_SYM ; break ; case THREEDNOW_MAP : decision = & THREEDNOW_MAP_SYM ; break ; } return decision -> opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] . modrm_type != MODRM_ONEENTRY ;


<s> if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ;

if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

int64_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) : <NUM_LIT> ;


<s> SelectionDAG & DAG = CLI . DAG ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const char * <ISA_LIT>16HelperFunction = nullptr ; bool Need<ISA_LIT>16Helper = false ; if ( Subtarget . in<ISA_LIT>16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { const char * Symbol = S -> getSymbol ( ) ; <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { Symbol , <STR_LIT> } ; const <STR_LIT> * Signature = <STR_LIT> ( Symbol ) ; if ( ! IsPICCall && ( Signature && ( FuncInfo -> StubsNeeded . find ( Symbol ) == FuncInfo -> StubsNeeded . end ( ) ) ) ) { FuncInfo -> StubsNeeded [ Symbol ] = Signature ; if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } const <ISA_LIT>16IntrinsicHelperType * Helper = std :: lower_bound ( std :: begin ( <ISA_LIT>16IntrinsicHelper ) , std :: end ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ; if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . getArgs ( ) , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ;

JumpTarget = DAG . getExternalSymbol ( <ISA_LIT>16HelperFunction , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


<s> return Is64Bit && ( TargetTriple . isX32 ( ) || TargetTriple . isOSNaCl ( ) ) ;


<s> std :: string <ISA_LIT>Name = CPU ; if ( <ISA_LIT>Name . empty ( ) ) <ISA_LIT>Name = <STR_LIT> ;


<s> return arm_gen_multiple_op ( FALSE , regs , count , basereg , write_back , basemem , offsetp ) ;


<s> bool <ISA_LIT>FastISel :: SelectCall ( const Instruction * I , const char * IntrMemName = nullptr ) { const CallInst * CI = cast < CallInst > ( I ) ; const Value * Callee = CI -> getCalledOperand ( ) ; if ( isa < InlineAsm > ( Callee ) ) return false ; if ( CI -> isTailCall ( ) ) return false ; CallingConv :: ID CC = CI -> getCallingConv ( ) ; FunctionType * FTy = CI -> getFunctionType ( ) ; bool isVarArg = FTy -> isVarArg ( ) ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , isVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < Register , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; unsigned arg_size = CI -> arg_size ( ) ; Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( auto ArgI = CI -> arg_begin ( ) , ArgE = CI -> arg_end ( ) ; ArgI != ArgE ; ++ ArgI ) { if ( IntrMemName && ArgE - ArgI <= <NUM_LIT> ) break ; <STR_LIT> Flags ;

unsigned ArgIdx = ArgI - CI -> arg_begin ( ) ;


<s> CallContext ( ) : FrameSetup ( nullptr ) , Call ( nullptr ) , SPCopy ( nullptr ) , ExpectedDist ( <NUM_LIT> ) , MovVector ( <NUM_LIT> , nullptr ) , NoStackParams ( false ) , UsePush ( false ) {


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { static const uint16_t GPR64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( MCRegAliasIterator AI ( GPR64 [ n ] , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } return Reserved ;


<s> if ( ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ;

if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ;


<s> return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ;


<s> if ( PostRA && III . ZeroIsSpecialOrig != III . ZeroIsSpecialNew ) { unsigned PosForOrigZero = III . ZeroIsSpecialOrig ? III . ZeroIsSpecialOrig : III . ZeroIsSpecialNew + <NUM_LIT> ; unsigned OrigZeroReg = MI . getOperand ( PosForOrigZero ) . getReg ( ) ; unsigned NewZeroReg = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; if ( ( NewZeroReg == <STR_LIT> || NewZeroReg == <STR_LIT> ) && ConstantOpNo != III . ZeroIsSpecialNew ) return false ; if ( ( OrigZeroReg == <STR_LIT> || OrigZeroReg == <STR_LIT> ) && ConstantOpNo != PosForOrigZero ) return false ; } unsigned Opc = MI . getOpcode ( ) ; bool SpecialShift32 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool SpecialShift64 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool SetCR = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool RightShift = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; MI . setDesc ( get ( III . ImmOpcode ) ) ; if ( ConstantOpNo == III . ConstantOpNo ) { if ( SpecialShift32 || SpecialShift64 ) { LoadImmediateInfo LII ; LII . Imm = <NUM_LIT> ; LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; MI . getOperand ( III . ConstantOpNo ) . ChangeToImmediate ( SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; MI . getOperand ( III . ConstantOpNo ) . ChangeToImmediate ( SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ;


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> return ( uint16x8_t ) __builtin_neon_vdup_nv8hi ( ( __builtin_neon_hi ) __a ) ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) {

ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , uint8_t _OSABI ) : <ISA_LIT>AsmBackend ( T , TT ) , OSABI ( _OSABI ) {


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {


<s> if ( VT . isVector ( ) ) return false ; Type * Ty = I -> getType ( ) ; if ( Ty -> isFloatTy ( ) && ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Ty -> isDoubleTy ( ) && ( ! Subtarget -> hasVFP2Base ( ) || ! Subtarget -> hasFP64 ( ) ) ) return false ; unsigned Opc ; bool is64bit = VT == <STR_LIT> || VT == <STR_LIT> ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ;


<s> return ( __m512i ) __builtin_ia32_vcvtph2w512_mask_round ( __B , ( __v32hi ) _mm512_setzero_si512 ( ) , __A , _MM_FROUND_CUR_DIRECTION ) ;


<s> MCSymbol * <ISA_LIT>_MachoTargetObjectFile :: getCFIPersonalitySymbol ( const GlobalValue * GV , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI ) const { return TM . getSymbol ( GV , Mang ) ;


<s> Value * Temp [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < ( VecElems / <NUM_LIT> ) * Stride ; i += <NUM_LIT> ) { genShuffleBland ( VT , VPShuf , OptimizeShuf , ( i / Stride ) * <NUM_LIT> , ( i + <NUM_LIT> ) / Stride * <NUM_LIT> ) ; Temp [ i / <NUM_LIT> ] = Builder . CreateShuffleVector ( Vec [ i % Stride ] , Vec [ ( i + <NUM_LIT> ) % Stride ] , OptimizeShuf ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _tzcnt_u16 ( unsigned short __X ) { return __builtin_ia32_tzcnt_u16 ( __X ) ;


<s> RTX_FLAG ( new_mem_exp , jump ) = RTX_FLAG ( original_mem_exp , jump ) ; RTX_FLAG ( new_mem_exp , call ) = RTX_FLAG ( original_mem_exp , call ) ; RTX_FLAG ( new_mem_exp , unchanging ) = RTX_FLAG ( original_mem_exp , unchanging ) ; RTX_FLAG ( new_mem_exp , volatil ) = RTX_FLAG ( original_mem_exp , volatil ) ; RTX_FLAG ( new_mem_exp , frame_related ) = RTX_FLAG ( original_mem_exp , frame_related ) ; RTX_FLAG ( new_mem_exp , in_struct ) = RTX_FLAG ( original_mem_exp , in_struct ) ; RTX_FLAG ( new_mem_exp , return_val ) = RTX_FLAG ( original_mem_exp , return_val ) ; struct mem_attrs original_attrs = * get_mem_attrs ( original_mem_exp ) ; alias_set_type set = original_attrs . alias ; set_mem_alias_set ( new_mem_exp , set ) ; addr_space_t addrspace = original_attrs . addrspace ; set_mem_addr_space ( new_mem_exp , addrspace ) ; unsigned int align = original_attrs . align ; set_mem_align ( new_mem_exp , align ) ;


<s> unsigned Vec = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int Off = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Reg ; computeIndirectRegAndOffset ( Vec , Reg , Off ) ;

MachineInstr * MovRel = BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Reg ) . addReg ( Vec , RegState :: Implicit ) ;


<s> return DAG . getNode ( <STR_LIT> + ShiftOffset / <NUM_LIT> , SL , <STR_LIT> , Shift ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedBits = APInt :: getBitsSet ( <NUM_LIT> , <NUM_LIT> * Offset , <NUM_LIT> * Offset + <NUM_LIT> ) ; if ( TLI . SimplifyDemandedBits ( Src , DemandedBits , DCI ) ) return SDValue ( N , <NUM_LIT> ) ;

if ( SDValue DemandedSrc = TLI . SimplifyMultipleUseDemandedBits ( Src , DemandedBits , DAG ) ) return DAG . getNode ( N -> getOpcode ( ) , SL , <STR_LIT> , DemandedSrc ) ;


ix86_builtins [ ( int ) IX86_BUILTIN_FABSQ ] = t ;


<s> AllAnalyzable &= Term . isBranch ( ) && ! Term . isIndirectBranch ( ) ; }

assert ( ( AnyBarrier || AllAnalyzable ) && <STR_LIT> ) ;


<s> if ( ! CN1 ) return SDValue ( ) ; const ConstantSDNode * CAdd = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! CAdd ) return SDValue ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; APInt Offset = CAdd -> getAPIntValue ( ) << CN1 -> getAPIntValue ( ) ; if ( ! TII -> canFoldOffset ( Offset . getZExtValue ( ) , AddrSpace ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue ShlX = DAG . getNode ( <STR_LIT> , SL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; SDValue COffset = DAG . getConstant ( Offset , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , ShlX , COffset ) ;


<s> if ( fcode >= RS6000_OVLD_MAX ) return error_mark_node ;


<s> if ( Cond . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; if ( ( DAG . isConstantValueOfAnyType ( True ) || DAG . isConstantValueOfAnyType ( True ) ) && ( ! DAG . isConstantValueOfAnyType ( False ) && ! DAG . isConstantValueOfAnyType ( False ) ) ) { SDLoc SL ( N ) ; <STR_LIT> NewCC = getSetCCInverse ( cast < CondCodeSDNode > ( CC ) -> get ( ) , LHS . getValueType ( ) . isInteger ( ) ) ; SDValue NewCond = DAG . getSetCC ( SL , Cond . getValueType ( ) , LHS , RHS , NewCC ) ; return DAG . getNode ( <STR_LIT> , SL , VT , NewCond , False , True ) ;


<s> return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return EmitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> :


<s> break ; case RVV_VXSAT : __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv ) : : <STR_LIT> ) ; break ; case RVV_VXRM :


<s> for ( unsigned reg = <STR_LIT> ; reg <= <STR_LIT> ; ++ reg ) if ( MRI -> isPhysRegUsed ( reg ) ) return false ;


<s> APInt ShlConst = ( cast < ConstantSDNode > ( N01 ) ) -> getAPIntValue ( ) ; APInt SarConst = ( cast < ConstantSDNode > ( N1 ) ) -> getAPIntValue ( ) ; EVT CVT = N1 . getValueType ( ) ; if ( SarConst . isNegative ( ) ) return SDValue ( ) ; for ( MVT SVT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { unsigned ShiftSize = SVT . getSizeInBits ( ) ; if ( ShiftSize >= Size || ShlConst != Size - ShiftSize ) continue ; SDLoc DL ( N ) ; SDValue NN = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getValueType ( SVT ) ) ; SarConst = SarConst - ( Size - ShiftSize ) ; if ( SarConst == <NUM_LIT> ) return NN ; else if ( SarConst . isNegative ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , NN , DAG . getConstant ( - SarConst , DL , CVT ) ) ; else return DAG . getNode ( <STR_LIT> , DL , VT , NN , DAG . getConstant ( SarConst , DL , CVT ) ) ; }


<s> return ( uint32x4_t ) __builtin_neon_vshru_nv4si ( ( int32x4_t ) __a , __b ) ;


<s> return ( __m512i ) __builtin_ia32_prolq512_mask ( ( __v8di ) __A , __B , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> __inline__ static unsigned long long sh_media_MSAD_UBQ ( unsigned long long mm , unsigned long long mn , unsigned long long mw ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) , <STR_LIT> ( mw ) ) ;


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ! ConstantSize ) return SDValue ( ) ;


<s> void setFAIndex ( int Index ) { FrameAddrIndex = Index ;