<s> bool RequiresBundling = STI -> isTargetWindows ( ) && IsAnAddressOperand ( MO ) ; MachineInstrBuilder LO16 , HI16 ; if ( ! STI -> hasV6T2Ops ( ) && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) { assert ( ! STI -> isTargetWindows ( ) && <STR_LIT> ) ; LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned ImmVal = ( unsigned ) MO . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; LO16 = LO16 . addImm ( SOImmValV1 ) ; HI16 = HI16 . addImm ( SOImmValV2 ) ; LO16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; HI16 -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; LO16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; HI16 . addImm ( Pred ) . addReg ( PredReg ) . add ( condCodeOp ( ) ) ; TransferImpOps ( MI , LO16 , HI16 ) ; MI . eraseFromParent ( ) ; return ; } unsigned LO16Opc = <NUM_LIT> ; unsigned HI16Opc = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } else { LO16Opc = <STR_LIT> ; HI16Opc = <STR_LIT> ; } LO16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( LO16Opc ) , DstReg ) ; HI16 = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( HI16Opc ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : { unsigned Imm = MO . getImm ( ) ; unsigned Lo16 = Imm & <NUM_LIT> ; unsigned Hi16 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; LO16 = LO16 . addImm ( Lo16 ) ; HI16 = HI16 . addImm ( Hi16 ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * ES = MO . getSymbolName ( ) ; unsigned TF = MO . getTargetFlags ( ) ; LO16 = LO16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ;

HI16 = HI16 . addExternalSymbol ( ES , TF | <STR_LIT> ) ;


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const {

return ( STI . isTargetIOS ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ;


<s> if ( TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA ) return ;

std :: unique_ptr < MCSubtargetInfo > STI ( TM . getTarget ( ) . createMCSubtargetInfo ( TM . getTargetTriple ( ) . str ( ) , TM . getTargetCPU ( ) , TM . getTargetFeatureString ( ) ) ) ;


<s> void GCNMaxOccupancySchedStrategy :: initialize ( ScheduleDAGMI * DAG ) { GenericScheduler :: initialize ( DAG ) ; MF = & DAG -> MF ; const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; const unsigned ErrorMargin = <NUM_LIT> ; SGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & <STR_LIT> ) ; VGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & <STR_LIT> ) ; <ISA_LIT>MachineFunctionInfo & MFI = * MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; TargetOccupancy = MFI . getOccupancy ( ) ; SGPRCriticalLimit = std :: min ( ST . getMaxNumSGPRs ( TargetOccupancy , true ) , SGPRExcessLimit ) ;

VGPRCriticalLimit = std :: min ( ST . getMaxNumVGPRs ( TargetOccupancy ) , VGPRExcessLimit ) ;


return offsetMinAlignForOpcode ( OpC ) ;


<s> EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( Node ) ; SDValue Upper = CurDAG -> getConstant ( UpperVal , VT ) ; if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant ( LowerVal , VT ) ;

SDValue Or = CurDAG -> getNode ( Opcode , DL , VT , Upper , Lower ) ;


<s> if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; break ; case CONST : inner = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( inner ) == PLUS && SPARC_SYMBOL_REF_TLS_P ( XEXP ( inner , <NUM_LIT> ) ) ) return false ; break ;


<s> CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useHVXOps ( ) ) return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>_HVX ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ;

AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ;


<s> } else if ( ! MRI -> hasOneDef ( Reg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto DI = MRI -> def_begin ( Reg ) , DE = MRI -> def_end ( ) ; DI != DE ; ++ DI ) { LLVM_DEBUG ( DI -> getParent ( ) -> dump ( ) ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ElimComparePass ( get<ISA_LIT>TargetMachine ( ) ) , false ) ;

addPass ( create<ISA_LIT>LongBranchPass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> DominatorTree & DT = getAnalysis < DominatorTreeWrapperPass > ( * NewPt -> getParent ( ) -> getParent ( ) ) . getDomTree ( ) ; for ( auto & IPI : InsertPts ) { if ( NewPt == IPI . first || DT . dominates ( IPI . first , NewPt ) || ( IPI . first -> getParent ( ) != NewPt -> getParent ( ) && DT . dominates ( IPI . first -> getParent ( ) , NewPt -> getParent ( ) ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( IPI . first -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << '\n' ) ; IPI . second . push_back ( UseIt ) ; return true ; }


<s> Register <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ;


<s> printSysRegOperand ( <STR_LIT> ( ) , MI , OpNum , O ) ;


<s> unsigned Op = Win64EH :: UOP_AllocSmall ; if ( Size >= <NUM_LIT> ) Op = Win64EH :: UOP_AllocLarge ; else if ( Size >= <NUM_LIT> ) Op = Win64EH :: UOP_AllocMedium ;

emitARM64WinUnwindCode ( Op , - <NUM_LIT> , Size ) ;


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> , <NUM_LIT> ) ;


<s> static bool sh_rtx_costs ( rtx x , int code , int outer_code , int * total ) { switch ( code ) { case CONST_INT : if ( TARGET_SHMEDIA ) { if ( INTVAL ( x ) == <NUM_LIT> ) * total = <NUM_LIT> ; else if ( outer_code == AND && and_operand ( ( x ) , DImode ) ) * total = <NUM_LIT> ; else if ( ( outer_code == IOR || outer_code == XOR || outer_code == PLUS ) && CONST_OK_FOR_I10 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else if ( CONST_OK_FOR_I16 ( INTVAL ( x ) ) ) * total = COSTS_N_INSNS ( outer_code != SET ) ; else if ( CONST_OK_FOR_I16 ( INTVAL ( x ) >> <NUM_LIT> ) ) * total = COSTS_N_INSNS ( ( outer_code != SET ) + <NUM_LIT> ) ; else if ( CONST_OK_FOR_I16 ( ( INTVAL ( x ) >> <NUM_LIT> ) >> <NUM_LIT> ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } if ( CONST_OK_FOR_I08 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else if ( ( outer_code == AND || outer_code == IOR || outer_code == XOR ) && CONST_OK_FOR_K08 ( INTVAL ( x ) ) ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : if ( TARGET_SHMEDIA64 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( TARGET_SHMEDIA32 ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = <NUM_LIT> ; return true ; case CONST_DOUBLE :

if ( TARGET_SHMEDIA ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> static DecodeStatus DecodeShiftLeftImm16 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) {

if ( Val > <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; int Offset = VA . getLocMemOffset ( ) ; MemOpChains . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Arg , DAG . getConstant ( Offset / <NUM_LIT> , dl , <STR_LIT> ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getConstant ( NumBytes , dl , PtrVT , true ) , DAG . getConstant ( <NUM_LIT> , dl , PtrVT , true ) , InFlag , dl ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; return LowerCallResult ( Chain , InFlag , RVLocs , dl , DAG , InVals ) ;


<s> static void BuildEndSignature ( BasicBlock & BB , Function & F ) { return BuildSignatureCall ( symbols :: END_FUNCTION_SIGNATURE , BB , F ) ;


<s> return ( STI . getFeatureBits ( ) & <STR_LIT> ) ;


<s> static inline bool isIndirectBranchOpcode ( int Opc ) { return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> void EmitCOFFSymbolType ( int Type ) override {


<s> while ( MemTransferSz > <NUM_LIT> ) { MemTransferSz -= ( int ) OptMemTransferScalar ( IRB , CurrSrc , CurrDst , Inst ) ; if ( MemTransferSz > <NUM_LIT> ) { CurrSrc = GetNextSrcGep ( IRB ) ; CurrDst = GetNextDstGep ( IRB ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {


<s> OutlinerCosts ( const <ISA_LIT>Subtarget & target ) : CallTailCall ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameTailCall ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallThunk ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameThunk ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallNoLRSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameNoLRSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , CallRegSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) , FrameRegSave ( target . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) {


<s> assert ( TII . getSubtarget ( ) . hasVFP2Base ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ;

unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> Current -> replaceLiveOut ( Register , NewRegister ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Current -> print ( dbgs ( ) , MRI -> getTargetRegisterInfo ( ) ) ) ; Current = Current -> getParent ( ) ; } } for ( MachineRegisterInfo :: reg_iterator I = MRI -> reg_begin ( Register ) , E = MRI -> reg_end ( ) ; I != E ; ) { MachineOperand & O = * I ; ++ I ; if ( O . isDef ( ) ) continue ; bool IsInside = contains ( O . getParent ( ) -> getParent ( ) ) ; bool IsLoopPHI = IsInside && ( O . getParent ( ) -> isPHI ( ) && O . getParent ( ) -> getParent ( ) == getEntry ( ) ) ; bool ShouldReplace = ( IsInside && ReplaceInside ) || ( ! IsInside && ReplaceOutside ) || ( IncludeLoopPHI && IsLoopPHI ) ; if ( ShouldReplace ) { if ( TargetRegisterInfo :: isPhysicalRegister ( NewRegister ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( NewRegister , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } else {

DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Register , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> << PrintReg ( NewRegister , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ;


<s> MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ;

cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ;


<s> if ( ! MCID . mayLoad ( ) || ! MI -> hasOneMemOperand ( ) ) return <STR_LIT> ; const MachineOperand * Segment = getNamedOperand ( * MI , <STR_LIT> :: segment ) ; if ( ! Segment || Segment -> getImm ( ) != <STR_LIT> ) return <STR_LIT> ;

int AddressIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: address ) ;


<s> int ok = frv_assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT , <NUM_LIT> ) ; gcc_assert ( ok ) ;


<s> SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ; OutOps . push_back ( NewOp ) ; return false ;


<s> if ( cum -> arg_count [ SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! named || GET_SH_ARG_CLASS ( mode ) == SH_ARG_INT || ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT && cum -> arg_count [ SH_ARG_FLOAT ] >= NPARM_REGS ( SFmode ) ) ) && size > <NUM_LIT> && ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * cum , mode , type , named ) ) return size ;


<s> if ( OpIdx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI -> getOperand ( OpIdx ) ; if ( usesConstantBus ( MRI , MO ) ) { if ( MO . isReg ( ) ) { if ( MO . getReg ( ) != SGPRUsed ) ++ ConstantBusCount ; SGPRUsed = MO . getReg ( ) ; } else { ++ ConstantBusCount ; } } } if ( ConstantBusCount > <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } if ( Src1Idx != - <NUM_LIT> && ( isVOP2 ( Opcode ) || isVOPC ( Opcode ) ) ) { const MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( Src1 . isImm ( ) ) { ErrInfo = <STR_LIT> ; return false ; } } if ( isVOP3 ( Opcode ) ) { if ( Src0Idx != - <NUM_LIT> && isLiteralConstant ( MI -> getOperand ( Src0Idx ) ) ) { ErrInfo = <STR_LIT> ; return false ; } if ( Src1Idx != - <NUM_LIT> && isLiteralConstant ( MI -> getOperand ( Src1Idx ) ) ) { ErrInfo = <STR_LIT> ; return false ; } if ( Src2Idx != - <NUM_LIT> && isLiteralConstant ( MI -> getOperand ( Src2Idx ) ) ) { ErrInfo = <STR_LIT> ; return false ; } } if ( Desc . getOpcode ( ) == AMDGPU :: V_DIV_SCALE_F32 || Desc . getOpcode ( ) == AMDGPU :: V_DIV_SCALE_F64 ) { const MachineOperand & Src0 = MI -> getOperand ( Src0Idx ) ; const MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; const MachineOperand & Src2 = MI -> getOperand ( Src2Idx ) ; if ( Src0 . isReg ( ) && Src1 . isReg ( ) && Src2 . isReg ( ) ) { if ( ! compareMachineOp ( Src0 , Src1 ) && ! compareMachineOp ( Src0 , Src2 ) ) { ErrInfo = <STR_LIT> ; return false ; } } } return true ;


<s> operands [ <NUM_LIT> ] = gen_rtx_REG ( mode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( mode , REGNO ( operands [ <NUM_LIT> ] ) ) ; break ; case MEM : operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , mode , GET_MODE_SIZE ( mode ) ) ; operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; break ; default : gcc_unreachable ( ) ;


<s> MIB . addDef ( PhysReg , RegState :: Implicit ) ; MIRBuilder . buildCopy ( ValVReg , PhysReg ) ;


<s> RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ;

TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;


<s> assert ( SP ) ; return slice ( SP -> ITState , <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return ! G -> getGlobal ( ) -> isDeclaration ( ) && ! G -> getGlobal ( ) -> isWeakForLinker ( ) ;


<s> SDLoc SL ( N ) ; uint64_t CVal = Val . getZExtValue ( ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DAG . getConstant ( Lo_32 ( CVal ) , SL , <STR_LIT> ) , DAG . getConstant ( Hi_32 ( CVal ) , SL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , DestVT , Vec ) ; } break ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performShlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSrlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSraCombine ( N , DCI ) ; } case <STR_LIT> : return performTruncateCombine ( N , DCI ) ; case <STR_LIT> : return performMulCombine ( N , DCI ) ; case <STR_LIT> : return performMulhsCombine ( N , DCI ) ; case <STR_LIT> : return performMulhuCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( SDValue V = simplifyI24 ( N , DCI ) ) return V ; return SDValue ( ) ; } case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performFNegCombine ( N , DCI ) ; case <STR_LIT> : return performFAbsCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) {

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ;


<s> } DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> << getBlockExitStateName ( CurState ) << '\n' ) ; if ( CurState == EXITS_DIRTY ) for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; BlockStates [ MBB . getNumber ( ) ] . ExitState = CurState ;


<s> if ( Subtarget -> isFlavorIntel ( ) ) {

return new <ISA_LIT>IntelAsmPrinter ( o , tm , tm . getTargetAsmInfo ( ) , fast ) ;


<s> } } if ( ! ContainsFPCode ) { const BasicBlock * LLVMBB = MBB -> getBasicBlock ( ) ; const PHINode * PN ; for ( succ_const_iterator SI = succ_begin ( LLVMBB ) , E = succ_end ( LLVMBB ) ; ! ContainsFPCode && SI != E ; ++ SI ) { for ( BasicBlock :: const_iterator II = SI -> begin ( ) ; ( PN = dyn_cast < PHINode > ( II ) ) ; ++ II ) { if ( PN -> getType ( ) == Type :: get<ISA_LIT>_FP80Ty ( LLVMBB -> getContext ( ) ) || ( ! Subtarget . hasSSE1 ( ) && PN -> getType ( ) -> isFloatingPoint ( ) ) || ( ! Subtarget . hasSSE2 ( ) && PN -> getType ( ) == Type :: getDoubleTy ( LLVMBB -> getContext ( ) ) ) ) { ContainsFPCode = true ; break ; } } } } if ( ContainsFPCode ) { BuildMI ( * MBB , MBBI -> getFirstTerminator ( ) , DebugLoc :: getUnknownLoc ( ) , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) ) ; ++ NumFPKill ; Changed = true ; }


<s> if ( ! Desc . isCommutable ( ) ) return false ; unsigned Opc = Desc . getOpcode ( ) ; int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; if ( Src0Idx == - <NUM_LIT> ) return false ; int Src1Idx = <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return false ;

return fixCommutedOpIndices ( SrcOpIdx0 , SrcOpIdx1 , Src0Idx , Src1Idx ) ;


<s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'r' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ;


<s> SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts * Scale , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) { if ( UndefElts [ i ] ) continue ; int VecIdx = Scale * Idx + i ; ShuffleMask [ VecIdx ] = EltBits [ i ] . isNullValue ( ) ? SM_SentinelZero : VecIdx ; }

if ( SDValue Shuffle = combine<ISA_LIT>ShufflesRecursively ( { SrcVec } , <NUM_LIT> , SrcVec , ShuffleMask , { } , <NUM_LIT> , false , DAG , Subtarget ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Shuffle , N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ;


<s> processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * TFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> adjustsStack ( ) ) { TFI -> setRAStackOffset ( <NUM_LIT> ) ; MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; } if ( hasFP ( MF ) ) { TFI -> setFPStackOffset ( <NUM_LIT> ) ; MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ;


<s> int64_t MulImm = cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ; if ( ( MulImm % std :: abs ( Scale ) ) == <NUM_LIT> ) {


<s> unsigned getMaxCallFrameSize ( ) const {


<s> assert ( MF && <STR_LIT> ) ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: GHC ) return CSR_<ISA_LIT>_NoRegs_SaveList ; if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_SaveList ; else if ( isSVEFunction ( * MF ) ) return CSR_<ISA_LIT>_SVE_AAPCS_SaveList ;


<s> u = Imm | ( Imm << <NUM_LIT> ) ; if ( Vs == u ) return ( ( ( Vs == V ) ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | Imm ;

if ( Vs == ( u | ( u << <NUM_LIT> ) ) ) return ( <NUM_LIT> << <NUM_LIT> ) | Imm ;


<s> unsigned CombineOpcode = N . getOpcode ( ) ; SDValue V = N . getOperand ( <NUM_LIT> ) ; for ( ; V . hasOneUse ( ) ; V = V . getOperand ( <NUM_LIT> ) ) { switch ( V . getOpcode ( ) ) { default : return false ; case <STR_LIT> : continue ; case <STR_LIT> : case <STR_LIT> : if ( V . getOpcode ( ) == CombineOpcode ) break ; continue ; case <STR_LIT> : { SmallVector < int , <NUM_LIT> > VMask = getPSHUFShuffleMask ( V ) ; int DOffset = CombineOpcode == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ! ( ( VMask [ DOffset + <NUM_LIT> ] < <NUM_LIT> && VMask [ DOffset + <NUM_LIT> ] < <NUM_LIT> ) || ( VMask [ DOffset + <NUM_LIT> ] >= <NUM_LIT> && VMask [ DOffset + <NUM_LIT> ] >= <NUM_LIT> ) ) ) return false ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) Mask [ i ] = <NUM_LIT> * ( VMask [ DOffset + Mask [ i ] / <NUM_LIT> ] % <NUM_LIT> ) + Mask [ i ] % <NUM_LIT> ; CombineOpcode = VMask [ DOffset + Mask [ <NUM_LIT> ] / <NUM_LIT> ] < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; continue ;


<s> AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ;

AU . addPreserved < MachineDominatorTree > ( ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

const MachineModuleInfo & MMI = MF . getMMI ( ) ;


<s> unsigned CCMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; MachineMemOperand * MMO = nullptr ; for ( auto * I : MI . memoperands ( ) ) if ( I -> isStore ( ) ) { MMO = I ; break ; } if ( STOCOpcode && ! IndexReg && Subtarget . hasLoadStoreOnCond ( ) ) { if ( Invert ) CCMask ^= CCValid ; BuildMI ( * MBB , MI , DL , TII -> get ( STOCOpcode ) ) . addReg ( SrcReg ) . add ( Base ) . addImm ( Disp ) . addImm ( CCValid ) . addImm ( CCMask ) . addMemOperand ( MMO ) ; MI . eraseFromParent ( ) ; return MBB ; } if ( ! Invert ) CCMask ^= CCValid ;


<s> static void fold_compare_helper ( gimple_stmt_iterator * gsi , tree_code code , gimple * stmt ) { tree arg0 = gimple_call_arg ( stmt , <NUM_LIT> ) ; tree arg1 = gimple_call_arg ( stmt , <NUM_LIT> ) ; tree lhs = gimple_call_lhs ( stmt ) ; tree cmp = fold_build_vec_cmp ( code , TREE_TYPE ( lhs ) , arg0 , arg1 , gsi ) ;

gimple * g = gimple_build_assign ( lhs , cmp ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( <STR_LIT> . contains ( DestReg ) && ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ) { printf ( <STR_LIT> ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) {


<s> void printNegZeroOperand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) {


<s> <ISA_LIT>Section ( const StringRef & name , SectionKind K , const std :: string & addr , int color ) : MCSection ( K ) , Name ( name ) , Address ( addr ) , Color ( color ) {


<s> static void ia64_soft_fp_init_libfuncs ( void ) {


<s> } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcLo = HRI . getSubReg ( SrcR , <STR_LIT> ) ; unsigned SrcHi = HRI . getSubReg ( SrcR , <STR_LIT> ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = HRI . getSpillSize ( <STR_LIT> ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc ; if ( LPR . contains ( SrcLo ) ) { StoreOpc = NeedAlign <= HasAlign ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcLo , getKillRegState ( IsKill ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; } if ( LPR . contains ( SrcHi ) ) {

StoreOpc = NeedAlign <= MinAlign ( HasAlign , Size ) ? <STR_LIT> : <STR_LIT> ;


<s> break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ;


<s> Expected < const D * > as ( ) const { if ( descsz < sizeof ( D ) ) { return make_error < StringError > ( <STR_LIT> , object :: object_error :: parse_failed ) ; } return reinterpret_cast < const D * > ( getDesc ( ) . data ( ) ) ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > Worklist ; MachineFunction :: iterator NextBB ; for ( MachineFunction :: iterator BI = MF . begin ( ) ; BI != MF . end ( ) ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock * MBB = & * BI ; MachineBasicBlock :: iterator I , E , Next ; E = MBB -> end ( ) ; for ( I = MBB -> begin ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; MachineBasicBlock * SplitMBB = MBB ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : SplitMBB = process ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( InsertKillCleanups ) Worklist . push_back ( & MI ) ; else SplitMBB = process ( MI ) ; break ; default :


<s> return getOpTypeArray ( Ty -> getArrayNumElements ( ) , El , MIRBuilder , EmitIR ) ; } if ( auto SType = dyn_cast < StructType > ( Ty ) ) { if ( isOpenCLBuiltinType ( SType ) ) return handleOpenCLBuiltin ( SType , MIRBuilder , AccQual ) ; if ( is<ISA_LIT>BuiltinType ( SType ) ) return handle<ISA_LIT>Builtin ( SType , MIRBuilder , AccQual ) ; if ( SType -> isOpaque ( ) ) return getOpTypeOpaque ( SType , MIRBuilder ) ; return getOpTypeStruct ( SType , MIRBuilder , EmitIR ) ; } if ( auto FType = dyn_cast < FunctionType > ( Ty ) ) { <ISA_LIT>Type * RetTy = find<ISA_LIT>Type ( FType -> getReturnType ( ) , MIRBuilder ) ; SmallVector < <ISA_LIT>Type * , <NUM_LIT> > ParamTypes ; for ( const auto & t : FType -> params ( ) ) { ParamTypes . push_back ( find<ISA_LIT>Type ( t , MIRBuilder ) ) ; } return getOpTypeFunction ( RetTy , ParamTypes , MIRBuilder ) ; } if ( auto PType = dyn_cast < PointerType > ( Ty ) ) { <ISA_LIT>Type * SpvElementType ; if ( PType -> isOpaque ( ) ) { SpvElementType = getOrCreate<ISA_LIT>IntegerType ( <NUM_LIT> , MIRBuilder ) ; } else { Type * ElemType = PType -> getPointerElementType ( ) ; if ( auto SType = dyn_cast < StructType > ( ElemType ) ) { if ( isOpenCLBuiltinType ( SType ) ) return handleOpenCLBuiltin ( SType , MIRBuilder , AccQual ) ; if ( is<ISA_LIT>BuiltinType ( SType ) ) return handle<ISA_LIT>Builtin ( SType , MIRBuilder , AccQual ) ; } SpvElementType = find<ISA_LIT>Type ( ElemType , MIRBuilder , AQ :: ReadWrite , EmitIR ) ; } auto SC = addressSpaceToStorageClass ( PType -> getAddressSpace ( ) ) ; if ( SpvElementType == nullptr ) { if ( ForwardPointerTypes . find ( Ty ) == ForwardPointerTypes . end ( ) ) ForwardPointerTypes [ PType ] = getOpTypeForwardPointer ( SC , MIRBuilder ) ;


<s> if ( reg_classes_intersect_p ( from , CR_REGS ) ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ; if ( reg_classes_intersect_p ( to , CR_REGS ) ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ; if ( from == MEM_REGS || to == MEM_REGS ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ;

else if ( reg_classes_intersect_p ( from , MEM_REGS ) || reg_classes_intersect_p ( to , MEM_REGS ) ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> auto Name = Lexer . getTok ( ) . getString ( ) ; Parser . Lex ( ) ; return Name ;


<s> return OriginalArgWas<ISA_LIT>F128 [ ValNo ] ;


<s> assert ( ! Subtarget . is<ISA_LIT>64 ( ) && <STR_LIT> ) ;

return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , Op , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) , Align ( <NUM_LIT> ) , false , true , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> if ( TARGET_DIRECT_MOVE && ( ( mode == SDmode ) || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE ) || ( to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ; else if ( TARGET_MFPGPR && TARGET_POWERPC64 && size == <NUM_LIT> && ( ( to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE ) || ( to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ;

else if ( ( size == <NUM_LIT> || ( TARGET_POWERPC64 && size == <NUM_LIT> ) ) && ( ( to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE ) || ( to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE ) ) ) return true ;


<s> GetElementPtrInst * UserG = cast < GetElementPtrInst > ( * UI ) ; if ( isHandledGepForm ( UserG ) ) continue ; } Us . insert ( & UI . getUse ( ) ) ; } Nodes . push_back ( N ) ; NodeOrder . special_insert_for_special_msvc ( N ) ; NodeOrder . insert ( N ) ; GepNode * PN = N ; Type * PtrTy = cast < PointerType > ( PtrOp -> getType ( ) ) -> getElementType ( ) ; for ( User :: op_iterator OI = GepI -> idx_begin ( ) + <NUM_LIT> , OE = GepI -> idx_end ( ) ; OI != OE ; ++ OI ) { Value * Op = * OI ; GepNode * Nx = new ( * Mem ) GepNode ; Nx -> Parent = PN ; Nx -> Flags |= GepNode :: Internal ; Nx -> PTy = PtrTy ; Nx -> Idx = Op ;


<s> for ( unsigned i = Size / <NUM_LIT> ; i > <NUM_LIT> ; ) { unsigned Shift = -- i * <NUM_LIT> ; EmitShort ( ( Val >> Shift ) & <NUM_LIT> , OS ) ;


<s> return ( int32x2_t ) __builtin_neon_vsubhnv2di ( __a , __b ) ;


<s> static void * c6x_alloc_sched_context ( void ) {

return xmalloc ( sizeof ( struct c6x_sched_context ) ) ;


<s> return AsmPrinter :: lowerConstant ( CV ) ;


<s> if ( isa < ConstantPointerNull > ( Op1 ) ) Op1 = Constant :: getNullValue ( TD . getIntPtrType ( Op0 -> getContext ( ) ) ) ; if ( ConstantInt * Op1C = dyn_cast < ConstantInt > ( Op1 ) ) { if ( unsigned CompareImmOpc = <ISA_LIT>ChooseCmpImmediateOpcode ( VT , Op1C ) ) { BuildMI ( MBB , DL , TII . get ( CompareImmOpc ) ) . addReg ( Op0Reg ) . addImm ( Op1C -> getSExtValue ( ) ) ; return true ;


<s> SchedModel ( SM ) , TotalPackets ( <NUM_LIT> ) { ResourcesModel = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> CreateTargetScheduleState ( * TM . getSubtargetImpl ( ) ) ; assert ( ResourcesModel && <STR_LIT> ) ; Packet . resize ( SchedModel -> getIssueWidth ( ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Block . getDivergent ( ) -> MI ) ; return false ; } SmallVectorImpl < PredicatedMI > & Insts = Block . getInsts ( ) ; for ( auto & PredMI : Insts ) { if ( PredMI . Predicates . count ( VCTP ) || isVCTP ( PredMI . MI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * PredMI . MI << <STR_LIT> ; for ( auto * MI : PredMI . Predicates ) dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } if ( ! ValidateLiveOuts ( ) ) return false ; Register NumElements = VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineBasicBlock * InsertBB = StartInsertPt -> getParent ( ) ; if ( ! RDA . isReachingDefLiveOut ( StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( InsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; InsertBB -> insert ( MachineBasicBlock :: iterator ( StartInsertPt ) , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; InsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return false ; } } } auto CannotProvideElements = [ this ] ( MachineBasicBlock * MBB , Register NumElements ) { if ( RDA . hasLocalDefBefore ( & MBB -> back ( ) , NumElements ) ) return true ; if ( MBB -> pred_size ( ) > <NUM_LIT> ) return true ; return false ; } ; MachineBasicBlock * MBB = MLI . findLoopPreheader ( & ML , true ) ; if ( ! MBB ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } while ( MBB != InsertBB ) { if ( CannotProvideElements ( MBB , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MBB = * MBB -> pred_begin ( ) ; } auto IsValidSub = [ ] ( MachineInstr * MI , unsigned ExpectedVecWidth ) { unsigned ImmOpIdx = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) {


<s> VariantKind getKind ( ) const { return Kind ;


<s> gcc_assert ( dem == * m_vector_manager -> vector_exprs [ i ] ) ; insn_info * insn = dem . get_insn ( ) ; gcc_assert ( insn && insn -> rtl ( ) ) ; rtx_insn * rinsn ; if ( vector_config_insn_p ( insn -> rtl ( ) ) ) { m_vector_manager -> to_delete_vsetvls . add ( insn -> rtl ( ) ) ; continue ; } gcc_assert ( has_vtype_op ( insn -> rtl ( ) ) ) ; rinsn = PREV_INSN ( insn -> rtl ( ) ) ; gcc_assert ( vector_config_insn_p ( PREV_INSN ( insn -> rtl ( ) ) ) ) ; eliminate_insn ( rinsn ) ; } }


<s> bool isRegListWithAPSR ( ) const { return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList ;


<s> if ( sched_verbose ) fprintf ( dump , <STR_LIT> ) ; if ( reload_completed && rs6000_sched_groups ) { if ( sel_sched_p ( ) ) return ; if ( rs6000_sched_insert_nops == sched_finish_none ) return ; if ( rs6000_sched_insert_nops == sched_finish_pad_groups ) n_groups = pad_groups ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ;


<s> assert ( Kind == k_CondCode && <STR_LIT> ) ;


<s> riscv_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; if ( info . num_fprs ) return false ; }

return ! IN_RANGE ( size , <NUM_LIT> , <NUM_LIT> * UNITS_PER_WORD ) ;


<s> } ConstantSDNode * ND = cast < ConstantSDNode > ( Op ) ; APInt C ( SVTBits , ND -> getAPIntValue ( ) . getZExtValue ( ) ) ; uint64_t ShAmt = C . getZExtValue ( ) ; if ( ShAmt >= SVTBits ) { Elts . push_back ( DAG . getUNDEF ( SVT ) ) ; continue ; } Elts . push_back ( DAG . getConstant ( One . shl ( ShAmt ) , dl , SVT ) ) ; } return DAG . getBuildVector ( VT , dl , Elts ) ; } if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ;

Amt = DAG . getBitcast ( <STR_LIT> , Amt ) ;


<s> if ( cfun -> machine -> interrupt_handler_p && ! df_regs_ever_live_p ( regno ) ) return false ;


<s> <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; SDValue PSHUFBMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) PSHUFBMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < <NUM_LIT> ? Mask [ i ] : Mask [ i ] - <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ; } if ( SDValue Result = lowerVectorShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Result ;

return lowerVectorShuffleAsSplitOrBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ;


<s> bool KillsOp0 = MI . killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI . getOperand ( <NUM_LIT> ) . setIsRenamable ( false ) ; MI . RemoveOperand ( <NUM_LIT> ) ;

MI . setDesc ( TII -> get ( getConcreteOpcode ( MI . getOpcode ( ) ) ) ) ;


<s> void <ISA_LIT>InstrInfo :: addSCCDefUsersToVALUWorklist ( MachineOperand & Op , MachineInstr & SCCDefInst , SetVectorType & Worklist ) const { assert ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) && ! Op . isDead ( ) && Op . getParent ( ) == & SCCDefInst ) ; for ( MachineInstr & MI :

make_range ( std :: next ( MachineBasicBlock :: iterator ( SCCDefInst ) ) , SCCDefInst . getParent ( ) -> end ( ) ) ) {


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : align = <NUM_LIT> ; break ; case <NUM_LIT> : align = <NUM_LIT> ; break ; default :


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitEHSjLjLongJmp ( MachineInstr * MI , MachineBasicBlock * MBB ) const { DebugLoc DL = MI -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * MBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( i ) ) ; }


<s> vld1_f16 ( const float16_t * __a ) { return __builtin_neon_vld1v4hf ( __a ) ;


<s> a = shift_alg_qi [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_qi [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_qi [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; case E_HImode : a = shift_alg_hi [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_hi [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_hi [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; case E_SImode : a = shift_alg_si [ cpu ] [ SHIFT_ASHIFT ] [ count ] ;

lr = shift_alg_si [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const Triple & TT ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI -> getOpcode ( ) ) ) if ( isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <NUM_LIT> ;


<s> if ( ! PhysReg ) return NSA_Status :: FIXED ; if ( MRI -> getRegClass ( Reg ) != & <STR_LIT> || Op . getSubReg ( ) ) return NSA_Status :: FIXED ; const MachineInstr * Def = MRI -> getUniqueVRegDef ( Reg ) ; if ( Def && Def -> isCopy ( ) && Def -> getOperand ( <NUM_LIT> ) . getReg ( ) == PhysReg ) return NSA_Status :: FIXED ; for ( auto U : MRI -> use_nodbg_operands ( Reg ) ) { if ( U . isImplicit ( ) ) return NSA_Status :: FIXED ;

const MachineInstr * UseInst = U . getParent ( ) ;


<s> unsigned Opcode = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return LowerToPredicatedOp ( Op , DAG , Opcode ) ; } uint64_t VTSize = VT . getFixedSizeInBits ( ) ; uint64_t InVTSize = InVT . getFixedSizeInBits ( ) ; if ( VTSize < InVTSize ) { MVT CastVT = <STR_LIT> ( <STR_LIT> ( InVT . getScalarSizeInBits ( ) ) , InVT . getVectorNumElements ( ) ) ; In = DAG . getNode ( Op . getOpcode ( ) , dl , CastVT , In ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; }


<s> Values ( int64_t i ) : ImmVal ( i ) {


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


return ( __m512d ) __builtin_ia32_broadcastf64x4_512 ( ( __v4df ) __A , ( __v8df ) _mm512_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( Generated . tryCombineAll ( Observer , MI , B ) ) return true ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector ( MI ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Target & T , StringRef TT ) {


<s> return DAG . getIntPtrConstant ( <NUM_LIT> * RegInfo -> getSlotSize ( ) ) ;


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> bool isVIS ( ) const { return IsVIS ;


<s> const Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getTargetData ( ) -> getIntPtrType ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ;

Entry . Node = FPtr ; Args . push_back ( Entry ) ;


<s> const std :: vector < MVT > & getLocals ( ) const {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DataLayout ( <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> assert ( AsmPrinterCtor && <STR_LIT> ) ; if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( Out , * this , Fast ) ) ;


<s> return SC ; } if ( VT . isVector ( ) ) return Op ; if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && ( RHSVT == <STR_LIT> || RHSVT == <STR_LIT> ) && ( LHSVT == <STR_LIT> || LHSVT == <STR_LIT> ) ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ; if ( C && C -> getAPIntValue ( ) . isNegative ( ) ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , LHS , RHS , Op . getOperand ( <NUM_LIT> ) ) ; } if ( isSExtFree ( LHS ) || isSExtFree ( RHS ) ) {


<s> MachineBasicBlock * <ISA_LIT>CFGStructurizer :: getLoopLandInfo ( MachineLoop * LoopRep ) const { LoopLandInfoMap :: const_iterator It = LLInfoMap . find ( LoopRep ) ; if ( It == LLInfoMap . end ( ) ) return nullptr ; return ( * It ) . second ;


<s> assert ( Inst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ; MachineOperand Op1 = Inst -> getOperand ( <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) {


<s> void <ISA_LIT>InstPrinter :: printBDRAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { unsigned Base = MI -> getOperand ( OpNum ) . getReg ( ) ; uint64_t Disp = MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ; unsigned Length = MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) ; O << Disp << <STR_LIT> << getRegisterName ( Length ) ;

if ( Base ) O << <STR_LIT> << getRegisterName ( Base ) ;


<s> <ISA_LIT>AddressSanitizer ( MCSubtargetInfo & sti ) : STI ( sti ) {


<s> case 'i' : mmix_output_shiftvalue_op_from_str ( stream , <STR_LIT> , ( uint64_t ) mmix_intval ( x ) ) ; return ; case 'o' : mmix_output_shiftvalue_op_from_str ( stream , <STR_LIT> , ( uint64_t ) mmix_intval ( x ) ) ; return ; case 's' : mmix_output_shiftvalue_op_from_str ( stream , <STR_LIT> , ( uint64_t ) mmix_intval ( x ) ) ; return ; case 'd' : case 'D' : mmix_output_condition ( stream , x , ( code == 'D' ) ) ; return ; case 'e' : if ( TARGET_FCMP_EPSILON ) fprintf ( stream , <STR_LIT> ) ; return ; case 'm' : if ( GET_CODE ( x ) != CONST_INT ) { fatal_insn ( <STR_LIT> , x ) ; } fprintf ( stream , <STR_LIT> PRId64 , ( int64_t ) ( mmix_intval ( x ) - <NUM_LIT> ) ) ; return ; case 'r' : if ( ! REG_P ( x ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_destination_register = MMIX_OUTPUT_REGNO ( regno ) ; return ; case 'I' : if ( GET_CODE ( x ) != CONST_INT && ( GET_CODE ( x ) != CONST_DOUBLE || ( GET_MODE ( x ) != VOIDmode && GET_MODE ( x ) != DFmode && GET_MODE ( x ) != SFmode ) ) ) fatal_insn ( <STR_LIT> , x ) ; mmix_output_register_setting ( stream , mmix_output_destination_register , mmix_intval ( x ) , <NUM_LIT> ) ; return ; case 'U' : if ( TARGET_ZERO_EXTEND ) putc ( 'U' , stream ) ; return ; case 'v' : mmix_output_shifted_value ( stream , ( int64_t ) mmix_intval ( x ) ) ; return ; case 'V' : mmix_output_shifted_value ( stream , ( int64_t ) ~ mmix_intval ( x ) ) ; return ; case 'W' : if ( GET_CODE ( x ) != CONST_INT ) fatal_insn ( <STR_LIT> , x ) ; fprintf ( stream , <STR_LIT> , ( int ) ( INTVAL ( x ) & <NUM_LIT> ) ) ; return ;


<s> if ( MO . isImm ( ) ) return isInlineConstant ( APInt ( <NUM_LIT> , MO . getImm ( ) , true ) ) ; if ( MO . isFPImm ( ) ) { APFloat FpImm = MO . getFPImm ( ) -> getValueAPF ( ) ;

return isInlineConstant ( FpImm . bitcastToAPInt ( ) ) ;


<s> for ( MachineBasicBlock :: iterator I = BegBB , E = EndBB ; I != E ; ) { MachineInstr & MI = * I ; ++ I ; if ( ! MI . isPseudo ( ) || <ISA_LIT>II :: isLoopInst ( MI . getDesc ( ) ) ) { for ( int j = <NUM_LIT> ; j < numPreNops ; ++ j ) { TII -> insertNoop ( MBB , MachineBasicBlock :: iterator ( MI ) ) ; }


<s> return ; case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; return ; case MachineOperand :: MO_ExternalSymbol : { if ( TM . getRelocationModel ( ) == Reloc :: Static ) { O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; return ; } MCSymbol * NLPSym = OutContext . GetOrCreateSymbol ( StringRef ( MAI -> getGlobalPrefix ( ) ) + MO . getSymbolName ( ) + <STR_LIT> ) ; MCSymbol * & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( NLPSym ) ; if ( StubSym == <NUM_LIT> ) StubSym = GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; O << * NLPSym ; return ; } case MachineOperand :: MO_GlobalAddress : { GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * SymToPrint ; if ( TM . getRelocationModel ( ) != Reloc :: Static && ( GV -> isDeclaration ( ) || GV -> isWeakForLinker ( ) ) ) { if ( ! GV -> hasHiddenVisibility ( ) ) { SymToPrint = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ;

MCSymbol * & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( SymToPrint ) ;


<s> Type * Params [ ] = { IRB . getInt32Ty ( ) , IRB . getInt32Ty ( ) } ; FunctionType * FTy = FunctionType :: get ( IRB . getVoidTy ( ) , Params , false ) ; Function * F = Function :: Create ( FTy , GlobalValue :: ExternalLinkage , SetThrewFName , & M ) ; Argument * Arg1 = & * ( F -> arg_begin ( ) ) ; Argument * Arg2 = & * ( ++ F -> arg_begin ( ) ) ; Arg1 -> setName ( <STR_LIT> ) ; Arg2 -> setName ( <STR_LIT> ) ; BasicBlock * EntryBB = BasicBlock :: Create ( C , <STR_LIT> , F ) ; BasicBlock * ThenBB = BasicBlock :: Create ( C , <STR_LIT> , F ) ; BasicBlock * EndBB = BasicBlock :: Create ( C , <STR_LIT> , F ) ; IRB . SetInsertPoint ( EntryBB ) ; Value * Threw = IRB . CreateLoad ( ThrewGV , ThrewGV -> getName ( ) + <STR_LIT> ) ; Value * Cmp = IRB . CreateICmpEQ ( Threw , IRB . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; IRB . CreateCondBr ( Cmp , ThenBB , EndBB ) ; IRB . SetInsertPoint ( ThenBB ) ;


<s> if ( ! V0EltVT . isInteger ( ) ) return SDValue ( ) ; const unsigned EltSize = EltVT . getSizeInBits ( ) ; const unsigned V0EltSize = V0EltVT . getSizeInBits ( ) ; if ( V0EltSize <= EltSize ) return SDValue ( ) ; assert ( ( ( V0EltSize % EltSize ) == <NUM_LIT> ) && <STR_LIT> ) ; const unsigned V0Opc = V0 . getOpcode ( ) ; const unsigned Scale = V0EltSize / EltSize ; const unsigned V0BroadcastIdx = BroadcastIdx / Scale ; if ( ( V0Opc != <STR_LIT> || V0BroadcastIdx != <NUM_LIT> ) && V0Opc != <STR_LIT> ) return SDValue ( ) ; SDValue Scalar = V0 . getOperand ( V0BroadcastIdx ) ; if ( const int OffsetIdx = BroadcastIdx % Scale ) Scalar = DAG . getNode ( <STR_LIT> , DL , Scalar . getValueType ( ) , Scalar , DAG . getConstant ( OffsetIdx * EltSize , DL , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , EltVT , Scalar ) ) ;


<s> if ( STI . splitFramePushPop ( ) ) { GPRCS2Size += <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; GPRCS1Size += <NUM_LIT> ; break ; default : DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; } unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; int FramePtrOffsetInBlock = <NUM_LIT> ; unsigned adjustedGPRCS1Size = GPRCS1Size ; if ( tryFoldSPUpdateIntoPushPop ( STI , MF , & * std :: prev ( MBBI ) , NumBytes ) ) { FramePtrOffsetInBlock = NumBytes ; adjustedGPRCS1Size += NumBytes ; NumBytes = <NUM_LIT> ; } if ( adjustedGPRCS1Size ) { CFAOffset -= adjustedGPRCS1Size ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { unsigned Reg = I -> getReg ( ) ; int FI = I -> getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( STI . splitFramePushPop ( ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , MFI -> getObjectOffset ( FI ) ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; break ; } } if ( HasFP ) { FramePtrOffsetInBlock += MFI -> getObjectOffset ( FramePtrSpillFI ) + GPRCS1Size + ArgRegsSaveSize ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addReg ( <STR_LIT> ) . addImm ( FramePtrOffsetInBlock / <NUM_LIT> ) . setMIFlags ( MachineInstr :: FrameSetup ) ) ;


<s> EVT VT = TLI -> getValueType ( DL , DataType ) ; return TLI -> isOperationLegalOrCustom ( IsSigned ? <STR_LIT> : <STR_LIT> , VT ) ;


<s> void <ISA_LIT>CodeEmitter :: emitNEON2RegInstruction ( const MachineInstr & MI ) { const TargetInstrDesc & TID = MI . getDesc ( ) ;

unsigned Binary = getBinaryCodeForInstr ( MI ) ;


<s> auto SysReg = <STR_LIT> ( Imm ) ; if ( SysReg && SysReg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) O << SysReg -> Name ;


<s> return <NUM_LIT> * NumLoads ; } unsigned Cost = VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ? FloatFactor : <NUM_LIT> ; Alignment = std :: min ( Alignment , <NUM_LIT> ) ; unsigned AlignWidth = <NUM_LIT> * std :: max ( <NUM_LIT> , Alignment ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; if ( Alignment == <NUM_LIT> || Alignment == <NUM_LIT> ) return Cost * NumLoads ; unsigned LogA = Log2_32 ( Alignment ) ; return ( <NUM_LIT> - LogA ) * Cost * NumLoads ; } return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , I ) ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MachineInstr & Old = * I ; DebugLoc DL = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != <NUM_LIT> ) { unsigned Opc = Old . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } else { assert ( Opc == <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } }


<s> SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; static const unsigned OpcMap [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; unsigned Opc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ; unsigned CarryOpc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ; SDNode * AddLo ; if ( ! ConsumeCarry ) { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( Opc , DL , VTList , Args ) ; } else { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , Args ) ;


<s> <STR_LIT> , <STR_LIT> } } ; size_t i ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( shell_commands ) ; i ++ ) if ( strcmp ( shell_commands [ i ] [ <NUM_LIT> ] , shell_name + <NUM_LIT> ) == <NUM_LIT> ) { fnotice ( stderr , <STR_LIT> , shell_commands [ i ] [ <NUM_LIT> ] ) ; } } if ( global_dc -> abort_on_error ) fancy_abort ( __FILE__ , __LINE__ , __FUNCTION__ ) ; exit ( FATAL_EXIT_CODE ) ; } fprintf ( stderr , <STR_LIT> , uc -> uc_mcontext -> MC_FLD ( es ) . MC_FLD ( dar ) , uc -> uc_mcontext -> MC_FLD ( ss ) . MC_FLD ( srr0 ) ) ;


<s> rtx src_addr ; rtx dest_addr ; rtx src_mem ; rtx dest_mem ; rtx tmp_reg ; rtx stores [ MAX_MOVE_REG ] ; int move_bytes ; enum machine_mode mode ; if ( ! constp ) return FALSE ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= <NUM_LIT> ) return TRUE ; if ( bytes > TOTAL_MOVE_REG * align ) return FALSE ; dest_reg = copy_addr_to_reg ( XEXP ( orig_dest , <NUM_LIT> ) ) ; src_reg = copy_addr_to_reg ( XEXP ( orig_src , <NUM_LIT> ) ) ; num_reg = offset = <NUM_LIT> ; for ( ; bytes > <NUM_LIT> ; ( bytes -= move_bytes ) , ( offset += move_bytes ) ) { if ( offset == <NUM_LIT> ) {


<s> bool Modified = false ; MachineBasicBlock :: instr_iterator NextMII ; for ( MachineBasicBlock :: instr_iterator MII = MBB . instr_begin ( ) , E = MBB . instr_end ( ) ; MII != E ; MII = NextMII ) { NextMII = next_nodbg ( MII , E ) ; if ( NextMII != E && isFirstMul ( * MII ) && isSecondMulOrBranch ( * NextMII ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; const MCInstrDesc & NewMCID = <ISA_LIT>II . get ( <STR_LIT> ) ; BuildMI ( MBB , NextMII , DebugLoc ( ) , NewMCID ) ; Modified = true ; }


<s> bool <ISA_LIT>Subtarget :: hasSinCos ( ) const {

return getTargetTriple ( ) . isiOS ( ) && ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) <STR_LIT> :: write < uint64_t > ( OS , <NUM_LIT> , Endian ) ; return true ;


<s> if ( Values . size ( ) == <NUM_LIT> ) return Values [ <NUM_LIT> ] ; Value * NewVal = UndefValue :: get ( Ty ) ; for ( int I = <NUM_LIT> , E = Values . size ( ) ; I != E ; ++ I ) NewVal = Builder . CreateInsertElement ( NewVal , Values [ I ] , I ) ; return NewVal ;


<s> void <ISA_LIT>InstPrinter :: printFCCOperand ( const MCInst * MI , int opNum , raw_ostream & O ) {

const MCOperand & MO = MI -> getOperand ( opNum ) ;


<s> int pic_reg_used = flag_pic && ( crtl -> uses_pic_offset_table | crtl -> profile ) ; var_size = M32R_STACK_ALIGN ( size ) ; args_size = M32R_STACK_ALIGN ( crtl -> outgoing_args_size ) ; pretend_size = crtl -> args . pretend_args_size ; extra_size = FIRST_PARM_OFFSET ( <NUM_LIT> ) ; total_size = extra_size + pretend_size + args_size + var_size ; reg_size = <NUM_LIT> ; gmask = <NUM_LIT> ; fn_type = m32r_compute_function_type ( current_function_decl ) ; interrupt_p = M32R_INTERRUPT_P ( fn_type ) ; for ( regno = <NUM_LIT> ; regno < M32R_MAX_INT_REGS ; regno ++ ) { if ( MUST_SAVE_REGISTER ( regno , interrupt_p ) || ( regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used ) ) {


<s> const DebugLoc & DL = RetI . getDebugLoc ( ) ; MachineBasicBlock * ClearBB , * DoneBB ; if ( STI -> hasMinSize ( ) ) { ClearBB = DoneBB = & MBB ; } else { MachineFunction * MF = MBB . getParent ( ) ; ClearBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , ClearBB ) ; MF -> insert ( ++ ClearBB -> getIterator ( ) , DoneBB ) ; DoneBB -> splice ( DoneBB -> end ( ) , & MBB , MBBI , MBB . end ( ) ) ; DoneBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( ClearBB ) ; MBB . addSuccessor ( DoneBB ) ; ClearBB -> addSuccessor ( DoneBB ) ; for ( const MachineOperand & Op : RetI . operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) continue ; assert ( Register :: isPhysicalRegister ( Reg ) && <STR_LIT> ) ; ClearBB -> addLiveIn ( Reg ) ; DoneBB -> addLiveIn ( Reg ) ; } ClearBB -> addLiveIn ( <STR_LIT> ) ; DoneBB -> addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , MBB . end ( ) , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBB . end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( MBB , MBB . end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } for ( unsigned D = <NUM_LIT> ; D < <NUM_LIT> ; D ++ ) { if ( ClearRegs [ D * <NUM_LIT> + <NUM_LIT> ] && ClearRegs [ D * <NUM_LIT> + <NUM_LIT> ] ) { unsigned Reg = <STR_LIT> + D ; BuildMI ( ClearBB , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else { if ( ClearRegs [ D * <NUM_LIT> + <NUM_LIT> ] ) { unsigned Reg = <STR_LIT> + D * <NUM_LIT> ; BuildMI ( ClearBB , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; }


<s> if ( ST . getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return <NUM_LIT> ; std :: set < unsigned > ClauseDefs ; std :: set < unsigned > ClauseUses ; for ( MachineInstr * MI : EmittedInstrs ) { if ( ! MI || ! <ISA_LIT>InstrInfo :: isSMRD ( * MI ) ) break ; addRegsToSet ( MI -> defs ( ) , ClauseDefs ) ; addRegsToSet ( MI -> uses ( ) , ClauseUses ) ; } if ( ClauseDefs . empty ( ) ) return <NUM_LIT> ; if ( SMEM -> mayStore ( ) ) return <NUM_LIT> ; addRegsToSet ( SMEM -> defs ( ) , ClauseDefs ) ; addRegsToSet ( SMEM -> uses ( ) , ClauseUses ) ;

std :: vector < unsigned > Result ( std :: max ( ClauseDefs . size ( ) , ClauseUses . size ( ) ) ) ;


<s> bool isBarriernXS ( ) const { return Kind == k_Barrier && getBarriernXSModifier ( ) ;


<s> int ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { OS << ( char ) ( Bits >> ShiftValue ) ; Bits <<= <NUM_LIT> ; } ++ MCNumEmitted ;


<s> return ( __m256bh ) __builtin_ia32_cvtne2ps2bf16_v16hi ( __A , __B ) ;


<s> static fixed_size_mode mips_get_reg_raw_mode ( int regno ) {

if ( TARGET_FLOATXX && FP_REG_P ( regno ) ) return DFmode ;


<s> rtx op0 = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; rtx op2 = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( op1 ) && op2 == const0_rtx && CONST_INT_P ( XEXP ( op0 , <NUM_LIT> ) ) && aarch64_is_extend_from_extract ( mode , XEXP ( op0 , <NUM_LIT> ) , op1 ) ) {


<s> if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isPICBase = false ; for ( MachineRegisterInfo :: def_iterator I = MRI . def_begin ( BaseReg ) , E = MRI . def_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = I . getOperand ( ) . getParent ( ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase && <STR_LIT> ) ; isPICBase = true ; } return isPICBase ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) return true ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( BaseReg == <NUM_LIT> ) return true ;


<s> break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED :


<s> bool isMemoryUnscaled ( ) const { if ( ! isMem ( ) ) return false ; if ( Mem . Mode != ImmediateOffset ) return false ; if ( ! Mem . OffsetImm ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Mem . OffsetImm ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( Value >= - <NUM_LIT> && Value < <NUM_LIT> ) ;


<s> if ( isSingleSpacedVectorList ( ) ) return false ; return ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( VectorList . RegNum ) ) ;


<s> errs ( ) << <STR_LIT> << Base . FrameIndex << '\n' ; } errs ( ) << <STR_LIT> << Disp << '\n' ; if ( GV ) { errs ( ) << <STR_LIT> ; GV -> dump ( ) ; } else if ( CP ) { errs ( ) << <STR_LIT> ; CP -> dump ( ) ; errs ( ) << <STR_LIT> << Align << '\n' ; } else if ( ES ) { errs ( ) << <STR_LIT> ; errs ( ) << ES << '\n' ;

} else if ( JT != - <NUM_LIT> ) errs ( ) << <STR_LIT> << JT << <STR_LIT> << Align << '\n' ;


<s> Triple TheTriple ( TT ) ; AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ;


<s> unsigned HOST_WIDE_INT temp , op ; if ( op_const == <NUM_LIT> ) return NULL ;


<s> if ( GET_CODE ( x ) == LO_SUM ) iter . skip_subrtxes ( ) ; else if ( small_symbolic_operand ( x , Pmode ) ) return true ;


<s> BlockInformation ( ) : IsRetired ( false ) , SccNum ( INVALIDSCCNUM ) {


<s> if ( ! Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) ) return Op ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isVShiftLImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) { unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; } unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue NegShift = DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ;

SDValue NegShiftLeft = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Opc , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , NegShift ) ;


<s> } for ( auto const & P : LISLR ) { auto I = TrackedLR . find ( P . first ) ; if ( I == TrackedLR . end ( ) ) { dbgs ( ) << <STR_LIT> << PrintReg ( P . first , TRI ) << <STR_LIT> << PrintLaneMask ( P . second ) << <STR_LIT> ; }


<s> BitsToCheck |= ~ Constant & ( <NUM_LIT> << <NUM_LIT> * i ) ; } } } if ( BitsToCheck && ! CurDAG -> MaskedValueIsZero ( LHS , APInt ( LHS . getValueSizeInBits ( ) , BitsToCheck ) ) ) return <NUM_LIT> ;


<s> Type = ELF :: R_<ISA_LIT>_THM_JUMP24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_TLSCALL : Type = ELF :: R_<ISA_LIT>_THM_TLS_CALL ; break ; default : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS8 ; break ; } break ; case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS16 ; break ; } break ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : Type = ELF :: R_<ISA_LIT>_NONE ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_GOT_BREL ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL : Type = ELF :: R_<ISA_LIT>_GOT_PREL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ;

case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 :


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeImm ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { if ( isa < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) ) { return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( Fixup ) ; Fixups . push_back ( MCFixup :: create ( Offset , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ;


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ;


<s> extern __inline __m256i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_i32gather_epi32 ( int const * base , __m256i index , const int scale ) { __v8si src = __extension__ ( __v8si ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v8si mask = __extension__ ( __v8si ) { ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> } ; return ( __m256i ) __builtin_ia32_gathersiv8si ( src , base , ( __v8si ) index , mask , scale ) ;


<s> weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ;


<s> return CallsEhReturn && ( FI == EhDataRegFI [ <NUM_LIT> ] || FI == EhDataRegFI [ <NUM_LIT> ] ) ;


<s> void <ISA_LIT>InstrInfo :: legalizeGenericOperand ( MachineBasicBlock & InsertMBB , MachineBasicBlock :: iterator I , const TargetRegisterClass * DstRC , MachineOperand & Op , MachineRegisterInfo & MRI , const DebugLoc & DL ) const { unsigned OpReg = Op . getReg ( ) ; unsigned OpSubReg = Op . getSubReg ( ) ; const TargetRegisterClass * OpRC = RI . getSubClassWithSubReg ( RI . getRegClassForReg ( MRI , OpReg ) , OpSubReg ) ; if ( DstRC == OpRC ) return ; unsigned DstReg = MRI . createVirtualRegister ( DstRC ) ; MachineInstr * Copy = BuildMI ( InsertMBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addOperand ( Op ) ; Op . setReg ( DstReg ) ; Op . setSubReg ( <NUM_LIT> ) ; MachineInstr * Def = MRI . getVRegDef ( OpReg ) ; if ( ! Def ) return ;

if ( Def -> isMoveImmediate ( ) ) FoldImmediate ( * Copy , * Def , OpReg , & MRI ) ;


<s> bool isVecListFourQHWordIndexed ( ) const {

if ( ! isDoubleSpacedVectorIndexed ( ) ) return false ;


<s> bool <ISA_LIT>TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const {

const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ;


<s> if ( Name . endswith ( <STR_LIT> ) ) { Mnemonic = Name . substr ( <NUM_LIT> , Name . size ( ) - <NUM_LIT> ) ; IsBRR = true ; } if ( Mnemonic [ <NUM_LIT> ] == 'b' || ( Mnemonic [ <NUM_LIT> ] == 's' && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ) ) { LPCC :: CondCode CondCode = LPCC :: suffixTo<ISA_LIT>CondCode ( Mnemonic . substr ( <NUM_LIT> , Next ) ) ; if ( CondCode != LPCC :: UNKNOWN ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , <NUM_LIT> ) ; Operands -> push_back ( <STR_LIT> ( Mnemonic , NameLoc ) ) ; Operands -> push_back ( <STR_LIT> ( MCConstantExpr :: create ( CondCode , getContext ( ) ) , NameLoc , NameLoc ) ) ;


<s> unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; bool Upper = IdxVal >= NumElems / <NUM_LIT> ; Vec = Extract128BitVector ( Vec , DAG . getConstant ( Upper ? NumElems / <NUM_LIT> : <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , Upper ? DAG . getConstant ( IdxVal - NumElems / <NUM_LIT> , <STR_LIT> ) : Idx ) ; } assert ( Vec . getValueSizeInBits ( ) <= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget -> hasSSE41orAVX ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ;

} else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) {


<s> static inline int getFP32Imm ( const APFloat & FPImm ) { return getFP32Imm ( FPImm . bitcastToAPInt ( ) ) ;


return ( __m256d ) __builtin_ia32_cvtudq2pd256_mask ( ( __v4si ) __A , ( __v4df ) _mm256_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> if ( isa < MCSymbolRefExpr > ( Disp ) && ! Info . IsVarDecl ) { unsigned RegNo = is64BitMode ( ) ? <STR_LIT> : <STR_LIT> ; return <STR_LIT> ( RegNo , Start , End , true , SMLoc ( ) , Identifier , Info . OpDecl ) ; } const MCBinaryExpr * BinOp = dyn_cast < MCBinaryExpr > ( Disp ) ; bool IsSymRef = isa < MCSymbolRefExpr > ( BinOp ? BinOp -> getLHS ( ) : Disp ) ; if ( IsSymRef ) {


<s> void DecodeScalarMoveMask ( MVT VT , bool IsLoad , SmallVectorImpl < int > & Mask ) {

unsigned NumElts = VT . getVectorNumElements ( ) ;


<s> int bytes_left , size ; if ( * cum >= <NUM_LIT> ) return <NUM_LIT> ; if ( ft32_pass_by_reference ( cum_v , arg ) ) size = <NUM_LIT> ; else if ( arg . type ) { if ( AGGREGATE_TYPE_P ( arg . type ) ) return <NUM_LIT> ; size = int_size_in_bytes ( arg . type ) ; } else size = GET_MODE_SIZE ( arg . mode ) ; bytes_left = ( <NUM_LIT> * <NUM_LIT> ) - ( ( * cum - <NUM_LIT> ) * <NUM_LIT> ) ; if ( size > bytes_left ) return bytes_left ;


<s> static bool loongarch_valid_pointer_mode ( scalar_int_mode mode ) {

return mode == SImode || ( TARGET_64BIT && mode == DImode ) ;


<s> unsigned sign1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned sign2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( sign1 != sign2 ) return MCDisassembler :: Fail ; const unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; DecodeStatus S = DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ; unsigned Val = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;

Val |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ;


<s> LLVM_DEBUG ( llvm :: dbgs ( ) << <STR_LIT> ) ;


<s> shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;

shmask . i [ ( ( si_to_uint ( a ) + ( unsigned int ) ( imm ) ) >> <NUM_LIT> ) & <NUM_LIT> ] = <NUM_LIT> ;


<s> { LatenciesAlone , BlockRegUsageLatency } , { LatenciesGrouped , BlockLatencyRegUsage } , { LatenciesAlonePlusConsecutive , BlockLatencyRegUsage } , } ; for ( std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > v : Variants ) { Temp = Scheduler . scheduleVariant ( v . first , v . second ) ; if ( Temp . MaxVGPRUsage < Best . MaxVGPRUsage ) Best = Temp ; } } if ( Best . MaxVGPRUsage > <NUM_LIT> ) { static const std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > Variants [ ] = { { LatenciesAlone , BlockRegUsage } , { LatenciesGrouped , BlockRegUsageLatency } , { LatenciesGrouped , BlockRegUsage } , { LatenciesAlonePlusConsecutive , BlockRegUsageLatency } , { LatenciesAlonePlusConsecutive , BlockRegUsage } } ; for ( std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > v : Variants ) { Temp = Scheduler . scheduleVariant ( v . first , v . second ) ; if ( Temp . MaxVGPRUsage < Best . MaxVGPRUsage ) Best = Temp ; } } ScheduledSUnits = Best . SUs ; ScheduledSUnitsInv . resize ( SUnits . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ( unsigned ) SUnits . size ( ) ; i != e ; ++ i ) { ScheduledSUnitsInv [ ScheduledSUnits [ i ] ] = i ; } moveLowLatencies ( ) ; assert ( TopRPTracker . getPos ( ) == RegionBegin && <STR_LIT> ) ; TopRPTracker . setPos ( CurrentTop ) ; for ( std :: vector < unsigned > :: iterator I = ScheduledSUnits . begin ( ) , E = ScheduledSUnits . end ( ) ; I != E ; ++ I ) { SUnit * SU = & SUnits [ * I ] ; scheduleMI ( SU , true ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> << * SU -> getInstr ( ) ) ; } assert ( CurrentTop == CurrentBottom && <STR_LIT> ) ; placeDebugValues ( ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << printMBBReference ( * begin ( ) -> getParent ( ) ) << <STR_LIT> ; dumpSchedule ( ) ; dbgs ( ) << '\n' ;


<s> SMLoc EndLoc = SMLoc :: getFromPointer ( Loc . getPointer ( ) + Str . size ( ) ) ; auto Res = std :: make_unique < <ISA_LIT>Operand > ( Token , Loc , EndLoc ) ; Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length = Str . size ( ) ; return Res ;


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Parser . eatToEndOfStatement ( ) ; Error ( L , <STR_LIT> ) ; return false ; } RegisterReqs . erase ( Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ) ; Parser . Lex ( ) ;


<s> return <ISA_LIT>Operand :: CreateImm ( this , <NUM_LIT> , SMLoc ( ) , <ISA_LIT>Operand :: ImmTyOffset ) ;


<s> unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; bool emit_frame_chain = cfun -> machine -> frame . emit_frame_chain ; rtx_insn * insn ; if ( flag_stack_clash_protection && known_eq ( callee_adjust , <NUM_LIT> ) ) { initial_adjust += sve_callee_adjust ; sve_callee_adjust = <NUM_LIT> ; } if ( aarch64_return_address_signing_enabled ( ) ) { switch ( aarch64_ra_sign_key ) { case AARCH64_KEY_A : insn = emit_insn ( gen_paciasp ( ) ) ; break ; case AARCH64_KEY_B : insn = emit_insn ( gen_pacibsp ( ) ) ; break ; default : gcc_unreachable ( ) ; } add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( flag_stack_usage_info ) current_function_static_stack_size = constant_lower_bound ( frame_size ) ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( maybe_gt ( frame_size , PROBE_INTERVAL ) && maybe_gt ( frame_size , get_stack_check_protect ( ) ) ) aarch64_emit_probe_stack_range ( get_stack_check_protect ( ) , ( frame_size - get_stack_check_protect ( ) ) ) ; } else if ( maybe_gt ( frame_size , <NUM_LIT> ) ) aarch64_emit_probe_stack_range ( get_stack_check_protect ( ) , frame_size ) ; } rtx tmp0_rtx = gen_rtx_REG ( Pmode , EP0_REGNUM ) ; rtx tmp1_rtx = gen_rtx_REG ( Pmode , EP1_REGNUM ) ; gcc_assert ( known_eq ( initial_adjust , <NUM_LIT> ) || callee_adjust == <NUM_LIT> ) ; aarch64_allocate_and_probe_stack_space ( tmp0_rtx , tmp1_rtx , initial_adjust , true , false ) ; if ( callee_adjust != <NUM_LIT> ) aarch64_push_regs ( reg1 , reg2 , callee_adjust ) ; poly_int64 chain_offset = ( initial_adjust + callee_adjust - cfun -> machine -> frame . hard_fp_offset ) ; gcc_assert ( known_ge ( chain_offset , <NUM_LIT> ) ) ;


<s> bool <STR_LIT> ( SDNode * N , bool isUnary ) { if ( ! isUnary ) { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getOperand ( i ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getOperand ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getOperand ( i ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getOperand ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getOperand ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) || ! isConstantOrUndef ( N -> getOperand ( i + <NUM_LIT> ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ;


<s> MachineInstr * NewMI = MF . CreateMachineInstr ( TII . get ( Opcode ) , MI -> getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , NewMI ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( i == OpNo ) { assert ( MO . isReg ( ) && <STR_LIT> ) ; addOperands ( MIB , MOs , PtrOffset ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ;


<s> virtual void PrintSwitchToSection ( const MCAsmInfo & MAI , raw_ostream & OS , const MCExpr * Subsection ) const {


<s> assert ( ( I . getOpcode ( ) == TargetOpcode :: G_BRCOND ) && <STR_LIT> ) ; const unsigned CondReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineInstr & TestInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( DestMBB ) . addImm ( <STR_LIT> ) ;

constrainSelectedInstRegOperands ( TestInst , TII , TRI , RBI ) ;


<s> if ( Subtarget -> isAAPCS_ABI ( ) && NSAAOffset != <NUM_LIT> && size > excess ) { while ( State -> AllocateReg ( GPRArgRegs , <NUM_LIT> ) ) ; return ; } unsigned ByValRegBegin = reg ; unsigned ByValRegEnd = ( size < excess ) ? reg + size / <NUM_LIT> : ( unsigned ) <STR_LIT> ; State -> addInRegsParamInfo ( ByValRegBegin , ByValRegEnd ) ; for ( unsigned i = reg + <NUM_LIT> ; i != ByValRegEnd ; ++ i ) State -> AllocateReg ( GPRArgRegs , <NUM_LIT> ) ; if ( size < excess ) size = <NUM_LIT> ; else size -= excess ;


<s> bool <ISA_LIT>InstrInfo :: DefinesPredicate ( MachineInstr * MI , std :: vector < MachineOperand > & Pred ) const { return isPredicateSetter ( MI -> getOpcode ( ) ) ;


<s> assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) { Opc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } } else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return ;


<s> else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> ishtmcr = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> ismma = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isquad = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> ispair = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> ismmaint = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isno32bit = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> is32bit = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> iscpu = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isldstmask = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> islxvrse = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> islxvrze = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isendian = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isibmld = <NUM_LIT> ; else if ( ! strcmp ( attrname , <STR_LIT> ) ) attrptr -> isibm128 = <NUM_LIT> ; else {


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;

RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


<s> bool <ISA_LIT>TTIImpl :: isLegalToVectorizeStoreChain ( unsigned ChainSizeInBytes , unsigned Alignment , unsigned AddrSpace ) const {

return isLegalToVectorizeMemChain ( ChainSizeInBytes , Alignment , AddrSpace ) ;


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI , Register SwiftErrorVReg ) const { assert ( VRegs . size ( ) < <NUM_LIT> && <STR_LIT> ) ; if ( Val ) { const auto & STI = MIRBuilder . getMF ( ) . getSubtarget ( ) ; return MIRBuilder . buildInstr ( <STR_LIT> ) . addUse ( VRegs [ <NUM_LIT> ] ) . constrainAllUses ( MIRBuilder . getTII ( ) , * STI . getRegisterInfo ( ) , * STI . getRegBankInfo ( ) ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ;

return resolveCrossBlockLatency ( MBB , & MBB , topdown , deep , <NUM_LIT> , check_only , ignore_loop_instr , ProcessedBB ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;

SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> TM = & TPC -> getTM < TargetMachine > ( ) ; } if ( ! <STR_LIT> ( F . getCallingConv ( ) ) ) return false ;

return <ISA_LIT>PropagateAttributes ( TM , false ) . process ( F ) ;


<s> mips_emit_move ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; if ( Pmode == DImode ) emit_jump_insn ( gen_cbranchdi4 ( test , src_reg , final_src , label ) ) ; else emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ;

if ( leftover ) mips_block_move_straight ( dest , src , leftover ) ;


<s> if ( STI . getFeatureBits ( ) [ Feature ] ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString ) ) ) ;


<s> case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op , DAG ) ; case <STR_LIT> : return LowerVectorOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> :


<s> if ( offset < <NUM_LIT> ) { if ( offset > - <NUM_LIT> ) insn = emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( offset ) ) ) ; else { rtx tmpr = gen_rtx_REG ( DImode , <NUM_LIT> ) ; RTX_FRAME_RELATED_P ( emit_move_insn ( tmpr , GEN_INT ( offset ) ) ) = <NUM_LIT> ; insn = emit_insn ( gen_adddi3 ( stack_pointer_rtx , stack_pointer_rtx , tmpr ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false ;


<s> return <ISA_LIT>_MERGE_BASE_OFFSET_NAME ;


<s> FunctionPass * create<ISA_LIT>DelaySlotFiller ( ) { return new <ISA_LIT>DelaySlotFiller ( ) ;


<s> if ( ! Copy -> isCopy ( ) ) return Copy ; unsigned CopySrc = Copy -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Subreg = Copy -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( CopySrc ) ) { const TargetRegisterInfo * TRI = & TII -> getRegisterInfo ( ) ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; if ( CopySrc == <STR_LIT> || CopySrc == <STR_LIT> ) Subreg = <STR_LIT> ; MachineBasicBlock :: iterator Me = Copy , B = Copy -> getParent ( ) -> begin ( ) ;

while ( Me != B ) if ( ( -- Me ) -> modifiesRegister ( CopySrc , TRI ) ) return & * Me ;


<s> if ( S != MCDisassembler :: Success ) return Decode2OpInstructionFail ( Inst , Insn , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ;

DecodeBitpOperand ( Inst , Op2 , Address , Decoder ) ;


<s> for ( const MachineInstr & UseInst : MRI -> use_nodbg_instructions ( VirtReg ) ) { if ( UseInst . getParent ( ) != MBB ) { MayLiveAcrossBlocks . set ( Register :: virtReg2Index ( VirtReg ) ) ; return true ;


<s> if ( ! TM . Options . UseSoftFloat ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( ! Subtarget -> isSingleFloat ( ) ) { if ( Has<ISA_LIT>64 ) addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; else addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; computeRegisterProperties ( ) ;


<s> MBB . addLiveIn ( it -> getReg ( ) ) ; storeRegToStackSlot ( MBB , MI , it -> getReg ( ) , true , it -> getFrameIdx ( ) , it -> getRegClass ( ) ) ; if ( emitFrameMoves ) { MCSymbol * SaveLabel = MF -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addSym ( SaveLabel ) ; XFI -> getSpillLabels ( ) . push_back ( std :: make_pair ( SaveLabel , * it ) ) ;


<s> static MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym , const AsmPrinter & AP ) { MCContext & Ctx = AP . OutContext ; const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;


<s> static const char * BadConditionCode ( T cc ) { DEBUG ( dbgs ( ) << <STR_LIT> << cc << <STR_LIT> ) ; return <STR_LIT> ;


<s> } if ( isImmU16 ( Value ) ) { int Opcode = isImmU6 ( Value ) ? <STR_LIT> : <STR_LIT> ; return BuildMI ( MBB , MI , dl , get ( Opcode ) , Reg ) . addImm ( Value ) . getInstr ( ) ; } MachineConstantPool * ConstantPool = MBB . getParent ( ) -> getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Value ) ;

unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ;


<s> if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; }


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;

if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> return ( uint64x1_t ) { __builtin_aarch64_usri_ndi_uuus ( __a [ <NUM_LIT> ] , __b [ <NUM_LIT> ] , __c ) } ;


<s> static bool ia64_print_operand_punct_valid_p ( unsigned char code ) { return ( code == '+' || code == ',' ) ;


<s> bool skipSIG = false ; for ( std :: list < MachineBasicBlock * > :: iterator iter = intSkipBlock . begin ( ) ; iter != intSkipBlock . end ( ) ; ++ iter ) { if ( * iter == & ( * MBB ) ) { skipSIG = true ; break ; } } if ( skipSIG ) continue ; DebugLoc DL3 = MBB -> begin ( ) -> getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator startPoint = MBB -> begin ( ) ; MachineBasicBlock :: iterator firstTerminator ; MachineBasicBlock :: iterator I = MBB -> begin ( ) ; for ( MachineBasicBlock :: iterator E = MBB -> end ( ) ; I != E ; ++ I ) { unsigned int opcode = I -> getOpcode ( ) ; if ( I -> isBranch ( ) && ! ( opcode > <NUM_LIT> && opcode < <NUM_LIT> ) ) { break ; } else if ( opcode == <STR_LIT> || opcode == <STR_LIT> || opcode == <STR_LIT> ) { break ; } } firstTerminator = I ; unsigned int count = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) ; I != firstTerminator ; ++ I ) {


<s> void <ISA_LIT>TargetLowering :: emitAtomicCmpXchgNoStoreLLBalance ( IRBuilder < > & Builder ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Builder . CreateCall ( <STR_LIT> ( M , <STR_LIT> ) ) ;