<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) {


<s> case <STR_LIT> : return FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ; case <STR_LIT> : return FirstOpcode == <STR_LIT> || FirstOpcode == <STR_LIT> ; }


<s> if ( Op . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { unsigned Elem = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; GS . add ( Op . getOperand ( <NUM_LIT> ) , Elem ) ; FoundOne = true ; } else if ( Op . isUndef ( ) ) { GS . addUndef ( ) ; } else { GS . add ( SDValue ( ) , ResidueOps . size ( ) ) ; ResidueOps . push_back ( BVN -> getOperand ( I ) ) ; } } if ( ! FoundOne ) return SDValue ( ) ; if ( ! ResidueOps . empty ( ) ) { while ( ResidueOps . size ( ) < NumElements ) ResidueOps . push_back ( DAG . getUNDEF ( ResidueOps [ <NUM_LIT> ] . getValueType ( ) ) ) ; for ( auto & Op : GS . Ops ) { if ( ! Op . getNode ( ) ) { Op = DAG . getBuildVector ( VT , SDLoc ( BVN ) , ResidueOps ) ; break ;


<s> static void emitLEAzii ( MCStreamer & OutStreamer , MCOperand & RS1 , MCOperand & Imm , MCOperand & RD , const MCSubtargetInfo & STI ) { MCInst LEAInst ; LEAInst . setOpcode ( <STR_LIT> ) ; LEAInst . addOperand ( RD ) ; MCOperand CZero = MCOperand :: createImm ( <NUM_LIT> ) ; LEAInst . addOperand ( CZero ) ; LEAInst . addOperand ( RS1 ) ; LEAInst . addOperand ( Imm ) ; OutStreamer . emitInstruction ( LEAInst , STI ) ;


<s> if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << '\n' ) ; if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << '\n' ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; }


<s> RegisterTargetMachine < <ISA_LIT>LETargetMachine > X ( getThe<ISA_LIT>LETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>LETargetMachine > A ( getTheThumbLETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > Y ( getThe<ISA_LIT>BETarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>BETargetMachine > B ( getTheThumbBETarget ( ) ) ; PassRegistry & Registry = * PassRegistry :: getPassRegistry ( ) ;


<s> } if ( isMIMG ( MI ) ) { int VAddr0Idx = <STR_LIT> ( Opc , <STR_LIT> :: vaddr0 ) ; if ( VAddr0Idx < <NUM_LIT> ) return <NUM_LIT> ; int RSrcIdx = <STR_LIT> ( Opc , <STR_LIT> :: srsrc ) ; return <NUM_LIT> + <NUM_LIT> * ( ( RSrcIdx - VAddr0Idx + <NUM_LIT> ) / <NUM_LIT> ) ; } switch ( Opc ) { case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) , & ST ) ; } default : if ( MI . isMetaInstruction ( ) ) return <NUM_LIT> ;


<s> TargetLowering :: ArgListEntry Entry ; for ( const SDValue & Op : Node -> op_values ( ) ) { EVT ArgVT = Op . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Node = Op ; Entry . Ty = ArgTy ; Entry . IsSExt = shouldSignExtendTypeInLibCall ( ArgVT , isSigned ) ; Entry . IsZExt = ! shouldSignExtendTypeInLibCall ( ArgVT , isSigned ) ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DAG . getDataLayout ( ) ) ) ;

EVT RetVT = Node -> getValueType ( <NUM_LIT> ) ;


<s> static NewSense Def ( unsigned PR , bool True , bool Float ) {

NewSense NS = { PR , Float , false , True } ;


<s> const auto * SExt = cast < SExtInst > ( I ) ; const Value * Op = SExt -> getOperand ( <NUM_LIT> ) ; <STR_LIT> From = getSimpleType ( Op -> getType ( ) ) ; <STR_LIT> To = getLegalType ( getSimpleType ( SExt -> getType ( ) ) ) ; Register In = getRegForValue ( Op ) ;


<s> if ( isAllOnesConstant ( Mask ) ) return Op ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( PreservedSrc . isUndef ( ) ) PreservedSrc = getZeroVector ( VT , Subtarget , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , IMask , Op , PreservedSrc ) ;


<s> rtx op0 = nds32_read_argument ( exp , <NUM_LIT> ) ; rtx addr_helper = gen_reg_rtx ( insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ) ; target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , <NUM_LIT> , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , addr_helper ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( pat ) ;


<s> Bid = B ? MAX / countPopulation ( B ) : <NUM_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> void <ISA_LIT>TargetLowering :: emitAtomicCmpXchgNoStoreLLBalance ( IRBuilder < > & Builder ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Builder . CreateCall ( <STR_LIT> ( M , <STR_LIT> ) ) ;


<s> if ( TID . isCall ( ) || TID . isTerminator ( ) || TID . hasUnmodeledSideEffects ( ) ) return false ; if ( isLd && TID . mayStore ( ) ) return false ; if ( ! isLd ) { if ( TID . mayLoad ( ) ) return false ; if ( TID . mayStore ( ) ) return false ; } for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return CSR_RegMask ;


<s> if ( vec_value && i > GET_MODE_SIZE ( GET_MODE ( value ) ) ) destmem = emit_memset ( destmem , destptr , vec_value , i ) ; else destmem = emit_memset ( destmem , destptr , value , i ) ; } else destmem = emit_memmov ( destmem , & srcmem , destptr , srcptr , i ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: get_crbitm_encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ;

assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ;


<s> if ( tls_unspec_mentioned_p ( x ) ) return true ;

if ( csky_symbol_mentioned_p ( x ) || csky_label_mentioned_p ( x ) ) return false ;


<s> assert ( Carry . getOpcode ( ) != <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( IntCCTo<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) , DL , <STR_LIT> ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , Cmp . getValue ( <NUM_LIT> ) , SDValue ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand * VData = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ; buildSpillLoadStore ( MI , <STR_LIT> , Index , VData -> getReg ( ) , VData -> isKill ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) -> getReg ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) -> getReg ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: offset ) -> getImm ( ) , * MI -> memoperands_begin ( ) , RS ) ; MI -> eraseFromParent ( ) ; break ; } default : { const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsMUBUF = TII -> isMUBUF ( * MI ) ; if ( ! IsMUBUF && MFI -> getFrameOffsetReg ( ) != MFI -> getScratchWaveOffsetReg ( ) ) { unsigned DiffReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; bool IsCopy = MI -> getOpcode ( ) == <STR_LIT> ; unsigned ResultReg = IsCopy ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , DiffReg ) . addReg ( MFI -> getFrameOffsetReg ( ) ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) ) ; int64_t Offset = FrameInfo . getObjectOffset ( Index ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , ResultReg ) . addImm ( Log2_32 ( ST . getWavefrontSize ( ) ) ) . addReg ( DiffReg ) ; } else { unsigned ScaledReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , ScaledReg ) . addImm ( Log2_32 ( ST . getWavefrontSize ( ) ) ) . addReg ( DiffReg , RegState :: Kill ) ;


<s> void printGlobalOperand ( const MachineInstr * MI , unsigned OpNo ) {

printOp ( MI -> getOperand ( OpNo ) , false ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> static DecodeStatus Decode3RImmInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Op1 , Op2 , Op3 ; DecodeStatus S = Decode3OpInstruction ( Insn , Op1 , Op2 , Op3 ) ; if ( S == MCDisassembler :: Success ) { Inst . addOperand ( MCOperand :: CreateImm ( Op1 ) ) ; DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op3 , Address , Decoder ) ; } return S ;


<s> SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( <STR_LIT> , Res ) ) ; } unsigned FPOpcode ; switch ( N0 . getOpcode ( ) ) { case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( ! ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue LogicOp0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue LogicOp1 = N0 . getOperand ( <NUM_LIT> ) ; SDLoc DL0 ( N0 ) ; if ( N0 . hasOneUse ( ) && LogicOp0 . getOpcode ( ) == <STR_LIT> && LogicOp0 . hasOneUse ( ) && LogicOp0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && ! isa < ConstantSDNode > ( LogicOp0 . getOperand ( <NUM_LIT> ) ) ) { SDValue CastedOp1 = DAG . getBitcast ( VT , LogicOp1 ) ; return DAG . getNode ( FPOpcode , DL0 , VT , LogicOp0 . getOperand ( <NUM_LIT> ) , CastedOp1 ) ; } if ( N0 . hasOneUse ( ) && LogicOp1 . getOpcode ( ) == <STR_LIT> && LogicOp1 . hasOneUse ( ) && LogicOp1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && ! isa < ConstantSDNode > ( LogicOp1 . getOperand ( <NUM_LIT> ) ) ) { SDValue CastedOp0 = DAG . getBitcast ( VT , LogicOp0 ) ; return DAG . getNode ( FPOpcode , DL0 , VT , LogicOp1 . getOperand ( <NUM_LIT> ) , CastedOp0 ) ; } return SDValue ( ) ;


<s> GPRPad = NumGPRs % ( ( align + <NUM_LIT> ) / <NUM_LIT> ) ; StackPad = StackOffset % align ; unsigned firstGPR = NumGPRs + GPRPad ; switch ( ObjectVT . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( firstGPR < <NUM_LIT> ) NeededGPRs = <NUM_LIT> ; else NeededStackSize = <NUM_LIT> ; break ;


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ;


<s> return <ISA_LIT>ProcFamily == IntelGLM || <ISA_LIT>ProcFamily == IntelGLP || <ISA_LIT>ProcFamily == IntelTRM ;


<s> case <NUM_LIT> : Inst . addOperand ( MCOperand :: CreateImm ( ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) | ( imm << <NUM_LIT> ) | imm ) ) ; break ; } } else { unsigned unrot = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) | <NUM_LIT> ; unsigned rot = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = ( unrot >> rot ) | ( unrot << ( ( <NUM_LIT> - rot ) & <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; } return MCDisassembler :: Success ;


<s> code = ROTATERT ; * amountp = <NUM_LIT> - INTVAL ( XEXP ( op , <NUM_LIT> ) ) ; mnem = <STR_LIT> ; break ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATERT : mnem = arm_shift_nmem ( code ) ; if ( CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) { * amountp = INTVAL ( XEXP ( op , <NUM_LIT> ) ) ; } else if ( REG_P ( XEXP ( op , <NUM_LIT> ) ) ) { * amountp = - <NUM_LIT> ; return mnem ; }


<s> else Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; const MCExpr * Res = <ISA_LIT>MCTargetExpr :: Create ( Sym , <ISA_LIT>MCTargetExpr :: GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO ::

getExprForDwarfGlobalReference ( GV , Mang , MMI , Encoding , Streamer ) ;


<s> case R1_REGNO : return <NUM_LIT> ; case R2_REGNO : return <NUM_LIT> ; case R3_REGNO : return <NUM_LIT> ; case A0_REGNO : return <NUM_LIT> ; case A1_REGNO : return <NUM_LIT> ; case FB_REGNO : return <NUM_LIT> ; case SB_REGNO : return <NUM_LIT> ; case SP_REGNO : return <NUM_LIT> ; case PC_REGNO : return <NUM_LIT> ; default :


<s> if ( DEBUGME ) { errs ( ) << <STR_LIT> ; branchInstr -> dump ( ) ; } spliceEnd = CFGTraits :: getInstrPos ( srcBlk , branchInstr ) ; } if ( DEBUGME ) { errs ( ) << <STR_LIT> << dstBlk -> size ( ) << <STR_LIT> << srcBlk -> size ( ) << <STR_LIT> ; } dstBlk -> splice ( insertPos , srcBlk , srcBlk -> begin ( ) , spliceEnd ) ; if ( DEBUGME ) { errs ( ) << <STR_LIT> << dstBlk -> size ( ) << <STR_LIT> << srcBlk -> size ( ) << <STR_LIT> ; }


<s> continue ; } assert ( MI . getDesc ( ) . getNumDefs ( ) <= <NUM_LIT> ) ; if ( MI . getDesc ( ) . getNumDefs ( ) == <NUM_LIT> ) { unsigned OldReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MFI . isVRegStackified ( OldReg ) ) { const TargetRegisterClass * RC = MRI . getRegClass ( OldReg ) ; unsigned NewReg = MRI . createVirtualRegister ( RC ) ; auto InsertPt = std :: next ( MachineBasicBlock :: iterator ( & MI ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . eraseFromParent ( ) ; Changed = true ; continue ; } if ( UseEmpty [ TargetRegisterInfo :: virtReg2Index ( OldReg ) ] ) { unsigned Opc = getDropOpcode ( RC ) ; MachineInstr * Drop = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( NewReg ) ; Drop -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; } else { unsigned LocalId = getLocalId ( Reg2Local , CurLocal , OldReg ) ; unsigned Opc = getSetLocalOpcode ( RC ) ; BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . addImm ( LocalId ) . addReg ( NewReg ) ; } MI . getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; MI . getOperand ( <NUM_LIT> ) . setIsDead ( false ) ; MFI . stackifyVReg ( NewReg ) ; Changed = true ; } } MachineInstr * InsertPt = & MI ; for ( MachineOperand & MO : reverse ( MI . explicit_uses ( ) ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned OldReg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { assert ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM ) ; unsigned LocalId = getLocalId ( Reg2Local , CurLocal , OldReg ) ; MRI . removeRegOperandFromUseList ( & MO ) ; MO = MachineOperand :: CreateImm ( LocalId ) ; continue ; } if ( MFI . isVRegStackified ( OldReg ) ) { InsertPt = FindStartOfTree ( MO , MRI , MFI ) ; continue ; } if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM ) { unsigned LocalId = getLocalId ( Reg2Local , CurLocal , OldReg ) ;


<s> switch ( mode ) { case E_DFmode : return gen_aarch64_rsqrtedf ; case E_SFmode : return gen_aarch64_rsqrtesf ; case E_V2DFmode : return gen_aarch64_rsqrtev2df ; case E_V2SFmode : return gen_aarch64_rsqrtev2sf ; case E_V4SFmode : return gen_aarch64_rsqrtev4sf ; default : gcc_unreachable ( ) ;


<s> for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) { if ( ! MRI . isPhysRegUsed ( * I ) ) return * I ;


<s> void <ISA_LIT>MCInstrInfo :: tryCompound ( MCInstrInfo const & MCII , MCSubtargetInfo const & STI , MCContext & Context , MCInst & MCI ) { assert ( <ISA_LIT>MCInstrInfo :: isBundle ( MCI ) && <STR_LIT> ) ; if ( MCI . size ( ) < <NUM_LIT> ) return ; bool StartedValid = llvm :: <ISA_LIT>MCShuffle ( Context , false , MCII , STI , MCI ) ; MCInst CheckList ( MCI ) ; while ( lookForCompound ( MCII , Context , CheckList ) ) { MCInst OriginalBundle ( MCI ) ; MCI = CheckList ; if ( StartedValid && ! llvm :: <ISA_LIT>MCShuffle ( Context , false , MCII , STI , MCI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MCI = OriginalBundle ; } }


<s> Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock :

O << * MO . getMBB ( ) -> getSymbol ( ) ;


<s> if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_ZC ; return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ;


<s> bool <ISA_LIT>RegStackify :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << MF . getName ( ) << '\n' ) ; bool Changed = false ;


<s> return makeArrayRef ( std :: begin ( RegListYMM ) , std :: end ( RegListYMM ) ) ; } static const MCPhysReg RegListXMM [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return makeArrayRef ( std :: begin ( RegListXMM ) , std :: end ( RegListXMM ) ) ;


<s> int getMUBUFOpcode ( unsigned BaseOpc , unsigned Elements ) { const MUBUFInfo * Info = getMUBUFInfoFromBaseOpcodeAndElements ( BaseOpc , Elements ) ;

return Info ? Info -> Opcode : - <NUM_LIT> ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) {


<s> continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( * ( __GCC_FV * ) fvf ) : <STR_LIT> ( * ( const __GCC_FV * ) fvh ) , <STR_LIT> ( * ( const __GCC_MTRX * ) mtrxg ) ) ;


<s> const MachineOperand * Op1 = & MI1 . getOperand ( N1 + <STR_LIT> ) ; const MachineOperand * Op2 = & MI2 . getOperand ( N2 + <STR_LIT> ) ; if ( ! isIdenticalOp ( * Op1 , * Op2 ) ) { if ( Op1 -> isImm ( ) && Op2 -> isImm ( ) ) AddrDispShift = Op1 -> getImm ( ) - Op2 -> getImm ( ) ; else if ( Op1 -> isGlobal ( ) && Op2 -> isGlobal ( ) && Op1 -> getGlobal ( ) == Op2 -> getGlobal ( ) ) AddrDispShift = Op1 -> getOffset ( ) - Op2 -> getOffset ( ) ;


<s> return MI -> getOperand ( TII -> getOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: Enabled ) ) . getImm ( ) ;


addPass ( create<ISA_LIT>PreTileConfigPass ( ) ) ;


<s> return TM . TargetABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ;


<s> SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT> ) ;


<s> return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , <NUM_LIT> ) ;


<s> MCSection * ELFSection = getContext ( ) . getELFSection ( Section , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; getParser ( ) . getStreamer ( ) . SwitchSection ( ELFSection ) ;


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ;


<s> Register SrcReg = MRI -> createVirtualRegister ( SuperRC ) ; const auto * Src0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Src1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , Paired . I , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; const unsigned Regs = getRegs ( Opcode , * TII ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; unsigned JoinedFormat = getBufferFormatWithCompCount ( CI . Format , CI . Width + Paired . Width , * STI ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ;

const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : break ; } if ( Opcode == <STR_LIT> ) { NumOpsAdded = <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; return true ; } if ( Opcode == <STR_LIT> ) { unsigned Option = slice ( insn , <NUM_LIT> , <NUM_LIT> ) | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; MI . addOperand ( MCOperand :: CreateImm ( Option ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateImm ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ) ; NumOpsAdded = <NUM_LIT> ; return true ;


<s> return ( isThumb && ( C & ~ <NUM_LIT> ) == <NUM_LIT> ) || ( ! isThumb && <STR_LIT> ( C ) != - <NUM_LIT> ) ;


return ! ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ;


return ( __m128i ) __builtin_ia32_pmovusdb512_mask ( ( __v16si ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> Op -> Mem . Index = Index ; Op -> Mem . Disp = Disp ; Op -> Mem . Update = Update ;


<s> if ( type == NULL ) return false ; return AGGREGATE_TYPE_P ( type ) ;


<s> UsedRegUnits . clear ( ) ; MBBI = next_nodbg ( MBBI , E ) ; const bool BaseRegSP = BaseReg == <STR_LIT> ; if ( BaseRegSP ) { const MCAsmInfo * MAI = I -> getMF ( ) -> getTarget ( ) . getMCAsmInfo ( ) ; if ( MAI -> usesWindowsCFI ( ) && I -> getMF ( ) -> getFunction ( ) . needsUnwindTableEntry ( ) ) return E ; } for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; MBBI = next_nodbg ( MBBI , E ) ) { MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( isMatchingUpdateInsn ( * I , MI , BaseReg , UnscaledOffset ) ) return MBBI ; LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; if ( ! ModifiedRegUnits . available ( BaseReg ) || ! UsedRegUnits . available ( BaseReg ) || ( BaseRegSP && MBBI -> mayLoadOrStore ( ) ) ) return E ;


<s> return __builtin_mve_vrhaddq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __b , __p ) ;


<s> void printopaquemem ( const MCInst * MI , unsigned OpNo ) { O << <STR_LIT> ; printMemReference ( MI , OpNo ) ;


<s> if ( Num == <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ; ) ;

Num = handleJumpintoIfImp ( HeadMBB , FalseMBB , TrueMBB ) ;


<s> for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ;


<s> Res . Tok . Length = Str . size ( ) ; return Res ;


<s> static rtx loongarch_got_load_tls_le ( rtx dest , rtx sym ) { return gen_got_load_tls_le ( Pmode , dest , sym ) ;


<s> <ISA_LIT>AvoidSFBPass ( ) : MachineFunctionPass ( ID ) {


<s> const SMLoc SSS = getLoc ( ) ; StringRef Pred = Parser . getTok ( ) . getString ( ) ; bool zeroing = false ; if ( Pred . equals_lower ( <STR_LIT> ) ) zeroing = true ; else if ( ! Pred . equals_lower ( <STR_LIT> ) ) { Error ( SSS , <STR_LIT> ) ; return false ; } Parser . Lex ( ) ;

const char * zm = zeroing ? <STR_LIT> : <STR_LIT> ;


<s> static BrigType getParamBrigType ( Type * Ty , const DataLayout & DL , bool IsSExt ) { BrigType BT = <STR_LIT> ( Ty , DL , IsSExt ) ; if ( BT == BRIG_TYPE_B1 ) { assert ( ! IsSExt && <STR_LIT> ) ;

return IsSExt ? BRIG_TYPE_S8 : BRIG_TYPE_U8 ;


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtsd_si32 ( __m128d __A ) { __v2df rounded = vec_rint ( ( __v2df ) __A ) ; int result = ( ( __v2df ) rounded ) [ <NUM_LIT> ] ; return result ;


<s> registered_function * rfn = function_table -> find_with_hash ( instance , instance . hash ( ) ) ;


<s> SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( MF , NewRetAddr ) , false , false , <NUM_LIT> ) ; if ( Subtarget . isDarwinABI ( ) ) { int NewFPLoc = SPDiff + FL -> getFramePointerSaveOffset ( ) ; int NewFPIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewFPLoc , true ) ; SDValue NewFramePtrIdx = DAG . getFrameIndex ( NewFPIdx , VT ) ; Chain = DAG . getStore ( Chain , dl , OldFP , NewFramePtrIdx , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , NewFPIdx ) , false , false , <NUM_LIT> ) ; }


<s> return ( uint8x16_t ) __builtin_aarch64_uhaddv16qi ( ( int8x16_t ) __a , ( int8x16_t ) __b ) ;


<s> unsigned <ISA_LIT>ABIInfo :: GetNullPtr ( ) const { return ArePtrs64bit ( ) ? <STR_LIT> : <STR_LIT> ;


<s> static SDValue lowerV4X128VectorShuffle ( SDLoc DL , MVT VT , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { assert ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( VT . is512BitVector ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( ! canWidenShuffleElements ( Mask , WidenedMask ) ) return SDValue ( ) ; SDValue Ops [ <NUM_LIT> ] = { DAG . getUNDEF ( VT ) , DAG . getUNDEF ( VT ) } ; int MaxOp1Index = VT . getVectorNumElements ( ) / <NUM_LIT> - <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = WidenedMask . size ( ) ; i < Size ; ++ i ) { if ( WidenedMask [ i ] == SM_SentinelZero ) return SDValue ( ) ; if ( WidenedMask [ i ] == SM_SentinelUndef ) continue ; SDValue Op = WidenedMask [ i ] > MaxOp1Index ? V2 : V1 ; unsigned OpIndex = ( i < Size / <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Ops [ OpIndex ] . isUndef ( ) ) Ops [ OpIndex ] = Op ; else if ( Ops [ OpIndex ] != Op ) return SDValue ( ) ; } unsigned PermMask = <NUM_LIT> , Imm = <NUM_LIT> ; unsigned ControlBitsNum = WidenedMask . size ( ) / <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = WidenedMask . size ( ) ; i < Size ; ++ i ) { Imm = ( WidenedMask [ i ] == SM_SentinelUndef ) ? <NUM_LIT> : WidenedMask [ i ] ; PermMask |= ( Imm % WidenedMask . size ( ) ) << ( i * ControlBitsNum ) ;


<s> unsigned CountD = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned CountS = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned InVal = <NUM_LIT> + CountS ; ShuffleMask [ CountD ] = InVal ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ;


<s> if ( ! OPTION_SET_P ( flag_web ) ) flag_web = flag_unroll_loops ; if ( ! OPTION_SET_P ( flag_rename_registers ) ) flag_rename_registers = flag_unroll_loops ;

if ( ! OPTION_SET_P ( flag_cunroll_grow_size ) ) flag_cunroll_grow_size = flag_unroll_loops || flag_peel_loops || optimize >= <NUM_LIT> ;


<s> Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - imm ) ) ;


<s> dest = gen_rtx_ZERO_EXTRACT ( SImode , scratch_reg , rtx16 , rtx16 ) ; if ( mask ) emit_insn ( gen_rtx_SET ( dest , gen_int_mode ( mask , SImode ) ) ) ; emit_insn ( gen_andsi3 ( cleared_reg , cleared_reg , scratch_reg ) ) ; } if ( saved_clearing ) emit_move_insn ( clearing_reg , saved_clearing_reg ) ; if ( clearing_regno <= maxregno && bitmap_bit_p ( to_clear_bitmap , clearing_regno ) ) { emit_move_insn ( clearing_reg , const0_rtx ) ; emit_use ( clearing_reg ) ; bitmap_clear_bit ( to_clear_bitmap , clearing_regno ) ; } for ( regno = minregno ; regno <= maxregno ; regno ++ ) { if ( ! bitmap_bit_p ( to_clear_bitmap , regno ) ) continue ; if ( IS_VFP_REGNUM ( regno ) ) { if ( TARGET_VFP_DOUBLE && VFP_REGNO_OK_FOR_DOUBLE ( regno ) && bitmap_bit_p ( to_clear_bitmap , regno + <NUM_LIT> ) ) { emit_move_insn ( gen_rtx_REG ( DFmode , regno ) , CONST1_RTX ( DFmode ) ) ; emit_use ( gen_rtx_REG ( DFmode , regno ) ) ; regno ++ ; } else { emit_move_insn ( gen_rtx_REG ( SFmode , regno ) , CONST1_RTX ( SFmode ) ) ; emit_use ( gen_rtx_REG ( SFmode , regno ) ) ; } } else { emit_move_insn ( gen_rtx_REG ( SImode , regno ) , clearing_reg ) ;

emit_use ( gen_rtx_REG ( SImode , regno ) ) ;


<s> else if ( ( OpMI = getOpcodeDef ( TargetOpcode :: G_FCONSTANT , I . getOperand ( Idx ) . getReg ( ) , MRI ) ) ) Csts . emplace_back ( const_cast < ConstantFP * > ( OpMI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) ) ) ; else return false ; } Constant * CV = ConstantVector :: get ( Csts ) ; MachineIRBuilder MIB ( I ) ; if ( CV -> isNullValue ( ) ) { Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DstSize == <NUM_LIT> ) { auto Mov = MIB . buildInstr ( <STR_LIT> , { DstReg } , { } ) . addImm ( <NUM_LIT> ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Mov , TII , TRI , RBI ) ; } else if ( DstSize == <NUM_LIT> ) { auto Mov = MIB . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { } ) . addImm ( <NUM_LIT> ) ; MIB . buildInstr ( TargetOpcode :: COPY , { DstReg } , { } ) . addReg ( Mov . getReg ( <NUM_LIT> ) , <NUM_LIT> , <STR_LIT> ) ; I . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( DstReg , <STR_LIT> , MRI ) ; } } auto * CPLoad = emitLoadFromConstantPool ( CV , MIB ) ;


<s> if ( get<ISA_LIT>Subtarget ( ) . isCheri ( ) ) { addPass ( createCheriAddressingModeFolder ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: Level :: None ) addPass ( & DeadMachineInstructionElimID ) ;

addPass ( createCheri128FailHardPass ( ) ) ;


<s> CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; default : return false ; } } else if ( I -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { CReg = <STR_LIT> ; RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; default : return false ; } } else { return false ; }


<s> const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << <STR_LIT> ; O . write_hex ( Address ) ; } else {


<s> } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; OS << '[' ;

Op . getExpr ( ) -> print ( OS , & MAI ) ;


<s> if ( UseC [ R ] == <NUM_LIT> ) continue ; All0 = false ; break ; } Accept = All0 ; } else if ( SelectHas0 ) { bool Has0 = false ; for ( unsigned R = Us . find_first ( ) ; R ; R = Us . find_next ( R ) ) { if ( UseC [ R ] != <NUM_LIT> ) continue ; Has0 = true ; break ; } Accept = Has0 ; } if ( Accept ) LL . push_back ( M ) ; } AllRMs . clear ( ) ; for ( IFMapType :: iterator I = IFMap . begin ( ) ; I != End ; ++ I ) { const IFListType & LL = I -> second ; if ( LL . size ( ) > <NUM_LIT> ) AllRMs . insert ( LL [ <NUM_LIT> ] . second ) ; } for ( IFMapType :: iterator I = IFMap . begin ( ) ; I != End ; ++ I ) { IFListType & LL = I -> second ; if ( LL . size ( ) == <NUM_LIT> ) continue ;

unsigned SR = LL [ <NUM_LIT> ] . first . SrcR , IR = LL [ <NUM_LIT> ] . first . InsR ;


return getStreamer ( ) . getContext ( ) ;


<s> <ISA_LIT>PromoteAlloca ( const <ISA_LIT>Subtarget & st ) : FunctionPass ( ID ) , ST ( st ) , LocalMemAvailable ( <NUM_LIT> ) {


<s> const unsigned FractBits = <NUM_LIT> ; const unsigned ExpBits = <NUM_LIT> ; LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto Const0 = B . buildConstant ( S32 , FractBits - <NUM_LIT> ) ; auto Const1 = B . buildConstant ( S32 , ExpBits ) ; auto ExpPart = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( Hi ) . addUse ( Const0 . getReg ( <NUM_LIT> ) ) . addUse ( Const1 . getReg ( <NUM_LIT> ) ) ; return B . buildSub ( S32 , ExpPart , B . buildConstant ( S32 , <NUM_LIT> ) ) ;


<s> case GE : cmp_mode = CCVHmode ; new_code = LE ; swap_p = true ; break ; case LT : cmp_mode = CCVHmode ; new_code = GT ; swap_p = true ; break ; case LE : cmp_mode = CCVHmode ; new_code = LE ; break ; case GTU : cmp_mode = CCVHUmode ; break ; case GEU : cmp_mode = CCVHUmode ; new_code = LEU ; swap_p = true ; break ; case LTU : cmp_mode = CCVHUmode ; new_code = GTU ; swap_p = true ; break ; case LEU : cmp_mode = CCVHUmode ; new_code = LEU ; break ; default : gcc_unreachable ( ) ; } scratch_mode = GET_MODE ( cmp1 ) ; } else if ( GET_MODE ( cmp1 ) == V2DFmode ) { switch ( code ) { case EQ : cmp_mode = CCVEQmode ; break ; case NE : cmp_mode = CCVEQmode ; break ; case GT : cmp_mode = CCVFHmode ; break ; case GE : cmp_mode = CCVFHEmode ; break ; case UNLE : cmp_mode = CCVFHmode ; break ; case UNLT : cmp_mode = CCVFHEmode ; break ;

case LT : cmp_mode = CCVFHmode ; new_code = GT ; swap_p = true ; break ;


<s> unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ;


<s> assert ( Adjusted < FrameSize && <STR_LIT> ) ; int remaining = FrameSize - Adjusted ; int OpImm = ( remaining > MaxImmU16 ) ? MaxImmU16 : remaining ; int Opcode = isImmU6 ( OpImm ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opcode ) ) . addImm ( OpImm ) ; Adjusted += OpImm ;

if ( emitFrameMoves ) EmitDefCfaOffset ( MBB , MBBI , dl , TII , Adjusted * <NUM_LIT> ) ;


<s> static bool ix86_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( must_pass_in_stack_var_size_or_pad ( mode , type ) ) return true ;

return ( ! TARGET_64BIT && mode == TImode && type && TREE_CODE ( type ) != VECTOR_TYPE ) ;


<s> case GT_S_I64 : Def -> setDesc ( TII . get ( LE_S_I64 ) ) ; Inverted = true ; break ; case GE_S_I64 : Def -> setDesc ( TII . get ( LT_S_I64 ) ) ; Inverted = true ; break ; case LT_S_I64 : Def -> setDesc ( TII . get ( GE_S_I64 ) ) ; Inverted = true ; break ; case LE_S_I64 : Def -> setDesc ( TII . get ( GT_S_I64 ) ) ; Inverted = true ; break ; case GT_U_I64 : Def -> setDesc ( TII . get ( LE_U_I64 ) ) ; Inverted = true ; break ; case GE_U_I64 : Def -> setDesc ( TII . get ( LT_U_I64 ) ) ; Inverted = true ; break ; case LT_U_I64 : Def -> setDesc ( TII . get ( GE_U_I64 ) ) ; Inverted = true ; break ; case LE_U_I64 : Def -> setDesc ( TII . get ( GT_U_I64 ) ) ; Inverted = true ; break ; case EQ_F32 : Def -> setDesc ( TII . get ( NE_F32 ) ) ; Inverted = true ; break ; case NE_F32 : Def -> setDesc ( TII . get ( EQ_F32 ) ) ; Inverted = true ; break ; case EQ_F64 : Def -> setDesc ( TII . get ( NE_F64 ) ) ; Inverted = true ; break ; case NE_F64 : Def -> setDesc ( TII . get ( EQ_F64 ) ) ; Inverted = true ; break ; default : break ; } } if ( ! Inverted ) { unsigned Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Tmp ) . addReg ( Cond ) ; MFI . stackifyVReg ( Tmp ) ; Cond = Tmp ;


<s> case MCOI :: OPERAND_IMMEDIATE : { uint64_t Region = Addr & ~ uint64_t ( <NUM_LIT> ) ; Target = Region + Inst . getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; return true ; } case MCOI :: OPERAND_PCREL : Target = Addr + Inst . getOperand ( NumOps - <NUM_LIT> ) . getImm ( ) ; return true ; default : return false ;


assert ( DIToIdMap . find ( Ty ) != DIToIdMap . end ( ) && <STR_LIT> ) ;


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return & FrameLowering ;


<s> return ( __m128i ) __builtin_ia32_vcvtps2ph256_mask ( ( __v8sf ) __A , __I , ( __v8hi ) _mm_setzero_hi ( ) , ( __mmask8 ) __U ) ;


<s> unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rt = getReg ( Decoder , <STR_LIT> , Rt ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( Rt ) ) ; } Inst . addOperand ( MCOperand :: CreateReg ( Rt ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , GOTFlag ) ) ;

SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> FunctionPass * llvm :: createAMDGPUCFGStructurizerPass ( TargetMachine & tm ) { return new AMDGPUCFGPerform ( tm ) ;


<s> uint64_t Flags = MCID . TSFlags ; if ( ( Flags & <STR_LIT> ) != <STR_LIT> ) continue ; if ( isVCTP ( & MI ) || isVPTOpcode ( MI . getOpcode ( ) ) ) continue ; if ( isVectorPredicated ( & MI ) ) { if ( MI . mayLoad ( ) ) FalseLanesZero . insert ( & MI ) ; Predicated . insert ( & MI ) ; continue ; } if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; if ( ! producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) { if ( retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ) return false ; FalseLanesUnknown . insert ( & MI ) ; } else if ( ! isHorizontalReduction ( MI ) ) FalseLanesZero . insert ( & MI ) ; } auto HasPredicatedUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Predicated ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Predicated . count ( Use ) ) return false ; } return true ; } ; SmallPtrSet < MachineInstr * , <NUM_LIT> > NonPredicated ; for ( auto * MI : reverse ( FalseLanesUnknown ) ) { for ( auto & MO : MI -> operands ( ) ) { if ( ! isRegInClass ( MO , QPRs ) || ! MO . isDef ( ) ) continue ; if ( ! HasPredicatedUsers ( MI , MO , Predicated ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI . getRegAsmName ( MO . getReg ( ) ) << <STR_LIT> << * MI ) ; NonPredicated . insert ( MI ) ; continue ; } } Predicated . insert ( MI ) ; } SmallPtrSet < MachineInstr * , <NUM_LIT> > LiveOutMIs ; SmallPtrSet < MachineInstr * , <NUM_LIT> > LiveOutUsers ;

SmallVector < MachineBasicBlock * , <NUM_LIT> > ExitBlocks ;


<s> DebugLoc DL = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> const TargetRegisterClass * ARC = getAGPRClassForBitWidth ( Size ) ; if ( ! ARC ) { assert ( getVGPRClassForBitWidth ( Size ) && <STR_LIT> ) ; return false ; }

return getCommonSubClass ( ARC , RC ) != nullptr ;


<s> const auto & FPR128 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; return llvm :: any_of ( MI , [ & ] ( const MCOperand & Op ) { return Op . isReg ( ) && FPR128 . contains ( Op . getReg ( ) ) ; } ) ;


<s> void setSGPRSpillVGPRs ( Register NewVGPR , Optional < int > newFI , int Index ) {


if ( Kind < FirstTargetFixupKind ) return TargetAsmBackend :: getFixupKindInfo ( Kind ) ;


<s> if ( regno == MDB_REGNUM ) return CEIL ( GET_MODE_SIZE ( mode ) , <NUM_LIT> * UNITS_PER_WORD ) ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ;


<s> ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( SubAdd ) { unsigned Opc = SubAdd -> getOpcode ( ) ; bool IsSub = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; unsigned OpI = Opc != <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ! IsSub || ( SrcReg2 != <NUM_LIT> && SubAdd -> getOperand ( OpI ) . getReg ( ) == SrcReg2 && SubAdd -> getOperand ( OpI + <NUM_LIT> ) . getReg ( ) == SrcReg ) ) { if ( IsInstrVSel ) return false ; <STR_LIT> NewCC = ( IsSub ? getSwappedCondition ( CC ) : getCmpToAddCondition ( CC ) ) ; if ( NewCC == <STR_LIT> ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } } if ( ! isSafe ) { MachineBasicBlock * MBB = CmpInstr . getParent ( ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; } if ( ! IsThumb1 ) {

MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ;


<s> void <ISA_LIT>65816TargetStreamer :: anchor ( ) {


<s> fprintf ( asm_out_file , <STR_LIT> <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; assemble_name ( asm_out_file , sec -> name ) ; fprintf ( asm_out_file , <STR_LIT> ) ; sec = sec -> next ; }


<s> static const <ISA_LIT>MCExpr * CreateGOTTPREL ( const MCExpr * Expr , MCContext & Ctx ) {

return Create ( VK_AARCH64_GOTTPREL , Expr , Ctx ) ;


<s> regrename_analyze ( NULL ) ; compute_bb_for_insn ( ) ; calculate_dominance_info ( CDI_DOMINATORS ) ; loop_optimizer_init ( AVOID_CFG_MODIFICATIONS ) ; FOR_EACH_LOOP ( loop , LI_FROM_INNERMOST ) { tag_map_t tag_map ( <NUM_LIT> ) ; record_loads ( tag_map , loop ) ; avoid_collisions ( tag_map ) ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , loop -> num ) ; tag_map . traverse < void * , dump_insn_list > ( NULL ) ; } tag_map . traverse < void * , free_insn_info > ( NULL ) ; } loop_optimizer_finalize ( ) ;


<s> if ( MCSym -> isDefined ( ) ) return ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMachO . getFnStubEntry ( MCSym ) ;

if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl :: StubValueTy ( MCSym , false ) ;


<s> unsigned Alignment = LI -> getAlignment ( ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( Result == <NUM_LIT> ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ;


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_avg_pu16 ( __m64 __A , __m64 __B ) { __vector unsigned short a , b , c ; a = ( __vector unsigned short ) vec_splats ( __A ) ; b = ( __vector unsigned short ) vec_splats ( __B ) ; c = vec_avg ( a , b ) ;

return ( __m64 ) ( ( __vector long long ) c ) [ <NUM_LIT> ] ;


<s> <ISA_LIT>_32TargetMachine :: <ISA_LIT>_32TargetMachine ( const Module & M , const std :: string & FS ) : <ISA_LIT>TargetMachine ( M , FS , false ) {


<s> if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return <NUM_LIT> ; } return get ( Opcode ) . getSize ( ) ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getNode ( ) -> hasOneUse ( ) ) { SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI , AllOnes ) ; if ( Result . getNode ( ) ) return Result ; } if ( N1 . getNode ( ) -> hasOneUse ( ) ) { SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI , AllOnes ) ; if ( Result . getNode ( ) ) return Result ; } return SDValue ( ) ;


<s> ValueToNodeMap NM ; for ( ValueVect :: iterator I = BO . begin ( ) , E = BO . end ( ) ; I != E ; ++ I ) {

BasicBlock * B = cast < BasicBlock > ( * I ) ;


if ( i == e - <NUM_LIT> ) Flags . setInConsecutiveRegsLast ( ) ;


<s> unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Opcode = Inst . getOpcode ( ) ; switch ( Opcode ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rs , Addr , Decoder ) ; LLVM_FALLTHROUGH ; case <STR_LIT> :


<s> unsigned getScoreUB ( InstCounterType T ) const { assert ( T < NUM_INST_CNTS ) ; return ScoreUBs [ T ] ;


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V16HImode ; goto do_subreg ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V8SImode ; goto do_subreg ; case V16HImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) break ; if ( i < <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) rperm [ i ] = ( d -> perm [ i / <NUM_LIT> ] < <NUM_LIT> ? const0_rtx : constm1_rtx ) ; vmode = V32QImode ; nelt = <NUM_LIT> ; target = gen_reg_rtx ( vmode ) ; op0 = gen_lowpart ( vmode , op0 ) ; op1 = gen_lowpart ( vmode , op1 ) ; goto finish_pblendvb ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i ] >= <NUM_LIT> ) << i ; break ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V8SImode ; goto do_subreg ; case V4DImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i ] >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << ( i * <NUM_LIT> ) ; vmode = V8SImode ; goto do_subreg ; default : gcc_unreachable ( ) ; } switch ( vmode ) { case V8DFmode : case V8DImode : mmode = QImode ; break ;


<s> SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDNode * Hi64 = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , StNode -> getValue ( ) , SubRegEven ) ; SDNode * Lo64 = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , StNode -> getValue ( ) , SubRegOdd ) ; unsigned alignment = StNode -> getAlignment ( ) ; if ( alignment > <NUM_LIT> ) alignment = <NUM_LIT> ; SDValue OutChains [ <NUM_LIT> ] ; OutChains [ <NUM_LIT> ] = DAG . getStore ( StNode -> getChain ( ) , dl , SDValue ( Hi64 , <NUM_LIT> ) , StNode -> getBasePtr ( ) , MachinePointerInfo ( ) , false , false , alignment ) ; EVT addrVT = StNode -> getBasePtr ( ) . getValueType ( ) ;

SDValue LoPtr = DAG . getNode ( <STR_LIT> , dl , addrVT , StNode -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , dl , addrVT ) ) ;


<s> return new <ISA_LIT>ReplacePhysRegs ( ) ;


<s> MachineFunction & MF = * MBB -> getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; Register SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = getRegTy ( SrcReg , MF ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;

if ( MVT ( getRegTy ( SrcReg , MF ) ) . isFatPointer ( ) ) DstReg = <STR_LIT> ;


<s> static machine_mode maybe_split_mode ( machine_mode mode ) {

if ( COMPLEX_MODE_P ( mode ) ) return GET_MODE_INNER ( mode ) ;


<s> if ( TREE_CODE ( decl ) != VAR_DECL ) return false ; if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ) return false ; section = DECL_SECTION_NAME ( decl ) ; if ( section ) { char * name = ( char * ) TREE_STRING_POINTER ( section ) ;

if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return true ;


<s> BitPermutationSelector ( SelectionDAG * DAG ) : CurDAG ( DAG ) {


<s> InstructionCost <ISA_LIT>TTIImpl :: getOperandsScalarizationOverhead ( ArrayRef < const Value * > Args , ArrayRef < Type * > Tys ) { return BaseT :: getOperandsScalarizationOverhead ( Args , Tys ) ;


<s> static int match_bracketed_pair ( typeinfo * typedata , char open , char close , restriction restr ) { if ( linebuf [ pos ] == open ) { safe_inc_pos ( ) ; int oldpos = pos ; char * x = match_integer ( ) ; if ( x == NULL ) { diag ( oldpos , <STR_LIT> ) ; return <NUM_LIT> ; } consume_whitespace ( ) ; if ( linebuf [ pos ] != ',' ) { diag ( pos , <STR_LIT> ) ; return <NUM_LIT> ; } safe_inc_pos ( ) ; consume_whitespace ( ) ; oldpos = pos ; char * y = match_integer ( ) ; if ( y == NULL ) { diag ( oldpos , <STR_LIT> ) ; return <NUM_LIT> ; } typedata -> restr = restr ; typedata -> val1 = x ; typedata -> val2 = y ; consume_whitespace ( ) ; if ( linebuf [ pos ] != close ) { diag ( pos , <STR_LIT> ) ; return <NUM_LIT> ; } safe_inc_pos ( ) ;


<s> MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;


<s> bool Unpacked = Subtarget -> hasUnpackedD16VMem ( ) ; EVT LoadVT = M -> getValueType ( <NUM_LIT> ) ; EVT EquivLoadVT = LoadVT ; if ( Unpacked && LoadVT . isVector ( ) ) { EquivLoadVT = LoadVT . isVector ( ) ? EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , LoadVT . getVectorNumElements ( ) ) : LoadVT ;


<s> unsigned getSOImmOpValue ( const MachineInstr & MI , unsigned Op ) const {


<s> assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; else return LowerToTLSExecModels ( GA , DAG ) ;


<s> if ( ! insn_data [ icode ] . operand [ op ] . predicate ( value , mode ) ) { value = copy_to_mode_reg ( mode , value ) ; if ( ! insn_data [ icode ] . operand [ op ] . predicate ( value , mode ) ) { error ( <STR_LIT> ) ; return const0_rtx ; }


<s> void addX2Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isX2 ( ) && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( X2 . Val ) ) ;


if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return <NUM_LIT> ;


<s> StringRef getPassName ( ) const override {


<s> void <ISA_LIT>InstPrinter :: printConstpool ( const MCInst * MI , uint64_t Address , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { if ( PrintBranchImmAsAddress ) { uint64_t Target = Address + MO . getImm ( ) ; Target &= <NUM_LIT> ; O << formatHex ( Target ) ; } else { O << MO . getImm ( ) ; } return ; } assert ( MO . isExpr ( ) && <STR_LIT> ) ;


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ;

NopInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> name = XSTR ( op , <NUM_LIT> ) ; return ( strcasecmp ( name , <STR_LIT> ) == <NUM_LIT> || strcasecmp ( name , <STR_LIT> ) == <NUM_LIT> || strcasecmp ( name , <STR_LIT> ) == <NUM_LIT> || strcasecmp ( name , <STR_LIT> ) == <NUM_LIT> || strcasecmp ( name , <STR_LIT> ) == <NUM_LIT> || strcasecmp ( name , <STR_LIT> ) == <NUM_LIT> || strcasecmp ( name , <STR_LIT> ) == <NUM_LIT> || strcasecmp ( name , <STR_LIT> ) == <NUM_LIT> || strcasecmp ( name , <STR_LIT> ) == <NUM_LIT> || strcasecmp ( name , <STR_LIT> ) == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; case PLUS : case MINUS : return must_parenthesize ( XEXP ( op , <NUM_LIT> ) ) || must_parenthesize ( XEXP ( op , <NUM_LIT> ) ) ; case MEM : case CONST : case ZERO_EXTEND :


<s> static bool aarch64_symbol_binds_local_p ( const_rtx x ) {

return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ;


<s> <ISA_LIT>ConstantPoolValue * ACPV0 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE0 . Val . MachineCPVal ) ; <ISA_LIT>ConstantPoolValue * ACPV1 = static_cast < <ISA_LIT>ConstantPoolValue * > ( MCPE1 . Val . MachineCPVal ) ; return ACPV0 -> hasSameValue ( ACPV1 ) ; } else if ( ! is<ISA_LIT>CP0 && ! is<ISA_LIT>CP1 ) { return MCPE0 . Val . ConstVal == MCPE1 . Val . ConstVal ; } return false ; } else if ( Opcode == <STR_LIT> ) { if ( MI1 . getOpcode ( ) != Opcode ) return false ; if ( MI0 . getNumOperands ( ) != MI1 . getNumOperands ( ) ) return false ; unsigned Addr0 = MI0 . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Addr1 = MI1 . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Addr0 != Addr1 ) { if ( ! MRI || ! TargetRegisterInfo :: isVirtualRegister ( Addr0 ) || ! TargetRegisterInfo :: isVirtualRegister ( Addr1 ) ) return false ; MachineInstr * Def0 = MRI -> getVRegDef ( Addr0 ) ; MachineInstr * Def1 = MRI -> getVRegDef ( Addr1 ) ; if ( ! produceSameValue ( * Def0 , * Def1 , MRI ) ) return false ; } for ( unsigned i = <NUM_LIT> , e = MI0 . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO0 = MI0 . getOperand ( i ) ; const MachineOperand & MO1 = MI1 . getOperand ( i ) ; if ( ! MO0 . isIdenticalTo ( MO1 ) ) return false ; }


<s> <ISA_LIT>ConstantPoolValue :: <ISA_LIT>ConstantPoolValue ( const Constant * value ) : MachineConstantPoolValue ( value -> getType ( ) ) , Value ( value ) {


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { printS16ImmOperand ( MI , OpNo , O ) ; } else {

printOp ( MI -> getOperand ( OpNo ) , O ) ;


<s> Warning ( Loc , <STR_LIT> ) ; getParser ( ) . Lex ( ) ; return false ; } if ( IdVal == <STR_LIT> ) { getParser ( ) . Lex ( ) ; return false ; } if ( IdVal == <STR_LIT> ) return parseSetFpDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetOddSPRegDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNoOddSPRegDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetPopDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetPushDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetReorderDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNoReorderDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetMacroDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNoMacroDirective ( ) ; if ( IdVal == <STR_LIT> ) return parseSet<ISA_LIT>16Directive ( ) ; if ( IdVal == <STR_LIT> ) return parseSetNo<ISA_LIT>16Directive ( ) ; if ( IdVal == <STR_LIT> ) { clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return false ; } if ( IdVal == <STR_LIT> ) { if ( has<ISA_LIT>64r6 ( ) ) { Error ( Loc , <STR_LIT> ) ; return false ; } return parseSetFeature ( <STR_LIT> ) ; } if ( IdVal == <STR_LIT> ) return parseSet<ISA_LIT>0Directive ( ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ; if ( IdVal == <STR_LIT> ) return parseSetFeature ( <STR_LIT> ) ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) ; addFrameReference ( MIB , FrameIx , <NUM_LIT> , false ) . addImm ( Offset ) . addMetadata ( MDPtr ) ;


<s> const MachineOperand & MO = * I ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isDef ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( AMDGPU :: R600_Reg128RegClass . contains ( Reg ) ) DstMI = Reg ; else DstMI = TRI -> getMatchingSuperReg ( Reg , TRI -> getSubRegFromChannel ( TRI -> getHWRegChan ( Reg ) ) , & AMDGPU :: R600_Reg128RegClass ) ;


<s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : Res = combineToCMPB ( N ) ; break ; } if ( ! Res ) foldBoolExts ( Res , N ) ; if ( Res ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Res . getNode ( ) -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Res ) ; MadeChange = true ; } } if ( MadeChange ) CurDAG -> RemoveDeadNodes ( ) ;


<s> static <ISA_LIT>Operand * CreateTLSReg ( const MCSymbolRefExpr * Sym , SMLoc S , SMLoc E , bool Is<ISA_LIT>64 ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( TLSRegister ) ; Op -> TLSReg . Sym = Sym ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> else if ( CDX_LDSTWM_VALID_REGS_1 & ( <NUM_LIT> << regno ) ) * regset = CDX_LDSTWM_VALID_REGS_1 ; else return false ; return true ; } else return ( * regset & ( <NUM_LIT> << regno ) ) != <NUM_LIT> ;


<s> MachineInstr * MI = & * MII ; if ( MI -> isBundle ( ) || MI -> isTransient ( ) ) continue ;

Modified |= ReduceMI ( MII , NextMII ) ;


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;

AsmPrinter :: runOnMachineFunction ( MF ) ;


<s> std :: string Text ; { llvm :: raw_string_ostream Stream ( Text ) ;

Stream << <STR_LIT> << bits << <STR_LIT> << kind ;


<s> void altivec_expand_lvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx load = gen_rtx_SET ( VOIDmode , tmp , op1 ) ; rtx lvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , load , lvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ;

rtx vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , tmp , tmp , sel ) , UNSPEC_VPERM ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned <ISA_LIT>Reg = <STR_LIT> ; SDValue <ISA_LIT> = DAG . getCopyFromReg ( Chain , dl , <ISA_LIT>Reg , <STR_LIT> ) ; SDValue New<ISA_LIT> = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , <ISA_LIT> , Size ) ; Chain = DAG . getCopyToReg ( <ISA_LIT> . getValue ( <NUM_LIT> ) , dl , <ISA_LIT>Reg , New<ISA_LIT> ) ; SDValue NewVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , New<ISA_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ops [ <NUM_LIT> ] = { NewVal , Chain } ;

return DAG . getMergeValues ( Ops , <NUM_LIT> , dl ) ;


else return SCS ? CSR_<ISA_LIT>_AAPCS_SCS_RegMask : CSR_<ISA_LIT>_AAPCS_RegMask ;


<s> unsigned Op1 , Op2 ; DecodeStatus S = Decode2OpInstruction ( Insn , Op1 , Op2 ) ; if ( S == MCDisassembler :: Success ) {

DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ;


<s> case CC_DGTUmode : code = ARM_HI ; goto dominance ; case CC_DLEUmode : code = ARM_LS ; goto dominance ; case CC_DLTUmode : code = ARM_CC ; dominance : gcc_assert ( comp_code == EQ || comp_code == NE ) ; if ( comp_code == EQ ) return ARM_INVERSE_CONDITION_CODE ( code ) ; return code ; case CC_NOOVmode : switch ( comp_code ) { case NE : return ARM_NE ; case EQ : return ARM_EQ ; case GE : return ARM_PL ; case LT : return ARM_MI ; default : gcc_unreachable ( ) ; } case CC_Zmode : switch ( comp_code ) { case NE : return ARM_NE ; case EQ : return ARM_EQ ; default : gcc_unreachable ( ) ; } case CC_Nmode : switch ( comp_code ) { case NE : return ARM_MI ; case EQ : return ARM_PL ; default : gcc_unreachable ( ) ; } case CCFPEmode : case CCFPmode : switch ( comp_code ) { case GE : return ARM_GE ; case GT : return ARM_GT ; case LE : return ARM_LS ; case LT : return ARM_MI ; case NE : return ARM_NE ; case EQ : return ARM_EQ ; case ORDERED : return ARM_VC ; case UNORDERED : return ARM_VS ; case UNLT : return ARM_LT ; case UNLE : return ARM_LE ; case UNGT : return ARM_HI ; case UNGE : return ARM_PL ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } case CC_SWPmode : switch ( comp_code ) { case NE : return ARM_NE ; case EQ : return ARM_EQ ; case GE : return ARM_LE ; case GT : return ARM_LT ; case LE : return ARM_GE ; case LT : return ARM_GT ; case GEU : return ARM_LS ; case GTU : return ARM_CC ; case LEU : return ARM_CS ; case LTU : return ARM_HI ; default : gcc_unreachable ( ) ; } case CC_Cmode : switch ( comp_code ) { case LTU : return ARM_CS ; case GEU : return ARM_CC ; default : gcc_unreachable ( ) ; } case CCmode : switch ( comp_code ) { case NE : return ARM_NE ; case EQ : return ARM_EQ ; case GE : return ARM_GE ; case GT : return ARM_GT ; case LE : return ARM_LE ;


<s> case E_SFmode : cum -> arg_words ++ ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DFmode : cum -> arg_words += <NUM_LIT> ; if ( ! cum -> gp_reg_found && cum -> arg_number <= <NUM_LIT> ) cum -> fp_code += <NUM_LIT> << ( ( cum -> arg_number - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case E_DImode : cum -> gp_reg_found = <NUM_LIT> ;


<s> unsigned int <ISA_LIT>AsmBackend :: getNumFixupKinds ( ) const { return <STR_LIT> :: NumTargetFixupKinds ;


<s> void <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ;

} else if ( RC == <STR_LIT> || RC == <STR_LIT> ) {


<s> return ( int64x1_t ) __builtin_neon_vpaddlsv2si ( __a ) ;


<s> emitSled ( MI , SledKind :: TAIL_CALL ) ;


<s> IsWin64 = Subtarget . isTargetWin64 ( ) ; if ( Is64Bit ) { SlotSize = <NUM_LIT> ; StackPtr = ( Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ) ? <STR_LIT> : <STR_LIT> ; FramePtr = ( Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ) ? <STR_LIT> : <STR_LIT> ; } else {


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> bool AMDGPUDAGToDAGISel :: FoldOperands ( unsigned Opcode , const R600InstrInfo * TII , std :: vector < SDValue > & Ops ) { int OperandIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) } ; int SelIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) } ; int NegIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) } ; int AbsIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> ) , TII -> getOperandIdx ( Opcode , <STR_LIT> ) , - <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( OperandIdx [ i ] < <NUM_LIT> ) return false ; SDValue Operand = Ops [ OperandIdx [ i ] - <NUM_LIT> ] ; switch ( Operand . getOpcode ( ) ) { case <STR_LIT> : { if ( i == <NUM_LIT> ) break ; SDValue CstOffset ; if ( ! Operand . getValueType ( ) . isVector ( ) && SelectGlobalValueConstantOffset ( Operand . getOperand ( <NUM_LIT> ) , CstOffset ) ) { Ops [ OperandIdx [ i ] - <NUM_LIT> ] = CurDAG -> getRegister ( AMDGPU :: ALU_CONST , <STR_LIT> ) ; Ops [ SelIdx [ i ] - <NUM_LIT> ] = CstOffset ; return true ; } } break ; case <STR_LIT> : if ( NegIdx [ i ] < <NUM_LIT> ) break ; Ops [ OperandIdx [ i ] - <NUM_LIT> ] = Operand . getOperand ( <NUM_LIT> ) ; Ops [ NegIdx [ i ] - <NUM_LIT> ] = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : if ( AbsIdx [ i ] < <NUM_LIT> ) break ; Ops [ OperandIdx [ i ] - <NUM_LIT> ] = Operand . getOperand ( <NUM_LIT> ) ; Ops [ AbsIdx [ i ] - <NUM_LIT> ] = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : Ops [ OperandIdx [ i ] - <NUM_LIT> ] = Operand . getOperand ( <NUM_LIT> ) ;


<s> SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ;

SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( Op , DAG , LoFlag ) ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) {

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ;


<s> <ISA_LIT>LowerAlloca ( ) : FunctionPass ( ID ) {


<s> return true ; case <STR_LIT> : expandLOCPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandLOCPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandLOCRPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandRXYPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandRXYPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandRXYPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandLOCPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , true ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIEPseudo ( MI , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRIPseudo ( MI , <STR_LIT> , <STR_LIT> , false ) ; return true ; case <STR_LIT> : expandRXYPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : expandRXYPseudo ( MI , <STR_LIT> , <STR_LIT> ) ; return true ; case <STR_LIT> : { bool DestIsHigh = isHighReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;

bool SrcIsHigh = isHighReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM ) ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset << <NUM_LIT> ) ) ; return MCDisassembler :: Success ;


<s>
for
(
auto
&
C
:
RQ
)
dbgs
(
)
<<
' '
<<
C
.
SU
->
NodeNum
<<
<STR_LIT>
<<
C
.
Priority
<<
')'
;
dbgs
(
)
<<
'\n'
;
)
;
auto
C
=
pickCandidate
(
)
;
assert
(
C
)
;
RQ
.
remove
(
*
C
)
;
auto
SU
=
C
->
SU
;
DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
SU
->
dump
(
&
DAG
)
)
;
releaseSuccessors
(
SU
,
StepNo
)
;
Schedule
.
push_back
(
SU
)
;
setIsScheduled
(
SU
)
;
if
(
getReadySuccessors
(
SU
)
==
<NUM_LIT>
)
bumpPredsPriority
(
SU
,
StepNo
)
;
++
StepNo
;
}

assert ( SUnits . size ( ) == Schedule . size ( ) ) ;


<s> case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * Sym = getSymbol ( GV ) ; assert ( ! MO . getTargetFlags ( ) && <STR_LIT> ) ; O << * Sym ; printOffset ( MO . getOffset ( ) , O ) ;


<s> if ( ( AS == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) ) { return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ; } return true ;


<s> if ( DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) return false ;


<s> enum aarch64_parse_opt_result res = aarch64_parse_branch_protection ( const_str , & str ) ; if ( res == AARCH64_PARSE_INVALID_ARG ) error ( <STR_LIT> , str ) ; else if ( res == AARCH64_PARSE_MISSING_ARG ) error ( <STR_LIT> ) ;


<s> void emitRR ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { emitRX ( Opcode , Reg0 , MCOperand :: createReg ( Reg1 ) , IDLoc , Instructions ) ;


<s> bool IsLdsOpcode = IsLds ; bool HasLdsModifier = false ; OptionalImmIndexMap OptionalIdx ; assert ( IsAtomicReturn ? IsAtomic : true ) ; unsigned FirstOperandIdx = <NUM_LIT> ; for ( unsigned i = FirstOperandIdx , e = Operands . size ( ) ; i != e ; ++ i ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ i ] ) ; if ( Op . isReg ( ) ) { Op . addRegOperands ( Inst , <NUM_LIT> ) ; if ( IsAtomicReturn && i == FirstOperandIdx ) Op . addRegOperands ( Inst , <NUM_LIT> ) ; continue ; } if ( Op . isImm ( ) && Op . getImmTy ( ) == <ISA_LIT>Operand :: ImmTyNone ) { Op . addImmOperands ( Inst , <NUM_LIT> ) ; continue ; } HasLdsModifier = Op . isLDS ( ) ;


<s> do { if ( statep ) arc_ccfsm_post_advance ( insn , statep ) ; insn = NEXT_INSN ( insn ) ; if ( ! insn || BARRIER_P ( insn ) ) return NULL ; if ( statep ) arc_ccfsm_advance ( insn , statep ) ; } while ( NOTE_P ( insn ) || ( cfun -> machine -> arc_reorg_started && LABEL_P ( insn ) && ! label_to_alignment ( insn ) ) || ( NONJUMP_INSN_P ( insn ) && ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) ) ) ; if ( ! LABEL_P ( insn ) ) { gcc_assert ( INSN_P ( insn ) ) ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == ADDR_VEC || GET_CODE ( pat ) == ADDR_DIFF_VEC ) return NULL ; if ( GET_CODE ( pat ) == SEQUENCE ) return as_a < rtx_insn * > ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; }


<s> <ISA_LIT>TargetELFStreamer ( MCStreamer & S ) : <ISA_LIT>TargetStreamer ( S ) {


<s> return gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , val ) , UNSPEC_RA ) ;


<s> static const unsigned HiRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned LoRegList [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , LoRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , <STR_LIT> , LocInfo ) ) ;

State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , LoRegList [ i ] , <STR_LIT> , LocInfo ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const {


<s> if ( io1 -> type == FRV_IO_WRITE && io2 -> type == FRV_IO_WRITE ) return true ;

if ( io1 -> type != FRV_IO_WRITE && io2 -> type != FRV_IO_WRITE ) return false ;


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI -> readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else { if ( MI -> readsRegister ( Reg , TRI ) ) return <NUM_LIT> ; }


<s> else if ( rs6000_warn_altivec_long ) warning ( <NUM_LIT> , <STR_LIT> ) ; } else if ( type == long_long_unsigned_type_node || type == long_long_integer_type_node ) error ( <STR_LIT> ) ; else if ( type == double_type_node ) error ( <STR_LIT> ) ; else if ( type == long_double_type_node ) error ( <STR_LIT> ) ; else if ( type == boolean_type_node ) error ( <STR_LIT> ) ; else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) error ( <STR_LIT> ) ; switch ( altivec_type ) { case 'v' : unsigned_p = TYPE_UNSIGNED ( type ) ; switch ( mode ) { case SImode : result = ( unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node ) ; break ; case HImode : result = ( unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node ) ; break ; case QImode : result = ( unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node ) ; break ; case SFmode : result = V4SF_type_node ; break ; case V4SImode : case V8HImode : case V16QImode : case V4SFmode : result = type ; default : break ; } break ; case 'b' : switch ( mode ) { case SImode : case V4SImode : result = bool_V4SI_type_node ; break ; case HImode : case V8HImode : result = bool_V8HI_type_node ; break ;

case QImode : case V16QImode : result = bool_V16QI_type_node ;


<s> bool hasFreeRegister ( set < Location > & FreeLocs ) { return ( ! FreeLocs . empty ( ) && ( FreeLocs . begin ( ) -> getType ( ) == Register ) ) || ( NumLocs < MaxRegs ) ;


<s> } register_builtin_types ( ) ; for ( unsigned int type_i = <NUM_LIT> ; type_i < NUM_VECTOR_TYPES ; ++ type_i ) {


<s> bool TValIsAllZeros = <STR_LIT> ( LHS . getNode ( ) ) ; if ( TValIsAllZeros && Subtarget . hasAVX512 ( ) && Cond . hasOneUse ( ) && CondVT . getVectorElementType ( ) == <STR_LIT> ) { SDValue CondNew = DAG . getNOT ( DL , Cond , CondVT ) ; return DAG . getSelect ( DL , VT , CondNew , RHS , LHS ) ; } if ( CondVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ; bool TValIsAllOnes = <STR_LIT> ( LHS . getNode ( ) ) ; bool FValIsAllZeros = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! TValIsAllOnes && ! FValIsAllZeros && Cond . getOpcode ( ) == <STR_LIT> && TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) == CondVT ) { bool FValIsAllOnes = <STR_LIT> ( RHS . getNode ( ) ) ; if ( TValIsAllZeros || FValIsAllOnes ) { SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; <STR_LIT> NewCC = <STR_LIT> ( cast < CondCodeSDNode > ( CC ) -> get ( ) , Cond . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; Cond = DAG . getSetCC ( DL , CondVT , Cond . getOperand ( <NUM_LIT> ) , Cond . getOperand ( <NUM_LIT> ) , NewCC ) ; std :: swap ( LHS , RHS ) ; TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros ;


<s> BasicBlock * Entry = PrevNode -> getEntry ( ) ; if ( ! PrevNode -> isSubRegion ( ) ) { killTerminator ( Entry ) ; if ( ! NeedEmpty || Entry -> getFirstInsertionPt ( ) == Entry -> end ( ) ) return Entry ; } BasicBlock * Flow = getNextFlow ( Entry ) ;


<s> } ArrayRef < int > Mask = cast < ShuffleVectorSDNode > ( N ) -> getMask ( ) ; int ParitySrc [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> } ; unsigned Size = Mask . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( ( M % Size ) != i ) return false ; int Src = M / Size ; if ( ParitySrc [ i % <NUM_LIT> ] >= <NUM_LIT> && ParitySrc [ i % <NUM_LIT> ] != Src ) return false ; ParitySrc [ i % <NUM_LIT> ] = Src ; } if ( ParitySrc [ <NUM_LIT> ] < <NUM_LIT> || ParitySrc [ <NUM_LIT> ] < <NUM_LIT> || ParitySrc [ <NUM_LIT> ] == ParitySrc [ <NUM_LIT> ] ) return false ;

IsSubAdd = ParitySrc [ <NUM_LIT> ] == <NUM_LIT> ? V1 -> getOpcode ( ) == <STR_LIT> : V2 -> getOpcode ( ) == <STR_LIT> ;


<s> MCSectionXCOFF * FnDescSec = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor ( & MF . getFunction ( ) , TM ) ) ; FnDescSec -> setAlignment ( Align ( Subtarget -> is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; CurrentFnDescSym = FnDescSec -> getQualNameSymbol ( ) ;

return AsmPrinter :: SetupMachineFunction ( MF ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( Offset . getExpr ( ) ) ) ; } else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ) { if ( inMicro<ISA_LIT>Mode ( ) ) Inst . setOpcode ( has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ) ; } else { if ( ! isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ) return Error ( IDLoc , <STR_LIT> ) ; if ( offsetToAlignment ( Offset . getImm ( ) , Align ( <NUM_LIT> ) ) ) return Error ( IDLoc , <STR_LIT> ) ;


<s> break ; case RSHIFT_EXPR : case LSHIFT_EXPR : case LROTATE_EXPR : case RROTATE_EXPR : { tree op2 = gimple_assign_rhs2 ( stmt_info -> stmt ) ; stmt_cost = ix86_shift_rotate_cost ( ix86_cost , mode , TREE_CODE ( op2 ) == INTEGER_CST , cst_and_fits_in_hwi ( op2 ) ? int_cst_value ( op2 ) : - <NUM_LIT> , true , false , false , NULL , NULL ) ; } break ; case NOP_EXPR : if ( tree_nop_conversion_p ( TREE_TYPE ( gimple_assign_lhs ( stmt_info -> stmt ) ) , TREE_TYPE ( gimple_assign_rhs1 ( stmt_info -> stmt ) ) ) ) stmt_cost = <NUM_LIT> ; break ; case BIT_IOR_EXPR : case ABS_EXPR : case ABSU_EXPR : case MIN_EXPR : case MAX_EXPR : case BIT_XOR_EXPR : case BIT_AND_EXPR : case BIT_NOT_EXPR : if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) stmt_cost = ix86_cost -> sse_op ; else if ( VECTOR_MODE_P ( mode ) ) stmt_cost = ix86_vec_cost ( mode , ix86_cost -> sse_op ) ; else stmt_cost = ix86_cost -> add ; break ; default : break ; } } combined_fn cfn ; if ( ( kind == vector_stmt || kind == scalar_stmt ) && stmt_info && stmt_info -> stmt && ( cfn = gimple_call_combined_fn ( stmt_info -> stmt ) ) != CFN_LAST ) switch ( cfn ) { case CFN_FMA : stmt_cost = ix86_vec_cost ( mode , mode == SFmode ? ix86_cost -> fmass : ix86_cost -> fmasd ) ; break ; default : break ; } if ( ( kind == vec_construct || kind == vec_to_scalar ) && stmt_info && ( STMT_VINFO_TYPE ( stmt_info ) == load_vec_info_type || STMT_VINFO_TYPE ( stmt_info ) == store_vec_info_type ) && STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_ELEMENTWISE && TREE_CODE ( DR_STEP ( STMT_VINFO_DATA_REF ( stmt_info ) ) ) != INTEGER_CST ) { stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost *= ( TYPE_VECTOR_SUBPARTS ( vectype ) + <NUM_LIT> ) ; } if ( stmt_cost == - <NUM_LIT> ) stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( TARGET_BONNELL && kind == vector_stmt && vectype && GET_MODE_INNER ( TYPE_MODE ( vectype ) ) == DFmode ) stmt_cost *= <NUM_LIT> ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( ( TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_GOLDMONT_PLUS || TARGET_TREMONT || TARGET_INTEL ) && stmt_info && stmt_info -> stmt ) {

tree lhs_op = gimple_get_lhs ( stmt_info -> stmt ) ;


return ( poly8x16_t ) __builtin_neon_vcntv16qi ( ( int8x16_t ) __a ) ;


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { return true ;


<s> MachineInstr * MI = getReturnInstr ( MBB ) ;

bool IsReturn = ( MBB -> succ_size ( ) == <NUM_LIT> ) ;


return ( uint64x2_t ) ( __a > __AARCH64_INT64_C ( <NUM_LIT> ) ) ;


<s> SDLoc dl ( Op ) ; if ( ( InVTElt == <STR_LIT> ) && ( ( ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget . hasBWI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget . hasDQI ( ) && Subtarget . hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) || ( ( Subtarget . hasDQI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) { if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( In . getOpcode ( ) , dl , VT , In . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; } assert ( InVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT ExtVT = NumElts == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue NegOne = DAG . getConstant ( APInt :: getAllOnesValue ( ExtVT . getScalarSizeInBits ( ) ) , dl , ExtVT ) ;

SDValue Zero = DAG . getConstant ( APInt :: getNullValue ( ExtVT . getScalarSizeInBits ( ) ) , dl , ExtVT ) ;


<s> auto F = MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ; if ( F . isNaN ( ) && F . isSignaling ( ) ) return false ; return ! F . isDenormal ( ) || denormalsEnabledForType ( MRI . getType ( Reg ) , MF ) ; } if ( MaxDepth == <NUM_LIT> ) return false ; switch ( Opcode ) { case <STR_LIT> :


<s> for ( const CalleeSavedInfo & CCSI : reverse ( CSI ) ) { unsigned Reg = CCSI . getReg ( ) ; bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( IsNotLiveIn ) { MBB . addLiveIn ( Reg ) ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; CalleeFrameSize += <NUM_LIT> ; } <ISA_LIT>Z80FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


<s> bool hasBase ( ) const { return Base != <NUM_LIT> ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI . eraseFromParent ( ) ;


<s> insn = get_insns ( ) ; pop_topmost_sequence ( ) ; for ( ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) { enum attr_type type = get_attr_type ( insn ) ;

if ( type == TYPE_LDSYM || type == TYPE_JSR ) return <NUM_LIT> ;


<s> rtx func_addr = func_desc ; gcc_assert ( INTVAL ( cookie ) == <NUM_LIT> ) ; if ( global_tlsarg ) tlsarg = global_tlsarg ; if ( GET_CODE ( func_desc ) != SYMBOL_REF && DEFAULT_ABI == ABI_ELFv2 ) { r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( r12 , func_desc ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ;


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( Type * SrcTy , Type * DstTy ) const { if ( ! SrcTy -> isIntegerTy ( ) || ! DstTy -> isIntegerTy ( ) ) return false ; return SrcTy -> getPrimitiveSizeInBits ( ) > DstTy -> getPrimitiveSizeInBits ( ) ;


<s> return CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ;


<s> if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ; } return TargetLowering :: LowerXConstraint ( ConstraintVT ) ;


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { addPass ( create<ISA_LIT>PrologEpilogPass ( ) , false ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> switch ( mode ) { case <ISA_LIT>II :: LoopEQ : return <ISA_LIT>II :: LoopEQ ; case <ISA_LIT>II :: LoopNE : return <ISA_LIT>II :: LoopNE ; case <ISA_LIT>II :: LoopLT : return <ISA_LIT>II :: LoopGT ;

case <ISA_LIT>II :: LoopLE : return <ISA_LIT>II :: LoopGE ;


<s> if ( isa < LSBaseSDNode > ( MemN ) || ( ( MemN -> getOpcode ( ) == <STR_LIT> || MemN -> getOpcode ( ) == <STR_LIT> ) && MemN -> getConstantOperandVal ( MemN -> getNumOperands ( ) - <NUM_LIT> ) == <NUM_LIT> ) ) { unsigned MMOAlign = MemN -> getAlignment ( ) ; unsigned MemSize = MemN -> getMemoryVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( MMOAlign >= MemSize && MemSize > <NUM_LIT> ) Alignment = MemSize ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM , TM . getOptLevel ( ) ) , Lowering ( * TM . getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ; if ( GET_CODE ( addr ) == CONST ) { if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ; } else if ( GET_CODE ( addr ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ;


<s> char loop_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; output_asm_insn ( <STR_LIT> , xops ) ; if ( TARGET_ARCH64 ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , loop_lab ) ; fputc ( '\n' , asm_out_file ) ; xops [ <NUM_LIT> ] = GEN_INT ( SPARC_STACK_BIAS ) ;


<s> if ( isa < FixedVectorType > ( ValTy ) && ISD == <STR_LIT> ) { const int AmortizationCost = <NUM_LIT> ; if ( VecPred == CmpInst :: BAD_ICMP_PREDICATE && I && I -> getType ( ) == ValTy ) { CmpInst :: Predicate CurrentPred ; if ( match ( I , m_Select ( m_Cmp ( CurrentPred , m_Value ( ) , m_Value ( ) ) , m_Value ( ) , m_Value ( ) ) ) ) VecPred = CurrentPred ; } if ( CmpInst :: isIntPredicate ( VecPred ) ) { static const auto ValidMinMaxTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; } static const TypeConversionCostTblEntry VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost }


<s> unsigned AS = GV -> getType ( ) -> getAddressSpace ( ) ; NameStr += getSymbolPrefixForAddressSpace ( AS ) ; } SmallString < <NUM_LIT> > Mangled ; SmallString < <NUM_LIT> > Sanitized ; getNameWithPrefix ( Mangled , GV ) ; NameStr += Mangled ;

if ( <STR_LIT> ( Mangled , Sanitized ) ) NameStr += Sanitized ;


<s> bool reg_offset_p = reg_offset_addressing_ok_p ( mode ) ; bool quad_offset_p = mode_supports_vsx_dform_quad ( mode ) ; if ( VECTOR_MEM_ALTIVEC_P ( mode ) && GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( x , <NUM_LIT> ) ) == - <NUM_LIT> ) x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return <NUM_LIT> ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return <NUM_LIT> ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , <NUM_LIT> ) , reg_ok_strict ) ) return <NUM_LIT> ; if ( quad_offset_p ) { if ( quad_address_p ( x , mode , reg_ok_strict ) ) return <NUM_LIT> ; } else if ( virtual_stack_registers_memory_p ( x ) ) return <NUM_LIT> ; else if ( reg_offset_p ) {

if ( legitimate_small_data_p ( mode , x ) ) return <NUM_LIT> ;


<s> static unsigned int tilepro_function_arg_boundary ( machine_mode mode , const_tree type ) { unsigned int alignment ; alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ;


<s> TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>beTarget , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>leTarget , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>beTarget , create<ISA_LIT>beAsmBackend ) ; if ( sys :: IsLittleEndianHost ) { TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; } else { TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>beAsmBackend ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const {


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = {


<s> static void checkIs32 ( MCContext & Ctx , SMLoc Loc , <ISA_LIT>_64RelType Type ) {

if ( Type != RT64_32 ) Ctx . reportError ( Loc , <STR_LIT> ) ;


<s> O << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << ( int32_t ) Op . getImm ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; if ( MO . isUse ( ) ) Uses . push_back ( MO . getReg ( ) ) ; if ( MO . isDef ( ) ) Defs . push_back ( MO . getReg ( ) ) ; }


<s> const uint32_t <ISA_LIT>v6T2_NopEncoding = <NUM_LIT> ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write16 ( nopEncoding ) ; if ( Count & <NUM_LIT> ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? <ISA_LIT>v6T2_NopEncoding : <ISA_LIT>v4_NopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % <NUM_LIT> ) { default : break ;

case <NUM_LIT> : OW -> Write8 ( <NUM_LIT> ) ; break ;


<s> SMLoc ErrorLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseIdentifier ( Format ) ) return Error ( ErrorLoc , <STR_LIT> ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Operands ; auto EntryRange = std :: equal_range ( std :: begin ( InsnMatchTable ) , std :: end ( InsnMatchTable ) , Format , CompareInsn ( ) ) ; if ( EntryRange . first == EntryRange . second ) return Error ( ErrorLoc , <STR_LIT> ) ; struct InsnMatchEntry * Entry = EntryRange . first ; assert ( Entry -> Format == Format ) ; for ( int i = <NUM_LIT> ; i < Entry -> NumOperands ; i ++ ) { MatchClassKind Kind = Entry -> OperandKinds [ i ] ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( StartLoc , <STR_LIT> ) ; Lex ( ) ; OperandMatchResultTy ResTy ; if ( Kind == MCK_AnyReg ) ResTy = parseAnyReg ( Operands ) ; else if ( Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20 ) ResTy = parseBDXAddr64 ( Operands ) ; else if ( Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20 ) ResTy = parseBDAddr64 ( Operands ) ; else if ( Kind == MCK_PCRel32 ) ResTy = parsePCRel32 ( Operands ) ; else if ( Kind == MCK_PCRel16 ) ResTy = parsePCRel16 ( Operands ) ; else { const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( Expr ) ) return Error ( StartLoc , <STR_LIT> ) ; SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ; ResTy = MatchOperand_Success ; } if ( ResTy != MatchOperand_Success ) return true ; } MCInst Inst = MCInstBuilder ( Entry -> Opcode ) ; for ( size_t i = <NUM_LIT> ; i < Operands . size ( ) ; i ++ ) {

MCParsedAsmOperand & Operand = * Operands [ i ] ;