<s> if ( ! ArgFlags . isInConsecutiveRegsLast ( ) ) return true ; auto & DL = State . getMachineFunction ( ) . getDataLayout ( ) ; unsigned StackAlign = DL . getStackAlignment ( ) . value ( ) ; unsigned Align = std :: min ( PendingMembers [ <NUM_LIT> ] . getExtraInfo ( ) , StackAlign ) ; ArrayRef < MCPhysReg > RegList ; switch ( LocVT . SimpleTy ) { case <STR_LIT> : { RegList = RRegList ; unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; unsigned RegAlign = alignTo ( Align , <NUM_LIT> ) / <NUM_LIT> ; while ( RegIdx % RegAlign != <NUM_LIT> && RegIdx < RegList . size ( ) ) State . AllocateReg ( RegList [ RegIdx ++ ] ) ; break ; } case <STR_LIT> : case <STR_LIT> : RegList = SRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Size ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return true ; } else if ( LocVT != <STR_LIT> ) RegList = SRegList ;

for ( auto Reg : RegList ) State . AllocateReg ( Reg ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerSDIV ( Op , DAG ) ; case <STR_LIT> : return LowerUDIV ( Op , DAG ) ;


<s> void <ISA_LIT>TargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const {

TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ;


<s> if ( ! It -> isDebugInstr ( ) ) { InstrExec . insert ( & * It ) ; visitNonBranch ( * It ) ; } ++ It ; } if ( It != End ) { visitBranchesFrom ( * It ) ; } else { unsigned SBN = SB -> getNumber ( ) ; for ( const MachineBasicBlock * SSB : SB -> successors ( ) ) FlowQ . push ( CFGEdge ( SBN , SSB -> getNumber ( ) ) ) ; } } LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; Cells . print ( dbgs ( ) , MCE . TRI ) ; dbgs ( ) << <STR_LIT> ; for ( const MachineBasicBlock & B : MF ) { unsigned BN = B . getNumber ( ) ; for ( const MachineBasicBlock * SB : B . successors ( ) ) { unsigned SN = SB -> getNumber ( ) ;

if ( ! EdgeExec . count ( CFGEdge ( BN , SN ) ) ) dbgs ( ) << <STR_LIT> << printMBBReference ( B ) << <STR_LIT> << printMBBReference ( * SB ) << '\n' ;


<s> return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ;


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; if ( ! FPSI ) { int FPOffset = Subtarget . getFrameLowering ( ) -> getFramePointerSaveOffset ( ) ; FPSI = MF . getFrameInfo ( ) . CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Neg , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Cmp . getValue ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = N1 . getValueType ( ) . bitsLT ( ShiftVT ) ? <STR_LIT> : <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } SDValue ExpandArg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , ExpandArg , N1 ) ) ; } case <STR_LIT> :


<s> if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( TARGET_USE_GOT && ( regno ) == GOT_VERSION_REGNUM ) return true ; if ( cfun -> machine -> interrupt_handler_p && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return false ;


<s> unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool FP = hasFP ( MF ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BaseRegister = FP ? <STR_LIT> : <STR_LIT> ; MI . getOperand ( i ) . ChangeToRegister ( BaseRegister , false ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; Offset += MF . getFrameInfo ( ) -> getStackSize ( ) ; if ( Offset <= <NUM_LIT> && Offset >= - <NUM_LIT> ) { MI . getOperand ( i ) . ChangeToRegister ( <STR_LIT> , false ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( BaseRegister ) . addImm ( Offset ) ; } else { MI . getOperand ( i ) . ChangeToRegister ( <STR_LIT> , false ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( Offset ) ;

BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( BaseRegister ) . addReg ( <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: getStackSlotRange ( const TargetRegisterClass * RC , unsigned SubIdx , unsigned & Size , unsigned & Offset , const MachineFunction & MF ) const { Size = <NUM_LIT> ; Offset = <NUM_LIT> ;


<s> SDValue XformMskToBitPosU5Imm ( uint32_t Imm , const SDLoc & DL ) { int32_t bitPos ; bitPos = Log2_32 ( Imm ) ; assert ( bitPos >= <NUM_LIT> && bitPos < <NUM_LIT> && <STR_LIT> ) ; return CurDAG -> getTargetConstant ( bitPos , DL , <STR_LIT> ) ;


<s> SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue ConstTrue = CurDAG -> getConstant ( N -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : <NUM_LIT> , dl , VT ) ; SDValue ConstFalse = CurDAG -> getConstant ( <NUM_LIT> , dl , VT ) ; do { SDNode * User = * N -> use_begin ( ) ; if ( User -> getNumOperands ( ) != <NUM_LIT> ) break ; auto TryFold = [ this , N , User , dl ] ( SDValue Val ) { SDValue UserO0 = User -> getOperand ( <NUM_LIT> ) , UserO1 = User -> getOperand ( <NUM_LIT> ) ; SDValue O0 = UserO0 . getNode ( ) == N ? Val : UserO0 ; SDValue O1 = UserO1 . getNode ( ) == N ? Val : UserO1 ; return CurDAG -> FoldConstantArithmetic ( User -> getOpcode ( ) , dl , User -> getValueType ( <NUM_LIT> ) , O0 . getNode ( ) , O1 . getNode ( ) ) ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; UseHardFloat = false ; UseHardFloatABI = false ; HasFPUv2SingleFloat = false ; HasFPUv2DoubleFloat = false ; HasFPUv3SingleFloat = false ; HasFPUv3DoubleFloat = false ; HasBTST16 = false ; HasJAVA = false ; HasExtendLrw = false ; HasDoloop = false ; HasHighRegisters = false ;


<s> for ( uint64_t i = <NUM_LIT> ; i < ( SizeVal / CapSize ) ; i ++ ) { uint64_t DstOff = i * CapSize ; SDValue Store = DAG . getStore ( Chain , dl , ZeroCap , DAG . getMemBasePlusOffset ( Dst , TypeSize :: Fixed ( DstOff ) , dl ) , DstPtrInfo . getWithOffset ( DstOff ) , Alignment , isVolatile ? MachineMemOperand :: MOVolatile : MachineMemOperand :: MONone ) ; OutChains . push_back ( Store ) ; } uint64_t Remainder = SizeVal % CapSize ; SDValue Zero64 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; uint64_t Done = ( SizeVal / CapSize ) * CapSize ; while ( Remainder >= <NUM_LIT> ) { SDValue Store = DAG . getStore ( Chain , dl , Zero64 , DAG . getMemBasePlusOffset ( Dst , TypeSize :: Fixed ( Done ) , dl ) , DstPtrInfo . getWithOffset ( Done ) , Alignment , isVolatile ? MachineMemOperand :: MOVolatile : MachineMemOperand :: MONone ) ; OutChains . push_back ( Store ) ; Done += <NUM_LIT> ; Remainder -= <NUM_LIT> ; } while ( Remainder > <NUM_LIT> ) { SDValue Zero = Zero64 ; uint64_t DstOff ; switch ( Remainder ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : Zero = Zero64 ; DstOff = SizeVal - <NUM_LIT> ; Remainder -= <NUM_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; ; DstOff = SizeVal - Remainder ; Remainder -= <NUM_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; ; DstOff = SizeVal - Remainder ; Remainder -= <NUM_LIT> ; break ; case <NUM_LIT> : Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; ; DstOff = SizeVal - Remainder ; Remainder -= <NUM_LIT> ; break ; } SDValue Store = DAG . getStore ( Chain , dl , Zero , DAG . getMemBasePlusOffset ( Dst , TypeSize :: Fixed ( DstOff ) , dl ) , DstPtrInfo . getWithOffset ( DstOff ) , Alignment , isVolatile ? MachineMemOperand :: MOVolatile : MachineMemOperand :: MONone ) ; OutChains . push_back ( Store ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ; }


<s> emitSled ( MI , SledKind :: FUNCTION_EXIT ) ;


<s> op_chain = regrename_chain_from_id ( info -> op_info [ i ] . heads [ <NUM_LIT> ] -> id ) ; involved_chains . safe_push ( op_chain ) ; tmp_mask &= ~ ( <NUM_LIT> << i ) ; } if ( involved_chains . length ( ) > <NUM_LIT> ) goto out_fail ; this_head = involved_chains [ <NUM_LIT> ] ; if ( this_head -> cannot_rename ) goto out_fail ; for ( chain = this_head -> first ; chain ; chain = chain -> next_use ) { unsigned int mask1 , mask2 , mask_changed ; int count , side1 , side2 , req1 , req2 ; insn_rr_info * this_rr = & insn_rr [ INSN_UID ( chain -> insn ) ] ; count = get_unit_reqs ( chain -> insn , & req1 , & side1 , & req2 , & side2 ) ; if ( count == <NUM_LIT> ) goto out_fail ; if ( ! get_unit_operand_masks ( chain -> insn , & mask1 , & mask2 ) ) goto out_fail ; extract_insn ( chain -> insn ) ; mask_changed = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) { int j ; int n_this_op = this_rr -> op_info [ i ] . n_chains ; for ( j = <NUM_LIT> ; j < n_this_op ; j ++ ) {

du_head_p other = this_rr -> op_info [ i ] . heads [ j ] ;


<s> if ( TT . isOSBinFormatELF ( ) ) return llvm :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) || TT . isWindowsCoreCLREnvironment ( ) ) return llvm :: make_unique < <ISA_LIT>WindowsTargetObjectFile > ( ) ;

if ( TT . isOSBinFormatCOFF ( ) ) return llvm :: make_unique < TargetLoweringObjectFileCOFF > ( ) ;


<s> if ( Val == DoubleToBits ( <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return <NUM_LIT> ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> unsigned Opc = MI . getOpcode ( ) ; int VOP3Idx [ <NUM_LIT> ] = { <STR_LIT> ( Opc , <STR_LIT> :: src0 ) , <STR_LIT> ( Opc , <STR_LIT> :: src1 ) , <STR_LIT> ( Opc , <STR_LIT> :: src2 ) } ; int ConstantBusLimit = ST . getConstantBusLimit ( Opc ) ; int LiteralLimit = ST . hasVOP3Literal ( ) ? <NUM_LIT> : <NUM_LIT> ; SmallDenseSet < unsigned > SGPRsUsed ; unsigned SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; if ( SGPRReg != <STR_LIT> ) { SGPRsUsed . insert ( SGPRReg ) ; -- ConstantBusLimit ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx == - <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) { if ( ! isLiteralConstantLike ( MO , get ( Opc ) . OpInfo [ Idx ] ) ) continue ; if ( LiteralLimit > <NUM_LIT> && ConstantBusLimit > <NUM_LIT> ) { -- LiteralLimit ; -- ConstantBusLimit ; continue ; } -- LiteralLimit ; -- ConstantBusLimit ; legalizeOpWithMove ( MI , Idx ) ;


<s> case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ;

case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ;


<s> CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; PCSymbol = <STR_LIT> ;


<s> set_optab_libfunc ( udiv_optab , HImode , <STR_LIT> ) ;

set_optab_libfunc ( smod_optab , HImode , <STR_LIT> ) ;


<s> const auto * RegInfo = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; return MFI -> isFrameAddressTaken ( ) || MFI -> hasVarSizedObjects ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ;


<s> bool m68k_legitimate_constant_p ( machine_mode mode , rtx x ) { return mode != XFmode && ! m68k_illegitimate_symbolic_constant_p ( x ) ;


<s> <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ;

EmitToStreamer ( * OutStreamer , TmpInst ) ;


<s> int mmix_local_regno ( int regno ) { return regno <= MMIX_LAST_STACK_REGISTER_REGNUM && ! call_used_regs [ regno ] ;


<s> SDValue Tmp1 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT SrcVT = Tmp1 . getValueType ( ) ; SDValue AbsVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp0 ) ;

SDValue Cmp = getVFPCmp ( Tmp1 , DAG . getConstantFP ( <NUM_LIT> , SrcVT ) , DAG , dl ) ;


<s> SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> ) Cond = Cond . getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) != <STR_LIT> || ! Cond . hasOneUse ( ) ) return false ; MVT VT = Cond . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( VT == <STR_LIT> ) return true ; if ( VT == <STR_LIT> ) { auto ST = static_cast < const <ISA_LIT>Subtarget * > ( Subtarget ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return ( CC == <STR_LIT> || CC == <STR_LIT> ) && ST -> hasScalarCompareEq64 ( ) ; } return false ;


<s> } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( needsLowering ) { Addr . Base . Reg = fastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . Base . Reg , false , Addr . Offset , <STR_LIT> ) ;


<s> if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && ! <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } else {

return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ;


<s> auto * I = dyn_cast < Instruction > ( V ) ; if ( ! I ) return false ; switch ( I -> getOpcode ( ) ) { case Instruction :: Add : if ( Match ( I -> getOperand ( <NUM_LIT> ) ) || ( Match ( I -> getOperand ( <NUM_LIT> ) ) ) ) return true ; break ; case Instruction :: Mul : { Value * Op0 = I -> getOperand ( <NUM_LIT> ) ; Value * Op1 = I -> getOperand ( <NUM_LIT> ) ; if ( IsExtendingLoad < SExtInst , <NUM_LIT> > ( Op0 ) && IsExtendingLoad < SExtInst , <NUM_LIT> > ( Op1 ) ) { ValueList LHS = { cast < SExtInst > ( Op0 ) -> getOperand ( <NUM_LIT> ) , Op0 } ; ValueList RHS = { cast < SExtInst > ( Op1 ) -> getOperand ( <NUM_LIT> ) , Op1 } ; Candidates . push_back ( make_unique < BinOpChain > ( I , LHS , RHS ) ) ; } return false ; } case Instruction :: SExt : return Match ( I -> getOperand ( <NUM_LIT> ) ) ; } return false ; } ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) return true ;

return ( RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { if ( Val ) return false ;

MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> NumOpsAdded = <NUM_LIT> ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; <STR_LIT> AddrOpcode = getUBit ( insn ) ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOp = getShiftOpcForBits ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned ShImm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; getImmShiftSE ( ShOp , ShImm ) ;

MI . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ( AddrOpcode , ShImm , ShOp ) ) ) ;


<s> const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned PC ; if ( STI . isPICStyleGOT ( ) ) PC = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; else PC = GlobalBaseReg ; if ( STI . is64Bit ( ) ) { if ( TM -> getCodeModel ( ) == CodeModel :: Medium ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , PC ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( TM -> getCodeModel ( ) == CodeModel :: Large ) { Register PBReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; Register GOTReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , PBReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( MF . getPICBaseSymbol ( ) ) . addReg ( <NUM_LIT> ) ; std :: prev ( MBBI ) -> setPreInstrSymbol ( MF , MF . getPICBaseSymbol ( ) ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , GOTReg ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , PC ) . addReg ( PBReg , RegState :: Kill ) . addReg ( GOTReg , RegState :: Kill ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , PC ) . addImm ( <NUM_LIT> ) ; if ( STI . isPICStyleGOT ( ) ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; } } return true ;


<s> DarwinDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; UseSoftFloat = false ; HasAltivec = false ; HasSPE = false ; HasQPX = false ; HasVSX = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ;


<s> if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; S -> EmitBundleAlignMode ( Log2 ( MIPS_NACL_BUNDLE_ALIGN ) ) ; return S ;


<s> <ISA_LIT>MCExpr :: VariantKind <ISA_LIT>MCExpr :: getVariantKindForName ( StringRef name ) {

return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;


<s> else FrameReg = getFrameRegister ( MF ) ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false ) ;

MI . getOperand ( OpNo + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned DNum = CSI [ i ] . getReg ( ) - <STR_LIT> ; if ( DNum >= <NUM_LIT> ) continue ; int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectAlignment ( FI , DNum % <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( DNum == <NUM_LIT> ) MFI . setObjectAlignment ( FI , MFI . getMaxAlignment ( ) ) ; } bool isThumb = AFI -> isThumbFunction ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; AFI -> setShouldRestoreSPFromFP ( true ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * NumAlignedDPRCS2Regs ) ) ) ; unsigned MaxAlign = MF . getFrameInfo ( ) -> getMaxAlignment ( ) ; emitAligningInstructions ( MF , AFI , TII , MBB , MI , DL , <STR_LIT> , MaxAlign , true ) ;


<s> SDLoc dl ( Op ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; MVT ResVT = Op . getSimpleValueType ( ) ; MVT InVT = In . getSimpleValueType ( ) ;


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; MCRegister RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: isConstantLoad ( const MemSDNode * N , int CbId ) const {

if ( ! N -> readMem ( ) ) return false ;


<s> bool sh2a_function_vector_p ( tree func ) {

if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ;


<s> if ( N . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> ) { SDValue Index = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDNode * Extract = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , VT , N , Index ) ; return SDValue ( Extract , <NUM_LIT> ) ; }

assert ( N . getValueType ( ) == VT && <STR_LIT> ) ;


int WaitStatesNeededForUse = AccVgprReadLdStWaitStates - getWaitStatesSinceDef ( Reg , IsAccVgprReadFn , MaxWaitStates ) ;


<s> if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && FloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && FloatDomain ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ; return true ; }


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>Disassembler ) ;

TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>Disassembler ) ;


<s> void adds3_6ImmOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; uint64_t Flags = MCID . TSFlags ; return ( Flags & <STR_LIT> ) != <NUM_LIT> ;


<s> vmul_n_u32 ( uint32x2_t a , uint32_t b ) { uint32x2_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> ComplexRendererFns selectArithShiftedRegister ( MachineOperand & Root ) const {


<s> CMPTermImag8_match ( Register & LHS , Register & RHS , Register & Flag ) : Cmp_match ( LHS , Flag ) , RHS ( RHS ) {


<s> if ( PredEdge -> isWeak ( ) ) { -- PredSU -> WeakSuccsLeft ; return ; } if ( PredSU -> NumSuccsLeft == <NUM_LIT> ) { dbgs ( ) << <STR_LIT> ; PredSU -> dump ( this ) ; dbgs ( ) << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } -- PredSU -> NumSuccsLeft ; if ( PredSU -> NumSuccsLeft == <NUM_LIT> && PredSU != & EntrySU ) SchedImpl -> releaseBottomNode ( PredSU ) ;


<s> unsigned AMDGPUFrameLowering :: getStackWidth ( const MachineFunction & MF ) const { return <NUM_LIT> ;


<s> void <ISA_LIT>RegisterSema :: updateEFLAGS ( Value * Def ) { LastEFLAGSChangingDef = <NUM_LIT> ; getReg ( <STR_LIT> ) ;


<s> return __builtin_mve_veorq_uv16qi ( __a , __b ) ;


<s> int64_t Offset = N -> getOffset ( ) ; MVT XLenVT = <STR_LIT> ; const GlobalValue * GV = N -> getGlobal ( ) ;

bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> return ( __m512i ) __builtin_ia32_loaddqudi512_mask ( ( const long long * ) __P , ( __v8di ) __W , ( __mmask8 ) __U ) ;


Result = evaluateAsInt64 ( Value . getConstant ( ) ) ;


<s> int <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ;

return vectorCostAdjustment ( LT . first , Instruction :: ShuffleVector , Tp , nullptr ) ;


<s> return IR . first . Wdh == <NUM_LIT> && ( IR . first . Off == <NUM_LIT> || IR . first . Off == <NUM_LIT> ) ; } ; auto End = llvm :: remove_if ( LL , IsCopy ) ;

if ( End != LL . end ( ) ) LL . erase ( End , LL . end ( ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> assert ( FrameBaseLocal != - <NUM_LIT> && <STR_LIT> ) ;


<s> if ( IDVal == <STR_LIT> ) return parseDirectiveAttribute ( ) ; return true ;


<s> } Options . setMacro ( ) ; Parser . Lex ( ) ; return false ;


<s> static enum loongarch_symbol_type loongarch_classify_symbol ( const_rtx x ) {

if ( LABEL_REF_P ( x ) ) return SYMBOL_GOT_DISP ;


<s> static bool IsStackChange ( MachineInstr & MI ) { return MI . modifiesRegister ( <STR_LIT> , NULL ) || MI . modifiesRegister ( <STR_LIT> , NULL ) ;


<s> if ( isUInt < <NUM_LIT> > ( imm ) ) CmpOpc = CmpiOpc ; else if ( ( ! ImmSigned && isUInt < <NUM_LIT> > ( imm ) ) || ( ImmSigned && isInt < <NUM_LIT> > ( imm ) ) ) CmpOpc = CmpiXOpc ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addImm ( imm ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( BtOpc ) ) . addMBB ( target ) ; MI -> eraseFromParent ( ) ; return BB ;


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ;

return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : Op = AtomicRMWInst :: UMin ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Op = AtomicRMWInst :: Max ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Op = AtomicRMWInst :: UMax ; break ; } const unsigned ValIdx = <NUM_LIT> ; const bool ValDivergent = DA -> isDivergent ( I . getOperand ( ValIdx ) ) ; if ( ValDivergent && ( ! HasDPP || ( DL -> getTypeSizeInBits ( I . getType ( ) ) != <NUM_LIT> ) ) ) { return ; } for ( unsigned Idx = <NUM_LIT> ; Idx < I . getNumOperands ( ) ; Idx ++ ) { if ( DA -> isDivergent ( I . getOperand ( Idx ) ) ) { return ; }


<s> static bool isKnownNeverSNan ( SelectionDAG & DAG , SDValue Op ) {

if ( ! DAG . getTargetLoweringInfo ( ) . hasFloatingPointExceptions ( ) ) return true ;


<s> } emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , <NUM_LIT> ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ; return <NUM_LIT> ; } else { x = gen_compare_reg_1 ( compare_code , x , y ) ; y = const0_rtx ; gcc_assert ( GET_MODE ( x ) != CC_NOOVmode && GET_MODE ( x ) != CCX_NOOVmode ) ; emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ;

emit_insn ( gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , GET_MODE ( x ) , x , y ) , const1_rtx , dest ) ) ) ;


<s> case 'r' : if ( GET_CODE ( op ) == REG ) fputs ( reg_names [ REGNO ( op ) ] , file ) ; else fputs ( reg_names [ <NUM_LIT> ] , file ) ; return ; case 'f' : if ( GET_CODE ( op ) == REG ) fputs ( reg_names [ REGNO ( op ) ] , file ) ; else fputs ( reg_names [ FP_FIRST_REGNUM ] , file ) ; return ; } switch ( GET_CODE ( op ) ) { case REG : if ( letter == 'd' ) fputs ( reg_names [ REGNO ( op ) + <NUM_LIT> ] , file ) ; else fputs ( reg_names [ REGNO ( op ) ] , file ) ; break ; case SYMBOL_REF : case LABEL_REF : case CONST : output_addr_const ( file , op ) ; break ; case MEM : visium_output_address ( file , GET_MODE ( op ) , XEXP ( op , <NUM_LIT> ) ) ; break ; case CONST_INT : fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( op ) ) ; break ; case CODE_LABEL : asm_fprintf ( file , <STR_LIT> , CODE_LABEL_NUMBER ( op ) ) ; break ; case HIGH : print_operand ( file , XEXP ( op , <NUM_LIT> ) , letter ) ; break ;


<s> case MCSymbolRefExpr :: VK_WASM_TYPEINDEX : return <STR_LIT> ; default : break ; } switch ( unsigned ( Fixup . getKind ( ) ) ) { case <STR_LIT> : if ( SymA . isFunction ( ) ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( SymA . isFunction ( ) ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( SymA . isGlobal ( ) ) return <STR_LIT> ; if ( SymA . isFunction ( ) ) return <STR_LIT> ; if ( SymA . isEvent ( ) ) return <STR_LIT> ; if ( SymA . isTable ( ) ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : assert ( SymA . isData ( ) ) ; return <STR_LIT> ; case FK_Data_4 : if ( SymA . isFunction ( ) ) return <STR_LIT> ; if ( SymA . isGlobal ( ) ) return <STR_LIT> ; if ( auto Section = static_cast < const MCSectionWasm * > ( getFixupSection ( Fixup . getValue ( ) ) ) ) { if ( Section -> getKind ( ) . isText ( ) ) return <STR_LIT> ; else if ( ! Section -> isWasmData ( ) ) return <STR_LIT> ; } return <STR_LIT> ; case FK_Data_8 : if ( SymA . isFunction ( ) ) return <STR_LIT> ; if ( SymA . isGlobal ( ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DL ( Subtarget . getDataLayoutString ( ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> if ( A . isStringAttribute ( ) ) { StringRef Str = A . getValueAsString ( ) ; Str . getAsInteger ( <NUM_LIT> , ShaderType ) ; } if ( ShaderType == ShaderType :: COMPUTE ) return false ;


<s> } if ( ! EarlyTermInstrs . empty ( ) ) { MachineBasicBlock * EarlyExitBlock = MF . CreateMachineBasicBlock ( ) ; DebugLoc DL ; MF . insert ( MF . end ( ) , EarlyExitBlock ) ; BuildMI ( * EarlyExitBlock , EarlyExitBlock -> end ( ) , DL , TII -> get ( MovOpc ) , ExecReg ) . addImm ( <NUM_LIT> ) ; generateEndPgm ( * EarlyExitBlock , EarlyExitBlock -> end ( ) , DL , TII , MF ) ; for ( MachineInstr * Instr : EarlyTermInstrs ) { if ( MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: <ISA_LIT>_GS ) earlyTerm ( * Instr , EarlyExitBlock ) ; Instr -> eraseFromParent ( ) ; } EarlyTermInstrs . clear ( ) ; MadeChange = true ; } if ( ! EpilogInstrs . empty ( ) ) { MachineBasicBlock * EmptyMBBAtEnd = nullptr ; assert ( ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( EpilogInstrs . size ( ) > <NUM_LIT> ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } for ( auto MI : EpilogInstrs ) { auto MBB = MI -> getParent ( ) ; if ( MBB == & MF . back ( ) && MI == & MBB -> back ( ) ) continue ; if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB -> addSuccessor ( EmptyMBBAtEnd ) ; MDT -> getBase ( ) . insertEdge ( MBB , EmptyMBBAtEnd ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( EmptyMBBAtEnd ) ;


<s> assert ( MO . isImm ( ) || MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . isImm ( ) ? MCConstantExpr :: create ( MO . getImm ( ) , Ctx ) : MO . getExpr ( ) ;

Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , static_cast < MCFixupKind > ( <STR_LIT> ) , MI . getLoc ( ) ) ) ;


<s> static void packSplitRegsToOrigType ( MachineIRBuilder & B , ArrayRef < Register > OrigRegs , ArrayRef < Register > Regs , LLT LLTy , LLT PartLLT ) { MachineRegisterInfo & MRI = * B . getMRI ( ) ; if ( ! LLTy . isVector ( ) && ! PartLLT . isVector ( ) ) { assert ( OrigRegs . size ( ) == <NUM_LIT> ) ; LLT OrigTy = MRI . getType ( OrigRegs [ <NUM_LIT> ] ) ; unsigned SrcSize = PartLLT . getSizeInBits ( ) * Regs . size ( ) ; if ( SrcSize == OrigTy . getSizeInBits ( ) ) B . buildMerge ( OrigRegs [ <NUM_LIT> ] , Regs ) ; else { auto Widened = B . buildMerge ( LLT :: scalar ( SrcSize ) , Regs ) ; B . buildTrunc ( OrigRegs [ <NUM_LIT> ] , Widened ) ; } return ; } if ( LLTy . isVector ( ) && PartLLT . isVector ( ) ) { assert ( OrigRegs . size ( ) == <NUM_LIT> ) ; assert ( LLTy . getElementType ( ) == PartLLT . getElementType ( ) ) ; mergeVectorRegsToResultRegs ( B , OrigRegs , Regs ) ; return ; } assert ( LLTy . isVector ( ) && ! PartLLT . isVector ( ) ) ; LLT DstEltTy = LLTy . getElementType ( ) ; LLT RealDstEltTy = MRI . getType ( OrigRegs [ <NUM_LIT> ] ) . getElementType ( ) ; assert ( DstEltTy . getSizeInBits ( ) == RealDstEltTy . getSizeInBits ( ) ) ; if ( DstEltTy == PartLLT ) { if ( RealDstEltTy . isPointer ( ) ) { for ( Register Reg : Regs ) MRI . setType ( Reg , RealDstEltTy ) ; } B . buildBuildVector ( OrigRegs [ <NUM_LIT> ] , Regs ) ; } else if ( DstEltTy . getSizeInBits ( ) > PartLLT . getSizeInBits ( ) ) { SmallVector < Register , <NUM_LIT> > EltMerges ; int PartsPerElt = DstEltTy . getSizeInBits ( ) / PartLLT . getSizeInBits ( ) ; assert ( DstEltTy . getSizeInBits ( ) % PartLLT . getSizeInBits ( ) == <NUM_LIT> ) ; for ( int I = <NUM_LIT> , NumElts = LLTy . getNumElements ( ) ; I != NumElts ; ++ I ) {

auto Merge = B . buildMerge ( RealDstEltTy , Regs . take_front ( PartsPerElt ) ) ;


<s> if ( Opcode == <STR_LIT> ) { unsigned Temp = Reg1 ; Reg1 = Reg2 ; Reg2 = Temp ; } I . setOpcode ( Opcode ) ;

I . addOperand ( MCOperand :: CreateReg ( Reg1 ) ) ;


<s> StringRef getPassName ( ) const override { return SYSTEMZ_COPYPHYSREGS_NAME ;


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ;

if ( MO . isExpr ( ) ) return <NUM_LIT> ;


<s> } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( auto * AndRHS = dyn_cast < ConstantSDNode > ( Op1 ) ) { uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } if ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS ;

RHS = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , DL , LHS . getValueType ( ) ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } Register VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return Val ; return convertLocVTToValVT ( DAG , Val , VA , DL ) ;


<s> } DEBUG ( errs ( ) << <STR_LIT> ) ; return TargetTransformInfo ( BasicTTIImpl ( this , F ) ) ;


<s> case FK_DTPRel_8 : case FK_TPRel_4 : case FK_TPRel_8 : case FK_GPRel_4 : case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) {


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddrSImm10 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { return nullptr ;


<s> unsigned NumVariadicDefs = <NUM_LIT> ; if ( Desc . variadicOpsAreDefs ( ) ) { NumVariadicDefs = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Start = <NUM_LIT> ; } bool NeedsComma = Desc . getNumOperands ( ) > <NUM_LIT> && ! Desc . variadicOpsAreDefs ( ) ; for ( auto I = Start , E = MI -> getNumOperands ( ) ; I < E ; ++ I ) { if ( MI -> getOpcode ( ) == <STR_LIT> && I - Start == NumVariadicDefs ) { ++ I ; continue ; } if ( NeedsComma ) OS << <STR_LIT> ; printOperand ( MI , I , OS , I - Start < NumVariadicDefs ) ; NeedsComma = true ; } } printAnnotation ( OS , Annot ) ; if ( CommentStream ) { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowCounter ) + ':' ) ; ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter ++ , true ) ) ; return ; case <STR_LIT> : case <STR_LIT> : ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter ++ , false ) ) ; return ; case <STR_LIT> : case <STR_LIT> : ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter , false ) ) ; EHPadStack . push_back ( ControlFlowCounter ++ ) ; return ; case <STR_LIT> : case <STR_LIT> : if ( ControlFlowStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { ControlFlowStack . pop_back ( ) ; } return ; case <STR_LIT> : case <STR_LIT> : if ( ControlFlowStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowStack . pop_back_val ( ) . first ) + ':' ) ; } return ; case <STR_LIT> : case <STR_LIT> : if ( ControlFlowStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowStack . pop_back_val ( ) . first ) + ':' ) ; } return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( EHPadStack . empty ( ) ) { printAnnotation ( OS , <STR_LIT> ) ; } else { printAnnotation ( OS , <STR_LIT> + utostr ( EHPadStack . pop_back_val ( ) ) + ':' ) ; } return ; case <STR_LIT> : case <STR_LIT> : if ( EHPadStack . empty ( ) ) {


<s> EmitRawState ( <ISA_LIT>MCNaClSFIState & S ) : State ( S ) { State . EmitRaw = true ;


<s> assert ( MBB && TBB && FBB && <STR_LIT> ) ; std :: set < PHIEntryInfo > replacedPhisInfo ; std :: list < MachineInstr * > deadPhis ; MachineBasicBlock :: iterator MI ; for ( MI = MBB -> begin ( ) ; MI != MBB -> end ( ) && MI -> isPHI ( ) ; ++ MI ) { unsigned indexTBB = getPHISourceRegIndex ( * MI , FBB ) ; unsigned indexFBB = getPHISourceRegIndex ( * MI , TBB ) ; if ( indexTBB && indexFBB ) { unsigned destReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned valueTBB = MI -> getOperand ( indexTBB ) . getReg ( ) ; unsigned valueFBB = MI -> getOperand ( indexFBB ) . getReg ( ) ; PHIEntryInfo PEI ( destReg , std :: make_pair ( valueTBB , valueFBB ) ) ; assert ( ! replacedPhisInfo . count ( PEI ) && <STR_LIT> ) ; replacedPhisInfo . insert ( PEI ) ; assert ( MI -> getNumOperands ( ) < <NUM_LIT> && <STR_LIT> ) ; deadPhis . push_back ( MI ) ; }


<s> if ( VT . isVector ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) { EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Mid = truncateVectorWithPACK ( <STR_LIT> , MidVT , USatVal , DL , DAG , Subtarget ) ; if ( Mid ) return truncateVectorWithPACK ( <STR_LIT> , VT , Mid , DL , DAG , Subtarget ) ; } else if ( SVT == <STR_LIT> || Subtarget . hasSSE41 ( ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , USatVal , DL , DAG , Subtarget ) ; } }


<s> static int mcore_ior_cost ( rtx x ) { HOST_WIDE_INT val ;

if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ;


<s> uint64_t NotKnownZero = ( ~ Known . Zero ) . getZExtValue ( ) ; if ( ! isShiftedMask ( Known . Zero . getZExtValue ( ) , VT ) ) return false ; if ( ( OrImm & NotKnownZero ) != <NUM_LIT> ) { return false ; } int LSB = countTrailingOnes ( NotKnownZero ) ; int Width = BitWidth - APInt ( BitWidth , NotKnownZero ) . countPopulation ( ) ; unsigned ImmR = ( BitWidth - LSB ) % BitWidth ; unsigned ImmS = Width - <NUM_LIT> ; bool IsBFI = LSB != <NUM_LIT> ; uint64_t BFIImm = OrImm >> LSB ; if ( IsBFI && ! <STR_LIT> ( BFIImm , BitWidth ) ) { unsigned OrChunks = <NUM_LIT> , BFIChunks = <NUM_LIT> ; for ( unsigned Shift = <NUM_LIT> ; Shift < BitWidth ; Shift += <NUM_LIT> ) { if ( ( ( OrImm >> Shift ) & <NUM_LIT> ) != <NUM_LIT> ) ++ OrChunks ; if ( ( ( BFIImm >> Shift ) & <NUM_LIT> ) != <NUM_LIT> ) ++ BFIChunks ; } if ( BFIChunks > OrChunks ) return false ;


<s> MCContext & Ctx = MF -> getContext ( ) ; if ( MF -> getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) { EmitNop ( Ctx , * OutStreamer , <NUM_LIT> , getSubtargetInfo ( ) ) ; return ; }

MCSymbol * fentry = Ctx . getOrCreateSymbol ( <STR_LIT> ) ;


<s> ADefined = true ; AOffs = Target . getConstant ( ) + Layout . getFragmentOffset ( Fragment ) ; }

if ( ! Target . getSymB ( ) && ( ! ADefined || Target . getConstant ( ) == <NUM_LIT> || AOffs > <NUM_LIT> ) ) recordRegularRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue , FK ) ;


<s> void <ISA_LIT>InstPrinter :: printExtOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { const <ISA_LIT>MCInst * HMCI = static_cast < const <ISA_LIT>MCInst * > ( MI ) ; if ( HMCI -> isConstExtended ( ) ) O << <STR_LIT> ; printOperand ( MI , OpNo , O ) ;


<s> return isVectorIndexInRange < <NUM_LIT> > ( ) ;


<s> return ( __a + ( __b * __aarch64_vget_lane_any ( __c , __lane ) ) ) ;


<s> static __inline unsigned long long sh_media_MSHALDS_W ( unsigned long long mm , unsigned int mn ) {

typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ;


<s> ~ <ISA_LIT>SchedBoundary ( ) { delete ResourceModel ;


<s> bool Changed = false ; for ( auto * F : Functions ) { DominatorTree * DT = & getAnalysis < DominatorTreeWrapperPass > ( * F ) . getDomTree ( ) ; BasicBlock * Root = DT -> getRoot ( ) ; ReversePostOrderTraversal < BasicBlock * > RPOT ( Root ) ; for ( auto * BB : RPOT ) for ( Instruction & I : make_early_inc_range ( * BB ) ) Changed |= optimizeIntrinsic ( & I ) ; }


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new <ISA_LIT>PassConfig ( this , PM ) ;


<s> nelt_v16 = GET_MODE_NUNITS ( V16QImode ) ; if ( length >= nelt_v16 && unaligned_access && ! BYTES_BIG_ENDIAN ) mode = V16QImode ; else mode = V8QImode ; nelt_mode = GET_MODE_NUNITS ( mode ) ; gcc_assert ( length >= nelt_mode ) ; if ( ! arm_block_set_vect_profit_p ( length , align , mode ) ) return false ; dst = copy_addr_to_reg ( XEXP ( dstbase , <NUM_LIT> ) ) ; reg = gen_reg_rtx ( mode ) ; val_vec = gen_const_vec_duplicate ( mode , gen_int_mode ( value , QImode ) ) ; emit_move_insn ( reg , val_vec ) ; i = <NUM_LIT> ; if ( mode == V16QImode ) { mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; emit_insn ( gen_movmisalignv16qi ( mem , reg ) ) ; i += nelt_mode ; if ( i + nelt_v8 < length && i + nelt_v16 > length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( length - nelt_mode ) ) ) ; offset += length - nelt_mode ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; if ( ( length & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT * <NUM_LIT> ) ;

else if ( ( length & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT * <NUM_LIT> ) ;


<s> bool isVarArg = CLI . IsVarArg ; CLI . IsTailCall = false ; assert ( ! isVarArg && <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SDValue Glue ; for ( size_t i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; if ( VA . isRegLoc ( ) ) { Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RegsToPass . emplace_back ( VA . getLocReg ( ) , Arg ) ; } if ( isa < GlobalAddressSDNode > ( Callee ) ) Callee = LowerGlobalAddress ( Callee , DAG ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops { Chain , Callee } ; std :: transform ( RegsToPass . begin ( ) , RegsToPass . end ( ) , std :: back_inserter ( Ops ) , [ & ] ( std :: pair < unsigned , SDValue > & elt ) { return DAG . getRegister ( elt . first , elt . second . getValueType ( ) ) ; } ) ; if ( Glue . getNode ( ) ) Ops . push_back ( Glue ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( auto & Loc : RVLocs ) { auto RetValue = DAG . getCopyFromReg ( Chain , DL , Loc . getLocReg ( ) , Loc . getValVT ( ) , Glue ) ; Chain = RetValue . getValue ( <NUM_LIT> ) ; Glue = RetValue . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } } return Chain ;


<s> const MCSymbol * Symbol = CLI . Symbol ; if ( ! Callee && ! Symbol ) return false ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; Type * RetTy = CLI . RetTy ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; else if ( RetVT == <STR_LIT> && Subtarget -> useCRBits ( ) ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , IsVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , RetCC_<ISA_LIT>64_ELF_FIS ) ; if ( RVLocs . size ( ) > <NUM_LIT> ) return false ; } unsigned NumArgs = CLI . OutVals . size ( ) ; if ( NumArgs > <NUM_LIT> ) return false ; SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; Args . reserve ( NumArgs ) ;


<s> if ( ! Subtarget -> hasVFP2 ( ) || Subtarget -> isFPOnlySP ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ;

if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ;


<s> AU . addRequired < MachinePostDominatorTree > ( ) ; AU . setPreservesCFG ( ) ;

AU . addPreserved < LiveIntervals > ( ) ;


<s> explicit <ISA_LIT>FrameInfo ( const <ISA_LIT>Subtarget & sti ) : TargetFrameInfo ( TargetFrameInfo :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> return checkAsmConstraintValA ( Op , Val ) ; case 'B' : return isInt < <NUM_LIT> > ( Val ) ; case 'C' : return isUInt < <NUM_LIT> > ( clearUnusedBits ( Val , Op . getScalarValueSizeInBits ( ) ) ) || <STR_LIT> ( Val ) ; default : break ; } } else if ( Constraint . size ( ) == <NUM_LIT> ) { if ( Constraint == <STR_LIT> ) { int64_t HiBits = static_cast < int32_t > ( Val >> <NUM_LIT> ) ; int64_t LoBits = static_cast < int32_t > ( Val ) ; return checkAsmConstraintValA ( Op , HiBits , <NUM_LIT> ) && checkAsmConstraintValA ( Op , LoBits , <NUM_LIT> ) ;


<s> unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OpReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; warnIfNoMacro ( IDLoc ) ; if ( SrcReg != <STR_LIT> && OpReg != <STR_LIT> ) { TOut . emitRRR ( <STR_LIT> , DstReg , SrcReg , OpReg , IDLoc , STI ) ;

TOut . emitRRR ( <STR_LIT> , DstReg , <STR_LIT> , DstReg , IDLoc , STI ) ;


<s> MI . setDesc ( HII -> get ( NewOpcode ) ) ;


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( OpIdx ++ ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= encodeVFPRd ( MI , OpIdx + <NUM_LIT> ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; ++ NumRegs ; } Binary |= NumRegs * <NUM_LIT> ; emitWordLE ( Binary ) ;


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result ;


<s> MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEMI , U . getLongFormMaxDisp ( ) , U . NegOk , true ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; UserMI -> setDesc ( TII -> get ( U . getLongFormOpcode ( ) ) ) ; U . setMaxDisp ( U . getLongFormMaxDisp ( ) ) ; return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getLongFormMaxDisp ( ) , U . NegOk ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) { UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount ++ ; return decrementCPEReferenceCount ( CPI , CPEMI ) ? <NUM_LIT> : <NUM_LIT> ; } }


<s> void addImmShiftOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { O << <STR_LIT> ;


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> , <NUM_LIT> , false ) ;


<s> std :: vector < std :: string > mov2s ( Px a , ArRn2 b , ArStep2 bs ) {

return D ( <STR_LIT> , R ( a ) , MemARS ( b , bs ) ) ;


<s> return D ( <STR_LIT> , a , R ( b ) ) ;


<s> if ( ! isValidIndexedStore ( ST ) ) return NULL ; MVT VT = ST -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned Opcode = <NUM_LIT> ; switch ( VT . SimpleTy ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;


<s> case CONST_WIDE_INT : case CONST_VECTOR : return false ; case NEG : switch ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ) { case CONST_INT : case CONST_DOUBLE : case CONST_WIDE_INT : return false ; default : return true ; } case LABEL_REF : return flag_pic != <NUM_LIT> ; case SYMBOL_REF : if ( tls_symbolic_operand ( x ) ) return true ; else return flag_pic != <NUM_LIT> ; case CONST : return s390_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : return s390_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) ) || s390_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) ) ; case UNSPEC : switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_LTREL_OFFSET : case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : case UNSPEC_TLSGD : case UNSPEC_TLSLDM : case UNSPEC_NTPOFF : case UNSPEC_DTPOFF : case UNSPEC_GOTNTPOFF : case UNSPEC_INDNTPOFF : return false ; case UNSPEC_INSN : default : return true ; }


<s> } } else { const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; bool IsIndirect = Subtarget . isGVIndirectSymbol ( GV ) ; unsigned TargetFlags = <STR_LIT> ; if ( Subtarget . isTargetMachO ( ) ) { TargetFlags |= <STR_LIT> ; } else if ( Subtarget . isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) TargetFlags |= <STR_LIT> ; else if ( IsIndirect ) TargetFlags |= <STR_LIT> ; } else if ( Subtarget . isGVInGOT ( GV ) ) { TargetFlags |= <STR_LIT> ; } BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , TargetFlags ) ; if ( IsIndirect ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ;

MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ;


<s> MEM_VOLATILE_P ( mem ) = <NUM_LIT> ; return mem ;


<s> Mul = getMul24 ( DAG , DL , N0 , N1 , Size , false ) ; } else if ( Subtarget -> hasMulI24 ( ) && isI24 ( N0 , DAG ) && isI24 ( N1 , DAG ) ) { N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getSExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = getMul24 ( DAG , DL , N0 , N1 , Size , true ) ; } else { return SDValue ( ) ;


<s> bool isRegOrImmWithInputMods ( unsigned RCID , MVT type ) const { return isRegClass ( RCID ) || isInlinableImm ( type ) ;


<s> SmallVector < int , <NUM_LIT> > Mask ; if ( Subtarget . isHVXVectorType ( ResTy , true ) ) { unsigned Rep = VecTy . getVectorNumElements ( ) / ResLen ; assert ( isPowerOf2_32 ( Rep ) && HwLen % Rep == <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != HwLen / Rep ; ++ i ) { for ( unsigned j = <NUM_LIT> ; j != Rep ; ++ j ) Mask . push_back ( i + Offset ) ; } SDValue ShuffV = DAG . getVectorShuffle ( ByteTy , dl , ByteVec , Undef , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , ResTy , ShuffV ) ; } unsigned Rep = <NUM_LIT> / ResLen ; for ( unsigned r = <NUM_LIT> ; r != HwLen / ResLen ; ++ r ) { for ( unsigned i = <NUM_LIT> ; i != ResLen ; ++ i ) { for ( unsigned j = <NUM_LIT> ; j != Rep ; ++ j ) Mask . push_back ( Offset + i * BitBytes ) ; }


<s> if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { unsigned SuperReg = TRI -> getMatchingSuperReg ( DestReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && SrcReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; DestReg = SuperReg ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { unsigned SuperReg = TRI -> getMatchingSuperReg ( DestReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && SrcReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; DestReg = SuperReg ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned SuperReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && DestReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; SrcReg = SuperReg ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned SuperReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && DestReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; SrcReg = SuperReg ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned CRReg = getCRFromCRBit ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( CRReg ) ; getKillRegState ( KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ;

else if ( <STR_LIT> . contains ( DestReg , SrcReg ) || <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ;


<s> return ! CheckSingleUse || N -> hasOneUse ( ) ;


<s> bool <ISA_LIT>MCInstrInfo :: isCVINew ( MCInstrInfo const & MCII , MCInst const & MCI ) {

const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ;


<s> return NO_REGS ; } if ( mode == QImode && ( ( ! TARGET_64BIT && ! in_p && INTEGER_CLASS_P ( rclass ) && MAYBE_NON_Q_CLASS_P ( rclass ) ) || ( ! TARGET_AVX512DQ && MAYBE_MASK_CLASS_P ( rclass ) ) ) ) { int regno = true_regnum ( x ) ; if ( regno == - <NUM_LIT> ) return Q_REGS ; return NO_REGS ; } if ( ( mode == HFmode || mode == HImode || mode == V2QImode || mode == BFmode ) && ! TARGET_SSE4_1 && SSE_CLASS_P ( rclass ) && ! in_p && MEM_P ( x ) ) { sri -> extra_cost = <NUM_LIT> ;


<s> for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( mag_comparisons ) ; i ++ ) { HOST_WIDE_INT new_rhs ; bool increment = * code == mag_comparisons [ i ] [ <NUM_LIT> ] ; bool decrement = * code == mag_comparisons [ i ] [ <NUM_LIT> ] ; if ( ! increment && ! decrement ) continue ; if ( ( increment && rhs == HOST_WIDE_INT_MAX ) || ( decrement && rhs == HOST_WIDE_INT_MIN ) ) break ; new_rhs = rhs + ( increment ? <NUM_LIT> : - <NUM_LIT> ) ; if ( loongarch_integer_cost ( new_rhs ) < loongarch_integer_cost ( rhs ) ) { * op1 = GEN_INT ( new_rhs ) ; * code = mag_comparisons [ i ] [ increment ] ; } break ;


<s> const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ;

if ( TLOF -> IsConstantInSmallSection ( DAG . getDataLayout ( ) , N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>TargetMachine & tm , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] < Size ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) {


<s> AsmToken :: TokenKind kind = getLexer ( ) . getKind ( ) ; switch ( kind ) { default : return true ; case AsmToken :: Minus : case AsmToken :: Integer :

if ( getParser ( ) . parseExpression ( EVal ) ) return true ;


<s> arc_print_operand_address ( file , base ) ; if ( CONSTANT_P ( base ) && CONST_INT_P ( index ) ) fputc ( '+' , file ) ; else fputc ( ',' , file ) ; gcc_assert ( OBJECT_P ( index ) ) ; arc_print_operand_address ( file , index ) ; break ; case CONST : { rtx c = XEXP ( addr , <NUM_LIT> ) ; if ( ( GET_CODE ( c ) == UNSPEC && ( XINT ( c , <NUM_LIT> ) == UNSPEC_TLS_OFF || XINT ( c , <NUM_LIT> ) == UNSPEC_TLS_IE ) ) || ( GET_CODE ( c ) == PLUS && GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == UNSPEC && ( XINT ( XEXP ( c , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS_OFF || XINT ( XEXP ( c , <NUM_LIT> ) , <NUM_LIT> ) == ARC_UNSPEC_GOTOFFPC ) ) ) { arc_output_pic_addr_const ( file , c , <NUM_LIT> ) ; break ;


<s> if ( NumLaneElts == <NUM_LIT> ) return false ; for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { unsigned i ; for ( i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { if ( Mask [ i + l ] >= <NUM_LIT> ) break ; } if ( i == NumLaneElts ) continue ; int Start = Mask [ i + l ] ; if ( ! isUndefOrInRange ( Start , l , l + NumLaneElts ) && ! isUndefOrInRange ( Start , l + NumElts , l + NumElts + NumLaneElts ) ) return false ; if ( l != <NUM_LIT> && Mask [ i ] >= <NUM_LIT> && ! isUndefOrEqual ( Start , Mask [ i ] + l ) ) return false ; if ( Start >= ( int ) NumElts ) Start -= NumElts - NumLaneElts ; if ( Start <= ( int ) ( i + l ) ) return false ; Start -= i ; for ( ++ i ; i != NumLaneElts ; ++ i ) { int Idx = Mask [ i + l ] ; if ( ! isUndefOrInRange ( Idx , l , l + NumLaneElts ) && ! isUndefOrInRange ( Idx , l + NumElts , l + NumElts + NumLaneElts ) ) return false ; if ( l != <NUM_LIT> && Mask [ i ] >= <NUM_LIT> && ! isUndefOrEqual ( Idx , Mask [ i ] + l ) ) return false ;

if ( Idx >= ( int ) NumElts ) Idx -= NumElts - NumLaneElts ;


<s> for ( const SDUse & U : Op -> ops ( ) ) DAG . ExtractVectorElements ( U . get ( ) , Args ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Args ) ;


<s> void <ISA_LIT>AsmParser :: cvtSdwaVOP2 ( MCInst & Inst , const OperandVector & Operands ) { cvtSDWA ( Inst , Operands , <STR_LIT> ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> } else if ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ; } else if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && <STR_LIT> ) ;

emitToStreamer ( Out , MCInstBuilder ( Opcode ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> ) ) ;


<s> <ISA_LIT>AsmBackendELF ( const Target & T , StringRef TT , uint8_t OSABI , bool IsLittle ) : <ISA_LIT>AsmBackend ( T , TT , IsLittle ) , OSABI ( OSABI ) {


<s> MemOpClusterMutation ( const <ISA_LIT>InstrInfo * tii ) : TII ( tii ) {


<s> Fits = true ; } else if ( ( NumBytes & <NUM_LIT> ) == <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( NumBytes >> <NUM_LIT> ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Fits = true ; } if ( Fits ) { if ( isSub ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addReg ( DestReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) ; BaseReg = <STR_LIT> ; continue ; }


<s> inline SDValue XformM5ToU5Imm ( signed Imm , SDLoc DL ) { assert ( ( Imm >= - <NUM_LIT> && Imm <= - <NUM_LIT> ) && <STR_LIT> ) ;

return CurDAG -> getTargetConstant ( - Imm , DL , <STR_LIT> ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; int types [ ] = { ( int ) <STR_LIT> , ( int ) <STR_LIT> } ; size_t NumTypes = sizeof ( types ) / sizeof ( * types ) ; for ( unsigned int x = <NUM_LIT> ; x < NumTypes ; ++ x ) { <STR_LIT> VT = ( <STR_LIT> ) types [ x ] ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ;


return isImm ( ) && isa < MCConstantExpr > ( getImm ( ) ) ;


<s> assert ( BBPrevious && <STR_LIT> ) ; MachineBasicBlock * AfterNext = After -> getNextNode ( ) ; MachineBasicBlock * BBNext = BB -> getNextNode ( ) ; BB -> moveAfter ( After ) ; auto FixFallthrough = [ & ] ( MachineBasicBlock * From , MachineBasicBlock * To ) { LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> ) ; assert ( From -> isSuccessor ( To ) && <STR_LIT> ) ; MachineInstr & Terminator = * ( -- From -> terminators ( ) . end ( ) ) ; if ( ! Terminator . isUnconditionalBranch ( ) ) { MachineInstrBuilder MIB = BuildMI ( From , Terminator . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addMBB ( To ) ; MIB . addImm ( <STR_LIT> :: AL ) ; MIB . addReg ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> << * MIB . getInstr ( ) ) ;


<s> ob_fcode -= S390_BUILTIN_MAX ; for ( b_arg_chain = TYPE_ARG_TYPES ( TREE_TYPE ( ob_fndecl ) ) ; ! VOID_TYPE_P ( TREE_VALUE ( b_arg_chain ) ) ; b_arg_chain = TREE_CHAIN ( b_arg_chain ) ) ob_args_num ++ ; if ( ob_args_num != in_args_num ) { error_at ( loc , <STR_LIT> <STR_LIT> , ob_fndecl , ob_args_num , in_args_num ) ; return error_mark_node ; } for ( i = <NUM_LIT> ; i < in_args_num ; i ++ ) if ( ( * arglist ) [ i ] == error_mark_node ) return error_mark_node ; if ( desc_start_for_overloaded_builtin [ ob_fcode ] == S390_OVERLOADED_BUILTIN_VAR_MAX ) return s390_expand_overloaded_builtin ( loc , ob_fcode , arglist , NULL_TREE ) ; for ( bindex = desc_start_for_overloaded_builtin [ ob_fcode ] ; bindex <= desc_end_for_overloaded_builtin [ ob_fcode ] ; bindex = ( enum s390_overloaded_builtin_vars ) ( ( int ) bindex + <NUM_LIT> ) ) { int match_type ; enum s390_builtin_ov_type_index type_index = type_for_overloaded_builtin_var [ bindex ] ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , ( int ) bindex ) ; match_type = s390_fn_types_compatible ( type_index , arglist ) ; if ( match_type == INT_MAX ) continue ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , match_type == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , match_type ) ; if ( match_type < last_match_type ) { num_matches = <NUM_LIT> ; last_match_type = match_type ; last_match_fntype_index = type_index ; last_match_index = bindex ; } else if ( match_type == last_match_type ) num_matches ++ ; } if ( last_match_type == INT_MAX ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } else if ( num_matches > <NUM_LIT> ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } if ( ! TARGET_VXE && bflags_overloaded_builtin_var [ last_match_index ] & B_VXE ) { error_at ( loc , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; return error_mark_node ; } if ( bflags_overloaded_builtin_var [ last_match_index ] & B_DEP ) warning_at ( loc , <NUM_LIT> , <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( ob_fndecl ) ) ) ; if ( bt_for_overloaded_builtin_var [ last_match_index ] == S390_BUILTIN_MAX ) target_builtin_decl = ob_fndecl ;


<s> case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = ( BaseReg == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Offset += getFrameIndexInstrOffset ( MI , i ) ;

if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; FirstOp = <NUM_LIT> ; isZBranch = true ; break ; } unsigned NZCV = <STR_LIT> ( CmpBBTailCC ) ; const MCInstrDesc & MCID = TII -> get ( Opc ) ; MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; if ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . isReg ( ) ) MRI -> constrainRegClass ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) . getReg ( ) , TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * Head , CmpMI , CmpMI -> getDebugLoc ( ) , MCID ) . add ( CmpMI -> getOperand ( FirstOp ) ) ; if ( isZBranch ) MIB . addImm ( <NUM_LIT> ) ; else MIB . add ( CmpMI -> getOperand ( FirstOp + <NUM_LIT> ) ) ; MIB . addImm ( NZCV ) . addImm ( HeadCmpBBCC ) ; if ( isZBranch ) {

bool isNZ = CmpMI -> getOpcode ( ) == <STR_LIT> || CmpMI -> getOpcode ( ) == <STR_LIT> ;


<s> MCAssembler * getAssembler ( ) const { return Assembler ;


<s> static bool canGuaranteeTCO ( CallingConv :: ID CC ) { return ( CC == CallingConv :: Fast || CC == CallingConv :: GHC || CC == CallingConv :: X86_RegCall || CC == CallingConv :: HiPE || CC == CallingConv :: HHVM ) ;


<s> } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineIRBuilder MIB ( I ) ; auto UShl = MIB . buildInstr ( Opc , { DstReg } , { Src1Reg , Src2Reg } ) ; constrainSelectedInstRegOperands ( * UShl , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return true ;


<s> void Emitter < CodeEmitter > :: emitPseudoInstruction ( const MachineInstr & MI ) { unsigned Opcode = MI . getDesc ( ) . Opcode ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case TargetInstrInfo :: INLINEASM : { if ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) [ <NUM_LIT> ] ) { llvm_report_error ( <STR_LIT> ) ; } break ; } case TargetInstrInfo :: DBG_LABEL : case TargetInstrInfo :: EH_LABEL : MCE . emitLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case TargetInstrInfo :: IMPLICIT_DEF : case TargetInstrInfo :: DECLARE : case <STR_LIT> : break ; case <STR_LIT> :


<s> if ( TARGET_FDPIC ) bitmap_set_bit ( regs , FDPIC_REGNO ) ;


<s> for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( ! isSetCCr ( MI . getOpcode ( ) ) ) continue ; MachineInstr * ZExt = nullptr ; for ( auto & Use : MRI -> use_instructions ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) if ( Use . getOpcode ( ) == <STR_LIT> ) ZExt = & Use ; if ( ! ZExt ) continue ; MachineInstr * FlagsDefMI = findFlagsImpDef ( MI . getParent ( ) , MachineBasicBlock :: reverse_iterator ( & MI ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitCALL_NOLINK ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> SDValue TLSOffsetSym = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , PtrVT , GA -> getOffset ( ) , <NUM_LIT> ) ; MachineSDNode * TLSBase = CurDAG -> getMachineNode ( GlobalGetIns , DL , PtrVT , TLSBaseSym ) ; MachineSDNode * TLSOffset = CurDAG -> getMachineNode ( ConstIns , DL , PtrVT , TLSOffsetSym ) ; MachineSDNode * TLSAddress = CurDAG -> getMachineNode ( AddIns , DL , PtrVT , SDValue ( TLSBase , <NUM_LIT> ) , SDValue ( TLSOffset , <NUM_LIT> ) ) ; ReplaceNode ( Node , TLSAddress ) ; return ; } case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { case <STR_LIT> : { MachineSDNode * TLSSize = CurDAG -> getMachineNode ( GlobalGetIns , DL , PtrVT , CurDAG -> getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ) ; ReplaceNode ( Node , TLSSize ) ; return ; } case <STR_LIT> : { MachineSDNode * TLSAlign = CurDAG -> getMachineNode ( GlobalGetIns , DL , PtrVT , CurDAG -> getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ) ; ReplaceNode ( Node , TLSAlign ) ; return ; } } break ; } case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { case <STR_LIT> : { MachineSDNode * TLSBase = CurDAG -> getMachineNode ( GlobalGetIns , DL , PtrVT , <STR_LIT> , CurDAG -> getTargetExternalSymbol ( <STR_LIT> , PtrVT ) , Node -> getOperand ( <NUM_LIT> ) ) ; ReplaceNode ( Node , TLSBase ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; }


<s> fprintf ( f , <STR_LIT> ) ; asm_fprintf ( f , <STR_LIT> , STATIC_CHAIN_REGNUM , PC_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , PC_REGNUM , PC_REGNUM ) ; } else if ( TARGET_THUMB2 ) { fprintf ( f , <STR_LIT> ) ; asm_fprintf ( f , <STR_LIT> , STATIC_CHAIN_REGNUM , PC_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , PC_REGNUM , PC_REGNUM ) ; }


<s> DenseSet < const char * > Allowed ( { & AAAMDAttributes :: ID , & AAUniformWorkGroupSize :: ID , & AACallEdges :: ID } ) ; Attributor A ( Functions , InfoCache , CGUpdater , & Allowed ) ; for ( Function & F : M ) { if ( ! F . isIntrinsic ( ) ) { A . getOrCreateAAFor < AAAMDAttributes > ( IRPosition :: function ( F ) ) ;

A . getOrCreateAAFor < AAUniformWorkGroupSize > ( IRPosition :: function ( F ) ) ;


<s> if ( Lo ) { unsigned TmpReg = createResultReg ( RC ) ; EmitInst ( <STR_LIT> , TmpReg ) . addImm ( Hi ) ; EmitInst ( <STR_LIT> , ResultReg ) . addReg ( TmpReg ) . addImm ( Lo ) ; } else { EmitInst ( <STR_LIT> , ResultReg ) . addImm ( Hi ) ;


<s> SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; if ( Src0 . isUndef ( ) && Src1 . isUndef ( ) ) return DCI . DAG . getUNDEF ( N -> getValueType ( <NUM_LIT> ) ) ;


<s> return __builtin_aarch64_smax_nanpv2df ( a , b ) ;


<s> LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ;

ST = TM ? TM -> getSubtargetImpl ( F ) : nullptr ;


<s> int thumb_shiftable_const ( unsigned HOST_WIDE_INT val ) { unsigned HOST_WIDE_INT mask = <NUM_LIT> ; int i ; val = val & ( unsigned HOST_WIDE_INT ) <NUM_LIT> ; if ( val == <NUM_LIT> ) return <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ( val & ( mask << i ) ) == val ) return <NUM_LIT> ;


<s> static inline <STR_LIT> getMemExtendType ( unsigned Imm ) {

return getExtendType ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> <ISA_LIT>LowerAMXType ( Function & F ) : Func ( F ) , DL ( F . getParent ( ) -> getDataLayout ( ) ) {


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S ) : <ISA_LIT>TargetStreamer ( S ) {


<s> EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ;

SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> uint64_t Disp = Field & <NUM_LIT> ; assert ( Length < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( Disp ) ) ;


<s> dest = adjust_address ( dest , BLKmode , <NUM_LIT> ) ; set_mem_size ( dest , size ) ; s390_expand_cpymem ( dest , src_mem , GEN_INT ( size ) ) ; return true ; } else if ( register_operand ( src , word_mode ) ) { if ( bitsize <= <NUM_LIT> ) emit_move_insn ( gen_rtx_ZERO_EXTRACT ( word_mode , dest , op1 , const0_rtx ) , src ) ; else { int stcmh_width = bitsize - <NUM_LIT> ; int size = stcmh_width / BITS_PER_UNIT ; emit_move_insn ( adjust_address ( dest , SImode , size ) , gen_lowpart ( SImode , src ) ) ; set_mem_size ( dest , size ) ; emit_move_insn ( gen_rtx_ZERO_EXTRACT ( word_mode , dest , GEN_INT ( stcmh_width ) , const0_rtx ) , gen_rtx_LSHIFTRT ( word_mode , src , GEN_INT ( <NUM_LIT> ) ) ) ; } return true ; } } if ( ( bitpos % BITS_PER_UNIT ) == <NUM_LIT> && ( bitsize % BITS_PER_UNIT ) == <NUM_LIT> && ( bitpos & <NUM_LIT> ) == ( ( bitpos + bitsize - <NUM_LIT> ) & <NUM_LIT> ) && MEM_P ( src ) && ( mode == DImode || mode == SImode ) && mode != smode && register_operand ( dest , mode ) ) { if ( smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize ) { rtx low_dest = gen_lowpart ( smode , dest ) ; rtx low_src = gen_lowpart ( smode , src ) ; switch ( smode ) { case E_QImode : emit_insn ( gen_movstrictqi ( low_dest , low_src ) ) ; return true ; case E_HImode : emit_insn ( gen_movstricthi ( low_dest , low_src ) ) ; return true ; case E_SImode : emit_insn ( gen_movstrictsi ( low_dest , low_src ) ) ; return true ; default : break ; } } } if ( TARGET_Z10 && ( mode == DImode || mode == SImode ) ) { machine_mode mode_s = GET_MODE ( src ) ; if ( CONSTANT_P ( src ) ) { if ( src == const0_rtx && bitpos / <NUM_LIT> == ( bitpos + bitsize - <NUM_LIT> ) / <NUM_LIT> ) return false ; else src = force_reg ( mode , src ) ; } else if ( mode_s != mode ) { gcc_assert ( GET_MODE_BITSIZE ( mode_s ) >= bitsize ) ; src = force_reg ( mode_s , src ) ; src = gen_lowpart ( mode , src ) ; } op = gen_rtx_ZERO_EXTRACT ( mode , dest , op1 , op2 ) , op = gen_rtx_SET ( op , src ) ; if ( ! TARGET_ZEC12 ) { clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , CC_REGNUM ) ) ;

op = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , op , clobber ) ) ;


<s> static void generateEndPgm ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , const <ISA_LIT>InstrInfo * TII , bool IsPS ) { if ( IsPS ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> :: ET_NULL ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getTarget ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; LIs = LI ; DEBUG ( MF -> dump ( ) ; ) ; for ( MachineFunction :: const_iterator mbbItr = MF -> begin ( ) , mbbEnd = MF -> end ( ) ; mbbItr != mbbEnd ; ++ mbbItr ) { const MachineBasicBlock * MBB = & * mbbItr ; Chains . clear ( ) ; for ( MachineBasicBlock :: const_iterator miItr = MBB -> begin ( ) , miEnd = MBB -> end ( ) ; miItr != miEnd ; ++ miItr ) { const MachineInstr * MI = & * miItr ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> :


<s> if ( ! GlobalsEmitted ) { emitGlobals ( * MF -> getFunction ( ) -> getParent ( ) ) ; GlobalsEmitted = true ; } MRI = & MF -> getRegInfo ( ) ; F = MF -> getFunction ( ) ; emitLinkageDirective ( F , O ) ; if ( llvm :: isKernelFunction ( * F ) ) O << <STR_LIT> ; else { O << <STR_LIT> ;


<s> bool bid ( unsigned B ) { unsigned b = B & ~ isSold ; if ( b ) {

for ( unsigned i = <NUM_LIT> ; i < HEXAGON_PACKET_SIZE ; ++ i ) if ( b & ( <NUM_LIT> << i ) ) {


<s> { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; return emitAddSub ( OpcTable , Dst , LHS , RHS , MIRBuilder ) ;


<s> res = parseNamedBit ( Op . Name , Operands , Op . Type ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyOMod<ISA_LIT> ) { res = parseOModOperand ( Operands ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTySdwaDstSel || Op . Type == <ISA_LIT>Operand :: ImmTySdwaSrc0Sel || Op . Type == <ISA_LIT>Operand :: ImmTySdwaSrc1Sel ) { res = parseSDWASel ( Operands , Op . Name , Op . Type ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTySdwaDstUnused ) { res = parseSDWADstUnused ( Operands ) ; } else { res = parseIntWithPrefix ( Op . Name , Operands , Op . Type , Op . ConvertResult ) ; } if ( res != MatchOperand_NoMatch ) { return res ; }


<s> SmallVector < Instruction * , <NUM_LIT> > Users ; Instruction * InstTo = dyn_cast < Instruction > ( To ) ; for ( Use & U : From -> uses ( ) ) {

auto * User = cast < Instruction > ( U . getUser ( ) ) ;


<s> void <ISA_LIT>GOT :: applyGOT0 ( uint64_t pAddress ) { llvm :: cast < <ISA_LIT>GOTEntry > ( * ( m_SectionData -> getFragmentList ( ) . begin ( ) ) ) . setValue ( pAddress ) ;


<s> if ( ud2 != <NUM_LIT> ) emit_move_insn ( dest , gen_rtx_IOR ( DImode , dest , GEN_INT ( ud2 ) ) ) ; emit_move_insn ( dest , gen_rtx_ASHIFT ( DImode , dest , GEN_INT ( <NUM_LIT> ) ) ) ; if ( ud1 != <NUM_LIT> ) emit_move_insn ( dest , gen_rtx_IOR ( DImode , dest , GEN_INT ( ud1 ) ) ) ; } else { if ( ud4 & <NUM_LIT> ) emit_move_insn ( dest , GEN_INT ( ( ( ud4 << <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ) ) ; else emit_move_insn ( dest , GEN_INT ( ud4 << <NUM_LIT> ) ) ; if ( ud3 != <NUM_LIT> ) emit_move_insn ( dest , gen_rtx_IOR ( DImode , dest , GEN_INT ( ud3 ) ) ) ; emit_move_insn ( dest , gen_rtx_ASHIFT ( DImode , dest , GEN_INT ( <NUM_LIT> ) ) ) ; if ( ud2 != <NUM_LIT> ) emit_move_insn ( dest , gen_rtx_IOR ( DImode , dest , GEN_INT ( ud2 << <NUM_LIT> ) ) ) ; if ( ud1 != <NUM_LIT> ) emit_move_insn ( dest , gen_rtx_IOR ( DImode , dest , GEN_INT ( ud1 ) ) ) ;


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( REAL_VALUES_EQUAL ( * r , values_fp [ i ] ) ) return strings_fp [ i ] ; gcc_unreachable ( ) ;


<s> if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , * I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) ) { * PredCost = <NUM_LIT> ; } if ( ! ItinData ) return MI . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Class = MCID . getSchedClass ( ) ; if ( ! ItinData -> isEmpty ( ) && ItinData -> getNumMicroOps ( Class ) < <NUM_LIT> ) return getNumMicroOps ( ItinData , MI ) ; unsigned Latency = ItinData -> getStageLatency ( Class ) ; unsigned DefAlign = MI . hasOneMemOperand ( ) ? ( * MI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Adj = adjustDefLatency ( Subtarget , MI , MCID , DefAlign ) ; if ( Adj >= <NUM_LIT> || ( int ) Latency > - Adj ) {


<s> bool <ISA_LIT>InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { unsigned NumOperands = MI . getDesc ( ) . getNumOperands ( ) ; if ( NumOperands < <NUM_LIT> ) return false ; const MachineOperand & PredMO = MI . getOperand ( NumOperands - <NUM_LIT> ) ; if ( ! PredMO . isReg ( ) ) return false ; return PredMO . getReg ( ) == <STR_LIT> ;


<s> SchedCandidate ( ) : SU ( NULL ) , SCost ( <NUM_LIT> ) {


<s> return UNSPEC_VSEL4SI ; break ; case V4SFmode : return UNSPEC_VSEL4SF ; break ; case V8HImode : return UNSPEC_VSEL8HI ; break ; case V16QImode : return UNSPEC_VSEL16QI ; break ;


<s> void EmitInstruction ( uint32_t Val , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { EmitByte ( Val & <NUM_LIT> , OS ) ; Val >>= <NUM_LIT> ;


<s> for ( regclass_iterator I = regclass_begin ( ) , E = regclass_end ( ) ; I != E ; ++ I ) { const TargetRegisterClass * RC = * I ; if ( ( VT == <STR_LIT> || RC -> hasType ( VT ) ) && RC -> contains ( reg ) && ( ! BestRC || RC -> getNumRegs ( ) < BestRC -> getNumRegs ( ) ) ) BestRC = RC ; } assert ( BestRC && <STR_LIT> ) ; return BestRC ;


<s> MVT VT = V . getSimpleValueType ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > NewVecC ; SDLoc DL ( V ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { auto * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getSimpleValueType ( <NUM_LIT> ) != EltVT ) return SDValue ( ) ;

const APInt & EltC = Elt -> getAPIntValue ( ) ;


<s> if ( N . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) . bitsLE ( <STR_LIT> ) ) { Val = N ; return true ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr ; unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long ) FIOffset + Imm ) ) && <STR_LIT> ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { uint64_t Offset = FIOffset + ( uint64_t ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getOffset ( ) ;

MI . getOperand ( FIOperandNum + <NUM_LIT> ) . setOffset ( Offset ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; } else { return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > ToErase ; for ( auto * MI : C . instructions ( ) ) if ( Converters . find ( { Domain , MI -> getOpcode ( ) } ) -> second -> convertInstr ( MI , TII , MRI ) ) ToErase . push_back ( MI ) ; for ( Register Reg : C . edges ( ) ) {

MRI -> setRegClass ( Reg , getDstRC ( MRI -> getRegClass ( Reg ) , Domain ) ) ;


<s> static const char * dlerror ( void ) { return _ ( <STR_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool Trad ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , Trad ) , DataLayout ( <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) {


<s> if ( VT == <STR_LIT> ) { assert ( Mask . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Index . getValueType ( ) == <STR_LIT> && Subtarget . hasVLX ( ) ) { Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Src , Mask , BasePtr , Index , Scale } ; SDValue NewScatter = DAG . getTargetMemSDNode < <ISA_LIT>MaskedScatterSDNode > ( VTs , Ops , dl , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ; return SDValue ( NewScatter . getNode ( ) , <NUM_LIT> ) ; } return SDValue ( ) ; } if ( VT == <STR_LIT> ) { assert ( Mask . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ; if ( Index . getValueType ( ) == <STR_LIT> && Subtarget . hasVLX ( ) ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Src , Mask , BasePtr , Index , Scale } ; SDValue NewScatter = DAG . getTargetMemSDNode < <ISA_LIT>MaskedScatterSDNode > ( VTs , Ops , dl , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ; return SDValue ( NewScatter . getNode ( ) , <NUM_LIT> ) ; } EVT NewIndexVT = EVT :: getVectorVT ( * DAG . getContext ( ) , Index . getValueType ( ) . getVectorElementType ( ) , <NUM_LIT> ) ; Index = DAG . getNode ( <STR_LIT> , dl , NewIndexVT , Index , DAG . getUNDEF ( Index . getValueType ( ) ) ) ;

Mask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> assert ( Last . getParent ( ) == First . getParent ( ) && <STR_LIT> ) ;

assert ( InstrPos . find ( & First ) != InstrPos . end ( ) && InstrPos . find ( & Last ) != InstrPos . end ( ) && <STR_LIT> ) ;


<s> return ( __m128d ) __builtin_ia32_cmpunordsd ( ( __v2df ) __A , ( __v2df ) __B ) ;


<s> vector_type_index function_resolver :: infer_vector_base_type ( unsigned int argno ) { type_suffix_index type = infer_vector_type ( argno ) ; if ( type == NUM_TYPE_SUFFIXES ) return NUM_VECTOR_TYPES ; if ( type == TYPE_SUFFIX_u32 || type == TYPE_SUFFIX_u64 ) return type_suffixes [ type ] . vector_type ; error_at ( location , <STR_LIT> <STR_LIT> , get_argument_type ( argno ) , argno + <NUM_LIT> , fndecl , <STR_LIT> , <STR_LIT> ) ;


<s> LDSSize = YamlMFI . LDSSize ; GDSSize = YamlMFI . GDSSize ; DynLDSAlign = YamlMFI . DynLDSAlign ; HighBitsOf32BitAddress = YamlMFI . HighBitsOf32BitAddress ; Occupancy = YamlMFI . Occupancy ; IsEntryFunction = YamlMFI . IsEntryFunction ; NoSignedZerosFPMath = YamlMFI . NoSignedZerosFPMath ; MemoryBound = YamlMFI . MemoryBound ; WaveLimiter = YamlMFI . WaveLimiter ; HasSpilledSGPRs = YamlMFI . HasSpilledSGPRs ; HasSpilledVGPRs = YamlMFI . HasSpilledVGPRs ; BytesInStackArgArea = YamlMFI . BytesInStackArgArea ; ReturnsVoid = YamlMFI . ReturnsVoid ; if ( YamlMFI . ScavengeFI ) { auto FIOrErr = YamlMFI . ScavengeFI -> getFI ( MF . getFrameInfo ( ) ) ; if ( ! FIOrErr ) { const MemoryBuffer & Buffer = * PFS . SM -> getMemoryBuffer ( PFS . SM -> getMainFileID ( ) ) ; Error = SMDiagnostic ( * PFS . SM , SMLoc ( ) , Buffer . getBufferIdentifier ( ) , <NUM_LIT> , <NUM_LIT> , SourceMgr :: DK_Error , toString ( FIOrErr . takeError ( ) ) , <STR_LIT> , None , None ) ; SourceRange = YamlMFI . ScavengeFI -> SourceRange ; return true ; } ScavengeFI = * FIOrErr ;


<s> return HII -> getCondOpcode ( Opc , ! IfTrue ) ;


<s> static void add_sve_type_attribute ( tree type , unsigned int num_zr , unsigned int num_pr , const char * mangled_name , const char * acle_name ) { tree mangled_name_tree = ( mangled_name ? get_identifier ( mangled_name ) : NULL_TREE ) ;

tree value = tree_cons ( NULL_TREE , get_identifier ( acle_name ) , NULL_TREE ) ;


<s> break ; case ENCODING_IW : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case ENCODING_ID : if ( immediate & <NUM_LIT> ) immediate |= ~ ( <NUM_LIT> ) ; break ; case ENCODING_IO : break ; } } switch ( type ) { case TYPE_XMM : mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_YMM : mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; case TYPE_ZMM : mcInst . addOperand ( MCOperand :: createReg ( <STR_LIT> + ( immediate >> <NUM_LIT> ) ) ) ; return ; default : break ; } if ( ! Dis -> tryAddingSymbolicOperand ( mcInst , immediate + pcrel , insn . startLocation , isBranch , insn . immediateOffset , insn . immediateSize , insn . length ) ) mcInst . addOperand ( MCOperand :: createImm ( immediate ) ) ; if ( type == TYPE_MOFFS ) {