<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_HI22 || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LE_HIX22 ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) && <STR_LIT> ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_ADD || TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_ADD ) && <STR_LIT> ) ;

else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( TF == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_LD && <STR_LIT> ) ;


<s> I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; I |= ( Exp & <NUM_LIT> ) << <NUM_LIT> ;


<s> MachineBasicBlock & MBB = * BI ; bool HaveSkipBlock = false ; if ( ! ExecBranchStack . empty ( ) && ExecBranchStack . back ( ) == & MBB ) { ExecBranchStack . pop_back ( ) ; } if ( HaveKill && ExecBranchStack . empty ( ) ) { HaveKill = false ; } MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : ExecBranchStack . push_back ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; break ; case <STR_LIT> : ExecBranchStack . push_back ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case <STR_LIT> : if ( MBB . isLayoutSuccessor ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { MI . eraseFromParent ( ) ; } else if ( HaveSkipBlock ) { MI . eraseFromParent ( ) ; }


<s> bool enableNamedBit ( const MachineBasicBlock :: iterator & MI ) { int BitIdx = <STR_LIT> ( MI -> getOpcode ( ) , BitName ) ; if ( BitIdx == - <NUM_LIT> ) return false ;

MachineOperand & Bit = MI -> getOperand ( BitIdx ) ;


<s> if ( ST -> hasNEON ( ) ) return TypeSize :: getFixed ( <NUM_LIT> ) ; if ( ST -> hasMVEIntegerOps ( ) ) return TypeSize :: getFixed ( <NUM_LIT> ) ;


<s> <ISA_LIT>Operand :: Ptr <ISA_LIT>AsmParser :: defaultSMEMOffset ( ) const {

return <ISA_LIT>Operand :: CreateImm ( this , <NUM_LIT> , SMLoc ( ) , <ISA_LIT>Operand :: ImmTyOffset ) ;


<s> bool Modified = false ; BlockIt MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { BlockIt NMBBI = std :: next ( MBBI ) ; Modified |= runOnInstruction ( MBB , MBBI ) ; MBBI = NMBBI ;


<s> const char * p ; symbol_type = mips_classify_symbolic_expression ( op , context ) ; gcc_assert ( relocs [ symbol_type ] ) ; fputs ( relocs [ symbol_type ] , file ) ; output_addr_const ( file , mips_strip_unspec_address ( op ) ) ;

for ( p = relocs [ symbol_type ] ; * p != <NUM_LIT> ; p ++ ) if ( * p == '(' ) fputc ( ')' , file ) ;


<s> WeakRefDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;

if ( T . getOS ( ) == Triple :: OpenBSD && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = <NUM_LIT> ;


<s> if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( MayFoldLoad ( V ) ) return true ;


<s> OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) ; <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; const unsigned EntryByteSize = Subtarget -> is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ; const unsigned TOCEntriesByteSize = TOC . size ( ) * EntryByteSize ; if ( TOCEntriesByteSize > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first ) ) ;

OutStreamer -> SwitchSection ( TCEntry ) ;


<s> if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == ST -> get<ISA_LIT>AS ( ) . PRIVATE_ADDRESS ; if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) return <STR_LIT> ( Intrinsic -> getIntrinsicID ( ) ) ;

if ( isa < CallInst > ( V ) || isa < InvokeInst > ( V ) ) return true ;


<s> if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ;


<s> void addConditionCodeOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> ClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeCopy ( & MBB ) ;


<s> bool SelectAddrIdxOffs ( SDValue N , SDValue & Out ) const { if ( isa < ConstantSDNode > ( N ) || N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) return false ; Out = N ;


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const { SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


<s> SDLoc dl ( Op ) ; const TargetRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; SDValue Stack = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RegInfo -> getFrameRegister ( MF ) , <STR_LIT> ) ; SDValue FrameToArgs = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Stack = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Stack , FrameToArgs ) ; Stack = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Stack , Offset ) ; unsigned StackReg = <STR_LIT> ; unsigned HandlerReg = <STR_LIT> ; SDValue OutChains [ ] = { DAG . getCopyToReg ( Chain , dl , StackReg , Stack ) , DAG . getCopyToReg ( Chain , dl , HandlerReg , Handler ) } ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( StackReg , <STR_LIT> ) , DAG . getRegister ( HandlerReg , <STR_LIT> ) ) ;


<s> void <ISA_LIT>AsmPrinter :: printFCCOperand ( const MachineInstr * MI , int opNum , const char * Modifier ) {

const MachineOperand & MO = MI -> getOperand ( opNum ) ;


<s> return cum -> fntype == NULL_TREE || stdarg_p ( cum -> fntype ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) {


<s> unsigned Imm25 = slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( S ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I1 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ; if ( I2 ) Imm25 |= <NUM_LIT> << <NUM_LIT> ;

return SignExtend32 < <NUM_LIT> > ( Imm25 ) ;


<s> assert ( Value == <NUM_LIT> && <STR_LIT> ) ;


<s> TargetIRAnalysis <ISA_LIT>TargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } ) ;


<s> void addMemOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBase ( ) ) ) ;


<s> static SDValue LowerVectorIntUnary ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned SizeInBits = VT . getSizeInBits ( ) ; MVT EltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; assert ( EltVT == Src . getSimpleValueType ( ) . getVectorElementType ( ) && <STR_LIT> ) ;


<s> bool isGP64bit ( ) const { return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> if ( MBB . back ( ) . getOpcode ( ) == AMDGPU :: S_ENDPGM ) { MBB . back ( ) . addOperand ( * MF , MachineOperand :: CreateReg ( VGPR , false , true ) ) ; return VGPR ;


<s> return new <ISA_LIT>StackTagging ( ) ;


<s> int64_t ImmVal = ValAndVReg -> Value . getSExtValue ( ) ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal ) return None ; unsigned SignExtend = <NUM_LIT> ; if ( WantsExt ) { if ( ! LookedThroughZExt ) { MachineInstr * ExtInst = getDefIgnoringCopies ( OffsetReg , MRI ) ; auto Ext = getExtendTypeForInst ( * ExtInst , MRI , true ) ; if ( Ext == <STR_LIT> ) return None ; SignExtend = isSignExtendShiftType ( Ext ) ? <NUM_LIT> : <NUM_LIT> ; if ( SignExtend && Ext != <STR_LIT> ) return None ; OffsetReg = ExtInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineIRBuilder MIB ( * MRI . getVRegDef ( Root . getReg ( ) ) ) ;

OffsetReg = moveScalarRegClass ( OffsetReg , <STR_LIT> , MIB ) ;


<s> MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = FunctionAlignment . getValue ( ) ? std :: log2 ( FunctionAlignment . getValue ( ) ) : <NUM_LIT> ; PrefLoopAlignment = LoopAlignment . getValue ( ) ? std :: log2 ( LoopAlignment . getValue ( ) ) : <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 :


<s> if ( IsVarArg ) { llvm_unreachable ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { const unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgIn = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; InVals . push_back ( ArgIn ) ;


<s> vtrnq_u8 ( uint8x16_t a , uint8x16_t b ) { return ( uint8x16x2_t ) { vtrn1q_u8 ( a , b ) , vtrn2q_u8 ( a , b ) } ;


<s> const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; auto ShlMemOp = <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , Basereg , <NUM_LIT> , <NUM_LIT> , SMLoc { } , SMLoc { } , <NUM_LIT> ) ; ShlInst . setOpcode ( <STR_LIT> ) ; ShlMemOp -> addMemOperands ( ShlInst , <NUM_LIT> ) ; ShlInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; FenceInst . setOpcode ( <STR_LIT> ) ; Out . emitInstruction ( ShlInst , getSTI ( ) ) ; Out . emitInstruction ( FenceInst , getSTI ( ) ) ; return ; } case <STR_LIT> : case <STR_LIT> :


<s> BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; getAddNoCarry ( Entry , Insert , DL , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; }

BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( <NUM_LIT> ) . addReg ( TIDReg ) ;


<s> case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MCSymbol * & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = AsmPrinter . GetGlobalValueSymbol ( MO . getGlobal ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MCSymbol * & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = AsmPrinter . GetGlobalValueSymbol ( MO . getGlobal ( ) ) ; } else { Name . erase ( Name . end ( ) - <NUM_LIT> , Name . end ( ) ) ; StubSym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; } return Sym ; } }

return Ctx . GetOrCreateSymbol ( Name . str ( ) ) ;


<s> bool isPIC ( ) const { return IsPIC ;


<s> if ( ST -> hasAVX ( ) ) return <NUM_LIT> ;


<s> SDValue Value0 , Value1 ; std :: tie ( Value0 , Value1 ) = splitVector ( StoredVal , DAG , DL ) ; unsigned HalfAlign = ( StoredVal . getValueType ( ) . is256BitVector ( ) ? <NUM_LIT> : <NUM_LIT> ) ; SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , HalfAlign , DL ) ; unsigned Alignment = Store -> getAlignment ( ) ;

SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Alignment , Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> CONSTEXPR svqshl_impl ( ) : unspec_based_function ( UNSPEC_SQSHL , UNSPEC_UQSHL , - <NUM_LIT> ) {


<s> if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG ) { rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( XEXP ( x , <NUM_LIT> ) , temp ) ; if ( val != temp ) emit_move_insn ( temp , val ) ; x = gen_rtx_PLUS ( Pmode , XEXP ( x , <NUM_LIT> ) , temp ) ; } else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG ) { rtx temp = gen_reg_rtx ( Pmode ) ; rtx val = force_operand ( XEXP ( x , <NUM_LIT> ) , temp ) ; if ( val != temp ) emit_move_insn ( temp , val ) ; x = gen_rtx_PLUS ( Pmode , temp , XEXP ( x , <NUM_LIT> ) ) ; } } if ( constant_term != const0_rtx ) x = gen_rtx_PLUS ( Pmode , x , constant_term ) ; return x ;


<s> default : assert ( CI . InstClass == BUFFER_LOAD || CI . InstClass == BUFFER_STORE ) ; return <STR_LIT> ( <STR_LIT> ( CI . I -> getOpcode ( ) ) , Width ) ; case UNKNOWN : llvm_unreachable ( <STR_LIT> ) ; case S_BUFFER_LOAD_IMM : switch ( Width ) { default : return <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> vdup_n_u64 ( uint64_t __a ) { return ( uint64x1_t ) { __a } ;


<s> scope_counter ( int & counter ) : m_counter ( counter ) { ++ m_counter ;


<s> unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Alignment . value ( ) , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( ( unsigned ) Alignment . value ( ) , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , Alignment ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue Chain2 = DAG . getStore ( Chain , DL , Byte , Dst2 , DstPtrInfo . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } assert ( Bytes >= <NUM_LIT> && <STR_LIT> ) ; auto * CByte = dyn_cast < ConstantSDNode > ( Byte ) ;

if ( CByte && CByte -> getZExtValue ( ) == <NUM_LIT> ) return emitMemMem ( DAG , DL , <STR_LIT> , <STR_LIT> , Chain , Dst , Dst , Bytes ) ;


<s> case <STR_LIT> : return instCombineSVEDup ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVECmpNE ( IC , II ) ; case <STR_LIT> : return instCombineRDFFR ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVELast ( IC , II ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEPTest ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVEVectorMul ( IC , II ) ; case <STR_LIT> : return instCombineSVETBL ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEUnpack ( IC , II ) ; }


<s> Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( <NUM_LIT> ) ; SDValue Glue = End . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( End ) ; Ops . push_back ( DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ;


<s> if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , VT . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ;

if ( Src . isUndef ( ) || <STR_LIT> ( VMask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ;


<s> SDValue CmpLHS = Cmp . getOperand ( <NUM_LIT> ) ; SDValue CmpRHS = Cmp . getOperand ( <NUM_LIT> ) ; if ( ! CmpLHS . hasOneUse ( ) ) return SDValue ( ) ; unsigned Opc = CmpLHS . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return SDValue ( ) ; SDValue OpRHS = CmpLHS . getOperand ( <NUM_LIT> ) ; auto * OpRHSC = dyn_cast < ConstantSDNode > ( OpRHS ) ; if ( ! OpRHSC ) return SDValue ( ) ; APInt Addend = OpRHSC -> getAPIntValue ( ) ; if ( Opc == <STR_LIT> ) Addend = - Addend ; auto * CmpRHSC = dyn_cast < ConstantSDNode > ( CmpRHS ) ; if ( ! CmpRHSC ) return SDValue ( ) ; APInt Comparison = CmpRHSC -> getAPIntValue ( ) ; if ( Comparison == - Addend ) { auto * AN = cast < AtomicSDNode > ( CmpLHS . getNode ( ) ) ; auto AtomicSub = DAG . getAtomic ( <STR_LIT> , SDLoc ( CmpLHS ) , CmpLHS . getValueType ( ) , CmpLHS . getOperand ( <NUM_LIT> ) , CmpLHS . getOperand ( <NUM_LIT> ) , DAG . getConstant ( - Addend , SDLoc ( CmpRHS ) , CmpRHS . getValueType ( ) ) , AN -> getMemOperand ( ) ) ; auto LockOp = lowerAtomicArithWithLOCK ( AtomicSub , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( CmpLHS . getValue ( <NUM_LIT> ) , DAG . getUNDEF ( CmpLHS . getValueType ( ) ) ) ; DAG . ReplaceAllUsesOfValueWith ( CmpLHS . getValue ( <NUM_LIT> ) , LockOp . getValue ( <NUM_LIT> ) ) ; return LockOp ; } if ( ! Comparison . isNullValue ( ) ) return SDValue ( ) ; if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC = <STR_LIT> ; else if ( CC == <STR_LIT> && Addend == <NUM_LIT> ) CC = <STR_LIT> ;

else if ( CC == <STR_LIT> && Addend == - <NUM_LIT> ) CC = <STR_LIT> ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; for ( MachineInstr & HiLUI : MBB ) { MachineInstr * LoADDI = nullptr ; if ( ! detectLuiAddiGlobal ( HiLUI , LoADDI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * LoADDI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) << <STR_LIT> ) ; MadeChange |= detectAndFoldOffset ( HiLUI , * LoADDI ) ; }


<s> SDValue OneVec = Node -> getOperand ( <NUM_LIT> ) ; APInt SplatVal ; if ( ! <STR_LIT> ( OneVec , SplatVal ) || ! SplatVal . isOneValue ( ) ) return false ; SDLoc DL ( Node ) ; SDValue AllOnesVec ; APInt Ones = APInt :: getAllOnesValue ( <NUM_LIT> ) ; assert ( VT . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; unsigned NumElts = VT . getSizeInBits ( ) / <NUM_LIT> ; assert ( NumElts > <NUM_LIT> && <STR_LIT> ) ; AllOnesVec = CurDAG -> getConstant ( Ones , DL , <STR_LIT> ( <STR_LIT> , NumElts ) ) ;

insertDAGNode ( * CurDAG , X , AllOnesVec ) ;


<s> GCNRPTracker ( const LiveIntervals & LIS_ ) : LIS ( LIS_ ) {


<s> explicit <ISA_LIT>AsmPrinter ( raw_ostream & o , TargetMachine & tm , const TargetAsmInfo * T , CodeGenOpt :: Level OL , bool V ) : AsmPrinter ( o , tm , T , OL , V ) {


<s> if ( TOCEntry == <NUM_LIT> ) TOCEntry = OutContext . GetOrCreateSymbol ( StringRef ( MAI -> getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( LabelID ++ ) ) ; O << * TOCEntry << <STR_LIT> ;


<s> return <ISA_LIT>Lowering -> SelectAddressRegImm ( N , Disp , Base , * CurDAG , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; assert ( ( Subtarget -> isTargetLinux ( ) || Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetNaCl ( ) ) && <STR_LIT> ) ; assert ( Op . getNode ( ) -> getNumOperands ( ) == <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> void EndCOFFSymbolDef ( ) override {


<s> Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; Vec = Concat128BitVectors ( Vec , Vec , <STR_LIT> , <NUM_LIT> , DAG , dl ) ; } } else if ( VT . is128BitVector ( ) ) { Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } else llvm_unreachable ( <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Vec ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> for ( i = <NUM_LIT> ; i < num_elements ; i ++ ) { bool invert = opts [ i ] . invert ; const char * name = opts [ i ] . name ; const char * no_str = <STR_LIT> ; HOST_WIDE_INT mask = opts [ i ] . mask ; size_t len = comma_len + prefix_len + strlen ( name ) ; if ( ! invert ) { if ( ( flags & mask ) == <NUM_LIT> ) { no_str = <STR_LIT> ; len += strlen ( <STR_LIT> ) ; } flags &= ~ mask ;


<s> static machine_mode mips_dwarf_frame_reg_mode ( int regno ) { machine_mode mode = default_dwarf_frame_reg_mode ( regno ) ; if ( FP_REG_P ( regno ) && mips_abi == ABI_32 && TARGET_FLOAT64 ) mode = SImode ;


<s> assert ( ChunkIdx < <NUM_LIT> && <STR_LIT> ) ;

return ( Imm >> ( ChunkIdx * <NUM_LIT> ) ) & <NUM_LIT> ;


<s> case RISCV_BUILTIN_GENERAL : if ( subcode >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ; return riscv_builtin_decls [ subcode ] ; case RISCV_BUILTIN_VECTOR :

return <STR_LIT> ( subcode , initialize_p ) ;


<s> int m32c_extra_memory_constraint ( char c , const char * str ATTRIBUTE_UNUSED ) { return c == 'S' ;


<s> <ISA_LIT>MemoryLegalizer ( ) : MachineFunctionPass ( ID ) {


<s> unsigned BasePtr ; unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; bool IsWinEH = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; int Offset ; if ( IsWinEH ) Offset = TFI -> getFrameIndexOffsetFromSP ( MF , FrameIndex ) ; else Offset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; FI . ChangeToImmediate ( Offset ) ; return ; } if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long ) FIOffset + Imm ) ) && <STR_LIT> ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { uint64_t Offset = FIOffset + ( uint64_t ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getOffset ( ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . setOffset ( Offset ) ;


<s> if ( ! QII -> mayBeNewStore ( MI ) ) return false ; if ( GetStoreValueOperand ( MI ) . isReg ( ) && GetStoreValueOperand ( MI ) . getReg ( ) != DepReg ) return false ; const <ISA_LIT>RegisterInfo * QRI = ( const <ISA_LIT>RegisterInfo * ) TM . getRegisterInfo ( ) ; const MCInstrDesc & MCID = PacketMI -> getDesc ( ) ; const TargetRegisterClass * PacketRC = QII -> getRegClass ( MCID , <NUM_LIT> , QRI , MF ) ; for ( std :: vector < MachineInstr * > :: iterator VI = CurrentPacketMIs . begin ( ) , VE = CurrentPacketMIs . end ( ) ; ( VI != VE ) ; ++ VI ) { SUnit * PacketSU = MIToSUnit [ * VI ] ; if ( PacketSU -> getInstr ( ) -> getDesc ( ) . mayStore ( ) || PacketSU -> getInstr ( ) -> getOpcode ( ) == <STR_LIT> || PacketSU -> getInstr ( ) -> getOpcode ( ) == <STR_LIT> ) return false ; } if ( PacketRC == & <STR_LIT> ) { return false ; } if ( QII -> isPostIncrement ( MI ) && MI -> getDesc ( ) . mayStore ( ) && GetPostIncrementOperand ( MI , QII ) . getReg ( ) == DepReg ) { return false ; } if ( QII -> isPostIncrement ( PacketMI ) && PacketMI -> getDesc ( ) . mayLoad ( ) && GetPostIncrementOperand ( PacketMI , QII ) . getReg ( ) == DepReg ) { return false ; } if ( QII -> isPredicated ( PacketMI ) ) { if ( ! QII -> isPredicated ( MI ) ) return false ; unsigned predRegNumSrc = <NUM_LIT> ; unsigned predRegNumDst = <NUM_LIT> ; const TargetRegisterClass * predRegClass = NULL ; for ( unsigned opNum = <NUM_LIT> ; opNum < PacketMI -> getNumOperands ( ) ; opNum ++ ) { if ( PacketMI -> getOperand ( opNum ) . isReg ( ) ) predRegNumSrc = PacketMI -> getOperand ( opNum ) . getReg ( ) ; predRegClass = QRI -> getMinimalPhysRegClass ( predRegNumSrc ) ; if ( predRegClass == & <STR_LIT> ) { break ; } } assert ( ( predRegClass == & <STR_LIT> ) && ( <STR_LIT> ) ) ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) {

if ( MI -> getOperand ( opNum ) . isReg ( ) ) predRegNumDst = MI -> getOperand ( opNum ) . getReg ( ) ;


<s> SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , EltVT ) ; SDValue AllOnes = DAG . getAllOnesConstant ( DL , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > VMaskOps ( Mask . size ( ) , Zero ) ; SDValue V ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) {


<s> Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; }


<s> bool <ISA_LIT>AsmParser :: missingFeature ( llvm :: SMLoc const & Loc , uint64_t const & ErrorInfo ) {


<s> for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ;

if ( ! usesRegClass ( MO , & <STR_LIT> ) && ! usesRegClass ( MO , & <STR_LIT> ) ) continue ;


<s> const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = MI -> mayStore ( ) ; unsigned Opc = MI -> getOpcode ( ) ; int LoadStoreOp = IsStore ? getOffsetMUBUFStore ( Opc ) : getOffsetMUBUFLoad ( Opc ) ; if ( LoadStoreOp == - <NUM_LIT> ) return false ; const MachineOperand * Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ; if ( spillVGPRtoAGPR ( ST , * MBB , MI , Index , <NUM_LIT> , Reg -> getReg ( ) , false ) . getInstr ( ) ) return true ; MachineInstrBuilder NewMI = BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . add ( * Reg ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; const MachineOperand * VDataIn = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata_in ) ;

if ( VDataIn ) NewMI . add ( * VDataIn ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveOptionNoPIC ( ) { OS << <STR_LIT> ;


<s> MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ;

MIB . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isCheapAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { if ( SrcAS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) return true ;

return isNoopAddrSpaceCast ( SrcAS , DestAS ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx ) : MCII ( mcii ) , STI ( sti ) , Ctx ( ctx ) {


<s> if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , DestReg , SrcReg , NumBytes , Pred , PredReg , TII , MIFlags ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , DestReg , SrcReg , NumBytes , Pred , PredReg , TII , MIFlags ) ;


<s> case SImode : return TARGET_AVX512F ? V16SImode : ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) ? V8SImode : V4SImode ; case DImode : return TARGET_AVX512F ? V8DImode : ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) ? V4DImode : V2DImode ; case SFmode : if ( TARGET_AVX512F ) return V16SFmode ; else if ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) return V8SFmode ; else return V4SFmode ; case DFmode : if ( TARGET_AVX512F ) return V8DFmode ; else if ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) return V4DFmode ;

else if ( TARGET_SSE2 ) return V2DFmode ;


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> fprintf ( stream , <STR_LIT> , reg_names [ MMIX_STATIC_CHAIN_REGNUM ] ) ; fprintf ( stream , <STR_LIT> ) ; fprintf ( stream , <STR_LIT> ) ; fprintf ( stream , <STR_LIT> ) ; fprintf ( stream , <STR_LIT> ) ;


<s> <ISA_LIT>JITInfo * getJITInfo ( ) override { return & JITInfo ;


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ;

SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , getPointerTy ( DL ) , Offset ) ;


<s> void emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const override {


<s> PM . add ( createBlackfinISelDag ( * this , OptLevel ) ) ;


<s> emitFrameDirective ( ) ; if ( OutStreamer . hasRawTextSupport ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask ( OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ;


<s> if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCOFF ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; }

if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ;


<s> void WinEHStatePass :: unlinkExceptionRegistration ( IRBuilder < > & Builder ) { if ( auto * GEP = dyn_cast < GetElementPtrInst > ( Link ) ) { GEP = cast < GetElementPtrInst > ( GEP -> clone ( ) ) ; Builder . Insert ( GEP ) ; Link = GEP ; } Type * LinkTy = getEHLinkRegistrationType ( ) ; Value * Next = Builder . CreateLoad ( LinkTy -> getPointerTo ( ) , Builder . CreateStructGEP ( LinkTy , Link , <NUM_LIT> ) ) ; Constant * FSZero = Constant :: getNullValue ( LinkTy -> getPointerTo ( ) -> getPointerTo ( <NUM_LIT> ) ) ; Builder . CreateStore ( Next , FSZero ) ;


<s> AU . addPreservedID ( MachineLoopInfoID ) ;

AU . addPreservedID ( MachineDominatorsID ) ;


<s> unsigned CPEEnd = CPEOffset + Size ; if ( CPEEnd > NextBlockOffset ) { Growth = CPEEnd - NextBlockOffset ; Growth += OffsetToAlignment ( CPEEnd , <NUM_LIT> << NextBlockAlignment ) ; if ( CPEOffset < UserOffset ) UserOffset += Growth + UnknownPadding ( MF -> getAlignment ( ) , CPELogAlign ) ; } else Growth = <NUM_LIT> ; return isOffsetInRange ( UserOffset , CPEOffset , U ) ;


<s> const AsmToken & lexedToken = lexDefinite ( ) ; switch ( lexedToken . getKind ( ) ) { default : return AsmToken ( lexedToken ) ; case AsmToken :: Error : SetError ( Lexer -> getErrLoc ( ) , Lexer -> getErr ( ) ) ; return AsmToken ( lexedToken ) ; case AsmToken :: Identifier : { unsigned regID = MatchRegisterName ( lexedToken . getString ( ) . lower ( ) ) ; if ( regID ) { return AsmToken ( AsmToken :: Register , lexedToken . getString ( ) , static_cast < int64_t > ( regID ) ) ; } else {


<s> ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ;

SDValue UnpckNode = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> long long prev_pow10 ; long long next_pow10 ; while ( ( ( j * <NUM_LIT> ) < abs_multiplier ) && ( j < ( j * <NUM_LIT> ) ) ) j = j * <NUM_LIT> ; prev_pow10 = j ; next_pow10 = j * <NUM_LIT> ; if ( ( abs_multiplier - prev_pow10 <= <NUM_LIT> ) || ( next_pow10 - abs_multiplier <= <NUM_LIT> ) ) return true ; } if ( num_ops <= <NUM_LIT> ) return true ; if ( __builtin_popcount ( multiplier ) <= <NUM_LIT> || __builtin_popcount ( multiplier ) >= <NUM_LIT> ) return true ;

if ( ( find_mult_constants_used ( multiplier ) ) ) return true ;


<s> static unsigned char ix86_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( MAYBE_INTEGER_CLASS_P ( rclass ) ) { if ( mode == XFmode ) return ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; else if ( mode == XCmode ) return ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; else return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } else { if ( COMPLEX_MODE_P ( mode ) ) return <NUM_LIT> ; else return <NUM_LIT> ; }


<s> static StringRef computeDataLayout ( const Triple & TT ) { if ( TT . isArch64Bit ( ) ) return <STR_LIT> ; assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ; return <STR_LIT> ;


<s> tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; tmpInst . clear ( ) ; tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue & <NUM_LIT> ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode1 , regno1 ) , GEN_INT ( offset1 ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode2 , regno2 ) , GEN_INT ( offset2 ) ) ) ) ;


<s> return ; } LatticeCell DefC = Cells . get ( DefR . Reg ) ; for ( unsigned i = <NUM_LIT> , n = PN . getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { const MachineBasicBlock * PB = PN . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; unsigned PBN = PB -> getNumber ( ) ; if ( ! EdgeExec . count ( CFGEdge ( PBN , MBN ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * PB ) << <STR_LIT> << printMBBReference ( * MB ) << <STR_LIT> ) ; continue ; } const MachineOperand & SO = PN . getOperand ( i ) ; RegisterSubReg UseR ( SO ) ; if ( ! UseR . Reg . isVirtual ( ) ) goto Bottomize ; if ( ! Cells . has ( UseR . Reg ) ) continue ; LatticeCell SrcC ; bool Eval = MCE . evaluate ( UseR , Cells . get ( UseR . Reg ) , SrcC ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * PB ) << <STR_LIT> << printReg ( UseR . Reg , & MCE . TRI , UseR . SubReg ) << SrcC << '\n' ) ; Changed |= Eval ? DefC . meet ( SrcC ) : DefC . setBottom ( ) ;


<s> unsigned InsertMask = RKnown . Zero . getZExtValue ( ) ; if ( ( TargetMask | InsertMask ) == <NUM_LIT> ) { unsigned Op0Opc = Op0 . getOpcode ( ) ; unsigned Op1Opc = Op1 . getOpcode ( ) ; unsigned Value , SH = <NUM_LIT> ; TargetMask = ~ TargetMask ; InsertMask = ~ InsertMask ; if ( Op0Opc == <STR_LIT> && Op1Opc == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } } else if ( Op0Opc == <STR_LIT> || Op0Opc == <STR_LIT> ) { if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( isRunOfOnes ( InsertMask , MB , ME ) ) { if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } if ( Op1Opc == <STR_LIT> ) { KnownBits MKnown = CurDAG -> computeKnownBits ( Op1 . getOperand ( <NUM_LIT> ) ) ; bool CanFoldMask = InsertMask == MKnown . One . getZExtValue ( ) ; unsigned SHOpc = Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) ; if ( ( SHOpc == <STR_LIT> || SHOpc == <STR_LIT> ) && CanFoldMask && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SH = ( SHOpc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ; } } SH &= <NUM_LIT> ; SDValue Ops [ ] = { Op0 , Op1 , getI32Imm ( SH , dl ) , getI32Imm ( MB , dl ) , getI32Imm ( ME , dl ) } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( hasBasePointer ( MF ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : if ( FramePtr == Reg && TFI -> hasFP ( MF ) ) return true ;


<s> virtual bool isConditionalBranch ( const MCInst & Inst ) const { if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ) return false ; return MCInstrAnalysis :: isConditionalBranch ( Inst ) ;


<s> for ( const auto & Op : x86OperandSets [ insn -> spec -> operands ] ) { switch ( Op . encoding ) { case ENCODING_NONE : case ENCODING_SI : case ENCODING_DI : break ; case ENCODING_REG : CASE_ENCODING_RM : if ( readModRM ( insn ) ) return - <NUM_LIT> ; if ( fixupReg ( insn , & Op ) ) return - <NUM_LIT> ; if ( Op . encoding != ENCODING_REG && insn -> eaDisplacement == EA_DISP_8 ) insn -> displacement *= <NUM_LIT> << ( Op . encoding - ENCODING_RM ) ; break ; case ENCODING_IB : if ( sawRegImm ) { insn -> immediates [ insn -> numImmediatesConsumed ] = insn -> immediates [ insn -> numImmediatesConsumed - <NUM_LIT> ] & <NUM_LIT> ; ++ insn -> numImmediatesConsumed ; break ; } if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; if ( Op . type == TYPE_XMM128 || Op . type == TYPE_XMM256 ) sawRegImm = <NUM_LIT> ; break ; case ENCODING_IW : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_ID : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_IO : if ( readImmediate ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Iv : if ( readImmediate ( insn , insn -> immediateSize ) ) return - <NUM_LIT> ; break ; case ENCODING_Ia : if ( readImmediate ( insn , insn -> addressSize ) ) return - <NUM_LIT> ; break ; case ENCODING_RB : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RW : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RD : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_RO : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ; break ; case ENCODING_Rv : if ( readOpcodeRegister ( insn , <NUM_LIT> ) ) return - <NUM_LIT> ;


<s> if ( in_p ) sri -> icode = ( TARGET_64BIT ? CODE_FOR_reloaddi_la_in : CODE_FOR_reloadsi_la_in ) ; else sri -> icode = ( TARGET_64BIT ? CODE_FOR_reloaddi_la_out : CODE_FOR_reloadsi_la_out ) ; } } if ( TARGET_Z10 ) { HOST_WIDE_INT offset ; rtx symref ; if ( in_p && s390_loadrelative_operand_p ( x , & symref , & offset ) && mode == Pmode && ! SYMBOL_FLAG_NOTALIGN2_P ( symref ) && ( offset & <NUM_LIT> ) == <NUM_LIT> ) sri -> icode = ( ( mode == DImode ) ? CODE_FOR_reloaddi_larl_odd_addend_z10 : CODE_FOR_reloadsi_larl_odd_addend_z10 ) ; if ( MEM_P ( x ) && s390_loadrelative_operand_p ( XEXP ( x , <NUM_LIT> ) , NULL , NULL ) && ( mode == QImode || ! reg_class_subset_p ( rclass , GENERAL_REGS ) || GET_MODE_SIZE ( mode ) > UNITS_PER_WORD || ! s390_check_symref_alignment ( XEXP ( x , <NUM_LIT> ) , GET_MODE_SIZE ( mode ) ) ) ) { case E_ ## M ## mode : \ if ( TARGET_64BIT ) \ sri -> icode = in_p ? CODE_FOR_reload ## m ## di_toreg_z10 : \ CODE_FOR_reload ## m ## di_tomem_z10 ; \ else \ sri -> icode = in_p ? CODE_FOR_reload ## m ## si_toreg_z10 : \ CODE_FOR_reload ## m ## si_tomem_z10 ; \ break ; switch ( GET_MODE ( x ) ) { __SECONDARY_RELOAD_CASE ( QI , qi ) ; __SECONDARY_RELOAD_CASE ( HI , hi ) ; __SECONDARY_RELOAD_CASE ( SI , si ) ; __SECONDARY_RELOAD_CASE ( DI , di ) ; __SECONDARY_RELOAD_CASE ( TI , ti ) ; __SECONDARY_RELOAD_CASE ( SF , sf ) ; __SECONDARY_RELOAD_CASE ( DF , df ) ; __SECONDARY_RELOAD_CASE ( TF , tf ) ; __SECONDARY_RELOAD_CASE ( SD , sd ) ; __SECONDARY_RELOAD_CASE ( DD , dd ) ; __SECONDARY_RELOAD_CASE ( TD , td ) ; __SECONDARY_RELOAD_CASE ( V1QI , v1qi ) ; __SECONDARY_RELOAD_CASE ( V2QI , v2qi ) ; __SECONDARY_RELOAD_CASE ( V4QI , v4qi ) ; __SECONDARY_RELOAD_CASE ( V8QI , v8qi ) ; __SECONDARY_RELOAD_CASE ( V16QI , v16qi ) ; __SECONDARY_RELOAD_CASE ( V1HI , v1hi ) ; __SECONDARY_RELOAD_CASE ( V2HI , v2hi ) ; __SECONDARY_RELOAD_CASE ( V4HI , v4hi ) ; __SECONDARY_RELOAD_CASE ( V8HI , v8hi ) ; __SECONDARY_RELOAD_CASE ( V1SI , v1si ) ; __SECONDARY_RELOAD_CASE ( V2SI , v2si ) ; __SECONDARY_RELOAD_CASE ( V4SI , v4si ) ; __SECONDARY_RELOAD_CASE ( V1DI , v1di ) ; __SECONDARY_RELOAD_CASE ( V2DI , v2di ) ; __SECONDARY_RELOAD_CASE ( V1TI , v1ti ) ; __SECONDARY_RELOAD_CASE ( V1SF , v1sf ) ; __SECONDARY_RELOAD_CASE ( V2SF , v2sf ) ; __SECONDARY_RELOAD_CASE ( V4SF , v4sf ) ; __SECONDARY_RELOAD_CASE ( V1DF , v1df ) ;


<s> O << format ( <STR_LIT> PRIu32 , Op . getImm ( ) ) ; return ; }


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetMsa ( ) ; return false ;


<s> I . addOperand ( MCOperand :: createExpr ( MCSymbolRefExpr :: create ( Symbol , OutContext ) ) ) ;

OutStreamer -> emitInstruction ( I , STI ) ;


<s> bool <ISA_LIT>AsmParser :: validateBLGP ( const MCInst & Inst , const OperandVector & Operands ) { unsigned Opc = Inst . getOpcode ( ) ; int BlgpIdx = <STR_LIT> ( Opc , <STR_LIT> :: blgp ) ; if ( BlgpIdx == - <NUM_LIT> ) return true ; SMLoc BLGPLoc = getBLGPLoc ( Operands ) ; if ( ! BLGPLoc . isValid ( ) ) return true ; bool IsNeg = StringRef ( BLGPLoc . getPointer ( ) ) . startswith ( <STR_LIT> ) ; auto FB = getFeatureBits ( ) ; bool UsesNeg = false ; if ( FB [ <STR_LIT> ] ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : UsesNeg = true ;


<s> for ( unsigned i = <NUM_LIT> , n = outputs . length ( ) ; i < n ; ++ i ) if ( reg_overlap_mentioned_p ( mof_reg , outputs [ i ] ) ) return NULL ; for ( unsigned i = <NUM_LIT> , n = inputs . length ( ) ; i < n ; ++ i ) if ( reg_overlap_mentioned_p ( mof_reg , inputs [ i ] ) ) return NULL ;


<s> auto ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) { if ( OffsetOpc == TargetOpcode :: G_SHL ) return None ; std :: swap ( OffsetReg , ConstantReg ) ; ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) return None ; } int64_t ImmVal = ValAndVReg -> Value ; if ( OffsetOpc == TargetOpcode :: G_MUL ) { if ( ! isPowerOf2_32 ( ImmVal ) ) return None ; ImmVal = Log2_32 ( ImmVal ) ; } if ( ( ImmVal & <NUM_LIT> ) != ImmVal ) return None ; if ( ImmVal != LegalShiftVal ) return None ; unsigned SignExtend = <NUM_LIT> ; if ( WantsExt ) { if ( ! LookedThroughZExt ) { MachineInstr * ExtInst = getDefIgnoringCopies ( OffsetReg , MRI ) ; auto Ext = getExtendTypeForInst ( * ExtInst , MRI , true ) ; if ( Ext == <STR_LIT> ) return None ; SignExtend = isSignExtendShiftType ( Ext ) ? <NUM_LIT> : <NUM_LIT> ; if ( SignExtend && Ext != <STR_LIT> ) return None ; OffsetReg = ExtInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; }

MachineIRBuilder MIB ( * MRI . getVRegDef ( Root . getReg ( ) ) ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; const <ISA_LIT>FunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; if ( AFI -> isThumb2Function ( ) ) {

if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ;


<s> void setMergeForward ( bool V = true ) { MergeForward = V ;


<s> const char * load_string ; int r ; if ( GET_CODE ( mem ) == FLOAT_EXTEND || GET_CODE ( mem ) == ZERO_EXTEND ) { mem = XEXP ( mem , <NUM_LIT> ) ; mode = GET_MODE ( mem ) ; } if ( GET_CODE ( reg ) == SUBREG ) { gcc_assert ( SUBREG_BYTE ( reg ) == <NUM_LIT> ) ; reg = SUBREG_REG ( reg ) ; } if ( ! REG_P ( reg ) ) fatal_insn ( <STR_LIT> , reg ) ; r = REGNO ( reg ) ; if ( FP_REGNO_P ( r ) ) { if ( mode == SFmode ) load_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) load_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( ALTIVEC_REGNO_P ( r ) && TARGET_P9_DFORM_SCALAR ) { if ( mode == SFmode ) load_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) load_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( INT_REGNO_P ( r ) ) { switch ( mode ) { case E_QImode : load_string = <STR_LIT> ; break ; case E_HImode : load_string = <STR_LIT> ; break ; case E_SImode : case E_SFmode :


<s> bool Changed = false ; if ( T . TopDown ) Changed = T . processBlock ( B , AVs ) ; RegisterSet Defs ; for ( auto & I : B ) getInstrDefs ( I , Defs ) ;


<s> Pos = - <NUM_LIT> ; } else { assert ( It -> getParent ( ) == B ) ; Pos = std :: distance ( B -> begin ( ) , It ) ; }


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { llvm :: RegisterTarget < llvm :: Triple :: <ISA_LIT> > X ( llvm :: getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ;


<s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {


<s> void <ISA_LIT>AsmBackend :: relaxInstruction ( const MCInst & Inst , MCInst & Res ) const {


<s> Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>FrameInfo :: hasFP ( const MachineFunction & MF ) const {

const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


<s> case 'Q' : part_mode = QImode ; break ; case 'H' : part_mode = HImode ; break ; case 'S' : part_mode = SImode ; break ; default : return <NUM_LIT> ; } switch ( str [ <NUM_LIT> ] ) { case 'H' : mode = HImode ; break ; case 'S' : mode = SImode ; break ; case 'D' : mode = DImode ; break ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


<s> } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { unsigned TCOpcode = ( RetOpcode == <STR_LIT> ) ? ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) : ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ;


<s> if ( UseTraps ) TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; else TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; return false ; } if ( ImmValue == <NUM_LIT> ) { TOut . emitRRR ( <STR_LIT> , RdReg , RsReg , <STR_LIT> , IDLoc , STI ) ; return false ; } else if ( Signed && ImmValue == - <NUM_LIT> ) { TOut . emitRRR ( SubOp , RdReg , ZeroReg , RsReg , IDLoc , STI ) ; return false ; } else { if ( loadImmediate ( ImmValue , ATReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , Inst . getLoc ( ) , Out , STI ) ) return true ; TOut . emitRR ( DivOp , RsReg , ATReg , IDLoc , STI ) ; TOut . emitR ( <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } return true ; } if ( RtReg == <STR_LIT> || RtReg == <STR_LIT> ) { if ( UseTraps ) { TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; return false ; } TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; return false ; } MCContext & Context = TOut . getStreamer ( ) . getContext ( ) ; MCSymbol * BrTarget ; MCOperand LabelOp ; if ( UseTraps ) { TOut . emitRRI ( <STR_LIT> , RtReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; } else { BrTarget = Context . createTempSymbol ( ) ; LabelOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( BrTarget , Context ) ) ; TOut . emitRRX ( <STR_LIT> , RtReg , ZeroReg , LabelOp , IDLoc , STI ) ; } TOut . emitRR ( DivOp , RsReg , RtReg , IDLoc , STI ) ; if ( ! UseTraps ) TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; if ( ! Signed ) { if ( ! UseTraps ) TOut . getStreamer ( ) . EmitLabel ( BrTarget ) ; TOut . emitR ( <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ;


<s> } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; if ( NeedTrunc ) { Op0Reg = EmitIntExt ( RetVT , Op0Reg , <STR_LIT> , false ) ; Op1Reg = emitAND_ri ( <STR_LIT> , Op1Reg , Op1IsKill , Mask ) ; Op0IsKill = Op1IsKill = true ; } unsigned ResultReg = FastEmitInst_rr ( Opc , RC , Op0Reg , Op0IsKill , Op1Reg , Op1IsKill ) ; if ( NeedTrunc ) ResultReg = emitAND_ri ( <STR_LIT> , ResultReg , true , Mask ) ; return ResultReg ;


<s> obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , host_descr_filename ) ; obstack_ptr_grow ( & argv_obstack , target_so_filename ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , out_obj_filename ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; char * * new_argv = XOBFINISH ( & argv_obstack , char * * ) ; fork_execute ( new_argv [ <NUM_LIT> ] , new_argv , false , NULL ) ; obstack_free ( & argv_obstack , NULL ) ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , symbols [ <NUM_LIT> ] ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , symbols [ <NUM_LIT> ] ) ;


<s> unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * MI -> getParent ( ) ) << <STR_LIT> << MaxDisp << <STR_LIT> << getOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ; if ( BrOffset <= DestOffset ) { if ( DestOffset - BrOffset <= MaxDisp ) return true ; } else {

if ( BrOffset - DestOffset <= MaxDisp ) return true ;


<s> <ISA_LIT>16FrameLowering :: <ISA_LIT>16FrameLowering ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>FrameLowering ( STI , STI . stackAlignment ( ) ) {


<s> ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + VT . getVectorNumElements ( ) * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getNode ( <STR_LIT> , DL , ResVT , ResHi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } } else { unsigned ReducedSizeInBits = ReducedVT . getSizeInBits ( ) ; if ( ( RegSize % ReducedSizeInBits ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( RegSize / ReducedSizeInBits , DAG . getUNDEF ( ReducedVT ) ) ; Ops [ <NUM_LIT> ] = NewN0 ; NewN0 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; Ops [ <NUM_LIT> ] = NewN1 ; NewN1 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; if ( Mode == MULU8 || Mode == MULS8 ) { SDValue Mul = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue Res = DAG . getNode ( Mode == MULU8 ? <STR_LIT> : <STR_LIT> , DL , ResVT , Mul ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } else { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , OpsVT , MulLo , MulHi ) ; Res = DAG . getNode ( <STR_LIT> , DL , ResVT , Res ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; return ( Rn << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; } unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; unsigned Imm = MO2 . getImm ( ) ; bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ;

bool isImm = MO1 . getReg ( ) == <NUM_LIT> ;


<s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; CurrentFnSym -> redefineIfPossible ( ) ; if ( CurrentFnSym -> isVariable ( ) ) report_fatal_error ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) + <STR_LIT> ) ; if ( CurrentFnSym -> isDefined ( ) ) report_fatal_error ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) + <STR_LIT> ) ; OS << <STR_LIT> << toSymbol ( CurrentFnSym -> getName ( ) ) ;

OutStreamer -> EmitRawText ( OS . str ( ) ) ;


addPass ( create<ISA_LIT>HardwareLoops ( ) ) ;


<s> EVT VT = Vl . getValueType ( ) ; uint64_t ShAmt = cast < ConstantSDNode > ( ShiftAmt . getNode ( ) ) -> getZExtValue ( ) ; for ( uint64_t i = <NUM_LIT> ; i < ShAmt ; i ++ ) {

Vl = DAG . getNode ( <STR_LIT> , DL , VT , Vl , Vl ) ;


<s> if ( ( * annotationCache ) . find ( m ) == ( * annotationCache ) . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;

else if ( ( * annotationCache ) [ m ] . find ( gv ) == ( * annotationCache ) [ m ] . end ( ) ) cacheAnnotationFromMD ( m , gv ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_AGPR ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> void <ISA_LIT>CodeEmitter :: emitMachineBasicBlock ( MachineBasicBlock * BB , unsigned Reloc ) const { MCE . addRelocation ( MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( ) , Reloc , BB ) ) ;


<s> static DecodeStatus DecodeZPR4RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = ZZZZDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> return new CheriAddressingModeFolder ( ) ;


<s> unsigned reset ( unsigned NewTop ) {


<s> if ( CCMI -> getOpcode ( ) != TargetOpcode :: G_ICMP ) return false ; Register LHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; if ( ! VRegAndVal ) std :: swap ( RHS , LHS ) ; VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; if ( ! VRegAndVal || VRegAndVal -> Value != <NUM_LIT> ) { MachineIRBuilder MIB ( I ) ; if ( ! emitIntegerCompare ( CCMI -> getOperand ( <NUM_LIT> ) , CCMI -> getOperand ( <NUM_LIT> ) , CCMI -> getOperand ( <NUM_LIT> ) , MIB ) ) return false ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( ( CmpInst :: Predicate ) CCMI -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC ) . addMBB ( DestMBB ) ; I . eraseFromParent ( ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ;


<s> MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( get<ISA_LIT>SubSuperRegister ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ) ; } else { assert ( MIB -> getOpcode ( ) == <STR_LIT> ) ; StackAdjustment = <NUM_LIT> ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) ) . addImm ( Imm ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>FrameLowering * TFL = Subtarget . getFrameLowering ( ) ; bool IsWin64Prologue = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool NeedsDwarfCFI = ! IsWin64Prologue && MF . needsFrameMoves ( ) ; bool EmitCFI = ! TFL -> hasFP ( MF ) && NeedsDwarfCFI ; if ( EmitCFI ) { TFL -> BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , StackAdjustment ) ) ; TFL -> BuildCFI ( MBB , std :: next ( I ) , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - StackAdjustment ) ) ;


<s> return DAG . getTarget ( ) . shouldAssumeDSOLocal ( * Mod , GV ) && ! dyn_cast_or_null < GlobalIFunc > ( GV ) ; } ; bool UsePlt = Subtarget . is32BitELFABI ( ) && ! isLocalCallee ( ) && Subtarget . getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; const auto getAIXFuncEntryPointSymbolSDNode = [ & ] ( const GlobalValue * GV ) { const TargetMachine & TM = Subtarget . getTargetMachine ( ) ; const TargetLoweringObjectFile * TLOF = TM . getObjFileLowering ( ) ; MCSymbolXCOFF * S = cast < MCSymbolXCOFF > ( TLOF -> getFunctionEntryPointSymbol ( GV , TM ) ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; return DAG . getMCSymbol ( S , PtrVT ) ; } ; if ( isFunctionGlobalAddress ( Callee ) ) { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Callee ) -> getGlobal ( ) ; if ( Subtarget . isAIXABI ( ) ) { assert ( ! isa < GlobalIFunc > ( GV ) && <STR_LIT> ) ; return getAIXFuncEntryPointSymbolSDNode ( GV ) ; } return DAG . getTargetGlobalAddress ( GV , dl , Callee . getValueType ( ) , <NUM_LIT> , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( Subtarget . isAIXABI ( ) ) { const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ;

if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName ) ) ) return getAIXFuncEntryPointSymbolSDNode ( F ) ;


<s> EmitImmediate ( const MCOperand & DispOp , SMLoc Loc , unsigned Size , MCFixupKind FixupKind , unsigned & CurByte , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , int ImmOffset ) const { const MCExpr * Expr = NULL ; if ( DispOp . isImm ( ) ) { if ( FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 && FixupKind != FK_PCRel_4 ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } Expr = MCConstantExpr :: Create ( DispOp . getImm ( ) , Ctx ) ; } else { Expr = DispOp . getExpr ( ) ; }

if ( ( FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || FixupKind == MCFixupKind ( <STR_LIT> ) ) ) {


<s> void <ISA_LIT>InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DestReg , unsigned SubIdx , const MachineInstr & Orig , const TargetRegisterInfo & TRI ) const { bool ClobbersEFLAGS = Orig . modifiesRegister ( <STR_LIT> , & TRI ) ; if ( ClobbersEFLAGS && MBB . computeRegisterLiveness ( & TRI , <STR_LIT> , I ) != MachineBasicBlock :: LQR_Dead ) { int Value ; switch ( Orig . getOpcode ( ) ) { case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = <NUM_LIT> ; break ; case <STR_LIT> : Value = - <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }

const DebugLoc & DL = Orig . getDebugLoc ( ) ;


<s> unsigned getPrefetchDistance ( ) const override { return <NUM_LIT> ;


<s> sh_fsca_sf2int_rtx = const_double_from_real_value ( rv , SFmode ) ; } return sh_fsca_sf2int_rtx ;


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; printOperand ( MI , OpNo ) ; return false ;


<s> MachineBasicBlock * ExitMBB = & MFI ; if ( ExitMBB -> succ_size ( ) == <NUM_LIT> ) { return ExitMBB ; } }


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) {

TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target , create<ISA_LIT>Disassembler ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerELFTLSDescCallSeq ( SDValue SymAddr , const SDLoc & DL , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , { Chain , SymAddr } ) ;


<s> for ( unsigned J = <NUM_LIT> , E = BBInfo . size ( ) ; J != E ; ++ J ) { const BasicBlockInfo & BBI = BBInfo [ J ] ;

dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << format ( <STR_LIT> , BBInfo [ J ] . Size ) ;


<s> break ; case <STR_LIT> : { APInt KnownZero2 , KnownOne2 ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , KnownZero2 , KnownOne2 , Depth + <NUM_LIT> ) ; KnownZero &= KnownZero2 ; KnownOne &= KnownOne2 ; break ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = KnownOne . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarType ( ) . getSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; }


<s> rtx rs6000_longcall_ref ( rtx call_ref ) { const char * call_name ; tree node ; if ( GET_CODE ( call_ref ) != SYMBOL_REF ) return call_ref ; call_name = XSTR ( call_ref , <NUM_LIT> ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name ++ ; node = get_identifier ( call_name ) ; call_ref = gen_rtx_SYMBOL_REF ( VOIDmode , IDENTIFIER_POINTER ( node ) ) ; }


<s> bool isFPDRegListWithVPR ( ) const { return Kind == k_FPDRegisterListWithVPR ;


<s> static bool isAnyInRange ( ArrayRef < int > Mask , int Low , int Hi ) { return llvm :: any_of ( Mask , [ Low , Hi ] ( int M ) { return isInRange ( M , Low , Hi ) ; } ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createImm ( const MCExpr * Val , SMLoc S , SMLoc E , bool IsRV64 ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( KindTy :: Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ;


<s> static void encode_pdp11_f ( const struct real_format * fmt ATTRIBUTE_UNUSED , long * buf , const REAL_VALUE_TYPE * r ) { ( * vax_f_format . encode ) ( fmt , buf , r ) ; buf [ <NUM_LIT> ] = ( ( buf [ <NUM_LIT> ] >> <NUM_LIT> ) & <NUM_LIT> ) | ( ( buf [ <NUM_LIT> ] & <NUM_LIT> ) << <NUM_LIT> ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( <STR_LIT> ( Cond . getNode ( ) ) ) { SmallVector < int , <NUM_LIT> > Mask ;

if ( createShuffleMaskFromVSELECT ( Mask , Cond ) ) return DAG . getVectorShuffle ( VT , SDLoc ( Op ) , LHS , RHS , Mask ) ;


return ( poly64x1_t ) __builtin_neon_vreinterpretdiv4hi ( ( int16x4_t ) __a ) ;


<s> auto NextBBI = std :: next ( MBB . getIterator ( ) ) ; bool NoSuccessor = llvm :: find ( MBB . successors ( ) , & * NextBBI ) == MBB . succ_end ( ) ; MachineBasicBlock * SkipBB ; if ( NoSuccessor ) { SkipBB = & MBB ; } else { SkipBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( NextBBI , SkipBB ) ; BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( & * NextBBI ) ; MBB . addSuccessor ( SkipBB ) ;


<s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) , TailAgnostic ( false ) , MaskAgnostic ( false ) , MaskRegOp ( false ) , StoreOp ( false ) , ScalarMovOp ( false ) , SEWLMULRatioOnly ( false ) {


<s> Register lreg = operand -> getReg ( ) ; return SRegToNumber ( lreg ) > <NUM_LIT> ; } return false ;


<s> FuncReturnHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder & MIB , CCAssignFn * AssignFn ) : ValueHandler ( MIRBuilder , MRI , AssignFn ) , MIB ( MIB ) {


<s> return std :: make_pair ( Register ( ) , Offset ) ; } int64_t Offset ; if ( Def -> getOpcode ( ) == TargetOpcode :: G_ADD ) { if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Offset ) ) ) return std :: make_pair ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , Offset ) ;

if ( mi_match ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_Copy ( m_ICst ( Offset ) ) ) ) return std :: make_pair ( Def -> getOperand ( <NUM_LIT> ) . getReg ( ) , Offset ) ;


<s> bool <ISA_LIT>16RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return false ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , CTX ( ctx ) {


<s> std :: vector < std :: string > mov2 ( ArRn2 a , ArStep2 as , Px b ) { return D ( <STR_LIT> , MemARS ( a , as ) , R ( b ) ) ;


<s> ELF<ISA_LIT>_64AsmBackend ( const Target & T , uint8_t OSABI , StringRef CPU ) : ELF<ISA_LIT>AsmBackend ( T , OSABI , CPU ) {


<s> std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != <STR_LIT> ) return NumRegisters ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return <NUM_LIT> ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ;


<s> bool <ISA_LIT>TargetLowering :: isProfitableToHoist ( Instruction * I ) const {

if ( I -> getOpcode ( ) == Instruction :: Call ) return false ;


<s> Value /= Multiply ; Value &= ~ ( uint64_t ( ~ <NUM_LIT> ) << Size ) ;

<STR_LIT> :: write64le ( RawData , <STR_LIT> :: read64le ( RawData ) | Value ) ;


<s> static bool is_microcoded_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_tune == PROCESSOR_CELL ) return get_attr_cell_micro ( insn ) == CELL_MICRO_ALWAYS ; if ( rs6000_sched_groups && ( rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_update ( insn ) == UPDATE_YES && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES ) || ( ( type == TYPE_LOAD || type == TYPE_STORE ) && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) || type == TYPE_MFCR ) return true ; }


<s> SplitParts = TRI . getRegSplitParts ( RC , EltSize ) ; NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; if ( IsWave32 ) { ExecReg = <STR_LIT> ; MovOpc = <STR_LIT> ; NotOpc = <STR_LIT> ; } else { ExecReg = <STR_LIT> ; MovOpc = <STR_LIT> ; NotOpc = <STR_LIT> ; } assert ( SuperReg != <STR_LIT> && <STR_LIT> ) ;

assert ( SuperReg != <STR_LIT> && SuperReg != <STR_LIT> && SuperReg != <STR_LIT> && <STR_LIT> ) ;


<s> bool hasITBlocks ( ) const { return HasITBlocks ;


<s> return insertShift ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return insertMul ( MI , MBB ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const <ISA_LIT>InstrInfo & TII = ( const <ISA_LIT>InstrInfo & ) * MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * FallThrough = MBB -> getFallThrough ( ) ; if ( FallThrough != nullptr ) { BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( FallThrough ) ; } MachineBasicBlock * trueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * falseMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ;


<s> if ( splittable_const_int_operand ( src , mode ) ) { mips_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( mips_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , dest , src ) ) ; return ; } if ( mips_tls_symbol_p ( src ) ) { mips_emit_move ( dest , mips_legitimize_tls_address ( src ) ) ; return ;


<s> MF -> insert ( I , trueMBB ) ; MF -> insert ( I , falseMBB ) ; trueMBB -> splice ( trueMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; trueMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; <STR_LIT> CC = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( MBB , dl , TII . getBrCond ( CC ) ) . addMBB ( trueMBB ) ; BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( falseMBB ) ; MBB -> addSuccessor ( falseMBB ) ; MBB -> addSuccessor ( trueMBB ) ; BuildMI ( falseMBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( trueMBB ) ; falseMBB -> addSuccessor ( trueMBB ) ;

BuildMI ( * trueMBB , trueMBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( falseMBB ) ;


<s> bool AMDGPUInstrInfo :: DefinesPredicate ( MachineInstr * MI , std :: vector < MachineOperand > & Pred ) const {


<s> if ( isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } status = DecodeAS ( MI , insn , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( ! isLoad ) { status = DecodeSX ( MI , sx , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ;


<s> if ( ! isUInt < <NUM_LIT> > ( MFI . getStackSize ( ) ) ) return true ;

return MF . getSubtarget < GCNSubtarget > ( ) . hasScalarStores ( ) && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasSpilledSGPRs ( ) ;


<s> for ( unsigned i = <NUM_LIT> , e = Data . size ( ) ; i != e ; ++ i ) { unsigned char C = Data [ i ] ; if ( C == '"' || C == '\\' ) { OS << '\\' << ( char ) C ; continue ; } if ( isprint ( ( unsigned char ) C ) ) { OS << ( char ) C ; continue ; } switch ( C ) { case '\b' : OS << <STR_LIT> ; break ; case '\f' : OS << <STR_LIT> ; break ; case '\n' : OS << <STR_LIT> ; break ; case '\r' : OS << <STR_LIT> ; break ;


<s> SDValue Flag = EmitCmp ( LHS , RHS , CC , <ISA_LIT>CC , DAG ) ;

return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , <ISA_LIT>CC , Flag ) ;


<s> RS -> enterBasicBlockEnd ( MBB ) ; Register Scav = RS -> scavengeRegisterBackwards ( <STR_LIT> , MachineBasicBlock :: iterator ( GetPC ) , false , <NUM_LIT> , false ) ; if ( Scav ) { RS -> setRegUsed ( Scav ) ; MRI . replaceRegWith ( PCReg , Scav ) ; MRI . clearVirtRegs ( ) ; } else { const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; TRI -> spillEmergencySGPR ( GetPC , RestoreBB , <STR_LIT> , RS ) ; MRI . replaceRegWith ( PCReg , <STR_LIT> ) ; MRI . clearVirtRegs ( ) ; } MCSymbol * DestLabel = Scav ? DestBB . getSymbol ( ) : RestoreBB . getSymbol ( ) ; auto * Offset = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( DestLabel , MCCtx ) , MCSymbolRefExpr :: create ( PostGetPCLabel , MCCtx ) , MCCtx ) ; auto * Mask = MCConstantExpr :: create ( <NUM_LIT> , MCCtx ) ; OffsetLo -> setVariableValue ( MCBinaryExpr :: createAnd ( Offset , Mask , MCCtx ) ) ; auto * ShAmt = MCConstantExpr :: create ( <NUM_LIT> , MCCtx ) ; OffsetHi -> setVariableValue ( MCBinaryExpr :: createAShr ( Offset , ShAmt , MCCtx ) ) ; return ;


<s> rtx tmp10 = gen_reg_rtx ( DImode ) ; rtx tmp11 = gen_reg_rtx ( DImode ) ; rtx tmp12 = gen_reg_rtx ( DImode ) ; rtx tmp13 = gen_reg_rtx ( DImode ) ; rtx result_lo = gen_reg_rtx ( DImode ) ; if ( sign ) { emit_insn ( gen_insn_mul_hs_lu ( tmp0 , op1 , op2 ) ) ; emit_insn ( gen_insn_mul_hs_lu ( tmp1 , op2 , op1 ) ) ; emit_insn ( gen_insn_mul_lu_lu ( tmp2 , op1 , op2 ) ) ; emit_insn ( gen_insn_mul_hs_hs ( tmp3 , op1 , op2 ) ) ; } else { emit_insn ( gen_insn_mul_hu_lu ( tmp0 , op1 , op2 ) ) ; emit_insn ( gen_insn_mul_hu_lu ( tmp1 , op2 , op1 ) ) ; emit_insn ( gen_insn_mul_lu_lu ( tmp2 , op1 , op2 ) ) ; emit_insn ( gen_insn_mul_hu_hu ( tmp3 , op1 , op2 ) ) ; } emit_move_insn ( tmp4 , ( gen_rtx_ASHIFT ( DImode , tmp0 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_move_insn ( tmp5 , ( gen_rtx_ASHIFT ( DImode , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_move_insn ( tmp6 , ( gen_rtx_PLUS ( DImode , tmp4 , tmp5 ) ) ) ; emit_move_insn ( result_lo , ( gen_rtx_PLUS ( DImode , tmp2 , tmp6 ) ) ) ; emit_move_insn ( tmp7 , gen_rtx_LTU ( DImode , tmp6 , tmp4 ) ) ; emit_move_insn ( tmp8 , gen_rtx_LTU ( DImode , result_lo , tmp2 ) ) ; if ( sign ) { emit_move_insn ( tmp9 , ( gen_rtx_ASHIFTRT ( DImode , tmp0 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_move_insn ( tmp10 , ( gen_rtx_ASHIFTRT ( DImode , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ) ; } else { emit_move_insn ( tmp9 , ( gen_rtx_LSHIFTRT ( DImode , tmp0 , GEN_INT ( <NUM_LIT> ) ) ) ) ; emit_move_insn ( tmp10 , ( gen_rtx_LSHIFTRT ( DImode , tmp1 , GEN_INT ( <NUM_LIT> ) ) ) ) ; } emit_move_insn ( tmp11 , ( gen_rtx_PLUS ( DImode , tmp3 , tmp7 ) ) ) ;

emit_move_insn ( tmp12 , ( gen_rtx_PLUS ( DImode , tmp8 , tmp9 ) ) ) ;


<s> unsigned NumOperands = MI . getNumOperands ( ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> snprintf ( mcu_name , sizeof ( mcu_name ) - <NUM_LIT> , <STR_LIT> , target_mcu ) ; for ( i = strlen ( mcu_name ) ; i -- ; ) mcu_name [ i ] = TOUPPER ( mcu_name [ i ] ) ; return mcu_name ; } return msp430x ? <STR_LIT> : <STR_LIT> ;


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>InstrInfo :: getRegisterInfo ( ) const { return RI ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_<ISA_LIT>_SaveList ;


<s> unsigned regno = REGNO ( reg ) ; unsigned nregs = hard_regno_nregs [ regno ] [ GET_MODE ( reg ) ] ; while ( nregs -- > <NUM_LIT> ) ss . reg_set_in_cycle [ regno + nregs ] = cycles ;


<s> return C && C -> getAPIntValue ( ) . ule ( <NUM_LIT> ) ;


<s> return __builtin_neon_vminnmhf ( __a , __b ) ;


<s> return SDValue ( ) ; } SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = split64BitValue ( N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue LoRHS = DAG . getConstant ( Lo_32 ( Val ) , SL , <STR_LIT> ) ; SDValue HiRHS = DAG . getConstant ( Hi_32 ( Val ) , SL , <STR_LIT> ) ; SDValue LoAnd = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , LoRHS ) ; SDValue HiAnd = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi , HiRHS ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoAnd , HiAnd ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: hexagon , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> } else { assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; Name = <STR_LIT> + utostr ( getFunctionNumber ( ) ) + <STR_LIT> ;


<s> return <NUM_LIT> <= MsgId && isUInt < ID_WIDTH_ > ( MsgId ) ;


if ( ! ( isRegIdx ( ) && RegIdx . Kind ) ) return false ;


<s> return true ; case <STR_LIT> : if ( ! Abs . getNode ( ) ) return false ; Src = Src . getOperand ( <NUM_LIT> ) ; Abs = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> void unstackifyVReg ( unsigned VReg ) { auto I = Register :: virtReg2Index ( VReg ) ;

if ( I < VRegStackified . size ( ) ) VRegStackified . reset ( I ) ;


<s> cum -> stdarg = stdarg_p ( fntype ) ; cum -> libcall = libcall ; cum -> nargs_prototype = <NUM_LIT> ; if ( incoming || cum -> prototype ) cum -> nargs_prototype = n_named_args ; if ( ( ! fntype && rs6000_default_long_calls ) || ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) ) cum -> call_cookie |= CALL_LONG ; if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> ) ; if ( fntype ) { tree ret_type = TREE_TYPE ( fntype ) ; fprintf ( stderr , <STR_LIT> , get_tree_code_name ( TREE_CODE ( ret_type ) ) ) ; } if ( cum -> call_cookie & CALL_LONG ) fprintf ( stderr , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> , cum -> prototype , cum -> nargs_prototype ) ; } if ( DEFAULT_ABI == ABI_V4 ) { cum -> escapes = call_ABI_of_interest ( fndecl ) ; if ( cum -> escapes ) { tree return_type ; if ( fntype ) { return_type = TREE_TYPE ( fntype ) ; return_mode = TYPE_MODE ( return_type ) ; } else return_type = lang_hooks . types . type_for_mode ( return_mode , <NUM_LIT> ) ; if ( return_type != NULL ) { if ( TREE_CODE ( return_type ) == RECORD_TYPE && TYPE_TRANSPARENT_AGGR ( return_type ) ) { return_type = TREE_TYPE ( first_field ( return_type ) ) ; return_mode = TYPE_MODE ( return_type ) ; } if ( AGGREGATE_TYPE_P ( return_type ) && ( ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( return_type ) <= <NUM_LIT> ) ) rs6000_returns_struct = true ; } if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( return_mode ) ) rs6000_passes_float = true ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( return_mode ) || SPE_VECTOR_MODE ( return_mode ) ) rs6000_passes_vector = true ;


<s> Inst . addOperand ( MCOperand :: createReg ( getMatrixReg ( ) ) ) ;


<s> unsigned int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { ix86_emit_save_reg_using_mov ( word_mode , regno , cfa_offset ) ; cfa_offset -= UNITS_PER_WORD ;


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Chain , Jump , Cond ) ;


<s> vst1_u64 ( uint64_t * a , uint64x1_t b ) { * a = b [ <NUM_LIT> ] ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;

BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ;


<s> return get<ISA_LIT>ArchVersion ( ) >= <STR_LIT> :: V5 ;


<s> Inner -> Parent = Simple ; if ( Blocks . size ( ) > <NUM_LIT> ) { Blocks . remove ( Inner ) ; GetBlocksOut ( Inner , NextEntries , & Blocks ) ; BlockSet JustInner ; JustInner . insert ( Inner ) ;

for ( const auto & iter : NextEntries ) Solipsize ( iter , Branch :: Direct , Simple , JustInner ) ;


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; }

if ( RegInfo -> requiresRegisterScavenging ( MF ) ) if ( needsFP ( MF ) || spillsCR ( MF ) ) {


<s> SGPRSpillVGPRCSR ( Register V , Optional < int > F ) : VGPR ( V ) , FI ( F ) {


<s> return true ; } scalar_float_mode mode ; if ( GET_CODE ( value ) != CONST_DOUBLE || ! is_a < scalar_float_mode > ( GET_MODE ( value ) , & mode ) || GET_MODE_BITSIZE ( mode ) > HOST_BITS_PER_WIDE_INT || GET_MODE_BITSIZE ( mode ) > GET_MODE_BITSIZE ( DFmode ) ) return false ; unsigned HOST_WIDE_INT ival = <NUM_LIT> ; long res [ <NUM_LIT> ] ; real_to_target ( res , CONST_DOUBLE_REAL_VALUE ( value ) , REAL_MODE_FORMAT ( mode ) ) ; if ( mode == DFmode ) { int order = BYTES_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ; ival = zext_hwi ( res [ order ] , <NUM_LIT> ) ; ival |= ( zext_hwi ( res [ <NUM_LIT> - order ] , <NUM_LIT> ) << <NUM_LIT> ) ; } else ival = zext_hwi ( res [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> PseudoSourceValue ( PseudoSourceValue :: TargetCustom ) {


<s> unsigned SrcAS = ASC -> getSrcAddressSpace ( ) ; return SrcAS == <ISA_LIT>AS :: LOCAL_ADDRESS || SrcAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ;


<s> else if ( small_symbolic_operand ( x , Pmode ) ) { * ptr = gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , x ) ; iter . skip_subrtxes ( ) ;


<s> virtual const char * getPassName ( ) const {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FirstMI << <STR_LIT> ) ; return false ; } auto canRenameMOP = [ TRI ] ( const MachineOperand & MOP ) { if ( MOP . isReg ( ) ) { auto * RegClass = TRI -> getMinimalPhysRegClass ( MOP . getReg ( ) ) ; if ( RegClass -> HasDisjunctSubRegs ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MOP << <STR_LIT> ) ; return false ; } } return MOP . isImplicit ( ) || ( MOP . isRenamable ( ) && ! MOP . isEarlyClobber ( ) && ! MOP . isTied ( ) ) ; } ; bool FoundDef = false ; std :: function < bool ( MachineInstr & , bool ) > CheckMIs = [ & ] ( MachineInstr & MI , bool IsDef ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; if ( MI . getFlag ( MachineInstr :: FrameSetup ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } UsedInBetween . accumulate ( MI ) ; FoundDef = IsDef ; if ( FoundDef ) { if ( MI . isPseudo ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } for ( auto & MOP : MI . operands ( ) ) { if ( ! MOP . isReg ( ) || ! MOP . isDef ( ) || MOP . isDebug ( ) || ! MOP . getReg ( ) || ! TRI -> regsOverlap ( MOP . getReg ( ) , RegToRename ) ) continue ; if ( ! canRenameMOP ( MOP ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MOP << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } RequiredClasses . insert ( TRI -> getMinimalPhysRegClass ( MOP . getReg ( ) ) ) ; } return true ;


<s> return ( TARGET_BRANCH_CHEAP ? <NUM_LIT> : <NUM_LIT> ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) , Has65816 ( STI . hasFeature ( <STR_LIT> ) ) {


<s> case ALTIVEC_BUILTIN_STVXL : return altivec_expand_stv_builtin ( CODE_FOR_altivec_stvxl , arglist ) ; case ALTIVEC_BUILTIN_MFVSCR : icode = CODE_FOR_altivec_mfvscr ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; pat = GEN_FCN ( icode ) ( target ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return target ; case ALTIVEC_BUILTIN_MTVSCR : icode = CODE_FOR_altivec_mtvscr ; arg0 = TREE_VALUE ( arglist ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node ) return const0_rtx ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; pat = GEN_FCN ( icode ) ( op0 ) ; if ( pat ) emit_insn ( pat ) ; return NULL_RTX ; case ALTIVEC_BUILTIN_DSSALL : emit_insn ( gen_altivec_dssall ( ) ) ; return NULL_RTX ; case ALTIVEC_BUILTIN_DSS : icode = CODE_FOR_altivec_dss ; arg0 = TREE_VALUE ( arglist ) ; STRIP_NOPS ( arg0 ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node ) return const0_rtx ; if ( TREE_CODE ( arg0 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg0 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return const0_rtx ; } if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; emit_insn ( gen_altivec_dss ( op0 ) ) ; return NULL_RTX ; case ALTIVEC_BUILTIN_VEC_INIT_V4SI : case ALTIVEC_BUILTIN_VEC_INIT_V8HI : case ALTIVEC_BUILTIN_VEC_INIT_V16QI : case ALTIVEC_BUILTIN_VEC_INIT_V4SF : return altivec_expand_vec_init_builtin ( TREE_TYPE ( exp ) , arglist , target ) ; case ALTIVEC_BUILTIN_VEC_SET_V4SI : case ALTIVEC_BUILTIN_VEC_SET_V8HI : case ALTIVEC_BUILTIN_VEC_SET_V16QI : case ALTIVEC_BUILTIN_VEC_SET_V4SF : return altivec_expand_vec_set_builtin ( arglist ) ; case ALTIVEC_BUILTIN_VEC_EXT_V4SI :


<s> bool isStrictlyFGRAsmReg ( ) const {

return isRegIdx ( ) && RegIdx . Kind == RegKind_FGR && RegIdx . Index <= <NUM_LIT> ;


<s> void WinEHStatePass :: insertStateNumberStore ( Value * ParentRegNode , Instruction * IP , int State ) {


<s> FrameIdx = MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; } XFI -> setUsesLR ( FrameIdx ) ; XFI -> setLRSpillSlot ( FrameIdx ) ; } if ( requiresRegisterScavenging ( MF ) ) { RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ; } if ( hasFP ( MF ) ) { XFI -> setFPSpillSlot ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ;


<s> assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; <STR_LIT> Domain = <STR_LIT> ; if ( Subtarget -> isMClass ( ) ) { Domain = <STR_LIT> ; } else if ( Subtarget -> preferISHSTBarriers ( ) && Ord == AtomicOrdering :: Release ) { Domain = <STR_LIT> ; }

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , DAG . getConstant ( Domain , dl , <STR_LIT> ) ) ;


<s> void printMemOffs64 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


<s> printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ;


<s> end_sequence ( ) ; return NULL_RTX ; } op0 = prepare_operand ( icode , op0 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; op1 = prepare_operand ( icode , op1 , <NUM_LIT> , op_mode , cmp_mode , unsignedp ) ; if ( ! op0 || ! op1 ) { end_sequence ( ) ; return NULL_RTX ; } * prep_seq = get_insns ( ) ; end_sequence ( ) ; cmp = gen_rtx_fmt_ee ( ( enum rtx_code ) code , cmp_mode , op0 , op1 ) ; target = gen_rtx_REG ( CCmode , CC_REGNUM ) ; create_output_operand ( & ops [ <NUM_LIT> ] , target , CCmode ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , cmp ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , op0 ) ; create_fixed_operand ( & ops [ <NUM_LIT> ] , op1 ) ; start_sequence ( ) ; if ( ! maybe_expand_insn ( icode , <NUM_LIT> , ops ) ) { end_sequence ( ) ;


<s> if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) || I -> isIndirectBranch ( ) ) return true ; if ( ! isPredicated ( * I ) ) { if ( ! I -> isUnconditionalBranch ( ) ) fixOpcodeForGuard ( * I ) ; TBB = getBranchTarget ( & * I ) ; if ( AllowModify ) { while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; } continue ; }


<s> offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; } else if ( SYMBOL_REF_P ( x ) ) sym = x ; else if ( CONST_INT_P ( x ) ) offset = INTVAL ( x ) ; else if ( GET_CODE ( x ) == LABEL_REF ) offset = <NUM_LIT> ; else return false ; unsigned align = <NUM_LIT> ; if ( sym ) { tree decl = SYMBOL_REF_DECL ( sym ) ; if ( TARGET_MACHO && flag_pic && ! machopic_offs_p ) return false ; if ( MACHO_SYMBOL_INDIRECTION_P ( sym ) ) ; else if ( decl && DECL_ALIGN ( decl ) ) align = DECL_ALIGN_UNIT ( decl ) ; } unsigned int extra = <NUM_LIT> ; switch ( mode ) { case E_DFmode : case E_DDmode : case E_DImode : if ( VECTOR_MEM_VSX_P ( mode ) ) return false ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( ( offset & <NUM_LIT> ) || ( align & <NUM_LIT> ) ) return false ; break ; case E_TFmode : case E_IFmode : case E_KFmode : case E_TDmode : case E_TImode :


<s> SchedModel . init ( * ST . getSchedModel ( ) , & ST , TII ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF -> getName ( ) << '\n' ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : * MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; unsigned BaseReg ; unsigned Offset ;

if ( TII -> getLdStBaseRegImmOfs ( & MI , BaseReg , Offset , TRI ) ) {


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ;


<s> case <STR_LIT> : case <STR_LIT> : SDSTName = <STR_LIT> :: vdst ; break ; default : SDSTName = <STR_LIT> :: sdst ; break ; } const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; const <STR_LIT> IV = <STR_LIT> ( ST . getCPU ( ) ) ; const MachineOperand * SDST = TII -> getNamedOperand ( * MI , SDSTName ) ; if ( ! SDST ) { for ( const auto & MO : MI -> implicit_operands ( ) ) { if ( MO . isDef ( ) && TRI -> isSGPRClass ( TRI -> getPhysRegClass ( MO . getReg ( ) ) ) ) { SDST = & MO ; break ; } } } if ( ! SDST ) return false ; const unsigned SDSTReg = SDST -> getReg ( ) ; auto IsHazardFn = [ SDSTReg , TRI ] ( MachineInstr * I ) { return <ISA_LIT>InstrInfo :: isSMRD ( * I ) && I -> readsRegister ( SDSTReg , TRI ) ; } ; auto IsExpiredFn = [ TII , IV ] ( MachineInstr * MI , int ) { if ( MI ) { if ( TII -> isSALU ( * MI ) ) { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> :

return ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) && ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF ) const {


<s> virtual bool doInitialization ( Module & M ) override {

if ( ! TOC . empty ( ) ) TOC . clear ( ) ;