<s> return ; } else if ( IS_VTX ( Desc ) ) { uint64_t InstWord01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t InstWord2 = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { InstWord2 |= <NUM_LIT> << <NUM_LIT> ; } Emit ( InstWord01 , OS ) ; Emit ( InstWord2 , OS ) ; Emit ( ( uint32_t ) <NUM_LIT> , OS ) ; } else if ( IS_TEX ( Desc ) ) { int64_t Sampler = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t SrcSelect [ <NUM_LIT> ] = { MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) } ; int64_t Offsets [ <NUM_LIT> ] = { MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> } ; uint64_t Word01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t Word2 = Sampler << <NUM_LIT> | SrcSelect [ ELEMENT_X ] << <NUM_LIT> | SrcSelect [ ELEMENT_Y ] << <NUM_LIT> | SrcSelect [ ELEMENT_Z ] << <NUM_LIT> | SrcSelect [ ELEMENT_W ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> ; Emit ( Word01 , OS ) ; Emit ( Word2 , OS ) ; Emit ( ( uint32_t ) <NUM_LIT> , OS ) ; } else { uint64_t Inst = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) && ( ( Desc . TSFlags & <STR_LIT> ) || Desc . TSFlags & <STR_LIT> ) ) { uint64_t ISAOpCode = Inst & ( <NUM_LIT> << <NUM_LIT> ) ; Inst &= ~ ( <NUM_LIT> << <NUM_LIT> ) ;


<s> int NumLoInputs = count_if ( Mask , [ Size ] ( int M ) { return M >= <NUM_LIT> && M % Size < Size / <NUM_LIT> ; } ) ; int NumHiInputs = count_if ( Mask , [ Size ] ( int M ) { return M % Size >= Size / <NUM_LIT> ; } ) ; bool UnpackLo = NumLoInputs >= NumHiInputs ; auto TryUnpack = [ & ] ( MVT UnpackVT , int Scale ) { SmallVector < int , <NUM_LIT> > V1Mask ( Mask . size ( ) , - <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > V2Mask ( Mask . size ( ) , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; int UnpackIdx = i / Scale ; if ( ( UnpackIdx % <NUM_LIT> == <NUM_LIT> ) != ( Mask [ i ] < Size ) ) return SDValue ( ) ; SmallVectorImpl < int > & VMask = ( UnpackIdx % <NUM_LIT> == <NUM_LIT> ) ? V1Mask : V2Mask ; VMask [ ( UnpackIdx / <NUM_LIT> ) * Scale + i % Scale + ( UnpackLo ? <NUM_LIT> : Size / <NUM_LIT> ) ] = Mask [ i ] % Size ; } if ( ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) && ! isNoopShuffleMask ( V1Mask ) && ! isNoopShuffleMask ( V2Mask ) ) return SDValue ( ) ; V1 = DAG . getVectorShuffle ( VT , DL , V1 , DAG . getUNDEF ( VT ) , V1Mask ) ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Mask ) ; V1 = DAG . getBitcast ( UnpackVT , V1 ) ; V2 = DAG . getBitcast ( UnpackVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( UnpackLo ? <STR_LIT> : <STR_LIT> , DL , UnpackVT , V1 , V2 ) ) ; } ; int OrigNumElements = VT . getVectorNumElements ( ) ; int OrigScalarSize = VT . getScalarSizeInBits ( ) ; for ( int ScalarSize = <NUM_LIT> ; ScalarSize >= OrigScalarSize ; ScalarSize /= <NUM_LIT> ) { int Scale = ScalarSize / OrigScalarSize ; int NumElements = OrigNumElements / Scale ; MVT UnpackVT = <STR_LIT> ( <STR_LIT> ( ScalarSize ) , NumElements ) ; if ( SDValue Unpack = TryUnpack ( UnpackVT , Scale ) ) return Unpack ; } if ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) { assert ( ( NumLoInputs > <NUM_LIT> || NumHiInputs > <NUM_LIT> ) && <STR_LIT> ) ; int HalfOffset = NumLoInputs == <NUM_LIT> ? Size / <NUM_LIT> : <NUM_LIT> ;

SmallVector < int , <NUM_LIT> > PermMask ( ( unsigned ) Size , - <NUM_LIT> ) ;


<s> uint64_t Rsrc23 = getDefaultRsrcDataFormat ( ) | <STR_LIT> | <NUM_LIT> ;

uint64_t EltSizeValue = Log2_32 ( ST . getMaxPrivateElementSize ( ) ) - <NUM_LIT> ;


<s> MachineBasicBlock :: iterator Prev = std :: prev ( MBBI ) ; if ( ! Prev -> isCall ( ) || ! Prev -> getOperand ( <NUM_LIT> ) . isRegMask ( ) ) return false ; unsigned Regs [ <NUM_LIT> ] ; unsigned FoundRegs = <NUM_LIT> ; auto RegMask = Prev -> getOperand ( <NUM_LIT> ) ; for ( auto Candidate : <STR_LIT> ) { if ( ! RegMask . clobbersPhysReg ( Candidate ) ) continue ; bool IsDef = false ; for ( const MachineOperand & MO : Prev -> implicit_operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == Candidate ) {


<s> pReloc . target ( ) = pReloc . symValue ( ) + A - pReloc . place ( ) ; return Relocator :: OK ;


<s> bool supportSwiftError ( ) const override { return true ;


<s> case CONST : case CONST_INT : if ( UNSIGNED_INT6 ( INTVAL ( operands [ opno ] ) ) ) return true ; default :


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget -> hasLZCNT ( ) ;


<s> case EQ : case NE : case GTU : case LTU : case GEU : case LEU : return <NUM_LIT> ;


<s> if ( isDesirableToShrinkOp ( Op . getOpcode ( ) , <STR_LIT> , Op . getValueType ( ) ) ) return false ; PVT = <STR_LIT> ;


<s> O << <STR_LIT> ; SwitchToSection ( BSSSections [ i ] -> S_ ) ; std :: vector < const GlobalVariable * > Items = BSSSections [ i ] -> Items ; for ( unsigned j = <NUM_LIT> ; j < Items . size ( ) ; j ++ ) { std :: string Name = Mang -> getValueName ( Items [ j ] ) ; Constant * C = Items [ j ] -> getInitializer ( ) ;


<s> MIB -> setDesc ( Desc ) ; MIB . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ;

assert ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg && MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg && <STR_LIT> ) ;


<s> void sh_pr_trapa ( struct cpp_reader * pfile ATTRIBUTE_UNUSED ) {


<s> MachineInstrBuilder MIB ( * MF , newInstr ) ; MIB . addReg ( dstReg , RegState :: Define ) ; MIB . addReg ( src1Reg ) ; MIB . addReg ( src2Reg ) ;


<s> FOR_EACH_SUBRTX_VAR ( iter , array , PATTERN ( x ) , ALL ) { rtx sub = * iter ; if ( sub && GET_CODE ( sub ) == UNSPEC ) { int unspec_val = XINT ( sub , <NUM_LIT> ) ; switch ( unspec_val ) { case UNSPEC_PACIASP : case UNSPEC_PACIBSP : return true ; default : return false ; } iter . skip_subrtxes ( ) ; }


<s> if ( IdxN -> isNullValue ( ) && ValTy . getSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; } if ( ValWidth == <NUM_LIT> ) { SDValue A0 = getInstr ( <STR_LIT> , dl , <STR_LIT> , { VecV } , DAG ) ; SDValue M0 = DAG . getConstant ( <NUM_LIT> / VecWidth , dl , <STR_LIT> ) ; SDValue I0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , M0 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A0 , I0 ) ; } unsigned Scale = VecWidth / ValWidth ; assert ( ty ( IdxV ) == <STR_LIT> ) ; unsigned VecRep = <NUM_LIT> / VecWidth ; SDValue S0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( <NUM_LIT> * VecRep , dl , <STR_LIT> ) ) ; SDValue T0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VecV ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T0 , S0 ) ; while ( Scale > <NUM_LIT> ) { T1 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , T1 ) ; T1 = expandPredicate ( T1 , dl , DAG ) ; Scale /= <NUM_LIT> ; } return DAG . getNode ( <STR_LIT> , dl , ResTy , T1 ) ; } assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ; SDValue ExtV ; if ( IdxN ) { unsigned Off = IdxN -> getZExtValue ( ) * ElemWidth ; if ( VecWidth == <NUM_LIT> && ValWidth == <NUM_LIT> ) { assert ( Off == <NUM_LIT> || Off == <NUM_LIT> ) ; unsigned SubIdx = Off == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; ExtV = DAG . getTargetExtractSubreg ( SubIdx , dl , <STR_LIT> , VecV ) ; } else if ( Off == <NUM_LIT> && ( ValWidth % <NUM_LIT> ) == <NUM_LIT> ) { ExtV = DAG . getZeroExtendInReg ( VecV , dl , tyScalar ( ValTy ) ) ; } else { SDValue OffV = DAG . getConstant ( Off , dl , <STR_LIT> ) ; ExtV = DAG . getNode ( <STR_LIT> , dl , ScalarTy , { VecV , WidthV , OffV } ) ; } } else { if ( ty ( IdxV ) != <STR_LIT> ) IdxV = DAG . getZExtOrTrunc ( IdxV , dl , <STR_LIT> ) ;

SDValue OffV = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( ElemWidth , dl , <STR_LIT> ) ) ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) , UC ( Parser ) { MCAsmParserExtension :: Initialize ( Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( AddBuildAttributes ) getTargetStreamer ( ) . emitTargetAttributes ( STI ) ; ITState . CurPosition = ~ <NUM_LIT> ;


<s> Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! Tok . getIdentifier ( ) . startswith ( <STR_LIT> ) ) return MatchOperand_NoMatch ; StringRef NumString = Tok . getIdentifier ( ) . substr ( <NUM_LIT> ) ; unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return MatchOperand_NoMatch ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( <STR_LIT> ) ;


<s> if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getGlobalVariable ( <STR_LIT> ) ;

return TargetLowering :: getSDagStackGuard ( M ) ;


<s> Register ShiftSrc ; const unsigned Size = Ty . getScalarSizeInBits ( ) ; if ( ! mi_match ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_GAnd ( m_OneNonDBGUse ( m_GAShr ( m_Reg ( ShiftSrc ) , m_ICst ( ShrAmt ) ) ) , m_ICst ( AndImm ) ) ) ) return false ; auto MaybeMask = static_cast < uint64_t > ( AndImm ) ; if ( MaybeMask & ( MaybeMask + <NUM_LIT> ) ) return false ; if ( static_cast < uint64_t > ( ShrAmt ) >= Size ) return false ; uint64_t Width = APInt ( Size , AndImm ) . countTrailingOnes ( ) ; if ( static_cast < uint64_t > ( ShrAmt ) + Width >= Size && ! Helper . getKnownBits ( ) -> signBitIsZero ( ShiftSrc ) ) return false ; MatchInfo = [ = ] ( MachineIRBuilder & B ) { auto WidthCst = B . buildConstant ( ExtractTy , Width ) ; auto LSBCst = B . buildConstant ( ExtractTy , ShrAmt ) ; B . buildInstr ( TargetOpcode :: G_UBFX , { Dst } , { ShiftSrc , LSBCst , WidthCst } ) ; } ; return true ;


<s> printAddress ( & MAI , MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) , MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) , O ) ;


<s> const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ) ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ;

return MRI -> canReserveReg ( BasePtr ) ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ;

SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> getAlignment ( ) , S -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> return TargetABI == <ISA_LIT>_ABI_APCS ;


<s> static bool rs6000_legitimate_combined_insn ( rtx_insn * insn ) { int icode = INSN_CODE ( insn ) ;

if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_ctrsi_internal1 || icode == CODE_FOR_ctrdi_internal1 || icode == CODE_FOR_ctrsi_internal2 || icode == CODE_FOR_ctrdi_internal2 || icode == CODE_FOR_ctrsi_internal3 || icode == CODE_FOR_ctrdi_internal3 || icode == CODE_FOR_ctrsi_internal4 || icode == CODE_FOR_ctrdi_internal4 ) ) return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( I -> isDeclaration ( ) ) continue ; if ( EmitSpecialLLVMGlobal ( I ) ) continue ; std :: string name = Mang -> getValueName ( I ) ; Constant * C = I -> getInitializer ( ) ; unsigned Align = TD -> getPreferredAlignmentLog ( I ) ; bool bCustomSegment = false ; switch ( I -> getLinkage ( ) ) { case GlobalValue :: CommonLinkage : case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : SwitchToDataSection ( <STR_LIT> ) ; O << name << <STR_LIT> ; bCustomSegment = true ; break ; case GlobalValue :: AppendingLinkage : SwitchToDataSection ( <STR_LIT> ) ; O << name << <STR_LIT> ; bCustomSegment = true ; break ; case GlobalValue :: DLLExportLinkage : DLLExportedGVs . insert ( name ) ; case GlobalValue :: ExternalLinkage : O << <STR_LIT> << name << <STR_LIT> ; case GlobalValue :: InternalLinkage : SwitchToSection ( TAI -> getDataSection ( ) ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } if ( ! bCustomSegment ) EmitAlignment ( Align , I ) ; O << name << <STR_LIT> ; if ( VerboseAsm ) O << name << <STR_LIT> << TAI -> getCommentString ( ) << <STR_LIT> << I -> getName ( ) ; O << '\n' ; EmitGlobalConstant ( C ) ; if ( bCustomSegment ) O << name << <STR_LIT> ; } if ( ! DLLExportedGVs . empty ( ) || ! DLLExportedFns . empty ( ) ) { SwitchToDataSection ( <STR_LIT> ) ; O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; O << <STR_LIT> ; }

for ( StringSet < > :: iterator i = DLLExportedGVs . begin ( ) , e = DLLExportedGVs . end ( ) ;


<s> AlignFragment * align = NULL ; if ( pFrom . getSection ( ) . align ( ) > <NUM_LIT> ) { unsigned int alignment = pFrom . getSection ( ) . align ( ) ; align = new AlignFragment ( alignment , <NUM_LIT> , <NUM_LIT> , alignment - <NUM_LIT> ) ; pFrom . getFragmentList ( ) . push_front ( align ) ; } if ( found ) to_list . splice ( fragInsert , pFrom . getFragmentList ( ) ) ;

else to_list . splice ( frag , pFrom . getFragmentList ( ) ) ;


<s> else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; assert ( Ins [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ;


<s> SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


<s>
const
MCOperand
&
MO3
=
MI
->
getOperand
(
OpNum
+
<NUM_LIT>
)
;
printRegName
(
O
,
MO1
.
getReg
(
)
)
;
<STR_LIT>
ShOpc
=
<STR_LIT>
(
MO3
.
getImm
(
)
)
;
O
<<
<STR_LIT>
<<
<STR_LIT>
(
ShOpc
)
;
if
(
ShOpc
==
<STR_LIT>
)
return
;
O
<<
' '
;
printRegName
(
O
,
MO2
.
getReg
(
)
)
;
assert
(
<STR_LIT>
(
MO3
.
getImm
(
)
)
==
<NUM_LIT>
)
;


<s> EVT IndexVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Index . getValueType ( ) . getVectorNumElements ( ) ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , IndexVT , Index ) ; SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ <NUM_LIT> ] = Trunc ; DAG . UpdateNodeOperands ( N , NewOps ) ; DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) { SDValue Index = N -> getOperand ( <NUM_LIT> ) ; if ( Index . getScalarValueSizeInBits ( ) == <NUM_LIT> && Index . getOpcode ( ) == <STR_LIT> && Index . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) == <NUM_LIT> ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ <NUM_LIT> ] = Index . getOperand ( <NUM_LIT> ) ; DAG . UpdateNodeOperands ( N , NewOps ) ; DCI . AddToWorklist ( Index . getNode ( ) ) ; DCI . AddToWorklist ( N ) ;


<s> static bool nvptx_vpropagate ( bool is_call , basic_block block , rtx_insn * insn ) { return nvptx_propagate ( is_call , block , insn , PM_read_write , vprop_gen , <NUM_LIT> ) ;


<s> if ( GVMap . empty ( ) ) { return false ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; } IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ; for ( Function :: iterator BBI = I -> begin ( ) , BBE = I -> end ( ) ; BBI != BBE ; ++ BBI ) { for ( BasicBlock :: iterator II = BBI -> begin ( ) , IE = BBI -> end ( ) ; II != IE ; ++ II ) { for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i < e ; ++ i ) { Value * Operand = II -> getOperand ( i ) ; if ( isa < Constant > ( Operand ) ) { II -> setOperand ( i , remapConstant ( & M , I , cast < Constant > ( Operand ) , Builder ) ) ; } } } } ConstantToValueMap . clear ( ) ; } for ( Module :: named_metadata_iterator I = M . named_metadata_begin ( ) , E = M . named_metadata_end ( ) ; I != E ; I ++ ) { remapNamedMDNode ( & M , I ) ; } for ( GVMapTy :: iterator I = GVMap . begin ( ) , E = GVMap . end ( ) ; I != E ; ) { GlobalVariable * GV = I -> first ; GlobalVariable * NewGV = I -> second ; ++ I ; Constant * BitCastNewGV = ConstantExpr :: getBitCast ( NewGV , GV -> getType ( ) ) ; for ( Value :: use_iterator UI = GV -> use_begin ( ) , UE = GV -> use_end ( ) ; UI != UE ; ) { Use & U = ( UI ++ ) . getUse ( ) ; U . set ( BitCastNewGV ) ; } std :: string Name = GV -> getName ( ) ; GV -> removeDeadConstantUsers ( ) ; GV -> eraseFromParent ( ) ; NewGV -> setName ( Name ) ; } GVMap . clear ( ) ;


<s> const std :: pair < int , unsigned > & Src = Srcs [ j ] ; if ( Src . first < <NUM_LIT> ) continue ; if ( Vector [ Src . second ] [ j ] < <NUM_LIT> ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return false ; } } return true ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , PointerSize ( computePointerSize ( TT ) ) , UsesLogicalAddressing ( TT . is<ISA_LIT>Logical ( ) ) , UsesVulkanEnv ( TT . isVulkanEnvironment ( ) ) , UsesOpenCLEnv ( TT . isOpenCLEnvironment ( ) ) , Target<ISA_LIT>Version ( <NUM_LIT> ) , TargetOpenCLVersion ( <NUM_LIT> ) , TargetVulkanVersion ( computeTargetVulkanVersion ( TT ) ) , OpenCLFullProfile ( computeOpenCLFullProfile ( TT ) ) , OpenCLImageSupport ( computeOpenCLImageSupport ( TT ) ) , InstrInfo ( ) , FrameLowering ( initSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) { initAvailableExtensions ( TT ) ; initAvailableExtInstSets ( TT ) ; initAvailableCapabilities ( TT ) ; GR = std :: make_unique < <ISA_LIT>GlobalRegistry > ( PointerSize ) ; CallLoweringInfo = std :: make_unique < <ISA_LIT>CallLowering > ( TLInfo , GR . get ( ) ) ; Legalizer = std :: make_unique < <ISA_LIT>LegalizerInfo > ( * this ) ; RegBankInfo = std :: make_unique < <ISA_LIT>RegisterBankInfo > ( ) ;

InstSelector . reset ( create<ISA_LIT>InstructionSelector ( TM , * this , * RegBankInfo . get ( ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> unsigned Rt = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ;

if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ;


<s> rtx high ; if ( TARGET_MIPS16 ) { high = GEN_INT ( offset ) ; offset = <NUM_LIT> ; } else { high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitFEXT_CCRX16_ins ( unsigned SltOpc , MachineInstr * MI , MachineBasicBlock * BB ) const { if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned CC = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addReg ( regY ) ;


<s> unsigned getMinNumSGPRs ( const MCSubtargetInfo * STI , unsigned WavesPerEU ) { assert ( WavesPerEU != <NUM_LIT> ) ; if ( WavesPerEU >= getMaxWavesPerEU ( ) ) return <NUM_LIT> ; unsigned MinNumSGPRs = getTotalNumSGPRs ( STI ) / ( WavesPerEU + <NUM_LIT> ) ;

if ( STI -> getFeatureBits ( ) . test ( FeatureTrapHandler ) ) MinNumSGPRs -= std :: min ( MinNumSGPRs , ( unsigned ) TRAP_NUM_SGPRS ) ;


<s> if ( ! BasePtr ) return nullptr ; Value * Load = tryCreateIncrementingGatScat ( I , BasePtr , Offsets , GEP , Builder ) ; if ( Load ) return Load ; int Scale = computeScale ( BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) , OriginalTy -> getScalarSizeInBits ( ) ) ; if ( Scale == - <NUM_LIT> ) return nullptr ; Root = Extend ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { ResultTy , BasePtr -> getType ( ) , Offsets -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( OriginalTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Builder . getInt32 ( Unsigned ) , Mask } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { ResultTy , BasePtr -> getType ( ) , Offsets -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( OriginalTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Builder . getInt32 ( Unsigned ) } ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> const bool FullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; if ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( ! FullFP16 && LHS . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; RHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RHS ) ; SDValue NewSetcc = DAG . getSetCC ( dl , <STR_LIT> , LHS , RHS , CC ) ; DAG . ReplaceAllUsesWith ( Op , NewSetcc ) ; CmpVT = <STR_LIT> ; } else return SDValue ( ) ; } assert ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> || LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT> ) { SDValue Cmp2 = EmitVectorComparison ( LHS , RHS , CC2 , NoNaNs , CmpVT , dl , DAG ) ;

if ( ! Cmp2 . getNode ( ) ) return SDValue ( ) ;


<s> Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: udiv ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ;


<s> } const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { printRegOperand ( Op . getReg ( ) , O , MRI ) ; } else if ( Op . isImm ( ) ) { switch ( Desc . OpInfo [ OpNo ] . OperandType ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case MCOI :: OPERAND_IMMEDIATE : printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate64 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate16 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! isUInt < <NUM_LIT> > ( Op . getImm ( ) ) && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediateV216 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O << <STR_LIT> ; } switch ( MI -> getOpcode ( ) ) {


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) + <NUM_LIT> , SDLoc ( N ) , VT ) ) ; } } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , false ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; if ( SDValue V = combineIncDecVector ( N , DAG ) ) return V ; return combineAddOrSubToADCOrSBB ( N , DAG ) ;


<s> } else if ( SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> ) { MVT CVT = <STR_LIT> ( SplatBitSize ) ; Constant * C = SplatBitSize == <NUM_LIT> ? ConstantFP :: get ( Type :: getFloatTy ( * Ctx ) , SplatValue . bitsToFloat ( ) ) : ConstantFP :: get ( Type :: getDoubleTy ( * Ctx ) , SplatValue . bitsToDouble ( ) ) ; SDValue CP = DAG . getConstantPool ( C , PVT ) ; unsigned Repeat = VT . getSizeInBits ( ) / SplatBitSize ; unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( CVT , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Alignment ) ; SDValue Brdcst = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( CVT , Repeat ) , Ld ) ; return DAG . getBitcast ( VT , Brdcst ) ; } else if ( SplatBitSize > <NUM_LIT> ) { MVT CVT = VT . getScalarType ( ) ; Constant * VecC = getConstantVector ( VT , SplatValue , SplatBitSize , * Ctx ) ; SDValue VCP = DAG . getConstantPool ( VecC , PVT ) ; unsigned NumElm = SplatBitSize / VT . getScalarSizeInBits ( ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( VCP ) -> getAlignment ( ) ; Ld = DAG . getLoad ( <STR_LIT> ( CVT , NumElm ) , dl , DAG . getEntryNode ( ) , VCP , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , Alignment ) ; SDValue Brdcst = DAG . getNode ( <STR_LIT> , dl , VT , Ld ) ; return DAG . getBitcast ( VT , Brdcst ) ; } } } return SDValue ( ) ; } bool ConstSplatVal = ( Ld . getOpcode ( ) == <STR_LIT> || Ld . getOpcode ( ) == <STR_LIT> ) ; if ( ! ConstSplatVal && ! BVOp -> isOnlyUserOf ( Ld . getNode ( ) ) ) return SDValue ( ) ; unsigned ScalarSize = Ld . getValueSizeInBits ( ) ;

bool IsGE256 = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) ;


<s> LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ; } ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>FunctionInfo & MFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const <ISA_LIT>TargetLowering & TLI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) ; auto & LibInfo = getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( ) ; bool Changed = false ; for ( auto & MBB : MF ) for ( auto & MI : MBB ) switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MachineOperand & Op1 = MI . getOperand ( <NUM_LIT> ) ; if ( Op1 . isSymbol ( ) ) { StringRef Name ( Op1 . getSymbolName ( ) ) ; if ( Name == TLI . getLibcallName ( RTLIB :: MEMCPY ) || Name == TLI . getLibcallName ( RTLIB :: MEMMOVE ) || Name == TLI . getLibcallName ( RTLIB :: MEMSET ) ) { LibFunc Func ; if ( LibInfo . getLibFunc ( Name , Func ) ) { const auto & Op2 = MI . getOperand ( <NUM_LIT> ) ; if ( ! Op2 . isReg ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; unsigned OldReg = MO . getReg ( ) ; unsigned NewReg = Op2 . getReg ( ) ; if ( MRI . getRegClass ( NewReg ) != MRI . getRegClass ( OldReg ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; Changed |= maybeRewriteToDrop ( OldReg , NewReg , MO , MFI , MRI ) ; } } } break ; } case <STR_LIT> : Changed |= maybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= maybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= maybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ;


<s> const MCExpr * TargetExpr = MCSymbolRefExpr :: create ( Target , MCSymbolRefExpr :: VariantKind :: VK_None , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TargetExpr ) ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; OutStreamer -> emitLabel ( Target ) ;


<s> InstrInfo & II = Instructions [ & MI ] ; assert ( Flag == StateWQM || Flag == StateExact ) ; if ( II . Needs ) return ;


<s> if ( Op . isExpr ( ) ) { Op . getExpr ( ) -> print ( O , & MAI ) ; return ; } llvm_unreachable ( <STR_LIT> ) ;


<s> return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) ) ; } } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ;

SDValue Chain = DAG . getEntryNode ( ) ;


<s> return __builtin_mve_vminnmq_fv8hf ( __a , __b ) ;


<s> static SDValue getFFBH_U32 ( const TargetLowering & TLI , SelectionDAG & DAG , const SDLoc & SL , SDValue Op ) { EVT VT = Op . getValueType ( ) ; EVT LegalVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , VT ) ;

if ( LegalVT != <STR_LIT> ) return SDValue ( ) ;


<s> else * total = <NUM_LIT> ; return true ; case SYMBOL_REF : * total = optimize_size ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : * total = ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ) ;


<s> break ; } MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ; if ( Offset % <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; } FIOp . ChangeToRegister ( <STR_LIT> , false ) ; ImmOp . setImm ( Offset ) ;


<s> return SDValue ( ) ; } if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && CanFoldXORWithAllOnes ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && CanFoldXORWithAllOnes ( N1 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , N0 ) ;


<s> countXMM ++ ; } } } countXMM -- ; for ( MachineFunction :: iterator BBi = MF . begin ( ) ; BBi != MF . end ( ) ; BBi ++ ) { for ( MachineBasicBlock :: iterator MCi = BBi -> begin ( ) ; MCi != BBi -> end ( ) ; MCi ++ ) { if ( MCi -> getOpcode ( ) == <STR_LIT> && ( MCi -> getFlags ( ) & MachineInstr :: FrameSetup ) ) { assert ( MCi -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; MCi -> getOperand ( <NUM_LIT> ) . setImm ( countXMM * <NUM_LIT> ) ; countXMM -- ; } }


<s> if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDValue GA = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( JT ) , <STR_LIT> , GA , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOHiFlag ) ;

SDValue JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOLoFlag ) ;


<s> for ( unsigned I = <NUM_LIT> ; CSRegs [ I ] ; ++ I ) if ( TRI -> isSubRegisterEq ( Reg , CSRegs [ I ] ) && ! LRM -> isPhysRegUsed ( CSRegs [ I ] ) ) return false ;


<s> bool <ISA_LIT>PreAMXConfig :: getKeyAMXShapes ( IntrinsicInst * KeyAMX , SmallVector < Value * , <NUM_LIT> > & Shapes ) { for ( unsigned I = <NUM_LIT> ; I < KeyAMX -> getNumOperands ( ) ; I ++ ) { Value * Op = KeyAMX -> getOperand ( I ) ; if ( ! Op -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) continue ; IntrinsicInst * TileDef = dyn_cast < IntrinsicInst > ( Op ) ; assert ( ( TileDef && isTileLoad ( TileDef ) ) && <STR_LIT> ) ; Shapes . push_back ( TileDef -> getOperand ( <NUM_LIT> ) ) ; Shapes . push_back ( TileDef -> getOperand ( <NUM_LIT> ) ) ; } if ( ! isTileStore ( KeyAMX ) ) { Shapes . push_back ( KeyAMX -> getOperand ( <NUM_LIT> ) ) ; Shapes . push_back ( KeyAMX -> getOperand ( <NUM_LIT> ) ) ;


<s> MVT SVT = ShAmt . getSimpleValueType ( ) ; assert ( ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && <STR_LIT> ) ; if ( ConstantSDNode * CShAmt = dyn_cast < ConstantSDNode > ( ShAmt ) ) return getTargetVShiftByConstNode ( Opc , dl , VT , SrcOp , CShAmt -> getZExtValue ( ) , DAG ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( SVT == <STR_LIT> ) ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; else if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> && ShAmt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) == <STR_LIT> ) { ShAmt = ShAmt . getOperand ( <NUM_LIT> ) ; ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; ShAmt = DAG . getZeroExtendVectorInReg ( ShAmt , SDLoc ( ShAmt ) , <STR_LIT> ) ; } else if ( Subtarget . hasSSE41 ( ) && ShAmt . getOpcode ( ) == <STR_LIT> ) { ShAmt = DAG . getNode ( <STR_LIT> , SDLoc ( ShAmt ) , <STR_LIT> , ShAmt ) ; ShAmt = DAG . getZeroExtendVectorInReg ( ShAmt , SDLoc ( ShAmt ) , <STR_LIT> ) ; } else { SDValue ShOps [ <NUM_LIT> ] = { ShAmt , DAG . getConstant ( <NUM_LIT> , dl , SVT ) , DAG . getUNDEF ( SVT ) , DAG . getUNDEF ( SVT ) } ; ShAmt = DAG . getBuildVector ( <STR_LIT> , dl , ShOps ) ; } MVT EltVT = VT . getVectorElementType ( ) ; MVT ShVT = <STR_LIT> ( EltVT , <NUM_LIT> / EltVT . getSizeInBits ( ) ) ; ShAmt = DAG . getBitcast ( ShVT , ShAmt ) ; return DAG . getNode ( Opc , dl , VT , SrcOp , ShAmt ) ;


<s> static bool isUseSafeToFold ( const MachineInstr & MI , const MachineOperand & UseMO ) {


<s> emitRRR ( Is64Bit ? <STR_LIT> : <STR_LIT> , DstReg , SrcReg , TrgReg , SMLoc ( ) , STI ) ;


<s> void <ISA_LIT>InstPrinter :: printExecutionMode ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {

if ( OpNo < MI -> getNumOperands ( ) ) {


<s> if ( MFI -> getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned IgnoredFrameReg ; Offset = TFL -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) ; return getIndirectIndexBegin ( MF ) + Offset ;


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; lower_argument_func lower_argument ; switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case CallingConv :: <ISA_LIT>_Kernel : MFI -> setKernel ( ) ; lower_argument = lower_kernel_argument ; break ; case CallingConv :: <ISA_LIT>_Device : MFI -> setKernel ( false ) ; lower_argument = lower_device_argument ; break ; } for ( struct argmap_entry * i = argmap , * e = argmap + array_lengthof ( argmap ) ; i != e ; ++ i ) i -> reset ( ) ; for ( int i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { <STR_LIT> VT = Ins [ i ] . VT . SimpleTy ; struct argmap_entry * entry = std :: find ( argmap , argmap + array_lengthof ( argmap ) , VT ) ; if ( entry == argmap + array_lengthof ( argmap ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>AsmParser :: matchSVEVectorNameAlias ( StringRef Name ) { unsigned RegNum = matchSVEVectorRegName ( Name ) ; if ( RegNum == <NUM_LIT> ) RegNum = matchReqRegisterNameAlias ( Name , RegKind :: SVEVector ) ;


<s> RegisterTarget < Triple :: mips > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: mipsel > Y ( The<ISA_LIT>elTarget , <STR_LIT> , <STR_LIT> ) ;


<s> int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;

if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ;


<s> ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , <NUM_LIT> ) ; -- I ;

CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Result ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


<s> Type * Ty = GTI . getIndexedType ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( Idx ) ) { if ( CI -> isZero ( ) ) continue ; TotalOffs += DL . getTypeAllocSize ( Ty ) * cast < ConstantInt > ( CI ) -> getSExtValue ( ) ; continue ; } if ( TotalOffs ) { N = emitAdd_ri_ ( VT , N , TotalOffs ) ; if ( ! N ) return false ; TotalOffs = <NUM_LIT> ; } uint64_t ElementSize = DL . getTypeAllocSize ( Ty ) ; unsigned IdxN = getRegForGEPIndex ( Idx ) ; if ( ! IdxN ) return false ; if ( ElementSize != <NUM_LIT> ) { unsigned C = fastEmit_i ( VT , VT , <STR_LIT> , ElementSize ) ; if ( ! C ) return false ; IdxN = emitMul_rr ( VT , IdxN , C ) ; if ( ! IdxN ) return false ; } N = fastEmit_rr ( VT , VT , <STR_LIT> , N , IdxN ) ; if ( ! N ) return false ; } }


<s> MachineOperand oper = Instr -> getOperand ( i ) ; if ( ! oper . isReg ( ) ) continue ; if ( ! oper . isDef ( ) ) continue ; def = i ; numDefs ++ ; } assert ( ( numDefs <= <NUM_LIT> ) && <STR_LIT> ) ; if ( numDefs == <NUM_LIT> ) { unsigned regnum = Instr -> getOperand ( def ) . getReg ( ) ; if ( ISVECEXTRACT ( Instr ) ) regnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return get<ISA_LIT>VectorSize ( MRI -> getRegClass ( regnum ) ) ; } else if ( numDefs == <NUM_LIT> ) {

assert ( ISVECSTORE ( Instr ) && <STR_LIT> ) ;


return __builtin_ia32_cvttss2si64 ( ( __v4sf ) __A ) ;


<s> void Thumb1InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { assert ( ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) && <STR_LIT> ) ; if ( RC -> hasSuperClassEq ( & <STR_LIT> ) || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { DebugLoc DL ;

if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;


<s> if ( SCALAR_FLOAT_TYPE_P ( t ) || INTEGRAL_TYPE_P ( t ) || POINTER_TYPE_P ( t ) ) { HOST_WIDE_INT s = tree_to_shwi ( TYPE_SIZE_UNIT ( t ) ) ;

return s == <NUM_LIT> || s == <NUM_LIT> || s == <NUM_LIT> || s == <NUM_LIT> ;


<s> unsigned int startbit , endbit ; int intregs , intoffset ; if ( cum -> floats_in_gpr == <NUM_LIT> && ( cum -> intoffset % <NUM_LIT> == <NUM_LIT> || ( cum -> intoffset == - <NUM_LIT> && final ) ) ) { cum -> words ++ ; cum -> floats_in_gpr = <NUM_LIT> ; } if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; cum -> floats_in_gpr = <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , <NUM_LIT> ) . exists ( ) ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; } } startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; cum -> words += intregs ;

if ( ( unsigned ) cum -> words < ( endbit / BITS_PER_WORD ) ) {


<s> unsigned ScalarSize = N -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) ; SDValue Op = peekThroughBitcasts ( SDValue ( N , <NUM_LIT> ) ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; if ( VT . getScalarSizeInBits ( ) != ScalarSize ) return SDValue ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : { if ( ! Op . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; if ( SDValue NegOp0 = isFNEG ( DAG , Op . getOperand ( <NUM_LIT> ) . getNode ( ) , Depth + <NUM_LIT> ) ) if ( NegOp0 . getValueType ( ) == VT ) return DAG . getVectorShuffle ( VT , SDLoc ( Op ) , NegOp0 , DAG . getUNDEF ( VT ) , cast < ShuffleVectorSDNode > ( Op ) -> getMask ( ) ) ; break ; }


<s> for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_dst ) ; i ++ , d ++ ) if ( d -> code == fcode ) { arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg2 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; op2 = expand_normal ( arg2 ) ; mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; * expandedp = true ; STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> , d -> name ) ; return const0_rtx ; } if ( ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( Pmode , op0 ) ; if ( ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 , op2 ) ; if ( pat != <NUM_LIT> ) emit_insn ( pat ) ;


<s> static SDValue LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { DebugLoc dl = Op . getDebugLoc ( ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) {

Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> static unsigned GetNumLeafArrayDimensions ( GetElementPtrInst * V ) { int i = <NUM_LIT> ; SmallVector < Type * , <NUM_LIT> > WorkList ; for ( gep_type_iterator Itr = gep_type_begin ( V ) ; Itr != gep_type_end ( V ) ; Itr ++ ) WorkList . push_back ( Itr . getIndexedType ( ) ) ; WorkList . pop_back ( ) ; while ( WorkList . size ( ) ) {


<s> } if ( Target . getSymB ( ) ) { recordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ; return ; } const MCSymbol * A = nullptr ; if ( Target . getSymA ( ) ) A = & Target . getSymA ( ) -> getSymbol ( ) ; uint32_t Offset = Target . getConstant ( ) ; if ( IsPCRel ) Offset += <NUM_LIT> << Log2Size ; if ( Offset && A && ! Writer -> doesSymbolRequireExternRelocation ( * A ) && recordScatteredRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , Log2Size , FixedValue ) ) return ; uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned Index = <NUM_LIT> ; unsigned Type = <NUM_LIT> ;


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) ; emitWordLE ( Binary ) ;


<s> if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isSLM ( ) ) processInstructionForSLM ( I , MFI ) ; else processInstruction ( I , MFI ) ;


<s> if ( MIOffset % MemSize ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ;


<s> const TargetAsmInfo * <ISA_LIT>TargetMachine :: createTargetAsmInfo ( ) const {

return new <ISA_LIT>LinuxTargetAsmInfo ( * this ) ;


<s> return trunc_int_for_mode ( value , SImode ) == value ; case 'p' :

return value == <NUM_LIT> || s390_single_part ( GEN_INT ( value ) , DImode , SImode , <NUM_LIT> ) == <NUM_LIT> ;


<s> else if ( cfun -> machine -> frame . wb_candidate2 == FIRST_PSEUDO_REGISTER ) cfun -> machine -> frame . wb_candidate2 = regno ; offset += UNITS_PER_WORD ; } for ( regno = V0_REGNUM ; regno <= V31_REGNUM ; regno ++ ) if ( cfun -> machine -> frame . reg_offset [ regno ] == SLOT_REQUIRED ) { cfun -> machine -> frame . reg_offset [ regno ] = offset ; if ( cfun -> machine -> frame . wb_candidate1 == FIRST_PSEUDO_REGISTER ) cfun -> machine -> frame . wb_candidate1 = regno ; else if ( cfun -> machine -> frame . wb_candidate2 == FIRST_PSEUDO_REGISTER && cfun -> machine -> frame . wb_candidate1 >= V0_REGNUM ) cfun -> machine -> frame . wb_candidate2 = regno ; offset += UNITS_PER_WORD ; } cfun -> machine -> frame . padding0 = ( AARCH64_ROUND_UP ( offset , STACK_BOUNDARY / BITS_PER_UNIT ) - offset ) ; offset = AARCH64_ROUND_UP ( offset , STACK_BOUNDARY / BITS_PER_UNIT ) ; cfun -> machine -> frame . saved_regs_size = offset ; cfun -> machine -> frame . hard_fp_offset = AARCH64_ROUND_UP ( cfun -> machine -> frame . saved_varargs_size + get_frame_size ( ) + cfun -> machine -> frame . saved_regs_size , STACK_BOUNDARY / BITS_PER_UNIT ) ;

cfun -> machine -> frame . frame_size = AARCH64_ROUND_UP ( cfun -> machine -> frame . hard_fp_offset + crtl -> outgoing_args_size , STACK_BOUNDARY / BITS_PER_UNIT ) ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {


<s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {


<s> if ( MID . mayStore ( ) ) { MachineOperand StOp = MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; if ( StOp . isReg ( ) && StOp . getReg ( ) == TfrDefR ) return false ; } if ( HII -> getAddrMode ( MI ) == <STR_LIT> ) return ( HII -> changeAddrMode_rr_ur ( MI ) >= <NUM_LIT> ) ; else if ( HII -> getAddrMode ( MI ) == <STR_LIT> ) return ( HII -> changeAddrMode_io_abs ( MI ) >= <NUM_LIT> ) ;


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ;


<s> for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; MIB . addReg ( SrcReg , false , false , isKill ) ; NewMIs . push_back ( MIB ) ; return ;


<s> OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetNoAt ( ) ;


<s> case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerABS ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerREM ( Op , DAG ) ; case <STR_LIT> : return LowerBSWAP ( Op , DAG ) ;


<s> bool CloseParen = false ; if ( MI -> getOpcode ( ) == <STR_LIT> && ! MO . isReg ( ) && ! MO . isImm ( ) ) { O << <STR_LIT> ; CloseParen = true ; } else if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && ! MO . isReg ( ) && ! MO . isImm ( ) ) { O << <STR_LIT> ; CloseParen = true ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << LowercaseString ( getRegisterName ( MO . getReg ( ) ) ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ;

case MachineOperand :: MO_GlobalAddress :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; break ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MOVT_ABS ; break ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MOVW_ABS_NC ; break ;


<s> int sh_expand_t_scc ( enum rtx_code code , rtx target ) { rtx result = target ; HOST_WIDE_INT val ; if ( GET_CODE ( sh_compare_op0 ) != REG || REGNO ( sh_compare_op0 ) != T_REG || GET_CODE ( sh_compare_op1 ) != CONST_INT ) return <NUM_LIT> ; if ( GET_CODE ( result ) != REG ) result = gen_reg_rtx ( SImode ) ; val = INTVAL ( sh_compare_op1 ) ; if ( ( code == EQ && val == <NUM_LIT> ) || ( code == NE && val == <NUM_LIT> ) ) emit_insn ( gen_movt ( result ) ) ; else if ( ( code == EQ && val == <NUM_LIT> ) || ( code == NE && val == <NUM_LIT> ) ) { emit_insn ( gen_rtx_CLOBBER ( VOIDmode , result ) ) ; emit_insn ( gen_subc ( result , result , result ) ) ; emit_insn ( gen_addsi3 ( result , result , const1_rtx ) ) ; } else if ( code == EQ || code == NE ) emit_insn ( gen_move_insn ( result , GEN_INT ( code == NE ) ) ) ; else return <NUM_LIT> ;

if ( result != target ) emit_move_insn ( target , result ) ;


<s> if ( Subtarget -> hasV7Ops ( ) ) { if ( Subtarget -> isAClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> isRClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> isMClass ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } ATS . emitAttribute ( <STR_LIT> , Subtarget -> has<ISA_LIT>Ops ( ) ? <STR_LIT> : <STR_LIT> ) ; if ( Subtarget -> isThumb1Only ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasThumb2 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { if ( Subtarget -> hasCrypto ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; else ATS . emitFPU ( <STR_LIT> ) ; if ( Subtarget -> hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP3 ( ) ) ATS . emitFPU ( Subtarget -> hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( Subtarget -> hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> if ( ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) ) ) return false ; Type * Ty = GVA -> getValueType ( ) ; if ( ! Ty -> isSized ( ) ) return false ;

return isInSmallSection ( GVA -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ;


<s> void printARID8Mem ( const MCInst * MI , unsigned opNum , raw_ostream & O ) { printARIDMem ( MI , opNum , O ) ;


<s> const MachineOperand * Offset1Imm = getNamedOperand ( * LdSt , AMDGPU :: OpName :: offset1 ) ; uint8_t Offset0 = Offset0Imm -> getImm ( ) ; uint8_t Offset1 = Offset1Imm -> getImm ( ) ; assert ( Offset1 > Offset0 ) ; if ( Offset1 - Offset0 == <NUM_LIT> ) { unsigned EltSize ; if ( LdSt -> mayLoad ( ) ) EltSize = getOpRegClass ( * LdSt , <NUM_LIT> ) -> getSize ( ) / <NUM_LIT> ; else { assert ( LdSt -> mayStore ( ) ) ; int Data0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: data0 ) ; EltSize = getOpRegClass ( * LdSt , Data0Idx ) -> getSize ( ) ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , AMDGPU :: OpName :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = EltSize * Offset0 ; return true ; } return false ; } if ( isMUBUF ( Opc ) || isMTBUF ( Opc ) ) { if ( AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: soffset ) != - <NUM_LIT> ) return false ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , AMDGPU :: OpName :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , AMDGPU :: OpName :: offset ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } if ( isSMRD ( Opc ) ) { const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , AMDGPU :: OpName :: offset ) ; if ( ! OffsetImm ) return false ; const MachineOperand * SBaseReg = getNamedOperand ( * LdSt , AMDGPU :: OpName :: sbase ) ; BaseReg = SBaseReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ;


<s> void <ISA_LIT>TargetStreamer :: emit<ISA_LIT>WinCFISaveSP ( unsigned Reg ) {


<s> OpCodes ( unsigned WideOpc , unsigned NarrowOpc ) : WideOpc ( WideOpc ) , NarrowOpc ( NarrowOpc ) {


<s> return ( __m64 ) __builtin_arm_wsrawi ( ( __v2si ) __m , __count ) ;


<s> assert ( ( Subtarget -> hasSSE42 ( ) || Subtarget -> hasAVX ( ) ) && <STR_LIT> ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; unsigned Opc ; if ( ! Subtarget -> hasAVX ( ) ) { if ( memArg ) Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else Opc = numArgs == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; } else {


<s> monitor ( NULL , NULL , NULL , <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( SrcVT == <STR_LIT> ) return Op ; if ( SrcVT == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) { SDNodeFlags Flags ; Flags . setNoFPExcept ( Op -> getFlags ( ) . hasNoFPExcept ( ) ) ; if ( IsSigned ) { SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( IsStrict ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { Op . getOperand ( <NUM_LIT> ) , Lo , Hi } , Flags ) ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { Res . getValue ( <NUM_LIT> ) , Res } , Flags ) ; } else { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; } } else { const uint64_t TwoE31 [ ] = { <NUM_LIT> , <NUM_LIT> } ; APFloat APF = APFloat ( APFloat :: <ISA_LIT>DoubleDouble ( ) , APInt ( <NUM_LIT> , TwoE31 ) ) ; SDValue Cst = DAG . getConstantFP ( APF , dl , SrcVT ) ; SDValue SignMask = DAG . getConstant ( <NUM_LIT> , dl , DstVT ) ;


<s> unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ;


<s> BasicBlockInfo ( ) : Offset ( <NUM_LIT> ) , Size ( <NUM_LIT> ) , KnownBits ( <NUM_LIT> ) , Unalign ( <NUM_LIT> ) {


return llvm :: ELF :: EF_<ISA_LIT>_EABI_VER5 ;


<s> low_dest = riscv_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; } else { riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ;


<s> tree addr , incr ; bool indirect ; tree ptrtype = build_pointer_type ( type ) ; if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { indirect = true ; size = rsize = UNITS_PER_WORD ; align = <NUM_LIT> ; } else { indirect = false ; size = int_size_in_bytes ( type ) ; rsize = ( size + UNITS_PER_WORD - <NUM_LIT> ) & - UNITS_PER_WORD ; align = <NUM_LIT> ; if ( TARGET_ARCH64 ) { if ( TYPE_ALIGN ( type ) >= <NUM_LIT> * ( unsigned ) BITS_PER_WORD ) align = <NUM_LIT> * UNITS_PER_WORD ; if ( AGGREGATE_TYPE_P ( type ) ) { if ( size == <NUM_LIT> ) size = rsize = UNITS_PER_WORD ; else size = rsize ; } } } incr = valist ; if ( align ) { incr = fold ( build2 ( PLUS_EXPR , ptr_type_node , incr , ssize_int ( align - <NUM_LIT> ) ) ) ; incr = fold ( build2 ( BIT_AND_EXPR , ptr_type_node , incr , ssize_int ( - align ) ) ) ; } gimplify_expr ( & incr , pre_p , post_p , is_gimple_val , fb_rvalue ) ; addr = incr ; if ( BYTES_BIG_ENDIAN && size < rsize ) addr = fold ( build2 ( PLUS_EXPR , ptr_type_node , incr , ssize_int ( rsize - size ) ) ) ; if ( indirect ) { addr = fold_convert ( build_pointer_type ( ptrtype ) , addr ) ; addr = build_va_arg_indirect_ref ( addr ) ;


<s> Value * Num = FDiv . getOperand ( <NUM_LIT> ) ; Value * Den = FDiv . getOperand ( <NUM_LIT> ) ; Value * NewFDiv = nullptr ; if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { NewFDiv = UndefValue :: get ( VT ) ; for ( unsigned I = <NUM_LIT> , E = VT -> getNumElements ( ) ; I != E ; ++ I ) { Value * NumEltI = Builder . CreateExtractElement ( Num , I ) ; Value * DenEltI = Builder . CreateExtractElement ( Den , I ) ; Value * NewElt ; if ( shouldKeepFDivF32 ( NumEltI , UnsafeDiv , HasFP32Denormals ) ) { NewElt = Builder . CreateFDiv ( NumEltI , DenEltI ) ; } else { NewElt = Builder . CreateCall ( Decl , { NumEltI , DenEltI } ) ; } NewFDiv = Builder . CreateInsertElement ( NewFDiv , NewElt , I ) ; } } else { if ( ! shouldKeepFDivF32 ( Num , UnsafeDiv , HasFP32Denormals ) ) NewFDiv = Builder . CreateCall ( Decl , { Num , Den } ) ; } if ( NewFDiv ) {


<s> const bool Is64Bit = <STR_LIT> . contains ( Reg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Reg << <STR_LIT> ) ;

BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addDef ( Reg ) . addUse ( Reg ) ;


<s> -- I ; } if ( AllowModify && I -> getOpcode ( ) == <STR_LIT> && MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; I -> eraseFromParent ( ) ; I = MBB . instr_end ( ) ; if ( I == MBB . instr_begin ( ) ) return false ; -- I ; } if ( ! isUnpredicatedTerminator ( I ) ) return false ; MachineInstr * LastInst = I ; MachineInstr * SecondLastInst = nullptr ; do { if ( & * I != LastInst && ! I -> isBundle ( ) && isUnpredicatedTerminator ( I ) ) { if ( ! SecondLastInst ) SecondLastInst = I ; else return true ; } if ( I == MBB . instr_begin ( ) ) break ; -- I ; } while ( I ) ; int LastOpcode = LastInst -> getOpcode ( ) ; bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNot = PredOpcodeHasNot ( LastOpcode ) ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LastOpcodeHasNot ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } int SecLastOpcode = SecondLastInst -> getOpcode ( ) ; bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNot = PredOpcodeHasNot ( SecLastOpcode ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( SecLastOpcodeHasNot ) Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ;

Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>GNULDBackend :: <ISA_LIT>GNULDBackend ( const LinkerConfig & pConfig , GNUInfo * pInfo ) : GNULDBackend ( pConfig , pInfo ) , m_pRelocator ( NULL ) , m_pGOT ( NULL ) , m_pPLT ( NULL ) , m_pRelDyn ( NULL ) , m_pRelPLT ( NULL ) , m_pAttrData ( NULL ) , m_pDynamic ( NULL ) , m_pGOTSymbol ( NULL ) , m_pEXIDXStart ( NULL ) , m_pEXIDXEnd ( NULL ) , m_pEXIDX ( NULL ) , m_pEXTAB ( NULL ) , m_pAttributes ( NULL ) {


<s> if ( type && TYPE_MODE ( type ) == BLKmode && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( size = int_size_in_bytes ( type ) ) > UNITS_PER_WORD && ( size % UNITS_PER_WORD != <NUM_LIT> ) && ( reg + mcore_num_arg_regs ( mode , type ) <= ( FIRST_PARM_REG + NPARM_REGS ) ) ) { rtx arg_regs [ NPARM_REGS ] ; int nregs ; rtx result ; rtvec rtvec ;

for ( nregs = <NUM_LIT> ; size > <NUM_LIT> ; size -= UNITS_PER_WORD ) {


<s> return ; } if ( MI -> getOperand ( OpNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { } else { printOperand ( MI , OpNum + <NUM_LIT> , STI , O ) ; } if ( MI -> getOperand ( OpNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI -> getOperand ( OpNum ) . isImm ( ) && MI -> getOperand ( OpNum ) . getImm ( ) == <NUM_LIT> ) { if ( MI -> getOperand ( OpNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { O << <STR_LIT> ; } else { } } else { O << <STR_LIT> ; if ( MI -> getOperand ( OpNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { } else { printOperand ( MI , OpNum + <NUM_LIT> , STI , O ) ; } if ( MI -> getOperand ( OpNum ) . isImm ( ) && MI -> getOperand ( OpNum ) . getImm ( ) == <NUM_LIT> ) { } else { O << <STR_LIT> ; printOperand ( MI , OpNum , STI , O ) ;


<s> if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; SmallVector < IntrinsicInst * , <NUM_LIT> > Gathers ; SmallVector < IntrinsicInst * , <NUM_LIT> > Scatters ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == <STR_LIT> ) Gathers . push_back ( II ) ; else if ( II && II -> getIntrinsicID ( ) == <STR_LIT> ) Scatters . push_back ( II ) ; }


<s> } if ( ! Subtarget -> hasUnalignedScratchAccess ( ) && ( AddrSpace == <ISA_LIT>AS :: PRIVATE_ADDRESS || AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS ) ) { bool AlignedBy4 = Align >= <NUM_LIT> ; if ( IsFast ) * IsFast = AlignedBy4 ; return AlignedBy4 ; } if ( Subtarget -> hasUnalignedBufferAccess ( ) ) { if ( IsFast ) { * IsFast = ( AddrSpace == <ISA_LIT>AS :: CONSTANT_ADDRESS || AddrSpace == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) ? ( Align % <NUM_LIT> == <NUM_LIT> ) : true ;


<s> LC = RTLIB :: getFPEXT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;

return LowerF128Call ( Op , DAG , LC ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresDifferentSrcAndDst : return Error ( IDLoc , <STR_LIT> ) ; case Match_Immz : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm1_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm2_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm2_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm3_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm4_0 :


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) { StackAlignment = <NUM_LIT> ; DarwinDirective = <STR_LIT> ; HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasAltivec = false ; HasQPX = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ;


<s> return ( int16x8_t ) __builtin_neon_vreinterpretv8hiv16qi ( ( int8x16_t ) __a ) ;


<s> RegKind = IS_SPECIAL ; } else { unsigned RegNumIndex = <NUM_LIT> ; if ( RegName [ <NUM_LIT> ] == 'v' ) { RegNumIndex = <NUM_LIT> ; RegKind = IS_VGPR ; } else if ( RegName [ <NUM_LIT> ] == 's' ) { RegNumIndex = <NUM_LIT> ; RegKind = IS_SGPR ; } else if ( RegName . startswith ( <STR_LIT> ) ) { RegNumIndex = strlen ( <STR_LIT> ) ; RegKind = IS_TTMP ; } else { return false ; } if ( RegName . size ( ) > RegNumIndex ) { if ( RegName . substr ( RegNumIndex ) . getAsInteger ( <NUM_LIT> , RegNum ) ) return false ; Parser . Lex ( ) ; RegWidth = <NUM_LIT> ; } else { Parser . Lex ( ) ; int64_t RegLo , RegHi ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return false ; Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( RegLo ) ) return false ; const bool isRBrace = getLexer ( ) . is ( AsmToken :: RBrac ) ; if ( ! isRBrace && getLexer ( ) . isNot ( AsmToken :: Colon ) ) return false ; Parser . Lex ( ) ; if ( isRBrace ) { RegHi = RegLo ; } else { if ( getParser ( ) . parseAbsoluteExpression ( RegHi ) ) return false ; if ( getLexer ( ) . isNot ( AsmToken :: RBrac ) ) return false ; Parser . Lex ( ) ; } RegNum = ( unsigned ) RegLo ; RegWidth = ( RegHi - RegLo ) + <NUM_LIT> ; } }

} else if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) {


<s> SDValue Add = DAG . getNode ( <STR_LIT> , DL , OpVT , RHS , LHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } if ( RHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDValue Add = DAG . getNode ( <STR_LIT> , DL , OpVT , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } if ( SDValue V = combineVectorSizedSetCCEquality ( N , DAG , Subtarget ) ) return V ; } if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { if ( LHS . getOpcode ( ) == <STR_LIT> ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; } bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( IsSEXT0 && IsVZero1 ) { assert ( VT == LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNOT ( DL , LHS . getOperand ( <NUM_LIT> ) , VT ) ; assert ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && <STR_LIT> ) ; return LHS . getOperand ( <NUM_LIT> ) ; } } if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && VT . getVectorNumElements ( ) > <NUM_LIT> && ( OpVT . getVectorElementType ( ) == <STR_LIT> || OpVT . getVectorElementType ( ) == <STR_LIT> ) ) { SDValue Setcc = DAG . getNode ( <STR_LIT> , DL , OpVT , LHS , RHS , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Setcc ) ; } if ( Subtarget . hasSSE1 ( ) && ! Subtarget . hasSSE2 ( ) && VT == <STR_LIT> && LHS . getValueType ( ) == <STR_LIT> ) return LowerVSETCC ( SDValue ( N , <NUM_LIT> ) , Subtarget , DAG ) ; return SDValue ( ) ;


<s> if ( TREE_CODE ( * node ) != FUNCTION_TYPE && TREE_CODE ( * node ) != METHOD_TYPE && TREE_CODE ( * node ) != FIELD_DECL && TREE_CODE ( * node ) != TYPE_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; return NULL_TREE ;


<s> bool <ISA_LIT>BitSimplify :: getSubregMask ( const BitTracker :: RegisterRef & RR , unsigned & Begin , unsigned & Width , MachineRegisterInfo & MRI ) { const TargetRegisterClass * RC = MRI . getRegClass ( RR . Reg ) ; if ( RC == & <STR_LIT> ) { assert ( RR . Sub == <NUM_LIT> ) ; Begin = <NUM_LIT> ; Width = <NUM_LIT> ; return true ; } if ( RC == & <STR_LIT> ) { if ( RR . Sub == <NUM_LIT> ) { Begin = <NUM_LIT> ; Width = <NUM_LIT> ; return true ; } assert ( RR . Sub == <STR_LIT> || RR . Sub == <STR_LIT> ) ; Width = <NUM_LIT> ; Begin = ( RR . Sub == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; return true ; }


<s> } const GCNSubtarget & STI = MF -> getSubtarget < GCNSubtarget > ( ) ; if ( STI . dumpCode ( ) ) { DisasmLines . push_back ( MF -> getName ( ) . str ( ) + <STR_LIT> ) ; DisasmLineMaxLen = std :: max ( DisasmLineMaxLen , DisasmLines . back ( ) . size ( ) ) ; HexLines . push_back ( <STR_LIT> ) ; } AsmPrinter :: EmitFunctionEntryLabel ( ) ;


<s> inline static const char * <ISA_LIT>CondCodeToString ( <STR_LIT> CC ) { switch ( CC ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ;


<s> SDNode * User = * UI ; if ( ! User -> isMachineOpcode ( ) ) return false ; switch ( User -> getMachineOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( UI . getOperandNo ( ) != <NUM_LIT> || Bits < <NUM_LIT> ) return false ; break ;


<s> report_fatal_error ( <STR_LIT> <STR_LIT> <STR_LIT> ) ; MachineIRBuilder MIRBuilder ; MIRBuilder . setMF ( * MBB . getParent ( ) ) ; MIRBuilder . setMBB ( MBB ) ; int LocalBytesAdded = <NUM_LIT> ; int InstsAdded = <NUM_LIT> ; if ( Cond . size ( ) > <NUM_LIT> ) { assert ( TBB != nullptr && <STR_LIT> ) ; assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; auto falseBlock = FBB ; auto MIB = MIRBuilder . buildInstr ( <STR_LIT> ) . addUse ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; if ( falseBlock ) { MIB . addMBB ( falseBlock ) ; } LocalBytesAdded = <NUM_LIT> ; InstsAdded = <NUM_LIT> ; } else { assert ( ! FBB && <STR_LIT> ) ; if ( TBB ) { if ( MBB . empty ( ) ) { MIRBuilder . buildInstr ( <STR_LIT> ) . addMBB ( TBB ) ; LocalBytesAdded = <NUM_LIT> ; } else { auto MI = MBB . getLastNonDebugInstr ( ) ; if ( MI . isValid ( ) && ! MI -> isKnownSentinel ( ) && MI -> getOpcode ( ) == <STR_LIT> ) { if ( MI -> getNumOperands ( ) == <NUM_LIT> ) { MI -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ; } else { MI -> addOperand ( MachineOperand :: CreateMBB ( TBB ) ) ; } } else { MIRBuilder . buildInstr ( <STR_LIT> ) . addMBB ( TBB ) ; LocalBytesAdded = <NUM_LIT> ; } } InstsAdded = <NUM_LIT> ; }


<s> bool <ISA_LIT>InstrInfo :: isBaseImmOffset ( const MachineInstr & MI ) const {

return getAddrMode ( MI ) == <STR_LIT> ;


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> if ( offset >= cfun_frame_layout . f8_offset ) next_fpr = i ; } if ( ! TARGET_PACKED_STACK ) next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : <NUM_LIT> ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun_frame_layout . frame_size ; if ( cfun_frame_layout . frame_size > <NUM_LIT> ) { rtx frame_off = GEN_INT ( - cfun_frame_layout . frame_size ) ; rtx real_frame_off ; if ( s390_stack_size ) { HOST_WIDE_INT stack_guard ; if ( s390_stack_guard ) stack_guard = s390_stack_guard ; else { stack_guard = <NUM_LIT> ; while ( stack_guard < cfun_frame_layout . frame_size ) stack_guard <<= <NUM_LIT> ; } if ( cfun_frame_layout . frame_size >= s390_stack_size ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , current_function_name ( ) , cfun_frame_layout . frame_size , s390_stack_size ) ; emit_insn ( gen_trap ( ) ) ; } else { if ( stack_guard >= s390_stack_size ) { warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> , current_function_name ( ) , cfun_frame_layout . frame_size ) ; } else { HOST_WIDE_INT stack_check_mask = ( ( s390_stack_size - <NUM_LIT> ) & ~ ( stack_guard - <NUM_LIT> ) ) ; rtx t = gen_rtx_AND ( Pmode , stack_pointer_rtx , GEN_INT ( stack_check_mask ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_ctrapdi4 ( gen_rtx_EQ ( VOIDmode , t , const0_rtx ) , t , const0_rtx , const0_rtx ) ) ; else emit_insn ( gen_ctrapsi4 ( gen_rtx_EQ ( VOIDmode , t , const0_rtx ) , t , const0_rtx , const0_rtx ) ) ; } } } if ( s390_warn_framesize > <NUM_LIT> && cfun_frame_layout . frame_size >= s390_warn_framesize ) warning ( <NUM_LIT> , <STR_LIT> , current_function_name ( ) , cfun_frame_layout . frame_size ) ; if ( s390_warn_dynamicstack_p && cfun -> calls_alloca ) warning ( <NUM_LIT> , <STR_LIT> , current_function_name ( ) ) ; if ( TARGET_BACKCHAIN || next_fpr ) insn = emit_insn ( gen_move_insn ( temp_reg , stack_pointer_rtx ) ) ; if ( DISP_IN_RANGE ( INTVAL ( frame_off ) ) ) { insn = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , frame_off ) ) ; insn = emit_insn ( insn ) ; } else { if ( ! CONST_OK_FOR_K ( INTVAL ( frame_off ) ) ) frame_off = force_const_mem ( Pmode , frame_off ) ; insn = emit_insn ( gen_add2_insn ( stack_pointer_rtx , frame_off ) ) ; annotate_constant_pool_refs ( & PATTERN ( insn ) ) ; }

RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;


<s> rtx set_dst ( void ) const { return set_rtx == NULL_RTX ? NULL_RTX : XEXP ( set_rtx , <NUM_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: cahp > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> SDLoc DL ( JT ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ;


<s> const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( MachineBasicBlock * MBB : JTBBs ) { const MCExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ;

if ( isPositionIndependent ( ) || Subtarget -> isROPI ( ) || Subtarget -> isPIP ( ) ) Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( JTISymbol , OutContext ) , OutContext ) ;


<s> virtual bool addPassesToEmitMC ( PassManagerBase & , MCContext * & , raw_ostream & , bool = true ) {


<s> break ; case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetMicro<ISA_LIT> ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>1 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>4 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R6 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ;

getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R2 ( ) ;


<s> static int s390_adjust_priority ( rtx insn ATTRIBUTE_UNUSED , int priority ) { if ( ! INSN_P ( insn ) ) return priority ; if ( s390_tune != PROCESSOR_2084_Z990 && s390_tune != PROCESSOR_2094_Z9_109 ) return priority ; switch ( s390_safe_attr_type ( insn ) ) { case TYPE_FSTOREDF : case TYPE_FSTORESF :


<s> BaseTAI ( TM ) { const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

BaseTAI :: AsmTransCBE = x86_asm_table ;


<s> static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo == <NUM_LIT> ) { return MCDisassembler :: Fail ; }

return DecodeGPRNoX0RegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> case <STR_LIT> : return true ; default : return false ; }


<s> const MCExpr * Expr ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; int64_t Val ; if ( ! Expr -> EvaluateAsAbsolute ( Val ) ) { Error ( S , <STR_LIT> ) ;


<s> static SDValue LowerANY_EXTEND ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDValue In = Op -> getOperand ( <NUM_LIT> ) ;

MVT InVT = In . getSimpleValueType ( ) ;


<s> if ( BitSize & <NUM_LIT> ) ImmVal = Imm . sext ( ( BitSize + <NUM_LIT> ) & ~ <NUM_LIT> ) ; int Cost = <NUM_LIT> ; for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < BitSize ; ShiftVal += <NUM_LIT> ) { APInt Tmp = ImmVal . ashr ( ShiftVal ) . sextOrTrunc ( <NUM_LIT> ) ; int64_t Val = Tmp . getSExtValue ( ) ; Cost += getIntImmCost ( Val ) ;


<s> if ( RegNo > <NUM_LIT> ) return Fail ; return DecodeZPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>ISelDag ( * this ) ) ;


<s> x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == MINUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CODE_LABEL && INSN_DELETED_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) return <NUM_LIT> ; output_addr_const ( file , x ) ; return <NUM_LIT> ;


<s> case MEK_Special : llvm_unreachable ( <STR_LIT> ) ; break ; case MEK_CALL_HI16 : case MEK_CALL_LO16 : case MEK_GOT : case MEK_GOT_CALL : case MEK_GOT_DISP : case MEK_GOT_HI16 : case MEK_GOT_LO16 : case MEK_GOT_OFST : case MEK_GOT_PAGE : case MEK_GPREL : case MEK_HI : case MEK_HIGHER : case MEK_HIGHEST : case MEK_LO : case MEK_NEG : case MEK_PCREL_HI16 : case MEK_PCREL_LO16 : if ( const <ISA_LIT>MCExpr * E = dyn_cast < const <ISA_LIT>MCExpr > ( getSubExpr ( ) ) ) E -> fixELFSymbolsInTLSFixups ( Asm ) ; break ; case MEK_DTPREL : case MEK_DTPREL_HI : case MEK_DTPREL_LO : case MEK_TLSLDM : case MEK_TLSGD : case MEK_GOTTPREL : case MEK_TPREL_HI : case MEK_TPREL_LO : fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ; break ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Reinterpret ; } } if ( <STR_LIT> ( InOp . getNode ( ) ) ) return Reinterpret ; SDValue Mask = getPTrue ( DAG , DL , InVT , <STR_LIT> ) ; SDValue MaskReinterpret = DAG . getNode ( <STR_LIT> , DL , OutVT , Mask ) ;

return DAG . getNode ( <STR_LIT> , DL , OutVT , Reinterpret , MaskReinterpret ) ;


<s> if ( isa < FrameIndexSDNode > ( Src . getNode ( ) ) ) { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned Reg = cast < RegisterSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; EVT VT = Src . getValueType ( ) ;

SDValue Copy ( DAG . getMachineNode ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , VT , Src ) , <NUM_LIT> ) ;


<s> void addToBlocksSet ( MachineBasicBlock * MBB ) { BlockSet . insert ( MBB ) ;


<s> if ( ! maybe_expand_insn ( icode , nops , ops ) ) { error ( <STR_LIT> ) ;

return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ;


<s> const RegisterBankInfo :: InstructionMapping & <ISA_LIT>RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_MUL : case G_UMULH : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_FADD : case G_FSUB : case G_FMUL : case G_FDIV : case G_FABS : case G_FSQRT : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; OperandsMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; break ; } case G_FCONSTANT : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; OperandsMapping = getOperandsMapping ( { FPRValueMapping , nullptr } ) ; break ; } case G_FCMP : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , FPRValueMapping , FPRValueMapping } ) ; break ; } case G_FPEXT : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_FPTRUNC : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_CONSTANT : case G_FRAME_INDEX :


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; if ( Kind == Immediate ) Inst . addOperand ( MCOperand :: createImm ( getImm ( ) / <NUM_LIT> ) ) ;

else Inst . addOperand ( MCOperand :: createExpr ( getExpr ( ) ) ) ;


<s> SDValue TrueVal2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FalseVal2 = Op2 . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC2 = cast < CondCodeSDNode > ( Op2 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue * K1 = isa < ConstantSDNode > ( LHS1 ) ? & LHS1 : isa < ConstantSDNode > ( RHS1 ) ? & RHS1 : NULL ; SDValue * K2 = isa < ConstantSDNode > ( LHS2 ) ? & LHS2 : isa < ConstantSDNode > ( RHS2 ) ? & RHS2 : NULL ; SDValue K2Tmp = isa < ConstantSDNode > ( TrueVal2 ) ? TrueVal2 : FalseVal2 ; SDValue V1Tmp = ( K1 && * K1 == LHS1 ) ? RHS1 : LHS1 ; SDValue V2Tmp = ( K2 && * K2 == LHS2 ) ? RHS2 : LHS2 ; SDValue V2 = ( K2Tmp == TrueVal2 ) ? FalseVal2 : TrueVal2 ; SDValue V2TmpReg = V2Tmp ; if ( V2Tmp -> getOpcode ( ) == <STR_LIT> ) V2TmpReg = V2Tmp -> getOperand ( <NUM_LIT> ) ; if ( ! K1 || ! K2 || * K1 == Op2 || * K2 != K2Tmp || V1Tmp != V2Tmp || V2TmpReg != V2 ) return false ; const SDValue * LowerCheckOp = isLowerSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isLowerSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : NULL ;

const SDValue * UpperCheckOp = isUpperSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isUpperSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : NULL ;


<s> for ( i = REG_P0 ; i <= REG_P5 ; i ++ ) if ( ( regs_ever_live [ i ] && ( is_inthandler || ! call_used_regs [ i ] ) ) || ( i == PIC_OFFSET_TABLE_REGNUM && ( current_function_uses_pic_offset_table || ( TARGET_ID_SHARED_LIBRARY && ! current_function_is_leaf ) ) ) ) return REG_P5 - i + <NUM_LIT> ;


<s> tree m88k_build_va_list ( ) { tree field_reg , field_stk , field_arg , int_ptr_type_node , record ; int_ptr_type_node = build_pointer_type ( integer_type_node ) ; record = make_node ( RECORD_TYPE ) ;


<s> EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcSV , SrcSVOff + SrcOff ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstSV , DstSVOff + DstOff ) ; ++ i ; DstOff += VTSize ; BytesLeft -= VTSize ; }

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ;


<s> } else { DecodeGPR64RegisterClass ( Inst , Rd , Address , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rn , Address , Decoder ) ; } Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return Success ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & RI ;


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) ) return SDValue ( ) ; SDValue In = N -> getOperand ( <NUM_LIT> ) ; if ( ! In . getValueType ( ) . isSimple ( ) ) return SDValue ( ) ; MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; if ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( SVT == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) return SDValue ( ) ; unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ;

unsigned NumPackedZeroBits = Subtarget . hasSSE41 ( ) ? NumPackedSignBits : <NUM_LIT> ;


<s> bool isGatherScatter ( IntrinsicInst * IntInst ) { if ( IntInst == nullptr ) return false ; unsigned IntrinsicID = IntInst -> getIntrinsicID ( ) ; return ( IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> ) ;


<s> return StringSwitch < <STR_LIT> > ( ID ) . Case ( <STR_LIT> , <STR_LIT> :: I32 ) . Case ( <STR_LIT> , <STR_LIT> :: I64 ) . Case ( <STR_LIT> , <STR_LIT> :: F32 ) . Case ( <STR_LIT> , <STR_LIT> :: F64 ) . Case ( <STR_LIT> , <STR_LIT> :: V128 ) . Case ( <STR_LIT> , <STR_LIT> :: Funcref ) . Case ( <STR_LIT> , <STR_LIT> :: Externref ) . Case ( <STR_LIT> , <STR_LIT> :: Void ) . Default ( <STR_LIT> :: Invalid ) ;


<s> for ( int i = <NUM_LIT> ; i < Num ; i ++ ) Tmp += <STR_LIT> + utostr ( Aux [ i ] & <NUM_LIT> ) ; OS . EmitRawText ( <STR_LIT> + Twine ( VarName ) + <STR_LIT> + Tmp ) ;


<s> StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < <NUM_LIT> > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; PreferVectorWidthOverride = Width ; } } unsigned RequiredVectorWidth = UINT32_MAX ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; RequiredVectorWidth = Width ; } }

FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ;


<s> <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>ABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , Align ( <NUM_LIT> ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; setLocInfo ( ArgLocs , Ins ) ; <ISA_LIT>IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; if ( F . isVarArg ( ) ) { ArrayRef < MCPhysReg > ArgRegs = ABI . GetVarArgRegs ( ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; int VaArgOffset ; unsigned RegSize = <NUM_LIT> ; if ( ArgRegs . size ( ) == Idx ) VaArgOffset = alignTo ( CCInfo . getNextStackOffset ( ) , RegSize ) ; else { VaArgOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( CCInfo . getCallingConv ( ) ) - ( int ) ( RegSize * ( ArgRegs . size ( ) - Idx ) ) ; } MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( RegSize , VaArgOffset , true ) ; MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setVarArgsFrameIndex ( FI ) ;

for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += RegSize ) {


<s> unsigned Reg = I64RegDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Src ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Mods ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; }