<s> getBDXAddr12Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ;

uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ;


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; if ( Subtarget -> is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; } else if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; } else { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TII -> getGlobalBaseReg ( F ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ;


<s> if ( ! BT . has ( S ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( S ) ; if ( SC . width ( ) != W || ctlz ( SC ) != W - Z ) continue ; const BitTracker :: BitValue & S0 = SC [ <NUM_LIT> ] ; if ( S0 . Type != BitTracker :: BitValue :: Ref || S0 . RefI . Reg != SrcR ) continue ; unsigned P = S0 . RefI . Pos ; if ( Pos <= P && ( Pos + W - Z ) != P ) continue ; if ( P < Pos && ( P + Z ) != Pos ) continue ; if ( std :: min ( P , Pos ) != <NUM_LIT> && std :: min ( P , Pos ) != <NUM_LIT> ) continue ; unsigned I ; for ( I = <NUM_LIT> ; I < Z ; ++ I ) { const BitTracker :: BitValue & V = SC [ I ] ; if ( V . Type != BitTracker :: BitValue :: Ref ) break ; if ( V . RefI . Reg != SrcR || V . RefI . Pos != P + I ) break ; } if ( I != Z ) continue ; if ( MaxBitSplit . getNumOccurrences ( ) ) CountBitSplit ++ ; MachineInstr * DefS = MRI . getVRegDef ( S ) ; assert ( DefS != nullptr ) ; DebugLoc DL = DefS -> getDebugLoc ( ) ; MachineBasicBlock & B = * DefS -> getParent ( ) ; auto At = DefS -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( DefS ) ; if ( MRI . getRegClass ( SrcR ) -> getID ( ) == <STR_LIT> ) SrcSR = ( std :: min ( Pos , P ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( ! validateReg ( { SrcR , SrcSR } , <STR_LIT> , <NUM_LIT> ) ) continue ; unsigned ImmOp = Pos <= P ? W - Z : Z ; unsigned NewR = <NUM_LIT> ; for ( MachineInstr * In : NewMIs ) { if ( In -> getOpcode ( ) != <STR_LIT> ) continue ; MachineOperand & Op1 = In -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getReg ( ) != SrcR || Op1 . getSubReg ( ) != SrcSR ) continue ; if ( In -> getOperand ( <NUM_LIT> ) . getImm ( ) != ImmOp ) continue ; MachineOperand & Op0 = In -> getOperand ( <NUM_LIT> ) ; MachineInstr * DefI = MRI . getVRegDef ( Op0 . getReg ( ) ) ; assert ( DefI != nullptr ) ; if ( ! MDT . dominates ( DefI , & * At ) ) continue ; assert ( Op0 . getSubReg ( ) == <NUM_LIT> ) ;


<s> bool PredValid = true ; do { -- I ; MachineInstr * MI = & * I ; if ( PredValid && HII -> isPredicated ( * MI ) ) { if ( MI -> readsRegister ( PredR ) && ( Cond != HII -> isPredicatedTrue ( * MI ) ) ) continue ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; RegisterRef RR = Op ;


<s> if ( TARGET_AVX2 && GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> ) ; else if ( TARGET_AVX && ( d -> vmode == V8SFmode || d -> vmode == V4DFmode ) ) ; else return false ; nelt = d -> nelt ; if ( d -> perm [ <NUM_LIT> ] != <NUM_LIT> && d -> perm [ <NUM_LIT> ] != nelt / <NUM_LIT> ) return false ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) if ( d -> perm [ i ] != d -> perm [ <NUM_LIT> ] + i / <NUM_LIT> || d -> perm [ i + <NUM_LIT> ] != d -> perm [ <NUM_LIT> ] + i / <NUM_LIT> + nelt ) return false ; if ( d -> testing_p ) return true ; switch ( d -> vmode ) {


<s> case PROCESSOR_SUPERSPARC : return <NUM_LIT> ; case PROCESSOR_HYPERSPARC : case PROCESSOR_SPARCLITE86X : case PROCESSOR_V9 : case PROCESSOR_NIAGARA4 : case PROCESSOR_NIAGARA7 : return <NUM_LIT> ; case PROCESSOR_NIAGARA : case PROCESSOR_NIAGARA2 : case PROCESSOR_NIAGARA3 : default : return <NUM_LIT> ; }


<s> if ( ! MRI -> getRegClassOrNull ( SrcReg ) ) MRI -> setRegClass ( SrcReg , TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ) ; I . eraseFromParent ( ) ; return true ; } const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ; if ( RC && ! RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ) return false ; if ( Src . isUndef ( ) ) { const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ; if ( SrcRC && ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; } return true ; } for ( const MachineOperand & MO : I . operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , * MRI ) ;


<s> Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; Ptr = N2 ; VAddr = N3 ; Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , <STR_LIT> ) ; return ; } VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; Ptr = N0 ; Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , <STR_LIT> ) ; return ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; Ptr = N0 ; VAddr = N1 ;

Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> bool SelectAddrMode2Base ( SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) {

return SelectAddrMode2Worker ( N , Base , Offset , Opc ) == AM2_BASE ;


<s> void addKillWaitBracket ( BlockWaitcntBrackets * Bracket ) {

KillWaitBrackets . push_back ( llvm :: make_unique < BlockWaitcntBrackets > ( * Bracket ) ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitLocal ( ArrayRef < MVT > Types ) { Streamer . EmitULEB128IntValue ( Types . size ( ) ) ;

for ( MVT Type : Types ) Streamer . EmitIntValue ( int64_t ( <STR_LIT> ( Type ) ) , <NUM_LIT> ) ;


<s> Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UseDataRegionDirectives = false ; WeakRefDirective = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> addPass ( createSNITCHFrepLoopsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ; addPass ( create<ISA_LIT>CleanupVSETVLIPass ( ) ) ; addPass ( createPULPHardwareLoops ( ) ) ; }


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {

addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> if ( ReadOnlySection . getAlignment ( ) < <NUM_LIT> ) ReadOnlySection . setAlignment ( <NUM_LIT> ) ; SmallString < <NUM_LIT> > KernelName ; getNameWithPrefix ( KernelName , & MF -> getFunction ( ) ) ; getTargetStreamer ( ) -> EmitAmdhsaKernelDescriptor ( * getSTI ( ) , KernelName , getAmdhsaKernelDescriptor ( * MF , CurrentProgramInfo ) , CurrentProgramInfo . NumVGPRsForWavesPerEU , CurrentProgramInfo . NumSGPRsForWavesPerEU - IsaInfo :: getNumExtraSGPRs ( getSTI ( ) , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed ) , CurrentProgramInfo . VCCUsed , CurrentProgramInfo . FlatUsed , hasXNACK ( * getSTI ( ) ) ) ;


<s> B2BB [ B ] = & BB ; } for ( Block * B : R . Blocks ) { const BasicBlock * BB = B2BB [ B ] ; for ( const BasicBlock * Successor : successors ( BB ) ) B -> AddBranchTo ( BB2B [ Successor ] , nullptr , nullptr ) ; } R . Calculate ( BB2B [ & F . getEntryBlock ( ) ] ) ; return false ;


<s> break ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; } if ( Res . getNode ( ) ) Results . push_back ( Res ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) return ! hasFP32Denormals ( DAG . getMachineFunction ( ) ) ;


<s> ret = emit_library_call_value ( libcall , NULL_RTX , LCT_CONST , dmode , <NUM_LIT> , operands [ <NUM_LIT> ] , smode ) ; equiv = gen_rtx_fmt_e ( code , dmode , operands [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : ret = emit_library_call_value ( libcall , NULL_RTX , LCT_CONST , dmode , <NUM_LIT> , operands [ <NUM_LIT> ] , smode , operands [ <NUM_LIT> ] , smode ) ; equiv = gen_rtx_fmt_ee ( code , dmode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } insns = get_insns ( ) ;


<s> const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , false , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , false , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , true , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , true , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , false , true , <STR_LIT> ) ; case <STR_LIT> :

return LowerFPToInt ( MI , DL , BB , TII , true , false , true , <STR_LIT> ) ;


<s> if ( suffix == 'w' ) return XFmode ;


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm , JITCodeEmitter & mce ) : MachineFunctionPass ( ID ) , JTI ( <NUM_LIT> ) , II ( ( const <ISA_LIT>InstrInfo * ) tm . getInstrInfo ( ) ) , TD ( tm . getTargetData ( ) ) , TM ( tm ) , MCE ( mce ) , MCPEs ( <NUM_LIT> ) , MJTEs ( <NUM_LIT> ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , IsThumb ( false ) {


<s> bool <ISA_LIT>AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) {


<s> void <ISA_LIT>SEInstrInfo :: expandExtractElementF64 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , bool FP64 ) const { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc dl = I -> getDebugLoc ( ) ; assert ( N < <NUM_LIT> && <STR_LIT> ) ; unsigned SubIdx = N ? <STR_LIT> : <STR_LIT> ; unsigned SubReg = getRegisterInfo ( ) . getSubReg ( SrcReg , SubIdx ) ;


<s> default : report_fatal_error ( <STR_LIT> ) ; case ADDRESS_SPACE_GLOBAL : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_CONST : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; case ADDRESS_SPACE_LOCAL : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ; } return CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Src ) ; } else { if ( SrcAddrSpace != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ;


<s> MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned SrcReg = Compare -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg2 = ( Compare -> getOperand ( <NUM_LIT> ) . isReg ( ) ? Compare -> getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; MachineOperand Target ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) . addOperand ( Compare -> getOperand ( <NUM_LIT> ) ) . addOperand ( Compare -> getOperand ( <NUM_LIT> ) ) . addOperand ( CCMask ) . addOperand ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; MBBI = Compare ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) {

MBBI -> clearRegisterKills ( SrcReg , TRI ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) {


<s> return Imm >= - <NUM_LIT> && Imm <= <NUM_LIT> ;


<s> bool Result = ParseRegister ( RegNo , StartLoc , EndLoc , true ) ;

bool PendingErrors = getParser ( ) . hasPendingError ( ) ;


<s> __ev64_opaque__ t ; t = __ev_mwhumi ( a , b ) ;


<s> bool UseHvx = false ; for ( unsigned F : { ExtensionHVX , ExtensionHVX64B , ExtensionHVX128B } ) { if ( ! FB . test ( F ) ) continue ; UseHvx = true ; break ; } bool HasHvxVer = false ; for ( unsigned F : { ExtensionHVXV60 , ExtensionHVXV62 , ExtensionHVXV65 , ExtensionHVXV66 , ExtensionHVXV67 , ExtensionHVXV68 , ExtensionHVXV69 } ) { if ( ! FB . test ( F ) ) continue ; HasHvxVer = true ; UseHvx = true ; break ; } if ( ! UseHvx || HasHvxVer ) return FB ; switch ( CpuArch ) { case ArchV69 : FB . set ( ExtensionHVXV69 ) ; LLVM_FALLTHROUGH ; case ArchV68 : FB . set ( ExtensionHVXV68 ) ; LLVM_FALLTHROUGH ; case ArchV67 : FB . set ( ExtensionHVXV67 ) ; LLVM_FALLTHROUGH ; case ArchV66 : FB . set ( ExtensionHVXV66 ) ; LLVM_FALLTHROUGH ; case ArchV65 : FB . set ( ExtensionHVXV65 ) ; LLVM_FALLTHROUGH ; case ArchV62 : FB . set ( ExtensionHVXV62 ) ; LLVM_FALLTHROUGH ; case ArchV60 :


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ; static const TransPair TableZRF [ ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ; const TransPair * TablePtr ; switch ( Kind ) { case LongRegisterKind :: ARF :


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadPhis ; if ( isDead ( MI , DeadPhis ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; MachineRegisterInfo :: use_iterator nextI ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) { nextI = std :: next ( I ) ; MachineOperand & Use = * I ; MachineInstr * UseMI = I -> getParent ( ) ; if ( UseMI == MI ) continue ; if ( Use . isDebug ( ) ) UseMI -> getOperand ( <NUM_LIT> ) . setReg ( <NUM_LIT> ) ; } } MI -> eraseFromParent ( ) ;

for ( unsigned i = <NUM_LIT> ; i < DeadPhis . size ( ) ; ++ i ) DeadPhis [ i ] -> eraseFromParent ( ) ;


<s> SDValue V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Idx128 = Op . getOperand ( <NUM_LIT> ) ; auto * CIdx = dyn_cast < ConstantSDNode > ( Idx128 ) ; if ( CIdx && ( CIdx -> getZExtValue ( ) <= <NUM_LIT> ) ) { SDValue CI = DAG . getTargetConstant ( CIdx -> getZExtValue ( ) , DL , <STR_LIT> ) ; SDNode * DUPQ = DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , V , CI ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( DUPQ , <NUM_LIT> ) ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue SplatOne = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One ) ;

SDValue SV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One ) ;


<s> bool avoiding_indexed_address_p ( machine_mode mode ) { unsigned int msize = GET_MODE_SIZE ( mode ) ; if ( msize > <NUM_LIT> ) return msize != <NUM_LIT> ; return ( TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P ( mode ) ) ;


<s> static SDValue EmitCMP ( SDValue & LHS , SDValue & RHS , SDValue & TargetCC , <STR_LIT> CC , DebugLoc dl , SelectionDAG & DAG ) {


<s> static int64_t getStoreOffset ( const MachineInstr * MI ) { unsigned OpC = MI -> getOpcode ( ) ; assert ( <ISA_LIT>StoreWidening :: handledStoreType ( MI ) && <STR_LIT> ) ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm ( ) ; } }


<s> int ia64_load_pair_ok ( rtx dst , rtx src ) { if ( GET_CODE ( dst ) != REG || ! ( FP_REGNO_P ( REGNO ( dst ) ) && FP_REGNO_P ( REGNO ( dst ) + <NUM_LIT> ) ) ) return <NUM_LIT> ; if ( GET_CODE ( src ) != MEM || MEM_VOLATILE_P ( src ) ) return <NUM_LIT> ; switch ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) ) { case REG : case POST_INC : break ; case POST_DEC : return <NUM_LIT> ; case POST_MODIFY : { rtx adjust = XEXP ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( adjust ) != CONST_INT || INTVAL ( adjust ) != GET_MODE_SIZE ( GET_MODE ( src ) ) ) return <NUM_LIT> ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( unsigned Kind ) const {


<s> int64_t SVal = int64_t ( Value ) ; if ( SVal < Min || SVal > Max ) { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> + Twine ( SVal ) + <STR_LIT> + Twine ( Min ) + <STR_LIT> + Twine ( Max ) + <STR_LIT> ) ; return false ; } return true ; } ; auto handlePCRelFixupValue = [ & ] ( unsigned W ) -> uint64_t { if ( Value % <NUM_LIT> != <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( ! checkFixupInRange ( minIntN ( W ) * <NUM_LIT> , maxIntN ( W ) * <NUM_LIT> ) ) return <NUM_LIT> ; return ( int64_t ) Value / <NUM_LIT> ; } ; switch ( unsigned ( Kind ) ) { case <STR_LIT> : return handlePCRelFixupValue ( <NUM_LIT> ) ; case <STR_LIT> : return handlePCRelFixupValue ( <NUM_LIT> ) ; case <STR_LIT> : return handlePCRelFixupValue ( <NUM_LIT> ) ; case <STR_LIT> : return handlePCRelFixupValue ( <NUM_LIT> ) ; case <STR_LIT> : if ( ! checkFixupInRange ( <NUM_LIT> , maxUIntN ( <NUM_LIT> ) ) ) return <NUM_LIT> ; return Value ; case <STR_LIT> : { if ( ! checkFixupInRange ( minIntN ( <NUM_LIT> ) , maxIntN ( <NUM_LIT> ) ) ) return <NUM_LIT> ; uint64_t DLo = Value & <NUM_LIT> ; uint64_t DHi = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; return ( DLo << <NUM_LIT> ) | DHi ; }


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isImm ( ) ) {

OS << formatHex ( ( Op . getImm ( ) << <NUM_LIT> ) | <NUM_LIT> ) ;


<s> if ( VM1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VM1 . logBase2 ( ) , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; } APInt VP1 = Value + <NUM_LIT> ; if ( VP1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VP1 . logBase2 ( ) , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; } } else { APInt VNP1 = - Value + <NUM_LIT> ; if ( VNP1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VNP1 . logBase2 ( ) , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , ShiftedVal ) ; } APInt VNM1 = - Value - <NUM_LIT> ; if ( VNM1 . isPowerOf2 ( ) ) { SDValue ShiftedVal = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( VNM1 . logBase2 ( ) , DL , <STR_LIT> ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , ShiftedVal , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Add ) ; } } } return SDValue ( ) ;


<s> getVPermMask ( cast < ShuffleVectorSDNode > ( Op ) , Bytes ) ; int First ; if ( ! getShuffleInput ( Bytes , Index * BytesPerElement , BytesPerElement , First ) ) break ; if ( First < <NUM_LIT> ) return DAG . getUNDEF ( ResVT ) ; unsigned Byte = unsigned ( First ) % Bytes . size ( ) ; if ( Byte % BytesPerElement != <NUM_LIT> ) break ; Index = Byte / BytesPerElement ; Op = Op . getOperand ( unsigned ( First ) / Bytes . size ( ) ) ; Force = true ; } else if ( Opcode == <STR_LIT> && canTreatAsByteVector ( Op . getValueType ( ) ) ) { EVT OpVT = Op . getValueType ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( OpBytesPerElement < BytesPerElement ) break ; unsigned End = ( Index + <NUM_LIT> ) * BytesPerElement ; if ( End % OpBytesPerElement != <NUM_LIT> ) break ; Op = Op . getOperand ( End / OpBytesPerElement - <NUM_LIT> ) ; if ( ! Op . getValueType ( ) . isInteger ( ) ) { EVT VT = <STR_LIT> ( Op . getValueSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; } EVT VT = <STR_LIT> ( ResVT . getSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; if ( VT != ResVT ) { DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , ResVT , Op ) ; } return Op ; } else if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && canTreatAsByteVector ( Op . getValueType ( ) ) && canTreatAsByteVector ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { EVT ExtVT = Op . getValueType ( ) ; EVT OpVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned ExtBytesPerElement = ExtVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned Byte = Index * BytesPerElement ; unsigned SubByte = Byte % ExtBytesPerElement ; unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement ; if ( SubByte < MinSubByte || SubByte + BytesPerElement > ExtBytesPerElement ) break ; Byte = Byte / ExtBytesPerElement * OpBytesPerElement ; Byte += SubByte - MinSubByte ; if ( Byte % BytesPerElement != <NUM_LIT> ) break ;


<s> const auto * LWEOp = TII . getNamedOperand ( * CI . I , <STR_LIT> :: lwe ) ; if ( ( TFEOp && TFEOp -> getImm ( ) ) || ( LWEOp && LWEOp -> getImm ( ) ) ) return false ; unsigned OperandsToMatch [ ] = { <STR_LIT> :: glc , <STR_LIT> :: slc , <STR_LIT> :: d16 , <STR_LIT> :: unorm , <STR_LIT> :: da , <STR_LIT> :: r128 , <STR_LIT> :: a16 , <STR_LIT> :: dlc } ; for ( auto op : OperandsToMatch ) {

int Idx = <STR_LIT> ( CI . I -> getOpcode ( ) , op ) ;


<s> int s390_arg_frame_offset ( ) { struct s390_frame frame ; s390_frame_info ( & frame ) ; return frame . frame_size + STACK_POINTER_OFFSET ;


<s> ExternalSucc = Succ ; } } for ( auto & TI : Exit -> terminators ( ) ) { for ( auto & UI : TI . uses ( ) ) { if ( UI . isMBB ( ) ) { auto Target = UI . getMBB ( ) ; if ( Target != InternalSucc && Target != ExternalSucc ) { UI . setMBB ( ExternalSucc ) ; }


<s> assert ( <ISA_LIT>MCInstrInfo :: isExtendable ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: isExtended ( MCII , MCI ) ) ; MCOperand & exOp = MCI . getOperand ( <ISA_LIT>MCInstrInfo :: getExtendableOp ( MCII , MCI ) ) ; int64_t Value ; if ( exOp . getExpr ( ) -> evaluateAsAbsolute ( Value ) ) { unsigned Shift = <ISA_LIT>MCInstrInfo :: getExtentAlignment ( MCII , MCI ) ; exOp . setExpr ( MCConstantExpr :: create ( ( Value & <NUM_LIT> ) << Shift , Context ) ) ;


<s> int fr30_const_double_is_zero ( rtx operand ) {

if ( operand == NULL || GET_CODE ( operand ) != CONST_DOUBLE ) return <NUM_LIT> ;


<s> static SDValue getGatherNode ( unsigned Opc , SDValue Op , SelectionDAG & DAG , SDValue Src , SDValue Mask , SDValue Base , SDValue Index , SDValue ScaleOp , SDValue Chain , const <ISA_LIT>Subtarget & Subtarget ) { MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; auto * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , VT . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ;

if ( Src . isUndef ( ) || <STR_LIT> ( VMask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ;


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetLowering :: getSubtarget ( ) const {

return static_cast < const <ISA_LIT>Subtarget * > ( Subtarget ) ;


<s> unsigned Align = MF . getFrameInfo ( ) -> getObjectAlignment ( FI ) ; assert ( ( - ( Offset + StackSize ) ) % Align == <NUM_LIT> ) ; Align = <NUM_LIT> ; return Offset + StackSize ; } } else {

if ( ! hasFP ( MF ) ) return Offset + StackSize ;


<s> static DecodeStatus DecodeBRNInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned disp15 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned n_0 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned n_1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned n = ( n_0 << <NUM_LIT> ) | ( n_1 << <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ;

Inst . addOperand ( MCOperand :: createImm ( disp15 ) ) ;


<s> assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerAndToBT ( Op0 , CC , dl , DAG ) ) return NewSetCC ; } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; return getSETCC ( CCode , Op0 . getOperand ( <NUM_LIT> ) , dl , DAG ) ; } } bool IsFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ;

<STR_LIT> <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , dl , IsFP , Op0 , Op1 , DAG ) ;


<s> return ( int16x4_t ) __builtin_neon_vget_lowv8hi ( __a ) ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) {


<s> if ( Subtarget -> isTargetNaCl ( ) ) return true ; return false ;


<s> break ; case <NUM_LIT> : print_operand ( file , index , 'T' ) ; fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : print_operand ( file , index , 'S' ) ; fputs ( <STR_LIT> , file ) ; break ; } } else { print_operand_address ( file , XEXP ( addr , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ; print_operand_address ( file , XEXP ( addr , <NUM_LIT> ) ) ; } fprintf ( file , <STR_LIT> ) ; break ; case CONST_INT : { int n = INTVAL ( addr ) ; if ( TARGET_H8300 ) n = ( int ) ( short ) n ; fprintf ( file , <STR_LIT> , n ) ; break ; }


<s> avr_need_clear_bss_p = true ; output_section_asm_op ( data ) ;


<s> if ( reg_classes_intersect_p ( rclass , CR_REGS ) ) { switch ( GET_MODE ( x ) ) { case E_QImode : newclass = HL_REGS ; break ; default : break ; } } else if ( newclass == QI_REGS && GET_MODE_SIZE ( GET_MODE ( x ) ) > <NUM_LIT> ) newclass = SI_REGS ;

else if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > <NUM_LIT> && ! reg_class_subset_p ( R03_REGS , rclass ) ) newclass = DI_REGS ;


<s> set_optab_libfunc ( umod_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( and_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( ior_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( xor_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( one_cmpl_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( add_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , SFmode , <STR_LIT> ) ; set_optab_libfunc ( add_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( sub_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( smul_optab , DFmode , <STR_LIT> ) ; set_optab_libfunc ( sdiv_optab , DFmode , <STR_LIT> ) ; set_conv_libfunc ( sext_optab , DFmode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( trunc_optab , SFmode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , SFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , SImode , DFmode , <STR_LIT> ) ; set_conv_libfunc ( sfix_optab , DImode , DFmode , <STR_LIT> ) ;

set_conv_libfunc ( ufix_optab , SImode , SFmode , <STR_LIT> ) ;


<s> const TargetIntrinsicInfo * getIntrinsicInfo ( ) const { return & IntrinsicInfo ;


<s> } } if ( Single . getNode ( ) && ( Count > <NUM_LIT> || Single . getOpcode ( ) == <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Single ) ; if ( VT == <STR_LIT> ) return joinDwords ( DAG , DL , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; if ( VT == <STR_LIT> ) return buildMergeScalars ( DAG , DL , VT , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; if ( VT == <STR_LIT> ) { SDValue Op01 = buildMergeScalars ( DAG , DL , VT , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; SDValue Op23 = buildMergeScalars ( DAG , DL , VT , Elems [ <NUM_LIT> ] , Elems [ <NUM_LIT> ] ) ; if ( Op01 . isUndef ( ) ) Op01 = Op23 ; else if ( Op23 . isUndef ( ) ) Op23 = Op01 ; if ( Op01 . getOpcode ( ) == <STR_LIT> && Op01 == Op23 ) return Op01 ; Op01 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op01 ) ; Op23 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op23 ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op01 , Op23 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; } SmallVector < SDValue , <STR_LIT> > Constants ( NumElements , SDValue ( ) ) ; SmallVector < bool , <STR_LIT> > Done ( NumElements , false ) ; unsigned NumConstants = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumElements ; ++ I ) { SDValue Elem = Elems [ I ] ; if ( Elem . getOpcode ( ) == <STR_LIT> || Elem . getOpcode ( ) == <STR_LIT> ) {


<s> qword q ; int i [ <NUM_LIT> ] ; } x ; x . q = q ; return ( x . i [ <NUM_LIT> ] ) ;


<s> return ~ __X & ( __X - <NUM_LIT> ) ;


<s> unsigned CPURegSize = <STR_LIT> . getSize ( ) ; unsigned FGR32RegSize = <STR_LIT> . getSize ( ) ; unsigned AFGR64RegSize = <STR_LIT> . getSize ( ) ; bool HasAFGR64Reg = false ; unsigned CSFPRegsSize = <NUM_LIT> ; for ( const auto & I : CSI ) { unsigned Reg = I . getReg ( ) ; unsigned RegNum = TRI -> getEncodingValue ( Reg ) ; if ( <STR_LIT> . contains ( Reg ) ) {


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ;


<s> SDLoc DL ( N ) ; SDValue Gl = getTargetNode ( N , Ty , DAG , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Gl ) ;


<s> Op -> VectorList . NumElements = NumElements ; Op -> VectorList . ElementKind = ElementKind ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> void setSinglePath ( bool convert = true ) { SinglePathConvert = convert ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; } ResultReg = createResultReg ( RC ) ;

addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , AM ) ;


<s> assert ( I != MBB -> end ( ) && <STR_LIT> ) ; Offset += TII -> getInstSizeInBytes ( * I ) ; }


<s> bool hasVLX ( ) const { return HasVLX ;


<s> if ( ( ( class1 == FP_REGS ) != ( class2 == FP_REGS ) ) && ( ( TARGET_FLOATXX && ! ISA_HAS_MXHC1 ) || TARGET_O32_FP64A_ABI ) && GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return true ;


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Small ) { SDValue Small = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( DAG . getDataLayout ( ) ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Small ) ) ; } else { uint8_t OpFlagHi = <STR_LIT> ; uint8_t OpFlagLo = <STR_LIT> ; SDValue Hi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( DAG . getDataLayout ( ) ) , OpFlagHi ) ; SDValue Lo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( DAG . getDataLayout ( ) ) , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Lo ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasVOP3PInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAClampVOPC ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { AS = <STR_LIT> ( TT ) ;

initializeSubtargetDependencies ( TT , GPU , FS ) ;


<s> static void microblaze_elf_asm_destructor ( rtx symbol , int priority ) {

microblaze_elf_asm_cdtor ( symbol , priority , false ) ;


<s> if ( Opc == <STR_LIT> ) continue ; if ( Opc != <STR_LIT> ) { if ( InsertIndices . size ( ) > <NUM_LIT> ) return SDValue ( ) ; InsertIndices . push_back ( i ) ; continue ; } SDValue ExtractedFromVec = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; SDValue ExtIdx = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( ExtractedFromVec . getValueType ( ) != VT ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( ExtIdx ) ) return SDValue ( ) ; if ( VecIn1 . getNode ( ) == <NUM_LIT> ) VecIn1 = ExtractedFromVec ; else if ( VecIn1 != ExtractedFromVec ) { if ( VecIn2 . getNode ( ) == <NUM_LIT> ) VecIn2 = ExtractedFromVec ; else if ( VecIn2 != ExtractedFromVec ) return SDValue ( ) ; } unsigned Idx = cast < ConstantSDNode > ( ExtIdx ) -> getZExtValue ( ) ; if ( ExtractedFromVec == VecIn1 ) Mask [ i ] = Idx ; else if ( ExtractedFromVec == VecIn2 ) Mask [ i ] = Idx + NumElems ; } if ( VecIn1 . getNode ( ) == <NUM_LIT> ) return SDValue ( ) ; VecIn2 = VecIn2 . getNode ( ) ? VecIn2 : DAG . getUNDEF ( VT ) ; SDValue NV = DAG . getVectorShuffle ( VT , DL , VecIn1 , VecIn2 , & Mask [ <NUM_LIT> ] ) ; for ( unsigned i = <NUM_LIT> , e = InsertIndices . size ( ) ; i != e ; ++ i ) { unsigned Idx = InsertIndices [ i ] ; NV = DAG . getNode ( <STR_LIT> , DL , VT , NV , Op . getOperand ( Idx ) , DAG . getIntPtrConstant ( Idx ) ) ;


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { emitSPAdjustment ( MF , MBB , MBBI , NumBytes , None ) ; }

emitEpilogueInsns ( MF , MBB , MBBI , NumBytes , true ) ;


<s> if ( DecodeRegListOperand16 ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;

Inst . addOperand ( MCOperand :: createImm ( Offset << <NUM_LIT> ) ) ;


<s> if ( Idx == - <NUM_LIT> ) return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; return LT . first * NEONShuffleTbl [ Idx ] . Cost ; } if ( Kind == TTI :: SK_Alternate ) { static const CostTblEntry < <STR_LIT> > NEONAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ;

std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Tp ) ;


<s> const auto * DDTy = cast < DIDerivedType > ( Element ) ; BTFMember . NameOff = BDebug . addString ( DDTy -> getName ( ) ) ; if ( HasBitField ) { uint8_t BitFieldSize = DDTy -> isBitField ( ) ? DDTy -> getSizeInBits ( ) : <NUM_LIT> ; BTFMember . Offset = BitFieldSize << <NUM_LIT> | DDTy -> getOffsetInBits ( ) ; } else { BTFMember . Offset = DDTy -> getOffsetInBits ( ) ;


<s> if ( ! Index . getNode ( ) ) Index = CurDAG -> getRegister ( <NUM_LIT> , VT ) ;


<s> bool <ISA_LIT>AsmPrinter :: doInitialization ( Module & M ) { SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( OutContext , & TM ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ;

if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ;


<s> static unsigned getAddrSpaceFromEPtrKind ( unsigned Kind ) { Kind = Kind & ADDR_SPACE ; assert ( Kind >= <NUM_LIT> ) ;


<s> if ( Bytes . size ( ) < <NUM_LIT> ) break ; const uint32_t DW = eatBytes < uint32_t > ( Bytes ) ; Res = tryDecodeInst ( DecoderTableVI32 , MI , DW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTable<ISA_LIT>32 , MI , DW , Address ) ; if ( Res ) break ; if ( Bytes . size ( ) < <NUM_LIT> ) break ; const uint64_t QW = ( ( uint64_t ) eatBytes < uint32_t > ( Bytes ) << <NUM_LIT> ) | DW ; Res = tryDecodeInst ( DecoderTableVI64 , MI , QW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTable<ISA_LIT>64 , MI , QW , Address ) ; } while ( false ) ; Size = Res ? ( MaxInstBytesNum - Bytes . size ( ) ) : <NUM_LIT> ;


<s> Type * const Ty = V -> getType ( ) ; Module * M = B . GetInsertBlock ( ) -> getModule ( ) ; Function * UpdateDPP = <STR_LIT> ( M , <STR_LIT> , Ty ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; Idx ++ ) { V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: ROW_SHR0 | <NUM_LIT> << Idx ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; } if ( ST -> hasDPPBroadcasts ( ) ) { V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: BCAST15 ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: BCAST31 ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; } else { assert ( ST -> hasPermLaneX16 ( ) ) ; Value * const PermX = B . CreateIntrinsic ( <STR_LIT> , { } , { V , V , B . getInt32 ( - <NUM_LIT> ) , B . getInt32 ( - <NUM_LIT> ) , B . getFalse ( ) , B . getFalse ( ) } ) ;

V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , PermX , B . getInt32 ( DPP :: QUAD_PERM_ID ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ;


<s> static DecodeStatus readInstruction32 ( ArrayRef < uint8_t > Bytes , uint64_t Address , uint64_t & Size , uint64_t & Insn , bool IsBigEndian , bool IsMicro<ISA_LIT> ) { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } if ( IsBigEndian ) { Insn = ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; } else { Insn = ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ;

case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ;


<s> return getSubExpr ( ) -> FindAssociatedSection ( ) ;


<s> if ( flags == MASK_MIPS16 ) return <STR_LIT> ; return <STR_LIT> ;


<s> unsigned int i , nelt_v8 , nelt_v16 , nelt_mode ; rtx dst , addr , mem ; rtx val_vec , reg ; machine_mode mode ; unsigned int offset = <NUM_LIT> ; gcc_assert ( ( align & <NUM_LIT> ) == <NUM_LIT> ) ; nelt_v8 = GET_MODE_NUNITS ( V8QImode ) ; nelt_v16 = GET_MODE_NUNITS ( V16QImode ) ; if ( length >= nelt_v16 && unaligned_access && ! BYTES_BIG_ENDIAN ) mode = V16QImode ; else mode = V8QImode ; nelt_mode = GET_MODE_NUNITS ( mode ) ; gcc_assert ( length >= nelt_mode ) ; if ( ! arm_block_set_vect_profit_p ( length , align , mode ) ) return false ; dst = copy_addr_to_reg ( XEXP ( dstbase , <NUM_LIT> ) ) ; reg = gen_reg_rtx ( mode ) ; val_vec = gen_const_vec_duplicate ( mode , gen_int_mode ( value , QImode ) ) ; emit_move_insn ( reg , val_vec ) ; i = <NUM_LIT> ; if ( mode == V16QImode ) { mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; emit_insn ( gen_movmisalignv16qi ( mem , reg ) ) ; i += nelt_mode ; if ( i + nelt_v8 < length && i + nelt_v16 > length ) { emit_insn ( gen_add2_insn ( dst , GEN_INT ( length - nelt_mode ) ) ) ; offset += length - nelt_mode ; mem = adjust_automodify_address ( dstbase , mode , dst , offset ) ; if ( ( length & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT * <NUM_LIT> ) ; else if ( ( length & <NUM_LIT> ) == <NUM_LIT> ) set_mem_align ( mem , BITS_PER_UNIT * <NUM_LIT> ) ; else set_mem_align ( mem , BITS_PER_UNIT ) ;


<s> CheriLoopPointerDecanonicalize ( ) : FunctionPass ( ID ) {


<s> addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ;


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectStore ( Instruction * I ) { EVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ;

if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM ) ) return false ;


<s> } assert ( ( ! MI -> isCall ( ) && ! MI -> isReturn ( ) ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; unsigned Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) || IsRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( ) ) { if ( IsRegInSet ( RegDefs , Reg ) ) return true ; } }


<s> rtx_code_label * label = dyn_cast < rtx_code_label * > ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( label && label -> deleted ( ) ) return true ;


<s> SDValue MinRHS = Op1 . getOperand ( <NUM_LIT> ) ; if ( MinLHS == Op0 ) SubusRHS = MinRHS ; else if ( MinRHS == Op0 ) SubusRHS = MinLHS ; else return SDValue ( ) ; } else return SDValue ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , SubusLHS , SubusRHS ) ; KnownBits Known ; DAG . computeKnownBits ( SubusLHS , Known ) ; unsigned NumZeros = Known . countMinLeadingZeros ( ) ; if ( ( VT == <STR_LIT> && NumZeros < <NUM_LIT> ) || NumZeros < <NUM_LIT> ) return SDValue ( ) ; EVT ExtType = SubusLHS . getValueType ( ) ; EVT ShrinkedType ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) ShrinkedType = <STR_LIT> ; else ShrinkedType = NumZeros >= <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;

SDValue SaturationConst = DAG . getConstant ( APInt :: getLowBitsSet ( ExtType . getScalarSizeInBits ( ) , ShrinkedType . getScalarSizeInBits ( ) ) , SDLoc ( SubusLHS ) , ExtType ) ;


<s> for ( MachineBasicBlock :: iterator E = MBB . end ( ) ; I != E ; ++ I ) { if ( IsTrivialInst ( I ) ) continue ; if ( AluInstCount >= MaxFetchInst ) break ; if ( ( IsTex && ! TII -> usesTextureCache ( I ) ) || ( ! IsTex && ! TII -> usesVertexCache ( I ) ) ) break ;

if ( ! isCompatibleWithClause ( I , DstRegs ) ) break ;


<s> if ( VT . getVectorElementType ( ) == <STR_LIT> && ! static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasBF16 ( ) ) return SDValue ( ) ; if ( IsFixedLength ) { assert ( Subtarget -> useSVEForFixedLengthVectors ( ) && <STR_LIT> ) ; IndexVT = getContainerForFixedLengthVector ( DAG , IndexVT ) ; MemVT = IndexVT . changeVectorElementType ( MemVT . getVectorElementType ( ) ) ; InputVT = DAG . getValueType ( MemVT . changeTypeToInteger ( ) ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , StoreVal ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , StoreVal ) ; StoreVal = convertToScalableVector ( DAG , IndexVT , StoreVal ) ; Mask = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , Mask ) ; } else if ( VT . isFloatingPoint ( ) ) { EVT StoreValVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; StoreVal = getSVESafeBitCast ( StoreValVT , StoreVal , DAG ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; } if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ;

unsigned Opcode = getScatterVecOpcode ( IsScaled , IsSigned , NeedsExtend ) ;


<s> Register <ISA_LIT>LegalizerInfo :: getKernargParameterPtr ( MachineIRBuilder & B , int64_t Offset ) const { LLT PtrTy = LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ; Register KernArgReg = B . getMRI ( ) -> createGenericVirtualRegister ( PtrTy ) ; if ( ! loadInputValue ( KernArgReg , B , <STR_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ;

auto COffset = B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , Offset ) ;


<s> return MI -> getOpcode ( ) == <STR_LIT> || ( isInt < <NUM_LIT> > ( Offset ) && ( ! usesIXAddr ( * MI ) || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) ;


<s> switch ( TargetFlag ) { default : return false ; case <STR_LIT> : case <STR_LIT> :


<s> return ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ;


<s> case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerANDOR ( Op , DAG ) ; case <STR_LIT> : return LowerRET ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ;

case <STR_LIT> : return LowerSETCC ( Op , DAG ) ;


<s> void <ISA_LIT>InstrInfo :: StoreRegToStackSlot ( MachineFunction & MF , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * > & NewMIs ) const { unsigned Opcode = getStoreOpcodeForSpill ( RC ) ; DebugLoc DL ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> APInt ShiftAmt = AmtSplat -> getAPIntValue ( ) ; unsigned MaxAmount = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ShiftAmt . trunc ( <NUM_LIT> ) . uge ( MaxAmount ) ) return getZeroVector ( VT , Subtarget , DAG , DL ) ; } return SDValue ( ) ;


<s> void rs6000_expand_interleave ( rtx target , rtx op0 , rtx op1 , bool highp ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , high , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , <NUM_LIT> ) ; high = ( highp ? <NUM_LIT> : nelt / <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt / <NUM_LIT> ; i ++ ) { perm . quick_push ( i + high ) ; perm . quick_push ( i + nelt + high ) ; }

rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , perm ) ;


<s> static DecodeStatus DecodeExtRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo < <NUM_LIT> || RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ;

return <NUM_LIT> - ( MO . getImm ( ) | <NUM_LIT> ) ;


<s> } SDValue LO32 ; SDValue HI32 ; SmallVector < SDValue , <NUM_LIT> > ShufBytes ; SDValue Result ; if ( ! lower_special ) { SDValue LO32C = DAG . getConstant ( lower , <STR_LIT> ) ; LO32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LO32C , LO32C , LO32C , LO32C ) ) ; } if ( ! upper_special ) { SDValue HI32C = DAG . getConstant ( upper , <STR_LIT> ) ; HI32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HI32C , HI32C , HI32C , HI32C ) ) ; } if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t val = <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { SDValue V ; bool process_upper , process_lower ; val <<= <NUM_LIT> ;

process_upper = ( upper_special && ( i & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> RegSaveOffset ( unsigned Reg , unsigned Offset ) : Reg ( Reg ) , Offset ( Offset ) {


<s> unsigned AccessSize = <NUM_LIT> ; unsigned long OpIx = Operands . size ( ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; OpIx = <NUM_LIT> ; break ; case <STR_LIT> : AccessSize = <NUM_LIT> ;


<s> int ValueSplitCost = getScalarizationOverhead ( SrcVTy , IsLoad , IsStore ) ; int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ;

if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= expandMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ;


<s> unsigned NumElts = ToVT . getVectorNumElements ( ) ; if ( NumElts != M . size ( ) ) return false ; unsigned Off0 = rev ? NumElts : <NUM_LIT> ; unsigned Off1 = rev ? <NUM_LIT> : NumElts ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) ( Off0 + i / <NUM_LIT> ) ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ] != ( int ) ( Off1 + i / <NUM_LIT> ) ) return false ; } return true ; } ; if ( auto * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Trunc -> getOperand ( <NUM_LIT> ) ) ) if ( isVMOVNOriginalMask ( Shuffle -> getMask ( ) , false ) || isVMOVNOriginalMask ( Shuffle -> getMask ( ) , true ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewFromVT = EVT :: getVectorVT ( C , FromEltVT , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Stores ;

for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) {


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI ) {


<s> return create<ISA_LIT>MCCodeEmitter ( MCII , MRI , STI , Ctx ) ; } else {

return createR600MCCodeEmitter ( MCII , MRI , STI ) ;


<s> else _this = reg_names [ FIRST_ARGUMENT_REGNUM ] ; fprintf ( file , <STR_LIT> , ASM_COMMENT_START ) ; if ( delta ) fprintf ( file , <STR_LIT> , ( int ) delta , _this ) ; if ( vcall_offset ) { const char * scratch = reg_names [ FIRST_ADDRESS_REGNUM + <NUM_LIT> ] ; fprintf ( file , <STR_LIT> , _this , scratch ) ; fprintf ( file , <STR_LIT> , scratch , scratch ) ; fprintf ( file , <STR_LIT> , ( int ) vcall_offset , scratch ) ; fprintf ( file , <STR_LIT> , scratch , scratch ) ; fprintf ( file , <STR_LIT> , scratch , _this ) ; } fputs ( <STR_LIT> , file ) ; assemble_name ( file , XSTR ( XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> static SDValue PromoteSplat ( ShuffleVectorSDNode * SV , SelectionDAG & DAG ) { EVT SrcVT = SV -> getValueType ( <NUM_LIT> ) ; SDValue V1 = SV -> getOperand ( <NUM_LIT> ) ; DebugLoc dl = SV -> getDebugLoc ( ) ; int EltNo = SV -> getSplatIndex ( ) ;

int NumElems = SrcVT . getVectorNumElements ( ) ;


<s> void <ISA_LIT>AsmPrinter :: PrintDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) { OS << <STR_LIT> ;


<s> assert ( Extended . isExpr ( ) ) ; int64_t Value ;

if ( ! Extended . getExpr ( ) -> evaluateAsAbsolute ( Value ) ) return false ;


<s> if ( ! Subtarget -> isTargetDarwin ( ) ) return <NUM_LIT> ;

return Subtarget -> isThumb ( ) ? <STR_LIT> : <STR_LIT> ;


<s> unsigned NumElts = DemandedElts . getBitWidth ( ) ; if ( DemandedElts . isAllOnes ( ) ) return false ; SDValue Mask = Op . getOperand ( MaskIndex ) ; if ( ! Mask . hasOneUse ( ) ) return false ; APInt MaskUndef , MaskZero ; if ( SimplifyDemandedVectorElts ( Mask , DemandedElts , MaskUndef , MaskZero , TLO , Depth + <NUM_LIT> ) ) return true ; SDValue BC = peekThroughOneUseBitcasts ( Mask ) ; EVT BCVT = BC . getValueType ( ) ; auto * Load = dyn_cast < LoadSDNode > ( BC ) ; if ( ! Load ) return false ; const Constant * C = getTargetConstantFromNode ( Load ) ; if ( ! C ) return false ; Type * CTy = C -> getType ( ) ; if ( ! CTy -> isVectorTy ( ) || CTy -> getPrimitiveSizeInBits ( ) != Mask . getValueSizeInBits ( ) ) return false ; unsigned NumCstElts = cast < FixedVectorType > ( CTy ) -> getNumElements ( ) ; if ( NumCstElts != NumElts && NumCstElts != ( NumElts * <NUM_LIT> ) ) return false ; unsigned Scale = NumCstElts / NumElts ; bool Simplified = false ; SmallVector < Constant * , <NUM_LIT> > ConstVecOps ; for ( unsigned i = <NUM_LIT> ; i != NumCstElts ; ++ i ) { Constant * Elt = C -> getAggregateElement ( i ) ; if ( ! DemandedElts [ i / Scale ] && ! isa < UndefValue > ( Elt ) ) { ConstVecOps . push_back ( UndefValue :: get ( Elt -> getType ( ) ) ) ; Simplified = true ; continue ; } ConstVecOps . push_back ( Elt ) ; } if ( ! Simplified ) return false ; SDLoc DL ( Op ) ; SDValue CV = TLO . DAG . getConstantPool ( ConstantVector :: get ( ConstVecOps ) , BCVT ) ; SDValue LegalCV = LowerConstantPool ( CV , TLO . DAG ) ; SDValue NewMask = TLO . DAG . getLoad ( BCVT , DL , TLO . DAG . getEntryNode ( ) , LegalCV , MachinePointerInfo :: getConstantPool ( TLO . DAG . getMachineFunction ( ) ) , Load -> getAlign ( ) ) ; return TLO . CombineTo ( Mask , TLO . DAG . getBitcast ( Mask . getValueType ( ) , NewMask ) ) ;


<s> const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; tree version_attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ; if ( version_attr ) { tree v = TREE_VALUE ( TREE_VALUE ( version_attr ) ) ; const char * p = TREE_STRING_POINTER ( v ) ; fprintf ( stream , <STR_LIT> , name , name , p ) ; }

targetm . asm_out . globalize_label ( stream , name ) ;


<s> vmul_n_f32 ( float32x2_t a , float32_t b ) {


<s> if ( Expr == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ;


<s> void DecodePUNPCKLMask ( EVT VT , SmallVectorImpl < unsigned > & ShuffleMask ) {

DecodeUNPCKLPMask ( VT , ShuffleMask ) ;


<s> auto Arg = ArgInfo . getPreloadedValue ( Value ) . first ; return Arg ? Arg -> getRegister ( ) : <NUM_LIT> ;


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . parseEOL ( <STR_LIT> ) ) return addErrorSuffix ( <STR_LIT> ) ; return getTargetStreamer ( ) . emitFPOEndPrologue ( L ) ;


return cast < ConstantSDNode > ( VOffset ) -> getSExtValue ( ) + cast < ConstantSDNode > ( SOffset ) -> getSExtValue ( ) + cast < ConstantSDNode > ( Offset ) -> getSExtValue ( ) ;


<s> return isLegalToVectorizeMemChain ( ChainSizeInBytes , Alignment , AddrSpace ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeImm6 ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {

return encodeImmN ( MI , Op , Fixups , STI , MCFixupKind ( <STR_LIT> ) ) ;


<s> unsigned preg1 = Pred1 [ <NUM_LIT> ] . getReg ( ) ; int flag1 = Pred1 [ <NUM_LIT> ] . getImm ( ) ;

if ( ( preg1 == <STR_LIT> || preg1 == <STR_LIT> ) && ! flag1 ) return true ;


<s> return ( uint64x1_t ) { vcvtd_u64_f64 ( __a [ <NUM_LIT> ] ) } ;


<s> MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ;


<s> return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ;


<s> return get ( MI . getOpcode ( ) ) . TSFlags & <STR_LIT> ;


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( canWidenShuffleElements ( Mask , WidenedMask ) ) return lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { if ( isSingleInputShuffleMask ( Mask ) ) { int PSHUFDMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) { PSHUFDMask [ <NUM_LIT> * i ] = <NUM_LIT> * RepeatedMask [ i ] ; PSHUFDMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * RepeatedMask [ i ] + <NUM_LIT> ; } return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ;


<s> void copy_technique_from ( ExpressionTree * other ) {


<s> const static MCFixupKindInfo Infos [ ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsTarget } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; static_assert ( ( array_lengthof ( Infos ) ) == <STR_LIT> , <STR_LIT> ) ; if ( Kind >= FirstLiteralRelocationKind ) return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;

return Infos [ Kind - FirstTargetFixupKind ] ;


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ;


<s> case CallingConv :: <ISA_LIT>_Device : MFI -> setKernel ( false ) ; break ; } if ( MFI -> isKernel ( ) || ST . useParamSpaceForDeviceArgs ( ) ) { for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { assert ( ( ! MFI -> isKernel ( ) || Ins [ i ] . VT != <STR_LIT> ) && <STR_LIT> ) ; unsigned ParamSize = Ins [ i ] . VT . getStoreSizeInBits ( ) ; unsigned Param = PM . addArgumentParam ( ParamSize ) ; const std :: string & ParamName = PM . getParamName ( Param ) ; SDValue ParamValue = DAG . getTargetExternalSymbol ( ParamName . c_str ( ) , <STR_LIT> ) ; SDValue ArgValue = DAG . getNode ( <STR_LIT> , dl , Ins [ i ] . VT , Chain , ParamValue ) ; InVals . push_back ( ArgValue ) ; } } else { for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) {


<s> if ( ! s390_decompose_address ( XEXP ( op , <NUM_LIT> ) , & addr ) ) return false ; if ( addr . indx ) return false ;


<s> if ( DCI . Level == BeforeLegalizeTypes && VT . isVector ( ) && isTypeLegal ( VT ) && DAG . isConstantIntBuildVectorOrConstantInt ( N -> getOperand ( <NUM_LIT> ) ) ) return DAG . UnrollVectorOp ( N ) ; return SDValue ( ) ;


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShifts ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue Res ; if ( ( C = dyn_cast < ConstantSDNode > ( N1 ) ) ) { unsigned Val = C -> getZExtValue ( ) ; if ( ! <STR_LIT> ( Mask ) || ( Val & ~ Mask ) != Val ) return SDValue ( ) ; Val >>= CountTrailingZeros_32 ( ~ Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Val , <STR_LIT> ) , DAG . getConstant ( Mask , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; } else if ( N1 . getOpcode ( ) == <STR_LIT> ) { C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; unsigned Mask2 = C -> getZExtValue ( ) ; if ( <STR_LIT> ( Mask ) && <STR_LIT> ( ~ Mask2 ) && ( CountPopulation_32 ( Mask ) == CountPopulation_32 ( ~ Mask2 ) ) ) { if ( Subtarget -> hasT2ExtractPack ( ) && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) return SDValue ( ) ; unsigned lsb = CountTrailingZeros_32 ( Mask2 ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( lsb , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , Res , DAG . getConstant ( Mask , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; } else if ( <STR_LIT> ( ~ Mask ) && <STR_LIT> ( Mask2 ) && ( CountPopulation_32 ( ~ Mask ) == CountPopulation_32 ( Mask2 ) ) ) { if ( Subtarget -> hasT2ExtractPack ( ) && ( Mask2 == <NUM_LIT> || Mask2 == <NUM_LIT> ) ) return SDValue ( ) ; unsigned lsb = CountTrailingZeros_32 ( Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( lsb , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , Res , DAG . getConstant ( Mask2 , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getPreloadedValue ( SelectionDAG & DAG , const <ISA_LIT>MachineFunctionInfo & MFI , EVT VT , <STR_LIT> PVID ) const { const ArgDescriptor * Reg ; const TargetRegisterClass * RC ; LLT Ty ; std :: tie ( Reg , RC , Ty ) = MFI . getPreloadedValue ( PVID ) ; if ( ! Reg ) { if ( PVID == <STR_LIT> :: KERNARG_SEGMENT_PTR ) {

return DAG . getConstant ( <NUM_LIT> , SDLoc ( ) , VT ) ;


<s> unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; EVT WideVT = RegSeq . getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; static unsigned QSubs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) { SDValue NV = CurDAG -> getTargetExtractSubreg ( QSubs [ i ] , dl , WideVT , SuperReg ) ;

if ( Narrow ) NV = NarrowVector ( NV , * CurDAG ) ;


<s> subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( MEM_P ( * iter ) ) return true ;


<s> bool <ISA_LIT>RegisterInfo :: needsFrameBaseReg ( MachineInstr * MI , int64_t Offset ) const { for ( unsigned i = <NUM_LIT> ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) return false ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int64_t FPOffset = Offset - <NUM_LIT> * <NUM_LIT> ; Offset += MFI -> getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; if ( TFI -> hasFP ( MF ) && isFrameOffsetLegal ( MI , FPOffset ) ) return false ; if ( isFrameOffsetLegal ( MI , Offset ) ) return false ; return true ;


<s> bool <ISA_LIT>FrameLowering :: useSpillFunction ( MachineFunction & MF , const CSIVect & CSI ) const { if ( shouldInlineCSR ( MF , CSI ) ) return false ; unsigned NumCSI = CSI . size ( ) ; if ( NumCSI <= <NUM_LIT> ) return false ;

unsigned Threshold = isOptSize ( MF ) ? SpillFuncThresholdOs : SpillFuncThreshold ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E ) {

auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Immediate ) ;


<s> if ( LS1 . isProperty ( ) ) { if ( LS1 . properties ( ) & ConstantProperties :: Zero ) { const Constant * C = intToConst ( A2 ) ; Result . add ( C ) ; return ! Result . isBottom ( ) ; } return false ; } APInt A , XA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) { bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateXORii ( A , A2 , XA ) ; if ( ! Eval ) return false ; const Constant * C = intToConst ( XA ) ; Result . add ( C ) ; } return ! Result . isBottom ( ) ;


<s> man = spu_and ( ( vec_uint4 ) ( a ) , spu_splats ( ( unsigned int ) <NUM_LIT> ) ) ; return ( ( int ) ( spu_extract ( spu_gather ( spu_andc ( spu_cmpeq ( exp , exp_mask ) , spu_cmpeq ( man , <NUM_LIT> ) ) ) , <NUM_LIT> ) == <NUM_LIT> ) ) ;


<s> } else { O << Sym . getName ( ) ; } } else { O << * Expr ; } O << <STR_LIT> ; if ( NumArgs > <NUM_LIT> ) { printOperand ( MI , Index ++ , O ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { O << <STR_LIT> ; printOperand ( MI , Index ++ , O ) ; } } O << <STR_LIT> ;


<s> MachineInstrBuilder MIB = emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , LowOpcode , Size , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ;

for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) MIB . add ( MI . getOperand ( I ) ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ;


<s> else if ( ! RDA -> hasSameReachingDef ( From , To , MO . getReg ( ) ) ) return false ; } for ( auto I = ++ Iterator ( From ) , E = Iterator ( To ) ; I != E ; ++ I ) { for ( auto & MO : I -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && Defs . count ( MO . getReg ( ) ) ) return false ; } return true ;


<s> bool NegateCC ; tie ( Chain , NegateCC ) = ConvertSETCC ( op , DAG ) ; if ( NegateCC ) Chain = DAG . getNode ( <STR_LIT> , op . getDebugLoc ( ) , <STR_LIT> , Chain , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return Chain ;


<s> if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue Val = Op1 . getOperand ( <NUM_LIT> ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) { if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> ) { SDValue U0 = U -> getOperand ( <NUM_LIT> ) ; SDValue U1 = U -> getOperand ( <NUM_LIT> ) ; if ( U0 . getOpcode ( ) == <STR_LIT> ) { auto * C = dyn_cast < ConstantSDNode > ( U0 . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getSExtValue ( ) == - <NUM_LIT> ) return false ; } if ( U1 . getOpcode ( ) == <STR_LIT> ) { auto * C = dyn_cast < ConstantSDNode > ( U1 . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getSExtValue ( ) == - <NUM_LIT> ) return false ; } } break ; } case <STR_LIT> : case <STR_LIT> :


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; }


<s> int regnum ; if ( GET_CODE ( op ) == REG ) regnum = REGNO ( op ) ;

else if ( GET_CODE ( op ) == PLUS && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) regnum = REGNO ( XEXP ( op , <NUM_LIT> ) ) ;


<s> bool usesPhysRegsForPEI ( ) const override {


<s> void Thumb1RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , <STR_LIT> Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ;

MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ;


<s> MachineInstr * NewMI = std :: prev ( MBBI ) ; NewMI -> copyImplicitOps ( * MBBI -> getParent ( ) -> getParent ( ) , MBBI ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; const bool Uses64BitFramePtr = STI -> isTarget64BitLP64 ( ) || STI -> isTargetNaCl64 ( ) ; unsigned StackPtr = TRI -> getStackRegister ( ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; return true ; } case <STR_LIT> : { int64_t StackAdj = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , StackAdj , true ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : { bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( MBB . getParent ( ) -> getFunction ( ) -> getPersonalityFn ( ) ) ) ; <ISA_LIT>FL -> restoreWin32EHStackPointers ( MBB , MBBI , DL , IsSEH ) ; MBBI -> eraseFromParent ( ) ;


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const {


<s> case 'v' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ;


<s> <ISA_LIT>Argument ( bool ) : IsRegister ( true ) , RegisterName ( ) {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DefClamp << <STR_LIT> << * Def << '\n' ) ; DefClamp -> setImm ( <NUM_LIT> ) ; MRI -> replaceRegWith ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent ( ) ;


<s> MandarinTargetMachine :: MandarinTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> MachineInstrBuilder MIB ; MIB = BuildMI ( * MBB , InsertionPoint , DL , TII -> get ( getMatchingWideOpcode ( Opc ) ) ) . addReg ( isNarrowStore ( Opc ) ? <STR_LIT> : <STR_LIT> ) . add ( BaseRegOp ) . addImm ( OffsetImm ) . setMemRefs ( I -> mergeMemRefsWith ( * MergeMI ) ) . setMIFlags ( I -> mergeFlagsWith ( * MergeMI ) ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MergeMI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( ( ( MachineInstr * ) MIB ) -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent ( ) ; MergeMI -> eraseFromParent ( ) ;


<s> return ( __m256i ) __builtin_ia32_pmovsxbd256 ( ( __v16qi ) __X ) ;


<s> <ISA_LIT>InstrAnalyzer * PIA = new <ISA_LIT>InstrAnalyzer ( Ctx ) ; const MCSection * TS = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getText ( ) ) ; PIA -> SwitchSection ( TS ) ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) , STI ( STI ) {


<s> Swap = true ; } else return false ; DM = ( ( ( ~ M1 ) & <NUM_LIT> ) << <NUM_LIT> ) + ( ( ~ M0 ) & <NUM_LIT> ) ; return true ; } else { if ( M0 < <NUM_LIT> && M1 > <NUM_LIT> ) { Swap = false ; } else if ( M0 > <NUM_LIT> && M1 < <NUM_LIT> ) { M0 = ( M0 + <NUM_LIT> ) % <NUM_LIT> ; M1 = ( M1 + <NUM_LIT> ) % <NUM_LIT> ; Swap = true ; } else return false ; DM = ( M0 << <NUM_LIT> ) + ( M1 & <NUM_LIT> ) ; return true ;


<s> continue ; } } if ( STI . hasFeature ( <STR_LIT> ) && getLexer ( ) . is ( AsmToken :: LBrac ) ) { eatThatToken ( Operands ) ; if ( ! tryParseExpr ( Operands , <STR_LIT> ) ) { FirstTime = false ; continue ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Lex ( ) ; continue ; } StringRef TokName ; SMLoc TokLoc ; TokName = getLexer ( ) . getTok ( ) . getString ( ) ; TokLoc = getLexer ( ) . getTok ( ) . getLoc ( ) ; if ( FirstTime && ( TokName == <STR_LIT> || TokName == <STR_LIT> ) ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return <STR_LIT> ; return VT . changeVectorElementTypeToInteger ( ) ;


<s> return ST -> hasBCNT ( TyWidth ) ? TTI :: PSK_FastHardware : TTI :: PSK_Software ;


<s> <ISA_LIT>FrameLowering :: ~ <ISA_LIT>FrameLowering ( ) {


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue R = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; unsigned Opcode = Op . getOpcode ( ) ; unsigned <ISA_LIT>OpcI = getTargetVShiftUniformOpcode ( Opcode , false ) ; unsigned <ISA_LIT>OpcV = getTargetVShiftUniformOpcode ( Opcode , true ) ; Amt = peekThroughEXTRACT_SUBVECTORs ( Amt ) ; if ( SupportedVectorShiftWithBaseAmnt ( VT , Subtarget , Opcode ) ) { if ( SDValue BaseShAmt = IsSplatValue ( VT , Amt , dl , DAG , Subtarget , Opcode ) ) { MVT EltVT = VT . getVectorElementType ( ) ; assert ( EltVT . bitsLE ( <STR_LIT> ) && <STR_LIT> ) ;

if ( EltVT != <STR_LIT> && EltVT . bitsGT ( <STR_LIT> ) ) BaseShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BaseShAmt ) ;


<s> static DecodeStatus decodePixelRotOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) {

return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm << <NUM_LIT> ) ;


<s> const TargetRegisterClass * RC = TRI . getConstrainedRegClassForOperand ( MO , MRI ) ; if ( RC ) RBI . constrainGenericRegister ( MO . getReg ( ) , * RC , MRI ) ; I . setDesc ( TII . get ( TargetOpcode :: IMPLICIT_DEF ) ) ; return true ;


<s> if ( VECTOR_MODE_P ( mode ) || mode == TImode ) { insn_entry [ uid ] . is_relevant = <NUM_LIT> ; if ( mode == TImode || mode == V1TImode ) insn_entry [ uid ] . is_128_int = <NUM_LIT> ; if ( DF_REF_INSN_INFO ( mention ) ) insn_entry [ uid ] . contains_subreg = ! rtx_equal_p ( DF_REF_REG ( mention ) , DF_REF_REAL_REG ( mention ) ) ; else if ( REG_FUNCTION_VALUE_P ( DF_REF_REG ( mention ) ) ) insn_entry [ uid ] . is_live_out = <NUM_LIT> ; union_uses ( insn_entry , insn , mention ) ; } } if ( insn_entry [ uid ] . is_relevant ) { insn_entry [ uid ] . is_load = insn_is_load_p ( insn ) ; insn_entry [ uid ] . is_store = insn_is_store_p ( insn ) ; if ( insn_is_swap_p ( insn ) ) insn_entry [ uid ] . is_swap = <NUM_LIT> ; else { unsigned int special = SH_NONE ; insn_entry [ uid ] . is_swappable = insn_is_swappable_p ( insn_entry , insn , & special ) ; if ( special != SH_NONE && insn_entry [ uid ] . contains_subreg ) insn_entry [ uid ] . is_swappable = <NUM_LIT> ;

else if ( special != SH_NONE ) insn_entry [ uid ] . special_handling = special ;


<s> static unsigned getBasePointerSaveOffset ( bool is<ISA_LIT>64 , bool isDarwinABI , bool isPIC ) { if ( isDarwinABI ) return is<ISA_LIT>64 ? - <NUM_LIT> : - <NUM_LIT> ;


<s> static DecodeStatus DecodeMatrixTile ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) {

unsigned LastReg = ( <NUM_LIT> << NumBitsForTile ) - <NUM_LIT> ;


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> auto CopySign = B . buildFCopysign ( Ty , C1 , Src ) ; auto Tmp1 = B . buildFAdd ( Ty , Src , CopySign ) ; auto Tmp2 = B . buildFSub ( Ty , Tmp1 , CopySign ) ; auto C2 = B . buildFConstant ( Ty , C2Val ) ; auto Fabs = B . buildFAbs ( Ty , Src ) ; auto Cond = B . buildFCmp ( CmpInst :: FCMP_OGT , LLT :: scalar ( <NUM_LIT> ) , Fabs , C2 ) ; B . buildSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Cond , Src , Tmp2 ) ;


<s> return TARGET_64BIT || ! TARGET_PARTIAL_REG_STALL ; case DImode : return TARGET_64BIT ; default : return false ;


<s> } else if ( MI . getOpcode ( ) == <STR_LIT> ) { } else { llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>BranchExpansion :: handleForbiddenSlot ( ) { if ( ! STI -> has<ISA_LIT>32r6 ( ) || STI -> inMicro<ISA_LIT>Mode ( ) ) return false ; const <ISA_LIT>InstrInfo * TII = STI -> getInstrInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = MFp -> begin ( ) ; FI != MFp -> end ( ) ; ++ FI ) { for ( Iter I = FI -> begin ( ) ; I != FI -> end ( ) ; ++ I ) { if ( ! TII -> HasForbiddenSlot ( * I ) ) continue ; Iter Inst ; bool LastInstInFunction = std :: next ( I ) == FI -> end ( ) && std :: next ( FI ) == MFp -> end ( ) ; if ( ! LastInstInFunction ) { std :: pair < Iter , bool > Res = getNextMachineInstr ( std :: next ( I ) , & * FI ) ; LastInstInFunction |= Res . second ; Inst = Res . first ; } if ( LastInstInFunction || ! TII -> SafeInForbiddenSlot ( * Inst ) ) { MachineBasicBlock :: instr_iterator Iit = I -> getIterator ( ) ;

if ( std :: next ( Iit ) == FI -> end ( ) || std :: next ( Iit ) -> getOpcode ( ) != <STR_LIT> ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return HasVSX ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned internalKnownBits ( ) const { unsigned Bits = Unalign ? Unalign : KnownBits ; if ( Size & ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) ) Bits = CountTrailingZeros_32 ( Size ) ;


<s> removeOperands ( MI , FrameRegIdx ) ; MachineInstrBuilder MIB ( & MI ) ; AddDefaultPred ( AddDefaultT1CC ( MIB ) . addReg ( FrameReg ) . addImm ( Mask ) ) ; } else { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( Mask ) ; } Offset = ( Offset - Mask * Scale ) ; MachineBasicBlock :: iterator NII = llvm :: next ( II ) ; emitThumbRegPlusImmediate ( MBB , NII , DestReg , DestReg , Offset , TII , * this , dl ) ; } else { emitThumbConstant ( MBB , II , DestReg , Offset , TII , * this , dl ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( DestReg , false , false , true ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false ) ; if ( Opcode == <STR_LIT> ) { MachineInstrBuilder MIB ( & MI ) ; AddDefaultPred ( MIB ) ; } } return true ; } else { unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; return true ; } bool isThumSpillRestore = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( AddrMode == <STR_LIT> ) { NumBits = <NUM_LIT> ; Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; } if ( AddrMode == <STR_LIT> && isThumSpillRestore ) ImmOp . ChangeToImmediate ( <NUM_LIT> ) ;


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) , FrameIndex ) ; if ( DestReg != <STR_LIT> ) {


<s> uint64_t Used = allOnes ( Op . getValueType ( ) . getSizeInBits ( ) ) ; if ( Used != ( AndMask | InsertMask ) ) { APInt KnownZero , KnownOne ; CurDAG -> ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne ) ; if ( Used != ( AndMask | InsertMask | KnownZero . getZExtValue ( ) ) ) return false ; } Op = Op . getOperand ( <NUM_LIT> ) ; return true ;


<s> offset = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( offset ) == REG ) { fprintf ( file , <STR_LIT> , reg_names [ REGNO ( reg ) ] , reg_names [ REGNO ( offset ) ] ) ; } else if ( GET_CODE ( offset ) == CONST_INT ) { fprintf ( file , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( offset ) , reg_names [ REGNO ( reg ) ] ) ; } else abort ( ) ; break ; case CONST : case LABEL_REF : case SYMBOL_REF : case CONST_INT : output_addr_const ( file , addr ) ; break ;


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; SDValue Ins = N -> getOperand ( <NUM_LIT> ) ; EVT IdxVT = Idx . getValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned I = <NUM_LIT> , E = VecVT . getVectorNumElements ( ) ; I < E ; ++ I ) { SDValue IC = DAG . getConstant ( I , SL , IdxVT ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec , IC ) ; SDValue V = DAG . getSelectCC ( SL , Idx , IC , Ins , Elt , <STR_LIT> ) ; Ops . push_back ( V ) ; }

return DAG . getBuildVector ( VecVT , SL , Ops ) ;


<s> if ( in == <NUM_LIT> ) return MAX ( ix86_cost -> hard_register . movzbl_load , ix86_cost -> hard_register . int_store [ <NUM_LIT> ] + <NUM_LIT> ) ; if ( in ) return ix86_cost -> hard_register . movzbl_load ; else return ix86_cost -> hard_register . int_store [ <NUM_LIT> ] + <NUM_LIT> ; } break ; case <NUM_LIT> : { int cost ; if ( in == <NUM_LIT> ) cost = MAX ( ix86_cost -> hard_register . int_load [ <NUM_LIT> ] , ix86_cost -> hard_register . int_store [ <NUM_LIT> ] ) ; else cost = in ? ix86_cost -> hard_register . int_load [ <NUM_LIT> ] : ix86_cost -> hard_register . int_store [ <NUM_LIT> ] ; if ( mode == E_HFmode ) { int sse_cost ; int index = sse_store_index ( mode ) ; if ( in == <NUM_LIT> ) sse_cost = MAX ( ix86_cost -> hard_register . sse_load [ index ] , ix86_cost -> hard_register . sse_store [ index ] ) ; else sse_cost = ( in ? ix86_cost -> hard_register . sse_load [ index ] : ix86_cost -> hard_register . sse_store [ index ] ) ; if ( sse_cost >= cost ) cost = sse_cost + <NUM_LIT> ; } return cost ; } default : if ( in == <NUM_LIT> ) cost = MAX ( ix86_cost -> hard_register . int_load [ <NUM_LIT> ] , ix86_cost -> hard_register . int_store [ <NUM_LIT> ] ) ; else if ( in ) cost = ix86_cost -> hard_register . int_load [ <NUM_LIT> ] ; else cost = ix86_cost -> hard_register . int_store [ <NUM_LIT> ] ; return cost * CEIL ( ( int ) GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ;


<s> if ( ! SetHiMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; int64_t imm = SetHiMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( imm ) ) return false ; imm = ( imm << <NUM_LIT> ) & <NUM_LIT> ; assert ( RestoreMI -> getOpcode ( ) == <STR_LIT> ) ; RestoreMI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( reg - <STR_LIT> + <STR_LIT> ) ;

RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ;


if ( size ( ) <= Idx ) resize ( std :: max ( Idx + <NUM_LIT> , <NUM_LIT> ) ) ;


<s> offset = SUBREG_BYTE ( op ) ; op = SUBREG_REG ( op ) ; src_mode = GET_MODE ( op ) ; if ( GET_MODE_SIZE ( dest_mode ) == GET_MODE_SIZE ( src_mode ) ) return false ; if ( GET_CODE ( op ) != REG ) return false ; if ( REGNO ( op ) >= MEM0_REGNO ) return false ; offset = ( <NUM_LIT> << offset ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( legal_subregs ) ; i ++ ) if ( legal_subregs [ i ] . outer_mode_size == GET_MODE_SIZE ( dest_mode ) && legal_subregs [ i ] . regno == REGNO ( op ) && legal_subregs [ i ] . inner_mode_size == GET_MODE_SIZE ( src_mode ) && legal_subregs [ i ] . byte_mask & offset ) { switch ( legal_subregs [ i ] . legal_when ) { case <NUM_LIT> : return false ; case <NUM_LIT> : if ( TARGET_A16 ) return false ; break ; case <NUM_LIT> :


<s> return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm , Address , false , Decoder ) ;


<s> do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } fixTCReturn ( MF , MBB ) ;

if ( ArgRegsSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , ArgRegsSaveSize ) ;


<s> int32_t BranchOffset = ( SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ) + <NUM_LIT> ;

Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ;


<s> } } else { return false ; } auto setcc_inner = Dest . getOperand ( select ) . getOperand ( <NUM_LIT> ) ; auto reg_xxx = & Dest . getOperand ( select ) . getOperand ( <NUM_LIT> ) ; const SDValue * reg_out ; int inner_pos_constant_low_cc ; if ( setcc_inner . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { inner_pos_constant_low_cc = <NUM_LIT> ; reg_out = & setcc_inner . getOperand ( <NUM_LIT> ) ; } else if ( setcc_outer . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { reg_out = & setcc_inner . getOperand ( <NUM_LIT> ) ; inner_pos_constant_low_cc = <NUM_LIT> ; } else { return false ; } MemSDNode * mem_in = cast < MemSDNode > ( * reg_in ) ; MemSDNode * mem_out = cast < MemSDNode > ( * reg_out ) ; MemSDNode * mem_xxx = cast < MemSDNode > ( * reg_xxx ) ; if ( * ( mem_in -> getMemOperand ( ) ) != * ( mem_out -> getMemOperand ( ) ) || * ( mem_in -> getMemOperand ( ) ) != * ( mem_xxx -> getMemOperand ( ) ) ) { return false ; } int32_t inner_low_constant_cc = setcc_inner . getConstantOperandVal ( inner_pos_constant_low_cc ) ; if ( setcc_inner . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && cast < CondCodeSDNode > ( * setcc_inner . getOperand ( <NUM_LIT> ) . getNode ( ) ) . get ( ) == <STR_LIT> ) { if ( ! unsign && inner_low_constant_cc != - low_constant_cc ) { return false ; }


<s> Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I ; for ( I = BB -> getIterator ( ) ; I != F -> end ( ) && & ( * I ) != BB ; ++ I ) ; if ( I != F -> end ( ) ) ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; auto ShiftMI = BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; if ( HasRepeatedOperand ) ShiftMI . addReg ( ShiftReg ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( LoopBB ) ;

BuildMI ( * RemBB , RemBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ;


<s> bool isImmInRange ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= N && Val <= M ) ;