<s> APInt ccResultAllOnes = APInt :: getAllOnesValue ( ccResultVT . getSizeInBits ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , ccResultVT , DAG . getSetCC ( dl , ccResultVT , lhs , DAG . getConstantFP ( <NUM_LIT> , lhsVT ) , <STR_LIT> ) , DAG . getConstant ( ccResultAllOnes , ccResultVT ) ) ; } else if ( CC -> get ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , ccResultVT , DAG . getSetCC ( dl , ccResultVT , lhsHi32abs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) , DAG . getSetCC ( dl , ccResultVT , lhsLo32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ) ; } SDValue i64rhs = DAG . getNode ( <STR_LIT> , dl , IntVT , rhs ) ; SDValue rhsHi32 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , IntVT , i64rhs , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; SDValue signMag2TC = DAG . getConstant ( <NUM_LIT> , IntVT ) ; SDValue lhsSelectMask = DAG . getNode ( <STR_LIT> , dl , ccResultVT , lhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue lhsSignMag2TC = DAG . getNode ( <STR_LIT> , dl , IntVT , signMag2TC , i64lhs ) ; SDValue lhsSelect = DAG . getNode ( <STR_LIT> , dl , IntVT , lhsSelectMask , lhsSignMag2TC , i64lhs ) ; SDValue rhsSelectMask = DAG . getNode ( <STR_LIT> , dl , ccResultVT , rhsHi32 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue rhsSignMag2TC = DAG . getNode ( <STR_LIT> , dl , IntVT , signMag2TC , i64rhs ) ; SDValue rhsSelect = DAG . getNode ( <STR_LIT> , dl , IntVT , rhsSelectMask , rhsSignMag2TC , i64rhs ) ; unsigned compareOp ; switch ( CC -> get ( ) ) { case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : compareOp = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> :


<s> static bool isImmSExti16i8Value ( uint64_t Value ) {

return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) ) ;


<s> unsigned rv = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MissingFeatures , matchingInlineAsm , VariantID ) ; if ( Code16GCC ) SwitchMode ( <STR_LIT> ) ;


<s> } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry SSSE3CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry SSE2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; unsigned ISD = <STR_LIT> ; switch ( IID ) { default : break ; case <STR_LIT> : ISD = <STR_LIT> ; break ; case <STR_LIT> : ISD = <STR_LIT> ;


<s> return ( ( ( insn ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ;

Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ;


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; const Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ; Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ; Args . push_back ( Entry ) ; Entry . Node = FPtr ; Args . push_back ( Entry ) ; Entry . Node = Nest ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , Op . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; SDValue Ops [ ] = { CallResult . first , CallResult . second } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , dl ) ;


<s> auto DL = & F -> getParent ( ) -> getDataLayout ( ) ; Type * DstEltTy = BCInst -> getDestTy ( ) -> getVectorElementType ( ) -> getPointerElementType ( ) ; unsigned DestSize = DL -> getTypeStoreSize ( DstEltTy ) ; unsigned AggSize = DL -> getTypeStoreSize ( SrcEltTy ) ; if ( AggSize % DestSize ) { DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; continue ; } unsigned Stride = AggSize / DestSize ; IRBuilder < > B ( cast < Instruction > ( Offsets ) ) ; auto NewBase = B . CreateShl ( SVBase , ConstantInt :: get ( SVBase -> getType ( ) , Log2_64 ( Stride ) ) ) ; B . SetInsertPoint ( I ) ; auto NewOffsets = B . CreateSeriesVector ( cast < VectorType > ( Offsets -> getType ( ) ) -> getElementCount ( ) , NewBase , ConstantInt :: get ( SVStep -> getType ( ) , Stride ) ) ; auto BaseGEP = cast < GetElementPtrInst > ( GEP -> getPointerOperand ( ) ) ; SmallVector < Value * , <NUM_LIT> > Indices ; for ( auto II = BaseGEP -> idx_begin ( ) , IE = BaseGEP -> idx_end ( ) ; II != IE ; ++ II ) Indices . push_back ( * II ) ; Indices . push_back ( B . getInt32 ( <NUM_LIT> ) ) ; auto NewBaseGEP = GetElementPtrInst :: Create ( nullptr , BaseGEP -> getPointerOperand ( ) , Indices , <STR_LIT> , BaseGEP ) ; NewBaseGEP -> setDebugLoc ( BaseGEP -> getDebugLoc ( ) ) ; auto NewGEP = GetElementPtrInst :: Create ( nullptr , NewBaseGEP , { NewOffsets } ) ; NewGEP -> setDebugLoc ( GEP -> getDebugLoc ( ) ) ; B . Insert ( NewGEP ) ; auto NewBC = B . CreateBitCast ( NewGEP , BC -> getType ( ) ) ; BC -> replaceAllUsesWith ( NewBC ) ; ProcessedInsts . push_back ( BCInst ) ; ProcessedInsts . push_back ( GEP ) ; ProcessedInsts . push_back ( BaseGEP ) ; LoopChanged = true ; } for ( auto & I : ProcessedInsts ) { if ( I -> getNumUses ( ) == <NUM_LIT> ) I -> eraseFromParent ( ) ;


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , <NUM_LIT> , <NUM_LIT> ) ; } return false ; } default : const <ISA_LIT>InstrFMA3Group * FMA3Group = <ISA_LIT>InstrFMA3Info :: getFMA3Group ( MI . getOpcode ( ) ) ; if ( FMA3Group ) return findFMA3CommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 , * FMA3Group ) ;

return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { SDNode * Elt = N -> getOperand ( i ) . getNode ( ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Elt ) ) {

unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ;


<s> return Info ? Info -> Opcode : - <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : return SplitHvxMemOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) { default : break ; case <STR_LIT> : return LowerHvxBuildVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxBitcast ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxCttz ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSelect ( Op , DAG ) ; case <STR_LIT> :


<s> bool isKernelCC ( const Function * Func ) { return <STR_LIT> ( Func -> getCallingConv ( ) ) ;


<s> nds32_compute_stack_frame ( ) ; if ( frame_pointer_needed ) cfun -> machine -> fp_as_gp_p = false ; if ( cfun -> machine -> va_args_size != <NUM_LIT> ) { Rb = cfun -> machine -> va_args_first_regno ; Re = cfun -> machine -> va_args_last_regno ; nds32_emit_stack_push_multiple ( Rb , Re , false , false , false , true ) ; if ( cfun -> machine -> va_args_area_padding_bytes ) { sp_adjust = cfun -> machine -> va_args_area_padding_bytes ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - <NUM_LIT> * sp_adjust ) ; } } if ( cfun -> machine -> naked_p && ! flag_pic ) return ; Rb = cfun -> machine -> callee_saved_first_gpr_regno ; Re = cfun -> machine -> callee_saved_last_gpr_regno ; if ( ! ( Rb == SP_REGNUM && Re == SP_REGNUM && cfun -> machine -> fp_size == <NUM_LIT> && cfun -> machine -> gp_size == <NUM_LIT> && cfun -> machine -> lp_size == <NUM_LIT> ) ) { nds32_emit_stack_push_multiple ( Rb , Re , cfun -> machine -> fp_size , cfun -> machine -> gp_size , cfun -> machine -> lp_size , false ) ; } if ( cfun -> machine -> use_eh_return_p ) { Rb = cfun -> machine -> eh_return_data_first_regno ; Re = cfun -> machine -> eh_return_data_last_regno ; nds32_emit_stack_push_multiple ( Rb , Re , false , false , false , false ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size + cfun -> machine -> eh_return_data_regs_size ; nds32_emit_adjust_frame ( hard_frame_pointer_rtx , stack_pointer_rtx , fp_adjust ) ; } if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { int fpr_offset = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_fpr_regs_size ; if ( ! satisfies_constraint_Is14 ( GEN_INT ( fpr_offset ) ) ) { int fpr_space = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , - <NUM_LIT> * fpr_space ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , bool IsLittle ) : MCAsmBackend ( ) , STI ( STI ) , isThumbMode ( STI . getTargetTriple ( ) . isThumb ( ) ) , IsLittleEndian ( IsLittle ) {


<s> MachineBasicBlock :: iterator MI = MBB . getFirstTerminator ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; if ( useRestoreFunction ( MF , CSI ) ) { bool HasTC = hasTailCall ( MBB ) || ! hasReturn ( MBB ) ; unsigned MaxR = getMaxCalleeSavedReg ( CSI , HRI ) ; SpillKind Kind = HasTC ? SK_FromMemTailcall : SK_FromMem ; const char * RestoreFn = getSpillFunctionFor ( MaxR , Kind ) ; auto & HTM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; bool IsPIC = HTM . isPositionIndependent ( ) ; bool LongCalls = HST . useLongCalls ( ) || EnableSaveRestoreLong ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : MBB . findDebugLoc ( MBB . end ( ) ) ; MachineInstr * DeallocCall = nullptr ; if ( HasTC ) {


<s> MCSymbol * <ISA_LIT>AsmPrinter :: Get<ISA_LIT>GVSymbol ( const GlobalValue * GV ) { bool isIndirect = Subtarget -> isTargetDarwin ( ) && Subtarget -> GVIsIndirectSymbol ( GV , TM . getRelocationModel ( ) ) ; if ( ! isIndirect ) return Mang -> getSymbol ( GV ) ; MCSymbol * MCSym = GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> hasHiddenVisibility ( ) ? MMIMachO . getHiddenGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry ( MCSym ) ;

if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl ::


<s> } if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) ) { CanAcceptPredicationCode = false ; } else { CanAcceptPredicationCode = true ; } if ( isThumb ) if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) CanAcceptPredicationCode = false ;


<s> bool <ISA_LIT>InstrInfo :: usesAddressRegister ( MachineInstr & MI ) const { return MI . findRegisterUseOperandIdx ( <STR_LIT> , false , & RI ) != - <NUM_LIT> ;


<s> SDNode * Mul = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InFlag = SDValue ( Mul , <NUM_LIT> ) ; if ( HasLo ) { unsigned Opcode = Subtarget . in<ISA_LIT>16Mode ( ) ? <STR_LIT> : ( Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Lo = CurDAG -> getMachineNode ( Opcode , dl , Ty , <STR_LIT> , InFlag ) ; InFlag = SDValue ( Lo , <NUM_LIT> ) ; } if ( HasHi ) { unsigned Opcode = Subtarget . in<ISA_LIT>16Mode ( ) ? <STR_LIT> : ( Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Hi = CurDAG -> getMachineNode ( Opcode , dl , Ty , InFlag ) ;


<s> if ( ! Subtarget . hasVLX ( ) ) return ; Register XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { Register XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ;


<s> void printMemRegReg ( const MachineInstr * MI , unsigned OpNo ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; printRegister ( MO , true ) ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ;


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const {

OS . write_zeros ( Count % <NUM_LIT> ) ;


<s> static DecodeStatus DecodeFPRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = FPRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> return m16_check_op ( op , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ;


<s> Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ;

return std :: unique_ptr < <ISA_LIT>Operand > ( Op ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; return ( ( <NUM_LIT> - MO . getImm ( ) ) & <NUM_LIT> ) | ( <NUM_LIT> - MO . getImm ( ) ) << <NUM_LIT> ;


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) {


<s> strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; } else { strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ;


<s> for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) O . write_hex ( ( Value & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ) >> ( i * <NUM_LIT> ) ) ;


<s> if ( ! isRetiredBlock ( LoopLand ) ) return true ; LoopRep = LoopRep -> getParentLoop ( ) ; } return false ;


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_FUNCTION_EXIT ( const MachineInstr & MI ) {

EmitSled ( MI , SledKind :: FUNCTION_EXIT ) ;


<s> case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0Reg ) return false ; bool Op0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned ResultReg = FastEmitInst_r ( Opc , RC , Op0Reg , Op0IsKill ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I , ResultReg ) ; return true ;


<s> { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { std :: array < SDValue , <NUM_LIT> > Ops = { { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { std :: array < SDValue , <NUM_LIT> > Ops = { { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } ReplaceUses ( N , Result ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; else if ( ! Subtarget . has<ISA_LIT>64 ( ) ) return CSR_O32_RegMask ; else if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ;


if ( ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> ) ) {


<s> if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; AsmPrinter . getNameWithPrefix ( Name , GV ) ; } else if ( MO . isSymbol ( ) ) { Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else if ( MO . isMBB ( ) ) { assert ( Suffix . empty ( ) ) ; Sym = MO . getMBB ( ) -> getSymbol ( ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; if ( ! Sym ) Sym = Ctx . getOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; switch ( MO . getTargetFlags ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) {

assert ( MO . isGlobal ( ) && <STR_LIT> ) ;


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = & TII -> getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; assert ( MFI -> isEntryFunction ( ) ) ; Register ScratchRsrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ! ScratchRsrcReg || ( ! MRI . isPhysRegUsed ( ScratchRsrcReg ) && allStackObjectsAreDead ( MF . getFrameInfo ( ) ) ) ) return Register ( ) ; if ( ST . hasSGPRInitBug ( ) || ScratchRsrcReg != TRI -> reservedPrivateSegmentBufferReg ( MF ) ) return ScratchRsrcReg ; unsigned NumPreloaded = ( MFI -> getNumPreloadedSGPRs ( ) + <NUM_LIT> ) / <NUM_LIT> ; ArrayRef < MCPhysReg > AllSGPR128s = TRI -> getAllSGPR128 ( MF ) ; AllSGPR128s = AllSGPR128s . slice ( std :: min ( static_cast < unsigned > ( AllSGPR128s . size ( ) ) , NumPreloaded ) ) ; Register GITPtrLoReg = MFI -> getGITPtrLoReg ( MF ) ; for ( MCPhysReg Reg : AllSGPR128s ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) && ! TRI -> isSubRegisterEq ( Reg , GITPtrLoReg ) ) { MRI . replaceRegWith ( ScratchRsrcReg , Reg ) ; MFI -> setScratchRSrcReg ( Reg ) ; return Reg ; } }


<s> if ( IsPS ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> :: ET_NULL ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; }

BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> c4x_external_ref ( XSTR ( fun , <NUM_LIT> ) ) ;


<s> MFI . stackifyVReg ( Reg ) ; } else { unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( Reg ) ) ; Def -> getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; Op . setReg ( NewReg ) ; LIS . createAndComputeVirtRegInterval ( NewReg ) ; LiveInterval & LI = LIS . getInterval ( Reg ) ; LI . removeSegment ( LIS . getInstructionIndex ( * Def ) . getRegSlot ( ) , LIS . getInstructionIndex ( * Op . getParent ( ) ) . getRegSlot ( ) , true ) ; MFI . stackifyVReg ( NewReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; Def -> dump ( ) ) ; } ImposeStackOrdering ( Def ) ; return Def ;


<s> assert ( LD -> isUnindexed ( ) && <STR_LIT> ) ; if ( MemVT == <STR_LIT> && Subtarget -> hasV5TEOps ( ) && ! Subtarget -> isThumb1Only ( ) && LD -> isVolatile ( ) ) { SDLoc dl ( N ) ;

SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LD -> getChain ( ) , LD -> getBasePtr ( ) } , MemVT , LD -> getMemOperand ( ) ) ;


<s> subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) { const_rtx x = * iter ; if ( SYMBOL_REF_P ( x ) && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) return true ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ; }


<s> <ISA_LIT>V8TargetMachine :: <ISA_LIT>V8TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM , OL , false ) {


<s> unsigned FltOpc = <STR_LIT> ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area1Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area2Register , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , true , & is<ISA_LIT>Area3Register , MachineInstr :: FrameSetup ) ; return true ;


<s> Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; bool IsZExt = isa < ZExtInst > ( I ) ; Register SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; EVT SrcEVT , DestEVT ; SrcEVT = TLI . getValueType ( DL , SrcTy , true ) ; DestEVT = TLI . getValueType ( DL , DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; Register AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = ( AssignedReg ? MRI . getRegClass ( AssignedReg ) :


<s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : fail ( DL , DAG , <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : fail ( DL , DAG , <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerCopyToReg ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAccessVectorElement ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerIntrinsic ( Op , DAG ) ;


<s> } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else if ( VT . getVectorElementType ( ) == <STR_LIT> ) { assert ( ( Subtarget -> hasBWI ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( Subtarget -> hasVLX ( ) || VT . getVectorNumElements ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( VT . getVectorNumElements ( ) , Cst ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops ) ; } else llvm_unreachable ( <STR_LIT> ) ; return DAG . getBitcast ( VT , Vec ) ;


<s> if ( non_prefixed == NON_PREFIXED_X ) return false ; rtx addr = XEXP ( mem , <NUM_LIT> ) ; enum insn_form iform = address_to_insn_form ( addr , mode , non_prefixed ) ;

return ( iform == INSN_FORM_BASE_REG || iform == INSN_FORM_D || iform == INSN_FORM_DS || iform == INSN_FORM_DQ ) ;


<s> SDValue N0 = Op -> getOperand ( <NUM_LIT> ) ; SDValue N1 = Op -> getOperand ( <NUM_LIT> ) ; EVT VT = N0 . getValueType ( ) ; if ( VT . isInteger ( ) && ! VT . isVector ( ) ) { KnownBits LHSKnown , RHSKnown ; DAG . computeKnownBits ( N0 , LHSKnown ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { DAG . computeKnownBits ( N1 , RHSKnown ) ; if ( ! ( ~ RHSKnown . Zero & ~ LHSKnown . Zero ) ) return true ; } }


<s> return ( Compare -> getNumExplicitOperands ( ) == <NUM_LIT> && Compare -> getOperand ( <NUM_LIT> ) . isImm ( ) && Compare -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ;


<s> return getSubtargetImpl ( ) -> getInstrInfo ( ) ;


<s> if ( ! isa < ConstantSDNode > ( N2 ) ) return SDValue ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ; SDValue V = Extract128BitVector ( N0 , IdxVal , DAG , dl ) ; unsigned NumEltsIn128 = <NUM_LIT> / EltVT . getSizeInBits ( ) ; unsigned IdxIn128 = IdxVal - ( IdxVal / NumEltsIn128 ) * NumEltsIn128 ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( IdxIn128 , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } if ( Subtarget -> hasSSE41 ( ) ) return LowerINSERT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( EltVT == <STR_LIT> ) return SDValue ( ) ; if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) { Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( getTypeName ( cast < ValueAsMetadata > ( Node -> getOperand ( <NUM_LIT> ) ) -> getType ( ) , mdconst :: extract < ConstantInt > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) , true ) ; } if ( Func . hasFnAttribute ( <STR_LIT> ) ) { Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( Func . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . str ( ) , true ) ; }

if ( Func . hasFnAttribute ( <STR_LIT> ) ) Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( <STR_LIT> ) ;


<s> BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addSym ( RetSymbol ) ; } else { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; } } ++ InsertPt ; if ( ! ExpectedRetAddrReg ) { ExpectedRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ExpectedRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } unsigned NewStateReg = extractPredStateFromSP ( MBB , InsertPt , Loc ) ; if ( MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Small && ! Subtarget -> isPositionIndependent ( ) ) { BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addSym ( RetSymbol ) ; } else { Register ActualRetAddrReg = MRI -> createVirtualRegister ( AddrRC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , ActualRetAddrReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addSym ( RetSymbol ) . addReg ( <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) ) . addReg ( ExpectedRetAddrReg , RegState :: Kill ) . addReg ( ActualRetAddrReg , RegState :: Kill ) ; } int PredStateSizeInBytes = TRI -> getRegSizeInBits ( * PS -> RC ) / <NUM_LIT> ; auto CMovOp = <STR_LIT> ( PredStateSizeInBytes ) ;

Register UpdatedStateReg = MRI -> createVirtualRegister ( PS -> RC ) ;


<s> bool RequiresBW ; bool HasAVX512Solution = isSupportedOnAVX512 ( VecTy , RequiresBW ) ; if ( ST -> hasAVX512 ( ) && HasAVX512Solution && ( ! RequiresBW || ST -> hasBWI ( ) ) ) return getInterleavedMemoryOpCostAVX512 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ;

if ( ST -> hasAVX2 ( ) ) return getInterleavedMemoryOpCostAVX2 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ;


<s> LowerGlobalDtors ( ) : ModulePass ( ID ) {


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> static Value * calculateVectorIndex ( Value * Ptr , const std :: map < GetElementPtrInst * , Value * > & GEPIdx ) {

GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( stripBitcasts ( Ptr ) ) ;


<s> OS << <STR_LIT> ; Mem . Base -> print ( OS ) ; OS << <STR_LIT> ; Mem . Off -> print ( OS ) ; OS << <STR_LIT> ; break ; case k_PhysRegister : OS << <STR_LIT> << PhysReg . Num << <STR_LIT> ; break ; case k_RegisterIndex : OS << <STR_LIT> << RegIdx . Index << <STR_LIT> << RegIdx . Kind << <STR_LIT> ; break ; case k_Token : OS << Tok . Data ; break ;


<s> const char * cr16_cmp_str ; switch ( GET_CODE ( x ) ) { case EQ : cr16_cmp_str = <STR_LIT> ; break ; case NE : cr16_cmp_str = <STR_LIT> ; break ; case GT : cr16_cmp_str = <STR_LIT> ; break ; case GTU : cr16_cmp_str = <STR_LIT> ; break ; case LT : cr16_cmp_str = <STR_LIT> ; break ; case LTU : cr16_cmp_str = <STR_LIT> ; break ; case GE : cr16_cmp_str = <STR_LIT> ; break ; case GEU : cr16_cmp_str = <STR_LIT> ; break ; case LE : cr16_cmp_str = <STR_LIT> ; break ; case LEU : cr16_cmp_str = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } fprintf ( file , <STR_LIT> , cr16_cmp_str ) ; return ; } case '$' : putc ( '$' , file ) ; return ; case 'p' : if ( GET_CODE ( x ) == REG ) { fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; return ; } break ; case 'b' : fprintf ( file , <STR_LIT> , INTVAL ( x ) ) ; return ; case 'r' : fprintf ( file , <STR_LIT> , cr16_operand_bit_pos ( INTVAL ( x ) , <NUM_LIT> ) ) ; return ; case 's' : fprintf ( file , <STR_LIT> , cr16_operand_bit_pos ( INTVAL ( x ) , <NUM_LIT> ) ) ; return ; case 'g' : ptr_dereference = <NUM_LIT> ; case 'f' : case <NUM_LIT> : switch ( GET_CODE ( x ) ) { case REG : if ( GET_MODE_BITSIZE ( GET_MODE ( x ) ) > BITS_PER_WORD ) { if ( LONG_REG_P ( REGNO ( x ) ) ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) + <NUM_LIT> ] , reg_names [ REGNO ( x ) ] ) ; } else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; return ; case MEM : output_address ( GET_MODE ( x ) , XEXP ( x , <NUM_LIT> ) ) ; return ; case CONST_DOUBLE : { long l ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( x ) , l ) ; fprintf ( file , <STR_LIT> , l ) ; return ; } case CONST_INT : { fprintf ( file , <STR_LIT> , INTVAL ( x ) ) ; return ; } case UNSPEC : switch ( XINT ( x , <NUM_LIT> ) ) { default : gcc_unreachable ( ) ; } break ; default : if ( ! ptr_dereference ) { putc ( '$' , file ) ; } cr16_print_operand_address ( file , VOIDmode , x ) ; return ; } gcc_unreachable ( ) ; default :


<s> case S2_asl_i_p : ImN = <NUM_LIT> ; RegN = <NUM_LIT> ; Width = <NUM_LIT> ; break ; case S2_asl_i_p_acc : case S2_asl_i_p_and : case S2_asl_i_p_nac : case S2_asl_i_p_or : case S2_asl_i_p_xacc : ImN = <NUM_LIT> ; RegN = <NUM_LIT> ; Width = <NUM_LIT> ; break ; case S2_asl_i_r : ImN = <NUM_LIT> ; RegN = <NUM_LIT> ; Width = <NUM_LIT> ; break ; case S2_addasl_rrri : case S4_andi_asl_ri : case S4_ori_asl_ri : case S4_addi_asl_ri : case S4_subi_asl_ri : case S2_asl_i_r_acc : case S2_asl_i_r_and : case S2_asl_i_r_nac : case S2_asl_i_r_or : case S2_asl_i_r_sat : case S2_asl_i_r_xacc : ImN = <NUM_LIT> ; RegN = <NUM_LIT> ; Width = <NUM_LIT> ; break ;


<s> if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( Start , IOK_LENGTH ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( Start , IOK_SIZE ) ; if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( Start , IOK_TYPE ) ; } if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Real ) || getLexer ( ) . is ( AsmToken :: Minus ) ) { const MCExpr * Val ; if ( ! getParser ( ) . parseExpression ( Val , End ) ) { return <STR_LIT> ( Val , Start , End ) ; } } unsigned RegNo = <NUM_LIT> ; if ( ! ParseRegister ( RegNo , Start , End ) ) {

if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ;


<s> <ISA_LIT>AsmPrinter :: <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & MCS ) : AsmPrinter ( TM , MCS ) , UnitStrings ( <ISA_LIT>InstrInfo :: getUnitStrings ( ) ) , ST ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , BundleMode ( ST . enablePostRAScheduler ( ) ) {


<s> TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;

TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCSubtargetInfo ) ;


<s> return new <ISA_LIT>FixCortexA57AES1742098 ( ) ;


<s> build_32_64 ( b , signature , group , MODE_none , MODE_u64index ) ;


<s> StringRef getPassName ( ) const override {


<s> virtual const char * getPassName ( ) const {


<s> case MI : return PL ; case PL : return MI ; case VS : return VC ; case VC : return VS ; case HI : return LS ; case LS : return HI ; case GE : return LT ;


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , true , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> Reloc ( R ) , Sym ( S ) , Offset ( O ) {


<s> SDWADstPreserveOperand ( MachineOperand * TargetOp , MachineOperand * ReplacedOp , MachineOperand * PreserveOp , SdwaSel DstSel_ = DWORD ) : SDWADstOperand ( TargetOp , ReplacedOp , DstSel_ , UNUSED_PRESERVE ) , Preserve ( PreserveOp ) {


<s> unsigned FPInstClass = Flags & <STR_LIT> ; if ( MI -> isInlineAsm ( ) ) FPInstClass = <STR_LIT> ; if ( MI -> isCopy ( ) && isFPCopy ( MI ) ) FPInstClass = <STR_LIT> ; if ( MI -> isImplicitDef ( ) && <STR_LIT> . contains ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) FPInstClass = <STR_LIT> ; if ( FPInstClass == <STR_LIT> ) continue ; MachineInstr * PrevMI = <NUM_LIT> ; if ( I != BB . begin ( ) ) PrevMI = std :: prev ( I ) ; ++ NumFP ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; SmallVector < unsigned , <NUM_LIT> > DeadRegs ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDead ( ) ) DeadRegs . push_back ( MO . getReg ( ) ) ; }


<s> return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , false , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertDivByZeroTrap ( MI , * BB , * Subtarget . getInstrInfo ( ) , true , false ) ; case <STR_LIT> : case <STR_LIT> :


<s> return StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> bool preferZeroCompareBranch ( ) const override { return true ;


<s> inline unsigned getImmStart ( const MCInstrDesc & MCInstD ) {

return static_cast < unsigned > ( ( MCInstD . TSFlags >> ImmStartBitStart ) & <ISA_LIT>II :: ImmStartBitMask ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( * this , is64bit ) {


<s> std :: vector < std :: string > pacr1 ( Ax a ) {


<s> LLVM_DUMP_METHOD void <ISA_LIT>WholeQuadMode :: printInfo ( ) { for ( const auto & BII : Blocks ) { dbgs ( ) << <STR_LIT> << BII . first -> getNumber ( ) << <STR_LIT> << <STR_LIT> << PrintState ( BII . second . InNeeds ) << <STR_LIT> << PrintState ( BII . second . Needs ) << <STR_LIT> << PrintState ( BII . second . OutNeeds ) << <STR_LIT> ; for ( const MachineInstr & MI : * BII . first ) {

auto III = Instructions . find ( & MI ) ;


return __builtin_ia32_rcpph512_mask ( __B , _mm512_setzero_ph ( ) , __A ) ;


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_ARM , false ) {


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> seen_barsync = true ; continue ; } if ( ! seen_barsync ) continue ; if ( NOTE_P ( insn ) || DEBUG_INSN_P ( insn ) ) continue ; else if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_fork : case CODE_FOR_nvptx_forked : case CODE_FOR_nvptx_joining : case CODE_FOR_nvptx_join : continue ; default : break ; }


<s> assert ( isPowerOf2_32 ( TyWidth ) && <STR_LIT> ) ; if ( TyWidth == <NUM_LIT> || TyWidth == <NUM_LIT> ) return PSK_FastHardware ; return PSK_Software ;


<s> <ISA_LIT>AsmTypeCheck :: <ISA_LIT>AsmTypeCheck ( MCAsmParser & Parser , const MCInstrInfo & MII , bool is64 ) : Parser ( Parser ) , MII ( MII ) , is64 ( is64 ) {


<s> void reset ( ) { Inst2Replace = nullptr ; BackedgeInst = nullptr ;


<s> MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> assert ( MemOpcodes && <STR_LIT> ) ; return MemOpcodes [ Form231 ] ;


<s> return Variant == <ISA_LIT>MCExpr :: VK_AARCH64_None || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_GOT || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_GOTTPREL || Variant == <ISA_LIT>MCExpr :: VK_AARCH64_TLSDESC ; }

return isLabel < <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> } if ( ! Val . getNode ( ) -> isMachineOpcode ( ) || Val . getNode ( ) -> getMachineOpcode ( ) == AMDGPU :: IMPLICIT_DEF ) { continue ; } const MCInstrDesc Desc = TM . getInstrInfo ( ) -> get ( Val . getNode ( ) -> getMachineOpcode ( ) ) ; const TargetRegisterInfo * TRI = TM . getRegisterInfo ( ) ; RegInfo -> setRegClass ( Reg , TRI -> getRegClass ( Desc . OpInfo [ <NUM_LIT> ] . RegClass ) ) ; continue ; } } MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( I ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; if ( ResNode != Node ) { ReplaceUses ( Node , ResNode ) ;


<s> unsigned int alignment ; alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ; if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ; return alignment ;


<s> if ( ( GET_CODE ( x ) == SYMBOL_REF ) && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_FUNCVEC_FUNCTION ) ) { t = SYMBOL_REF_DECL ( x ) ; if ( TREE_CODE ( t ) != FUNCTION_DECL ) return <NUM_LIT> ; list = SH_ATTRIBUTES ( t ) ;


<s> if ( x == tocrel_base_oac && tocrel_offset_oac != const0_rtx ) { if ( INTVAL ( tocrel_offset_oac ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , CONST_CAST_RTX ( tocrel_offset_oac ) ) ; } if ( ! TARGET_AIX || ( TARGET_ELF && TARGET_MINIMAL_TOC ) ) { putc ( '-' , file ) ; assemble_name ( file , toc_label_name ) ; need_toc_init = <NUM_LIT> ; } else if ( TARGET_ELF ) fputs ( <STR_LIT> , file ) ; return true ; case UNSPEC_MACHOPIC_OFFSET : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; putc ( '-' , file ) ; machopic_output_function_base_name ( file ) ; return true ; } return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI . isInvariantLoad ( AA ) ) { unsigned BaseReg = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> :


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & , const MCTargetOptions & ) { const Triple & TT = STI . getTargetTriple ( ) ;

if ( ! TT . isOSBinFormatELF ( ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>PassConfig :: addILPOpts ( ) {


<s> if ( ( GET_CODE ( in ) == MEM || ( GET_CODE ( in ) == REG && REGNO ( in ) >= FIRST_PSEUDO_REGISTER ) || ( GET_CODE ( in ) == SUBREG && GET_CODE ( SUBREG_REG ( in ) ) == REG && REGNO ( SUBREG_REG ( in ) ) >= FIRST_PSEUDO_REGISTER ) ) && ( mode == QImode || mode == HImode ) && ( class == ADDRESS_REGS || class == SP_REGS || class == SP_OR_ADDRESS_REGS ) ) { if ( TARGET_AM33 ) return DATA_OR_EXTENDED_REGS ; return DATA_REGS ; } if ( class != SP_REGS && class != ADDRESS_REGS && class != SP_OR_ADDRESS_REGS && class != SP_OR_EXTENDED_REGS && class != ADDRESS_OR_EXTENDED_REGS && class != SP_OR_ADDRESS_OR_EXTENDED_REGS && ( in == stack_pointer_rtx || ( GET_CODE ( in ) == PLUS && ( XEXP ( in , <NUM_LIT> ) == stack_pointer_rtx || XEXP ( in , <NUM_LIT> ) == stack_pointer_rtx ) ) ) ) return ADDRESS_REGS ; if ( GET_CODE ( in ) == PLUS && ( XEXP ( in , <NUM_LIT> ) == stack_pointer_rtx || XEXP ( in , <NUM_LIT> ) == stack_pointer_rtx ) ) { if ( TARGET_AM33 ) return DATA_OR_EXTENDED_REGS ; return DATA_REGS ;


<s> else Register = RegisterTableSPU [ RegNo ] ; if ( Register == ~ <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> ConstantSDNode * IMMOffset ; if ( Addr . getOpcode ( ) == <STR_LIT> && ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( IMMOffset -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } else if ( ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) {

Base = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( CurDAG -> getEntryNode ( ) ) , AMDGPU :: ZERO , <STR_LIT> ) ;


<s> return __builtin_mve_vcmulq_rot180_m_fv8hf ( __arm_vuninitializedq_f16 ( ) , __a , __b , __p ) ;


<s> if ( d -> perm [ <NUM_LIT> ] < nelt ) return ; for ( unsigned i = <NUM_LIT> ; i != nelt ; i ++ ) d -> perm [ i ] = ( d -> perm [ i ] + nelt ) % ( <NUM_LIT> * nelt ) ; std :: swap ( d -> op0 , d -> op1 ) ;


<s> __o = __builtin_aarch64_ld3v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ;

ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ;


<s> for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; if ( SrcVT == <STR_LIT> ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SrcReg , <NUM_LIT> , <STR_LIT> ) ; SrcReg = ResultReg ; } UpdateValueMap ( I , SrcReg ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath ; if ( ! Unsafe && VT == <STR_LIT> && Subtarget -> hasFP32Denormals ( ) ) return SDValue ( ) ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( Unsafe || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } if ( CLHS -> isExactlyValue ( - <NUM_LIT> ) ) { SDValue FNegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , FNegRHS ) ; } } }

const SDNodeFlags * Flags = Op -> getFlags ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>SEISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) {

return new <ISA_LIT>SEDAGToDAGISel ( TM , OptLevel ) ;


<s> MachineInstr * LoopEnd , * LoopPhi , * LoopStart , * LoopDec ; if ( ! findLoopComponents ( ML , MRI , LoopStart , LoopPhi , LoopDec , LoopEnd ) ) return false ; if ( LoopDec != LoopEnd || LoopStart -> getOpcode ( ) != <STR_LIT> ) return false ; SmallVector < MachineInstr * , <NUM_LIT> > VCTPs ; for ( MachineBasicBlock * BB : ML -> blocks ( ) ) for ( MachineInstr & MI : * BB ) if ( isVCTP ( & MI ) ) VCTPs . push_back ( & MI ) ; if ( VCTPs . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineInstr * FirstVCTP = * VCTPs . begin ( ) ; for ( MachineInstr * VCTP : VCTPs ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VCTP ) ; if ( VCTP -> getOpcode ( ) != FirstVCTP -> getOpcode ( ) || VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) != FirstVCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } Register CountReg = FirstVCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! CountReg . isVirtual ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineInstr * Phi = LookThroughCOPY ( MRI -> getVRegDef ( CountReg ) , MRI ) ; if ( ! Phi || Phi -> getOpcode ( ) != TargetOpcode :: PHI || Phi -> getNumOperands ( ) != <NUM_LIT> || ( Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getLoopLatch ( ) && Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getLoopLatch ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CountReg = Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) == ML -> getLoopLatch ( ) ? Phi -> getOperand ( <NUM_LIT> ) . getReg ( ) : Phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = LoopStart -> getParent ( ) ; MachineBasicBlock :: iterator InsertPt = MBB -> getFirstTerminator ( ) ; for ( MachineInstr & Use : MRI -> use_instructions ( LoopStart -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) if ( ( InsertPt != MBB -> end ( ) && ! DT -> dominates ( & * InsertPt , & Use ) ) || ! DT -> dominates ( ML -> getHeader ( ) , Use . getParent ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }

MachineInstrBuilder MI = BuildMI ( * MBB , InsertPt , LoopStart -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( LoopStart -> getOperand ( <NUM_LIT> ) ) . add ( LoopStart -> getOperand ( <NUM_LIT> ) ) . addReg ( CountReg ) ;


<s> return ( int8x8_t ) __builtin_aarch64_raddhnv8hi ( __a , __b ) ;


if ( whichway ( dst , src ) < <NUM_LIT> ) return <STR_LIT> ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printAddSubImmLSL0Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Imm12Op = MI -> getOperand ( OpNum ) ; if ( Imm12Op . isImm ( ) ) { int64_t Imm12 = Imm12Op . getImm ( ) ; assert ( Imm12 >= <NUM_LIT> && <STR_LIT> ) ; O << <STR_LIT> << Imm12 ;


<s> else return Field >= <NUM_LIT> && Field <= <NUM_LIT> ;


<s> break ; case MachineOperand :: MO_Register : if ( Subtarget -> useRetpolineIndirectCalls ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst CallInst ; CallInst . setOpcode ( CallOpcode ) ; CallInst . addOperand ( CallTargetMCOp ) ;

OutStreamer -> EmitInstruction ( CallInst , getSubtargetInfo ( ) ) ;


<s> if ( SR1 ) * SR1 = R0 ; if ( SR2 ) { assert ( SR1 && <STR_LIT> ) ; * SR2 = R12 ; } if ( ( UseAtEnd && MBB -> isReturnBlock ( ) ) || ( ! UseAtEnd && ( & MBB -> getParent ( ) -> front ( ) == MBB ) ) ) return true ; RS . enterBasicBlock ( MBB ) ; if ( UseAtEnd && ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator MBBI = MBB -> getFirstTerminator ( ) ; if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) && ! RS . isRegUsed ( R12 ) ) return true ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MBB -> getParent ( ) ) ; BitVector BV = RS . getRegsAvailable ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; for ( int i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) BV . reset ( CSRegs [ i ] ) ; if ( SR1 ) { int FirstScratchReg = BV . find_first ( ) ; * SR1 = FirstScratchReg == - <NUM_LIT> ? ( unsigned ) <STR_LIT> : FirstScratchReg ; }


<s> void <ISA_LIT>TTI :: getUnrollingPreferences ( const Function * F , Loop * L , UnrollingPreferences & UP ) const { UP . PartialOptSizeThreshold = <NUM_LIT> ;


<s> return type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == VECTOR_TYPE ) ;


<s> MachineFunction & MF = * MI . getMF ( ) ; auto Val = MF . getRegInfo ( ) . createGenericVirtualRegister ( LLT :: scalar ( VaListSize * <NUM_LIT> ) ) ; MachineIRBuilder MIB ( MI ) ; MIB . buildLoad ( Val , MI . getOperand ( <NUM_LIT> ) , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , VaListSize , Align ( PtrSize ) ) ) ; MIB . buildStore ( Val , MI . getOperand ( <NUM_LIT> ) , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , VaListSize , Align ( PtrSize ) ) ) ; MI . eraseFromParent ( ) ; return true ; } case <STR_LIT> : { MachineIRBuilder & MIB = Helper . MIRBuilder ; MIB . buildConstant ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ; MI . eraseFromParent ( ) ;


<s> __builtin_ia32_pmovusqw128mem_mask ( ( unsigned int * ) __P , ( __v2di ) __A , __M ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> unsigned createPICLabelUId ( ) { return PICLabelUId ++ ;


<s> case TargetOpcode :: G_STORE : { bool Changed = contractCrossBankCopyIntoStore ( I , MRI ) ; MachineOperand & SrcOp = I . getOperand ( <NUM_LIT> ) ; if ( MRI . getType ( SrcOp . getReg ( ) ) . isPointer ( ) ) { auto Copy = MIB . buildCopy ( LLT :: scalar ( <NUM_LIT> ) , SrcOp ) ; Register NewSrc = Copy . getReg ( <NUM_LIT> ) ; SrcOp . setReg ( NewSrc ) ; RBI . constrainGenericRegister ( NewSrc , <STR_LIT> , MRI ) ; Changed = true ; } return Changed ; } case TargetOpcode :: G_PTR_ADD : return convertPtrAddToAdd ( I , MRI ) ; case TargetOpcode :: G_LOAD : { Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; if ( ! DstTy . isPointer ( ) ) return false ; MRI . setType ( DstReg , LLT :: scalar ( <NUM_LIT> ) ) ; return true ; } case <STR_LIT> : { LLT DstTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! DstTy . getElementType ( ) . isPointer ( ) ) return false ; auto NewSrc = MIB . buildCopy ( LLT :: scalar ( <NUM_LIT> ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MRI . setType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , DstTy . changeElementType ( LLT :: scalar ( <NUM_LIT> ) ) ) ; MRI . setRegClass ( NewSrc . getReg ( <NUM_LIT> ) , & <STR_LIT> ) ; I . getOperand ( <NUM_LIT> ) . setReg ( NewSrc . getReg ( <NUM_LIT> ) ) ; return true ; } case TargetOpcode :: G_UITOFP : case TargetOpcode :: G_SITOFP : { Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT SrcTy = MRI . getType ( SrcReg ) ; LLT DstTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( SrcTy . isVector ( ) || SrcTy . getSizeInBits ( ) != DstTy . getSizeInBits ( ) ) return false ; if ( RBI . getRegBank ( SrcReg , MRI , TRI ) -> getID ( ) == <STR_LIT> ) { if ( I . getOpcode ( ) == TargetOpcode :: G_SITOFP ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else I . setDesc ( TII . get ( <STR_LIT> ) ) ; return true ; } return false ; }


<s> switch ( Opcode ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> <ISA_LIT>LETargetMachine :: <ISA_LIT>LETargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> tree subtype = TREE_TYPE ( eff_type ) ; tree real , imag ; imag = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; imag = get_initialized_tmp_var ( imag , pre_p , NULL ) ; real = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; real = get_initialized_tmp_var ( real , pre_p , NULL ) ; result = build2 ( COMPLEX_EXPR , eff_type , real , imag ) ; if ( type != eff_type ) result = build1 ( VIEW_CONVERT_EXPR , type , result ) ; result = get_initialized_tmp_var ( result , pre_p , NULL ) ; } tmp = build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_false ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_stack ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , unshare_expr ( valist ) , pre_p ) ; gimplify_assign ( unshare_expr ( valist ) , unshare_expr ( next_fp_tmp ) , post_p ) ; valist = next_fp_tmp ; } else { tmp = fold_build_pointer_plus_hwi ( unshare_expr ( next_o ) , rsize ) ; tmp = build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( next_o_limit ) ) ; tmp = build3 ( COND_EXPR , void_type_node , tmp , build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_false ) ) , NULL_TREE ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_o ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; tmp = build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_false ) ) ; gimplify_and_add ( tmp , pre_p ) ; if ( size > <NUM_LIT> && ! ( TARGET_SH4 || TARGET_SH2A ) ) gimplify_assign ( unshare_expr ( next_o ) , unshare_expr ( next_o_limit ) , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_stack ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; } if ( ! result ) { tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; } } tmp = std_gimplify_va_arg_expr ( valist , type , pre_p , NULL ) ; if ( result ) { gimplify_assign ( result , tmp , pre_p ) ; result = build1 ( NOP_EXPR , TREE_TYPE ( result ) , result ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_over ) ) ;


<s> SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ && ! Subtarget -> is64Bit ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Result ) ; } if ( isGlobalStubReference ( OpFlag ) ) Result = DAG . getLoad ( getPointerTy ( ) , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> void <ISA_LIT>64elTargetMachine :: anchor ( ) {


<s> Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; const MCExpr * SubExpr ;

if ( getParser ( ) . parseParenExpression ( SubExpr , E ) ) {


<s> break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = LowerSymbolOperand ( MO , GetBlockAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , GetJumpTableSymbol ( MO ) ) ;


<s> static bool arm_function_value_regno_p ( const unsigned int regno ) {

if ( regno == ARG_REGISTER ( <NUM_LIT> ) || ( TARGET_32BIT && TARGET_AAPCS_BASED && TARGET_HARD_FLOAT && regno == FIRST_VFP_REGNUM ) || ( TARGET_IWMMXT_ABI && regno == FIRST_IWMMXT_REGNUM ) ) return true ;


<s> <ISA_LIT>WinCOFFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > AB , std :: unique_ptr < MCCodeEmitter > CE , raw_pwrite_stream & OS ) : MCWinCOFFStreamer ( C , std :: move ( AB ) , std :: move ( CE ) , OS ) {


<s> MRI . setSimpleHint ( Data0 , Src -> getReg ( ) ) ; } BuildMI ( * LoopBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * LoopBB , I , DL , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( EncodedReg ) ; BuildMI ( * LoopBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LoopBB , I , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( LoopBB ) ;


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getHiLo16ImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; const MCExpr * E = MO . getExpr ( ) ; if ( E -> getKind ( ) == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>16Expr = cast < <ISA_LIT>MCExpr > ( E ) ; E = <ISA_LIT>16Expr -> getSubExpr ( ) ; MCFixupKind Kind ; switch ( <ISA_LIT>16Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 : if ( ! isTargetDarwin ( ) && EvaluateAsPCRel ( E ) ) Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; else Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 : if ( ! isTargetDarwin ( ) && EvaluateAsPCRel ( E ) ) Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; else Kind = MCFixupKind ( isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ) ; break ; } Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , E , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } ; llvm_unreachable ( <STR_LIT> ) ;


<s> mask = spu_or ( mask , spu_xor ( ( vec_uint4 ) ( spu_rlmaska ( spu_add ( exp , - <NUM_LIT> ) , - <NUM_LIT> ) ) , - <NUM_LIT> ) ) ;

return ( spu_andc ( a , ( vec_float4 ) ( mask ) ) ) ;


<s> if ( ! IsMemcpySmall ( Len ) ) return false ; bool i64Legal = Subtarget -> is64Bit ( ) ; while ( Len ) { MVT VT ; if ( Len >= <NUM_LIT> && i64Legal ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else if ( Len >= <NUM_LIT> ) VT = <STR_LIT> ; else { assert ( Len == <NUM_LIT> ) ; VT = <STR_LIT> ; } unsigned Reg ; bool RV = <ISA_LIT>FastEmitLoad ( VT , SrcAM , nullptr , Reg ) ; RV &= <ISA_LIT>FastEmitStore ( VT , Reg , true , DestAM ) ; assert ( RV && <STR_LIT> ) ; unsigned Size = VT . getSizeInBits ( ) / <NUM_LIT> ;


return val . coeffs [ <NUM_LIT> ] + val . coeffs [ <NUM_LIT> ] * over_128 / <NUM_LIT> ;


<s> return true ; case FK_Data_8 : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_Branch24Bit ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_ThumbBranch22Bit ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_ThumbBranch22Bit ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ;


<s> bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) ) MadeChange |= optimizeThumb2Branches ( ) ; if ( GenerateTBB && ! STI -> genExecuteOnly ( ) ) MadeChange |= optimizeThumb2JumpTables ( ) ; verify ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; if ( CPE . CPEMI && CPE . CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) AFI -> recordCPEClone ( i , CPE . CPI ) ; } } LLVM_DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBUtils -> clear ( ) ;


if ( isSingleInputShuffleMask ( Mask ) ) {


<s> MachineInstrBuilder MIB = BuildMI ( & MBB , DL , MCID ) ; for ( unsigned i = <NUM_LIT> ; i < Cond . size ( ) ; ++ i ) { if ( Cond [ i ] . isReg ( ) ) MIB . addReg ( Cond [ i ] . getReg ( ) ) ; else if ( Cond [ i ] . isImm ( ) ) MIB . addImm ( Cond [ i ] . getImm ( ) ) ; else assert ( false && <STR_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> pass_remove_partial_avx_dependency ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_remove_partial_avx_dependency , ctxt ) {


<s> } else { R1 = Addr ; R2 = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; } else { R1 = Addr ; R2 = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; } return true ;


<s> void ThumbBETargetMachine :: anchor ( ) {


<s> if ( Bits == <NUM_LIT> ) Bits = <NUM_LIT> ; uint32_t FullValue = fullValue ( * Disassembler . MCII , * * Disassembler . CurrentBundle , MI , SignExtend64 ( tmp , Bits ) ) ; int64_t Extended = SignExtend64 < <NUM_LIT> > ( FullValue ) + Address ;

if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> if ( NumBytes == <NUM_LIT> && DestReg != BaseReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; return ; } bool isSub = NumBytes < <NUM_LIT> ;


<s> auto B = bit_cast < std :: array < int8_t , <NUM_LIT> >> ( Imm ) ; if ( isSVEMaskOfIdenticalElements < int32_t > ( Imm ) && isSVECpyImm < int32_t > ( S [ <NUM_LIT> ] ) ) return false ; if ( isSVEMaskOfIdenticalElements < int16_t > ( Imm ) && isSVECpyImm < int16_t > ( H [ <NUM_LIT> ] ) ) return false ; if ( isSVEMaskOfIdenticalElements < int8_t > ( Imm ) && isSVECpyImm < int8_t > ( B [ <NUM_LIT> ] ) ) return false ; return isLogicalImmediate ( Imm , <NUM_LIT> ) ;


<s> unsigned getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const override { case <STR_LIT> ## X : \ return ELF :: R_<ISA_LIT>_ ## X switch ( ( unsigned ) Fixup . getKind ( ) ) { FIXUP ( NONE ) ; FIXUP ( PC2_12 ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ReserveAppRegisters ) Reserved . set ( <STR_LIT> ) ; if ( ReserveAppRegisters || ! Subtarget . is64Bit ( ) ) Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> static rtx aarch64_emit_move ( rtx dest , rtx src ) {

return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isInt < <NUM_LIT> > ( BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OS . write ( <STR_LIT> , <NUM_LIT> ) ;


<s> EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValArg != <ISA_LIT>CCInfo . byval_end ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , <ISA_LIT>CCInfo , * ByValArg ) ; ++ ByValArg ; continue ; } if ( IsRegLoc ) { MVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; else if ( Subtarget . isABI_O32 ( ) && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = addLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , DL , Reg2 , RegVT ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ;

ArgValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArgValue , ArgValue2 ) ;


<s> unsigned CarryInReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; if ( DstTy != LLT :: scalar ( <NUM_LIT> ) ) return false ; MachineInstr * Def = MRI . getVRegDef ( CarryInReg ) ; while ( Def -> getOpcode ( ) == TargetOpcode :: G_TRUNC ) { CarryInReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Def = MRI . getVRegDef ( CarryInReg ) ; } unsigned Opcode ; if ( Def -> getOpcode ( ) == TargetOpcode :: G_UADDE ) { BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CarryInReg ) ;

if ( ! RBI . constrainGenericRegister ( CarryInReg , <STR_LIT> , MRI ) ) return false ;


<s> auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) , UnwindHelpFI ) . addImm ( - <NUM_LIT> ) ;


<s> unsigned Reg = getLdStRegOp ( FirstMI ) . getReg ( ) ; unsigned BaseReg = getLdStBaseOp ( FirstMI ) . getReg ( ) ; int Offset = getLdStOffsetOp ( FirstMI ) . getImm ( ) ; int OffsetStride = IsUnscaled ? getMemScale ( FirstMI ) : <NUM_LIT> ; bool IsPromotableZeroStore = isPromotableZeroStoreInst ( FirstMI ) ; ModifiedRegs . reset ( ) ; UsedRegs . reset ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > MemInsns ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI . mayLoadOrStore ( ) && <STR_LIT> ) ; unsigned MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) { TII -> trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { TII -> trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { TII -> trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { TII -> trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM ) ;


<s> auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , Align ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ;


<s> assert ( StartIdx == StartIdx2 && <STR_LIT> ) ; } unsigned ScratchIdx = StartIdx , e = MI . getNumOperands ( ) ; while ( ScratchIdx < e && ! ( MI . getOperand ( ScratchIdx ) . isReg ( ) && MI . getOperand ( ScratchIdx ) . isDef ( ) && MI . getOperand ( ScratchIdx ) . isImplicit ( ) && MI . getOperand ( ScratchIdx ) . isEarlyClobber ( ) ) ) ++ ScratchIdx ; assert ( ScratchIdx != e && <STR_LIT> ) ; int64_t ID = MI . getOperand ( StartIdx ) . getImm ( ) ; assert ( ( int32_t ) ID == ID && <STR_LIT> ) ; bool isAnyRegCC = MI . getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) == CallingConv :: AnyReg ; assert ( ( ( hasDef && isAnyRegCC ) || ! hasDef ) && <STR_LIT> ) ; int64_t StackMapIdx = isAnyRegCC ? StartIdx + <NUM_LIT> : StartIdx + <NUM_LIT> + MI . getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) ; assert ( StackMapIdx <= MI . getNumOperands ( ) && <STR_LIT> ) ; SM . recordStackMap ( MI , ID , llvm :: next ( MI . operands_begin ( ) , StackMapIdx ) , getStackMapEndMOP ( MI . operands_begin ( ) , MI . operands_end ( ) ) , isAnyRegCC && hasDef ) ; unsigned EncodedBytes = <NUM_LIT> ;

int64_t CallTarget = MI . getOperand ( StartIdx + <NUM_LIT> ) . getImm ( ) ;


<s> bool might_split_p ; rtx set ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( mem ) ; might_split_p = true ; if ( GET_MODE_BITSIZE ( mode ) . to_constant ( ) <= <NUM_LIT> ) might_split_p = false ; else if ( GET_MODE_BITSIZE ( mode ) . to_constant ( ) == <NUM_LIT> ) { set = single_set ( insn ) ; if ( set && ! riscv_split_64bit_move_p ( SET_DEST ( set ) , SET_SRC ( set ) ) ) might_split_p = false ; }

return riscv_address_insns ( XEXP ( mem , <NUM_LIT> ) , mode , might_split_p ) ;


<s> ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) ? V8SImode : V4SImode ; case DImode : return TARGET_AVX512F ? V8DImode : ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) ? V4DImode : V2DImode ; case SFmode : if ( TARGET_AVX512F ) return V16SFmode ; else if ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) return V8SFmode ; else return V4SFmode ; case DFmode :

if ( ! TARGET_VECTORIZE_DOUBLE ) return word_mode ;


<s> bool <ISA_LIT>PacketizerList :: cannotCoexist ( const MachineInstr * MI , const MachineInstr * MJ ) {

return cannotCoexistAsymm ( MI , MJ , * HII ) || cannotCoexistAsymm ( MJ , MI , * HII ) ;


<s> <STR_LIT> From = getSimpleType ( V -> getType ( ) ) ; <STR_LIT> To = getLegalType ( From ) ; Register VReg = getRegForValue ( V ) ;

if ( VReg == <NUM_LIT> ) return <NUM_LIT> ;


<s> static __inline void _mm_empty ( void ) { __builtin_ia32_emms ( ) ;


<s>
bool
<ISA_LIT>MCAsmStreamer
::
EmitDwarfFileDirective
(
unsigned
FileNo
,
StringRef
Filename
)
{
OS
<<
<STR_LIT>
<<
FileNo
<<
' '
;
PrintQuotedString
(
Filename
,
OS
)
;
EmitEOL
(
)
;

return this -> MCStreamer :: EmitDwarfFileDirective ( FileNo , Filename ) ;


<s> unsigned GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MBBI != FirstMBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; unsigned PC = RegInfo . createVirtualRegister ( <STR_LIT> ) ; const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , PC ) . addImm ( <NUM_LIT> ) ;

if ( TM . getRelocationModel ( ) == Reloc :: PIC_ && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isPICStyleGOT ( ) ) {


<s> SCAEdge newEdge ( parent , this , site ) ; parent -> Children . insert ( newEdge ) ;


<s> } if ( ( ( Imm % <NUM_LIT> ) == <NUM_LIT> ) && ( Imm >= - <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { Base = CurDAG -> getTargetConstant ( Imm / <NUM_LIT> , DL , Ty ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , Ty ) ; return true ;


<s> const GlobalAddressSDNode * GADN = dyn_cast < GlobalAddressSDNode > ( OP1N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; const ConstantSDNode * CDN = dyn_cast < ConstantSDNode > ( OP2 . getNode ( ) ) ; if ( GADN && CDN ) to_replace = getConstantFieldValue ( GADN , CDN -> getZExtValue ( ) , size , new_val . c ) ; } else if ( LDAddrNode -> getOpcode ( ) > <STR_LIT> && LDAddrNode -> getNumOperands ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; LD -> dump ( ) ; dbgs ( ) << '\n' ) ; SDValue OP1 = LDAddrNode -> getOperand ( <NUM_LIT> ) ; if ( const GlobalAddressSDNode * GADN = dyn_cast < GlobalAddressSDNode > ( OP1 . getNode ( ) ) ) to_replace = getConstantFieldValue ( GADN , <NUM_LIT> , size , new_val . c ) ; } if ( ! to_replace ) return ; uint64_t val ; if ( size == <NUM_LIT> ) val = new_val . c [ <NUM_LIT> ] ; else if ( size == <NUM_LIT> ) val = new_val . s ; else if ( size == <NUM_LIT> ) val = new_val . i ; else { val = new_val . d ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << size << <STR_LIT> << val << '\n' ) ; SDValue NVal = CurDAG -> getConstant ( val , DL , LD -> getValueType ( <NUM_LIT> ) ) ; I -- ; SDValue From [ ] = { SDValue ( Node , <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) } ; SDValue To [ ] = { NVal , NVal } ; CurDAG -> ReplaceAllUsesOfValuesWith ( From , To , <NUM_LIT> ) ;


<s> void <ISA_LIT>AsmPrinter :: customEmitInstruction ( const MachineInstr * MI ) { <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCSubtargetInfo STI = getSubtargetInfo ( ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ;

OutStreamer -> EmitInstruction ( TmpInst , STI ) ;


<s> assert ( ACPV -> isGlobalValue ( ) && <STR_LIT> ) ; const GlobalValue * GV = ACPV -> getGV ( ) ; if ( GV ) { Reloc :: Model RelocM = TM . getRelocationModel ( ) ; emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) , ( intptr_t ) ACPV ) ; } else { emitExternalSymbolAddress ( ACPV -> getSymbol ( ) , <STR_LIT> ) ; } emitWordLE ( <NUM_LIT> ) ; } else { const Constant * CV = MCPE . Val . ConstVal ; DEBUG ( { errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( CV ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * CV ; errs ( ) << '\n' ; } ) ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { emitGlobalAddress ( GV , <STR_LIT> , isa < Function > ( GV ) , false ) ; emitWordLE ( <NUM_LIT> ) ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint32_t Val = uint32_t ( * CI -> getValue ( ) . getRawData ( ) ) ; emitWordLE ( Val ) ; } else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( CV ) ) { if ( CFP -> getType ( ) -> isFloatTy ( ) ) emitWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else if ( CFP -> getType ( ) -> isDoubleTy ( ) ) emitDWordLE ( CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else {


<s> for ( unsigned I = <NUM_LIT> , E = Sig -> Params . size ( ) ; I < E ; I ++ ) Ret += getInvokeSig ( Sig -> Params [ I ] ) ;


<s> * code = EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == HFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quiethfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == HFmode ) \ emit_insn ( gen_f ## CMP ## _quiethfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ;


<s> unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; EFlags |= getEFlagsForFeatureSet ( STI . getFeatureBits ( ) ) ;


<s> MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: <ISA_LIT>_SPILL_V512_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V256_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V128_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V96_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V64_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_V32_SAVE : buildScratchLoadStore ( MI , AMDGPU :: BUFFER_STORE_DWORD_OFFSET , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: src ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_rsrc ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_offset ) -> getReg ( ) , FrameInfo -> getObjectOffset ( Index ) , RS ) ; MI -> eraseFromParent ( ) ; break ; case AMDGPU :: <ISA_LIT>_SPILL_V32_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V64_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V96_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V128_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V256_RESTORE : case AMDGPU :: <ISA_LIT>_SPILL_V512_RESTORE : { buildScratchLoadStore ( MI , AMDGPU :: BUFFER_LOAD_DWORD_OFFSET , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: dst ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_rsrc ) -> getReg ( ) , TII -> getNamedOperand ( * MI , AMDGPU :: OpName :: scratch_offset ) -> getReg ( ) , FrameInfo -> getObjectOffset ( Index ) , RS ) ; MI -> eraseFromParent ( ) ; break ; } default : { int64_t Offset = FrameInfo -> getObjectOffset ( Index ) ; FIOp . ChangeToImmediate ( Offset ) ; if ( ! TII -> isImmOperandLegal ( MI , FIOperandNum , FIOp ) ) { unsigned TmpReg = RS -> scavengeRegister ( & AMDGPU :: VGPR_32RegClass , MI , SPAdj ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , TmpReg ) . addImm ( Offset ) ;

FIOp . ChangeToRegister ( TmpReg , false , false , true ) ;


<s> if ( results [ class ] [ mode ] == <NUM_LIT> ) { int r , n , i ; results [ class ] [ mode ] = <NUM_LIT> ;

for ( r = <NUM_LIT> ; r < FIRST_PSEUDO_REGISTER ; r ++ ) if ( class_contents [ class ] [ <NUM_LIT> ] & ( <NUM_LIT> << r ) && HARD_REGNO_MODE_OK ( r , mode ) ) {


<s> fprintf ( file , <STR_LIT> ) ; assemble_name ( file , name ) ; fprintf ( file , <STR_LIT> , public ? ( int ) C_EXT : ( int ) C_STAT , ( int ) DT_FCN << N_BTSHFT ) ;


<s> } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; <STR_LIT> AddSub = <STR_LIT> ; if ( RHSC < <NUM_LIT> ) { AddSub = <STR_LIT> ; RHSC = - RHSC ; }

Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( AddSub , RHSC ) , <STR_LIT> ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ;


<s> t2 = REGNO ( rt2 ) ; n = REGNO ( rn ) ; if ( ( TARGET_THUMB2 ) && ( ( wback && ( n == t || n == t2 ) ) || ( t == SP_REGNUM ) || ( t == PC_REGNUM ) || ( t2 == SP_REGNUM ) || ( t2 == PC_REGNUM ) || ( ! load && ( n == PC_REGNUM ) ) || ( load && ( t == t2 ) ) || ( ! wback && load && fix_cm3_ldrd && ( n == t ) ) ) ) return false ;

if ( ( TARGET_ARM ) && ( ( wback && ( n == t || n == t2 ) ) || ( t2 == PC_REGNUM ) || ( t % <NUM_LIT> != <NUM_LIT> ) || ( t2 != t + <NUM_LIT> ) || ( n == PC_REGNUM ) ) ) return false ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , unsigned SrcReg , bool KillSrc ) const { assert ( <STR_LIT> . contains ( DstReg , SrcReg ) && <STR_LIT> ) ;

BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ;


<s> if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return <NUM_LIT> ; if ( ! s390_short_displacement ( addr . disp ) ) return <NUM_LIT> ; } break ; case 'S' : if ( ! TARGET_LONG_DISPLACEMENT ) return <NUM_LIT> ; if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return <NUM_LIT> ; if ( addr . indx ) return <NUM_LIT> ; if ( s390_short_displacement ( addr . disp ) ) return <NUM_LIT> ; break ; case 'T' : if ( ! TARGET_LONG_DISPLACEMENT ) return <NUM_LIT> ; if ( ( decomposed || s390_decompose_address ( op , & addr ) ) && s390_short_displacement ( addr . disp ) ) return <NUM_LIT> ; break ; default : return <NUM_LIT> ; } return <NUM_LIT> ;


<s> } if ( C . CallConstructionID == MachineOutlinerNoLRSave || C . CallConstructionID == MachineOutlinerThunk ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; return It ; } MachineBasicBlock :: iterator CallPt ; MachineInstr * STRXpre = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; It = MBB . insert ( It , STRXpre ) ; It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; CallPt = It ; It ++ ;

MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> static bool arm_output_ttype ( rtx x ) {


<s> assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ;


<s> O << ( unsigned ) MI -> getOperand ( OpNo ) . getImm ( ) ;


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) switch ( Constraint [ <NUM_LIT> ] ) { case 'r' :

return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;


<s> if ( SUBREG_P ( op ) && MEM_P ( SUBREG_REG ( op ) ) && ( GET_MODE_SIZE ( GET_MODE ( op ) ) > GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( op ) ) ) ) ) {


<s> int i ; rtx regs [ <NUM_LIT> ] ; i = <NUM_LIT> ; regs [ i ++ ] = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; if ( hard_frame_needed ) regs [ i ++ ] = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( ! ( REGNO ( fp ) == STACK_POINTER_REGNUM || ( hard_frame_needed && REGNO ( fp ) == HARD_FRAME_POINTER_REGNUM ) ) ) regs [ i ++ ] = fp ; p = rtvec_alloc ( i ) ; while ( -- i >= <NUM_LIT> ) {

rtx mem = gen_frame_mem ( BLKmode , regs [ i ] ) ;


bool Res = compressInst ( CInst , Inst , * Subtarget , OutStreamer -> getContext ( ) ) ;


<s> return RC == & <STR_LIT> || RC == & <STR_LIT> ;


<s> bool <ISA_LIT>AsmParser :: parsePrefix ( <ISA_LIT>MCExpr :: VariantKind & RefKind ) { MCAsmParser & Parser = getParser ( ) ; RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( getLexer ( ) . is ( AsmToken :: Hash ) ) Parser . Lex ( ) ; assert ( getLexer ( ) . is ( AsmToken :: Colon ) && <STR_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } enum { COFF = ( <NUM_LIT> << MCObjectFileInfo :: IsCOFF ) , ELF = ( <NUM_LIT> << MCObjectFileInfo :: IsELF ) , MACHO = ( <NUM_LIT> << MCObjectFileInfo :: IsMachO ) } ; static const struct PrefixEntry { const char * Spelling ; <ISA_LIT>MCExpr :: VariantKind VariantKind ; uint8_t SupportedFormats ; } PrefixEntries [ ] = { { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 , COFF | ELF | MACHO } , { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 , COFF | ELF | MACHO } , } ; StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; const auto & Prefix = std :: find_if ( std :: begin ( PrefixEntries ) , std :: end ( PrefixEntries ) , [ & IDVal ] ( const PrefixEntry & PE ) { return PE . Spelling == IDVal ; } ) ; if ( Prefix == std :: end ( PrefixEntries ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } uint8_t CurrentFormat ; switch ( getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ) { case MCObjectFileInfo :: IsMachO : CurrentFormat = MACHO ; break ; case MCObjectFileInfo :: IsELF : CurrentFormat = ELF ; break ; case MCObjectFileInfo :: IsCOFF : CurrentFormat = COFF ; break ; } if ( ~ Prefix -> SupportedFormats & CurrentFormat ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } RefKind = Prefix -> VariantKind ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; }


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> } aa ; aa . v = ( vector signed int ) ( a ) ; if ( aa . i [ <NUM_LIT> ] > b ) { SPU_HALT_ACTION ; } ;


<s> void <ISA_LIT>MachineFunctionInfo :: anchor ( ) {


<s> ASM_GENERATE_INTERNAL_LABEL ( begin_label_name , FUNC_BEGIN_PROLOG_LABEL , label_no ) ; begin_label_rtx = gen_rtx_SYMBOL_REF ( SImode , ggc_strdup ( begin_label_name ) ) ; emit_move_insn ( gen_rtx_REG ( word_mode , <NUM_LIT> ) , gen_rtx_REG ( word_mode , <NUM_LIT> ) ) ; if ( ! use_mcount_pcrel_call ) { if ( TARGET_PA_20 ) emit_insn ( gen_lcla2 ( reg , label_rtx ) ) ; else emit_insn ( gen_lcla1 ( reg , label_rtx ) ) ; emit_insn ( gen_load_offset_label_address ( gen_rtx_REG ( SImode , <NUM_LIT> ) , reg , begin_label_rtx , label_rtx ) ) ; } if ( ! NO_DEFERRED_PROFILE_COUNTERS ) { rtx count_label_rtx , addr , r24 ; char count_label_name [ <NUM_LIT> ] ; funcdef_nos . safe_push ( label_no ) ; ASM_GENERATE_INTERNAL_LABEL ( count_label_name , <STR_LIT> , label_no ) ; count_label_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( count_label_name ) ) ; addr = force_reg ( Pmode , count_label_rtx ) ; r24 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( r24 , addr ) ; arg_bytes = GEN_INT ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; if ( use_mcount_pcrel_call ) call_insn = emit_call_insn ( gen_call_mcount ( mcount , arg_bytes , begin_label_rtx ) ) ; else call_insn = emit_call_insn ( gen_call ( mcount , arg_bytes ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , r24 ) ;


<s> InstrReplacerDstCOPY ( unsigned SrcOpcode , unsigned DstOpcode ) : InstrConverterBase ( SrcOpcode ) , DstOpcode ( DstOpcode ) {