<s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , This2Reg ) . addReg ( Start2Reg ) . addMBB ( StartMBB ) . addReg ( End2Reg ) . addMBB ( LoopMBB ) ; BuildMI ( MBB , DL , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( CharReg ) ; BuildMI ( MBB , DL , TII -> get ( Opcode ) ) . addReg ( End1Reg , RegState :: Define ) . addReg ( End2Reg , RegState :: Define ) . addReg ( This1Reg ) . addReg ( This2Reg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <STR_LIT> ) . addMBB ( LoopMBB ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB -> addSuccessor ( DoneMBB ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitCondStore ( MachineInstr * MI , MachineBasicBlock * MBB , unsigned StoreOpcode , unsigned STOCOpcode , bool Invert ) const { const <ISA_LIT>InstrInfo * TII = TM . getInstrInfo ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand Base = MI -> getOperand ( <NUM_LIT> ) ; int64_t Disp = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned IndexReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CCValid = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; if ( STOCOpcode && ! IndexReg && TM . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) { if ( Invert ) CCMask ^= CCValid ; BuildMI ( * MBB , MI , DL , TII -> get ( STOCOpcode ) ) . addReg ( SrcReg ) . addOperand ( Base ) . addImm ( Disp ) . addImm ( CCValid ) . addImm ( CCMask ) ; MI -> eraseFromParent ( ) ; return MBB ; } if ( ! Invert ) CCMask ^= CCValid ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ;

BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ;


<s> static SDValue performORCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( Subtarget . hasStdExtZbp ( ) ) { if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ; if ( auto GORC = combineORToGORC ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GORC ; if ( auto SHFL = combineORToSHFL ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return SHFL ; }

return combineSelectAndUseCommutative ( N , DAG , false ) ;


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createOffset ( nullptr , DwarfReg , Offset ) ) ; }


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasStdExtV ( ) ) return false ; TII = ST . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; assert ( BlockInfo . empty ( ) && <STR_LIT> ) ; BlockInfo . resize ( MF . getNumBlockIDs ( ) ) ; bool HaveVectorOp = false ; for ( const MachineBasicBlock & MBB : MF ) HaveVectorOp |= computeVLVTYPEChanges ( MBB ) ; if ( HaveVectorOp ) { for ( const MachineBasicBlock & MBB : MF ) {


<s> return MCDisassembler :: Fail ; } Size = <NUM_LIT> ; Hi = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; Lo = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> } if ( auto GEP = dyn_cast < GetElementPtrInst > ( V ) ) { auto P = GEP -> getPointerOperand ( ) ; WorkSet . insert ( P ) ; for ( unsigned I = <NUM_LIT> , E = GEP -> getNumIndices ( ) + <NUM_LIT> ; I != E ; ++ I ) WorkSet . insert ( GEP -> getOperand ( I ) ) ; continue ; } if ( auto U = dyn_cast < UnaryInstruction > ( V ) ) { WorkSet . insert ( U -> getOperand ( <NUM_LIT> ) ) ; continue ; } if ( auto BO = dyn_cast < BinaryOperator > ( V ) ) { WorkSet . insert ( BO -> getOperand ( <NUM_LIT> ) ) ; WorkSet . insert ( BO -> getOperand ( <NUM_LIT> ) ) ; continue ; } if ( auto S = dyn_cast < SelectInst > ( V ) ) { WorkSet . insert ( S -> getFalseValue ( ) ) ;

WorkSet . insert ( S -> getTrueValue ( ) ) ;


<s> if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } } } AddDefaultPred ( BuildMI ( MBB , UseMI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) ) ; return true ;


<s> Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ;

unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , createMCStreamer ) ;

TargetRegistry :: RegisterMCRelocationInfo ( The<ISA_LIT>Target , create<ISA_LIT>ElfRelocation ) ;


<s> f_ovfl = TYPE_FIELDS ( va_list_type_node ) ; f_gbase = TREE_CHAIN ( f_ovfl ) ; f_fbase = TREE_CHAIN ( f_gbase ) ; f_gbytes = TREE_CHAIN ( f_fbase ) ; f_fbytes = TREE_CHAIN ( f_gbytes ) ; addr = create_tmp_var ( ptr_type_node , <STR_LIT> ) ; lab_false = create_artificial_label ( UNKNOWN_LOCATION ) ; lab_over = create_artificial_label ( UNKNOWN_LOCATION ) ; if ( float_reg_arg_p ) bytes = build3 ( COMPONENT_REF , TREE_TYPE ( f_fbytes ) , unshare_expr ( valist ) , f_fbytes , NULL_TREE ) ; else bytes = build3 ( COMPONENT_REF , TREE_TYPE ( f_gbytes ) , unshare_expr ( valist ) , f_gbytes , NULL_TREE ) ; t = fold_convert ( TREE_TYPE ( bytes ) , size_int ( rsize ) ) ; t = build2 ( LT_EXPR , boolean_type_node , bytes , t ) ; u = build1 ( GOTO_EXPR , void_type_node , lab_false ) ; t = build3 ( COND_EXPR , void_type_node , t , u , NULL_TREE ) ; gimplify_and_add ( t , pre_p ) ; t = fold_convert ( sizetype , bytes ) ; offs = build2 ( MINUS_EXPR , sizetype , size_int ( max_save_area_size ) , t ) ; if ( float_reg_arg_p ) base = build3 ( COMPONENT_REF , TREE_TYPE ( f_fbase ) , valist , f_fbase , NULL_TREE ) ; else base = build3 ( COMPONENT_REF , TREE_TYPE ( f_gbase ) , valist , f_gbase , NULL_TREE ) ;

t = build2 ( POINTER_PLUS_EXPR , TREE_TYPE ( base ) , base , offs ) ;


<s> if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . is<ISA_LIT>64 ( ) && MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( <STR_LIT> ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) {


<s> static void EncodeTypes ( MCStreamer & Streamer , ArrayRef < MVT > Types ) { Streamer . EmitIntValue ( Types . size ( ) , sizeof ( uint64_t ) ) ; for ( MVT Type : Types ) Streamer . EmitIntValue ( Type . SimpleTy , sizeof ( uint64_t ) ) ;


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override {


<s> return StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> switch ( get_attr_cc ( insn ) ) { case CC_NONE : break ; case CC_SET_N : CC_STATUS_INIT ; break ; case CC_SET_ZN : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) { cc_status . flags |= CC_NO_OVERFLOW ; cc_status . value1 = SET_DEST ( set ) ; } break ; case CC_SET_CZN : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) { cc_status . value1 = SET_DEST ( set ) ; cc_status . flags |= CC_OVERFLOW_UNUSABLE ; } break ; case CC_COMPARE : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) cc_status . value1 = SET_SRC ( set ) ; break ; case CC_CLOBBER : CC_STATUS_INIT ; set = single_set ( insn ) ; if ( set ) {


<s> return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue T = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op ) , <NUM_LIT> ) ; T = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , T , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { T , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } } } else if ( Imm == ~ <NUM_LIT> ) { SDValue Op = N -> getOperand ( <NUM_LIT> ) ; switch ( CC ) { default : break ; case <STR_LIT> : Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> ) ) , <NUM_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( <NUM_LIT> ) ) , <NUM_LIT> ) , Op . getValue ( <NUM_LIT> ) ) ; case <STR_LIT> : { Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op , Op ) , <NUM_LIT> ) ; SDNode * AD = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Op , getI32Imm ( ~ <NUM_LIT> ) ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( AD , <NUM_LIT> ) , Op , SDValue ( AD , <NUM_LIT> ) ) ; } case <STR_LIT> : { SDValue AD = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op , getI32Imm ( <NUM_LIT> ) ) , <NUM_LIT> ) ; SDValue AN = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , AD , Op ) , <NUM_LIT> ) ; SDValue Ops [ ] = { AN , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; } case <STR_LIT> : { SDValue Ops [ ] = { Op , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ;

Op = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> ) * <NUM_LIT> ;


<s> ResVT = <STR_LIT> ; TruncVT = <STR_LIT> ; Opc = <STR_LIT> ; Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } SDValue Res = DAG . getNode ( Opc , dl , ResVT , Src ) ; Res = DAG . getNode ( <STR_LIT> , dl , TruncVT , Res ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget . hasDQI ( ) && Subtarget . hasVLX ( ) && <STR_LIT> ) ; if ( VT == <STR_LIT> && Src . getSimpleValueType ( ) == <STR_LIT> ) { return DAG . getNode ( IsSigned ? <STR_LIT> : <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( <STR_LIT> ) ) ) ; } return SDValue ( ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> } } else if ( MO . isRegMask ( ) ) { for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , IE = RC -> end ( ) ; I != IE ; ++ I ) if ( MO . clobbersPhysReg ( * I ) ) { Pred . push_back ( MO ) ; Found = true ; } } } } return Found ;


<s> if ( ! SrcReg ) return false ; EVT SrcEVT , DestEVT ; SrcEVT = TLI . getValueType ( SrcTy , true ) ; DestEVT = TLI . getValueType ( DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = ( AssignedReg ? MRI . getRegClass ( AssignedReg ) : ( DestVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ) ; unsigned ResultReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , DestVT , ResultReg , IsZExt ) ) return false ; UpdateValueMap ( I , ResultReg ) ; return true ;


<s> else if ( mode == ADD_TO_DISPATCH_WINDOW ) add_to_dispatch_window ( insn ) ;


<s> Entry . Node = Op . getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( Call ) , getPointerTy ( ) ) ; Type * RetTy = Op . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue TCChain = InChain ; bool isTailCall = isInTailCallPosition ( DAG , Op . getNode ( ) , TCChain ) ; if ( isTailCall ) InChain = TCChain ; TargetLowering :: CallLoweringInfo CLI ( InChain , RetTy , false , false , false , false , <NUM_LIT> , getLibcallCallingConv ( Call ) , isTailCall , false , true , Callee , Args , DAG , SDLoc ( Op ) ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; if ( ! CallInfo . second . getNode ( ) ) return DAG . getRoot ( ) ;


<s> return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) {


<s> const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr & BMI = * MII ;


<s> if ( insn && CALL_P ( insn ) ) { rtx call = get_call_rtx_from ( insn ) ; if ( call ) return CALL_EXPR_WITH_BOUNDS_P ( call ) ; } return chkp_function_instrumented_p ( current_function_decl ) ;


<s> assert ( R -> isReg ( ) ) ; R -> Reg . IsForcedVOP3 = isForcedVOP3 ( ) ; Operands . push_back ( std :: move ( R ) ) ; return MatchOperand_Success ; } return MatchOperand_NoMatch ;


<s> if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } } llvm_unreachable ( <STR_LIT> ) ;


<s> N . dump ( ) ; errs ( ) << <STR_LIT> ; N0 . dump ( ) ; ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; DEBUG ( errs ( ) << <STR_LIT> << AM . Disp ) ; }


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return true ;


<s> static rtx iq2000_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool outgoing ATTRIBUTE_UNUSED ) { int reg = GP_RETURN ; machine_mode mode = TYPE_MODE ( valtype ) ;

int unsignedp = TYPE_UNSIGNED ( valtype ) ;


<s> unsigned FltOpc = <STR_LIT> ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area1Register ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & is<ISA_LIT>Area2Register ) ; emitPushInst ( MBB , MI , CSI , FltOpc , <NUM_LIT> , true , & is<ISA_LIT>Area3Register ) ;


<s> bool RegisterAliasInfo :: covers ( const RegisterSet & RRs , RegisterRef RR ) const { if ( RRs . count ( RR ) ) return true ; if ( TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) { if ( RR . Sub != <NUM_LIT> ) return RRs . count ( { RR . Reg , <NUM_LIT> } ) ; return false ; } unsigned Reg = RR . Sub == <NUM_LIT> ? RR . Reg : TRI . getSubReg ( RR . Reg , RR . Sub ) ;

for ( MCSuperRegIterator SR ( Reg , & TRI ) ; SR . isValid ( ) ; ++ SR ) if ( RRs . count ( { * SR , <NUM_LIT> } ) ) return true ;


<s> RegT = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegT ) ; Binary |= ( RegT << <STR_LIT> ) ; Binary |= encodeNEONRn ( MI , <NUM_LIT> ) ; emitWordLE ( Binary ) ;


<s> static int get_arc_condition_code ( rtx comparison ) { switch ( GET_CODE ( comparison ) ) { case EQ : return <NUM_LIT> ; case NE : return <NUM_LIT> ; case GT : return <NUM_LIT> ; case LE : return <NUM_LIT> ; case GE : return <NUM_LIT> ; case LT : return <NUM_LIT> ;


<s> bool AtStart = MI == MBB . begin ( ) ; MachineBasicBlock :: iterator BeforeI = MI ; if ( ! AtStart ) -- BeforeI ; for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { unsigned Reg = it -> getReg ( ) ;

assert ( Reg != <STR_LIT> && ! ( Reg == <STR_LIT> && hasFP ( * MF ) ) && <STR_LIT> ) ;


return STI . getFeatureBits ( ) & <STR_LIT> ;


<s> TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmBackend ) ;

TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ;


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const ScheduleDAG * DAG ) : ScoreboardHazardRecognizer ( ItinData , DAG , <STR_LIT> ) {


<s> return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> return ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; default : break ; } return ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ;


<s> bool hasAndNotCompare ( SDValue V ) const override { return V . getValueType ( ) . isScalarInteger ( ) ;


<s> VTs . push_back ( <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { LHS , RHS } ; CompareFlag = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) . getValue ( <NUM_LIT> ) ; Opc = <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = IntCondCCodeToICC ( CC ) ; } else { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; Opc = <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = FPCondCCodeToFCC ( CC ) ; }

return DAG . getNode ( Opc , dl , TrueVal . getValueType ( ) , TrueVal , FalseVal , DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> ) , CompareFlag ) ;


<s> BuildMI ( LoopBB , I , DL , TII -> get ( TargetOpcode :: PHI ) , PhiReg ) . addReg ( InitReg ) . addMBB ( & OrigBB ) . addReg ( ResultReg ) . addMBB ( & LoopBB ) ; BuildMI ( LoopBB , I , DL , TII -> get ( TargetOpcode :: PHI ) , PhiExec ) . addReg ( InitSaveExecReg ) . addMBB ( & OrigBB ) . addReg ( NewExec ) . addMBB ( & LoopBB ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , getUndefRegState ( IdxReg . isUndef ( ) ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CondReg ) . addReg ( CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , <NUM_LIT> , IdxReg . getSubReg ( ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , NewExec ) . addReg ( CondReg , RegState :: Kill ) ; MRI . setSimpleHint ( NewExec , CondReg ) ; if ( UseGPRIdxMode ) { unsigned IdxReg ; if ( Offset == <NUM_LIT> ) { IdxReg = CurrentIdxReg ; } else { IdxReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , IdxReg ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ; } unsigned IdxMode = IsIndirectSrc ? VGPRIndexMode :: SRC0_ENABLE : VGPRIndexMode :: DST_ENABLE ; MachineInstr * SetOn = BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IdxReg , RegState :: Kill ) . addImm ( IdxMode ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; } else {


<s> if ( ! isNopMCInst ( BMI ) ) { if ( <ISA_LIT>II :: isVPUInst ( MC ) ) hasVPU = true ; else if ( <ISA_LIT>II :: isSPUInst ( MC ) ) hasSPU = true ; else if ( <ISA_LIT>II :: isLoadInst ( MC ) ) hasLD = true ; else if ( <ISA_LIT>II :: isStoreInst ( MC ) ) hasST = true ; } } if ( ( hasVPU || hasSPU ) && ( hasLD || hasST ) ) { return false ; }


<s> unsigned returnReg = RI . getRARegister ( ) ;

unsigned stackSize = MF -> getFrameInfo ( ) . getStackSize ( ) ;


<s> libfunc = optab_libfunc ( sdiv_optab , SImode ) ; lab1 = gen_label_rtx ( ) ; lab3 = gen_label_rtx ( ) ; or_result = expand_simple_binop ( SImode , IOR , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; emit_cmp_and_jump_insns ( or_result , GEN_INT ( <NUM_LIT> ) , GTU , <NUM_LIT> , GET_MODE ( or_result ) , <NUM_LIT> , lab3 ) ; JUMP_LABEL ( get_last_insn ( ) ) = lab3 ; shift_left_result = expand_simple_binop ( SImode , ASHIFT , operands [ <NUM_LIT> ] , GEN_INT ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; lookup_value = expand_simple_binop ( SImode , IOR , shift_left_result , operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; table = gen_rtx_PLUS ( SImode , lookup_value , gen_rtx_SYMBOL_REF ( SImode , <STR_LIT> ) ) ;

convert_move ( operands [ <NUM_LIT> ] , gen_rtx_MEM ( QImode , table ) , <NUM_LIT> ) ;


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Subtarget -> hasAVX512 ( ) && <STR_LIT> ) ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( VT . SimpleTy , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ;


<s> unsigned Expcnt = getBitMask ( getExpcntBitShift ( ) , getExpcntBitWidth ( ) ) ; unsigned Lgkmcnt = getBitMask ( getLgkmcntBitShift ( ) , getLgkmcntBitWidth ( ) ) ; unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt ; if ( Version . Major < <NUM_LIT> ) return Waitcnt ; unsigned VmcntHi = getBitMask ( getVmcntBitShiftHi ( ) , getVmcntBitWidthHi ( ) ) ;


<s> bool <ISA_LIT>TargetLowering :: directMoveIsProfitable ( const SDValue & Op ) const { SDNode * Origin = Op . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( Origin -> getOpcode ( ) != <STR_LIT> ) return true ;

MachineMemOperand * MMO = cast < LoadSDNode > ( Origin ) -> getMemOperand ( ) ;


<s> void <ISA_LIT>GNULDBackend :: doPostLayout ( Module & pModule , IRBuilder & pBuilder ) {


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ;

return vectorCostAdjustment ( Cost , Opcode , Ty , nullptr ) ;


<s> Offset = CurDAG -> getTargetConstant ( EncodedOffset , SL , <STR_LIT> ) ; Imm = true ; return true ; } if ( ! isUInt < <NUM_LIT> > ( EncodedOffset ) || ! isUInt < <NUM_LIT> > ( ByteOffset ) ) return false ; if ( Gen == <ISA_LIT>Subtarget :: SEA_ISLANDS && isUInt < <NUM_LIT> > ( EncodedOffset ) ) { Offset = CurDAG -> getTargetConstant ( EncodedOffset , SL , <STR_LIT> ) ; } else { SDValue C32Bit = CurDAG -> getTargetConstant ( ByteOffset , SL , <STR_LIT> ) ; Offset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , C32Bit ) , <NUM_LIT> ) ;


<s> int KCacheMode = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( KCacheMode > <NUM_LIT> ) { int KCacheBank = MI -> getOperand ( OpNo - <NUM_LIT> ) . getImm ( ) ;


if ( TheTriple . isOSDarwin ( ) ) return new <ISA_LIT>MCAsmInfoDarwin ( ) ;


<s> if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) , * this , Fast ) ) ;


<s> O << markup ( <STR_LIT> ) << <STR_LIT> ; O . write_hex ( Val ) ; O << markup ( <STR_LIT> ) ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( InVT . isVector ( ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { SDLoc dl ( N ) ; EVT DstVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , InVT . getVectorNumElements ( ) ) ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; if ( TLI . isOperationLegal ( <STR_LIT> , DstVT ) ) return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; return DAG . getNode ( <STR_LIT> , dl , VT , P ) ; } if ( DAG . SignBitIsZero ( Op0 ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 ) ; return SDValue ( ) ;


<s> } } live_regs_mask &= ~ <NUM_LIT> ; } had_to_push_lr = ( live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ) != <NUM_LIT> ; live_regs_mask &= <NUM_LIT> ; if ( crtl -> args . pretend_args_size == <NUM_LIT> || TARGET_BACKTRACE ) { if ( had_to_push_lr ) live_regs_mask |= <NUM_LIT> << PC_REGNUM ; if ( live_regs_mask ) thumb_pop ( asm_out_file , live_regs_mask ) ; if ( ! had_to_push_lr ) thumb_exit ( asm_out_file , LR_REGNUM ) ; } else { if ( live_regs_mask ) thumb_pop ( asm_out_file , live_regs_mask ) ; if ( had_to_push_lr ) { if ( size > <NUM_LIT> ) { asm_fprintf ( asm_out_file , <STR_LIT> , IP_REGNUM , LAST_ARG_REGNUM ) ; } thumb_pop ( asm_out_file , <NUM_LIT> << LAST_ARG_REGNUM ) ; if ( size > <NUM_LIT> ) { asm_fprintf ( asm_out_file , <STR_LIT> , LR_REGNUM , LAST_ARG_REGNUM ) ; asm_fprintf ( asm_out_file , <STR_LIT> , LAST_ARG_REGNUM , IP_REGNUM ) ; regno = LR_REGNUM ; }


<s> initialize<ISA_LIT>AAWrapperPassPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> if ( GV -> hasInitializer ( ) ) { if ( EmitSpecialLLVMGlobal ( GV ) ) { return ; } } MCSymbol * GVSym = getSymbol ( GV ) ; if ( ! GV -> hasInitializer ( ) ) { return ; } GVSym -> redefineIfPossible ( ) ; if ( GVSym -> isDefined ( ) || GVSym -> isVariable ( ) ) report_fatal_error ( <STR_LIT> + Twine ( GVSym -> getName ( ) ) + <STR_LIT> ) ; SectionKind GVKind = TargetLoweringObjectFile :: getKindForGlobal ( GV , TM ) ; const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; unsigned Align = DL . getPreferredAlignment ( GV ) ; MCSection * TheSection = getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ; OutStreamer -> SwitchSection ( TheSection ) ; TS -> emitAlign ( Align ) ; if ( ! GV -> hasLocalLinkage ( ) ) { TS -> emitGlobal ( GVSym ) ; } OutStreamer -> EmitLabel ( GVSym ) ; if ( GVKind . isBSS ( ) ) { TS -> emitBlock ( Size ) ; } else {

EmitGlobalConstant ( DL , GV -> getInitializer ( ) ) ;


<s> return __arm_vddupq_wb_u16 ( __a , __imm ) ;


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS ) const { bool closeParen = printVariantKind ( OS , Kind ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> case AND : case IOR : case XOR : return ( const_ok_for_op ( hi_val , code ) || hi_val == <NUM_LIT> ) && ( const_ok_for_op ( lo_val , code ) || lo_val == <NUM_LIT> ) ; case PLUS : return arm_not_operand ( hi , SImode ) && arm_add_operand ( lo , SImode ) ;


<s> <ISA_LIT>CA53Erratum835769Stub :: ~ <ISA_LIT>CA53Erratum835769Stub ( ) {


<s> GlobalVariable * GVSP = cast < GlobalVariable > ( * UUI ) ; DISubprogram * SP = new DISubprogram ( GVSP ) ; std :: string Name ; SP -> getLinkageName ( Name ) ; FunctNameMap [ Name ] = SP ; }


<s> SmallVector < CallInst * , <NUM_LIT> > ToErase ; LLVMContext & C = LongjmpF -> getParent ( ) -> getContext ( ) ; IRBuilder < > IRB ( C ) ; for ( User * U : LongjmpF -> users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ;

if ( CI && CI -> getCalledFunction ( ) == LongjmpF ) {


<s> static std :: string GetAEABIUnwindPersonalityName ( unsigned Index ) { assert ( Index < NUM_PERSONALITY_INDEX && <STR_LIT> ) ; return ( Twine ( <STR_LIT> ) + Twine ( Index ) ) . str ( ) ;


<s> std :: vector < std :: string > mov_mixp ( Register a ) { return D ( <STR_LIT> , R ( a ) , <STR_LIT> ) ;


<s> switch ( symRef . getKind ( ) ) { default : return ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GD_GOT : case MCSymbolRefExpr :: VK_<ISA_LIT>_LD_GOT : case MCSymbolRefExpr :: VK_<ISA_LIT>_GD_PLT : case MCSymbolRefExpr :: VK_<ISA_LIT>_LD_PLT : case MCSymbolRefExpr :: VK_<ISA_LIT>_IE : case MCSymbolRefExpr :: VK_<ISA_LIT>_IE_GOT : case MCSymbolRefExpr :: VK_TPREL : break ; } cast < MCSymbolELF > ( symRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; break ; } case MCExpr :: Unary : fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


<s> bool <ISA_LIT>InstructionSelector :: tryOptSelect ( MachineInstr & I ) { MachineRegisterInfo & MRI = * MIB . getMRI ( ) ; MachineInstr * CondDef = MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; while ( CondDef ) { Register CondDefReg = CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . hasOneNonDBGUse ( CondDefReg ) ) { for ( const MachineInstr & UI : MRI . use_nodbg_instructions ( CondDefReg ) ) { if ( CondDef == & UI ) continue ; if ( UI . getOpcode ( ) != TargetOpcode :: G_SELECT ) return false ; } } unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ; if ( CondOpc == TargetOpcode :: G_ICMP ) { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; CondCode = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; emitIntegerCompare ( CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , CondDef -> getOperand ( <NUM_LIT> ) , MIB ) ; } else { auto Pred = static_cast < CmpInst :: Predicate > ( CondDef -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; <STR_LIT> CondCode2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CondCode , CondCode2 ) ;

if ( CondCode2 != <STR_LIT> ) return false ;


<s> for ( ; I != E ; I ++ ) { if ( I -> isBranch ( ) && TII -> getBranchDestBlock ( * I ) == S ) return nullptr ; } } return S ; } ; for ( auto & I : MBB . instrs ( ) ) { if ( ! I . isDebugInstr ( ) && ! I . isUnconditionalBranch ( ) ) return false ; } assert ( MBB . succ_size ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock * Succ = * MBB . succ_begin ( ) ; MachineBasicBlock * FallThrough = nullptr ; while ( ! MBB . predecessors ( ) . empty ( ) ) { MachineBasicBlock * P = * MBB . pred_begin ( ) ; if ( GetFallThroughSucc ( P ) == & MBB ) FallThrough = P ; P -> ReplaceUsesOfBlockWith ( & MBB , Succ ) ; } MBB . removeSuccessor ( Succ ) ; if ( LIS ) { for ( auto & I : MBB . instrs ( ) ) LIS -> RemoveMachineInstrFromMaps ( I ) ; } if ( MDT ) MDT -> eraseNode ( & MBB ) ; MBB . clear ( ) ; MBB . eraseFromParent ( ) ;

if ( FallThrough && ! FallThrough -> isLayoutSuccessor ( Succ ) ) {


<s> } if ( bisReversable ) { if ( isOrderedDuplexPair ( MCII , * MCB . getOperand ( j ) . getInst ( ) , <ISA_LIT>MCInstrInfo :: hasExtenderForIndex ( MCB , j - <NUM_LIT> ) , * MCB . getOperand ( k ) . getInst ( ) , <ISA_LIT>MCInstrInfo :: hasExtenderForIndex ( MCB , k - <NUM_LIT> ) , bisReversable ) ) { unsigned iClass = iClassOfDuplexPair ( getDuplexCandidateGroup ( * MCB . getOperand ( j ) . getInst ( ) ) , getDuplexCandidateGroup ( * MCB . getOperand ( k ) . getInst ( ) ) ) ; duplexToTry . push_back ( DuplexCandidate ( k , j , iClass ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << k << <STR_LIT> << j << <STR_LIT> << MCB . getOperand ( j ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> << MCB . getOperand ( k ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << k << <STR_LIT> << j << <STR_LIT> << MCB . getOperand ( j ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> << MCB . getOperand ( k ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> ) ; }


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ;


<s> void <ISA_LIT>AsmPrinter :: emitArrayBound ( MCSymbol * Sym , const GlobalVariable * GV ) { assert ( ( GV -> hasExternalLinkage ( ) || GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) || GV -> hasCommonLinkage ( ) ) && <STR_LIT> ) ; if ( ArrayType * ATy = dyn_cast < ArrayType > ( cast < PointerType > ( GV -> getType ( ) ) -> getElementType ( ) ) ) { MCSymbol * SymGlob = OutContext . getOrCreateSymbol ( Twine ( Sym -> getName ( ) + StringRef ( <STR_LIT> ) ) ) ; OutStreamer -> EmitSymbolAttribute ( SymGlob , MCSA_Global ) ; OutStreamer -> EmitAssignment ( SymGlob , MCConstantExpr :: create ( ATy -> getNumElements ( ) , OutContext ) ) ; if ( GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) || GV -> hasCommonLinkage ( ) ) { OutStreamer -> EmitSymbolAttribute ( SymGlob , MCSA_Weak ) ; }


<s> unsigned getSwitchSet ( ) const { assert ( Kind >= OpKind :: SwitchSet && <STR_LIT> ) ; return SwitchSet ;


<s> static inline struct bpf_sock * bpf_get_listener_sock ( struct bpf_sock * sk ) {

return ( struct bpf_sock * ) __builtin_bpf_helper_get_listener_sock ( ( void * ) sk ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; EVT ResVT = Op . getValueType ( ) ; assert ( ResVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ;

SDValue V1 = Op . getOperand ( <NUM_LIT> ) ;


<s> llvm :: SmallVector < std :: pair < std :: string , std :: string > , <NUM_LIT> > Tools ; if ( const NamedMDNode * Ident = M . getNamedMetadata ( <STR_LIT> ) ) { llvm :: SmallSet < StringRef , <NUM_LIT> > SeenTools ; for ( size_t I = <NUM_LIT> , E = Ident -> getNumOperands ( ) ; I < E ; ++ I ) { const auto * S = cast < MDString > ( Ident -> getOperand ( I ) -> getOperand ( <NUM_LIT> ) ) ; std :: pair < StringRef , StringRef > Field = S -> getString ( ) . split ( <STR_LIT> ) ; StringRef Name = Field . first . trim ( ) ; StringRef Version = Field . second . trim ( ) ; if ( SeenTools . insert ( Name ) . second ) Tools . emplace_back ( Name . str ( ) , Version . str ( ) ) ; } } int FieldCount = int ( ! Languages . empty ( ) ) + int ( ! Tools . empty ( ) ) ; if ( FieldCount != <NUM_LIT> ) { MCSectionWasm * Producers = OutContext . getWasmSection ( <STR_LIT> , SectionKind :: getMetadata ( ) ) ; OutStreamer -> PushSection ( ) ; OutStreamer -> SwitchSection ( Producers ) ; OutStreamer -> EmitULEB128IntValue ( FieldCount ) ; for ( auto & Producers : { std :: make_pair ( <STR_LIT> , & Languages ) , std :: make_pair ( <STR_LIT> , & Tools ) } ) { if ( Producers . second -> empty ( ) ) continue ; OutStreamer -> EmitULEB128IntValue ( strlen ( Producers . first ) ) ; OutStreamer -> EmitBytes ( Producers . first ) ; OutStreamer -> EmitULEB128IntValue ( Producers . second -> size ( ) ) ; for ( auto & Producer : * Producers . second ) { OutStreamer -> EmitULEB128IntValue ( Producer . first . size ( ) ) ; OutStreamer -> EmitBytes ( Producer . first ) ; OutStreamer -> EmitULEB128IntValue ( Producer . second . size ( ) ) ; OutStreamer -> EmitBytes ( Producer . second ) ;


<s> int n ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_DOUBLE ) { gcc_assert ( HOST_BITS_PER_WIDE_INT != <NUM_LIT> ) ; lval = CONST_DOUBLE_LOW ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ; hval = CONST_DOUBLE_HIGH ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ; } else { lval = INTVAL ( operands [ <NUM_LIT> ] ) ; hval = <NUM_LIT> ; } if ( lval != <NUM_LIT> && ( n = exact_log2 ( lval & ( - lval ) ) ) != - <NUM_LIT> && ( lval >> n ) < <NUM_LIT> ) { lval >>= n ; if ( HOST_BITS_PER_WIDE_INT == <NUM_LIT> && hval != <NUM_LIT> ) { if ( n <= <NUM_LIT> || hval >= ( ( unsigned ) <NUM_LIT> << ( n - <NUM_LIT> ) ) ) n = <NUM_LIT> ; else lval |= hval << ( <NUM_LIT> - n ) ; } if ( n > <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( lval ) ; operands [ <NUM_LIT> ] = GEN_INT ( n ) ; return <STR_LIT> ; } } else if ( hval != <NUM_LIT> && ( n = exact_log2 ( hval & ( - hval ) ) - <NUM_LIT> ) != - <NUM_LIT> && ( hval >> n ) < <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( hval >> n ) ; operands [ <NUM_LIT> ] = GEN_INT ( n + <NUM_LIT> ) ; return <STR_LIT> ; } } if ( vax_maybe_split_dimode_move ( operands ) ) { hi [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; hi [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; split_quadword_operands ( insn , SET , hi , lo , <NUM_LIT> ) ; pattern_lo = vax_output_int_move ( NULL , lo , SImode ) ; pattern_hi = vax_output_int_move ( NULL , hi , SImode ) ; if ( ( ! strncmp ( pattern_lo , <STR_LIT> , <NUM_LIT> ) && ! strncmp ( pattern_hi , <STR_LIT> , <NUM_LIT> ) ) || ( ! strncmp ( pattern_lo , <STR_LIT> , <NUM_LIT> ) && ! strncmp ( pattern_hi , <STR_LIT> , <NUM_LIT> ) ) ) return <STR_LIT> ; if ( MEM_P ( operands [ <NUM_LIT> ] ) && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == PRE_DEC ) { output_asm_insn ( pattern_hi , hi ) ; operands [ <NUM_LIT> ] = lo [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = lo [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = lo [ <NUM_LIT> ] ; return pattern_lo ; }


<s> void <ISA_LIT>RegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const {


<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( ! TM . isPositionIndependent ( ) ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( SPAllowed ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , DL , ValTy ) ; return true ;


<s> if ( PointerType * PT = dyn_cast < PointerType > ( GType ) ) GType = PT -> getElementType ( ) ; if ( isa < ArrayType > ( GType ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( StructType * ST = dyn_cast < StructType > ( GType ) ) { if ( ST -> isOpaque ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } unsigned Size = GVar -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( GType ) ;


<s> if ( <STR_LIT> ( Val ) == <STR_LIT> && <STR_LIT> ( Val ) == <NUM_LIT> ) return ; O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( Val ) ) << <STR_LIT> << <STR_LIT> ( Val ) ;


<s> ( void ) Subtarget ; assert ( Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) && <STR_LIT> ) ; UseFP = true ; } else { if ( FPOffsetFits && PreferFP ) UseFP = true ; } } } assert ( ( ( isFixed || isCSR ) || ! RegInfo -> needsStackRealignment ( MF ) || ! UseFP ) && <STR_LIT> <STR_LIT> ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ; else { assert ( ! MFI . hasVarSizedObjects ( ) && <STR_LIT> ) ; FrameReg = <STR_LIT> ; if ( canUseRedZone ( MF ) ) Offset -= AFI -> getLocalStackSize ( ) ; } return Offset ;


<s> } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && RHS . getOpcode ( ) == <STR_LIT> ) if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) == <NUM_LIT> && RHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , RHS . getValueType ( ) , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , addV . getValueType ( ) ) , CC ) ; } return SDValue ( ) ;


<s> MCI . setLoc ( IDLoc ) ; } switch ( result ) { default : break ; case Match_Success : return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= InstOperands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( static_cast < <ISA_LIT>Operand * > ( InstOperands [ ErrorInfo ] . get ( ) ) ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; }


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : { if ( MI -> isPseudo ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI -> getOpcode ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } break ; } case <STR_LIT> : case <STR_LIT> : OutStreamer -> AddComment ( <STR_LIT> ) ; break ; } MCInst TmpInst0 ; MCInstLowering -> Lower ( MI , TmpInst0 ) ; OutStreamer -> EmitInstruction ( TmpInst0 , getSubtargetInfo ( ) ) ;


<s> SDNode * CmpSwap = DAG . getMachineNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineSDNode :: mmo_iterator MemOp = MF . allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( CmpSwap ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ; Results . push_back ( SDValue ( CmpSwap , <NUM_LIT> ) ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx ) ;


<s> MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDLoc dl ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ;

SDValue Offset = DAG . getConstant ( DAG . getDataLayout ( ) . getPointerSize ( ) , dl , <STR_LIT> ) ;


<s> bool <ISA_LIT>FastISel :: SelectCmp ( const Instruction * I ) { const CmpInst * CI = cast < CmpInst > ( I ) ; <STR_LIT> <ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( <ISA_LIT>Pred == <STR_LIT> ) return false ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CI -> isEquality ( ) ) ) return false ; unsigned MovCCOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; Constant * Zero = ConstantInt :: get ( Type :: getInt32Ty ( * Context ) , <NUM_LIT> ) ; unsigned ZeroReg = fastMaterializeConstant ( Zero ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( MovCCOpc ) , DestReg ) . addReg ( ZeroReg ) . addImm ( <NUM_LIT> ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; updateValueMap ( I , DestReg ) ;


<s> Op -> StartLoc = S ; Op -> EndLoc = S ; return std :: unique_ptr < <ISA_LIT>Operand > ( Op ) ;


<s> return ( uint16x8_t ) __builtin_neon_vrshluv8hi ( ( int16x8_t ) __a , __b ) ;


<s> RegMap [ Stack [ -- StackTop ] ] = ~ <NUM_LIT> ; int Opcode = Lookup ( PopTable , array_lengthof ( PopTable ) , I -> getOpcode ( ) ) ; if ( Opcode != - <NUM_LIT> ) { I -> setDesc ( TII -> get ( Opcode ) ) ; if ( Opcode == <STR_LIT> ) I -> RemoveOperand ( <NUM_LIT> ) ;


<s> if ( SyntaxVariant == <NUM_LIT> ) return ( new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ) ; else return nullptr ;


<s> SDValue XformMskToBitPosU3Imm ( uint8_t Imm , SDLoc DL ) { return XformMskToBitPosU5Imm ( Imm , DL ) ;


<s> bool isLegalAndnType = VT == <STR_LIT> || VT == <STR_LIT> ; if ( ! Subtarget . hasBMI ( ) || ! isAndn || ! isLegalAndnType ) break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : { if ( ! NeedTruncation && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { if ( SDValue EFLAGS = LowerVectorAllZeroTest ( Op , Subtarget , DAG ) ) return EFLAGS ; } Opcode = <STR_LIT> ; break ; } } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( NeedTruncation ) { EVT VT = Op . getValueType ( ) ; SDValue WideVal = Op -> getOperand ( <NUM_LIT> ) ; EVT WideVT = WideVal . getValueType ( ) ; unsigned ConvertedOp = <NUM_LIT> ; switch ( WideVal . getOpcode ( ) ) { default : break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; } if ( ConvertedOp ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isOperationLegal ( WideVal . getOpcode ( ) , WideVT ) ) { SDValue V0 = DAG . getNode ( <STR_LIT> , dl , VT , WideVal . getOperand ( <NUM_LIT> ) ) ; SDValue V1 = DAG . getNode ( <STR_LIT> , dl , VT , WideVal . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( ConvertedOp , dl , VT , V0 , V1 ) ; } } } if ( Opcode == <NUM_LIT> ) {

if ( auto Node = EmitKTEST ( Op , DAG , Subtarget ) ) return Node ;


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! CI -> isTailCall ( ) ) return false ; const Function * ParentFn = CI -> getParent ( ) -> getParent ( ) ; if ( <STR_LIT> ( ParentFn -> getCallingConv ( ) ) ) return false ; auto Attr = ParentFn -> getFnAttribute ( <STR_LIT> ) ;

return ( Attr . getValueAsString ( ) != <STR_LIT> ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 ; } else if ( IDVal == <STR_LIT> ) {

RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { llvm_unreachable ( <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ;


<s> void addModImmOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> for ( unsigned virtReg : virtRegs ) { for ( auto & useDef : regInfo . reg_operands ( virtReg ) ) { ( void ) useDef ; ++ useDefCount ; } }


<s> else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'v' : if ( Subtarget . hasVector ( ) ) { if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; } } if ( Constraint . size ( ) > <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' ) { if ( Constraint [ <NUM_LIT> ] == 'r' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; } if ( Constraint [ <NUM_LIT> ] == 'f' ) { if ( useSoftFloat ( ) ) return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( nullptr ) ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; } if ( Constraint [ <NUM_LIT> ] == 'v' ) { if ( ! Subtarget . hasVector ( ) ) return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( nullptr ) ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ; return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ;


<s> int first_elt_regno ; rtx elt ; count = XVECLEN ( op , <NUM_LIT> ) ; elt = XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( elt ) != SET || count <= <NUM_LIT> || count > <NUM_LIT> ) return false ; if ( load_p ) { if ( GET_CODE ( SET_DEST ( elt ) ) != REG || GET_CODE ( SET_SRC ( elt ) ) != MEM ) return false ;

first_elt_regno = REGNO ( SET_DEST ( elt ) ) ;


<s> SDValue Mult = ROOTNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ? ROOTNode -> getOperand ( <NUM_LIT> ) : ROOTNode -> getOperand ( <NUM_LIT> ) ; SDValue AddOperand = ROOTNode -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ? ROOTNode -> getOperand ( <NUM_LIT> ) : ROOTNode -> getOperand ( <NUM_LIT> ) ; if ( ! Mult . hasOneUse ( ) ) return SDValue ( ) ; SDValue MultLHS = Mult -> getOperand ( <NUM_LIT> ) ; SDValue MultRHS = Mult -> getOperand ( <NUM_LIT> ) ; bool IsSigned = MultLHS -> getOpcode ( ) == <STR_LIT> && MultRHS -> getOpcode ( ) == <STR_LIT> ; bool IsUnsigned = MultLHS -> getOpcode ( ) == <STR_LIT> && MultRHS -> getOpcode ( ) == <STR_LIT> ; if ( ! IsSigned && ! IsUnsigned ) return SDValue ( ) ; SDLoc DL ( ROOTNode ) ; SDValue TopHalf ; SDValue BottomHalf ; BottomHalf = CurDAG . getNode ( <STR_LIT> , DL , <STR_LIT> , AddOperand , CurDAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TopHalf = CurDAG . getNode ( <STR_LIT> , DL , <STR_LIT> , AddOperand , CurDAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue ACCIn = CurDAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BottomHalf , TopHalf ) ; bool IsAdd = ROOTNode -> getOpcode ( ) == <STR_LIT> ;

unsigned Opcode = IsAdd ? ( IsUnsigned ? <STR_LIT> : <STR_LIT> ) : ( IsUnsigned ? <STR_LIT> : <STR_LIT> ) ;


<s> if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) { if ( <STR_LIT> ( Opcode , <STR_LIT> :: imm ) != - <NUM_LIT> ) { ++ ConstantBusUseCount ; } SmallDenseSet < unsigned > SGPRsUsed ; unsigned SGPRUsed = findImplicitSGPRReadInVOP ( Inst ) ; if ( SGPRUsed != <STR_LIT> ) { SGPRsUsed . insert ( SGPRUsed ) ; ++ ConstantBusUseCount ; } const int Src0Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src0 ) ; const int Src1Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src1 ) ; const int Src2Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src2 ) ; const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx } ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) break ; const MCOperand & MO = Inst . getOperand ( OpIdx ) ; if ( usesConstantBus ( Inst , OpIdx ) ) {


<s> return ! Is64Bit && IsTailCall && getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget -> isPICStyleGOT ( ) ;


<s> step1 -= step2 ; } if ( step1 > <NUM_LIT> ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; rtx adjust = GEN_INT ( step1 ) ; if ( ! SMALL_OPERAND ( step1 ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( use_restore_libcall ) frame -> mask = <NUM_LIT> ; riscv_for_each_saved_reg ( frame -> total_size - step2 , riscv_restore_reg ) ; if ( use_restore_libcall ) { frame -> mask = mask ; gcc_assert ( step2 >= frame -> save_libcall_adjustment ) ; step2 -= frame -> save_libcall_adjustment ; } if ( need_barrier_p ) riscv_emit_stack_tie ( ) ;


<s> TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; writeData ( Binary , Size , OS ) ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) ;


<s> elementize ( F ) ; if ( RemoveRedundantMoves ) while ( <NUM_LIT> ) { if ( copyProp ( F ) == <NUM_LIT> ) break ; removeDeadMoves ( F ) ; } return true ;


<s> return TargetInstrInfo :: commuteInstructionImpl ( WorkingMI , false , OpIdx1 , OpIdx2 ) ; } case CASE_VFMA_OPCODE_LMULS ( FMADD , VV ) : case CASE_VFMA_OPCODE_LMULS ( FMSUB , VV ) : case CASE_VFMA_OPCODE_LMULS ( FNMADD , VV ) : case CASE_VFMA_OPCODE_LMULS ( FNMSUB , VV ) : { assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; if ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) { unsigned Opc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_VFMA_CHANGE_OPCODE_LMULS ( FMADD , FMACC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FMSUB , FMSAC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FNMADD , FNMACC , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FNMSUB , FNMSAC , VV ) } auto & WorkingMI = cloneIfNew ( MI ) ; WorkingMI . setDesc ( get ( Opc ) ) ; return TargetInstrInfo :: commuteInstructionImpl ( WorkingMI , false , OpIdx1 , OpIdx2 ) ; } break ;


<s> MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) , DestReg ) ;

for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ;


<s> void <ISA_LIT>MISimplifyPatchable :: processDstReg ( MachineRegisterInfo * MRI , Register & DstReg , Register & SrcReg , const GlobalValue * GVal , bool doSrcRegProp , bool IsAma ) { auto Begin = MRI -> use_begin ( DstReg ) , End = MRI -> use_end ( ) ; decltype ( End ) NextI ; for ( auto I = Begin ; I != End ; I = NextI ) {


<s> unsigned JumpOffset = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( JumpOffset ) ) ;


<s> void <ISA_LIT>InstPrinter :: printFPImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ;

O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( MO . getImm ( ) ) << markup ( <STR_LIT> ) ;


<s> if ( AsmVariant != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ;


<s> if ( cfun -> static_chain_decl != NULL ) size += ( <NUM_LIT> * UNITS_PER_WORD ) ; cfun -> machine -> callee_save_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; ++ regno ) { if ( xtensa_call_save_reg ( regno ) ) cfun -> machine -> callee_save_size += UNITS_PER_WORD ; }

cfun -> machine -> current_frame_size = XTENSA_STACK_ALIGN ( size + cfun -> machine -> callee_save_size + crtl -> outgoing_args_size + ( WINDOW_SIZE * UNITS_PER_WORD ) ) ;


<s> assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT ShVT = <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI . getShiftAmountTy ( SrcOp . getValueType ( ) ) ) ) ) ;


<s> return true ; case E_KFmode : return TARGET_FLOAT128_TYPE && ! TARGET_IEEEQUAD ; default : return false ;


<s> SDLoc dl ( Op . getNode ( ) ) ; SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && SubVec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ;

return Insert128BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ;


<s> enum tree_code code = TREE_CODE ( expr ) ; if ( code == COMPONENT_REF || code == ARRAY_REF ) return <NUM_LIT> ; if ( code == ADDR_EXPR ) return bpf_core_is_maybe_aggregate_access ( TREE_OPERAND ( expr , <NUM_LIT> ) ) ; return <NUM_LIT> ;


<s> nvptx_emit_joining ( GOMP_DIM_MASK ( mode ) , false ) ;


<s> if ( RegNo == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ;


<s> for ( auto & VA : ArgLocs ) { if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << '\n' ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else {

DiagnosticInfoUnsupported Err ( DL , * MF . getFunction ( ) , <STR_LIT> , SDValue ( ) ) ;


<s> MachineFunctionPass ( ID ) , TRI ( nullptr ) , TII ( nullptr ) {


<s> if ( ( ( class1 == FP_REGS ) != ( class2 == FP_REGS ) ) && ( ( TARGET_FLOATXX && ! ISA_HAS_MXHC1 ) || TARGET_O32_FP64A_ABI ) && GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return true ; return false ;


<s> int32x4_t result = vcombine_s32 ( a , vcreate_s32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) : ) ;


<s> if ( ! MI -> definesRegister ( <STR_LIT> ) ) MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true ) ) ;

if ( ! MI -> readsRegister ( <STR_LIT> ) ) MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ;


<s> const TargetRegisterClass * RC = TII -> getOpRegClass ( MI , i ) ; RegInterval Interval = getRegInterval ( RC , Op ) ; for ( unsigned j = Interval . first ; j < Interval . second ; ++ j ) { if ( Op . isDef ( ) ) { increaseCounters ( Result , UsedRegs [ j ] ) ; increaseCounters ( Result , DefinedRegs [ j ] ) ; } if ( Op . isUse ( ) ) increaseCounters ( Result , DefinedRegs [ j ] ) ; } }


<s> if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr ) ) return false ; UpdateValueMap ( I , ResultReg ) ;


<s> OutgoingArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder MIB , CCAssignFn * AssignFn , CCAssignFn * AssignFnVarArg ) : ValueHandler ( MIRBuilder , MRI , AssignFn ) , MIB ( MIB ) , AssignFnVarArg ( AssignFnVarArg ) , StackSize ( <NUM_LIT> ) {


<s> case <STR_LIT> : Inst . insert ( Inst . begin ( ) , MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; break ; } Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Disp ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ;


<s> unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ;


<s> DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; DReg = getCorrespondingDRegAndLane ( TRI , SrcReg , Lane ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB . addReg ( DstReg , RegState :: Define ) . addReg ( DReg , RegState :: Undef ) . addImm ( Lane ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; break ; case <STR_LIT> : { if ( Domain != ExeNEON ) break ; assert ( ! isPredicated ( MI ) && <STR_LIT> ) ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DReg = getCorrespondingDRegAndLane ( TRI , DstReg , Lane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DReg , Lane , ImplicitSReg ) ) break ; for ( unsigned i = MI -> getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI -> RemoveOperand ( i - <NUM_LIT> ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DReg , RegState :: Define ) . addReg ( DReg , getUndefRegState ( ! MI -> readsRegister ( DReg , TRI ) ) ) . addReg ( SrcReg ) . addImm ( Lane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Define | RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } case <STR_LIT> : { if ( Domain != ExeNEON ) break ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLane = <NUM_LIT> , SrcLane = <NUM_LIT> , DDst , DSrc ; DDst = getCorrespondingDRegAndLane ( TRI , DstReg , DstLane ) ; DSrc = getCorrespondingDRegAndLane ( TRI , SrcReg , SrcLane ) ; unsigned ImplicitSReg ;

if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DSrc , SrcLane , ImplicitSReg ) ) break ;


<s> static char buf [ <NUM_LIT> ] ; bool useskip ; int nullify = INSN_ANNULLED_BRANCH_P ( insn ) ; int length = get_attr_length ( insn ) ; int xdelay ; if ( branch_to_delay_slot_p ( insn ) ) return <STR_LIT> ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode && operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = gen_rtx_REG ( DImode , <NUM_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode && operands [ <NUM_LIT> ] == const0_rtx ) operands [ <NUM_LIT> ] = gen_rtx_REG ( DImode , <NUM_LIT> ) ; if ( length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = <NUM_LIT> ; if ( ! nullify && length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = forward_branch_p ( insn ) ; useskip = ( length == <NUM_LIT> && nullify ) ? use_skip_p ( insn ) : FALSE ; switch ( length ) { case <NUM_LIT> : if ( useskip ) strcpy ( buf , <STR_LIT> ) ; else strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; if ( useskip ) strcat ( buf , <STR_LIT> ) ; else if ( nullify ) { if ( branch_needs_nop_p ( insn ) ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; } else strcat ( buf , <STR_LIT> ) ; break ; case <NUM_LIT> : if ( dbr_sequence_length ( ) != <NUM_LIT> && ! forward_branch_p ( insn ) && nullify ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ; if ( negated ) strcat ( buf , <STR_LIT> ) ; else strcat ( buf , <STR_LIT> ) ; strcat ( buf , <STR_LIT> ) ; } else if ( dbr_sequence_length ( ) == <NUM_LIT> && ! forward_branch_p ( insn ) && INSN_ADDRESSES_SET_P ( ) && VAL_14_BITS_P ( INSN_ADDRESSES ( INSN_UID ( JUMP_LABEL ( insn ) ) ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) - <NUM_LIT> ) ) { strcpy ( buf , <STR_LIT> ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) strcat ( buf , <STR_LIT> ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( AMDGPUTargetMachine & tm , const TargetInstrInfo & tii ) : AMDGPURegisterInfo ( tm , tii ) , TM ( tm ) , TII ( tii ) {


<s> return ( uint16x4_t ) __builtin_neon_vrsubhnv4si ( ( int32x4_t ) __a , ( int32x4_t ) __b ) ;


<s> if ( ImmVal >= - <NUM_LIT> && ImmVal < <NUM_LIT> ) { Imm = CurDAG -> getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; return true ; } } return false ;


<s> bool PostRA = ! MRI . isSSA ( ) ; if ( ( ConstantOpNo != III . OpNoForForwarding ) && ! III . IsCommutative ) return false ; if ( Imm % III . ImmMustBeMultipleOf ) return false ; if ( III . TruncateImmTo ) Imm &= ( ( <NUM_LIT> << III . TruncateImmTo ) - <NUM_LIT> ) ; if ( III . SignedImm ) { APInt ActualValue ( <NUM_LIT> , Imm , true ) ; if ( ! ActualValue . isSignedIntN ( III . ImmWidth ) ) return false ; } else { uint64_t UnsignedMax = ( <NUM_LIT> << III . ImmWidth ) - <NUM_LIT> ; if ( ( uint64_t ) Imm > UnsignedMax ) return false ; } if ( PostRA && III . ZeroIsSpecialOrig != III . ZeroIsSpecialNew ) { unsigned PosForOrigZero = III . ZeroIsSpecialOrig ? III . ZeroIsSpecialOrig : III . ZeroIsSpecialNew + <NUM_LIT> ; Register OrigZeroReg = MI . getOperand ( PosForOrigZero ) . getReg ( ) ; Register NewZeroReg = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; if ( ( NewZeroReg == <STR_LIT> || NewZeroReg == <STR_LIT> ) && ConstantOpNo != III . ZeroIsSpecialNew ) return false ; if ( ( OrigZeroReg == <STR_LIT> || OrigZeroReg == <STR_LIT> ) && ConstantOpNo != PosForOrigZero ) return false ; } unsigned ForwardKilledOperandReg = ~ <NUM_LIT> ; if ( PostRA && MI . getOperand ( ConstantOpNo ) . isKill ( ) ) ForwardKilledOperandReg = MI . getOperand ( ConstantOpNo ) . getReg ( ) ; unsigned Opc = MI . getOpcode ( ) ;

bool SpecialShift32 = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> static <STR_LIT> getSwappedCondition ( <STR_LIT> CC ) { switch ( CC ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : break ; } DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ;

DecodeSImm < <NUM_LIT> > ( Inst , offset , Addr , Decoder ) ;


<s> unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsHigh = isHighReg ( Reg ) ; MI -> setDesc ( get ( IsHigh ? HighOpcode : LowOpcode ) ) ; if ( IsHigh && ConvertHigh ) MI -> getOperand ( <NUM_LIT> ) . setImm ( uint32_t ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ;


<s> } if ( ! loop -> incoming_dest ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , loop -> loop_no ) ; return false ; } if ( loop -> incoming_dest != loop -> head ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , loop -> loop_no ) ; return false ; } if ( loop -> has_call || loop -> has_asm ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , loop -> loop_no ) ; return false ; } if ( loop -> iter_reg_used || loop -> iter_reg_used_outside ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , loop -> loop_no ) ; return false ; } insn = loop -> start_label ; while ( insn && insn != loop -> loop_end ) insn = NEXT_INSN ( insn ) ; if ( ! insn ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> , loop -> loop_no ) ; return false ; } iter_reg = loop -> iter_reg ; gcc_assert ( REG_P ( iter_reg ) ) ; entry_edge = NULL ; FOR_EACH_VEC_SAFE_ELT ( loop -> incoming , i , entry_edge ) if ( entry_edge -> flags & EDGE_FALLTHRU ) break ; if ( entry_edge == NULL ) return false ; entry_bb = entry_edge -> src ; start_sequence ( ) ; insn = emit_insn ( gen_zero_cost_loop_start ( loop -> iter_reg , loop -> start_label , loop -> iter_reg ) ) ; seq = get_insns ( ) ; entry_after = BB_END ( entry_bb ) ; if ( ! single_succ_p ( entry_bb ) || vec_safe_length ( loop -> incoming ) > <NUM_LIT> || ! entry_after ) { basic_block new_bb ; edge e ; edge_iterator ei ; emit_insn_before ( seq , BB_HEAD ( loop -> head ) ) ; seq = emit_label_before ( gen_label_rtx ( ) , seq ) ; new_bb = create_basic_block ( seq , insn , entry_bb ) ; FOR_EACH_EDGE ( e , ei , loop -> incoming ) { if ( ! ( e -> flags & EDGE_FALLTHRU ) ) redirect_edge_and_branch_force ( e , new_bb ) ; else redirect_edge_succ ( e , new_bb ) ;


<s> default : return ; case <NUM_LIT> : RC = & AMDGPU :: VReg_32RegClass ; break ; case <NUM_LIT> : RC = & AMDGPU :: VReg_64RegClass ; break ; case <NUM_LIT> : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ;

MI -> setDesc ( TII -> get ( NewOpcode ) ) ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; i ++ ) BuildMI ( MBB , MI , dl , TII . get ( <STR_LIT> ) , CSI [ i ] . getReg ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printSpecialCapRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ;

auto SpecialCapReg = <STR_LIT> ( Imm ) ;


<s> DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DataLayoutPass * DLP = getAnalysisIfAvailable < DataLayoutPass > ( ) ; DL = DLP ? & DLP -> getDataLayout ( ) : nullptr ; LibInfo = getAnalysisIfAvailable < TargetLibraryInfo > ( ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> CallFlags ( CallingConv :: ID CC , bool IsTailCall , bool IsVarArg , bool IsPatchPoint , bool IsIndirect , bool HasNest ) : CallConv ( CC ) , IsTailCall ( IsTailCall ) , IsVarArg ( IsVarArg ) , IsPatchPoint ( IsPatchPoint ) , IsIndirect ( IsIndirect ) , HasNest ( HasNest ) {


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> emit_move_insn ( mem , a ) ; i = <NUM_LIT> ; } mem = adjust_address ( m_tramp , HImode , i + <NUM_LIT> ) ; emit_move_insn ( mem , gen_lowpart ( HImode , t1 ) ) ; emit_insn ( gen_ashrsi3 ( t1 , t1 , GEN_INT ( <NUM_LIT> ) ) ) ; mem = adjust_address ( m_tramp , HImode , i + <NUM_LIT> ) ; emit_move_insn ( mem , gen_lowpart ( HImode , t1 ) ) ; mem = adjust_address ( m_tramp , HImode , i + <NUM_LIT> ) ; emit_move_insn ( mem , gen_lowpart ( HImode , t2 ) ) ;


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVar ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GVar = dyn_cast_or_null < GlobalVariable > ( GA -> resolveAliasedGlobal ( ) ) ; } if ( ! GVar ) { assert ( <NUM_LIT> && <STR_LIT> ) ; return SDValue ( ) ; } const Type * Ty = cast < PointerType > ( GV -> getType ( ) ) -> getElementType ( ) ; if ( ! Ty -> isSized ( ) || isZeroLengthArray ( Ty ) ) { cerr << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> ; abort ( ) ; }

SDValue base = getGlobalAddressWrapper ( GA , GV , DAG ) ;


<s> bool IdxNIsKill = hasTrivialKill ( Idx ) ; MVT PtrVT = TLI . getPointerTy ( DL ) ; EVT IdxVT = EVT :: getEVT ( Idx -> getType ( ) , false ) ; if ( IdxVT . bitsLT ( PtrVT ) ) {

IdxN = emitIntExt ( IdxVT . getSimpleVT ( ) , IdxN , PtrVT , false ) ;


<s> const int this_slotno = data -> slotno + bitpos / BITS_PER_WORD ; machine_mode mode = DECL_MODE ( field ) ; int nregs , nslots ; if ( VECTOR_TYPE_P ( TREE_TYPE ( field ) ) && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = <NUM_LIT> ; } else nregs = <NUM_LIT> ; nslots = CEIL_NWORDS ( nregs * GET_MODE_SIZE ( mode ) ) ; if ( nslots > SPARC_FP_ARG_MAX - this_slotno ) { nslots = SPARC_FP_ARG_MAX - this_slotno ; nregs = ( nslots * UNITS_PER_WORD ) / GET_MODE_SIZE ( mode ) ; data -> stack = <NUM_LIT> ;

if ( nregs <= <NUM_LIT> ) return false ;


<s> if ( Opc != <STR_LIT> ) return false ; unsigned BN = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BitTracker :: RegisterRef RS = MI -> getOperand ( <NUM_LIT> ) ; unsigned F , W ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! BT . has ( RS . Reg ) || ! HBS :: getSubregMask ( RS , F , W , MRI ) ) return false ; MachineBasicBlock & B = * MI -> getParent ( ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; const BitTracker :: BitValue & V = SC [ F + BN ] ; if ( V . Type == BitTracker :: BitValue :: Ref && V . RefI . Reg != RS . Reg ) { const TargetRegisterClass * TC = MRI . getRegClass ( V . RefI . Reg ) ; unsigned P = UINT_MAX ; BitTracker :: RegisterRef RR ( V . RefI . Reg , <NUM_LIT> ) ; if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; RR . Sub = <STR_LIT> ; if ( P >= <NUM_LIT> ) { P -= <NUM_LIT> ; RR . Sub = <STR_LIT> ; } } else if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; } if ( P != UINT_MAX ) { unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( RR . Reg , <NUM_LIT> , RR . Sub ) . addImm ( P ) ; HBS :: replaceReg ( RD . Reg , NewR , MRI ) ;


<s> return ( regno == R0_REGNO || regno == MEM0_REGNO ) ;


<s> return ; } if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << getRegisterName ( MO1 . getReg ( ) ) ; if ( <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> ; return ; }

O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ;


<s> return _mm_getcsr ( ) & _MM_ROUND_MASK ;


<s> default : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> unsigned axis = TREE_INT_CST_LOW ( arg ) ; if ( axis < GOMP_DIM_WORKER ) return false ;

if ( dims [ axis ] == <NUM_LIT> ) return false ;


<s> MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , HRI . getFrameRegister ( ) , VT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512BWCostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasBWI ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512BWCostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ;

if ( ST -> hasAVX512 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ;


<s> static SDValue combineFMA ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; auto invertIfNegative = [ & DAG ] ( SDValue & V ) { if ( SDValue NegVal = isFNEG ( V . getNode ( ) ) ) { V = DAG . getBitcast ( V . getValueType ( ) , NegVal ) ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) {

if ( SDValue NegVal = isFNEG ( V . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) {


<s> for ( auto RegNo : getRegList ( ) ) Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ;


<s> OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; case <NUM_LIT> : OS << <STR_LIT> ; break ; } unsigned VReg = RegNo & <NUM_LIT> ; OS << VReg ;


<s> } for ( aedges :: iterator i ( BackEdges . begin ( ) ) , ie ( BackEdges . end ( ) ) ; i != ie ; i ++ ) {

rewriteEdge ( i -> second -> Src , i -> second -> Dst ) ;


<s> return ( __m128i ) __builtin_ia32_pmovdb128_mask ( ( __v4si ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) return true ; switch ( I . getOpcode ( ) ) { default : break ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_CONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP :


<s> bool isRegList16 ( ) const { if ( ! isRegList ( ) ) return false ; int Size = RegList . List -> size ( ) ; if ( Size < <NUM_LIT> || Size > <NUM_LIT> || * RegList . List -> begin ( ) != <STR_LIT> || RegList . List -> back ( ) != <STR_LIT> ) return false ; int PrevReg = * RegList . List -> begin ( ) ; for ( int i = <NUM_LIT> ; i < Size - <NUM_LIT> ; i ++ ) { int Reg = ( * ( RegList . List ) ) [ i ] ; if ( Reg != PrevReg + <NUM_LIT> ) return false ;


<s> reportParseError ( <STR_LIT> ) ; return false ; } const MCExpr * StackOffset ; int64_t StackOffsetVal ; if ( Parser . parseExpression ( StackOffset ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! StackOffset -> evaluateAsAbsolute ( StackOffsetVal , getStreamer ( ) ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( StackOffsetVal < <NUM_LIT> ) { Warning ( Loc , <STR_LIT> ) ; IsCpRestoreSet = false ; } else { IsCpRestoreSet = true ; CpRestoreOffset = StackOffsetVal ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! getTargetStreamer ( ) . emitDirectiveCpRestore ( CpRestoreOffset , [ & ] ( ) { return getATReg ( Loc ) ; } , Loc , STI ) ) return true ; Parser . Lex ( ) ;


<s> bool isUImm3 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;

return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> LoadSDNode * LD = cast < LoadSDNode > ( N ) ; EVT LoadedVT = LD -> getMemoryVT ( ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM == <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || AM != <STR_LIT> || LoadedVT . getSimpleVT ( ) . SimpleTy != <STR_LIT> ) return false ; auto * COffs = dyn_cast < ConstantSDNode > ( LD -> getOffset ( ) ) ; if ( ! COffs || COffs -> getZExtValue ( ) != <NUM_LIT> ) return false ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , getAL ( CurDAG , SDLoc ( N ) ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ) ;


<s> if ( LHS . getValueType ( ) . isInteger ( ) ) { assert ( ( LHS . getValueType ( ) == RHS . getValueType ( ) ) && ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ) ; const ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( RHSC && RHSC -> getZExtValue ( ) == <NUM_LIT> ) { if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> ) { uint64_t Mask = LHS . getValueSizeInBits ( ) - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , DAG . getConstant ( Mask , dl , <STR_LIT> ) , Dest ) ; } } if ( RHSC && RHSC -> getSExtValue ( ) == - <NUM_LIT> && CC == <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> ) { uint64_t Mask = LHS . getValueSizeInBits ( ) - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , DAG . getConstant ( Mask , dl , <STR_LIT> ) , Dest ) ;


<s> const MachineOperand & Segment = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( Segment . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O , Modifier ) ; O << ':' ; } printLeaMemReference ( MI , Op , O , Modifier ) ;


<s> case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } case <NUM_LIT> : { switch ( Model ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return ( Em64T ) ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : return ( Em64T ) ? <STR_LIT> : <STR_LIT> ; } } default : return <STR_LIT> ; } } else if ( memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { switch ( Family ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : switch ( Model ) { case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; default : return <STR_LIT> ; } case <NUM_LIT> : switch ( Model ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> if ( ExtractedIndex . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! IndicesVec ) IndicesVec = ExtractedIndex . getOperand ( <NUM_LIT> ) ; else if ( IndicesVec != ExtractedIndex . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; auto * PermIdx = dyn_cast < ConstantSDNode > ( ExtractedIndex . getOperand ( <NUM_LIT> ) ) ; if ( ! PermIdx || PermIdx -> getZExtValue ( ) != Idx ) return SDValue ( ) ; } MVT VT = V . getSimpleValueType ( ) ; MVT ShuffleVT = VT ; unsigned Opcode = LegalPermuteOpcode ( VT , ShuffleVT ) ; if ( ! Opcode ) return SDValue ( ) ; assert ( VT . getScalarSizeInBits ( ) == ShuffleVT . getScalarSizeInBits ( ) && VT . getVectorNumElements ( ) == ShuffleVT . getVectorNumElements ( ) && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( IndicesVec . getValueType ( ) . getVectorNumElements ( ) < NumElts ) return SDValue ( ) ; else if ( IndicesVec . getValueType ( ) . getVectorNumElements ( ) > NumElts ) { IndicesVec = extractSubVector ( IndicesVec , <NUM_LIT> , DAG , SDLoc ( IndicesVec ) , NumElts * VT . getScalarSizeInBits ( ) ) ; } MVT IndicesVT = EVT ( VT ) . changeVectorElementTypeToInteger ( ) . getSimpleVT ( ) ; IndicesVec = DAG . getZExtOrTrunc ( IndicesVec , SDLoc ( IndicesVec ) , IndicesVT ) ; if ( SrcVec . getValueSizeInBits ( ) > VT . getSizeInBits ( ) ) return SDValue ( ) ; else if ( SrcVec . getValueSizeInBits ( ) < VT . getSizeInBits ( ) ) { SrcVec = DAG . getNode ( <STR_LIT> , SDLoc ( SrcVec ) , VT , DAG . getUNDEF ( VT ) , SrcVec , DAG . getIntPtrConstant ( <NUM_LIT> , SDLoc ( SrcVec ) ) ) ; } SrcVec = DAG . getBitcast ( ShuffleVT , SrcVec ) ;

SDValue Res = Opcode == <STR_LIT> ? DAG . getNode ( Opcode , SDLoc ( V ) , ShuffleVT , IndicesVec , SrcVec ) : DAG . getNode ( Opcode , SDLoc ( V ) , ShuffleVT , SrcVec , IndicesVec ) ;


<s> return getGOT ( GN , DAG , OpFlags ) ; } SDValue Result ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) { Result = getAddrLarge ( GN , DAG , OpFlags ) ; } else if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Tiny ) { Result = getAddrTiny ( GN , DAG , OpFlags ) ; } else { Result = getAddr ( GN , DAG , OpFlags ) ; } EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( GN ) ;

if ( OpFlags & ( <STR_LIT> | <STR_LIT> ) ) Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> } } else { assert ( ( Offset + FulleSizeInBytes ) <= DataSize && <STR_LIT> ) ; assert ( NumBytes <= FulleSizeInBytes && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = FulleSizeInBytes - <NUM_LIT> - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; }


<s> void timode_scalar_chain :: mark_dual_mode_def ( df_ref ) { gcc_unreachable ( ) ;


<s> if ( IsRIPRel ) { SDValue Val = N . getOperand ( <NUM_LIT> ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) IsRIPRelTLS = true ; } CodeModel :: Model M = TM . getCodeModel ( ) ; if ( Subtarget -> is64Bit ( ) && ( ( M == CodeModel :: Large && ! IsRIPRelTLS ) || ( M == CodeModel :: Medium && ! IsRIPRel ) ) ) return true ; if ( IsRIPRel && AM . hasBaseOrIndexReg ( ) ) return true ; <ISA_LIT>ISelAddressMode Backup = AM ; int64_t Offset = <NUM_LIT> ; SDValue N0 = N . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; Offset = G -> getOffset ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Alignment = CP -> getAlign ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; Offset = CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ;

} else if ( BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( N0 ) ) {


<s> bool <ISA_LIT>RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * InstrInfo = Subtarget . getInstrInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & Info = MFI . getCalleeSavedInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) ) return true ; unsigned FrameSize = MFI . getStackSize ( ) ; if ( FrameSize & ~ <NUM_LIT> ) return true ; for ( unsigned i = <NUM_LIT> ; i < Info . size ( ) ; i ++ ) { int FrIdx = Info [ i ] . getFrameIdx ( ) ; unsigned Reg = Info [ i ] . getReg ( ) ;

unsigned Opcode = InstrInfo -> getStoreOpcodeForSpill ( Reg ) ;


<s> Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_ThumbBranch22Bit ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_HalfDifference ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RelocType = unsigned ( macho :: RIT_<ISA_LIT>_Half ) ; Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; return true ; }


<s> rtx target = operands [ <NUM_LIT> ] ;

enum rtx_code code = GET_CODE ( operands [ <NUM_LIT> ] ) ;


<s> unsigned Start = <NUM_LIT> ; unsigned End = NumLaneElts / <NUM_LIT> ; for ( unsigned s = <NUM_LIT> ; s < NumLanes ; ++ s ) { for ( unsigned i = Start ; i != End ; ++ i ) { ShuffleMask . push_back ( i ) ; ShuffleMask . push_back ( i + NumLaneElts ) ;


if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ;


<s> RTVEC_ELT ( vec , <NUM_LIT> ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , CRIS_CC0_REGNUM ) ) ;

return emit_insn ( gen_rtx_PARALLEL ( VOIDmode , vec ) ) ;


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( PhysReg ) ) ; if ( TM . isELFv2ABI ( ) && PhysReg == <STR_LIT> ) {

return ( getReservedRegs ( MF ) . test ( <STR_LIT> ) ) ;


<s> case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_ABS_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_TPREL_HI ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_Mips_TPREL_LO ; break ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , Kind , Ctx ) ;


<s> if ( skipFunction ( * MF . getFunction ( ) ) || No<ISA_LIT>CFOpt . getValue ( ) ) return false ; return false ;


<s> static void ATTRIBUTE_UNUSED nios2_init_libfuncs ( void ) { init_sync_libfuncs ( UNITS_PER_WORD ) ;


<s> for ( MachineBasicBlock * PB : BB -> predecessors ( ) ) { if ( ! Visited . insert ( PB ) . second ) continue ; if ( PB == BB ) continue ;

for ( auto I = PB -> instr_rbegin ( ) , E = PB -> instr_rend ( ) ; I != E ; ++ I ) {


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) {

return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> break ; case TYPE_DIV : if ( divmod_p ( producer ) ) { rtx def_reg1 = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ; rtx def_reg2 = SET_DEST ( parallel_element ( producer , <NUM_LIT> ) ) ;

return ( n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg1 ) || n9_3r2w_consumed_by_ex_dep_p ( consumer , def_reg2 ) ) ;


<s> std :: vector < std :: string > mov_mixp_r6 ( ) { return D ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


return __builtin_ia32_vcvtph2psx256_mask ( __B , _mm256_setzero_ps ( ) , __A ) ;


<s> insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; riscv_emit_stack_tie ( ) ; } if ( size > <NUM_LIT> ) {


<s> int hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return ( regno & <NUM_LIT> ) == <NUM_LIT> && GPR_P ( regno ) ; else return <NUM_LIT> ;


<s> create<ISA_LIT>DelaySlotFillerPass ( const <ISA_LIT>TargetMachine & tm , bool ForceDisable ) {

return new <ISA_LIT>DelaySlotFiller ( tm , ForceDisable ) ;


<s> static SDValue lowerVECTOR_SHUFFLE_ILVEV ( SDValue Op , EVT ResTy , SmallVector < int , <NUM_LIT> > Indices , SelectionDAG & DAG ) { assert ( ( Indices . size ( ) % <NUM_LIT> ) == <NUM_LIT> ) ; int WsIdx = <NUM_LIT> ; int WtIdx = ResTy . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < Indices . size ( ) ; i += <NUM_LIT> ) { if ( Indices [ i ] != - <NUM_LIT> && Indices [ i ] != WsIdx ) return SDValue ( ) ;

if ( Indices [ i + <NUM_LIT> ] != - <NUM_LIT> && Indices [ i + <NUM_LIT> ] != WtIdx ) return SDValue ( ) ;


<s> GetCommentOS ( ) << <STR_LIT> ; } if ( InstPrinter ) InstPrinter -> printInst ( & Inst , OS , <STR_LIT> ) ; else Inst . print ( OS , & MAI ) ; EmitEOL ( ) ;


<s> int MaskIdx = Mask [ i ] ; int ExpectedIdx = ExpectedMask [ i ] ; if ( MaskIdx == SM_SentinelUndef || MaskIdx == ExpectedIdx ) continue ; if ( <NUM_LIT> <= Mask [ i ] && <NUM_LIT> <= ExpectedMask [ i ] ) { SDValue MaskV = MaskIdx < Size ? V1 : V2 ; SDValue ExpectedV = ExpectedIdx < Size ? V1 : V2 ; MaskIdx = MaskIdx < Size ? MaskIdx : ( MaskIdx - Size ) ; ExpectedIdx = ExpectedIdx < Size ? ExpectedIdx : ( ExpectedIdx - Size ) ; if ( IsElementEquivalent ( Size , MaskV , ExpectedV , MaskIdx , ExpectedIdx ) ) continue ; } return false ; } return true ;


<s> static bool usesLGKM_CNT ( const MachineInstr & MI ) {

return MI . getDesc ( ) . TSFlags & <STR_LIT> ;


<s> if ( ! ( CN = dyn_cast < ConstantSDNode > ( ShiftRight . getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; uint64_t Pos = CN -> getZExtValue ( ) ; uint64_t SMPos , SMSize ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Mask ) ) || ! IsShiftedMask ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ;

EVT ValTy = N -> getValueType ( <NUM_LIT> ) ;


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; const TargetRegisterInfo * RI = STI -> getRegisterInfo ( ) ; Register Reg = MO . getReg ( ) ; unsigned RegToPrint = RC -> getRegister ( RI -> getEncodingValue ( Reg ) ) ;

assert ( RI -> regsOverlap ( RegToPrint , Reg ) ) ;


<s> ShuffleVT = <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; ShuffleVT = Mask . size ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return true ; } if ( Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || Mask . equals ( { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) {


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) {

BaseT :: getUnrollingPreferences ( L , SE , UP ) ;


<s> return new <ISA_LIT>ExternalAAWrapper ( ) ;


<s> static bool m68k_interrupt_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; a = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func ) ) ;


<s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ;

return isLegalElementTypeForRVV ( DataType -> getScalarType ( ) ) ;


<s> return ( uint32x4_t ) __builtin_aarch64_uaddlv4hi ( ( int16x4_t ) __a , ( int16x4_t ) __b ) ;