<s> const AsmToken Tok2 = Parser . getTok ( ) ; SMLoc E ; const MCExpr * EVal ; if ( ! Tok2 . is ( AsmToken :: Integer ) || getParser ( ) . parseExpression ( EVal , E ) ) { getLexer ( ) . UnLex ( Tok1 ) ; return MatchOperand_NoMatch ; } const AsmToken Tok3 = Parser . getTok ( ) ; if ( ! Tok3 . is ( AsmToken :: RParen ) ) { getLexer ( ) . UnLex ( Tok2 ) ; getLexer ( ) . UnLex ( Tok1 ) ; return MatchOperand_NoMatch ; } Parser . Lex ( ) ; const AsmToken & Tok4 = Parser . getTok ( ) ; StringRef Suffix = Tok4 . getString ( ) ; if ( Suffix != <STR_LIT> && Suffix != <STR_LIT> ) {


<s> RegisterTarget < Triple :: vc4 > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> RegisterTargetMachine < <ISA_LIT>V8TargetMachine > X ( The<ISA_LIT>Target ) ;

RegisterTargetMachine < <ISA_LIT>V9TargetMachine > Y ( The<ISA_LIT>V9Target ) ;


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ;


<s> return ( __m64 ) __builtin_ia32_psllq ( __m , __count ) ;


<s> SDValue LV ; if ( <NUM_LIT> * HwLen == VecLen ) { SDValue B0 = DAG . getBuildVector ( SingleTy , dl , { Ops . data ( ) , HwLen } ) ; SDValue L0 = Lower . LowerOperation ( B0 , DAG ) ; SDValue B1 = DAG . getBuildVector ( SingleTy , dl , { Ops . data ( ) + HwLen , HwLen } ) ; SDValue L1 = Lower . LowerOperation ( B1 , DAG ) ; LV = DAG . getNode ( <STR_LIT> , dl , ResTy , { L0 , L1 } ) ; } else { SDValue BV = DAG . getBuildVector ( ResTy , dl , Ops ) ; LV = Lower . LowerOperation ( BV , DAG ) ; } assert ( ! N -> use_empty ( ) ) ; SDValue IS = DAG . getNode ( <STR_LIT> , dl , ResTy , LV ) ; ISel . ReplaceNode ( N , IS . getNode ( ) ) ; select ( IS . getNode ( ) ) ; DAG . RemoveDeadNodes ( ) ; return true ;


<s> const ReturnInst * Ret = cast < ReturnInst > ( I ) ; if ( ! FuncInfo . CanLowerReturn ) return false ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) {


<s> bool wasResultExplicitMentioned ( ) { return ExplicitMentioned ;


<s> if ( V1 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( <NUM_LIT> ) ) ; } if ( V1 . getOpcode ( ) == <STR_LIT> ) { bool IsScalarToVector = true ; for ( unsigned i = <NUM_LIT> , e = V1 . getNumOperands ( ) ; i != e ; ++ i ) if ( V1 . getOperand ( i ) . getOpcode ( ) != <STR_LIT> && i != ( unsigned ) Lane ) { IsScalarToVector = false ; break ; } if ( IsScalarToVector ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( Lane ) ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , V1 , DAG . getConstant ( Lane , <STR_LIT> ) ) ; } int Length = ShuffleMask . size ( ) ; int V1EltNum = V1 . getValueType ( ) . getVectorNumElements ( ) ; if ( V1EltNum == Length ) { bool IsSequential = true ; int CurMask = ShuffleMask [ <NUM_LIT> ] ; for ( int I = <NUM_LIT> ; I < Length ; ++ I ) { if ( ShuffleMask [ I ] != CurMask ) { IsSequential = false ; break ; } CurMask ++ ; } if ( IsSequential ) { assert ( ( EltSize % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; unsigned VecSize = EltSize * V1EltNum ; unsigned Index = ( EltSize / <NUM_LIT> ) * ShuffleMask [ <NUM_LIT> ] ; if ( VecSize == <NUM_LIT> || VecSize == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( Index , <STR_LIT> ) ) ; } } SmallVector < int , <NUM_LIT> > NV1Elt ; SmallVector < int , <NUM_LIT> > N1Index ; SmallVector < int , <NUM_LIT> > NV2Elt ; SmallVector < int , <NUM_LIT> > N2Index ; for ( int I = <NUM_LIT> ; I != Length ; ++ I ) { if ( ShuffleMask [ I ] != I ) { NV1Elt . push_back ( ShuffleMask [ I ] ) ; N1Index . push_back ( I ) ; } } for ( int I = <NUM_LIT> ; I != Length ; ++ I ) { if ( ShuffleMask [ I ] != ( I + V1EltNum ) ) {

NV2Elt . push_back ( ShuffleMask [ I ] ) ;


<s> uint64_t Offset = ST . getTargetLowering ( ) -> getImplicitParameterOffset ( B . getMF ( ) , <ISA_LIT>TargetLowering :: FIRST_IMPLICIT ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( DstReg ) ; LLT IdxTy = LLT :: scalar ( DstTy . getSizeInBits ( ) ) ; const ArgDescriptor * Arg ; const TargetRegisterClass * RC ;

std :: tie ( Arg , RC ) = MFI -> getPreloadedValue ( <STR_LIT> ) ;


<s> if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; if ( Identifier . consume_back ( <STR_LIT> ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) { getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } Res = V ; } else Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; MCBinaryExpr :: Opcode Opcode ; switch ( getLexer ( ) . getKind ( ) ) { default : Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success ; case AsmToken :: Plus :


<s> switch ( Kind ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 : break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HHI8 : Value >>= <NUM_LIT> ; break ;


<s> } <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) { continue ; } if ( isRegOrImmWithInputMods ( Desc , Inst . getNumOperands ( ) ) ) { Op . addRegWithFPInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isDPPCtrl ( ) ) { Op . addImmOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { llvm_unreachable ( <STR_LIT> ) ; } }

addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDppRowMask , <NUM_LIT> ) ;


<s> for ( int i = <NUM_LIT> ; i < NumResults ; i ++ ) Results . push_back ( N . getOperand ( i ) ) ;


<s> if ( MC . isReg ( ) ) O << getRegisterName ( MC . getReg ( ) ) ; else if ( MC . isImm ( ) ) O << MC . getImm ( ) ; else if ( MC . isExpr ( ) ) MC . getExpr ( ) -> print ( O , & MAI , true ) ;


<s> break ; case <STR_LIT> : Op = emitIntrinsicWithGlue ( DAG , C . Op0 , C . Opcode ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return SDValue ( Op . getNode ( ) , Op -> getNumValues ( ) - <NUM_LIT> ) ; } if ( C . Opcode == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , C . Op0 , C . Op1 , DAG . getConstant ( C . ICmpType , DL , <STR_LIT> ) ) ; if ( C . Opcode == <STR_LIT> ) {

bool RegisterOnly = ( bool ( C . CCMask & <STR_LIT> ) != bool ( C . CCMask & <STR_LIT> ) ) ;


<s> SDLoc DL ( LD ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , NewLD1 . getValue ( <NUM_LIT> ) , OffsetPtr , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) / <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getTargetLoweringInfo ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; DCI . RemoveFromWorklist ( LD ) ;


<s> if ( ( Idx == <NUM_LIT> ) && Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TCC_Free ; break ; case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ;


<s> O << * GetGlobalValueSymbol ( MO . getGlobal ( ) ) ; printOffset ( MO . getOffset ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ;


<s> BlackfinAsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCContext & Ctx , MCStreamer & Streamer , const MCAsmInfo * MAI ) : AsmPrinter ( O , TM , Ctx , Streamer , MAI ) {


<s> SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Vec . getValueType ( ) ; unsigned VecSize = VecVT . getSizeInBits ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; DAGCombinerInfo DCI ( DAG , AfterLegalizeVectorOps , true , nullptr ) ; if ( SDValue Combined = performExtractVectorEltCombine ( Op . getNode ( ) , DCI ) ) return Combined ; if ( VecSize == <NUM_LIT> ) { SDValue Lo , Hi ; EVT LoVT , HiVT ; SDValue V2 = DAG . getBitcast ( <STR_LIT> , Vec ) ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VecVT ) ; Lo = DAG . getBitcast ( LoVT , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , V2 , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ) ; Hi = DAG . getBitcast ( HiVT , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , V2 , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ) ; EVT IdxVT = Idx . getValueType ( ) ; unsigned NElem = VecVT . getVectorNumElements ( ) ; assert ( isPowerOf2_32 ( NElem ) ) ; SDValue IdxMask = DAG . getConstant ( NElem / <NUM_LIT> - <NUM_LIT> , SL , IdxVT ) ; SDValue NewIdx = DAG . getNode ( <STR_LIT> , SL , IdxVT , Idx , IdxMask ) ; SDValue Half = DAG . getSelectCC ( SL , Idx , IdxMask , Hi , Lo , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SL , EltVT , Half , NewIdx ) ; } assert ( VecSize <= <NUM_LIT> ) ; MVT IntVT = <STR_LIT> ( VecSize ) ; SDValue VecBC = peekThroughBitcasts ( Vec ) ; if ( VecBC . getOpcode ( ) == <STR_LIT> ) { SDValue Src = VecBC . getOperand ( <NUM_LIT> ) ; Src = DAG . getBitcast ( Src . getValueType ( ) . changeTypeToInteger ( ) , Src ) ; Vec = DAG . getAnyExtOrTrunc ( Src , SL , IntVT ) ; } unsigned EltSize = EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( EltSize ) ) ; SDValue ScaleFactor = DAG . getConstant ( Log2_32 ( EltSize ) , SL , <STR_LIT> ) ; SDValue ScaledIdx = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Idx , ScaleFactor ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , IntVT , Vec ) ;

SDValue Elt = DAG . getNode ( <STR_LIT> , SL , IntVT , BC , ScaledIdx ) ;


<s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const <ISA_LIT>InstrInfo & LII = * static_cast < const <ISA_LIT>InstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;

BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> bool hasStdExtZhinx ( ) const { return HasStdExtZhinx ;


<s> static void ReadByValArg ( MachineFunction & MF , SDValue Chain , DebugLoc dl , std :: vector < SDValue > & OutChains , SelectionDAG & DAG , unsigned NumWords , SDValue FIN , const CCValAssign & VA , const <STR_LIT> & Flags ) { unsigned LocMem = VA . getLocMemOffset ( ) ; unsigned FirstWord = LocMem / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumWords ; ++ i ) { unsigned CurWord = FirstWord + i ; if ( CurWord >= O32IntRegsSize ) break ;

unsigned SrcReg = O32IntRegs [ CurWord ] ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti , mii ) , Parser ( Parser ) , Lexer ( Parser . getLexer ( ) ) , LastLabel ( nullptr ) {

setAvailableFeatures ( ComputeAvailableFeatures ( sti . getFeatureBits ( ) ) ) ;


<s> switch ( unspec ) { case UNSPEC_PIC_SYM : return <STR_LIT> ; case UNSPEC_PIC_CALL_SYM : return <STR_LIT> ; case UNSPEC_PIC_GOTOFF_SYM : return <STR_LIT> ; case UNSPEC_LOAD_TLS_IE : return <STR_LIT> ; case UNSPEC_ADD_TLS_LE : return <STR_LIT> ; case UNSPEC_ADD_TLS_GD : return <STR_LIT> ;


<s> MVT SVT = VT . getScalarType ( ) ; MVT InVT = In . getValueType ( ) . getSimpleVT ( ) ; MVT InSVT = InVT . getScalarType ( ) ; if ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; if ( SVT == <STR_LIT> && VT . getSizeInBits ( ) < <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget . hasAVX512 ( ) && ! ( ! Subtarget . useAVX512Regs ( ) && VT . is256BitVector ( ) && InVT . is512BitVector ( ) ) ) { SmallVector < SDValue > ConcatOps ; if ( VT . getSizeInBits ( ) > <NUM_LIT> || ! collectConcatOps ( In . getNode ( ) , ConcatOps ) ) return SDValue ( ) ; } unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned NumPackedZeroBits = Subtarget . hasSSE41 ( ) ? NumPackedSignBits : <NUM_LIT> ; KnownBits Known = DAG . computeKnownBits ( In ) ; unsigned NumLeadingZeroBits = Known . countMinLeadingZeros ( ) ; if ( NumLeadingZeroBits >= ( InSVT . getSizeInBits ( ) - NumPackedZeroBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ; if ( SVT == <STR_LIT> && NumSignBits != InSVT . getSizeInBits ( ) ) return SDValue ( ) ; unsigned MinSignBits = InSVT . getSizeInBits ( ) - NumPackedSignBits ; if ( NumSignBits > MinSignBits ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ; if ( In . getOpcode ( ) == <STR_LIT> && N -> isOnlyUserOf ( In . getNode ( ) ) ) if ( const APInt * ShAmt = DAG . getValidShiftAmountConstant ( In , APInt :: getAllOnesValue ( VT . getVectorNumElements ( ) ) ) ) { if ( * ShAmt == MinSignBits ) { SDValue NewIn = DAG . getNode ( <STR_LIT> , DL , InVT , In -> ops ( ) ) ; return truncateVectorWithPACK ( <STR_LIT> , VT , NewIn , DL , DAG , Subtarget ) ; }


<s> if ( Opc ) { addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) ) , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; return true ; } } unsigned ValReg = getRegForValue ( Val ) ; if ( ValReg == <NUM_LIT> ) return false ; return <ISA_LIT>FastEmitStore ( VT , ValReg , AM ) ;


<s> } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ) return Result ; if ( SDValue Result = PerformORCombineToSMULWBT ( N , DCI , Subtarget ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ;


<s> if ( VT . getSimpleVT ( ) . isVector ( ) ) return false ; if ( VT == <STR_LIT> ) return false ;


<s> else if ( Unpacked && IsD16 && Ty . isVector ( ) ) LoadDstReg = B . getMRI ( ) -> createGenericVirtualRegister ( UnpackedTy ) ; else LoadDstReg = Dst ; if ( ! VIndex ) VIndex = B . buildConstant ( S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; auto MIB = B . buildInstr ( Opc ) . addDef ( LoadDstReg ) . addUse ( RSrc ) . addUse ( VIndex ) . addUse ( VOffset ) . addUse ( SOffset ) . addImm ( ImmOffset ) ; if ( IsTyped ) MIB . addImm ( Format ) ; MIB . addImm ( AuxiliaryData ) . addImm ( HasVIndex ? - <NUM_LIT> : <NUM_LIT> ) . addMemOperand ( MMO ) ; if ( LoadDstReg != Dst ) { B . setInsertPt ( B . getMBB ( ) , ++ B . getInsertPt ( ) ) ; if ( IsExtLoad ) B . buildTrunc ( Dst , LoadDstReg ) ; else { auto Unmerge = B . buildUnmerge ( S32 , LoadDstReg ) ; SmallVector < Register , <NUM_LIT> > Repack ; for ( unsigned I = <NUM_LIT> , N = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != N ; ++ I ) Repack . push_back ( B . buildTrunc ( EltTy , Unmerge . getReg ( I ) ) . getReg ( <NUM_LIT> ) ) ; B . buildMerge ( Dst , Repack ) ;


<s> Instruction * Load = tryCreateIncrementingGatScat ( I , Ptr , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = SelectInst :: Create ( Mask , Load , PassThru ) ; Builder . Insert ( Load ) ; } Root -> replaceAllUsesWith ( Load ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ;


<s> static bool sh_cannot_substitute_mem_equiv_p ( rtx ) { if ( TARGET_SHMEDIA ) return false ;


<s> ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue = DAG . getLoad ( LocVT , dl , Chain , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; } if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ;

if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ;


<s> for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; if ( ! Subtarget . is64Bit ( ) ) { getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 } , { p0 } ) . maxScalar ( <NUM_LIT> , s32 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UDIV , G_UREM } ) . legalFor ( { s8 , s16 , s32 } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR } ) . legalFor ( { { s8 , s8 } , { s16 , s8 } , { s32 , s8 } } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) . clampScalar ( <NUM_LIT> , s8 , s8 ) ; } setAction ( { G_BRCOND , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 } ) { setAction ( { G_ZEXT , Ty } , Legal ) ; setAction ( { G_SEXT , Ty } , Legal ) ;

setAction ( { G_ANYEXT , Ty } , Legal ) ;


<s> unsigned Reg = FPRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> if ( ! <STR_LIT> . contains ( DestReg , SrcReg ) ) return <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ;

AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ;


<s> static int rs6000_sched_reorder2 ( FILE * dump , int sched_verbose , rtx_insn * * ready , int * pn_ready , int clock_var ATTRIBUTE_UNUSED ) {

if ( sched_verbose ) fprintf ( dump , <STR_LIT> ) ;


<s> AMDGPUCFGStructurizer :: AMDGPUCFGStructurizer ( char & pid , TargetMachine & tm ) : MachineFunctionPass ( pid ) , TM ( tm ) , TII ( tm . getInstrInfo ( ) ) , TRI ( static_cast < const AMDGPURegisterInfo * > ( tm . getRegisterInfo ( ) ) ) {


<s> if ( ! dominated_by_p ( CDI_POST_DOMINATORS , bb , exit_bb ) ) return false ;


<s> if ( ! isLaneMaskReg ( Reg ) ) return false ; } if ( MI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; int64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm == <NUM_LIT> ) { Val = false ;


<s> OriginalMCID = & TII -> get ( I . OrigOpc ) ; for ( auto & Repl : I . ReplOpc ) ReplInstrMCID . push_back ( & TII -> get ( Repl ) ) ; if ( shouldReplaceInst ( MF , OriginalMCID , ReplInstrMCID ) ) { InterlEarlyExit [ Subtarget ] = false ; return false ; } ReplInstrMCID . clear ( ) ; }


<s> int num_ops ( ExpressionTree * s ) { int n = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < s -> m_num_vals ; i ++ ) { Expr * e = & s -> m_exprs [ i ] ; if ( e -> m_op != NULL ) n ++ ; } return n ;


<s> case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG , * this , hasHardQuad ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerF128Load ( Op , DAG ) ; case <STR_LIT> : return LowerF128Store ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG , * this , is64Bit ) ; case <STR_LIT> : return LowerFABS ( Op , DAG , isV9 ) ; case <STR_LIT> : return LowerF128_FPEXTEND ( Op , DAG , * this ) ; case <STR_LIT> : return LowerF128_FPROUND ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ;


<s> bool <ISA_LIT>InstrInfo :: isNewValueJump ( unsigned Opcode ) const {

return isNewValue ( Opcode ) && get ( Opcode ) . isBranch ( ) && isPredicated ( Opcode ) ;


<s> bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + <NUM_LIT> ) ; bitmap_clear ( components ) ; for ( unsigned regno = <NUM_LIT> ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( ( ! call_used_regs [ regno ] ) && ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) ) { unsigned regno2 , offset , offset2 ; bitmap_set_bit ( components , regno ) ; offset = cfun -> machine -> frame . reg_offset [ regno ] ; regno2 = ( ( offset & <NUM_LIT> ) == <NUM_LIT> ) ? regno + <NUM_LIT> : regno - <NUM_LIT> ; if ( regno2 <= LAST_SAVED_REGNUM ) { offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( ( offset & ~ <NUM_LIT> ) == ( offset2 & ~ <NUM_LIT> ) ) bitmap_set_bit ( components , regno2 ) ; }


<s> unsigned Opc = N -> getOpcode ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { if ( Opc == <STR_LIT> ) { AtomicSDNode * AN = cast < AtomicSDNode > ( N . getNode ( ) ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , RHS ) ; return DAG . getAtomic ( <STR_LIT> , DL , VT , Chain , LHS , RHS , AN -> getMemOperand ( ) , AN -> getOrdering ( ) , AN -> getSynchScope ( ) ) ; }

assert ( Opc == <STR_LIT> && <STR_LIT> ) ;


<s> <ISA_LIT>ClauseMergePass ( ) : MachineFunctionPass ( ID ) {


<s> cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( cur_tree ) ) ; } else { cur_tree = nios2_valid_target_attribute_tree ( args ) ; if ( ! cur_tree ) return false ; } target_option_current_node = cur_tree ;


<s> bool isTypedVectorList ( ) const { if ( Kind != k_VectorList ) return false ; if ( VectorList . Count != NumRegs ) return false ; if ( VectorList . ElementKind != ElementKind ) return false ;

return VectorList . NumElements == NumElements ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; if ( HasI64In ) { SDValue InLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op -> getOperand ( <NUM_LIT> + HasChainIn ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue InHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op -> getOperand ( <NUM_LIT> + HasChainIn ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , InLo , SDValue ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , InHi , Chain . getValue ( <NUM_LIT> ) ) ; Ops . push_back ( Chain ) ; Ops . append ( Op -> op_begin ( ) + HasChainIn + <NUM_LIT> , Op -> op_end ( ) ) ; Ops . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } else { Ops . push_back ( Chain ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> assert ( Candidate . packetIndexJ < MCB . size ( ) ) ; assert ( isBundle ( MCB ) ) ; MCInst * Duplex = deriveDuplex ( Context , Candidate . iClass , * MCB . getOperand ( Candidate . packetIndexJ ) . getInst ( ) , * MCB . getOperand ( Candidate . packetIndexI ) . getInst ( ) ) ; assert ( Duplex != nullptr ) ; MCB . getOperand ( Candidate . packetIndexI ) . setInst ( Duplex ) ;

MCB . erase ( MCB . begin ( ) + Candidate . packetIndexJ ) ;


<s> SUnit * UnslotedSU = PopInst ( AvailableAlus [ AluAny ] , AnyAlu ) ; if ( UnslotedSU ) AssignSlot ( UnslotedSU -> getInstr ( ) , Slot ) ; return UnslotedSU ;


<s> auto Op = TII . getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Op -> isReg ( ) && Op -> getReg ( ) != Exec ) return Op -> getReg ( ) ; Op = TII . getNamedOperand ( MI , <STR_LIT> :: src0 ) ; if ( Op -> isReg ( ) && Op -> getReg ( ) != Exec ) return Op -> getReg ( ) ;


<s> bool <ISA_LIT>InstrInfo :: BlockHasNoFallThrough ( const MachineBasicBlock & MBB ) const { return ( ! MBB . empty ( ) && isUncondBranch ( & MBB . back ( ) ) ) ;


<s> case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } if ( NegAcc ) { switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } if ( NegRes ) { switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;


<s> if ( is128BitLaneCrossingShuffleMask ( MaskEltVT , Mask ) ) { if ( Subtarget . hasAVX2 ( ) && MaskVT . is256BitVector ( ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( AllowFloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( Mask ) ; return true ; } if ( Subtarget . hasAVX512 ( ) && MaskVT . is512BitVector ( ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( AllowFloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( RepeatedMask ) ; return true ; } } } else if ( AllowFloatDomain && Subtarget . hasAVX ( ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , Mask . size ( ) ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } } if ( ( MaskScalarSizeInBits == <NUM_LIT> || MaskScalarSizeInBits == <NUM_LIT> ) && ! ContainsZeros && ( AllowIntDomain || Subtarget . hasAVX ( ) ) ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask < int > ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( AllowIntDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = <STR_LIT> ( ShuffleVT , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( WordMask ) ; return true ; } } if ( ! ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( LoMask ) ; return true ; } if ( isUndefOrInRange ( HiMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( LoMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { int OffsetHiMask [ <NUM_LIT> ] ;

for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) OffsetHiMask [ i ] = ( HiMask [ i ] < <NUM_LIT> ? HiMask [ i ] : HiMask [ i ] - <NUM_LIT> ) ;


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) && ! MFI -> getMode ( ) . allFP32Denormals ( ) ) return true ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) && ! MFI -> getMode ( ) . allFP64FP16Denormals ( ) ) return true ; MachineIRBuilder HelperBuilder ( MI ) ; GISelObserverWrapper DummyObserver ; LegalizerHelper Helper ( MF , DummyObserver , HelperBuilder ) ; HelperBuilder . setMBB ( * MI . getParent ( ) ) ; return Helper . lowerFMad ( MI ) == LegalizerHelper :: Legalized ;


<s> alias_set_type get_TOC_alias_set ( void ) { if ( set == - <NUM_LIT> ) set = new_alias_set ( ) ;


<s> Op = DAG . getNode ( <STR_LIT> , dl , VT128 , Op . getOperand ( <NUM_LIT> ) ) ; return insert128BitVector ( DAG . getUNDEF ( OpVT ) , Op , <NUM_LIT> , DAG , dl ) ; } assert ( OpVT . is128BitVector ( ) && OpVT . isInteger ( ) && OpVT != <STR_LIT> && <STR_LIT> ) ; if ( OpVT == <STR_LIT> || ( OpVT == <STR_LIT> && Subtarget . hasFP16 ( ) ) ) return Op ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getBitcast ( OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AnyExt ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: FPToUI } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: SIToFP } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: UIToFP } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_MustBeOn } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_MustBeOn } ; case <STR_LIT> : return { Instruction :: FDiv , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FDiv , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FDiv , FTZ_MustBeOn } ; case <STR_LIT> : return { SPC_Reciprocal , FTZ_Any } ; case <STR_LIT> : return { SPC_Reciprocal , FTZ_MustBeOff } ; case <STR_LIT> : return { SPC_Reciprocal , FTZ_MustBeOn } ; default : return { } ; } } ( ) ; if ( Action . FtzRequirement != FTZ_Any ) { StringRef Attr = II -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; DenormalMode Mode = parseDenormalFPAttribute ( Attr ) ; bool FtzEnabled = Mode . Output != DenormalMode :: IEEE ; if ( FtzEnabled != ( Action . FtzRequirement == FTZ_MustBeOn ) ) return nullptr ; } if ( Action . IID ) { SmallVector < Value * , <NUM_LIT> > Args ( II -> args ( ) ) ; Type * Tys [ ] = { II -> getArgOperand ( <NUM_LIT> ) -> getType ( ) } ; return CallInst :: Create ( <STR_LIT> ( II -> getModule ( ) , * Action . IID , Tys ) , Args ) ; } if ( Action . BinaryOp ) return BinaryOperator :: Create ( * Action . BinaryOp , II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) , II -> getName ( ) ) ; if ( Action . CastOp ) return CastInst :: Create ( * Action . CastOp , II -> getArgOperand ( <NUM_LIT> ) , II -> getType ( ) , II -> getName ( ) ) ; if ( ! Action . Special ) return nullptr ;


<s> return TARGET_32BIT ? arm_arm_address_cost ( x ) : arm_thumb_address_cost ( x ) ;


<s> if ( ! TARGET_ARCH64 && GET_MODE ( x ) == DImode ) { if ( GET_CODE ( y ) == UNSPEC && ( XINT ( y , <NUM_LIT> ) == UNSPEC_ADDV || XINT ( y , <NUM_LIT> ) == UNSPEC_SUBV || XINT ( y , <NUM_LIT> ) == UNSPEC_NEGV ) ) return CCVmode ; else return CCCmode ; } if ( TARGET_ARCH64 && GET_MODE ( x ) == DImode ) return CCXmode ; else return CCmode ;


<s> if ( TT . isOSNaCl ( ) || TT . isOSIAMCU ( ) ) ; else if ( TT . isArch64Bit ( ) || TT . isOSDarwin ( ) || TT . isWindowsMSVCEnvironment ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isOSIAMCU ( ) ) Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ;

if ( ( ! TT . isArch64Bit ( ) && TT . isOSWindows ( ) ) || TT . isOSIAMCU ( ) ) Ret += <STR_LIT> ;


<s> <ISA_LIT>V9TargetMachine :: <ISA_LIT>V9TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>TargetMachine ( T , TT , FS , true ) {


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain ;


<s> StringRef Option ; if ( Parser . parseIdentifier ( Option ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { if ( ! isABI_O32 ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { return parseDirectiveModuleFP ( ) ; } else if ( Option == <STR_LIT> ) { setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleSoftFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleHardFloat ( ) ;


<s> case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : Asm . getContext ( ) . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGE21 ) ; return true ; } return true ; case <STR_LIT> :


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) {


<s> SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue InsV = Insert128BitVector ( Zeros , V1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } if ( isShuffleHigh128VectorInsertLow ( SVOp ) ) { SDValue V = Extract128BitVector ( V1 , DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; SDValue InsV = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , VT ) , V , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } if ( isShuffleLow128VectorInsertHigh ( SVOp ) ) { SDValue V = Extract128BitVector ( V1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; SDValue InsV = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , VT ) , V , DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return DCI . CombineTo ( N , InsV ) ; } return SDValue ( ) ;


<s> assert ( ! CPE . isMachineConstantPoolEntry ( ) ) ;

if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CPE . Val . ConstVal ) ) {


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override {


<s> return ( ( REG_P ( x ) && v850_reg_ok_for_base_p ( x , strict_p ) ) || ( SUBREG_P ( x ) && REG_P ( SUBREG_REG ( x ) ) && v850_reg_ok_for_base_p ( SUBREG_REG ( x ) , strict_p ) ) ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return Bottom ;

MapType :: const_iterator F = Map . find ( R ) ;


<s> const TargetRegisterClass * <ISA_LIT>16RegisterInfo :: intRegClass ( unsigned Size ) const { assert ( Size == <NUM_LIT> ) ;


<s> if ( isFrameStoreOpcode ( MI . getOpcode ( ) ) && ! MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> uint64_t MaxAlign = TRI -> hasStackRealignment ( MF ) ? calculateMaxStackAlign ( MF ) : <NUM_LIT> ; if ( Offset > ProbeChunk ) { emitStackProbeInlineGenericLoop ( MF , MBB , MBBI , DL , Offset , MaxAlign % StackProbeSize ) ; } else { emitStackProbeInlineGenericBlock ( MF , MBB , MBBI , DL , Offset , MaxAlign % StackProbeSize ) ;


<s> TypePair ty ( const VectorPair & Ops ) const { return { Ops . first . getValueType ( ) . getSimpleVT ( ) , Ops . second . getValueType ( ) . getSimpleVT ( ) } ;


<s> bool <ISA_LIT>PromoteKernelArguments :: runOnFunction ( Function & F ) {

MemorySSA & MSSA = getAnalysis < MemorySSAWrapperPass > ( ) . getMSSA ( ) ;


<s> bool <ISA_LIT>InstrInfo :: isMovDualGroup ( const MachineInstr & MI , unsigned * pSrcG , unsigned * pDstG ) const { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; unsigned Sw = Op . getImm ( ) ; if ( Sw != <ISA_LIT>II :: SW_MDG_TYPE_SINGLE ) return false ; * pSrcG = ( Sw & <ISA_LIT>II :: SW_SRC_DUAL_GROUP ) >> <ISA_LIT>II :: SW_SRC_DUAL_GROUP_SHIFT ; * pDstG = ( Sw & <ISA_LIT>II :: SW_DST_DUAL_GROUP ) >> <ISA_LIT>II :: SW_DST_DUAL_GROUP_SHIFT ;


<s> SDValue B ; if ( ExtOpcode == <STR_LIT> ) { A = Op0 . getOperand ( <NUM_LIT> ) ; B = Op0 . getOperand ( <NUM_LIT> ) ; if ( A . getOpcode ( ) != B . getOpcode ( ) || A . getOperand ( <NUM_LIT> ) . getValueType ( ) != B . getOperand ( <NUM_LIT> ) . getValueType ( ) ) return SDValue ( ) ; ExtOpcode = A . getOpcode ( ) ; } if ( ExtOpcode != <STR_LIT> && ExtOpcode != <STR_LIT> ) return SDValue ( ) ; EVT Op0VT = A . getOperand ( <NUM_LIT> ) . getValueType ( ) ;

if ( Op0VT != <STR_LIT> && Op0VT != <STR_LIT> ) return SDValue ( ) ;


<s> unsigned EltBits = VT . getScalarSizeInBits ( ) ; unsigned ScalarBits = Op1 . getValueSizeInBits ( ) ; if ( ScalarBits < EltBits ) return SDValue ( ) ; if ( IsSignExt ) { if ( DAG . ComputeNumSignBits ( Op1 ) <= ( ScalarBits - NarrowSize ) ) return SDValue ( ) ; } else { APInt Mask = APInt :: getBitsSetFrom ( ScalarBits , NarrowSize ) ; if ( ! DAG . MaskedValueIsZero ( Op1 , Mask ) ) return SDValue ( ) ; } Op1 = DAG . getNode ( <STR_LIT> , DL , NarrowVT , Op1 , VL ) ; } else return SDValue ( ) ; Op0 = Op0 . getOperand ( <NUM_LIT> ) ; unsigned ExtOpc = IsSignExt ? <STR_LIT> : <STR_LIT> ; if ( Op0 . getValueType ( ) != NarrowVT ) Op0 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op0 , Mask , VL ) ; ExtOpc = IsVWMULSU ? <STR_LIT> : ExtOpc ; if ( Op1 . getValueType ( ) != NarrowVT ) Op1 = DAG . getNode ( ExtOpc , DL , NarrowVT , Op1 , Mask , VL ) ; unsigned WMulOpc = <STR_LIT> ;

if ( ! IsVWMULSU ) WMulOpc = IsSignExt ? <STR_LIT> : <STR_LIT> ;


<s> if ( IsTrivialInst ( * I ) ) continue ; if ( AluInstCount >= MaxFetchInst ) break ; if ( ( IsTex && ! TII -> usesTextureCache ( * I ) ) || ( ! IsTex && ! TII -> usesVertexCache ( * I ) ) ) break ; if ( ! isCompatibleWithClause ( * I , DstRegs ) ) break ; AluInstCount ++ ; ClauseContent . push_back ( & * I ) ; } MachineInstr * MIb = BuildMI ( MBB , ClauseHead , MBB . findDebugLoc ( ClauseHead ) , getHWInstrDesc ( IsTex ? CF_TC : CF_VC ) ) . addImm ( <NUM_LIT> ) . addImm ( AluInstCount - <NUM_LIT> ) ; return ClauseFile ( MIb , std :: move ( ClauseContent ) ) ;


<s> for ( const auto & Symbol : OutContext . getSymbols ( ) ) if ( ! Symbol . second -> isDefined ( ) ) TS -> emitExtern ( Symbol . second ) ;


<s> gimple_stmt_iterator gsi ; for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { gimple stmt = gsi_stmt ( gsi ) ; stmt_vec_info stmt_info = vinfo_for_stmt ( stmt ) ; if ( ! STMT_VINFO_RELEVANT_P ( stmt_info ) && ! STMT_VINFO_IN_PATTERN_P ( stmt_info ) ) not_vec_cost ++ ; } } free ( bbs ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << UNodeList . size ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UseN = * I ; assert ( ! ( UseN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && <STR_LIT> ) ; NodeAddr < StmtNode * > OwnerN = UseN . Addr -> getOwner ( * DFG ) ; MachineInstr * UseMI = OwnerN . Addr -> getCode ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << UseMI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * UseMI << <STR_LIT> ) ; int UseMOnum = - <NUM_LIT> ; unsigned NumOperands = UseMI -> getNumOperands ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumOperands - <NUM_LIT> ; ++ j ) {

const MachineOperand & op = UseMI -> getOperand ( j ) ;


<s> assert ( BaseMO . isReg ( ) && <STR_LIT> ) ; assert ( OffsetMO . isImm ( ) && <STR_LIT> ) ; int Offset = OffsetMO . getImm ( ) ; if ( ExtraCode ) { if ( ExtraCode [ <NUM_LIT> ] == 'D' ) Offset += <NUM_LIT> ; else return true ;


<s> bool PredicateDefinition :: can_merge_into_swap ( PredicateDefinition & other ) { return is_simple ( ) && other . is_simple ( ) && simple . type == RAInfo :: Register && other . simple . type == RAInfo :: Register && simple . predicate == other . simple . guard && simple . guard == other . simple . predicate ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; return Reserved ;


<s> extern __inline __m256i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_setr_epi64x ( long long __A , long long __B , long long __C , long long __D ) {


<s> return false ; } unsigned TUnpredCost = Probability . getNumerator ( ) * TCycles ; TUnpredCost /= Probability . getDenominator ( ) ; uint32_t Comp = Probability . getDenominator ( ) - Probability . getNumerator ( ) ; unsigned FUnpredCost = Comp * FCycles ; FUnpredCost /= Probability . getDenominator ( ) ; unsigned UnpredCost = TUnpredCost + FUnpredCost ; UnpredCost += <NUM_LIT> ;


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn & <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ;


<s> addRegOperands ( Inst , N ) ; } else { Inst . addOperand ( MCOperand :: createImm ( Imm . Modifiers ) ) ; addImmOperands ( Inst , N , false ) ;


<s> if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ; return <NUM_LIT> ; }


<s> } MachineBasicBlock * EmptyMBB = MF . CreateMachineBasicBlock ( ) ; MF . push_back ( EmptyMBB ) ; DebugLoc DL ; AddDefaultPred ( BuildMI ( * EmptyMBB , EmptyMBB -> end ( ) , DL , TM . getInstrInfo ( ) -> get ( <STR_LIT> ) ) ) ;


<s> if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) {

MI . setDesc ( MII . get ( <STR_LIT> ) ) ;


<s> return new MandarinDAGToDAGISel ( TM ) ;


<s> unsigned Opc = N -> getOpcode ( ) ; assert ( ( ( Opc >= <STR_LIT> && Opc <= <STR_LIT> ) || ( Opc >= <STR_LIT> && Opc <= <STR_LIT> ) ) && <STR_LIT> ) ; const bool Scaled = Opc == <STR_LIT> || Opc == <STR_LIT> ; const bool Signed = Opc == <STR_LIT> || Opc == <STR_LIT> ; const bool Extended = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; SDLoc DL ( N ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Pg = N -> getOperand ( <NUM_LIT> ) ; SDValue Base = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; SDValue Ty = N -> getOperand ( <NUM_LIT> ) ;

EVT ResVT = N -> getValueType ( <NUM_LIT> ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const {


<s> MachineBasicBlock :: iterator MII = Inst ; DebugLoc DL = Inst -> getDebugLoc ( ) ; MachineOperand & Dest = Inst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = Inst -> getOperand ( <NUM_LIT> ) ; const MCInstrDesc & InstDesc = get ( AMDGPU :: V_BCNT_U32_B32_e64 ) ; const TargetRegisterClass * SrcRC = Src . isReg ( ) ? MRI . getRegClass ( Src . getReg ( ) ) : & AMDGPU :: SGPR_32RegClass ; unsigned MidReg = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; unsigned ResultReg = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; const TargetRegisterClass * SrcSubRC = RI . getSubRegClass ( SrcRC , AMDGPU :: sub0 ) ;

MachineOperand SrcRegSub0 = buildExtractSubRegOrImm ( MII , MRI , Src , SrcRC , AMDGPU :: sub0 , SrcSubRC ) ;


<s> SDValue GLC , TFE , DLC , SWZ ; return SelectMUBUFOffset ( Addr , SRsrc , Soffset , Offset , GLC , SLC , TFE , DLC , SWZ ) ;


<s> bool IsIntrin = Node24 -> getOpcode ( ) == <STR_LIT> ; SDValue LHS = IsIntrin ? Node24 -> getOperand ( <NUM_LIT> ) : Node24 -> getOperand ( <NUM_LIT> ) ; SDValue RHS = IsIntrin ? Node24 -> getOperand ( <NUM_LIT> ) : Node24 -> getOperand ( <NUM_LIT> ) ; unsigned NewOpcode = Node24 -> getOpcode ( ) ; if ( IsIntrin ) { unsigned IID = cast < ConstantSDNode > ( Node24 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; NewOpcode = IID == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } APInt Demanded = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ; SDValue DemandedLHS = DAG . GetDemandedBits ( LHS , Demanded ) ; SDValue DemandedRHS = DAG . GetDemandedBits ( RHS , Demanded ) ;

if ( DemandedLHS || DemandedRHS ) return DAG . getNode ( NewOpcode , SDLoc ( Node24 ) , Node24 -> getVTList ( ) , DemandedLHS ? DemandedLHS : LHS , DemandedRHS ? DemandedRHS : RHS ) ;


<s> EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasFP16 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode , DL , N00Type , N00 , N10 ) ;

return DAG . getBitcast ( VT , FPLogic ) ;


<s> unsigned <ISA_LIT>FrameLowering :: getFPReg ( const MachineFunction & MF ) {

return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAddr64 ( ) ? <STR_LIT> : <STR_LIT> ;


<s> std :: pair < unsigned , unsigned > WavesPerEU = MFI . getWavesPerEU ( ) ; unsigned MaxNumSGPRs = getMaxNumSGPRs ( WavesPerEU . first , false ) ; unsigned MaxAddressableNumSGPRs = getMaxNumSGPRs ( WavesPerEU . first , true ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Requested = <STR_LIT> ( F , <STR_LIT> , MaxNumSGPRs ) ; if ( Requested && ( Requested <= getReservedNumSGPRs ( MF ) ) ) Requested = <NUM_LIT> ; unsigned InputNumSGPRs = MFI . getNumPreloadedSGPRs ( ) ; if ( Requested && Requested < InputNumSGPRs ) Requested = InputNumSGPRs ; if ( Requested && Requested > getMaxNumSGPRs ( WavesPerEU . first , false ) ) Requested = <NUM_LIT> ; if ( WavesPerEU . second && Requested && Requested < getMinNumSGPRs ( WavesPerEU . second ) ) Requested = <NUM_LIT> ;

if ( Requested ) MaxNumSGPRs = Requested ;


<s> machine_mode mode = TYPE_MODE ( ret_type ) ; if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && GET_MODE_SIZE ( mode ) < <NUM_LIT> && ! COMPLEX_MODE_P ( mode ) ) return gen_rtx_REG ( SImode , FUNC_RETURN_REGNUM ) ; return gen_rtx_REG ( mode , FUNC_RETURN_REGNUM ) ;


<s> return ( int16x4_t ) __builtin_neon_vdup_lanev4hi ( __a , __b ) ;


<s> if ( req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode && req_mode != CCSRmode && req_mode != CCURmode && req_mode != CCZ1mode ) return <NUM_LIT> ; break ; case E_CCAPmode : case E_CCANmode : if ( req_mode != CCAmode ) return <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } return ( GET_MODE ( SET_SRC ( set ) ) == set_mode ) ;


<s> } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( is64Bit ( ) ) {

if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) return <STR_LIT> ;


<s> unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; return <NUM_LIT> * NumLoads ; } unsigned Cost = VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ? FloatFactor : <NUM_LIT> ; Alignment = std :: min ( Alignment , <NUM_LIT> ) ; unsigned AlignWidth = <NUM_LIT> * std :: max ( <NUM_LIT> , Alignment ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ;

if ( Alignment == <NUM_LIT> || Alignment == <NUM_LIT> ) return Cost * NumLoads ;


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { if ( dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) || dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { return false ; } R1 = N . getOperand ( <NUM_LIT> ) ; R2 = N . getOperand ( <NUM_LIT> ) ; return true ; }


<s> if ( EnableSROA ) addPass ( createSROAPass ( ) ) ; addStraightLineScalarOptimizationPasses ( ) ; if ( Enable<ISA_LIT>AliasAnalysis ) { addPass ( create<ISA_LIT>AAWrapperPass ( ) ) ; addPass ( createExternalAAWrapperPass ( [ ] ( Pass & P , Function & , AAResults & AAR ) { if ( auto * WrapperPass = P . getAnalysisIfAvailable < <ISA_LIT>AAWrapperPass > ( ) ) AAR . addAAResult ( WrapperPass -> getResult ( ) ) ; } ) ) ; } } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ;


<s> return ( ( vec_double2 ) ( si_dfms ( ( qword ) ( a ) , ( qword ) ( b ) , ( qword ) ( c ) ) ) ) ;


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getTestBranchTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; ++ MCNumFixups ;


<s> static int h8300_stack_offset_p ( rtx x , int offset ) {

if ( offset == <NUM_LIT> ) return x == stack_pointer_rtx ;


<s> void ELF<ISA_LIT>AsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const {

if ( ! IsLittleEndian && Fixup . getKind ( ) == FK_Data_4 ) {


<s> setCC ( <STR_LIT> , Builder -> CreateICmpEQ ( LHS , RHS ) ) ; setCC ( <STR_LIT> , Builder -> CreateICmpNE ( LHS , RHS ) ) ; return computeEFLAGSForDef ( Builder -> CreateSub ( LHS , RHS ) , OldEFLAGS ) ; } else { setSF ( <STR_LIT> , Builder -> getFalse ( ) ) ; setSF ( <STR_LIT> , Builder -> getFalse ( ) ) ; setSF ( <STR_LIT> , Builder -> getFalse ( ) ) ; setSF ( <STR_LIT> , Builder -> CreateFCmpUEQ ( LHS , RHS ) ) ; setSF ( <STR_LIT> , Builder -> CreateFCmpUNO ( LHS , RHS ) ) ;

setSF ( <STR_LIT> , Builder -> CreateFCmpULT ( LHS , RHS ) ) ;


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; unsigned Align = inferAlignmentFromPtrInfo ( MF , MPO ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , Align ) ;

MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ;


<s> if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == <NUM_LIT> ) return <STR_LIT> ; if ( TYPE_NAME ( type ) != NULL ) { const char * res = <STR_LIT> ( type ) ;


<s> bool getHasStackArgs ( ) const { return HasStackArgs ;


<s> else alignment = type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ;

return MIN ( STACK_BOUNDARY , MAX ( PARM_BOUNDARY , alignment ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ;


<s> case TargetOpcode :: G_ADDRSPACE_CAST : return legalizeAddrSpaceCast ( MI , MRI , B ) ; case TargetOpcode :: G_FRINT : return legalizeFrint ( MI , MRI , B ) ; case TargetOpcode :: G_FCEIL : return legalizeFceil ( MI , MRI , B ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C_TRUNC : return legalizeIntrinsicTrunc ( MI , MRI , B ) ; case TargetOpcode :: G_<ISA_LIT>TOFP : return legalizeITOFP ( MI , MRI , B , true ) ; case TargetOpcode :: G_UITOFP : return legalizeITOFP ( MI , MRI , B , false ) ; case TargetOpcode :: G_FMINNUM : case TargetOpcode :: G_FMAXNUM : case TargetOpcode :: G_FMINNUM_IEEE : case TargetOpcode :: G_FMAXNUM_IEEE : return legalizeMinNumMaxNum ( MI , MRI , B ) ; case TargetOpcode :: G_EXTRACT_VECTOR_ELT :

return legalizeExtractVectorElt ( MI , MRI , B ) ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ; else InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , Start , Len , Imm ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { if ( SM . getSym ( ) ) return <STR_LIT> ( getPointerWidth ( ) , SM . getSym ( ) , Start , End , Size ) ; const MCExpr * ImmExpr = MCConstantExpr :: create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End ) ; } if ( Imm < <NUM_LIT> ) return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ; return ParseIntelMemOperand ( Imm , Start , Size ) ; } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] && getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start , End ) ; unsigned RegNo = <NUM_LIT> ;

if ( ! ParseRegister ( RegNo , Start , End ) ) {


<s> const MCRegister <ISA_LIT>ElfTargetObjectFile :: getStaticBase ( ) const { return <STR_LIT> ;


<s> bool <ISA_LIT>GOT :: hasGOT1 ( ) const { return ( ( ! m_GOT . empty ( ) ) || ( ! m_GOTPLT . empty ( ) ) ) ;


<s> if ( SUBREG_P ( reg ) ) reg = SUBREG_REG ( reg ) ; if ( ! REG_P ( reg ) ) return NO_REG_TYPE ; regno = REGNO ( reg ) ; if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! lra_in_progress && ! reload_completed ) return PSEUDO_REG_TYPE ; regno = true_regnum ( reg ) ; if ( regno < <NUM_LIT> || ! HARD_REGISTER_NUM_P ( regno ) ) return PSEUDO_REG_TYPE ; } gcc_assert ( regno >= <NUM_LIT> ) ; if ( is_altivec && ALTIVEC_REGNO_P ( regno ) ) * is_altivec = true ; rclass = rs6000_regno_regclass [ regno ] ; return reg_class_to_reg_type [ ( int ) rclass ] ;


<s> unsigned IsExtern = <NUM_LIT> ; unsigned Type = <NUM_LIT> ; if ( Target . isAbsolute ( ) ) { Type = macho :: RIT_Vanilla ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( SD ) ) { IsExtern = <NUM_LIT> ; Index = SD -> getIndex ( ) ; if ( ! SD -> Symbol -> isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; FixedValue += Writer -> getSectionAddress ( & SymSD ) ; }

if ( IsPCRel ) FixedValue -= Writer -> getSectionAddress ( Fragment -> getParent ( ) ) ;


<s> const std :: string FuncName = Func -> getName ( ) ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ) ; const char * tmpName = createESName ( PAN :: getTempdataLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , <STR_LIT> ) ; SDValue Store = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , Op , ES , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( GetTmpOffsetForFI ( FI , <NUM_LIT> ) , <STR_LIT> ) ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

SDValue Load = DAG . getNode ( <STR_LIT> , dl , Tys , Store , ES , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( GetTmpOffsetForFI ( FI , <NUM_LIT> ) , <STR_LIT> ) ) ;


<s> const int AmortizationCost = <NUM_LIT> ; static const TypeConversionCostTblEntry < <STR_LIT> > VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { int Idx = ConvertCostTableLookup ( VectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ; if ( Idx != - <NUM_LIT> ) return VectorSelectTbl [ Idx ] . Cost ; } }

return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy ) ;


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? i : ( NumBytes - <NUM_LIT> ) - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> aarch64_add_constant_internal ( Pmode , SP_REGNUM , scratchreg , - delta , frame_related_p , true ) ;


<s> return ( __m128i ) __builtin_ia32_vphaddubq ( ( __v16qi ) __A ) ;


<s> MIRBuilder . buildCopy ( SPReg , <STR_LIT> ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ;

MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , TargetTriple ( TT ) , In16BitMode ( TT . isArch16Bit ( ) || TT . getEnvironment ( ) == Triple :: CODE16 ) , In24BitMode ( ! In16BitMode ) , HasUndocOps ( false ) , HasZ180Ops ( false ) , HasE<ISA_LIT>Ops ( false ) , HasIdxHalfRegs ( false ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this ) {


<s> int Offset = getFrameIndexReferencePreferSP ( MF , Info . PSPSymFrameIdx , SPReg , true ) . getFixed ( ) ; assert ( Offset >= <NUM_LIT> && SPReg == TRI -> getStackRegister ( ) ) ;

return static_cast < unsigned > ( Offset ) ;


<s> SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , ShiftAmount ) ; SDValue Sra = DAG . getNode ( <STR_LIT> , DL , VT , Shl , ShiftAmount ) ; SDValue MergedValues [ <NUM_LIT> ] = { Sra , Chain } ; return DAG . getMergeValues ( MergedValues , <NUM_LIT> , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != <STR_LIT> ) { return SDValue ( ) ; } const MachineFunction & MF = DAG . getMachineFunction ( ) ; const AMDGPUFrameLowering * TFL = static_cast < const AMDGPUFrameLowering * > ( getTargetMachine ( ) . getFrameLowering ( ) ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; Ptr = stackPtrToRegIndex ( Ptr , StackWidth , DAG ) ; if ( VT . isVector ( ) ) { unsigned NumElemVT = VT . getVectorNumElements ( ) ; EVT ElemVT = VT . getVectorElementType ( ) ; SDValue Loads [ <NUM_LIT> ] ; assert ( NumElemVT >= StackWidth && <STR_LIT> <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElemVT ; ++ i ) { unsigned Channel , PtrIncr ; getStackAddress ( StackWidth , i , Channel , PtrIncr ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( PtrIncr , <STR_LIT> ) ) ; Loads [ i ] = DAG . getNode ( <STR_LIT> , DL , ElemVT , Chain , Ptr , DAG . getTargetConstant ( Channel , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } for ( unsigned i = NumElemVT ; i < <NUM_LIT> ; ++ i ) { Loads [ i ] = DAG . getUNDEF ( ElemVT ) ; } EVT TargetVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElemVT , <NUM_LIT> ) ; LoweredLoad = DAG . getNode ( <STR_LIT> , DL , TargetVT , Loads ) ; } else { LoweredLoad = DAG . getNode ( <STR_LIT> , DL , VT , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } SDValue Ops [ <NUM_LIT> ] = { LoweredLoad , Chain } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , DL ) ;


<s> return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ;

MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override {


<s> else MIB . addImm ( Addr . getOffset ( ) ) ; if ( Addr . isRegBase ( ) ) MIB . addReg ( Addr . getReg ( ) ) ; else MIB . addFrameIndex ( Addr . getFI ( ) ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> unsigned Size = RC -> getSize ( ) ; unsigned NeedAlign = RC -> getAlignment ( ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned LoadOpc ; if ( NeedAlign <= HasAlign ) LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstLo ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; if ( NeedAlign <= MinAlign ( HasAlign , Size ) ) LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstHi ) . addFrameIndex ( FI ) . addImm ( Size ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; B . erase ( It ) ;


<s> bool hasStdExtM ( ) const { return HasStdExtM ;


<s> if ( Offset . isExpr ( ) ) { Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( Offset . getExpr ( ) ) ) ; } else { assert ( Offset . isImm ( ) && <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ) { if ( inMicro<ISA_LIT>Mode ( ) ) Inst . setOpcode ( has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ) ; } else {

if ( ! isInt < <NUM_LIT> > ( Offset . getImm ( ) ) ) return Error ( IDLoc , <STR_LIT> ) ;


<s> const MCSymbol * Symbol = <NUM_LIT> ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = AP . getSymbol ( MO . getGlobal ( ) ) ; break ;

case MachineOperand :: MO_BlockAddress :


<s> SelectPatternFlavor MinSPF = matchSelectPattern ( MinInst , MinLHS , MinRHS ) . Flavor ; if ( MinSPF == SPF_SMIN && PatternMatch :: match ( MinRHS , PatternMatch :: m_ConstantInt ( MinC ) ) && MinC -> getValue ( ) == ( ( - Imm ) - <NUM_LIT> ) ) return true ; } return false ; } ; if ( isSSatMin ( Inst -> getOperand ( <NUM_LIT> ) ) ) return cast < Instruction > ( Inst -> getOperand ( <NUM_LIT> ) ) -> getOperand ( <NUM_LIT> ) ; if ( Inst -> hasNUses ( <NUM_LIT> ) && ( isSSatMin ( * Inst -> user_begin ( ) ) || isSSatMin ( * ( ++ Inst -> user_begin ( ) ) ) ) ) return Inst -> getOperand ( <NUM_LIT> ) ;


<s> fprintf ( dump_file , <STR_LIT> <STR_LIT> <STR_LIT> , INSN_UID ( insn ) , reg_names [ cur_dest_reg ] ) ; } CLEAR_HARD_REG_SET ( unavailable ) ; if ( frame_pointer_needed ) { add_to_hard_reg_set ( & unavailable , Pmode , FRAME_POINTER_REGNUM ) ; add_to_hard_reg_set ( & unavailable , Pmode , HARD_FRAME_POINTER_REGNUM ) ; } mode = GET_MODE ( SET_DEST ( PATTERN ( insn ) ) ) ;

for ( reg = cur_parity ; reg < FIRST_PSEUDO_REGISTER ; reg += <NUM_LIT> ) add_to_hard_reg_set ( & unavailable , mode , reg ) ;


<s> <ISA_LIT>PromoteAllocaImpl ( TargetMachine & TM ) : TM ( TM ) {


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : CalleeSavedFrameSize ( <NUM_LIT> ) , ReturnAddrIndex ( <NUM_LIT> ) {


<s> static bool xtensa_function_value_regno_p ( const unsigned int regno ) {

return IN_RANGE ( regno , GP_RETURN_FIRST , GP_RETURN_LAST ) ;


<s> return create<ISA_LIT>ELFObjectWriter ( OS , false , true , OSABI ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: x86 , true > X ( The<ISA_LIT>_32Target , <STR_LIT> , <STR_LIT> ) ;

RegisterTarget < Triple :: x86_64 , true > Y ( The<ISA_LIT>_64Target , <STR_LIT> , <STR_LIT> ) ;


<s> const Function * F = CI -> getParent ( ) -> getParent ( ) ; Attribute Attr = F -> getFnAttribute ( <STR_LIT> ) ;

return Attr . getValueAsString ( ) == <STR_LIT> ;


<s> static unsigned getPrologueDeath ( MachineFunction & MF , unsigned Reg ) { bool IsLiveIn = MF . getRegInfo ( ) . isLiveIn ( Reg ) ; return getKillRegState ( ! IsLiveIn ) ;


<s> for ( ; BlockI != End ; ++ BlockI ) { MachineInstr & MI = * BlockI ; if ( promoteConstantOffsetToImm ( MI , Visited , AnchorList ) ) Modified = true ; if ( MI . hasOrderedMemoryRef ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; ++ BlockI ; break ; } const InstClassEnum InstClass = getInstClass ( MI . getOpcode ( ) , * TII ) ; if ( InstClass == UNKNOWN ) continue ; CombineInfo CI ; CI . setMI ( MI , * TII , * STM ) ; CI . Order = Order ++ ; if ( ! CI . hasMergeableAddress ( * MRI ) ) continue ;


<s> if ( ! MI -> getDesc ( ) . isPredicable ( ) ) { return false ; } if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { return false ;


<s> if ( Node -> getOpcode ( ) == <STR_LIT> ) { if ( Node -> getOperand ( <NUM_LIT> ) != Node -> getOperand ( <NUM_LIT> ) ) return false ; SDNodeFlags Flags = Node -> getFlags ( ) ; if ( ScalarBits == <NUM_LIT> && ! Flags . hasNoInfs ( ) && IsUnsigned ) return false ; unsigned Opcode ; switch ( ScalarBits ) { case <NUM_LIT> : Opcode = IsUnsigned ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : Opcode = IsUnsigned ? <STR_LIT> : <STR_LIT> ; break ; }

SmallVector < SDValue , <NUM_LIT> > Ops { Node -> getOperand ( <NUM_LIT> ) , CurDAG -> getConstant ( <NUM_LIT> , dl , <STR_LIT> ) } ;


<s> void <ISA_LIT>InstPrinter :: printFI ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { using namespace llvm :: <STR_LIT> ;

unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ;


<s> unsigned Opc = MI . getOpcode ( ) ; unsigned DescNumOps = MCII -> get ( Opc ) . getNumOperands ( ) ; if ( MI . getNumOperands ( ) < DescNumOps && <STR_LIT> ( Opc , <STR_LIT> :: src0_modifiers ) != - <NUM_LIT> ) insertNamedMCOperand ( MI , MCOperand :: createImm ( <NUM_LIT> ) , <STR_LIT> :: src0_modifiers ) ; if ( MI . getNumOperands ( ) < DescNumOps && <STR_LIT> ( Opc , <STR_LIT> :: src1_modifiers ) != - <NUM_LIT> ) insertNamedMCOperand ( MI , MCOperand :: createImm ( <NUM_LIT> ) , <STR_LIT> :: src1_modifiers ) ; return isValidDPP8 ( MI ) ? MCDisassembler :: Success : MCDisassembler :: SoftFail ;


<s> const <STR_LIT> InvCC = changeICMPPredTo<ISA_LIT>CC ( CmpInst :: getInversePredicate ( ( CmpInst :: Predicate ) Pred ) ) ; auto I = MIRBuilder . buildInstr ( <STR_LIT> , { DefReg } , { Register ( <STR_LIT> ) , Register ( <STR_LIT> ) } ) . addImm ( InvCC ) ;

constrainSelectedInstRegOperands ( * I , TII , TRI , RBI ) ;


<s> unsigned CPELogAlign = getCPELogAlign ( * U . CPEMI ) ; unsigned CPEOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( CPELogAlign ) ; unsigned NextBlockOffset , NextBlockLogAlignment ; MachineFunction :: const_iterator NextBlock = ++ Water -> getIterator ( ) ; if ( NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockLogAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ] . Offset ; NextBlockLogAlignment = NextBlock -> getLogAlignment ( ) ; } unsigned Size = U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> O << <STR_LIT> << Lmul ; } else { Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } bool TailAgnostic = Imm & <NUM_LIT> ; bool MaskedoffAgnostic = Imm & <NUM_LIT> ; if ( TailAgnostic ) O << <STR_LIT> ; else O << <STR_LIT> ;

if ( MaskedoffAgnostic ) O << <STR_LIT> ;


<s> if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Store = tryCreateMaskedScatterOffset ( I , Ptr , Builder ) ;

if ( ! Store ) Store = tryCreateMaskedScatterBase ( I , Ptr , Builder ) ;


<s> break ; case <STR_LIT> : if ( Const ) { assert ( ConstVal != - <NUM_LIT> && <STR_LIT> ) ; ++ ConstVal ; TCC = <STR_LIT> ; break ; } Const = nullptr ; std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : Const = nullptr ; std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : LHS = EmitFlipSign ( DL , LHS , DAG ) ; if ( Const ) ConstVal ^= SignVal ; else RHS = EmitFlipSign ( DL , RHS , DAG ) ; TCC = <STR_LIT> ; break ; case <STR_LIT> : Const = nullptr ; std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : LHS = EmitFlipSign ( DL , LHS , DAG ) ; if ( Const ) ConstVal ^= SignVal ; else RHS = EmitFlipSign ( DL , RHS , DAG ) ; TCC = <STR_LIT> ; break ; } switch ( TCC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : if ( VT != <STR_LIT> && Const ) {


<s> if ( ! MOp . isGlobal ( ) ) return false ;

auto * CalleeFn = dyn_cast < Function > ( MOp . getGlobal ( ) ) ;


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ;


<s> <STR_LIT> ( const Function & F , const GCNSubtarget & ST ) { * this = getDefaultForCallingConv ( F . getCallingConv ( ) ) ;

StringRef IEEEAttr = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ;


<s> for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg , i } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; <ISA_LIT>IncomingValueAssigner Assigner ( AssignFn , AssignFn ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; uint64_t StackOffset = Assigner . StackOffset ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Assigner . StackOffset , Subtarget . isTargetILP32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , <NUM_LIT> ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ;

handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ;


<s> ResolveInfo * rsym = pReloc . symInfo ( ) ; int64_t result ; Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; FragmentRef & target_fragref = pReloc . targetRef ( ) ; Fragment * target_frag = target_fragref . frag ( ) ; LDSection & target_sect = target_frag -> getParent ( ) -> getSection ( ) ; result = ( int64_t ) ( S + A - P ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) == <NUM_LIT> ) { return applyRel ( pReloc , result ) ; } if ( ! rsym -> isLocal ( ) ) {

if ( rsym -> reserved ( ) & <ISA_LIT>Relocator :: ReservePLT ) {


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>Disassembler ) ;


<s> void <ISA_LIT>TargetELFStreamer :: EmitAMDKernelCodeT ( const amd_kernel_code_t & Header ) { MCStreamer & OS = getStreamer ( ) ;


errs ( ) . write_hex ( Word ) << <STR_LIT> ) ;


<s> Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align = <NUM_LIT> ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; Info . vol = ! Vol || ! Vol -> isNullValue ( ) ; Info . readMem = true ; Info . writeMem = true ; return true ; } default :


<s> void consumeArguments ( size_t NumSlots ) { assert ( NumSlots <= Data . size ( ) ) ; Data . erase ( std :: begin ( Data ) , std :: begin ( Data ) + NumSlots ) ;


<s> if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy , MaybeAlign ( Alignment ) ) ) ) Scalarize = true ; if ( ST -> hasAVX512 ( ) && ( VF == <NUM_LIT> || ( VF == <NUM_LIT> && ! ST -> hasVLX ( ) ) ) ) Scalarize = true ;

if ( Scalarize ) return getGSScalarCost ( Opcode , SrcVTy , VariableMask , Alignment , AddressSpace ) ;


<s> if ( SrcTy == DestTy ) return Val ; if ( HST . isTypeForHVX ( SrcTy , true ) ) { if ( cast < VectorType > ( SrcTy ) -> getElementType ( ) == BoolTy ) { <STR_LIT> TC = HwLen == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Function * FI = <STR_LIT> ( F . getParent ( ) , TC , { DestTy , Val -> getType ( ) } ) ; return Builder . CreateCall ( FI , { Val } ) ; } return Builder . CreateBitCast ( Val , DestTy ) ; } llvm_unreachable ( <STR_LIT> ) ; } ; SmallVector < Value * , <NUM_LIT> > IntOps ; for ( Value * A : Args ) IntOps . push_back ( getCast ( Builder , A , getTypeForIntrin ( A -> getType ( ) ) ) ) ; Function * FI = <STR_LIT> ( F . getParent ( ) , IntID ) ; Value * Call = Builder . CreateCall ( FI , IntOps ) ; Type * CallTy = Call -> getType ( ) ; if ( CallTy == RetTy ) return Call ; assert ( HST . isTypeForHVX ( CallTy , true ) ) ; if ( cast < VectorType > ( CallTy ) -> getElementType ( ) == BoolTy ) return getCast ( Builder , Call , RetTy ) ;

return Builder . CreateBitCast ( Call , RetTy ) ;


<s> if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DAG ) ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] , <STR_LIT> ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) ) ;

if ( Subtarget -> hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) ) , V1 ) ;


<s> bool SelectAddrModeIndexedU6S128 ( SDValue N , SDValue & Base , SDValue & OffImm ) {

return SelectAddrModeIndexedBitWidth ( N , false , <NUM_LIT> , <NUM_LIT> , Base , OffImm ) ;


<s> case SPRRegisterList : Registers = o . Registers ; break ; case CoprocNum : case CoprocReg : Cop = o . Cop ; break ; case Immediate : Imm = o . Imm ; break ; case MemBarrierOpt : MBOpt = o . MBOpt ; break ; case Memory :


<s> bool <ISA_LIT>FastISel :: selectBranch ( const Instruction * I ) { const BranchInst * BI = cast < BranchInst > ( I ) ; if ( BI -> isUnconditional ( ) ) { MachineBasicBlock * MSucc = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; fastEmitBranch ( MSucc , BI -> getDebugLoc ( ) ) ; return true ; } MachineBasicBlock * TBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { if ( CI -> hasOneUse ( ) && isValueAvailable ( CI ) ) { CmpInst :: Predicate Predicate = optimizeCmpPredicate ( CI ) ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_FALSE : fastEmitBranch ( FBB , DbgLoc ) ; return true ; case CmpInst :: FCMP_TRUE : fastEmitBranch ( TBB , DbgLoc ) ; return true ; } if ( emitCompareAndBranch ( BI ) ) return true ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; Predicate = CmpInst :: getInversePredicate ( Predicate ) ; } if ( ! emitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) ) ) return false ; <STR_LIT> CC = getCompareCC ( Predicate ) ; <STR_LIT> ExtraCC = <STR_LIT> ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_UEQ : ExtraCC = <STR_LIT> ; CC = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : ExtraCC = <STR_LIT> ; CC = <STR_LIT> ; break ; } assert ( ( CC != <STR_LIT> ) && <STR_LIT> ) ; if ( ExtraCC != <STR_LIT> ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( ExtraCC ) . addMBB ( TBB ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( CC ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; if ( ! CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ) { return false ; } if ( CCInfo . getNextStackOffset ( ) != <NUM_LIT> && isVarArg ) { return false ;


<s> CPU = select<ISA_LIT>CPU ( TT , CPU ) ; MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ;


<s> void <ISA_LIT>HazardRecognizer :: EmitInstruction ( SUnit * SU ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( isPseudo ( SU ) ) return ; if ( emitMove ( SU ) ) return ; Hzd -> book ( getUnitIndex ( SU ) , getExtraUse ( SU ) ) ;


<s> if ( auto * Element = dyn_cast_or_null < DINode > ( Elements [ I ] ) ) if ( Element -> getTag ( ) == dwarf :: DW_TAG_subrange_type ) { const DISubrange * SR = cast < DISubrange > ( Element ) ; auto * CI = SR -> getCount ( ) . dyn_cast < ConstantInt * > ( ) ; int64_t Count = CI -> getSExtValue ( ) ; auto TypeEntry = llvm :: make_unique < BTFTypeArray > ( ElemTypeId , Count ) ; if ( I == <NUM_LIT> ) ElemTypeId = addType ( std :: move ( TypeEntry ) , CTy ) ; else ElemTypeId = addType ( std :: move ( TypeEntry ) ) ;


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) , M ( const_cast < Module & > ( * funcInfo . Fn -> getParent ( ) ) ) , TM ( funcInfo . MF -> getTarget ( ) ) , TII ( * TM . getInstrInfo ( ) ) , TLI ( * TM . getTargetLowering ( ) ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; isThumb2 = AFI -> isThumbFunction ( ) ;

Context = & funcInfo . Fn -> getContext ( ) ;


<s> unsigned getMaxFlatWorkGroupSize ( ) const {

return <STR_LIT> :: getMaxFlatWorkGroupSize ( SubtargetFeatureBits ) ;


<s> return ( uint8x8_t ) ( __a == <NUM_LIT> ) ;


<s> if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Enable<ISA_LIT>LongCalls ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) { if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ; else CalleeReg = getRegForValue ( Callee ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( UseReg ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; unsigned char OpFlags = <NUM_LIT> ;

if ( Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) OpFlags = <STR_LIT> ;


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) return N -> getOperand ( <NUM_LIT> ) ; SDValue Op = peekThroughBitcasts ( SDValue ( N , <NUM_LIT> ) ) ; if ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Op1 = peekThroughBitcasts ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Op1 . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; SDValue Op0 = peekThroughBitcasts ( Op . getOperand ( <NUM_LIT> ) ) ; unsigned EltBits = Op1 . getScalarValueSizeInBits ( ) ;

auto isSignBitValue = [ & ] ( const ConstantFP * C ) {


<s> } OptionalIdx [ Op . getImmTy ( ) ] = i ; } addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOffset ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyGDS ) ; if ( ! GDSOnly ) { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyGDS ) ;


<s> assert ( And . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue Op0 = And . getOperand ( <NUM_LIT> ) ; SDValue Op1 = And . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( isOneConstant ( Op0 . getOperand ( <NUM_LIT> ) ) ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { KnownBits Known = DAG . computeKnownBits ( Op0 ) ; if ( Known . countMinLeadingZeros ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } else { bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) || ( OptForSize && ! isUInt < <NUM_LIT> > ( AndRHSVal ) ) ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS ;

RHS = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , dl , LHS . getValueType ( ) ) ;


<s> SectMap :: const_iterator it = m_SectToExData . find ( & pSect ) ; if ( it == m_SectToExData . end ( ) ) {


<s> for ( GlobalVariable & GV : M . globals ( ) ) { if ( GV . hasLocalLinkage ( ) ) { GV . setName ( cleanUpName ( GV . getName ( ) ) ) ; } } for ( Function & F : M . functions ( ) ) if ( F . hasLocalLinkage ( ) ) F . setName ( cleanUpName ( F . getName ( ) ) ) ;


<s> DenseSet < unsigned > NopInserted ; for ( auto & MBB : MF ) { for ( auto MI = MBB . begin ( ) ; MI != MBB . end ( ) ; ++ MI ) { if ( MI -> isDebugValue ( ) || ! MI -> getDebugLoc ( ) ) continue ; auto DL = MI -> getDebugLoc ( ) ; if ( NopInserted . find ( DL . getLine ( ) ) == NopInserted . end ( ) ) {

BuildMI ( MBB , * MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> MachineLocation <ISA_LIT>AsmPrinter :: getDebugValueLocation ( const MachineInstr * MI ) const { assert ( MI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; return MachineLocation ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const MCInstrDesc & Mfc1Tdd = TII -> get ( <STR_LIT> ) ;


<s> auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; MCInst Noop ; Subtarget -> getInstrInfo ( ) -> getNoopForElfTarget ( Noop ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) { OutStreamer -> EmitInstruction ( Noop , getSubtargetInfo ( ) ) ; } OutStreamer -> EmitLabel ( Target ) ;


<s> explicit <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {


<s> const unsigned IndexMap [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> } ; unsigned SubNdx = IndexMap [ IndexVal -> getZExtValue ( ) ] ; SDValue NIndex = DAG . getTargetConstant ( SubNdx , DL , <STR_LIT> ) ; SDNode * N = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , DL , VT , Vector , Item , NIndex ) ; return SDValue ( N , <NUM_LIT> ) ;


<s> return encodeImmN ( MI , Op , Fixups , STI , MCFixupKind ( <STR_LIT> ) ) ;


<s> static SDValue LowerVACOPY ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; DebugLoc DL = Op . getDebugLoc ( ) ; return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( Subtarget -> has64BitPointers ( ) ? <NUM_LIT> : <NUM_LIT> ) , Subtarget -> has64BitPointers ( ) ? <NUM_LIT> : <NUM_LIT> , false , false , MachinePointerInfo ( DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ;

if ( SrcIsKill ) ( * MIB ) . addRegisterKilled ( SrcReg , TRI , true ) ;


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ;

const <ISA_LIT>InstrInfo * InstrInfo = static_cast < const <ISA_LIT>InstrInfo * > ( & MCII ) ;


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StringRef LayoutSpec ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseImm ( OperandVector & Operands , bool HasSP3AbsModifier ) { assert ( ! isRegister ( ) ) ; assert ( ! isModifier ( ) ) ; const auto & Tok = getToken ( ) ; const auto & NextTok = peekToken ( ) ; bool IsReal = Tok . is ( AsmToken :: Real ) ; SMLoc S = getLoc ( ) ; bool Negate = false ; if ( ! IsReal && Tok . is ( AsmToken :: Minus ) && NextTok . is ( AsmToken :: Real ) ) { lex ( ) ; IsReal = true ; Negate = true ; } if ( IsReal ) { StringRef Num = getTokenStr ( ) ; lex ( ) ; APFloat RealVal ( APFloat :: IEEEdouble ( ) ) ; auto roundMode = APFloat :: rmNearestTiesToEven ; if ( RealVal . convertFromString ( Num , roundMode ) == APFloat :: opInvalidOp ) { return MatchOperand_ParseFail ; } if ( Negate ) RealVal . changeSign ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , RealVal . bitcastToAPInt ( ) . getZExtValue ( ) , S , <ISA_LIT>Operand :: ImmTyNone , true ) ) ; return MatchOperand_Success ; } else { int64_t IntVal ; const MCExpr * Expr ; SMLoc S = getLoc ( ) ; if ( HasSP3AbsModifier ) { SMLoc EndLoc ; if ( getParser ( ) . parsePrimaryExpr ( Expr , EndLoc ) ) return MatchOperand_ParseFail ; } else { if ( Parser . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; } if ( Expr -> evaluateAsAbsolute ( IntVal ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , IntVal , S ) ) ; } else { Operands . push_back ( <ISA_LIT>Operand :: CreateExpr ( this , Expr , S ) ) ; } return MatchOperand_Success ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) {


<s> void <ISA_LIT>65816Subtarget :: anchor ( ) {


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( TM . getRelocationModel ( ) == Reloc :: Static ) { if ( ! ST -> usingLargeMem ( ) ) { return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; } else { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , PtrVT , GA , Zero ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Hi , Lo ) ; } } else {


<s> inline SDValue getImm ( const SDNode * Node , uint64_t Imm ) { return CurDAG -> getTargetConstant ( Imm , Node -> getValueType ( <NUM_LIT> ) ) ;


<s> MF . getFrameInfo ( ) -> setFrameAddressIsTaken ( true ) ; SDLoc DL ( Op ) ;

SDValue Offset = DAG . getNode ( <STR_LIT> , DL , TLI . getPointerTy ( ) , DAG . getRegister ( <STR_LIT> , TLI . getPointerTy ( ) ) , DAG . getIntPtrConstant ( FuncInfo -> getVarArgsFrameOffset ( ) ) ) ;


<s> size_t SizeInWords = ( Size + <NUM_LIT> ) / <NUM_LIT> ; assert ( SizeInWords <= <NUM_LIT> && <STR_LIT> ) ;

EmitByte ( static_cast < uint8_t > ( SizeInWords - <NUM_LIT> ) ) ;


<s> virtual unsigned getTTypeEncoding ( ) const {