__asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( s ) ) ;


<s> bool <ISA_LIT>16TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , bool * Fast ) const {


<s> MachineBasicBlock * MBB = Worklist . pop_back_val ( ) ; if ( MBB == End || ! Visited . insert ( MBB ) . second ) continue ; for ( auto & Term : MBB -> terminators ( ) ) if ( TII -> isKillTerminator ( Term . getOpcode ( ) ) ) return true ; Worklist . append ( MBB -> succ_begin ( ) , MBB -> succ_end ( ) ) ;


<s> Error ( Loc , Twine ( DepCtrName , <STR_LIT> ) ) ; return ; case OPR_ID_DUPLICATE : Error ( Loc , Twine ( <STR_LIT> , DepCtrName ) ) ; return ;


<s> O << <STR_LIT> ; if ( isABI ) { if ( Ty -> isFloatingPointTy ( ) || Ty -> isIntegerTy ( ) ) { unsigned size = <NUM_LIT> ; if ( const IntegerType * ITy = dyn_cast < IntegerType > ( Ty ) ) { size = ITy -> getBitWidth ( ) ; if ( size < <NUM_LIT> ) size = <NUM_LIT> ; } else { assert ( Ty -> isFloatingPointTy ( ) && <STR_LIT> ) ; size = Ty -> getPrimitiveSizeInBits ( ) ; } O << <STR_LIT> << size << <STR_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { O << <STR_LIT> << TLI -> getPointerTy ( ) . getSizeInBits ( ) << <STR_LIT> ; } else if ( ( Ty -> getTypeID ( ) == Type :: StructTyID ) || isa < VectorType > ( Ty ) ) { unsigned totalsz = TD -> getTypeAllocSize ( Ty ) ; unsigned retAlignment = <NUM_LIT> ; if ( ! llvm :: getAlign ( * F , <NUM_LIT> , retAlignment ) ) retAlignment = TD -> getABITypeAlignment ( Ty ) ; O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) {


<s> case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : fail ( DL , DAG , <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> :


<s> bool IsOpSigned ; } ResultTable [ NumOps ] ; } OpTable [ NumTypes ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> , { { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , S } , { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , S } , { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , U } , { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , U } , } } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , { { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , { { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , { <NUM_LIT> , <STR_LIT> , <STR_LIT> , { { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , } ; auto OpEntryIt = llvm :: find_if ( OpTable , [ RegTy ] ( const DivRemEntry & El ) { return El . SizeInBits == RegTy . getSizeInBits ( ) ; } ) ; if ( OpEntryIt == std :: end ( OpTable ) ) return false ; unsigned OpIndex ; switch ( I . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case TargetOpcode :: G_SDIV : OpIndex = <NUM_LIT> ; break ; case TargetOpcode :: G_SREM : OpIndex = <NUM_LIT> ; break ; case TargetOpcode :: G_UDIV : OpIndex = <NUM_LIT> ; break ; case TargetOpcode :: G_UREM : OpIndex = <NUM_LIT> ; break ; } const DivRemEntry & TypeEntry = * OpEntryIt ; const DivRemEntry :: DivRemResult & OpEntry = TypeEntry . ResultTable [ OpIndex ] ; const TargetRegisterClass * RegRC = getRegClass ( RegTy , * RegRB ) ; if ( ! RBI . constrainGenericRegister ( Op1Reg , * RegRC , MRI ) || ! RBI . constrainGenericRegister ( Op2Reg , * RegRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * RegRC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ;


<s> APInt One ( SVTBits , <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Op = Amt -> getOperand ( i ) ; if ( Op -> isUndef ( ) ) { Elts . push_back ( Op ) ; continue ; } ConstantSDNode * ND = cast < ConstantSDNode > ( Op ) ; APInt C ( SVTBits , ND -> getZExtValue ( ) ) ; uint64_t ShAmt = C . getZExtValue ( ) ; if ( ShAmt >= SVTBits ) { Elts . push_back ( DAG . getUNDEF ( SVT ) ) ; continue ; } Elts . push_back ( DAG . getConstant ( One . shl ( ShAmt ) , dl , SVT ) ) ; } return DAG . getBuildVector ( VT , dl , Elts ) ; } if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getBitcast ( <STR_LIT> , Amt ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Amt ) ; } if ( VT == <STR_LIT> && ! Subtarget . hasAVX2 ( ) ) { SDValue Z = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue Lo = DAG . getBitcast ( <STR_LIT> , getUnpackl ( DAG , dl , VT , Amt , Z ) ) ; SDValue Hi = DAG . getBitcast ( <STR_LIT> , getUnpackh ( DAG , dl , VT , Amt , Z ) ) ; Lo = convertShiftLeftToScale ( Lo , dl , Subtarget , DAG ) ; Hi = convertShiftLeftToScale ( Hi , dl , Subtarget , DAG ) ; if ( Subtarget . hasSSE41 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Lo , Hi ) ; return DAG . getVectorShuffle ( VT , dl , DAG . getBitcast ( VT , Lo ) , DAG . getBitcast ( VT , Hi ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; }


<s> <ISA_LIT>CCState ( const llvm :: Function & F , CallingConv :: ID CC , bool IsVarArg , MachineFunction & MF , SmallVectorImpl < CCValAssign > & Locs , LLVMContext & C ) : CCState ( CC , IsVarArg , MF , Locs , C ) , F ( F ) {


<s> SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; }


<s> static rtx nios2_expand_custom_builtin ( tree exp , unsigned int index , rtx target ) { bool has_target_p = ( TREE_TYPE ( exp ) != void_type_node ) ; machine_mode tmode = VOIDmode ; int nargs , argno ; rtx value , insn , unspec_args [ <NUM_LIT> ] ; tree arg ; if ( has_target_p ) { tmode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; if ( ! target || GET_MODE ( target ) != tmode || ! REG_P ( target ) ) target = gen_reg_rtx ( tmode ) ; } nargs = call_expr_nargs ( exp ) ;

for ( argno = <NUM_LIT> ; argno < nargs ; argno ++ ) {


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) { return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , Addr , <STR_LIT> ) ; } else { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , Addr , <STR_LIT> ) ; }


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; if ( IdxVal == <NUM_LIT> && Vec . isUndef ( ) ) return Op ; MVT OpVT = Op . getSimpleValueType ( ) ; MVT SubVecVT = SubVec . getSimpleValueType ( ) ; unsigned NumElems = OpVT . getVectorNumElements ( ) ; unsigned SubVecNumElems = SubVecVT . getVectorNumElements ( ) ; assert ( IdxVal + SubVecNumElems <= NumElems && IdxVal % SubVecVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MVT MinVT = Subtarget . hasDQI ( ) ? <STR_LIT> : <STR_LIT> ; MVT WideOpVT = OpVT ; if ( OpVT . getSizeInBits ( ) < MinVT . getStoreSizeInBits ( ) ) WideOpVT = MinVT ; SDValue ZeroIdx = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Undef = DAG . getUNDEF ( WideOpVT ) ; SDValue WideSubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , SubVec , ZeroIdx ) ; auto ExtractSubVec = [ & ] ( SDValue V ) { return ( WideOpVT == OpVT ) ? V : DAG . getNode ( <STR_LIT> , dl , OpVT , V , ZeroIdx ) ; } ; if ( Vec . isUndef ( ) ) { if ( IdxVal != <NUM_LIT> ) { SDValue ShiftBits = DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ; WideSubVec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , WideSubVec , ShiftBits ) ; } return ExtractSubVec ( WideSubVec ) ; } if ( <STR_LIT> ( Vec . getNode ( ) ) ) { NumElems = WideOpVT . getVectorNumElements ( ) ; unsigned ShiftLeft = NumElems - SubVecNumElems ; unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal ; Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , WideSubVec , DAG . getConstant ( ShiftLeft , dl , <STR_LIT> ) ) ; Vec = ShiftRight ? DAG . getNode ( <STR_LIT> , dl , WideOpVT , Vec , DAG . getConstant ( ShiftRight , dl , <STR_LIT> ) ) : Vec ; return ExtractSubVec ( Vec ) ; } if ( IdxVal == <NUM_LIT> ) { SDValue ShiftBits = DAG . getConstant ( SubVecNumElems , dl , <STR_LIT> ) ;

Vec = DAG . getNode ( <STR_LIT> , dl , WideOpVT , Undef , Vec , ZeroIdx ) ;


<s> bool <ISA_LIT>16RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ;


<s> void <ISA_LIT>PassConfig :: addPreLegalizeMachineIR ( ) { addPass ( create<ISA_LIT>Combiner ( ) ) ;


<s> const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) -> getObjectSize ( FrameIdx ) >= RC -> getSize ( ) && <STR_LIT> ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ;

addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ;

case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ;


<s> MVT <ISA_LIT>AsmPrinter :: getRegType ( unsigned RegNo ) const { const TargetRegisterClass * TRC = TargetRegisterInfo :: isVirtualRegister ( RegNo ) ? MRI -> getRegClass ( RegNo ) : MRI -> getTargetRegisterInfo ( ) -> getMinimalPhysRegClass ( RegNo ) ;

for ( MVT T : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( TRC -> hasType ( T ) ) return T ;


<s> return isUImm < <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> if ( ! IsPreserveDIAccessIndexCall ( Call , CInfo ) || AIChain . find ( Call ) != AIChain . end ( ) ) continue ;


<s> if ( Info -> getScratchRSrcReg ( ) != <STR_LIT> ) MRI . replaceRegWith ( <STR_LIT> , Info -> getScratchRSrcReg ( ) ) ; if ( Info -> getFrameOffsetReg ( ) != <STR_LIT> ) MRI . replaceRegWith ( <STR_LIT> , Info -> getFrameOffsetReg ( ) ) ; Info -> limitOccupancy ( MF ) ; if ( ST . isWave32 ( ) && ! MF . empty ( ) ) { const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; DebugLoc DL ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . getFirstNonDebugInstr ( ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , <STR_LIT> ) ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { TII -> fixImplicitOperands ( MI ) ; } } } TargetLoweringBase :: finalizeLowering ( MF ) ;

if ( VGPRReserveforSGPRSpill && ! Info -> VGPRReservedForSGPRSpill && ! Info -> isEntryFunction ( ) && MF . getFrameInfo ( ) . hasStackObjects ( ) ) Info -> reserveVGPRforSGPRSpills ( MF ) ;


<s> THMToTHMStub :: ~ THMToTHMStub ( ) {


<s> BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } ZERO = <STR_LIT> ; MOVE = <STR_LIT> ; } else { LL = STI -> has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = STI -> has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; MOVE = <STR_LIT> ; } unsigned Dest = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scratch = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const BasicBlock * LLVM_BB = BB . getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB . getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , & BB , std :: next ( MachineBasicBlock :: iterator ( I ) ) , BB . end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( & BB ) ; BB . addSuccessor ( loop1MBB , BranchProbability :: getOne ( ) ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop1MBB -> normalizeSuccProbs ( ) ; loop2MBB -> addSuccessor ( loop1MBB ) ;


<s> Scale = getI8Imm ( AM . Scale ) ; Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else Disp = CurDAG -> getTargetConstant ( AM . Disp , <STR_LIT> ) ; if ( AM . Segment . getNode ( ) ) Segment = AM . Segment ;

else Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;


<s> return false ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { R1 = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; R2 = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; } else { R1 = Addr ; R2 = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; } } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; } else { R1 = Addr ; R2 = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ;


<s> fputs ( <STR_LIT> , stream ) ; assemble_name ( stream , funname ) ; fputs ( <STR_LIT> , stream ) ; ASM_OUTPUT_LABEL ( stream , funname ) ; fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , funname ) ; fprintf ( stream , <STR_LIT> , alpha_procedure_type == PT_STACK ? <STR_LIT> : alpha_procedure_type == PT_REGISTER ? <STR_LIT> : <STR_LIT> ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_SwiftError_RegMask ; return CSR_<ISA_LIT>_RegMask ;


<s> Increment = & Use ; continue ; } int BaseOp = getBaseOperandIndex ( Use ) ; if ( BaseOp == - <NUM_LIT> ) return false ; if ( ! Use . getOperand ( BaseOp ) . isReg ( ) || Use . getOperand ( BaseOp ) . getReg ( ) != Base ) return false ; if ( isPreIndex ( Use ) || isPostIndex ( Use ) ) PrePostInc = & Use ; else if ( Use . getOperand ( BaseOp + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) BaseAccess = & Use ; else OtherAccesses . insert ( & Use ) ; } int IncrementOffset ; Register NewBaseReg ; if ( BaseAccess && Increment ) { if ( PrePostInc || BaseAccess -> getParent ( ) != Increment -> getParent ( ) ) return false ; Register PredReg ; if ( Increment -> definesRegister ( <STR_LIT> ) || getInstrPredicate ( * Increment , PredReg ) != <STR_LIT> ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Base . virtRegIndex ( ) << <STR_LIT> ) ; for ( MachineInstr & Use : MRI -> use_nodbg_instructions ( Increment -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { if ( ! DT -> dominates ( BaseAccess , & Use ) || & Use == BaseAccess ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } IncrementOffset = getAddSubImmediate ( * Increment ) ; unsigned NewPostIncOpcode = getPostIndexedLoadStoreOpcode ( BaseAccess -> getOpcode ( ) , IncrementOffset > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( ! isLegalAddressImm ( NewPostIncOpcode , IncrementOffset , TII ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else if ( PrePostInc ) { if ( Increment ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Base . virtRegIndex ( ) << <STR_LIT> ) ; int BaseOp = getBaseOperandIndex ( * PrePostInc ) ; IncrementOffset = PrePostInc -> getOperand ( BaseOp + <NUM_LIT> ) . getImm ( ) ; BaseAccess = PrePostInc ; NewBaseReg = PrePostInc -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else return false ; SmallPtrSet < MachineInstr * , <NUM_LIT> > SuccessorAccesses ; int CodesizeEstimate = - <NUM_LIT> ; for ( auto * Use : OtherAccesses ) { if ( DT -> dominates ( BaseAccess , Use ) ) { SuccessorAccesses . insert ( Use ) ; unsigned BaseOp = getBaseOperandIndex ( * Use ) ; if ( ! isLegalOrConvertableAddressImm ( Use -> getOpcode ( ) , Use -> getOperand ( BaseOp + <NUM_LIT> ) . getImm ( ) - IncrementOffset , TII , CodesizeEstimate ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else if ( ! DT -> dominates ( Use , BaseAccess ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }


<s> case <STR_LIT> :: <ISA_LIT>V8_5A : case <STR_LIT> :: <ISA_LIT>V8_6A : S . setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; S . setAttributeItem ( MPextension_use , Allowed , false ) ; S . setAttributeItem ( Virtualization_use , AllowTZVirtualization , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V8MBaseline : case <STR_LIT> :: <ISA_LIT>V8MMainline : S . setAttributeItem ( THUMB_ISA_use , AllowThumbDerived , false ) ; S . setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; break ; case <STR_LIT> :: IWMMXT : S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; S . setAttributeItem ( WMMX_arch , AllowWMMXv1 , false ) ; break ; case <STR_LIT> :: IWMMXT2 : S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; S . setAttributeItem ( WMMX_arch , AllowWMMXv2 , false ) ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( <STR_LIT> ( Arch ) ) ) ; break ;


<s> if ( ! decl ) return <NUM_LIT> ; cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && ( target_opts_for_fn ( target -> decl ) -> x_ix86_fpmath & FPMATH_SSE ) && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { if ( target -> local && target -> can_change_signature ) { if ( ! TARGET_SSE && warn ) return - <NUM_LIT> ; return TARGET_SSE2_P ( target_opts_for_fn ( target -> decl ) -> x_ix86_isa_flags ) ? <NUM_LIT> : <NUM_LIT> ; } } return <NUM_LIT> ;


<s> } } if ( ! Subtarget . useSoftFloat ( ) && Subtarget . hasX87 ( ) && Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT LdVT = Ld -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( Subtarget . hasDQI ( ) && VT != <STR_LIT> ) return SDValue ( ) ; if ( Ld -> isSimple ( ) && ! VT . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! Subtarget . is64Bit ( ) && LdVT == <STR_LIT> ) { SDValue FILDChain = Subtarget . getTargetLowering ( ) -> BuildFILD ( SDValue ( N , <NUM_LIT> ) , LdVT , Ld -> getChain ( ) , Op0 , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op0 . getValue ( <NUM_LIT> ) , FILDChain . getValue ( <NUM_LIT> ) ) ;


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; unsigned OpIdx = <NUM_LIT> ; if ( IsUpdating ) ++ OpIdx ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( OpIdx ++ ) ; Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( IsUpdating ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && RegNum < <NUM_LIT> ) ; Binary |= <NUM_LIT> << RegNum ; }


<s> rtx op0 , op1 ; const struct cpu_cost_table * extra_cost = aarch64_tune_params -> insn_extra_cost ; int cost = <NUM_LIT> ; bool maybe_fma = ( outer == PLUS || outer == MINUS ) ; machine_mode mode = GET_MODE ( x ) ; gcc_checking_assert ( code == MULT ) ; op0 = XEXP ( x , <NUM_LIT> ) ; op1 = XEXP ( x , <NUM_LIT> ) ; if ( VECTOR_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( CONST_INT_P ( op1 ) && exact_log2 ( INTVAL ( op1 ) ) > <NUM_LIT> ) { if ( speed ) { if ( maybe_fma ) cost += extra_cost -> alu . arith_shift ; else cost += extra_cost -> alu . shift ; } cost += rtx_cost ( op0 , GET_CODE ( op0 ) , <NUM_LIT> , speed ) ; return cost ; } if ( ( GET_CODE ( op0 ) == ZERO_EXTEND && GET_CODE ( op1 ) == ZERO_EXTEND ) || ( GET_CODE ( op0 ) == SIGN_EXTEND && GET_CODE ( op1 ) == SIGN_EXTEND ) ) { cost += rtx_cost ( XEXP ( op0 , <NUM_LIT> ) , MULT , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( op1 , <NUM_LIT> ) , MULT , <NUM_LIT> , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ <NUM_LIT> ] . extend_add ; else cost += extra_cost -> mult [ <NUM_LIT> ] . extend ; } return cost ; } cost += rtx_cost ( op0 , MULT , <NUM_LIT> , speed ) + rtx_cost ( op1 , MULT , <NUM_LIT> , speed ) ; if ( speed ) { if ( maybe_fma ) cost += extra_cost -> mult [ mode == DImode ] . add ;

else cost += extra_cost -> mult [ mode == DImode ] . simple ;


<s> if ( VSN -> isSplat ( ) ) { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; unsigned Index = VSN -> getSplatIndex ( ) ; assert ( Index < VT . getVectorNumElements ( ) && <STR_LIT> ) ; if ( ( Index == <NUM_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || Op0 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( Index ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Index , DL , <STR_LIT> ) ) ; } GeneralShuffle GS ( VT ) ; for ( unsigned I = <NUM_LIT> ; I < NumElements ; ++ I ) { int Elt = VSN -> getMaskElt ( I ) ;

if ( Elt < <NUM_LIT> ) GS . addUndef ( ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ;


<s> auto * BCastInst = Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , PointerType :: get ( II . getType ( ) , <NUM_LIT> ) ) ; return Builder . CreateAlignedLoad ( II . getType ( ) , BCastInst , Align ( Alignment ) ) ;


<s> DeadCodeElimination ( DataFlowGraph & dfg , MachineRegisterInfo & mri ) : Trace ( false ) , DFG ( dfg ) , MRI ( mri ) , LV ( mri , dfg ) {


<s> if ( A -> Mask ) Arg = ArgDescriptor :: createArg ( Arg , A -> Mask . getValue ( ) ) ; MFI -> NumUserSGPRs += UserSGPRs ; MFI -> NumSystemSGPRs += SystemSGPRs ; return false ; } ; if ( YamlMFI . ArgInfo && ( parseAndCheckArgument ( YamlMFI . ArgInfo -> PrivateSegmentBuffer , <STR_LIT> , MFI -> ArgInfo . PrivateSegmentBuffer , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> DispatchPtr , <STR_LIT> , MFI -> ArgInfo . DispatchPtr , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> QueuePtr , <STR_LIT> , MFI -> ArgInfo . QueuePtr , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> KernargSegmentPtr , <STR_LIT> , MFI -> ArgInfo . KernargSegmentPtr , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> DispatchID , <STR_LIT> , MFI -> ArgInfo . DispatchID , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> FlatScratchInit , <STR_LIT> , MFI -> ArgInfo . FlatScratchInit , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> PrivateSegmentSize , <STR_LIT> , MFI -> ArgInfo . PrivateSegmentSize , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkGroupIDX , <STR_LIT> , MFI -> ArgInfo . WorkGroupIDX , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkGroupIDY , <STR_LIT> , MFI -> ArgInfo . WorkGroupIDY , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkGroupIDZ , <STR_LIT> , MFI -> ArgInfo . WorkGroupIDZ , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkGroupInfo , <STR_LIT> , MFI -> ArgInfo . WorkGroupInfo , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> PrivateSegmentWaveByteOffset , <STR_LIT> , MFI -> ArgInfo . PrivateSegmentWaveByteOffset , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> ImplicitArgPtr , <STR_LIT> , MFI -> ArgInfo . ImplicitArgPtr , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> ImplicitBufferPtr , <STR_LIT> , MFI -> ArgInfo . ImplicitBufferPtr , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkItemIDX , <STR_LIT> , MFI -> ArgInfo . WorkItemIDX , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkItemIDY , <STR_LIT> , MFI -> ArgInfo . WorkItemIDY , <NUM_LIT> , <NUM_LIT> ) || parseAndCheckArgument ( YamlMFI . ArgInfo -> WorkItemIDZ , <STR_LIT> , MFI -> ArgInfo . WorkItemIDZ , <NUM_LIT> , <NUM_LIT> ) ) ) return true ; MFI -> Mode . IEEE = YamlMFI . Mode . IEEE ; MFI -> Mode . DX10Clamp = YamlMFI . Mode . DX10Clamp ; MFI -> Mode . FP32InputDenormals = YamlMFI . Mode . FP32InputDenormals ; MFI -> Mode . FP32OutputDenormals = YamlMFI . Mode . FP32OutputDenormals ; MFI -> Mode . FP64FP16InputDenormals = YamlMFI . Mode . FP64FP16InputDenormals ; MFI -> Mode . FP64FP16OutputDenormals = YamlMFI . Mode . FP64FP16OutputDenormals ; return false ;


<s> static __inline void si_hlgti ( qword a , unsigned int b ) { union { vector unsigned int v ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSet<ISA_LIT>16 ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ;


<s> static SDValue peekThroughEXTRACT_SUBVECTORs ( SDValue V ) {

while ( V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ;


<s> if ( rec . fName == fName && rec . reg >= <STR_LIT> && rec . reg <= <STR_LIT> ) regList . push_back ( rec . reg ) ; } if ( regList . size ( ) == <NUM_LIT> ) return <STR_LIT> ; unsigned lastReg = regList . back ( ) ;

if ( lastReg == <STR_LIT> ) return UNKNOWN_REG ;


return ( int16x4_t ) __builtin_neon_vqmovnsv4si ( __a ) ;


<s> static bool ContainsReg ( const ArrayRef < std :: pair < unsigned , bool >> & Regs , unsigned Reg ) {

for ( const std :: pair < unsigned , bool > & R : Regs ) if ( R . first == Reg ) return true ;


<s> return __builtin_mve_vbrsrq_m_n_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __b , __p ) ;


<s> bool isBlockAddress ( ) { return Kind == <STR_LIT> ;


<s> void addMemOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getMemBase ( ) ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isHighLatencyDef ( int Opc ) const {

return get ( Opc ) . mayLoad ( ) && ( isMUBUF ( Opc ) || isMTBUF ( Opc ) || isMIMG ( Opc ) || isFLAT ( Opc ) ) ;


<s> for ( int i = NumMove - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { MemOps . insert ( Ops [ i ] ) ; MemRegs . insert ( Ops [ i ] -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } bool DoMove = ( LastLoc - FirstLoc ) <= NumMove * <NUM_LIT> ; if ( DoMove ) DoMove = IsSafeAndProfitableToMove ( isLd , Base , FirstOp , LastOp , MemOps , MemRegs , TRI ) ; if ( ! DoMove ) { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( InsertPos ) || InsertPos -> isDebugValue ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned FirstReg = <NUM_LIT> , SecondReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , FirstReg , SecondReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; const MCInstrDesc & MCID = TII -> get ( NewOpc ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ; MRI -> constrainRegClass ( FirstReg , TRC ) ; MRI -> constrainRegClass ( SecondReg , TRC ) ; if ( isLd ) { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( FirstReg , RegState :: Define ) . addReg ( SecondReg , RegState :: Define ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; MIB . setMemRefs ( Op0 -> mergeMemRefsWith ( * Op1 ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumLDRDFormed ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( FirstReg ) . addReg ( SecondReg ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; MIB . setMemRefs ( Op0 -> mergeMemRefsWith ( * Op1 ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * From << <STR_LIT> << * To << <STR_LIT> ) ; for ( Use & U : From -> uses ( ) ) { auto * User = cast < Instruction > ( U . getUser ( ) ) ; if ( InstTo && User -> isIdenticalTo ( InstTo ) ) { ReplacedAll = false ; continue ; }


<s> if ( INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } } if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) ) { if ( INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) unroll = <NUM_LIT> ; else { lastbyte = INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ; if ( optimize_size || INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) unroll = <NUM_LIT> ; else if ( INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) unroll = <NUM_LIT> ; else unroll = <NUM_LIT> ; } operands [ <NUM_LIT> ] = GEN_INT ( INTVAL ( operands [ <NUM_LIT> ] ) >> unroll ) ; output_asm_insn ( <STR_LIT> , operands ) ; } else { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; if ( TARGET_40_PLUS && INTVAL ( operands [ <NUM_LIT> ] ) > <NUM_LIT> ) { unroll = <NUM_LIT> ; output_asm_insn ( <STR_LIT> , operands ) ; } else { unroll = <NUM_LIT> ; output_asm_insn ( <STR_LIT> , operands ) ; } sprintf ( buf , <STR_LIT> , count + <NUM_LIT> ) ; output_asm_insn ( buf , NULL ) ; } sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , NULL ) ; switch ( unroll ) { case <NUM_LIT> : output_asm_insn ( <STR_LIT> , operands ) ; break ; case <NUM_LIT> : output_asm_insn ( <STR_LIT> , operands ) ; break ; case <NUM_LIT> : output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; break ; default : output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; break ; } if ( TARGET_40_PLUS ) { sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , operands ) ; } else { output_asm_insn ( <STR_LIT> , operands ) ; sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , NULL ) ; } count ++ ; if ( lastbyte ) output_asm_insn ( <STR_LIT> , operands ) ;

else if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) ) {


<s> static MCInst lowerRILow ( const MachineInstr * MI , unsigned Opcode ) { return MCInstBuilder ( Opcode ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addReg ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( GV -> isDeclaration ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ;

Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ;


<s> const char * getPassName ( ) const override {


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoDsp ( ) { OS << <STR_LIT> ;

<ISA_LIT>TargetStreamer :: emitDirectiveSetNoDsp ( ) ;


<s> if ( tmp < <NUM_LIT> ) tmp = abs ( tmp ) ; else Value |= <NUM_LIT> ;


<s> Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> getAPIntValue ( ) . isAllOnesValue ( ) && ! Subtarget -> slowIncDec ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) && Op -> hasOneUse ( ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) && ! hasNonFlagsUse ( Op ) ) { EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt >= BitWidth ) break ; APInt Mask = ArithOp . getOpcode ( ) == <STR_LIT> ? APInt :: getHighBitsSet ( BitWidth , BitWidth - ShAmt ) : APInt :: getLowBitsSet ( BitWidth , BitWidth - ShAmt ) ; if ( ! Mask . isSignedIntN ( <NUM_LIT> ) ) break ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , VT ) ) ; DAG . ReplaceAllUsesWith ( Op , New ) ; Op = New ; } break ; case <STR_LIT> : if ( ! hasNonFlagsUse ( Op ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : { if ( ! NeedTruncation && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { SDValue EFLAGS = LowerVectorAllZeroTest ( Op , Subtarget , DAG ) ; if ( EFLAGS . getNode ( ) ) return EFLAGS ; } Opcode = <STR_LIT> ; break ; } } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( NeedTruncation ) { EVT VT = Op . getValueType ( ) ; SDValue WideVal = Op -> getOperand ( <NUM_LIT> ) ; EVT WideVT = WideVal . getValueType ( ) ; unsigned ConvertedOp = <NUM_LIT> ;


<s> CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2 ( ) ) return ( ScheduleHazardRecognizer * ) new <ISA_LIT>HazardRecognizer ( II , * this , getRegisterInfo ( ) , Subtarget ) ; return TargetInstrInfoImpl :: CreateTargetPostRAHazardRecognizer ( II ) ;


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ;

if ( MO . getType ( ) == MachineOperand :: MO_Register ) {


<s> bool Modified = false ; BlockIt MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { BlockIt NMBBI = std :: next ( MBBI ) ; Modified |= expandMI ( MBB , MBBI ) ; MBBI = NMBBI ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrModeUnscaled ( SDValue N , unsigned Size , SDValue & Base , SDValue & OffImm ) { if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = RHS -> getSExtValue ( ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Log2_32 ( Size ) ) ) return false ; if ( RHSC >= - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) {

int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ;


<s> static SDValue lowerV8F64VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ;

ArrayRef < int > Mask = SVOp -> getMask ( ) ;


<s> if ( ST -> is64Bit ( ) ) { if ( Vector && ST -> hasAVX512 ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } return <NUM_LIT> ;


<s> return [ = ] ( const LegalityQuery & Query ) { const LLT QueryTy = Query . Types [ TypeIdx ] ; return QueryTy . isVector ( ) && QueryTy . getElementType ( ) == Type ; } ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator FalseInsertionPoint = FalseMBB -> begin ( ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , unsigned > FalseBBRegRewriteTable ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ) { auto & MI = * MIIt ++ ; if ( ! MI . mayLoad ( ) ) { unsigned FalseReg = MI . getOperand ( <STR_LIT> ( MI ) == CC ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; while ( true ) { auto FRIt = FalseBBRegRewriteTable . find ( FalseReg ) ; if ( FRIt == FalseBBRegRewriteTable . end ( ) ) break ; FalseReg = FRIt -> second ; } FalseBBRegRewriteTable [ MI . getOperand ( <NUM_LIT> ) . getReg ( ) ] = FalseReg ; continue ; } assert ( <STR_LIT> ( MI ) == OppCC && <STR_LIT> <STR_LIT> ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned TmpReg = MRI -> createVirtualRegister ( RC ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; bool Unfolded = TII -> unfoldMemoryOperand ( * MBB -> getParent ( ) , MI , TmpReg , true , false , NewMIs ) ; ( void ) Unfolded ; assert ( Unfolded && <STR_LIT> ) ; auto * NewCMOV = NewMIs . pop_back_val ( ) ; assert ( <STR_LIT> ( * NewCMOV ) == OppCC && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewCMOV -> dump ( ) ) ; MBB -> insert ( MachineBasicBlock :: iterator ( MI ) , NewCMOV ) ; if ( & * MIItBegin == & MI ) MIItBegin = MachineBasicBlock :: iterator ( NewCMOV ) ; for ( auto * NewMI : NewMIs ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ) ; FalseMBB -> insert ( FalseInsertionPoint , NewMI ) ; for ( auto & MOp : NewMI -> uses ( ) ) { if ( ! MOp . isReg ( ) ) continue ; auto It = FalseBBRegRewriteTable . find ( MOp . getReg ( ) ) ; if ( It == FalseBBRegRewriteTable . end ( ) ) continue ; MOp . setReg ( It -> second ) ; MOp . setIsKill ( false ) ; } } MBB -> erase ( MachineBasicBlock :: iterator ( MI ) , std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) ;

FalseBBRegRewriteTable [ NewCMOV -> getOperand ( <NUM_LIT> ) . getReg ( ) ] = TmpReg ;


<s> case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ;


<s> } int RHSC ; if ( isScaledConstantInRange ( N , <NUM_LIT> << Shift , <NUM_LIT> , <NUM_LIT> , RHSC ) ) {

OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) : CurDAG -> getTargetConstant ( - RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> auto Target = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ) ; emitNops ( NoopsInSledCount ) ; OutStreamer -> emitLabel ( Target ) ; recordSled ( CurSled , MI , Kind , <NUM_LIT> ) ;


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSSE3 ( ) ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; return LowerVectorCTPOPBitmath ( Op0 , DL , Subtarget , DAG ) ; } if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue LHS = Extract128BitVector ( Op0 , <NUM_LIT> , DAG , DL ) ; SDValue RHS = Extract128BitVector ( Op0 , NumElems / <NUM_LIT> , DAG , DL ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , LowerVectorCTPOPInRegLUT ( LHS , DL , Subtarget , DAG ) , LowerVectorCTPOPInRegLUT ( RHS , DL , Subtarget , DAG ) ) ;


<s> return BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opcode ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) . addUse ( SrcReg ) . constrainAllUses ( TII , TRI , RBI ) ;


<s> for ( i = <NUM_LIT> ; i < count ; i ++ ) { rtx vector_element = XVECEXP ( op , <NUM_LIT> , i ) ; gcc_assert ( GET_CODE ( vector_element ) == SET ) ; gcc_assert ( GET_CODE ( SET_DEST ( vector_element ) ) == REG ) ; gcc_assert ( register_is_ok_for_epilogue ( SET_DEST ( vector_element ) , SImode ) ) ; mask |= <NUM_LIT> << REGNO ( SET_DEST ( vector_element ) ) ; } for ( first = <NUM_LIT> ; first < <NUM_LIT> ; first ++ ) { if ( mask & ( <NUM_LIT> << first ) ) break ; } gcc_assert ( first < <NUM_LIT> ) ; if ( mask & ( <NUM_LIT> << LINK_POINTER_REGNUM ) ) { gcc_assert ( stack_bytes == <NUM_LIT> ) ; last = LINK_POINTER_REGNUM ; } else { gcc_assert ( ! stack_bytes ) ; gcc_assert ( mask & ( <NUM_LIT> << <NUM_LIT> ) ) ; last = <NUM_LIT> ; } if ( TARGET_LONG_CALLS ) { char name [ <NUM_LIT> ] ; if ( first == last ) sprintf ( name , <STR_LIT> , reg_names [ first ] ) ; else sprintf ( name , <STR_LIT> , reg_names [ first ] , reg_names [ last ] ) ; sprintf ( buff , <STR_LIT> , name , name ) ;


<s> MVT M1VT = getLMUL1VT ( ContainerVT ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue NeutralElem = DAG . getNeutralElement ( BaseOpc , DL , VecEltVT , SDNodeFlags ( ) ) ; SDValue IdentitySplat = DAG . getSplatVector ( M1VT , DL , NeutralElem ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , Vec , IdentitySplat , Mask , VL ) ; SDValue Elt0 = DAG . getNode ( <STR_LIT> , DL , VecEltVT , Reduction , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ; return DAG . getSExtOrTrunc ( Elt0 , DL , Op . getValueType ( ) ) ;


<s> } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > StackSlotSize ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , LRSaveSize + VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } if ( isVarArg ) { static const unsigned ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FirstVAReg = CCInfo . getFirstUnallocated ( ArgRegs , array_lengthof ( ArgRegs ) ) ; if ( FirstVAReg < array_lengthof ( ArgRegs ) ) { SmallVector < SDValue , <NUM_LIT> > MemOps ; int offset = <NUM_LIT> ; for ( int i = array_lengthof ( ArgRegs ) - <NUM_LIT> ; i >= ( int ) FirstVAReg ; -- i ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , offset , true ) ; if ( i == ( int ) FirstVAReg ) { XFI -> setVarArgsFrameIndex ( FI ) ; } offset -= StackSlotSize ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ; } else { XFI -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , LRSaveSize + CCInfo . getNextStackOffset ( ) , true ) ) ; } }


<s> if ( TT . getArch ( ) == Triple :: bpfeb ) return <STR_LIT> ;


<s> for ( const MCPhysReg * CSR = TRI -> getCalleeSavedRegs ( ) ; * CSR ; ++ CSR ) { unsigned CalleeSavedReg = * CSR ; if ( MI -> modifiesRegister ( CalleeSavedReg , TRI ) ) return true ; } return false ;


<s> OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; OpNum = <NUM_LIT> ; break ; default : return false ; } auto IsDead = [ this ] ( NodeAddr < DefNode * > DA ) -> bool { return getDeadNodes ( ) . count ( DA . Id ) ; } ; NodeList Defs ; MachineOperand & Op = MI . getOperand ( OpNum ) ; for ( NodeAddr < DefNode * > DA : IA . Addr -> members_if ( DFG . IsDef , DFG ) ) { if ( & DA . Addr -> getOp ( ) != & Op ) continue ; Defs = DFG . getRelatedRefs ( IA , DA ) ; if ( ! llvm :: all_of ( Defs , IsDead ) ) return false ; break ; } for ( auto D : Defs ) Remove . insert ( D . Id ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ; MI . setDesc ( HII . get ( NewOpc ) ) ; MI . getOperand ( OpNum + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; removeOperand ( IA , OpNum ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << MI ;


<s> std :: string Name = AccessInfo . IsWrite ? <STR_LIT> : <STR_LIT> ; std :: string SymName = <STR_LIT> + Name + utostr ( <NUM_LIT> << AccessInfo . AccessSizeIndex ) + <STR_LIT> + utostr ( Reg ) ; Sym = OutContext . getOrCreateSymbol ( SymName ) ; }

EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( Sym , OutContext ) ) ) ;


<s> <ISA_LIT>Operand * MemOp = static_cast < <ISA_LIT>Operand * > ( Op ) ; if ( IsStackReg ( MemOp -> getMemBaseReg ( ) ) || IsStackReg ( MemOp -> getMemIndexReg ( ) ) ) return ; InstrumentMemOperandImpl ( MemOp , AccessSize , IsWrite , Ctx , Out ) ;


<s> unsigned InsertReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & InsMI = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: INSERT_SUBREG ) , InsertReg ) . addUse ( ImpDefReg ) . addUse ( SrcReg ) . addImm ( <STR_LIT> ) ; constrainSelectedInstRegOperands ( ImpDefMI , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( InsMI , TII , TRI , RBI ) ; InsertRegs . push_back ( InsertReg ) ; } } unsigned CopyTo = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FirstCopy = MIB . buildInstr ( TargetOpcode :: COPY , { CopyTo } , { } ) . addReg ( InsertRegs [ <NUM_LIT> ] , <NUM_LIT> , ExtractSubReg ) ; constrainSelectedInstRegOperands ( * FirstCopy , TII , TRI , RBI ) ; unsigned LaneIdx = <NUM_LIT> ; for ( unsigned InsReg : InsertRegs ) { unsigned CopyTo = I . getOperand ( LaneIdx ) . getReg ( ) ; MachineInstr & CopyInst = * BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( CopyOpc ) , CopyTo ) . addUse ( InsReg ) . addImm ( LaneIdx ) ; constrainSelectedInstRegOperands ( CopyInst , TII , TRI , RBI ) ; ++ LaneIdx ; } const TargetRegisterClass * RC = MRI . getRegClassOrNull ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> if ( isFloatingPointZero ( Op ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ;

if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Op ) ) return DAG . getLoad ( <STR_LIT> , SDLoc ( Op ) , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ;


<s> SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; bool IsStructRet = ( Outs . empty ( ) ) ? false : Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ; if ( IsStructRet ) fail ( DL , DAG , <STR_LIT> ) ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; if ( Ins . size ( ) > <NUM_LIT> ) fail ( DL , DAG , <STR_LIT> ) ; bool IsVarArg = CLI . IsVarArg ; if ( IsVarArg ) fail ( DL , DAG , <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; auto Zero = DAG . getConstant ( <NUM_LIT> , DL , PtrVT , true ) ; auto NB = DAG . getConstant ( NumBytes , DL , PtrVT , true ) ; Chain = DAG . getCALLSEQ_START ( Chain , NB , DL ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; Ops . append ( OutVals . begin ( ) , OutVals . end ( ) ) ; SmallVector < EVT , <NUM_LIT> > Tys ; for ( const auto & In : Ins ) Tys . push_back ( In . VT ) ; Tys . push_back ( <STR_LIT> ) ; SDVTList TyList = DAG . getVTList ( Tys ) ; SDValue Res = DAG . getNode ( Ins . empty ( ) ? <STR_LIT> : <STR_LIT> , DL , TyList , Ops ) ; if ( Ins . empty ( ) ) { Chain = Res ; } else { InVals . push_back ( Res ) ;


<s> return DecodeMVE_MEM_pre ( Inst , Val , Address , Decoder , fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) , DecoderGPRRegisterClass , DecodeT2AddrModeImm7 < shift , <NUM_LIT> > ) ;


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ;


<s> return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ;

const <ISA_LIT>SEInstrInfo * II = static_cast < const <ISA_LIT>SEInstrInfo * > ( & TII ) ;


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ;


<s> mode = V4SImode ; break ; default : return - <NUM_LIT> ; } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = aapcs_vfp_sub_candidate ( TREE_TYPE ( type ) , modep ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( wi :: ne_p ( TYPE_SIZE ( type ) , count * GET_MODE_BITSIZE ( * modep ) ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ;


<s> SDValue PassThru = LoadNode -> getPassThru ( ) ; SDValue Mask = LoadNode -> getMask ( ) ; if ( PassThru -> isUndef ( ) || isZerosVector ( PassThru . getNode ( ) ) ) return Op ;

SDValue Load = DAG . getMaskedLoad ( VT , DL , LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) , LoadNode -> getOffset ( ) , Mask , DAG . getUNDEF ( VT ) , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) , LoadNode -> getAddressingMode ( ) , LoadNode -> getExtensionType ( ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , UserReservedRegister ( <STR_LIT> ) , TM ( TM ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , TT , FS , TM ) ) , FrameLowering ( * this , this -> getStackAlignment ( ) ) , TLInfo ( TM , * this ) , TargetTriple ( TT ) {


<s> if ( Size >= <NUM_LIT> ) TS = CurDAG -> getStore ( SDValue ( LoadN , <NUM_LIT> ) , dl , SDValue ( LoadN , <NUM_LIT> ) , Loc , PI , false , false , Size ) ; else TS = CurDAG -> getTruncStore ( SDValue ( LoadN , <NUM_LIT> ) , dl , SDValue ( LoadN , <NUM_LIT> ) , Loc , PI , <STR_LIT> ( Size * <NUM_LIT> ) , false , false , Size ) ; SDNode * StoreN = SelectStore ( TS . getNode ( ) ) ; ReplaceUses ( SDValue ( IntN , <NUM_LIT> ) , SDValue ( LoadN , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( IntN , <NUM_LIT> ) , SDValue ( StoreN , <NUM_LIT> ) ) ; return StoreN ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : TargetInstrInfoImpl ( <ISA_LIT>Insts , array_lengthof ( <ISA_LIT>Insts ) ) , TM ( tm ) , RI ( * TM . getSubtargetImpl ( ) , * this ) {


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> return ; } if ( hasFP ( MF ) ) { MachineFunction :: iterator I ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( I = std :: next ( MF . begin ( ) ) ; I != MF . end ( ) ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } unsigned StackReg = <STR_LIT> ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) {

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> default : return <NUM_LIT> ; case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : if ( getParser ( ) . ParseExpression ( EVal ) ) return <NUM_LIT> ; int64_t ans ; EVal -> EvaluateAsAbsolute ( ans ) ;


<s> unsigned BaseRegFlags = <NUM_LIT> ; if ( CI . BaseOff ) { unsigned ImmReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , ImmReg ) . addImm ( CI . BaseOff ) ; BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BaseRegFlags = RegState :: Kill ; TII -> getAddNoCarry ( * MBB , CI . Paired , DL , BaseReg ) . addReg ( ImmReg ) . addReg ( AddrReg -> getReg ( ) , <NUM_LIT> , BaseSubReg ) ; BaseSubReg = <NUM_LIT> ; } MachineInstrBuilder Read2 = BuildMI ( * MBB , CI . Paired , DL , Read2Desc , DestReg ) . addReg ( BaseReg , BaseRegFlags , BaseSubReg ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ; ( void ) Read2 ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , CI . InstsToMove ) ; MachineBasicBlock :: iterator Next = std :: next ( CI . I ) ; CI . I -> eraseFromParent ( ) ;


<s> explicit <ISA_LIT>MCInst ( ) : MCInst ( ) , startPacket ( <NUM_LIT> ) , endPacket ( <NUM_LIT> ) {


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { if ( ! T . isOSBinFormatELF ( ) ) llvm_unreachable ( <STR_LIT> ) ; return createELFStreamer ( Context , std :: move ( MAB ) , OS , std :: move ( Emitter ) , RelaxAll ) ;


<s> bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsQPXType = ST -> hasQPX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || Alignment >= SrcBytes ) return Cost ;

if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ;


<s> bool isABI_EABI ( ) const { return <ISA_LIT>ABI == EABI ;


<s> DiagnosticInfoUnsupported BadIntrin ( * DAG . getMachineFunction ( ) . getFunction ( ) , <STR_LIT> , DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadIntrin ) ;


<s> unsigned getMinimumNopSize ( ) const override {


<s> MapVector < AllocaInst * , AllocaInfo > Allocas ; SmallVector < Instruction * , <NUM_LIT> > RetVec ; SmallVector < Instruction * , <NUM_LIT> > UnrecognizedLifetimes ; for ( auto & BB : * F ) { for ( BasicBlock :: iterator IT = BB . begin ( ) ; IT != BB . end ( ) ; ++ IT ) { Instruction * I = & * IT ; if ( auto * AI = dyn_cast < AllocaInst > ( I ) ) { Allocas [ AI ] . AI = AI ; Allocas [ AI ] . OldAI = AI ; continue ; } if ( auto * DVI = dyn_cast < DbgVariableIntrinsic > ( I ) ) { for ( Value * V : DVI -> location_ops ( ) ) if ( auto * AI = dyn_cast_or_null < AllocaInst > ( V ) ) if ( Allocas [ AI ] . DbgVariableIntrinsics . empty ( ) || Allocas [ AI ] . DbgVariableIntrinsics . back ( ) != DVI ) Allocas [ AI ] . DbgVariableIntrinsics . push_back ( DVI ) ; continue ; } auto * II = dyn_cast < IntrinsicInst > ( I ) ; if ( II && ( II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> ) ) { AllocaInst * AI = findAllocaForValue ( II -> getArgOperand ( <NUM_LIT> ) ) ; if ( ! AI ) { UnrecognizedLifetimes . push_back ( I ) ; continue ; } if ( II -> getIntrinsicID ( ) == <STR_LIT> ) Allocas [ AI ] . LifetimeStart . push_back ( II ) ; else Allocas [ AI ] . LifetimeEnd . push_back ( II ) ; } if ( isa < ReturnInst > ( I ) || isa < ResumeInst > ( I ) || isa < CleanupReturnInst > ( I ) ) RetVec . push_back ( I ) ; } } if ( Allocas . empty ( ) ) return false ; int NextTag = <NUM_LIT> ; int NumInterestingAllocas = <NUM_LIT> ; for ( auto & I : Allocas ) { AllocaInfo & Info = I . second ; assert ( Info . AI ) ; if ( ! isInterestingAlloca ( * Info . AI ) ) { Info . Tag = - <NUM_LIT> ; continue ; } alignAndPadAlloca ( Info ) ; NumInterestingAllocas ++ ; Info . Tag = NextTag ; NextTag = ( NextTag + <NUM_LIT> ) % <NUM_LIT> ; } if ( NumInterestingAllocas == <NUM_LIT> ) return true ; std :: unique_ptr < DominatorTree > DeleteDT ; DominatorTree * DT = nullptr ;

if ( auto * P = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ) DT = & P -> getDomTree ( ) ;


<s> if ( ! MaybeSub || MaybeSub -> getOpcode ( ) != TargetOpcode :: G_SUB || ! CmpInst :: isEquality ( Pred ) ) return false ;

auto MaybeZero = getConstantVRegValWithLookThrough ( MaybeSub -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ;


<s> const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> getPreservesR0 ( ) ) SavedRegs . set ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>ScalarTargetTransformImpl :: getIntImmCost ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Bits > <NUM_LIT> ) return <NUM_LIT> ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ;


<s> SmallVector < StringRef , <NUM_LIT> > TargetIDSplit ; TargetID . split ( TargetIDSplit , ':' ) ; for ( const auto & FeatureString : TargetIDSplit ) { if ( FeatureString . startswith ( <STR_LIT> ) ) XnackSetting = getTargetIDSettingFromFeatureString ( FeatureString ) ;

if ( FeatureString . startswith ( <STR_LIT> ) ) SramEccSetting = getTargetIDSettingFromFeatureString ( FeatureString ) ;


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return MaterializeInt ( C , VT ) ; return <NUM_LIT> ;


<s> OutStreamer -> emitLabel ( CurSled ) ; unsigned OpCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst Ret ; Ret . setOpcode ( OpCode ) ; for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) Ret . addOperand ( MaybeOperand . getValue ( ) ) ;

OutStreamer -> emitInstruction ( Ret , getSubtargetInfo ( ) ) ;


<s> if ( b == <NUM_LIT> ) return a ; tmp = LZ ( b ) ; for ( tmp = <NUM_LIT> ; ( ( ( long ) b & ( <NUM_LIT> << tmp ) ) == <NUM_LIT> ) ; tmp -- ) ; tmp = <NUM_LIT> - tmp ; if ( ( b << tmp ) > a ) { a -= b << ( tmp - <NUM_LIT> ) ;


<s> static int getBranchNzeroOpcode ( int oldOpcode ) { switch ( oldOpcode ) { case AMDGPU :: JUMP_COND : case AMDGPU :: JUMP : return AMDGPU :: IF_PREDICATE_SET ; case AMDGPU :: BRANCH_COND_i32 : case AMDGPU :: BRANCH_COND_f32 : return AMDGPU :: IF_LOGICALNZ_f32 ;


<s> if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ;

const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : nullptr ;


<s> return ; } int64_t Residue ; std :: unique_ptr < <ISA_LIT>Operand > NewOp = AddDisplacement ( Op , Displacement , Ctx , & Residue ) ; EmitLEA ( * NewOp , VT , Reg , Out ) ; while ( Residue != <NUM_LIT> ) { const MCConstantExpr * Disp = MCConstantExpr :: Create ( ApplyDisplacementBounds ( Residue ) , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > DispOp = <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , Reg , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ;


<s> case CM_MEDIUM : ptr -> x_ix86_cmodel = CM_MEDIUM_PIC ; break ; case CM_LARGE : ptr -> x_ix86_cmodel = CM_LARGE_PIC ; break ; case CM_KERNEL : error ( <STR_LIT> , <STR_LIT> ) ; break ; default : break ; } else switch ( ptr -> x_ix86_cmodel ) { case CM_SMALL_PIC : ptr -> x_ix86_cmodel = CM_SMALL ; break ; case CM_MEDIUM_PIC : ptr -> x_ix86_cmodel = CM_MEDIUM ; break ; case CM_LARGE_PIC :


<s> int i ; if ( ! is_fmul_fmac_insn ( insn , true ) ) continue ; dest_op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; dest_regno = REGNO ( SET_DEST ( PATTERN ( insn ) ) ) ; for ( i = <NUM_LIT> ; i < dest_op_info -> n_chains ; i ++ ) { if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ;

if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ;


<s> <ISA_LIT>ElimCompare ( const <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) {


<s> switch ( ID ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( STI . hasMOVW ( ) && <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { Register DestLo , DestHi , SrcLo , SrcHi ; TRI . splitReg ( DestReg , DestLo , DestHi ) ; TRI . splitReg ( SrcReg , SrcLo , SrcHi ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestLo ) . addReg ( SrcLo , getKillRegState ( KillSrc ) ) ;


<s> return true ; } const MDNode * LoopMD = nullptr ; if ( MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isMetadata ( ) ) { LoopMD = MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . getMetadata ( ) ; }

if ( LoopMD ) return getLoopTakenFromMetadata ( LoopMD ) ;


<s> int64_t Offset = SignExtend64 < <NUM_LIT> > ( ( Insn >> <NUM_LIT> ) & <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rt = getReg ( Decoder , <STR_LIT> , Rt ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ;

if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) {


<s> MachineRegisterInfo & getRegInfo ( Block & MBB ) {

return MBB . getParent ( ) -> getRegInfo ( ) ;


<s> explicit <ISA_LIT>MCExpr ( <ISA_LIT>ExprKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , TM ( tm ) , RI ( * TM . getSubtargetImpl ( ) , * this ) {


<s> SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , getPointerTy ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> BlackfinRegisterInfo :: BlackfinRegisterInfo ( BlackfinSubtarget & st , const TargetInstrInfo & tii ) : BlackfinGenRegisterInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( st ) , TII ( tii ) {


<s> bool <ISA_LIT>FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ;


<s> RegisterSubReg ( const Register & Reg ) : R ( Reg ) , S ( <NUM_LIT> ) {


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : return true ;


<s> unsigned <ISA_LIT>ABIInfo :: GetPtrAdduOp ( ) const {


<s> if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned DivOpc ; bool Is64bit = ( DestVT == <STR_LIT> ) ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : DivOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : DivOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned MSubOpc = Is64bit ? <STR_LIT> : <STR_LIT> ; unsigned Src0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src0Reg ) return false ; bool Src0IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ; unsigned Src1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Src1Reg ) return false ; bool Src1IsKill = hasTrivialKill ( I -> getOperand ( <NUM_LIT> ) ) ;

const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ;


<s> if ( ! Memory . OffsetImm ) return true ;

int64_t Val = Memory . OffsetImm -> getValue ( ) ;


<s> int Offset = BlockInfo [ MBB . getNumber ( ) ] ; for ( MachineInstr & MI : MBB ) { Changed |= compressJumpTable ( MI , Offset ) ; Offset += TII -> getInstSizeInBytes ( MI ) ; } }


<s> if ( ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) || ( TargetFlags == <STR_LIT> ) ) { if ( TargetFlags != <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } if ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned Src1Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src1Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> || TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src1Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { unsigned MaskReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == MaskReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } } else if ( TargetFlags == <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( DestReg == Src2Reg + <NUM_LIT> ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } else if ( TargetFlags == <STR_LIT> || TargetFlags == <STR_LIT> ) { unsigned Src2Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; if ( TargetFlags == <STR_LIT> ) { if ( DestReg + <NUM_LIT> == Src2Reg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ; } if ( Inst . getNumOperands ( ) == <NUM_LIT> ) { unsigned MaskReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( Ty -> isVectorTy ( ) ) { std :: pair < int , MVT > LT = TLI . getTypeLegalizationCost ( DL , Ty ) ; if ( LT . second . isFloatingPoint ( ) ) return LT . first + FloatFactor * getTypeNumElements ( Ty ) ; } return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ;


<s> std :: string <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( const Triple & TT , StringRef CPU ) { std :: string <ISA_LIT>ArchFeature ; <STR_LIT> ArchID = <STR_LIT> ( TT . getArchName ( ) ) ; if ( ArchID != <STR_LIT> :: INVALID && ( CPU . empty ( ) || CPU == <STR_LIT> ) ) <ISA_LIT>ArchFeature = ( <ISA_LIT>ArchFeature + <STR_LIT> + <STR_LIT> ( ArchID ) ) . str ( ) ; if ( TT . isThumb ( ) ) { if ( ! <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature += <STR_LIT> ; <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSNaCl ( ) ) { if ( ! <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature += <STR_LIT> ; <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSWindows ( ) ) { if ( ! <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature += <STR_LIT> ; <ISA_LIT>ArchFeature += <STR_LIT> ; }


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrWithOffset . first ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PtrWithOffset . second ) ; } , } } ;


<s> case NAME ## rri : \ case NAME ## rzi : \ case NAME ## iri : \ case NAME ## izi : \ case NAME ## rri_nt : \ case NAME ## rzi_nt : \ case NAME ## iri_nt : \ case NAME ## izi_nt : \ case NAME ## rri_t : \ case NAME ## rzi_t : \ case NAME ## iri_t : \ case NAME ## izi_t : case NAME ## rr : \ case NAME ## ir : \ case NAME ## rr_nt : \ case NAME ## ir_nt : \ case NAME ## rr_t : \ case NAME ## ir_t : {


<s> fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , nds32_isr_vector_size ) ; fprintf ( asm_out_file , <STR_LIT> ) ; if ( TARGET_ISA_V2 ) fprintf ( asm_out_file , <STR_LIT> , <STR_LIT> ) ; if ( TARGET_ISA_V3 ) fprintf ( asm_out_file , <STR_LIT> , <STR_LIT> ) ; if ( TARGET_ISA_V3M ) fprintf ( asm_out_file , <STR_LIT> , <STR_LIT> ) ; if ( TARGET_CMODEL_SMALL ) fprintf ( asm_out_file , <STR_LIT> , <STR_LIT> ) ; if ( TARGET_CMODEL_MEDIUM ) fprintf ( asm_out_file , <STR_LIT> , <STR_LIT> ) ; if ( TARGET_CMODEL_LARGE ) fprintf ( asm_out_file , <STR_LIT> , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , ( ( TARGET_BIG_ENDIAN ) ? <STR_LIT> : <STR_LIT> ) ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , ( ( TARGET_CMOV ) ? <STR_LIT> : <STR_LIT> ) ) ; fprintf ( asm_out_file , <STR_LIT> , ( ( TARGET_PERF_EXT ) ? <STR_LIT> : <STR_LIT> ) ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , ( ( TARGET_V3PUSH ) ? <STR_LIT> : <STR_LIT> ) ) ; fprintf ( asm_out_file , <STR_LIT> , ( ( TARGET_16_BIT ) ? <STR_LIT> : <STR_LIT> ) ) ;

fprintf ( asm_out_file , <STR_LIT> , ( ( TARGET_REDUCED_REGS ) ? <STR_LIT> : <STR_LIT> ) ) ;


<s> unsigned int cnt = Removables . size ( ) ; for ( std :: set < MachineInstr * > :: iterator I = Removables . begin ( ) , E = Removables . end ( ) ; I != E ; ++ I ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * * I ) ; ( * I ) -> eraseFromParent ( ) ; } Removables . clear ( ) ; return cnt ;


<s> <ISA_LIT>OptimizeVSETVLUses ( ) : MachineFunctionPass ( ID ) {


<s> if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; IsPIC = TM . getRelocationModel ( ) == Reloc :: PIC_ ; JTI -> Initialize ( MF , IsPIC ) ; MMI = & getAnalysis < MachineModuleInfo > ( ) ; MCE . setModuleInfo ( MMI ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getHWRegChan ( unsigned reg ) const { return MRI . getEncodingValue ( reg ) >> HW_CHAN_SHIFT ;


<s> unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( DstRC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( DstRC , <STR_LIT> ) ; assert ( ( Sub1 == SubLo && Sub2 == SubHi ) || ( Sub1 == SubHi && Sub2 == SubLo ) ) ; if ( Sub1 == SubLo && Sub2 == SubHi ) { SL = I . getOperand ( <NUM_LIT> ) ; SH = I . getOperand ( <NUM_LIT> ) ; return true ; } if ( Sub1 == SubHi && Sub2 == SubLo ) { SH = I . getOperand ( <NUM_LIT> ) ; SL = I . getOperand ( <NUM_LIT> ) ;


<s> return RegisterBankInfo :: copyCost ( A , B , Size ) ;


<s> return DAG . getNode ( ( invert ? <STR_LIT> : <STR_LIT> ) , DL , True . getValueType ( ) , True , False , Cond ) ;


<s> if ( strstr ( argv [ i ] , <STR_LIT> ) ) target_ilp32 = true ; else if ( ! strstr ( argv [ i ] , <STR_LIT> ) ) fatal_error ( input_location , <STR_LIT> ) ; break ; } const char * target_so_filename = prepare_target_image ( target_compiler , argc , argv ) ; const char * host_descr_filename = generate_host_descr_file ( host_compiler ) ; unsigned new_argc = <NUM_LIT> ; const char * new_argv [ <NUM_LIT> ] ; new_argv [ new_argc ++ ] = <STR_LIT> ; new_argv [ new_argc ++ ] = <STR_LIT> ; if ( target_ilp32 ) new_argv [ new_argc ++ ] = <STR_LIT> ; else new_argv [ new_argc ++ ] = <STR_LIT> ; new_argv [ new_argc ++ ] = <STR_LIT> ; new_argv [ new_argc ++ ] = host_descr_filename ; new_argv [ new_argc ++ ] = target_so_filename ; new_argv [ new_argc ++ ] = <STR_LIT> ; new_argv [ new_argc ++ ] = out_obj_filename ; new_argv [ new_argc ++ ] = NULL ; fork_execute ( new_argv [ <NUM_LIT> ] , CONST_CAST ( char * * , new_argv ) , false ) ; new_argv [ <NUM_LIT> ] = <STR_LIT> ; new_argv [ <NUM_LIT> ] = <STR_LIT> ; new_argv [ <NUM_LIT> ] = symbols [ <NUM_LIT> ] ; new_argv [ <NUM_LIT> ] = <STR_LIT> ;


<s> return ( ( AM5Opc >> <NUM_LIT> ) & <NUM_LIT> ) ? sub : add ;


<s> if ( ! isInt < <NUM_LIT> > ( Src . getImm ( ) ) || TII -> isInlineConstant ( Src ) ) return false ; ReverseImm = reverseBits < int32_t > ( static_cast < int32_t > ( Src . getImm ( ) ) ) ;

return ReverseImm >= - <NUM_LIT> && ReverseImm <= <NUM_LIT> ;


<s> <ISA_LIT>ELFDynamic :: ~ <ISA_LIT>ELFDynamic ( ) {


<s> static __inline qword si_sfi ( qword a , int b ) {

return ( ( qword ) ( vec_sub ( vec_splat ( ( vec_int4 ) ( si_from_int ( b ) ) , <NUM_LIT> ) , ( vec_int4 ) ( a ) ) ) ) ;


<s> return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , DL , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( VaListSize , DL , <STR_LIT> ) , Align ( PtrSize ) , false , false , false , MachinePointerInfo ( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> if ( ! crtl -> is_leaf && call_used_regs [ regno ] ) current_frame_info . save_regs [ regno ] = <NUM_LIT> ; else if ( df_regs_ever_live_p ( regno ) ) current_frame_info . save_regs [ regno ] = <NUM_LIT> ; else current_frame_info . save_regs [ regno ] = <NUM_LIT> ; } else { if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] || regno == RETURN_ADDRESS_REGNUM ) ) current_frame_info . save_regs [ regno ] = <NUM_LIT> ; else current_frame_info . save_regs [ regno ] = <NUM_LIT> ; } } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; ; ++ i ) {


<s> static SDValue foldADCToCINC ( SDNode * N , SelectionDAG & DAG ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( ! isNullConstant ( RHS ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue CC = DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHS , CC , Cond ) ;


<s> unsigned getStackEntry ( unsigned STi ) const {

assert ( STi < StackTop && <STR_LIT> ) ;


<s> Register Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT SrcTy = MRI . getType ( Src1Reg ) ; const LLT DstTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto LaneIdx = getSplatIndex ( MI ) ; if ( ! LaneIdx ) return false ; if ( * LaneIdx >= SrcTy . getNumElements ( ) ) return false ; if ( DstTy != SrcTy ) return false ; LLT ScalarTy = SrcTy . getElementType ( ) ; unsigned ScalarSize = ScalarTy . getSizeInBits ( ) ; unsigned Opc = <NUM_LIT> ; switch ( SrcTy . getNumElements ( ) ) { case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; else if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( ScalarSize == <NUM_LIT> ) Opc = <STR_LIT> ; break ; default : break ; } if ( ! Opc ) return false ;


<s> rtx addr ; if ( count != <NUM_LIT> ) { offset = - <NUM_LIT> ; addr = plus_constant ( Pmode , frameaddr , offset ) ; addr = memory_address ( Pmode , addr ) ; return gen_rtx_MEM ( Pmode , addr ) ; }

return get_hard_reg_initial_val ( Pmode , LP_REGNUM ) ;


<s> auto Token = Parser . getTok ( ) ; SMLoc S = Token . getLoc ( ) ; if ( Token . isNot ( AsmToken :: Dollar ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Token . is ( AsmToken :: Identifier ) ) { if ( searchSymbolAlias ( Operands ) ) return MatchOperand_Success ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MatchOperand_NoMatch ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; OperandMatchResultTy ResTy = matchAnyRegisterWithoutDollar ( Operands , S ) ; if ( ResTy == MatchOperand_Success ) {


<s> unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeAddrModeImm12Operand ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( Root ) ;


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return __builtin_aarch64_qtbx3v16qi ( r , __o , ( int8x16_t ) idx ) ;


<s>
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
<NUM_LIT>
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
getTextSection
(
)
)
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
const
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_PROGBITS
,
<NUM_LIT>
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
.
emitRawComment
(
<STR_LIT>
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
FloatMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
ScratchSize
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
.
emitRawComment
(
Twine
(
<STR_LIT>
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
&&
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_NOTE
,
<NUM_LIT>
,
SectionKind
::
getReadOnly
(
)
)
)
;
for
(
size_t
i
=
<NUM_LIT>
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
<STR_LIT>
+
HexLines
[
i
]
+
<STR_LIT>
;

OutStreamer . EmitBytes ( StringRef ( DisasmLines [ i ] ) ) ;


<s> if ( op2_def . set_src == NULL_RTX || ! MEM_P ( op2_def . set_src ) || GET_MODE ( op2_def . set_src ) != QImode || ! rx_is_restricted_memory_address ( XEXP ( op2_def . set_src , <NUM_LIT> ) , GET_MODE ( op2_def . set_src ) ) || reg_used_between_p ( operands [ <NUM_LIT> ] , op2_def . insn , curr_insn ) || ! rx_reg_dead_or_unused_after_insn ( curr_insn , REGNO ( op2_reg ) ) ) return false ; rtx mem = op2_def . set_src ; if ( GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == POST_INC || GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == PRE_INC || GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == POST_DEC || GET_CODE ( XEXP ( mem , <NUM_LIT> ) ) == PRE_DEC ) return false ; rtx_insn * op0_use = rx_find_use_of_reg ( operands [ <NUM_LIT> ] , curr_insn , next_nonnote_nondebug_insn_bb ) ;

if ( op0_use == NULL || ! ( GET_CODE ( PATTERN ( op0_use ) ) == SET && RX_REG_P ( XEXP ( PATTERN ( op0_use ) , <NUM_LIT> ) ) && reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , XEXP ( PATTERN ( op0_use ) , <NUM_LIT> ) ) && rtx_equal_p ( mem , XEXP ( PATTERN ( op0_use ) , <NUM_LIT> ) ) ) || ! rx_reg_dead_or_unused_after_insn ( op0_use , REGNO ( operands [ <NUM_LIT> ] ) ) || reg_set_between_p ( operands [ <NUM_LIT> ] , curr_insn , op0_use ) ) return false ;


<s> return Kind == k_VectorListIndexed && ! VectorList . isDoubleSpaced ;


<s> return ( __m256i ) __builtin_ia32_pbroadcastb256 ( ( __v16qi ) __X ) ;


<s> <STR_LIT> SimpleTy = RegVT . getSimpleVT ( ) . SimpleTy ; switch ( SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << '\n' ; llvm_unreachable ( nullptr ) ; } case <STR_LIT> : case <STR_LIT> : Register VReg = RegInfo . createVirtualRegister ( SimpleTy == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } } else { fail ( DL , DAG , <STR_LIT> ) ;

InVals . push_back ( DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ;


<s> switch ( MOTy ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock :

case MachineOperand :: MO_GlobalAddress :


<s> TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; DEBUG ( cerr << <STR_LIT> ) ; DEBUG ( LastInst -> dump ( ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( isCondBranch ( SecondLastInst ) && isUncondBranch ( LastInst ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; DEBUG ( cerr << <STR_LIT> ) ; DEBUG ( SecondLastInst -> dump ( ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ;

Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ;


<s> J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ;


<s> if ( PB != Latch ) { assert ( Prolog == nullptr && <STR_LIT> ) ; Prolog = PB ; } } LoopInst = & ( * ( -- Prolog -> end ( ) ) ) ; if ( ! isLoop ( LoopInst ) ) { return false ; } if ( checkForProhibitingInstructions ( ) ) { return false ; } PrologInserter = -- Prolog -> end ( ) ; const MDNode * LoopMD = nullptr ; calcLoopForm ( ) ; if ( EndInstr . getOperand ( EndInstr . getNumOperands ( ) - <NUM_LIT> ) . isMetadata ( ) ) { LoopMD = EndInstr . getOperand ( EndInstr . getNumOperands ( ) - <NUM_LIT> ) . getMetadata ( ) ; } if ( LoopMD ) { unsigned UnrollCount = getUnrollCountFromMetadata ( LoopMD ) ; bool DoPipeline = getPipelineFromMetadata ( LoopMD ) ; if ( UnrollCount > <NUM_LIT> ) { if ( LoopInst -> getOperand ( <NUM_LIT> ) . isImm ( ) && LoopInst -> getOperand ( <NUM_LIT> ) . isImm ( ) && LoopInst -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { int Start = LoopInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int Bound = LoopInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int Step = LoopInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( Bound - Start / Step ) % UnrollCount != <NUM_LIT> ) {


<s> Src0 . ChangeToImmediate ( MovSrc . getImm ( ) ) ; ConstantFolded = true ; } else if ( MovSrc . isFI ( ) ) { Src0 . ChangeToFrameIndex ( MovSrc . getIndex ( ) ) ; ConstantFolded = true ; } else if ( MovSrc . isGlobal ( ) ) { Src0 . ChangeToGA ( MovSrc . getGlobal ( ) , MovSrc . getOffset ( ) , MovSrc . getTargetFlags ( ) ) ; ConstantFolded = true ; } } if ( ConstantFolded ) { if ( MRI -> use_nodbg_empty ( Reg ) ) Def -> eraseFromParent ( ) ;


<s> if ( In<ISA_LIT>16Mode && ! IsSoftFloat ) In<ISA_LIT>16HardFloat = true ; if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ; else if ( isABI_N32 ( ) || isABI_N64 ( ) ) stackAlignment = Align ( <NUM_LIT> ) ; else { assert ( isABI_O32 ( ) && <STR_LIT> ) ;


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_ARM , false ) {


<s> MVT MulVT = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; bool IsSigned = Op -> getOpcode ( ) == <STR_LIT> ; unsigned Opcode = ( ! IsSigned || ! Subtarget . hasSSE41 ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue Mul1 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getBitcast ( VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget . hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT , DAG . getDataLayout ( ) ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ; SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op1 , ShAmt ) , Op0 ) ; SDValue Fixup = DAG . getNode ( <STR_LIT> , dl , VT , T1 , T2 ) ; Highs = DAG . getNode ( <STR_LIT> , dl , VT , Highs , Fixup ) ; } SDValue Ops [ ] = { Lows , Highs } ;

return DAG . getMergeValues ( Ops , dl ) ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , NULL , <NUM_LIT> , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , NULL , <NUM_LIT> , MemVT , false , false , <NUM_LIT> ) ; -- I ;

CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Result ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredCatchPad ( MachineInstr & MI , MachineBasicBlock * BB ) const { MachineFunction * MF = BB -> getParent ( ) ;

const Constant * PerFn = MF -> getFunction ( ) -> getPersonalityFn ( ) ;


<s> if ( ExtraSteps == TargetLoweringBase :: ReciprocalEstimate :: Unspecified ) ExtraSteps = VT . getScalarType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; return DAG . getNode ( Opcode , SDLoc ( Operand ) , VT , Operand ) ; }


<s> PostGenericScheduler :: enterMBB ( MBB ) ;


<s> return ( ( vec_double2 ) ( si_rotqbybi ( ( qword ) ( a ) , si_from_int ( count ) ) ) ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const {


<s> unsigned MaxLen = EnableOpt ? <NUM_LIT> : <NUM_LIT> ; return ( ! EnableMinSize ) ? Helper . tryCombineMemCpyFamily ( MI , MaxLen ) : false ; } default : break ; } } if ( Generated . tryCombineAll ( Observer , MI , B ) ) return true ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector ( MI ) ; } return false ;


<s> bool hasHardQuad ( ) const { return HasHardQuad ;


<s> assert ( Factor >= <NUM_LIT> && Factor <= getMaxSupportedInterleaveFactor ( ) && <STR_LIT> ) ; assert ( ! Shuffles . empty ( ) && <STR_LIT> ) ; assert ( Shuffles . size ( ) == Indices . size ( ) && <STR_LIT> ) ; VectorType * VecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; Type * EltTy = VecTy -> getElementType ( ) ; const DataLayout & DL = LI -> getModule ( ) -> getDataLayout ( ) ; if ( ! isLegalInterleavedAccessType ( Factor , VecTy , DL ) ) return false ; unsigned NumLoads = getNumInterleavedAccesses ( VecTy , DL ) ; if ( EltTy -> isPointerTy ( ) ) VecTy = VectorType :: get ( DL . getIntPtrType ( EltTy ) , VecTy -> getNumElements ( ) ) ; IRBuilder < > Builder ( LI ) ; Value * BaseAddr = LI -> getPointerOperand ( ) ; if ( NumLoads > <NUM_LIT> ) { VecTy = VectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / NumLoads ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ) ; } assert ( isTypeLegal ( EVT :: getEVT ( VecTy ) ) && <STR_LIT> ) ; auto createLoadIntrinsic = [ & ] ( Value * BaseAddr ) { if ( Subtarget -> hasNEON ( ) ) { Type * Int8Ptr = Builder . getInt8PtrTy ( LI -> getPointerAddressSpace ( ) ) ; Type * Tys [ ] = { VecTy , Int8Ptr } ; static const <STR_LIT> LoadInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * VldnFunc = <STR_LIT> ( LI -> getModule ( ) , LoadInts [ Factor - <NUM_LIT> ] , Tys ) ; SmallVector < Value * , <NUM_LIT> > Ops ; Ops . push_back ( Builder . CreateBitCast ( BaseAddr , Int8Ptr ) ) ; Ops . push_back ( Builder . getInt32 ( LI -> getAlignment ( ) ) ) ; return Builder . CreateCall ( VldnFunc , Ops , <STR_LIT> ) ; } else { assert ( ( Factor == <NUM_LIT> || Factor == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> LoadInts = Factor == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;

Type * VecEltTy = VecTy -> getElementType ( ) -> getPointerTo ( LI -> getPointerAddressSpace ( ) ) ;