<s> bool Changed = false ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ;

if ( ( TM -> getCodeModel ( ) == CodeModel :: Large || MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) {


<s> const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - <NUM_LIT> ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != <NUM_LIT> ) return true ; unsigned RegOp = OpNo + <NUM_LIT> ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; return false ; }


<s> else if ( STI . isTargetWindows ( ) ) FramePtr = <STR_LIT> ; else FramePtr = STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> void m68k_output_pic_call ( rtx dest ) { const char * out ; if ( ! ( GET_CODE ( dest ) == MEM && GET_CODE ( XEXP ( dest , <NUM_LIT> ) ) == SYMBOL_REF ) ) out = <STR_LIT> ; else if ( TARGET_PCREL ) out = <STR_LIT> ;

else if ( TARGET_68020 ) out = <STR_LIT> ;


<s> std :: unique_ptr < ScheduleDAGMutation > create<ISA_LIT>MacroFusionDAGMutation ( ) {

return createBranchMacroFusionDAGMutation ( shouldScheduleAdjacent ) ;


<s> bool arg0 ( unsigned idx ) { return idx == <NUM_LIT> ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & C , EVT VT ) const { if ( VT . isVector ( ) ) return VT . changeVectorElementTypeToInteger ( ) ; return TargetLowering :: getSetCCResultType ( DL , C , VT ) ;


<s> src = gen_rtx_MEM ( mode , src_reg ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ; } if ( ! reload_in_progress && ! reload_completed && GET_CODE ( dest ) == MEM && ( GET_CODE ( XEXP ( dest , <NUM_LIT> ) ) != CONST_INT || ! xstormy16_legitimate_address_p ( mode , XEXP ( dest , <NUM_LIT> ) , <NUM_LIT> ) ) && ! xstormy16_below100_operand ( dest , mode ) && GET_CODE ( src ) != REG && GET_CODE ( src ) != SUBREG ) src = copy_to_mode_reg ( mode , src ) ; if ( reload_completed && mode != HImode && mode != QImode ) { xstormy16_split_move ( mode , dest , src ) ; return ;


<s> if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s3 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( const4 ) ) ; status = DecodeOperandRegister ( Inst , s1 , Address , Decoder ) ;


<s> if ( N . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> ) return CurDAG -> getTargetInsertSubreg ( <STR_LIT> , DL , VT , getUNDEF64 ( DL ) , N ) ; if ( N . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> ) return CurDAG -> getTargetExtractSubreg ( <STR_LIT> , DL , VT , N ) ; assert ( N . getValueType ( ) == VT && <STR_LIT> ) ; return N ;


<s> Attribute CPUAttr = F . getFnAttribute ( <STR_LIT> ) ; Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ;

std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ;


<s> case <STR_LIT> : case TargetOpcode :: COPY : if ( isPredReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { RegisterSubReg RD = MI -> getOperand ( <NUM_LIT> ) ; if ( Register :: isVirtualRegister ( RD . R ) ) PredGPRs . insert ( RD ) ; } break ; } } }


<s> addPass ( create<ISA_LIT>CFGStructurizerPass ( ) , false ) ;

addPass ( create<ISA_LIT>PreEmitImmPass ( get<ISA_LIT>TargetMachine ( ) . MCP ) , false ) ;


return ( EncVal << <NUM_LIT> ) | ( EncVal << <NUM_LIT> ) | <NUM_LIT> ;


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; <ISA_LIT>MachineFunctionInfo * FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int BackChainIdx = FI -> getFramePointerSaveIndex ( ) ; if ( ! BackChainIdx ) { BackChainIdx = MFI -> CreateFixedObject ( <NUM_LIT> , - <STR_LIT> , false ) ; FI -> setFramePointerSaveIndex ( BackChainIdx ) ; }

SDValue BackChain = DAG . getFrameIndex ( BackChainIdx , PtrVT ) ;


<s> return ( __m128 ) __builtin_ia32_addsubps ( ( __v4sf ) __X , ( __v4sf ) __Y ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: glueCopyToM0 ( SDNode * N , SDValue Val ) const { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue M0 = Lowering . copyToM0 ( * CurDAG , N -> getOperand ( <NUM_LIT> ) , SDLoc ( N ) , Val ) ; SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> rtx condition , cmp_result ; int cmp_value ; if ( target == <NUM_LIT> || GET_MODE ( target ) != SImode ) target = gen_reg_rtx ( SImode ) ; cmp_result = gen_rtx_REG ( CCDSPmode , CCDSP_PO_REGNUM ) ; if ( builtin_type == MIPS_BUILTIN_BPOSGE32 ) cmp_value = <NUM_LIT> ; else gcc_assert ( <NUM_LIT> ) ;

condition = gen_rtx_GE ( VOIDmode , cmp_result , GEN_INT ( cmp_value ) ) ;


<s> int stack_top_dies = find_regno_note ( insn , REG_DEAD , FIRST_STACK_REG ) != <NUM_LIT> ; int dimode_p = GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ; int round_mode = get_attr_i387_cw ( insn ) ; if ( ( dimode_p || fisttp ) && ! stack_top_dies ) output_asm_insn ( <STR_LIT> , operands ) ; gcc_assert ( STACK_TOP_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( MEM_P ( operands [ <NUM_LIT> ] ) ) ; gcc_assert ( GET_MODE ( operands [ <NUM_LIT> ] ) != TFmode ) ; if ( fisttp ) output_asm_insn ( <STR_LIT> , operands ) ; else { if ( round_mode != I387_CW_ANY ) output_asm_insn ( <STR_LIT> , operands ) ; if ( stack_top_dies || dimode_p ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( <STR_LIT> , operands ) ; } return <STR_LIT> ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetDsp ( ) {


<s> assert ( bool ( isExactFPImm < ImmIs0 , ImmIs1 > ( ) ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( bool ( isExactFPImm < ImmIs1 > ( ) ) ) ) ;


<s> switch ( IntrinID ) { default : return false ; case <STR_LIT> : MIRBuilder . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIRBuilder . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; } I . eraseFromParent ( ) ; return true ;


<s> if ( op == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( op ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <STR_LIT> ) -> addRegisterDead ( <STR_LIT> , RegInfo ) ; else BuildMI ( MBB , I , DL , get ( op ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) -> addRegisterDead ( <STR_LIT> , RegInfo ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; if ( op == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( op ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <STR_LIT> ) ; else BuildMI ( MBB , I , DL , get ( op ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> static bool s390_function_arg_float ( machine_mode mode , const_tree type ) { int size = s390_function_arg_size ( mode , type ) ; if ( size > <NUM_LIT> ) return false ; if ( TARGET_SOFT_FLOAT ) return false ; if ( ! type ) return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode ; while ( TREE_CODE ( type ) == RECORD_TYPE ) { tree field , single = NULL_TREE ; for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( single == NULL_TREE ) single = TREE_TYPE ( field ) ; else return false ; } if ( single == NULL_TREE ) return false ; else type = single ;


<s> MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset FeatureBits = STI . getFeatureBits ( ) ; FeatureBits &= ~ <ISA_LIT>AssemblerOptions :: AllArchRelatedMask ; STI . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( ArchFeature ) ) ) ;

AssemblerOptions . back ( ) -> setFeatures ( STI . getFeatureBits ( ) ) ;


else Expr = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ;


<s> case <STR_LIT> : case <STR_LIT> : { MemSDNode * M = cast < MemSDNode > ( Op ) ; unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( Opc , SDLoc ( Op ) , M -> getVTList ( ) , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; } default :


<s> ForCodeSize = MF . getFunction ( ) -> hasFnAttribute ( Attribute :: OptimizeForSize ) || MF . getFunction ( ) -> hasFnAttribute ( Attribute :: MinSize ) ; Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> bool ReadDef = MI . readsVirtualRegister ( Def -> getReg ( ) ) ; if ( ReadDef ) { Insts . push_back ( & MI ) ; addDefsToList ( MI , Defs ) ; return true ; } } return false ;


<s> const std :: string & <ISA_LIT>LA25Stub :: name ( ) const { return m_Name ;


<s> if ( WaterIsInRange ( UserOffset , WaterBB , U ) ) { if ( isThumb && ( BBOffsets [ WaterBB -> getNumber ( ) ] + BBSizes [ WaterBB -> getNumber ( ) ] ) % <NUM_LIT> != <NUM_LIT> ) { if ( ! WaterBBThatWouldPad ) { WaterBBThatWouldPad = WaterBB ; IPThatWouldPad = IP ; } } else {

* NewMBB = AcceptWater ( WaterBB , IP ) ;


<s> temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_s16 ( val . val [ <NUM_LIT> ] , vcreate_s16 ( __AARCH64_INT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( getDataType ( ) ) ) ;


<s> for ( const MachineOperand & Op : MI . explicit_operands ( ) ) if ( isIndex ( Op , RI ) ) { return true ; }


<s> void emitExportName ( const MCSymbolWasm * , StringRef ) override {


<s> void <ISA_LIT>TargetAsmStreamer :: emitArchExtension ( unsigned ArchExt ) {

OS << <STR_LIT> << <STR_LIT> ( ArchExt ) << <STR_LIT> ;


<s> for ( CallGraphNode * I : SCC ) { Function * F = I -> getFunction ( ) ; if ( ! F || F -> isDeclaration ( ) || <STR_LIT> ( F -> getCallingConv ( ) ) ) continue ; Changed |= addFeatureAttributes ( * F ) ; }


<s> } else if ( ( name [ <NUM_LIT> ] == FASTCALL_PREFIX ) || ( strncmp ( name , DLL_EXPORT_PREFIX , strlen ( DLL_EXPORT_PREFIX ) ) == <NUM_LIT> && name [ strlen ( DLL_EXPORT_PREFIX ) ] == FASTCALL_PREFIX ) ) { fprintf ( stream , <STR_LIT> , i386_pe_strip_name_encoding ( name ) ) ; } else { fprintf ( stream , <STR_LIT> , USER_LABEL_PREFIX , i386_pe_strip_name_encoding ( name ) ) ; }


<s> SBase -> setReg ( SGPR ) ; } MachineOperand * SOff = getNamedOperand ( MI , <STR_LIT> :: soff ) ; if ( SOff && ! RI . isSGPRClass ( MRI . getRegClass ( SOff -> getReg ( ) ) ) ) { Register SGPR = readlaneVGPRToSGPR ( SOff -> getReg ( ) , MI , MRI ) ; SOff -> setReg ( SGPR ) ;


<s> } else { errs ( ) << <STR_LIT> << Base . FrameIndex << '\n' ; } if ( ! isRI ) { errs ( ) << <STR_LIT> ; if ( IndexReg . getNode ( ) != <NUM_LIT> ) IndexReg . getNode ( ) -> dump ( ) ;


<s> <ISA_LIT>SchedulerCandidate ( ) : Reason ( NoCand ) , RepeatReasonSet ( <NUM_LIT> ) {


<s> if ( arity >= MAX_ARGS ) return NULL_RTX ; if ( O_IMM_P ( op_flags ) && TREE_CODE ( arg ) != INTEGER_CST ) { error ( <STR_LIT> , fndecl , arity + <NUM_LIT> ) ; return const0_rtx ; } if ( ! s390_const_operand_ok ( arg , arity + <NUM_LIT> , op_flags , fndecl ) ) return const0_rtx ; insn_op = & insn_data [ icode ] . operand [ arity + nonvoid ] ; op [ arity ] = expand_expr ( arg , NULL_RTX , insn_op -> mode , EXPAND_NORMAL ) ; if ( CONST_INT_P ( op [ arity ] ) && SCALAR_INT_MODE_P ( insn_op -> mode ) && GET_MODE ( op [ arity ] ) != insn_op -> mode ) op [ arity ] = GEN_INT ( trunc_int_for_mode ( INTVAL ( op [ arity ] ) , insn_op -> mode ) ) ; if ( POINTER_TYPE_P ( TREE_TYPE ( arg ) ) && insn_op -> predicate != address_operand ) op [ arity ] = gen_rtx_MEM ( insn_op -> mode , op [ arity ] ) ; if ( op_flags == O_ELEM ) { gcc_assert ( last_vec_mode != VOIDmode ) ; op [ arity ] = simplify_expand_binop ( SImode , code_to_optab ( AND ) , op [ arity ] , GEN_INT ( GET_MODE_NUNITS ( last_vec_mode ) - <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; } if ( VECTOR_MODE_P ( insn_op -> mode ) ) last_vec_mode = insn_op -> mode ; if ( insn_op -> predicate ( op [ arity ] , insn_op -> mode ) ) { arity ++ ; continue ; } if ( MEM_P ( op [ arity ] ) && insn_op -> predicate == memory_operand && ( GET_MODE ( XEXP ( op [ arity ] , <NUM_LIT> ) ) == Pmode || GET_MODE ( XEXP ( op [ arity ] , <NUM_LIT> ) ) == VOIDmode ) ) { op [ arity ] = replace_equiv_address ( op [ arity ] , copy_to_mode_reg ( Pmode , XEXP ( op [ arity ] , <NUM_LIT> ) ) ) ; } else if ( GET_MODE ( op [ arity ] ) == insn_op -> mode || GET_MODE ( op [ arity ] ) == VOIDmode || ( insn_op -> predicate == address_operand && GET_MODE ( op [ arity ] ) == Pmode ) ) { machine_mode target_mode = ( insn_op -> predicate == address_operand ? Pmode : insn_op -> mode ) ; op [ arity ] = copy_to_mode_reg ( target_mode , op [ arity ] ) ; } if ( ! insn_op -> predicate ( op [ arity ] , insn_op -> mode ) ) {

error ( <STR_LIT> , arity + <NUM_LIT> , fndecl ) ;


<s> void <ISA_LIT>_64GNULDBackend :: setRelPLTSize ( ) { ELFFileFormat * file_format = getOutputFormat ( ) ;

file_format -> getRelaPlt ( ) . setSize ( m_pRelPLT -> numOfRelocs ( ) * getRelaEntrySize ( ) ) ;


<s> if ( startswith ( s -> named . name , <STR_LIT> ) ) { char * name = ( char * ) alloca ( strlen ( s -> named . name ) + <NUM_LIT> ) ; sprintf ( name , <STR_LIT> , s -> named . name + <NUM_LIT> ) ; return get_section ( name , s -> named . common . flags , NULL ) ; } if ( s == data_section ) return sdata_section ; } return s ;


<s> if ( auto Const = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return Const -> getZExtValue ( ) == <NUM_LIT> ;


<s> if ( Type == <STR_LIT> ) { unsigned subInst0Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ; unsigned subInst1Opcode = ID . getOperand ( <NUM_LIT> ) . getInst ( ) -> getOpcode ( ) ;

Result += ! isDuplexAGroup ( subInst0Opcode ) ;


<s> const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) . addReg ( PredReg ) . setMIFlags ( MIFlags ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const {


<s> return false ; } if ( ! Mem . WithPreDec ) { return false ; }


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> emit_insn ( gen_rtx_SET ( dest , gen_rtx_IOR ( SImode , temp , GEN_INT ( c & <NUM_LIT> ) ) ) ) ; break ; case E_DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( dest , WORDS_BIG_ENDIAN == <NUM_LIT> , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != <NUM_LIT> , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> <NUM_LIT> ) ) ; c = sext_hwi ( c , <NUM_LIT> ) ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ;

if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , GEN_INT ( c ) ) ;


<s> AnalyzeFormalArguments ( CCInfo , Splits ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) , ArgIdx = <NUM_LIT> ; i != e ; ++ i ) { const <STR_LIT> & Arg = Ins [ i ] ; if ( Skipped & ( <NUM_LIT> << i ) ) { InVals . push_back ( DAG . getUNDEF ( Arg . VT ) ) ; continue ; } CCValAssign & VA = ArgLocs [ ArgIdx ++ ] ; EVT VT = VA . getLocVT ( ) ; if ( VA . isMemLoc ( ) ) { VT = Ins [ i ] . VT ; EVT MemVT = Splits [ i ] . VT ; SDValue Arg = LowerParameter ( DAG , VT , MemVT , DL , DAG . getRoot ( ) , <NUM_LIT> + VA . getLocMemOffset ( ) , Ins [ i ] . Flags . isSExt ( ) ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; unsigned Reg = VA . getLocReg ( ) ; if ( VT == <STR_LIT> ) { Reg = TRI -> getMatchingSuperReg ( Reg , AMDGPU :: sub0 , & AMDGPU :: SReg_64RegClass ) ; Reg = MF . addLiveIn ( Reg , & AMDGPU :: SReg_64RegClass ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ) ; continue ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; Reg = MF . addLiveIn ( Reg , RC ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; if ( Arg . VT . isVector ( ) ) { Type * ParamType = FType -> getParamType ( Arg . OrigArgIndex ) ; unsigned NumElements = ParamType -> getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Regs ;


<s> return ( int16x4_t ) __builtin_aarch64_sqnegv4hi ( __a ) ;


<s> void mmix_asm_output_aligned_local ( FILE * stream , const char * name , int size , int align ) {


<s> assemble_name ( file , fnname ) ; putc ( '\n' , file ) ; } inside_function = FALSE ; if ( TARGET_ABI_UNICOSMK ) {

unicosmk_output_ssib ( file , fnname ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU , bool isLittle ) { switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MachO :: CPUSubType<ISA_LIT> CS = getMachOSubTypeFromArch ( TheTriple . getArchName ( ) ) ; return new <ISA_LIT>AsmBackendDarwin ( T , TheTriple , CS ) ; } case Triple :: COFF :

assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ;


<s> StringMapEntry < unsigned > & Entry = SourceIdMap . GetOrCreateValue ( FileName ) ; if ( Entry . getValue ( ) ) return Entry . getValue ( ) ; unsigned SrcId = SourceIdMap . size ( ) ; Entry . setValue ( SrcId ) ; OutStreamer . EmitDwarfFileDirective ( SrcId , <STR_LIT> , Entry . getKey ( ) ) ;


<s> return MachineJumpTableInfo :: EK_Custom32 ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;

return DecodeDPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> while ( m != <NUM_LIT> ) { c = __builtin_clzl ( m ) ; t = __X << ( p - c ) ; m ^= ( mask >> c ) ; result |= ( t & ( mask >> c ) ) ; p ++ ; } return ( result ) ;


<s> if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = layout . sp_minus_fp - layout . locals_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - layout . locals_size ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) result = - layout . fp_minus_ap ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) result = - ( layout . sp_minus_fp + layout . fp_minus_ap ) ; else gcc_unreachable ( ) ;


<s> if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } if ( hasFP ( MF ) ) { for ( auto & I = LastFrameDestroy ; I != MBBI ; ++ I ) { if ( I -> mayLoad ( ) && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register DestReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == FPReg ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( SPReg , true ) , - FPOffset ) ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; break ; } } } }

const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ;


<s> condition = ix86_expand_fp_compare ( code , op1 , op2 , tmp ) ; i = emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition , target1 , target2 ) ) ) ;

if ( split_branch_probability >= <NUM_LIT> ) add_int_reg_note ( i , REG_BR_PROB , split_branch_probability ) ;


<s> if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ;

if ( type == float128_type_node || type == float64x_type_node ) return NULL ;


<s> return Kind == Immediate && Imm . Type != ImmTyNone ;


<s> NumVGPR ( <NUM_LIT> ) , NumSGPR ( <NUM_LIT> ) , Priority ( <NUM_LIT> ) , FloatMode ( <NUM_LIT> ) , Priv ( <NUM_LIT> ) , DX10Clamp ( <NUM_LIT> ) , DebugMode ( <NUM_LIT> ) , IEEEMode ( <NUM_LIT> ) , ScratchSize ( <NUM_LIT> ) , CodeLen ( <NUM_LIT> ) {


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> if ( Opcode == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; else if ( Opcode == <STR_LIT> && canTreatAsByteVector ( Op . getValueType ( ) ) ) { SmallVector < int , <STR_LIT> > Bytes ; getVPermMask ( cast < ShuffleVectorSDNode > ( Op ) , Bytes ) ; int First ; if ( ! getShuffleInput ( Bytes , Index * BytesPerElement , BytesPerElement , First ) ) break ; if ( First < <NUM_LIT> ) return DAG . getUNDEF ( ResVT ) ; unsigned Byte = unsigned ( First ) % Bytes . size ( ) ; if ( Byte % BytesPerElement != <NUM_LIT> ) break ; Index = Byte / BytesPerElement ; Op = Op . getOperand ( unsigned ( First ) / Bytes . size ( ) ) ; Force = true ; } else if ( Opcode == <STR_LIT> && canTreatAsByteVector ( Op . getValueType ( ) ) ) { EVT OpVT = Op . getValueType ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( OpBytesPerElement < BytesPerElement ) break ; unsigned End = ( Index + <NUM_LIT> ) * BytesPerElement ; if ( End % OpBytesPerElement != <NUM_LIT> ) break ; Op = Op . getOperand ( End / OpBytesPerElement - <NUM_LIT> ) ; if ( ! Op . getValueType ( ) . isInteger ( ) ) { EVT VT = <STR_LIT> ( Op . getValueType ( ) . getSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; DCI . AddToWorklist ( Op . getNode ( ) ) ; } EVT VT = <STR_LIT> ( ResVT . getSizeInBits ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; if ( VT != ResVT ) { DCI . AddToWorklist ( Op . getNode ( ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , ResVT , Op ) ; } return Op ; } else if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && canTreatAsByteVector ( Op . getValueType ( ) ) && canTreatAsByteVector ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { EVT ExtVT = Op . getValueType ( ) ; EVT OpVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned ExtBytesPerElement = ExtVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned OpBytesPerElement = OpVT . getVectorElementType ( ) . getStoreSize ( ) ; unsigned Byte = Index * BytesPerElement ; unsigned SubByte = Byte % ExtBytesPerElement ; unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement ;

if ( SubByte < MinSubByte || SubByte + BytesPerElement > ExtBytesPerElement ) break ;


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } assert ( TBB && Cond [ <NUM_LIT> ] . isImm ( ) ) ; unsigned Opcode = getBranchOpcode ( static_cast < BranchPredicate > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; if ( ! FBB ) { BuildMI ( & MBB , DL , get ( Opcode ) ) . addMBB ( TBB ) ; return <NUM_LIT> ;


<s> } } break ; } if ( V . getOpcode ( ) == <STR_LIT> && VT . isInteger ( ) ) if ( SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast ( DL , VT , V . getOperand ( <NUM_LIT> ) , BroadcastIdx , Subtarget , DAG ) ) return TruncBroadcast ; MVT BroadcastVT = VT ; SDValue BC = peekThroughBitcasts ( V ) ; if ( V . getOpcode ( ) == <STR_LIT> || ( V . getOpcode ( ) == <STR_LIT> && BroadcastIdx == <NUM_LIT> ) ) { V = V . getOperand ( BroadcastIdx ) ; if ( ! BroadcastFromReg && ! isShuffleFoldableLoad ( V ) ) return SDValue ( ) ; } else if ( MayFoldLoad ( BC ) && ! cast < LoadSDNode > ( BC ) -> isVolatile ( ) ) { if ( ! Subtarget . is64Bit ( ) && VT . getScalarType ( ) == <STR_LIT> ) { BroadcastVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; Opcode = ( BroadcastVT . is128BitVector ( ) ? <STR_LIT> : Opcode ) ; } LoadSDNode * Ld = cast < LoadSDNode > ( BC ) ; SDValue BaseAddr = Ld -> getOperand ( <NUM_LIT> ) ; EVT SVT = BroadcastVT . getScalarType ( ) ; unsigned Offset = BroadcastIdx * SVT . getStoreSize ( ) ; SDValue NewAddr = DAG . getMemBasePlusOffset ( BaseAddr , Offset , DL ) ; V = DAG . getLoad ( SVT , DL , Ld -> getChain ( ) , NewAddr , DAG . getMachineFunction ( ) . getMachineMemOperand ( Ld -> getMemOperand ( ) , Offset , SVT . getStoreSize ( ) ) ) ; if ( Ld -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( Ld , <NUM_LIT> ) , SDValue ( V . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( Ld , <NUM_LIT> ) , SDValue ( V . getNode ( ) , <NUM_LIT> ) ) ; } } else if ( ! BroadcastFromReg ) { return SDValue ( ) ; } else if ( BroadcastIdx != <NUM_LIT> ) { if ( ! VT . is256BitVector ( ) && ! VT . is512BitVector ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( ( ( BroadcastIdx * EltSize ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; MVT ExtVT = <STR_LIT> ( VT . getScalarType ( ) , <NUM_LIT> / EltSize ) ; V = DAG . getNode ( <STR_LIT> , DL , ExtVT , V , DAG . getIntPtrConstant ( BroadcastIdx , DL ) ) ; }

if ( Opcode == <STR_LIT> && ! V . getValueType ( ) . isVector ( ) ) V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V ) ) ;


<s> if ( P . first == <ISA_LIT>InstrInfo :: BT_None ) return false ; if ( ( P . first != <ISA_LIT>InstrInfo :: BT_Uncond ) && ( P . first != <ISA_LIT>InstrInfo :: BT_NoBranch ) ) { HasMultipleSuccs = true ; RegDU . addLiveOut ( Pred , Succ ) ; } BrMap [ & Pred ] = P . second ;


<s> if ( Subtarget -> isTargetELF ( ) ) return LowerELFGlobalTLSAddress ( Op , DAG ) ; if ( Subtarget -> isTargetWindows ( ) ) return LowerWindowsGlobalTLSAddress ( Op , DAG ) ;


<s> return RegisterAggr ( PRI ) . insert ( RA ) . hasCoverOf ( RB ) ;


<s> bool IsOptimizingSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool HasFastHOps = Subtarget . hasFastHorizontalOps ( ) ;

return ! IsSingleSource || IsOptimizingSize || HasFastHOps ;


<s> if ( mode == CCV2mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % <NUM_LIT> == <NUM_LIT> ) ; if ( mode == CCV4mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % <NUM_LIT> == <NUM_LIT> ) ; if ( mode == CCmode ) return ISA_HAS_8CC ? ST_REG_P ( regno ) : regno == FPSW_REGNUM ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) && mode != CCFmode ) return ( ( regno - GP_REG_FIRST ) & <NUM_LIT> ) == <NUM_LIT> || size <= UNITS_PER_WORD ;

if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == <NUM_LIT> || ( MIN_FPRS_PER_FMT == <NUM_LIT> && size <= UNITS_PER_FPREG ) ) ) {


<s> BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , LoReg ) . addImm ( Imm . trunc ( <NUM_LIT> ) . getZExtValue ( ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , HiReg ) . addImm ( Imm . ashr ( <NUM_LIT> ) . getZExtValue ( ) ) ;

BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( LoReg ) . addImm ( <STR_LIT> ) . addReg ( HiReg ) . addImm ( <STR_LIT> ) ;


<s> MVT InSVT = InVT . getScalarType ( ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) return SDValue ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; unsigned NumPackedSignBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned NumPackedZeroBits = Subtarget . hasSSE41 ( ) ? NumPackedSignBits : <NUM_LIT> ; KnownBits Known ; DAG . computeKnownBits ( In , Known ) ; unsigned NumLeadingZeroBits = Known . countMinLeadingZeros ( ) ; if ( NumLeadingZeroBits >= ( InSVT . getSizeInBits ( ) - NumPackedZeroBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ;

if ( NumSignBits > ( InSVT . getSizeInBits ( ) - NumPackedSignBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ;


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : return SelectConstant ( N ) ; case <STR_LIT> : return SelectConstantFP ( N ) ; case <STR_LIT> : return SelectAdd ( N ) ; case <STR_LIT> : return SelectSHL ( N ) ; case <STR_LIT> : return SelectLoad ( N ) ; case <STR_LIT> :


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI ) : MCInstPrinter ( MAI ) {


<s> static const uint16_t ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned NumArgRegs = array_lengthof ( ArgRegs ) ;

unsigned Reg = State . AllocateReg ( ArgRegs , NumArgRegs ) ;


<s> printNamedBit ( MI , OpNo , O , <STR_LIT> ) ;


<s> return output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ) ;


<s> if ( ! HARD_REGISTER_NUM_P ( regno ) ) { if ( ! strict_p ) return true ; if ( ! reg_renumber ) return false ; regno = reg_renumber [ regno ] ; }

return ( GP_REGNUM_P ( regno ) || regno == SP_REGNUM || regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) ;


<s> static inline unsigned char getAM3Offset ( unsigned AM3Opc ) {


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_LONGJMP ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> bool hasMed3_16 ( ) const { return getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 ;


return Kind == Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ;


<s> return ( __m128i ) __builtin_ia32_compressqi128_mask ( ( __v16qi ) __B , ( __v16qi ) _mm_setzero_si128 ( ) , ( __mmask16 ) __A ) ;


<s> Instruction * Induction = nullptr ; if ( ! match ( V , m_ICmp ( Pred , m_Instruction ( Induction ) , m_Instruction ( Shuffle ) ) ) || Pred != ICmpInst :: ICMP_ULE || ! L -> isLoopInvariant ( Shuffle ) ) return false ; Instruction * Insert = nullptr ; if ( ! match ( Shuffle , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * BECount = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( BECount ) , m_Zero ( ) ) ) ) return false ; Value * TripCount = nullptr ; if ( ! match ( BECount , m_Add ( m_Value ( TripCount ) , m_AllOnes ( ) ) ) ) return false ; if ( TripCount != NumElements ) return false ; Instruction * BroadcastSplat = nullptr ; Constant * Const = nullptr ; if ( ! match ( Induction , m_Add ( m_Instruction ( BroadcastSplat ) , m_Constant ( Const ) ) ) ) return false ; if ( auto * CDS = dyn_cast < ConstantDataSequential > ( Const ) ) { for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) { if ( CDS -> getElementAsInteger ( i ) != i ) return false ; } } else return false ; if ( ! match ( BroadcastSplat , m_ShuffleVector ( m_Instruction ( Insert ) , m_Undef ( ) , m_Zero ( ) ) ) ) return false ; Instruction * IV = nullptr ; if ( ! match ( Insert , m_InsertElement ( m_Undef ( ) , m_Instruction ( IV ) , m_Zero ( ) ) ) ) return false ; auto * Phi = dyn_cast < PHINode > ( IV ) ; if ( ! Phi ) return false ; Value * OnEntry = Phi -> getIncomingValueForBlock ( L -> getLoopPreheader ( ) ) ; if ( ! match ( OnEntry , m_Zero ( ) ) ) return false ; Value * InLoop = Phi -> getIncomingValueForBlock ( L -> getLoopLatch ( ) ) ; unsigned Lanes = cast < VectorType > ( Insert -> getType ( ) ) -> getNumElements ( ) ; Instruction * LHS = nullptr ; if ( ! match ( InLoop , m_Add ( m_Instruction ( LHS ) , m_SpecificInt ( Lanes ) ) ) ) return false ;


<s> switch ( CC ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> Windows<ISA_LIT>AsmBackend ( const Target & T , bool is64Bit , const MCSubtargetInfo & STI ) : <ISA_LIT>AsmBackend ( T , STI ) , Is64Bit ( is64Bit ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> case BRIG_ATOMIC_MAX : O << <STR_LIT> ; break ; case BRIG_ATOMIC_MIN : O << <STR_LIT> ; break ; case BRIG_ATOMIC_OR : O << <STR_LIT> ; break ; case BRIG_ATOMIC_ST : O << <STR_LIT> ; break ; case BRIG_ATOMIC_SUB : O << <STR_LIT> ; break ; case BRIG_ATOMIC_WRAPDEC : O << <STR_LIT> ; break ; case BRIG_ATOMIC_WRAPINC : O << <STR_LIT> ; break ; case BRIG_ATOMIC_XOR : O << <STR_LIT> ; break ; case BRIG_ATOMIC_WAIT_EQ : O << <STR_LIT> ; break ; case BRIG_ATOMIC_WAIT_NE : O << <STR_LIT> ; break ; case BRIG_ATOMIC_WAIT_LT : O << <STR_LIT> ; break ; case BRIG_ATOMIC_WAIT_GTE : O << <STR_LIT> ; break ; case BRIG_ATOMIC_WAITTIMEOUT_EQ : O << <STR_LIT> ;


<s> const FunctionType * FTy = Func -> getFunctionType ( ) ; const AttrListPtr & Attrs = Func -> getAttributes ( ) ; if ( ! Attrs . isEmpty ( ) && ! Func -> isVarArg ( ) ) { unsigned InRegCount = <NUM_LIT> ; unsigned Idx = <NUM_LIT> ; for ( FunctionType :: param_iterator I = FTy -> param_begin ( ) , E = FTy -> param_end ( ) ; I != E ; ++ I , ++ Idx ) if ( Attrs . paramHasAttr ( Idx , Attribute :: InReg ) ) InRegCount += ( TD -> getTypeSizeInBits ( * I ) + <NUM_LIT> ) / <NUM_LIT> ; if ( InRegCount > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } break ; } case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: Fast : NestReg = <STR_LIT> ; break ; } SDValue OutChains [ <NUM_LIT> ] ; SDValue Addr , Disp ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Disp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPtr , Addr ) ; const unsigned char MOV32ri = <NUM_LIT> ; const unsigned char N86Reg = RegInfo -> get<ISA_LIT>RegNum ( NestReg ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( MOV32ri | N86Reg , <STR_LIT> ) , Trmp , TrmpAddr , <NUM_LIT> , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Nest , Addr , TrmpAddr , <NUM_LIT> , false , false , <NUM_LIT> ) ; const unsigned char JMP = <NUM_LIT> ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( JMP , <STR_LIT> ) , Addr , TrmpAddr , <NUM_LIT> , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Disp , Addr , TrmpAddr , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Ops [ ] = { Trmp , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains , <NUM_LIT> ) } ;

return DAG . getMergeValues ( Ops , <NUM_LIT> , dl ) ;


<s> void markPhysRegUsed ( unsigned PhysReg ) override { MIB . addDef ( PhysReg , RegState :: Implicit ) ;


<s> <ISA_LIT>ELFDynamic :: <ISA_LIT>ELFDynamic ( const GNULDBackend & pParent , const LinkerConfig & pConfig ) : ELFDynamic ( pParent , pConfig ) {


<s> inline const MachineInstrBuilder & addLeaRegOffset ( const MachineInstrBuilder & MIB , unsigned Reg , bool isKill , int Offset ) { return addLeaOffset ( MIB . addReg ( Reg , getKillRegState ( isKill ) ) , Offset ) ;


<s> assert ( ( Subtarget -> isTargetAEABI ( ) || Subtarget -> isTargetAndroid ( ) ) && <STR_LIT> ) ; unsigned Opcode = Op -> getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = ( Opcode == <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC = getDivRemLibcall ( Op . getNode ( ) , VT . getSimpleVT ( ) . SimpleTy ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args = getDivRemArgList ( Op . getNode ( ) , DAG . getContext ( ) ) ; SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ;


<s> SDValue FakeOp ; std :: vector < SDValue > Ops ( Node -> op_begin ( ) , Node -> op_end ( ) ) ; if ( Opcode == <STR_LIT> ) { int OperandIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_W ) } ; int NegIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_neg_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_neg_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_neg_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_neg_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_neg_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_neg_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_neg_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_neg_W ) } ; int AbsIdx [ ] = { TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_abs_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_abs_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_abs_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src0_abs_W ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_abs_X ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_abs_Y ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_abs_Z ) , TII -> getOperandIdx ( Opcode , <STR_LIT> :: src1_abs_W ) } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( OperandIdx [ i ] < <NUM_LIT> ) return Node ; SDValue & Src = Ops [ OperandIdx [ i ] - <NUM_LIT> ] ; SDValue & Neg = Ops [ NegIdx [ i ] - <NUM_LIT> ] ; SDValue & Abs = Ops [ AbsIdx [ i ] - <NUM_LIT> ] ; bool HasDst = TII -> getOperandIdx ( Opcode , <STR_LIT> :: dst ) > - <NUM_LIT> ; int SelIdx = TII -> getSelIdx ( Opcode , OperandIdx [ i ] ) ; if ( HasDst ) SelIdx -- ; SDValue & Sel = ( SelIdx > - <NUM_LIT> ) ? Ops [ SelIdx ] : FakeOp ; if ( FoldOperand ( Node , i , Src , Neg , Abs , Sel , FakeOp , DAG ) ) return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ;


<s> MVT PromoteTo = EVT ( VT ) . changeVectorElementTypeToInteger ( ) . getSimpleVT ( ) ; setOperationPromotedToType ( <STR_LIT> , VT , PromoteTo ) ; setOperationPromotedToType ( <STR_LIT> , VT , PromoteTo ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget -> hasFullFP16 ( ) ) ) setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> const TargetRegisterClass * RC = static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) . in<ISA_LIT>16Mode ( ) ? & <STR_LIT> : static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ? & <STR_LIT> : & <STR_LIT> ;

return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ;


<s> for ( ++ A ; CurrentIteration < MaxInstructions && A != E ; ++ A ) { if ( A -> isDebugInstr ( ) ) continue ; if ( Pred ( & * A ) ) return & * A ; for ( MCRegister Reg : NonModifiableRegs ) { if ( A -> modifiesRegister ( Reg , TRI ) ) return nullptr ; } ++ CurrentIteration ; }


<s> if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeEven [ i ] ) ) MatchEvenMask = false ; if ( ! isUndefOrEqual ( Mask [ i ] , MaskToOptimizeOdd [ i ] ) ) MatchOddMask = false ; } if ( ! MatchEvenMask && ! MatchOddMask ) return SDValue ( ) ; SDValue UndefNode = DAG . getNode ( <STR_LIT> , dl , VT ) ; SDValue Op0 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = SVOp -> getOperand ( <NUM_LIT> ) ; if ( MatchEvenMask ) { static const int ShiftRightMask [ ] = { - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> } ; Op1 = DAG . getVectorShuffle ( VT , dl , Op1 , UndefNode , ShiftRightMask ) ; } else {

static const int ShiftLeftMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ;


<s> const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = VRC -> getSize ( ) / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) {

unsigned SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> const MachineOperand & HiOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & LoOp = MI -> getOperand ( <NUM_LIT> ) ; assert ( DstOp . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; mapRegs ( { DstOp . getReg ( ) , <STR_LIT> } , { HiOp . getReg ( ) , HiOp . getSubReg ( ) } ) ; mapRegs ( { DstOp . getReg ( ) , <STR_LIT> } , { LoOp . getReg ( ) , LoOp . getSubReg ( ) } ) ; return true ; } case <STR_LIT> : { const MachineOperand & A = MI -> getOperand ( <NUM_LIT> ) ; if ( ! A . isImm ( ) || A . getImm ( ) != <NUM_LIT> ) return false ; } case <STR_LIT> : { const MachineOperand & DstOp = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & SrcOp = MI -> getOperand ( <NUM_LIT> ) ; mapRegs ( { DstOp . getReg ( ) , DstOp . getSubReg ( ) } , { SrcOp . getReg ( ) , SrcOp . getSubReg ( ) } ) ; return true ;


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isImm ( ) ) { OS << formatHex ( <NUM_LIT> | Op . getImm ( ) ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print ( OS , & MAI ) ; }


<s> } else if ( VPTBlock . instrInVPTBlock ( ) ) { VCC = VPTBlock . getVPTPred ( ) ; VPTBlock . advanceVPTState ( ) ; } const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; MCInst :: iterator CCI = MI . begin ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ CCI ) { if ( OpInfo [ i ] . isPredicate ( ) || CCI == MI . end ( ) ) break ; } if ( <ISA_LIT>Insts [ MI . getOpcode ( ) ] . isPredicable ( ) ) { CCI = MI . insert ( CCI , MCOperand :: createImm ( CC ) ) ; ++ CCI ; if ( CC == <STR_LIT> ) MI . insert ( CCI , MCOperand :: createReg ( <NUM_LIT> ) ) ; else MI . insert ( CCI , MCOperand :: createReg ( <STR_LIT> ) ) ; } else if ( CC != <STR_LIT> ) { Check ( S , SoftFail ) ; } MCInst :: iterator VCCI = MI . begin ( ) ; unsigned VCCPos ; for ( VCCPos = <NUM_LIT> ; VCCPos < NumOps ; ++ VCCPos , ++ VCCI ) { if ( <STR_LIT> ( OpInfo [ VCCPos ] . OperandType ) || VCCI == MI . end ( ) ) break ; } if ( isVectorPredicable ( MI . getOpcode ( ) ) ) { VCCI = MI . insert ( VCCI , MCOperand :: createImm ( VCC ) ) ; ++ VCCI ;

if ( VCC == <STR_LIT> ) VCCI = MI . insert ( VCCI , MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> default : break ; case <STR_LIT> : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI ) ; case <STR_LIT> : return OptimizeConditionalInDecrement ( N , DAG ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : return PerformZExtCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG ) ; case <STR_LIT> :


<s> AssemblerOptions . push_back ( llvm :: make_unique < <ISA_LIT>AssemblerOptions > ( getSTI ( ) . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; CurrentFn = nullptr ; IsPicEnabled = getContext ( ) . getObjectFileInfo ( ) -> isPositionIndependent ( ) ; IsCpRestoreSet = false ; CpRestoreOffset = - <NUM_LIT> ; const Triple & TheTriple = sti . getTargetTriple ( ) ; IsLittleEndian = TheTriple . isLittleEndian ( ) ; if ( getSTI ( ) . getCPU ( ) == <STR_LIT> && inMicro<ISA_LIT>Mode ( ) ) report_fatal_error ( <STR_LIT> , false ) ;

if ( ! isABI_O32 ( ) && inMicro<ISA_LIT>Mode ( ) ) report_fatal_error ( <STR_LIT> , false ) ;


<s> case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Op = <STR_LIT> ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) Op = <STR_LIT> ; bool writeback = ( P == <NUM_LIT> ) || ( W == <NUM_LIT> ) ; unsigned idx_mode = <NUM_LIT> ; if ( P && writeback ) idx_mode = <STR_LIT> ; else if ( ! P && writeback ) idx_mode = <STR_LIT> ; if ( writeback && ( Rn == <NUM_LIT> || Rn == Rt ) ) S = MCDisassembler :: SoftFail ; if ( reg ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Opc = <STR_LIT> ; switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; default : return MCDisassembler :: Fail ; } unsigned amt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Opc == <STR_LIT> && amt == <NUM_LIT> ) Opc = <STR_LIT> ; unsigned imm = <STR_LIT> ( Op , amt , Opc , idx_mode ) ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; } else { Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; unsigned tmp = <STR_LIT> ( Op , imm , <STR_LIT> , idx_mode ) ; Inst . addOperand ( MCOperand :: CreateImm ( tmp ) ) ; } if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> PrevState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_RBRAC : case IES_INTEGER : case IES_RPAREN : State = IES_PLUS ; IC . pushOperator ( IC_PLUS ) ; CurType . Length = <NUM_LIT> ; CurType . Size = CurType . ElementSize ;


<s> static bool m68k_jump_table_ref_p ( rtx x ) { if ( GET_CODE ( x ) != LABEL_REF ) return false ;

rtx_insn * insn = as_a < rtx_insn * > ( XEXP ( x , <NUM_LIT> ) ) ;


<s> LDSSize = YamlMFI . LDSSize ; IsEntryFunction = YamlMFI . IsEntryFunction ; NoSignedZerosFPMath = YamlMFI . NoSignedZerosFPMath ; MemoryBound = YamlMFI . MemoryBound ;


<s> Register getGlobalBaseReg ( ) const { return GlobalBaseReg ;


<s> <ISA_LIT>PostRASchedStrategy :: ~ <ISA_LIT>PostRASchedStrategy ( ) {


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> <ISA_LIT>CC = <STR_LIT> ; SDValue CompareFlag ; if ( LHS . getValueType ( ) . isInteger ( ) ) { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; <ISA_LIT>CC = DAGIntCCTo<ISA_LIT>CC ( CC ) ; } else {


<s> int findSubst ( const <ISA_LIT>LibFunc :: Param & P ) const {

for ( unsigned I = <NUM_LIT> ; I < Str . size ( ) ; ++ I ) {


<s> return get ( MI . getOpcode ( ) ) . TSFlags & <STR_LIT> ;


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; bool CanFoldLoad = false ; if ( MayFoldVectorLoad ( V2 ) ) CanFoldLoad = true ; else if ( MayFoldVectorLoad ( V1 ) && MayFoldIntoStore ( Op ) ) CanFoldLoad = true ;

ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ;


<s> } MachineInstr * HeaderPhi = HeaderPHIBuilder ; MachineInstr * <ISA_LIT>IFBREAK = BuildMI ( * ( MF ) , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) , BackEdgeReg ) . addReg ( DstReg ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * <ISA_LIT>LOOP = BuildMI ( * ( MF ) , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( BackEdgeReg ) . addMBB ( LoopEntry ) ; LoopEntry -> insert ( LoopEntry -> begin ( ) , HeaderPhi ) ; LoopEnd -> erase ( TI ) ; LoopEnd -> insert ( LoopEnd -> end ( ) , <ISA_LIT>IFBREAK ) ; LoopEnd -> insert ( LoopEnd -> end ( ) , <ISA_LIT>LOOP ) ; }


<s> const TargetRegisterClass * getRegClassForTypeOnBank ( LLT Ty , const RegisterBank & Bank , const MachineRegisterInfo & MRI ) const { return getRegClassForSizeOnBank ( Ty . getSizeInBits ( ) , Bank , MRI ) ;


<s> MachineInstr & MI = * I ; int Off = Offset ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) {


<s> static SDValue BuildSplatI ( int Val , unsigned SplatSize , EVT VT , SelectionDAG & DAG , SDLoc dl ) { assert ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> && <STR_LIT> ) ; static const MVT VTys [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; EVT ReqVT = VT != <STR_LIT> ? VT : VTys [ SplatSize - <NUM_LIT> ] ; if ( Val == - <NUM_LIT> ) SplatSize = <NUM_LIT> ; EVT CanonicalVT = VTys [ SplatSize - <NUM_LIT> ] ; SDValue Elt = DAG . getConstant ( Val , dl , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( CanonicalVT . getVectorNumElements ( ) , Elt ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , ReqVT , Res ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>_32MCCodeEmitter ( const Target & , TargetMachine & TM , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( TM , Ctx , false ) ;


<s> fputs ( <STR_LIT> , file ) ; switch ( size ) { case <NUM_LIT> : break ; case <NUM_LIT> :


<s> static MCSymbol * getPICLabel ( const char * Prefix , unsigned FunctionNumber , unsigned LabelId , MCContext & Ctx ) {

MCSymbol * Label = Ctx . GetOrCreateSymbol ( Twine ( Prefix ) + <STR_LIT> + Twine ( FunctionNumber ) + <STR_LIT> + Twine ( LabelId ) ) ;


<s> OutStreamer . EmitRawText ( Twine ( <STR_LIT> ) ) ;


<s> auto NEG_RCP_LO = B . buildSub ( S32 , Zero , RCP_LO ) ; auto CmpRcpHiZero = B . buildICmp ( CmpInst :: ICMP_EQ , S1 , RCP_HI , Zero ) ; auto ABS_RCP_LO = B . buildSelect ( S32 , CmpRcpHiZero , NEG_RCP_LO , RCP_LO ) ; auto E = B . buildUMulH ( S32 , ABS_RCP_LO , RCP ) ; auto RCP_A_E = B . buildAdd ( S32 , RCP , E ) ; auto RCP_S_E = B . buildSub ( S32 , RCP , E ) ; auto Tmp0 = B . buildSelect ( S32 , CmpRcpHiZero , RCP_A_E , RCP_S_E ) ; auto Quotient = B . buildUMulH ( S32 , Tmp0 , Num ) ; auto Num_S_Remainder = B . buildMul ( S32 , Quotient , Den ) ; auto Remainder = B . buildSub ( S32 , Num , Num_S_Remainder ) ; auto Remainder_GE_Den = B . buildICmp ( CmpInst :: ICMP_UGE , S1 , Remainder , Den ) ; auto Remainder_GE_Zero = B . buildICmp ( CmpInst :: ICMP_UGE , S1 , Num , Num_S_Remainder ) ; auto Tmp1 = B . buildAnd ( S1 , Remainder_GE_Den , Remainder_GE_Zero ) ; auto One = B . buildConstant ( S32 , <NUM_LIT> ) ; auto Quotient_A_One = B . buildAdd ( S32 , Quotient , One ) ; auto Quotient_S_One = B . buildSub ( S32 , Quotient , One ) ; auto Div = B . buildSelect ( S32 , Tmp1 , Quotient , Quotient_A_One ) ; if ( IsRem ) { Div = B . buildSelect ( S32 , Remainder_GE_Zero , Div , Quotient_S_One ) ; auto Remainder_S_Den = B . buildSub ( S32 , Remainder , Den ) ; auto Remainder_A_Den = B . buildAdd ( S32 , Remainder , Den ) ; auto Rem = B . buildSelect ( S32 , Tmp1 , Remainder_S_Den , Remainder ) ; B . buildSelect ( DstReg , Remainder_GE_Zero , Rem , Remainder_A_Den ) ; } else { B . buildSelect ( DstReg , Remainder_GE_Zero , Div , Quotient_S_One ) ; }


<s> else this_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( ! ( delta >= - <NUM_LIT> && delta <= <NUM_LIT> ) ) { addend = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( addend , GEN_INT ( delta ) ) ; } else addend = GEN_INT ( delta ) ; if ( TARGET_32BIT ) emit_insn ( gen_addsi3 ( this_rtx , this_rtx , addend ) ) ; else emit_insn ( gen_adddi3 ( this_rtx , this_rtx , addend ) ) ; if ( vcall_offset ) { rtx tmp ; tmp = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( ! ( vcall_offset >= - <NUM_LIT> && vcall_offset <= <NUM_LIT> ) ) { addend = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( addend , GEN_INT ( vcall_offset ) ) ; } else addend = GEN_INT ( vcall_offset ) ; if ( TARGET_32BIT ) emit_insn ( gen_addsi3 ( tmp , tmp , addend ) ) ; else emit_insn ( gen_adddi3 ( tmp , tmp , addend ) ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; if ( TARGET_32BIT ) emit_insn ( gen_addsi3 ( this_rtx , this_rtx , tmp ) ) ; else emit_insn ( gen_adddi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) {


<s> SDLoc DL ( Op ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , SSFI ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , <STR_LIT> , MPI , Align ( <NUM_LIT> ) , MachineMemOperand :: MOStore ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , DL , Chain , StackSlot , MPI , Align ( <NUM_LIT> ) ) ; Chain = CWD . getValue ( <NUM_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ; SDValue LUT = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LUT , Shift ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; RetVal = DAG . getZExtOrTrunc ( RetVal , DL , VT ) ;

return DAG . getMergeValues ( { RetVal , Chain } , DL ) ;


<s> Filler ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , TII ( tm . getInstrInfo ( ) ) {


<s> EVT SatVT = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ;

if ( ( ResT == <STR_LIT> || ResT == <STR_LIT> ) && ( SatVT == <STR_LIT> || SatVT == <STR_LIT> ) ) return Op ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> } case <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo :: ALU_VEC_120_SCL_212 : { unsigned Cycles [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return Cycles [ Op ] ; } case <ISA_LIT>InstrInfo :: ALU_VEC_102_SCL_221 : {


<s> return std :: max ( LogAlign , internalKnownBits ( ) ) ;


<s> MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; const GlobalValue * FName = & MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } if ( ! MF . getTarget ( ) . isPositionIndependent ( ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; return ; } MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( ABI . IsN32 ( ) ) { const GlobalValue * FName = & MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } assert ( ABI . IsO32 ( ) ) ; MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> LDTLSCleanup ( ) : MachineFunctionPass ( ID ) {


<s> int64_t MaxArgOffset = <NUM_LIT> ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= <NUM_LIT> ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ;


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rt = getReg ( Decoder , <STR_LIT> , Rt ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: createReg ( Rt ) ) ; } Inst . addOperand ( MCOperand :: createReg ( Rt ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ;

Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ;


<s> bool <ISA_LIT>AsmParser :: needsExpansion ( MCInst & Inst ) { return false ;


if ( getOptLevel ( ) != CodeGenOpt :: None ) {


<s> int32_t a_field = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( a_field > <NUM_LIT> ) { a_field = - ( ( ~ a_field & <NUM_LIT> ) + <NUM_LIT> ) ; }

Inst . addOperand ( MCOperand :: createImm ( a_field ) ) ;


<s> unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool IsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SubReg = Is16BitOp ? <STR_LIT> : <STR_LIT> ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; BuildMI ( * MFI , MBBI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , InRegLEA ) ; MachineInstr * InsMI = BuildMI ( * MFI , MBBI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( InRegLEA , RegState :: Define , SubReg ) . addReg ( Src , getKillRegState ( IsKill ) ) ; MachineInstrBuilder MIB = BuildMI ( * MFI , MBBI , MI . getDebugLoc ( ) , get ( Opcode ) , OutRegLEA ) ; switch ( MIOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { unsigned ShAmt = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> << ShAmt ) . addReg ( InRegLEA , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; break ; } case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , <NUM_LIT> ) ; break ; case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Src2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill2 = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; unsigned InRegLEA2 = <NUM_LIT> ; MachineInstr * InsMI2 = nullptr ; if ( Src == Src2 ) { addRegReg ( MIB , InRegLEA , true , InRegLEA , false ) ; } else { if ( Subtarget . is64Bit ( ) ) InRegLEA2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; else InRegLEA2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , & * MIB , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , InRegLEA2 ) ; InsMI2 = BuildMI ( * MFI , & * MIB , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( InRegLEA2 , RegState :: Define , SubReg ) . addReg ( Src2 , getKillRegState ( IsKill2 ) ) ;

addRegReg ( MIB , InRegLEA , true , InRegLEA2 , true ) ;


<s> virtual ~ <ISA_LIT>Disassembler ( ) {


<s> SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ;

SDValue Ops [ ] = { VMask , Base , Scale , Index , Disp , Segment , Chain } ;


<s> generateInstSeq ( Chunk . getSExtValue ( ) , IsRV64 , MatSeq ) ; Cost += MatSeq . size ( ) ; }

return std :: max ( <NUM_LIT> , Cost ) ;


<s> unsigned bytes = <NUM_LIT> ; MachineBasicBlock :: iterator it = MI ; for ( ; cycles > <NUM_LIT> ; ) { it ++ ; assert ( it != MBB -> end ( ) && <STR_LIT> ) ; assert ( ! it -> isInlineAsm ( ) && <STR_LIT> ) ;


<s> if ( argc == <NUM_LIT> ) return NULL ; return argv [ argc - <NUM_LIT> ] ;


<s> if ( Subtarget -> hasSSE3 ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; } if ( Subtarget -> hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( Subtarget -> hasSSE41 ( ) ) { if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleAsInsertPS ( Op , V1 , V2 , Mask , DAG ) ) return V ; if ( ! isSingleSHUFPSMask ( Mask ) ) if ( SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BlendPerm ; } if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: NEONThumb2LoadStorePostEncoder ( const MCInst & MI , unsigned EncodedValue ) const { if ( isThumb2 ( ) ) { EncodedValue &= <NUM_LIT> ; EncodedValue |= <NUM_LIT> ;


<s> addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ;


<s> CostPair spillCosts ( <NUM_LIT> , <NUM_LIT> ) ; Root = new SCANode ( node , occupancyCosts , maxdisplacment , spillCosts , hascallfreepath ) ; Root -> yId = yamlId ++ ;

Nodes [ std :: make_pair ( node , occupancyCosts ) ] = Root ;


<s> bool avx_upper_reg_found = false ; note_stores ( insn , ix86_check_avx_upper_stores , & avx_upper_reg_found ) ; return avx_upper_reg_found ? AVX_U128_DIRTY : AVX_U128_CLEAN ; }


<s> DEBUG ( errs ( ) << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> << * MI ) ; MCE . processDebugLoc ( MI -> getDebugLoc ( ) , true ) ; ++ NumEmitted ; switch ( MI -> getOpcode ( ) ) { default : { emitWord ( getBinaryCodeForInstr ( * MI ) ) ; break ;


<s> for ( unsigned S = StallCycles ; S && Def != B && Defs != <NUM_LIT> ; -- S ) { if ( MI . isDebugInstr ( ) ) continue ; -- Def ; if ( Def -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) continue ;

if ( Def -> modifiesRegister ( Reg1 , TRI ) ) Defs |= <NUM_LIT> ;


<s> } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) ; } else { MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . add ( Pred [ <NUM_LIT> ] ) ; } return true ; } else if ( OpC == <STR_LIT> ) { if ( Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) { bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; MI . setDesc ( get ( Pred [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) , RegState :: Implicit ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) , RegState :: ImplicitDefine ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ; } else if ( Pred [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ; } else { MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . add ( Pred [ <NUM_LIT> ] ) . addMBB ( MBB ) ;


<s> int speci , regi ; gcc_assert ( REG_P ( op ) ) ; if ( ! canon_reg_names [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] ) { for ( regi = <NUM_LIT> ; regi < LAST_GP_REGNUM ; regi ++ ) for ( speci = <NUM_LIT> ; speci < <NUM_LIT> ; speci ++ ) { const int sz = ( speci == <NUM_LIT> ) ? <NUM_LIT> : ( ( speci == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( regi + sz ) > ( <NUM_LIT> * <NUM_LIT> ) ) continue ; const char * suffix = <STR_LIT> ; switch ( ( sz << <NUM_LIT> ) | ( regi % <NUM_LIT> ) ) { case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; case ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> : suffix = <STR_LIT> ; break ; default : continue ; } sprintf ( & canon_reg_names [ speci ] [ regi ] [ <NUM_LIT> ] , <STR_LIT> , regi / <NUM_LIT> , suffix ) ; } } switch ( GET_MODE_SIZE ( GET_MODE ( op ) ) ) {

case <NUM_LIT> : speci = <NUM_LIT> ; break ;


<s> if ( ! isAAPCS_ABI ) return TargetLoweringObjectFileELF :: getStaticDtorSection ( Priority ) ; if ( Priority == <NUM_LIT> ) return StaticDtorSection ; std :: string Name = std :: string ( <STR_LIT> ) + utostr ( Priority ) ; return getContext ( ) . getELFSection ( Name , ELF :: SHT_FINI_ARRAY , ELF :: SHF_ALLOC | ELF :: SHF_WRITE , SectionKind :: getDataRel ( ) ) ;


<s> MRI . setRegBank ( Tmp , RegBank ) ; MachineInstr & InsertInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_INSERT ) , Tmp ) . addReg ( DefReg ) . addReg ( I . getOperand ( Idx ) . getReg ( ) ) . addImm ( ( Idx - <NUM_LIT> ) * SrcSize ) ; DefReg = Tmp ; if ( ! select ( InsertInst ) ) return false ; } MachineInstr & CopyInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( DefReg ) ; if ( ! select ( CopyInst ) ) return false ;


<s> else if ( AM . BaseType == <STR_LIT> ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity += <NUM_LIT> ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ;

if ( AM . Disp && ( AM . Base . Reg . getNode ( ) || AM . IndexReg . getNode ( ) ) ) Complexity += <NUM_LIT> ;


<s> bool isUncondBranchOpcode ( int opc ) { return opc == <STR_LIT> ;


<s> for ( const CalleeSavedInfo & I : CSI ) { unsigned Reg = I . getReg ( ) ;

bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ;


<s> TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( T , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( T , create<ISA_LIT>ObjectTargetStreamer ) ;


<s> break ; case Match_Success : { Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; } case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; }


<s> else { if ( ! anchor_reg ) { anchor_reg = gen_rtx_REG ( Pmode , STACK_CLASH_SVE_CFA_REGNUM ) ; emit_insn ( gen_add3_insn ( anchor_reg , base_rtx , gen_int_mode ( fp_offset , Pmode ) ) ) ; } base_rtx = anchor_reg ; } offset -= fp_offset ; } mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; bool need_cfa_note_p = ( base_rtx != stack_pointer_rtx ) ; if ( ! aarch64_sve_mode_p ( mode ) && ( regno2 = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ) <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && known_eq ( GET_MODE_SIZE ( mode ) , cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine -> frame . reg_offset [ regno ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset += GET_MODE_SIZE ( mode ) ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; if ( aarch64_emit_cfi_for_reg_p ( regno2 ) ) { if ( need_cfa_note_p ) aarch64_add_cfa_expression ( insn , reg2 , stack_pointer_rtx , sp_offset + GET_MODE_SIZE ( mode ) ) ; else RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } regno = regno2 ; } else if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) { insn = emit_insn ( gen_aarch64_pred_mov ( mode , mem , ptrue , reg ) ) ; need_cfa_note_p = true ; }

else if ( aarch64_sve_mode_p ( mode ) ) insn = emit_insn ( gen_rtx_SET ( mem , reg ) ) ;


<s> if ( warn ) { if ( decl ) error ( <STR_LIT> <STR_LIT> , decl ) ; else error ( <STR_LIT> <STR_LIT> , type ) ; } return <NUM_LIT> ; } return <NUM_LIT> ; } if ( ! decl ) return <NUM_LIT> ; cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && ( target_opts_for_fn ( target -> decl ) -> x_ix86_fpmath & FPMATH_SSE ) && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { cgraph_local_info * i = & target -> local ; if ( i && i -> local && i -> can_change_signature ) { if ( ! TARGET_SSE && warn ) { error ( <STR_LIT> <STR_LIT> , decl ) ; return <NUM_LIT> ; } return TARGET_SSE2_P ( target_opts_for_fn ( target -> decl ) -> x_ix86_isa_flags ) ? <NUM_LIT> : <NUM_LIT> ;


<s> bool <ISA_LIT>AsmParser :: validateMFMA ( const MCInst & Inst , const OperandVector & Operands ) { const unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & Desc = MII . get ( Opc ) ; if ( ( Desc . TSFlags & <STR_LIT> ) == <NUM_LIT> ) return true ; const int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( Src2Idx == - <NUM_LIT> ) return true ; const MCOperand & Src2 = Inst . getOperand ( Src2Idx ) ; if ( ! Src2 . isReg ( ) ) return true ; MCRegister Src2Reg = Src2 . getReg ( ) ; MCRegister DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Src2Reg == DstReg ) return true ; const MCRegisterInfo * TRI = getContext ( ) . getRegisterInfo ( ) ; if ( TRI -> getRegClass ( Desc . OpInfo [ <NUM_LIT> ] . RegClass ) . getSizeInBits ( ) <= <NUM_LIT> ) return true ;

if ( TRI -> regsOverlap ( Src2Reg , DstReg ) ) {


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; SeparatorString = <STR_LIT> ; AlignmentIsInBytes = false ; UsesELFSectionDirectiveForBSS = true ; UseIntegratedAssembler = true ;


<s> else { SDValue C63 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue LL = Op . getOperand ( <NUM_LIT> ) ; SDValue RL = Op . getOperand ( <NUM_LIT> ) ; SDValue LH = DAG . getNode ( <STR_LIT> , DL , VT , LL , C63 ) ; SDValue RH = DAG . getNode ( <STR_LIT> , DL , VT , RL , C63 ) ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , LL , RL , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SDValue NegLLTimesRH = DAG . getNode ( <STR_LIT> , DL , VT , LL , RH ) ; SDValue NegLHTimesRL = DAG . getNode ( <STR_LIT> , DL , VT , LH , RL ) ; SDValue NegSum = DAG . getNode ( <STR_LIT> , DL , VT , NegLLTimesRH , NegLHTimesRL ) ; Ops [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Ops [ <NUM_LIT> ] , NegSum ) ; } return DAG . getMergeValues ( Ops , DL ) ;


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> return ( __m128i ) __builtin_ia32_vpmultishiftqb128_mask ( ( __v16qi ) __X , ( __v16qi ) __Y , ( __v16qi ) _mm_setzero_si128 ( ) , ( __mmask16 ) __M ) ;


<s> if ( Register :: isVirtualRegister ( TrueReg ) ) { DefMI = MRI -> getVRegDef ( TrueReg ) ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { OpNoForForwarding = i ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) break ; } } } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; bool IsVFReg = ( MI . getNumOperands ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ? isVFRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : false ; if ( ! ConvertibleImmForm && ! instrHasImmForm ( Opc , IsVFReg , III , true ) ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { Register Reg = MI . getOperand ( i ) . getReg ( ) ; MachineInstr * DefMI = getDefMIPostRA ( Reg , MI , SeenIntermediateUse ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Target32 ( The<ISA_LIT>_32Target ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Target64 ( The<ISA_LIT>_64Target ) ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { if ( get<ISA_LIT>Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( createInsertDivideCheckPass ( ) ) ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ;

return MI -> getDesc ( ) . mayLoad ( ) && hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ;


<s> return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask1 ) ; In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask2 ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getBitcast ( VT , In ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; OpLo = DAG . getVectorShuffle ( <STR_LIT> , DL , OpLo , OpLo , ShufMask1 ) ; OpHi = DAG . getVectorShuffle ( <STR_LIT> , DL , OpHi , OpHi , ShufMask1 ) ;


<s> rtx tilepro_simd_int ( rtx num , machine_mode mode ) { HOST_WIDE_INT n = <NUM_LIT> ; gcc_assert ( CONST_INT_P ( num ) ) ; n = INTVAL ( num ) ; switch ( mode ) { case E_QImode : n = <NUM_LIT> * ( n & <NUM_LIT> ) ; break ; case E_HImode : n = <NUM_LIT> * ( n & <NUM_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateReg ( getGPRMM16Reg ( ) ) ) ;


<s> assert ( ( <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) || <STR_LIT> == N -> getOpcode ( ) ) && <STR_LIT> ) ; if ( SDValue V = combineHorizOpWithShuffle ( N , DAG , Subtarget ) ) return V ; return SDValue ( ) ;


<s> unsigned char <ISA_LIT>Subtarget :: classifyBlockAddressReference ( ) const { return <STR_LIT> ;


<s> EVT VT = Op . getValueType ( ) ; assert ( VT . isInteger ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; bool isSigned ; switch ( Op -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIV_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIV_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UREM_I128 ; break ; case <STR_LIT> : isSigned = true ; LC = RTLIB :: SDIVREM_I128 ; break ; case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get ( ArgTy , <NUM_LIT> ) ;


<s> case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( const SDValue & V : PN -> ops ( ) ) { if ( ! ToPromote . count ( V . getNode ( ) ) && V . getValueType ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V ) ) { SDValue ReplOpOps [ ] = { ISR . getOperand ( <NUM_LIT> ) , V , ISR . getOperand ( <NUM_LIT> ) } ; SDNode * ReplOp = CurDAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , SDLoc ( V ) , ISR . getNode ( ) -> getVTList ( ) , ReplOpOps ) ; Ops . push_back ( SDValue ( ReplOp , <NUM_LIT> ) ) ; } else { Ops . push_back ( V ) ; } } SmallVector < EVT , <NUM_LIT> > NewVTs ; SDVTList VTs = PN -> getVTList ( ) ; for ( unsigned i = <NUM_LIT> , ie = VTs . NumVTs ; i != ie ; ++ i ) if ( VTs . VTs [ i ] == <STR_LIT> ) NewVTs . push_back ( <STR_LIT> ) ; else NewVTs . push_back ( VTs . VTs [ i ] ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( PN -> dump ( CurDAG ) ) ; CurDAG -> SelectNodeTo ( PN , NewOpcode , CurDAG -> getVTList ( NewVTs ) , Ops ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( PN -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; bool Changed = false ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { if ( IsPseudoCallIndirect ( MI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI << '\n' ) ;

const MCInstrDesc & Desc = TII -> get ( GetNonPseudoCallIndirectOpcode ( MI ) ) ;


<s> return ( ( qword ) ( vec_cmpeq ( ( vec_char16 ) ( a ) , vec_splat ( ( vec_char16 ) ( si_from_char ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> StringRef getPassName ( ) const override {


<s> tmp = gen_rtx_REG ( fpcmp_mode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_COMPARE ( fpcmp_mode , op0 , op1 ) ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ;

tmp = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ;


<s> fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ;


<s> void addImm0_1020s4Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) / <NUM_LIT> ) ) ;


<s> if ( ! Header || ! Preheader || ! Latch || ! ExitingBlock ) { return false ; } using RegisterBump = std :: pair < unsigned , int64_t > ; using InductionMap = std :: map < unsigned , RegisterBump > ; InductionMap IndMap ; using instr_iterator = MachineBasicBlock :: instr_iterator ; for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * Phi = & * I ; for ( unsigned i = <NUM_LIT> , n = Phi -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { if ( Phi -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) != Latch ) continue ; unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ; MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ; if ( DI -> getDesc ( ) . getOpcode ( ) == <STR_LIT> ) { unsigned IndReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Opnd2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V ; if ( MRI -> getVRegDef ( IndReg ) == Phi && checkForImmediate ( Opnd2 , V ) ) { unsigned UpdReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; } } } } if ( IndMap . empty ( ) ) { return false ; } MachineBasicBlock * TB = nullptr , * FB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; if ( NotAnalyzed || Cond . empty ( ) ) { return false ; } MachineInstr * condTerm = & ( * Latch -> getFirstTerminator ( ) ) ; MachineInstr * uncondTerm = & ( * std :: next ( Latch -> getFirstTerminator ( ) ) ) ; if ( ! ( condTerm -> getDesc ( ) . isConditionalBranch ( ) && uncondTerm -> getDesc ( ) . isUnconditionalBranch ( ) ) ) { return false ; }

unsigned CmpReg1 = Cond [ <NUM_LIT> ] . isReg ( ) ? ( unsigned ) Cond [ <NUM_LIT> ] . getReg ( ) : <NUM_LIT> ;


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( <STR_LIT> ) Opcode ) { case <STR_LIT> : break ; case <STR_LIT> : \ return <STR_LIT> # node ;


<s> rtx body = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == MEM ) ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; rtx_insn * and_insn ; rtx and_operation = find_alignment_op ( insn , base_reg , & and_insn ) ; if ( and_operation != <NUM_LIT> ) { df_ref def ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ;

rtx and_base = XEXP ( and_operation , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const {

JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ;


<s> Lower ( const MachineInstr * MI , MCInst & OutMI ) const { DEBUG ( dbgs ( ) << <STR_LIT> ) ; OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ;


<s> bool Hanging2Byte = BytesLeft & <NUM_LIT> ; bool Hanging1Byte = BytesLeft & <NUM_LIT> ; if ( Hanging4Byte ) { BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( SrcReg ) . addImm ( Offset ) ; BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( DstReg ) . addImm ( Offset ) ; Offset += <NUM_LIT> ; } if ( Hanging2Byte ) { BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Define ) . addReg ( SrcReg ) . addImm ( Offset ) ; BuildMI ( * BB , MI , dl , get ( <STR_LIT> ) ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( DstReg ) . addImm ( Offset ) ; Offset += <NUM_LIT> ; } if ( Hanging1Byte ) {


<s> ForCodeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) || FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> switch ( In ) { case MCDisassembler :: Success : return true ; case MCDisassembler :: SoftFail : Out = In ; return true ; case MCDisassembler :: Fail :


<s> if ( NONDEBUG_INSN_P ( insn ) && NONJUMP_INSN_P ( insn ) ) { rtx set = single_set ( insn ) ; if ( set ) { avoid_func_arg_motion ( arg , insn ) ; return ; } } if ( insn == BB_HEAD ( bb ) ) return ; insn = PREV_INSN ( insn ) ;


<s> bool equal_nonrecursive ( stdict ) const {


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_failure_address ( void * const TM_buff ) { return * _TFIAR_PTR ( TM_buff ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( ! StubSym . getPointer ( ) ) { MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_Sparc_R_DI<ISA_LIT>32 , MCSymbolRefExpr :: create ( SSym , Ctx ) , Ctx ) ; }

return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , Mang , TM , MMI , Streamer ) ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> Old . ChangeToImmediate ( Fold . ImmToFold & <NUM_LIT> ) ; return true ; } break ; default : break ; } } } } if ( ( Fold . isImm ( ) || Fold . isFI ( ) || Fold . isGlobal ( ) ) && Fold . needsShrink ( ) ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; auto Liveness = MBB -> computeRegisterLiveness ( & TRI , <STR_LIT> , MI , <NUM_LIT> ) ; if ( Liveness != MachineBasicBlock :: LQR_Dead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; int Op32 = Fold . getShrinkOpcode ( ) ; MachineOperand & Dst0 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Dst1 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Dst0 . isDef ( ) && Dst1 . isDef ( ) ) ; bool HaveNonDbgCarryUse = ! MRI . use_nodbg_empty ( Dst1 . getReg ( ) ) ; const TargetRegisterClass * Dst0RC = MRI . getRegClass ( Dst0 . getReg ( ) ) ; Register NewReg0 = MRI . createVirtualRegister ( Dst0RC ) ; MachineInstr * Inst32 = TII . buildShrunkInst ( * MI , Op32 ) ; if ( HaveNonDbgCarryUse ) { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Dst1 . getReg ( ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } Dst0 . setReg ( NewReg0 ) ; for ( unsigned I = MI -> getNumOperands ( ) - <NUM_LIT> ; I > <NUM_LIT> ; -- I ) MI -> removeOperand ( I ) ; MI -> setDesc ( TII . get ( <STR_LIT> ) ) ; if ( Fold . isCommuted ( ) ) TII . commuteInstruction ( * Inst32 , false ) ; return true ; } assert ( ! Fold . needsShrink ( ) && <STR_LIT> ) ; if ( Fold . isImm ( ) ) { if ( Old . isTied ( ) ) { int NewMFMAOpc = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NewMFMAOpc == - <NUM_LIT> ) return false ; MI -> setDesc ( TII . get ( NewMFMAOpc ) ) ; MI -> untieRegOperand ( <NUM_LIT> ) ; } Old . ChangeToImmediate ( Fold . ImmToFold ) ; return true ; } if ( Fold . isGlobal ( ) ) { Old . ChangeToGA ( Fold . OpToFold -> getGlobal ( ) , Fold . OpToFold -> getOffset ( ) , Fold . OpToFold -> getTargetFlags ( ) ) ; return true ; } if ( Fold . isFI ( ) ) { Old . ChangeToFrameIndex ( Fold . FrameIndexToFold ) ;


<s> if ( TSFlags & <STR_LIT> ) EmitByte ( <NUM_LIT> , CurByte , OS ) ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } if ( is64BitMode ( STI ) ) { if ( unsigned REX = DetermineREXPrefix ( MI , TSFlags , Desc ) ) EmitByte ( <NUM_LIT> | REX , CurByte , OS ) ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ;


<s> const int CC3 = <NUM_LIT> << <NUM_LIT> ; gcc_assert ( GET_CODE ( XEXP ( code , <NUM_LIT> ) ) == REG ) ; gcc_assert ( REGNO ( XEXP ( code , <NUM_LIT> ) ) == CC_REGNUM ) ; gcc_assert ( XEXP ( code , <NUM_LIT> ) == const0_rtx || ( GET_MODE ( XEXP ( code , <NUM_LIT> ) ) == CCRAWmode && CONST_INT_P ( XEXP ( code , <NUM_LIT> ) ) ) ) ; switch ( GET_MODE ( XEXP ( code , <NUM_LIT> ) ) ) { case CCZmode : case CCZ1mode : switch ( GET_CODE ( code ) ) { case EQ : return CC0 ; case NE : return CC1 | CC2 | CC3 ; default : return - <NUM_LIT> ; } break ; case CCT1mode : switch ( GET_CODE ( code ) ) { case EQ : return CC1 ; case NE : return CC0 | CC2 | CC3 ; default : return - <NUM_LIT> ; } break ; case CCT2mode : switch ( GET_CODE ( code ) ) { case EQ : return CC2 ; case NE : return CC0 | CC1 | CC3 ; default : return - <NUM_LIT> ; } break ; case CCT3mode : switch ( GET_CODE ( code ) ) { case EQ : return CC3 ; case NE : return CC0 | CC1 | CC2 ; default : return - <NUM_LIT> ; } break ; case CCLmode : switch ( GET_CODE ( code ) ) { case EQ : return CC0 | CC2 ; case NE : return CC1 | CC3 ; default : return - <NUM_LIT> ; } break ; case CCL1mode : switch ( GET_CODE ( code ) ) { case LTU : return CC2 | CC3 ; case GEU : return CC0 | CC1 ; default : return - <NUM_LIT> ; } break ; case CCL2mode : switch ( GET_CODE ( code ) ) { case GTU : return CC0 | CC1 ; case LEU : return CC2 | CC3 ; default : return - <NUM_LIT> ; } break ; case CCL3mode : switch ( GET_CODE ( code ) ) { case EQ : return CC0 | CC2 ; case NE : return CC1 | CC3 ; case LTU : return CC1 ; case GTU : return CC3 ; case LEU : return CC1 | CC2 ; case GEU : return CC2 | CC3 ; default : return - <NUM_LIT> ; } case CCUmode : switch ( GET_CODE ( code ) ) { case EQ : return CC0 ; case NE : return CC1 | CC2 | CC3 ; case LTU : return CC1 ; case GTU : return CC2 ; case LEU : return CC0 | CC1 ; case GEU : return CC0 | CC2 ; default : return - <NUM_LIT> ; } break ; case CCURmode :


<s> static tree types [ <NUM_LIT> * ( int ) MAX_MACHINE_MODE ] ; int mode_index ; mode_index = ( int ) mode ; if ( TREE_CODE ( type ) == INTEGER_TYPE && TYPE_UNSIGNED ( type ) ) mode_index += MAX_MACHINE_MODE ;

if ( types [ mode_index ] == NULL_TREE ) types [ mode_index ] = build_vector_type_for_mode ( type , mode ) ;


<s> EmitInt8 ( <STR_LIT> :: UNWIND_OPCODE_SET_VSP | Reg ) ;


<s> const Section * <ISA_LIT>TargetAsmInfo :: SelectSectionForMachineConst ( const Type * Ty ) const {


<s> SDValue <ISA_LIT>TargetLowering :: LowerFixedLengthBitcastToSVE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; auto SrcOp = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; EVT ContainerDstVT = getContainerForFixedLengthVector ( DAG , VT ) ; EVT ContainerSrcVT = getContainerForFixedLengthVector ( DAG , SrcOp . getValueType ( ) ) ;

SrcOp = convertToScalableVector ( DAG , ContainerSrcVT , SrcOp ) ;


<s> enum machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; op1 = op0 ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode0 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ;

pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ;