<s> unsigned CC = MI -> getOperand ( OpNo ) . getImm ( ) ; switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << 'l' ; break ;


<s> if ( In64BitMode || isTargetWin32 ( ) ) return false ; return isTargetELF ( ) || TM . getRelocationModel ( ) == Reloc :: Static ;


<s> final_emit_insn_group_barriers ( dump ) ; bundling ( dump , sched_verbose , current_sched_info -> prev_head , current_sched_info -> next_tail ) ;

if ( sched_verbose && dump ) fprintf ( dump , <STR_LIT> , INSN_UID ( NEXT_INSN ( current_sched_info -> prev_head ) ) , INSN_UID ( PREV_INSN ( current_sched_info -> next_tail ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( F -> getReturnType ( ) -> isDoubleTy ( ) && ! ST -> hasFP64 ( ) ) return true ; if ( F -> getReturnType ( ) -> isHalfTy ( ) && ! ST -> hasFullFP16 ( ) ) return true ; return ! ST -> hasFP<ISA_LIT>v8Base ( ) && ! ST -> hasVFP2Base ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! ST -> hasMVEIntegerOps ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> assert ( Kind == Memory && <STR_LIT> ) ; return Mem . Disp ;


<s> RegToUseForCFI = getSubReg ( Reg , <STR_LIT> ) ; for ( int I = <NUM_LIT> ; CSR_<ISA_LIT>_AAPCS_SaveList [ I ] ; ++ I ) { if ( CSR_<ISA_LIT>_AAPCS_SaveList [ I ] == RegToUseForCFI ) return true ; } return false ; } RegToUseForCFI = Reg ; return true ;


<s> OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; } else { const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_REGINFO , ELF :: SHF_ALLOC , SectionKind :: getMetadata ( ) ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> virtual void printDesc ( raw_ostream & os , const MachineInstr * Instr ) { if ( LongSerialize ) {


<s> static ConstantFPSDNode * getSplatConstantFP ( SDValue Op ) {

if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( Op ) ) return C ;


<s> D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( hasWriteBack ) { bool WBIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned WBReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; MIB . addReg ( WBReg , RegState :: Define | getDeadRegState ( WBIsDead ) ) ; } bool AddrIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( AddrIsKill ) ) ; MIB . addImm ( MI . getOperand ( OpIdx ++ ) . getImm ( ) ) ; if ( hasWriteBack ) { bool OffsetIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( OffsetIsKill ) ) ;


<s> auto Expr = MCBinaryExpr :: create ( MCBinaryExpr :: Sub , End , Start , getContext ( ) ) ; getStreamer ( ) . emitELFSize ( LastFunctionLabel , Expr ) ;


<s> MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) . addImm ( <STR_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ;

BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ;


<s> if ( high == <NUM_LIT> || high == - <NUM_LIT> ) return <NUM_LIT> ; high >>= <NUM_LIT> ; if ( low == <NUM_LIT> ) return num_insns_constant_wide ( high ) + <NUM_LIT> ;

else if ( high == <NUM_LIT> ) return num_insns_constant_wide ( low ) + <NUM_LIT> ;


<s> MachineOperand & VLOp = MI . getOperand ( MI . getNumExplicitOperands ( ) - Offset ) ; if ( VLOp . isReg ( ) ) { VLOp . setReg ( <STR_LIT> ) ; VLOp . setIsKill ( false ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; } MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; if ( ! CurInfo . isValid ( ) ) { assert ( BlockInfo [ MBB . getNumber ( ) ] . Pred . isValid ( ) && <STR_LIT> ) ; if ( needVSETVLI ( NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) && needVSETVLIPHI ( NewInfo , MBB ) ) { insertVSETVLI ( MBB , MI , NewInfo , BlockInfo [ MBB . getNumber ( ) ] . Pred ) ; CurInfo = NewInfo ; } } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , CurInfo ) && needVSETVLI ( NewInfo , CurInfo ) ) { bool NeedInsertVSETVLI = true ; if ( PrevVSETVLIMI ) { bool HasSameAVL = CurInfo . hasSameAVL ( NewInfo ) || ( NewInfo . hasAVLReg ( ) && NewInfo . getAVLReg ( ) . isVirtual ( ) && NewInfo . getAVLReg ( ) == PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( HasSameAVL && CurInfo . getSEWLMULRatio ( ) == NewInfo . getSEWLMULRatio ( ) ) { PrevVSETVLIMI -> getOperand ( <NUM_LIT> ) . setImm ( NewInfo . encodeVTYPE ( ) ) ;


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED ) { cum -> words = <NUM_LIT> ;

cum -> prototype_p = fntype && TYPE_ARG_TYPES ( fntype ) ;


<s> assert ( Size && <STR_LIT> ) ; const GlobalValue * GV = dyn_cast < GlobalValue > ( CV -> stripPointerCasts ( ) ) ; assert ( GV && <STR_LIT> ) ; const MCExpr * E = MCSymbolRefExpr :: create ( Get<ISA_LIT>GVSymbol ( GV , <STR_LIT> ) , ( Subtarget -> isTargetELF ( ) ? MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : MCSymbolRefExpr :: VK_None ) , OutContext ) ; OutStreamer -> EmitValue ( E , Size ) ;


<s> return ( float32x2_t ) __builtin_neon_vreinterpretv2sfv8qi ( ( int8x8_t ) __a ) ;


OS << <STR_LIT> << ByteAlignment << '\n' ;


<s> virtual unsigned int execute ( function * ) {


<s> uint64_t AlignMask = StackAlignment - <NUM_LIT> ; int64_t Offset = StackSize ; uint64_t SlotSize = TD -> getPointerSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) {

Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ;


<s> auto * DescSZ = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( DescEnd , Context ) , MCSymbolRefExpr :: create ( DescBegin , Context ) , Context ) ; EmitNote ( ElfNote :: NoteNameV2 , DescSZ , ELF :: NT_AMD_HSA_ISA_NAME , [ & ] ( MCELFStreamer & OS ) { OS . emitLabel ( DescBegin ) ; OS . emitBytes ( getTargetID ( ) -> toString ( ) ) ; OS . emitLabel ( DescEnd ) ;


<s> <STR_LIT> getMode ( ) const { return Mode ;


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBE = MF . end ( ) ; MBB != MBE ; ++ MBB ) { for ( llvm :: MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( ( I -> getOpcode ( ) == <STR_LIT> ) && std :: next ( I ) != E && I != MBB -> begin ( ) ) if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MachineBasicBlock * newBB = splitBlockAfterInstr ( I , MF ) ; MBB -> setHasAddressTaken ( ) ; break ; } if ( ( I -> getOpcode ( ) == <STR_LIT> ) && std :: next ( I ) == E && I != MBB -> begin ( ) ) if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MachineBasicBlock * newBB = MF . CreateMachineBasicBlock ( ( I -> getParent ( ) ) -> getBasicBlock ( ) ) ; MachineFunction :: iterator It = MBB -> getIterator ( ) ; if ( It != MF . end ( ) ) MF . insert ( It , newBB ) ;


<s> rtx_insn * seq ; if ( ! crtl -> uses_pic_offset_table ) return ; start_sequence ( ) ; load_got_register ( ) ; if ( ! TARGET_VXWORKS_RTP ) emit_move_insn ( pic_offset_table_rtx , global_offset_table_rtx ) ; seq = get_insns ( ) ;


<s> void <ISA_LIT>InstPrinter :: printU2ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) {

printUImmOperand < <NUM_LIT> > ( MI , OpNum , O ) ;


<s> auto IPtr = SwitchesOfInstruction . find ( MnemonicKey { Mnemonic , getSlotCode ( Slot ) } ) ; if ( IPtr == SwitchesOfInstruction . end ( ) || IPtr -> second . Switches . empty ( ) ) return false ; if ( IPtr -> second . Switches . size ( ) == <NUM_LIT> && ( * IPtr -> second . Switches . begin ( ) ) -> Name . equals ( <STR_LIT> ) ) return false ; return true ;


<s> auto Mul = B . buildMul ( S64 , DivScale1 . getReg ( <NUM_LIT> ) , Fma3 , Flags ) ; auto Fma4 = B . buildFMA ( S64 , NegDivScale0 , Mul , DivScale1 . getReg ( <NUM_LIT> ) , Flags ) ; Register Scale ; if ( ! ST . hasUsableDivScaleConditionOutput ( ) ) { Scale = MRI . createGenericVirtualRegister ( S1 ) ; LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; auto NumUnmerge = B . buildUnmerge ( S32 , LHS ) ; auto DenUnmerge = B . buildUnmerge ( S32 , RHS ) ; auto Scale0Unmerge = B . buildUnmerge ( S32 , DivScale0 ) ; auto Scale1Unmerge = B . buildUnmerge ( S32 , DivScale1 ) ; auto CmpNum = B . buildICmp ( ICmpInst :: ICMP_EQ , S1 , NumUnmerge . getReg ( <NUM_LIT> ) , Scale1Unmerge . getReg ( <NUM_LIT> ) ) ; auto CmpDen = B . buildICmp ( ICmpInst :: ICMP_EQ , S1 , DenUnmerge . getReg ( <NUM_LIT> ) , Scale0Unmerge . getReg ( <NUM_LIT> ) ) ;

B . buildXor ( Scale , CmpNum , CmpDen ) ;


<s> static void riscv_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; enum machine_mode mode ; rtx * regs ; bits = MAX ( BITS_PER_UNIT , MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ) ; mode = mode_for_size ( bits , MODE_INT , <NUM_LIT> ) . require ( ) ;


<s> rtx rawaddr ; if ( op0 == const0_rtx ) rawaddr = op1 ; else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; rawaddr = gen_rtx_PLUS ( Pmode , op1 , op0 ) ; } addr = gen_rtx_AND ( Pmode , rawaddr , gen_rtx_CONST_INT ( Pmode , - <NUM_LIT> ) ) ; addr = gen_rtx_MEM ( blk ? BLKmode : tmode , addr ) ; emit_insn ( gen_rtx_SET ( target , addr ) ) ; } else { if ( op0 == const0_rtx ) addr = gen_rtx_MEM ( blk ? BLKmode : tmode , op1 ) ; else { op0 = copy_to_mode_reg ( mode0 , op0 ) ;

addr = gen_rtx_MEM ( blk ? BLKmode : tmode , gen_rtx_PLUS ( Pmode , op1 , op0 ) ) ;


<s> switch ( Option ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: createLower16 ( Expr , OutContext ) ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; Expr = <ISA_LIT>MCExpr :: createUpper16 ( Expr , OutContext ) ;


<s> if ( Op . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; if ( ! LHS . getValueType ( ) . isFloatingPoint ( ) ) return Op ;

SDValue RHS = Op . getOperand ( <NUM_LIT> ) ;


<s> if ( size ) fprintf ( file , <STR_LIT> , align , reg_names [ regno ] , size ) ; fprintf ( file , <STR_LIT> , POINTER_SIZE , reg_names [ regno ] ) ;

fprintf ( file , ( size ? <STR_LIT> : <STR_LIT> ) , POINTER_SIZE , reg_names [ regno ] , reg_names [ regno ] ) ;


<s> addPass ( create<ISA_LIT>LongBranchPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return true ;


<s> void printS16ImmOperand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) {

O << ( int16_t ) MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> EVT InVT = Zext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned RegSize = std :: max ( <NUM_LIT> , InVT . getSizeInBits ( ) ) ; unsigned NumConcat = RegSize / InVT . getSizeInBits ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , DAG . getConstant ( <NUM_LIT> , DL , InVT ) ) ; Ops [ <NUM_LIT> ] = Zext0 . getOperand ( <NUM_LIT> ) ; MVT ExtendedVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue SadOp0 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; Ops [ <NUM_LIT> ] = Zext1 . getOperand ( <NUM_LIT> ) ; SDValue SadOp1 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; auto PSADBWBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT VT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } ; MVT SadVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ;

return SplitOpsAndApply ( DAG , Subtarget , DL , SadVT , { SadOp0 , SadOp1 } , PSADBWBuilder ) ;


<s> bool isGPR64x8 ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> else if ( RC == & <STR_LIT> ) opc = isValidFrameIdx ? <STR_LIT> : <STR_LIT> ; else if ( RC == & <STR_LIT> ) opc = isValidFrameIdx ? <STR_LIT> : <STR_LIT> ; else if ( RC == & <STR_LIT> ) opc = isValidFrameIdx ? <STR_LIT> : <STR_LIT> ; else if ( RC == & <STR_LIT> ) opc = isValidFrameIdx ? <STR_LIT> : <STR_LIT> ; else if ( RC == & <STR_LIT> ) opc = isValidFrameIdx ? <STR_LIT> : <STR_LIT> ; else if ( RC == & <STR_LIT> ) opc = isValidFrameIdx ? <STR_LIT> : <STR_LIT> ; else if ( RC == & <STR_LIT> ) opc = isValidFrameIdx ? <STR_LIT> : <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( opc ) , DestReg ) , FrameIdx ) ;


<s> else if ( Base . getValueType ( ) == <STR_LIT> && ! dyn_cast < FrameIndexSDNode > ( Base ) ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Base , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } RN = dyn_cast < RegisterSDNode > ( Index ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Index = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else { assert ( Index . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Index = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Index , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; }


<s> unsigned Mods = <NUM_LIT> ; MachineInstr * MI = MRI . getVRegDef ( Src ) ; if ( MI && MI -> getOpcode ( ) == <STR_LIT> && MRI . getType ( Src ) == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Mods ^= ( <STR_LIT> | <STR_LIT> ) ; Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget -> isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer -> getCurrentSection ( ) ; MCSectionELF * Section = OutStreamer -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Section ) ; OutStreamer -> EmitLabel ( CurrentFnSym ) ; OutStreamer -> EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = CurrentFnSymForSize ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Symbol1 , OutContext ) , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOCBASE , OutContext ) , <NUM_LIT> ) ;

OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ;


<s> MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID ) . addOperand ( CPEMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; decrementCPEReferenceCount ( CPI , CPEMI ) ; NewIsland -> setAlignment ( getCPELogAlign ( U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( & * -- NewIsland -> getIterator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i ) . setIndex ( ID ) ;


<s> R600EmitClauseMarkers ( ) : MachineFunctionPass ( ID ) , TII ( <NUM_LIT> ) , Address ( <NUM_LIT> ) {

initializeR600EmitClauseMarkersPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> void makeLive ( Register PhysReg ) override {

Call . addDef ( PhysReg , RegState :: Implicit ) ;


<s> static void BuildEndSignature ( BasicBlock & BB , Function & F ) { return BuildSignatureCall ( symbols :: END_FUNCTION_SIGNATURE , BB , F ) ;


<ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) :


<s> val = expand_simple_binop ( SImode , AND , val , GEN_INT ( GET_MODE_MASK ( mode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; return expand_simple_binop ( SImode , ASHIFT , val , count , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ;


<s> Value * UO = GetUnderlyingObject ( LI -> getPointerOperand ( ) , F . getParent ( ) -> getDataLayout ( ) ) ; if ( Argument * Arg = dyn_cast < Argument > ( UO ) ) { if ( Arg -> hasByValAttr ( ) ) { markPointerAsGlobal ( LI ) ; } } } } } } } for ( Argument & Arg : F . args ( ) ) { if ( Arg . getType ( ) -> isPointerTy ( ) ) { if ( Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ; else if ( TM && TM -> getDrvInterface ( ) == <STR_LIT> ) markPointerAsGlobal ( & Arg ) ; }


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: create ( INT32_MIN , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Parser . getTok ( ) . getString ( ) , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } } case AsmToken :: Colon : { S = Parser . getTok ( ) . getLoc ( ) ; <ISA_LIT>MCExpr :: VariantKind RefKind ; if ( parsePrefix ( RefKind ) ) return true ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; const MCExpr * ExprVal = <ISA_LIT>MCExpr :: create ( RefKind , SubExprVal , getContext ( ) ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ExprVal , S , E ) ) ; return false ; } case AsmToken :: Equal : { S = Parser . getTok ( ) . getLoc ( ) ; if ( Mnemonic != <STR_LIT> ) return Error ( S , <STR_LIT> ) ; Parser . Lex ( ) ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateConstantPoolImm ( SubExprVal , S , E ) ) ; return false ; }


<s> unsigned AS = Memop -> getAddrSpace ( ) ; if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return true ;


<s> StringRef getPassName ( ) const override {


<s> return __builtin_loongson_psubd_u ( s , t ) ;


<s> Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , NameLoc , NameLoc , <STR_LIT> { static_cast < int64_t > ( BT ) } ) ) ;


<s> Register Rs = TailAdd . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Rt = TailAdd . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Reg = Rs == GAReg ? Rt : Rs ; if ( ! MRI -> hasOneUse ( Reg ) ) return false ; MachineInstr & OffsetTail = * MRI -> getVRegDef ( Reg ) ; if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { MachineOperand & AddiImmOp = OffsetTail . getOperand ( <NUM_LIT> ) ; if ( AddiImmOp . getTargetFlags ( ) != <STR_LIT> ) return false ; int64_t OffLo = AddiImmOp . getImm ( ) ;

MachineInstr & OffsetLui = * MRI -> getVRegDef ( OffsetTail . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= <NUM_LIT> ) || ( TARGET_ARCH64 && size <= <NUM_LIT> ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , SPARC_FP_ARG_FIRST ) ; mclass = MODE_FLOAT ; } if ( TARGET_ARCH64 && type ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_record_value ( type , mode , <NUM_LIT> , <NUM_LIT> , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; return function_arg_union_value ( size , mode , <NUM_LIT> , regbase ) ; } else if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) ; else if ( AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= <NUM_LIT> ) ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , <NUM_LIT> ) ; if ( mode == BLKmode ) return function_arg_union_value ( size , mode , <NUM_LIT> , regbase ) ; else mclass = MODE_INT ; }

else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ;


<s> static MachineBasicBlock * getPHIPred ( MachineInstr & PHI , unsigned Index ) {


<s> unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> TokError ( <STR_LIT> ) ; return false ; } if ( ! Section ) { getStreamer ( ) . InitSections ( ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; } if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> ) ; return false ;


<s> if ( Value . getOpcode ( ) != <STR_LIT> ) return false ; if ( Store -> getMemoryVT ( ) . getSizeInBits ( ) != Value . getValueSizeInBits ( ) ) return false ; SDValue ElemV = Value . getOperand ( <NUM_LIT> ) ; auto * ElemN = dyn_cast < ConstantSDNode > ( ElemV ) ; if ( ! ElemN ) return false ; SDValue Vec = Value . getOperand ( <NUM_LIT> ) ; EVT VT = Vec . getValueType ( ) ; unsigned Elem = ElemN -> getZExtValue ( ) ; if ( Elem >= VT . getVectorNumElements ( ) ) return false ; SDValue Base , Disp , Index ; if ( ! selectBDVAddr12Only ( Store -> getBasePtr ( ) , ElemV , Base , Disp , Index ) || Index . getValueType ( ) != VT . changeVectorElementTypeToInteger ( ) ) return false ; SDLoc DL ( Store ) ; SDValue Ops [ ] = { Vec , Base , Disp , Index , CurDAG -> getTargetConstant ( Elem , DL , <STR_LIT> ) , Store -> getChain ( ) } ; ReplaceNode ( Store , CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ) ; return true ;


return ( __m64 ) __builtin_arm_wqmulmr ( ( __v4hi ) a , ( __v4hi ) b ) ;


<s> bool isO32 ( ) const { return STI . getFeatureBits ( ) & <STR_LIT> ;


<s> MCSymbol * EndOfSled = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( BeginOfSled ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( EndOfSled , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( <STR_LIT> ) , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; OutStreamer -> EmitLabel ( EndOfSled ) ; recordSled ( BeginOfSled , * MI , SledKind :: FUNCTION_ENTER ) ; break ; } case TargetOpcode :: PATCHABLE_FUNCTION_EXIT : { const MachineInstr * Next = [ & ] { MachineBasicBlock :: const_iterator It ( MI ) ; assert ( It != MI -> getParent ( ) -> end ( ) ) ; ++ It ; assert ( It -> isReturn ( ) ) ; return & * It ; } ( ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; MCSymbol * BeginOfSled = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( BeginOfSled ) ; MCInst TmpInst ; Lower<ISA_LIT>MachineInstrToMCInst ( Next , TmpInst , * this , false ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( <STR_LIT> ) , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ;

recordSled ( BeginOfSled , * MI , SledKind :: FUNCTION_EXIT ) ;


<s> return TargetABI == <ISA_LIT>_ABI_AAPCS ;


<s> if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ;


<s> return DoSelectCall ( & I , <STR_LIT> ) ; } case <STR_LIT> : { EVT PtrTy = TLI . getPointerTy ( ) ; const Value * Op1 = I . getArgOperand ( <NUM_LIT> ) ; const AllocaInst * Slot = cast < AllocaInst > ( I . getArgOperand ( <NUM_LIT> ) ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( Slot , AM ) ) return false ; if ( ! <ISA_LIT>FastEmitStore ( PtrTy , Op1 , AM ) ) return false ; return true ; } case <STR_LIT> : { const DbgDeclareInst * DI = cast < DbgDeclareInst > ( & I ) ; <ISA_LIT>AddressMode AM ; assert ( DI -> getAddress ( ) && <STR_LIT> ) ; if ( ! <ISA_LIT>SelectAddress ( DI -> getAddress ( ) , AM ) ) return false ; const MCInstrDesc & II = TII . get ( TargetOpcode :: DBG_VALUE ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) , AM ) . addImm ( <NUM_LIT> ) . addMetadata ( DI -> getVariable ( ) ) ; return true ; } case <STR_LIT> : { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; MVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; const Value * Op1 = I . getArgOperand ( <NUM_LIT> ) ; const Value * Op2 = I . getArgOperand ( <NUM_LIT> ) ;

unsigned Reg1 = getRegForValue ( Op1 ) ;


<s> static void insertDAGNode ( SelectionDAG * DAG , SDNode * Pos , SDValue N ) {

if ( N . getNode ( ) -> getNodeId ( ) == - <NUM_LIT> || N . getNode ( ) -> getNodeId ( ) > Pos -> getNodeId ( ) ) {


<s> if ( TREE_CODE ( intr_vector ) == STRING_CST ) sprintf ( buf , <STR_LIT> , TREE_STRING_POINTER ( intr_vector ) ) ; else sprintf ( buf , <STR_LIT> , ( unsigned int ) TREE_INT_CST_LOW ( intr_vector ) ) ; switch_to_section ( get_section ( buf , SECTION_CODE , decl ) ) ; fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputc ( '\n' , file ) ; fputc ( '\t' , file ) ; } } switch_to_section ( function_section ( decl ) ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( file , name , <STR_LIT> ) ;

ASM_OUTPUT_FUNCTION_LABEL ( file , name , decl ) ;


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Vec = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

unsigned Off = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ; SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue TLS = DAG . getLoad ( PtrVT , DL , Chain , DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSArray , Slot ) , MachinePointerInfo ( ) ) ; const auto * GA = cast < GlobalAddressSDNode > ( Op ) ;

auto * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <STR_LIT> ) ;


<s> case MCCFIInstruction :: OpRelOffset : break ; default : DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> <STR_LIT> << Inst . getOperation ( ) << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; break ; } } if ( ( CFARegister == <STR_LIT> ) && ( CFARegisterOffset == <NUM_LIT> ) ) return <NUM_LIT> ; if ( CFARegister != <STR_LIT> ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << CFARegister << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } int StackAdjust = CFARegisterOffset - <NUM_LIT> ; if ( RegOffsets . lookup ( <STR_LIT> ) != ( - <NUM_LIT> - StackAdjust ) ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << StackAdjust << <STR_LIT> << CFARegisterOffset << <STR_LIT> << RegOffsets [ <NUM_LIT> ] << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } if ( RegOffsets . lookup ( <STR_LIT> ) != ( - <NUM_LIT> - StackAdjust ) ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } uint32_t CompactUnwindEncoding = CU :: UNWIND_<ISA_LIT>_MODE_FRAME ; switch ( StackAdjust ) { case <NUM_LIT> : break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; default : DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << StackAdjust << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } static struct { unsigned Reg ; unsigned Encoding ; } GPRCSRegs [ ] = { { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R6 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R5 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R4 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R12 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R11 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R10 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R9 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R8 } } ; int CurOffset = - <NUM_LIT> - StackAdjust ; for ( auto CSReg : GPRCSRegs ) { auto Offset = RegOffsets . find ( CSReg . Reg ) ; if ( Offset == RegOffsets . end ( ) ) continue ; int RegOffset = Offset -> second ; if ( RegOffset != CurOffset - <NUM_LIT> ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << MRI . getName ( CSReg . Reg ) << <STR_LIT> << RegOffset << <STR_LIT> << CurOffset << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } CompactUnwindEncoding |= CSReg . Encoding ; CurOffset -= <NUM_LIT> ;


<s> return gen_rtx_REG ( mode , RETURN_VALUE_REGNUM ) ;


<s> inline vector float vec_vmaxfp ( vector float a1 , vector float a2 ) {

return ( vector float ) __builtin_altivec_vmaxfp ( ( vector float ) a1 , ( vector float ) a2 ) ;


<s> return ; case OPCODE_IS_ZERO : static_cast < MachineInstr * > ( I ) -> getOperand ( <NUM_LIT> ) . setImm ( OPCODE_IS_NOT_ZERO ) ; return ; case OPCODE_IS_NOT_ZERO : static_cast < MachineInstr * > ( I ) -> getOperand ( <NUM_LIT> ) . setImm ( OPCODE_IS_ZERO ) ; return ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectStore ( Instruction * I ) { MVT VT ; if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT ) ) return false ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM , false ) ) return false ;

return <ISA_LIT>FastEmitStore ( VT , I -> getOperand ( <NUM_LIT> ) , AM ) ;


<s> SDValue True ; SDValue False ; if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( ) ) { EVT VT = Op . getValueType ( ) ; SDValue <ISA_LIT>cc = Cond . getOperand ( <NUM_LIT> ) ; SDValue CCR = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = duplicateCmp ( Cond . getOperand ( <NUM_LIT> ) , DAG ) ; assert ( True . getValueType ( ) == VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , True , False , <ISA_LIT>cc , CCR , Cmp ) ; } } }

return DAG . getSelectCC ( dl , Cond , DAG . getConstant ( <NUM_LIT> , Cond . getValueType ( ) ) , SelectTrue , SelectFalse , <STR_LIT> ) ;


<s> rtx i32vl = NULL_RTX ; if ( CONST_INT_P ( avl ) ) { unsigned elt_size = GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ; unsigned min_size = get_unknown_min_value ( mode ) ; unsigned vlen_max = RVV_65536 ; unsigned vlmax_max = compute_vlmax ( vlen_max , elt_size , min_size ) ; unsigned vlen_min = TARGET_MIN_VLEN ; unsigned vlmax_min = compute_vlmax ( vlen_min , elt_size , min_size ) ; unsigned HOST_WIDE_INT avl_int = INTVAL ( avl ) ; if ( avl_int <= vlmax_min ) i32vl = gen_int_mode ( <NUM_LIT> * avl_int , Pmode ) ; else if ( avl_int >= <NUM_LIT> * vlmax_max ) { i32vl = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_no_side_effects_vsetvl_rtx ( demote_mode , i32vl , RVV_VLMAX ) ) ; } else { } } if ( ! i32vl ) {


<s> const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_RVC ;


<s> tree cr6_form = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode tmode = SImode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; int cr6_form_int ; if ( TREE_CODE ( cr6_form ) != INTEGER_CST ) { error ( <STR_LIT> , <STR_LIT> ) ; return const0_rtx ; } else cr6_form_int = TREE_INT_CST_LOW ( cr6_form ) ; gcc_assert ( mode0 == mode1 ) ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; scratch = gen_reg_rtx ( mode0 ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; switch ( cr6_form_int ) { case <NUM_LIT> : emit_insn ( gen_cr6_test_for_zero ( target ) ) ; break ; case <NUM_LIT> : emit_insn ( gen_cr6_test_for_zero_reverse ( target ) ) ; break ; case <NUM_LIT> : emit_insn ( gen_cr6_test_for_lt ( target ) ) ; break ; case <NUM_LIT> : emit_insn ( gen_cr6_test_for_lt_reverse ( target ) ) ; break ; default : error ( <STR_LIT> , <STR_LIT> ) ;


<s> OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return SDValue ( OutRetAddr . getNode ( ) , <NUM_LIT> ) ;


<s> if ( DECL_FUNCTION_SPECIFIC_TARGET ( current_function_decl ) == NULL ) return ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; s390_asm_output_machine_for_arch ( asm_out_file ) ;


<s> const MCSymbol * SB = & B -> getSymbol ( ) ; if ( ! SB -> getFragment ( ) ) Asm . getContext ( ) . reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: <ISA_LIT>_RELOC_SECTDIFF || Type == MachO :: <ISA_LIT>_RELOC_LOCAL_SECTDIFF ) { MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: <ISA_LIT>_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ;


<s> if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { unsigned DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; }


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : return Expand2AddrUndef ( MI , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> unsigned NumElts = VecTy -> getVectorNumElements ( ) ; auto * SubVecTy = VectorType :: get ( VecTy -> getScalarType ( ) , NumElts / Factor ) ; if ( NumElts % Factor == <NUM_LIT> && TLI -> isLegalInterleavedAccessType ( SubVecTy , DL ) ) return Factor * TLI -> getNumInterleavedAccesses ( SubVecTy , DL ) ; }

return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ;


<s> Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; } Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; return MCDisassembler :: Success ;


<s> else DstMI = TRI -> getMatchingSuperReg ( Reg , TRI -> getSubRegFromChannel ( TRI -> getHWRegChan ( Reg ) ) , & <STR_LIT> ) ; } if ( MO . isUse ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) SrcMI = Reg ; else SrcMI = TRI -> getMatchingSuperReg ( Reg , TRI -> getSubRegFromChannel ( TRI -> getHWRegChan ( Reg ) ) , & <STR_LIT> ) ; } } if ( ( DstRegs . find ( SrcMI ) == DstRegs . end ( ) ) ) {


<s> LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; isKernelFunc = F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_KERNEL ; visit ( F ) ; noClobberClones . clear ( ) ; return true ;


<s> } return ( STy -> getNumElements ( ) == <NUM_LIT> ) ? <NUM_LIT> : SmallestElement ; } case Type :: ArrayTyID : { const ArrayType * ATy = cast < const ArrayType > ( Ty ) ; return getSmallestAddressableSize ( ATy -> getElementType ( ) , GV , TM ) ; } case Type :: FixedVectorTyID : case Type :: ScalableVectorTyID : { const VectorType * PTy = cast < const VectorType > ( Ty ) ; return getSmallestAddressableSize ( PTy -> getElementType ( ) , GV , TM ) ; } case Type :: PointerTyID : case Type :: HalfTyID : case Type :: FloatTyID : case Type :: DoubleTyID : case Type :: IntegerTyID : { const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ;

return DL . getTypeAllocSize ( const_cast < Type * > ( Ty ) ) ;


<s> call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; } if ( TARGET_FDPIC ) { fixed_regs [ PIC_REG ] = <NUM_LIT> ; call_used_regs [ PIC_REG ] = <NUM_LIT> ; call_really_used_regs [ PIC_REG ] = <NUM_LIT> ; } if ( TARGET_HITACHI && ! TARGET_NOMACSAVE ) { call_really_used_regs [ MACH_REG ] = <NUM_LIT> ; call_really_used_regs [ MACL_REG ] = <NUM_LIT> ; } if ( TARGET_SHMEDIA ) { for ( regno = FIRST_TARGET_REG ; regno <= LAST_TARGET_REG ; regno ++ ) if ( ! fixed_regs [ regno ] && call_really_used_regs [ regno ] ) SET_HARD_REG_BIT ( reg_class_contents [ SIBCALL_REGS ] , regno ) ; } else for ( regno = FIRST_GENERAL_REG ; regno <= LAST_GENERAL_REG ; regno ++ ) if ( ! fixed_regs [ regno ] && call_really_used_regs [ regno ] ) SET_HARD_REG_BIT ( reg_class_contents [ SIBCALL_REGS ] , regno ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBaseOffsetValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & RegMO = MI . getOperand ( OpIdx ) ; const MCOperand & ImmMO = MI . getOperand ( OpIdx + <NUM_LIT> ) ;

unsigned Reg = getMachineOpValue ( MI , RegMO , Fixups , STI ) ;


<s> static MCTargetStreamer * create<ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) {

return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;


<s> <ISA_LIT>TargetStreamer & CTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ;

if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) CTS . finishAttributeSection ( ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

llvm :: RegisterTarget < llvm :: Triple :: mina32 > X ( llvm :: getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> static void unsigned_width ( unsigned Width , uint64_t Value , std :: string Description , const MCFixup & Fixup , MCContext * Ctx = nullptr ) { if ( ! isUIntN ( Width , Value ) ) { std :: string Diagnostic = <STR_LIT> + Description ; int64_t Max = maxUIntN ( Width ) ; Diagnostic += <STR_LIT> + std :: to_string ( Max ) + <STR_LIT> ;


<s> if ( amount < <NUM_LIT> ) amount = <NUM_LIT> ; if ( ( unsigned int ) amount > GET_MODE_BITSIZE ( mode ) ) amount = GET_MODE_BITSIZE ( mode ) ; if ( ( unsigned int ) amount > GET_MODE_BITSIZE ( mode ) / ( unsigned ) <NUM_LIT> ) { amount = GET_MODE_BITSIZE ( mode ) - amount ; rotate_type = ( rotate_type == SHIFT_ASHIFT ) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT ; } if ( ( mode == HImode && TARGET_H8300 && amount >= <NUM_LIT> ) || ( mode == HImode && TARGET_H8300H && amount >= <NUM_LIT> ) || ( mode == HImode && TARGET_H8300S && amount == <NUM_LIT> ) || ( mode == SImode && TARGET_H8300H && amount >= <NUM_LIT> ) || ( mode == SImode && TARGET_H8300S && amount >= <NUM_LIT> ) ) { switch ( mode ) { case HImode : insn_buf = <STR_LIT> ; output_asm_insn ( insn_buf , operands ) ; break ; case SImode : insn_buf = <STR_LIT> ; output_asm_insn ( insn_buf , operands ) ; break ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) return false ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const <ISA_LIT>RegisterInfo & TRI = * MO . getParent ( ) -> getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; switch ( MO . getType ( ) ) { default : errs ( ) << <STR_LIT> << MO << <STR_LIT> ; return true ; case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; break ; case MachineOperand :: MO_GlobalAddress : OS << MO . getGlobal ( ) -> getName ( ) ;


<s> else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ;


<s> return DecodePPRRegisterClass ( Inst , RegNo , Addr , Decoder ) ;


return ( __m256i ) __builtin_ia32_compressqi256_mask ( ( __v32qi ) __B , ( __v32qi ) _mm256_setzero_si256 ( ) , ( __mmask32 ) __A ) ;


<s> FPS ( ) : MachineFunctionPass ( & ID ) {


<s> for ( i = <NUM_LIT> , d = bdesc_cut ; i < ARRAY_SIZE ( bdesc_cut ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_cut_builtin ( d -> icode , exp , target ) ; for ( i = <NUM_LIT> , d = bdesc_2argimm ; i < ARRAY_SIZE ( bdesc_2argimm ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_binopimm_builtin ( d -> icode , exp , target ) ; for ( i = <NUM_LIT> , d = bdesc_void2arg ; i < ARRAY_SIZE ( bdesc_void2arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_voidbinop_builtin ( d -> icode , exp ) ; for ( i = <NUM_LIT> , d = bdesc_void3arg ; i < ARRAY_SIZE ( bdesc_void3arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_voidtriop_builtin ( d -> icode , exp ) ; for ( i = <NUM_LIT> , d = bdesc_voidacc ; i < ARRAY_SIZE ( bdesc_voidacc ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_voidaccop_builtin ( d -> icode , exp ) ; for ( i = <NUM_LIT> , d = bdesc_int_void2arg ; i < ARRAY_SIZE ( bdesc_int_void2arg ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_int_void2arg ( d -> icode , exp ) ; for ( i = <NUM_LIT> , d = bdesc_prefetches ; i < ARRAY_SIZE ( bdesc_prefetches ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_prefetches ( d -> icode , exp ) ; for ( i = <NUM_LIT> , d = bdesc_loads ; i < ARRAY_SIZE ( bdesc_loads ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_load_builtin ( d -> icode , TYPE_MODE ( TREE_TYPE ( exp ) ) , exp , target ) ; for ( i = <NUM_LIT> , d = bdesc_stores ; i < ARRAY_SIZE ( bdesc_stores ) ; i ++ , d ++ ) if ( d -> code == fcode ) return frv_expand_store_builtin ( d -> icode , exp ) ; return <NUM_LIT> ;


<s> local_cum = * get_cumulative_args ( cum ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) riscv_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == <NUM_LIT> ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ;


<s> for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( lowerOperand ( MO , MCOp ) ) OutMI . addOperand ( MCOp ) ;


<s> if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ;

if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) } ) ;


<s> return __builtin_mve_vcmpeqq_v8hi ( ( int16x8_t ) __a , ( int16x8_t ) __b ) ;


<s> } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << BTs [ i ] -> getNumber ( ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; typedef MachineBasicBlock :: const_succ_iterator succ_iterator ; if ( ! DefaultToAll ) { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) { const MachineBasicBlock * SB = * I ; if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; } } else { for ( succ_iterator I = B . succ_begin ( ) , E = B . succ_end ( ) ; I != E ; ++ I ) Targets . insert ( * I ) ;


<s> STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ;


<s> const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; } else if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: Static ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; } else {

MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {


<s> parseExternFuncCallArgs ( * Outs , Args ) ; } else { assert ( F != nullptr && <STR_LIT> ) ; parseFunctionArgs ( F , TD , Args ) ; } unsigned RegsLeft = array_lengthof ( RegList8 ) , ValNo = <NUM_LIT> ; bool UsesStack = false ; for ( unsigned i = <NUM_LIT> , pos = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { unsigned Size = Args [ i ] ; MVT LocVT = ( IsCall ) ? ( * Outs ) [ pos ] . VT : ( * Ins ) [ pos ] . VT ; if ( ! UsesStack && ( Size <= RegsLeft ) ) { const MCPhysReg * RegList = ( LocVT == <STR_LIT> ) ? RegList16 : RegList8 ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Reg = CCInfo . AllocateReg ( ArrayRef < MCPhysReg > ( RegList , array_lengthof ( RegList8 ) ) ) ; CCInfo . addLoc ( CCValAssign :: getReg ( ValNo ++ , LocVT , Reg , LocVT , CCValAssign :: Full ) ) ;


<s> if ( get_cumulative_args ( ca ) -> regs == CRIS_MAX_ARGS_IN_REGS - <NUM_LIT> && ! targetm . calls . must_pass_in_stack ( mode , type ) && CRIS_FUNCTION_ARG_SIZE ( mode , type ) > <NUM_LIT> && CRIS_FUNCTION_ARG_SIZE ( mode , type ) <= <NUM_LIT> ) return UNITS_PER_WORD ; else return <NUM_LIT> ;


<s> return ( getKill ( ) && isKillImmutable ( ) ) || ! getKill ( ) ;


<s> uint64_t getStackSizeSVE ( ) const {


<s> bool isNEONi16splat ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( Value >= <NUM_LIT> && Value < <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) ;


<s> bool ScheduleDAGPostRA :: canAddEdge ( SUnit * SuccSU , SUnit * PredSU ) {

return SuccSU == & ExitSU || ! Topo . IsReachable ( PredSU , SuccSU ) ;


<s> void addNEONi32vmovNegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; unsigned Value = encodeNeonVMOVImmediate ( ~ CE -> getValue ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( Value ) ) ;


<s> auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ) ;

SecurityCheckCookie -> setCallingConv ( CallingConv :: Win64 ) ;


<s> } else if ( MEM_P ( operands [ <NUM_LIT> ] ) ) { if ( ! reg_or_0_operand ( operands [ <NUM_LIT> ] , mode ) ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ;

alpha_expand_unaligned_store ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( ! Register :: isVirtualRegister ( Reg ) ) return nullptr ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return nullptr ;

MachineInstr & DefMI = * MRI -> getVRegDef ( Reg ) ;


<s> assert ( ( IsLoad || isi32Store ( Opcode ) ) && <STR_LIT> ) ; unsigned LoadStoreOpcode = IsLoad ? <STR_LIT> : <STR_LIT> ; assert ( Regs . size ( ) == <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , InsertBefore , DL , TII -> get ( LoadStoreOpcode ) ) ; if ( IsLoad ) { MIB . addReg ( Regs [ <NUM_LIT> ] . first , RegState :: Define ) . addReg ( Regs [ <NUM_LIT> ] . first , RegState :: Define ) ; } else { MIB . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) ; }

MIB . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ;


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI ) : <ISA_LIT>AsmBackend ( T ) , MRI ( MRI ) {


<s> break ; } if ( NeedsWinCFI ) { auto SEH = std :: next ( MBBI ) ; if ( <ISA_LIT>InstrInfo :: isSEHInstruction ( * SEH ) ) SEH -> eraseFromParent ( ) ; } TypeSize Scale = TypeSize :: Fixed ( <NUM_LIT> ) ; unsigned Width ; int64_t MinOffset , MaxOffset ; bool Success = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) -> getMemOpInfo ( NewOpc , Scale , Width , MinOffset , MaxOffset ) ; ( void ) Success ; assert ( Success && <STR_LIT> ) ; MachineFunction & MF = * MBB . getParent ( ) ; if ( MBBI -> getOperand ( MBBI -> getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || CSStackSizeInc < MinOffset || CSStackSizeInc > MaxOffset ) { emitFrameOffset ( MBB , MBBI , DL , <STR_LIT> , <STR_LIT> , StackOffset :: getFixed ( CSStackSizeInc ) , TII , FrameFlag , false , false , nullptr , EmitCFI , StackOffset :: getFixed ( CFAOffset ) ) ; return std :: prev ( MBBI ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; MIB . addReg ( <STR_LIT> , RegState :: Define ) ; unsigned OpndIdx = <NUM_LIT> ; for ( unsigned OpndEnd = MBBI -> getNumOperands ( ) - <NUM_LIT> ; OpndIdx < OpndEnd ;

++ OpndIdx ) MIB . add ( MBBI -> getOperand ( OpndIdx ) ) ;


<s> unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; Vec = Extract128BitVector ( Vec , IdxVal , DAG , dl ) ; MVT EltVT = VecVT . getVectorElementType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ElemsPerChunk - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; if ( isNullConstant ( Op . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; }


<s> unsigned AddiOpc = ( Is64Bit && Hi20 ) ? <STR_LIT> : <STR_LIT> ; Res . push_back ( Inst ( AddiOpc , Lo12 ) ) ; } return ; } assert ( Is64Bit && <STR_LIT> ) ; int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ; int64_t Hi52 = ( Val + <NUM_LIT> ) >> <NUM_LIT> ; int ShiftAmount = <NUM_LIT> + findFirstSet ( ( uint64_t ) Hi52 ) ; Hi52 = SignExtend64 ( Hi52 >> ( ShiftAmount - <NUM_LIT> ) , <NUM_LIT> - ShiftAmount ) ; generateInstSeq ( Hi52 , Is64Bit , Res ) ; Res . push_back ( Inst ( <STR_LIT> , ShiftAmount ) ) ; if ( Lo12 ) Res . push_back ( Inst ( <STR_LIT> , Lo12 ) ) ;


<s> bool isNegated ( ) const { return Negated ;


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( UNITS_PER_WORD ) ) ; x = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , x ) ;

add_reg_note ( insn , REG_FRAME_RELATED_EXPR , x ) ;


<s> if ( RemSize < LoadSize ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalSizeLoaded ; else Shamt = ( RegSize - ( TotalSizeLoaded + LoadSize ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val = Shift ; Offset += LoadSize ; TotalSizeLoaded += LoadSize ; Alignment = std :: min ( Alignment , LoadSize ) ; } unsigned ArgReg = ArgRegs [ ByVal . FirstIdx + I ] ;

RegsToPass . push_back ( std :: make_pair ( ArgReg , Val ) ) ;


<s> return getABI ( ) . IsCheriPureCap ( ) ;


<s> unsigned int cost , alt_cost ; cost = mips_build_shift ( codes , value ) ; alt_cost = mips_build_lower ( alt_codes , value ) ; if ( alt_cost < cost ) { memcpy ( codes , alt_codes , alt_cost * sizeof ( codes [ <NUM_LIT> ] ) ) ; cost = alt_cost ; }


<s> <ISA_LIT>ArchVersion = <ISA_LIT>1 ; ParseSubtargetFeatures ( FS , CPU ) ; if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ; if ( TT . find ( <STR_LIT> ) != std :: string :: npos || TT . find ( <STR_LIT> ) != std :: string :: npos ) { <ISA_LIT>ABI = EABI ; IsSingleFloat = true ; <ISA_LIT>ArchVersion = <ISA_LIT>2 ; HasVFPU = true ; HasSEInReg = true ; HasBitCount = true ;


<s> assert ( ( RegIdx . Kind & RegKind_GPR ) && <STR_LIT> ) ; unsigned RegNo = getRegPair ( ) ; AsmParser . warnIfRegIndexIsAT ( RegNo , StartLoc ) ; Inst . addOperand ( MCOperand :: createReg ( RegIdx . RegInfo -> getRegClass ( AsmParser . getABI ( ) . AreGprs64bit ( ) ? <STR_LIT> : <STR_LIT> ) . getRegister ( RegNo ++ ) ) ) ;

Inst . addOperand ( MCOperand :: createReg ( RegIdx . RegInfo -> getRegClass ( AsmParser . getABI ( ) . AreGprs64bit ( ) ? <STR_LIT> : <STR_LIT> ) . getRegister ( RegNo ) ) ) ;


<s> return FullVT -> getNumElements ( ) == <NUM_LIT> * HalfVT -> getNumElements ( ) ; } ; ArrayRef < int > M1 , M2 ; Value * S1Op1 , * S2Op1 ; if ( ! match ( Op1 , m_ShuffleVector ( m_Value ( S1Op1 ) , m_Undef ( ) , m_Mask ( M1 ) ) ) || ! match ( Op2 , m_ShuffleVector ( m_Value ( S2Op1 ) , m_Undef ( ) , m_Mask ( M2 ) ) ) ) return false ; if ( ! areTypesHalfed ( S1Op1 , Op1 ) || ! areTypesHalfed ( S2Op1 , Op2 ) || ! extractHalf ( S1Op1 , Op1 ) || ! extractHalf ( S2Op1 , Op2 ) ) return false ; int M1Start = - <NUM_LIT> ; int M2Start = - <NUM_LIT> ; int NumElements = cast < VectorType > ( Op1 -> getType ( ) ) -> getNumElements ( ) * <NUM_LIT> ;

if ( ! ShuffleVectorInst :: isExtractSubvectorMask ( M1 , NumElements , M1Start ) || ! ShuffleVectorInst :: isExtractSubvectorMask ( M2 , NumElements , M2Start ) || M1Start != M2Start || ( M1Start != <NUM_LIT> && M2Start != ( NumElements / <NUM_LIT> ) ) ) return false ;


<s> const TargetRegisterClass * getMinClassForRegBank ( const RegisterBank & RB , unsigned SizeInBits , bool GetAllRegSet = false ) { unsigned RegBankID = RB . getID ( ) ; if ( RegBankID == <STR_LIT> ) { if ( SizeInBits <= <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( SizeInBits == <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; } if ( RegBankID == <STR_LIT> ) { switch ( SizeInBits ) { default : return nullptr ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ;


<s> CASE ( ImageChannelDataType , SnormInt8 ) CASE ( ImageChannelDataType , SnormInt16 ) CASE ( ImageChannelDataType , UnormInt8 ) CASE ( ImageChannelDataType , UnormInt16 ) CASE ( ImageChannelDataType , UnormShort565 ) CASE ( ImageChannelDataType , UnormShort555 ) CASE ( ImageChannelDataType , UnormInt101010 ) CASE ( ImageChannelDataType , SignedInt8 ) CASE ( ImageChannelDataType , SignedInt16 ) CASE ( ImageChannelDataType , SignedInt32 ) CASE ( ImageChannelDataType , UnsignedInt8 ) CASE ( ImageChannelDataType , UnsignedInt16 ) CASE ( ImageChannelDataType , UnsigendInt32 ) CASE ( ImageChannelDataType , HalfFloat ) CASE ( ImageChannelDataType , Float ) CASE ( ImageChannelDataType , UnormInt24 ) CASE ( ImageChannelDataType , UnormInt101010_2 ) break ; } llvm_unreachable ( <STR_LIT> ) ;


<s> if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( DefInfo . hasSameAVL ( CurInfo ) && DefInfo . hasSameVTYPE ( CurInfo ) ) return false ; } } }


<s> static inline bool isValidDecodeLogicalImmediate ( uint64_t val , unsigned regSize ) { unsigned N = ( val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned imms = val & <NUM_LIT> ;

if ( regSize == <NUM_LIT> && N != <NUM_LIT> ) return false ;


<s> popStackAfter ( I ) ; return ; } unsigned STReg = getSTReg ( FPRegNo ) ; unsigned OldSlot = getSlot ( FPRegNo ) ; unsigned TopReg = Stack [ StackTop - <NUM_LIT> ] ;


<s> if ( BytesAdded ) * BytesAdded += <NUM_LIT> ; } if ( Cond . empty ( ) || FBB ) { BuildMI ( MBB , MBB . end ( ) , DL , get ( <STR_LIT> ) ) . addMBB ( Cond . empty ( ) ? TBB : FBB ) ; NumInserted ++ ; if ( BytesAdded ) * BytesAdded += <NUM_LIT> ; } return NumInserted ;


<s> SDLoc DL ( N ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) && LHS . hasOneUse ( ) ) { SDValue Add = DAG . getNode ( <STR_LIT> , DL , OpVT , RHS , LHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } if ( RHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDValue Add = DAG . getNode ( <STR_LIT> , DL , OpVT , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } if ( SDValue V = combineVectorSizedSetCCEquality ( N , DAG , Subtarget ) ) return V ; } if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { SDValue Op0 = LHS ; SDValue Op1 = RHS ; <STR_LIT> TmpCC = CC ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; TmpCC = <STR_LIT> ( TmpCC ) ; } bool IsSEXT0 = ( Op0 . getOpcode ( ) == <STR_LIT> ) && ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( Op1 . getNode ( ) ) ; if ( IsSEXT0 && IsVZero1 ) { assert ( VT == Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; if ( TmpCC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( TmpCC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( TmpCC == <STR_LIT> || TmpCC == <STR_LIT> ) return DAG . getNOT ( DL , Op0 . getOperand ( <NUM_LIT> ) , VT ) ; assert ( ( TmpCC == <STR_LIT> || TmpCC == <STR_LIT> ) && <STR_LIT> ) ; return Op0 . getOperand ( <NUM_LIT> ) ;


<s> & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : return CalleeSavedRegClassesV3 ; }


<s> static const char * const specialTypes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Type * Ty = arg -> getType ( ) ; auto * PTy = dyn_cast < PointerType > ( Ty ) ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> if ( ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , DAG , Subtarget , IsFadd ) ) return DAG . getNode ( HorizOpcode , SDLoc ( N ) , VT , LHS , RHS ) ;


<s> PrivateLabelPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SunStyleELFSectionSwitchSyntax = true ; UsesELFSectionDirectiveForBSS = true ; HasAggressiveSymbolFolding = true ; COMMDirectiveAlignmentIsInBytes = false ; HasNoDeadStrip = true ; SupportsDebugInformation = true ; UsesCFIForDebug = true ; DwarfRegNumForCFI = true ; UseIntegratedAssembler = false ;


<s> if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) || ( TARGET_HAVE_MVE && ( VALID_MVE_MODE ( mode1 ) || VALID_MVE_STRUCT_MODE ( mode1 ) ) && ( VALID_MVE_MODE ( mode2 ) || VALID_MVE_STRUCT_MODE ( mode2 ) ) ) ) return true ; return false ;


<s> bool isInlineCompatible ( <ISA_LIT>ModeRegisterDefaults CalleeMode ) const { if ( DX10Clamp != CalleeMode . DX10Clamp ) return false ; if ( IEEE != CalleeMode . IEEE ) return false ;

return oneWayCompatible ( FP64FP16InputDenormals , CalleeMode . FP64FP16InputDenormals ) && oneWayCompatible ( FP64FP16OutputDenormals , CalleeMode . FP64FP16OutputDenormals ) && oneWayCompatible ( FP32InputDenormals , CalleeMode . FP32InputDenormals ) && oneWayCompatible ( FP32OutputDenormals , CalleeMode . FP32OutputDenormals ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << BB -> getName ( ) << <STR_LIT> << <STR_LIT> << BB -> getNumber ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << <STR_LIT> << <STR_LIT> << MF . getNumBlockIDs ( ) << <STR_LIT> ) ; for ( unsigned i = BBNum + <NUM_LIT> , e = MF . getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned LogAlign = MF . getBlockNumbered ( i ) -> getAlignment ( ) ; unsigned Offset = BBInfo [ i - <NUM_LIT> ] . postOffset ( LogAlign ) ; unsigned KnownBits = BBInfo [ i - <NUM_LIT> ] . postKnownBits ( LogAlign ) ; if ( i > BBNum + <NUM_LIT> && BBInfo [ i ] . Offset == Offset && BBInfo [ i ] . KnownBits == KnownBits ) break ; BBInfo [ i ] . Offset = Offset ; BBInfo [ i ] . KnownBits = KnownBits ;


<s> ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ; ImmToIdxMap [ <STR_LIT> ] = <STR_LIT> ;


<s> vtst_p64 ( poly64x1_t a , poly64x1_t b ) {

return ( uint64x1_t ) ( ( a & b ) != __AARCH64_INT64_C ( <NUM_LIT> ) ) ;


<s> return MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( Reg ) . addImm ( SC ) . addUse ( get<ISA_LIT>TypeID ( ElemType ) ) ;


<s> } if ( ( producer . the_slotID == e_issue_slot_load ) && ( ( producer . the_opCode == <NUM_LIT> ) || ( producer . the_opCode == <NUM_LIT> ) ) && ( producer_is2xLookupAddSub == <NUM_LIT> ) ) latency = latency + <NUM_LIT> ; if ( tpc_generation > <NUM_LIT> ) { bool consumer_is_fma_accumulator = ( ( ( consumer . the_opCode == OP_MAC ) || ( consumer . the_opCode == OP_MADD ) ) && consumer . the_operandID == e_src_c && consumer . the_isOpTypeFloat == <NUM_LIT> ) || ( ( consumer . the_opCode == OP_ADD || consumer . the_opCode == OP_SUB ) && ( consumer . the_isFp16 == true || consumer . the_isFp8 == true || consumer . the_is2xLookupAddSub == true ) && consumer . the_operandID == e_src_a ) ; bool producer_is_fma_accumulator = ( ( ( ( producer . the_opCode == OP_MAC ) || ( producer . the_opCode == OP_MADD ) || ( producer . the_opCode == OP_MUL ) ) && producer . the_isOpTypeFloat == <NUM_LIT> ) || ( ( producer . the_opCode == OP_ADD || producer . the_opCode == OP_SUB ) && ( producer . the_isFp16 == true || producer . the_isFp8 == true || producer . the_is2xLookupAddSub == true ) ) ) && producer . the_operandID == e_dst ; if ( consumer_is_fma_accumulator ) { if ( ! producer_is_fma_accumulator && ( ( ( producer . the_slotID == ISSUE_SLOT_ID_VPU ) && ( producer . the_opCode == OP_SHUFFLE || producer . the_opCode == OP_PACK || producer . the_opCode == OP_UNPACK || producer . the_opCode == OP_MOV_GROUP || producer . the_opCode == OP_MOV_DUAL_GROUP || producer . the_opCode == OP_MSAC ) ) || ( ( producer . the_slotID == ISSUE_SLOT_ID_SPU ) && ( producer . the_opCode == OP_UDIV_4STEP || ( producer . the_opCode == OP_MOV_IRF_DIM && producer . the_is2SrfDst == true ) ) && ( consumer . the_slotID == ISSUE_SLOT_ID_SPU ) ) ) ) { latency = latency + <NUM_LIT> ; } if ( producer_is_fma_accumulator && consumer_is_fma_accumulator && latency == <NUM_LIT> ) { bool SPUSlot = ( consumer . the_slotID == ISSUE_SLOT_ID_SPU ) ; bool VPUSlotSameIdxDst = ( ( consumer . the_slotID == ISSUE_SLOT_ID_VPU ) && ( consumer_idxDst0 == producer_idxDst0 ) ) ; bool atLeastOneAcc = ( consumer_isAccFp32 == <NUM_LIT> || producer_isAccFp32 == <NUM_LIT> ) ; bool isSameLaneBypass = ( SPUSlot || VPUSlotSameIdxDst || ! ( atLeastOneAcc ) ) ; if ( ( producer_isAccFp32 == consumer_isAccFp32 ) && isSameLaneBypass && ( producer . the_isFp16 == consumer . the_isFp16 ) ) latency = <NUM_LIT> ; else { latency = <NUM_LIT> ; } } } } if ( tpc_generation > <NUM_LIT> ) { producer . the_isAccFp32 = producer_isAccFp32 ; consumer . the_isAccFp32 = consumer_isAccFp32 ; producer . the_idxDst0 = producer_idxDst0 ; consumer . the_idxDst0 = consumer_idxDst0 ; producer . the_is2xLookupAddSub = producer_is2xLookupAddSub ; } if ( DEBUG_LATNECIES ) {


<s> LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) . getContext ( ) ; C . emitError ( <STR_LIT> + Err ) ; MI -> print ( errs ( ) ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> ) + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ;

EmitToStreamer ( * OutStreamer , TmpInst ) ;


<s> case FK_PCRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( MBB . empty ( ) ) return false ; MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; if ( MBBI != MBB . begin ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { MachineInstr * PrevMI = prior ( MBBI ) ; if ( PrevMI -> getOpcode ( ) == <STR_LIT> || PrevMI -> getOpcode ( ) == <STR_LIT> ) { MachineOperand & MO = PrevMI -> getOperand ( PrevMI -> getNumOperands ( ) - <NUM_LIT> ) ; if ( MO . getReg ( ) != <STR_LIT> ) return false ; unsigned NewOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; PrevMI -> setDesc ( TII -> get ( NewOpc ) ) ; MO . setReg ( <STR_LIT> ) ; MBB . erase ( MBBI ) ; return true ; } }


<s> unsigned dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; bool isThumb2 = Subtarget -> isThumb2 ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; if ( isThumb2 ) { MRI . constrainRegClass ( dest , & <STR_LIT> ) ; MRI . constrainRegClass ( ptr , & <STR_LIT> ) ; MRI . constrainRegClass ( incr , & <STR_LIT> ) ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , Ord , isThumb2 , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ;

BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> bool <ISA_LIT>BaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;

if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ;


<s> if ( ! Phi -> hasOneUse ( ) ) return false ;

Instruction * U = cast < Instruction > ( * Phi -> user_begin ( ) ) ;


<s> static int avr_operand_rtx_cost ( rtx x , machine_mode mode , enum rtx_code outer , int opno , bool speed ) { enum rtx_code code = GET_CODE ( x ) ; int total ;


<s> if ( decl && const_call_insn_operand ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , VOIDmode ) && mips_call_may_need_jalx_p ( decl ) ) return false ;

if ( decl && TARGET_CALL_SAVED_GP && ! TARGET_ABICALLS_PIC0 && ! targetm . binds_local_p ( decl ) ) return false ;


<s> return makeArrayRef ( <STR_LIT> . begin ( ) , ST . getMaxNumSGPRs ( MF ) ) ;


<s> return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , N0 ) , DAG . getBitcast ( <STR_LIT> , N1 ) ) ) ; } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineLogicBlendIntoPBLENDV ( N , DAG , Subtarget ) ) return R ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . optForSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const {

if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfh ( ) ) return <NUM_LIT> ;


<s> unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDiu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( Amount == <NUM_LIT> ) return ; if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; }


<s> assemble_align ( POINTER_SIZE ) ; if ( TARGET_FDPIC ) { int ok = frv_assemble_integer ( symbol , POINTER_SIZE / BITS_PER_UNIT , <NUM_LIT> ) ; gcc_assert ( ok ) ;


<s> if ( SDValue Val = performUADDVCombine ( N , DAG ) ) return Val ; return performAddSubLongCombine ( N , DCI , DAG ) ;


<s> if ( ! STI . getInstrInfo ( ) -> verifyInstruction ( MI , Err ) ) { errs ( ) << <STR_LIT> << Err << <STR_LIT> ; MI -> dump ( ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = MI ; ++ I ; while ( I != MBB -> end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( I ) ; ++ I ; } } else { MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; AMDGPUInstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * MF -> getSubtarget ( ) . getInstrInfo ( ) , * MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , MF -> getSubtarget ( ) ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; MCObjectStreamer & ObjStreamer = ( MCObjectStreamer & ) OutStreamer ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . EncodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ;


<s> <ISA_LIT>LDCleanup ( const <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) , TII ( nullptr ) , MF ( nullptr ) {


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ;

return CCInfo . CheckReturn ( Outs , CCAssignFnForReturn ( CallConv , isVarArg ) ) ;


<s> SMLoc getEndLoc ( ) const override {


<s> return get<ISA_LIT>ArchVersion ( ) >= V62 ;


<s> unsigned <ISA_LIT>LoadStoreOptimizer :: getNewOpcode ( const CombineInfo & CI ) { const unsigned Width = CI . Width0 + CI . Width1 ; switch ( CI . InstClass ) { default : return <STR_LIT> ( CI . InstClass , Width ) ; case UNKNOWN :


<s> if ( UnitInfos [ U ] . Reg != <NUM_LIT> ) continue ; MCRegUnitRootIterator R ( U , & TRI ) ; assert ( R . isValid ( ) ) ; RegisterId F = * R ; ++ R ; if ( R . isValid ( ) ) { UnitInfos [ U ] . Mask = LaneBitmask :: getAll ( ) ; UnitInfos [ U ] . Reg = F ; } else { for ( MCRegUnitMaskIterator I ( F , & TRI ) ; I . isValid ( ) ; ++ I ) { std :: pair < uint32_t , LaneBitmask > P = * I ; UnitInfo & UI = UnitInfos [ P . first ] ; UI . Reg = F ; if ( P . second . any ( ) ) { UI . Mask = P . second ; } else { if ( const TargetRegisterClass * RC = RegInfos [ F ] . RegClass ) UI . Mask = RC -> LaneMask ; else UI . Mask = LaneBitmask :: getAll ( ) ; } } } } for ( const uint32_t * RM : TRI . getRegMasks ( ) ) RegMasks . insert ( RM ) ; for ( const MachineBasicBlock & B : mf ) for ( const MachineInstr & In : B ) for ( const MachineOperand & Op : In . operands ( ) ) if ( Op . isRegMask ( ) ) RegMasks . insert ( Op . getRegMask ( ) ) ; MaskInfos . resize ( RegMasks . size ( ) + <NUM_LIT> ) ; for ( uint32_t M = <NUM_LIT> , NM = RegMasks . size ( ) ; M <= NM ; ++ M ) { BitVector PU ( TRI . getNumRegUnits ( ) ) ; const uint32_t * MB = RegMasks . get ( M ) ; for ( unsigned i = <NUM_LIT> , e = TRI . getNumRegs ( ) ; i != e ; ++ i ) { if ( ! ( MB [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) ) continue ; for ( MCRegUnitIterator U ( i , & TRI ) ; U . isValid ( ) ; ++ U ) PU . set ( * U ) ; } MaskInfos [ M ] . Units = PU . flip ( ) ; }


<s> emitFrameDirective ( ) ; SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ;


<s> SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; }


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) { unsigned NewImm = Imm ;

for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i != e ; ++ i ) {


<s> return move_by_pieces_ninsns ( size , align , MOVE_MAX_PIECES + <NUM_LIT> ) < ( ! speed_p ? <NUM_LIT> : ( align >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; case STORE_BY_PIECES : case SET_BY_PIECES : return move_by_pieces_ninsns ( size , align , STORE_MAX_PIECES + <NUM_LIT> ) < ( ! speed_p ? <NUM_LIT> : ( align >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; default : return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ; }


<s> return MAX ( GET_MODE_ALIGNMENT ( mode ) , <NUM_LIT> ) ;


<s> unsigned OpNo ; for ( OpNo = <NUM_LIT> ; ! MCID . OpInfo [ OpNo ] . isOptionalDef ( ) && OpNo < MCID . NumOperands ; ++ OpNo ) ; if ( isThumbOne ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> ) return Match_RequiresFlagSetting ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> && ! inITBlock ( ) ) return Match_RequiresITBlock ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; if ( Opc == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; } else if ( isThumbOne ( ) ) { if ( Opc == <STR_LIT> && ! hasV6MOps ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresThumb2 ; else if ( Opc == <STR_LIT> && ! hasV6Ops ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresV6 ; } if ( Opc == <STR_LIT> && ! hasV8Ops ( ) ) { if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresV8 ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return Match_RequiresV8 ; } switch ( Inst . getOpcode ( ) ) {


<s> if ( nios2_large_offset_p ( unspec ) ) return force_reg ( Pmode , nios2_large_got_address ( offset , NULL_RTX ) ) ; return gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , offset ) ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; if ( Dst . isReg ( ) && Dst . getReg ( ) == ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } case <STR_LIT> : case <STR_LIT> :


<s> case AMDGPU :: VCC : switch ( Channel ) { case <NUM_LIT> : return AMDGPU :: VCC_LO ; case <NUM_LIT> : return AMDGPU :: VCC_HI ; default : llvm_unreachable ( <STR_LIT> ) ; } break ;


<s> return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> for ( ArrayRef < int > :: iterator I = ShuffleMask . begin ( ) , E = ShuffleMask . end ( ) ; I != E ; ++ I ) VTBLMask . push_back ( DAG . getConstant ( * I , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & VTBLMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & VTBLMask [ <NUM_LIT> ] , <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>RegisterInfo :: hasReservedCallFrame ( MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> if ( regno == A0_REGNO && mode == SImode && TARGET_A16 ) return <NUM_LIT> ; if ( ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> || mode == PSImode ) && TARGET_A24 ) return nregs_table [ regno ] . pi_regs ;

if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return nregs_table [ regno ] . si_regs ;


<s> if ( ! IsARPop && ListContainsSP ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsPC && ListContainsLR ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( inITBlock ( ) && ! lastInITBlock ( ) && ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasV60TOps ( ) && Subtarget . useHVXOps ( ) && Subtarget . useHVX128BOps ( ) ) RRC = & <STR_LIT> ; else RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> AAAMDFlatWorkGroupSize & AAAMDFlatWorkGroupSize :: createForPosition ( const IRPosition & IRP , Attributor & A ) {

if ( IRP . getPositionKind ( ) == IRPosition :: IRP_FUNCTION ) return * new ( A . Allocator ) AAAMDFlatWorkGroupSize ( IRP , A ) ;


<s> <ISA_LIT>MCAsmInfoELF :: <ISA_LIT>MCAsmInfoELF ( const Triple & TT ) { AssemblerDialect = AD_ATT ; CalleeSaveStackSlotSize = <NUM_LIT> ; CodePointerSize = <NUM_LIT> ; Data64bitsDirective = <STR_LIT> ;

ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> int getVarArgsFrameOffset ( ) const {


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( & ID ) {


<s> MVT VecTy = ty ( VecV ) ; assert ( ! ValTy . isVector ( ) || VecTy . getVectorElementType ( ) == ValTy . getVectorElementType ( ) ) ; unsigned VecWidth = VecTy . getSizeInBits ( ) ; unsigned ValWidth = ValTy . getSizeInBits ( ) ; unsigned ElemWidth = VecTy . getVectorElementType ( ) . getSizeInBits ( ) ; assert ( VecWidth == <NUM_LIT> || VecWidth == <NUM_LIT> ) ; assert ( ( VecWidth % ElemWidth ) == <NUM_LIT> ) ; MVT ScalarTy = tyScalar ( VecTy ) ; VecV = DAG . getBitcast ( ScalarTy , VecV ) ; SDValue WidthV = DAG . getConstant ( ValWidth , dl , <STR_LIT> ) ; SDValue ExtV ;

if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( IdxV ) ) {


<s> Relocator :: Result unsupported ( Relocation & pReloc , <ISA_LIT>_64Relocator & pParent ) { return Relocator :: Unsupported ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & ctx , AsmPrinter & printer ) : Ctx ( ctx ) , Printer ( printer ) , TargetTriple ( printer . getTargetTriple ( ) ) {


<s> BitVector Candidates = TRI -> getAllocatableSet ( * MBB . getParent ( ) , & <STR_LIT> ) ; for ( MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; } BitVector Available = RS . getRegsAvailable ( & <STR_LIT> ) ; Available &= Candidates ; signed Reg = Available . find_first ( ) ; assert ( Reg != - <NUM_LIT> && <STR_LIT> ) ;


<s> } else { Reloc = <STR_LIT> ; DIType * Ty = cast < DIType > ( MD ) ; if ( Ty -> getName ( ) . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; } BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt32Ty ( BB -> getContext ( ) ) ; std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ; GlobalVariable * GV = new GlobalVariable ( * M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , GVName ) ; GV -> addAttribute ( <STR_LIT> ) ; GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , MD ) ; auto * LDInst = new LoadInst ( Type :: getInt32Ty ( BB -> getContext ( ) ) , GV , <STR_LIT> , Call ) ; Instruction * PassThroughInst = <STR_LIT> ( M , BB , LDInst , Call ) ; Call -> replaceAllUsesWith ( PassThroughInst ) ; Call -> eraseFromParent ( ) ; Count ++ ; } return true ;


<s> uint32_t count = <NUM_LIT> ; for ( auto & rec : regRecord ) { if ( rec . fName . compare ( fName ) == <NUM_LIT> ) count ++ ; } return count ;


<s> char buf [ <NUM_LIT> ] ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; fprintf ( file , <STR_LIT> ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; assemble_name ( file , buf ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fputs ( <STR_LIT> , file ) ; } if ( TARGET_PROFILE_KERNEL && crtl -> profile ) { gcc_assert ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) ; gcc_assert ( ! TARGET_32BIT ) ; asm_fprintf ( file , <STR_LIT> , reg_names [ <NUM_LIT> ] ) ; if ( DEFAULT_ABI != ABI_ELFv2 && cfun -> static_chain_decl != NULL ) {


<s> OpBegins . push_back ( <NUM_LIT> ) ;


<s> return Dummy . getValue ( ) . getNode ( ) ; } std :: vector < Constant * > CV ; for ( size_t i = <NUM_LIT> ; i < bvNode -> getNumOperands ( ) ; ++ i ) { ConstantSDNode * V = cast < ConstantSDNode > ( bvNode -> getOperand ( i ) ) ; CV . push_back ( const_cast < ConstantInt * > ( V -> getConstantIntValue ( ) ) ) ; } const Constant * CP = ConstantVector :: get ( CV ) ; SDValue CPIdx = CurDAG -> getConstantPool ( CP , <ISA_LIT>tli . getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue CGPoolOffset = <STR_LIT> ( CPIdx , * CurDAG , TM ) ; HandleSDNode Dummy ( CurDAG -> getLoad ( vecVT , dl , CurDAG -> getEntryNode ( ) , CGPoolOffset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ) ; CurDAG -> ReplaceAllUsesWith ( SDValue ( bvNode , <NUM_LIT> ) , Dummy . getValue ( ) ) ;

if ( SDNode * N = SelectCode ( Dummy . getValue ( ) . getNode ( ) ) ) return N ;


<s> return ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Zero , Zero , LHS , RHS ) ; SDValue Lo ( Hi . getNode ( ) , <NUM_LIT> ) ; SDValue Ops [ ] = { Lo , Hi } ;

return DAG . getMergeValues ( Ops , dl ) ;


<s> return i ; } if ( ( val & <NUM_LIT> ) == <NUM_LIT> || ( val & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; i = <NUM_LIT> ; while ( ( ( val <<= <NUM_LIT> ) & <NUM_LIT> ) != <NUM_LIT> ) ++ i ;


<s> static bool readInstruction48 ( ArrayRef < uint8_t > Bytes , uint64_t Address , uint64_t & Size , uint64_t & Insn ) { Size = <NUM_LIT> ; Insn = ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( ( uint64_t ) Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return true ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const {

BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> case <STR_LIT> : return LowerF64Op ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ;

case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { return new <ISA_LIT>AsmBackend ( false ) ;


<s> Mang = new Mangler ( TM . getDataLayout ( ) ) ; emitHeader ( M , OS1 , STI ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ;


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , bool HasAVX2 ) { return :: isUNPCKH_v_undef_Mask ( N -> getMask ( ) , N -> getValueType ( <NUM_LIT> ) , HasAVX2 ) ;