<s> EVT LoadedVT = LD -> getMemoryVT ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Base ) -> getOffset ( ) ; if ( Offset != <NUM_LIT> && OffsetFitsS11 ( LoadedVT , Offset ) ) { MVT PointerTy = getTargetLowering ( ) -> getPointerTy ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Base ) -> getGlobal ( ) ; SDValue TargAddr = CurDAG -> getTargetGlobalAddress ( GV , dl , PointerTy , <NUM_LIT> ) ; SDNode * NewBase = CurDAG -> getMachineNode ( <STR_LIT> , dl , PointerTy , TargAddr ) ; if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue TargetConstOff = CurDAG -> getTargetConstant ( Offset , PointerTy ) ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , SDValue ( NewBase , <NUM_LIT> ) , TargetConstOff , Chain ) ;

MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ;


<s> static int get_element_number ( tree vec_type , tree arg ) { unsigned HOST_WIDE_INT elt , max = TYPE_VECTOR_SUBPARTS ( vec_type ) - <NUM_LIT> ; if ( ! tree_fits_uhwi_p ( arg ) || ( elt = tree_to_uhwi ( arg ) , elt > max ) ) { error ( <STR_LIT> , max ) ; return <NUM_LIT> ; } return elt ;


<s> EVT AmtVT = Z . getValueType ( ) ; Z = DAG . getNode ( <STR_LIT> , dl , AmtVT , Z , DAG . getConstant ( BitWidth - <NUM_LIT> , dl , AmtVT ) ) ; SDValue SubZ = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , dl , AmtVT ) , Z ) ; X = DAG . getNode ( <STR_LIT> , dl , VT , X , IsFSHL ? Z : SubZ ) ; Y = DAG . getNode ( <STR_LIT> , dl , VT , Y , IsFSHL ? SubZ : Z ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , X , Y ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ; }


<s> static rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG ) addr = XEXP ( addr , <NUM_LIT> ) ;

else if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG ) addr = XEXP ( addr , <NUM_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch ( SMLoc L ) { StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ;


<s> void ReplaceTXF ( CallInst & I ) { Value * Coord = I . getArgOperand ( <NUM_LIT> ) ; Value * ResourceId = I . getArgOperand ( <NUM_LIT> ) ; Value * SamplerId = I . getArgOperand ( <NUM_LIT> ) ; unsigned TextureType = dyn_cast < ConstantInt > ( I . getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;

unsigned SrcSelect [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ;


<s> StackFixup StackFixup :: DiffForHiddenStack ( const Stack & Src , size_t Element , unsigned OutRegister ) { Stack CurrentStack ( Src ) ; StackFixup rv ; rv ( CurrentStack += rv ( pushHidden ( Src . size ( ) + Element , OutRegister ) ) ) ; return rv ;


<s> void <ISA_LIT>FastTileConfig :: rewriteTileCfg ( SmallVector < MachineOperand * > & ShapedTiles , std :: map < unsigned , MachineInstr * > & RowCfgs , std :: map < unsigned , MachineInstr * > & ColCfgs ) { assert ( ( RowCfgs . size ( ) == ShapedTiles . size ( ) ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = ShapedTiles . size ( ) ; I < E ; I ++ ) { MachineOperand * MO = ShapedTiles [ I ] ;

unsigned TmmIdx = getTilePhysRegIdx ( MO ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI . setDesc ( get ( NewOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI . getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI . getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . isPositionIndependent ( ) ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ;


<s> return std :: find ( Caps . begin ( ) , Caps . end ( ) , C ) != Caps . end ( ) ;


return ( __m128i ) __builtin_ia32_pmovsqb256_mask ( ( __v4di ) __A , ( __v16qi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( ! MaybeIdxVal ) return true ; int64_t IdxVal = MaybeIdxVal -> Value . getSExtValue ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Vec = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ins = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT VecTy = MRI . getType ( Vec ) ; LLT EltTy = VecTy . getElementType ( ) ; assert ( EltTy == MRI . getType ( Ins ) ) ; if ( IdxVal < VecTy . getNumElements ( ) ) B . buildInsert ( Dst , Vec , Ins , IdxVal * EltTy . getSizeInBits ( ) ) ; else B . buildUndef ( Dst ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ;

if ( ! TLOF . IsSmallDataEnabled ( ) ) {


<s> break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;

Expr = <ISA_LIT>MCExpr :: create ( Kind , Expr , Ctx ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasDistinctOps ( false ) , HasLoadStoreOnCond ( false ) , HasHighWord ( false ) , HasFPExtension ( false ) , HasFastSerialization ( false ) , HasInterlockedAccess1 ( false ) , TargetTriple ( TT ) , DL ( <STR_LIT> ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , TSInfo ( DL ) , FrameLowering ( ) {


<s> bool hasEIJMPCALL ( ) const { return m_hasEIJMPCALL ;


<s> addPass ( create<ISA_LIT>ProxyRegErasurePass ( ) ) ;


return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) || isLiteralImm ( <STR_LIT> ) || isExpr ( ) ;


<s> return __builtin_neon_vcadd90v4sf ( __a , __b ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const GCNSubtarget & ST ) {


<s> last_insn = emit_insn_after ( gen_nopv ( ) , last_insn ) ; } add_reg_note ( last_insn , REG_SAVE_NOTE , GEN_INT ( <NUM_LIT> ) ) ; loop -> last_insn = last_insn ; iter_reg = loop -> iter_reg ; gcc_assert ( REG_P ( iter_reg ) ) ; entry_edge = NULL ; FOR_EACH_VEC_SAFE_ELT ( loop -> incoming , i , entry_edge ) if ( entry_edge -> flags & EDGE_FALLTHRU ) break ; if ( entry_edge == NULL ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , loop -> loop_no ) ; return false ; } end_label = gen_label_rtx ( ) ; loop -> end_label = end_label ; entry_bb = entry_edge -> src ; start_sequence ( ) ; if ( need_fix ) { emit_insn ( gen_rtx_SET ( lp_reg , iter_reg ) ) ; SET_HARD_REG_BIT ( loop -> regs_set_in_loop , LP_COUNT ) ; iter_reg = lp_reg ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , loop -> loop_no ) ; } } insn = emit_insn ( gen_arc_lp ( loop -> start_label , loop -> end_label ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; entry_after = BB_END ( entry_bb ) ; if ( ! single_succ_p ( entry_bb ) || vec_safe_length ( loop -> incoming ) > <NUM_LIT> || ! entry_after ) { basic_block new_bb ; edge e ; edge_iterator ei ; emit_insn_before ( seq , BB_HEAD ( loop -> head ) ) ; seq = emit_label_before ( gen_label_rtx ( ) , seq ) ; new_bb = create_basic_block ( seq , insn , entry_bb ) ; FOR_EACH_EDGE ( e , ei , loop -> incoming ) { if ( ! ( e -> flags & EDGE_FALLTHRU ) ) redirect_edge_and_branch_force ( e , new_bb ) ; else redirect_edge_succ ( e , new_bb ) ; } make_edge ( new_bb , loop -> head , <NUM_LIT> ) ; } else { while ( DEBUG_INSN_P ( entry_after ) || ( NOTE_P ( entry_after ) && NOTE_KIND ( entry_after ) != NOTE_INSN_BASIC_BLOCK && NOTE_KIND ( entry_after ) != NOTE_INSN_CALL_ARG_LOCATION ) ) entry_after = NEXT_INSN ( entry_after ) ; entry_after = next_nonnote_insn_bb ( entry_after ) ;


<s> const <ISA_LIT>TargetMachine & getTargetMachine ( ) {

return static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ;


<s> <ISA_LIT>BaseRegisterInfo :: <ISA_LIT>BaseRegisterInfo ( const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , STI ( sti ) , FramePtr ( ( STI . isTargetMachO ( ) || STI . isThumb ( ) ) ? <STR_LIT> : <STR_LIT> ) , BasePtr ( <STR_LIT> ) {


<s> const MachineInstr * DefInst = Def . getParent ( ) ; if ( ! TII -> isFoldableCopy ( * DefInst ) || ! isSameBB ( Op . getParent ( ) , DefInst ) ) return None ; const MachineOperand & Copied = DefInst -> getOperand ( <NUM_LIT> ) ; if ( ! Copied . isImm ( ) ) return None ; return Copied . getImm ( ) ;


<s> Register UsedSGPRs [ <NUM_LIT> ] = { <STR_LIT> } ; const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = OpIndices [ i ] ; if ( Idx == - <NUM_LIT> ) break ; const MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) continue ; const TargetRegisterClass * OpRC = RI . getRegClass ( Desc . OpInfo [ Idx ] . RegClass ) ; bool IsRequiredSGPR = RI . isSGPRClass ( OpRC ) ; if ( IsRequiredSGPR ) return MO . getReg ( ) ; Register Reg = MO . getReg ( ) ; const TargetRegisterClass * RegRC = MRI . getRegClass ( Reg ) ; if ( RI . isSGPRClass ( RegRC ) ) UsedSGPRs [ i ] = Reg ; } if ( UsedSGPRs [ <NUM_LIT> ] != <STR_LIT> ) { if ( UsedSGPRs [ <NUM_LIT> ] == UsedSGPRs [ <NUM_LIT> ] || UsedSGPRs [ <NUM_LIT> ] == UsedSGPRs [ <NUM_LIT> ] ) SGPRReg = UsedSGPRs [ <NUM_LIT> ] ; } if ( SGPRReg == <STR_LIT> && UsedSGPRs [ <NUM_LIT> ] != <STR_LIT> ) { if ( UsedSGPRs [ <NUM_LIT> ] == UsedSGPRs [ <NUM_LIT> ] ) SGPRReg = UsedSGPRs [ <NUM_LIT> ] ;


<s> mask &= ( GOMP_DIM_MASK ( GOMP_DIM_WORKER ) | GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ;


<s> if ( VT . isInteger ( ) && ! VT . isVector ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else return false ; const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; unsigned Src1Reg = getRegForValue ( SI -> getTrueValue ( ) ) ; unsigned Src2Reg = getRegForValue ( SI -> getFalseValue ( ) ) ; unsigned CondReg = getRegForValue ( Cond ) ; if ( ! Src1Reg || ! Src2Reg || ! CondReg ) return false ; unsigned ZExtCondReg = createResultReg ( & <STR_LIT> ) ; if ( ! ZExtCondReg ) return false ; if ( ! emitIntExt ( <STR_LIT> , CondReg , <STR_LIT> , ZExtCondReg , true ) ) return false ; unsigned ResultReg = createResultReg ( RC ) ; unsigned TempReg = createResultReg ( RC ) ; if ( ! ResultReg || ! TempReg ) return false ; emitInst ( TargetOpcode :: COPY , TempReg ) . addReg ( Src2Reg ) ; emitInst ( CondMovOpc , ResultReg ) . addReg ( Src1Reg ) . addReg ( ZExtCondReg ) . addReg ( TempReg ) ;


<s> RegisterRef LRExtRR ; NodeId LRExtRegRD = <NUM_LIT> ; for ( NodeAddr < UseNode * > UA : SN . Addr -> members_if ( DFG -> IsUse , * DFG ) ) { RegisterRef RR = UA . Addr -> getRegRef ( * DFG ) ; if ( LRExtReg == RR . Reg ) { LRExtRR = RR ; LRExtRegRD = UA . Addr -> getReachingDef ( ) ; } } for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UA = * I ; NodeAddr < InstrNode * > IA = UA . Addr -> getOwner ( * DFG ) ; if ( UA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) return false ; NodeAddr < RefNode * > AA = LV -> getNearestAliasedRef ( LRExtRR , IA ) ; if ( ( DFG -> IsDef ( AA ) && AA . Id != LRExtRegRD ) || AA . Addr -> getReachingDef ( ) != LRExtRegRD ) {


<s> rtx off ; if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , <NUM_LIT> ) ; switch ( GET_CODE ( x ) ) { case PLUS : off = XEXP ( x , <NUM_LIT> ) ; output_address ( XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ; output_address ( off ) ; break ; case SYMBOL_REF : case LABEL_REF : output_addr_const ( file , x ) ; break ; default : gcc_assert ( GET_CODE ( x ) != MEM ) ; nvptx_print_operand ( file , x , <NUM_LIT> ) ; break ; }


<s> static bool shouldScheduleAdjacent ( const TargetInstrInfo & TII , const TargetSubtargetInfo & TSI , const MachineInstr * FirstMI , const MachineInstr & SecondMI ) { const <ISA_LIT>Subtarget & ST = static_cast < const <ISA_LIT>Subtarget & > ( TSI ) ; unsigned FirstOpc = FirstMI ? FirstMI -> getOpcode ( ) : static_cast < unsigned > ( <STR_LIT> ) ; unsigned SecondOpc = SecondMI . getOpcode ( ) ; if ( ST . hasArithmeticBccFusion ( ) && isArithmeticBccPair ( FirstOpc , SecondOpc , FirstMI ) ) return true ; if ( ST . hasArithmeticCbzFusion ( ) && isArithmeticCbzPair ( FirstOpc , SecondOpc , FirstMI ) ) return true ; if ( ST . hasFuseAES ( ) && isAESPair ( FirstOpc , SecondOpc ) ) return true ; if ( ST . hasFuseCryptoEOR ( ) && isCryptoEORPair ( FirstOpc , SecondOpc ) ) return true ;

if ( ST . hasFuseLiterals ( ) && isLiteralsPair ( FirstOpc , SecondOpc , FirstMI , SecondMI ) ) return true ;


<s> IRBuilder < > Builder ( InsertAtEnd ) ; Value * Idx [ <NUM_LIT> ] ; Idx [ <NUM_LIT> ] = Builder . getInt32 ( <NUM_LIT> ) ;

Idx [ <NUM_LIT> ] = Builder . getInt32 ( getTranslator ( ) . getRegSetDesc ( ) . RegOffsetsInSet [ getTranslator ( ) . getRegSetDesc ( ) . RegLargestSupers [ <STR_LIT> ] ] ) ;


<s> return new ELF<ISA_LIT>AsmBackend ( T , STI . getTargetTriple ( ) . getOS ( ) ) ;


<s> else { s << <STR_LIT> << ID ; } return s . str ( ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeRelCondBrTarget ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( Fixup ) , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } assert ( MO . isImm ( ) ) ; auto target = MO . getImm ( ) ;

<STR_LIT> :: adjustBranchTarget ( target ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ;


<s> static SDValue combineSExt ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ;


<s> const BasicBlock * getBBHead ( ) { return BB ;


<s> return false ; } if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : PrintMemReference ( MI , OpNo , O , <STR_LIT> ) ; return false ; case 'P' : PrintMemReference ( MI , OpNo , O , <STR_LIT> ) ; return false ; }


for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( CVX64Regs ) ; ++ I ) MRI -> mapLLVMRegToCVReg ( CVX64Regs [ I ] , CVX64RegStart + I ) ;


<s> for ( auto * U : V -> users ( ) ) Worklist . push_back ( U ) ; while ( ! Worklist . empty ( ) ) { auto * U = Worklist . pop_back_val ( ) ; if ( isa < ConstantExpr > ( U ) ) { for ( auto * UU : U -> users ( ) ) Worklist . push_back ( UU ) ; continue ; } auto * I = dyn_cast < Instruction > ( U ) ;

if ( ! I || I -> getParent ( ) -> getParent ( ) != F ) return false ;


<s> MachineInstrBuilder buildMI ( Block & MBB , BlockIt MBBI , unsigned Opcode , unsigned DstReg ) {

return BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( Opcode ) , DstReg ) ;


return ( __m128i ) __builtin_ia32_pmovdw256_mask ( ( __v8si ) __A , ( __v8hi ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return ( unsigned char ) __builtin_ia32_kortestzqi ( __A , __B ) ;


<s> InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } if ( genExecuteOnly ) { unsigned Type = ELF :: SHT_PROGBITS ; unsigned Flags = ELF :: SHF_EXECINSTR | ELF :: SHF_ALLOC | ELF :: SHF_<ISA_LIT>_PURECODE ;

TextSection = Ctx . getELFSection ( <STR_LIT> , Type , Flags , <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> HOST_WIDE_INT size ; tree section_name ; if ( TREE_CODE ( decl ) != VAR_DECL || DECL_ARTIFICIAL ( decl ) ) return false ; section_name = DECL_SECTION_NAME ( decl ) ; if ( section_name ) { gcc_assert ( TREE_CODE ( section_name ) == STRING_CST ) ; if ( frv_string_begins_with ( section_name , <STR_LIT> ) ) return true ; if ( frv_string_begins_with ( section_name , <STR_LIT> ) ) return true ; return false ; } size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ;

if ( size > <NUM_LIT> && ( unsigned HOST_WIDE_INT ) size <= g_switch_value ) return true ;


<s> AllowSwitchFromAlu = true ; } else { unsigned NeededWF = <NUM_LIT> / ALUFetchRationEstimate ; LLVM_DEBUG ( dbgs ( ) << NeededWF << <STR_LIT> ) ; unsigned NearRegisterRequirement = <NUM_LIT> * Available [ IDFetch ] . size ( ) ; if ( NeededWF > getWFCountLimitedByGPR ( NearRegisterRequirement ) ) AllowSwitchFromAlu = true ; } } if ( ! SU && ( ( AllowSwitchToAlu && CurInstKind != IDAlu ) || ( ! AllowSwitchFromAlu && CurInstKind == IDAlu ) ) ) { SU = pickAlu ( ) ; if ( ! SU && ! PhysicalRegCopy . empty ( ) ) { SU = PhysicalRegCopy . front ( ) ; PhysicalRegCopy . erase ( PhysicalRegCopy . begin ( ) ) ;


<s> find_regmode_weight ( b -> index , SFmode ) ;


<s> return D ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> unsigned Idx = CurrGroupSize ; if ( GrpCount % <NUM_LIT> ) Idx += <NUM_LIT> ; return Idx ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; } case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> :


<s> if ( IDVal == <STR_LIT> ) return ParseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( <STR_LIT> ) ) return ParseDirectiveCode ( IDVal , DirectiveID . getLoc ( ) ) ; return true ;


<s> unsigned ResultReg = <NUM_LIT> ; if ( RetVT == CopyVT ) { const TargetRegisterClass * CpyRC = TLI . getRegClassFor ( CopyVT ) ; ResultReg = createResultReg ( CpyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SourcePhysReg ) ; } else if ( CopyVT == <STR_LIT> ) { ResultReg = createResultReg ( TLI . getRegClassFor ( RetVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( SourcePhysReg ) ; } else if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) { ResultReg = createResultReg ( & <STR_LIT> ) ; SourcePhysReg -= <STR_LIT> - <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SourcePhysReg ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> mem = gen_frame_mem ( GET_MODE ( reg ) , addr ) ;

return gen_rtx_SET ( store ? mem : reg , store ? reg : mem ) ;


<s> last = first + rounded_size ; emit_insn ( gen_probe_stack_range ( Pmode , sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) , rounded_size - size ) ) ; release_scratch_register_on_entry ( & sr , size , true ) ; }


<s> MachineInstr * RegSeq = <NUM_LIT> ; for ( unsigned R = <NUM_LIT> ; R < NumRegs ; ++ R ) { const MachineOperand & MO = MI -> getOperand ( FirstOpnd + R ) ; assert ( MO . isReg ( ) && MO . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned VirtReg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isVirtualRegister ( VirtReg ) && <STR_LIT> ) ; if ( ! MRI -> hasOneNonDBGUse ( VirtReg ) ) return false ; MachineInstr * UseMI = & * MRI -> use_nodbg_begin ( VirtReg ) ; if ( ! UseMI -> isRegSequence ( ) ) return false ; if ( RegSeq && RegSeq != UseMI ) return false ; unsigned OpIdx = <NUM_LIT> + ( Offset + R * Stride ) * <NUM_LIT> ; if ( UseMI -> getOperand ( OpIdx ) . getReg ( ) != VirtReg ) llvm_unreachable ( <STR_LIT> ) ; unsigned SubIdx = UseMI -> getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; if ( LastSubIdx ) { if ( LastSubIdx != SubIdx - Stride ) return false ; } else { if ( SubIdx != ( <STR_LIT> + Offset ) && SubIdx != ( <STR_LIT> + Offset ) ) return false ; } RegSeq = UseMI ; LastSubIdx = SubIdx ; } if ( NumRegs == <NUM_LIT> ) { unsigned OpIdx = <NUM_LIT> + ( Offset + <NUM_LIT> * Stride ) * <NUM_LIT> ; const MachineOperand & MO = RegSeq -> getOperand ( OpIdx ) ; unsigned VirtReg = MO . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( VirtReg ) ; if ( ! DefMI || ! DefMI -> isImplicitDef ( ) ) return false ; } return true ;


<s> auto & Ctx = MIRBuilder . getMF ( ) . getFunction ( ) -> getContext ( ) ; assert ( ( OpSize == <NUM_LIT> || OpSize == <NUM_LIT> ) && <STR_LIT> ) ; auto * ArgTy = OpSize == <NUM_LIT> ? Type :: getFloatTy ( Ctx ) : Type :: getDoubleTy ( Ctx ) ; auto * RetTy = Type :: getInt32Ty ( Ctx ) ; SmallVector < unsigned , <NUM_LIT> > Results ; for ( auto Libcall : Libcalls ) { auto LibcallResult = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildConstant ( Zero , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred , ProcessedResult , LibcallResult , Zero ) ; } Results . push_back ( ProcessedResult ) ; }

if ( Results . size ( ) != <NUM_LIT> ) {


<s> bool hasWAITPKG ( ) const { return HasWAITPKG ;


<s> return DCI . DAG . getConstant ( - <NUM_LIT> , dl , ty ( Op ) ) ; case <STR_LIT> : return getZero ( dl , ty ( Op ) , DCI . DAG ) ; default : break ; } } else if ( Opc == <STR_LIT> ) { SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; if ( Cond -> getOpcode ( ) == <STR_LIT> ) { SDValue C0 = Cond . getOperand ( <NUM_LIT> ) , C1 = Cond . getOperand ( <NUM_LIT> ) ; if ( C1 -> getOpcode ( ) == <STR_LIT> ) { SDValue VSel = DCI . DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , C0 , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return VSel ; } } } return SDValue ( ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res ;


<s> assert ( Store && Store -> getValue ( ) . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; if ( allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , Store -> getMemoryVT ( ) , * Store -> getMemOperand ( ) ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue StoredVal = Store -> getValue ( ) ; MVT VT = StoredVal . getSimpleValueType ( ) ; unsigned EltSizeBits = VT . getScalarSizeInBits ( ) ; assert ( ( EltSizeBits == <NUM_LIT> || EltSizeBits == <NUM_LIT> || EltSizeBits == <NUM_LIT> ) && <STR_LIT> ) ; MVT NewVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * ( EltSizeBits / <NUM_LIT> ) ) ; assert ( NewVT . isValid ( ) && <STR_LIT> ) ; StoredVal = DAG . getBitcast ( NewVT , StoredVal ) ;

return DAG . getStore ( Store -> getChain ( ) , DL , StoredVal , Store -> getBasePtr ( ) , Store -> getPointerInfo ( ) , Store -> getOriginalAlign ( ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ;


static const std :: pair < unsigned , const char * > TargetFlags [ ] = {


<s> switch ( code ) { case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATERT : case PLUS : case MINUS : case COMPARE : case NEG : case NOT : return COSTS_N_INSNS ( <NUM_LIT> ) ; case MULT : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { int cycles = <NUM_LIT> ; unsigned HOST_WIDE_INT i = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; while ( i ) { i >>= <NUM_LIT> ; cycles ++ ; } return COSTS_N_INSNS ( <NUM_LIT> ) + cycles ; } return COSTS_N_INSNS ( <NUM_LIT> ) + <NUM_LIT> ; case SET : return ( COSTS_N_INSNS ( <NUM_LIT> ) + <NUM_LIT> * ( ( GET_CODE ( SET_SRC ( x ) ) == MEM ) + GET_CODE ( SET_DEST ( x ) ) == MEM ) ) ; case CONST_INT : if ( outer == SET ) { if ( ( unsigned HOST_WIDE_INT ) INTVAL ( x ) < <NUM_LIT> ) return <NUM_LIT> ; if ( thumb_shiftable_const ( INTVAL ( x ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> SDLoc dl ( Op ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , dl , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ;


<s> PreservedAnalyses <ISA_LIT>LoopIdiomRecognitionPass :: run ( Loop & L , LoopAnalysisManager & AM , LoopStandardAnalysisResults & AR , LPMUpdater & U ) {

return <ISA_LIT>LoopIdiomRecognize ( & AR . AA , & AR . DT , & AR . LI , & AR . TLI , & AR . SE ) . run ( & L ) ? getLoopPassPreservedAnalyses ( ) : PreservedAnalyses :: all ( ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < LN ; ++ i ) { bool Eval = constToInt ( LSL . Values [ i ] , LoVs [ i ] ) ; if ( ! Eval ) return false ; assert ( LoVs [ i ] . getBitWidth ( ) == <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < HN ; ++ i ) { bool Eval = constToInt ( LSH . Values [ i ] , HiVs [ i ] ) ; if ( ! Eval ) return false ; assert ( HiVs [ i ] . getBitWidth ( ) == <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < HiVs . size ( ) ; ++ i ) { APInt HV = HiVs [ i ] . zextOrSelf ( <NUM_LIT> ) << <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < LoVs . size ( ) ; ++ j ) { APInt LV = LoVs [ j ] . zextOrSelf ( <NUM_LIT> ) ; const Constant * C = intToConst ( HV | LV ) ; Result . add ( C ) ; if ( Result . isBottom ( ) ) return false ; } } return ! Result . isBottom ( ) ;


<s> bool hasRegisterBanking ( ) const { return HasRegisterBanking ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ;

if ( TFI -> hasFP ( * MF ) ) return CalleeSavedRegsFP ;


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;

if ( Opcode == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ) return true ;


<s> if ( isGFX940 ( ) ) return true ; uint64_t TSFlags = MII . get ( Inst . getOpcode ( ) ) . TSFlags ;

if ( ( TSFlags & ( <STR_LIT> | <STR_LIT> ) ) != ( <STR_LIT> | <STR_LIT> ) ) return true ;


<s> if ( VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ) { MVT LocVT = VA . getLocVT ( ) ; MVT ValVT = VA . getValVT ( ) ; if ( VA . getValVT ( ) == <STR_LIT> || VA . getValVT ( ) == <STR_LIT> ) { std :: swap ( ValVT , LocVT ) ; MemSize = VA . getValVT ( ) . getStoreSize ( ) ; } ValVReg = extendRegister ( ValVReg , VA , MaxSize ) ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBits ( ) < LocVT . getSizeInBits ( ) ) ValVReg = MIRBuilder . buildTrunc ( RegTy , ValVReg ) . getReg ( <NUM_LIT> ) ; } else {


<s> for ( unsigned BTI = <NUM_LIT> , BTE = Block . NumTerminators ; BTI != BTE ; ++ BTI ) { skipTerminator ( Position , * TI , true ) ;


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ; return MCDisassembler :: Success ;


<s> if ( regno == C_REG || regno == B_REG || regno == E_REG || regno == L_REG ) return true ; return false ;


<s> if ( ( reload_in_progress || reload_completed ) && ! strict_memory_address_p ( Pmode , XEXP ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ;

if ( lra_in_progress && ! memory_address_p ( Pmode , XEXP ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ;


<s> setForcedEncodingSize ( <NUM_LIT> ) ; if ( Name . endswith ( <STR_LIT> ) ) setForcedEncodingSize ( <NUM_LIT> ) ; else if ( Name . endswith ( <STR_LIT> ) ) setForcedEncodingSize ( <NUM_LIT> ) ; Operands . push_back ( AMDGPUOperand :: CreateToken ( Name , NameLoc ) ) ; while ( ! getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { AMDGPUAsmParser :: OperandMatchResultTy Res = parseOperand ( Operands , Name ) ; if ( getLexer ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ; switch ( Res ) { case MatchOperand_Success : break ; case MatchOperand_ParseFail : return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; case MatchOperand_NoMatch : return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; } }

AMDGPUAsmParser :: OperandMatchResultTy Res ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> vqmovn_high_s32 ( int16x4_t a , int32x4_t b ) { int16x8_t result = vcombine_s16 ( a , vcreate_s16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( b ) : ) ;


<s> if ( GlobalBaseReg ) return GlobalBaseReg ; if ( FixGlobalBaseReg ) return GlobalBaseReg = <STR_LIT> ;


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>BETarget ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getTheThumbLETarget ( ) , create<ISA_LIT>Disassembler ) ;

TargetRegistry :: RegisterMCDisassembler ( getTheThumbBETarget ( ) , create<ISA_LIT>Disassembler ) ;


<s> if ( MFI . isFixedObjectIndex ( FI ) ) FrameReg = hasFP ( MF ) ? ABI . GetFramePtr ( ) : ABI . GetStackPtr ( ) ;

else FrameReg = hasBP ( MF ) ? ABI . GetBasePtr ( ) : ABI . GetStackPtr ( ) ;


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ;

int FI = MFI . CreateFixedObject ( Size , Offset , true ) ;


<s> static tree spu_handle_fndecl_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( <NUM_LIT> , <STR_LIT> , name ) ; * no_add_attrs = true ; }


<s> return __builtin_loongson_pandn_sd ( s , t ) ;


<s> if ( Desc . TSFlags & <STR_LIT> ) printRptDirective ( MI , O ) ; if ( ! printAliasInstr ( MI , Address , O ) ) printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ;


<s> assert ( I . getOpcode ( ) == TargetOpcode :: G_ASHR || I . getOpcode ( ) == TargetOpcode :: G_LSHR ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; bool IsASHR = I . getOpcode ( ) == TargetOpcode :: G_ASHR ; unsigned Opc = <NUM_LIT> ; unsigned NegOpc = <NUM_LIT> ; const TargetRegisterClass * RC = getRegClassForTypeOnBank ( Ty , RBI . getRegBank ( <STR_LIT> ) , RBI ) ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> if ( I . getOperand ( <NUM_LIT> ) . getIntrinsicID ( ) != <STR_LIT> ) return false ;

BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ;


<s> unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; ArrayRef < MCPhysReg > ByValArgRegs = ABI . GetByValArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( ( ByValArgRegs . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! NumRegs ) return ; MVT RegTy = <STR_LIT> ( GPRSizeInBytes * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ;

for ( unsigned I = <NUM_LIT> ; I < NumRegs ; ++ I ) {


<s> for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { const MachineOperand & MO = * I ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isDef ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) DstMI = Reg ;

else DstMI = TRI -> getMatchingSuperReg ( Reg , <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( TRI -> getHWRegChan ( Reg ) ) , & <STR_LIT> ) ;


<s> bool HasEVEX = ( TSFlags & <STR_LIT> ) == <STR_LIT> ; int CD8_Scale = ( TSFlags & <STR_LIT> ) >> <STR_LIT> ; if ( ! HasEVEX || CD8_Scale == <NUM_LIT> ) return isInt < <NUM_LIT> > ( Value ) ; assert ( isPowerOf2_32 ( CD8_Scale ) && <STR_LIT> ) ;

if ( Value & ( CD8_Scale - <NUM_LIT> ) ) return false ;


<s> EVT Type = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Two = DAG . getConstantFP ( <NUM_LIT> , DL , Type ) ; SDValue Denominator = Op . getOperand ( <NUM_LIT> ) ; SDValue Estimate = DAG . getNode ( <STR_LIT> , DL , Type , Denominator ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue Trial = DAG . getNode ( <STR_LIT> , DL , Type , Estimate , Denominator ) ; SDValue Error = DAG . getNode ( <STR_LIT> , DL , Type , Two , Trial ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , Type , Estimate , Error ) ; } bool IsOne = false ; if ( Type . isVector ( ) ) { if ( isSplatVector ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; IsOne = C && C -> isExactlyValue ( <NUM_LIT> ) ;


<s> static inline void desc_reg_gr ( unsigned char reg , unsigned char dst , struct unw_state_record * sr ) {

set_reg ( sr -> curr . reg + reg , UNW_WHERE_GR , sr -> region_start + sr -> region_len - <NUM_LIT> , dst ) ;


<s> if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; if ( FloatBits != <NUM_LIT> && FloatBits != <NUM_LIT> ) return SDValue ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; if ( IntBits != <NUM_LIT> && IntBits != <NUM_LIT> && IntBits != <NUM_LIT> ) return SDValue ( ) ; if ( IntBits > FloatBits ) return SDValue ( ) ; BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t Bits = IntBits == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , Bits + <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > Bits ) return SDValue ( ) ; MVT ResTy ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; switch ( NumLanes ) { default : return SDValue ( ) ; case <NUM_LIT> : ResTy = FloatBits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ResTy = <STR_LIT> ; break ; } SDLoc DL ( N ) ; bool IsSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = IsSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , DL , ResTy , DAG . getConstant ( IntrinsicOpcode , DL , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , DL , <STR_LIT> ) ) ; if ( IntBits < FloatBits ) FixConv = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , FixConv ) ;


<s> SDValue SplatVal ; if ( ! ( ShiftVec = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) || ! ( SplatVal = ShiftVec -> getSplatValue ( ) ) ) return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; ConstantSDNode * SplatConst = dyn_cast < ConstantSDNode > ( SplatVal ) ; if ( ! SplatConst || Op . getSimpleValueType ( ) != <STR_LIT> ) return Op ; unsigned Opcode ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> getDispOpValue ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , <STR_LIT> Kind ) const { const MCOperand & MO = MI . getOperand ( OpNum ) ; if ( MO . isImm ( ) ) return static_cast < uint64_t > ( MO . getImm ( ) ) ; if ( MO . isExpr ( ) ) { unsigned ByteOffs = Fixups . size ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; Fixups . push_back ( MCFixup :: create ( ByteOffs , MO . getExpr ( ) , ( MCFixupKind ) Kind ) ) ; assert ( Fixups . size ( ) <= <NUM_LIT> && <STR_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ;


<s> unsigned NumElts = SrcVT . getVectorNumElements ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; SDValue Mid , SplitLo , SplitHi , ExtLo , ExtHi ; EVT MidVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , SrcEltSize * <NUM_LIT> ) , NumElts ) ; EVT SplitVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , SrcEltSize * <NUM_LIT> ) , NumElts / <NUM_LIT> ) ; EVT ExtVT = EVT :: getVectorVT ( Ctx , EVT :: getIntegerVT ( Ctx , DestEltSize ) , NumElts / <NUM_LIT> ) ; Mid = DAG . getNode ( N -> getOpcode ( ) , dl , MidVT , Op ) ;

SplitLo = DAG . getNode ( <STR_LIT> , dl , SplitVT , Mid , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; x = arc_delegitimize_address_0 ( x ) ; if ( ! x ) return orig_x ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ;


<s> case AMDGPU :: TEX_SAMPLE_L : case AMDGPU :: TEX_SAMPLE_C_L : case AMDGPU :: TEX_SAMPLE_LB : case AMDGPU :: TEX_SAMPLE_C_LB : case AMDGPU :: TEX_SAMPLE_G : case AMDGPU :: TEX_SAMPLE_C_G : case AMDGPU :: TEX_GET_GRADIENTS_H : case AMDGPU :: TEX_GET_GRADIENTS_V :


<s> return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ;


<s> if ( auto E = Obj . takeError ( ) ) return std :: move ( E ) ;

std :: unique_ptr < HSACodeObject > Ret ( new HSACodeObject ( std :: move ( * Obj ) ) ) ;


<s> case FB_REGNO : case SP_REGNO : return <NUM_LIT> ; default : if ( IS_PSEUDO ( patternr [ <NUM_LIT> ] , strict ) ) return <NUM_LIT> ; return <NUM_LIT> ; } } if ( RTX_IS ( <STR_LIT> ) ) { int rn = REGNO ( patternr [ <NUM_LIT> ] ) ; HOST_WIDE_INT offs = INTVAL ( patternr [ <NUM_LIT> ] ) ; switch ( rn ) { case A0_REGNO : case A1_REGNO : case SB_REGNO : if ( TARGET_A16 ) return ( offs >= - <NUM_LIT> && offs <= <NUM_LIT> - mode_adjust ) ; if ( rn == SB_REGNO ) return ( offs >= <NUM_LIT> && offs <= <NUM_LIT> - mode_adjust ) ; return ( offs >= - <NUM_LIT> && offs <= <NUM_LIT> ) ; case FB_REGNO : if ( TARGET_A16 ) return ( offs >= - <NUM_LIT> && offs <= <NUM_LIT> - mode_adjust ) ; return ( offs >= - <NUM_LIT> && offs <= <NUM_LIT> - mode_adjust ) ; case SP_REGNO : return ( offs >= - <NUM_LIT> && offs <= <NUM_LIT> - mode_adjust ) ; default : if ( IS_PSEUDO ( patternr [ <NUM_LIT> ] , strict ) ) return <NUM_LIT> ; return <NUM_LIT> ; } } if ( RTX_IS ( <STR_LIT> ) || RTX_IS ( <STR_LIT> ) ) { rtx reg = patternr [ <NUM_LIT> ] ; switch ( REGNO ( reg ) ) { case A0_REGNO : case A1_REGNO : return <NUM_LIT> ; default : if ( IS_PSEUDO ( reg , strict ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ; case <STR_LIT> : O << <STR_LIT> ; return ;


<s> unsigned <ISA_LIT>MachineFunctionInfo :: addImplicitBufferPtr ( const <ISA_LIT>RegisterInfo & TRI ) { ImplicitBufferPtrUserSGPR = TRI . getMatchingSuperReg ( getNextUserSGPR ( ) , <STR_LIT> , & <STR_LIT> ) ; NumUserSGPRs += <NUM_LIT> ; return ImplicitBufferPtrUserSGPR ;


<s> f_skip = TREE_CHAIN ( f_args ) ; args = build3 ( COMPONENT_REF , TREE_TYPE ( f_args ) , valist , f_args , NULL_TREE ) ; skip = build3 ( COMPONENT_REF , TREE_TYPE ( f_skip ) , valist , f_skip , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( args ) , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , UNITS_PER_WORD * ( crtl -> args . info - TILEPRO_NUM_ARG_REGS ) ) ; if ( crtl -> args . pretend_args_size > <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , - STACK_POINTER_OFFSET ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( args ) , args , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( skip ) , virtual_incoming_args_rtx ) ; t = fold_build_pointer_plus_hwi ( t , - STACK_POINTER_OFFSET ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( skip ) , skip , t ) ;


<s> if ( isTopOfStack ( BB ) ) closeControlFlow ( BB ) ; continue ; } if ( I . nodeVisited ( Term -> getSuccessor ( <NUM_LIT> ) ) ) { if ( isTopOfStack ( BB ) ) closeControlFlow ( BB ) ; handleLoop ( Term ) ; continue ; } if ( isTopOfStack ( BB ) ) { PHINode * Phi = dyn_cast < PHINode > ( Term -> getCondition ( ) ) ; if ( Phi && Phi -> getParent ( ) == BB && isElse ( Phi ) ) { insertElse ( Term ) ; eraseIfUnused ( Phi ) ; continue ; }


<s> for ( int i = <NUM_LIT> ; i < Half ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , NumElems , NumElems * <NUM_LIT> ) ) return false ; for ( int i = Half ; i < NumElems ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , NumElems ) ) return false ; return true ;


<s> const char * <ISA_LIT>MCAsmInfo :: getDataASDirective ( unsigned Size , unsigned AS ) const { if ( AS != <STR_LIT> ) return <NUM_LIT> ; switch ( Size ) { case <NUM_LIT> : return RomData8bitsDirective ;

case <NUM_LIT> : return RomData16bitsDirective ;


<s> DAG . computeKnownBits ( X , Known ) ; unsigned LZ = Known . countMinLeadingZeros ( ) ; if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } case <STR_LIT> : if ( ! isOrEquivalentToAdd ( DAG , LHS ) ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : { if ( ConstantSDNode * C2 = dyn_cast < ConstantSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) ) { SDValue Shl = DAG . getNode ( <STR_LIT> , SL , VT , LHS -> getOperand ( <NUM_LIT> ) , SDValue ( RHS , <NUM_LIT> ) ) ; SDValue C2V = DAG . getConstant ( C2 -> getAPIntValue ( ) << RHSVal , SDLoc ( C2 ) , VT ) ; return DAG . getNode ( LHS -> getOpcode ( ) , SL , VT , Shl , C2V ) ; } break ; } } if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( RHSVal < <NUM_LIT> ) return SDValue ( ) ; SDValue ShiftAmt = DAG . getConstant ( RHSVal - <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LHS ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo , ShiftAmt ) ; const SDValue Zero = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ;

SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { Zero , NewShift } ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Module & M , const std :: string & FS ) : DataLayout ( <STR_LIT> ) , Subtarget ( M , FS ) , TLInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> static void mips_end_function_definition ( const char * name ) {


<s> <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCContext & Ctx , MCStreamer & Streamer , const MCAsmInfo * MAI ) : AsmPrinter ( O , TM , Ctx , Streamer , MAI ) {


<s> assert ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getTargetConstant ( SplatBits , <STR_LIT> ) ; case <NUM_LIT> : if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits , <STR_LIT> ) ; break ; case <NUM_LIT> : if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> || ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits , <STR_LIT> ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits | <NUM_LIT> , <STR_LIT> ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) return DAG . getTargetConstant ( SplatBits | <NUM_LIT> , <STR_LIT> ) ; break ; case <NUM_LIT> : { uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) Val |= BitMask ; else if ( ( SplatBits & BitMask ) != <NUM_LIT> ) return SDValue ( ) ; BitMask <<= <NUM_LIT> ; } return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } default :


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { unsigned BitSize = N . getValueType ( ) . getSizeInBits ( ) ; unsigned Val = RHS -> getZExtValue ( ) & ( BitSize - <NUM_LIT> ) ;

unsigned ShVal = <STR_LIT> ( ShType , Val ) ;


<s> if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ;

if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ;


<s> const char * getPassName ( ) const override {


<s> Out . EmitInstruction ( Inst , STI ) ; return false ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FramePointerSaveIndex ( <NUM_LIT> ) , ReturnAddrSaveIndex ( <NUM_LIT> ) , BasePointerSaveIndex ( <NUM_LIT> ) , PICBasePointerSaveIndex ( <NUM_LIT> ) , HasSpills ( false ) , HasNonRISpills ( false ) , SpillsCR ( false ) , SpillsVRSAVE ( false ) , LRStoreRequired ( false ) , UsesTOCBasePtr ( false ) , MinReservedArea ( <NUM_LIT> ) , TailCallSPDelta ( <NUM_LIT> ) , HasFastCall ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgsStackOffset ( <NUM_LIT> ) , VarArgsNumGPR ( <NUM_LIT> ) , VarArgsNumFPR ( <NUM_LIT> ) , CRSpillFrameIndex ( <NUM_LIT> ) , MF ( MF ) , UsesPICBase ( <NUM_LIT> ) {


<s> if ( ! MI -> getDesc ( ) . mayLoad ( ) || ! isPredicated ( * MI ) ) return false ; int PNewOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; return PNewOpcode >= <NUM_LIT> ;


<s> std :: tie ( Lo1 , Hi1 ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; SDValue Lo2 , Hi2 ; std :: tie ( Lo2 , Hi2 ) = DAG . SplitVectorOperand ( Op . getNode ( ) , <NUM_LIT> ) ; SDLoc SL ( Op ) ;

SDValue OpLo = DAG . getNode ( Opc , SL , Lo0 . getValueType ( ) , Lo0 , Lo1 , Lo2 , Op -> getFlags ( ) ) ;


<s> void MetadataStreamer :: emitKernelDebugProps ( const amd_kernel_code_t & KernelCode ) { if ( ! ( KernelCode . code_properties & AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED ) ) return ; auto & DebugProps = CodeObjectMetadata . mKernels . back ( ) . mDebugProps ; DebugProps . mDebuggerABIVersion . push_back ( <NUM_LIT> ) ; DebugProps . mDebuggerABIVersion . push_back ( <NUM_LIT> ) ; DebugProps . mReservedNumVGPRs = KernelCode . reserved_vgpr_count ; DebugProps . mReservedFirstVGPR = KernelCode . reserved_vgpr_first ; DebugProps . mPrivateSegmentBufferSGPR = KernelCode . debug_private_segment_buffer_sgpr ;


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; Reg = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; int32_t SImm = MO1 . getImm ( ) ;


<s> <ISA_LIT>AsmInstrumentation * llvm :: Create<ISA_LIT>AsmInstrumentation ( const MCTargetOptions & MCOptions , const MCContext & Ctx , const MCSubtargetInfo * & STI ) { Triple T ( STI -> getTargetTriple ( ) ) ; const bool hasCompilerRTSupport = T . isOSLinux ( ) ; if ( ClAsanInstrumentAssembly && hasCompilerRTSupport && MCOptions . SanitizeAddress ) { if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer32 ( STI ) ;

if ( STI -> getFeatureBits ( ) [ <STR_LIT> ] != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer64 ( STI ) ;


<s> virtual const char * getPassName ( ) const {


return ( poly128_t ) __builtin_neon_vreinterprettiv8hi ( ( int16x8_t ) __a ) ;


<s> AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ; CommentString = <STR_LIT> ;

ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const uint64_t StackSize = MFI . getStackSize ( ) ; if ( MFI . isFixedObjectIndex ( FI ) && TRI -> needsStackRealignment ( MF ) && ! STI . isTargetWin64 ( ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ;

if ( ! IgnoreSPUpdates && ! TFI -> hasReservedCallFrame ( MF ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ;


<s> static DecodeStatus DecodeSPR_8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; return DecodeSPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) {


<s> label_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) ; test_rtx = gen_rtx_fmt_ee ( test , cc_mode , cc_reg , const0_rtx ) ;


<s> return D ( <STR_LIT> , <STR_LIT> ) ;


<s> Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = getValueType ( DL , I . getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOStore ;


<s> struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; enum insn_code icode = N2FPU_ICODE ( code ) ; int nargs , argno , opno = <NUM_LIT> ; int num_operands = N2FPU ( code ) . num_operands ; machine_mode dst_mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; bool has_target_p = ( dst_mode != VOIDmode ) ; if ( N2FPU_N ( code ) < <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> <STR_LIT> , N2FPU_NAME ( code ) , N2FPU_NAME ( code ) ) ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , dst_mode ) ; else num_operands -= <NUM_LIT> ; nargs = call_expr_nargs ( exp ) ; for ( argno = <NUM_LIT> ; argno < nargs ; argno ++ ) { tree arg = CALL_EXPR_ARG ( exp , argno ) ; create_input_operand ( & ops [ opno ++ ] , expand_normal ( arg ) , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } if ( ! maybe_expand_insn ( icode , num_operands , ops ) ) { error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; }

return has_target_p ? ops [ <NUM_LIT> ] . value : const0_rtx ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( getReg ( ) ) ) ;


<s> if ( isTailCall ( MI ) ) return MachineOutlinerInstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . modifiesRegister ( <STR_LIT> , & RI ) || MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . readsRegister ( <STR_LIT> , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( <STR_LIT> ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) return MachineOutlinerInstrType :: Illegal ; if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ;

for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return MachineOutlinerInstrType :: Illegal ;


<s> const char * SpecialMemcpyName = <STR_LIT> ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; bool LongCalls = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useLongCalls ( ) ; unsigned Flags = LongCalls ? <STR_LIT> : <NUM_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ;

CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) , Flags ) , std :: move ( Args ) ) . setDiscardResult ( ) ;


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetIOS ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { ++ MBBI ; if ( MBBI != MBB . end ( ) ) dl = MBBI -> getDebugLoc ( ) ; } unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; NumBytes = DPRCSOffset ; if ( hasFP ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlags ( MachineInstr :: FrameSetup ) ) ; if ( NumBytes > <NUM_LIT> ) AFI -> setShouldRestoreSPFromFP ( true ) ; }

if ( NumBytes ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , - NumBytes , MachineInstr :: FrameSetup ) ;


<s> static void addRegUnits ( const <ISA_LIT>RegisterInfo & TRI , BitVector & BV , MCRegister Reg ) { for ( MCRegUnitIterator RUI ( Reg , & TRI ) ; RUI . isValid ( ) ; ++ RUI ) BV . set ( * RUI ) ;


<s> static SDValue LowerMINMAX ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getScalarType ( ) != <STR_LIT> && VT . is256BitVector ( ) ) return Lower256IntArith ( Op , DAG ) ; SDLoc DL ( Op ) ; unsigned Opcode = Op . getOpcode ( ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; SDValue Sign = DAG . getConstant ( APInt :: getSignedMinValue ( <NUM_LIT> ) , DL , VT ) ; N0 = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Sign ) ; N1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 , Sign ) ; Opcode = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue Result = DAG . getNode ( Opcode , DL , VT , N0 , N1 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Result , Sign ) ; } <STR_LIT> CC ; switch ( Opcode ) { case <STR_LIT> : CC = <STR_LIT> :: SETLT ; break ; case <STR_LIT> : CC = <STR_LIT> :: SETGT ; break ; case <STR_LIT> : CC = <STR_LIT> :: SETULT ; break ; case <STR_LIT> : CC = <STR_LIT> :: SETUGT ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDValue Cond = DAG . getSetCC ( DL , VT , N0 , N1 , CC ) ; return DAG . getSelect ( DL , VT , Cond , N0 , N1 ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> return __builtin_mve_vctp16q_mv8bi ( __a , __p ) ;


<s> HaveCond = true ; break ; case <STR_LIT> : if ( HaveCond ) return true ; if ( ! MI . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; Cond . push_back ( MachineOperand :: CreateImm ( false ) ) ; Cond . push_back ( MI . getOperand ( <NUM_LIT> ) ) ; TBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; HaveCond = true ; break ; case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( ! HaveCond ) TBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; else FBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> if ( result != <NUM_LIT> ) return true ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = llvm :: find ( WaterList , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB -> getIterator ( ) , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; decrementCPEReferenceCount ( CPI , CPEMI ) ; unsigned ID = createPICLabelUId ( ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; NewIsland -> setAlignment ( getCPEAlign ( * U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( & * -- NewIsland -> getIterator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) { UserMI -> getOperand ( i ) . setIndex ( ID ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ID << <STR_LIT> << CPI << format ( <STR_LIT> , BBInfo [ NewIsland -> getNumber ( ) ] . Offset ) ) ;


<s> if ( Subtarget -> isTargetNaCl ( ) ) EmitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { TS . emitDirectiveSetMicro<ISA_LIT> ( ) ; TS . setUsesMicro<ISA_LIT> ( ) ; TS . updateABIInfo ( * Subtarget ) ; } else TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ;

if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) TS . emitDirectiveSet<ISA_LIT>16 ( ) ;


RegisterTargetMachine < MDSPTargetMachine > X ( TheMDSPTarget ) ;


<s> break ; case I387_CW_FLOOR : emit_insn ( gen_andhi3 ( reg , reg , GEN_INT ( ~ <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_FLOOR ; break ; case I387_CW_CEIL : emit_insn ( gen_andhi3 ( reg , reg , GEN_INT ( ~ <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_CEIL ; break ; case I387_CW_MASK_PM : emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_MASK_PM ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case I387_CW_TRUNC : emit_insn ( gen_movsi_insv_1 ( reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_TRUNC ; break ;


<s> if ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: dst_sel ) != - <NUM_LIT> ) { MachineOperand * DstSel = TII -> getNamedOperand ( MI , <STR_LIT> :: dst_sel ) ; if ( DstSel ) { SDWAInst . add ( * DstSel ) ; } else { SDWAInst . addImm ( <STR_LIT> :: SdwaSel :: DWORD ) ; } } if ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: dst_unused ) != - <NUM_LIT> ) { MachineOperand * DstUnused = TII -> getNamedOperand ( MI , <STR_LIT> :: dst_unused ) ; if ( DstUnused ) { SDWAInst . add ( * DstUnused ) ; } else { SDWAInst . addImm ( <STR_LIT> :: DstUnused :: UNUSED_PAD ) ; } } assert ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: src0_sel ) != - <NUM_LIT> ) ; MachineOperand * Src0Sel = TII -> getNamedOperand ( MI , <STR_LIT> :: src0_sel ) ; if ( Src0Sel ) { SDWAInst . add ( * Src0Sel ) ; } else { SDWAInst . addImm ( <STR_LIT> :: SdwaSel :: DWORD ) ; } if ( Src1 ) { assert ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: src1_sel ) != - <NUM_LIT> ) ; MachineOperand * Src1Sel = TII -> getNamedOperand ( MI , <STR_LIT> :: src1_sel ) ; if ( Src1Sel ) { SDWAInst . add ( * Src1Sel ) ; } else { SDWAInst . addImm ( <STR_LIT> :: SdwaSel :: DWORD ) ; } } auto DstUnused = TII -> getNamedOperand ( MI , <STR_LIT> :: dst_unused ) ; if ( DstUnused && DstUnused -> getImm ( ) == <STR_LIT> :: DstUnused :: UNUSED_PRESERVE ) { assert ( Dst && Dst -> isTied ( ) ) ; assert ( Opcode == static_cast < unsigned int > ( SDWAOpcode ) ) ; auto PreserveDstIdx = <STR_LIT> ( SDWAOpcode , <STR_LIT> :: vdst ) ; assert ( PreserveDstIdx != - <NUM_LIT> ) ; auto TiedIdx = MI . findTiedOperandIdx ( PreserveDstIdx ) ; auto Tied = MI . getOperand ( TiedIdx ) ; SDWAInst . add ( Tied ) ; SDWAInst -> tieOperands ( PreserveDstIdx , SDWAInst -> getNumOperands ( ) - <NUM_LIT> ) ; } bool Converted = false ; for ( auto & Operand : SDWAOperands ) { DEBUG ( dbgs ( ) << * SDWAInst << <STR_LIT> << * Operand ) ; if ( PotentialMatches . count ( Operand -> getParentInst ( ) ) == <NUM_LIT> ) Converted |= Operand -> convertToSDWA ( * SDWAInst , TII ) ; }


<s> if ( ! Op . isImm ( ) ) return printOperand ( MI , OpNo , STI , O ) ; if ( PrintBranchImmAsAddress ) O << formatHex ( Op . getImm ( ) ) ;

else O << formatImm ( Op . getImm ( ) ) ;


<s> SDValue InFlag ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , PtrVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

return GetTLSADDR ( DAG , Chain , GA , & InFlag , PtrVT , <STR_LIT> , <STR_LIT> ) ;


<s> break ; case <STR_LIT> : SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; if ( N0 -> getOpcode ( ) == <STR_LIT> && N0 -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) { SExtVT = <STR_LIT> ; FPCastVT = <STR_LIT> ; } break ; case <STR_LIT> : SExtVT = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget . hasInt256 ( ) ) return SDValue ( ) ; SExtVT = <STR_LIT> ; break ; } ; SDLoc DL ( BitCast ) ; SDValue V = DAG . getSExtOrTrunc ( N0 , DL , SExtVT ) ; if ( SExtVT == <STR_LIT> ) { V = DAG . getBitcast ( <STR_LIT> , V ) ;

V = DAG . getVectorShuffle ( <STR_LIT> , DL , V , DAG . getUNDEF ( <STR_LIT> ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ) ;


<s> static void translateImmediate ( MCInst & mcInst , uint64_t immediate ) { mcInst . addOperand ( MCOperand :: CreateImm ( immediate ) ) ;


<s> static bool extract_base_offset_in_addr ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; if ( REG_P ( addr ) || GET_CODE ( addr ) == SYMBOL_REF ) { * base = addr ; * offset = const0_rtx ; return true ;


<s> if ( Amount != <NUM_LIT> ) { <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; bool isThumb = AFI -> isThumbFunction ( ) ; <STR_LIT> Pred = isThumb ? <STR_LIT> : ( <STR_LIT> ) Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) {

unsigned PredReg = isThumb ? <NUM_LIT> : Old -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> __vector signed int a , b , c ; a = ( __vector signed int ) vec_splats ( __m1 ) ; b = ( __vector signed int ) vec_splats ( __m2 ) ; c = vec_add ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> ) ) ; __m64_union m1 , m2 , res ; m1 . as_m64 = __m1 ; m2 . as_m64 = __m2 ; res . as_int [ <NUM_LIT> ] = m1 . as_int [ <NUM_LIT> ] + m2 . as_int [ <NUM_LIT> ] ; res . as_int [ <NUM_LIT> ] = m1 . as_int [ <NUM_LIT> ] + m2 . as_int [ <NUM_LIT> ] ; return ( __m64 ) res . as_m64 ;


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override {


<s> if ( IncInstruction -> getNumUses ( ) != <NUM_LIT> ) { IncInstruction = BinaryOperator :: Create ( Instruction :: BinaryOps ( IncInstruction -> getOpcode ( ) ) , Phi , IncrementPerRound , <STR_LIT> , IncInstruction ) ; Phi -> setIncomingValue ( IncrementingBlock , IncInstruction ) ; } NewPhi = Phi ; } else { NewPhi = PHINode :: Create ( Phi -> getType ( ) , <NUM_LIT> , <STR_LIT> , Phi ) ; NewPhi -> addIncoming ( Phi -> getIncomingValue ( IncrementingBlock == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) , Phi -> getIncomingBlock ( IncrementingBlock == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; IncInstruction = BinaryOperator :: Create ( Instruction :: BinaryOps ( IncInstruction -> getOpcode ( ) ) , NewPhi , IncrementPerRound , <STR_LIT> , IncInstruction ) ; NewPhi -> addIncoming ( IncInstruction , Phi -> getIncomingBlock ( IncrementingBlock ) ) ; IncrementingBlock = <NUM_LIT> ; } IRBuilder < > Builder ( BB -> getContext ( ) ) ; Builder . SetInsertPoint ( Phi ) ; Builder . SetCurrentDebugLocation ( Offs -> getDebugLoc ( ) ) ; switch ( Offs -> getOpcode ( ) ) { case Instruction :: Add : case Instruction :: Or : pushOutAdd ( NewPhi , OffsSecondOperand , IncrementingBlock == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; break ; case Instruction :: Mul : case Instruction :: Shl : pushOutMulShl ( Offs -> getOpcode ( ) , NewPhi , IncrementPerRound , OffsSecondOperand , IncrementingBlock , Builder ) ; break ; default : return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ;


<s> bool rs6000_legitimate_offset_address_p ( machine_mode mode , rtx x , bool strict , bool worst_case ) { unsigned HOST_WIDE_INT offset ; unsigned int extra ; if ( GET_CODE ( x ) != PLUS ) return false ; if ( ! REG_P ( XEXP ( x , <NUM_LIT> ) ) ) return false ; if ( ! INT_REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return false ; if ( ! reg_offset_addressing_ok_p ( mode ) ) return virtual_stack_registers_memory_p ( x ) ; if ( legitimate_constant_pool_address_p ( x , mode , strict || lra_in_progress ) ) return true ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return false ; offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; extra = <NUM_LIT> ; switch ( mode ) { case V4HImode : case V2SImode : case V1DImode : case V2SFmode : return SPE_CONST_OFFSET_OK ( offset ) ; case DFmode : case DDmode : case DImode : if ( TARGET_E500_DOUBLE ) return SPE_CONST_OFFSET_OK ( offset ) ; if ( VECTOR_MEM_VSX_P ( mode ) ) return false ; if ( ! worst_case ) break ; if ( ! TARGET_POWERPC64 ) extra = <NUM_LIT> ; else if ( offset & <NUM_LIT> ) return false ;


<s> return ( __m256i ) __builtin_ia32_broadcasti32x2_256_mask ( ( __v4si ) __A , ( __v8si ) _mm256_undefined_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> int32_t max = ( <NUM_LIT> << ( bits - <NUM_LIT> ) ) - <NUM_LIT> ;

int32_t min = - ( <NUM_LIT> << ( bits - <NUM_LIT> ) ) ;


<s> BI != BE ; ++ BI ) for ( MachineBasicBlock :: iterator MBBI = BI -> end ( ) ; MBBI != BI -> begin ( ) ; ) { -- MBBI ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) continue ; switch ( MO . getReg ( ) ) { case <STR_LIT> : MO . setReg ( FPReg ) ;


<s> Fixups . push_back ( llvm :: MCFixup :: create ( <NUM_LIT> , DiffExpr , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } assert ( MO . isImm ( ) && BranchMO . isImm ( ) ) ; int Diff = MO . getImm ( ) - BranchMO . getImm ( ) ;

assert ( Diff == <NUM_LIT> || Diff == <NUM_LIT> ) ;


<s> void <ISA_LIT>CodeEmitter :: emitExternalSymbolAddress ( const char * ES , unsigned Reloc ) const { MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , ES , <NUM_LIT> , <NUM_LIT> ) ) ;


<s> const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ;

getParser ( ) . getStreamer ( ) . EmitGPRel32Value ( Value ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> , <NUM_LIT> ) , ST ( st ) {


<s> MachineFunction * MF = BB -> getParent ( ) ; const Constant * PerFn = MF -> getFunction ( ) -> getPersonalityFn ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( PerFn ) ) ; if ( IsSEH && Subtarget -> is32Bit ( ) ) { const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ;

BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) ;


<s> void <ISA_LIT>InstrInfo :: insertOutlinerPrologue ( MachineBasicBlock & MBB , MachineFunction & MF , bool IsTailCall ) const {


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ;

exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ;


<s> } CandPolicy BotPolicy ; setPolicy ( BotPolicy , false , Bot , & Top ) ; CandPolicy TopPolicy ; setPolicy ( TopPolicy , false , Top , & Bot ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( ! BotCand . isValid ( ) || BotCand . SU -> isScheduled || BotCand . Policy != BotPolicy ) { BotCand . reset ( CandPolicy ( ) ) ; pickNodeFromQueue ( Bot , BotPolicy , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotCand . Reason != NoCand && <STR_LIT> ) ; } else { DEBUG ( traceCandidate ( BotCand ) ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( ! TopCand . isValid ( ) || TopCand . SU -> isScheduled || TopCand . Policy != TopPolicy ) { TopCand . reset ( CandPolicy ( ) ) ; pickNodeFromQueue ( Top , TopPolicy , DAG -> getTopRPTracker ( ) , TopCand ) ; assert ( TopCand . Reason != NoCand && <STR_LIT> ) ; } else { DEBUG ( traceCandidate ( TopCand ) ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ; traceCandidate ( TopCand ) ; dbgs ( ) << <STR_LIT> ; traceCandidate ( BotCand ) ; ) ; SchedCandidate Cand ; if ( TopCand . Reason == BotCand . Reason ) { Cand = BotCand ; GenericSchedulerBase :: CandReason TopReason = TopCand . Reason ;


<s> emit_frame_insn ( gen_MOVEI ( hard_frame_pointer_rtx , plus_constant ( stack_pointer_rtx , offset ) ) ) ;


<s> MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( InVT == <STR_LIT> ) { if ( ! ExperimentalVectorWideningLegalization || VT != <STR_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , In ) ;


<s> static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry SSSE3CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry SSE2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; unsigned ISD = <STR_LIT> ; switch ( IID ) { default : break ; case <STR_LIT> : ISD = <STR_LIT> ;


<s> return ( GET_MODE_SIZE ( mode ) / UNITS_PER_VREG ) * <NUM_LIT> ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {

const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ;


<s> if ( Instruction * I = dyn_cast < Instruction > ( V ) ) return I -> getOpcode ( ) == Opcode ; if ( ConstantExpr * E = dyn_cast < ConstantExpr > ( V ) ) return E -> getOpcode ( ) == Opcode ; return false ;


<s> note_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - xtensa_callee_save_size ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; offset = xtensa_callee_save_size - UNITS_PER_WORD ; } else { rtx tmp_reg = gen_rtx_REG ( Pmode , A9_REG ) ; emit_move_insn ( tmp_reg , GEN_INT ( total_size ) ) ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp_reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; note_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - total_size ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; offset = total_size - UNITS_PER_WORD ; } } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; ++ regno ) { if ( xtensa_call_save_reg ( regno ) ) { rtx x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; rtx mem = gen_frame_mem ( SImode , x ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; offset -= UNITS_PER_WORD ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( mem , reg ) ) ; } } if ( total_size > <NUM_LIT> ) { rtx tmp_reg = gen_rtx_REG ( Pmode , A9_REG ) ; emit_move_insn ( tmp_reg , GEN_INT ( total_size - xtensa_callee_save_size ) ) ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp_reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; note_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , xtensa_callee_save_size - total_size ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; } } if ( frame_pointer_needed ) { if ( cfun -> machine -> set_frame_ptr_insn ) { rtx_insn * first ;


<s> int <ISA_LIT>InstrInfo :: getCondOpcode ( int Opc , bool IfTrue ) const {


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) {


<s> unsigned RegAreaSize = NumRegs * GPRSizeInBytes ; unsigned FrameObjSize = std :: max ( Flags . getByValSize ( ) , RegAreaSize ) ; int FrameObjOffset ; ArrayRef < MCPhysReg > ByValArgRegs = ABI . GetByValArgRegs ( ) ; if ( RegAreaSize ) FrameObjOffset = ( int ) ABI . GetCalleeAllocdArgSizeInBytes ( State . getCallingConv ( ) ) - ( int ) ( ( ByValArgRegs . size ( ) - FirstReg ) * GPRSizeInBytes ) ; else FrameObjOffset = VA . getLocMemOffset ( ) ; EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; int FI = MFI -> CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ;


<s> if ( known_eq ( TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( pred ) ) , TYPE_VECTOR_SUBPARTS ( vectype ) ) ) return pred ;

return gimple_build ( & stmts , VIEW_CONVERT_EXPR , truth_type_for ( vectype ) , pred ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> static SDValue RewriteAsNarrowerShuffle ( ShuffleVectorSDNode * SVOp , SelectionDAG & DAG , DebugLoc dl ) { EVT VT = SVOp -> getValueType ( <NUM_LIT> ) ; SDValue V1 = SVOp -> getOperand ( <NUM_LIT> ) ; SDValue V2 = SVOp -> getOperand ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; unsigned NewWidth = ( NumElems == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; EVT NewVT ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : assert ( false && <STR_LIT> ) ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; case <STR_LIT> : NewVT = <STR_LIT> ; break ; }


<s> if ( ! s390_decompose_address ( op1 , & addr ) ) return false ; if ( addr . base && ! REGNO_OK_FOR_BASE_P ( REGNO ( addr . base ) ) ) return false ; if ( addr . indx && ! REGNO_OK_FOR_INDEX_P ( REGNO ( addr . indx ) ) ) return false ; if ( addr . indx && s390_tune >= PROCESSOR_2817_Z196 ) return false ; if ( ! TARGET_64BIT && ! addr . pointer ) return false ; if ( addr . pointer ) return true ; if ( ( addr . base && REG_P ( addr . base ) && REG_POINTER ( addr . base ) ) || ( addr . indx && REG_P ( addr . indx ) && REG_POINTER ( addr . indx ) ) ) return true ;


<s> bool AMDGPUDAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) { IntPtr = CurDAG -> getIntPtrConstant ( Cst -> getZExtValue ( ) / <NUM_LIT> , true ) ; return true ; }


<s> bool hasDirectMove ( ) const { return HasDirectMove ;


<s> case <STR_LIT> : Opcode = <STR_LIT> ; OpcodeR = <STR_LIT> ; break ; } if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opcode ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; transferImpOps ( MI , MIB , MIB ) ; MI . eraseFromParent ( ) ; return true ; } if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( OpcodeR ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; transferImpOps ( MI , MIB , MIB ) ; MI . eraseFromParent ( ) ; return true ;


<s> Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } MI . clear ( ) ; Result = decodeInstruction ( DecoderTableThumbSBit16 , MI , Insn16 , Address , this , STI ) ; if ( Result ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( Result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return Result ; } MI . clear ( ) ; Result = decodeInstruction ( DecoderTableThumb216 , MI , Insn16 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> && ITBlock . instrInITBlock ( ) ) Result = MCDisassembler :: SoftFail ; Check ( Result , AddThumbPredicate ( MI ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned Firstcond = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Mask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; ITBlock . setITState ( Firstcond , Mask ) ; } return Result ; } if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t Insn32 = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; MI . clear ( ) ; Result = decodeInstruction ( DecoderTableThumb32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( Result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return Result ; }


<s> m_pGOTSymbol = pBuilder . AddSymbol < IRBuilder :: AsReferred , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Null ( ) , ResolveInfo :: Hidden ) ;


<s> static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NumRegs = sizeof ( RegList ) / sizeof ( RegList [ <NUM_LIT> ] ) ; SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; if ( ArgFlags . isSplit ( ) || ! PendingMembers . empty ( ) ) { PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isSplitEnd ( ) ) return true ; } if ( PendingMembers . empty ( ) ) { if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; }


<s> ~ <ISA_LIT>Disassembler ( ) override {


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ;

TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ;


<s> raw_svector_ostream ( Name ) << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) {

default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( PerformTailCallOpt && I -> getOpcode ( ) == <STR_LIT> ) { if ( int CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; CalleeAmt *= - <NUM_LIT> ; unsigned StackReg = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned LISInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ORIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt16 ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ;


<s> break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( StringRef ( GV -> getName ( ) ) ) ; const MCExpr * SymExpr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; const MCExpr * Expr = MCBinaryExpr :: createAdd ( SymExpr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; MCOp = MCOperand :: createExpr ( Expr ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { MCSymbol * Sym = Ctx . getOrCreateSymbol ( StringRef ( MO . getSymbolName ( ) ) ) ; Sym -> setExternal ( true ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; MCOp = MCOperand :: createExpr ( Expr ) ; break ; } }


<s> static void buildDefCFAReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned Reg , const <ISA_LIT>InstrInfo * ZII ) { MachineFunction & MF = * MBB . getParent ( ) ;

MachineModuleInfo & MMI = MF . getMMI ( ) ;


<s> void <ISA_LIT>Subtarget :: updateLatency ( MachineInstr & SrcInst , MachineInstr & DstInst , SDep & Dep ) const { if ( Dep . isArtificial ( ) ) {


<s> new GOTPLTEntry ( <NUM_LIT> , m_SectionData ) ;


<s> std :: vector < std :: string > shfc ( Ab a , Ab b , Cond cond ) { return D ( <STR_LIT> , R ( a ) , R ( b ) , cond ) ;


<s> return create<ISA_LIT>ELFObjectWriter ( OSABI , CPU ) ;


<s> StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveOption ( ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveAttribute ( ) ; return true ;


<s> if ( ( int_or_sig_p && ! leaf_func_p && call_used_regs [ reg ] ) || ( regs_ever_live [ reg ] && ( int_or_sig_p || ! call_used_regs [ reg ] ) && ! ( frame_pointer_needed && ( reg == REG_Y || reg == ( REG_Y + <NUM_LIT> ) ) ) ) ) { if ( set ) SET_HARD_REG_BIT ( * set , reg ) ;


<s> void printlea64_32mem ( const MachineInstr * MI , unsigned OpNo ) { O << <STR_LIT> ;

printMemReference ( MI , OpNo , <STR_LIT> ) ;


<s> void Emitter < CodeEmitter > :: emitBasicBlock ( MachineBasicBlock & MBB ) { MCE . StartMachineBasicBlock ( & MBB ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { const MachineInstr & MI = * I ; MCE . processDebugLoc ( MI . getDebugLoc ( ) ) ; switch ( MI . getOpcode ( ) ) { default : MCE . emitWordLE ( getBinaryCodeForInstr ( * I ) ) ; break ;


<s> for ( unsigned i = <NUM_LIT> , e = MD . size ( ) ; i != e ; ++ i ) { Load -> setMetadata ( MD [ i ] . first , MD [ i ] . second ) ; } Value * BitCastLoad = Builder . CreateBitCast ( Load , I . getType ( ) ) ; I . replaceAllUsesWith ( BitCastLoad ) ; I . eraseFromParent ( ) ; }


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) {


<s> DebugLoc dl = Op . getDebugLoc ( ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> ) ;

MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;


<s> bool isITBlockFull ( ) { return inITBlock ( ) && ( ITState . Mask & <NUM_LIT> ) ;


<s> return ( int16_t ) __builtin_aarch64_sqrshrun_nsi ( __a , __b ) ;


<s> CurDAG -> computeKnownBits ( And , Known ) ; uint64_t NotKnownZero = ( ~ Known . Zero ) . getZExtValue ( ) ; if ( ! isShiftedMask ( Known . Zero . getZExtValue ( ) , VT ) ) return false ; if ( ( OrImm & NotKnownZero ) != <NUM_LIT> ) { return false ; } int LSB = countTrailingOnes ( NotKnownZero ) ; int Width = BitWidth - APInt ( BitWidth , NotKnownZero ) . countPopulation ( ) ; unsigned ImmR = ( BitWidth - LSB ) % BitWidth ; unsigned ImmS = Width - <NUM_LIT> ; bool IsBFI = LSB != <NUM_LIT> ; uint64_t BFIImm = OrImm >> LSB ; if ( IsBFI && ! <STR_LIT> ( BFIImm , BitWidth ) ) { unsigned OrChunks = <NUM_LIT> , BFIChunks = <NUM_LIT> ; for ( unsigned Shift = <NUM_LIT> ; Shift < BitWidth ; Shift += <NUM_LIT> ) { if ( ( ( OrImm >> Shift ) & <NUM_LIT> ) != <NUM_LIT> ) ++ OrChunks ; if ( ( ( BFIImm >> Shift ) & <NUM_LIT> ) != <NUM_LIT> ) ++ BFIChunks ; } if ( BFIChunks > OrChunks ) return false ; }


<s> SDValue LoadVal = DAG . getNode ( <STR_LIT> , DL , IntVT , BufferLoad ) ; LoadVal = DAG . getNode ( <STR_LIT> , DL , LoadVT , LoadVal ) ;

return DAG . getMergeValues ( { LoadVal , BufferLoad . getValue ( <NUM_LIT> ) } , DL ) ;


<s> gcc_assert ( i == avr_addrspace [ i ] . id ) ; if ( ! ADDR_SPACE_GENERIC_P ( i ) ) c_register_addr_space ( avr_addrspace [ i ] . name , avr_addrspace [ i ] . id ) ;


<s> gcc_assert ( ! strict ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ! TARGET_INTER_UNIT_MOVES && ! optimize_size ) return true ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; if ( mode == SFmode || mode == DFmode ) return true ; } return false ;


<s> break ; } if ( I != BI && clobbersCTR ( * I ) ) { DEBUG ( dbgs ( ) << printMBBReference ( * MBB ) << <STR_LIT> << MBB -> getFullName ( ) << <STR_LIT> << * I << <STR_LIT> << printMBBReference ( * BI -> getParent ( ) ) << <STR_LIT> << BI -> getParent ( ) -> getFullName ( ) << <STR_LIT> << * BI << <STR_LIT> ) ; return false ; } if ( I == IE ) break ; } if ( ! CheckPreds && Preds . empty ( ) ) return true ; if ( CheckPreds ) { queue_preds : if ( MachineFunction :: iterator ( MBB ) == MBB -> getParent ( ) -> begin ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * BI -> getParent ( ) ) << <STR_LIT> << BI -> getParent ( ) -> getFullName ( ) << <STR_LIT> << * BI << <STR_LIT> ) ; return false ; } for ( MachineBasicBlock :: pred_iterator PI = MBB -> pred_begin ( ) , PIE = MBB -> pred_end ( ) ; PI != PIE ; ++ PI ) Preds . push_back ( * PI ) ; } do { MBB = Preds . pop_back_val ( ) ; if ( ! Visited . count ( MBB ) ) { I = MBB -> getLastNonDebugInstr ( ) ; goto check_block ;


<s> uint64_t DemandedBits = Demanded . getZExtValue ( ) ; Imm &= DemandedBits ; while ( true ) { uint64_t NonDemandedBits = ~ DemandedBits ; uint64_t InvertedImm = ~ Imm & DemandedBits ; uint64_t RotatedImm = ( ( InvertedImm << <NUM_LIT> ) | ( InvertedImm >> ( EltSize - <NUM_LIT> ) & <NUM_LIT> ) ) & NonDemandedBits ; uint64_t Sum = RotatedImm + NonDemandedBits ; bool Carry = NonDemandedBits & ~ Sum & ( <NUM_LIT> << ( EltSize - <NUM_LIT> ) ) ; uint64_t Ones = ( Sum + Carry ) & NonDemandedBits ; NewImm = ( Imm | Ones ) & Mask ; if ( isShiftedMask_64 ( NewImm ) || isShiftedMask_64 ( ~ ( NewImm | ~ Mask ) ) ) break ; if ( EltSize == <NUM_LIT> ) return false ; EltSize /= <NUM_LIT> ; Mask >>= EltSize ; uint64_t Hi = Imm >> EltSize , DemandedBitsHi = DemandedBits >> EltSize ; if ( ( ( Imm ^ Hi ) & ( DemandedBits & DemandedBitsHi ) & Mask ) != <NUM_LIT> ) return false ; Imm |= Hi ; DemandedBits |= DemandedBitsHi ; } ++ NumOptimizedImms ; while ( EltSize < Size ) { NewImm |= NewImm << EltSize ; EltSize *= <NUM_LIT> ; } ( void ) OldImm ; assert ( ( ( OldImm ^ NewImm ) & Demanded . getZExtValue ( ) ) == <NUM_LIT> && <STR_LIT> ) ; assert ( OldImm != NewImm && <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; if ( NewImm == <NUM_LIT> || NewImm == OrigMask ) return TLO . CombineTo ( Op . getOperand ( <NUM_LIT> ) , TLO . DAG . getConstant ( NewImm , DL , VT ) ) ; Enc = <STR_LIT> ( NewImm , Size ) ; SDValue EncConst = TLO . DAG . getTargetConstant ( Enc , DL , VT ) ; SDValue New ( TLO . DAG . getMachineNode ( NewOpc , DL , VT , Op . getOperand ( <NUM_LIT> ) , EncConst ) , <NUM_LIT> ) ; return TLO . CombineTo ( Op , New ) ;


<s> ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; SDLoc dl ( Op ) ; const Constant * C = N -> getConstVal ( ) ; SDValue CP = DAG . getTargetConstantPool ( C , <STR_LIT> , N -> getAlignment ( ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CP ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ;


<s> void nvptx_output_aligned_decl ( FILE * file , const char * name , const_tree decl , HOST_WIDE_INT size , unsigned align ) { write_var_marker ( file , true , TREE_PUBLIC ( decl ) , name ) ; fprintf ( file , <STR_LIT> , TREE_PUBLIC ( decl ) ? <STR_LIT> : <STR_LIT> ) ; nvptx_assemble_decl_begin ( file , name , section_for_decl ( decl ) , TREE_TYPE ( decl ) , size , align ) ; nvptx_assemble_decl_end ( ) ;


<s> Operands . push_back ( Op . take ( ) ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { OwningPtr < <ISA_LIT>Operand > Op ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( Op . take ( ) ) ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Op ) ) return true ; Operands . push_back ( Op . take ( ) ) ; }


<s> TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ;

TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ;


<s> unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ;

O << <STR_LIT> ( val , ( STI . getFeatureBits ( ) & <STR_LIT> ) ) ;