<s> SDValue Offset = DAG . getConstant ( i * MemEltVT . getStoreSize ( ) , SL , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Store -> getBasePtr ( ) , Offset ) ; SDValue NewStore = DAG . getTruncStore ( Store -> getChain ( ) , SL , Val , Ptr , SrcValue . getWithOffset ( i * EltSize ) , MemEltVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , MinAlign ( BaseAlign , i * EltSize ) ) ;


<s> return isDarwin ? <STR_LIT> : <STR_LIT> ; } else { return isDarwin ? <STR_LIT> : <STR_LIT> ; }


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Triple & T ) { CodePointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = false ;


<s> rtx frame_rtx = stack_pointer_rtx ; HOST_WIDE_INT sp_offset = <NUM_LIT> ; rtx tmp ; if ( frame_pointer_needed || cfun -> calls_alloca || info -> total_size > <NUM_LIT> ) { tmp = gen_frame_mem ( Pmode , frame_rtx ) ; emit_move_insn ( operands [ <NUM_LIT> ] , tmp ) ;


<s> const MCOperand & Index = MI . getOperand ( Op + <STR_LIT> ) ; const MCRegisterClass & RC = <ISA_LIT>MCRegisterClasses [ RegClassID ] ; return ( Base . isReg ( ) && Base . getReg ( ) != <NUM_LIT> && RC . contains ( Base . getReg ( ) ) ) || ( Index . isReg ( ) && Index . getReg ( ) != <NUM_LIT> && RC . contains ( Index . getReg ( ) ) ) ;


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;

else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;


<s> Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != <NUM_LIT> ) return false ; } else { Expr = getImm ( ) ; } <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( <ISA_LIT>AsmParser :: classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) {

return DarwinRefKind == MCSymbolRefExpr :: VK_PAGEOFF || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGEOFF || ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGEOFF && Addend == <NUM_LIT> ) || ELFRefKind == <ISA_LIT>MCExpr :: VK_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC || ELFRefKind == <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_SECREL_HI12 || ELFRefKind == <ISA_LIT>MCExpr :: VK_SECREL_LO12 ;


<s> assert ( isImm ( ) ) ; return Imm . Type ;


<s> return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; bool NeedsAligna = needsAligna ( MF ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;

Align NeedAlign = HRI . getSpillAlign ( <STR_LIT> ) ;


<s> NumIntermediates = VT . getSizeInBits ( ) < RegisterVT . getSizeInBits ( ) ? VT . getVectorNumElements ( ) : VT . getSizeInBits ( ) / RegisterVT . getSizeInBits ( ) ; return NumIntermediates ;


<s> unsigned S = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned J1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned J2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned I1 = ! ( J1 ^ S ) ; unsigned I2 = ! ( J2 ^ S ) ; unsigned imm10 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm11 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned tmp = ( S << <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) | ( imm10 << <NUM_LIT> ) | imm11 ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ;

if ( ! tryAddingSymbolicOperand ( Address , Address + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm32 ) ) ;


<s> void <ISA_LIT>SEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>ABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ;

if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ;


<s> void <ISA_LIT>PassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ;

if ( ! IsOptNone ) addPass ( create<ISA_LIT>PostLegalizeCombiner ( IsOptNone ) ) ;


<s> tmp = gen_rtx_REG ( fpcmp_mode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , gen_rtx_COMPARE ( fpcmp_mode , op0 , op1 ) ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , tmp ) ) ;


<s> getParser ( ) . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Off ) ) return true ;

if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ;


<s> size = build_int_cst ( sizetype , <NUM_LIT> ) ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; return TargetTransformInfo ( F . getParent ( ) -> getDataLayout ( ) ) ; } LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ;

return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , false ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> :


<s> const <ISA_LIT>ABIInfo & getABI ( ) const {


<s> Tile64Type Tile64VLIWPacketizerList :: Tile64TypeOf ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ;

return ( Tile64Type ) ( ( F >> TypePos ) & TypeMask ) ;


<s> EVT <ISA_LIT>TargetLowering :: getAsmOperandValueType ( const DataLayout & DL , llvm :: Type * Ty , bool AllowUnknown ) const { if ( Subtarget -> hasLS64 ( ) && Ty -> isIntegerTy ( <NUM_LIT> ) ) return EVT ( <STR_LIT> ) ; return TargetLowering :: getAsmOperandValueType ( DL , Ty , AllowUnknown ) ;


<s> unsigned Ad = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; switch ( Rd ) { case <NUM_LIT> : return Ad ? amSymbolic : amRegister ; case <NUM_LIT> : return Ad ? amAbsolute : amRegister ; default : break ; }


<s> int m16_nuimm8_1 ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return m16_check_op ( op , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ;


<s> const int OldImm = ( int ) CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int NewImm = std :: abs ( OldImm + Correction ) ; if ( OldImm == <NUM_LIT> && ( ( Negative && Correction == <NUM_LIT> ) || ( ! Negative && Correction == - <NUM_LIT> ) ) ) { Opc = getComplementOpc ( Opc ) ; }

return CmpInfo ( NewImm , Opc , getAdjustedCmp ( Cmp ) ) ;


<s> MachineFunction * MF = MBB . getParent ( ) ; DebugLoc DL = Cmp . getDebugLoc ( ) ; MachineInstr * Loop = findLoopInstr ( PreHeader ) ; if ( ! Loop ) return <NUM_LIT> ; Register LoopCountReg = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineInstr * LoopCount = MRI . getUniqueVRegDef ( LoopCountReg ) ; if ( ! LoopCount ) return <NUM_LIT> ; if ( LoopCount -> getOpcode ( ) == <STR_LIT> || LoopCount -> getOpcode ( ) == <STR_LIT> ) { int64_t Offset = LoopCount -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset <= <NUM_LIT> ) { LoopCount -> eraseFromParent ( ) ; Loop -> eraseFromParent ( ) ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; bool isStore = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool isDW = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ;


<s> int Iterations = <ISA_LIT>SubTarget . hasRecipPrec ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( VT . getScalarType ( ) == <STR_LIT> ) ++ Iterations ; SelectionDAG & DAG = DCI . DAG ; SDLoc dl ( Op ) ; SDValue FPOne = DAG . getConstantFP ( <NUM_LIT> , VT . getScalarType ( ) ) ; if ( VT . isVector ( ) ) { assert ( VT . getVectorNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; FPOne = DAG . getNode ( <STR_LIT> , dl , VT , FPOne , FPOne , FPOne , FPOne ) ; } SDValue Est = DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; DCI . AddToWorklist ( Est . getNode ( ) ) ;

for ( int i = <NUM_LIT> ; i < Iterations ; ++ i ) {


<s> if ( Opc == <STR_LIT> && U -> getOperand ( <NUM_LIT> ) . getNode ( ) == N ) return false ; if ( Opc == <STR_LIT> && U -> getOperand ( <NUM_LIT> ) . getNode ( ) == N ) return false ;

if ( isTargetShuffle ( Opc ) ) return true ;


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; switch ( CC ) { case <STR_LIT> : BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ;


<s> rgroup_controls * rgc ; unsigned int num_vectors_m1 ; unsigned int shift_cnt = <NUM_LIT> ; FOR_EACH_VEC_ELT ( LOOP_VINFO_LENS ( loop_vinfo ) , num_vectors_m1 , rgc ) if ( rgc -> type ) shift_cnt += num_vectors_m1 + <NUM_LIT> ; rs6000_add_stmt_cost ( loop_vinfo , ( void * ) data , shift_cnt , scalar_stmt , NULL , NULL_TREE , <NUM_LIT> , vect_body ) ;


<s> case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> :


<s> Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT> << Pos ) ; Mask |= ( CC & <NUM_LIT> ) << <NUM_LIT> ; MIB . addImm ( Mask ) ; LastITMI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( ) ; MachineBasicBlock :: instr_iterator LI = LastITMI ; finalizeBundle ( MBB , InsertPos . getInstrIterator ( ) , llvm :: next ( LI ) ) ; Modified = true ;


<s> static bool isSupportedCmpOp ( unsigned opCode ) {

return ( opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> ) ;


<s> bool <ISA_LIT>16TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { return false ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < <ISA_LIT>SPBundling > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> if ( CALL_P ( insn ) && dep_type == REG_DEP_TRUE ) {


<s> BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) ) ; STI . getInstrInfo ( ) -> loadRegFromStackSlot ( MBB , MBBI , <STR_LIT> , <ISA_LIT>FI -> getISRRegFI ( <NUM_LIT> ) , PtrRC , STI . getRegisterInfo ( ) ) ; BuildMI ( MBB , MBBI , DL , STI . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> return __builtin_mve_vqdmulhq_n_sv4si ( __a , __b ) ;


<s> static SDValue combineCarryThroughADD ( SDValue EFLAGS ) { if ( EFLAGS . getOpcode ( ) == <STR_LIT> ) { if ( isAllOnesConstant ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue Carry = EFLAGS . getOperand ( <NUM_LIT> ) ; while ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || ( Carry . getOpcode ( ) == <STR_LIT> && isOneConstant ( Carry . getOperand ( <NUM_LIT> ) ) ) ) Carry = Carry . getOperand ( <NUM_LIT> ) ; if ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> ) { if ( Carry . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) return Carry . getOperand ( <NUM_LIT> ) ;


<s> unsigned NSlots ; if ( MCID && mustComeFirst ( MCID , NSlots ) && CurSlots ) return true ;

return ScoreboardHazardRecognizer :: ShouldPreferAnother ( SU ) ;


<s> static bool csky_far_jump_used_p ( void ) { rtx_insn * insn ; if ( cfun -> machine -> far_jump_used ) return true ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && get_attr_far_jump ( insn ) == FAR_JUMP_YES ) {

cfun -> machine -> far_jump_used = <NUM_LIT> ;


<s> if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ; if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) continue ;

if ( ( unsigned ) M [ i ] != ( i - i % BlockElts ) + ( BlockElts - <NUM_LIT> - i % BlockElts ) ) return false ;


__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> void <ISA_LIT>LongBranch :: initMBBInfo ( ) { for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ) splitMBB ( I ++ ) ; MF -> RenumberBlocks ( ) ; MBBInfos . clear ( ) ; MBBInfos . resize ( MF -> size ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MBBInfos . size ( ) ; I < E ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; for ( MachineBasicBlock :: instr_iterator MI = MBB -> instr_begin ( ) ; MI != MBB -> instr_end ( ) ; ++ MI ) MBBInfos [ I ] . Size += TII -> GetInstSizeInBytes ( & * MI ) ; ReverseIter End = MBB -> rend ( ) ; ReverseIter Br = getNonDebugInstr ( MBB -> rbegin ( ) , End ) ; if ( ( Br != End ) && ! Br -> isIndirectBranch ( ) && ( Br -> isConditionalBranch ( ) || ( Br -> isUnconditionalBranch ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) ) ) MBBInfos [ I ] . Br = ( ++ Br ) . base ( ) ;


<s> if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { CallingConv :: ID CC = F . getCallingConv ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = CC == CallingConv :: WebKit_JS ? RetCC_<ISA_LIT>_WebKit_JS : RetCC_<ISA_LIT>_AAPCS ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ;


<s> MVT PtrVT = getPointerTy ( DL , AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg ) , PtrVT ) ;

return DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ;


<s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } unsigned FrameReg ; if ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) FrameReg = <STR_LIT> ; else { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { FrameReg = <STR_LIT> ; } else { if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ;

Offset = SPOffset + ( int64_t ) StackSize ;


<s> vmlsq_u32 ( uint32x4_t a , uint32x4_t b , uint32x4_t c ) {


<s> case static_cast < unsigned > ( <STR_LIT> ) : return <STR_LIT> ; case static_cast < unsigned > ( <STR_LIT> ) : return <STR_LIT> ; case static_cast < unsigned > ( <STR_LIT> ) : return <STR_LIT> ; case static_cast < unsigned > ( <STR_LIT> ) : return <STR_LIT> ;


<s> bool <ISA_LIT>OffsetAllocator :: runOnMachineFunction ( MachineFunction & MFN ) { MF = & MFN ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF -> getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;

PerformAllocation ( DT -> getRootNode ( ) ) ;


<s> MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( errs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { SplitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBSizes [ MBB -> getNumber ( ) ] -= delta ; MachineBasicBlock * SplitBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ;

AdjustBBOffsetsAfter ( SplitBB , - delta ) ;


<s> case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ;

case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ;


return ( __m64 ) ( ( __vector long long ) __c ) [ <NUM_LIT> ] ;


<s> if ( fs . sp_realigned && cfa_offset > fs . sp_realigned_fp_last ) { gcc_assert ( cfa_offset >= fs . sp_realigned_offset ) ; return false ; }


<s> if ( ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) || ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; } else if ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> ) { if ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) || ( ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) && ! LdSt . getOperand ( <NUM_LIT> ) . isFI ( ) ) || ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; } else return false ; unsigned Scale = <NUM_LIT> ; int64_t Dummy1 , Dummy2 ; if ( ! getMemOpInfo ( LdSt . getOpcode ( ) , Scale , Width , Dummy1 , Dummy2 ) ) return false ; if ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> ) { BaseOp = & LdSt . getOperand ( <NUM_LIT> ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ; } else { assert ( LdSt . getNumExplicitOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; BaseOp = & LdSt . getOperand ( <NUM_LIT> ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ;


<s> if ( TARGET_MIPS16 ) sorry ( <STR_LIT> ) ; if ( first + size <= <NUM_LIT> ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r3 = MIPS_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = MIPS_PROLOGUE_TEMP2 ( Pmode ) ; gcc_assert ( first <= <NUM_LIT> ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( r3 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ) ; if ( rounded_size > <NUM_LIT> ) { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r12 , gen_rtx_MINUS ( Pmode , r3 , r12 ) ) ) ; } else emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , r3 , - rounded_size ) ) ) ; emit_insn ( PMODE_INSN ( gen_probe_stack_range , ( r3 , r3 , r12 ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; } emit_insn ( gen_blockage ( ) ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , const MCRegisterInfo * Info ) : MCDisassembler ( STI ) , RegInfo ( Info ) {


<s> <ISA_LIT>ReplaceImageHandles :: <ISA_LIT>ReplaceImageHandles ( ) : MachineFunctionPass ( ID ) {


<s> void <ISA_LIT>InstrInfo :: getNoopForMachoTarget ( MCInst & NopInst ) const { NopInst . setOpcode ( <STR_LIT> ) ;


<s> int NumBytes = ( int ) MFI . getStackSize ( ) ; unsigned SAVEri = <STR_LIT> ; unsigned SAVErr = <STR_LIT> ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == <NUM_LIT> ) return ; SAVEri = <STR_LIT> ; SAVErr = <STR_LIT> ; } if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) NumBytes += MFI . getMaxCallFrameSize ( ) ; NumBytes = Subtarget . getAdjustedFrameSize ( NumBytes ) ; if ( MFI . getMaxAlignment ( ) > <NUM_LIT> ) { NumBytes = alignTo ( NumBytes , MFI . getMaxAlignment ( ) ) ; } MFI . setStackSize ( NumBytes ) ; emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ; unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned regOutRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; if ( NeedsStackRealignment ) { int64_t Bias = Subtarget . getStackPointerBias ( ) ;


<s> CriticalPathRCs . push_back ( & <STR_LIT> ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ; CriticalPathRCs . push_back ( & <STR_LIT> ) ;

return OptLevel >= CodeGenOpt :: Default ;


<s> SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ; NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( MILabel ) ; SM . recordPatchPoint ( * MILabel , MI ) ; PatchPointOpers opers ( & MI ) ; unsigned ScratchIdx = opers . getNextScratchIdx ( ) ; unsigned EncodedBytes = <NUM_LIT> ; const MachineOperand & CalleeMO = opers . getCallTarget ( ) ;

if ( ! ( CalleeMO . isImm ( ) && ! CalleeMO . getImm ( ) ) ) {


<s> unsigned RegLoNum = MRI . getSubReg ( RegNum , <STR_LIT> ) ;

RegNum = ( RegLoNum != <STR_LIT> ) ? RegLoNum : RegNum ;


<s> default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; MaxDisplacement = std :: min ( ( int ) GV -> getAlignment ( ) - <NUM_LIT> , MaxDisplacement ) ; } bool UpdateHBase = false ; SDValue HBase = Base . getOperand ( <NUM_LIT> ) ; int Offset = N -> getConstantOperandVal ( FirstOp ) ; if ( ReplaceFlags ) { if ( Offset < <NUM_LIT> || Offset > MaxDisplacement ) { if ( Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! HBase . isMachineOpcode ( ) || HBase . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! Base . hasOneUse ( ) || ! HBase . hasOneUse ( ) ) continue ; SDValue HImmOpnd = HBase . getOperand ( <NUM_LIT> ) ; if ( HImmOpnd != ImmOpnd ) continue ; UpdateHBase = true ; } } else { if ( auto * C = dyn_cast < ConstantSDNode > ( ImmOpnd ) ) { Offset += C -> getSExtValue ( ) ; if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( Offset % <NUM_LIT> ) != <NUM_LIT> ) continue ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) continue ; ImmOpnd = CurDAG -> getTargetConstant ( Offset , SDLoc ( ImmOpnd ) , ImmOpnd . getValueType ( ) ) ; } else if ( Offset != <NUM_LIT> ) { continue ;


<s> for ( Instruction & I : inst_range ( & F ) ) { for ( Value * Op : I . operand_values ( ) ) {

Constant * Cst = dyn_cast < Constant > ( Op ) ;


<s> if ( DstScalarBits == <NUM_LIT> ) { if ( SrcScalarBits == <NUM_LIT> ) return NumDstVectors ; if ( SrcScalarBits == <NUM_LIT> ) return getBoolVecToIntConversionCost ( Opcode , Dst , I ) + NumDstVectors ; } unsigned ScalarCost = getCastInstrCost ( Opcode , Dst -> getScalarType ( ) , Src -> getScalarType ( ) ) ; unsigned TotCost = VF * ScalarCost ; bool NeedsInserts = true , NeedsExtracts = true ; if ( DstScalarBits == <NUM_LIT> && ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP ) ) NeedsInserts = false ; if ( SrcScalarBits == <NUM_LIT> && ( Opcode == Instruction :: FPToSI || Opcode == Instruction :: FPToUI ) ) NeedsExtracts = false ; TotCost += getScalarizationOverhead ( Dst , NeedsInserts , NeedsExtracts ) ; if ( VF == <NUM_LIT> && SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) TotCost *= <NUM_LIT> ; return TotCost ; } if ( Opcode == Instruction :: FPTrunc ) { if ( SrcScalarBits == <NUM_LIT> ) return VF + getScalarizationOverhead ( Dst , true , false ) ; else return VF / <NUM_LIT> + std :: max ( <NUM_LIT> , VF / <NUM_LIT> ) ; } if ( Opcode == Instruction :: FPExt ) { if ( SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) { return VF * <NUM_LIT> ;


<s> for ( Use & U : V -> uses ( ) ) { if ( BitCastOperator * BC = dyn_cast < BitCastOperator > ( U . getUser ( ) ) ) FindUses ( BC , F , Uses , ConstantBCs ) ; else if ( U . get ( ) -> getType ( ) != F . getType ( ) ) { if ( isa < Constant > ( U . get ( ) ) ) { auto c = ConstantBCs . insert ( cast < Constant > ( U . get ( ) ) ) ; if ( ! c . second ) continue ;


<s> if ( GET_MODE ( fnaddr ) != ptr_mode ) fnaddr = convert_memory_address ( ptr_mode , fnaddr ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , ptr_mode , tramp_code_sz + POINTER_BYTES ) ; emit_move_insn ( mem , chain_value ) ; a_tramp = XEXP ( m_tramp , <NUM_LIT> ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) , LCT_NORMAL , VOIDmode , <NUM_LIT> , a_tramp , ptr_mode , plus_constant ( ptr_mode , a_tramp , TRAMPOLINE_SIZE ) , ptr_mode ) ;


<s> static unsigned int s390_hard_regno_nregs ( unsigned int regno , machine_mode mode ) {

return s390_class_max_nregs ( REGNO_REG_CLASS ( regno ) , mode ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

for ( auto RegNo : getRegList ( ) ) Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ;


<s> if ( MI -> isDebugInstr ( ) || MI -> isLabel ( ) || MI -> isInlineAsm ( ) ) return ; auto RegOpcode = OutMI . getOpcode ( ) ; auto StackOpcode = <STR_LIT> ( RegOpcode ) ; assert ( StackOpcode != - <NUM_LIT> && <STR_LIT> ) ; OutMI . setOpcode ( StackOpcode ) ; for ( auto I = OutMI . getNumOperands ( ) ; I ; -- I ) { auto & MO = OutMI . getOperand ( I - <NUM_LIT> ) ; if ( MO . isReg ( ) ) { OutMI . erase ( & MO ) ; } }


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Val = CE -> getValue ( ) ; int64_t Min = - ( <NUM_LIT> * ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) ; int64_t Max = <NUM_LIT> * ( ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) - <NUM_LIT> ) ; return ( Val % <NUM_LIT> ) == <NUM_LIT> && Val >= Min && Val <= Max ; } return true ;


<s> static __inline void si_hgti ( qword a , signed int b ) { union {


<s> else if ( MI . getOpcode ( ) == <STR_LIT> ) End = & MI ; else if ( IsLoopStart ( MI ) ) Start = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) Revert = true ; if ( ! Dec ) continue ; if ( MI . mayLoad ( ) || MI . mayStore ( ) ) Revert = MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; } if ( Dec && End && Revert ) break ; } LLVM_DEBUG ( if ( Start ) dbgs ( ) << <STR_LIT> << * Start ; if ( Dec ) dbgs ( ) << <STR_LIT> << * Dec ; if ( End ) dbgs ( ) << <STR_LIT> << * End ; ) ; if ( ! Start && ! Dec && ! End ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } else if ( ! ( Start && Dec && End ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! End -> getOperand ( <NUM_LIT> ) . isMBB ( ) || End -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getHeader ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( BBUtils -> getOffsetOf ( End ) < BBUtils -> getOffsetOf ( ML -> getHeader ( ) ) || ! BBUtils -> isBBInRange ( End , ML -> getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; }

if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) {


<s> Parser . Lex ( ) ; if ( parseOperand ( Operands , Mnemonic ) ) { Parser . eatToEndOfStatement ( ) ; return true ; } numOperands ++ ; } while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; StringRef Str = getLexer ( ) . getTok ( ) . getString ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( Str , Loc ) ) ; Parser . Lex ( ) ; } } if ( InstructionIsConditional ( Mnemonic , numOperands , Operands ) ) { SMLoc S = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Mnemonic . size ( ) ) ; SMLoc E = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Name . size ( ) ) ; Operands . insert ( Operands . begin ( ) + <NUM_LIT> , <ISA_LIT>Operand :: createCondCode ( CondCode , S , E ) ) ; } else if ( CondCode != <STR_LIT> ) {

SMLoc Loc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Mnemonic . size ( ) ) ;


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: <STR_LIT> ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: <STR_LIT> ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: <STR_LIT> ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: <STR_LIT> ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: <STR_LIT> ( Value ) ; adjust :: <STR_LIT> ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: <STR_LIT> ( Value ) ; adjust :: <STR_LIT> ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: <STR_LIT> ( Value ) ; adjust :: <STR_LIT> ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: <STR_LIT> ( Value ) ; adjust :: <STR_LIT> ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ; Value &= <NUM_LIT> ; break ;


<s> mem = adjust_automodify_address_nv ( basemem , SImode , new_addr , offset ) ; reg = gen_rtx_REG ( SImode , base_regno + par_index ) ;

XVECEXP ( result , <NUM_LIT> , par_index ) = gen_rtx_SET ( VOIDmode , reg , mem ) ;


<s> explicit Thumb1FrameInfo ( const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>FrameInfo ( sti ) {


<s> RTX_FRAME_RELATED_P ( reg ) = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , indx ++ ) = reg ; off = nregs * UNITS_PER_WORD ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; save_blink = false ; } for ( regno = start_reg ; regno <= end_reg ; regno ++ , indx ++ , off -= UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; } if ( save_fp ) { mem = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , hard_frame_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; off -= UNITS_PER_WORD ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ++ ) ) = <NUM_LIT> ; save_fp = false ;


<s> for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI . getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ;

EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ;


<s> void setHasPushSequences ( bool HasPush ) { HasPushSequences = HasPush ;


<s> assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; if ( genExecuteOnly ( ) ) assert ( hasV8MBaselineOps ( ) && ! NoMovt && <STR_LIT> ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 :


<s> void <ISA_LIT>AsmPrinter :: printSavedRegsBitmask ( raw_ostream & O ) { unsigned CPUBitmask = <NUM_LIT> ; int CPUTopSavedRegOff ; const MachineFrameInfo * MFI = MF -> getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; unsigned CPURegSize = <STR_LIT> . getSize ( ) ;

unsigned i = <NUM_LIT> , e = CSI . size ( ) ;


<s> DEBUG ( dbgs ( ) << printMBBReference ( * MF -> getBlockNumbered ( I . first ) ) << <STR_LIT> ) ;

for ( const auto & VI : I . second ) DEBUG ( dbgs ( ) << <STR_LIT> ; VI -> print ( dbgs ( ) ) ) ;


<s> if ( AMDGPU :: SReg_64RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: SReg_64RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_MOV_B64 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( AMDGPU :: VReg_32RegClass . contains ( DestReg ) ) { assert ( AMDGPU :: VReg_32RegClass . contains ( SrcReg ) || AMDGPU :: SReg_32RegClass . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_MOV_B32_e32 ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( AMDGPU :: SReg_32RegClass . contains ( DestReg ) ) ;

assert ( AMDGPU :: SReg_32RegClass . contains ( SrcReg ) ) ;


<s> if ( FuncInfo -> allocateVGPRSpillToAGPR ( MF , FI , TRI -> isAGPR ( MRI , VReg ) ) ) { TRI -> eliminateFrameIndex ( MI , <NUM_LIT> , FIOp , nullptr ) ; continue ; } } if ( ! TII -> isSGPRSpill ( MI ) ) continue ; int FI = TII -> getNamedOperand ( MI , <STR_LIT> :: addr ) -> getIndex ( ) ; assert ( MFI . getStackID ( FI ) == TargetStackID :: SGPRSpill ) ; if ( FuncInfo -> allocateSGPRSpillToVGPR ( MF , FI ) ) { bool Spilled = TRI -> eliminateSGPRToVGPRSpillFrameIndex ( MI , FI , nullptr ) ; ( void ) Spilled ; assert ( Spilled && <STR_LIT> ) ; } } } for ( MachineBasicBlock & MBB : MF ) { for ( auto SSpill : FuncInfo -> getSGPRSpillVGPRs ( ) ) MBB . addLiveIn ( SSpill . VGPR ) ; for ( MCPhysReg Reg : FuncInfo -> getVGPRSpillAGPRs ( ) ) MBB . addLiveIn ( Reg ) ; for ( MCPhysReg Reg : FuncInfo -> getAGPRSpillVGPRs ( ) ) MBB . addLiveIn ( Reg ) ; MBB . sortUniqueLiveIns ( ) ; } MadeChange = true ; } SaveBlocks . clear ( ) ; RestoreBlocks . clear ( ) ; return MadeChange ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) {


<s> bool <ISA_LIT>MCInstrInfo :: isCompound ( MCInstrInfo const & MCII , MCInst const & MCI ) { return ( getType ( MCII , MCI ) == <STR_LIT> ) ;


<s> unsigned Opcode = MI . getOpcode ( ) ;

return Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx , true ) ;


<s> constrainSelectedInstRegOperands ( * MIB , * Subtarget . getInstrInfo ( ) , * Subtarget . getRegisterInfo ( ) , * Subtarget . getRegBankInfo ( ) ) ; } Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto MRI = MIRBuilder . getMRI ( ) ; assert ( MRI -> getType ( ResVReg ) . isPointer ( ) && <STR_LIT> ) ; if ( Reg != ResVReg ) { LLT RegLLTy = LLT :: pointer ( MRI -> getType ( ResVReg ) . getAddressSpace ( ) , <NUM_LIT> ) ; MRI -> setType ( Reg , RegLLTy ) ; assign<ISA_LIT>TypeToVReg ( BaseType , Reg , MIRBuilder . getMF ( ) ) ; } if ( GVar && GVar -> hasName ( ) ) buildOpName ( Reg , GVar -> getName ( ) , MIRBuilder ) ; if ( IsConst ) buildOpDecorate ( Reg , MIRBuilder , <STR_LIT> :: Constant , { } ) ; if ( GVar && GVar -> getAlign ( ) . valueOrOne ( ) . value ( ) != <NUM_LIT> ) buildOpDecorate ( Reg , MIRBuilder , <STR_LIT> :: Alignment , { static_cast < uint32_t > ( GVar -> getAlign ( ) . valueOrOne ( ) . value ( ) ) } ) ;

if ( HasLinkageTy ) buildOpDecorate ( Reg , MIRBuilder , <STR_LIT> :: LinkageAttributes , { static_cast < uint32_t > ( LinkageType ) } , Name ) ;


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


return ( __m64 ) __builtin_ia32_psubq ( ( long long ) __m1 , ( long long ) __m2 ) ;


<s> void addVecListOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( VectorList . RegNum ) ) ;


<s> } const <STR_LIT> & Flags = Ins [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) {


<s> if ( OpInfo . ConstraintVT . isVector ( ) || ! OpInfo . ConstraintVT . isInteger ( ) || OpInfo . ConstraintVT . getSizeInBits ( ) < <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Flag . getNode ( ) ) { Flag = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Flag ) ; Chain = Flag . getValue ( <NUM_LIT> ) ;

} else Flag = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ;


<s> else type = <STR_LIT> ; format = <STR_LIT> TYPE_OPERAND_FMT ; format = <STR_LIT> ; fprintf ( asm_out_file , format , type ) ; if ( flags & SECTION_ENTSIZE ) fprintf ( asm_out_file , <STR_LIT> , flags & SECTION_ENTSIZE ) ; if ( HAVE_COMDAT_GROUP && ( flags & SECTION_LINKONCE ) ) { if ( TREE_CODE ( decl ) == IDENTIFIER_NODE ) fprintf ( asm_out_file , <STR_LIT> , IDENTIFIER_POINTER ( decl ) ) ; else fprintf ( asm_out_file , <STR_LIT> , IDENTIFIER_POINTER ( DECL_COMDAT_GROUP ( decl ) ) ) ; } }


<s> return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL ( shft_amnt ) ) + <NUM_LIT> ) >= <NUM_LIT> && ( INTVAL ( mask ) & ( ( <NUM_LIT> << INTVAL ( shft_amnt ) ) - <NUM_LIT> ) ) == <NUM_LIT> ;


<s> addPass ( createStructurizeCFGPass ( ) ) ; return false ;


<s> inline bool isV8EligibleForIT ( InstrType * Instr ) { switch ( Instr -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return IsCPSRDead ( Instr ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> :


<s> unsigned ShiftedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned PtrLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskUpper = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal1 = RegInfo . createVirtualRegister ( RC ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned SrlRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addSuccessor ( exitMBB ) ; int64_t MaskImm = ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , MaskLSB2 ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AlignedAddr ) . addReg ( Ptr ) . addReg ( MaskLSB2 ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , PtrLSB2 ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . isLittle ( ) ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ShiftAmt ) . addReg ( PtrLSB2 ) . addImm ( <NUM_LIT> ) ; } else { unsigned Off = RegInfo . createVirtualRegister ( RC ) ;

BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Off ) . addReg ( PtrLSB2 ) . addImm ( ( Size == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = {

{ MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_S , <STR_LIT> } , { MO_TLS , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } } ;


<s> machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) ) ;


<s> return __builtin_mve_vrndaq_m_fv8hf ( __arm_vuninitializedq_f16 ( ) , __a , __p ) ;


if ( parseImmExpr ( Size ) ) return true ;


<s> void <ISA_LIT>ExpandCondsets :: removeInstr ( MachineInstr & MI ) { LIS -> RemoveMachineInstrFromMaps ( MI ) ; MI . eraseFromParent ( ) ;


<s> if ( STI . isTargetDarwin ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> if ( reload_completed ) { enum reg_type reg_type = GET_REG_TYPE ( regno ) ; int mask_bit = <NUM_LIT> << ( regno - first_regno [ reg_type ] ) ; return ( current_frame_info . mask [ reg_type ] & mask_bit ) != <NUM_LIT> ; } return <NUM_LIT> ;


<s> unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else if ( RegVT == <STR_LIT> || RegVT == <STR_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; InVals . push_back ( DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ) ; } else { assert ( <NUM_LIT> ) ; } } else if ( VA . isRegLoc ( ) && Flags . isByVal ( ) && Flags . getByValSize ( ) <= <NUM_LIT> ) { assert ( <NUM_LIT> && <STR_LIT> ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( Flags . isByVal ( ) ) { ObjSize = Flags . getByValSize ( ) ; } else { ObjSize = VA . getLocVT ( ) . getStoreSizeInBits ( ) >> <NUM_LIT> ; } StackLocation = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; FI = MFI -> CreateFixedObject ( ObjSize , StackLocation , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal ( ) ) { InVals . push_back ( FIN ) ; } else { InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) ) ) ; } } } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOps ) ; if ( isVarArg ) {

int FrameIndex = MFI -> CreateFixedObject ( <ISA_LIT>_PointerSize , HEXAGON_LRFP_SIZE + CCInfo . getNextStackOffset ( ) , true ) ;


<s> return ( STI . getFeatureBits ( ) & <STR_LIT> ) == <NUM_LIT> ;


<s> OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( POPCNT ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM32 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ;


<s> const <ISA_LIT>MachineFunction * MFI = MF -> getInfo < <ISA_LIT>MachineFunction > ( ) ; if ( ! MFI -> isEntryFunction ( ) ) return ; const <ISA_LIT>Subtarget & STM = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; amd_kernel_code_t KernelCode ; if ( STM . isAmdCodeObjectV2 ( * MF ) ) { getAmdKernelCode ( KernelCode , CurrentProgramInfo , * MF ) ;

OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ;


<s> ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; AscizDirective = <STR_LIT> ; HiddenVisibilityAttr = MCSA_Invalid ;

HiddenDeclarationVisibilityAttr = MCSA_Invalid ;


<s> static std :: string getUdataSectionName ( unsigned num , std :: string prefix = <STR_LIT> ) { std :: ostringstream o ;

o << getTagName ( PREFIX_SYMBOL ) << prefix << <STR_LIT> << num << <STR_LIT> ;


<s> SDValue Op0Op0 = Op0 -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ShAmount = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( ! ShAmount ) return SDValue ( ) ; if ( Op0Op0 -> getOpcode ( ) != <STR_LIT> && Op0Op0 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT ExtendTy = cast < VTSDNode > ( Op0Op0 -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; unsigned TotalBits = ShAmount -> getZExtValue ( ) + ExtendTy . getSizeInBits ( ) ; if ( TotalBits == <NUM_LIT> || ( Op0Op0 -> getOpcode ( ) == <STR_LIT> && TotalBits <= <NUM_LIT> ) ) { SDValue Ops [ ] = { Op0Op0 -> getOperand ( <NUM_LIT> ) , Op0Op0 -> getOperand ( <NUM_LIT> ) , Op0Op0 -> getOperand ( <NUM_LIT> ) } ; DAG . MorphNodeTo ( Op0Op0 . getNode ( ) , <STR_LIT> , Op0Op0 -> getVTList ( ) , Ops , Op0Op0 -> getNumOperands ( ) ) ; return Op0Op0 ; } } }

if ( ( Ty != <STR_LIT> ) && ( ( Ty != <STR_LIT> ) || ! Subtarget -> hasDSPR2 ( ) ) ) return SDValue ( ) ;


<s> int NVOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI . getOpcode ( ) ) { default : report_fatal_error ( Twine ( <STR_LIT> ) + std :: to_string ( MI . getOpcode ( ) ) ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> std :: vector < const GlobalVariable * > Items = ExternalVarDefs ; if ( ! Items . size ( ) ) return ;

O << <STR_LIT> << MAI -> getCommentString ( ) << <STR_LIT> << <STR_LIT> ;


<s> break ; case AluDiscarded : break ; default : { ++ CurEmitted ; for ( MachineInstr :: mop_iterator It = SU -> getInstr ( ) -> operands_begin ( ) , E = SU -> getInstr ( ) -> operands_end ( ) ; It != E ; ++ It ) { MachineOperand & MO = * It ; if ( MO . isReg ( ) && MO . getReg ( ) == AMDGPU :: ALU_LITERAL_X ) ++ CurEmitted ; } }


<s> CellMapType :: const_iterator F = Map . find ( Reg ) ; assert ( F != Map . end ( ) ) ; return F -> second ;


<s> if ( SrcMBB == DstMBB ) return SinglePath_InPath ; while ( SrcMBB && SrcMBB -> succ_size ( ) == <NUM_LIT> ) { SrcMBB = * SrcMBB -> succ_begin ( ) ; if ( SrcMBB == DstMBB ) return SinglePath_InPath ; if ( ! AllowSideEntry && SrcMBB -> pred_size ( ) > <NUM_LIT> ) return Not_SinglePath ; } if ( SrcMBB && SrcMBB -> succ_size ( ) == <NUM_LIT> ) return SinglePath_NotInPath ;


<s> if ( MBB . empty ( ) ) TS . emitDirectiveInsn ( ) ;


<s> return UsesOpenCLEnv || ! UsesLogicalAddressing ;


<s> return __builtin_aarch64_reduc_plus_scal_v2di ( __a ) ;


<s> for ( const auto & MO : MI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> && MO . isDef ( ) && ! MO . isDead ( ) ) return true ;


<s> for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasLoadFromStackSlot ( * MII , MMO , FrameIndex ) ) return true ; return false ;


<s> if ( AddrReg [ i ] -> isImm ( ) || AddrRegNext . isImm ( ) ) { if ( AddrReg [ i ] -> isImm ( ) != AddrRegNext . isImm ( ) || AddrReg [ i ] -> getImm ( ) != AddrRegNext . getImm ( ) ) { return false ;


<s> CUMULATIVE_ARGS * arg_regs_used_so_far = get_cumulative_args ( arg_regs_used_so_far_v ) ; int size ; gcc_assert ( mode != BLKmode ) ; if ( targetm . calls . strict_argument_naming ( arg_regs_used_so_far_v ) ) arg_regs_used_so_far += fr30_num_arg_regs ( mode , type ) ; size = FR30_NUM_ARG_REGS - ( * arg_regs_used_so_far ) ; if ( size <= <NUM_LIT> ) return ; * pretend_size = ( size * UNITS_PER_WORD ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getCFGStructurizerRegClass ( MVT VT ) const { switch ( VT . SimpleTy ) { default : case <STR_LIT> : return & AMDGPU :: VReg_32RegClass ;


<s> Lookahead . push_back ( Token ) ; Lexer . Lex ( ) ; bool Contigious = Lexer . getTok ( ) . getString ( ) . data ( ) == Lookahead . back ( ) . getString ( ) . data ( ) + Lookahead . back ( ) . getString ( ) . size ( ) ; bool Type = Lexer . is ( AsmToken :: Identifier ) || Lexer . is ( AsmToken :: Dot ) || Lexer . is ( AsmToken :: Integer ) || Lexer . is ( AsmToken :: Real ) || Lexer . is ( AsmToken :: Colon ) ; bool Workaround = Lexer . is ( AsmToken :: Colon ) || Lookahead . back ( ) . is ( AsmToken :: Colon ) ; Again = ( Contigious && Type ) || ( Workaround && Type ) ; NeededWorkaround = NeededWorkaround || ( Again && ! ( Contigious && Type ) ) ; } std :: string Collapsed = std :: string ( RawString ) ; llvm :: erase_if ( Collapsed , isSpace ) ; StringRef FullString = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = FullString . split ( '.' ) ; unsigned DotReg = matchRegister ( DotSplit . first . lower ( ) ) ; if ( DotReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { if ( DotSplit . second . empty ( ) ) { RegNo = DotReg ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } else { RegNo = DotReg ; size_t First = RawString . find ( '.' ) ; StringRef DotString ( RawString . data ( ) + First , RawString . size ( ) - First ) ; Lexer . UnLex ( AsmToken ( AsmToken :: Identifier , DotString ) ) ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return MatchOperand_NoMatch ; return MatchOperand_Success ;


<s> static bool v850_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) {

return GET_MODE_SIZE ( mode ) <= <NUM_LIT> || ( ( regno & <NUM_LIT> ) == <NUM_LIT> && regno != <NUM_LIT> ) ;


<s> void <ISA_LIT>AsmPrinter :: emitInstruction ( const MachineInstr * MI ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ;

EmitToStreamer ( * OutStreamer , TmpInst ) ;


<s> unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ; auto PMADDWDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { MVT VT = <STR_LIT> ( <STR_LIT> , Ops [ <NUM_LIT> ] . getValueSizeInBits ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } ; SDValue Madd = SplitOpsAndApply ( DAG , Subtarget , DL , MAddVT , { N0 , N1 } , PMADDWDBuilder ) ; SDValue Zero = getZeroVector ( Madd . getSimpleValueType ( ) , Subtarget , DAG , DL ) ; SDValue Concat = DAG . getNode ( <STR_LIT> , DL , VT , Madd , Zero ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , Concat , Phi ) ;


<s> static void insertCSRSaves ( MachineBasicBlock & SaveBlock , ArrayRef < CalleeSavedInfo > C<ISA_LIT> , LiveIntervals * LIS ) { MachineFunction & MF = * SaveBlock . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineBasicBlock :: iterator I = SaveBlock . begin ( ) ; if ( ! TFI -> spillCalleeSavedRegisters ( SaveBlock , I , C<ISA_LIT> , TRI ) ) { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( const CalleeSavedInfo & CS : C<ISA_LIT> ) { MCRegister Reg = CS . getReg ( ) ; MachineInstrSpan MIS ( I , & SaveBlock ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , <STR_LIT> ) ; const bool IsLiveIn = MRI . isLiveIn ( Reg ) ; TII . storeRegToStackSlot ( SaveBlock , I , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ; if ( LIS ) { assert ( std :: distance ( MIS . begin ( ) , I ) == <NUM_LIT> ) ; MachineInstr & Inst = * std :: prev ( I ) ; LIS -> InsertMachineInstrInMaps ( Inst ) ; LIS -> removeAllRegUnitsForPhysReg ( Reg ) ; } }


<s> emit_insn ( gen_strmov ( destptr , dest , srcptr , src ) ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ; } } else { rtx offset = force_reg ( Pmode , const0_rtx ) ; rtx tmp ; if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; src = change_address ( srcmem , SImode , srcptr ) ; dest = change_address ( destmem , SImode , destptr ) ; emit_move_insn ( dest , src ) ; tmp = expand_simple_binop ( Pmode , PLUS , offset , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_LIB_WIDEN ) ; if ( tmp != offset ) emit_move_insn ( offset , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ; } if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; tmp = gen_rtx_PLUS ( Pmode , srcptr , offset ) ; src = change_address ( srcmem , HImode , tmp ) ; tmp = gen_rtx_PLUS ( Pmode , destptr , offset ) ; dest = change_address ( destmem , HImode , tmp ) ; emit_move_insn ( dest , src ) ; tmp = expand_simple_binop ( Pmode , PLUS , offset , GEN_INT ( <NUM_LIT> ) , tmp , true , OPTAB_LIB_WIDEN ) ; if ( tmp != offset ) emit_move_insn ( offset , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = <NUM_LIT> ; } if ( max_size > <NUM_LIT> ) { rtx_code_label * label = ix86_expand_aligntest ( count , <NUM_LIT> , true ) ; tmp = gen_rtx_PLUS ( Pmode , srcptr , offset ) ; src = change_address ( srcmem , QImode , tmp ) ; tmp = gen_rtx_PLUS ( Pmode , destptr , offset ) ; dest = change_address ( destmem , QImode , tmp ) ; emit_move_insn ( dest , src ) ;


<s> case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; default : return - <NUM_LIT> ; }


if ( ! global_entry_needed_p || cfun -> machine -> global_entry_emitted ) default_print_patchable_function_entry ( file , patch_area_size , record_p ) ;


<s> case SWL : case SHL : case SBL : return <STR_LIT> ; case LWC : case LHC : case LBC : case LHUC : case LBUC : case SWC : case SHC : case SBC : return <STR_LIT> ; case LWM : case LHM : case LBM : case LHUM : case LBUM : case SWM : case SHM : case SBM : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;


<s> Scale = getI8Imm ( AM . Scale ) ; Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , DebugLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ;

else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ;


<s> SDLoc DL ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerToBTST ( Op0 , CC , DL , DAG ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CCode , DL , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( Op0 . getValueType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isOneConstant ( Op1 ) ) { <STR_LIT> NewCC = <STR_LIT> :: getSetCCInverse ( CC , true ) ; return DAG . getSetCC ( DL , VT , Op0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , NewCC ) ; } if ( ! isNullConstant ( Op1 ) ) { SDValue Xor = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ;

return DAG . getSetCC ( DL , VT , Xor , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CC ) ;


<s> SDValue Addr , VecIndex ; unsigned Alignment ; if ( ! getParamsForOneTrueMaskedElt ( MS , DAG , Addr , VecIndex , Alignment ) ) return SDValue ( ) ; SDLoc DL ( MS ) ; EVT VT = MS -> getValue ( ) . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ;

SDValue Extract = DAG . getNode ( <STR_LIT> , DL , EltVT , MS -> getValue ( ) , VecIndex ) ;


<s> if ( epilogue_completed && RTX_FRAME_RELATED_P ( cur_insn ) ) { if ( GET_CODE ( pat ) == SET && GENERAL_REG_P ( SET_DEST ( pat ) ) ) { if ( GET_MODE ( SET_SRC ( pat ) ) == DImode && FP_REG_P ( SET_SRC ( pat ) ) ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == MEM ) continue ; } if ( GET_CODE ( pat ) == PARALLEL && load_multiple_operation ( pat , VOIDmode ) ) continue ; } note_stores ( cur_insn , s390_reg_clobbered_rtx , regs_ever_clobbered ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitGlobalType ( const MCSymbolWasm * Sym ) { assert ( Sym -> isGlobal ( ) ) ; OS << <STR_LIT> << Sym -> getName ( ) << <STR_LIT> << <STR_LIT> ( static_cast < <STR_LIT> > ( Sym -> getGlobalType ( ) . Type ) ) ; if ( ! Sym -> getGlobalType ( ) . Mutable ) OS << <STR_LIT> ; OS << '\n' ;


<s> void <ISA_LIT>InstPrinter :: printU3ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) {

printUImmOperand < <NUM_LIT> > ( MI , OpNum , O ) ;


<s> if ( ( <NUM_LIT> + ( MMIX_FUNCTION_ARG_SIZE ( arg . mode , arg . type ) ) ) / <NUM_LIT> != <NUM_LIT> ) internal_error ( <STR_LIT> ) ;


<s> SDNode * N = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , elemType , reg , NIndex ) ;


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override {


<s> void print ( raw_ostream & OS ) const {


<s> if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) HSAMetadataStream -> begin ( M ) ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) getTargetStreamer ( ) -> getPALMetadata ( ) -> readFromIR ( M ) ; if ( isHsaAbiVersion3 ( getGlobalSTI ( ) ) ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectVersion ( <NUM_LIT> , <NUM_LIT> ) ;

IsaVersion Version = getIsaVersion ( getGlobalSTI ( ) -> getCPU ( ) ) ;


return ( unsigned char ) __builtin_ia32_ktestzhi ( __A , __B ) ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; addPass ( createMVEGatherScatterLoweringPass ( ) ) ;

addPass ( createMVELaneInterleavingPass ( ) ) ;


<s> if ( lastVreg && VReg == * lastVreg ) lastPos = curStack . position ( lastPos + <NUM_LIT> , VReg ) ; else lastPos = curStack . position ( VReg ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( Subtarget . is64Bit ( ) && Type == <STR_LIT> ) return true ; return IsSigned ;


<s> if ( HasSSE2 && VT == <STR_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ;


<s> SDLoc DL ( N ) ; const SDValue And = N -> getOperand ( <NUM_LIT> ) ; if ( And . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Shift = N -> getOperand ( <NUM_LIT> ) ; unsigned ShiftOpc = Shift . getOpcode ( ) ; if ( ( ShiftOpc != <STR_LIT> && ShiftOpc != <STR_LIT> ) ) return SDValue ( ) ; bool IsShiftRight = ShiftOpc == <STR_LIT> ; ConstantSDNode * C2node = dyn_cast < ConstantSDNode > ( Shift . getOperand ( <NUM_LIT> ) ) ; if ( ! C2node ) return SDValue ( ) ; uint64_t C1 ; if ( ! isAllConstantBuildVector ( And . getOperand ( <NUM_LIT> ) , C1 ) ) return SDValue ( ) ; uint64_t C2 = C2node -> getZExtValue ( ) ; unsigned ElemSizeInBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( C2 > ElemSizeInBits ) return SDValue ( ) ; unsigned ElemMask = ( <NUM_LIT> << ElemSizeInBits ) - <NUM_LIT> ; if ( ( C1 & ElemMask ) != ( ~ C2 & ElemMask ) ) return SDValue ( ) ; SDValue X = And . getOperand ( <NUM_LIT> ) ; SDValue Y = Shift . getOperand ( <NUM_LIT> ) ; unsigned Intrin = IsShiftRight ? <STR_LIT> : <STR_LIT> ; SDValue ResultSLI = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Intrin , DL , <STR_LIT> ) , X , Y , Shift . getOperand ( <NUM_LIT> ) ) ;


<s> for ( uint16_t i = B ; i < B + W ; ++ i ) if ( ! RC [ i ] . is ( <NUM_LIT> ) ) return false ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> ArgVal = convertArgType ( DAG , VT , MemVT , SL , ArgVal , Signed , Arg ) ; return DAG . getMergeValues ( { ArgVal , Load . getValue ( <NUM_LIT> ) } , SL ) ; } SDValue Ptr = lowerKernArgParameterPtr ( DAG , SL , Chain , Offset ) ; SDValue Load = DAG . getLoad ( MemVT , SL , Chain , Ptr , PtrInfo , Align , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; SDValue Val = convertArgType ( DAG , VT , MemVT , SL , Load , Signed , Arg ) ;

return DAG . getMergeValues ( { Val , Load . getValue ( <NUM_LIT> ) } , SL ) ;


<s> vmvnq_u32 ( uint32x4_t a ) { uint32x4_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> Value * <ISA_LIT>TargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilderBase & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const { assert ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && <STR_LIT> ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = Incr -> getType ( ) ; assert ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) ; Function * RMW = <STR_LIT> ( M , getIntrinsicForAtomicRMWBinOp128 ( AI -> getOperation ( ) ) ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ;

Value * IncrLo = Builder . CreateTrunc ( Incr , Int64Ty , <STR_LIT> ) ;


return ( ( vec_ullong2 ) ( si_dfcgt ( ( qword ) ( a ) , ( qword ) ( b ) ) ) ) ;


<s> O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( DL , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getPointerElementType ( ) ; if ( isABI || isKernelFunc ) { Align align = DL . getValueOrABITypeAlignment ( PAL . getParamAlignment ( paramIndex ) , ETy ) ; if ( ! isKernelFunc && align < Align ( <NUM_LIT> ) ) align = Align ( <NUM_LIT> ) ; unsigned sz = DL . getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align . value ( ) << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , DL , ETy , vtparts ) ;

for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) {


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> <ISA_LIT>SplitConst32AndConst64 ( ) : MachineFunctionPass ( ID ) {


<s> bool <ISA_LIT>DCInstruction :: translateImplicit ( unsigned RegNo ) {


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override {

const MCInstrDesc & MID = MII . get ( Inst . getOpcode ( ) ) ;


return ( __m128i ) __builtin_ia32_pmovuswb128_mask ( ( __v8hi ) __A , ( __v16qi ) _mm_setzero_si128 ( ) , __M ) ;


<s> if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( peekThroughBitcasts ( SubVec2 ) ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment ( ) ; unsigned AS = FirstLd -> getAddressSpace ( ) ; const <ISA_LIT>TargetLowering * TLI = Subtarget . getTargetLowering ( ) ; if ( TLI -> allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , OpVT , AS , Alignment , & Fast ) && Fast ) { SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Ld = EltsFromConsecutiveLoads ( OpVT , Ops , dl , DAG , Subtarget , false ) ) return Ld ; } } if ( auto * Ld = dyn_cast < LoadSDNode > ( peekThroughOneUseBitcasts ( SubVec2 ) ) ) if ( SubVec2 == SubVec && <STR_LIT> ( Ld ) && SDNode :: areOnlyUsersOf ( { N , Vec . getNode ( ) } , SubVec2 . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec ) ; if ( SubVec . getOpcode ( ) == <STR_LIT> && SubVec == SubVec2 ) return DAG . getNode ( <STR_LIT> , dl , OpVT , SubVec . getOperand ( <NUM_LIT> ) ) ; if ( <STR_LIT> ( SubVec . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , OpVT , getZeroVector ( OpVT , Subtarget , DAG , dl ) , SubVec2 , Vec . getOperand ( <NUM_LIT> ) ) ; if ( ! Vec . getOperand ( <NUM_LIT> ) . isUndef ( ) && Vec . hasOneUse ( ) ) { Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getUNDEF ( OpVT ) , SubVec2 , Vec . getOperand ( <NUM_LIT> ) ) ; DCI . AddToWorklist ( Vec . getNode ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , SubVec , Idx ) ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( unsigned ( getBankedReg ( ) ) ) ) ;


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ;

bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;


<s> bool isSImm6 ( ) const { if ( ! isImm ( ) ) return false ; <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ;

bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;


<s> } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { SDValue V0 = BVN -> getOperand ( <NUM_LIT> ) ; SDValue V1 = BVN -> getOperand ( <NUM_LIT> ) ; if ( V0 . isUndef ( ) ) V0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; if ( V1 . isUndef ( ) ) V1 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( V0 ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( V1 ) ; if ( ! C0 || ! C1 ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; if ( isInt < <NUM_LIT> > ( C0 -> getSExtValue ( ) ) || isInt < <NUM_LIT> > ( C1 -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { if ( BVN -> getOperand ( i ) . isUndef ( ) ) continue ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( i ) ) ; if ( ! Cst ) { SDValue pack = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BVN -> getOperand ( <NUM_LIT> ) , BVN -> getOperand ( <NUM_LIT> ) ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , pack ) ; } } } uint64_t Res = <NUM_LIT> ; unsigned EltSize = Size / NElts ; SDValue ConstVal ; uint64_t Mask = ~ uint64_t ( <NUM_LIT> ) >> ( <NUM_LIT> - EltSize ) ; bool HasNonConstantElements = false ; for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { unsigned OpIdx = NElts - i - <NUM_LIT> ; SDValue Operand = BVN -> getOperand ( OpIdx ) ; if ( Operand . isUndef ( ) ) continue ; int64_t Val = <NUM_LIT> ; if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Operand ) ) Val = Cst -> getSExtValue ( ) ; else HasNonConstantElements = true ;


<s> unsigned int i = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_simd_intrinsic_data ) ; ++ i ) { auto d = & aarch64_simd_intrinsic_data [ i ] ; if ( d -> skip ) continue ; tree return_type = void_type_node ; tree args = void_list_node ; for ( int op_num = d -> op_count - <NUM_LIT> ; op_num >= <NUM_LIT> ; op_num -- ) { machine_mode op_mode = d -> op_modes [ op_num ] ; enum aarch64_type_qualifiers qualifiers = d -> qualifiers [ op_num ] ; tree eltype = aarch64_simd_builtin_type ( op_mode , qualifiers ) ; if ( op_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } tree ftype = build_function_type ( return_type , args ) ; tree attrs = aarch64_get_attributes ( FLAG_AUTO_FP , d -> op_modes [ <NUM_LIT> ] ) ;

unsigned int code = ( d -> fcode << AARCH64_BUILTIN_SHIFT | AARCH64_BUILTIN_GENERAL ) ;


<s> if ( type ) return int_size_in_bytes ( type ) ; if ( mode != BLKmode ) return GET_MODE_SIZE ( mode ) ;


<s> static bool isLDSTPPI ( InsnType insn ) {

return ( ( ( insn ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectT2ShifterOperandReg ( SDValue N , SDValue & BaseReg , SDValue & Opc ) { if ( DisableShifterOp ) return false ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = getI32Imm ( <STR_LIT> ( ShOpcVal , ShImmVal ) , SDLoc ( N ) ) ;


<s> SDNodeFlags Flags = Old . getNode ( ) -> getFlags ( ) ;


<s> void mmix_make_decl_one_only ( tree decl ) {


<s> static void vax_option_override ( void ) {

if ( TARGET_G_FLOAT ) REAL_MODE_FORMAT ( DFmode ) = & vax_g_format ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> bool isSOPK ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> if ( VLIndex >= <NUM_LIT> ) { Register DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( MI . getOperand ( VLIndex ) . getReg ( ) ) ; } else MIB . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) ; bool TailAgnostic = true ; unsigned UseOpIdx ; if ( MI . isRegTiedToUseOperand ( <NUM_LIT> , & UseOpIdx ) && ! WritesElement0 ) { TailAgnostic = false ;

const MachineOperand & UseMO = MI . getOperand ( UseOpIdx ) ;


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; unsigned NumArgs = MI . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . add ( Op ) ; } if ( MI . hasOneMemOperand ( ) ) MIB -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ;


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __vis_edge32 ( void * __A , void * __B ) { return __builtin_vis_edge32 ( __A , __B ) ;


<s> if ( CmpOpc == <STR_LIT> ) return isUInt < <NUM_LIT> > ( Imm ) ; if ( CmpOpc == <STR_LIT> ) return isInt < <NUM_LIT> > ( Imm ) ; return true ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) {

unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ;


<s> return new AMDGPUCFGPrepare ( tm ) ;


<s> __o = __builtin_aarch64_ld2rv16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ;

ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregoiv16qi ( __o , <NUM_LIT> ) ;


<s> if ( emit_type == EMIT_DIRECT ) emit_insn ( pat ) ; else if ( emit_type == EMIT_BEFORE ) emit_insn_before ( pat , rinsn ) ; else emit_insn_after ( pat , rinsn ) ;


<s> std :: string getLinkStringForBuiltIn ( :: BuiltIn :: BuiltIn BuiltInValue ) { const SymbolicOperand * Lookup = lookupSymbolicOperandByCategoryAndValue ( :: OperandCategory :: BuiltInOperand , BuiltInValue ) ; if ( Lookup ) return <STR_LIT> + Lookup -> Mnemonic . str ( ) ;


<s> assert ( opcode == <STR_LIT> || opcode == <STR_LIT> ) ; SDValue SrcReg64 = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi32 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg64 ) ; SDValue Lo32 = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , SrcReg64 ) ; Hi32 = DAG . getNode ( opcode , dl , <STR_LIT> , Hi32 ) ;

SDValue DstReg64 = SDValue ( DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) , <NUM_LIT> ) ;


<s> DT . add ( LLVMTy , CurMF , get<ISA_LIT>TypeID ( SpirvType ) ) ;


<s> MCInstLowering . Initialize ( Mang , & MF -> getContext ( ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; }

} else if ( Subtarget . isTargetELF ( ) ) {


<s> return MF . getFrameInfo ( ) -> hasStackObjects ( ) ;


<s> return ( int8x8_t ) __builtin_aarch64_subhnv8hi ( __a , __b ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < AN -> getNumOperands ( ) ; ++ i ) Ops . push_back ( AN -> getOperand ( i ) ) ; Ops . push_back ( CurDAG -> getTargetConstant ( AN -> getOrdering ( ) , <STR_LIT> ) ) ;

Ops . push_back ( AN -> getOperand ( <NUM_LIT> ) ) ;


<s> const char * function_resolver :: get_scalar_type_name ( type_suffix_index type ) {

return vector_types [ type_suffixes [ type ] . vector_type ] . acle_name + <NUM_LIT> ;


<s> } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else return false ; if ( ! isT2 && ( Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) != Op1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( ! Op0 -> hasOneMemOperand ( ) || ! ( * Op0 -> memoperands_begin ( ) ) -> getValue ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getPrefTypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( Op0 ) ; if ( isT2 ) { if ( OffImm < <NUM_LIT> ) { if ( OffImm < - <NUM_LIT> ) return false ; } else { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; } Offset = OffImm ; } else {


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! LocalSData && GV -> hasLocalLinkage ( ) ) return false ;

if ( ! ExternSData && ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV -> hasCommonLinkage ( ) ) ) return false ;


<s> initialize<ISA_LIT>PreEmitImmPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> static void AnalyzeVarArgs ( CCState & State , const SmallVectorImpl < <STR_LIT> > & Ins ) {

State . AnalyzeFormalArguments ( Ins , CC_Mandarin_AssignStack ) ;


<s> bool <ISA_LIT>FrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( ! RegInfo -> hasStackRealignment ( * MF ) ) return true ;

return findScratchNonCalleeSaveRegister ( TmpMBB ) != <STR_LIT> ;


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) { default : break ; case <STR_LIT> : return LowerHvxBuildVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSplatVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxBitcast ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxCttz ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSelect ( Op , DAG ) ;


<s> for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>64Target ( ) } ) { TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>InstrAnalysis ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ;


<s> if ( <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) ) return getRegBank ( <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) || <STR_LIT> . hasSubClassEq ( & RC ) ) return getRegBank ( <STR_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , TargetOptions Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) {


<s> for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ;

I != E ; ++ I ) printModuleLevelGV ( I ) ;


<s> if ( frame_pointer_needed ) { emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; amount = offsets -> locals_base - offsets -> saved_regs ; } if ( amount ) { if ( amount < <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ; else { rtx reg = gen_rtx_REG ( SImode , LAST_ARG_REGNUM ) ; emit_insn ( gen_movsi ( reg , GEN_INT ( amount ) ) ) ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , reg ) ) ;


<s> return SDValue ( ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ;


<s> void <ISA_LIT>InstPrinter :: printOpExtInst ( const MCInst * MI , raw_ostream & O ) { llvm_unreachable ( <STR_LIT> ) ;


<s> for ( auto & Node1 : VectorNode ) Node1 -> setVisit ( false ) ; val += printTreeVal ( Root ) ; return val ;


<s> rs6000_function_arg_advance_1 ( get_cumulative_args ( cum ) , arg . mode , arg . type , arg . named , <NUM_LIT> ) ;


<s> if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) { OutMI . setOpcode ( TII -> pseudoToMCOpcode ( <STR_LIT> ) ) ; MCOperand Dest , Src ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Dest ) ; lowerOperand ( MI -> getOperand ( <NUM_LIT> ) , Src ) ; OutMI . addOperand ( Dest ) ; OutMI . addOperand ( Src ) ; return ; } else if ( Opcode == <STR_LIT> ) { Opcode = <STR_LIT> ; } int MCOpcode = TII -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) . getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp ; lowerOperand ( MO , MCOp ) ; OutMI . addOperand ( MCOp ) ; }

int FIIdx = <STR_LIT> ( MCOpcode , <STR_LIT> :: fi ) ;


<s> Stub * <ISA_LIT>ToTHMStub :: doClone ( ) {

return new <ISA_LIT>ToTHMStub ( m_pData , m_Size , fixup_begin ( ) , fixup_end ( ) ) ;


<s> case <NUM_LIT> : case 'c' : case 'C' : case <NUM_LIT> : case 'z' : case 'Z' : case <NUM_LIT> : case 's' : case 'S' : case <NUM_LIT> : case 'o' : case 'O' :


<s> bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , RegState :: Kill ) . addReg ( DstReg , RegState :: Kill ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MIRRC -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ;


<s> if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> needsStackRealignment ( MF ) ) { unsigned MaxAlignment = MFI . getMaxAlignment ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment ) ; } else { unsigned ShiftAmount = countTrailingZeros ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ; } if ( hasBP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , BPReg ) . addReg ( SPReg ) . addImm ( <NUM_LIT> ) ; }


<s> return new <ISA_LIT>FixSGPRCopies ( ) ;


<s> if ( MO . isImm ( ) ) { switch ( MI -> getOpcode ( ) ) { default : int32_t TruncatedImm = static_cast < int32_t > ( MO . getImm ( ) ) ; O << TruncatedImm ; return ; } } assert ( MO . isExpr ( ) && <STR_LIT> ) ; MO . getExpr ( ) -> print ( O , & MAI ) ;


<s> if ( ( EltIdx < <NUM_LIT> || EltIdx == ( int ) i ) && ( SndLaneEltIdx < <NUM_LIT> || SndLaneEltIdx == ( int ) ( i + NumElemsInLane ) ) ) continue ; if ( ( ( unsigned ) EltIdx == ( i + NumElems ) ) && ( SndLaneEltIdx < <NUM_LIT> || ( unsigned ) SndLaneEltIdx == i + NumElems + NumElemsInLane ) ) MaskValue |= ( <NUM_LIT> << i ) ; else return SDValue ( ) ; } MVT BlendVT = VT ; if ( EltVT == <STR_LIT> || ( EltVT == <STR_LIT> && ! Subtarget -> hasInt256 ( ) ) ) { BlendVT = <STR_LIT> ( <STR_LIT> ( EltVT . getSizeInBits ( ) ) , NumElems ) ;

V1 = DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ;


<s> SynchronizationScope FenceScope = static_cast < SynchronizationScope > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; if ( FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread ) { if ( Subtarget -> hasSSE2 ( ) || Subtarget -> is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) , Zero , Chain } ; SDNode * Res = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; return SDValue ( Res , <NUM_LIT> ) ;


<s> assert ( TFI -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } assert ( ! MI . isDebugValue ( ) && <STR_LIT> ) ; bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ; } if ( Done ) return ; assert ( ( Offset || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> || ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ScratchReg = <NUM_LIT> ; int PIdx = MI . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ;

unsigned PredReg = ( PIdx == - <NUM_LIT> ) ? <NUM_LIT> : MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ;


<s> const ConstantSDNode * CN = cast < ConstantSDNode > ( N ) ; Pred = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return true ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , R ) . addReg ( R ) ; }

if ( To == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return <NUM_LIT> ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > <NUM_LIT> && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! EnableOldKNLABI && Subtarget . useAVX512Regs ( ) && ! Subtarget . hasBWI ( ) ) return <NUM_LIT> ;

return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ;


<s> bool hasGridWorkgroupCountX ( ) const {


<s> tree id = TREE_VALUE ( TREE_VALUE ( attr ) ) ; const char * name ; if ( TREE_CODE ( id ) == IDENTIFIER_NODE ) name = IDENTIFIER_POINTER ( id ) ; else if ( TREE_CODE ( id ) == STRING_CST ) name = TREE_STRING_POINTER ( id ) ; else abort ( ) ; fprintf ( file , <STR_LIT> , name ) ;


<s> unsigned TargetFlags = get ( Opcode ) . TSFlags ;

return ( ( TargetFlags & <STR_LIT> ) | ( TargetFlags & <STR_LIT> ) ) ;


<s> return SelectStore ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; } return false ;


<s> report_non_ice ( location , fndecl , argno ) ; return false ; }