<s> MachineFunction :: iterator MBBIter = MBB ; ++ MBBIter ; MachineBasicBlock * XMMSaveMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = MBB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI -> getNumOperands ( ) <= <NUM_LIT> || ! MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget -> hasFp256 ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI -> getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ;


<s> if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; Peephole<ISA_LIT>64 ( ) ;


<s> int64_t rotamt = - vtm -> prefslot_byte ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( rotamt , PtrVT ) ) ; } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; } rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( - vtm -> prefslot_byte , PtrVT ) ) ; } result = DAG . getLoad ( <STR_LIT> , dl , the_chain , basePtr , LN -> getSrcValue ( ) , LN -> getSrcValueOffset ( ) , LN -> isVolatile ( ) , <NUM_LIT> ) ; the_chain = result . getValue ( <NUM_LIT> ) ; result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , result . getValue ( <NUM_LIT> ) , rotate ) ; MVT vecVT = <STR_LIT> ( InVT , ( <NUM_LIT> / InVT . getSizeInBits ( ) ) ) ; result = DAG . getNode ( <STR_LIT> , dl , InVT , DAG . getNode ( <STR_LIT> , dl , vecVT , result ) ) ; if ( ExtType == <STR_LIT> ) { result = DAG . getNode ( <STR_LIT> , dl , OutVT , result ) ; } else if ( ExtType == <STR_LIT> ) { result = DAG . getNode ( <STR_LIT> , dl , OutVT , result ) ; } else if ( ExtType == <STR_LIT> ) { unsigned NewOpc = <STR_LIT> ; if ( OutVT . isFloatingPoint ( ) ) NewOpc = <STR_LIT> ; result = DAG . getNode ( NewOpc , dl , OutVT , result ) ; } SDVTList retvts = DAG . getVTList ( OutVT , <STR_LIT> ) ; SDValue retops [ <NUM_LIT> ] = {


<s> auto * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( RVFI -> isHwlpBasicBlock ( & MBB ) ) {


<s> bool Tile64VLIWPacketizerList :: isDirectJump ( const MachineInstr * MI ) const { return ( MI -> getOpcode ( ) == <STR_LIT> ) ;


<s> if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( llvm :: next ( I ) != MBB . end ( ) ) llvm :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; return true ; }


<s> ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ;


<s> int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , <STR_LIT> ) ; COffsetVal = SplitImmOffset ; SDValue AddOffset = SAddr . getOpcode ( ) == <STR_LIT> ? getMaterializedScalarImm32 ( Lo_32 ( RemainderOffset ) , DL ) : CurDAG -> getTargetConstant ( RemainderOffset , DL , <STR_LIT> ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SAddr , AddOffset ) , <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( COffsetVal , DL , <STR_LIT> ) ; return true ;


<s> const CCValAssign & VA = ArgLocs [ i ] ; CCValAssign :: LocInfo LocInfo = determineLocInfo ( Arguments [ i ] . VT , Arguments [ i ] . ArgVT , Arguments [ i ] . Flags ) ; if ( VA . isMemLoc ( ) ) ArgLocs [ i ] = CCValAssign :: getMem ( VA . getValNo ( ) , VA . getValVT ( ) , VA . getLocMemOffset ( ) , VA . getLocVT ( ) , LocInfo ) ; else ArgLocs [ i ] = CCValAssign :: getReg ( VA . getValNo ( ) , VA . getValVT ( ) , VA . getLocReg ( ) , VA . getLocVT ( ) , LocInfo ) ;


<s> static int rid_int128 ( void ) { int i ; for ( i = <NUM_LIT> ; i < NUM_INT_N_ENTS ; i ++ ) if ( int_n_enabled_p [ i ] && int_n_data [ i ] . bitsize == <NUM_LIT> ) return RID_INT_N_0 + i ; return RID_MAX + <NUM_LIT> ;


<s> if ( NamedMD && NamedMD -> getNumOperands ( ) ) { BlobType = ELF :: NT_<ISA_LIT>_METADATA ; auto MDN = dyn_cast < MDTuple > ( NamedMD -> getOperand ( <NUM_LIT> ) ) ; if ( MDN && MDN -> getNumOperands ( ) ) { if ( auto MDS = dyn_cast < MDString > ( MDN -> getOperand ( <NUM_LIT> ) ) ) setFromMsgPackBlob ( MDS -> getString ( ) ) ; } return ; } BlobType = ELF :: NT_AMD_<ISA_LIT>_PAL_METADATA ; NamedMD = M . getNamedMetadata ( <STR_LIT> ) ; if ( ! NamedMD || ! NamedMD -> getNumOperands ( ) ) { BlobType = ELF :: NT_<ISA_LIT>_METADATA ; return ;


<s> if ( ! IsSigned && ! Subtarget -> hasFPCVT ( ) ) return false ; if ( DstVT == <STR_LIT> && ! Subtarget -> hasFPCVT ( ) ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { Register TmpReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , TmpReg , ! IsSigned ) ) return false ; SrcVT = <STR_LIT> ; SrcReg = TmpReg ; } unsigned FPReg = <ISA_LIT>MoveToFPReg ( SrcVT , SrcReg , IsSigned ) ; if ( FPReg == <NUM_LIT> ) return false ; const TargetRegisterClass * RC = & <STR_LIT> ; Register DestReg = createResultReg ( RC ) ; unsigned Opc ; if ( DstVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( FPReg ) ;


<s> Thumb2InstrInfo :: Thumb2InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>BaseInstrInfo ( STI ) , RI ( ) {


<s> Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC , DL ) ) ; SDValue Glue = emitCmp ( DAG , DL , C ) ; return emitSETCC ( DAG , DL , Glue , C . CCValid , C . CCMask ) ;


<s> static rtx aapcs_libcall_value ( machine_mode mode ) { if ( BYTES_BIG_ENDIAN && ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) mode = SImode ;

return aapcs_allocate_return_reg ( mode , NULL_TREE , NULL_TREE ) ;


<s> void <ISA_LIT>MachineFunctionInfo :: anchor ( ) {


<s> BUILTIN_VDQF ( UNOP , abs , <NUM_LIT> ) return fold_build1 ( ABS_EXPR , type , args [ <NUM_LIT> ] ) ; VAR1 ( UNOP , floatv2si , <NUM_LIT> , v2sf ) VAR1 ( UNOP , floatv4si , <NUM_LIT> , v4sf ) VAR1 ( UNOP , floatv2di , <NUM_LIT> , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ <NUM_LIT> ] ) ; default : break ; }


<s> } else { MachineBasicBlock :: iterator It = MBB . getFirstTerminator ( ) ; assert ( It -> isReturn ( ) && std :: next ( It ) == MBB . end ( ) ) ; unsigned ROpc = IsPIC ? <STR_LIT> : <STR_LIT> ; DeallocCall = BuildMI ( MBB , It , DL , HII . get ( ROpc ) ) . addExternalSymbol ( RestoreFn ) ; DeallocCall -> copyImplicitOps ( MF , * It ) ; } addCalleeSaveRegistersAsImpOperand ( DeallocCall , CSI , true , false ) ; return true ; } for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( Reg ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; HII . loadRegFromStackSlot ( MBB , MI , Reg , FI , RC , & HRI ) ;


<s> inline unsigned rotr32 ( unsigned Val , unsigned Amt ) { assert ( Amt < <NUM_LIT> && <STR_LIT> ) ; return ( Val >> Amt ) | ( Val << ( ( <NUM_LIT> - Amt ) & <NUM_LIT> ) ) ;


<s> assert ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setImm ( FrameOffset ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; } else { auto & MRI = MF . getRegInfo ( ) ; const auto * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( FrameOffset ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , OffsetReg ) . addReg ( <STR_LIT> ) . addReg ( OffsetReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( OffsetReg , false ) ;


<s> unsigned msb = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned lsb = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( lsb > msb ) { Check ( S , MCDisassembler :: SoftFail ) ; lsb = msb ; } uint32_t msb_mask = <NUM_LIT> ; if ( msb != <NUM_LIT> ) msb_mask = ( <NUM_LIT> << ( msb + <NUM_LIT> ) ) - <NUM_LIT> ; uint32_t lsb_mask = ( <NUM_LIT> << lsb ) - <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( ~ ( msb_mask ^ lsb_mask ) ) ) ; return S ;


<s> while ( Depth -- ) { int Offset = - ( XLenInBytes * <NUM_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ;


<s> return QUAL_TYPE ( SI ) ; case E_DImode : return QUAL_TYPE ( DI ) ; case E_TImode : return QUAL_TYPE ( TI ) ; case E_OImode : return arm_simd_intOI_type_node ; case E_EImode : return arm_simd_intEI_type_node ; case E_CImode : return arm_simd_intCI_type_node ; case E_XImode : return arm_simd_intXI_type_node ; case E_HFmode : return arm_fp16_type_node ; case E_SFmode :


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectArgLd ( MemSDNode * Node ) const { bool IsRetLd = Node -> getConstantOperandVal ( <NUM_LIT> ) ; bool IsSext = Node -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue Base , Reg , Offset ; if ( ! SelectAddr ( Node -> getOperand ( <NUM_LIT> ) , Base , Reg , Offset ) ) return nullptr ; MVT MemVT = Node -> getMemoryVT ( ) . getSimpleVT ( ) ; BrigType BT = getBrigType ( MemVT . SimpleTy , IsSext ) ; SDLoc SL ( Node ) ;


<s> if ( ( Idx >= <NUM_LIT> && Idx < LHSMaxIdx ) || ( Idx >= RHSMinIdx && Idx < RHSMaxIdx ) ) ShuffV [ i ] += HalfVec ; }


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;

if ( TRI -> hasBasePointer ( MF ) ) SavedRegs . set ( TRI -> getBaseRegister ( ) ) ;


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue NewV = ( Elt < ( int ) NumElems ) ? SV -> getOperand ( <NUM_LIT> ) : SV -> getOperand ( <NUM_LIT> ) ; return getShuffleScalarElt ( NewV . getNode ( ) , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( isTargetShuffle ( Opcode ) ) { MVT ShufVT = V . getSimpleValueType ( ) ; MVT ShufSVT = ShufVT . getVectorElementType ( ) ; int NumElems = ( int ) ShufVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool IsUnary ; if ( ! getTargetShuffleMask ( N , ShufVT , true , ShuffleMask , IsUnary ) ) return SDValue ( ) ; int Elt = ShuffleMask [ Index ] ; if ( Elt == SM_SentinelZero ) return ShufSVT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , ShufSVT ) : DAG . getConstantFP ( + <NUM_LIT> , SDLoc ( N ) , ShufSVT ) ; if ( Elt == SM_SentinelUndef ) return DAG . getUNDEF ( ShufSVT ) ; assert ( <NUM_LIT> <= Elt && Elt < ( <NUM_LIT> * NumElems ) && <STR_LIT> ) ; SDValue NewV = ( Elt < NumElems ) ? N -> getOperand ( <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> ) ;


<s> SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; unsigned OpCode = Subtarget -> hasFP32Denormals ( ) ? ( unsigned ) <STR_LIT> : ( unsigned ) <STR_LIT> ; SDValue fr = DAG . getNode ( OpCode , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ; fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT , iq , jq ) ; SDValue Rem = DAG . getNode ( <STR_LIT> , DL , VT , Div , RHS ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , LHS , Rem ) ; if ( Sign ) { SDValue InRegSize = DAG . getValueType ( EVT :: getIntegerVT ( * DAG . getContext ( ) , DivBits ) ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , InRegSize ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , InRegSize ) ; } else { SDValue TruncMask = DAG . getConstant ( ( UINT64_C ( <NUM_LIT> ) << DivBits ) - <NUM_LIT> , DL , VT ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , TruncMask ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , TruncMask ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetNoMicro<ISA_LIT> ( ) { Micro<ISA_LIT>Enabled = false ;


<s> assert ( Align > <NUM_LIT> && <STR_LIT> ) ; unsigned Idx = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; const TargetRegisterClass * RC = ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Align ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ;


<s> if ( VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned DestReg = createResultReg ( RC ) ; const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; bool IsThreadLocal = GVar && GVar -> isThreadLocal ( ) ; if ( IsThreadLocal ) return <NUM_LIT> ; emitInst ( <STR_LIT> , DestReg ) . addReg ( MFI -> getGlobalBaseReg ( * MF , IsThreadLocal ) ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ) {

unsigned TempReg = createResultReg ( RC ) ;


<s> MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : return EmitF128CSEL ( MI , BB ) ; case TargetOpcode :: STACKMAP : case TargetOpcode :: PATCHPOINT : return emitPatchPoint ( MI , BB ) ; } llvm_unreachable ( <STR_LIT> ) ;


<s> switch ( operand . type ) { default : debug ( <STR_LIT> ) ; return true ; case TYPE_R8 : case TYPE_R16 : case TYPE_R32 : case TYPE_R64 : case TYPE_Rv : case TYPE_MM64 : case TYPE_XMM : case TYPE_XMM32 : case TYPE_XMM64 : case TYPE_XMM128 : case TYPE_XMM256 : case TYPE_XMM512 : case TYPE_VK1 : case TYPE_VK8 : case TYPE_VK16 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : case TYPE_BNDR : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M256 : case TYPE_M512 : case TYPE_Mv : case TYPE_M32FP : case TYPE_M64FP : case TYPE_M80FP : case TYPE_M1616 : case TYPE_M1632 : case TYPE_M1664 : case TYPE_LEA :

return translateRMMemory ( mcInst , insn , Dis ) ;


<s> if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return true ; } return false ;


<s> if ( Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isDoubleTy ( ) ) { return LT . first * <NUM_LIT> ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: ParseMemoryOperandV10 ( OperandVector & Operands ) {

return ParseMemoryOperand ( Operands , <NUM_LIT> , true ) ;


<s> if ( Asm . isThumbFunc ( & Sym ) ) Value |= <NUM_LIT> ; } } if ( A && ( ( unsigned ) Fixup . getKind ( ) == <STR_LIT> || ( unsigned ) Fixup . getKind ( ) == <STR_LIT> || ( unsigned ) Fixup . getKind ( ) == <STR_LIT> || ( unsigned ) Fixup . getKind ( ) == <STR_LIT> || ( unsigned ) Fixup . getKind ( ) == <STR_LIT> ) ) IsResolved = false ; ( void ) adjustFixupValue ( Fixup , Value , & Asm . getContext ( ) ) ;


<s> if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; } OutStreamer . AddBlankLine ( ) ; return ; } const MCSection * StubSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { MCSymbol * Stub = Stubs [ i ] . first ; MCSymbol * RawSym = Stubs [ i ] . second . getPointer ( ) ; MCSymbol * LazyPtr = GetLazyPtr ( Stub , OutContext ) ; OutStreamer . SwitchSection ( StubSection ) ; EmitAlignment ( <NUM_LIT> ) ; OutStreamer . EmitLabel ( Stub ) ; OutStreamer . EmitSymbolAttribute ( RawSym , MCSA_IndirectSymbol ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> ) ; if ( is<ISA_LIT>64 ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> ) ; else OutStreamer . EmitRawText ( <STR_LIT> + Twine ( LazyPtr -> getName ( ) ) + <STR_LIT> ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ;


<s> InstrReplacer ( unsigned SrcOpcode , unsigned DstOpcode ) : InstrConverterBase ( SrcOpcode ) , DstOpcode ( DstOpcode ) {


<s> bool pa_cannot_change_mode_class ( machine_mode from , machine_mode to , enum reg_class rclass ) { if ( from == to ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return true ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return true ;


<s> static struct machine_function * avr_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ;


<s> } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } } if ( <ISA_LIT>FI -> needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . hasAltivec ( ) ) for ( TargetRegisterClass :: iterator I = <STR_LIT> . begin ( ) , IE = <STR_LIT> . end ( ) ; I != IE ; ++ I ) Reserved . set ( * I ) ; return Reserved ;


<s> static tree ix86_md_asm_clobbers ( tree outputs ATTRIBUTE_UNUSED , tree inputs ATTRIBUTE_UNUSED , tree clobbers ) {

clobbers = tree_cons ( NULL_TREE , build_string ( <NUM_LIT> , <STR_LIT> ) , clobbers ) ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) {


<s> ArrayRef < MCPhysReg > RegList = CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ; bool Is64bit = static_cast < const <ISA_LIT>Subtarget & > ( State . getMachineFunction ( ) . getSubtarget ( ) ) . is64Bit ( ) ; for ( auto Reg : RegList ) {


<s> cvtMubufImpl ( Inst , Operands , false ) ;


<s> SmallVectorImpl < MachineInstr * > & Insts = Block . getInsts ( ) ; for ( unsigned i = <NUM_LIT> ; i < Insts . size ( ) ; ++ i ) { MachineInstr * Next = Insts [ i ] ;

if ( isVectorPredicate ( Next ) ) return Next ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? ( Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) : ( Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {


<s> bool isUImm8Shift8 ( ) { return isUImm < <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> case IOK_TYPE : CVal = Info . Type ; break ; } unsigned Len = End . getPointer ( ) - TypeLoc . getPointer ( ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , TypeLoc , Len , CVal ) ) ; const MCExpr * Imm = MCConstantExpr :: create ( CVal , getContext ( ) ) ;

return <STR_LIT> ( Imm , Start , End ) ;


<s> else size = GET_MODE_SIZE ( mode ) ;

return ( size + <NUM_LIT> ) & ~ <NUM_LIT> ;


<s> bool SeenDbgInstr = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( MBB ) ) { int FrameIndex ; if ( MI . isDebugInstr ( ) ) SeenDbgInstr = true ; if ( TII -> isVGPRSpill ( MI ) ) { unsigned FIOp = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vaddr ) ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; Register VReg = TII -> getNamedOperand ( MI , <STR_LIT> :: vdata ) -> getReg ( ) ; if ( FuncInfo -> allocateVGPRSpillToAGPR ( MF , FI , TRI -> isAGPR ( MRI , VReg ) ) ) { RS -> enterBasicBlock ( MBB ) ; TRI -> eliminateFrameIndex ( MI , <NUM_LIT> , FIOp , RS ) ; SpillFIs . set ( FI ) ; continue ; } } else if ( TII -> isStoreToStackSlot ( MI , FrameIndex ) || TII -> isLoadFromStackSlot ( MI , FrameIndex ) ) if ( ! MFI . isFixedObjectIndex ( FrameIndex ) ) NonVGPRSpillFIs . set ( FrameIndex ) ; }


<s> Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } IntVal = IntVal32 . getSExtValue ( ) ; if ( Negate ) IntVal *= - <NUM_LIT> ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IntVal , S ) ) ; return MatchOperand_Success ; } case AsmToken :: Real : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal ; if ( getParser ( ) . parseAbsoluteExpression ( IntVal ) ) return MatchOperand_ParseFail ; APFloat F ( ( float ) BitsToDouble ( IntVal ) ) ; if ( Negate ) F . changeSign ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( F . bitcastToAPInt ( ) . getZExtValue ( ) , S ) ) ; return MatchOperand_Success ; } case AsmToken :: Identifier : { SMLoc S , E ; unsigned RegNo ; if ( ! ParseRegister ( RegNo , S , E ) ) { bool HasModifiers = operandsHaveModifiers ( Operands ) ; unsigned Modifiers = <NUM_LIT> ; if ( Negate ) Modifiers |= <NUM_LIT> ; if ( Abs ) { if ( getLexer ( ) . getKind ( ) != AsmToken :: Pipe ) return MatchOperand_ParseFail ;


<s> case <STR_LIT> : case <STR_LIT> : return legalizeInternalLoadStoreOp ( Op , CDAG ) ; } EVT IdiomVT = Op . getValueType ( ) ; if ( isPackedVectorType ( IdiomVT ) && ! supportsPackedMode ( Op . getOpcode ( ) , IdiomVT ) ) return splitVectorOp ( Op , CDAG ) ;

return legalizePackedAVL ( Op , CDAG ) ;


<s> case RS6000_BUILTIN_NANQ : case RS6000_BUILTIN_NANSQ : { tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; const char * str = c_getstr ( * args ) ; int quiet = fn_code == RS6000_BUILTIN_NANQ ; REAL_VALUE_TYPE real ; if ( str && real_nan ( & real , str , quiet , TYPE_MODE ( type ) ) ) return build_real ( type , real ) ; return NULL_TREE ; } case RS6000_BUILTIN_INFQ : case RS6000_BUILTIN_HUGE_VALQ : { tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; REAL_VALUE_TYPE inf ; real_inf ( & inf ) ; return build_real ( type , inf ) ; } default :


<s> if ( IsSlow3OpsLEA ) { if ( auto * NewMI = processInstrForSlow3OpLEA ( * I , MFI ) ) { MFI -> erase ( I ) ; I = NewMI ; } continue ; }


<s> const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = <NUM_LIT> ; int64_t IntVal ; if ( MatchRegisterName ( RegNo , IntVal ) ) return MatchOperand_NoMatch ; return MatchOperand_Success ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectIndexedLoad ( SDNode * N ) { const LoadSDNode * LD = cast < LoadSDNode > ( N ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; MVT VT = LD -> getMemoryVT ( ) . getSimpleVT ( ) ; auto PtrVT = getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ; if ( ( LD -> getExtensionType ( ) != <STR_LIT> ) || ( AM != <STR_LIT> && AM != <STR_LIT> ) ) { return false ; } unsigned Opcode = <NUM_LIT> ; bool isPre = ( AM == <STR_LIT> ) ; int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( ( ! isPre && Offs != <NUM_LIT> ) || ( isPre && Offs != - <NUM_LIT> ) ) { return false ; } Opcode = ( isPre ) ? <STR_LIT> : <STR_LIT> ; break ; } case <STR_LIT> : { if ( ( ! isPre && Offs != <NUM_LIT> ) || ( isPre && Offs != - <NUM_LIT> ) ) { return false ; } Opcode = ( isPre ) ? <STR_LIT> : <STR_LIT> ; break ; } default : return false ;


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = vec_splat ( __A , <NUM_LIT> ) ; c = vec_rsqrte ( a ) ; return ( vec_sel ( __A , c , mask ) ) ;


<s> if ( ! isa < ConstantSDNode > ( N ) ) return false ; int64_t MulImm = cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ; if ( MulImm >= <NUM_LIT> && MulImm <= Max ) { MulImm *= Scale ;

Imm = CurDAG -> getTargetConstant ( MulImm , SDLoc ( N ) , <STR_LIT> ) ;


<s> case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : case TargetOpcode :: G_FABS : case TargetOpcode :: G_FSQRT :


<s> void <ISA_LIT>InstPrinter :: printClamp ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { printIfSet ( MI , OpNo , O , <STR_LIT> ) ;


<s> if ( VCCUsed ) ExtraSGPRs = <NUM_LIT> ; if ( ST . getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( FlatScrUsed ) ExtraSGPRs = <NUM_LIT> ;


<s> bool <ISA_LIT>SEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const {

const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


<s> else if ( <STR_LIT> . contains ( DstReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DstReg ) ) Opc = <STR_LIT> ; if ( Opc ) { BuildMI ( MBB , MI , DL , get ( Opc ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } bool FromCCR = SrcReg == <STR_LIT> ; bool FromSR = SrcReg == <STR_LIT> ; bool ToCCR = DstReg == <STR_LIT> ; bool ToSR = DstReg == <STR_LIT> ; if ( FromCCR ) { assert ( <STR_LIT> . contains ( DstReg ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } else if ( ToCCR ) { assert ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> ) ; Opc = <STR_LIT> ; } else if ( FromSR || ToSR ) llvm_unreachable ( <STR_LIT> ) ; if ( Opc ) { BuildMI ( MBB , MI , DL , get ( Opc ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ;


<s> MCELFStreamer * llvm :: create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) {

return new <ISA_LIT>ELFStreamer ( Context , MAB , OS , Emitter ) ;


<s> assert ( ( ( ! Subtarget . hasAVX512 ( ) && VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , dl , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( Op0 . getValueType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) {


<s> case <STR_LIT> : return performADDECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSUBECombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRACombine ( N , DAG , DCI , Subtarget ) ;


<s> gcc_assert ( VECTOR_MODE_P ( p . mode ) && VECTOR_MODE_P ( prev . mode ) ) ; unsigned int nelems1 , nelems2 ;

if ( prev . orig_mode == p . orig_mode && known_eq ( prev . offset + GET_MODE_SIZE ( prev . mode ) , p . offset ) && constant_multiple_p ( GET_MODE_NUNITS ( prev . mode ) , GET_MODE_NUNITS ( p . orig_mode ) , & nelems1 ) && constant_multiple_p ( GET_MODE_NUNITS ( p . mode ) , GET_MODE_NUNITS ( p . orig_mode ) , & nelems2 ) && targetm . array_mode ( p . orig_mode , nelems1 + nelems2 ) . exists ( & prev . mode ) ) {


<s> const char * IntrMemName = isa < MemCpyInst > ( I ) ? <STR_LIT> : <STR_LIT> ; return SelectCall ( & I , IntrMemName ) ; } case <STR_LIT> : { const MemSetInst & MSI = cast < MemSetInst > ( I ) ; if ( MSI . isVolatile ( ) ) return false ; if ( ! MSI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MSI . getDestAddressSpace ( ) > <NUM_LIT> ) return false ; return SelectCall ( & I , <STR_LIT> ) ; } case <STR_LIT> : { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> unsigned postKnownBits ( unsigned LogAlign = <NUM_LIT> ) const {

return std :: max ( std :: max ( unsigned ( PostAlign ) , LogAlign ) , internalKnownBits ( ) ) ;


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . getCCAssignFn ( F . getCallingConv ( ) , true , F . isVarArg ( ) ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; if ( ! VRegs . empty ( ) ) { SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; ArgInfo OrigArg { VRegs , Val -> getType ( ) , <NUM_LIT> } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; <ISA_LIT>OutgoingArgHandler ArgHandler ( MIRBuilder , MRI , MIB ) ; Success = determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; }


<s> static bool IsFrameChange ( MachineInstr & MI ) {

return MI . modifiesRegister ( <STR_LIT> , NULL ) || MI . modifiesRegister ( <STR_LIT> , NULL ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {

PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> void <ISA_LIT>TargetELFStreamer :: EmitDirectiveHSACodeObjectVersion ( uint32_t Major , uint32_t Minor ) {


<s> bool <ISA_LIT>LowerEmscriptenEHSjLj :: runSjLjOnFunction ( Function & F ) { assert ( EnableEmSjLj || EnableWasmSjLj ) ; Module & M = * F . getParent ( ) ; LLVMContext & C = F . getContext ( ) ; IRBuilder < > IRB ( C ) ; SmallVector < Instruction * , <NUM_LIT> > ToErase ; SmallVector < Instruction * , <NUM_LIT> > SetjmpTableInsts ; SmallVector < Instruction * , <NUM_LIT> > SetjmpTableSizeInsts ; BasicBlock * Entry = & F . getEntryBlock ( ) ; DebugLoc FirstDL = getOrCreateDebugLoc ( & * Entry -> begin ( ) , F . getSubprogram ( ) ) ; SplitBlock ( Entry , & * Entry -> getFirstInsertionPt ( ) ) ; BinaryOperator * SetjmpTableSize = BinaryOperator :: Create ( Instruction :: Add , IRB . getInt32 ( <NUM_LIT> ) , IRB . getInt32 ( <NUM_LIT> ) , <STR_LIT> , Entry -> getTerminator ( ) ) ; SetjmpTableSize -> setDebugLoc ( FirstDL ) ; Instruction * SetjmpTable = CallInst :: CreateMalloc ( SetjmpTableSize , IRB . getInt32Ty ( ) , IRB . getInt32Ty ( ) , IRB . getInt32 ( <NUM_LIT> ) , nullptr , nullptr , <STR_LIT> ) ; SetjmpTable -> setDebugLoc ( FirstDL ) ; auto * MallocCall = SetjmpTable -> stripPointerCasts ( ) ; if ( auto * MallocCallI = dyn_cast < Instruction > ( MallocCall ) ) { MallocCallI -> setDebugLoc ( FirstDL ) ; } IRB . SetInsertPoint ( SetjmpTableSize ) ; IRB . CreateStore ( IRB . getInt32 ( <NUM_LIT> ) , SetjmpTable ) ; SetjmpTableInsts . push_back ( SetjmpTable ) ; SetjmpTableSizeInsts . push_back ( SetjmpTableSize ) ; SmallVector < PHINode * , <NUM_LIT> > SetjmpRetPHIs ; Function * SetjmpF = M . getFunction ( <STR_LIT> ) ; for ( User * U : SetjmpF -> users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( ! CI ) report_fatal_error ( <STR_LIT> ) ; BasicBlock * BB = CI -> getParent ( ) ; if ( BB -> getParent ( ) != & F ) continue ; BasicBlock * Tail = SplitBlock ( BB , CI -> getNextNode ( ) ) ; IRB . SetInsertPoint ( Tail -> getFirstNonPHI ( ) ) ;

PHINode * SetjmpRet = IRB . CreatePHI ( IRB . getInt32Ty ( ) , <NUM_LIT> , <STR_LIT> ) ;


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( ! IsPositionIndependent ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , Result , PICLabel ) ;


<s> unsigned CountS = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned InVal = <NUM_LIT> + CountS ; ShuffleMask [ CountD ] = InVal ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ; if ( ZMask & <NUM_LIT> ) ShuffleMask [ <NUM_LIT> ] = SM_SentinelZero ;


<s> if ( G -> requiresFixup ( ) && C != G -> getPreferredColor ( ) ) { C = G -> getPreferredColor ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << G -> str ( ) << <STR_LIT> <STR_LIT> << ColorNames [ ( int ) C ] << <STR_LIT> ) ; } Changed |= colorChain ( G , C , MBB ) ; Parity += ( C == Color :: Even ) ? G -> size ( ) : - G -> size ( ) ; PreferredColor = Parity < <NUM_LIT> ? Color :: Even : Color :: Odd ; }


<s> bool cris_return_address_on_stack ( void ) {

return df_regs_ever_live_p ( CRIS_SRP_REGNUM ) || cfun -> machine -> needs_return_address_on_stack ;


<s> else MAI = new <ISA_LIT>ELFMCAsmInfo ( is<ISA_LIT>64 , TheTriple ) ; unsigned Reg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( Reg , true ) , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> if ( ( Ty != <STR_LIT> ) && ( Ty != <STR_LIT> ) ) return SDValue ( ) ;

return performDSPShiftCombine ( <STR_LIT> , N , Ty , DAG , Subtarget ) ;


<s> static void collectFunctionUsers ( User * U , DenseSet < Function * > & Funcs ) { if ( auto * I = dyn_cast < Instruction > ( U ) ) { auto * F = I -> getParent ( ) -> getParent ( ) ; if ( Funcs . insert ( F ) . second ) collectCallers ( F , Funcs ) ; return ; }

if ( ! isa < Constant > ( U ) ) return ;


<s> unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ;

BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in ) . addImm ( Lane ) . addReg ( Wt ) ;


<s> case <STR_LIT> : return <ISA_LIT>II :: LoopLT ; case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>II :: LoopLE ; case <STR_LIT> : case <STR_LIT> : return <ISA_LIT>II :: LoopGT ; case <STR_LIT> :


<s> if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count ;


<s> if ( DCI . isBeforeLegalizeOps ( ) && Value . getOpcode ( ) == <STR_LIT> && Value . getNode ( ) -> hasOneUse ( ) && ST -> isUnindexed ( ) && Subtarget -> useSVEForFixedLengthVectors ( ) && Value . getValueType ( ) . isFixedLengthVector ( ) && Value . getValueType ( ) . getFixedSizeInBits ( ) >= Subtarget -> getMinSVEVectorSizeInBits ( ) ) return DAG . getTruncStore ( Chain , SDLoc ( N ) , Value . getOperand ( <NUM_LIT> ) , Ptr , ST -> getMemoryVT ( ) , ST -> getMemOperand ( ) ) ; if ( SDValue Split = splitStores ( N , DCI , DAG , Subtarget ) ) return Split ;

if ( Subtarget -> supportsAddressTopByteIgnored ( ) && performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) { CondCycles = <NUM_LIT> ; TrueCycles = <NUM_LIT> ; FalseCycles = <NUM_LIT> ; return true ; }


<s> return __builtin_mve_vcmpeqq_uv8hi ( __a , __b ) ;


<s> static inline bool has_func_attr ( const_tree decl , const char * func_attr ) { if ( decl == NULL_TREE ) decl = current_function_decl ;

return lookup_attribute ( func_attr , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ;


<s> return ( uint16x4_t ) __builtin_neon_vshrn_nv4si ( ( int32x4_t ) __a , __b ) ;


<s> if ( ! get<ISA_LIT>Subtarget ( ) . is64Bit ( ) ) PM -> add ( createGlobalBaseRegPass ( ) ) ; return false ;


<s> static rtx gen_no_side_effects_vsetvl_rtx ( machine_mode vmode , rtx vl , rtx avl ) { unsigned int sew = get_sew ( vmode ) ;

return gen_vsetvl_no_side_effects ( Pmode , vl , avl , gen_int_mode ( sew , Pmode ) , gen_int_mode ( get_vlmul ( vmode ) , Pmode ) , const0_rtx , const0_rtx ) ;


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) {


<s> } } unsigned Opc = LHS . getOpcode ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ; } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ;


<s> for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , AP ) ) OutMI . addOperand ( MCOp ) ; }


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedFrameMoves ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool IsPrologue ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) {

int64_t Offset = MFI . getObjectOffset ( I . getFrameIdx ( ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectTLSADDRAddr ( SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment ) { assert ( N . getOpcode ( ) == <STR_LIT> ) ; const GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( N ) ; <ISA_LIT>ISelAddressMode AM ; AM . GV = GA -> getGlobal ( ) ; AM . Disp += GA -> getOffset ( ) ; AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , N . getValueType ( ) ) ; AM . SymbolFlags = GA -> getTargetFlags ( ) ; if ( N . getValueType ( ) == <STR_LIT> && ! Subtarget -> isTargetNaCl64 ( ) ) {


<s> void <ISA_LIT>AsmPrinter :: EmitSectionList ( Module & M , const std :: vector < <ISA_LIT>Section * > & SList ) { for ( unsigned i = <NUM_LIT> ; i < SList . size ( ) ; i ++ ) { if ( SList [ i ] -> getName ( ) . find ( <STR_LIT> ) != std :: string :: npos ) continue ; O << <STR_LIT> ; EmitSingleSection ( SList [ i ] ) ;


<s> AU . addRequired < MachineDominanceFrontier > ( ) ;


<s> if ( Cond . empty ( ) ) { BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; } else { unsigned Opc = GetCondBranchFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ) ; const TargetInstrDesc & TID = get ( Opc ) ; if ( TID . getNumOperands ( ) == <NUM_LIT> ) BuildMI ( & MBB , dl , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ;

else BuildMI ( & MBB , dl , TID ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ;


<s> static __inline qword si_or ( qword a , qword b ) {

return ( ( qword ) ( vec_or ( ( vec_uchar16 ) ( a ) , ( vec_uchar16 ) ( b ) ) ) ) ;


<s> if ( mode == VOIDmode ) mode = TImode ; gcc_assert ( ! FP_REG_RTX_P ( op ) ) ;

if ( MEM_P ( op ) ) return mips_rewrite_small_data ( adjust_address ( op , word_mode , byte ) ) ;


<s> unsigned getStoredByValParamsPadding ( ) const {


<s> decl = exp ; } else { type = exp ; decl = NULL ; } if ( ! TARGET_64BIT && align == <NUM_LIT> && ix86_preferred_stack_boundary < <NUM_LIT> && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = <NUM_LIT> ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_IAMCU ) return align ; if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ;

if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ;


<s> return DAG . getVectorShuffle ( OpVT , dl , Vec , SubVec . getOperand ( <NUM_LIT> ) , Mask ) ; } } if ( ( Vec . isUndef ( ) || Vec . getOpcode ( ) == <STR_LIT> ) && SubVec . getOpcode ( ) == <STR_LIT> ) { SDValue VecSrc = peekThroughBitcasts ( Vec ) ; SDValue SubVecSrc = peekThroughBitcasts ( SubVec ) ; MVT VecSrcSVT = VecSrc . getSimpleValueType ( ) . getScalarType ( ) ; MVT SubVecSrcSVT = SubVecSrc . getSimpleValueType ( ) . getScalarType ( ) ; if ( Vec . isUndef ( ) || VecSrcSVT == SubVecSrcSVT ) { MVT NewOpVT ; SDValue NewIdx ; unsigned NumElts = OpVT . getVectorNumElements ( ) ; unsigned EltSizeInBits = OpVT . getScalarSizeInBits ( ) ; if ( ( EltSizeInBits % SubVecSrcSVT . getSizeInBits ( ) ) == <NUM_LIT> ) { unsigned Scale = EltSizeInBits / SubVecSrcSVT . getSizeInBits ( ) ; NewOpVT = <STR_LIT> ( SubVecSrcSVT , NumElts * Scale ) ; NewIdx = DAG . getIntPtrConstant ( IdxVal * Scale , dl ) ; } else if ( ( SubVecSrcSVT . getSizeInBits ( ) % EltSizeInBits ) == <NUM_LIT> ) { unsigned Scale = SubVecSrcSVT . getSizeInBits ( ) / EltSizeInBits ; if ( ( IdxVal % Scale ) == <NUM_LIT> ) { NewOpVT = <STR_LIT> ( SubVecSrcSVT , NumElts / Scale ) ; NewIdx = DAG . getIntPtrConstant ( IdxVal / Scale , dl ) ; } } if ( NewIdx && DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , NewOpVT ) ) { SDValue Res = DAG . getBitcast ( NewOpVT , VecSrc ) ; Res = DAG . getNode ( <STR_LIT> , dl , NewOpVT , Res , SubVecSrc , NewIdx ) ; return DAG . getBitcast ( OpVT , Res ) ; } } } if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . getSizeInBits ( ) == SubVecVT . getSizeInBits ( ) * <NUM_LIT> ) { if ( isNullConstant ( Vec . getOperand ( <NUM_LIT> ) ) ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Fold = combineConcatVectorOps ( dl , OpVT , Ops , DAG , DCI , Subtarget ) ) return Fold ; if ( ! Vec . getOperand ( <NUM_LIT> ) . isUndef ( ) && Vec . hasOneUse ( ) ) {

Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getUNDEF ( OpVT ) , SubVec2 , Vec . getOperand ( <NUM_LIT> ) ) ;


<s> if ( D -> front ( ) == I1 && D -> back ( ) == I2 && D -> iterations ( ) == Iters ) return D ;


<s> if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs ( ) ) ; }


<s> static bool csky_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { return ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) || ! reg_classes_intersect_p ( V_REGS , rclass ) ) ;


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ;

bool IsILP32 = Options . getABIName ( ) == <STR_LIT> ;


<s> if ( Offset >= NumElts || Offset < <NUM_LIT> ) return std :: make_pair ( <STR_LIT> , Offset ) ;

return std :: make_pair ( <STR_LIT> + Offset , <NUM_LIT> ) ;


<s> bool HasPackedStackAttr = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ;

bool CallConv = MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: GHC ;


<s> if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , MII ) ;


<s> MBB . splice ( Insert , & MBB , Def ) ; LIS . handleMove ( Def ) ; const auto * RegClass = MRI . getRegClass ( Reg ) ; unsigned NewReg = MRI . createVirtualRegister ( RegClass ) ; unsigned TeeReg = MRI . createVirtualRegister ( RegClass ) ; MRI . replaceRegWith ( Reg , NewReg ) ; MachineInstr * Tee = BuildMI ( MBB , Insert , Insert -> getDebugLoc ( ) , TII -> get ( GetTeeLocalOpcode ( RegClass ) ) , TeeReg ) . addReg ( NewReg , RegState :: Define ) . addReg ( Reg ) ; Op . setReg ( TeeReg ) ; Def -> getOperand ( <NUM_LIT> ) . setReg ( Reg ) ; LIS . InsertMachineInstrInMaps ( Tee ) ; LIS . shrinkToUses ( & LIS . getInterval ( Reg ) ) ; LIS . createAndComputeVirtRegInterval ( NewReg ) ; LIS . createAndComputeVirtRegInterval ( TeeReg ) ; MFI . stackifyVReg ( Reg ) ; MFI . stackifyVReg ( TeeReg ) ; ImposeStackOrdering ( Def ) ;


<s> const char * RegName = getRegisterName ( Op . getReg ( ) ) ; if ( ! isDarwinSyntax ( ) ) RegName = stripRegisterPrefix ( RegName ) ; O << RegName ; return ;


<s> int legitimate_pic_operand_p ( rtx op ) { if ( ! SYMBOLIC_CONST ( op ) ) return <NUM_LIT> ; if ( larl_operand ( op , VOIDmode ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << '\n' ) ;


<s> if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = EltSize * Offset0 ; return true ; } return false ; } if ( isMUBUF ( * LdSt ) || isMTBUF ( * LdSt ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: soffset ) != - <NUM_LIT> ) return false ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , <STR_LIT> :: offset ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } if ( isSMRD ( * LdSt ) ) { const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , <STR_LIT> :: offset ) ; if ( ! OffsetImm ) return false ; const MachineOperand * SBaseReg = getNamedOperand ( * LdSt , <STR_LIT> :: sbase ) ; BaseReg = SBaseReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } if ( isFLAT ( * LdSt ) ) { const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: addr ) ;


<s> if ( AsmTokStr == <STR_LIT> || AsmTokStr == <STR_LIT> ) return ParseIntelOperator ( IOK_TYPE ) ; } unsigned Size = getIntelMemOperandSize ( Tok . getString ( ) ) ; if ( Size ) { Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; } Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Minus ) || getLexer ( ) . is ( AsmToken :: LParen ) ) { AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ;

if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ;


<s> <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int RASI = FI -> getReturnAddrSaveIndex ( ) ; if ( ! RASI ) { int LROffset = Subtarget . getFrameLowering ( ) -> getReturnSaveOffset ( ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , LROffset , false ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; SU -> dump ( DAG ) ; ) ; if ( isPhysicalRegCopy ( SU -> getInstr ( ) ) ) { PhysicalRegCopy . push_back ( SU ) ; return ; } int IK = getInstKind ( SU ) ;

if ( IK == IDOther ) Available [ IDOther ] . push_back ( SU ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; MVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ;


<s> if ( RegName [ <NUM_LIT> ] == 'q' ) { std :: string RN ( RegName ) ; RN [ <NUM_LIT> ] = 'f' ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < EVT > & OutTys , const SmallVectorImpl < <STR_LIT> > & ArgsFlags , SelectionDAG & DAG ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; return CCInfo . CheckReturn ( OutTys , ArgsFlags , RetCC_<ISA_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitFNMADD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> SDValue NewAddr = DAG . getNode ( <STR_LIT> , dl , Addr . getSimpleValueType ( ) , Addr , DAG . getConstant ( Index * EVT . getStoreSize ( ) , dl , Addr . getSimpleValueType ( ) ) ) ; SDValue NewLoad = DAG . getLoad ( EVT , dl , Load -> getChain ( ) , NewAddr , DAG . getMachineFunction ( ) . getMachineMemOperand ( Load -> getMemOperand ( ) , <NUM_LIT> , EVT . getStoreSize ( ) ) ) ;


<s> if ( ST . enable<ISA_LIT>Scheduler ( ) ) return create<ISA_LIT>MachineScheduler ( C ) ;

return createGCNMaxOccupancyMachineScheduler ( C ) ;


Register Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { case VCCNZ : case VCCZ : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; assert ( MRI . getRegClass ( FalseReg ) == RC ) ; int NumInsts = <STR_LIT> ( RC -> getID ( ) ) / <NUM_LIT> ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return RI . hasVGPRs ( RC ) && NumInsts <= <NUM_LIT> ; } case SCC_TRUE : case SCC_FALSE : { const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( TrueReg ) ; assert ( MRI . getRegClass ( FalseReg ) == RC ) ; int NumInsts = <STR_LIT> ( RC -> getID ( ) ) / <NUM_LIT> ; if ( NumInsts % <NUM_LIT> == <NUM_LIT> ) NumInsts /= <NUM_LIT> ; CondCycles = TrueCycles = FalseCycles = NumInsts ; return RI . isSGPRClass ( RC ) ;


<s> bool <ISA_LIT>FrameLowering :: expandStoreVecPred ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const { MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; auto * RC = & <STR_LIT> ; unsigned TmpR0 = MRI . createVirtualRegister ( & <STR_LIT> ) ;

unsigned TmpR1 = MRI . createVirtualRegister ( RC ) ;


<s> static __inline vec_int4 spu_or ( vec_int4 a , signed int b ) { return ( ( vec_int4 ) ( si_ori ( ( qword ) ( a ) , ( unsigned int ) ( b ) ) ) ) ;


<s> <STR_LIT> Condition = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue VL = Op . getOperand ( <NUM_LIT> ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; Op1 = convertToScalableVector ( ContainerVT , Op1 , DAG , Subtarget ) ; Op2 = convertToScalableVector ( ContainerVT , Op2 , DAG , Subtarget ) ; } SDValue Result ; SDValue AllOneMask = DAG . getNode ( <STR_LIT> , DL , ContainerVT , VL ) ; switch ( Condition ) { default : break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op1 , Op2 , VL ) ; break ; case <STR_LIT> : { SDValue Temp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op1 , Op2 , VL ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Temp , AllOneMask , VL ) ; break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Temp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op1 , AllOneMask , VL ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Temp , Op2 , VL ) ; break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Temp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op2 , AllOneMask , VL ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op1 , Temp , VL ) ; break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Temp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op1 , AllOneMask , VL ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Temp , Op2 , VL ) ; break ; } case <STR_LIT> : case <STR_LIT> : { SDValue Temp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Op2 , AllOneMask , VL ) ; Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Temp , Op1 , VL ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < ScalarEvolutionWrapperPass > ( ) ;


<s> unsigned ScratchRegI32 = RegCtx . scratchReg ( <STR_LIT> ) ; ComputeMemOperandAddress ( Op , <STR_LIT> , AddressRegI64 , Ctx , Out ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( AddressRegI64 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI64 ) . addReg ( ShadowRegI64 ) . addImm ( <NUM_LIT> ) ) ; { MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( ShadowRegI8 ) ) ; const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; EmitInstruction ( Out , Inst ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI8 ) . addReg ( ShadowRegI8 ) ) ; MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( AddressRegI32 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( ScratchRegI32 ) . addImm ( <NUM_LIT> ) ) ; switch ( AccessSize ) { case <NUM_LIT> : break ; case <NUM_LIT> : { const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ScratchRegI32 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; EmitLEA ( * Op , <STR_LIT> , ScratchRegI32 , Out ) ; break ; } case <NUM_LIT> : EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( ScratchRegI32 ) . addImm ( <NUM_LIT> ) ) ; break ; default : assert ( false && <STR_LIT> ) ; break ;


<s> static unsigned getLinkageSize ( bool LP64 , bool isMacho ) { if ( isMacho ) return <NUM_LIT> * ( LP64 ? <NUM_LIT> : <NUM_LIT> ) ;


<s> ssize_t bytes = snprintf ( s , sizeof ( s ) , <STR_LIT> , n ) ; gcc_assert ( ( size_t ) bytes < sizeof ( s ) ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> static DecodeStatus DecodeI64RegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = IntRegDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser ( _Parser ) , MII ( MII ) , UC ( _Parser ) { MCAsmParserExtension :: Initialize ( _Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> if ( SDValue Select = pushAddIntoCmovOfConsts ( N , DAG ) ) return Select ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_3 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue V = combineToHorizontalAddSub ( N , DAG , Subtarget ) ) return V ; if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 , SExt ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ;

SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op1 . getOperand ( <NUM_LIT> ) ) ;


<s> OpDetailMap [ <STR_LIT> ] = std :: make_tuple ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ;


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ;

Cond . front ( ) = MachineOperand :: CreateImm ( ! Cond . front ( ) . getImm ( ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; return MI . getOperand ( <NUM_LIT> ) . isReg ( ) || RI . isAGPR ( MRI , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : return ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasDLInsts ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) offset = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) , base = XEXP ( addr , <NUM_LIT> ) ; else if ( CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) ) offset = INTVAL ( XEXP ( addr , <NUM_LIT> ) ) , base = XEXP ( addr , <NUM_LIT> ) ; else base = XEXP ( addr , <NUM_LIT> ) , index = XEXP ( addr , <NUM_LIT> ) ; if ( REG_P ( base ) ) { if ( index == <NUM_LIT> ) { if ( offset != <NUM_LIT> ) fprintf ( file , <STR_LIT> , offset ) ; fputs ( reg_names [ REGNO ( base ) ] , file ) ; } else if ( REG_P ( index ) ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( base ) ] , reg_names [ REGNO ( index ) ] ) ; else if ( GET_CODE ( index ) == SYMBOL_REF ) { output_addr_const ( file , index ) ; fputc ( ',' , file ) ; fputs ( reg_names [ REGNO ( base ) ] , file ) ; } else fatal_insn ( <STR_LIT> , addr ) ;


<s> if ( ! Subtarget . hasInt256 ( ) || VT . getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return false ; if ( VT . is512BitVector ( ) || Subtarget . hasVLX ( ) ) return true ;

bool LShift = VT . is128BitVector ( ) || VT . is256BitVector ( ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case POST_MODIFY : if ( REG_P ( XEXP ( op , <NUM_LIT> ) ) && ( ! reload_completed || ( REGNO ( XEXP ( op , <NUM_LIT> ) ) == regno ) ) ) return <NUM_LIT> ; if ( REG_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) && ( ! reload_completed || ( REGNO ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == regno ) ) ) return <NUM_LIT> ; break ; case PLUS : { rtx op0 = XEXP ( op , <NUM_LIT> ) ; rtx op1 = XEXP ( op , <NUM_LIT> ) ; if ( ( REG_P ( op0 ) && ( ! reload_completed || ( REGNO ( op0 ) == regno ) ) ) || ( REG_P ( op1 ) && ( ! reload_completed || ( REGNO ( op1 ) == regno ) ) ) ) return <NUM_LIT> ; } break ; default : break ; }


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {


<s> for ( p = & pool -> first ; * p != <NUM_LIT> ; p = & ( * p ) -> next ) { if ( mode == ( * p ) -> mode && rtx_equal_p ( value , ( * p ) -> value ) ) return ( * p ) -> label ; if ( GET_MODE_SIZE ( mode ) < GET_MODE_SIZE ( ( * p ) -> mode ) ) break ; if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( ( * p ) -> mode ) ) first_of_size_p = false ; } if ( pool -> first == <NUM_LIT> ) pool -> highest_address = pool -> insn_address - ( UNITS_PER_WORD - <NUM_LIT> ) + <NUM_LIT> ; pool -> highest_address -= GET_MODE_SIZE ( mode ) ; if ( first_of_size_p ) pool -> highest_address -= GET_MODE_SIZE ( mode ) - <NUM_LIT> ; c = ( struct mips16_constant * ) xmalloc ( sizeof * c ) ; c -> value = value ; c -> mode = mode ; c -> label = gen_label_rtx ( ) ; c -> next = * p ; * p = c ; return c -> label ;


<s> EVT MemVT = SN -> getMemoryVT ( ) ; if ( MemVT . isInteger ( ) && SN -> isTruncatingStore ( ) ) { if ( SDValue Value = combineTruncateExtract ( SDLoc ( N ) , MemVT , SN -> getValue ( ) , DCI ) ) { DCI . AddToWorklist ( Value . getNode ( ) ) ; return DAG . getTruncStore ( SN -> getChain ( ) , SDLoc ( SN ) , Value , SN -> getBasePtr ( ) , SN -> getMemoryVT ( ) , SN -> getMemOperand ( ) ) ; } } if ( ! SN -> isTruncatingStore ( ) && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getNode ( ) -> hasOneUse ( ) && ( Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> || Op1 . getValueType ( ) == <STR_LIT> ) ) {

SDValue BSwapOp = Op1 . getOperand ( <NUM_LIT> ) ;


<s> MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; if ( <ISA_LIT>MCExpr :: isSupportedBinaryExpr ( VK , BE ) ) return <ISA_LIT>MCExpr :: create ( VK , Expr , getContext ( ) ) ; const MCExpr * LExp = evaluateRelocExpr ( BE -> getLHS ( ) , RelocStr ) ; const MCExpr * RExp = evaluateRelocExpr ( BE -> getRHS ( ) , RelocStr ) ; Res = MCBinaryExpr :: create ( BE -> getOpcode ( ) , LExp , RExp , getContext ( ) ) ; return Res ; } if ( const MCUnaryExpr * UN = dyn_cast < MCUnaryExpr > ( Expr ) ) { const MCExpr * UnExp = evaluateRelocExpr ( UN -> getSubExpr ( ) , RelocStr ) ; Res = MCUnaryExpr :: create ( UN -> getOpcode ( ) , UnExp , getContext ( ) ) ; return Res ;


<s> void <ISA_LIT>HazardRecognizer :: emitInstruction ( MachineInstr * MI , bool TakenBranch ) { SUnit SU ( MI , <NUM_LIT> ) ; SU . isCall = MI -> isCall ( ) ; const MCSchedClassDesc * SC = SchedModel -> resolveSchedClass ( MI ) ; for ( const MCWriteProcResEntry & PRE : make_range ( SchedModel -> getWriteProcResBegin ( SC ) , SchedModel -> getWriteProcResEnd ( SC ) ) ) { switch ( SchedModel -> getProcResource ( PRE . ProcResourceIdx ) -> BufferSize ) { case <NUM_LIT> : SU . hasReservedResource = true ; break ; case <NUM_LIT> : SU . isUnbuffered = true ; break ; default : break ; } } EmitInstruction ( & SU ) ; if ( TakenBranch && CurrGroupSize > <NUM_LIT> ) nextGroup ( false ) ; assert ( ( ! MI -> isTerminator ( ) || isBranchRetTrap ( MI ) ) && <STR_LIT> ) ;


<s> ELF<ISA_LIT>_X32AsmBackend ( const Target & T , uint8_t OSABI , StringRef CPU ) : ELF<ISA_LIT>AsmBackend ( T , OSABI , CPU ) {


<s> inline SDValue getI32Imm ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


<s> mem = or1k_adjust_atomic_subword ( mem , & shift , & mask ) ; if ( oldval != const0_rtx ) { oldval = convert_modes ( SImode , mode , oldval , <NUM_LIT> ) ; oldval = expand_binop ( SImode , ashl_optab , oldval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } if ( newval != const0_rtx ) { newval = convert_modes ( SImode , mode , newval , <NUM_LIT> ) ; newval = expand_binop ( SImode , ashl_optab , newval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; scratch = gen_reg_rtx ( SImode ) ; emit_load_locked ( SImode , scratch , mem ) ; retval = expand_binop ( SImode , and_optab , scratch , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = expand_binop ( SImode , xor_optab , scratch , retval , scratch , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; emit_compare ( EQ , retval , oldval ) ;


<s> Newname = Name . substr ( <NUM_LIT> , pos ) + <STR_LIT> + getTagName ( id ) ; return Newname ; } return Name + <STR_LIT> ;


<s> } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dump_registers ( TmpSup , * TRI ) ; dbgs ( ) << <STR_LIT> ) ; SRegs |= TmpSup ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dump_registers ( SRegs , * TRI ) ; dbgs ( ) << <STR_LIT> ) ; for ( int x = SRegs . find_first ( ) ; x >= <NUM_LIT> ; x = SRegs . find_next ( x ) ) { unsigned R = x ; for ( MCSuperRegIterator SR ( R , TRI ) ; SR . isValid ( ) ; ++ SR ) { if ( ! SRegs [ * SR ] ) continue ; SRegs [ R ] = false ; break ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dump_registers ( SRegs , * TRI ) ; dbgs ( ) << <STR_LIT> ) ; CSI . clear ( ) ; using SpillSlot = TargetFrameLowering :: SpillSlot ; unsigned NumFixed ; int MinOffset = <NUM_LIT> ; const SpillSlot * FixedSlots = getCalleeSavedSpillSlots ( NumFixed ) ; for ( const SpillSlot * S = FixedSlots ; S != FixedSlots + NumFixed ; ++ S ) { if ( ! SRegs [ S -> Reg ] ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( S -> Reg ) ; int FI = MFI . CreateFixedSpillStackObject ( TRI -> getSpillSize ( * RC ) , S -> Offset ) ; MinOffset = std :: min ( MinOffset , S -> Offset ) ; CSI . push_back ( CalleeSavedInfo ( S -> Reg , FI ) ) ; SRegs [ S -> Reg ] = false ; } for ( int x = SRegs . find_first ( ) ; x >= <NUM_LIT> ; x = SRegs . find_next ( x ) ) { unsigned R = x ;

const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( R ) ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> } if ( get<ISA_LIT>Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { PM . add ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; }


<s> MachineInstr * Flat = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( PtrReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * Flat , TII , TRI , RBI ) ; I . eraseFromParent ( ) ;


<s> <ISA_LIT>ELFTargetAsmInfo :: <ISA_LIT>ELFTargetAsmInfo ( const Triple & Triple ) { AsmTransCBE = x86_asm_table ; AssemblerDialect = AsmWriterFlavor ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; HasLEB128 = true ;


<s> return getSramEccSetting ( ) == TargetIDSetting :: On || getSramEccSetting ( ) == TargetIDSetting :: Off ;


<s> <ISA_LIT>64TargetMachine :: <ISA_LIT>64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) {


<s> MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> SetCCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; unsigned Opc = <NUM_LIT> ; bool Unsigned = false ; bool Swap = false ; unsigned SSECC ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> CC = <STR_LIT> ( CC ) ; unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ; adjustBBOffsetsAfter ( MBB ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;

SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> bool shouldTransformSignedTruncationCheck ( EVT XVT , unsigned KeptBits ) const override { if ( XVT . isVector ( ) ) return false ; auto VTIsOk = [ ] ( EVT VT ) -> bool {

return VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ;


<s> Value * <ISA_LIT>IREmitter :: visitCMPZ ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> case CallingConv :: <ISA_LIT>_APCS : case CallingConv :: Swift : break ; } for ( const Argument & Arg : F -> args ( ) ) { if ( Arg . getArgNo ( ) >= <NUM_LIT> ) return false ; if ( Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: ByVal ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> :


<s> Inst . dump_pretty ( OS ) ; OS << <STR_LIT> ; report_fatal_error ( <STR_LIT> + OS . str ( ) ) ; } Inst . setOpcode ( RelaxedOp ) ;


<s> O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ;


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( need_to_save ( i * <NUM_LIT> ) || need_to_save ( i * <NUM_LIT> + <NUM_LIT> ) ) { cfun -> machine -> need_to_push [ i ] = <NUM_LIT> ; cfun -> machine -> framesize_regs += <NUM_LIT> ; }

else cfun -> machine -> need_to_push [ i ] = <NUM_LIT> ;


<s> case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getLocRange ( ) ) ; case Match_ConversionFail : return true ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; }


<s> bool hasJMPCALL ( ) const { return m_hasJMPCALL ;


<s> t = __ev_mwhsmf ( a , b ) ; return __ev_addsmiaaw ( t ) ;


<s> if ( fi >= Size ) { Size *= <NUM_LIT> ; if ( fi >= Size ) Size = fi + <NUM_LIT> ; GPRCS2Frames . resize ( Size ) ; }


<s> bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; }


<s> if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rn == <NUM_LIT> || Rd == Rn || Rd == Rt || Rd == Rt + <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRPairRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return LOW_REGS ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return MIDDLE_REGS ; else if ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) return HIGH_REGS ; else if ( regno == <NUM_LIT> ) return R15_TA_REG ;


<s> case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( ( ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) || Subtarget . hasStdExtZfh ( ) ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . hasStdExtZfh ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , Subtarget . getXLenVT ( ) , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } else if ( Op . getValueType ( ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) ) { if ( Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } return SDValue ( ) ; } case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : { assert ( Subtarget . hasStdExtZbp ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ;

unsigned Imm = VT . getSizeInBits ( ) - <NUM_LIT> ;


return ( __m128i ) __builtin_ia32_cvttps2uqq128_mask ( ( __v4sf ) __A , ( __v2di ) _mm_setzero_di ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> Register R0 = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; Register R12 = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( SR1 ) * SR1 = R0 ; if ( SR2 ) { assert ( SR1 && <STR_LIT> ) ; * SR2 = R12 ; } if ( ( UseAtEnd && MBB -> isReturnBlock ( ) ) || ( ! UseAtEnd && ( & MBB -> getParent ( ) -> front ( ) == MBB ) ) ) return true ; RS . enterBasicBlock ( * MBB ) ; if ( UseAtEnd && ! MBB -> empty ( ) ) { MachineBasicBlock :: iterator MBBI = MBB -> getFirstTerminator ( ) ; if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) && ! RS . isRegUsed ( R12 ) ) return true ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MBB -> getParent ( ) ) ; BitVector BV = RS . getRegsAvailable ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; for ( int i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) BV . reset ( CSRegs [ i ] ) ; if ( SR1 ) { int FirstScratchReg = BV . find_first ( ) ; * SR1 = FirstScratchReg == - <NUM_LIT> ? ( unsigned ) <STR_LIT> : FirstScratchReg ; } if ( SR2 ) { int SecondScratchReg = BV . find_next ( * SR1 ) ; if ( SecondScratchReg != - <NUM_LIT> ) * SR2 = SecondScratchReg ; else * SR2 = TwoUniqueRegsRequired ? Register ( ) : * SR1 ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectDSAppendConsume ( SDNode * N , unsigned IntrID ) { unsigned Opc = IntrID == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Ptr = N -> getOperand ( <NUM_LIT> ) ; MemIntrinsicSDNode * M = cast < MemIntrinsicSDNode > ( N ) ; MachineMemOperand * MMO = M -> getMemOperand ( ) ; bool IsGDS = M -> getAddressSpace ( ) == <ISA_LIT>AS :: REGION_ADDRESS ; SDValue Offset ; if ( CurDAG -> isBaseWithConstantOffset ( Ptr ) ) { SDValue PtrBase = Ptr . getOperand ( <NUM_LIT> ) ; SDValue PtrOffset = Ptr . getOperand ( <NUM_LIT> ) ; const APInt & OffsetVal = cast < ConstantSDNode > ( PtrOffset ) -> getAPIntValue ( ) ; if ( isDSOffsetLegal ( PtrBase , OffsetVal . getZExtValue ( ) ) ) { N = glueCopyToM0 ( N , PtrBase ) ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ; } } if ( ! Offset ) {


<s> return decodeSrcOp ( OPW32 , Val ) ;


<s> bool isBitfieldWidth ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ;

if ( Res . getSymB ( ) ) report_fatal_error ( <STR_LIT> ) ;


<s> const char * name ; while ( <NUM_LIT> ) { switch ( GET_CODE ( x ) ) { case MEM : case CONST : x = XEXP ( x , <NUM_LIT> ) ; break ; case UNSPEC : x = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; break ; case PLUS : if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; x = XEXP ( x , <NUM_LIT> ) ; break ; default : goto done ; } } done :

if ( GET_CODE ( x ) != SYMBOL_REF ) return <NUM_LIT> ;


<s> std :: string getNextCallSiteMagicPrivate ( ) {


<s> SDValue Ops [ <NUM_LIT> ] = { Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Data_Lo . getValue ( <NUM_LIT> ) } ; Data_Hi = DAG . getNode ( <STR_LIT> , dl , VTList , Ops , <NUM_LIT> ) ; SDValue PCLATH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Data_Hi ) ; Callee = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Data_Lo , PCLATH ) ; SDValue Call = DAG . getNode ( <STR_LIT> , dl , Tys , Chain , Callee , OperFlag ) ; Chain = getChain ( Call ) ; OperFlag = getOutFlag ( Call ) ; SDValue SeqEnd = DAG . getCALLSEQ_END ( Chain , ZeroOperand , ZeroOperand , OperFlag ) ; Chain = getChain ( SeqEnd ) ; OperFlag = getOutFlag ( SeqEnd ) ; DataAddr_Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Call , OperFlag ) ; SeqStart = DAG . getCALLSEQ_START ( Chain , ZeroOperand ) ; Chain = getChain ( SeqStart ) ; OperFlag = getOutFlag ( SeqStart ) ;

Data_Lo = DAG . getNode ( <STR_LIT> , dl , VTList , Lo , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> return __builtin_mve_vcmpeqq_fv8hf ( __a , __b ) ;


<s> unsigned Opc = <NUM_LIT> ; bool Signed = true ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : break ; case <STR_LIT> : Signed = false ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) Opc = <STR_LIT> ; break ; }


<s> Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( Rt == <NUM_LIT> || Rt2 == <NUM_LIT> || Rm == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodeSPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> DwarfAbbrevSection = <STR_LIT> ; DwarfInfoSection = <STR_LIT> ; DwarfLineSection = <STR_LIT> ; DwarfFrameSection = <STR_LIT> ; DwarfPubNamesSection = <STR_LIT> ; DwarfPubTypesSection = <STR_LIT> ; DwarfStrSection = <STR_LIT> ; DwarfLocSection = <STR_LIT> ; DwarfARangesSection = <STR_LIT> ; DwarfRangesSection = <STR_LIT> ; DwarfMacInfoSection = <STR_LIT> ; SupportsExceptionHandling = false ;


<s> if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return <STR_LIT> ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> hasExternalWeakLinkage ( ) ) {

if ( TM . getRelocationModel ( ) == Reloc :: Static ) return <STR_LIT> ;


<s> MachineOperand & Op1 = AluIter -> getOperand ( <NUM_LIT> ) ; MachineOperand & Op2 = AluIter -> getOperand ( <NUM_LIT> ) ; if ( ! isSameOperand ( Dest , Base ) || ! isSameOperand ( Dest , Op1 ) ) return false ; if ( Op2 . isImm ( ) ) { if ( Offset . isReg ( ) && Offset . getReg ( ) == <STR_LIT> ) return true ; if ( Offset . isImm ( ) && ( ( Offset . getImm ( ) == <NUM_LIT> && ( ( IsSpls && isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) ) || ( ! IsSpls && isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) ) ) ) || Offset . getImm ( ) == Op2 . getImm ( ) ) ) return true ; } else if ( Op2 . isReg ( ) ) { if ( Offset . isReg ( ) && Op2 . getReg ( ) == Offset . getReg ( ) ) return true ; } else return false ; return false ;


<s> if ( isVerbose ( ) ) { const MCSectionELF * CommentSection = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; OutStreamer . SwitchSection ( CommentSection ) ; if ( STM . getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { OutStreamer . emitRawComment ( <STR_LIT> , false ) ; OutStreamer . emitRawComment ( <STR_LIT> + Twine ( KernelInfo . CodeLen ) , false ) ; OutStreamer . emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumSGPR ) , false ) ; OutStreamer . emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumVGPR ) , false ) ; OutStreamer . emitRawComment ( <STR_LIT> + Twine ( KernelInfo . FloatMode ) , false ) ; OutStreamer . emitRawComment ( <STR_LIT> + Twine ( KernelInfo . IEEEMode ) , false ) ; OutStreamer . emitRawComment ( <STR_LIT> + Twine ( KernelInfo . ScratchSize ) , false ) ; } else {

R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ;


<s> if ( ! TII . isLegalFLATOffset ( Offset . getValue ( ) , AddrSpace , Signed ) ) return Default ; Register BasePtr = OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( BasePtr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset . getValue ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> if ( SDValue BlendOp = lowerVSELECTtoVectorShuffle ( Op , Subtarget , DAG ) ) return BlendOp ; MVT CondVT = Cond . getSimpleValueType ( ) ; unsigned CondEltSize = Cond . getScalarValueSizeInBits ( ) ; if ( CondEltSize == <NUM_LIT> ) return Op ; if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue Mask = DAG . getSetCC ( dl , MaskVT , Cond , DAG . getConstant ( <NUM_LIT> , dl , CondVT ) , <STR_LIT> ) ; return DAG . getSelect ( dl , VT , Mask , LHS , RHS ) ; } if ( CondEltSize != EltSize ) { if ( CondEltSize != DAG . ComputeNumSignBits ( Cond ) ) return SDValue ( ) ; MVT NewCondSVT = <STR_LIT> ( EltSize ) ; MVT NewCondVT = <STR_LIT> ( NewCondSVT , NumElts ) ; Cond = DAG . getSExtOrTrunc ( Cond , dl , NewCondVT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cond , LHS , RHS ) ; } switch ( VT . SimpleTy ) { default : return Op ; case <STR_LIT> : if ( Subtarget . hasAVX2 ( ) ) return Op ; return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : { MVT CastVT = <STR_LIT> ( <STR_LIT> , NumElts * <NUM_LIT> ) ;

Cond = DAG . getBitcast ( CastVT , Cond ) ;


<s> assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace ) ; bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsQPXType = ST -> hasQPX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ; if ( IsVSXType || ( ST -> hasVSX ( ) && IsAltivecType ) ) return Cost ; Cost += LT . first * ( SrcBytes / Alignment - <NUM_LIT> ) ; if ( Src -> isVectorTy ( ) && Opcode == Instruction :: Store ) for ( int i = <NUM_LIT> , e = Src -> getVectorNumElements ( ) ; i < e ; ++ i ) Cost += getVectorInstrCost ( Instruction :: ExtractElement , Src , i ) ; return Cost ;


<s> static SDValue constantFoldBFE ( SelectionDAG & DAG , IntTy Src0 , uint32_t Offset , uint32_t Width , const SDLoc & DL ) { if ( Width + Offset < <NUM_LIT> ) { uint32_t Shl = static_cast < uint32_t > ( Src0 ) << ( <NUM_LIT> - Offset - Width ) ; IntTy Result = static_cast < IntTy > ( Shl ) >> ( <NUM_LIT> - Width ) ; return DAG . getConstant ( Result , DL , <STR_LIT> ) ; } return DAG . getConstant ( Src0 >> Offset , DL , <STR_LIT> ) ;


<s> static void xtensa_reorg_loops ( void ) {

if ( TARGET_LOOPS ) reorg_loops ( false , & xtensa_doloop_hooks ) ;


<s> case BRIG_TYPE_U8X4 : case BRIG_TYPE_S8X4 : case BRIG_TYPE_F16X2 : case BRIG_TYPE_S16X2 : case BRIG_TYPE_U16X2 : return true ; default : return false ; } } case <NUM_LIT> : { switch ( BT ) { case BRIG_TYPE_U64 : case BRIG_TYPE_B64 : case BRIG_TYPE_F64 : case BRIG_TYPE_S64 : case BRIG_TYPE_F16X4 : case BRIG_TYPE_F32X2 : case BRIG_TYPE_ROIMG : case BRIG_TYPE_RWIMG : case BRIG_TYPE_S16X4 : case BRIG_TYPE_S32X2 : case BRIG_TYPE_S8X8 : case BRIG_TYPE_SAMP : case BRIG_TYPE_SIG32 : case BRIG_TYPE_SIG64 : case BRIG_TYPE_U16X4 : case BRIG_TYPE_U32X2 : case BRIG_TYPE_U8X8 : case BRIG_TYPE_WOIMG : return true ; default : return false ; } } case <NUM_LIT> : { switch ( BT ) { case BRIG_TYPE_B1 : case BRIG_TYPE_B8 : case BRIG_TYPE_S8 : case BRIG_TYPE_U8 : return true ; default : return false ; } } case <NUM_LIT> : { switch ( BT ) { case BRIG_TYPE_U16 : case BRIG_TYPE_B16 : case BRIG_TYPE_S16 : case BRIG_TYPE_F16 : return true ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { Triple TheTriple ( TT ) ; RM = TheTriple . isOSDarwin ( ) ? Reloc :: PIC_ : Reloc :: DynamicNoPIC ; }

X -> initMCCodeGenInfo ( RM , CM , OL ) ;


<s> static bool isVShiftRImm ( SDValue Op , EVT VT , bool isNarrow , bool isIntrinsic , int64_t & Cnt ) { assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; if ( isIntrinsic ) Cnt = - Cnt ;

return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) ) ;


<s> switch ( MO . getType ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case MachineOperand :: MO_Register : assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && <STR_LIT> ) ; operand = <STR_LIT> + LowercaseString ( getRegisterName ( MO . getReg ( ) ) ) ; break ; } unsigned mfNum = MI -> getParent ( ) -> getParent ( ) -> getFunctionNumber ( ) ; unsigned bbNum = MI -> getParent ( ) -> getNumber ( ) ; O << '\n' << <STR_LIT> << mfNum << '_' << bbNum << <STR_LIT> ; O << <STR_LIT> << mfNum << '_' << bbNum << '\n' ;

O << <STR_LIT> << <STR_LIT> << mfNum << '_' << bbNum << <STR_LIT> << operand << '\n' ;