<s> DebugLoc dl = MI -> getDebugLoc ( ) ; bool isAM5 = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isAM2 = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( isAM2 && <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) != <NUM_LIT> ) return false ; else if ( isAM5 && <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) != <NUM_LIT> ) return false ; else if ( isT2i32Load ( Opcode ) || isT2i32Store ( Opcode ) ) if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; bool isLd = isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( isLd && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base ) return false ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( MI , PredReg ) ; bool DoMerge = false ; <STR_LIT> AddSub = <STR_LIT> ; unsigned NewOpc = <NUM_LIT> ; unsigned Limit = isAM5 ? <NUM_LIT> : ( isAM2 ? <NUM_LIT> : <NUM_LIT> ) ; if ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; if ( isMatchingDecrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; NewOpc = getPreIndexedLoadStoreOpcode ( Opcode ) ; } else if ( ! isAM5 && isMatchingIncrement ( PrevMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; NewOpc = getPreIndexedLoadStoreOpcode ( Opcode ) ; } if ( DoMerge ) MBB . erase ( PrevMBBI ) ; } if ( ! DoMerge && MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; if ( ! isAM5 && isMatchingDecrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; AddSub = <STR_LIT> ; NewOpc = getPostIndexedLoadStoreOpcode ( Opcode ) ; } else if ( isMatchingIncrement ( NextMBBI , Base , Bytes , Limit , Pred , PredReg ) ) { DoMerge = true ; NewOpc = getPostIndexedLoadStoreOpcode ( Opcode ) ; } if ( DoMerge ) { if ( NextMBBI == I ) { Advance = true ; ++ I ;


<s> const MachineOperand * AddrOp = AddrReg [ i ] ; if ( AddrOp -> isImm ( ) ) continue ; if ( ! AddrOp -> isReg ( ) ) return false ; if ( AddrOp -> getReg ( ) . isPhysical ( ) ) return false ; if ( MRI . hasOneNonDBGUse ( AddrOp -> getReg ( ) ) ) return false ; } return true ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Identifier = getParser ( ) . getTok ( ) . getIdentifier ( ) ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: getVariantKindForName ( Identifier ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { Error ( getLoc ( ) , <STR_LIT> ) ;


<s> return ( Val == std :: numeric_limits < int32_t > :: min ( ) ) || ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ; unsigned Opc = is64Bit ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ;

BuildMI ( MBB , MI , DL , get ( Opc ) , Reg ) ;


<s> static bool important_for_bundling_p ( rtx_insn * insn ) {

return ( INSN_P ( insn ) && ia64_safe_itanium_class ( insn ) != ITANIUM_CLASS_IGNORE && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { int FrameIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> , true ) ;


<s> <ISA_LIT>Operand ( enum Kind Kind , SMLoc Start , SMLoc End ) : Base ( ) , Kind ( Kind ) , Start ( Start ) , End ( End ) {


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_VGPR_32 ( unsigned Val ) const { return createRegOperand ( <STR_LIT> , Val ) ;


<s> break ; case <NUM_LIT> : LoadMI = & * MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Adrp } ) . addConstantPoolIndex ( CPIdx , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; break ; case <NUM_LIT> : LoadMI = & * MIRBuilder . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Adrp } ) . addConstantPoolIndex ( CPIdx , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; break ; default : LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * CPVal -> getType ( ) ) ; return nullptr ; } LoadMI -> addMemOperand ( MF , MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ( Size ) ) ) ;

constrainSelectedInstRegOperands ( * Adrp , TII , TRI , RBI ) ;


<s> if ( SHFIndices [ i ] == - <NUM_LIT> ) SHFIndices [ i ] = Idx ; if ( ! ( Idx == - <NUM_LIT> || Idx == SHFIndices [ i ] ) ) return SDValue ( ) ; } } APInt Imm ( <NUM_LIT> , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { int Idx = SHFIndices [ i ] ; if ( Idx == - <NUM_LIT> ) Idx = <NUM_LIT> ; Imm <<= <NUM_LIT> ;


<s> for ( const unsigned * Alias = TM . getRegisterInfo ( ) -> getAliasSet ( Reg ) ;

* Alias ; ++ Alias ) if ( RegSet . count ( * Alias ) ) return true ;


<s> bool MadeChange = false ; for ( BasicBlock & BB : F ) { BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; } } return MadeChange ;


<s> case <STR_LIT> : case <STR_LIT> : return emitCALL ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return emitPEXTRACT ( MI , MBB , false ) ; case <STR_LIT> : case <STR_LIT> : return emitPEXTRACT ( MI , MBB , true ) ; case <STR_LIT> : return emitPINSERT ( MI , MBB ) ; case <STR_LIT> : return emitPBCLRSET ( MI , MBB , false ) ; case <STR_LIT> : return emitPBCLRSET ( MI , MBB , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitPRN ( MI , MBB ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> break ; } case Instruction :: GetElementPtr : { <ISA_LIT>AddressMode SavedAM = AM ; uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { Value * Op = * i ; if ( const StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; Disp += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; if ( ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { Disp += CI -> getSExtValue ( ) * S ; } else if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) ; if ( IndexReg == <NUM_LIT> ) return false ; } else goto unsupported_gep ; } } if ( ! isInt32 ( Disp ) ) break ; AM . IndexReg = IndexReg ; AM . Scale = Scale ; AM . Disp = ( uint32_t ) Disp ; if ( <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ) return true ; AM = SavedAM ; break ; unsupported_gep : break ; } } if ( GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; unsigned char GVFlags = Subtarget -> ClassifyGlobalReference ( GV , TM ) ; if ( isGlobalRelativeToPICBase ( GVFlags ) ) { AM . Base . Reg = getInstrInfo ( ) -> getGlobalBaseReg ( & MF ) ; } if ( ! isGlobalStubReference ( GVFlags ) ) {

if ( Subtarget -> isPICStyleRIPRel ( ) ) {


<s> Ops . push_back ( Target ) ; SDNode * Result = DAG . getNode ( Res . size ( ) > <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( Res ) , Ops ) . getNode ( ) ; if ( BR ) { SDValue Ops [ ] = { BR -> getOperand ( <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; SDValue NewBR = DAG . getNode ( <STR_LIT> , DL , BR -> getVTList ( ) , Ops ) ; DAG . ReplaceAllUsesWith ( BR , NewBR . getNode ( ) ) ; BR = NewBR . getNode ( ) ; } SDValue Chain = SDValue ( Result , Result -> getNumValues ( ) - <NUM_LIT> ) ;

for ( unsigned i = <NUM_LIT> , e = Intr -> getNumValues ( ) - <NUM_LIT> ; i != e ; ++ i ) {


<s> static bool classof ( const <ISA_LIT>ConstantPoolValue * ACPV ) { return ACPV -> isJT ( ) ;


<s> mergeable_constant_section ( mode , align , <NUM_LIT> ) ;


<s> uint64_t <ISA_LIT>FrameLowering :: getTOCSaveOffset ( ) const { return TOCSaveOffset ;


<s> void <ISA_LIT>DeadRegisterDefinitions :: processMachineBasicBlock ( MachineBasicBlock & MBB ) { const MachineFunction & MF = * MBB . getParent ( ) ; for ( MachineInstr & MI : MBB ) { if ( usesFrameIndex ( MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( MI . definesRegister ( <STR_LIT> ) || MI . definesRegister ( <STR_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( atomicBarrierDroppedOnZero ( MI . getOpcode ( ) ) || atomicReadDroppedOnZero ( MI . getOpcode ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ;

for ( int I = <NUM_LIT> , E = Desc . getNumDefs ( ) ; I != E ; ++ I ) {


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) {

unsigned SlotSize = Subtarget . getSlotSize ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerROTL ( SDValue Op , SelectionDAG & DAG ) const { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return Op ;


<s> bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , const BranchProbability & Probability ) const override {


<s> uint32_t Enc = <STR_LIT> ( - CE -> getValue ( ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Enc ) ) ;


<s> fprintf ( file , <STR_LIT> , i ) ; fprintf ( file , <STR_LIT> , ( optional_tbtab << <NUM_LIT> ) | ( ( info -> first_fp_reg_save != <NUM_LIT> ) << <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , ( ( optional_tbtab << <NUM_LIT> ) | ( ( optional_tbtab & frame_pointer_needed ) << <NUM_LIT> ) | ( info -> cr_save_p << <NUM_LIT> ) | ( info -> lr_save_p ) ) ) ; fprintf ( file , <STR_LIT> , ( info -> push_p << <NUM_LIT> ) | ( <NUM_LIT> - info -> first_fp_reg_save ) ) ; fprintf ( file , <STR_LIT> , ( <NUM_LIT> - first_reg_to_save ( ) ) ) ; if ( optional_tbtab ) { tree decl ; int next_parm_info_bit = <NUM_LIT> ; for ( decl = DECL_ARGUMENTS ( current_function_decl ) ; decl ; decl = DECL_CHAIN ( decl ) ) { rtx parameter = DECL_INCOMING_RTL ( decl ) ; machine_mode mode = GET_MODE ( parameter ) ; if ( GET_CODE ( parameter ) == REG ) { if ( SCALAR_FLOAT_MODE_P ( mode ) ) { int bits ; float_parms ++ ; switch ( mode ) { case SFmode : case SDmode : bits = <NUM_LIT> ; break ; case DFmode : case DDmode : case TFmode : case TDmode : case IFmode : case KFmode : bits = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( next_parm_info_bit > <NUM_LIT> ) parm_info |= ( bits << ( next_parm_info_bit - <NUM_LIT> ) ) ; next_parm_info_bit -= <NUM_LIT> ; } else { fixed_parms += ( ( GET_MODE_SIZE ( mode ) + ( UNITS_PER_WORD - <NUM_LIT> ) ) / UNITS_PER_WORD ) ; next_parm_info_bit -= <NUM_LIT> ; } } } } fprintf ( file , <STR_LIT> , fixed_parms ) ; fprintf ( file , <STR_LIT> , ( ( float_parms << <NUM_LIT> ) | ( ! optimize ) ) ) ; if ( optional_tbtab ) { if ( fixed_parms || float_parms ) fprintf ( file , <STR_LIT> , parm_info ) ; fputs ( <STR_LIT> , file ) ; ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , <STR_LIT> ) ; RS6000_OUTPUT_BASENAME ( file , fname ) ; putc ( '-' , file ) ; rs6000_output_function_entry ( file , fname ) ;


<s> void <ISA_LIT>JITInfo :: replaceMachineCodeForFunction ( void * Old , void * New ) {


<s> void printf256mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ; printMemReference ( MI , OpNo , O ) ;


<s> if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { unsigned Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace ) ; unsigned SplitCost = getScalarizationOverhead ( Src , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; return NumElem * Cost + SplitCost ; } } std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; unsigned Cost = LT . first * <NUM_LIT> ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> && ! ST -> hasAVX2 ( ) ) Cost *= <NUM_LIT> ;


<s> static inline bool getAM6WBFlag ( unsigned Mode ) {


<s> SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) . getRetAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForRet ( CC ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getValVT ( ) != TLI . getValueType ( RV -> getType ( ) ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DstReg = VA . getLocReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; if ( ! SrcRC -> contains ( DstReg ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg ) ; MRI . addLiveOut ( VA . getLocReg ( ) ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ; return true ;


<s> return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> return __builtin_aarch64_crypto_sha1cv4si_uuuu ( hash_abcd , hash_e , wk ) ;


<s> auto Signature = std :: make_unique < <STR_LIT> > ( std :: move ( Returns ) , std :: move ( Params ) ) ; MCSymbol * Sym = Printer . createTempSymbol ( <STR_LIT> ) ; auto * WasmSym = cast < MCSymbolWasm > ( Sym ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; Printer . addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( <STR_LIT> ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( WasmSym , MCSymbolRefExpr :: VK_WASM_TYPEINDEX , Ctx ) ;

return MCOperand :: createExpr ( Expr ) ;


<s> bool isIndirectJump ( const MCInst & MI ) { return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> if ( ! TT . isOSDarwin ( ) && ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ) ) CM = CodeModel :: Medium ; } X -> initMCCodeGenInfo ( RM , CM , OL ) ; return X ;


<s>
raw_string_ostream
OS
(
Str
)
;
if
(
DLoc
.
isUnknown
(
)
==
false
)
{
DILocation
DIL
(
DLoc
.
getAsMDNode
(
Fn
.
getContext
(
)
)
)
;
StringRef
Filename
=
DIL
.
getFilename
(
)
;
unsigned
Line
=
DIL
.
getLineNumber
(
)
;
unsigned
Column
=
DIL
.
getColumnNumber
(
)
;
OS
<<
Filename
<<
':'
<<
Line
<<
':'
<<
Column
<<
' '
;
}

OS
<<
<STR_LIT>
<<
Fn
.
getName
(
)
<<
' '
<<
*
Fn
.
getFunctionType
(
)
<<
'\n'
<<
Description
;


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; ReplaceUses ( N , Result_3 ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> } Register DestPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , DestPhiReg ) . addUse ( OpDestReg ) . addMBB ( TpEntry ) . addUse ( CurrDestReg ) . addMBB ( TpLoopBody ) ; Register LoopCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingLoopIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , LoopCounterPhiReg ) . addUse ( TotalIterationsReg ) . addMBB ( TpEntry ) . addUse ( RemainingLoopIterationsReg ) . addMBB ( TpLoopBody ) ; Register PredCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingElementsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , PredCounterPhiReg ) . addUse ( ElementCountReg ) . addMBB ( TpEntry ) . addUse ( RemainingElementsReg ) . addMBB ( TpLoopBody ) ; Register VccrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , VccrReg ) . addUse ( PredCounterPhiReg ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , RemainingElementsReg ) . addUse ( PredCounterPhiReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register SrcValueReg ; if ( IsMemcpy ) { SrcValueReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) ) . addDef ( CurrSrcReg ) . addDef ( SrcValueReg ) . addReg ( SrcPhiReg ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addUse ( VccrReg ) ;


<s> printMemReference ( MI , OpNo , O ) ;


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ;


<s> Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: Static ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , Result , PICLabel ) ;


<s> initialize ( MF ) ; unskipableSimplifyCode ( ) ; if ( skipFunction ( MF . getFunction ( ) ) ) return false ; return simplifyCode ( ) ;


<s> SDValue FPSCR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPSCR , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RMODE , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


initializeMVELaneInterleavingPass ( Registry ) ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizePreloadedArgIntrin ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B , <STR_LIT> ArgType ) const {

const ArgDescriptor * Arg = getArgDescriptor ( B , ArgType ) ;


<s> static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const MCPhysReg DoubleRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

return DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT> , DoubleRegDecoderTable ) ;


<s> edge e ; if ( ! crtl -> tail_call_emit ) return false ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) if ( e -> flags & EDGE_SIBCALL ) { rtx_insn * call = BB_END ( e -> src ) ; if ( ! CALL_P ( call ) ) call = prev_nonnote_nondebug_insn ( call ) ; gcc_assert ( CALL_P ( call ) && SIBLING_CALL_P ( call ) ) ; if ( find_regno_fusage ( call , USE , <NUM_LIT> ) || is_indirect_tailcall_p ( call ) ) return true ; }


<s> UsedNZCV ( ) : N ( false ) , Z ( false ) , C ( false ) , V ( false ) {


<s> NodeAddr < PhiUseNode * > PUA = newNode ( NodeAttrs :: Ref | NodeAttrs :: Use | Flags ) ; assert ( Flags & NodeAttrs :: PhiRef ) ; PUA . Addr -> setRegRef ( RR , * this ) ; PUA . Addr -> setPredecessor ( PredB . Id ) ; return PUA ;


<s> if ( ! cast < ConstantInt > ( DupQLane -> getArgOperand ( <NUM_LIT> ) ) -> isZero ( ) ) return None ; auto * VecIns = dyn_cast < IntrinsicInst > ( DupQLane -> getArgOperand ( <NUM_LIT> ) ) ; if ( ! VecIns || VecIns -> getIntrinsicID ( ) != <STR_LIT> ) return None ; if ( ! isa < UndefValue > ( VecIns -> getArgOperand ( <NUM_LIT> ) ) ) return None ; if ( ! cast < ConstantInt > ( VecIns -> getArgOperand ( <NUM_LIT> ) ) -> isZero ( ) ) return None ; auto * ConstVec = dyn_cast < Constant > ( VecIns -> getArgOperand ( <NUM_LIT> ) ) ; if ( ! ConstVec ) return None ; auto * VecTy = dyn_cast < FixedVectorType > ( ConstVec -> getType ( ) ) ; auto * OutTy = dyn_cast < ScalableVectorType > ( II . getType ( ) ) ; if ( ! VecTy || ! OutTy || VecTy -> getNumElements ( ) != OutTy -> getMinNumElements ( ) ) return None ; unsigned NumElts = VecTy -> getNumElements ( ) ; unsigned PredicateBits = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { auto * Arg = dyn_cast < ConstantInt > ( ConstVec -> getAggregateElement ( I ) ) ; if ( ! Arg ) return None ; if ( ! Arg -> isZero ( ) ) PredicateBits |= <NUM_LIT> << ( I * ( <NUM_LIT> / NumElts ) ) ; } if ( PredicateBits == <NUM_LIT> ) { auto * PFalse = Constant :: getNullValue ( II . getType ( ) ) ; PFalse -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , PFalse ) ; } unsigned Mask = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) if ( ( PredicateBits & ( <NUM_LIT> << I ) ) != <NUM_LIT> ) Mask |= ( I % <NUM_LIT> ) ; unsigned PredSize = Mask & - Mask ; auto * PredType = ScalableVectorType :: get ( Type :: getInt1Ty ( Ctx ) , <STR_LIT> / ( PredSize * <NUM_LIT> ) ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += PredSize ) if ( ( PredicateBits & ( <NUM_LIT> << I ) ) == <NUM_LIT> ) return None ; auto * PTruePat = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , <STR_LIT> ) ; auto * PTrue = Builder . CreateIntrinsic ( <STR_LIT> , { PredType } , { PTruePat } ) ; auto * ConvertToSVBool = Builder . CreateIntrinsic ( <STR_LIT> , { PredType } , { PTrue } ) ;

auto * ConvertFromSVBool = Builder . CreateIntrinsic ( <STR_LIT> , { II . getType ( ) } , { ConvertToSVBool } ) ;


<s> SDValue InsVal = Op . getOperand ( <NUM_LIT> ) ; if ( ! InsVector . isUndef ( ) ) return SDValue ( ) ; if ( SDValue NegInsVal = isFNEG ( DAG , InsVal . getNode ( ) , Depth + <NUM_LIT> ) ) if ( NegInsVal . getValueType ( ) == VT . getVectorElementType ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , InsVector , NegInsVal , Op . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Opc == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Op1 , ScalarSize , UndefElts , EltBits , true , false ) ) { for ( unsigned I = <NUM_LIT> , E = EltBits . size ( ) ; I < E ; I ++ ) if ( ! UndefElts [ I ] && ! EltBits [ I ] . isSignMask ( ) ) return SDValue ( ) ; Op0 = peekThroughBitcasts ( Op0 ) ;

if ( Op0 . getScalarValueSizeInBits ( ) == ScalarSize ) return Op0 ;


<s> MachineInstr & MI = * MBBI ; const bool UseZeroBasedSandbox = FlagUseZeroBasedSandbox ; if ( ! IsLoad ( MI ) && ! IsStore ( MI ) ) return false ; if ( IsPushPop ( MI ) ) return false ; unsigned MemOp ; if ( ! FindMemoryOperand ( MI , & MemOp ) ) return false ; assert ( isMem ( & MI , MemOp ) ) ; MachineOperand & BaseReg = MI . getOperand ( MemOp + <NUM_LIT> ) ; MachineOperand & Scale = MI . getOperand ( MemOp + <NUM_LIT> ) ; MachineOperand & IndexReg = MI . getOperand ( MemOp + <NUM_LIT> ) ; MachineOperand & SegmentReg = MI . getOperand ( MemOp + <NUM_LIT> ) ; if ( BaseReg . getReg ( ) == <STR_LIT> ) return false ; IndexReg . setReg ( PromoteRegTo64 ( IndexReg . getReg ( ) ) ) ; BaseReg . setReg ( PromoteRegTo64 ( BaseReg . getReg ( ) ) ) ;

assert ( IndexReg . getSubReg ( ) == <NUM_LIT> ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return isInt < <NUM_LIT> > ( MFI . getMaxCallFrameSize ( ) ) && ! MFI . hasVarSizedObjects ( ) ;


<s> break ; } const MCExpr * IdVal ; SMLoc S = getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ;

SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ;


<s> if ( <ISA_LIT> . first == SourceReg && ( <ISA_LIT> . second == nullptr || <ISA_LIT> . second == SourceMBB ) ) { return I ; } }


<s> initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( Align ( <NUM_LIT> ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; if ( isThumb && STI -> hasV8MBaselineOps ( ) ) MadeChange |= optimizeThumb2Branches ( ) ; if ( GenerateTBB && ! STI -> genExecuteOnly ( ) ) MadeChange |= optimizeThumb2JumpTables ( ) ; verify ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; if ( CPE . CPEMI && CPE . CPEMI -> getOperand ( <NUM_LIT> ) . isCPI ( ) ) AFI -> recordCPEClone ( i , CPE . CPI ) ; } }

LLVM_DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ;


return mode_for_vector ( elem_mode , nunits ) ;


<s> return ( ( val & ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << <NUM_LIT> ) ) == val || ( val & ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << <NUM_LIT> ) ) == val ) ;


<s> return HasDPP && getGeneration ( ) < GFX10 ;


<s> bool Is64Bit = Subtarget -> is64Bit ( ) ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } SDValue Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ; if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else {

Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecondLastInst -> getOpcode ( ) == <STR_LIT> && LastInst -> getOpcode ( ) == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } return true ;


<s> <ISA_LIT>PseudoSourceValue ( unsigned Kind , const TargetInstrInfo & TII ) : PseudoSourceValue ( Kind , TII ) {


<s> if ( VT == <STR_LIT> ) return TypeLegal ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;


<s> } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) {

CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ;


<s> Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ; assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ; SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , Ptr , LoadNode -> getPointerInfo ( ) , MemVT , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , DAG . getValueType ( MemVT ) ) ; SDValue MergedValues [ <NUM_LIT> ] = { Res , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return SDValue ( ) ; } if ( Ptr . getOpcode ( ) != <STR_LIT> ) { assert ( VT == <STR_LIT> ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr ) ; return DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , LoadNode -> getMemOperand ( ) ) ; }


<s> virtual const <ISA_LIT>MachOWriterInfo * getMachOWriterInfo ( ) const { return & MachOWriterInfo ;


<s> rtx call ; call = XVECEXP ( PATTERN ( branch ) , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ;

if ( GET_CODE ( call ) != CALL ) abort ( ) ;


<s> MachineFunctionProperties getClearedProperties ( ) const override {

return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoPHIs ) ;


<s> if ( isThumb2 && TotalAdj != <NUM_LIT> ) MaxDisp -= ( <NUM_LIT> - TotalAdj ) ; if ( UserOffset <= TrialOffset ) { if ( TrialOffset - UserOffset <= MaxDisp ) return true ; } else if ( NegativeOK ) { if ( UserOffset - TrialOffset <= MaxDisp ) return true ; } return false ;


<s> if ( V2 . getOpcode ( ) == <STR_LIT> ) { if ( <STR_LIT> ( SVOp , <NUM_LIT> ) || <STR_LIT> ( SVOp , <NUM_LIT> ) || <STR_LIT> ( SVOp , <NUM_LIT> ) || <STR_LIT> ( SVOp , true ) || <STR_LIT> ( SVOp , true ) || <STR_LIT> ( SVOp , true ) != - <NUM_LIT> || <STR_LIT> ( SVOp , <NUM_LIT> , true ) || <STR_LIT> ( SVOp , <NUM_LIT> , true ) || <STR_LIT> ( SVOp , <NUM_LIT> , true ) || <STR_LIT> ( SVOp , <NUM_LIT> , true ) || <STR_LIT> ( SVOp , <NUM_LIT> , true ) || <STR_LIT> ( SVOp , <NUM_LIT> , true ) ) { return Op ; } } if ( <STR_LIT> ( SVOp , false ) || <STR_LIT> ( SVOp , false ) || <STR_LIT> ( SVOp , false ) != - <NUM_LIT> || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) || <STR_LIT> ( SVOp , <NUM_LIT> , false ) ) return Op ; SmallVector < int , <NUM_LIT> > PermMask ; SVOp -> getMask ( PermMask ) ; unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle = false ; break ; } if ( EltNo == <NUM_LIT> ) { EltNo = ByteSource / <NUM_LIT> ; } else if ( EltNo != ByteSource / <NUM_LIT> ) { isFourElementShuffle = false ;


<s> void rs6000_expand_extract_even ( rtx target , rtx op0 , rtx op1 ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , <NUM_LIT> ) ;

for ( i = <NUM_LIT> ; i < nelt ; i ++ ) perm . quick_push ( i * <NUM_LIT> ) ;


<s> void addBarrierOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( getBarrier ( ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand MOp1 = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand MOp2 = MI -> getOperand ( <NUM_LIT> ) ; if ( MOp1 . isImm ( ) && MOp2 . isFI ( ) ) { FrameIndex = MOp2 . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> Forbidden . insert ( R ) ; continue ; } if ( FRC == & <STR_LIT> || FRC == & <STR_LIT> ) { unsigned SubLo = HRI . get<ISA_LIT>SubRegIndex ( * FRC , <STR_LIT> ) ; unsigned SubHi = HRI . get<ISA_LIT>SubRegIndex ( * FRC , <STR_LIT> ) ; BitTracker :: RegisterRef TL = { R , SubLo } ; BitTracker :: RegisterRef TH = { R , SubHi } ; BitTracker :: RegisterRef ML , MH ; if ( findMatch ( TL , ML , AVB ) && findMatch ( TH , MH , AVB ) ) { auto * FRC = HBS :: getFinalVRegClass ( R , MRI ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ; BuildMI ( B , At , DL , HII . get ( TargetOpcode :: REG_SEQUENCE ) , NewR ) . addReg ( ML . Reg , <NUM_LIT> , ML . Sub ) . addImm ( SubLo ) . addReg ( MH . Reg , <NUM_LIT> , MH . Sub ) . addImm ( SubHi ) ; BT . put ( BitTracker :: RegisterRef ( NewR ) , BT . get ( R ) ) ;


<s> } ; static const StringRef HSAIntrinsicToAttr [ ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ;

if ( TT . getOS ( ) == Triple :: AMDHSA ) Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ;


<s> return isImm ( - <NUM_LIT> , <NUM_LIT> ) ;


<s> return ( Imm & <NUM_LIT> ) >> <NUM_LIT> ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _tile_storeconfig ( void * __config ) { __asm__ volatile ( <STR_LIT> : <STR_LIT> ( * ( ( void * * ) __config ) ) ) ;


<s> const TargetRegisterClass * RC ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) RC = MRI . getRegClass ( Reg ) ; else RC = getPhysRegClass ( Reg ) ;


<s> SDLoc DL ( Op ) ; bool HasAddrDiversity = ! isNullConstant ( AddrDiscriminator ) ; uint64_t PtrOffsetC = <NUM_LIT> ; if ( Ptr . getOpcode ( ) == <STR_LIT> ) { PtrOffsetC = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } GlobalAddressSDNode * PtrN = cast < GlobalAddressSDNode > ( Ptr . getNode ( ) ) ; SDValue TPtr = DAG . getTargetGlobalAddress ( PtrN -> getGlobal ( ) , DL , VT , <NUM_LIT> , <NUM_LIT> ) ; PtrOffsetC += PtrN -> getOffset ( ) ; assert ( PtrN -> getTargetFlags ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Ld = LowerPtrAuthGlobalAddressViaGOT ( Wrapper , ( <STR_LIT> ) KeyC , HasAddrDiversity , PtrN , DAG ) ) return Ld ; if ( HasAddrDiversity ) {

SDValue BlendIntID = DAG . getTargetConstant ( <STR_LIT> , DL , VT ) ;


<s> assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue N0 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( Subtarget . hasXOP ( ) || useVPTERNLOG ( Subtarget , VT ) || ! N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) || ! N1 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) return SDValue ( ) ;


<s> <ISA_LIT>FunctionInfo :: ~ <ISA_LIT>FunctionInfo ( ) {


<s> else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ; else if ( CONSTANT_P ( XEXP ( addr , <NUM_LIT> ) ) ) addr = XEXP ( addr , <NUM_LIT> ) ; else gcc_unreachable ( ) ;


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; if ( isa < FrameIndexSDNode > ( Base ) ) { return false ; } ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ;


<s> DEBUG ( F64Val -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue From [ ] = { SDValue ( N , <NUM_LIT> ) , SDValue ( N , <NUM_LIT> ) } ; SDValue To [ ] = { F64Val . getOperand ( <NUM_LIT> ) , F64Val . getOperand ( <NUM_LIT> ) } ; CurDAG -> ReplaceAllUsesOfValuesWith ( From , To , <NUM_LIT> ) ; } }


<s> return new <ISA_LIT>MCELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( CE ) ) ;


<s> void <ISA_LIT>DAGToDAGISel :: PostprocessISelDAG ( ) { const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; bool IsModified = false ; do { IsModified = false ;

SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_begin ( ) ;


<s> static DecodeStatus DecodeG8RC_NOX0RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { return decodeRegisterClass ( Inst , RegNo , XRegsNoX0 ) ;


<s> EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


AttributesSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> , SectionKind :: getMetadata ( ) ) ;


<s> if ( CurFile != <STR_LIT> ) OS . EmitRawText ( StringRef ( <STR_LIT> ) ) ;


<s> assert ( hasVInstructions ( ) && <STR_LIT> ) ; assert ( ( RVVVectorBitsMin == <NUM_LIT> || ( RVVVectorBitsMin >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMin ) ) ) && <STR_LIT> <STR_LIT> ) ;

assert ( ( RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == <NUM_LIT> ) && <STR_LIT> <STR_LIT> ) ;


<s> return parseIntWithPrefix ( <STR_LIT> , Operands ) ;


<s> static bool isAbsoluteReg ( unsigned Reg ) {


<s> if ( BytesRemoved ) * BytesRemoved = <NUM_LIT> ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) { continue ; } if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; }


<s> assert ( MI -> getOpcode ( ) == TargetOpcode :: COPY && <STR_LIT> ) ; for ( const auto & MO : MI -> operands ( ) ) { if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return <NUM_LIT> ; RegDomain OpDomain = getDomain ( MRI -> getRegClass ( MO . getReg ( ) ) , MRI -> getTargetRegisterInfo ( ) ) ; if ( OpDomain == DstDomain ) return - <NUM_LIT> ; }


<s> const MCExpr * Imm = Op -> getImm ( ) ; Op -> Kind = MEMORY_REG_IMM ; Op -> Mem . BaseReg = BaseReg ; Op -> Mem . AluOp = AluOp ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ;


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) {

return std :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ;


<s> return <NUM_LIT> ; case FK_SecRel_4 : case FK_Data_4 : case FK_PCRel_4 : return <NUM_LIT> ; case FK_SecRel_8 : case FK_Data_8 :


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : GlobalBaseReg ( <NUM_LIT> ) , VarArgsFrameOffset ( <NUM_LIT> ) , SRetReturnReg ( <NUM_LIT> ) , IsLeafProc ( false ) {


<s> tree type = TREE_TYPE ( field ) ; if ( TARGET_64BIT || TARGET_ALIGN_DOUBLE ) return computed ; if ( TARGET_IAMCU ) return iamcu_alignment ( type , computed ) ; mode = TYPE_MODE ( strip_array_types ( type ) ) ; if ( mode == DFmode || mode == DCmode || GET_MODE_CLASS ( mode ) == MODE_INT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT ) return MIN ( <NUM_LIT> , computed ) ; return computed ;


<s> TSTInst . setOpcode ( <STR_LIT> ) ; TSTInst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; if ( FlagSfiZeroMask ) { TSTInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; } else {

TSTInst . addOperand ( MCOperand :: CreateImm ( Mask ) ) ;


<s> assert ( Mask . size ( ) % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; unsigned HalfSize = Mask . size ( ) / <NUM_LIT> ;

for ( unsigned i = <NUM_LIT> ; i != HalfSize ; ++ i ) {


<s> if ( MV55 ) return <STR_LIT> ; if ( MV60 ) return <STR_LIT> ; if ( MV62 ) return <STR_LIT> ; if ( MV65 ) return <STR_LIT> ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) return SDValue ( ) ; } return SDValue ( ) ;


<s> return __builtin_mve_vbicq_n_sv4si ( __a , __imm ) ;


<s> ValidSwizzle . clear ( ) ; unsigned ConstCount ; BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = <NUM_LIT> , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( * IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , <STR_LIT> :: bank_swizzle ) ; ValidSwizzle . push_back ( ( <ISA_LIT>InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned > > TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ;


<s> <ISA_LIT>GenInstrInfo ( NULL , NULL ) , RI ( tm , * this ) {


<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { return false ;


<s> return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > MemOps ; SDValue FIN = Op . getOperand ( <NUM_LIT> ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsGPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , DAG . getConstant ( FuncInfo -> getVarArgsFPOffset ( ) , DL , <STR_LIT> ) , FIN , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;

SDValue OVFIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ;


<s> SDValue PtrLo = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , Offset + <NUM_LIT> , GAFlags ) ; SDValue PtrHi ; if ( GAFlags == <ISA_LIT>InstrInfo :: MO_NONE ) { PtrHi = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { PtrHi = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , Offset + <NUM_LIT> , GAFlags + <NUM_LIT> ) ;


<s> O << RI . get ( MO . getReg ( ) ) . AsmName ; return ; case MachineOperand :: MO_Immediate : llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ExternalSymbol : O << MO . getSymbolName ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << Mang -> getMangledName ( MO . getGlobal ( ) ) ; return ; case MachineOperand :: MO_JumpTableIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; default :

O << <STR_LIT> << MO . getType ( ) << <STR_LIT> ;


<s> if ( isa < PointerType > ( Ty ) && AS == <STR_LIT> ) { return false ; } if ( Offs < <NUM_LIT> ) Offs = - Offs ; if ( AM . BaseGV == <NUM_LIT> && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isUInt < <NUM_LIT> > ( Offs ) ) { return true ; } return false ;


<s> static void init_alignment_context ( struct alignment_context * ac , rtx mem , enum machine_mode mode ) { ac -> shift = GEN_INT ( GET_MODE_SIZE ( SImode ) - GET_MODE_SIZE ( mode ) ) ; ac -> aligned = ( MEM_ALIGN ( mem ) >= GET_MODE_BITSIZE ( SImode ) ) ; if ( ac -> aligned ) ac -> memsi = adjust_address ( mem , SImode , <NUM_LIT> ) ; else { rtx byteoffset , addr , align ; addr = force_reg ( Pmode , XEXP ( mem , <NUM_LIT> ) ) ;

align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - GET_MODE_SIZE ( SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ;


<s> static bool arc_decl_anon_ns_mem_p ( const_tree decl ) { while ( <NUM_LIT> ) { if ( decl == NULL_TREE || decl == error_mark_node ) return false ;

if ( TREE_CODE ( decl ) == NAMESPACE_DECL && DECL_NAME ( decl ) == NULL_TREE ) return true ;


<s> if ( ! type ) return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode ;

if ( ! s390_single_field_struct_p ( REAL_TYPE , type , false ) ) return false ;


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ;


<s> if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - <NUM_LIT> ) ;

return TargetLowering :: getSafeStackPointerLocation ( IRB ) ;


<s> case <STR_LIT> ## <NUM_LIT> ## SUFFIX : \ case <STR_LIT> ## <NUM_LIT> ## SUFFIX : \ case <STR_LIT> ## <NUM_LIT> ## SUFFIX : \ case <STR_LIT> ## <NUM_LIT> ## SUFFIX : LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , rr ) \ LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , rr_REV ) \ LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , rm ) \ LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , mr ) \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : LLVM_EXPAND_ADC_SBB_INSTR ( ADC ) return FlagArithMnemonic :: ADC ; LLVM_EXPAND_ADC_SBB_INSTR ( SBB ) return FlagArithMnemonic :: SBB ;

LLVM_EXPAND_INSTR_SIZES ( RCL , rCL ) LLVM_EXPAND_INSTR_SIZES ( RCL , r1 ) LLVM_EXPAND_INSTR_SIZES ( RCL , ri ) return FlagArithMnemonic :: RCL ;


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ;


<s> void crx_function_arg_advance ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ATTRIBUTE_UNUSED ) { int l = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; if ( ! last_parm_in_reg ) return ; if ( targetm . calls . must_pass_in_stack ( mode , type ) || ( cum -> ints < <NUM_LIT> ) ) return ; if ( mode == SImode || mode == HImode || mode == QImode || mode == DImode ) { if ( l <= <NUM_LIT> ) cum -> ints += <NUM_LIT> ; else cum -> ints += l ; } else if ( mode == SFmode || mode == DFmode ) cum -> ints += l ;


<s> bool isLegalSMRDEncodedSignedOffset ( const MCSubtargetInfo & ST , int64_t EncodedOffset , bool IsBuffer ) { return ! IsBuffer && hasSMRDSignedImmOffset ( ST ) && isInt < <NUM_LIT> > ( EncodedOffset ) ;


<s> static unsigned Copy<ISA_LIT>64ByValRegs ( MachineFunction & MF , SDValue Chain , DebugLoc dl , std :: vector < SDValue > & OutChains , SelectionDAG & DAG , const CCValAssign & VA , const <STR_LIT> & Flags , MachineFrameInfo * MFI , bool IsRegLoc , SmallVectorImpl < SDValue > & InVals , <ISA_LIT>FunctionInfo * <ISA_LIT>FI , EVT PtrTy , const Argument * FuncArg ) { const uint16_t * Reg = <ISA_LIT>64IntRegs + <NUM_LIT> ; int FOOffset ; if ( IsRegLoc ) { Reg = std :: find ( <ISA_LIT>64IntRegs , <ISA_LIT>64IntRegs + <NUM_LIT> , VA . getLocReg ( ) ) ; FOOffset = ( Reg - <ISA_LIT>64IntRegs ) * <NUM_LIT> - <NUM_LIT> * <NUM_LIT> ; } else FOOffset = VA . getLocMemOffset ( ) ; unsigned NumRegs = ( Flags . getByValSize ( ) + <NUM_LIT> ) / <NUM_LIT> ; unsigned LastFI = MFI -> CreateFixedObject ( NumRegs * <NUM_LIT> , FOOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( LastFI , PtrTy ) ; InVals . push_back ( FIN ) ; for ( unsigned I = <NUM_LIT> ; ( Reg != <ISA_LIT>64IntRegs + <NUM_LIT> ) && ( I < NumRegs ) ; ++ Reg , ++ I ) { unsigned VReg = AddLiveIn ( MF , * Reg , & <STR_LIT> ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , FIN , DAG . getConstant ( I * <NUM_LIT> , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , dl , DAG . getRegister ( VReg , <STR_LIT> ) , StorePtr , MachinePointerInfo ( FuncArg , I * <NUM_LIT> ) , false , false , <NUM_LIT> ) ;


<s> Target & getThe<ISA_LIT>Target ( ) {


<s> ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o , <NUM_LIT> ) ; return ret ;


<s> return LDSMisalignedBug && ! EnableCuMode ;


<s> case <STR_LIT> : Reloc = <STR_LIT> ; useGOT = true ; break ; case <STR_LIT> : case <STR_LIT> : Reloc = <STR_LIT> ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; abort ( ) ; } if ( MO . isGlobal ( ) ) MCE . addRelocation ( MachineRelocation :: getGV ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getGlobal ( ) , Offset , isa < Function > ( MO . getGlobal ( ) ) , useGOT ) ) ; else if ( MO . isSymbol ( ) ) MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getSymbolName ( ) , Offset , true ) ) ;

else MCE . addRelocation ( MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , MO . getIndex ( ) , Offset ) ) ;


<s> void printHBROperand ( const MachineInstr * MI , unsigned OpNo ) { O << <STR_LIT> ;


<s> if ( this -> Options . TLSSize == <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; }


<s> const DataLayout & DL = getDataLayout ( ) ; Type * ETy = GVar -> getValueType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( GVar -> getType ( ) -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) DL . getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isFloatingPointTy ( ) || ETy -> isIntegerTy ( ) || ETy -> isPointerTy ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; getSymbol ( GVar ) -> print ( O , MAI ) ; return ;


initialize<ISA_LIT>UseNativeCallsPass ( * PR ) ;


<s> const <ISA_LIT>Z80Subtarget * <ISA_LIT>Z80TargetMachine :: getSubtargetImpl ( const Function & ) const {


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>_32Target ) ;

RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( The<ISA_LIT>_64Target ) ;


<s> bool isAISrc_512V2B16 ( ) const { return isAISrc_512B16 ( ) ;


<s> tmpInst . setOpcode ( Opcode ) ; tmpInst . addOperand ( MCOperand :: createReg ( Reg0 ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( Reg1 ) ) ; tmpInst . addOperand ( Op2 ) ; tmpInst . setLoc ( IDLoc ) ; Instructions . push_back ( tmpInst ) ;


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ;

return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ;


<s> if ( Cond [ <NUM_LIT> ] . getImm ( ) ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; } else { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; } if ( ! FBB ) return <NUM_LIT> ;

BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> SDValue Src = N0 ; while ( ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) && Src . getOperand ( <NUM_LIT> ) -> hasOneUse ( ) ) Src = Src . getOperand ( <NUM_LIT> ) ; <STR_LIT> <ISA_LIT>CC = <STR_LIT> ; if ( isBitwiseNot ( Src ) ) { Src = Src . getOperand ( <NUM_LIT> ) ; <ISA_LIT>CC = <STR_LIT> ; } if ( Src . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) { SDValue BitNo = Src . getOperand ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; if ( isBitwiseNot ( Src ) ) { Src = Src . getOperand ( <NUM_LIT> ) ; <ISA_LIT>CC = <ISA_LIT>CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } if ( SDValue BT = getBT ( Src , BitNo , dl , DAG ) ) return DAG . getZExtOrTrunc ( getSETCC ( <ISA_LIT>CC , BT , dl , DAG ) , dl , VT ) ; } } if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; auto GetDemandedMasks = [ & ] ( SDValue Op ) { APInt UndefElts ; SmallVector < APInt > EltBits ; int NumElts = VT . getVectorNumElements ( ) ; int EltSizeInBits = VT . getScalarSizeInBits ( ) ; APInt DemandedBits = APInt :: getAllOnes ( EltSizeInBits ) ; APInt DemandedElts = APInt :: getAllOnes ( NumElts ) ; if ( getTargetConstantBitsFromNode ( Op , EltSizeInBits , UndefElts , EltBits ) ) { DemandedBits . clearAllBits ( ) ; DemandedElts . clearAllBits ( ) ; for ( int I = <NUM_LIT> ; I != NumElts ; ++ I ) if ( ! EltBits [ I ] . isZero ( ) ) { DemandedBits |= EltBits [ I ] ; DemandedElts . setBit ( I ) ; } } return std :: make_pair ( DemandedBits , DemandedElts ) ; } ; std :: pair < APInt , APInt > Demand0 = GetDemandedMasks ( N1 ) ; std :: pair < APInt , APInt > Demand1 = GetDemandedMasks ( N0 ) ; if ( TLI . SimplifyDemandedVectorElts ( N0 , Demand0 . second , DCI ) || TLI . SimplifyDemandedVectorElts ( N1 , Demand1 . second , DCI ) || TLI . SimplifyDemandedBits ( N0 , Demand0 . first , Demand0 . second , DCI ) || TLI . SimplifyDemandedBits ( N1 , Demand1 . first , Demand1 . second , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } SDValue NewN0 = TLI . SimplifyMultipleUseDemandedBits ( N0 , Demand0 . first , Demand0 . second , DAG ) ;

SDValue NewN1 = TLI . SimplifyMultipleUseDemandedBits ( N1 , Demand1 . first , Demand1 . second , DAG ) ;


<s> const char * <ISA_LIT>DarwinTargetAsmInfo :: getEHGlobalPrefix ( ) const { const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( Subtarget -> getDarwinVers ( ) > <NUM_LIT> ) return PrivateGlobalPrefix ;


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return ( poly8x16_t ) __builtin_aarch64_tbl3v16qi ( __o , ( int8x16_t ) idx ) ;


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {

const MachineOperand & MO = MI -> getOperand ( i ) ;


<s> case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Identifier : if ( getParser ( ) . parseExpression ( Res ) ) return MatchOperand_ParseFail ; break ; }

Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ;


<s> __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ;

b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ;


<s> break ; default : llvm_unreachable ( <STR_LIT> ) ; }

return ( Kind == k_Register && Reg . Kind == RK ) && <ISA_LIT>MCRegisterClasses [ Class ] . contains ( getReg ( ) ) ;


<s> case AtomicOrdering :: SequentiallyConsistent : if ( ! Inst -> hasAtomicStore ( ) ) return nullptr ; return Builder . CreateFence ( AtomicOrdering :: SequentiallyConsistent ) ; } llvm_unreachable ( <STR_LIT> ) ;


<s> switch ( ID ) { default : return false ; case <STR_LIT> : return true ; }


<s> Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue CPIdx = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ;

unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ;


<s> bool riscv_can_use_return_insn ( void ) {

return ( reload_completed && cfun -> machine -> frame . total_size == <NUM_LIT> && ! cfun -> machine -> interrupt_handler_p ) ;


<s> const <ISA_LIT>InstrInfo * <ISA_LIT>InstrInfo :: create ( <ISA_LIT>Subtarget & STI ) { return llvm :: create<ISA_LIT>SEInstrInfo ( STI ) ;


<s> O << '(' ; printOperand ( MI , opNum , O ) ; O << ')' ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectStoreLane ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( St ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmParser ( ) {

RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> auto Features = computeAvailableFeatures ( STI . getFeatureBits ( ) ) ; verifyInstructionPredicates ( MI , Features ) ; EndianWriter OSE ( OS , <STR_LIT> ) ; const uint64_t OpCode = getBinaryCodeForInstr ( MI , Fixups , STI ) ; const uint32_t NumWords = MI . getNumOperands ( ) + <NUM_LIT> ; const uint32_t FirstWord = ( NumWords << <NUM_LIT> ) | OpCode ; OSE . write < uint32_t > ( FirstWord ) ;

if ( hasType ( MI , MCII , MRI ) ) emitTypedInstrOperands ( MI , OSE ) ;


<s> case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , numbers :: ln2f ) ; case <STR_LIT> : return LowerFLOG ( Op , DAG , numbers :: ln2f / numbers :: ln10f ) ; case <STR_LIT> : return lowerFEXP ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerCTLZ_CTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; } return Op ;


<s> unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm ( ) ) { printImm ( MI , OpNo , STI , O ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;

Op . getExpr ( ) -> print ( O , & MAI ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else {

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> static DecodeStatus s11_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> <STR_LIT> CC = StringSwitch < <STR_LIT> > ( Cond . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> :: COND_EQ ) . Case ( <STR_LIT> , <STR_LIT> :: COND_NE ) . Case ( <STR_LIT> , <STR_LIT> :: COND_GT ) . Case ( <STR_LIT> , <STR_LIT> :: COND_GT ) . Case ( <STR_LIT> , <STR_LIT> :: COND_LE ) . Case ( <STR_LIT> , <STR_LIT> :: COND_LE ) . Case ( <STR_LIT> , <STR_LIT> :: COND_GE ) . Case ( <STR_LIT> , <STR_LIT> :: COND_LT ) . Case ( <STR_LIT> , <STR_LIT> :: COND_GT ) . Default ( <STR_LIT> :: COND_INVAL ) ; return CC ;


<s> Builder . SetCurrentDebugLocation ( I . getDebugLoc ( ) ) ; Type * I32Ty = Builder . getInt32Ty ( ) ; Type * PT = PointerType :: get ( I32Ty , I . getPointerAddressSpace ( ) ) ; Value * BitCast = Builder . CreateBitCast ( I . getPointerOperand ( ) , PT ) ; Value * WidenLoad = Builder . CreateLoad ( BitCast ) ; int TySize = Mod -> getDataLayout ( ) . getTypeSizeInBits ( I . getType ( ) ) ; Type * IntNTy = Builder . getIntNTy ( TySize ) ;

Value * ValTrunc = Builder . CreateTrunc ( WidenLoad , IntNTy ) ;


if ( Subtarget -> isTargetWin64 ( ) ) return RetCC_<ISA_LIT>_Win64_C ;


<s> return CDP ? slice ( insn , <NUM_LIT> , <NUM_LIT> ) : slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> return BuildMI ( * MBB , I , DL , get ( AMDGPU :: <ISA_LIT>_INDIRECT_SRC ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg ) . addImm ( <NUM_LIT> ) ;


<s> SDValue Trmp = Op . getOperand ( <NUM_LIT> ) ; SDValue FPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue Nest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ;

Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ;


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo * TII = STM . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo * RI = & TII -> getRegisterInfo ( ) ; unsigned ExtraSGPRs = IsaInfo :: getNumExtraSGPRs ( & STM , ProgInfo . VCCUsed , ProgInfo . FlatUsed ) ; if ( STM . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS && ! STM . hasSGPRInitBug ( ) ) { unsigned MaxAddressableNumSGPRs = STM . getAddressableNumSGPRs ( ) ; if ( ProgInfo . NumSGPR > MaxAddressableNumSGPRs ) { LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; DiagnosticInfoResourceLimit Diag ( MF . getFunction ( ) , <STR_LIT> , ProgInfo . NumSGPR , DS_Error , DK_ResourceLimit , MaxAddressableNumSGPRs ) ; Ctx . diagnose ( Diag ) ; ProgInfo . NumSGPR = MaxAddressableNumSGPRs - <NUM_LIT> ; } } ProgInfo . NumSGPR += ExtraSGPRs ; unsigned WaveDispatchNumSGPR = <NUM_LIT> , WaveDispatchNumVGPR = <NUM_LIT> ; for ( auto & Arg : MF . getFunction ( ) . args ( ) ) { unsigned NumRegs = ( Arg . getType ( ) -> getPrimitiveSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; if ( Arg . hasAttribute ( Attribute :: InReg ) ) WaveDispatchNumSGPR += NumRegs ; else WaveDispatchNumVGPR += NumRegs ; } ProgInfo . NumSGPR = std :: max ( ProgInfo . NumSGPR , WaveDispatchNumSGPR ) ; ProgInfo . NumVGPR = std :: max ( ProgInfo . NumVGPR , WaveDispatchNumVGPR ) ; ProgInfo . NumSGPRsForWavesPerEU = std :: max ( std :: max ( ProgInfo . NumSGPR , <NUM_LIT> ) , STM . getMinNumSGPRs ( MFI -> getMaxWavesPerEU ( ) ) ) ; ProgInfo . NumVGPRsForWavesPerEU = std :: max ( std :: max ( ProgInfo . NumVGPR , <NUM_LIT> ) , STM . getMinNumVGPRs ( MFI -> getMaxWavesPerEU ( ) ) ) ; if ( STM . getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS || STM . hasSGPRInitBug ( ) ) { unsigned MaxAddressableNumSGPRs = STM . getAddressableNumSGPRs ( ) ; if ( ProgInfo . NumSGPR > MaxAddressableNumSGPRs ) { LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; DiagnosticInfoResourceLimit Diag ( MF . getFunction ( ) , <STR_LIT> , ProgInfo . NumSGPR , DS_Error , DK_ResourceLimit , MaxAddressableNumSGPRs ) ; Ctx . diagnose ( Diag ) ; ProgInfo . NumSGPR = MaxAddressableNumSGPRs ; ProgInfo . NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs ; } } if ( STM . hasSGPRInitBug ( ) ) { ProgInfo . NumSGPR = <STR_LIT> :: FIXED_NUM_SGPRS_FOR_INIT_BUG ; ProgInfo . NumSGPRsForWavesPerEU = <STR_LIT> :: FIXED_NUM_SGPRS_FOR_INIT_BUG ; } if ( MFI -> getNumUserSGPRs ( ) > STM . getMaxNumUserSGPRs ( ) ) { LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; DiagnosticInfoResourceLimit Diag ( MF . getFunction ( ) , <STR_LIT> , MFI -> getNumUserSGPRs ( ) , DS_Error ) ;


<s> if ( MO . isReg ( ) && MO . isUse ( ) && MO . isKill ( ) && getRegisterInfo ( ) . regsOverlap ( MO . getReg ( ) , RegNo ) ) MO . setIsKill ( false ) ; } ; int UseIndex = EndMI -> findRegisterUseOperandIdx ( RegNo , false , & getRegisterInfo ( ) ) ; if ( UseIndex != - <NUM_LIT> ) { EndMI -> getOperand ( UseIndex ) . setIsKill ( true ) ; IsKillSet = true ; for ( int i = <NUM_LIT> , e = EndMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( i != UseIndex ) clearOperandKillInfo ( * EndMI , i ) ; } MachineBasicBlock :: reverse_iterator It = * EndMI ; MachineBasicBlock :: reverse_iterator E = EndMI -> getParent ( ) -> rend ( ) ; It ++ ; MachineOperand * MO = nullptr ; for ( ; It != E ; ++ It ) {

if ( It -> isDebugInstr ( ) || It -> isPosition ( ) ) continue ;


<s> if ( CondSrc -> getOpcode ( ) == <STR_LIT> ) Cond = CondSrc -> getOperand ( <NUM_LIT> ) ; } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ;

if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return SDValue ( ) ;


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; SDValue MulOp = N -> getOperand ( <NUM_LIT> ) ; SDValue Phi = N -> getOperand ( <NUM_LIT> ) ; if ( MulOp . getOpcode ( ) != <STR_LIT> ) std :: swap ( MulOp , Phi ) ; if ( MulOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ShrinkMode Mode ; if ( ! canReduceVMulWidth ( MulOp . getNode ( ) , DAG , Mode ) || Mode == MULU16 ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . useBWIRegs ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ;

SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ;


<s> static bool aarch64_frame_pointer_required ( void ) { if ( flag_omit_leaf_frame_pointer && ( ! crtl -> is_leaf || df_regs_ever_live_p ( LR_REGNUM ) ) ) return true ; return false ;


<s> const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) -> getObjectSize ( FrameIdx ) >= RC -> getSize ( ) && <STR_LIT> ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , <NUM_LIT> ) ; bool isAligned = ( MF . getTarget ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ;

unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , Subtarget ) ;


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNo + <NUM_LIT> ) ;

O << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << ( int ) MO2 . getImm ( ) ;


<s> } if ( IsCRField ) { <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; }


<s> break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; case <STR_LIT> : MO . setImm ( <STR_LIT> ) ; break ; default : return true ; }

MachineOperand & MO2 = Cond [ <NUM_LIT> ] ;


PRINT_FIELD ( OS , <STR_LIT> , KD , compute_pgm_rsrc1 , amdhsa :: COMPUTE_PGM_RSRC1_WGP_MODE ) ;


<s> if ( USE_HIDDEN_LINKONCE ) sprintf ( name , <STR_LIT> ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , <STR_LIT> , <NUM_LIT> ) ;


<s> static bool rs6000_legitimate_combined_insn ( rtx_insn * insn ) { int icode = INSN_CODE ( insn ) ; if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_ctrsi_internal1 || icode == CODE_FOR_ctrdi_internal1 || icode == CODE_FOR_ctrsi_internal2 || icode == CODE_FOR_ctrdi_internal2 || icode == CODE_FOR_ctrsi_internal3 || icode == CODE_FOR_ctrdi_internal3 || icode == CODE_FOR_ctrsi_internal4 || icode == CODE_FOR_ctrdi_internal4 ) ) return false ;


<s> bool isLittle ( ) const { return IsLittle ;


<s> return decodeRegisterClass ( Inst , RegNo , GP0Regs ) ;


<s> bool <ISA_LIT>FrameLowering :: expandStoreInt ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const { MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Opc = MI -> getOpcode ( ) ;

Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> static DecodeStatus s3_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) {

signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> SDValue Read = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Read . getValue ( <NUM_LIT> ) , Read . getValue ( <NUM_LIT> ) ) ) ; Results . push_back ( Read . getOperand ( <NUM_LIT> ) ) ;


<s> if ( ! Instr ) return false ; if ( Index >= Instr -> getNumOperands ( ) ) return false ; const MachineOperand & Operand = Instr -> getOperand ( Index ) ; if ( ! Operand . isImm ( ) ) return false ; if ( ImmValue != Operand . getImm ( ) ) return false ;


<s> if ( STI . isTargetXPLINK64 ( ) ) return std :: make_unique < <ISA_LIT>XPLINKFrameLowering > ( ) ;

return std :: make_unique < <ISA_LIT>ELFFrameLowering > ( ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) , Subtarget ( & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> MCOp = lowerSymbolOperand ( MO , Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = lowerSymbolOperand ( MO , Printer . GetJTISymbol ( MO . getIndex ( ) ) ) ;


<s> if ( ! Subtarget . isTargetLinux ( ) ) return false ; if ( Subtarget . is64Bit ( ) ) { Offset = <NUM_LIT> ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = <NUM_LIT> ; else AddressSpace = <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { if ( Cond . size ( ) != <NUM_LIT> ) { return true ; } if ( Cond [ <NUM_LIT> ] . isImm ( ) ) {

Cond [ <NUM_LIT> ] . setImm ( - Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> if ( MachineInstr * DefMI = MRI -> getVRegDef ( Require . getAVLReg ( ) ) ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ;

if ( DefInfo . hasSameAVL ( CurInfo ) && DefInfo . hasSameVTYPE ( CurInfo ) ) return false ;


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; O << TRI -> getAsmName ( Reg ) ; O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << <STR_LIT> ;

assert ( MO2 . isImm ( ) && <STR_LIT> ) ;


<s> } else llvm_unreachable ( <STR_LIT> ) ; } else { SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * TLI , Ty , vtparts ) ; unsigned idx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = vtparts . size ( ) ; i != e ; ++ i ) { unsigned elems = <NUM_LIT> ; EVT elemtype = vtparts [ i ] ; if ( vtparts [ i ] . isVector ( ) ) { elems = vtparts [ i ] . getVectorNumElements ( ) ; elemtype = vtparts [ i ] . getVectorElementType ( ) ; } for ( unsigned j = <NUM_LIT> , je = elems ; j != je ; ++ j ) { unsigned sz = elemtype . getSizeInBits ( ) ; if ( elemtype . isInteger ( ) && ( sz < <NUM_LIT> ) ) sz = <NUM_LIT> ; O << <STR_LIT> << sz << <STR_LIT> << idx ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ idx ; } if ( i < e - <NUM_LIT> ) O << <STR_LIT> ; } } O << <STR_LIT> ;


<s> if ( ! REG_P ( tem1 ) && GET_CODE ( tem1 ) != MULT ) tem1 = tem2 , tem2 = XEXP ( x , <NUM_LIT> ) ; gcc_assert ( REG_P ( tem1 ) || GET_CODE ( tem1 ) == MULT ) ; if ( ( GET_CODE ( tem1 ) == MULT && cris_biap_index_p ( tem1 , false ) ) || REG_P ( tem2 ) ) return <NUM_LIT> / <NUM_LIT> ; if ( CONST_INT_P ( tem2 ) && INTVAL ( tem2 ) < <NUM_LIT> && INTVAL ( tem2 ) >= - <NUM_LIT> ) return <NUM_LIT> / <NUM_LIT> ; if ( satisfies_constraint_L ( tem2 ) ) return ( <NUM_LIT> + <NUM_LIT> ) / <NUM_LIT> ; if ( CONSTANT_P ( tem2 ) ) return ( <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ) / <NUM_LIT> ; return ( <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ) / <NUM_LIT> ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalizeOps ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { auto * Ld = cast < LoadSDNode > ( In ) ; if ( Ld -> isSimple ( ) ) { MVT SVT = In . getSimpleValueType ( ) . getVectorElementType ( ) ; <STR_LIT> Ext = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT MemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , VT . getVectorNumElements ( ) ) ; if ( TLI . isLoadExtLegal ( Ext , VT , MemVT ) ) { SDValue Load = DAG . getExtLoad ( Ext , SDLoc ( N ) , VT , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MemVT , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } }

if ( Subtarget . hasAVX ( ) && N -> getOpcode ( ) != <STR_LIT> ) {


<s> Value = ( Value << ( <NUM_LIT> - <NUM_LIT> ) ) >> ( <NUM_LIT> - <NUM_LIT> ) ; O << ( int ) Value ;


<s> bool <ISA_LIT>TargetLowering :: isCheapAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const {

if ( SrcAS == <ISA_LIT>AS :: FLAT_ADDRESS ) return true ;


<s> if ( Type -> getOpcode ( ) == TypeOpcode ) return true ; if ( Type -> getOpcode ( ) == <STR_LIT> ) { Register ScalarTypeVReg = Type -> getOperand ( <NUM_LIT> ) . getReg ( ) ; <ISA_LIT>Type * ScalarType = get<ISA_LIT>TypeForVReg ( ScalarTypeVReg ) ;

return ScalarType -> getOpcode ( ) == TypeOpcode ;


<s> void <ISA_LIT>Subtarget :: initializeEnvironment ( ) {


<s> auto Res = std :: make_unique < <ISA_LIT>Operand > ( OpKind :: WR , StartLoc , EndLoc ) ; Res -> MovDualGroup . Val = Val ; Res -> MovDualGroup . Name = Name ; return Res ;


<s> default : return SDValue ( ) ; case <STR_LIT> : { EVT VT = Op . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; auto & Context = MF . getMMI ( ) . getContext ( ) ; MCSymbol * S = Context . getOrCreateSymbol ( Twine ( <STR_LIT> ) + Twine ( MF . getFunctionNumber ( ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getMCSymbol ( S , PtrVT ) ) ; } case <STR_LIT> : {


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> getOperation ( ) == AtomicRMWInst :: Xchg ) { return AtomicExpansionKind :: None ; }


<s> DebugLoc dl = Op . getDebugLoc ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , DAG . getConstant ( FPCondCCodeToFCC ( CC ) , <STR_LIT> ) ) ;


<s> void MemIntrinsicsHandler :: AddToLazyDeletionSet ( User * Elm ) {

if ( DeletionSet . find ( Elm ) == DeletionSet . end ( ) ) DeletionSet . insert ( Elm ) ;


<s> if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == <STR_LIT> || Ty == <STR_LIT> ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> && Ty != <STR_LIT> ) return false ; if ( Subtarget -> isLittle ( ) ) { if ( Fast ) * Fast = true ; return true ; } else { if ( Ty == <STR_LIT> || ( ( Ty == <STR_LIT> || Ty == <STR_LIT> ) && Alignment >= <NUM_LIT> ) || ( ( Ty == <STR_LIT> || Ty == <STR_LIT> ) && Alignment >= <NUM_LIT> ) ) {


<s> RegisterRef ( const MachineOperand & MO ) : Reg ( MO . getReg ( ) ) , Sub ( MO . getSubReg ( ) ) {


<s> SDValue Chain = DAG . getEntryNode ( ) ; Lo = DAG . getStore ( Chain , DL , Lo , StackSlot , MPI , Align ( <NUM_LIT> ) ) ; SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , TypeSize :: Fixed ( <NUM_LIT> ) , DL ) ; Hi = DAG . getStore ( Chain , DL , Hi , OffsetSlot , MPI . getWithOffset ( <NUM_LIT> ) , Align ( <NUM_LIT> ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDVTList VTs = DAG . getVTList ( { VT , <STR_LIT> } ) ; SDValue IntID = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , IntID , StackSlot , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , VL } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , <STR_LIT> , MPI , Align ( <NUM_LIT> ) , MachineMemOperand :: MOLoad ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , VT , Value , Value ) ;


<s> if ( CC == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_RegMask ; else return CSR_<ISA_LIT>_AAPCS_RegMask ;


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) == <STR_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . useBWIRegs ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX ( ) ) RegSize = <NUM_LIT> ; if ( VT . getSizeInBits ( ) / <NUM_LIT> > RegSize ) return SDValue ( ) ; SDValue AbsOp = N -> getOperand ( <NUM_LIT> ) ; SDValue OtherOp = N -> getOperand ( <NUM_LIT> ) ; if ( AbsOp . getOpcode ( ) != <STR_LIT> ) std :: swap ( AbsOp , OtherOp ) ; if ( AbsOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SadOp0 , SadOp1 ; if ( ! detectZextAbsDiff ( AbsOp , SadOp0 , SadOp1 ) ) return SDValue ( ) ; SDValue Sad = createPSADBW ( DAG , SadOp0 , SadOp1 , DL , Subtarget ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , Sad . getValueSizeInBits ( ) / <NUM_LIT> ) ; if ( VT . getSizeInBits ( ) >= ResVT . getSizeInBits ( ) ) Sad = DAG . getNode ( <STR_LIT> , DL , ResVT , Sad ) ; else Sad = DAG . getNode ( <STR_LIT> , DL , VT , Sad ) ; if ( VT . getSizeInBits ( ) > ResVT . getSizeInBits ( ) ) { SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; Sad = DAG . getNode ( <STR_LIT> , DL , VT , Zero , Sad , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } SDNodeFlags Flags ; Flags . setVectorReduction ( true ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Sad , OtherOp , Flags ) ;


<s> inline int vec_all_nlt ( vector float a1 , vector float a2 ) {


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) != REG && ! legitimate_constant_pool_address_p ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , GET_MODE ( operands [ <NUM_LIT> ] ) , false ) ) operands [ <NUM_LIT> ] = replace_equiv_address ( operands [ <NUM_LIT> ] , copy_addr_to_reg ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ;


<s> break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 ) ;


<s> bool SelectAddrModeIndexed7S16 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectAddrModeIndexed7S ( N , <NUM_LIT> , Base , OffImm ) ;


<s> SDLoc DL ( Op ) ; SDValue Chain = Op -> getOperand ( <NUM_LIT> ) ; SDValue SysRegNo = DAG . getTargetConstant ( <STR_LIT> ( <STR_LIT> ) -> Encoding , DL , XLenVT ) ; SDVTList VTs = DAG . getVTList ( XLenVT , <STR_LIT> ) ; SDValue RM = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , SysRegNo ) ;

static const int Table = ( int ( RoundingMode :: NearestTiesToEven ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardZero ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardNegative ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardPositive ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: NearestTiesToAway ) << <NUM_LIT> * <STR_LIT> ) ;


<s> <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc Loc = MI . getDebugLoc ( ) ;


<s> SET_HARD_REG_BIT ( in , base + <NUM_LIT> ) ; SET_HARD_REG_BIT ( in , base + <NUM_LIT> ) ;


<s> N = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ! <STR_LIT> ( N ) ) return false ; if ( LD ) * LD = cast < LoadSDNode > ( N ) ; return true ;


<s> <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AFI -> isThumb2Function ( ) ; } return true ;


<s> unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) , M -> getOperand ( <NUM_LIT> ) } ; return DAG . getMemIntrinsicNode ( Opc , SDLoc ( Op ) , M -> getVTList ( ) , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Ops [ ] = { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Opc = ( IntrID == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EVT VT = Op . getValueType ( ) ; EVT IntVT = VT . changeTypeToInteger ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( MFI -> getBufferPSV ( ) ) , MachineMemOperand :: MOLoad , VT . getStoreSize ( ) , VT . getStoreSize ( ) ) ;

return DAG . getMemIntrinsicNode ( Opc , DL , Op -> getVTList ( ) , Ops , IntVT , MMO ) ;


<s> void <ISA_LIT>VectorLoopCarriedReuse :: findLoopCarriedDeps ( ) { BasicBlock * BB = CurLoop -> getHeader ( ) ; for ( auto I = BB -> begin ( ) , E = BB -> end ( ) ; I != E && isa < PHINode > ( I ) ; ++ I ) { auto * PN = cast < PHINode > ( I ) ; if ( ! isa < VectorType > ( PN -> getType ( ) ) ) continue ; DepChain * D = new DepChain ( ) ; findDepChainFromPHI ( PN , * D ) ; if ( D -> size ( ) != <NUM_LIT> ) Dependences . insert ( D ) ; else delete D ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Dependences . size ( ) << <STR_LIT> ) ; LLVM_DEBUG ( for ( const DepChain * D : Dependences ) dbgs ( ) << * D << <STR_LIT> ; ) ;


<s> return ggc_cleared_alloc < machine_function > ( ) ;


<s> if ( CC == CallingConv :: Fast && GuaranteedTailCallOpt ) return false ; if ( F . isVarArg ( ) ) return false ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) . getRetAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = FastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ; SrcVT = <STR_LIT> ; } unsigned Op = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ? <STR_LIT> : <STR_LIT> ;

SrcReg = FastEmit_r ( SrcVT . getSimpleVT ( ) , DstVT . getSimpleVT ( ) , Op , SrcReg , false ) ;


<s> unsigned MaxReg = MaxNumVGPRs - NumRegs + <STR_LIT> ; for ( unsigned Reg = <STR_LIT> ; Reg <= MaxReg ; ++ Reg ) { if ( ! canAssign ( Reg , NumRegs ) ) continue ; if ( tryAssignRegisters ( Intervals , Reg ) ) return true ; }


<s>
void
<ISA_LIT>InstPrinter
::
printOpConstantVarOps
(
const
MCInst
*
MI
,
unsigned
StartIndex
,
raw_ostream
&
O
)
{
O
<<
' '
;
if
(
MI
->
getNumOperands
(
)
StartIndex
==
<NUM_LIT>
)
{
uint64_t
Imm
=
MI
->
getOperand
(
StartIndex
)
.
getImm
(
)
;
Imm
|=
(
MI
->
getOperand
(
StartIndex
+
<NUM_LIT>
)
.
getImm
(
)
<<
<NUM_LIT>
)
;
O
<<
Imm
;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( Commuted ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << OpNo << <STR_LIT> << * MI ) ; FoldList . emplace_back ( MI , OpNo , FoldOp , Commuted , ShrinkOp ) ;


<s> return ( long long ) __builtin_ia32_cvtsd2si64 ( ( __v2df ) __A ) ;


<s> if ( getSTI ( ) . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA ) { return Error ( getParser ( ) . getTok ( ) . getLoc ( ) , ( Twine ( HSAMD :: AssemblerDirectiveBegin ) + Twine ( <STR_LIT> <STR_LIT> ) ) . str ( ) ) ; } std :: string HSAMetadataString ; raw_string_ostream YamlStream ( HSAMetadataString ) ; getLexer ( ) . setSkipSpace ( false ) ; bool FoundEnd = false ; while ( ! getLexer ( ) . is ( AsmToken :: Eof ) ) { while ( getLexer ( ) . is ( AsmToken :: Space ) ) { YamlStream << getLexer ( ) . getTok ( ) . getString ( ) ; Lex ( ) ; } if ( getLexer ( ) . is ( AsmToken :: Identifier ) ) { StringRef ID = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( ID == <STR_LIT> :: AssemblerDirectiveEnd ) { Lex ( ) ; FoundEnd = true ;


<s> typedef float v8qi __attribute__ ( ( mode ( V8QI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MEXTR3 ( ( v8qi ) mm , ( v8qi ) mn ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB ) ; case <STR_LIT> : return emitBuildPairF64Pseudo ( MI , BB ) ; case <STR_LIT> : return emitSplitF64Pseudo ( MI , BB ) ;


<s> void GCNTTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) {

CommonTTI . getPeelingPreferences ( L , SE , PP ) ;


<s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; else if ( RC -> hasType ( <STR_LIT> ) || RC -> hasType ( <STR_LIT> ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ;


<s> inline void gt_pch_nx ( function_instance * , void ( * ) ( void * , void * ) , void * ) {


<s> } SrcC = decodeCField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , SrcC , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;


<s> ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , <NUM_LIT> + arm_reg0 ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , ops ) ;


<s> static void moxie_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) {

CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;


<s> printMemReference ( MI , OpNo , O ) ;


<s> while ( II != MBB . end ( ) && isPseudo ( II ) ) { II ++ ;


<s> assert ( ! Val == VRegs . empty ( ) && <STR_LIT> ) ; CallingConv :: ID CC = B . getMF ( ) . getFunction ( ) . getCallingConv ( ) ; const bool IsShader = <STR_LIT> ( CC ) ; const bool IsWaveEnd = ( IsShader && MFI -> returnsVoid ( ) ) || <STR_LIT> ( CC ) ; if ( IsWaveEnd ) { B . buildInstr ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; return true ; } auto const & ST = B . getMF ( ) . getSubtarget < GCNSubtarget > ( ) ; unsigned ReturnOpc = IsShader ? <STR_LIT> : <STR_LIT> ; auto Ret = B . buildInstrNoInsert ( ReturnOpc ) ; Register ReturnAddrVReg ; if ( ReturnOpc == <STR_LIT> ) { ReturnAddrVReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Ret . addUse ( ReturnAddrVReg ) ; } if ( ! lowerReturnVal ( B , Val , VRegs , Ret ) ) return false ; if ( ReturnOpc == <STR_LIT> ) { const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; Register LiveInReturn = MF . addLiveIn ( TRI -> getReturnAddressReg ( MF ) , & <STR_LIT> ) ;

B . buildCopy ( ReturnAddrVReg , LiveInReturn ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> <ISA_LIT>Bid ( ) : Bid ( <NUM_LIT> ) {


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeRI5Operand ( const MCInst * MI , unsigned Op , raw_ostream & O , unsigned Scale ) { const MCOperand & MO1 = MI -> getOperand ( Op ) ; const MCOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO3 . getReg ( ) ) O << <STR_LIT> << getRegisterName ( MO3 . getReg ( ) ) ; else if ( unsigned ImmOffs = MO2 . getImm ( ) ) O << <STR_LIT> << ImmOffs * Scale ;


<s> rtx sh_treg_combine :: touched_insn ( rtx i ) { m_touched_insns . push_back ( i ) ; return i ;


<s> if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ;

return addOffset ( MIB . addFrameIndex ( FI ) , Offset ) . addMemOperand ( MMO ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ;


<s> if ( TT . isOSBinFormatMachO ( ) ) return <STR_LIT> ; if ( LittleEndian ) return <STR_LIT> ;


<s> else if ( ThisVal > MaxVal ) ThisVal = MaxVal ; } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII -> get ( Opcode ) , Reg ) . addReg ( Reg ) . addImm ( ThisVal ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; NumBytes -= ThisVal ; }


<s> case <STR_LIT> :: tc_7f7f45f5 : case <STR_LIT> :: tc_9783714b : case <STR_LIT> :: tc_9e72dc89 : case <STR_LIT> :: tc_9edb7c77 : case <STR_LIT> :: tc_f0e8e832 : case <STR_LIT> :: tc_f7569068 : return true ; default : return false ;


<s> } MachineBasicBlock * Copy0MBB = F -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( BB ) ; F -> insert ( It , Copy0MBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; MachineInstr * LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV ; if ( ! LastCCRSUser -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateCCRKill ( LastCCRSUser , MBB , TRI ) ) { Copy0MBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , MBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; if ( CascadedCMOV ) { MBB -> addSuccessor ( Jcc1MBB ) ; Jcc1MBB -> addSuccessor ( Copy0MBB ) ; Jcc1MBB -> addSuccessor ( SinkMBB ) ; } else { MBB -> addSuccessor ( Copy0MBB ) ; } MBB -> addSuccessor ( SinkMBB ) ; unsigned Opc = <STR_LIT> ( CC ) ; BuildMI ( MBB , DL , TII -> get ( Opc ) ) . addMBB ( SinkMBB ) ; if ( CascadedCMOV ) { unsigned Opc2 = <STR_LIT> ( ( <STR_LIT> ) CascadedCMOV -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( Jcc1MBB , DL , TII -> get ( Opc2 ) ) . addMBB ( SinkMBB ) ; } Copy0MBB -> addSuccessor ( SinkMBB ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { Register DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

Register Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> explicit <ISA_LIT>AAResult ( const DataLayout & DL ) : AAResultBase ( ) , DL ( DL ) {