<s> if ( isMesaKernel ( MF ) ) return <NUM_LIT> ; if ( isAmdHsaOS ( ) && isOpenCLEnv ( ) ) return <NUM_LIT> ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __crc32q ( unsigned long long __C , unsigned long long __V ) {


<s> SDLoc DL ( Op ) ; SDValue Vl = Op . getOperand ( <NUM_LIT> ) ; SDValue ShiftAmt = Op . getOperand ( <NUM_LIT> ) ; if ( ShiftAmt . getOpcode ( ) != <STR_LIT> ) { return ExpandLibCall ( <STR_LIT> , Op , false , DAG ) ; } EVT VT = Vl . getValueType ( ) ; uint64_t ShAmt = cast < ConstantSDNode > ( ShiftAmt . getNode ( ) ) -> getZExtValue ( ) ;

for ( uint64_t i = <NUM_LIT> ; i < ShAmt ; i ++ ) {


<s> unsigned FirstEncoding = RI -> getEncodingValue ( FirstReg ) ; if ( FirstEncoding & <NUM_LIT> ) { Error ( S , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc M = getLoc ( ) ; if ( getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( M , <STR_LIT> ) ; return MatchOperand_ParseFail ; } getParser ( ) . Lex ( ) ; SMLoc E = getLoc ( ) ; int SecondReg = tryParseRegister ( ) ; if ( SecondReg == - <NUM_LIT> ) { return MatchOperand_ParseFail ; } if ( RI -> getEncodingValue ( SecondReg ) != FirstEncoding + <NUM_LIT> || ( isXReg && ! XRegClass . contains ( SecondReg ) ) || ( isWReg && ! WRegClass . contains ( SecondReg ) ) ) { Error ( E , <STR_LIT> <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> return Flag ? CC_<ISA_LIT>64_ELF_FIS : RetCC_<ISA_LIT>64_ELF_FIS ;


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ;

AU . addPreserved < MachineLoopInfo > ( ) ;


<s> if ( ST -> hasAVX ( ) ) { int Idx = FindInTable ( AVX1CostTable , array_lengthof ( AVX1CostTable ) , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX1CostTable [ Idx ] . Cost ; }

return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty ) ;


<s> case <STR_LIT> : return lowerAnd ( Op , DAG ) ; case <STR_LIT> : return lowerOr ( Op , DAG ) ; case <STR_LIT> : return lowerXor ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ;


<s> } else if ( flag_delayed_branch ) { sparc_leaf_function_p = crtl -> uses_only_leaf_regs = <NUM_LIT> ; int_arg_first = SPARC_INCOMING_INT_ARG_FIRST ; } else { sparc_leaf_function_p = crtl -> uses_only_leaf_regs = <NUM_LIT> ; int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST ; } if ( TARGET_ARCH64 && aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , int_arg_first + <NUM_LIT> ) ; else this_rtx = gen_rtx_REG ( Pmode , int_arg_first ) ; if ( delta ) { rtx delta_rtx = GEN_INT ( delta ) ; if ( ! SPARC_SIMM13_P ( delta ) ) { rtx scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( scratch , delta_rtx ) ; delta_rtx = scratch ; } emit_insn ( gen_add2_insn ( this_rtx , delta_rtx ) ) ; } if ( vcall_offset ) { rtx vcall_offset_rtx = GEN_INT ( vcall_offset ) ; rtx scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; gcc_assert ( vcall_offset < <NUM_LIT> ) ; emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( SPARC_SIMM13_P ( vcall_offset ) ) ; else if ( ! fixed_regs [ <NUM_LIT> ] && vcall_offset < - <NUM_LIT> ) { rtx scratch2 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( scratch2 , vcall_offset_rtx ) ; vcall_offset_rtx = scratch2 ; } else { rtx increment = GEN_INT ( - <NUM_LIT> ) ; while ( ! SPARC_SIMM13_P ( vcall_offset ) ) { emit_insn ( gen_add2_insn ( scratch , increment ) ) ; vcall_offset += <NUM_LIT> ; } vcall_offset_rtx = GEN_INT ( vcall_offset ) ; } emit_move_insn ( scratch , gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , scratch , vcall_offset_rtx ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( flag_delayed_branch ) { funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; } else { rtx spill_reg , seq , scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( flag_pic ) { spill_reg = gen_rtx_REG ( word_mode , <NUM_LIT> ) ;


<s> static bool isVINSERTIndex ( SDNode * N , unsigned vecWidth ) { assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ;

unsigned ElSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ;


<s> byval_iterator byval_end ( ) const { return ByValArgs . end ( ) ;


<s> VariantKind getKind ( ) const { return Kind ;


<s> rtx avr_eval_addr_attrib ( rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_ADDRESS ) ) { tree decl = SYMBOL_REF_DECL ( x ) ; tree attr = NULL_TREE ; if ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_IO ) { attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ;

if ( ! attr || ! TREE_VALUE ( attr ) ) attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ;


<s> static void sh_file_start ( void ) { default_file_start ( ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_ELF ) fprintf ( asm_out_file , <STR_LIT> , TEXT_SECTION_ASM_OP ) ; else data_section ( ) ; if ( TARGET_LITTLE_ENDIAN ) fputs ( <STR_LIT> , asm_out_file ) ; if ( ! TARGET_ELF ) { if ( TARGET_SHCOMPACT ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( TARGET_SHMEDIA ) fprintf ( asm_out_file , <STR_LIT> , TARGET_SHMEDIA64 ? <NUM_LIT> : <NUM_LIT> ) ; }


<s> switch ( Opcode ) { default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> Inst . addOperand ( MCOperand :: createImm ( getVectorIndex ( ) ) ) ;


<s> bool <ISA_LIT>ReplaceImageHandles :: findIndexForHandle ( MachineOperand & Op , MachineFunction & MF , unsigned & Idx ) { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; assert ( Op . isReg ( ) && <STR_LIT> ) ; MachineInstr & TexHandleDef = * MRI . getVRegDef ( Op . getReg ( ) ) ; switch ( TexHandleDef . getOpcode ( ) ) { case <STR_LIT> : { const <ISA_LIT>Subtarget & ST = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . getDrvInterface ( ) == <STR_LIT> ) { return false ; } assert ( TexHandleDef . getOperand ( <NUM_LIT> ) . isSymbol ( ) && <STR_LIT> ) ; StringRef Sym = TexHandleDef . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; std :: string ParamBaseName = MF . getName ( ) ; ParamBaseName += <STR_LIT> ; assert ( Sym . startswith ( ParamBaseName ) && <STR_LIT> ) ; unsigned Param = atoi ( Sym . data ( ) + ParamBaseName . size ( ) ) ; std :: string NewSym ; raw_string_ostream NewSymStr ( NewSym ) ; NewSymStr << MF . getFunction ( ) -> getName ( ) << <STR_LIT> << Param ; InstrsToRemove . insert ( & TexHandleDef ) ; Idx = MFI -> getImageHandleSymbolIndex ( NewSymStr . str ( ) . c_str ( ) ) ; return true ; } case <STR_LIT> : { assert ( TexHandleDef . getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const GlobalValue * GV = TexHandleDef . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; assert ( GV -> hasName ( ) && <STR_LIT> ) ; InstrsToRemove . insert ( & TexHandleDef ) ; Idx = MFI -> getImageHandleSymbolIndex ( GV -> getName ( ) . data ( ) ) ; return true ; } case <STR_LIT> : case TargetOpcode :: COPY : { bool Res = findIndexForHandle ( TexHandleDef . getOperand ( <NUM_LIT> ) , MF , Idx ) ; if ( Res ) { InstrsToRemove . insert ( & TexHandleDef ) ; } return Res ; } default : llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( ! LD -> isSimple ( ) || ! N0 . hasOneUse ( ) || LD -> isIndexed ( ) || LD -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = LD -> getValueType ( <NUM_LIT> ) ; EVT ToVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && ( FromEltVT == <STR_LIT> || FromEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || FromVT . getVectorNumElements ( ) == NumElements || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = FromVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT NewToVT = ToVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; unsigned NewOffset = NewFromVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , NewOffset ) ; SDValue NewLoad1 = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , BasePtr , Offset , LD -> getPointerInfo ( ) , NewFromVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; SDValue NewLoad2 = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( NewLoad1 . getNode ( ) , <NUM_LIT> ) , SDValue ( NewLoad2 . getNode ( ) , <NUM_LIT> ) ) ;

DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewChain ) ;


<s> SDValue Res = DAG . getNode ( IntrData -> Opc0 , dl , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , GenCF . getValue ( <NUM_LIT> ) ) ; SDValue Store = DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , Res . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Res . getValue ( <NUM_LIT> ) ) ; SDValue Results [ ] = { SetCC , Store } ; return DAG . getMergeValues ( Results , dl ) ; } case COMPRESS_TO_MEM : { SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue DataToCompress = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; MVT VT = DataToCompress . getSimpleValueType ( ) ; MemIntrinsicSDNode * MemIntr = dyn_cast < MemIntrinsicSDNode > ( Op ) ; assert ( MemIntr && <STR_LIT> ) ; if ( isAllOnesConstant ( Mask ) ) return DAG . getStore ( Chain , dl , DataToCompress , Addr , MemIntr -> getMemOperand ( ) ) ; SDValue Compressed = getVectorMaskingNode ( DAG . getNode ( IntrData -> Opc0 , dl , VT , DataToCompress ) , Mask , DAG . getUNDEF ( VT ) , Subtarget , DAG ) ; return DAG . getStore ( Chain , dl , Compressed , Addr , MemIntr -> getMemOperand ( ) ) ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue DataToTruncate = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; MemIntrinsicSDNode * MemIntr = dyn_cast < MemIntrinsicSDNode > ( Op ) ; assert ( MemIntr && <STR_LIT> ) ; EVT VT = MemIntr -> getMemoryVT ( ) ; if ( isAllOnesConstant ( Mask ) ) return DAG . getTruncStore ( Chain , dl , DataToTruncate , Addr , VT , MemIntr -> getMemOperand ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; return DAG . getMaskedStore ( Chain , dl , DataToTruncate , Addr , VMask , VT , MemIntr -> getMemOperand ( ) , true ) ; } case EXPAND_FROM_MEM : { SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue PassThru = Op . getOperand ( <NUM_LIT> ) ; SDValue Addr = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ;


<s> using namespace llvm :: <STR_LIT> ; unsigned <ISA_LIT>mm16 = MI -> getOperand ( OpNo ) . getImm ( ) ; const unsigned Id = ( <ISA_LIT>mm16 & ID_MASK_ ) >> ID_SHIFT_ ; const unsigned Offset = ( <ISA_LIT>mm16 & OFFSET_MASK_ ) >> OFFSET_SHIFT_ ; const unsigned Width = ( ( <ISA_LIT>mm16 & WIDTH_M1_MASK_ ) >> WIDTH_M1_SHIFT_ ) + <NUM_LIT> ;


<s> if ( ! isBitfieldPositioningOp ( CurDAG , SDValue ( N , <NUM_LIT> ) , false , Op0 , DstLSB , Width ) ) return false ; unsigned ImmR = ( VT . getSizeInBits ( ) - DstLSB ) % VT . getSizeInBits ( ) ; unsigned ImmS = Width - <NUM_LIT> ; SDLoc DL ( N ) ; SDValue Ops [ ] = { Op0 , CurDAG -> getTargetConstant ( ImmR , DL , VT ) , CurDAG -> getTargetConstant ( ImmS , DL , VT ) } ;

unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> explicit BlackfinFrameInfo ( const BlackfinSubtarget & sti ) : TargetFrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> bool isNonTemporal ( ) const { return IsNonTemporal ;


<s> if ( Predicate_so_imm ( TrueVal . getNode ( ) ) ) { SDValue True = CurDAG -> getTargetConstant ( T -> getZExtValue ( ) , <STR_LIT> ) ; SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , True , CC , CCR , InFlag } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ;


<s> auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; Changed |= VisitLoop ( MF , MLI , nullptr ) ; SmallVector < MachineLoop * , <NUM_LIT> > Worklist ( MLI . begin ( ) , MLI . end ( ) ) ; while ( ! Worklist . empty ( ) ) { MachineLoop * CurLoop = Worklist . pop_back_val ( ) ; Worklist . append ( CurLoop -> begin ( ) , CurLoop -> end ( ) ) ; Changed |= VisitLoop ( MF , MLI , CurLoop ) ; } if ( LLVM_UNLIKELY ( Changed ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MF . getRegInfo ( ) . invalidateLiveness ( ) ; MF . RenumberBlocks ( ) ; getAnalysis < MachineDominatorTree > ( ) . runOnMachineFunction ( MF ) ; MLI . runOnMachineFunction ( MF ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectARIPI ( SDNode * Parent , SDValue N , SDValue & Base ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerBRCOND ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue Jump = Op . getOperand ( <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Chain , Jump , Cond ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>GenPredicate ( ) { return new <ISA_LIT>GenPredicate ( ) ;


<s> switch ( ValLow ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( ! ( FeatureBits [ <STR_LIT> ] ) ) return MCDisassembler :: Fail ; break ; default : return MCDisassembler :: Fail ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Mask = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! ( FeatureBits [ <STR_LIT> ] ) ) { if ( Mask != <NUM_LIT> ) S = MCDisassembler :: SoftFail ; } else { if ( Mask == <NUM_LIT> || ( Mask != <NUM_LIT> && ValLow > <NUM_LIT> ) || ( ! ( FeatureBits [ <STR_LIT> ] ) && ( Mask & <NUM_LIT> ) ) ) S = MCDisassembler :: SoftFail ; } } } else { if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return S ;


<s> if ( Op . isReg ( ) ) { unsigned WAReg = Op . getReg ( ) ; if ( int ( WAReg ) >= <NUM_LIT> ) printRegName ( O , WAReg ) ; else if ( OpNo >= MII . get ( MI -> getOpcode ( ) ) . getNumDefs ( ) ) O << <STR_LIT> << <ISA_LIT>FunctionInfo :: getWARegStackId ( WAReg ) ; else if ( WAReg != <ISA_LIT>FunctionInfo :: UnusedReg ) O << <STR_LIT> << <ISA_LIT>FunctionInfo :: getWARegStackId ( WAReg ) ; else O << <STR_LIT> ; if ( OpNo < MII . get ( MI -> getOpcode ( ) ) . getNumDefs ( ) ) O << '=' ; } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else if ( Op . isFPImm ( ) ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & Info = Desc . OpInfo [ OpNo ] ; if ( Info . OperandType == <STR_LIT> ) { O << :: toString ( APFloat ( float ( Op . getFPImm ( ) ) ) ) ; } else { assert ( Info . OperandType == <STR_LIT> ) ; O << :: toString ( APFloat ( Op . getFPImm ( ) ) ) ; } } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; auto SRE = static_cast < const MCSymbolRefExpr * > ( Op . getExpr ( ) ) ; if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_WASM_TYPEINDEX ) { auto & Sym = static_cast < const MCSymbolWasm & > ( SRE -> getSymbol ( ) ) ;

O << <STR_LIT> ( Sym . getSignature ( ) ) ;


<s> return strncmp ( str , prefix , strlen ( prefix ) ) == <NUM_LIT> ;


<s> MachineBasicBlock * <ISA_LIT>ConstantIslands :: splitBlockBeforeInstr ( MachineInstr & MI ) { MachineBasicBlock * OrigBB = MI . getParent ( ) ; MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( OrigBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ OrigBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ;

water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ;


<s> return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ;


<s> const DataLayout & DL = MF . getDataLayout ( ) ;

return MF . getContext ( ) . getOrCreateSymbol ( Twine ( DL . getPrivateGlobalPrefix ( ) ) + Twine ( MF . getFunctionNumber ( ) ) + <STR_LIT> ) ;


<s> unsigned Type = cast < MCSymbolELF > ( Sym ) -> getType ( ) ; if ( ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) ) { if ( Asm . isThumbFunc ( Sym ) && ( FixupKind == <STR_LIT> ) ) return true ; if ( ! Asm . isThumbFunc ( Sym ) && ( FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> ) ) return true ; } } if ( A && ( FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> ) ) return true ; return false ;


<s> static void h8300_encode_section_info ( tree decl , rtx rtl , int first ) { int extra_flags = <NUM_LIT> ; default_encode_section_info ( decl , rtl , first ) ;

if ( TREE_CODE ( decl ) == FUNCTION_DECL && h8300_funcvec_function_p ( decl ) ) extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION ;


<s> auto NamedMD = M . getNamedMetadata ( Name ) ; if ( ! NamedMD || NamedMD -> getNumOperands ( ) == <NUM_LIT> ) return false ; SmallVector < Metadata * , <NUM_LIT> > All ; for ( const auto & MD : NamedMD -> operands ( ) ) for ( const auto & Op : MD -> operands ( ) ) if ( std :: find ( All . begin ( ) , All . end ( ) , Op . get ( ) ) == All . end ( ) ) All . push_back ( Op . get ( ) ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Shifter ) ; Op -> Shift . ShiftTy = ShTy ; Op -> StartLoc = S ;


<s> void <ISA_LIT>InstPrinter :: printU6ImmOperand ( const MCInst * MI , int OpNo , raw_ostream & O ) { unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ;

assert ( Value <= <NUM_LIT> && <STR_LIT> ) ;


<s> bool SawStore = false ; for ( MachineBasicBlock :: reverse_instr_iterator I = ++ Slot . getReverse ( ) ; I != MBB . instr_rend ( ) ; ++ I ) { if ( I -> isDebugInstr ( ) ) continue ; MachineBasicBlock :: instr_iterator FI = I . getReverse ( ) ; if ( I -> isInlineAsm ( ) || I -> isLabel ( ) || FI == LastFiller || I -> isPseudo ( ) ) break ; if ( delayHasHazard ( FI , SawLoad , SawStore , RegDefs , RegUses ) ) { insertDefsUses ( FI , RegDefs , RegUses ) ; continue ; } Filler = FI ; return true ; } return false ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; NeedTrunc = true ; Mask = <NUM_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; if ( NeedTrunc ) Op1Reg = emitAnd_ri ( <STR_LIT> , Op1Reg , Mask ) ; unsigned ResultReg = fastEmitInst_rr ( Opc , RC , Op0Reg , Op1Reg ) ; if ( NeedTrunc ) ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , Mask ) ;


<s> return std :: max ( info1 . get_sew ( ) , info2 . get_sew ( ) ) ;


<s> static struct unw_reg_state * dup_state_stack ( struct unw_reg_state * rs ) { struct unw_reg_state * copy , * prev = NULL , * first = NULL ; while ( rs ) { copy = alloc_reg_state ( ) ;

memcpy ( copy , rs , sizeof ( * copy ) ) ;


<s> if ( ( OrigCallInst >> <NUM_LIT> ) == <NUM_LIT> ) { intptr_t Offset = ( ( intptr_t ) Target - ( intptr_t ) OrigCallAddr ) >> <NUM_LIT> ; if ( Offset >= - ( <NUM_LIT> << <NUM_LIT> ) && Offset < ( <NUM_LIT> << <NUM_LIT> ) ) { OrigCallInst &= ( <NUM_LIT> << <NUM_LIT> ) | <NUM_LIT> ; OrigCallInst |= ( Offset & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) << <NUM_LIT> ; * OrigCallAddr = OrigCallInst ; } } if ( ( * StubCallAddr >> <NUM_LIT> ) == <NUM_LIT> ) StubCallAddr -= <NUM_LIT> ; else {

assert ( ( * StubCallAddr >> <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ;


<s> gcc_checking_assert ( GET_CODE ( SET_SRC ( op1 ) ) == COMPARE ) ; flags = SET_DEST ( op1 ) ; flags_mode = GET_MODE ( flags ) ;

if ( GET_MODE ( SET_SRC ( op1 ) ) != flags_mode ) return false ;


<s> tree decl = <NUM_LIT> ; if ( ! flag_pic || ! ( TARGET_WARN_RELOC || TARGET_ERROR_RELOC ) ) return ; if ( GET_CODE ( x ) == SYMBOL_REF ) decl = SYMBOL_REF_DECL ( x ) ; else if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) decl = SYMBOL_REF_DECL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; if ( decl && ! DECL_P ( decl ) ) decl = <NUM_LIT> ; if ( decl && DECL_P ( decl ) ) { location_t loc ; if ( ! last_assemble_variable_decl || in_section == ctors_section ) loc = DECL_SOURCE_LOCATION ( decl ) ; else loc = DECL_SOURCE_LOCATION ( last_assemble_variable_decl ) ; if ( TARGET_WARN_RELOC ) warning_at ( loc , <NUM_LIT> , <STR_LIT> , decl ) ; else error_at ( loc , <STR_LIT> , decl ) ; }


<s> if ( ! Ret . hasValue ( ) ) { Error ( TagLoc , <STR_LIT> + Name ) ; return false ; } Tag = Ret . getValue ( ) ; Parser . Lex ( ) ; } else { const MCExpr * AttrExpr ; TagLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . parseExpression ( AttrExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( AttrExpr ) ; if ( check ( ! CE , TagLoc , <STR_LIT> ) ) return true ; Tag = CE -> getValue ( ) ; } if ( Parser . parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; StringRef StringValue = <STR_LIT> ; bool IsStringValue = false ; int64_t IntegerValue = <NUM_LIT> ; bool IsIntegerValue = false ; if ( Tag == <STR_LIT> || Tag == <STR_LIT> ) IsStringValue = true ; else if ( Tag == <STR_LIT> ) { IsStringValue = true ; IsIntegerValue = true ; } else if ( Tag < <NUM_LIT> || Tag % <NUM_LIT> == <NUM_LIT> ) IsIntegerValue = true ; else if ( Tag % <NUM_LIT> == <NUM_LIT> ) IsStringValue = true ;


<s> return __builtin_loongson_psllh_s ( s , amount ) ;


<s> for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) BlendMask |= <NUM_LIT> << i ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , DL , <STR_LIT> ) ) ; } uint64_t LoMask = BlendMask & <NUM_LIT> ; uint64_t HiMask = ( BlendMask >> <NUM_LIT> ) & <NUM_LIT> ; if ( LoMask == <NUM_LIT> || LoMask == <NUM_LIT> || HiMask == <NUM_LIT> || HiMask == <NUM_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( LoMask , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( HiMask , DL , <STR_LIT> ) ) ; return DAG . getVectorShuffle ( <STR_LIT> , DL , Lo , Hi , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; } LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : { assert ( ( VT . is128BitVector ( ) || Subtarget . hasAVX2 ( ) ) && <STR_LIT> ) ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) { MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( BlendMask , DL , IntegerType ) ; return getVectorMaskingNode ( V2 , MaskNode , V1 , Subtarget , DAG ) ; } int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; if ( ! <STR_LIT> ( V1 . getNode ( ) ) && <STR_LIT> ( V2 . getNode ( ) ) ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ;


<s> void addUImmOperands ( MCInst & Inst , unsigned N ) const { if ( isImm ( ) && ! isConstantImm ( ) ) { addExpr ( Inst , getImm ( ) ) ; return ; }

addConstantUImmOperands < Bits , <NUM_LIT> , <NUM_LIT> > ( Inst , N ) ;


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printOperand ( MI , OpNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , OpNum , O ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , const MCRegisterInfo * Info ) : MCDisassembler ( STI ) , RegInfo ( Info ) {


<s> static bool rl78_valid_pointer_mode ( machine_mode m ) { return ( m == HImode || m == SImode ) ;


<s> return TargetTriple . isWindowsCoreCLREnvironment ( ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , raw_ostream & O ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>ATTInstPrinter ( O , MAI ) ;

if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>IntelInstPrinter ( O , MAI ) ;


<s> case <STR_LIT> : case <STR_LIT> : case FK_PCRel_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_64_PC32 ; break ; case MCSymbolRefExpr :: VK_PLT : Type = ELF :: R_<ISA_LIT>_64_PLT32 ; break ; case MCSymbolRefExpr :: VK_GOTPCREL : Type = ELF :: R_<ISA_LIT>_64_GOTPCREL ; break ; case MCSymbolRefExpr :: VK_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_64_GOTTPOFF ; break ; case MCSymbolRefExpr :: VK_TLSGD : Type = ELF :: R_<ISA_LIT>_64_TLSGD ; break ; case MCSymbolRefExpr :: VK_TLSLD : Type = ELF :: R_<ISA_LIT>_64_TLSLD ; break ; } break ; case FK_PCRel_2 : assert ( Modifier == MCSymbolRefExpr :: VK_None ) ; Type = ELF :: R_<ISA_LIT>_64_PC16 ; break ; case FK_PCRel_1 : assert ( Modifier == MCSymbolRefExpr :: VK_None ) ; Type = ELF :: R_<ISA_LIT>_64_PC8 ; break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_8 : Type = ELF :: R_<ISA_LIT>_64_64 ; break ; case <STR_LIT> : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_64_32S ; break ; case MCSymbolRefExpr :: VK_GOT : Type = ELF :: R_<ISA_LIT>_64_GOT32 ; break ; case MCSymbolRefExpr :: VK_GOTPCREL : Type = ELF :: R_<ISA_LIT>_64_GOTPCREL ; break ; case MCSymbolRefExpr :: VK_TPOFF : Type = ELF :: R_<ISA_LIT>_64_TPOFF32 ; break ; case MCSymbolRefExpr :: VK_DTPOFF : Type = ELF :: R_<ISA_LIT>_64_DTPOFF32 ; break ; } break ; case FK_Data_4 : Type = ELF :: R_<ISA_LIT>_64_32 ; break ; case FK_Data_2 : Type = ELF :: R_<ISA_LIT>_64_16 ; break ; case FK_PCRel_1 : case FK_Data_1 : Type = ELF :: R_<ISA_LIT>_64_8 ; break ;


<s> getParser ( ) . Lex ( ) ; getStreamer ( ) . EmitWinCFIPushReg ( Reg , Loc ) ; return false ;


<s> return VectorType :: get ( ArrayTy -> getArrayElementType ( ) , ArrayTy -> getArrayNumElements ( ) ) ;


<s> if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) return true ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> Instruction * ArgInGlobal = new AddrSpaceCastInst ( Arg , PointerType :: get ( Arg -> getType ( ) -> getPointerElementType ( ) , ADDRESS_SPACE_GLOBAL ) , Arg -> getName ( ) , FirstInst ) ; Value * ArgInGeneric = new AddrSpaceCastInst ( ArgInGlobal , Arg -> getType ( ) , Arg -> getName ( ) , FirstInst ) ;

Arg -> replaceAllUsesWith ( ArgInGeneric ) ;


<s> MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; DebugLoc DL = MI . getDebugLoc ( ) ;

Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> static bool CC_<ISA_LIT>_APCS_Custom_f64 ( unsigned & ValNo , EVT & ValVT , EVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) {

if ( ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ;


<s> static bool isMemInstrToReplace ( Instruction * I ) {

return isa < StoreInst > ( I ) || isa < LoadInst > ( I ) || isa < InsertValueInst > ( I ) || isa < ExtractValueInst > ( I ) ;


<s> } if ( ! GVar ) { llvm_unreachable ( <STR_LIT> ) ; return SDValue ( ) ; } const Type * Ty = cast < PointerType > ( GV -> getType ( ) ) -> getElementType ( ) ; if ( ! Ty -> isSized ( ) || isZeroLengthArray ( Ty ) ) { errs ( ) << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } SDValue base = getGlobalAddressWrapper ( GA , GV , DAG ) ; const TargetData * TD = TM . getTargetData ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ;

SDValue offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BuildGetId ( DAG , dl ) , DAG . getConstant ( Size , <STR_LIT> ) ) ;


<s> void <ISA_LIT>AsmPrinter :: PrinterDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) { OS << <STR_LIT> ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RCW = DAG . getNode ( <STR_LIT> , DL , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RCW ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RCW . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ;


<s> if ( pFormat . hasGOTPLT ( ) ) reserveOne ( llvm :: ELF :: DT_PLTGOT ) ;


<s> for ( unsigned i = <NUM_LIT> ; ! MI -> getOperand ( i ) . isFI ( ) ; ++ i ) assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; if ( ! MI -> mayLoad ( ) && ! MI -> mayStore ( ) ) return false ; MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ;

const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;


<s> InstructionCost Cost = <NUM_LIT> ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case <STR_LIT> : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { InstructionCost MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case <STR_LIT> : if ( LT . second != <STR_LIT> ) return ( Cost + <NUM_LIT> ) * LT . first ; return LT . first * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Cost + <NUM_LIT> ) * LT . first ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

if ( ! Ty -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Cost + <NUM_LIT> ) * LT . first ;


<s> StringRef CPU = STI . getCPU ( ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ;

if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ;


<s> for ( int i = <NUM_LIT> ; i != Len ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; SDValue & V = ( M < Size ? V1 : V2 ) ; M = M % Size ; if ( i > M || M >= HalfSize ) return false ; if ( Idx < <NUM_LIT> || ( Src == V && Idx == ( M - i ) ) ) { Src = V ; Idx = M - i ; continue ;


<s> unsigned SubIdx = ( IsI64 ? <STR_LIT> : <STR_LIT> ) ; bool DstIsLarger , SrcIsLarger ; tie ( DstIsLarger , SrcIsLarger ) = compareOpndSize ( CvtOpc , * MBB . getParent ( ) ) ; if ( DstIsLarger ) TmpReg = getRegisterInfo ( ) . getSubReg ( DstReg , SubIdx ) ; if ( SrcIsLarger ) DstReg = getRegisterInfo ( ) . getSubReg ( DstReg , SubIdx ) ; BuildMI ( MBB , I , DL , MovDesc , TmpReg ) . addReg ( SrcReg , KillSrc ) ;

BuildMI ( MBB , I , DL , CvtDesc , DstReg ) . addReg ( TmpReg , RegState :: Kill ) ;


<s> switch ( arm_tune ) { case TARGET_CPU_cortexa7 :

cortexa7_sched_reorder ( file , verbose , ready , n_readyp , clock ) ;


<s> STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SetupMachineFunction ( MF ) ; if ( STI -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> emitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> emitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; return false ;


<s> case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( SubAdd ) { unsigned Opc = SubAdd -> getOpcode ( ) ; bool IsSub = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! IsSub || ( SrcReg2 != <NUM_LIT> && SubAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && SubAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) ) { if ( IsInstrVSel ) return false ; <STR_LIT> NewCC = ( IsSub ? getSwappedCondition ( CC ) : getCmpToAddCondition ( CC ) ) ; if ( NewCC == <STR_LIT> ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } } if ( ! isSafe ) { MachineBasicBlock * MBB = CmpInstr . getParent ( ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; } if ( ! IsThumb1 ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; } assert ( ! isPredicated ( * MI ) && <STR_LIT> ) ; CmpInstr . eraseFromParent ( ) ; for ( unsigned i = <NUM_LIT> , e = OperandsToUpdate . size ( ) ; i < e ; i ++ ) OperandsToUpdate [ i ] . first -> setImm ( OperandsToUpdate [ i ] . second ) ; MI -> clearRegisterDeads ( <STR_LIT> ) ; return true ;


<s> if ( FlagsVal == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! hasDSP ( ) && ( FlagsVal & <NUM_LIT> ) ) return MatchOperand_NoMatch ; if ( ! hasV7Ops ( ) && FlagsVal >= <NUM_LIT> && FlagsVal <= <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ! has8MSecExt ( ) && ( FlagsVal == <NUM_LIT> || FlagsVal == <NUM_LIT> || ( FlagsVal > <NUM_LIT> && FlagsVal < <NUM_LIT> ) ) ) return MatchOperand_NoMatch ; if ( ! hasV8MMainline ( ) && ( FlagsVal == <NUM_LIT> || FlagsVal == <NUM_LIT> || ( FlagsVal > <NUM_LIT> && FlagsVal <= <NUM_LIT> ) ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateMSRMask ( FlagsVal , S ) ) ; return MatchOperand_Success ; } size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ;


<s> switch ( NumVectorElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> void <ISA_LIT>AsmParser :: applyLVILoadHardeningMitigation ( MCInst & Inst , MCStreamer & Out ) { auto Opcode = Inst . getOpcode ( ) ; auto Flags = Inst . getFlags ( ) ; if ( ( Flags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> unsigned u [ <NUM_LIT> ] ; char c [ <NUM_LIT> ] ; } text ; if ( GetCpuIDAndInfo ( <NUM_LIT> , & EAX , text . u + <NUM_LIT> , text . u + <NUM_LIT> , text . u + <NUM_LIT> ) ) return ; GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) HasCMov = true ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = MMX ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE1 ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE2 ; if ( ECX & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE41 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE42 ; bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool IsAMD = ! IsIntel && memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; HasFMA3 = IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ;

HasAVX = ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstructionSelector :: isRegInGprb ( Register Reg , MachineRegisterInfo & MRI ) const { return RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) == <STR_LIT> ;


<s> if ( FP_REG_P ( src ) || FP_REG_P ( dst ) || VECTOR_REG_P ( src ) || VECTOR_REG_P ( dst ) ) return false ; if ( ( GET_CODE ( src ) == MEM && ! offsettable_memref_p ( src ) ) || ( GET_CODE ( dst ) == MEM && ! offsettable_memref_p ( dst ) ) ) return false ; if ( register_operand ( dst , mode ) ) { rtx subreg = operand_subword ( dst , first_subword , <NUM_LIT> , mode ) ; if ( reg_overlap_mentioned_p ( subreg , src ) ) return false ; }


<s> } xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) ) ; xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; xop [ <NUM_LIT> ] = GEN_INT ( trunc_int_for_mode ( intval0 , SImode ) ) ; xop [ <NUM_LIT> ] = GEN_INT ( trunc_int_for_mode ( intval1 , SImode ) ) ; emit_move_insn ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; emit_move_insn ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; return ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( MEM_P ( operands [ i ] ) && auto_inc_p ( XEXP ( operands [ i ] , <NUM_LIT> ) ) ) { rtx addr = XEXP ( operands [ i ] , <NUM_LIT> ) ; rtx r , o ; enum rtx_code code ; gcc_assert ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , addr ) ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : o = GEN_INT ( - <NUM_LIT> ) ; goto pre_modify ; case PRE_INC : o = GEN_INT ( <NUM_LIT> ) ; goto pre_modify ; case PRE_MODIFY : o = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; pre_modify : code = PRE_MODIFY ; break ; case POST_DEC : o = GEN_INT ( - <NUM_LIT> ) ; goto post_modify ; case POST_INC : o = GEN_INT ( <NUM_LIT> ) ; goto post_modify ; case POST_MODIFY : o = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; post_modify : code = POST_MODIFY ; swap = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } r = XEXP ( addr , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , gen_rtx_fmt_ee ( code , Pmode , r , gen_rtx_PLUS ( Pmode , r , o ) ) , <NUM_LIT> ) ; xop [ <NUM_LIT> + i ] = adjust_automodify_address_nv ( operands [ i ] , SImode , plus_constant ( Pmode , r , <NUM_LIT> ) , <NUM_LIT> ) ; } else { xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ; xop [ <NUM_LIT> + i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , mode ) ; } } if ( reg_overlap_mentioned_p ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ) { swap = <NUM_LIT> ;

gcc_assert ( ! reg_overlap_mentioned_p ( xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ) ;


<s> if ( Kind . isText ( ) || Kind . isReadOnly ( ) ) { Type = ST_ROM0 ; } else if ( Kind . isBSS ( ) || Kind . isData ( ) ) { Type = ST_WRAM0 ;


<s> void setVarArgsFrameOffset ( int Offset ) { VarArgsFrameOffset = Offset ;


<s> void setCalleeSavedFrameSize ( unsigned bytes ) { CalleeSavedFrameSize = bytes ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } return true ; } if ( <ISA_LIT>InstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) || <ISA_LIT>InstrInfo :: isSALU ( MI ) || <ISA_LIT>InstrInfo :: isSMRD ( MI ) ) return false ;


<s> TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . Offset = TmpOffset ; if ( <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = SI -> second ; return true ; }


<s> int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ;


<s> unsigned NewOpc = <NUM_LIT> ; if ( ( N0 -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N0 ) ) && ( N1 -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N1 ) ) ) { NewOpc = <STR_LIT> ; } else if ( ( N0 -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N0 ) ) && ( N1 -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N1 ) ) ) { NewOpc = <STR_LIT> ; } else if ( VT . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) { return SDValue ( ) ; } else { return Op ; } DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Op0 = SkipExtension ( N0 , DAG ) ; SDValue Op1 = SkipExtension ( N1 , DAG ) ; assert ( Op0 . getValueType ( ) . is64BitVector ( ) && Op1 . getValueType ( ) . is64BitVector ( ) && <STR_LIT> ) ;

return DAG . getNode ( NewOpc , DL , VT , Op0 , Op1 ) ;


<s> return ( ( struct u4 * ) ptr ) -> data ;


<s> printf ( <STR_LIT> , n + <NUM_LIT> , ( unsigned MUL_TYPE ) n ) ; } else { printf ( <STR_LIT> , n , ( unsigned ) n ) ; printf ( <STR_LIT> , n , ( unsigned MUL_TYPE ) n ) ; } bool first = true ; for ( int j = <NUM_LIT> ; j < s -> m_num_vals ; j ++ ) { Expr * e = & s -> m_exprs [ j ] ; const Operator * op = e -> m_op ; if ( op == NULL ) continue ; char buf [ <NUM_LIT> ] ; snprintf ( buf , sizeof buf , <STR_LIT> , first ? <STR_LIT> : <STR_LIT> , op -> m_top_index , e -> m_lhs , e -> m_rhs , ( j + <NUM_LIT> ) == s -> m_num_vals ? <STR_LIT> : <STR_LIT> ) ; char opnd0 [ <NUM_LIT> ] ; if ( e -> m_lhs ) snprintf ( opnd0 , sizeof opnd0 , <STR_LIT> , e -> m_lhs ) ; else snprintf ( opnd0 , sizeof opnd0 , <STR_LIT> ) ; printf ( <STR_LIT> , buf , op -> m_name , j , opnd0 , op -> is_unary ( ) ? <STR_LIT> : <STR_LIT> , e -> m_rhs ) ; first = false ; } printf ( <STR_LIT> ) ; comma_separator = <STR_LIT> ; }


<s> i &= ~ mask ; __builtin_spe_mtspefscr ( i ) ;


<s> inline vector float vec_vsubfp ( vector float a1 , vector float a2 ) { return ( vector float ) __builtin_altivec_vsubfp ( ( vector float ) a1 , ( vector float ) a2 ) ;


<s> int NewFI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( * RC ) , TRI -> getSpillAlign ( * RC ) , true , nullptr , TargetStackID :: SGPRSpill ) ; if ( TRI -> spillSGPRToVGPR ( ) && MFI -> allocateSGPRSpillToVGPR ( MF , NewFI ) ) { FI = NewFI ; } else { MF . getFrameInfo ( ) . RemoveStackObject ( NewFI ) ;

FI = MF . getFrameInfo ( ) . CreateSpillStackObject ( TRI -> getSpillSize ( * RC ) , Align ( TRI -> getSpillAlign ( * RC ) ) ) ;


<s> static int translate_unix ( char * name , int type ATTRIBUTE_UNUSED ) { strcpy ( filename_buff , name ) ;


<s> SMLoc getStartLoc ( ) const override { return StartLoc ;


<s> break ; } case <STR_LIT> : { auto ConditionCode = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( FalseValue ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( Dst ) . addReg ( <STR_LIT> ) . addReg ( TrueValue ) ; break ; } case <STR_LIT> : { auto Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ConditionCode = <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; auto TrueValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto FalseValue = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; resolveComparison ( MBB , MI , DL , ConditionCode , MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) ) ;


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; assert ( Op2 . isReg ( ) && ( Op2 . getReg ( ) == <STR_LIT> || TargetRegisterInfo :: isPhysicalRegister ( Op2 . getReg ( ) ) ) ) ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) || Op2 . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return None ; else if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op1 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) || ( Op2 . getReg ( ) != <STR_LIT> && TRI -> regsOverlap ( Op2 . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) return None ; int64_t Coef = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; SmallVector < uint64_t , <NUM_LIT> > Elements ; if ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) ) { Op = & Op1 ; } else if ( Op1 . isFI ( ) ) Op = & Op1 ; if ( Op && Op -> isReg ( ) && Op -> getReg ( ) == Op2 . getReg ( ) && Coef > <NUM_LIT> ) { Elements . push_back ( dwarf :: DW_OP_constu ) ; Elements . push_back ( Coef + <NUM_LIT> ) ; Elements . push_back ( dwarf :: DW_OP_mul ) ; } else { if ( Op && Op2 . getReg ( ) != <STR_LIT> ) { int dwarfReg = TRI -> getDwarfRegNum ( Op2 . getReg ( ) , false ) ; if ( dwarfReg < <NUM_LIT> ) return None ; else if ( dwarfReg < <NUM_LIT> ) Elements . push_back ( dwarf :: DW_OP_reg0 + dwarfReg ) ; else { Elements . push_back ( dwarf :: DW_OP_regx ) ;


<s> static DecodeStatus DecodeBitfieldMaskOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { unsigned msb = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned lsb = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( lsb > msb ) Check ( S , MCDisassembler :: SoftFail ) ; uint32_t msb_mask = <NUM_LIT> ;

if ( msb != <NUM_LIT> ) msb_mask = ( <NUM_LIT> << ( msb + <NUM_LIT> ) ) - <NUM_LIT> ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( MF ) ;

TII . storeRegToStackSlot ( * BB , MI , SrcReg , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , FI , SrcRC , RI ) ;


<s> explicit <ISA_LIT>AsmBackend ( bool Is64Bit , bool IsELF ) : MCAsmBackend ( <STR_LIT> ) , Is64Bit ( Is64Bit ) , IsELF ( IsELF ) {


<s> bool <ISA_LIT>InstructionSelector :: selectConcatVectors ( MachineInstr & I , MachineRegisterInfo & MRI ) { assert ( I . getOpcode ( ) == TargetOpcode :: G_CONCAT_VECTORS && <STR_LIT> ) ; Register Dst = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op1 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;

Register Op2 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> HOST_WIDE_INT max_offset ; if ( TARGET_THUMB2 && ( ( offset & <NUM_LIT> ) != <NUM_LIT> ) ) return false ; if ( TARGET_THUMB2 ) max_offset = <NUM_LIT> ; else if ( TARGET_ARM ) max_offset = <NUM_LIT> ; else return false ; return ( ( offset <= max_offset ) && ( offset >= - max_offset ) ) ;


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , true ) {


<s> if ( ! InsMI ) return false ; if ( ! getOpcodeDef ( TargetOpcode :: G_IMPLICIT_DEF , InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) return false ; int64_t Index = <NUM_LIT> ;

if ( ! mi_match ( InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_ICst ( Index ) ) || Index ) return false ;


<s> BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , ImmReg ) . addImm ( CI . BaseOff ) ; BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BaseRegFlags = RegState :: Kill ; TII -> getAddNoCarry ( * MBB , CI . Paired , DL , BaseReg ) . addReg ( ImmReg ) . addReg ( AddrReg -> getReg ( ) , <NUM_LIT> , BaseSubReg ) ; BaseSubReg = <NUM_LIT> ; } MachineInstrBuilder Write2 = BuildMI ( * MBB , CI . Paired , DL , Write2Desc ) . addReg ( BaseReg , BaseRegFlags , BaseSubReg ) . add ( * Data0 ) . add ( * Data1 ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ; moveInstsAfter ( Write2 , CI . InstsToMove ) ; MachineBasicBlock :: iterator Next = std :: next ( CI . I ) ; CI . I -> eraseFromParent ( ) ;


<s> static Target The<ISA_LIT>64Target ;


<s> static void do_add3 ( rtx dest , rtx src1 , rtx src2 ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_adddi3 ( dest , src1 , src2 ) ) ; else emit_insn ( gen_addsi3 ( dest , src1 , src2 ) ) ;


<s> printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ;


<s> Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> :


<s> MCOperand lowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; public : <ISA_LIT>MCInstLower ( MCContext & ctx , <ISA_LIT>AsmPrinter & printer ) : Ctx ( ctx ) , Printer ( printer ) { } void lower ( const MachineInstr * MI , MCInst & OutMI ) const ;


<s> if ( isTRNMask ( ShuffleMask , VT , WhichResult ) ) { unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , dl , V1 . getValueType ( ) , V1 , V2 ) ; } if ( isZIP_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) { unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , dl , V1 . getValueType ( ) , V1 , V1 ) ; } if ( isUZP_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) { unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , dl , V1 . getValueType ( ) , V1 , V1 ) ; } if ( isTRN_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) { unsigned Opc = ( WhichResult == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , dl , V1 . getValueType ( ) , V1 , V1 ) ; } if ( SDValue Concat = tryFormConcatFromShuffle ( Op , DAG ) ) return Concat ; bool DstIsLeft ; int Anomaly ; int NumInputElements = V1 . getValueType ( ) . getVectorNumElements ( ) ; if ( isINSMask ( ShuffleMask , NumInputElements , DstIsLeft , Anomaly ) ) { SDValue DstVec = DstIsLeft ? V1 : V2 ; SDValue DstLaneV = DAG . getConstant ( Anomaly , dl , <STR_LIT> ) ; SDValue SrcVec = V1 ; int SrcLane = ShuffleMask [ Anomaly ] ; if ( SrcLane >= NumInputElements ) { SrcVec = V2 ; SrcLane -= VT . getVectorNumElements ( ) ; } SDValue SrcLaneV = DAG . getConstant ( SrcLane , dl , <STR_LIT> ) ; EVT ScalarVT = VT . getVectorElementType ( ) ; if ( ScalarVT . getSizeInBits ( ) < <NUM_LIT> && ScalarVT . isInteger ( ) ) ScalarVT = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DstVec , DAG . getNode ( <STR_LIT> , dl , ScalarVT , SrcVec , SrcLaneV ) , DstLaneV ) ; } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ;

else PFIndexes [ i ] = ShuffleMask [ i ] ;


<s> else pat = gen_sp_adjust ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ; insn = emit_insn ( pat ) ; REG_NOTES ( insn ) = reg_notes ; if ( frame_related ) { rtx real = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , imm_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , real ) ; } return insn ;


<s> Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , dl ) ; Chain = LowerWindowsDYNAMIC_STACKALLOC ( Op , Chain , Size , DAG ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , <STR_LIT> ) ; Chain = SP . getValue ( <NUM_LIT> ) ; SP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SP , Size ) ; if ( Align ) SP = DAG . getNode ( <STR_LIT> , dl , VT , SP . getValue ( <NUM_LIT> ) , DAG . getConstant ( - ( uint64_t ) Align , dl , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , SP ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , SDValue ( ) , dl ) ; SDValue Ops [ <NUM_LIT> ] = { SP , Chain } ;

return DAG . getMergeValues ( Ops , dl ) ;


<s> { v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; rtx_insn * insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSGD , v0 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , dest , v0 , loc ) ; break ; } case TLS_MODEL_LOCAL_DYNAMIC : { v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; rtx_insn * insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSLDM , v0 ) ; tmp1 = gen_reg_rtx ( Pmode ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) , UNSPEC_TLS_LDM ) ; emit_libcall_block ( insn , tmp1 , v0 , eqv ) ; offset = mips_unspec_address ( loc , SYMBOL_DTPREL ) ; if ( mips_split_p [ SYMBOL_DTPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_DTPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , <NUM_LIT> , <NUM_LIT> , OPTAB_DIRECT ) ; break ; } case TLS_MODEL_INITIAL_EXEC : tp = mips_get_tp ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = mips_unspec_address ( loc , SYMBOL_GOTTPREL ) ; if ( Pmode == DImode ) emit_insn ( gen_load_gotdi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; else emit_insn ( gen_load_gotsi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp1 = mips_get_tp ( ) ; offset = mips_unspec_address ( loc , SYMBOL_TPREL ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldInsertFencesForAtomic ( const Instruction * I ) const { return isOpSuitableForLDPSTP ( I ) ;


<s> static void ATTRIBUTE_UNUSED ix86_encode_section_info ( tree decl , rtx rtl , int first ) {

default_encode_section_info ( decl , rtl , first ) ;


<s> if ( PDT . getRoots ( ) . size ( ) <= <NUM_LIT> ) return false ; DivergenceAnalysis & DA = getAnalysis < DivergenceAnalysis > ( ) ; SmallVector < BasicBlock * , <NUM_LIT> > ReturningBlocks ; SmallVector < BasicBlock * , <NUM_LIT> > UnreachableBlocks ; for ( BasicBlock * BB : PDT . getRoots ( ) ) { if ( isa < ReturnInst > ( BB -> getTerminator ( ) ) ) { if ( ! isUniformlyReached ( DA , * BB ) ) ReturningBlocks . push_back ( BB ) ; } else if ( isa < UnreachableInst > ( BB -> getTerminator ( ) ) ) { if ( ! isUniformlyReached ( DA , * BB ) ) UnreachableBlocks . push_back ( BB ) ; } } if ( ! UnreachableBlocks . empty ( ) ) { BasicBlock * UnreachableBlock = nullptr ; if ( UnreachableBlocks . size ( ) == <NUM_LIT> ) { UnreachableBlock = UnreachableBlocks . front ( ) ; } else { UnreachableBlock = BasicBlock :: Create ( F . getContext ( ) , <STR_LIT> , & F ) ; new UnreachableInst ( F . getContext ( ) , UnreachableBlock ) ; for ( BasicBlock * BB : UnreachableBlocks ) { BB -> getInstList ( ) . pop_back ( ) ; BranchInst :: Create ( UnreachableBlock , BB ) ;


<s> auto Pred = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( auto MaybeNewImmAndPred = tryAdjustICmpImmAndPred ( RHS , Pred , MRI ) ) { MatchInfo = * MaybeNewImmAndPred ; return true ; } return false ;


<s> int F = A [ <NUM_LIT> ] ; int E = F ; for ( unsigned I = <NUM_LIT> ; I != MaxLen ; ++ I ) { if ( A [ I ] - E != Inc ) return { F , I } ;


<s> if ( DstBank -> getID ( ) != <STR_LIT> ) return false ; Register Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getType ( Src0 ) != S32 ) return false ; const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; auto ConstSrc1 = getAnyConstantVRegValWithLookThrough ( Src1 , * MRI , true , true ) ; if ( ConstSrc1 ) { auto ConstSrc0 = getAnyConstantVRegValWithLookThrough ( Src0 , * MRI , true , true ) ; if ( ConstSrc0 ) { const int64_t K0 = ConstSrc0 -> Value . getSExtValue ( ) ; const int64_t K1 = ConstSrc1 -> Value . getSExtValue ( ) ; uint32_t Lo16 = static_cast < uint32_t > ( K0 ) & <NUM_LIT> ; uint32_t Hi16 = static_cast < uint32_t > ( K1 ) & <NUM_LIT> ; BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addImm ( Lo16 | ( Hi16 << <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) ; } } MachineInstr * Src1Def = getDefIgnoringCopies ( Src1 , * MRI ) ; if ( Src1Def && Src1Def -> getOpcode ( ) == <STR_LIT> ) { MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; return RBI . constrainGenericRegister ( Dst , <STR_LIT> , * MRI ) && RBI . constrainGenericRegister ( Src0 , <STR_LIT> , * MRI ) ; } Register ShiftSrc0 ; Register ShiftSrc1 ; bool Shift0 = mi_match ( Src0 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc0 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; bool Shift1 = mi_match ( Src1 , * MRI , m_OneUse ( m_GLShr ( m_Reg ( ShiftSrc1 ) , m_SpecificICst ( <NUM_LIT> ) ) ) ) ; unsigned Opc = <STR_LIT> ; if ( Shift0 && Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc0 ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift1 ) { Opc = <STR_LIT> ; MI . getOperand ( <NUM_LIT> ) . setReg ( ShiftSrc1 ) ; } else if ( Shift0 && ConstSrc1 && ConstSrc1 -> Value == <NUM_LIT> ) { auto MIB = BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( ShiftSrc0 ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } MI . setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( MI , TII , TRI , RBI ) ;


<s> rtx r1 , r2 ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int inner_bytes = GET_MODE_SIZE ( inner ) ; if ( FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else { regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= <NUM_LIT> ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= <NUM_LIT> ) return gen_rtx_REG ( mode , regno ) ;

r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno ) , const0_rtx ) ;


<s> bool isUndef ( SDValue Op ) const { if ( Op . isMachineOpcode ( ) ) return Op . getMachineOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ; return Op . getOpcode ( ) == <STR_LIT> ;


<s> static DecodeStatus DecodeVecShiftL32Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { return DecodeVecShiftLImm ( Inst , Imm , <NUM_LIT> ) ;


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const bool SpillVGPRToAGPR = ST . hasMAIInsts ( ) && FuncInfo -> hasSpilledVGPRs ( ) && EnableSpillVGPRToAGPR ; if ( SpillVGPRToAGPR ) { BitVector SpillFIs ( MFI . getObjectIndexEnd ( ) , false ) ; BitVector NonVGPRSpillFIs ( MFI . getObjectIndexEnd ( ) , false ) ; bool SeenDbgInstr = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( MBB ) ) { int FrameIndex ; if ( MI . isDebugInstr ( ) ) SeenDbgInstr = true ; if ( TII -> isVGPRSpill ( MI ) ) { unsigned FIOp = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vaddr ) ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; Register VReg = TII -> getNamedOperand ( MI , <STR_LIT> :: vdata ) -> getReg ( ) ; if ( FuncInfo -> allocateVGPRSpillToAGPR ( MF , FI , TRI -> isAGPR ( MRI , VReg ) ) ) { RS -> enterBasicBlock ( MBB ) ; TRI -> eliminateFrameIndex ( MI , <NUM_LIT> , FIOp , RS ) ; SpillFIs . set ( FI ) ; continue ; } } else if ( TII -> isStoreToStackSlot ( MI , FrameIndex ) || TII -> isLoadFromStackSlot ( MI , FrameIndex ) ) if ( ! MFI . isFixedObjectIndex ( FrameIndex ) ) NonVGPRSpillFIs . set ( FrameIndex ) ; } } for ( unsigned FI : SpillFIs . set_bits ( ) ) if ( ! NonVGPRSpillFIs . test ( FI ) ) FuncInfo -> setVGPRToAGPRSpillDead ( FI ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MCPhysReg Reg : FuncInfo -> getVGPRSpillAGPRs ( ) ) MBB . addLiveIn ( Reg ) ; for ( MCPhysReg Reg : FuncInfo -> getAGPRSpillVGPRs ( ) ) MBB . addLiveIn ( Reg ) ; MBB . sortUniqueLiveIns ( ) ; if ( ! SpillFIs . empty ( ) && SeenDbgInstr ) { for ( MachineInstr & MI : MBB ) { if ( MI . isDebugValue ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && SpillFIs [ MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ] ) { MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Register ( ) , false ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> Register NarrowStateReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , NarrowStateReg ) . addReg ( StateReg , <NUM_LIT> , SubRegImm ) ; StateReg = NarrowStateReg ; } unsigned FlagsReg = <NUM_LIT> ; if ( isEFLAGSLive ( MBB , InsertPt , * TRI ) ) FlagsReg = saveEFLAGS ( MBB , InsertPt , Loc ) ; Register NewReg = MRI -> createVirtualRegister ( RC ) ; unsigned OrOpCodes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned OrOpCode = OrOpCodes [ Log2_32 ( Bytes ) ] ; auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( OrOpCode ) , NewReg ) . addReg ( StateReg ) . addReg ( Reg ) ; OrI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ;


<s> void nvptx_expand_oacc_join ( unsigned mode ) { nvptx_emit_joining ( GOMP_DIM_MASK ( mode ) , false ) ;


<s> return SMRange ( StartLoc , EndLoc ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectXFormAddr ( SDNode * Op , SDValue N , SDValue & Base , SDValue & Index ) { if ( ! SelectAFormAddr ( Op , N , Base , Index ) && ! SelectDFormAddr ( Op , N , Base , Index ) ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ;


<s> break ; case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; break ;


<s> <ISA_LIT>64TargetMachine :: <ISA_LIT>64TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , JIT , true ) {


<s> EVT NewFromVT = EVT :: getVectorVT ( C , FromEltVT , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = i * NumElements * ToEltVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , DL , NewFromVT , Trunc . getOperand ( <NUM_LIT> ) , DAG . getConstant ( i * NumElements , DL , <STR_LIT> ) ) ; SDValue FPTrunc = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Extract , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Extract = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPTrunc ) ; SDValue Store = DAG . getTruncStore ( Ch , DL , Extract , NewPtr , St -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewToVT , Alignment . value ( ) , MMOFlags , AAInfo ) ; Stores . push_back ( Store ) ;


<s> TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_32Target , create<ISA_LIT>_32AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_64Target , create<ISA_LIT>_64AsmBackend ) ; TargetRegistry :: RegisterMCNaClExpander ( The<ISA_LIT>_32Target , create<ISA_LIT>_32MCNaClExpander ) ;

TargetRegistry :: RegisterMCNaClExpander ( The<ISA_LIT>_64Target , create<ISA_LIT>_64MCNaClExpander ) ;


<s> case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal , DL ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal , DL ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , DL , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . ShrinkDemandedConstant ( BitsFrom , Demanded , TLO ) || TLI . SimplifyDemandedBits ( BitsFrom , Demanded , KnownZero , KnownOne , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; } } break ; } case <STR_LIT> : return performLoadCombine ( N , DCI ) ; case <STR_LIT> : return performStoreCombine ( N , DCI ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue DBZCHK = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , Or ) ; SDValue Result = LowerWindowsDIVLibCall ( Op , DAG , Signed , DBZCHK ) ; SDValue Lower = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result ) ; SDValue Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DL ) ) ) ; Upper = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Upper ) ; Results . push_back ( Lower ) ; Results . push_back ( Upper ) ;


<s> const TargetRegisterClass * SrcRC , * DstRC ; std :: tie ( SrcRC , DstRC ) = getCopyRegClasses ( MI , * TRI , MRI ) ; if ( isVGPRToSGPRCopy ( SrcRC , DstRC , * TRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; } break ; } case <STR_LIT> : { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRClass ( MRI . getRegClass ( Reg ) ) ) break ; bool SGPRBranch = false ; bool HasBreakDef = false ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i += <NUM_LIT> ) { unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( TRI -> hasVGPRs ( MRI . getRegClass ( Reg ) ) ) { TII -> moveToVALU ( MI ) ; break ; } MachineInstr * DefInstr = MRI . getUniqueVRegDef ( Reg ) ; assert ( DefInstr ) ; switch ( DefInstr -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasBreakDef = true ; break ; } } if ( ! SGPRBranch && ! HasBreakDef ) TII -> moveToVALU ( MI ) ; break ; } case <STR_LIT> : { if ( TRI -> hasVGPRs ( TII -> getOpRegClass ( MI , <NUM_LIT> ) ) || ! hasVGPROperands ( MI , TRI ) ) { foldVGPRCopyIntoRegSequence ( MI , TRI , TII , MRI ) ; continue ; }


<s> } NumBytes += ArgumentPopSize ; unsigned NumRestores = <NUM_LIT> ; MachineBasicBlock :: iterator LastPopI = MBBI ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( LastPopI != MBB . begin ( ) ) { do { ++ NumRestores ; -- LastPopI ; } while ( LastPopI != MBB . begin ( ) && isCSRestore ( LastPopI , CSRegs ) ) ; if ( ! isCSRestore ( LastPopI , CSRegs ) ) { ++ LastPopI ; -- NumRestores ; } } NumBytes -= NumRestores * <NUM_LIT> ; assert ( NumBytes >= <NUM_LIT> && <STR_LIT> ) ; if ( ! hasFP ( MF ) ) { if ( ! canUseRedZone ( MF ) ) emitFrameOffset ( MBB , LastPopI , DL , <STR_LIT> , <STR_LIT> , NumBytes , TII ) ; return ; } if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) emitFrameOffset ( MBB , LastPopI , DL , <STR_LIT> , <STR_LIT> , - ( NumRestores - <NUM_LIT> ) * <NUM_LIT> , TII , MachineInstr :: NoFlags ) ;


<s> } } } if ( ! Header ) return ; if ( ! IsBranchedTo ) return ; assert ( & MBB != & MF . front ( ) && <STR_LIT> ) ; MachineBasicBlock * LayoutPred = & * std :: prev ( MachineFunction :: iterator ( & MBB ) ) ; for ( MachineFunction :: iterator I ( LayoutPred ) , E ( Header ) ; I != E ; -- I ) { if ( MachineBasicBlock * ScopeTop = ScopeTops [ I -> getNumber ( ) ] ) { if ( ScopeTop -> getNumber ( ) > Header -> getNumber ( ) ) { I = std :: next ( MachineFunction :: iterator ( ScopeTop ) ) ; } else { Header = ScopeTop ; break ; } } } SmallPtrSet < const MachineInstr * , <NUM_LIT> > BeforeSet ; SmallPtrSet < const MachineInstr * , <NUM_LIT> > AfterSet ; for ( const auto & MI : * Header ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { if ( MBB . getNumber ( ) > getBottom ( & MI ) -> getNumber ( ) ) AfterSet . insert ( & MI ) ; else BeforeSet . insert ( & MI ) ; } if ( MI . getOpcode ( ) == <STR_LIT> ) AfterSet . insert ( & MI ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) BeforeSet . insert ( & MI ) ; if ( MI . isTerminator ( ) ) AfterSet . insert ( & MI ) ; } for ( auto I = Header -> getFirstTerminator ( ) , E = Header -> begin ( ) ; I != E ; -- I ) { if ( std :: prev ( I ) -> isDebugInstr ( ) || std :: prev ( I ) -> isPosition ( ) ) continue ; if ( <STR_LIT> ( * std :: prev ( I ) , MFI ) ) AfterSet . insert ( & * std :: prev ( I ) ) ;


<s> } if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , true ) ) return Med3 ; } if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , false ) ) return Med3 ; }

if ( ( ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) ) && ( VT == <STR_LIT> || VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> has16BitInsts ( ) ) || ( VT == <STR_LIT> && Subtarget -> hasVOP3PInsts ( ) ) ) && Op0 . hasOneUse ( ) ) {


<s> uw_update_reg_address ( context , fs , i ) ; } for ( i = UNW_REG_BSP ; i < UNW_NUM_REGS ; ++ i ) uw_update_reg_address ( context , fs , i ) ; if ( ! ( fs -> no_reg_stack_frame ) ) { unsigned long pfs = * context -> pfs_loc ; unsigned long sol = ( pfs >> <NUM_LIT> ) & <NUM_LIT> ; context -> bsp = ( unsigned long ) ia64_rse_skip_regs ( ( unsigned long * ) context -> bsp , - sol ) ;


<s> static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_LO16 , <STR_LIT> } , { MO_HI16 , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; ShuffleMask . push_back ( <NUM_LIT> ) ;

for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) ShuffleMask . push_back ( SM_SentinelZero ) ;


<s> bool <ISA_LIT>ElimCompare :: convertToBRCT ( MachineInstr * MI , MachineInstr * Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { unsigned Opcode = MI -> getOpcode ( ) ; unsigned BRCT ; if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return false ; if ( CCUsers . size ( ) != <NUM_LIT> ) return false ;

MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ;


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ;

int32_t width = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - lsb ;


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size != <NUM_LIT> || isOpSuitableForLDPSTP ( LI ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: CmpXChg ; return AtomicExpansionKind :: LLSC ;


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ;


<s> dbgs ( ) << <STR_LIT> ; Header -> dump ( ) ; dbgs ( ) << <STR_LIT> ; L -> dump ( ) ) ; bool Changed = false ; ReductionList Reductions = MatchReductions ( F , L , Header ) ; for ( auto & R : Reductions ) { ParallelMACList MACCandidates = MatchParallelMACs ( R ) ; if ( ! SetMemoryLocations ( MACCandidates ) ) continue ; Instructions Aliases = AliasCandidates ( Header , MACCandidates ) ;

if ( AreAliased ( AA , Aliases , MACCandidates ) ) continue ;


<s> if ( IsNegative ) Op = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) , Op ) ; return Op ;


<s> return isImm ( ) && isConstantImm ( ) && isUInt < Bits > ( getConstantImm ( ) ) ;


<s> int32_t i [ <NUM_LIT> ] ; } u ; u . v = a ;


<s> reg = reload_reg_map [ rc ] . reg ; if ( reg >= <NUM_LIT> && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { bool small_int_vsx_p = ( small_int_p && ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) ) ; nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( small_int_vsx_p ) addr_mask |= RELOAD_REG_INDEXED ; else if ( nregs > <NUM_LIT> || m == BLKmode || complex_p ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= <NUM_LIT> && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 ) && ! complex_p && ! small_int_vsx_p && ( m2 != DFmode || ! TARGET_UPPER_REGS_DF ) && ( m2 != SFmode || ! TARGET_UPPER_REGS_SF ) && ! ( TARGET_E500_DOUBLE && msize == <NUM_LIT> ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case DFmode : case DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize <= <NUM_LIT> && ( rc == RELOAD_REG_GPR || ( ( msize == <NUM_LIT> || m2 == SFmode ) && ( rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_DFORM_SCALAR ) ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ; else if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize == <NUM_LIT> && TARGET_P9_DFORM_VECTOR && ( ALTIVEC_OR_VSX_VECTOR_MODE ( m2 ) || ( m2 == TImode && TARGET_VSX_TIMODE ) ) ) { addr_mask |= RELOAD_REG_OFFSET ; if ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) addr_mask |= RELOAD_REG_QUAD_OFFSET ; } if ( rc == RELOAD_REG_VMX && msize == <NUM_LIT> && ( addr_mask & RELOAD_REG_VALID ) != <NUM_LIT> ) addr_mask |= RELOAD_REG_AND_M16 ;

reg_addr [ m ] . addr_mask [ rc ] = addr_mask ;


<s> void <ISA_LIT>AsmPrinter :: emitImplicitDef ( const MachineInstr * MI ) const { unsigned RegNo = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterInfo * TRI = TM . getRegisterInfo ( ) ; if ( TRI -> isVirtualRegister ( RegNo ) ) { OutStreamer . AddComment ( Twine ( <STR_LIT> ) + getVirtualRegisterName ( RegNo ) ) ; } else { OutStreamer . AddComment ( Twine ( <STR_LIT> ) + TM . getRegisterInfo ( ) -> getName ( RegNo ) ) ; } OutStreamer . AddBlankLine ( ) ;


<s> return SMRange ( StartLoc , EndLoc ) ;


<s> if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , STI ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . isOSBinFormatCOFF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , STI ) ;

uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ;


<s> static std :: string getGraphName ( const SpillCostAnalysisGraph & G ) {


<s> if ( RHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { Opcode = <STR_LIT> ; RHS = RHS . getOperand ( <NUM_LIT> ) ; } else if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( RHS ) && cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) == <NUM_LIT> && ! isUnsignedIntSetCC ( CC ) ) { Opcode = <STR_LIT> ; RHS = LHS . getOperand ( <NUM_LIT> ) ; LHS = LHS . getOperand ( <NUM_LIT> ) ; } return DAG . getNode ( Opcode , dl , DAG . getVTList ( VT , MVT_CC ) , LHS , RHS ) . getValue ( <NUM_LIT> ) ;


<s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex ;


<s> int64_t ImmValue = ImmOp . getImm ( ) ; tmpInst . setLoc ( IDLoc ) ; if ( <NUM_LIT> <= ImmValue && ImmValue <= <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ImmValue < <NUM_LIT> && ImmValue >= - <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ( ImmValue & <NUM_LIT> ) == ImmValue ) { tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & <NUM_LIT> ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < <NUM_LIT> , false > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; } else if ( ( ImmValue & ( <NUM_LIT> << <NUM_LIT> ) ) == <NUM_LIT> ) { if ( ! isGP64bit ( ) ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & ( <NUM_LIT> << <NUM_LIT> ) ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < <NUM_LIT> , false > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; createShiftOr < <NUM_LIT> , true > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; } else { if ( ! isGP64bit ( ) ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ImmValue & ( <NUM_LIT> << <NUM_LIT> ) ) >> <NUM_LIT> ) ) ; Instructions . push_back ( tmpInst ) ; createShiftOr < <NUM_LIT> , false > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; createShiftOr < <NUM_LIT> , true > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; createShiftOr < <NUM_LIT> , true > ( ImmValue , RegOp . getReg ( ) , IDLoc , Instructions ) ; } return false ;


<s> TmpInst . addOperand ( MCOperand :: createImm ( Imm2 ) ) ; TmpInst . setLoc ( IDLoc ) ; getStreamer ( ) . EmitInstruction ( TmpInst , * STI ) ;


<s> static bool isPredicateCCSettingOp ( SDValue N ) {

if ( ( N . getOpcode ( ) == <STR_LIT> ) || ( N . getOpcode ( ) == <STR_LIT> && ( N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> || N . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) ) ) return true ;


<s> if ( Flags . isSExt ( ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG . getValueType ( ValVT ) ) ;

else if ( Flags . isZExt ( ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG . getValueType ( ValVT ) ) ;


return ( __m256i ) __builtin_ia32_pbroadcastd256 ( ( __v4si ) __X ) ;


<s> assert ( std :: prev ( MBBI ) -> isTerminator ( ) && <STR_LIT> ) ; const TargetInstrInfo * TII = ST -> getInstrInfo ( ) ; assert ( ST -> hasDataBarrier ( ) || ST -> hasSB ( ) ) ; bool ProduceSB = ST -> hasSB ( ) && ! AlwaysUseISBDSB ; unsigned BarrierOpc = ProduceSB ? ( ST -> isThumb ( ) ? <STR_LIT> : <STR_LIT> ) : ( ST -> isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ;

if ( MBBI == MBB . end ( ) || ! isSpeculationBarrierEndBBOpcode ( MBBI -> getOpcode ( ) ) ) BuildMI ( MBB , MBBI , DL , TII -> get ( BarrierOpc ) ) ;


<s> if ( TT . isOSBinFormatELF ( ) ) return create<ISA_LIT>ObjectTargetELFStreamer ( S ) ;


<s> return _mm_set_epi64x ( __A , __A ) ;


<s> else if ( qualifiers & qualifier_poly ) { type_signature [ arg_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ arg_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; eltype = arm_simd_builtin_type ( op_mode , ( qualifiers & qualifier_unsigned ) != <NUM_LIT> , ( qualifiers & qualifier_poly ) != <NUM_LIT> ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; if ( arg_num == <NUM_LIT> ) return_type = eltype ;

else args = tree_cons ( NULL_TREE , eltype , args ) ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti , const DataLayout * DL ) : TargetFrameLowering ( StackGrowsDown , DL -> getStackAlignment ( ) , <NUM_LIT> ) , STC ( sti ) {


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( RegCtx . shadowReg ( <STR_LIT> ) ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( RegCtx . addressReg ( <STR_LIT> ) ) ) ; if ( RegCtx . ScratchReg != <STR_LIT> ) { EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( RegCtx . scratchReg ( <STR_LIT> ) ) ) ; }


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) {


<s> u . i [ <NUM_LIT> ] = a ; u . i [ <NUM_LIT> ] = b ; u . i [ <NUM_LIT> ] = c ;


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeS1Operand ( const MachineInstr * MI , int Op ) {

printThumbAddrModeRI5Operand ( MI , Op , <NUM_LIT> ) ;


<s> if ( UseMI == & MI ) continue ; if ( MO . isDef ( ) || UseMI -> getParent ( ) != MI . getParent ( ) || UseMI -> getOpcode ( ) <= TargetOpcode :: GENERIC_OP_END || ! TII -> isOperandLegal ( * UseMI , UseMI -> getOperandNo ( & MO ) , & Src ) ) return false ; } MRI . setRegClass ( DstReg , TRI -> getEquivalentSGPRClass ( MRI . getRegClass ( DstReg ) ) ) ; return true ;


<s> return ( __mmask8 ) __builtin_ia32_korqi ( ( __mmask8 ) __A , ( __mmask8 ) __B ) ;


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> static SDValue combineZext ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) {


<s> fprintf ( stderr , <STR_LIT> ) ; if ( virt_insn_was_frame ) RTX_FRAME_RELATED_P ( r ) = <NUM_LIT> ;


<s> uint16_t Val = static_cast < uint16_t > ( Literal ) ; return Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> ;


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { UP . Runtime = UP . Partial = true ;


<s> case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt ) , dl , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> isUndef ( ) ) { Elts . push_back ( CurrentOp ) ; continue ; } ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . ashr ( ShiftAmt ) , dl , ElementType ) ) ; } break ; } return DAG . getBuildVector ( VT , dl , Elts ) ;


<s> MachineOperand & Src1 = Inst . getOperand ( <NUM_LIT> ) ; unsigned NewDest = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Interm = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & Not = * BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , Interm ) . add ( Src1 ) ; MachineInstr & Op = * BuildMI ( MBB , MII , DL , get ( Opcode ) , NewDest ) . add ( Src0 ) . addReg ( Interm ) ;


<s> bool isTargetIOS ( ) const { return TargetTriple . isiOS ( ) ;


<s> bool <ISA_LIT>InstrInfo :: unfoldMemoryOperand ( SelectionDAG & DAG , SDNode * N , SmallVectorImpl < SDNode * > & NewNodes ) const { return false ;


<s> if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; SmallVector < int , <NUM_LIT> > RepeatedMask ; bool Is128BitLaneRepeatedShuffle = is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ; if ( Is128BitLaneRepeatedShuffle ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Subtarget . hasBWI ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Is128BitLaneRepeatedShuffle && isSingleSHUFPSMask ( RepeatedMask ) ) { SDValue CastV1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; SDValue CastV2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; SDValue ShufPS = lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , CastV1 , CastV2 , DAG ) ; return DAG . getBitcast ( <STR_LIT> , ShufPS ) ;


<s> if ( ! Subtarget -> isTargetDarwin ( ) ) return <NUM_LIT> ;

return Subtarget -> isThumb ( ) ? <STR_LIT> : <STR_LIT> ;


<s> CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; Register Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorElementCount ( ) . isVector ( ) && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ;

bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineOperand & Dest = MI . getOperand ( <NUM_LIT> ) ; unsigned TempReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; unsigned AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DesiredReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand New = MI . getOperand ( <NUM_LIT> ) ; New . setIsKill ( false ) ; unsigned DestLo = TRI -> getSubReg ( Dest . getReg ( ) , <STR_LIT> ) ; unsigned DestHi = TRI -> getSubReg ( Dest . getReg ( ) , <STR_LIT> ) ; unsigned DesiredLo = TRI -> getSubReg ( DesiredReg , <STR_LIT> ) ; unsigned DesiredHi = TRI -> getSubReg ( DesiredReg , <STR_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoadCmpBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto StoreBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoadCmpBB ) ; MF -> insert ( ++ LoadCmpBB -> getIterator ( ) , StoreBB ) ; MF -> insert ( ++ StoreBB -> getIterator ( ) , DoneBB ) ; unsigned LDREXD = IsThumb ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB ; MIB = BuildMI ( LoadCmpBB , DL , TII -> get ( LDREXD ) ) ; addExclusiveRegPair ( MIB , Dest , RegState :: Define , IsThumb , TRI ) ; MIB . addReg ( AddrReg ) . add ( predOps ( <STR_LIT> ) ) ; unsigned CMPrr = IsThumb ? <STR_LIT> : <STR_LIT> ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestLo , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredLo ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( LoadCmpBB , DL , TII -> get ( CMPrr ) ) . addReg ( DestHi , getKillRegState ( Dest . isDead ( ) ) ) . addReg ( DesiredHi ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; unsigned Bcc = IsThumb ? <STR_LIT> : <STR_LIT> ;

BuildMI ( LoadCmpBB , DL , TII -> get ( Bcc ) ) . addMBB ( DoneBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> unsigned getLanes ( ) const { return Lanes ;


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;


<s> static bool containsLongjmpableCalls ( const Function * F ) { for ( const auto & BB : * F ) for ( const auto & I : BB ) if ( const auto * CB = dyn_cast < CallBase > ( & I ) ) if ( canLongjmp ( CB -> getCalledOperand ( ) ) ) return true ;