<s> if ( targetm . calls . must_pass_in_stack ( arg ) ) return true ;

if ( MMIX_FUNCTION_ARG_SIZE ( arg . mode , arg . type ) > <NUM_LIT> && ! TARGET_LIBFUNC && ( ! argsp || ! argsp -> lib ) ) return true ;


<s> if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , Subtarget ) ) { DCI . CombineTo ( N , Res ) ; return SDValue ( ) ; }


<s> case <STR_LIT> : return MCSymbolRefExpr :: VK_TLSGD ; case <STR_LIT> : return MCSymbolRefExpr :: VK_TPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_GOTTPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL ; }


<s> return ( int16x4_t ) __builtin_neon_vqrshrns_nv4si ( __a , __b ) ;


<s> return __aarch64_vdup_laneq_u64 ( __a , __b ) ;


<s> bool IsVector = false ; if ( RegNum == static_cast < unsigned > ( - <NUM_LIT> ) ) { StringRef Kind ; RegNum = tryMatchVectorRegister ( Kind , false ) ; if ( ! Kind . empty ( ) ) { Error ( SRegLoc , <STR_LIT> ) ; return false ; } IsVector = true ; } if ( RegNum == static_cast < unsigned > ( - <NUM_LIT> ) ) { Parser . eatToEndOfStatement ( ) ; Error ( SRegLoc , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ;


<s> return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , true ) ;


<s> struct cgraph_node * target = NULL ; memset ( cum , <NUM_LIT> , sizeof ( * cum ) ) ; if ( fndecl ) { target = cgraph_node :: get ( fndecl ) ; if ( target ) { target = target -> function_symbol ( ) ; i = cgraph_node :: local_info ( target -> decl ) ; cum -> call_abi = ix86_function_abi ( target -> decl ) ; } else cum -> call_abi = ix86_function_abi ( fndecl ) ; } else cum -> call_abi = ix86_function_type_abi ( fntype ) ; cum -> caller = caller ; cum -> nregs = ix86_regparm ; if ( TARGET_64BIT ) { cum -> nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; } if ( TARGET_SSE ) { cum -> sse_nregs = SSE_REGPARM_MAX ; if ( TARGET_64BIT ) { cum -> sse_nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_SSE_REGPARM_MAX : X86_64_MS_SSE_REGPARM_MAX ) ; } } if ( TARGET_MMX ) cum -> mmx_nregs = MMX_REGPARM_MAX ; cum -> warn_avx512f = true ; cum -> warn_avx = true ; cum -> warn_sse = true ; cum -> warn_mmx = true ; if ( i && i -> local && i -> can_change_signature ) fntype = TREE_TYPE ( target -> decl ) ;


<s> bool NeedsAligna = needsAligna ( MF ) ; unsigned Size = HRI . getSpillSize ( <STR_LIT> ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned LoadOpc ; auto UseAligned = [ & ] ( unsigned NeedAlign , unsigned HasAlign ) { return ! NeedsAligna && ( NeedAlign <= HasAlign ) ; } ; LoadOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstLo ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( TM . getCodeModel ( ) != CodeModel :: Small && TM . getCodeModel ( ) != CodeModel :: Kernel ) return NULL ; unsigned PICBase = <NUM_LIT> ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) PICBase = <STR_LIT> ; else return NULL ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; const Type * Ty ; if ( LoadMI -> getOpcode ( ) == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( LoadMI -> getOpcode ( ) == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ; const Constant * C = LoadMI -> getOpcode ( ) == <STR_LIT> ? Constant :: getAllOnesValue ( Ty ) : Constant :: getNullValue ( Ty ) ; unsigned CPI = MCP . getConstantPoolIndex ( C , Alignment ) ; MOs . push_back ( MachineOperand :: CreateReg ( PICBase , false ) ) ; MOs . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ; MOs . push_back ( MachineOperand :: CreateCPI ( CPI , <NUM_LIT> ) ) ; MOs . push_back ( MachineOperand :: CreateReg ( <NUM_LIT> , false ) ) ;


<s> MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CmpVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned AlignedAddr = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftAmt = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask2 = RegInfo . createVirtualRegister ( RC ) ; unsigned Mask3 = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned OldVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal0 = RegInfo . createVirtualRegister ( RC ) ; unsigned ShiftedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned PtrLSB2 = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskUpper = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedCmpVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedNewVal = RegInfo . createVirtualRegister ( RC ) ; unsigned MaskedOldVal1 = RegInfo . createVirtualRegister ( RC ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned SrlRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , sinkMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( sinkMBB ) ;


<s> if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( Reg ) ) continue ; auto & LiveMask = LiveRegs [ Reg ] ; auto PrevMask = LiveMask ;

LiveMask |= getDefRegMask ( MO , * MRI ) ;


<s> SDLoc dl ( Op ) ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Op = DAG . getNode ( Opc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ;


<s> default : return false ; } unsigned DstIdx = <NUM_LIT> ; unsigned SrcIdx = IncDec -> getNumExplicitDefs ( ) ; while ( IncDec -> getOperand ( DstIdx ) . getReg ( ) != Reg ) { if ( IncDec -> getOperand ( SrcIdx ) . isReg ( ) ) ++ DstIdx ; ++ SrcIdx ; }

if ( ! mi_match ( IncDec -> getOperand ( SrcIdx ) . getReg ( ) , MRI , m_all_of ( m_MInstr ( Load ) , m_FoldedLdAbs ( StoreMI , Addr , AA ) ) ) ) return false ;


<s> bool isSImm12 ( ) const { <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsValid ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ; return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) ;


<s> case <STR_LIT> : return PerformADDCCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ; case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformVCVTCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVDIVCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return CombineBaseUpdate ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MachineBasicBlock :: iterator IP = EntryBB . begin ( ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , UpdatedVRSAVE ) . addReg ( InVRSAVE ) ; BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) ) . addReg ( UpdatedVRSAVE ) ; for ( MachineFunction :: iterator BB = Fn . begin ( ) , E = Fn . end ( ) ; BB != E ; ++ BB ) { if ( ! BB -> empty ( ) && BB -> back ( ) . isReturn ( ) ) { IP = BB -> end ( ) ; -- IP ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , Op . getDebugLoc ( ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( BC0 . hasOneUse ( ) && SVT . isVector ( ) && SVT . getVectorNumElements ( ) * <NUM_LIT> == NumElts && TLI . isOperationLegal ( Opcode , VT ) ) { bool CanFold = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getNode ( <STR_LIT> , dl , VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getNode ( <STR_LIT> , dl , VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } }

SmallVector < SDValue , <NUM_LIT> > Elts ;


<s> static inline int getQuarterRateInstrCost ( TTI :: TargetCostKind CostKind = TTI :: TCK_RecipThroughput ) {

return CostKind == TTI :: TCK_CodeSize ? <NUM_LIT> : <NUM_LIT> * TargetTransformInfo :: TCC_Basic ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) {


<s> SDValue <ISA_LIT>TargetLowering :: getSqrtInputTest ( SDValue Op , SelectionDAG & DAG , const DenormalMode & Mode ) const { EVT VT = Op . getValueType ( ) ;

if ( ! isTypeLegal ( <STR_LIT> ) || ( VT != <STR_LIT> && ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || ! Subtarget . hasVSX ( ) ) ) ) return TargetLowering :: getSqrtInputTest ( Op , DAG , Mode ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemOffset ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ;

return ( ( Value & <NUM_LIT> ) == <NUM_LIT> && Value <= <NUM_LIT> && Value >= - <NUM_LIT> ) ;


<s> ArrayRef < int > OpMask = Op0 -> getMask ( ) ; for ( int i = <NUM_LIT> , e = NMask . size ( ) ; i != e ; i ++ ) { if ( NMask [ i ] > <NUM_LIT> && OpMask [ NMask [ i ] ] > <NUM_LIT> && OpMask [ NMask [ i ] ] != i ) return SDValue ( ) ; }

return DAG . getNode ( Op . getOpcode ( ) , SDLoc ( Op ) , Op . getValueType ( ) , Op0 -> getOperand ( <NUM_LIT> ) , Op1 -> getOperand ( <NUM_LIT> ) ) ;


<s> SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; unsigned MxOpcode ; unsigned MxCond ; SDVTList VTs ; switch ( CondOpcode ) { case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Inverted ) MxCond = <STR_LIT> ( ( <STR_LIT> ) MxCond ) ; if ( CondOpcode == <STR_LIT> ) VTs = DAG . getVTList ( LHS . getValueType ( ) , LHS . getValueType ( ) , <STR_LIT> ) ; else VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue MxOp = DAG . getNode ( MxOpcode , DL , VTs , LHS , RHS ) ; if ( CondOpcode == <STR_LIT> ) Cond = MxOp . getValue ( <NUM_LIT> ) ; else Cond = MxOp . getValue ( <NUM_LIT> ) ; CC = DAG . getConstant ( MxCond , DL , <STR_LIT> ) ; addTest = false ; } else { unsigned CondOpc ; if ( Cond . hasOneUse ( ) && isAndOrOfSetCCs ( Cond , CondOpc ) ) { SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( CondOpc == <STR_LIT> ) { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) ) { CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Cond = Cmp ; addTest = false ; } } else { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) && Op . getNode ( ) -> hasOneUse ( ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , DL , <STR_LIT> ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> ) { SDValue FalseBB = User -> getOperand ( <NUM_LIT> ) ; SDNode * NewBR = DAG . UpdateNodeOperands ( User , User -> getOperand ( <NUM_LIT> ) , Dest ) ; assert ( NewBR == User ) ; ( void ) NewBR ; Dest = FalseBB ;


return isInlineImm ( ) || ( isReg ( ) && isRegClass ( AMDGPU :: VS_32RegClassID ) ) ;


<s> SmallVector < LoadInst * , <NUM_LIT> > AggrLoads ; SmallVector < MemIntrinsic * , <NUM_LIT> > MemCalls ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; LLVMContext & Context = F . getParent ( ) -> getContext ( ) ; const TargetTransformInfo & TTI = getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { if ( LoadInst * LI = dyn_cast < LoadInst > ( & I ) ) { if ( ! LI -> hasOneUse ( ) ) continue ; if ( DL . getTypeStoreSize ( LI -> getType ( ) ) < MaxAggrCopySize ) continue ; if ( StoreInst * SI = dyn_cast < StoreInst > ( LI -> user_back ( ) ) ) { if ( SI -> getOperand ( <NUM_LIT> ) != LI ) continue ; AggrLoads . push_back ( LI ) ; } } else if ( MemIntrinsic * IntrCall = dyn_cast < MemIntrinsic > ( & I ) ) { if ( ConstantInt * LenCI = dyn_cast < ConstantInt > ( IntrCall -> getLength ( ) ) ) { if ( LenCI -> getZExtValue ( ) >= MaxAggrCopySize ) { MemCalls . push_back ( IntrCall ) ; } } else { MemCalls . push_back ( IntrCall ) ; } } } } if ( AggrLoads . size ( ) == <NUM_LIT> && MemCalls . size ( ) == <NUM_LIT> ) { return false ; } for ( LoadInst * LI : AggrLoads ) { auto * SI = cast < StoreInst > ( * LI -> user_begin ( ) ) ; Value * SrcAddr = LI -> getOperand ( <NUM_LIT> ) ; Value * DstAddr = SI -> getOperand ( <NUM_LIT> ) ; unsigned NumLoads = DL . getTypeStoreSize ( LI -> getType ( ) ) ; ConstantInt * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ; createMemCpyLoopKnownSize ( SI , SrcAddr , DstAddr , CopyLen , LI -> getAlign ( ) , SI -> getAlign ( ) , LI -> isVolatile ( ) , SI -> isVolatile ( ) , TTI ) ; SI -> eraseFromParent ( ) ; LI -> eraseFromParent ( ) ; } for ( MemIntrinsic * MemCall : MemCalls ) { if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( MemCall ) ) { expandMemCpyAsLoop ( Memcpy , TTI ) ; } else if ( MemMoveInst * Memmove = dyn_cast < MemMoveInst > ( MemCall ) ) { expandMemMoveAsLoop ( Memmove ) ; } else if ( MemSetInst * Memset = dyn_cast < MemSetInst > ( MemCall ) ) { expandMemSetAsLoop ( Memset ) ; } MemCall -> eraseFromParent ( ) ; }


<s> <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> emit_insn ( gen_rtx_SET ( VOIDmode , cc , gen_rtx_COMPARE ( mode , op0 , op1 ) ) ) ; ret = gen_rtx_fmt_ee ( code , VOIDmode , cc , const0_rtx ) ; } s390_compare_emitted = NULL_RTX ;


DebuggerWorkGroupIDStackObjectIndices [ Dim ] = ObjectIdx ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS1 ( SDNode * Op , SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) { return SelectThumbAddrModeRI5 ( Op , N , <NUM_LIT> , Base , OffImm , Offset ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>32Target ( ) ) ;

RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ;


memcpy ( reg_alloc_order , nds32_reg_alloc_order_for_speed , sizeof ( nds32_reg_alloc_order_for_speed ) ) ;


<s> if ( RegNo == <NUM_LIT> ) return Error ( StartLoc , <STR_LIT> ) ; Parser . Lex ( ) ; return false ; } bool ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) override { return true ; } bool ParseDirective ( AsmToken DirectiveID ) override { return true ; } bool MatchAndEmitInstruction ( SMLoc IDLoc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) override { MCInst Inst ; SMLoc ErrorLoc ; switch ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ) { case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; default :


<s> unsigned <ISA_LIT>ABIInfo :: GetGlobalPtr ( ) const {


<s> static const MCPhysReg HvxQRDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

return DecodeRegisterClass ( Inst , RegNo , HvxQRDecoderTable ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , getEffectiveRelocModel ( CM , RM ) , CM , OL ) {


<s> void <ISA_LIT>InstPrinter :: printBitfieldInvMaskImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; uint32_t v = ~ MO . getImm ( ) ; int32_t lsb = countTrailingZeros ( v ) ; int32_t width = ( <NUM_LIT> - countLeadingZeros ( v ) ) - lsb ; assert ( MO . isImm ( ) && <STR_LIT> ) ; O << markup ( <STR_LIT> ) << '#' << lsb << markup ( <STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) << '#' << width << markup ( <STR_LIT> ) ;


<s> void onEndOfFile ( ) override { for ( const StringRef & Label : OperatorLabels ) if ( FreeLabels . find ( Label ) == FreeLabels . end ( ) ) Error ( SMLoc :: getFromPointer ( Label . begin ( ) ) , <STR_LIT> , SMRange ( SMLoc :: getFromPointer ( Label . begin ( ) ) , SMLoc :: getFromPointer ( Label . end ( ) ) ) ) ;


<s> mergeable_constant_section ( mode , align , <NUM_LIT> ) ;


<s> static bool is_power9_pairable_vec_type ( enum attr_type type ) { switch ( type ) { case TYPE_VECSIMPLE : case TYPE_VECCOMPLEX :


<s> case <STR_LIT> : if ( ! Subtarget -> hasFp256 ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) ) { unsigned NumElems = VT . getVectorNumElements ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS1 = Extract128BitVector ( LHS , <NUM_LIT> , DAG , dl ) ; SDValue LHS2 = Extract128BitVector ( LHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) . getSimpleVT ( ) ; EVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ; EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; unsigned ExtraNumElems = ExtraVT . getVectorNumElements ( ) ; ExtraVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ExtraEltVT , ExtraNumElems / <NUM_LIT> ) ; SDValue Extra = DAG . getValueType ( ExtraVT ) ; LHS1 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , Extra ) ; LHS2 = DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , Extra ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS1 , LHS2 ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op00 = Op0 . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op00 . getOpcode ( ) == <STR_LIT> ) { Tmp1 = LowerVectorIntExtend ( Op00 , Subtarget , DAG ) ; if ( Tmp1 . getNode ( ) ) { EVT ExtraEltVT = ExtraVT . getVectorElementType ( ) ; if ( ExtraEltVT == <STR_LIT> || ExtraEltVT == <STR_LIT> || ExtraEltVT == <STR_LIT> ) { SDValue Tmp1Op0 = Tmp1 . getOperand ( <NUM_LIT> ) ; assert ( Tmp1Op0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Tmp1Op0 . getOperand ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerF128Load ( Op , DAG ) ; case <STR_LIT> : return LowerF128Store ( Op , DAG ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: ADD_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SUB_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: MUL_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: DIV_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerF128Op ( Op , DAG , getLibcallName ( RTLIB :: SQRT_F128 ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG , * this , is64Bit ) ; case <STR_LIT> : return LowerFABS ( Op , DAG , isV9 ) ; case <STR_LIT> : return LowerF128_FPEXTEND ( Op , DAG , * this ) ; case <STR_LIT> : return LowerF128_FPROUND ( Op , DAG , * this ) ; case <STR_LIT> : case <STR_LIT> :


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) + MI . getDesc ( ) . getNumImplicitUses ( ) ; return MI . getNumOperands ( ) == NumOps ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> const SCEV * ptr = AddRec -> getStepRecurrence ( * p_SEL ) ;

if ( const SCEVSignExtendExpr * ptr2 = dyn_cast < SCEVSignExtendExpr > ( ptr ) ) ptr = ptr2 -> getOperand ( ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) : MCII ( MCII ) , Ctx ( Ctx ) {


<s> static const char * const names [ ] = { } ; assert ( ! isOverloaded ( IntrID ) && <STR_LIT> ) ; if ( IntrID < <STR_LIT> ) return <NUM_LIT> ; assert ( IntrID < <STR_LIT> && <STR_LIT> ) ; std :: string Result ( names [ IntrID - <STR_LIT> ] ) ; return Result ;


<s> for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( Op . isReg ( ) ) { Op . addRegOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImmModifier ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else if ( ! Op . isToken ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } } bool IsGFX10 = isGFX10 ( ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDMask ) ; if ( IsGFX10 ) addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDim , - <NUM_LIT> ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyUNorm ) ; if ( IsGFX10 ) addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDLC ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyGLC ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTySLC ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyR128A16 ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyTFE ) ; addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyLWE ) ; if ( ! IsGFX10 ) addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyDA ) ;

addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyD16 ) ;


<s> unsigned int value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( value < ( <NUM_LIT> << <NUM_LIT> ) && <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: parseHwregBody ( OperandInfoTy & HwReg , OperandInfoTy & Offset , OperandInfoTy & Width ) { using namespace llvm :: <STR_LIT> ; HwReg . Loc = getLoc ( ) ; if ( isToken ( AsmToken :: Identifier ) && ( HwReg . Id = getHwregId ( getTokenStr ( ) , getSTI ( ) ) ) != OPR_ID_UNKNOWN ) { HwReg . IsSymbolic = true ; lex ( ) ;

} else if ( ! parseExpr ( HwReg . Id , <STR_LIT> ) ) {


<s> if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align , GO ) ;


<s> bool has24BitE<ISA_LIT>Ops ( ) const { return is24Bit ( ) && hasE<ISA_LIT>Ops ( ) ;


<s> unsigned ConstCount ; BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = <NUM_LIT> , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , AMDGPU :: OpName :: bank_swizzle ) ; ValidSwizzle . push_back ( ( R600InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned > > TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = IGSrcs . back ( ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const R600InstrInfo :: BankSwizzle TransSwz [ ] = {


<s> Writemask |= <NUM_LIT> << Lane ; } if ( Writemask == <NUM_LIT> ) return ; std :: vector < SDValue > Ops ; Ops . push_back ( DAG . getTargetConstant ( Writemask , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Node -> getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( Node -> getOperand ( i ) ) ; Node = ( MachineSDNode * ) DAG . UpdateNodeOperands ( Node , Ops . data ( ) , Ops . size ( ) ) ; if ( Writemask == ( <NUM_LIT> << Lane ) ) { SDValue RC = DAG . getTargetConstant ( AMDGPU :: VReg_32RegClassID , <STR_LIT> ) ; SDNode * Copy = DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( ) , Users [ Lane ] -> getValueType ( <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) , RC ) ; DAG . ReplaceAllUsesWith ( Users [ Lane ] , Copy ) ; return ; } for ( unsigned i = <NUM_LIT> , Idx = AMDGPU :: sub0 ; i < <NUM_LIT> ; ++ i ) { SDNode * User = Users [ i ] ; if ( ! User ) continue ; SDValue Op = DAG . getTargetConstant ( Idx , <STR_LIT> ) ; DAG . UpdateNodeOperands ( User , User -> getOperand ( <NUM_LIT> ) , Op ) ;


<s> if ( SDWA9EncValues :: SRC_SGPR_MIN <= Val && Val <= SDWA9EncValues :: SRC_SGPR_MAX ) { return createSRegOperand ( getSgprClassId ( Width ) , Val - SDWA9EncValues :: SRC_SGPR_MIN ) ; } if ( SDWA9EncValues :: SRC_TTMP_MIN <= Val && Val <= SDWA9EncValues :: SRC_TTMP_MAX ) { return createSRegOperand ( getTtmpClassId ( Width ) , Val - SDWA9EncValues :: SRC_TTMP_MIN ) ; } return decodeSpecialReg32 ( Val - SDWA9EncValues :: SRC_SGPR_MIN ) ; } else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { return createRegOperand ( getVgprClassId ( Width ) , Val ) ;


<s> } case <STR_LIT> : case <STR_LIT> : { if ( ! mayIgnoreSignedZero ( N0 ) ) return SDValue ( ) ; SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue MHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) LHS = LHS . getOperand ( <NUM_LIT> ) ; else if ( MHS . getOpcode ( ) == <STR_LIT> ) MHS = MHS . getOperand ( <NUM_LIT> ) ; else MHS = DAG . getNode ( <STR_LIT> , SL , VT , MHS ) ; if ( RHS . getOpcode ( ) != <STR_LIT> ) RHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; else RHS = RHS . getOperand ( <NUM_LIT> ) ; SDValue Res = DAG . getNode ( Opc , SL , VT , LHS , MHS , RHS ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N0 . getOperand ( <NUM_LIT> ) ; SDValue RHS = N0 . getOperand ( <NUM_LIT> ) ; if ( isConstantFPZero ( RHS ) ) return SDValue ( ) ; SDValue NegLHS = DAG . getNode ( <STR_LIT> , SL , VT , LHS ) ; SDValue NegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; unsigned Opposite = inverseMinMax ( Opc ) ; SDValue Res = DAG . getNode ( Opposite , SL , VT , NegLHS , NegRHS , N0 -> getFlags ( ) ) ; if ( ! N0 . hasOneUse ( ) ) DAG . ReplaceAllUsesWith ( N0 , DAG . getNode ( <STR_LIT> , SL , VT , Res ) ) ; return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue CvtSrc = N0 . getOperand ( <NUM_LIT> ) ; if ( CvtSrc . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( Opc , SL , VT , CvtSrc . getOperand ( <NUM_LIT> ) ) ; } if ( ! N0 . hasOneUse ( ) ) return SDValue ( ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , SL , CvtSrc . getValueType ( ) , CvtSrc ) ; return DAG . getNode ( Opc , SL , VT , Neg , N0 -> getFlags ( ) ) ; } case <STR_LIT> : { SDValue CvtSrc = N0 . getOperand ( <NUM_LIT> ) ;


<s> for ( i = REG_CC - <NUM_LIT> ; i > REG_P7 ; i -- ) if ( all || regs_ever_live [ i ] || ( ! leaf_function_p ( ) && call_used_regs [ i ] ) ) { if ( i == REG_A0 || i == REG_A1 ) { rtx mem = gen_rtx_MEM ( PDImode , postinc1 ) ; MEM_VOLATILE_P ( mem ) = <NUM_LIT> ; emit_move_insn ( gen_rtx_REG ( PDImode , i ) , mem ) ; } else emit_move_insn ( gen_rtx_REG ( SImode , i ) , postinc ) ; } expand_epilogue_reg_restore ( spreg , all , true ) ;

emit_move_insn ( gen_rtx_REG ( SImode , REG_ASTAT ) , postinc ) ;


<s> assemble_align ( POINTER_SIZE ) ; if ( DEFAULT_ABI == ABI_V4 && ( TARGET_RELOCATABLE || flag_pic > <NUM_LIT> ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , symbol ) ;


<s> Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: Create ( Symbol , Kind , * Ctx ) ; if ( ! Offset ) return MCOperand :: CreateExpr ( MCSym ) ; assert ( Offset > <NUM_LIT> ) ; const MCConstantExpr * OffsetExpr = MCConstantExpr :: Create ( Offset , * Ctx ) ; const MCBinaryExpr * Add = MCBinaryExpr :: CreateAdd ( MCSym , OffsetExpr , * Ctx ) ;

return MCOperand :: CreateExpr ( Add ) ;


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result ; { Result = readInstruction16 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } { Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ;

if ( Result != MCDisassembler :: Fail ) {


<s> unsigned Vn = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vn |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned q = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ;

unsigned rotate = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ;


<s> int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) . addImm ( <STR_LIT> ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI . getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ; }


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) {


<s> if ( ! LocalSData && GVA -> hasLocalLinkage ( ) ) return false ;

if ( ! ExternSData && ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) ) ) return false ;


<s> case FCOND_SF : case FCOND_ST : return <STR_LIT> ; case FCOND_NGLE : case FCOND_GLE : return <STR_LIT> ; case FCOND_SEQ : case FCOND_SNE : return <STR_LIT> ; case FCOND_NGL : case FCOND_GL : return <STR_LIT> ; case FCOND_LT : case FCOND_NLT : return <STR_LIT> ; case FCOND_NGE :


<s> SDValue OneSubAC = DAG . getNode ( <STR_LIT> , DL , VT , OneSubA , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) , OneSubAC ) ;


<s> inline bool vgpr_1reg_mode_p ( machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ;

return ( mode == SImode || mode == SFmode || mode == HImode || mode == HFmode || mode == QImode || mode == BImode ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget . isABI_N64 ( ) ) return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ;

return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ;


<s> int fi = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; PMFI . addSinglePathFI ( fi ) ; } PMFI . startSinglePathExcessSpill ( ) ; int numAllocatablePRegs = getNumUnusedPRegs ( MF ) ; int numSpillSlotsReq = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < requiredPreds . size ( ) ; i ++ ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << requiredPreds [ i ] << <STR_LIT> ) ; int cnt = requiredPreds [ i ] - numAllocatablePRegs ; if ( cnt > <NUM_LIT> ) { numSpillSlotsReq += ( cnt + <NUM_LIT> ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << numAllocatablePRegs << <STR_LIT> << numSpillSlotsReq << <STR_LIT> ) ; for ( unsigned j = <NUM_LIT> ; j <= ( numSpillSlotsReq + <NUM_LIT> ) / ( <NUM_LIT> * TRI -> getSpillSize ( RC ) ) ; j ++ ) { int fi = MFI . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; PMFI . addSinglePathFI ( fi ) ; } if ( MFI . hasCalls ( ) ) { PMFI . startSinglePathCallSpill ( ) ; int fi = MFI . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ; PMFI . addSinglePathFI ( fi ) ;


<s> IFMapType :: iterator End = IFMap . end ( ) ; for ( IFMapType :: iterator I = IFMap . begin ( ) ; I != End ; ++ I ) { const IFListType & LL = I -> second ; RegisterSet TT ; for ( unsigned i = <NUM_LIT> , n = LL . size ( ) ; i < n ; ++ i ) TT . insert ( LL [ i ] . second ) ; for ( unsigned R = TT . find_first ( ) ; R ; R = TT . find_next ( R ) ) RemC [ R ] ++ ; AllRMs . insert ( TT ) ; } for ( unsigned R = AllRMs . find_first ( ) ; R ; R = AllRMs . find_next ( R ) ) { using use_iterator = MachineRegisterInfo :: use_nodbg_iterator ; using InstrSet = SmallSet < const MachineInstr * , <NUM_LIT> > ; InstrSet UIs ; use_iterator E = MRI -> use_nodbg_end ( ) ; for ( use_iterator I = MRI -> use_nodbg_begin ( R ) ; I != E ; ++ I ) UIs . insert ( I -> getParent ( ) ) ; unsigned C = UIs . size ( ) ;


<s> BasicBlockInfo ( ) : Offset ( <NUM_LIT> ) , Size ( <NUM_LIT> ) {


<s> unsigned VGPRLimit = getNumVGPRsAllowed ( STI . getMaxWavesPerCU ( ) ) ; unsigned VSLimit = SGPRLimit + VGPRLimit ; for ( regclass_iterator I = regclass_begin ( ) , E = regclass_end ( ) ; I != E ; ++ I ) { const TargetRegisterClass * RC = * I ;

unsigned NumSubRegs = std :: max ( ( int ) RC -> getSize ( ) / <NUM_LIT> , <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>InstrInfo :: removeBranchAndFlags ( MachineBasicBlock & MBB , int * BytesRemoved ) const { return removeBranchImpl ( MBB , BytesRemoved , true ) ;


<s> if ( call_cookie & CALL_SHORT ) return <NUM_LIT> ; if ( TARGET_LONG_CALLS ) { if ( flag_function_sections || DECL_SECTION_NAME ( current_function_decl ) ) return <NUM_LIT> ; } if ( current_file_function_operand ( sym_ref ) ) return <NUM_LIT> ;

return ( call_cookie & CALL_LONG ) || ENCODED_LONG_CALL_ATTR_P ( XSTR ( sym_ref , <NUM_LIT> ) ) || TARGET_LONG_CALLS ;


<s> static void get_scratch_register_on_entry ( struct scratch_reg * sr , unsigned int regno1 , unsigned long live_regs ) { int regno = - <NUM_LIT> ; sr -> saved = false ; if ( regno1 != LR_REGNUM && ( live_regs & ( <NUM_LIT> << LR_REGNUM ) ) != <NUM_LIT> ) regno = LR_REGNUM ; else { unsigned int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( regno1 != i && ( live_regs & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) { regno = i ; break ; } if ( regno < <NUM_LIT> ) { if ( regno1 == IP_REGNUM && IS_NESTED ( arm_current_func_type ( ) ) ) regno1 = <NUM_LIT> ; regno = ( regno1 == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; sr -> saved = REGNO_REG_SET_P ( df_get_live_out ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) , regno ) ; } } sr -> reg = gen_rtx_REG ( SImode , regno ) ; if ( sr -> saved ) { rtx addr = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; rtx insn = emit_set_insn ( gen_frame_mem ( SImode , addr ) , sr -> reg ) ;

rtx x = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> ) ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const {

OS << '$' << LowercaseString ( getRegisterName ( RegNo ) ) ;


<s> if ( TARGET_VFP_BASE && IS_VFP_REGNUM ( regno ) ) { if ( mode == DFmode || mode == DImode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode || mode == BFmode || mode == HImode || mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) ; if ( TARGET_HAVE_MVE ) return ( ( VALID_MVE_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) ) ; return false ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; }


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , RegState :: Kill ) . addReg ( DstHiReg , RegState :: Kill ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , RegState :: Kill ) . addReg ( DstLoReg , RegState :: Kill ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , RegState :: Kill ) . addReg ( DstHiReg , RegState :: Kill ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg ) ; auto MIROL = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIROL -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;

MIROL -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ;


<s> if ( HII -> isDeallocRet ( MI ) ) if ( DepReg == HRI -> getFrameRegister ( ) || DepReg == HRI -> getStackRegister ( ) ) return true ;


<s> Register BasePtr = TRI -> getBaseRegister ( ) ;

if ( STI . isTarget64BitILP32 ( ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ;


<s> LLT Ty = MRI . getType ( Src ) ; assert ( Ty . isScalar ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> ) ; APFloat C1Val ( APFloat :: IEEEdouble ( ) , <STR_LIT> ) ; APFloat C2Val ( APFloat :: IEEEdouble ( ) , <STR_LIT> ) ; auto C1 = MIRBuilder . buildFConstant ( Ty , C1Val ) ; auto CopySign = MIRBuilder . buildFCopysign ( Ty , C1 , Src ) ; auto Tmp1 = MIRBuilder . buildFAdd ( Ty , Src , CopySign ) ; auto Tmp2 = MIRBuilder . buildFSub ( Ty , Tmp1 , CopySign ) ; auto C2 = MIRBuilder . buildFConstant ( Ty , C2Val ) ; auto Fabs = MIRBuilder . buildFAbs ( Ty , Src ) ; auto Cond = MIRBuilder . buildFCmp ( CmpInst :: FCMP_OGT , LLT :: scalar ( <NUM_LIT> ) , Fabs , C2 ) ; MIRBuilder . buildSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Cond , Src , Tmp2 ) ;


<s> int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast < LoadSDNode > ( LdNode ) ; if ( ! LN0 || ! LN0 -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) || LN0 -> isVolatile ( ) ) return SDValue ( ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; unsigned Align = LN0 -> getAlignment ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NewAlign = TLI . getDataLayout ( ) -> getABITypeAlignment ( EltVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( NewAlign > Align || ! TLI . isOperationLegalOrCustom ( <STR_LIT> , EltVT ) ) return SDValue ( ) ;


<s> return has_attr ( ATTR_CRIT , decl ) ;


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) return ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ;

if ( VT == <STR_LIT> || VT == <STR_LIT> ) return ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ;


<s> getAssembler ( ) . setIsThumbFunc ( Func ) ; emitSymbolAttribute ( Func , MCSA_ELF_TypeFunction ) ;


<s> case MachineOperand :: MO_GlobalAddress : { O << Mang -> getValueName ( MO . getGlobal ( ) ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { const char * Sname = MO . getSymbolName ( ) ; if ( PAN :: getSymbolTag ( Sname ) == PAN :: LIBCALL ) { LibcallDecls . push_back ( Sname ) ; } O << Sname ; break ; } case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; return ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; }


<s> } else if ( MOImm . isFPImm ( ) ) { const ConstantFP * fpImm = MOImm . getFPImm ( ) ; APFloat apf = fpImm -> getValueAPF ( ) ;

uint64_t res = apf . bitcastToAPInt ( ) . getZExtValue ( ) ;


<s> Offset = SignExtend64 < <NUM_LIT> > ( Imm ) ; } return addOperand ( Inst , MCOperand :: createImm ( Offset ) ) ;


<s> emitCommonHeader ( ) ; OS . emitInt32 ( <STR_LIT> ) ; uint32_t TypeLen = <NUM_LIT> , StrLen ; for ( const auto & TypeEntry : TypeEntries ) TypeLen += TypeEntry -> getSize ( ) ; StrLen = StringTable . getSize ( ) ; OS . emitInt32 ( <NUM_LIT> ) ; OS . emitInt32 ( TypeLen ) ; OS . emitInt32 ( TypeLen ) ; OS . emitInt32 ( StrLen ) ; for ( const auto & TypeEntry : TypeEntries ) TypeEntry -> emitType ( OS ) ; uint32_t StringOffset = <NUM_LIT> ; for ( const auto & S : StringTable . getTable ( ) ) { OS . AddComment ( <STR_LIT> + std :: to_string ( StringOffset ) ) ; OS . emitBytes ( S ) ; OS . emitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ;

StringOffset += S . size ( ) + <NUM_LIT> ;


<s> next_tail = NEXT_INSN ( tail ) ; for ( insn = head ; insn != next_tail ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) ) continue ;

if ( mode == SFmode ) INSN_REGMODE_WEIGHT ( insn , mode ) = find_insn_regmode_weight ( insn , mode ) + <NUM_LIT> * find_insn_regmode_weight ( insn , DFmode ) ;


<s> else if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { if ( II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> ) ShiftAmountOpNum = <NUM_LIT> ; } if ( ShiftAmountOpNum == - <NUM_LIT> ) return false ; auto * Shuf = dyn_cast < ShuffleVectorInst > ( I -> getOperand ( ShiftAmountOpNum ) ) ; if ( Shuf && getSplatIndex ( Shuf -> getShuffleMask ( ) ) >= <NUM_LIT> && isVectorShiftByScalarCheap ( I -> getType ( ) ) ) { Ops . push_back ( & I -> getOperandUse ( ShiftAmountOpNum ) ) ; return true ;


<s> return ( ( struct u4 * ) ptr ) -> data ;


<s> dmema = XEXP ( dmem , <NUM_LIT> ) ; if ( GET_CODE ( dmema ) == LO_SUM ) dmema = force_reg ( Pmode , dmema ) ; if ( data_regs != NULL ) for ( i = <NUM_LIT> ; i < words ; ++ i ) ins_tmps [ i ] = gen_reg_rtx ( DImode ) ; st_tmp_1 = gen_reg_rtx ( DImode ) ; st_tmp_2 = gen_reg_rtx ( DImode ) ; if ( ofs != <NUM_LIT> ) dmem = adjust_address ( dmem , GET_MODE ( dmem ) , ofs ) ; st_addr_2 = change_address ( dmem , DImode , gen_rtx_AND ( DImode , plus_constant ( dmema , words * <NUM_LIT> - <NUM_LIT> ) , im8 ) ) ; set_mem_alias_set ( st_addr_2 , <NUM_LIT> ) ; st_addr_1 = change_address ( dmem , DImode , gen_rtx_AND ( DImode , dmema , im8 ) ) ; set_mem_alias_set ( st_addr_1 , <NUM_LIT> ) ; emit_move_insn ( st_tmp_2 , st_addr_2 ) ; emit_move_insn ( st_tmp_1 , st_addr_1 ) ; dreg = copy_addr_to_reg ( dmema ) ; if ( WORDS_BIG_ENDIAN ) emit_move_insn ( dreg , plus_constant ( dreg , <NUM_LIT> ) ) ; if ( data_regs != NULL ) { for ( i = words - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { if ( WORDS_BIG_ENDIAN ) { emit_insn ( gen_insql_be ( ins_tmps [ i ] , data_regs [ i ] , dreg ) ) ;

emit_insn ( gen_insxh ( data_regs [ i ] , data_regs [ i ] , i64 , dreg ) ) ;


<s> if ( MI . isInlineAsm ( ) ) return MJ . isInlineAsm ( ) || MJ . isBranch ( ) || MJ . isBarrier ( ) || MJ . isCall ( ) || MJ . isTerminator ( ) ; return false ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Start , End ; unsigned Size ; if ( ParseIntelMemoryOperandSize ( Size ) ) return true ; bool PtrInOperand = bool ( Size ) ; Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: LCurly ) ) return ParseRoundingModeOp ( Start , Operands ) ; unsigned RegNo = <NUM_LIT> ; if ( Tok . is ( AsmToken :: Identifier ) && ! ParseRegister ( RegNo , Start , End ) ) { if ( RegNo == <STR_LIT> ) return Error ( Start , <STR_LIT> ) ; if ( Tok . isNot ( AsmToken :: Colon ) ) { if ( PtrInOperand ) return Error ( Start , <STR_LIT> <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( RegNo , Start , End ) ) ; return false ; } if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) return Error ( Start , <STR_LIT> ) ; Start = Lex ( ) . getLoc ( ) ; } IntelExprStateMachine SM ; if ( ParseIntelExpression ( SM , End ) ) return true ; if ( isParsingMSInlineAsm ( ) ) RewriteIntelExpression ( SM , Start , Tok . getLoc ( ) ) ; int64_t Imm = SM . getImm ( ) ; const MCExpr * Disp = SM . getSym ( ) ; const MCExpr * ImmDisp = MCConstantExpr :: create ( Imm , getContext ( ) ) ; if ( Disp && Imm ) Disp = MCBinaryExpr :: createAdd ( Disp , ImmDisp , getContext ( ) ) ; if ( ! Disp ) Disp = ImmDisp ; if ( ! SM . isMemExpr ( ) && ! RegNo ) { if ( isParsingMSInlineAsm ( ) && SM . isOffsetOperator ( ) ) { const InlineAsmIdentifierInfo Info = SM . getIdentifierInfo ( ) ; if ( Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { Operands . push_back ( <STR_LIT> ( Disp , Start , End , SM . getSymName ( ) , Info . Var . Decl , Info . Var . IsGlobalLV ) ) ; return false ; } } Operands . push_back ( <STR_LIT> ( Disp , Start , End ) ) ; return false ; } StringRef ErrMsg ; unsigned BaseReg = SM . getBaseReg ( ) ;

unsigned IndexReg = SM . getIndexReg ( ) ;


<s> if ( suffix == 'q' ) return TFmode ; if ( suffix == 'w' ) return XFmode ; return VOIDmode ;


<s> if ( ! reader ) { reader = new LineReader ( filename ) ; } if ( reader -> fileName ( ) != filename ) { delete reader ;


<s> assert ( ( VT . getSizeInBits ( ) == <NUM_LIT> || VT . getSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && VT != <STR_LIT> ) A = BITCAST ( A , <STR_LIT> ) ; SDValue B = DAG -> getNode ( <STR_LIT> , dl , <STR_LIT> , DAG -> getConstant ( <STR_LIT> , <STR_LIT> ) , A , Constant ( immInByte * <NUM_LIT> , <STR_LIT> ) ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

if ( MFI -> getStackProtectorIndex ( ) > <NUM_LIT> ) return StackSizeInBytes >= <NUM_LIT> ;


<s> bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI1 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg ) ; MI1 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI2 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI2 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI3 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg ) ;

if ( ImpIsDead ) MI3 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> bool <ISA_LIT>LateCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ;

AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ;


<s> const MCInstrDesc & NewDesc = TII -> get ( NewOpc ) ; MachineInstrBuilder MIB = BuildMI ( MBB , Br , DL , NewDesc ) ; for ( unsigned I = <NUM_LIT> , E = Br -> getDesc ( ) . getNumOperands ( ) ; I < E ; ++ I ) { MachineOperand & MO = Br -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) { assert ( MO . isMBB ( ) && <STR_LIT> ) ; break ; }


for ( const BasicBlock & BB : * F ) IDMap [ & BB ] = ++ Counter ;


<s> Pass * llvm :: createAMDGPUStructurizeCFGPass ( ) { return new AMDGPUStructurizeCFG ( ) ;


<s> if ( Subtarget . isUsingPCRelativeCalls ( ) ) return false ; if ( DisableSCO && ! TailCallOpt ) return false ; if ( isVarArg ) return false ; auto & Caller = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller . getCallingConv ( ) , CalleeCC ) ) return false ; if ( any_of ( Ins , [ ] ( const <STR_LIT> & IA ) { return IA . Flags . isByVal ( ) ; } ) ) return false ; if ( any_of ( Outs , [ ] ( const <STR_LIT> & OA ) { return OA . Flags . isByVal ( ) ; } ) ) return false ; if ( Caller . getCallingConv ( ) != CalleeCC && needStackSlotPassParameters ( Subtarget , Outs ) ) return false ; if ( ! isFunctionGlobalAddress ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) return false ; if ( ! callsShareTOCBase ( & Caller , Callee , getTargetMachine ( ) ) ) return false ; if ( CalleeCC == CallingConv :: Fast && TailCallOpt ) return true ; if ( DisableSCO ) return false ; if ( ! hasSameArgumentList ( & Caller , CS ) && needStackSlotPassParameters ( Subtarget , Outs ) ) { return false ; } return true ;


<s> void lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand lowerOperand ( const MachineOperand & MO ) const ; const MCExpr * getExpr ( const MachineOperand & MO , MCSymbolRefExpr :: VariantKind Kind ) const ;


<s> auto MIB = MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( ret ) . addUse ( GR -> get<ISA_LIT>TypeID ( retTy ) ) . addImm ( static_cast < uint32_t > ( ExtInstSet :: OpenCL_std ) ) . addImm ( extInstID ) ; for ( const auto & arg : args ) {


<s> if ( ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_NO ) || ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_NO && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( type == TYPE_STORE && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( ( type == TYPE_FPLOAD || type == TYPE_FPSTORE ) && get_attr_update ( insn ) == UPDATE_YES ) || ( type == TYPE_CR_LOGICAL && get_attr_cr_logical_3op ( insn ) == CR_LOGICAL_3OP_YES ) || ( type == TYPE_EXTS && get_attr_dot ( insn ) == DOT_YES ) || ( type == TYPE_SHIFT && get_attr_dot ( insn ) == DOT_YES && get_attr_var_shift ( insn ) == VAR_SHIFT_NO ) || ( type == TYPE_MUL && get_attr_dot ( insn ) == DOT_YES ) || type == TYPE_DIV || ( type == TYPE_INSERT && get_attr_size ( insn ) == SIZE_32 ) ) return true ; } return false ;


<s> for ( const MachineOperand & Op : MI . operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; unsigned R = Op . getReg ( ) ;

if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ;


<s> static bool ix86_frame_pointer_required ( void ) { if ( cfun -> machine -> accesses_prev_frame ) return true ;

if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ;


<s> if ( ArgTy -> isVectorTy ( ) ) return std :: min ( DL . getABITypeAlignment ( ArgTy ) , <NUM_LIT> ) ; return DL . getABITypeAlignment ( ArgTy ) ;


<s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const {

if ( Subtarget . hasSPE ( ) && VT == <STR_LIT> ) return <STR_LIT> ;


<s> static bool hasIndex ( const MachineInstr & MI , const MCRegisterInfo & RI ) {

for ( const MachineOperand & Op : MI . explicit_operands ( ) ) if ( isIndex ( Op , RI ) ) return true ;


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { switch ( MO . getTargetFlags ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : break ;


return default_scalar_mode_supported_p ( mode ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , StringRef TT ) {


<s> if ( ! HasFp256 || ! VT . is256BitVector ( ) ) return false ; unsigned HalfSize = VT . getVectorNumElements ( ) / <NUM_LIT> ; bool MatchA = false , MatchB = false ; for ( unsigned Half = <NUM_LIT> ; Half != <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , HalfSize , Half * HalfSize ) ) { MatchA = true ; break ; } }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == - <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Convert ; } if ( MI -> isCall ( ) || MI -> mayStore ( ) ) return Exit ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned int Reg = MO . getReg ( ) ; if ( ! RegInfo . isPhysicalRegister ( Reg ) ) continue ;

if ( RegInfo . regsOverlap ( Reg , RegInfo . getStackRegister ( ) ) ) return Exit ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> Value * Simplifier :: simplify ( Context & C ) { WorkListType Q ; Q . push_back ( C . Root ) ; unsigned Count = <NUM_LIT> ; const unsigned Limit = SimplifyLimit ; while ( ! Q . empty ( ) ) { if ( Count ++ >= Limit ) break ; Instruction * U = dyn_cast < Instruction > ( Q . pop_front_val ( ) ) ; if ( ! U || U -> getParent ( ) || ! C . Used . count ( U ) ) continue ; bool Changed = false ; for ( Rule & R : Rules ) { Value * W = R ( U , C . Ctx ) ; if ( ! W ) continue ; Changed = true ; C . record ( W ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( insn == NULL ) continue ; insn = prev_active_insn ( insn ) ; if ( insn == NULL || ! can_throw_internal ( insn ) ) continue ; for ( next = NEXT_INSN ( insn ) ; next != NULL ; next = NEXT_INSN ( next ) ) if ( NOTE_P ( next ) && ( NOTE_KIND ( next ) == NOTE_INSN_VAR_LOCATION || NOTE_KIND ( next ) == NOTE_INSN_CALL_ARG_LOCATION ) ) insn = next ; else break ;

emit_insn_after ( gen_nops ( const1_rtx ) , insn ) ;


<s> SelectRoot ( * CurDAG ) ; CurDAG -> RemoveDeadNodes ( ) ;


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == <NUM_LIT> ) return true ;


<s> bool hasFastPartialYMMorZMMWrite ( ) const { return HasFastPartialYMMorZMMWrite ;


<s> if ( ! isValidIndexedLoad ( LD ) ) return false ; MVT VT = LD -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned Opcode = <NUM_LIT> ; switch ( VT . SimpleTy ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default :


<s> xop [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> * ( words - <NUM_LIT> ) ) ; xop [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , xop ) ; return <STR_LIT> ; } else { for ( j = <NUM_LIT> ; j < words ; j ++ ) if ( j != i ) { xop [ <NUM_LIT> ] = GEN_INT ( j * <NUM_LIT> ) ; xop [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ;

xop [ <NUM_LIT> ] = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + j ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFNEG ( SDValue Op , SelectionDAG & DAG ) const { LLVMContext * Context = DAG . getContext ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ;

else C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , Ctx ( ctx ) {


<s> static void v850_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx mem , fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ; emit_move_insn ( mem , fnaddr ) ;


<s> static void rl78_start_function ( FILE * file , HOST_WIDE_INT hwi_local ATTRIBUTE_UNUSED ) { int i ; if ( cfun -> machine -> framesize == <NUM_LIT> ) return ; fprintf ( file , <STR_LIT> ) ; if ( cfun -> machine -> framesize_regs ) { fprintf ( file , <STR_LIT> , cfun -> machine -> framesize_regs ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( cfun -> machine -> need_to_push [ i ] ) fprintf ( file , <STR_LIT> , word_regnames [ i * <NUM_LIT> ] ) ; fprintf ( file , <STR_LIT> ) ; } if ( frame_pointer_needed ) fprintf ( file , <STR_LIT> ) ;

if ( cfun -> machine -> framesize_locals ) fprintf ( file , <STR_LIT> , cfun -> machine -> framesize_locals , cfun -> machine -> framesize_locals == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue BAGOTOffset = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue BALOOffset = DAG . getBlockAddress ( BA , <STR_LIT> , true , <STR_LIT> ) ; SDValue Load = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , BAGOTOffset , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BALOOffset ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load , Lo ) ; }


<s> if ( startswith ( section_name , <STR_LIT> ) ) return true ; if ( startswith ( section_name , <STR_LIT> ) ) return true ; return false ; } size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ;

if ( size > <NUM_LIT> && size <= g_switch_value ) return true ;


<s> SrcReg = get512BitSuperRegister ( SrcReg ) ; return <STR_LIT> ; } if ( MaskRegClassContains ( DestReg ) && MaskRegClassContains ( SrcReg ) ) return <STR_LIT> ; if ( MaskRegClassContains ( DestReg ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { SrcReg = get<ISA_LIT>SubSuperRegister ( SrcReg , <STR_LIT> ) ; return <STR_LIT> ; } if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && MaskRegClassContains ( SrcReg ) ) { DestReg = get<ISA_LIT>SubSuperRegister ( DestReg , <STR_LIT> ) ; return <STR_LIT> ; }


<s> rtx label2 = gen_label_rtx ( ) ; rtx tmp = gen_reg_rtx ( XFmode ) ; rtx tmp2 = gen_reg_rtx ( XFmode ) ; emit_insn ( gen_absxf2 ( tmp , op1 ) ) ; emit_insn ( gen_cmpxf ( tmp , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( <STR_LIT> , XFmode ) , XFmode ) ) ) ; emit_jump_insn ( gen_bge ( label1 ) ) ; emit_move_insn ( tmp2 , standard_80387_constant_rtx ( <NUM_LIT> ) ) ;


<s> assert ( AsmPrinterCtor && <STR_LIT> ) ;

if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( Out , * this , Fast ) ) ;


<s> } if ( IsVALU ) { unsigned Opc = IsAdd ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) } ) ; } else {

unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> } MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; bool IsLegalInsert = Subtarget . is64Bit ( ) || Val . getValueType ( ) != <STR_LIT> ; if ( ! IsLegalInsert && isa < ConstantSDNode > ( Val ) ) { const auto * CVal = cast < ConstantSDNode > ( Val ) ; if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) { IsLegalInsert = true ; Val = DAG . getConstant ( CVal -> getSExtValue ( ) , DL , <STR_LIT> ) ; } } SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue ValInVec ; if ( IsLegalInsert ) { unsigned Opc = VecVT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; if ( isNullConstant ( Idx ) ) { Vec = DAG . getNode ( Opc , DL , ContainerVT , Vec , Val , VL ) ; if ( ! VecVT . isFixedLengthVector ( ) ) return Vec ; return convertFromScalableVector ( VecVT , Vec , DAG , Subtarget ) ; } ValInVec = DAG . getNode ( Opc , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , Val , VL ) ; } else { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ;

SDValue ValLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val , Zero ) ;


<s> bool nds32_n13_last_load_to_e2_p ( rtx_insn * producer , rtx_insn * consumer ) {

rtx last_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT> ) ;


<s> if ( Flags == <STR_LIT> ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) == FlagSet ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) == FlagSet ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) == FlagSet ) return <STR_LIT> ; for ( auto FlagSet : AddrModesMap . at ( <STR_LIT> ) ) if ( ( Flags & FlagSet ) == FlagSet ) return <STR_LIT> ; return <STR_LIT> ;


<s> DP << <STR_LIT> << getDescription ( ) << <STR_LIT> << Fn . getName ( ) ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const DataLayout & DL ) : TargetSelectionDAGInfo ( & DL ) {


<s> unsigned <ISA_LIT>FastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill ) {

const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? & <STR_LIT> :


<s> if ( ST -> hasMVEIntegerOps ( ) && VT . getScalarSizeInBits ( ) == <NUM_LIT> ) return LowerEXTRACT_VECTOR_ELT_i1 ( Op , DAG , ST ) ; if ( Op . getValueType ( ) == <STR_LIT> && Vec . getScalarValueSizeInBits ( ) < <NUM_LIT> ) { SDLoc dl ( Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Lane ) ; } return Op ;


<s> bool Thumb2ITBlock :: MoveCopyOutOfITBlock ( MachineInstr * MI , <STR_LIT> CC , <STR_LIT> OCC , RegisterSet & Defs , RegisterSet & Uses ) { if ( ! isCopy ( MI ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Uses . count ( DstReg ) || Defs . count ( SrcReg ) ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MI -> hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineBasicBlock :: iterator I = MI ;


<s> void <ISA_LIT>TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const {


<s> B . setInstrAndDebugLoc ( MI ) ; ApplyFn ( B , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> assert ( Size && <STR_LIT> ) ; const GlobalValue * GV = dyn_cast < GlobalValue > ( CV -> stripPointerCasts ( true ) ) ; assert ( GV && <STR_LIT> ) ;

const MCExpr * E = MCSymbolRefExpr :: create ( Get<ISA_LIT>GVSymbol ( GV , <STR_LIT> ) , ( Subtarget -> isTargetELF ( ) ? MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : MCSymbolRefExpr :: VK_None ) , OutContext ) ;


<s> case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SBits = <NUM_LIT> ; break ; } Binary |= SBits << <NUM_LIT> ; if ( SOpc == <STR_LIT> ) return Binary ;

return Binary | <STR_LIT> ( MO1 . getImm ( ) ) << <NUM_LIT> ;


<s> if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return Value > <NUM_LIT> && Value <= <NUM_LIT> ;


<s> PrintRegister ( Register R , const TargetRegisterInfo & I ) : Reg ( R ) , TRI ( I ) {


<s> unsigned i = <NUM_LIT> ; for ( const MDCompileUnit * DIUnit : DbgFinder . compile_units ( ) ) { StringRef Filename = DIUnit -> getFilename ( ) ; StringRef Dirname = DIUnit -> getDirectory ( ) ; SmallString < <NUM_LIT> > FullPathName = Dirname ; if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) { sys :: path :: append ( FullPathName , Filename ) ; Filename = FullPathName ; } if ( filenameMap . find ( Filename ) != filenameMap . end ( ) ) continue ;


<s> <ISA_LIT>MCCodeEmitter ( MCContext & ctx ) : Ctx ( ctx ) {


<s> case <STR_LIT> : return LowerFP_TO_UINT ( Op , DAG ) ; case <STR_LIT> : return LowerFABS ( Op , DAG ) ; case <STR_LIT> : return LowerFNEG ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerFGETSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ ( Op , DAG ) ; case <STR_LIT> : return LowerCTLZ_ZERO_UNDEF ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI , unsigned UncondBr ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( STI ) , UncondBrOpc ( UncondBr ) {


<s> SrcReg = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( KillSrc ) ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> << <NUM_LIT> ) . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ;


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return expandLoadImm ( Inst , IDLoc , Instructions ) ;


<s> MVT DataDwordVT = NumDataDwords == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ( <STR_LIT> , NumDataDwords ) ; MVT MaskPopVT = MaskPopDwords == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ( <STR_LIT> , MaskPopDwords ) ; SDValue Data ( Result , <NUM_LIT> ) ; SDValue TexFail ; if ( DMaskPop > <NUM_LIT> && Data . getValueType ( ) != MaskPopVT ) { SDValue ZeroIdx = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( MaskPopVT . isVector ( ) ) { Data = DAG . getNode ( <STR_LIT> , DL , MaskPopVT , SDValue ( Result , <NUM_LIT> ) , ZeroIdx ) ; } else { Data = DAG . getNode ( <STR_LIT> , DL , MaskPopVT , SDValue ( Result , <NUM_LIT> ) , ZeroIdx ) ; } } if ( DataDwordVT . isVector ( ) ) Data = padEltsToUndef ( DAG , DL , DataDwordVT , Data , NumDataDwords - MaskPopDwords ) ; if ( IsD16 ) Data = adjustLoadValueTypeImpl ( Data , ReqRetVT , DL , DAG , Unpacked ) ; EVT LegalReqRetVT = ReqRetVT ; if ( ! ReqRetVT . isVector ( ) ) { if ( ! Data . getValueType ( ) . isInteger ( ) ) Data = DAG . getNode ( <STR_LIT> , DL , Data . getValueType ( ) . changeTypeToInteger ( ) , Data ) ; Data = DAG . getNode ( <STR_LIT> , DL , ReqRetVT . changeTypeToInteger ( ) , Data ) ; } else { if ( ( ReqRetVT . getVectorNumElements ( ) % <NUM_LIT> ) == <NUM_LIT> && ReqRetVT . getVectorElementType ( ) . getSizeInBits ( ) == <NUM_LIT> ) { LegalReqRetVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ReqRetVT . getVectorElementType ( ) , ReqRetVT . getVectorNumElements ( ) + <NUM_LIT> ) ; } }

Data = DAG . getNode ( <STR_LIT> , DL , LegalReqRetVT , Data ) ;


MDs . insert ( MDs . end ( ) , FunctionMDs . begin ( ) + R . First , FunctionMDs . begin ( ) + R . Last ) ;


<s> SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ;

PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ;


<s> void s390_output_pool_entry ( rtx exp , machine_mode mode , unsigned int align ) { switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : case MODE_DECIMAL_FLOAT : gcc_assert ( GET_CODE ( exp ) == CONST_DOUBLE ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( exp ) , as_a < scalar_float_mode > ( mode ) , align ) ; break ; case MODE_INT : assemble_integer ( exp , GET_MODE_SIZE ( mode ) , align , <NUM_LIT> ) ;


<s> MoveReg = <STR_LIT> ; } if ( CR2Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( RestoreOp ) , <STR_LIT> ) . addReg ( MoveReg , getKillRegState ( ! CR3Spilled && ! CR4Spilled ) ) ) ; if ( CR3Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( RestoreOp ) , <STR_LIT> ) . addReg ( MoveReg , getKillRegState ( ! CR4Spilled ) ) ) ; if ( CR4Spilled ) MBB . insert ( MI , BuildMI ( * MF , DL , TII . get ( RestoreOp ) , <STR_LIT> ) . addReg ( MoveReg , getKillRegState ( true ) ) ) ;


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( const Triple & TT ) { if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ; return make_unique < TargetLoweringObjectFileMachO > ( ) ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MI = MBB . getFirstTerminator ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int StackSize = int ( MFI . getStackSize ( ) ) ; const TargetRegisterClass * ScratchRC = Is24Bit ? & <STR_LIT> : & <STR_LIT> ; TargetRegisterClass :: iterator ScratchReg = ScratchRC -> begin ( ) ; for ( ; MI -> readsRegister ( TRI -> getSubReg ( * ScratchReg , <STR_LIT> ) , TRI ) ; ++ ScratchReg ) assert ( ScratchReg != ScratchRC -> end ( ) && <STR_LIT> ) ; assert ( ( hasFP ( MF ) || * ScratchReg != TRI -> getFrameRegister ( MF ) ) && <STR_LIT> ) ; while ( MI != MBB . begin ( ) ) if ( ! ( -- MI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) { ++ MI ; break ; } while ( MI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { StackSize += SlotSize ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { bool Is24Bit = Opc == <STR_LIT> ; unsigned Reg = PI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PI == MBB . begin ( ) ) break ; MachineBasicBlock :: iterator AI = std :: prev ( PI ) ; Opc = AI -> getOpcode ( ) ; if ( AI == MBB . begin ( ) || Opc != ( Is24Bit ? <STR_LIT> : <STR_LIT> ) || AI -> getOperand ( <NUM_LIT> ) . getReg ( ) != Reg || AI -> getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ) break ; MachineBasicBlock :: iterator LI = std :: prev ( AI ) ; Opc = LI -> getOpcode ( ) ; if ( Opc != ( Is24Bit ? <STR_LIT> : <STR_LIT> ) || LI -> getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ) break ; StackSize += LI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; LI -> removeFromParent ( ) ; AI -> removeFromParent ( ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {


<s> PatchPointOpers Opers ( & MI ) ; int64_t CallTarget = Opers . getCallTarget ( ) . getImm ( ) ; unsigned EncodedBytes = <NUM_LIT> ; if ( CallTarget ) { assert ( ( CallTarget & <NUM_LIT> ) == CallTarget && <STR_LIT> ) ; Register ScratchReg = MI . getOperand ( Opers . getNextScratchIdx ( ) ) . getReg ( ) ; EncodedBytes = <NUM_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( ( CallTarget >> <NUM_LIT> ) & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) . addImm ( <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = Opers . getNumPatchBytes ( ) ;

assert ( NumBytes >= EncodedBytes && <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( static_cast < uint32_t > ( OldOpnd -> getImm ( ) ) == std :: numeric_limits < uint32_t > :: max ( ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : if ( static_cast < int32_t > ( OldOpnd -> getImm ( ) ) == std :: numeric_limits < int32_t > :: max ( ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> :

if ( static_cast < int32_t > ( OldOpnd -> getImm ( ) ) == std :: numeric_limits < int32_t > :: min ( ) ) return true ;


<s> LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , Reloc :: Static , CodeModel :: Small , OL ) , TLOF ( std :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , subtarget ( TT , std :: string ( CPU ) , std :: string ( FS ) , * this ) {


<s> while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= ExpandMI ( MBB , MBBI ) ; MBBI = NMBBI ; } return Modified ;


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( MO . readsReg ( ) || MI -> readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else { if ( MI -> readsRegister ( Reg , TRI ) ) return <NUM_LIT> ; } return <NUM_LIT> ;


<s> <ISA_LIT>ExpandISEL ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ExpandISELPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveModuleOddSPReg ( ) { <ISA_LIT>TargetStreamer :: emitDirectiveModuleOddSPReg ( ) ;

OS << <STR_LIT> << ( ABIFlagsSection . OddSPReg ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ;


<s> unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;

Inst . addOperand ( MCOperand :: createReg ( Base ) ) ;


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ;

if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> It ++ ; for ( ; It != E ; ++ It ) { if ( It -> modifiesRegister ( Reg , & getRegisterInfo ( ) ) && ( & * It ) != & DefMI ) return false ; else if ( It -> killsRegister ( Reg , & getRegisterInfo ( ) ) && ( & * It ) != & DefMI ) IsFwdFeederRegKilled = true ; if ( ( & * It ) == & DefMI ) break ; } assert ( ( & * It ) == & DefMI && <STR_LIT> ) ; if ( DefMI . modifiesRegister ( Reg , & getRegisterInfo ( ) ) ) return KillDefMI ;


<s> if ( MBBI != MBB . begin ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { MachineBasicBlock :: iterator PrevI = std :: prev ( MBBI ) ; while ( PrevI -> isDebugValue ( ) && PrevI != MBB . begin ( ) ) -- PrevI ; MachineInstr * PrevMI = PrevI ; unsigned Opcode = PrevMI -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MachineOperand & MO = PrevMI -> getOperand ( PrevMI -> getNumOperands ( ) - <NUM_LIT> ) ; if ( MO . getReg ( ) != <STR_LIT> ) return false ; unsigned NewOpc = ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; assert ( ( ( isThumb2 && Opcode == <STR_LIT> ) || Opcode == <STR_LIT> ) && <STR_LIT> ) ; PrevMI -> setDesc ( TII -> get ( NewOpc ) ) ; MO . setReg ( <STR_LIT> ) ; PrevMI -> copyImplicitOps ( * MBB . getParent ( ) , * MBBI ) ; MBB . erase ( MBBI ) ; return true ;


<s> number_of_regs_before_varargs = * args_so_far + mcore_num_arg_regs ( mode , type ) ; number_of_regs_before_varargs = * args_so_far ; if ( number_of_regs_before_varargs > NPARM_REGS ) number_of_regs_before_varargs = NPARM_REGS ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> case E_V4SFmode : return ( gen_aarch64_frecpsv4sf ) ; case E_DFmode : return ( gen_aarch64_frecpsdf ) ; case E_V2DFmode : return ( gen_aarch64_frecpsv2df ) ; default : gcc_unreachable ( ) ; }


<s> Result = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , Op . getValueType ( ) , Chain , Jump , Cond ) ;


<s> return { Ops . first . getValueType ( ) . getSimpleVT ( ) , Ops . second . getValueType ( ) . getSimpleVT ( ) } ;


<s> PM . add ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . hoistCommonInsts ( true ) ) ) ; } ) ; Builder . addExtension ( PassManagerBuilder :: EP_ModuleOptimizerEarly , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { PM . add ( create<ISA_LIT>AdjustOpt ( ) ) ;


<s> if ( MRI -> isSSA ( ) ) { for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { if ( ! MI . getOperand ( i ) . isReg ( ) ) continue ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) continue ; unsigned TrueReg = TRI -> lookThruCopyLike ( Reg , MRI ) ; if ( TargetRegisterInfo :: isVirtualRegister ( TrueReg ) ) { DefMI = MRI -> getVRegDef ( TrueReg ) ; if ( DefMI -> getOpcode ( ) == <STR_LIT> || DefMI -> getOpcode ( ) == <STR_LIT> ) { OpNoForForwarding = i ; break ; } } } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! instrHasImmForm ( MI , III , true ) && ! ConvertibleImmForm ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { MachineBasicBlock :: reverse_iterator E = MI . getParent ( ) -> rend ( ) , It = MI ; It ++ ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) Reg = Reg - <STR_LIT> + <STR_LIT> ;


<s> insn -> reader = reader ; insn -> readerArg = readerArg ; insn -> dlog = logger ; insn -> dlogArg = loggerArg ; insn -> startLocation = startLoc ; insn -> readerCursor = startLoc ; insn -> mode = mode ; insn -> numImmediatesConsumed = <NUM_LIT> ; if ( readPrefixes ( insn ) || readOpcode ( insn ) || getID ( insn ) || insn -> instructionID == <NUM_LIT> || readOperands ( insn ) ) return - <NUM_LIT> ;

insn -> length = insn -> readerCursor - insn -> startLocation ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> if ( I . getUse ( ) . get ( ) != Value ) continue ; if ( I -> getOpcode ( ) == Opcode ) return * I ; } return <NUM_LIT> ;


<s> assert ( VecWidth == <NUM_LIT> && <STR_LIT> ) ; uint64_t Index = N -> getConstantOperandVal ( <NUM_LIT> ) ; MVT VecVT = N -> getSimpleValueType ( <NUM_LIT> ) ; uint64_t InsertIdx = ( Index * VecVT . getScalarSizeInBits ( ) ) / VecWidth ; assert ( ( InsertIdx == <NUM_LIT> || InsertIdx == <NUM_LIT> ) && <STR_LIT> ) ;

return getI8Imm ( InsertIdx ? <NUM_LIT> : <NUM_LIT> , DL ) ;


<s> TargetPassConfig * Tile64TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Tile64PassConfig ( this , PM ) ;


<s> int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ;

MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ;


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) {


<s> if ( consumer . the_registerFile != e_rf_i ) return false ; bool producerPartOfE1Bypass = ( ( producer . the_slotID == e_issue_slot_spu ) && ( producer . the_opCode == <NUM_LIT> ) ) || ( ( producer . the_slotID == e_issue_slot_spu ) && ( producer . the_opCode == <NUM_LIT> ) ) || ( ( producer . the_slotID == e_issue_slot_spu ) && ( producer . the_opCode == <NUM_LIT> ) ) || ( ( producer . the_slotID == e_issue_slot_spu ) && ( producer . the_opCode == <NUM_LIT> ) ) || ( ( producer . the_slotID == e_issue_slot_load ) && ( producer . the_opCode == <NUM_LIT> ) ) || ( ( producer . the_slotID == e_issue_slot_load ) && ( producer . the_opCode == <NUM_LIT> ) ) || ( ( producer . the_slotID == e_issue_slot_store ) && ( producer . the_opCode == <NUM_LIT> ) ) ;

bool consumerPartOfE1Bypass = ( ( consumer . the_slotID == e_issue_slot_load ) ) || ( ( consumer . the_slotID == e_issue_slot_store ) ) || ( ( consumer . the_slotID == e_issue_slot_spu ) && ( consumer . the_opCode == <NUM_LIT> ) ) || ( ( consumer . the_slotID == e_issue_slot_spu ) && ( consumer . the_opCode == <NUM_LIT> ) ) || ( ( consumer . the_slotID == e_issue_slot_spu ) && ( consumer . the_opCode == <NUM_LIT> ) ) || ( ( consumer . the_slotID == e_issue_slot_spu ) && ( consumer . the_opCode == <NUM_LIT> ) ) || ( ( consumer . the_slotID == e_issue_slot_spu ) && ( consumer . the_opCode == <NUM_LIT> ) ) ;


<s> case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> break ; case k_PostIndexRegister : OS << <STR_LIT> << ( PostIdxReg . isAdd ? <STR_LIT> : <STR_LIT> ) << PostIdxReg . RegNum ; if ( PostIdxReg . ShiftTy != <STR_LIT> ) OS << <STR_LIT> ( PostIdxReg . ShiftTy ) << <STR_LIT> << PostIdxReg . ShiftImm ; OS << <STR_LIT> ; break ; case k_ProcIFlags : { OS << <STR_LIT> ; unsigned IFlags = getProcIFlags ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) OS << <STR_LIT> ( <NUM_LIT> << i ) ; OS << <STR_LIT> ; break ; } case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_ShifterImmediate : OS << <STR_LIT> << ( ShifterImm . isASR ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ShifterImm . Imm << <STR_LIT> ; break ; case k_ShiftedRegister : OS << <STR_LIT> << RegShiftedReg . SrcReg << <STR_LIT> << <STR_LIT> ( RegShiftedReg . ShiftTy ) << <STR_LIT> << RegShiftedReg . ShiftReg << <STR_LIT> ; break ; case k_ShiftedImmediate : OS << <STR_LIT> << RegShiftedImm . SrcReg << <STR_LIT> << <STR_LIT> ( RegShiftedImm . ShiftTy ) << <STR_LIT> << RegShiftedImm . ShiftImm << <STR_LIT> ; break ; case k_RotateImmediate : OS << <STR_LIT> << <STR_LIT> << ( RotImm . Imm * <NUM_LIT> ) << <STR_LIT> ; break ; case k_ModifiedImmediate : OS << <STR_LIT> << ModImm . Bits << <STR_LIT> << ModImm . Rot << <STR_LIT> ; break ; case k_BitfieldDescriptor : OS << <STR_LIT> << <STR_LIT> << Bitfield . LSB << <STR_LIT> << Bitfield . Width << <STR_LIT> ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : { OS << <STR_LIT> ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( SmallVectorImpl < unsigned > :: const_iterator I = RegList . begin ( ) , E = RegList . end ( ) ; I != E ; ) { OS << * I ; if ( ++ I < E ) OS << <STR_LIT> ;


<s> MCAsmInfo * MAI ; if ( TheTriple . isOSBinFormatMachO ( ) ) { if ( is64Bit ) MAI = new <ISA_LIT>_64MCAsmInfoDarwin ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . isOSBinFormatELF ( ) ) { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } else if ( TheTriple . isWindowsMSVCEnvironment ( ) || TheTriple . isWindowsCoreCLREnvironment ( ) ) { if ( Options . getAssemblyLanguage ( ) . equals_lower ( <STR_LIT> ) ) MAI = new <ISA_LIT>MCAsmInfoMicrosoftMASM ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . isOSCygMing ( ) || TheTriple . isWindowsItaniumEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ;


<s> MCInst TmpInst0 ; MCInstLowering . Lower ( & * I , TmpInst0 ) ; OutStreamer -> EmitInstruction ( TmpInst0 , getSubtargetInfo ( ) ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ;


<s> const <ISA_LIT>TargetLowering * getTLI ( ) const { return TLI ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getMaxDisp ( ) , U . NegOk ) ) {

DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ;


<s> break ; case SH_EXTRACT : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_INSERT : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_NOSWAP_LD : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_NOSWAP_ST : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_SPLAT : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_XXPERMDI : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; case SH_COPYWIDEN : DEBUG ( dbgs ( ) << <STR_LIT> ) ; break ; } } if ( SwapVector [ EntryIdx ] . WebRejected ) DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( SwapVector [ EntryIdx ] . WillRemove ) DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ;


<s> if ( Op . isReg ( ) && Op . getReg ( ) == AMDGPU :: SCC ) Inst -> RemoveOperand ( i ) ; } if ( NewDesc . ImplicitUses ) { for ( unsigned i = <NUM_LIT> ; NewDesc . ImplicitUses [ i ] ; ++ i ) { unsigned Reg = NewDesc . ImplicitUses [ i ] ; Inst -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true ) ) ; } } if ( NewDesc . ImplicitDefs ) { for ( unsigned i = <NUM_LIT> ; NewDesc . ImplicitDefs [ i ] ; ++ i ) { unsigned Reg = NewDesc . ImplicitDefs [ i ] ; Inst -> addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; } }


<s> if ( ! REG_P ( op0 ) || ! INT_REG_OK_FOR_BASE_P ( op0 , strict ) ) return false ; op1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONST_INT_P ( op1 ) ) return false ; return quad_address_offset_p ( INTVAL ( op1 ) ) ;


<s> } const RegisterBank & RB = * RegClassOrBank . get < const RegisterBank * > ( ) ; DefRC = TRI . getRegClassForTypeOnBank ( DefTy , RB , * MRI ) ; if ( ! DefRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } I . setDesc ( TII . get ( TargetOpcode :: PHI ) ) ; return RBI . constrainGenericRegister ( DefReg , * DefRC , * MRI ) ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( class AsmPrinter & asmprinter ) : Printer ( asmprinter ) {


<s> unsigned SCIdx = TII -> get ( <STR_LIT> ) . getSchedClass ( ) ; const MCSchedClassDesc * SCDesc = SchedModel . getMCSchedModel ( ) -> getSchedClassDesc ( SCIdx ) ; if ( SCDesc -> isValid ( ) && ! SCDesc -> isVariant ( ) ) { unsigned ResLenWithSTP = BBTrace . getResourceLength ( None , SCDesc ) ; if ( ResLenWithSTP > ResLength ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << BB -> getNumber ( ) << <STR_LIT> << ResLength << <STR_LIT> << ResLenWithSTP << <STR_LIT> ) ; return false ; } } return true ;