<s> case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasAVX ( ) ) return SDValue ( ) ; ISDNo = <STR_LIT> ; OpTy = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasAVX ( ) ) return SDValue ( ) ; ISDNo = <STR_LIT> ; OpTy = <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasAVX2 ( ) ) return SDValue ( ) ; ISDNo = <STR_LIT> ; OpTy = <STR_LIT> ; break ; } assert ( ISDNo && <STR_LIT> ) ; unsigned MaskVals = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < MaskSize ; ++ i ) { int EltIdx = SVOp -> getMaskElt ( i ) ; if ( EltIdx == i || EltIdx == - <NUM_LIT> ) MaskVals |= ( <NUM_LIT> << i ) ; else if ( EltIdx == ( i + MaskSize ) ) continue ; else return SDValue ( ) ; } V1 = DAG . getNode ( <STR_LIT> , dl , OpTy , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , OpTy , V2 ) ; SDValue Ret = DAG . getNode ( ISDNo , dl , OpTy , V1 , V2 , DAG . getConstant ( MaskVals , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Ret ) ;


<s> const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ;


<s> void DigitalelTargetMachine :: anchor ( ) {


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( RegOrOffset ) ) ; } getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; const <ISA_LIT>MCExpr * HiExpr = <ISA_LIT>MCExpr :: createGpOff ( <ISA_LIT>MCExpr :: MEK_HI , MCSymbolRefExpr :: create ( & Sym , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; const <ISA_LIT>MCExpr * LoExpr = <ISA_LIT>MCExpr :: createGpOff ( <ISA_LIT>MCExpr :: MEK_LO , MCSymbolRefExpr :: create ( & Sym , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( HiExpr ) ) ; getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createExpr ( LoExpr ) ) ;


<s> Align Alignment = std :: max ( TargetAlign , MaxAlign ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ;

bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! FI -> mustSaveTOC ( ) && ! RegInfo -> hasBasePointer ( MF ) ;


<s> unsigned Code ; switch ( Val & <NUM_LIT> ) { case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ; break ; case <NUM_LIT> : Code = <STR_LIT> ;


<s> int <ISA_LIT>LoopIdiomRecognize :: getSCEVStride ( const SCEVAddRecExpr * S ) { if ( const SCEVConstant * SC = dyn_cast < SCEVConstant > ( S -> getOperand ( <NUM_LIT> ) ) ) return SC -> getAPInt ( ) . getSExtValue ( ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;

TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> return ( uint16x8_t ) __builtin_neon_vcgev8hi ( __b , __a ) ;


<s> if ( REG_P ( op ) ) gcc_assert ( ! FP_REG_RTX_P ( op ) ) ; return simplify_gen_subreg ( word_mode , op , mode , byte ) ;


<s> inline static bool isTruncatedShiftCountForLEA ( unsigned ShAmt ) {

return ShAmt < <NUM_LIT> && ShAmt > <NUM_LIT> ;


<s> isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v6 : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v5te : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v5 : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: <ISA_LIT>SubArch_v4t : <ISA_LIT>ArchFeature = <STR_LIT> ; break ; case Triple :: NoSubArch : break ; } if ( isThumb ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( TT . isOSNaCl ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } return <ISA_LIT>ArchFeature ;


<s> int NumEltsPerLane = NumElts / NumLanes ; int NumInnerEltsPerLane = NumInnerElts / NumLanes ; DemandedLHS = APInt :: getZero ( NumInnerElts ) ; DemandedRHS = APInt :: getZero ( NumInnerElts ) ; for ( int Lane = <NUM_LIT> ; Lane != NumLanes ; ++ Lane ) { for ( int Elt = <NUM_LIT> ; Elt != NumInnerEltsPerLane ; ++ Elt ) { int OuterIdx = ( Lane * NumEltsPerLane ) + Elt ; int InnerIdx = ( Lane * NumInnerEltsPerLane ) + Elt ; if ( DemandedElts [ OuterIdx ] ) DemandedLHS . setBit ( InnerIdx ) ;

if ( DemandedElts [ OuterIdx + NumInnerEltsPerLane ] ) DemandedRHS . setBit ( InnerIdx ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; UI != UE ;


<s> vaddlv_u16 ( uint16x4_t a ) { uint32_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> return createRegOperand ( IsAGPR ? getAgprClassId ( Width ) : getVgprClassId ( Width ) , Val - VGPR_MIN ) ; } if ( Val <= SGPR_MAX ) { assert ( SGPR_MIN == <NUM_LIT> ) ; return createSRegOperand ( getSgprClassId ( Width ) , Val - SGPR_MIN ) ; } int TTmpIdx = getTTmpIdx ( Val ) ; if ( TTmpIdx >= <NUM_LIT> ) { return createSRegOperand ( getTtmpClassId ( Width ) , TTmpIdx ) ; } if ( INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX ) return decodeIntImmed ( Val ) ; if ( INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX ) return decodeFPImmed ( Width , Val ) ;

if ( Val == LITERAL_CONST ) return decodeLiteralConstant ( ) ;


<s> <ISA_LIT>32GNULDBackend :: <ISA_LIT>32GNULDBackend ( const LinkerConfig & pConfig , <ISA_LIT>GNUInfo * pInfo ) : <ISA_LIT>GNULDBackend ( pConfig , pInfo ) {


<s> EVT CCVT = SrcVT . changeVectorElementTypeToInteger ( ) ; SDLoc DL ( N0 ) ; SDValue LHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getNode ( <STR_LIT> , DL , SrcVT , N0 . getOperand ( <NUM_LIT> ) ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , CCVT , LHS , RHS , N0 . getOperand ( <NUM_LIT> ) ) ; SmallVector < int , <NUM_LIT> > DUPMask ( CCVT . getVectorNumElements ( ) , <NUM_LIT> ) ;

SDValue Mask = DAG . getVectorShuffle ( CCVT , DL , SetCC , SetCC , DUPMask . data ( ) ) ;


<s> Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasQPX = false ; HasVSX = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ; IsQPXStackUnaligned = false ; HasHTM = false ; HasFusion = false ; HasFloat128 = false ;


<s> return getSubtargetImpl ( ) -> getTargetLowering ( ) ;


<s> MachineBasicBlock * MBB = Blocks [ i ] ; for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) , E = MBB -> end ( ) ; MII != E ; ++ MII ) { const MachineInstr * MI = & * MII ; if ( isInvalidLoopOperation ( MI , IsInnerHWLoop ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI -> dump ( ) ; ) ; return true ; }


<s> assert ( ( Cmp & ( L | G ) ) != ( L | G ) ) ; return Cmp ^ ( L | G ) ;


<s> if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ; int WidthA = MMOa -> getSize ( ) , WidthB = MMOb -> getSize ( ) ; int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; }


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st4v16qi ( ( __builtin_aarch64_simd_qi * ) __a , __o ) ;


<s> curr_range_str = strategy_str ; do { int maxs ; char alg_name [ <NUM_LIT> ] ; char align [ <NUM_LIT> ] ; next_range_str = strchr ( curr_range_str , ',' ) ; if ( next_range_str ) * next_range_str ++ = '\0' ; if ( sscanf ( curr_range_str , <STR_LIT> , alg_name , & maxs , align ) != <NUM_LIT> ) { error ( <STR_LIT> , curr_range_str , opt ) ; return ; } if ( n > <NUM_LIT> && ( maxs < ( input_ranges [ n - <NUM_LIT> ] . max + <NUM_LIT> ) && maxs != - <NUM_LIT> ) ) { error ( <STR_LIT> , opt ) ; return ; } for ( i = <NUM_LIT> ; i < last_alg ; i ++ ) if ( ! strcmp ( alg_name , stringop_alg_names [ i ] ) ) break ; if ( i == last_alg ) { error ( <STR_LIT> , alg_name , opt ) ; auto_vec < const char * > candidates ; for ( i = <NUM_LIT> ; i < last_alg ; i ++ ) if ( ( stringop_alg ) i != rep_prefix_8_byte || TARGET_64BIT ) candidates . safe_push ( stringop_alg_names [ i ] ) ; char * s ; const char * hint = candidates_list_and_hint ( alg_name , s , candidates ) ; if ( hint ) inform ( input_location , <STR_LIT> , opt , s , hint ) ; else inform ( input_location , <STR_LIT> , opt , s ) ; XDELETEVEC ( s ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * MBB ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : return emitBrCC ( MI , MBB ) ; case <STR_LIT> : return emitSelectCC ( MI , MBB ) ; default :


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;


<s> B . addAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! B . hasAttributes ( ) ) return false ; F . addAttributes ( AttributeList :: FunctionIndex , B ) ;


<s> UUSetMap P2Rs ; LoopRegMap IRM ; collectIndRegs ( IRM ) ; partitionRegisters ( P2Rs ) ; DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs . end ( ) ; I != E ; ++ I ) { dbgs ( ) << '#' << I -> first << <STR_LIT> ; dump_partition ( dbgs ( ) , I -> second , * TRI ) ; dbgs ( ) << '\n' ; } } ) ; bool Changed = false ; int Limit = MaxHSDR ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs . end ( ) ; I != E ; ++ I ) { if ( I -> first == <NUM_LIT> ) continue ; if ( Limit >= <NUM_LIT> && Counter >= Limit ) break ; USet & Part = I -> second ; DEBUG ( dbgs ( ) << <STR_LIT> << I -> first << '\n' ) ; if ( ! isProfitable ( Part , IRM ) ) continue ; Counter ++ ; Changed |= splitPartition ( Part ) ; } return Changed ;


<s> if ( isSlotPreAllocated ( MFI , ST . FI ) ) continue ; Register RetagReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( RetagReg ) ) continue ; int Score = <NUM_LIT> ; SmallVector < Register , <NUM_LIT> > WorkList ; WorkList . push_back ( RetagReg ) ; while ( ! WorkList . empty ( ) ) { Register UseReg = WorkList . pop_back_val ( ) ; for ( auto & UseI : MRI -> use_instructions ( UseReg ) ) { unsigned Opcode = UseI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) continue ; if ( UseI . isCopy ( ) ) { Register DstReg = UseI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isVirtualRegister ( DstReg ) ) WorkList . push_back ( DstReg ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ST . FI << <STR_LIT> << ST . Tag << <STR_LIT> << Register :: virtReg2Index ( UseReg ) << <STR_LIT> << UseI << <STR_LIT> ) ; Score ++ ; } } int TotalScore = RetagScore [ ST ] += Score ; if ( TotalScore > MaxScore || ( TotalScore == MaxScore && ST . FI > MaxScoreST . FI ) ) { MaxScore = TotalScore ; MaxScoreST = ST ; } } if ( MaxScoreST . FI < <NUM_LIT> ) return None ; if ( MaxScoreST . Tag == <NUM_LIT> ) return MaxScoreST . FI ; SlotWithTag SwapST { - <NUM_LIT> , - <NUM_LIT> } ; for ( auto * I : ReTags ) { SlotWithTag ST { * I } ;


<s> return ( __m256d ) __builtin_ia32_gatherdiv4df ( ( __v4df ) src , base , ( __v4di ) index , ( __v4df ) mask , scale ) ;


<s> Common = true ; break ; } if ( ! Common ) return ; for ( auto & R : RDefMap ) { if ( ! RRs . count ( R . first ) ) continue ; auto F = DefM . find ( R . first . Reg ) ;

if ( F == DefM . end ( ) || F -> second . empty ( ) ) continue ;


<s> static tree ix86_d_handle_target_float_abi ( void ) { const char * abi ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) abi = <STR_LIT> ; else abi = <STR_LIT> ;

return build_string_literal ( strlen ( abi ) + <NUM_LIT> , abi ) ;


<s> char * specfile_name ; const char * mmcu = NULL ; if ( verbose_flag ) fnotice ( stderr , <STR_LIT> , __FUNCTION__ , argc ) ; switch ( argc ) { case <NUM_LIT> : fatal_error ( input_location , <STR_LIT> , <STR_LIT> ) ; return X_NODEVLIB ; case <NUM_LIT> : if ( <NUM_LIT> == strcmp ( <STR_LIT> , argv [ <NUM_LIT> ] ) ) { return X_NODEVLIB ; } mmcu = AVR_MMCU_DEFAULT ; break ; default : mmcu = argv [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < argc ; i ++ ) if ( <NUM_LIT> != strcmp ( mmcu , argv [ i ] ) ) { error ( <STR_LIT> , <STR_LIT> ) ; return X_NODEVLIB ; } break ; } specfile_name = concat ( argv [ <NUM_LIT> ] , dir_separator_str , <STR_LIT> , mmcu , NULL ) ;

if ( verbose_flag ) fnotice ( stderr , <STR_LIT> , __FUNCTION__ , mmcu , __FUNCTION__ , specfile_name ) ;


<s> if ( ! Subtarget . hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : return true ; default : break ;


<s> if ( areCFlagsAliveInSuccessors ( CmpParent ) ) return None ; UsedNZCV NZCVUsedAfterCmp ; for ( MachineInstr & Instr : instructionsWithoutDebug ( std :: next ( CmpInstr . getIterator ( ) ) , CmpParent -> instr_end ( ) ) ) { if ( Instr . readsRegister ( <STR_LIT> , & TRI ) ) { <STR_LIT> CC = findCondCodeUsedByInstr ( Instr ) ; if ( CC == <STR_LIT> ) return None ; NZCVUsedAfterCmp |= getUsedNZCV ( CC ) ;

if ( CCUseInstrs ) CCUseInstrs -> push_back ( & Instr ) ;


<s> SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > TmpReg ; OperandMatchResultTy ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { reportParseError ( <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } <ISA_LIT>Operand & FuncRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! FuncRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( FuncRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } FuncReg = FuncRegOpnd . getGPR32Reg ( ) ; TmpReg . clear ( ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Integer ) ) {


<s> auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . hasStdExtV ( ) ) return false ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerVECTOR_SHIFT ( SDValue Op , SelectionDAG & DAG ) const { BuildVectorSDNode * BVN = nullptr ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; SDValue V3 ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V1 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V2 ; else if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V2 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V1 ; else return SDValue ( ) ; SDValue CommonSplat = BVN -> getOperand ( <NUM_LIT> ) ; SDValue Result ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; default : return SDValue ( ) ; } } else if ( VT . getSimpleVT ( ) == <STR_LIT> ) { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; default : return SDValue ( ) ; } } else {


<s> const MCRegister <ISA_LIT>ElfTargetObjectFile :: getStaticBase ( ) const { return <STR_LIT> ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveFPLRX ( SMLoc L ) { int64_t Offset ; if ( parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveFPLRX ( Offset ) ; return false ;


<s> static inline bool is<ISA_LIT>_64ExtendedReg ( unsigned RegNo ) { switch ( RegNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> uint64_t Binary = ( MO . getImm ( ) >> <NUM_LIT> ) & <NUM_LIT> ; return ( ( ( Binary & <NUM_LIT> ) >> <NUM_LIT> ) | ( Binary & <NUM_LIT> ) ) ; } return <NUM_LIT> ;


<s> return new <ISA_LIT>MCAsmInfo ( TT ) ;


<s> psllh_u ( uint16x4_t s , uint8_t amount ) {

return __builtin_loongson_psllh_u ( s , amount ) ;


<s> bool <ISA_LIT>InstrInfo :: getMemOperandWithOffset ( MachineInstr & MemOp , MachineOperand * & BaseOp , int64_t & Offset , const TargetRegisterInfo * TRI ) const { const MCInstrDesc & Desc = MemOp . getDesc ( ) ; int MemRefBegin = <STR_LIT> ( Desc . TSFlags ) ; if ( MemRefBegin < <NUM_LIT> ) return false ; MemRefBegin += <STR_LIT> ( Desc ) ; BaseOp = & MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ; assert ( BaseOp -> isReg ( ) && <STR_LIT> <STR_LIT> ) ; return true ;


<s> SDLoc DL ( Op ) ; SDValue AluOp = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; ; OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( AluOp ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ;


<s> if ( State . isVarArg ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; <STR_LIT> ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , <NUM_LIT> , <NUM_LIT> , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ;

if ( ! UseStack && Parts <= RegsLeft ) {


<s> SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ;

CmpMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI ) ) return Result ; return SDValue ( ) ;


<s> bool WritesElement0 = TSFlags & <STR_LIT> ; <ISA_LIT>VLMUL VLMul = static_cast < <ISA_LIT>VLMUL > ( ( TSFlags & <STR_LIT> ) >> <STR_LIT> ) ; return addVSetVL ( MI , BB , VLIndex , SEWIndex , VLMul , WritesElement0 ) ; } switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MCCodeEmitter * create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> bool isFlavorAtt ( ) const { return AsmFlavor == ATT ;


<s> for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; int InputIdx = Mask [ i ] >= Size ; if ( i < Size / <NUM_LIT> ) ++ NumLoInputs [ InputIdx ] ; else ++ NumHiInputs [ InputIdx ] ; if ( ( i % <NUM_LIT> ) == <NUM_LIT> ) ++ NumEvenInputs [ InputIdx ] ; else ++ NumOddInputs [ InputIdx ] ; } int InterleavedCrosses = std :: min ( NumEvenInputs [ <NUM_LIT> ] + NumOddInputs [ <NUM_LIT> ] , NumEvenInputs [ <NUM_LIT> ] + NumOddInputs [ <NUM_LIT> ] ) ; int SplitCrosses = std :: min ( NumLoInputs [ <NUM_LIT> ] + NumHiInputs [ <NUM_LIT> ] , NumLoInputs [ <NUM_LIT> ] + NumHiInputs [ <NUM_LIT> ] ) ; return InterleavedCrosses < SplitCrosses ;


<s> static bool inline isOff22 ( int64_t I ) {


<s> unsigned Reg ; int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveRegPX ( Reg , Offset ) ;


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Flags ) ; } return SDValue ( ) ;


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isEnvironmentMusl ( ) ) return true ; if ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasEHReturn ( ) ) return true ; if ( ! hasFP ( MF ) ) return true ; if ( ! isOptSize ( MF ) && ! isMinSize ( MF ) ) if ( MF . getTarget ( ) . getOptLevel ( ) > CodeGenOpt :: Default ) return true ; BitVector Regs ( <STR_LIT> ) ; for ( const CalleeSavedInfo & I : CSI ) { unsigned R = I . getReg ( ) ; if ( ! <STR_LIT> . contains ( R ) ) return true ; Regs [ R ] = true ; } int F = Regs . find_first ( ) ; if ( F != <STR_LIT> ) return true ;


<s> return ! ( MFI -> hasCalls ( ) || ! MRI . reg_nodbg_empty ( <STR_LIT> ) || ! MRI . reg_nodbg_empty ( <STR_LIT> ) || hasFP ( MF ) ) ;


<s> LEONMachineFunctionPass ( tm , ID ) {


<s> static bool CC_<ISA_LIT>_APCS_Custom_f64 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) {

if ( ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ;


<s> return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm , Address ) ;


<s> __v8sf mask = _mm256_cmp_ps ( src , src , _CMP_EQ_OQ ) ;

return ( __m256 ) __builtin_ia32_gathersiv8sf ( src , base , ( __v8si ) index , mask , scale ) ;


<s> return __builtin_mve_vaddq_n_uv8hi ( __a , __b ) ;


<s> case CortexA73 : case CortexA75 : case CortexA76 : PrefFunctionAlignment = <NUM_LIT> ; break ; case Cyclone : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM1 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ;


<s> if ( WasThumb != isThumb ( ) ) { if ( WasThumb && hasThumb ( ) ) { SwitchMode ( ) ; } else if ( ! WasThumb && has<ISA_LIT> ( ) ) { SwitchMode ( ) ; } else { getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( isThumb ( ) ? MCAF_Code16 : MCAF_Code32 ) ; Warning ( Loc , Twine ( <STR_LIT> ) + ( WasThumb ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> + ( ! WasThumb ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> ) ; }


<s> } return ; } if ( arm_ccfsm_state == <NUM_LIT> ) { if ( simplejump_p ( insn ) ) { start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == BARRIER ) { start_insn = next_nonnote_insn ( start_insn ) ; } if ( GET_CODE ( start_insn ) == CODE_LABEL && CODE_LABEL_NUMBER ( start_insn ) == arm_target_label && LABEL_NUSES ( start_insn ) == <NUM_LIT> ) reverse = TRUE ; else return ; } else if ( GET_CODE ( body ) == RETURN ) { start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == BARRIER ) start_insn = next_nonnote_insn ( start_insn ) ; if ( GET_CODE ( start_insn ) == CODE_LABEL && CODE_LABEL_NUMBER ( start_insn ) == arm_target_label && LABEL_NUSES ( start_insn ) == <NUM_LIT> ) { reverse = TRUE ; seeking_return = <NUM_LIT> ; } else return ; } else return ; } gcc_assert ( ! arm_ccfsm_state || reverse ) ; if ( GET_CODE ( insn ) != JUMP_INSN ) return ; if ( GET_CODE ( body ) == PARALLEL && XVECLEN ( body , <NUM_LIT> ) > <NUM_LIT> ) body = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( reverse || ( GET_CODE ( body ) == SET && GET_CODE ( SET_DEST ( body ) ) == PC && GET_CODE ( SET_SRC ( body ) ) == IF_THEN_ELSE ) ) { int insns_skipped ; int fail = FALSE , succeed = FALSE ; int then_not_else = TRUE ; rtx this_insn = start_insn , label = <NUM_LIT> ; if ( get_attr_conds ( insn ) == CONDS_JUMP_CLOB ) { jump_clobbers = <NUM_LIT> ; return ; } if ( reverse ) { if ( ! seeking_return ) label = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; } else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == LABEL_REF ) { label = XEXP ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) , <NUM_LIT> ) ; then_not_else = FALSE ; } else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == RETURN ) seeking_return = <NUM_LIT> ; else if ( GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == RETURN ) { seeking_return = <NUM_LIT> ; then_not_else = FALSE ; } else gcc_unreachable ( ) ; for ( insns_skipped = <NUM_LIT> ; ! fail && ! succeed && insns_skipped ++ < max_insns_skipped ; ) { rtx scanbody ; this_insn = next_nonnote_insn ( this_insn ) ; if ( ! this_insn ) break ; switch ( GET_CODE ( this_insn ) ) {


<s> break ; case COMPLEX_TYPE : mode = TYPE_MODE ( TREE_TYPE ( type ) ) ; if ( ! SCALAR_FLOAT_MODE_P ( mode ) ) return - <NUM_LIT> ; if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case VECTOR_TYPE : if ( ! TARGET_ALTIVEC_ABI || ! TARGET_ALTIVEC ) return - <NUM_LIT> ; size = int_size_in_bytes ( type ) ; switch ( size ) { case <NUM_LIT> : mode = V4SImode ; break ; default : return - <NUM_LIT> ; } if ( * modep == VOIDmode ) * modep = mode ; if ( * modep == mode ) return <NUM_LIT> ; break ; case ARRAY_TYPE : { int count ; tree index = TYPE_DOMAIN ( type ) ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; count = rs6000_aggregate_candidate ( TREE_TYPE ( type ) , modep , empty_base_seen , zero_width_bf_seen ) ; if ( count == - <NUM_LIT> || ! index || ! TYPE_MAX_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MAX_VALUE ( index ) ) || ! TYPE_MIN_VALUE ( index ) || ! tree_fits_uhwi_p ( TYPE_MIN_VALUE ( index ) ) || count < <NUM_LIT> ) return - <NUM_LIT> ; count *= ( <NUM_LIT> + tree_to_uhwi ( TYPE_MAX_VALUE ( index ) ) - tree_to_uhwi ( TYPE_MIN_VALUE ( index ) ) ) ; if ( wi :: to_wide ( TYPE_SIZE ( type ) ) != count * GET_MODE_BITSIZE ( * modep ) ) return - <NUM_LIT> ; return count ; } case RECORD_TYPE : { int count = <NUM_LIT> ; int sub_count ; tree field ; if ( ! COMPLETE_TYPE_P ( type ) || TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return - <NUM_LIT> ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD ( field ) ) { * zero_width_bf_seen = <NUM_LIT> ; continue ; } if ( DECL_FIELD_ABI_IGNORED ( field ) ) { if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( field ) ) ) * empty_base_seen |= <NUM_LIT> ; else * empty_base_seen |= <NUM_LIT> ; continue ; } sub_count = rs6000_aggregate_candidate ( TREE_TYPE ( field ) , modep , empty_base_seen , zero_width_bf_seen ) ;

if ( sub_count < <NUM_LIT> ) return - <NUM_LIT> ;


<s> base = emit_adjust_base_to_offset ( base , offset ) ; offset = <NUM_LIT> ; } offset = emit_save_or_restore_regs ( <NUM_LIT> , <NUM_LIT> , base , offset , <NUM_LIT> , save_global_or_fp_reg_p , action , SORR_NONE ) ;


<s> static bool isSupportedReturnType ( Type * T ) { if ( T -> isIntegerTy ( ) ) return true ; if ( T -> isPointerTy ( ) ) return true ;

if ( T -> isFloatingPointTy ( ) ) return true ;


<s> Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; bool OffsetInternal = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; OffsetInternal = MI -> getOperand ( <NUM_LIT> ) . isInternalRead ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm = <NUM_LIT> ; if ( HasImmOffset ) { OffsetImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MaxOffset = ( ( <NUM_LIT> << ImmLimit ) - <NUM_LIT> ) * Scale ; if ( ( OffsetImm & ( Scale - <NUM_LIT> ) ) || OffsetImm > MaxOffset ) return false ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , TII -> get ( Opc ) ) ; if ( Entry . WideOpc == <STR_LIT> ) MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define | RegState :: Dead ) ; if ( ! isLdStMul ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( HasImmOffset ) MIB . addImm ( OffsetImm / Scale ) ; assert ( ( ! HasShift || OffsetReg ) && <STR_LIT> ) ; if ( HasOffReg ) MIB . addReg ( OffsetReg , getKillRegState ( OffsetKill ) | getInternalReadRegState ( OffsetInternal ) ) ; } for ( unsigned e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . add ( MI -> getOperand ( OpNum ) ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - CE -> getValue ( ) ) ) ;


<s> void <ISA_LIT>64TargetMachine :: anchor ( ) {


<s> Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = lowerSymbolOperand ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = lowerSymbolOperand ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; break ;


<s> explicit <ISA_LIT>UnmangledLibFunc ( StringRef FName , FunctionType * FT ) { Name = std :: string ( FName ) ; FuncTy = FT ;


<s> void adds32_0ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> void Initialize ( const MachineFunction & MF , bool isPIC ) {


<s> void CFStack :: updateMaxStackSize ( ) { unsigned CurrentStackSize = CurrentEntries + ( alignTo ( CurrentSubEntries , <NUM_LIT> ) / <NUM_LIT> ) ;

MaxStackSize = std :: max ( CurrentStackSize , MaxStackSize ) ;


<s> static DecodeStatus DecodeGPCRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {

if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> for ( c = pool -> execute ; c != NULL ; c = c -> next ) if ( INSN_UID ( insn ) == INSN_UID ( c -> value ) ) break ; gcc_assert ( c ) ; return s390_pool_offset ( pool , gen_rtx_LABEL_REF ( Pmode , c -> label ) ) ;


<s> <ISA_LIT>Type * <ISA_LIT>GlobalRegistry :: getOpTypeByOpcode ( MachineIRBuilder & MIRBuilder , unsigned Opcode ) { Register ResVReg = createTypeVReg ( MIRBuilder ) ; auto MIB = MIRBuilder . buildInstr ( Opcode ) . addDef ( ResVReg ) ; constrainRegOperands ( MIB ) ; return MIB ;


<s> } else { if ( isDef ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( RelocM == Reloc :: PIC_ ) { if ( GV -> isDeclarationForLinker ( ) || GV -> hasCommonLinkage ( ) ) return true ; } }


<s> if ( ( ( mask2 == <NUM_LIT> || ( mask2 & ix86_isa_flags2 ) != <NUM_LIT> ) && ( mask == <NUM_LIT> || ( mask & ix86_isa_flags ) != <NUM_LIT> ) ) || ( ( mask & OPTION_MASK_ISA_MMX ) != <NUM_LIT> && TARGET_MMX_WITH_SSE ) || ( mask2 == OPTION_MASK_ISA2_AVXVNNI ) || ( mask2 == OPTION_MASK_ISA2_AVXIFMA ) || ( mask2 == ( OPTION_MASK_ISA2_AVXNECONVERT | OPTION_MASK_ISA2_AVX512BF16 ) ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; deferred_isa_values2 |= mask2 ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ;

ix86_builtins_isa [ ( int ) code ] . name = name ;


<s> static void frv_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx addr = XEXP ( m_tramp , <NUM_LIT> ) ; rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; rtx sc_reg = force_reg ( Pmode , static_chain ) ;

emit_library_call ( gen_rtx_SYMBOL_REF ( SImode , <STR_LIT> ) , LCT_NORMAL , VOIDmode , <NUM_LIT> , addr , Pmode , GEN_INT ( frv_trampoline_size ( ) ) , SImode , fnaddr , Pmode , sc_reg , Pmode ) ;


<s> auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; MCSymbol * Label = S . emitCFILabel ( ) ; CurFrame -> PrologEnd = Label ; WinEH :: Instruction Inst = WinEH :: Instruction ( Win64EH :: UOP_End , Label , - <NUM_LIT> , <NUM_LIT> ) ;

auto it = CurFrame -> Instructions . begin ( ) ;


<s> void <ISA_LIT>TargetStreamer :: emitPad ( int64_t Offset ) {


<s> if ( ! selectAddress ( Addr , AM ) ) return false ;

getAddressOperands ( AM , Addr . getValueType ( ) , Base , Disp , Index ) ;


<s> if ( Fn ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr ) ;


<s> if ( ! CurFrame ) return ; auto Inst = WinEH :: Instruction ( UnwindCode , nullptr , Reg , Offset ) ;

if ( InEpilogCFI ) CurFrame -> EpilogMap [ CurrentEpilog ] . Instructions . push_back ( Inst ) ;


<s> static unsigned loongarch_save_libcall_count ( unsigned mask ) {

for ( unsigned n = GP_REG_LAST ; n > GP_REG_FIRST ; n -- ) if ( BITSET_P ( mask , n ) ) return CALLEE_SAVED_REG_NUMBER ( n ) + <NUM_LIT> ;


<s> static SDValue emitSETCC ( SelectionDAG & DAG , SDLoc DL , SDValue Glue , unsigned CCValid , unsigned CCMask ) { IPMConversion Conversion = getIPMConversion ( CCValid , CCMask ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Glue ) ; if ( Conversion . XORValue ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . XORValue , <STR_LIT> ) ) ; if ( Conversion . AddValue ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . AddValue , <STR_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( Conversion . Bit , <STR_LIT> ) ) ; if ( Conversion . Bit != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool IsInc ; if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) return false ; if ( Ptr != Base ) return false ; AM = IsInc ? <STR_LIT> : <STR_LIT> ; return true ;


<s> bool <ISA_LIT>InstrInfo :: isLoadFromConstantPool ( MachineInstr * I ) const { if ( ! I -> hasOneMemOperand ( ) ) return false ;

MachineMemOperand * Op = I -> memoperands ( ) [ <NUM_LIT> ] ;


<s> assert ( CE && <STR_LIT> ) ; int Imm = CE -> getValue ( ) ; bool isAdd = Imm >= <NUM_LIT> ; if ( Imm == INT32_MIN ) Imm = <NUM_LIT> ; Imm = ( ( Imm < <NUM_LIT> ? - Imm : Imm ) / <NUM_LIT> ) | ( int ) isAdd << <NUM_LIT> ;

Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ;


<s> unsigned SizeRatio = FromSz / ToSz ; assert ( SizeRatio * NumElems * ToSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideVec = DAG . getBitcast ( WideVecVT , Mst -> getValue ( ) ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; SDValue TruncatedVal = DAG . getVectorShuffle ( WideVecVT , dl , WideVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; SDValue NewMask ; SDValue Mask = Mst -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ;

SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ;


<s> const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OS << '\x66' ; const uint8_t Rest = ThisNopLength - Prefixes ; if ( Rest != <NUM_LIT> ) OS . write ( Nops [ Rest - <NUM_LIT> ] , Rest ) ; Count -= ThisNopLength ; } while ( Count != <NUM_LIT> ) ;


<s> if ( V . getContext ( ) . isSubprogram ( ) ) O << DISubprogram ( V . getContext ( ) ) . getDisplayName ( ) << <STR_LIT> ; O << V . getName ( ) ; O << <STR_LIT> ; O << '[' ;

if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) printOperand ( MI , <NUM_LIT> , O ) ;


<s> switch ( I -> getOpcode ( ) ) { case TargetOpcode :: COPY : if ( ! expandCopy ( MBB , I ) ) return false ; break ; default : return false ; } MBB . erase ( I ) ; return true ;


<s> unsigned int pass_shorten_memrefs :: execute ( function * fn ) { basic_block bb ; FOR_ALL_BB_FN ( bb , fn ) { regno_map * m ; if ( optimize_bb_for_speed_p ( bb ) ) continue ; m = analyze ( bb ) ;


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; const GCNSubtarget & ST = MBB . getParent ( ) -> getSubtarget < GCNSubtarget > ( ) ; const bool IsWave32 = ST . isWave32 ( ) ; const unsigned CondReg = TRI -> getVCC ( ) ; const unsigned ExecReg = IsWave32 ? <STR_LIT> : <STR_LIT> ; const unsigned And = IsWave32 ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock :: reverse_iterator A = MI . getReverseIterator ( ) , E = MBB . rend ( ) ; bool ReadsCond = false ; unsigned Threshold = <NUM_LIT> ; for ( ++ A ; A != E ; ++ A ) { if ( ! -- Threshold ) return false ; if ( A -> modifiesRegister ( ExecReg , TRI ) ) return false ; if ( A -> modifiesRegister ( CondReg , TRI ) ) { if ( ! A -> definesRegister ( CondReg , TRI ) || A -> getOpcode ( ) != And ) return false ; break ; } ReadsCond |= A -> readsRegister ( CondReg , TRI ) ; } if ( A == E ) return false ; MachineOperand & Op1 = A -> getOperand ( <NUM_LIT> ) ; MachineOperand & Op2 = A -> getOperand ( <NUM_LIT> ) ; if ( Op1 . getReg ( ) != ExecReg && Op2 . isReg ( ) && Op2 . getReg ( ) == ExecReg ) { TII -> commuteInstruction ( * A ) ; Changed = true ; } if ( Op1 . getReg ( ) != ExecReg ) return Changed ; if ( Op2 . isImm ( ) && Op2 . getImm ( ) != - <NUM_LIT> ) return Changed ; unsigned SReg = <STR_LIT> ; if ( Op2 . isReg ( ) ) { SReg = Op2 . getReg ( ) ; auto M = std :: next ( A ) ; bool ReadsSreg = false ; for ( ; M != E ; ++ M ) { if ( M -> definesRegister ( SReg , TRI ) ) break ; if ( M -> modifiesRegister ( SReg , TRI ) ) return Changed ; ReadsSreg |= M -> readsRegister ( SReg , TRI ) ; }

if ( M == E || ! M -> isMoveImmediate ( ) || ! M -> getOperand ( <NUM_LIT> ) . isImm ( ) || M -> getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return Changed ;


<s> if ( ( MIaG != <STR_LIT> ) && ( MIbG != <STR_LIT> ) ) { if ( subInstWouldBeExtended ( MIa ) ) return false ; if ( subInstWouldBeExtended ( MIb ) && ! ExtendedB ) return false ; } if ( MIbG == <STR_LIT> ) { if ( ( MIb . getNumOperands ( ) > <NUM_LIT> ) && MIb . getOperand ( <NUM_LIT> ) . isReg ( ) && ( MIb . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ; if ( ( MIb . getNumOperands ( ) > <NUM_LIT> ) && MIb . getOperand ( <NUM_LIT> ) . isReg ( ) && ( MIb . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return false ; }

if ( ( MIbG == <STR_LIT> ) || ( MIbG == <STR_LIT> ) ) {


<s> <ISA_LIT>_64Relocator :: <ISA_LIT>_64Relocator ( <ISA_LIT>_64GNULDBackend & pParent , const LinkerConfig & pConfig ) : <ISA_LIT>Relocator ( pConfig ) , m_Target ( pParent ) {


<s> IntegerType * getPmpyType ( ) const { LLVMContext & Ctx = CurLoop -> getHeader ( ) -> getParent ( ) -> getContext ( ) ; return IntegerType :: get ( Ctx , <NUM_LIT> ) ;


<s> return true ; } AM . BaseType = <ISA_LIT>ISelAddressMode :: RegBase ; AM . Base . Reg = N ;


<s> MachineBasicBlock :: instr_iterator II ( MI -> getIterator ( ) ) ; for ( MachineBasicBlock :: instr_iterator I = ++ II , E = MBB . instr_end ( ) ; I != E && I -> isBundledWithPred ( ) ; ++ I ) { I -> unbundleFromPred ( ) ; for ( MachineOperand & MO : I -> operands ( ) ) if ( MO . isReg ( ) ) MO . setIsInternalRead ( false ) ; } MI -> eraseFromParent ( ) ; MI = II -> getIterator ( ) ; } if ( ! ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) ) continue ; if ( const auto & MOI = MOA . getLoadInfo ( MI ) ) Changed |= expandLoad ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getStoreInfo ( MI ) ) Changed |= expandStore ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicFenceInfo ( MI ) ) Changed |= expandAtomicFence ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicCmpxchgOrRmwInfo ( MI ) ) Changed |= expandAtomicCmpxchgOrRmw ( MOI . getValue ( ) , MI ) ; }


<s> unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; uint32_t Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ;

for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset + i ] |= static_cast < uint8_t > ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> addr = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; mem = gen_rtx_MEM ( SImode , addr ) ; create_input_operand ( & ops [ <NUM_LIT> ] , mem , SImode ) ; return nios2_expand_builtin_insn ( d , <NUM_LIT> , ops , false ) ;


<s> return __builtin_ia32_ucomilt ( ( __v4sf ) __A , ( __v4sf ) __B ) ;


<s> static SDValue getCCResult ( SelectionDAG & DAG , SDNode * After ) { SDLoc DL ( After ) ; SDValue Glue = SDValue ( After , After -> getNumValues ( ) - <NUM_LIT> ) ; SDValue IPM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Glue ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IPM , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ;


<s> static bool isEndChunk ( uint64_t Chunk ) { if ( Chunk == <NUM_LIT> || Chunk == UINT64_MAX ) return false ;


<s> auto Entry = RegisterReqs . find ( Name . lower ( ) ) ; if ( Entry == RegisterReqs . end ( ) ) return <NUM_LIT> ; if ( Kind == Entry -> getValue ( ) . first ) return Entry -> getValue ( ) . second ; return <NUM_LIT> ;


<s> return selectIntToBool ( IntReg , ResVReg , ArgType , ResType , I ) ; } bool IsSigned = GR . isScalarOrVectorSigned ( ResType ) ; unsigned Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; return selectUnOp ( ResVReg , ResType , I , Opcode ) ;


<s> return <NUM_LIT> - MI . getOperand ( Op ) . getImm ( ) ;


<s> void printS7ImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { int value = MI -> getOperand ( OpNo ) . getImm ( ) ;

value = ( value << ( <NUM_LIT> - <NUM_LIT> ) ) >> ( <NUM_LIT> - <NUM_LIT> ) ;


<s> MachineFunction & MF = B . getMF ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; Register KernArgSegmentPtr = MFI -> getPreloadedReg ( <STR_LIT> ) ; Register KernArgSegmentVReg = MRI . getLiveInVirtReg ( KernArgSegmentPtr ) ;

auto OffsetReg = B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , Offset ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; enum symbol_visibility vis = DECL_VISIBILITY ( decl ) ;


<s> for ( ; MI -> getOperand ( NumDefs ) . isReg ( ) && MI -> getOperand ( NumDefs ) . isDef ( ) ; ++ NumDefs ) ; const char * AsmStr = MI -> getOperand ( NumDefs ) . getSymbolName ( ) ; if ( AsmStr [ <NUM_LIT> ] == <NUM_LIT> ) return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { processReloc ( MI -> getOperand ( <NUM_LIT> ) ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { processReloc ( MI -> getOperand ( <NUM_LIT> ) ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { processFuncPrototypes ( dyn_cast < Function > ( MO . getGlobal ( ) ) ) ; } } const DebugLoc & DL = MI -> getDebugLoc ( ) ; if ( ! DL || PrevInstLoc == DL ) { if ( LineInfoGenerated == false ) { auto * S = MI -> getMF ( ) -> getFunction ( ) . getSubprogram ( ) ; MCSymbol * FuncLabel = Asm -> getFunctionBegin ( ) ;

constructLineInfo ( S , FuncLabel , S -> getLine ( ) , <NUM_LIT> ) ;


<s> unsigned HOST_WIDE_INT ival ; if ( GET_CODE ( x ) == CONST_DOUBLE && SCALAR_FLOAT_MODE_P ( mode ) && aarch64_reinterpret_float_as_int ( x , & ival ) ) { scalar_int_mode imode = ( mode == HFmode ? SImode : int_mode_for_mode ( mode ) . require ( ) ) ; int num_instr = aarch64_internal_mov_immediate ( NULL_RTX , gen_int_mode ( ival , imode ) , false , imode ) ; return num_instr < <NUM_LIT> ; }


<s> SDValue Opnd2 ; if ( isFMAddSubOrFMSubAdd ( Subtarget , DAG , Opnd0 , Opnd1 , Opnd2 , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0 , Opnd1 ) ;


<s> StripThreadLocal ( ) : ModulePass ( ID ) {


<s> MCValue Target ; if ( ! TargetFixup -> getValue ( ) -> evaluateAsValue ( Target , * Layout ) ) return false ; if ( ! Target . getSymA ( ) || ! Target . getSymA ( ) -> getSymbol ( ) . isInSection ( ) ) return false ; if ( & Target . getSymA ( ) -> getSymbol ( ) . getSection ( ) != findAssociatedFragment ( ) -> getParent ( ) ) return false ; uint64_t AUIPCOffset = AUIPCSymbol -> getOffset ( ) ; Res = MCValue :: get ( Target . getSymA ( ) , nullptr , Target . getConstant ( ) + ( Fixup -> getOffset ( ) - AUIPCOffset ) ) ;


<s> if ( Parser . getTargetParser ( ) . ParseRegister ( RegNo , StartLoc , EndLoc ) ) return true ; Parser . clearPendingErrors ( ) ; Res = <STR_LIT> ( RegNo , Parser . getContext ( ) ) ; return false ; }


<s> const bool SrcIsCheri = isCheriPointer ( SrcAS , nullptr ) ;

const bool DestIsCheri = isCheriPointer ( DestAS , nullptr ) ;


<s> void ix86_split_xorsign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , op0 , mask , x ; dest = operands [ <NUM_LIT> ] ;


<s> else OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ;


<s> if ( EnableA53Fix835769 ) addPass ( create<ISA_LIT>A53Fix835769 ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( - UNITS_PER_WORD ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; if ( NumBytes > <NUM_LIT> ) { assert ( ( NumBytes & <NUM_LIT> ) == <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; } EmitComment ( MBB , MBBI , dl , TII , <STR_LIT> ) ;


<s> bool Success = Extender -> getOperand ( <NUM_LIT> ) . getExpr ( ) -> evaluateAsAbsolute ( Bits ) ; assert ( Success ) ; ( void ) Success ; uint32_t Upper26 = static_cast < uint32_t > ( Bits ) ; uint32_t Operand = Upper26 | Lower6 ; return Operand ;


<s> unsigned InNumElts = InVT . getVectorNumElements ( ) ; unsigned OutNumElts = OutVT . getVectorNumElements ( ) ; unsigned NumInPerOut = InNumElts / OutNumElts ; SDValue ZeroVec = DAG . getSplatVector ( InVT , DL , DAG . getConstant ( <NUM_LIT> , DL , InVT . getScalarType ( ) ) ) ; SmallVector < int , <NUM_LIT> > Mask ( InNumElts ) ; unsigned ZeroVecElt = InNumElts ; for ( unsigned PackedElt = <NUM_LIT> ; PackedElt < OutNumElts ; PackedElt ++ ) { unsigned MaskElt = PackedElt * NumInPerOut ; unsigned End = MaskElt + NumInPerOut - <NUM_LIT> ; for ( ; MaskElt < End ; MaskElt ++ ) Mask [ MaskElt ] = ZeroVecElt ++ ; Mask [ MaskElt ] = PackedElt ; } SDValue Shuf = DAG . getVectorShuffle ( InVT , DL , PackedOp , ZeroVec , Mask ) ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Shuf ) ;


<s> default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C :

return selectG_INTRIN<ISA_LIT>C ( I , CoverageInfo ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDNode * P , SDValue N , SDValue & Base , SDValue & Disp , SDValue & Index ) { if ( <STR_LIT> ( N . getNode ( ) ) && IsLegalToFold ( N , P , P , OptLevel ) ) return SelectAddrRRI20 ( P , N . getOperand ( <NUM_LIT> ) , Base , Disp , Index ) ;


<s> } if ( GET_CODE ( op1 ) == SYMBOL_REF || GET_CODE ( op1 ) == LABEL_REF ) { rtx result ; if ( microblaze_tls_symbol_p ( op1 ) ) { result = microblaze_legitimize_tls_address ( op1 , NULL_RTX ) ; emit_move_insn ( op0 , result ) ; return true ; } else if ( flag_pic ) { if ( reload_in_progress ) df_set_regs_ever_live ( PIC_OFFSET_TABLE_REGNUM , true ) ; result = expand_pic_symbol_ref ( mode , op1 ) ; if ( TARGET_PIC_DATA_TEXT_REL && GET_CODE ( op0 ) == REG && REGNO ( op0 ) >= FIRST_PSEUDO_REGISTER ) result = force_reg ( SImode , result ) ; emit_move_insn ( op0 , result ) ; return true ; } } if ( GET_CODE ( op1 ) == PLUS && GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == CONST ) { rtx p0 , p1 = NULL , result , temp ; p0 = XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( p0 ) == PLUS ) { p1 = XEXP ( p0 , <NUM_LIT> ) ; p0 = XEXP ( p0 , <NUM_LIT> ) ; } if ( p1 == NULL ) gcc_unreachable ( ) ; if ( GET_CODE ( p0 ) == UNSPEC && GET_CODE ( p1 ) == CONST_INT && flag_pic && TARGET_PIC_DATA_TEXT_REL ) { result = gen_rtx_CONST ( Pmode , p0 ) ; result = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , result ) ; temp = force_reg ( SImode , result ) ; emit_move_insn ( op0 , gen_rtx_PLUS ( SImode , temp , p1 ) ) ; return true ; } }

if ( GET_CODE ( op1 ) == CONST && GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == PLUS ) {


<s> void onOr ( ) { IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_INTEGER : case IES_RPAREN : case IES_REGISTER : State = IES_OR ; IC . pushOperator ( IC_OR ) ; break ; } PrevState = CurrState ;


<s> for ( auto & MBB : MF ) { if ( MBB . isEHPad ( ) ) { if ( MCAI -> getExceptionHandlingType ( ) == ExceptionHandling :: Wasm && MF . getFunction ( ) . hasPersonalityFn ( ) ) placeTryMarker ( MBB ) ;


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , true ) {


<s> } else { selected_cpu = aarch64_get_tune_cpu ( aarch64_none ) ; aarch64_isa_flags = TARGET_CPU_DEFAULT >> <NUM_LIT> ; } if ( selected_tune ) explicit_tune_core = selected_tune -> ident ; } else if ( selected_arch ) { if ( selected_arch -> arch != selected_cpu -> arch ) { warning ( <NUM_LIT> , <STR_LIT> , all_architectures [ selected_cpu -> arch ] . name , selected_arch -> name ) ; } aarch64_isa_flags = arch_isa ; explicit_arch = selected_arch -> arch ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; } else { aarch64_isa_flags = cpu_isa ; explicit_tune_core = selected_tune ? selected_tune -> ident : selected_cpu -> ident ; gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; explicit_arch = selected_arch -> arch ; } if ( ! selected_arch ) { gcc_assert ( selected_cpu ) ; selected_arch = & all_architectures [ selected_cpu -> arch ] ; } if ( ! selected_tune ) selected_tune = selected_cpu ;

if ( TARGET_ILP32 ) error ( <STR_LIT> ) ;


<s> SmallVector < uint32_t , <NUM_LIT> > OptimizeShuf ; Value * Temp [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i < ( VecElems / <NUM_LIT> ) * Stride ; i += <NUM_LIT> ) { genShuffleBland ( VT , VPShuf , OptimizeShuf , ( i / Stride ) * <NUM_LIT> , ( i + <NUM_LIT> ) / Stride * <NUM_LIT> ) ; Temp [ i / <NUM_LIT> ] = Builder . CreateShuffleVector ( Vec [ i % Stride ] , Vec [ ( i + <NUM_LIT> ) % Stride ] , OptimizeShuf ) ; OptimizeShuf . clear ( ) ; }


<s> if ( TLI . SimplifyDemandedVectorElts ( Src , DemandedElts , KnownUndef , KnownZero , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( IsStrict ) return SDValue ( ) ; if ( <STR_LIT> ( Src . getNode ( ) ) && Src . hasOneUse ( ) ) { LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( LN -> isSimple ( ) ) { SDLoc dl ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ; SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , LN -> getPointerInfo ( ) , LN -> getOriginalAlign ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Convert = DAG . getNode ( N -> getOpcode ( ) , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , VZLoad ) ) ; DCI . CombineTo ( N , Convert ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN , <NUM_LIT> ) , VZLoad . getValue ( <NUM_LIT> ) ) ; return SDValue ( N , <NUM_LIT> ) ; } } }


<s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; auto SysReg = <STR_LIT> ( Imm ) ; if ( SysReg && SysReg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) O << SysReg -> Name ;


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> * <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> * <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> * <NUM_LIT> , <NUM_LIT> } , } ;

if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;


<s> if ( GET_MODE ( op ) == VOIDmode || GET_MODE ( op ) == BLKmode ) { if ( ( SCALAR_INT_MODE_P ( mode ) && GET_CODE ( op ) == CONST_INT ) || GET_MODE ( op ) == BLKmode ) return force_reg ( mode , convert_to_mode ( mode , op , <NUM_LIT> ) ) ; abort ( ) ; } r = force_reg ( GET_MODE ( op ) , op ) ; if ( GET_MODE_SIZE ( GET_MODE ( op ) ) == GET_MODE_SIZE ( mode ) ) { x = simplify_gen_subreg ( mode , r , GET_MODE ( op ) , <NUM_LIT> ) ; if ( x ) return x ; } x = gen_reg_rtx ( mode ) ; emit_insn ( gen_spu_convert ( x , r ) ) ;


<s> if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ;

const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ;


<s> auto STI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; return STI -> isSGPRClass ( RC ) ? ( STI -> getRegSizeInBits ( * RC ) == <NUM_LIT> ? SGPR32 : SGPR_TUPLE ) :

STI -> hasAGPRs ( RC ) ? ( STI -> getRegSizeInBits ( * RC ) == <NUM_LIT> ? AGPR32 : AGPR_TUPLE ) :


<s> bool isRegOrImmWithFP32InputMods ( ) const { return isRegOrImmWithInputMods ( <STR_LIT> , <STR_LIT> ) ;


<s> void InvalidateWithChildren ( Block * New ) { BlockList ToInvalidate ; ToInvalidate . push_back ( New ) ; while ( ! ToInvalidate . empty ( ) ) { Block * Invalidatee = ToInvalidate . front ( ) ; ToInvalidate . pop_front ( ) ; Block * Owner = Ownership [ Invalidatee ] ; if ( contains ( IndependentGroups , Owner ) ) IndependentGroups [ Owner ] . remove ( Invalidatee ) ; if ( Ownership [ Invalidatee ] ) { Ownership [ Invalidatee ] = nullptr ; for ( const auto & iter : Invalidatee -> BranchesOut ) { Block * Target = iter . first ;

BlockBlockMap :: iterator Known = Ownership . find ( Target ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg GPR_64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; switch ( ValVT . SimpleTy ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : assert ( Is<ISA_LIT>64 && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : State . AllocateStack ( PtrByteSize , PtrByteSize ) ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) { MVT RegVT = Is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; if ( ValVT . getSizeInBits ( ) < RegVT . getSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ;

State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ;


<s> } unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ;

O << markup ( <STR_LIT> ) << '#' << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs << markup ( <STR_LIT> ) ;


<s> void BTFTypeTag :: completeType ( BTFDebug & BDebug ) { if ( IsCompleted ) return ; IsCompleted = true ; BTFType . NameOff = BDebug . addString ( Tag ) ;


<s> auto * DesiredClass = TRI -> getRegClass ( RegClassIDs [ NumRegs - <NUM_LIT> ] ) ; auto RegSequence = MIB . buildInstr ( TargetOpcode :: REG_SEQUENCE , { DesiredClass } , { } ) ; for ( unsigned I = <NUM_LIT> , E = Regs . size ( ) ; I < E ; ++ I ) {


<s> const <STR_LIT> & Out = Outs [ i ] ; if ( Out . VT . isVector ( ) ) { MVT VT = Out . VT . getVectorElementType ( ) ; <STR_LIT> NewOut = Out ; NewOut . Flags . setSplit ( ) ; NewOut . VT = VT ; unsigned NumElements = Out . ArgVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j != NumElements ; ++ j ) { SDValue Elem = DAG . getNode ( <STR_LIT> , DL , VT , OutVals [ i ] , DAG . getConstant ( j , DL , <STR_LIT> ) ) ; SplitVals . push_back ( Elem ) ; Splits . push_back ( NewOut ) ; NewOut . PartOffset += NewOut . VT . getStoreSize ( ) ; } } else { SplitVals . push_back ( OutVals [ i ] ) ; Splits . push_back ( Out ) ; } } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturn ( CCInfo , Splits ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> , realRVLocIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = SplitVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; }


<s> for ( MachineBasicBlock * S : Preheader -> successors ( ) ) { if ( S == HB ) continue ; MachineLoop * T = MLI -> getLoopFor ( S ) ; if ( T && T -> getHeader ( ) == S ) return nullptr ; }


<s> if ( L == Seq . end ( ) ) Seq . push_back ( VR ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MachineFunction :: iterator MBBIter = MBB ; ++ MBBIter ; MachineBasicBlock * XMMSaveMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> transferSuccessors ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> void AMDGPUInstPrinter :: printCT ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned CT = MI -> getOperand ( OpNo ) . getImm ( ) ; switch ( CT ) { case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> :


<s> EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) continue ; EVT EltVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = VT . getSizeInBits ( ) / EltVT . getSizeInBits ( ) ; EVT DestVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumSrcElts ) ; if ( SrcVT . getSizeInBits ( ) < VT . getSizeInBits ( ) ) { assert ( <NUM_LIT> * SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getUNDEF ( Src . ShuffleVec . getValueType ( ) ) ) ; continue ; } assert ( SrcVT . getSizeInBits ( ) == <NUM_LIT> * VT . getSizeInBits ( ) ) ; if ( Src . MaxElt - Src . MinElt >= NumSrcElts ) { return SDValue ( ) ; } if ( Src . MinElt >= NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( NumSrcElts ) ) ; Src . WindowBase = - NumSrcElts ; } else if ( Src . MaxElt < NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else { SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getIntPtrConstant ( NumSrcElts ) ) ; unsigned Imm = Src . MinElt * getExtFactor ( VEXTSrc1 ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; Src . WindowBase = - Src . MinElt ; } } for ( auto & Src : Sources ) { EVT SrcEltTy = Src . ShuffleVec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy == SmallestEltTy ) continue ;

assert ( ShuffleVT . getVectorElementType ( ) == SmallestEltTy ) ;


<s> __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>BaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) return FramePtr ;


<s> OutStreamer -> EmitLabel ( CurrentFnSym ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & targetmachine , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( targetmachine , OptLevel ) , Subtarget ( targetmachine . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , TM ( targetmachine ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ) { initialize<ISA_LIT>DAGToDAGISelPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> <ISA_LIT>ABIInfo ( ABI ThisABI ) : ThisABI ( ThisABI ) {


<s> break ; case <STR_LIT> : RNext = <STR_LIT> ; RPair = <STR_LIT> ; break ; case <STR_LIT> : RNext = <STR_LIT> ; RPair = <STR_LIT> ; break ; case <STR_LIT> : RNext = <STR_LIT> ; RPair = <STR_LIT> ; break ; case <STR_LIT> : RNext = <STR_LIT> ; RPair = <STR_LIT> ; break ; } const MCParsedAsmOperand & Op3 = * Operands [ <NUM_LIT> + NumPredOps ] ; if ( ! Op3 . isReg ( ) || Op3 . getReg ( ) != RNext ) return Error ( Op3 . getStartLoc ( ) , <STR_LIT> ) ; Operands . erase ( Operands . begin ( ) + <NUM_LIT> + NumPredOps ) ;

Operands [ <NUM_LIT> + NumPredOps ] = <ISA_LIT>Operand :: CreateReg ( RPair , Op2 . getStartLoc ( ) , Op2 . getEndLoc ( ) ) ;


<s> struct constant_pool * pool , * * prev ; pool = s390_alloc_pool ( ) ;


<s> Register insertAssignInstr ( Register Reg , Type * Ty , <ISA_LIT>Type * SpirvTy , <ISA_LIT>GlobalRegistry * GR , MachineIRBuilder & MIB , MachineRegisterInfo & MRI ) { MachineInstr * Def = MRI . getVRegDef ( Reg ) ; assert ( ( Ty || SpirvTy ) && <STR_LIT> ) ;

MIB . setInsertPt ( * Def -> getParent ( ) , ( Def -> getNextNode ( ) ? Def -> getNextNode ( ) -> getIterator ( ) : Def -> getParent ( ) -> end ( ) ) ) ;


<s> } static unsigned SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned * SETFOpc = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = get<ISA_LIT>ConditionCode ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; unsigned Opc = <STR_LIT> ( CC ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ;


<s> SDValue OneSubA = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue OneSubAC = DAG . getNode ( <STR_LIT> , DL , VT , OneSubA , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , OneSubAC ) ;


<s> Thumb1InstrInfo :: Thumb1InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>BaseInstrInfo ( STI ) {


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ;


<s> unsigned OpNum = ( PFEntry >> <NUM_LIT> ) & <NUM_LIT> ; unsigned LHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned RHSID = ( PFEntry >> <NUM_LIT> ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; enum { OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ;


<s> GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = IsOptNone ? nullptr : & getAnalysis < MachineDominatorTree > ( ) ;

<ISA_LIT>RegBankCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , LI , KB , MDT ) ;


<s> int total_frame_size ( ) { unsigned int size = get_frame_size ( ) ; unsigned int outgoing_args_size = current_function_outgoing_args_size ; int i ; if ( optimize && ! current_function_needs_context && ! frame_pointer_needed ) { int inline_count , outline_count ; inline_count = <NUM_LIT> ; if ( regs_ever_live [ <NUM_LIT> ] ) inline_count += <NUM_LIT> ; if ( regs_ever_live [ <NUM_LIT> ] ) inline_count += <NUM_LIT> ; if ( regs_ever_live [ <NUM_LIT> ] ) inline_count += <NUM_LIT> ; if ( regs_ever_live [ <NUM_LIT> ] ) inline_count += <NUM_LIT> ;


<s> static bool isCPUValid ( std :: string CPU ) { std :: vector < std :: string > table { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; return std :: find ( table . begin ( ) , table . end ( ) , CPU ) != table . end ( ) ;


<s> if ( Vector ) return <NUM_LIT> ; else return <NUM_LIT> ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; auto & DL = MF -> getDataLayout ( ) ;

return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( DL ) ) . getNode ( ) ;


<s> if ( UseMI -> getParent ( ) != MBB ) return Reg ; while ( UseMI -> isCopy ( ) || UseMI -> isInsertSubreg ( ) ) { Reg = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isPhysicalRegister ( Reg ) || ! MRI -> hasOneNonDBGUse ( Reg ) ) return Reg ; UseMI = & * MRI -> use_instr_nodbg_begin ( Reg ) ; if ( UseMI -> getParent ( ) != MBB ) return Reg ;


<s> SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , RHS ) ; } } } return SDValue ( ) ;


<s> if ( eax == <NUM_LIT> ) return ; asm volatile ( <STR_LIT> : <STR_LIT> ( eax ) , <STR_LIT> ( ebx ) , <STR_LIT> ( ecx ) , <STR_LIT> ( edx ) : <STR_LIT> ( <NUM_LIT> ) ) ; if ( edx & SSE ) { unsigned int mxcsr = __builtin_ia32_stmxcsr ( ) ; mxcsr |= MXCSR_FTZ ; if ( edx & FXSAVE ) { struct { unsigned short int cwd ; unsigned short int swd ; unsigned short int twd ; unsigned short int fop ; long int fip ;


<s> static void ft32_setup_incoming_varargs ( cumulative_args_t cum_v , enum machine_mode mode , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;

int named_size = GET_MODE_SIZE ( SImode ) * ( * cum - FT32_R0 ) + GET_MODE_SIZE ( mode ) ;


return isImm ( ) && isField16 ( getImm ( ) ) ;


<s> MachineInstr * DefMI = MRI . getVRegDef ( SrcReg ) ; unsigned SMovOp ; int64_t Imm ; if ( isSafeToFoldImmIntoCopy ( & MI , DefMI , TII , SMovOp , Imm ) ) { MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Imm ) ; MI . addImplicitDefUseOperands ( MF ) ; MI . setDesc ( TII -> get ( SMovOp ) ) ; break ; } TII -> moveToVALU ( MI ) ; } else if ( isSGPRToVGPRCopy ( SrcRC , DstRC , * TRI ) ) { tryChangeVGPRtoSGPRinCopy ( MI , TRI , TII ) ; } break ; } case <STR_LIT> : { unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRClass ( MRI . getRegClass ( Reg ) ) ) break ; bool HasVGPROperand = phiHasVGPROperands ( MI , MRI , TRI , TII ) ; if ( MI . getNumExplicitOperands ( ) == <NUM_LIT> && ! HasVGPROperand ) { MachineBasicBlock * MBB0 = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock * MBB1 = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! predsHasDivergentTerminator ( MBB0 , TRI ) && ! predsHasDivergentTerminator ( MBB1 , TRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI << '\n' ) ; break ; } } SmallSet < unsigned , <NUM_LIT> > Visited ; if ( HasVGPROperand || ! phiHasBreakDef ( MI , MRI , Visited ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; } break ; } case <STR_LIT> : if ( TRI -> hasVGPRs ( TII -> getOpRegClass ( MI , <NUM_LIT> ) ) || ! hasVGPROperands ( MI , TRI ) ) { foldVGPRCopyIntoRegSequence ( MI , TRI , TII , MRI ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; break ; case <STR_LIT> : { const TargetRegisterClass * DstRC , * Src0RC , * Src1RC ; DstRC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Src0RC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Src1RC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TRI -> isSGPRClass ( DstRC ) && ( TRI -> hasVGPRs ( Src0RC ) || TRI -> hasVGPRs ( Src1RC ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; } break ; } } }


<s> emitExternalSymbolAddress ( const char * ES , unsigned Reloc ) const { MCE . addRelocation ( MachineRelocation :: getExtSym ( MCE . getCurrentPCOffset ( ) , Reloc , ES ) ) ;


<s> bool isEndPacket ( ) const { return ( endPacket ) ;


<s> int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> ) ; int Offset = ( spOffset < <NUM_LIT> ) ? ( stackSize - spOffset ) : ( spOffset + <NUM_LIT> ) ; Offset += MI . getOperand ( oi ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; MI . getOperand ( oi ) . ChangeToImmediate ( Offset ) ; MI . getOperand ( i ) . ChangeToRegister ( getFrameRegister ( MF ) , false ) ; return <NUM_LIT> ;


<s> IsaInfo :: streamIsaVersion ( getGlobalSTI ( ) , ExpectedTargetOS ) ; getTargetStreamer ( ) -> EmitDirectiveAMDGCNTarget ( ExpectedTarget ) ; } if ( TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA && TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDPAL ) return ; if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) HSAMetadataStream -> begin ( M ) ;

if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) readPALMetadata ( M ) ;


<s> int legitimate_constant_address_p ( rtx x ) { return ( GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST_INT || GET_CODE ( x ) == CONST || GET_CODE ( x ) == HIGH ) ;


<s> unsigned <ISA_LIT>MachineFunctionInfo :: addDispatchID ( const <ISA_LIT>RegisterInfo & TRI ) { ArgInfo . DispatchID = ArgDescriptor :: createRegister ( TRI . getMatchingSuperReg ( getNextUserSGPR ( ) , <STR_LIT> , & <STR_LIT> ) ) ;


<s> return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return true ; auto Keyword = Tok . getString ( ) ; Keyword = StringSwitch < StringRef > ( Keyword . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Keyword ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Keyword , Tok . getLoc ( ) , getContext ( ) ) ) ;


<s> void <ISA_LIT>MCInst :: setPacketEnd ( bool Y ) {


<s> LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; SDValue Chain = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; MachineMemOperand * MMO = LD -> getMemOperand ( ) ; SDValue NewLD = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( DAG . getDataLayout ( ) ) , Chain , BasePtr , <STR_LIT> , MMO ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewLD ) ; SDValue Ops [ ] = { Result , SDValue ( NewLD . getNode ( ) , <NUM_LIT> ) } ;

return DAG . getMergeValues ( Ops , dl ) ;


emit_move_insn ( tmp , copy_rtx ( XEXP ( mem , <NUM_LIT> ) ) ) ;


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ;


<s> unsigned HOST_WIDE_INT const1 ; unsigned HOST_WIDE_INT const2 = <NUM_LIT> ; if ( ! CONST_INT_P ( XEXP ( op0 , <NUM_LIT> ) ) ) return false ; const1 = UINTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ; if ( ! CONST_INT_P ( XEXP ( op1 , <NUM_LIT> ) ) || ~ UINTVAL ( XEXP ( op1 , <NUM_LIT> ) ) != const1 ) return false ; if ( GET_CODE ( XEXP ( op0 , <NUM_LIT> ) ) == ASHIFT && CONST_INT_P ( XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ) ) { const2 = UINTVAL ( XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ) ;

* sub0 = XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; Spill . FullyAllocated = true ; BitVector OtherUsedRegs ; OtherUsedRegs . resize ( TRI -> getNumRegs ( ) ) ; const uint32_t * CSRMask = TRI -> getCallPreservedMask ( MF , MF . getFunction ( ) . getCallingConv ( ) ) ; if ( CSRMask ) OtherUsedRegs . setBitsInMask ( CSRMask ) ; for ( MCPhysReg Reg : SpillAGPR ) OtherUsedRegs . set ( Reg ) ; for ( MCPhysReg Reg : SpillVGPR ) OtherUsedRegs . set ( Reg ) ; SmallVectorImpl < MCPhysReg > :: const_iterator NextSpillReg = Regs . begin ( ) ; for ( int I = NumLanes - <NUM_LIT> ; I >= <NUM_LIT> ; -- I ) { NextSpillReg = std :: find_if ( NextSpillReg , Regs . end ( ) , [ & MRI , & OtherUsedRegs ] ( MCPhysReg Reg ) { return MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) && ! OtherUsedRegs [ Reg ] ;


<s> NumModuleValues = Values . size ( ) ; incorporateFunctionMetadata ( F ) ; for ( const auto & I : F . args ( ) ) { EnumerateValue ( & I ) ; if ( I . hasAttribute ( Attribute :: ByVal ) ) EnumerateType ( I . getParamByValType ( ) ) ; else if ( I . hasAttribute ( Attribute :: StructRet ) ) EnumerateType ( I . getParamStructRetType ( ) ) ; else if ( I . hasAttribute ( Attribute :: ByRef ) ) EnumerateType ( I . getParamByRefType ( ) ) ; } FirstFuncConstantID = Values . size ( ) ; for ( const BasicBlock & BB : F ) { for ( const Instruction & I : BB ) { for ( const Use & OI : I . operands ( ) ) { if ( ( isa < Constant > ( OI ) && ! isa < GlobalValue > ( OI ) ) || isa < InlineAsm > ( OI ) ) EnumerateValue ( OI ) ; } if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( & I ) ) EnumerateValue ( SVI -> getShuffleMaskForBitcode ( ) ) ;


<s> for ( auto Ty : { s8 , s16 , s32 , s64 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , s64 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ;

setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createToken ( std :: string Str , SMLoc S , bool isInt = false , bool hasIntSign = false , bool hasIntType = false , unsigned intVal = <NUM_LIT> ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ; Op -> IsInt = isInt ; Op -> HasIntSign = hasIntSign ; Op -> HasIntType = hasIntType ; Op -> IntVal = intVal ; Op -> StartLoc = S ;


<s> bool isSafe = false ; I = CmpInstr ; E = CmpInstr . getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC ; bool IsInstrVSel = true ; switch ( Instr . getOpcode ( ) ) { default : IsInstrVSel = false ; CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( SubAdd ) { unsigned Opc = SubAdd -> getOpcode ( ) ; bool IsSub = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; unsigned OpI = Opc != <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ! IsSub || ( SrcReg2 != <NUM_LIT> && SubAdd -> getOperand ( OpI ) . getReg ( ) == SrcReg2 && SubAdd -> getOperand ( OpI + <NUM_LIT> ) . getReg ( ) == SrcReg ) ) { if ( IsInstrVSel ) return false ; <STR_LIT> NewCC = ( IsSub ? getSwappedCondition ( CC ) : getCmpToAddCondition ( CC ) ) ; if ( NewCC == <STR_LIT> ) return false ; OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } } else { switch ( CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } } }


<s> bool MustExtend = MO . getTargetFlags ( ) & <STR_LIT> ; switch ( MO . getType ( ) ) { default : MI -> print ( errs ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCO = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_FPImmediate : { APFloat Val = MO . getFPImm ( ) -> getValueAPF ( ) ; auto Expr = <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( * Val . bitcastToAPInt ( ) . getRawData ( ) , AP . OutContext ) , AP . OutContext ) ; <ISA_LIT>MCInstrInfo :: setMustExtend ( * Expr , MustExtend ) ; MCO = MCOperand :: createExpr ( Expr ) ; break ; } case MachineOperand :: MO_Immediate : { auto Expr = <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( MO . getImm ( ) , AP . OutContext ) , AP . OutContext ) ; <ISA_LIT>MCInstrInfo :: setMustExtend ( * Expr , MustExtend ) ; MCO = MCOperand :: createExpr ( Expr ) ; break ; } case MachineOperand :: MO_MachineBasicBlock : { MCExpr const * Expr = MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ; Expr = <ISA_LIT>MCExpr :: create ( Expr , AP . OutContext ) ; <ISA_LIT>MCInstrInfo :: setMustExtend ( * Expr , MustExtend ) ; MCO = MCOperand :: createExpr ( Expr ) ; break ; } case MachineOperand :: MO_GlobalAddress : MCO = GetSymbolRef ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP , MustExtend ) ;


WaitStatesNeeded = std :: max ( WaitStatesNeeded , WaitStatesNeededForUse ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ;


<s> VGPRBlocks ( <NUM_LIT> ) , SGPRBlocks ( <NUM_LIT> ) , Priority ( <NUM_LIT> ) , FloatMode ( <NUM_LIT> ) , Priv ( <NUM_LIT> ) , DX10Clamp ( <NUM_LIT> ) , DebugMode ( <NUM_LIT> ) , IEEEMode ( <NUM_LIT> ) , ScratchSize ( <NUM_LIT> ) , ComputePGMRSrc1 ( <NUM_LIT> ) , LDSBlocks ( <NUM_LIT> ) , ScratchBlocks ( <NUM_LIT> ) , ComputePGMRSrc2 ( <NUM_LIT> ) , NumVGPR ( <NUM_LIT> ) , NumSGPR ( <NUM_LIT> ) , FlatUsed ( false ) , VCCUsed ( false ) , CodeLen ( <NUM_LIT> ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Module & M , const std :: string & FS ) : Subtarget ( * this , M , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( ) , FrameInfo ( * this ) , TLInfo ( * this ) {


<s> if ( VecTy . getNumElements ( ) == <NUM_LIT> ) { Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; assert ( VecTy . getNumElements ( ) == <NUM_LIT> ) ; } break ; case <NUM_LIT> : assert ( VecTy . getNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; Opc = <STR_LIT> ; break ; } } assert ( Opc && <STR_LIT> ) ; if ( IsFP ) { MachineInstr * Widen = emitScalarToVector ( EltTy . getSizeInBits ( ) , & <STR_LIT> , ScalarReg , MIB ) ; if ( ! Widen ) return false ; ScalarReg = Widen -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } auto Dup = MIB . buildInstr ( Opc , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { ScalarReg } ) ; if ( IsFP ) Dup . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( * Dup , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return true ;


<s> return new <ISA_LIT>RegisterCounter ( ) ;


<s> if ( LoRegsToSave . count ( Reg ) ) { bool isKill = ! MF . getRegInfo ( ) . isLiveIn ( Reg ) ; if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; } static const unsigned AllCopyRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned AllHighRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned * AllCopyRegsEnd = std :: end ( AllCopyRegs ) ; const unsigned * AllHighRegsEnd = std :: end ( AllHighRegs ) ; const unsigned * HiRegToSave = findNextOrderedReg ( std :: begin ( AllHighRegs ) , HiRegsToSave , AllHighRegsEnd ) ; while ( HiRegToSave != AllHighRegsEnd ) { const unsigned * CopyReg = findNextOrderedReg ( std :: begin ( AllCopyRegs ) , CopyRegs , AllCopyRegsEnd ) ; MachineInstrBuilder PushMIB = BuildMI ( MF , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) ; SmallVector < unsigned , <NUM_LIT> > RegsToPush ; while ( HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd ) { if ( HiRegsToSave . count ( * HiRegToSave ) ) { bool isKill = ! MF . getRegInfo ( ) . isLiveIn ( * HiRegToSave ) ; if ( isKill ) MBB . addLiveIn ( * HiRegToSave ) ;

BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( * CopyReg , RegState :: Define ) . addReg ( * HiRegToSave , getKillRegState ( isKill ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ;


<s> const MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) { if ( ! TFI . hasFP ( MF ) ) report_fatal_error ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ;


<s> if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned LR = <STR_LIT> ; MFI . setReturnAddressIsTaken ( true ) ; unsigned Reg = MF . addLiveIn ( LR , getRegClassFor ( VT ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , SDLoc ( Op ) , Reg , VT ) ;


<s> if ( const ExternalSymbolSDNode * G = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) FuncName = G -> getSymbol ( ) ; else if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) FuncName = G -> getGlobal ( ) -> getName ( ) ; DiagnosticInfoUnsupported NoCalls ( Fn , Reason + FuncName , CLI . DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( NoCalls ) ; if ( ! CLI . IsTailCall ) { for ( unsigned I = <NUM_LIT> , E = CLI . Ins . size ( ) ; I != E ; ++ I ) InVals . push_back ( DAG . getUNDEF ( CLI . Ins [ I ] . VT ) ) ; }


<s> return __builtin_ia32_comigt ( ( __v4sf ) __A , ( __v4sf ) __B ) ;


<s> __inline__ static void sh_media_TRAPA ( unsigned long long mm ) { __asm__ __volatile__ ( <STR_LIT> : : <STR_LIT> ( mm ) ) ;


<s> } if ( AluDestReg == IndexReg ) { if ( BaseReg == IndexReg ) return false ; std :: swap ( BaseReg , IndexReg ) ; std :: swap ( KilledBase , KilledIndex ) ; } if ( BaseReg == IndexReg ) KilledBase = nullptr ; MachineInstr * NewMI1 , * NewMI2 ; unsigned NewOpcode = AluI -> getOpcode ( ) ; NewMI1 = BuildMI ( MBB , InsertPos , AluI -> getDebugLoc ( ) , TII -> get ( NewOpcode ) , AluDestReg ) . addReg ( AluDestReg , RegState :: Kill ) . addReg ( BaseReg , KilledBase ? RegState :: Kill : <NUM_LIT> ) ; NewMI1 -> addRegisterDead ( <STR_LIT> , TRI ) ;

NewMI2 = BuildMI ( MBB , InsertPos , AluI -> getDebugLoc ( ) , TII -> get ( NewOpcode ) , AluDestReg ) . addReg ( AluDestReg , RegState :: Kill ) . addReg ( IndexReg , KilledIndex ? RegState :: Kill : <NUM_LIT> ) ;


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> int CondCode = CD -> getSExtValue ( ) ; if ( CondCode < FCmpInst :: Predicate :: FIRST_FCMP_PREDICATE || CondCode > FCmpInst :: Predicate :: LAST_FCMP_PREDICATE ) { return DAG . getUNDEF ( VT ) ; } SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; EVT CmpVT = Src0 . getValueType ( ) ; SDLoc SL ( N ) ; if ( CmpVT == <STR_LIT> && ! TLI . isTypeLegal ( CmpVT ) ) { Src0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src0 ) ; Src1 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src1 ) ; } FCmpInst :: Predicate IcInput = static_cast < FCmpInst :: Predicate > ( CondCode ) ; <STR_LIT> CCOpcode = getFCmpCondCode ( IcInput ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Src0 , Src1 , DAG . getCondCode ( CCOpcode ) ) ;


return ( __m256i ) __builtin_ia32_pbroadcastb256_gpr_mask ( __A , ( __v32qi ) _mm256_setzero_si256 ( ) , __M ) ;


<s> static void EmitTST ( MCStreamer & Out , unsigned Reg ) { const unsigned Mask = <NUM_LIT> ; MCInst TSTInst ; TSTInst . setOpcode ( <STR_LIT> ) ; TSTInst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; if ( FlagSfiZeroMask ) { TSTInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; } else { TSTInst . addOperand ( MCOperand :: CreateImm ( Mask ) ) ;


<s> if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = RoundUpToAlignment ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) mergeSPUpdatesUp ( MBB , MBBI , StackPtr , & NumBytes ) ; if ( TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ;

uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ;


<s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const {

static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = {


<s> int s390_label_align ( rtx_insn * label ) { rtx_insn * prev_insn = prev_active_insn ( label ) ; rtx set , src ; if ( prev_insn == NULL_RTX ) goto old ; set = single_set ( prev_insn ) ; if ( set == NULL_RTX ) goto old ; src = SET_SRC ( set ) ; if ( GET_CODE ( src ) == UNSPEC && XINT ( src , <NUM_LIT> ) == UNSPEC_MAIN_BASE ) return <NUM_LIT> ; old :

return align_labels . levels [ <NUM_LIT> ] . log ;


<s> MachineInstr * Clone = MF -> CloneMachineInstr ( DBI ) ; Clone -> getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; MBB -> insert ( Insert , Clone ) ;


<s> if ( ! CN1 ) return SDValue ( ) ; const ConstantSDNode * CAdd = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! CAdd ) return SDValue ( ) ; APInt Offset = CAdd -> getAPIntValue ( ) << CN1 -> getAPIntValue ( ) ; if ( ! canFoldOffset ( Offset . getZExtValue ( ) , AddrSpace , * getSubtarget ( ) ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue ShlX = DAG . getNode ( <STR_LIT> , SL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ; SDValue COffset = DAG . getConstant ( Offset , SL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SL , VT , ShlX , COffset ) ;