<s> arc_regno_reg_class [ R30_REG ] = GENERAL_REGS ; } } if ( TARGET_MUL64_SET ) { fix_start = R57_REG ; fix_end = R59_REG ; strcpy ( rname57 , <STR_LIT> ) ; strcpy ( rname58 , <STR_LIT> ) ; strcpy ( rname59 , <STR_LIT> ) ; } if ( arc_tp_regno != - <NUM_LIT> ) fixed_regs [ arc_tp_regno ] = call_used_regs [ arc_tp_regno ] = <NUM_LIT> ; if ( TARGET_MULMAC_32BY16_SET ) { fix_start = MUL32x16_REG ; fix_end = fix_end > R57_REG ? fix_end : R57_REG ; strcpy ( rname56 , TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ; strcpy ( rname57 , TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ; } for ( regno = fix_start ; regno <= fix_end ; regno ++ ) { if ( ! fixed_regs [ regno ] ) warning ( <NUM_LIT> , <STR_LIT> , regno ) ; fixed_regs [ regno ] = call_used_regs [ regno ] = <NUM_LIT> ; } if ( TARGET_RF16 ) { for ( i = R4_REG ; i <= R9_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; for ( i = R16_REG ; i <= R25_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; } if ( TARGET_HS ) for ( regno = R1_REG ; regno < R32_REG ; regno += <NUM_LIT> ) arc_hard_regno_modes [ regno ] = S_MODES ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( i < ILINK1_REG ) { if ( ( i <= R3_REG ) || ( ( i >= R12_REG ) && ( i <= R15_REG ) ) ) arc_regno_reg_class [ i ] = ARCOMPACT16_REGS ; else arc_regno_reg_class [ i ] = GENERAL_REGS ; } else if ( i < LP_COUNT ) arc_regno_reg_class [ i ] = GENERAL_REGS ; else arc_regno_reg_class [ i ] = NO_REGS ; arc_regno_reg_class [ CC_REG ] = NO_REGS ; arc_regno_reg_class [ FRAME_POINTER_REGNUM ] = GENERAL_REGS ; arc_regno_reg_class [ ARG_POINTER_REGNUM ] = GENERAL_REGS ; if ( TARGET_DPFP ) for ( i = R40_REG ; i < R44_REG ; ++ i ) { arc_regno_reg_class [ i ] = DOUBLE_REGS ; if ( ! TARGET_ARGONAUT_SET ) CLEAR_HARD_REG_BIT ( reg_class_contents [ GENERAL_REGS ] , i ) ; } else { arc_regno_reg_class [ R40_REG ] = ALL_REGS ; arc_regno_reg_class [ R41_REG ] = ALL_REGS ; arc_regno_reg_class [ R42_REG ] = ALL_REGS ; arc_regno_reg_class [ R43_REG ] = ALL_REGS ; fixed_regs [ R40_REG ] = <NUM_LIT> ; fixed_regs [ R41_REG ] = <NUM_LIT> ; fixed_regs [ R42_REG ] = <NUM_LIT> ; fixed_regs [ R43_REG ] = <NUM_LIT> ; arc_hard_regno_modes [ R40_REG ] = <NUM_LIT> ; arc_hard_regno_modes [ R42_REG ] = <NUM_LIT> ; } if ( TARGET_SIMD_SET ) { gcc_assert ( ARC_FIRST_SIMD_VR_REG == <NUM_LIT> ) ; gcc_assert ( ARC_LAST_SIMD_VR_REG == <NUM_LIT> ) ; for ( i = ARC_FIRST_SIMD_VR_REG ; i <= ARC_LAST_SIMD_VR_REG ; i ++ ) arc_regno_reg_class [ i ] = SIMD_VR_REGS ;


<s> ++ NumMovwMovt ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; RelAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; RelAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; } SDValue SB = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , SB , RelAddr ) ; return Result ; } if ( Subtarget -> useMovt ( ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ;


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ;


<s> emitVersion ( ) ; emitTargetID ( TargetID ) ; emitPrintf ( Mod ) ; getRootMetadata ( <STR_LIT> ) = HSAMetadataDoc -> getArrayNode ( ) ;


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'd' : case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Subtarget . isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget . isSingleFloat ( ) ) ) { if ( Subtarget . isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'l' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return PerformADDCombine ( N , DCI ) ;

case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ;


<s> ++ RI ; assert ( RI -> getOpcode ( ) == <STR_LIT> && RI -> getOperand ( <NUM_LIT> ) . isReg ( ) && RI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && RI -> getOperand ( <NUM_LIT> ) . isReg ( ) && RI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; ++ RI ; MachineBasicBlock :: instr_iterator FI ( RI . base ( ) ) ; MBB . splice ( std :: next ( I ) , & MBB , FI , I ) ; FilledSlots += <NUM_LIT> ; } else {

if ( ! NopDelaySlotFiller && findDelayInstr ( MBB , I , J ) ) {


<s> bool <ISA_LIT>FastISel :: emitIntSExt32r2 ( MVT SrcVT , unsigned SrcReg , MVT DestVT , unsigned DestReg ) { switch ( SrcVT . SimpleTy ) { default : return false ;


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << <STR_LIT> << Value << <STR_LIT> ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> while ( ! WorkList . empty ( ) ) { auto Item = WorkList . back ( ) ; WorkList . pop_back ( ) ; IRBuilder < > IRB ( Item ) ; if ( isa < ConstantInt > ( Item -> getLength ( ) ) ) OptimizeMemCopy ( IRB , Item ) ;

else if ( MemCpyInst * Memcpy = dyn_cast < MemCpyInst > ( Item ) ) expandMemCpyAsLoop ( Memcpy , TTI ) ;


<s> SDLoc DL ( Op ) ; SDValue Ops [ <NUM_LIT> ] ; if ( is32Bit ( VT ) ) lowerMUL_LOHI32 ( DAG , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; else { SDValue C63 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue LL = Op . getOperand ( <NUM_LIT> ) ; SDValue RL = Op . getOperand ( <NUM_LIT> ) ; SDValue LH = DAG . getNode ( <STR_LIT> , DL , VT , LL , C63 ) ; SDValue RH = DAG . getNode ( <STR_LIT> , DL , VT , RL , C63 ) ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , LL , RL , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SDValue NegLLTimesRH = DAG . getNode ( <STR_LIT> , DL , VT , LL , RH ) ; SDValue NegLHTimesRL = DAG . getNode ( <STR_LIT> , DL , VT , LH , RL ) ; SDValue NegSum = DAG . getNode ( <STR_LIT> , DL , VT , NegLLTimesRH , NegLHTimesRL ) ; Ops [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Ops [ <NUM_LIT> ] , NegSum ) ; }

return DAG . getMergeValues ( Ops , DL ) ;


<s> RedundantInstrElimination ( BitTracker & bt , const <ISA_LIT>InstrInfo & hii , const <ISA_LIT>RegisterInfo & hri , MachineRegisterInfo & mri ) : Transformation ( true ) , HII ( hii ) , HRI ( hri ) , MRI ( mri ) , BT ( bt ) {


<s> Streamer . emitDataRegion ( MCDR_DataRegion ) ; for ( const ConstantPoolEntry & Entry : Entries ) { Streamer . emitCodeAlignment ( Entry . Size , Streamer . getContext ( ) . getSubtargetInfo ( ) ) ;

Streamer . emitLabel ( Entry . Label ) ;


<s> if ( decl == NULL_TREE ) decl = current_function_decl ; return lookup_attribute ( func_attr , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ;


<s> if ( TheTriple . isOSWindows ( ) ) assert ( <NUM_LIT> && <STR_LIT> ) ;

return new ELF<ISA_LIT>AsmBackend ( T , TheTriple . getOS ( ) ) ;


<s> Value * <ISA_LIT>TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ;

Value * LoHi = Builder . CreateCall ( Ldxr , Addr , <STR_LIT> ) ;


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_<ISA_LIT> , true ) {


<s> src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( GET_CODE ( src ) == MEM && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( GET_CODE ( dest ) == MEM && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ;

if ( * base == NULL_RTX || * offset == NULL_RTX ) fusion = SCHED_FUSION_NONE ;


<s> <ISA_LIT>TargetELFStreamer ( MCStreamer & S ) : <ISA_LIT>TargetStreamer ( S ) , CurrentVendor ( <STR_LIT> ) {


<s> explicit <ISA_LIT>IntelAsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , const TargetAsmInfo * T , bool V ) : AsmPrinter ( O , TM , T , V ) {


<s> if ( Subtarget . isGP64bit ( ) ) { Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Register ( ) ) ; if ( Reg ) return Reg ; } else { Register Reg = StringSwitch < Register > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( Register ( ) ) ; if ( Reg ) return Reg ; } report_fatal_error ( <STR_LIT> ) ;


<s> unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; int delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ; BBSizes [ UserMBB -> getNumber ( ) ] += delta ; AdjustBBOffsetsAfter ( UserMBB , delta ) ; } else { unsigned BaseInsertOffset = UserOffset + U . MaxDisp - <NUM_LIT> ; if ( BaseInsertOffset >= BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] ) BaseInsertOffset = BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] - ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = BaseInsertOffset + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = <NUM_LIT> ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm :: next ( MI ) ) { if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! OffsetIsInRange ( Offset , EndInsertOffset , U . MaxDisp , U . NegOk , U . IsSoImm ) ) { BaseInsertOffset -= ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; EndInsertOffset -= ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; } EndInsertOffset += CPUsers [ CPUIndex ] . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; }

if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = MI ;


<s> return __builtin_aarch64_uqshrn_nv4si_uus ( __a , __b ) ;


<s> Streamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . emitBytes ( <STR_LIT> ) ; Streamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> const RegisterBankInfo :: InstructionMapping & <ISA_LIT>RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { const InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : return getSameOperandsMapping ( MI , false ) ; break ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; break ;


<s> void <ISA_LIT>TTIImpl :: getUnrollingPreferences ( Loop * L , TTI :: UnrollingPreferences & UP ) { BaseT :: getUnrollingPreferences ( L , UP ) ; UP . Partial = UP . Runtime = true ;

UP . PartialThreshold = UP . Threshold / <NUM_LIT> ;


<s> } Function * NewF = findFunction ( CallerBits , & F ) ; if ( ! NewF ) { FeatureBitset NewFeatures ( ( CalleeBits & ~ TargetFeatures ) | CallerBits ) ; if ( ! AllowClone ) { setFeatures ( F , NewFeatures ) ; NewRoots . insert ( & F ) ; Changed = true ; break ; } NewF = cloneWithFeatures ( F , NewFeatures ) ; Clones . push_back ( Clone ( CallerBits , & F , NewF ) ) ; NewRoots . insert ( NewF ) ; } ToReplace . push_back ( std :: make_pair ( CI , NewF ) ) ; Replaced . insert ( & F ) ; Changed = true ; } while ( ! ToReplace . empty ( ) ) { auto R = ToReplace . pop_back_val ( ) ; R . first -> setCalledFunction ( R . second ) ; } } } while ( ! NewRoots . empty ( ) ) ;


<s> unsigned int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) {

ix86_emit_save_reg_using_mov ( word_mode , regno , cfa_offset ) ;


<s>
const
char
*
JTEntryDirective
=
MAI
->
getData32bitsDirective
(
)
;
const
MachineJumpTableInfo
*
MJTI
=
MF
->
getJumpTableInfo
(
)
;
const
std
::
vector
<
MachineJumpTableEntry
>
&
JT
=
MJTI
->
getJumpTables
(
)
;
const
std
::
vector
<
MachineBasicBlock
*
>
&
JTBBs
=
JT
[
JTI
]
.
MBBs
;
bool
UseSet
=
MAI
->
hasSetDirective
(
)
&&
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
SmallPtrSet
<
MachineBasicBlock
*
,
<NUM_LIT>
>
JTSets
;
for
(
unsigned
i
=
<NUM_LIT>
,
e
=
JTBBs
.
size
(
)
;
i
!=
e
;
++
i
)
{
MachineBasicBlock
*
MBB
=
JTBBs
[
i
]
;
bool
isNew
=
JTSets
.
insert
(
MBB
)
;
if
(
UseSet
&&
isNew
)
{
O
<<
<STR_LIT>
<<
*
Get<ISA_LIT>SetPICJumpTableLabel2
(
JTI
,
MO2
.
getImm
(
)
,
MBB
)
<<
','
<<
*
MBB
->
getSymbol
(
OutContext
)
<<
'-'
<<
*
JTISymbol
<<
'\n'
;
}
O
<<
JTEntryDirective
<<
' '
;
if
(
UseSet
)
O
<<
*
Get<ISA_LIT>SetPICJumpTableLabel2
(
JTI
,
MO2
.
getImm
(
)
,
MBB
)
;
else
if
(
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
)
O
<<
*
MBB
->
getSymbol
(
OutContext
)
<<
'-'
<<
*
JTISymbol
;
else
O
<<
*
MBB
->
getSymbol
(
OutContext
)
;


<s> forwardITPosition ( ) ; forwardVPTPosition ( ) ; return true ; } { bool wasInITBlock = inITBlock ( ) ; while ( processInstruction ( Inst , Operands , Out ) ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Inst . dump_pretty ( dbgs ( ) , MII . getName ( Inst . getOpcode ( ) ) ) ; dbgs ( ) << <STR_LIT> ) ; if ( wasInITBlock && hasV8Ops ( ) && isThumb ( ) && ! isV8EligibleForIT ( & Inst ) ) { Warning ( IDLoc , <STR_LIT> ) ; } } forwardITPosition ( ) ; forwardVPTPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ;


<s> MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ;


<s> AM . Scale = <NUM_LIT> ; } } if ( TM . getCodeModel ( ) == CodeModel :: Small && Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == <NUM_LIT> && AM . IndexReg . getNode ( ) == <NUM_LIT> && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > LocalIns ; if ( <STR_LIT> ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ;


<s> tree fndecl = add_builtin_function ( d -> name , nios2_ftype ( d -> ftype ) , i , BUILT_IN_MD , NULL , NULL ) ; nios2_register_builtin_fndecl ( i , fndecl ) ; }


<s> } } BitVector Available = rs . getRegsAvailable ( & <STR_LIT> ) ; Available &= Candidates ; unsigned FirstRegSaved = <NUM_LIT> , SecondRegSaved = <NUM_LIT> ; unsigned FirstRegSavedTo = <NUM_LIT> , SecondRegSavedTo = <NUM_LIT> ; Reg = Available . find_first ( ) ; if ( Reg == - <NUM_LIT> ) { Reg = Candidates . find_first ( ) ; Candidates . reset ( Reg ) ; if ( DefReg != Reg ) { FirstRegSaved = Reg ; FirstRegSavedTo = <STR_LIT> ; copyPhysReg ( MBB , II , DL , FirstRegSavedTo , FirstRegSaved , true ) ; } } else Available . reset ( Reg ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , Reg ) . addImm ( Imm ) . addImm ( - <NUM_LIT> ) ; NewImm = <NUM_LIT> ; if ( FrameReg == <STR_LIT> ) { SpReg = Available . find_first ( ) ; if ( SpReg == - <NUM_LIT> ) { SpReg = Candidates . find_first ( ) ; if ( DefReg != SpReg ) { SecondRegSaved = SpReg ; SecondRegSavedTo = <STR_LIT> ; } if ( SecondRegSaved ) copyPhysReg ( MBB , II , DL , SecondRegSavedTo , SecondRegSaved , true ) ;


<s> Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ;

CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , & Args , <NUM_LIT> ) . setDiscardResult ( ) ;


<s> <ISA_LIT>CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) , MF . getFunction ( ) . getFunctionType ( ) -> getNumParams ( ) ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool ByVal = Flags . isByVal ( ) ; if ( VA . isRegLoc ( ) && ByVal && Flags . getByValSize ( ) <= <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ; bool InReg = VA . isRegLoc ( ) && ( ! ByVal || ( ByVal && Flags . getByValSize ( ) > <NUM_LIT> ) ) ; if ( InReg ) { MVT RegVT = VA . getLocVT ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) RegVT = VA . getValVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; Register VReg = MRI . createVirtualRegister ( RC ) ; SDValue Copy = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getValVT ( ) == <STR_LIT> ) { assert ( RegVT . getSizeInBits ( ) <= <NUM_LIT> ) ; SDValue T = DAG . getNode ( <STR_LIT> , dl , RegVT , Copy , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) ) ; Copy = DAG . getSetCC ( dl , <STR_LIT> , T , DAG . getConstant ( <NUM_LIT> , dl , RegVT ) , <STR_LIT> ) ; } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ;

int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ;


<s> Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else if ( RC == & <STR_LIT> ) { Ret = ( <NUM_LIT> << <NUM_LIT> ) ; } else { report_fatal_error ( <STR_LIT> ) ; } Ret |= ( RegNum & <NUM_LIT> ) ; return Ret ; } else { return Reg & <NUM_LIT> ; }


<s> rtx addr = XEXP ( m_tramp , <NUM_LIT> ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , <NUM_LIT> ) ) , plus_constant ( SImode , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , <NUM_LIT> , NULL_RTX , <NUM_LIT> ) , <NUM_LIT> ) ) ;

emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , <NUM_LIT> ) ) , plus_constant ( SImode , expand_and ( SImode , fnaddr , GEN_INT ( <NUM_LIT> ) , NULL_RTX ) , <NUM_LIT> ) ) ;


<s> return OpType >= <STR_LIT> && OpType <= <STR_LIT> ;


<s> if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ;


<s> <ISA_LIT>V8TargetMachine :: <ISA_LIT>V8TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> if ( ! Offset || ! Offset -> isNullValue ( ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: max ( SignBits , Op0SignBits ) ; } case <STR_LIT> : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; return Width ? <NUM_LIT> - ( Width -> getZExtValue ( ) & <NUM_LIT> ) : <NUM_LIT> ; } default :


<s> UCB_FORCED_STOP_ARG ( ucbp ) = ( _uw ) stop_arg ; entry_vrs -> core . r [ R_PC ] = entry_vrs -> core . r [ R_LR ] ;

return unwind_phase2_forced ( ucbp , entry_vrs , <NUM_LIT> ) ;


<s> if ( N0 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI , AllOnes ) ) return Result ;

if ( N1 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI , AllOnes ) ) return Result ;


<s> <ISA_LIT>GNULDBackend & ld_backend = pParent . getTarget ( ) ; Relocation & rel_entry = * ld_backend . getRelDyn ( ) . create ( ) ; rel_entry . setType ( pType ) ; rel_entry . targetRef ( ) = pReloc . targetRef ( ) ; if ( pType == llvm :: ELF :: R_<ISA_LIT>_RELATIVE ) rel_entry . setSymInfo ( NULL ) ; else rel_entry . setSymInfo ( rsym ) ;


<s> if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier && Parser . getTok ( ) . getString ( ) == Id ) { Parser . Lex ( ) ; return true ; }


<s> unsigned SrcIdx = M / Size ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { KnownUndef . setBit ( i ) ; continue ; } if ( V . getOpcode ( ) == <STR_LIT> && ( Size % V . getValueType ( ) . getVectorNumElements ( ) ) == <NUM_LIT> ) { int Scale = Size / V . getValueType ( ) . getVectorNumElements ( ) ; int Idx = M / Scale ; if ( Idx != <NUM_LIT> && ! VT . isFloatingPoint ( ) ) KnownUndef . setBit ( i ) ; else if ( Idx == <NUM_LIT> && <STR_LIT> ( V . getOperand ( <NUM_LIT> ) ) ) KnownZero . setBit ( i ) ; continue ; } if ( V . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = V . getOperand ( <NUM_LIT> ) ; int NumVecElts = Vec . getValueType ( ) . getVectorNumElements ( ) ; if ( Vec . isUndef ( ) && Size == NumVecElts ) { int Idx = V . getConstantOperandVal ( <NUM_LIT> ) ; int NumSubElts = V . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) ; if ( M < Idx || ( Idx + NumSubElts ) <= M ) KnownUndef . setBit ( i ) ; } continue ; } if ( IsSrcConstant [ SrcIdx ] ) { if ( UndefSrcElts [ SrcIdx ] [ M ] ) KnownUndef . setBit ( i ) ; else if ( SrcEltBits [ SrcIdx ] [ M ] == <NUM_LIT> ) KnownZero . setBit ( i ) ; }


<s> case ImmTyDppCtrl : OS << <STR_LIT> ; break ; case ImmTyDppRowMask : OS << <STR_LIT> ; break ; case ImmTyDppBankMask : OS << <STR_LIT> ; break ; case ImmTyDppBoundCtrl : OS << <STR_LIT> ; break ; case ImmTySdwaDstSel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc0Sel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc1Sel : OS << <STR_LIT> ; break ; case ImmTySdwaDstUnused : OS << <STR_LIT> ; break ; case ImmTyDMask : OS << <STR_LIT> ; break ; case ImmTyUNorm : OS << <STR_LIT> ; break ; case ImmTyDA : OS << <STR_LIT> ; break ; case ImmTyR128 : OS << <STR_LIT> ; break ; case ImmTyLWE : OS << <STR_LIT> ; break ; case ImmTyOff : OS << <STR_LIT> ; break ; case ImmTyExpTgt : OS << <STR_LIT> ; break ;

case ImmTyExpCompr : OS << <STR_LIT> ; break ;


<s> if ( DAsm -> isVI ( ) ) { Offset = Imm & <NUM_LIT> ; } else { Offset = SignExtend64 < <NUM_LIT> > ( Imm ) ; } return addOperand ( Inst , MCOperand :: createImm ( Offset ) ) ;


<s> bool hasArchitectedFlatScratch ( ) const { return getFeatureBits ( ) [ <STR_LIT> ] ;


<s> return StringSwitch < AluCode > ( S ) . Case ( <STR_LIT> , ADD ) . Case ( <STR_LIT> , ADDC ) . Case ( <STR_LIT> , SUB ) . Case ( <STR_LIT> , SUBB ) . Case ( <STR_LIT> , AND ) . Case ( <STR_LIT> , OR ) . Case ( <STR_LIT> , XOR ) . Case ( <STR_LIT> , SHL ) . Case ( <STR_LIT> , SRL ) . Case ( <STR_LIT> , SRA ) . Default ( UNKNOWN ) ;


<s> if ( Elem [ i ] == Elem [ First ] || Elem [ i ] . getOpcode ( ) == <STR_LIT> ) continue ; IsSplat = false ; break ; } if ( IsSplat ) return DAG . getNode ( <STR_LIT> , dl , VecTy , Elem [ First ] ) ; } if ( AllConst ) { uint64_t Val = <NUM_LIT> ; unsigned W = ElemTy . getSizeInBits ( ) ; uint64_t Mask = ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Num ; ++ i ) Val = ( Val << W ) | ( Consts [ i ] -> getZExtValue ( ) & Mask ) ; SDValue V0 = DAG . getConstant ( Val , dl , <STR_LIT> ) ; return DAG . getBitcast ( VecTy , V0 ) ; } MVT HalfTy = <STR_LIT> ( ElemTy , Num / <NUM_LIT> ) ; SDValue L = ( ElemTy == <STR_LIT> ) ? Elem [ <NUM_LIT> ] : buildVector32 ( { Elem . data ( ) , Num / <NUM_LIT> } , dl , HalfTy , DAG ) ; SDValue H = ( ElemTy == <STR_LIT> ) ? Elem [ <NUM_LIT> ] : buildVector32 ( { Elem . data ( ) + Num / <NUM_LIT> , Num / <NUM_LIT> } , dl , HalfTy , DAG ) ; unsigned Id = <STR_LIT> ; SDNode * N = DAG . getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VecTy , { DAG . getTargetConstant ( Id , dl , <STR_LIT> ) , L , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , H , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ) ; return SDValue ( N , <NUM_LIT> ) ;


<s> static bool is<ISA_LIT>LogicalCmp ( SDValue Op ) { unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && Opc == <STR_LIT> ) return true ;


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , true , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> cr16_compute_frame ( ) ; if ( ( ( from ) == FRAME_POINTER_REGNUM ) && ( ( to ) == STACK_POINTER_REGNUM ) ) return ( ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : <NUM_LIT> ) ; else if ( ( ( from ) == ARG_POINTER_REGNUM ) && ( ( to ) == FRAME_POINTER_REGNUM ) ) return ( current_frame_info . reg_size + current_frame_info . var_size ) ;

else if ( ( ( from ) == ARG_POINTER_REGNUM ) && ( ( to ) == STACK_POINTER_REGNUM ) ) return ( current_frame_info . reg_size + current_frame_info . var_size + ( ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : <NUM_LIT> ) ) ;


<s> rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> ? d -> nelt : <NUM_LIT> ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) odd = <NUM_LIT> ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * <NUM_LIT> + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ;

case V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ;


<s> case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerANDOR ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; }


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override {


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'd' : case 'y' : case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; }


<s> bool doInitialization ( Module & M ) override {


<s> assert ( MemOpcodes && <STR_LIT> ) ; return MemOpcodes [ Form132 ] ;


<s> const DataLayout & DL = MF . getDataLayout ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const auto & TFI = static_cast < const <ISA_LIT>FrameLowering & > ( * MF . getSubtarget ( ) . getFrameLowering ( ) ) ; if ( TFI . isISR ( MF ) ) MIRBuilder . buildInstr ( <STR_LIT> ) ; SmallVector < ArgInfo > SplitArgs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ Idx ] , Arg . getType ( ) , Idx } ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL ) ; ++ Idx ; } <ISA_LIT>IncomingArgsHandler Handler ( MIRBuilder , MRI ) ; <ISA_LIT>ValueAssigner Assigner ( true , MRI , MF ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; if ( F . isVarArg ( ) ) { auto * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MF . getFrameInfo ( ) . CreateFixedObject ( <NUM_LIT> , Assigner . StackOffset , true ) ) ; } return true ;


<s> <ISA_LIT>BSel ( ) : MachineFunctionPass ( ID ) {


<s> OccupedSlotsMask = <NUM_LIT> ; InstructionsGroupCandidate . clear ( ) ; LoadAlu ( ) ;


<s> void InstrumentMemOperandEpilogue ( const RegisterContext & RegCtx , MCContext & Ctx , MCStreamer & Out ) override { unsigned LocalFrameReg = RegCtx . ChooseFrameReg ( <NUM_LIT> ) ; assert ( LocalFrameReg != <STR_LIT> ) ; RestoreFlags ( Out ) ;

if ( RegCtx . ScratchReg ( <NUM_LIT> ) != <STR_LIT> ) RestoreReg ( Out , RegCtx . ScratchReg ( <NUM_LIT> ) ) ;


<s> static DecodeStatus DecodeDataRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> const Triple & TT = STI . getTargetTriple ( ) ;

uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;


<s> unsigned SrcReg = getRegForValue ( Src ) ; if ( ! SrcReg ) return false ; EVT SrcEVT = TLI . getValueType ( SrcTy , true ) ; EVT DestEVT = TLI . getValueType ( DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; unsigned ResultReg = <NUM_LIT> ; bool IsZExt = isa < ZExtInst > ( I ) ; if ( const auto * Arg = dyn_cast < Argument > ( Src ) ) { if ( ( IsZExt && Arg -> hasZExtAttr ( ) ) || ( ! IsZExt && Arg -> hasSExtAttr ( ) ) ) { if ( DestVT == <STR_LIT> ) { ResultReg = createResultReg ( TLI . getRegClassFor ( DestVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; } else ResultReg = SrcReg ; } } if ( ! ResultReg ) ResultReg = emitIntExt ( SrcVT , SrcReg , DestVT , IsZExt ) ; if ( ! ResultReg ) return false ;


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> } for ( unsigned i = <NUM_LIT> , e = OrigChain . getNumOperands ( ) ; i != e ; ++ i ) Ops . push_back ( OrigChain . getOperand ( i ) ) ; CurDAG -> UpdateNodeOperands ( OrigChain . getNode ( ) , Ops ) ; CurDAG -> UpdateNodeOperands ( Load . getNode ( ) , Call . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) , Load . getOperand ( <NUM_LIT> ) ) ; unsigned NumOps = Call . getNode ( ) -> getNumOperands ( ) ; Ops . clear ( ) ;

Ops . push_back ( SDValue ( Load . getNode ( ) , <NUM_LIT> ) ) ;


<s> BuildMI ( * MBB , MBB -> begin ( ) , MI . getDebugLoc ( ) , TII -> get ( IsWave32 ? <STR_LIT> : <STR_LIT> ) , Exec ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( LIS ) LIS -> RemoveMachineInstrFromMaps ( MI ) ; MI . eraseFromParent ( ) ; return ; } Register InputReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * FirstMI = & * MBB -> begin ( ) ; if ( InputReg . isVirtual ( ) ) { MachineInstr * DefInstr = MRI -> getVRegDef ( InputReg ) ; assert ( DefInstr && DefInstr -> isCopy ( ) ) ; if ( DefInstr -> getParent ( ) == MBB ) { if ( DefInstr != FirstMI ) { DefInstr -> removeFromParent ( ) ; MBB -> insert ( FirstMI , DefInstr ) ; if ( LIS ) LIS -> handleMove ( * DefInstr ) ; } else { FirstMI = & * std :: next ( FirstMI -> getIterator ( ) ) ; } } } const DebugLoc DL = MI . getDebugLoc ( ) ; const unsigned WavefrontSize = ST . getWavefrontSize ( ) ; const unsigned Mask = ( WavefrontSize << <NUM_LIT> ) - <NUM_LIT> ; Register CountReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto BfeMI = BuildMI ( * MBB , FirstMI , DL , TII -> get ( <STR_LIT> ) , CountReg ) . addReg ( InputReg ) . addImm ( ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) & Mask ) | <NUM_LIT> ) ; if ( LV ) LV -> recomputeForSingleDefVirtReg ( InputReg ) ; auto BfmMI = BuildMI ( * MBB , FirstMI , DL , TII -> get ( IsWave32 ? <STR_LIT> : <STR_LIT> ) , Exec ) . addReg ( CountReg ) . addImm ( <NUM_LIT> ) ; auto CmpMI = BuildMI ( * MBB , FirstMI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg , RegState :: Kill ) . addImm ( WavefrontSize ) ; if ( LV ) LV -> getVarInfo ( CountReg ) . Kills . push_back ( CmpMI ) ; auto CmovMI = BuildMI ( * MBB , FirstMI , DL , TII -> get ( IsWave32 ? <STR_LIT> : <STR_LIT> ) , Exec ) . addImm ( - <NUM_LIT> ) ; if ( ! LIS ) { MI . eraseFromParent ( ) ; return ; } LIS -> RemoveMachineInstrFromMaps ( MI ) ; MI . eraseFromParent ( ) ; LIS -> InsertMachineInstrInMaps ( * BfeMI ) ;

LIS -> InsertMachineInstrInMaps ( * BfmMI ) ;


<s> emitDotSize ( SymStart , CurrCodeEnd ) ; EmitFStart ( SymStart , CurrCodeEnd , FStartAlignment ) ; } ( ( MachineBasicBlock & ) MBB ) . setAlignment ( Align ( <NUM_LIT> ) ) ; AsmPrinter :: emitBasicBlockStart ( MBB ) ; ( ( MachineBasicBlock & ) MBB ) . setAlignment ( align ) ; emitBasicBlockBegin ( MBB ) ;


<s> DAG . getNode ( <STR_LIT> , DL , MemVT , NewLD ) , NewLD . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } if ( ! MemVT . isVector ( ) ) return SDValue ( ) ; assert ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned AS = Load -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , AS , Load -> getAlignment ( ) ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , DL ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) AS = MFI -> hasFlatScratchInit ( ) ? AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS : AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS ; unsigned NumElements = MemVT . getVectorNumElements ( ) ; if ( AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS || AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS_32BIT ) { if ( isMemOpUniform ( Load ) ) return SDValue ( ) ; } if ( AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS || AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS_32BIT || AS == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS ) { if ( Subtarget -> getScalarizeGlobalBehavior ( ) && isMemOpUniform ( Load ) && ! Load -> isVolatile ( ) && isMemOpHasNoClobberedMemOperand ( Load ) ) return SDValue ( ) ; } if ( AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS || AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS_32BIT || AS == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; } if ( AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorLoad ( Load , DAG ) ; case <NUM_LIT> :


<s> return PTrue1VTy -> getElementCount ( ) . getKnownMinValue ( ) < PTrue2VTy -> getElementCount ( ) . getKnownMinValue ( ) ; } ) ; PTrues . remove ( MostEncompassingPTrue ) ; PTrues . remove_if ( [ ] ( auto * PTrue ) { return isPTruePromoted ( PTrue ) ; } ) ; MostEncompassingPTrue -> moveBefore ( BB , BB . getFirstInsertionPt ( ) ) ; LLVMContext & Ctx = BB . getContext ( ) ; IRBuilder < > Builder ( Ctx ) ; Builder . SetInsertPoint ( & BB , ++ MostEncompassingPTrue -> getIterator ( ) ) ; auto * MostEncompassingPTrueVTy = cast < VectorType > ( MostEncompassingPTrue -> getType ( ) ) ; auto * ConvertToSVBool = Builder . CreateIntrinsic ( <STR_LIT> , { MostEncompassingPTrueVTy } , { MostEncompassingPTrue } ) ; bool ConvertFromCreated = false ; for ( auto * PTrue : PTrues ) { auto * PTrueVTy = cast < VectorType > ( PTrue -> getType ( ) ) ;

if ( MostEncompassingPTrueVTy != PTrueVTy ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ;

int Shift = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> if ( llvm :: ELF :: R_386_32 == pReloc . type ( ) && helper_use_relative_reloc ( * rsym , * this ) ) { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , llvm :: ELF :: R_<ISA_LIT>_64_RELATIVE , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; } else { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , pReloc . type ( ) , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; } getTarget ( ) . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } } return ; case llvm :: ELF :: R_<ISA_LIT>_64_GOTPCREL : if ( rsym -> reserved ( ) & ReserveGOT ) return ; if ( ! getTarget ( ) . symbolFinalValueIsKnown ( * rsym ) ) helper_GOT_init ( pReloc , true , * this ) ; else helper_GOT_init ( pReloc , false , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveGOT ) ; return ; case llvm :: ELF :: R_<ISA_LIT>_64_PLT32 : if ( rsym -> reserved ( ) & ReservePLT ) return ; if ( getTarget ( ) . symbolFinalValueIsKnown ( * rsym ) ) return ; if ( rsym -> isDefine ( ) && ! rsym -> isDyn ( ) && ! getTarget ( ) . isSymbolPreemptible ( * rsym ) ) { return ; } helper_PLT_init ( pReloc , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReservePLT ) ; return ; case llvm :: ELF :: R_<ISA_LIT>_64_PC32 : case llvm :: ELF :: R_<ISA_LIT>_64_PC16 : case llvm :: ELF :: R_<ISA_LIT>_64_PC8 :

if ( getTarget ( ) . symbolNeedsPLT ( * rsym ) && LinkerConfig :: DynObj != config ( ) . codeGenType ( ) ) {


<s> if ( TARGET_ALIGN_BY_32 ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const {


<s> RegNo = <NUM_LIT> ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( isRV32E ( ) , ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ;


<s> bool hasCaymanISA ( ) const { return CaymanISA ;


<s> if ( blk -> begin ( ) != blk -> end ( ) ) { blk -> insert ( blk -> begin ( ) , newInstr ) ; } else { blk -> push_back ( newInstr ) ;


<s> explicit MachineModulePass ( char & ID ) : ModulePass ( ID ) {


<s> MachineInstrBuilder <ISA_LIT>InstrInfo :: buildIndirectWrite ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const {

const DebugLoc & DL = MBB -> findDebugLoc ( I ) ;


<s> case TargetOpcode :: G_FPTOUI : case TargetOpcode :: G_FCMP : return true ;


<s> return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , Tmp ) . add ( * Idx ) . addImm ( Offset ) ; MachineInstr * SetOn = BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Tmp , RegState :: Kill ) . addImm ( IdxMode ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; } return true ; } if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( * Idx ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( * Idx ) . addImm ( Offset ) ; } return true ;


<s> while ( param_size -- ) { gcc_assert ( regi >= FIRST_ARG_REGNUM && regi <= LAST_ARG_REGNUM ) ; gcc_assert ( ! cum -> regs_used [ regi - FIRST_ARG_REGNUM ] ) ; cum -> regs_used [ regi - FIRST_ARG_REGNUM ] = true ; regi ++ ; }


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {

assert ( ! I -> getOperand ( <NUM_LIT> ) . getImm ( ) && ( hasFP ( MF ) || hasBP ( MF ) ) && <STR_LIT> ) ;


<s> SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = N0 . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( SVT . getVectorElementType ( ) == <STR_LIT> ) { if ( SVT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ) ; MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , IntegerVT , N0 ) ) ; } switch ( SVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MVT NVT = <STR_LIT> ( <STR_LIT> , SVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NVT , N0 ) ) ; } case <STR_LIT> : case <STR_LIT> : return lowerUINT_TO_FP_vXi32 ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget . hasAVX512 ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ) ; }


<s> Value = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Mask = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Value = <NUM_LIT> ; Mask = <NUM_LIT> ; return true ;


<s> assert ( Offset . getValueType ( ) . isScalableVector ( ) && <STR_LIT> ) ; SDValue Shift = DAG . getConstant ( Log2_32 ( BitWidth / <NUM_LIT> ) , DL , <STR_LIT> ) ; SDValue SplatShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset , SplatShift ) ;


<s> bool isDisp8 ( ) const { return getDispSize ( ) == <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo MFI = MF . getFrameInfo ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> ; MF . dump ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; if ( ! VA . isRegLoc ( ) ) continue ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


<s> TargetRegisterClass :: iterator i = <STR_LIT> -> allocation_order_begin ( * MF ) ; c = <STR_LIT> ; for ( j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { if ( ( * i ) == reg ) { c = <STR_LIT> ; break ; }


<s> bool <ISA_LIT>DAGToDAGISel :: tryIntCompareInGPR ( SDNode * N ) { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> && N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return false ; if ( TM . getOptLevel ( ) == CodeGenOpt :: None || ! TM . is<ISA_LIT>64 ( ) ) return false ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> :


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) ) return SDValue ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Value ; SDValue Overflow ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Value = DAG . getNode ( <STR_LIT> , dl , VTs , LHS , RHS ) ; Overflow = ConvertCarryFlagToBooleanCarry ( Value . getValue ( <NUM_LIT> ) , VT , DAG ) ; break ; case <STR_LIT> : Value = DAG . getNode ( <STR_LIT> , dl , VTs , LHS , RHS ) ; Overflow = ConvertCarryFlagToBooleanCarry ( Value . getValue ( <NUM_LIT> ) , VT , DAG ) ; Overflow = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , Overflow ) ; break ; }

return DAG . getNode ( <STR_LIT> , dl , VTs , Value , Overflow ) ;


<s> const MCInstrDesc & UseMCID = get ( UseNode -> getMachineOpcode ( ) ) ; const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } } if ( DefAlign < <NUM_LIT> && Subtarget . isCortexA9 ( ) ) switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || ! ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) || ! MEM_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; if ( ! REG_P ( base_reg ) ) return false ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( MEM_P ( tocrel_expr ) ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false , & tocrel_base , NULL ) ) return false ; split_const ( XVECEXP ( tocrel_base , <NUM_LIT> , <NUM_LIT> ) , & base , & offset ) ; if ( ! SYMBOL_REF_P ( base ) || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; else { rtx const_vector = get_pool_constant ( base ) ;


<s> if ( ( ( I + <NUM_LIT> ) >= EndIdx ) || ( ( NumGradients / <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> && ( I == DimIdx + ( NumGradients / <NUM_LIT> ) - <NUM_LIT> || I == DimIdx + NumGradients - <NUM_LIT> ) ) || ! MI . getOperand ( I + <NUM_LIT> ) . isReg ( ) ) { PackedAddrs . push_back ( B . buildBuildVector ( V2S16 , { AddrReg , B . buildUndef ( S16 ) . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> MCFragment * findAssociatedFragment ( ) const override {

return getSubExpr ( ) -> findAssociatedFragment ( ) ;


initialize<ISA_LIT>AAWrapperPassPass ( * PR ) ;


<s> return true ; } else if ( ResTy == MatchOperand_ParseFail ) llvm_unreachable ( <STR_LIT> ) ; return false ; } } else if ( Expr -> getKind ( ) == MCExpr :: Constant ) { Parser . Lex ( ) ; const MCConstantExpr * Const = static_cast < const MCConstantExpr * > ( Expr ) ; Operands . push_back ( <STR_LIT> ( Const , S , Parser . getTok ( ) . getLoc ( ) , * this ) ) ; return true ;


<s> DecodeStatus S = MCDisassembler :: Success ; if ( RegNo == <NUM_LIT> ) { Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> addPass ( create<ISA_LIT>AAWrapperPass ( ) ) ; addPass ( createExternalAAWrapperPass ( [ ] ( Pass & P , Function & , AAResults & AAR ) { if ( auto * WrapperPass = P . getAnalysisIfAvailable < <ISA_LIT>AAWrapperPass > ( ) ) AAR . addAAResult ( WrapperPass -> getResult ( ) ) ; } ) ) ; } if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) { addPass ( create<ISA_LIT>CodeGenPreparePass ( ) ) ; } } TargetPassConfig :: addIRPasses ( ) ; if ( isPassEnabled ( EnableScalarIRPasses ) ) addEarlyCSEOrGVNPass ( ) ;


<s> static rtx rs6000_darwin64_record_arg ( CUMULATIVE_ARGS * orig_cum , tree type , int named , bool retval ) { rtx rvec [ FIRST_PSEUDO_REGISTER ] ; int k = <NUM_LIT> , kbase = <NUM_LIT> ; HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; CUMULATIVE_ARGS copy_cum = * orig_cum ; CUMULATIVE_ARGS * cum = & copy_cum ; if ( ! retval && TYPE_ALIGN ( type ) >= <NUM_LIT> * BITS_PER_WORD && ( cum -> words % <NUM_LIT> ) != <NUM_LIT> ) cum -> words ++ ; cum -> intoffset = <NUM_LIT> ; cum -> use_stack = <NUM_LIT> ; cum -> named = named ; rs6000_darwin64_record_arg_recurse ( cum , type , <NUM_LIT> , rvec , & k ) ; rs6000_darwin64_record_arg_flush ( cum , typesize * BITS_PER_UNIT , rvec , & k ) ; if ( cum -> use_stack ) { if ( retval ) return NULL_RTX ; kbase = <NUM_LIT> ; rvec [ <NUM_LIT> ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; }

if ( k > <NUM_LIT> || cum -> use_stack ) return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( k - kbase , & rvec [ kbase ] ) ) ;


<s> } if ( dump_file ) { fprintf ( dump_file , <STR_LIT> ) ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) if ( m_vector_manager -> vector_block_infos [ bb -> index ( ) ] . reaching_out . dirty_p ( ) ) fprintf ( dump_file , <STR_LIT> , bb -> index ( ) ) ; fprintf ( dump_file , <STR_LIT> ) ; }


<s> const <ISA_LIT>RegisterInfo * RegInfo = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ;

if ( RegInfo -> hasBasePointer ( MF ) ) FrameReg = RegInfo -> getBaseRegister ( ) ;


<s> static SDValue lowerVECTOR_SHUFFLE_VSHF ( SDValue Op , EVT ResTy , SmallVector < int , <NUM_LIT> > Indices , SelectionDAG & DAG ) { SmallVector < SDValue , <NUM_LIT> > Ops ; SDValue Op0 ; SDValue Op1 ; EVT MaskVecTy = ResTy . changeVectorElementTypeToInteger ( ) ; EVT MaskEltTy = MaskVecTy . getVectorElementType ( ) ; bool Using1stVec = false ; bool Using2ndVec = false ; SDLoc DL ( Op ) ; int ResTyNumElts = ResTy . getVectorNumElements ( ) ; for ( int i = <NUM_LIT> ; i < ResTyNumElts ; ++ i ) { int Idx = Indices [ i ] ; if ( <NUM_LIT> <= Idx && Idx < ResTyNumElts ) Using1stVec = true ; if ( ResTyNumElts <= Idx && Idx < ResTyNumElts * <NUM_LIT> ) Using2ndVec = true ; } for ( SmallVector < int , <NUM_LIT> > :: iterator I = Indices . begin ( ) ; I != Indices . end ( ) ; ++ I ) Ops . push_back ( DAG . getTargetConstant ( * I , DL , MaskEltTy ) ) ; SDValue MaskVec = DAG . getBuildVector ( MaskVecTy , DL , Ops ) ; if ( Using1stVec && Using2ndVec ) { Op0 = Op -> getOperand ( <NUM_LIT> ) ; Op1 = Op -> getOperand ( <NUM_LIT> ) ; } else if ( Using1stVec ) Op0 = Op1 = Op -> getOperand ( <NUM_LIT> ) ; else if ( Using2ndVec ) Op0 = Op1 = Op -> getOperand ( <NUM_LIT> ) ;


<s> assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ;


<s> return decodeRegisterClass ( Inst , RegNo , ACCRegs ) ;


<s> Align NeedAlign = HRI . getSpillAlign ( <STR_LIT> ) ; Align HasAlign = MFI . getObjectAlign ( FI ) ; unsigned LoadOpc ; auto UseAligned = [ & ] ( Align NeedAlign , Align HasAlign ) { return ! NeedsAligna && ( NeedAlign <= HasAlign ) ; } ; LoadOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstLo ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; LoadOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> : <STR_LIT> ;

BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstHi ) . addFrameIndex ( FI ) . addImm ( Size ) . cloneMemRefs ( * MI ) ;


<s> return new AMDGPUCFGPrepare ( tm ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blcfill_u32 ( unsigned int __X ) { return __X & ( __X + <NUM_LIT> ) ;


<s> O << formatDec ( SignExtend32 < <NUM_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ) ; } else { O << formatDec ( SignExtend32 < <NUM_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ) ; } }


<s> static unsigned char riscv_class_max_nregs ( reg_class_t rclass , machine_mode mode ) {

if ( reg_class_subset_p ( rclass , FP_REGS ) ) return riscv_hard_regno_nregs ( FP_REG_FIRST , mode ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getManipulatesSP ( ) ) ;


<s> StringRef FS = getFeatureString ( F ) ; SmallString < <NUM_LIT> > SubtargetKey ( GPU ) ; SubtargetKey . append ( FS ) ; auto & I = SubtargetMap [ SubtargetKey ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , GPU , FS , * this ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * I -> getTargetLowering ( ) ) ) ;


<s> TmpInst . setOpcode ( Opcode ) ; TmpInst . addOperand ( MCOperand :: createReg ( Reg0 ) ) ;


<s> assert ( Sym -> isTag ( ) ) ; OS << <STR_LIT> << Sym -> getName ( ) << <STR_LIT> ; OS << <STR_LIT> ( Sym -> getSignature ( ) -> Params ) ; OS << <STR_LIT> ;


<s> Ops . clear ( ) ; OpBegins . clear ( ) ; OpBegins . push_back ( <NUM_LIT> ) ; HasPersonality = false ;


<s> if ( ! VT . isVector ( ) ) return SDValue ( ) ; assert ( ST -> hasNEON ( ) && <STR_LIT> ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT ShiftVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ;

SDValue NegatedCount = DAG . getNode ( <STR_LIT> , dl , ShiftVT , getZeroVector ( ShiftVT , DAG , dl ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


<s> unsigned MaxNumVGPRs = alignDown ( getTotalNumVGPRs ( Features ) / WavesPerEU , getVGPRAllocGranule ( Features ) ) ;

unsigned AddressableNumVGPRs = getAddressableNumVGPRs ( Features ) ;


<s> GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; if ( Subtarget -> isTargetDarwin ( ) ) return LowerGlobalTLSAddressDarwin ( Op , DAG ) ; if ( Subtarget -> isTargetWindows ( ) ) return LowerGlobalTLSAddressWindows ( Op , DAG ) ; assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GA -> getGlobal ( ) ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel ( GA , DAG ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec :

return LowerToTLSExecModels ( GA , DAG , model ) ;


<s> const auto * GVar = dyn_cast < GlobalVariable > ( GO ) ; if ( GVar && GVar -> isConstant ( ) && GVar -> getInitializer ( ) -> needsRelocation ( ) ) Kind = SectionKind :: getReadOnlyWithRel ( ) ;


<s> } if ( PointerType * Ty = dyn_cast < PointerType > ( V -> getType ( ) ) ) if ( Ty -> getAddressSpace ( ) > <NUM_LIT> ) return false ; switch ( Opcode ) { default : break ; case Instruction :: BitCast : return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; case Instruction :: IntToPtr : if ( TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: Alloca : { const AllocaInst * A = cast < AllocaInst > ( V ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( A ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { AM . BaseType = <STR_LIT> ; AM . Base . FrameIndex = SI -> second ; return true ; } break ; } case Instruction :: Add : { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( U -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Disp = ( int32_t ) AM . Disp + ( uint64_t ) CI -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Disp ) ) {


<s> if ( MRI -> def_begin ( Reg ) == MRI -> def_end ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; } else if ( ! MRI -> hasOneDef ( Reg ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto DI = MRI -> def_begin ( Reg ) , DE = MRI -> def_end ( ) ; DI != DE ; ++ DI ) {

DEBUG ( DI -> getParent ( ) -> dump ( ) ) ;


<s> <ISA_LIT>BaseAsmLexer ( const Target & T , const MCAsmInfo & MAI ) : TargetAsmLexer ( T ) , AsmInfo ( MAI ) {


<s> return ( __m128i ) __builtin_ia32_cvtpd2qq128_mask ( ( __v2df ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) __U ) ;


<s> NewOpcode = isINC ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = isINC ? <STR_LIT> : <STR_LIT> ; break ; } MachineInstr * NewMI = BuildMI ( * MFI , I , MI . getDebugLoc ( ) , TII -> get ( NewOpcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) ) ; MFI -> erase ( I ) ; I = static_cast < MachineBasicBlock :: iterator > ( NewMI ) ; return true ;


<s> return CP_READ_MEMORY | CP_WRITE_CSR ;


<s> IdxN = emitIntExt ( IdxVT . getSimpleVT ( ) , IdxN , PtrVT , false ) ; } else if ( IdxVT . bitsGT ( PtrVT ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned RegNum ; StringRef Layout ; SMLoc RegEndLoc , LayoutLoc ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( ! IdentifyRegister ( RegNum , RegEndLoc , Layout , LayoutLoc ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , S , RegEndLoc ) ) ; if ( Layout . size ( ) != <NUM_LIT> ) { unsigned long long TmpLanes = <NUM_LIT> ; llvm :: getAsUnsignedInteger ( Layout . substr ( <NUM_LIT> ) , <NUM_LIT> , TmpLanes ) ; if ( TmpLanes != <NUM_LIT> ) { NumLanes = TmpLanes ; } else {


<s> if ( ListFrom == ListTo && ListFrom == <STR_LIT> ) return ( <NUM_LIT> << <NUM_LIT> ) ; else if ( ListFrom == ListTo && ListFrom == <STR_LIT> ) return ( <NUM_LIT> << <NUM_LIT> ) ; else if ( ListFrom == <STR_LIT> ) return ListTo - ListFrom + <NUM_LIT> ;

else if ( ListFrom == <STR_LIT> ) return ( ( ListTo - ListFrom + <NUM_LIT> ) << <NUM_LIT> ) ;


<s> if ( ! NumVGScaledBytes ) return MCCFIInstruction :: createOffset ( nullptr , DwarfReg , NumBytes ) ; std :: string CommentBuffer ; llvm :: raw_string_ostream Comment ( CommentBuffer ) ; Comment << printReg ( Reg , & TRI ) << <STR_LIT> ; SmallString < <NUM_LIT> > OffsetExpr ; appendVGScaledOffsetExpr ( OffsetExpr , NumBytes , NumVGScaledBytes , TRI . getDwarfRegNum ( <STR_LIT> , true ) , Comment ) ; SmallString < <NUM_LIT> > CfaExpr ; CfaExpr . push_back ( dwarf :: DW_CFA_expression ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) . isFixedLengthVector ( ) && <STR_LIT> ) ; EVT InVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Size = Op . getValueSizeInBits ( ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( InVT ) ) return SDValue ( ) ; if ( InVT . isScalableVector ( ) ) { if ( Idx == <NUM_LIT> && isPackedVectorType ( InVT , DAG ) ) return Op ; return SDValue ( ) ; } if ( Idx == <NUM_LIT> && InVT . getSizeInBits ( ) <= <NUM_LIT> ) return Op ;

if ( Size == <NUM_LIT> && Idx * InVT . getScalarSizeInBits ( ) == <NUM_LIT> && InVT . getSizeInBits ( ) == <NUM_LIT> ) return Op ;


<s> for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) ISRDataRegFI [ I ] = MF . getFrameInfo ( ) . CreateStackObject ( TRI . getSpillSize ( RC ) , TRI . getSpillAlign ( RC ) , false ) ;


<s> report_fatal_error ( <STR_LIT> + Twine ( ObjectVT . getEVTString ( ) ) ) ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( ArgRegs [ ArgRegIdx ] , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ;

for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) {


<s> const <ISA_LIT>RegisterInfo * TRI = TM . getRegisterInfo ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI -> getFrameRegister ( ) , VT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( ) ; bool IsTopNode = false ; while ( SUnit * SU = SchedImpl -> pickNode ( IsTopNode ) ) { if ( ! checkSchedLimit ( ) ) break ; scheduleMI ( SU , IsTopNode ) ; updateQueues ( SU , IsTopNode ) ; } assert ( CurrentTop == CurrentBottom && <STR_LIT> ) ; placeDebugValues ( ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( StringRef TT ) { Triple TheTriple ( TT ) ; if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; HasSingleParameterDotFile = false ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; SupportsDebugInformation = CompileForDebugging ; HasFunctionAlignment = false ;


<s> if ( index == <NUM_LIT> ) { if ( offset != <NUM_LIT> ) fprintf ( file , <STR_LIT> , offset ) ; fputs ( reg_names [ REGNO ( base ) ] , file ) ; } else if ( GET_CODE ( index ) == REG ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( base ) ] , reg_names [ REGNO ( index ) ] ) ; else if ( GET_CODE ( index ) == SYMBOL_REF ) { output_addr_const ( file , index ) ; fputc ( ',' , file ) ; fputs ( reg_names [ REGNO ( base ) ] , file ) ; } else fatal_insn ( <STR_LIT> , addr ) ; } else if ( GET_CODE ( base ) == LO_SUM ) { gcc_assert ( ! index && GET_CODE ( XEXP ( base , <NUM_LIT> ) ) == REG ) ; if ( small_data_operand ( XEXP ( base , <NUM_LIT> ) , VOIDmode ) ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; output_addr_const ( file , plus_constant ( XEXP ( base , <NUM_LIT> ) , offset ) ) ; fputs ( <STR_LIT> , file ) ; fputs ( reg_names [ REGNO ( XEXP ( base , <NUM_LIT> ) ) ] , file ) ;


<s> bool <ISA_LIT>AsmParser :: ParseIntelDotOperator ( const MCExpr * Disp , const MCExpr * & NewDisp ) { const AsmToken & Tok = Parser . getTok ( ) ; int64_t OrigDispVal , DotDispVal ; if ( const MCConstantExpr * OrigDisp = dyn_cast < MCConstantExpr > ( Disp ) ) OrigDispVal = OrigDisp -> getValue ( ) ; else return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; StringRef DotDispStr = Tok . getString ( ) ; if ( DotDispStr . startswith ( <STR_LIT> ) ) DotDispStr = DotDispStr . drop_front ( <NUM_LIT> ) ; if ( Tok . is ( AsmToken :: Real ) ) { APInt DotDisp ; DotDispStr . getAsInteger ( <NUM_LIT> , DotDisp ) ; DotDispVal = DotDisp . getZExtValue ( ) ; } else if ( isParsingInlineAsm ( ) && Tok . is ( AsmToken :: Identifier ) ) { unsigned DotDisp ; std :: pair < StringRef , StringRef > BaseMember = DotDispStr . split ( '.' ) ; if ( SemaCallback -> LookupInlineAsmField ( BaseMember . first , BaseMember . second , DotDisp ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; DotDispVal = DotDisp ;

} else return Error ( Tok . getLoc ( ) , <STR_LIT> ) ;


<s> case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : if ( Opd2Info != TTI :: OK_UniformValue && Opd2Info != TTI :: OK_UniformConstantValue ) Cost = VTy -> getNumElements ( ) * ( TargetTransformInfo :: TCC_Basic + getArithmeticInstrCost ( Opcode , VTy -> getElementType ( ) ) + TargetTransformInfo :: TCC_Basic ) ;


<s> <ISA_LIT>Relocator :: <ISA_LIT>Relocator ( const LinkerConfig & pConfig ) : Relocator ( pConfig ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> } } if ( ! returnEmitted ) { errs ( ) << <STR_LIT> << MF . getName ( ) . str ( ) << <STR_LIT> ; if ( noSuccessorFound ) { MachineBasicBlock :: iterator lastMI = noSuccessorBlock -> begin ( ) ; BuildMI ( * noSuccessorBlock , noSuccessorBlock -> end ( ) , ( * lastMI ) . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; } else {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const MCExpr * Disp = MCConstantExpr :: create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; EmitInstruction ( Out , Inst ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI8 ) . addReg ( ShadowRegI8 ) ) ; MCSymbol * DoneSym = Ctx . createTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( AddressRegI32 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( ScratchRegI32 ) . addImm ( <NUM_LIT> ) ) ; switch ( AccessSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; case <NUM_LIT> : { const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , ScratchRegI32 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; EmitLEA ( * Op , <NUM_LIT> , ScratchRegI32 , Out ) ; break ; } case <NUM_LIT> : EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( ScratchRegI32 ) . addImm ( <NUM_LIT> ) ) ; break ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI32 ) . addReg ( ShadowRegI8 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( ShadowRegI32 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitCallAsanReport ( AccessSize , IsWrite , Ctx , Out , RegCtx ) ;


<s> unsigned Imm = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( ! Is256 || Subtarget . hasAVX2 ( ) ) validDomains |= <NUM_LIT> ; } return validDomains ; } ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( <NUM_LIT> && ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) ) { push_reload ( XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) , & XEXP ( x , <NUM_LIT> ) , & XEXP ( x , <NUM_LIT> ) , POINTER_REGS , GET_MODE ( x ) , GET_MODE ( x ) , <NUM_LIT> , <NUM_LIT> , opnum , RELOAD_OTHER ) ; if ( avr_log . legitimize_reload_address ) avr_edump ( <STR_LIT> , POINTER_REGS , XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ; return x ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && <NUM_LIT> == reg_equiv_constant ( REGNO ( XEXP ( x , <NUM_LIT> ) ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> ) { bool fit = INTVAL ( XEXP ( x , <NUM_LIT> ) ) <= MAX_LD_OFFSET ( mode ) ; if ( fit ) { if ( reg_equiv_address ( REGNO ( XEXP ( x , <NUM_LIT> ) ) ) != <NUM_LIT> ) { int regno = REGNO ( XEXP ( x , <NUM_LIT> ) ) ; rtx mem = mk_memloc ( x , regno ) ; push_reload ( XEXP ( mem , <NUM_LIT> ) , NULL_RTX , & XEXP ( mem , <NUM_LIT> ) , NULL , POINTER_REGS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ( enum reload_type ) addr_type ) ; if ( avr_log . legitimize_reload_address ) avr_edump ( <STR_LIT> , POINTER_REGS , XEXP ( mem , <NUM_LIT> ) , NULL_RTX ) ; push_reload ( mem , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_POINTER_REGS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; if ( avr_log . legitimize_reload_address ) avr_edump ( <STR_LIT> , BASE_POINTER_REGS , mem , NULL_RTX ) ;


<s> void fixup_7_pcrel ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) {

adjustRelativeBranch ( Size , Fixup , Value , Ctx ) ;


<s> } if ( TrueMBB ) { dbgs ( ) << <STR_LIT> << TrueMBB -> getNumber ( ) << <STR_LIT> << TrueMBB -> size ( ) << <STR_LIT> << TrueMBB -> pred_size ( ) ; if ( Detail ) { dbgs ( ) << <STR_LIT> ; TrueMBB -> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; } } if ( FalseMBB ) { dbgs ( ) << <STR_LIT> << FalseMBB -> getNumber ( ) << <STR_LIT> << FalseMBB -> size ( ) << <STR_LIT> << FalseMBB -> pred_size ( ) ;


<s> if ( Subtarget -> hasFp256 ( ) && VT . is256BitVector ( ) && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ;

return EltsFromConsecutiveLoads ( VT , Elts , dl , DAG ) ;


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override {


<s> break ; } } if ( retval == <NUM_LIT> ) { report_fatal_error ( <STR_LIT> + Twine ( VT . getEVTString ( ) ) ) ; }


<s> switch ( TM . getTLSModel ( GV ) ) { case TLSModel :: GeneralDynamic : Modifier = <STR_LIT> ; break ; case TLSModel :: LocalDynamic : Modifier = <STR_LIT> ; break ; case TLSModel :: InitialExec : Modifier = <STR_LIT> ; break ; case TLSModel :: LocalExec : Modifier = <STR_LIT> ; break ; } } else if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) { Modifier = <STR_LIT> ; } } break ; case MachineOperand :: MO_BlockAddress :

Name = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> getName ( ) ;


<s> static int xtensa_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( from == to && from != BR_REGS && to != BR_REGS ) return <NUM_LIT> ; else if ( reg_class_subset_p ( from , AR_REGS ) && reg_class_subset_p ( to , AR_REGS ) ) return <NUM_LIT> ;

else if ( reg_class_subset_p ( from , AR_REGS ) && to == ACC_REG ) return <NUM_LIT> ;


<s> assert ( SrcMBB -> succ_size ( ) == <NUM_LIT> ) ; if ( SrcMBB -> pred_size ( ) > <NUM_LIT> ) {

SrcMBB = cloneBlockForPredecessor ( SrcMBB , PreMBB ) ;


<s> word_type i ; if ( b & <NUM_LIT> ) a >>= <NUM_LIT> ; if ( b & <NUM_LIT> ) a >>= <NUM_LIT> ;

for ( i = ( b & <NUM_LIT> ) ; i > <NUM_LIT> ; -- i ) a >>= <NUM_LIT> ;


<s> if ( Has<ISA_LIT>64 ) addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; else addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( Has<ISA_LIT>64 ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setTargetDAGCombine ( <STR_LIT> ) ; setTargetDAGCombine ( <STR_LIT> ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) {


<s> static void LookThroughSetCC ( SDValue & LHS , SDValue & RHS , <STR_LIT> CC , unsigned & <ISA_LIT>CC ) { if ( isNullConstant ( RHS ) && CC == <STR_LIT> && ( ( ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) || ( LHS . getOpcode ( ) == <STR_LIT> && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) && isOneConstant ( LHS . getOperand ( <NUM_LIT> ) ) && isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) ) { SDValue CMPCC = LHS . getOperand ( <NUM_LIT> ) ;

<ISA_LIT>CC = cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> bool <ISA_LIT>LibCalls :: fold_recip ( CallInst * CI , IRBuilder < > & B , const FuncInfo & FInfo ) { Value * opr0 = CI -> getArgOperand ( <NUM_LIT> ) ; if ( ConstantFP * CF = dyn_cast < ConstantFP > ( opr0 ) ) { Value * nval = B . CreateFDiv ( ConstantFP :: get ( CF -> getType ( ) , <NUM_LIT> ) , opr0 , <STR_LIT> ) ; DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << * nval << <STR_LIT> ) ; replaceCall ( nval ) ; return true ; } return false ;


<s> unsigned BPReg = HasBP ? ( unsigned ) RegInfo -> getBaseRegister ( MF ) : FPReg ; unsigned BP8Reg = HasBP ? ( unsigned ) <STR_LIT> : FPReg ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) for ( MachineBasicBlock :: iterator MBBI = BI -> end ( ) ; MBBI != BI -> begin ( ) ; ) { -- MBBI ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) continue ; switch ( MO . getReg ( ) ) { case <STR_LIT> : MO . setReg ( FPReg ) ; break ; case <STR_LIT> : MO . setReg ( FP8Reg ) ; break ; case <STR_LIT> : MO . setReg ( BPReg ) ; break ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ;


<s> MachineBasicBlock :: iterator MI = MBB . begin ( ) ; PrologueStubs = false ; MachineFunction & MF = * MBB . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; if ( useSpillFunction ( MF , CSI ) ) { PrologueStubs = true ; unsigned MaxReg = getMaxCalleeSavedReg ( CSI , HRI ) ; bool StkOvrFlowEnabled = EnableStackOVFSanitizer ; const char * SpillFun = getSpillFunctionFor ( MaxReg , SK_ToMem , StkOvrFlowEnabled ) ; auto & HTM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; bool IsPIC = HTM . isPositionIndependent ( ) ; bool LongCalls = HST . useLongCalls ( ) || EnableSaveRestoreLong ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned SpillOpc ; if ( StkOvrFlowEnabled ) { if ( LongCalls ) SpillOpc = IsPIC ? <STR_LIT> : <STR_LIT> ; else SpillOpc = IsPIC ? <STR_LIT> : <STR_LIT> ; } else { if ( LongCalls ) SpillOpc = IsPIC ? <STR_LIT> : <STR_LIT> ; else SpillOpc = IsPIC ? <STR_LIT> : <STR_LIT> ; } MachineInstr * SaveRegsCall = BuildMI ( MBB , MI , DL , HII . get ( SpillOpc ) ) . addExternalSymbol ( SpillFun ) ; addCalleeSaveRegistersAsImpOperand ( SaveRegsCall , CSI , false , true ) ; for ( unsigned I = <NUM_LIT> ; I < CSI . size ( ) ; ++ I ) MBB . addLiveIn ( CSI [ I ] . getReg ( ) ) ; return true ; }

for ( unsigned i = <NUM_LIT> , n = CSI . size ( ) ; i < n ; ++ i ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ;


<s> const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> void DecodeVPERM2X128Mask ( MVT VT , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) { if ( Imm & <NUM_LIT> ) return ; unsigned HalfSize = VT . getVectorNumElements ( ) / <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != <NUM_LIT> ; ++ l ) { unsigned HalfBegin = ( ( Imm >> ( l * <NUM_LIT> ) ) & <NUM_LIT> ) * HalfSize ;

for ( unsigned i = HalfBegin , e = HalfBegin + HalfSize ; i != e ; ++ i ) ShuffleMask . push_back ( i ) ;


return ( __m128d ) __builtin_ia32_cvtqq2pd128_mask ( ( __v2di ) __A , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> return isSImm < <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> else if ( SUnits [ su ] . getInstr ( ) -> isCompare ( ) && LastSequentialCall ) SUnits [ su ] . addPred ( SDep ( LastSequentialCall , SDep :: Barrier ) ) ; }


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFixedLengthVectorIntDivideToSVE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; bool Signed = Op . getOpcode ( ) == <STR_LIT> ; unsigned PredOpcode = Signed ? <STR_LIT> : <STR_LIT> ; bool Negated ; uint64_t SplatVal ; if ( Signed && isPow2Splat ( Op . getOperand ( <NUM_LIT> ) , SplatVal , Negated ) ) { EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; SDValue Op1 = convertToScalableVector ( DAG , ContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op2 = DAG . getTargetConstant ( Log2_64 ( SplatVal ) , dl , <STR_LIT> ) ; SDValue Pg = getPredicateForFixedLengthVector ( DAG , dl , VT ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , ContainerVT , Pg , Op1 , Op2 ) ; if ( Negated ) Res = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <NUM_LIT> , dl , VT ) , Res ) ; return convertFromScalableVector ( DAG , VT , Res ) ; } if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return LowerToPredicatedOp ( Op , DAG , PredOpcode , true ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; EVT HalfVT = VT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) ; EVT FixedWidenedVT = HalfVT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; EVT ScalableWidenedVT = getContainerForFixedLengthVector ( DAG , FixedWidenedVT ) ; EVT WidenedVT = VT . widenIntegerVectorElementType ( * DAG . getContext ( ) ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WidenedVT ) ) { unsigned ExtendOpcode = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( ExtendOpcode , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ;

SDValue Div = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0 , Op1 ) ;


<s> return ( <NUM_LIT> + memory_move_secondary_cost ( mode , rclass , in ) ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: get_crbitm_encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && ( MO . getReg ( ) >= <STR_LIT> && MO . getReg ( ) <= <STR_LIT> ) ) ;

return <NUM_LIT> >> <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ;


<s> const TargetRegisterClass * <ISA_LIT>BaseRegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return & <STR_LIT> ;


<s> if ( <STR_LIT> . contains ( Reg ) ) return true ;

assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ;


<s> if ( ! TEST_HARD_REG_BIT ( live_regs_mask , PR_REG ) ) { rtx rr = gen_rtx_REG ( SImode , PR_REG ) ; emit_insn ( GEN_MOV ( rr , ra ) ) ; emit_use ( rr ) ; return ; } int pr_offset = rounded_frame_size ( d ) ; emit_insn ( GEN_MOV ( tmp , GEN_INT ( pr_offset ) ) ) ;

if ( frame_pointer_needed ) emit_insn ( GEN_ADD3 ( tmp , tmp , hard_frame_pointer_rtx ) ) ;


<s> unsigned Mask2 = N11C -> getZExtValue ( ) ; if ( ( Mask & ( ~ Mask2 ) ) == <NUM_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } return SDValue ( ) ;


<s> static inline bool ignoreInstr ( MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) return true ; if ( MI -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) return true ;


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; switch ( Count % <NUM_LIT> ) { default : break ;

case <NUM_LIT> : OW -> Write8 ( <NUM_LIT> ) ; break ;


<s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; <ISA_LIT>VType :: printVType ( Imm , O ) ;


<s> tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; const char * str = c_getstr ( * args ) ; int quiet = fn_code == IA64_BUILTIN_NANQ ; REAL_VALUE_TYPE real ;

if ( str && real_nan ( & real , str , quiet , TYPE_MODE ( type ) ) ) return build_real ( type , real ) ;


<s> SDValue HiShift = DAG . getConstant ( EltSizeInBits , DL , Amt . getValueType ( ) ) ; Op0 = DAG . getAnyExtOrTrunc ( Op0 , DL , <STR_LIT> ) ; Op1 = DAG . getZExtOrTrunc ( Op1 , DL , <STR_LIT> ) ; Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , Mask ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , HiShift ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Op1 ) ; if ( IsFSHR ) { Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Amt ) ; } else { Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , Amt ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res , HiShift ) ; } return DAG . getZExtOrTrunc ( Res , DL , VT ) ; } if ( VT == <STR_LIT> || ExpandFunnel ) return SDValue ( ) ; if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ; unsigned FSHOp = ( IsFSHR ? <STR_LIT> : <STR_LIT> ) ;

return DAG . getNode ( FSHOp , DL , VT , Op0 , Op1 , Amt ) ;


<s> O << ( ( OpNo == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ;

printS13ImmDecOperand ( MI , OpNo , O ) ;


<s> const MCOperand MO = MI . getOperand ( OpIdx ) ; const MCOperand BranchMO = MI . getOperand ( <NUM_LIT> ) ; if ( MO . isExpr ( ) ) { assert ( BranchMO . isExpr ( ) ) ; const MCExpr * DiffExpr = MCBinaryExpr :: createSub ( MO . getExpr ( ) , BranchMO . getExpr ( ) , CTX ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( llvm :: MCFixup :: create ( <NUM_LIT> , DiffExpr , Kind , MI . getLoc ( ) ) ) ;


<s> assert ( ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVX64BOps ( ) ) || ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVX128BOps ( ) ) ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; MVT OpTy = Subtarget . useHVX64BOps ( ) ? <STR_LIT> : <STR_LIT> ; MVT ReTy = Subtarget . useHVX64BOps ( ) ? <STR_LIT> : <STR_LIT> ; SDValue B0 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec0 ) ; SDValue B1 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec1 ) ; SDValue VC = DAG . getNode ( <STR_LIT> , dl , ReTy , B1 , B0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , VC ) ; } } if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue C32 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue W = DAG . getConstant ( Width , dl , <STR_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , W , C32 ) ; SDValue V = C0 ; for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { unsigned N = NElts - i - <NUM_LIT> ; SDValue OpN = Op . getOperand ( N ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && OpN . getValueSizeInBits ( ) == <NUM_LIT> ) { SDValue C = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; OpN = DAG . getNode ( <STR_LIT> , dl , VT , C , OpN ) ; } SDValue Idx = DAG . getConstant ( N , dl , <STR_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Idx , W ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , S , Offset ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { V , OpN , Or } ) ; else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { V , OpN , Or } ) ; else return SDValue ( ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , V ) ;


<s> return ( vector signed char ) __builtin_altivec_vavgsb ( ( vector signed char ) a1 , ( vector signed char ) a2 ) ;