<s> SDValue <ISA_LIT>TargetLowering :: LowerVACOPY ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget . isEnvironmentMusl ( ) && <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DestPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ;

const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {


<s> Align Alignment ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; const Align PtrAlign = Align ( PtrSize ) ; auto List = MIRBuilder . buildLoad ( PtrTy , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrAlign ) ) ; MachineInstrBuilder DstPtr ; if ( Alignment > PtrAlign ) {

auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Alignment . value ( ) - <NUM_LIT> ) ;


<s> NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( reg ) ) { O << 'v' ;


<s> SDValue BasePtr = MemSD -> getBasePtr ( ) ; SDValue Val , Mask , VL ; if ( const auto * VPStore = dyn_cast < VPStoreSDNode > ( Op ) ) { Val = VPStore -> getValue ( ) ; Mask = VPStore -> getMask ( ) ; VL = VPStore -> getVectorLength ( ) ; } else { const auto * MStore = cast < MaskedStoreSDNode > ( Op ) ; Val = MStore -> getValue ( ) ; Mask = MStore -> getMask ( ) ; } MVT VT = Val . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ;


<s> void ms8 ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) {

Value = ( Value & <NUM_LIT> ) >> <NUM_LIT> ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) { MF . setAlignment ( <NUM_LIT> ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( ) , RI ( STI . getTargetTriple ( ) ) {


<s> unsigned LiteralPair0 = Literals [ i ] ; unsigned LiteralPair1 = ( i + <NUM_LIT> < e ) ? Literals [ i + <NUM_LIT> ] : <NUM_LIT> ;

InsertPos = BuildMI ( MBB , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( LiteralPair0 ) . addImm ( LiteralPair1 ) ;


<s> static inline void __ev_clr_spefscr_field ( int mask ) { int i ;


<s> break ; } SDValue Test ( DAG . getMachineNode ( Opc , DL , <STR_LIT> , Arg ) , <NUM_LIT> ) ; SDValue FNSTSW = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Test ) , <NUM_LIT> ) ; SDValue Extract = DAG . getTargetExtractSubreg ( <STR_LIT> , DL , <STR_LIT> , FNSTSW ) ; Extract = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Extract , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;

return DAG . getSetCC ( DL , ResultVT , Extract , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , <STR_LIT> :: SETLE ) ;


<s> if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return false ; break ; case V4HImode : case V2SImode : case V1DImode : case V2SFmode : if ( TARGET_PAIRED_FLOAT ) return false ; break ; case SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; }


<s> bool ix86_agi_dependent ( rtx_insn * set_insn , rtx_insn * use_insn ) { int i ; extract_insn_cached ( use_insn ) ; for ( i = recog_data . n_operands - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( MEM_P ( recog_data . operand [ i ] ) ) { rtx addr = XEXP ( recog_data . operand [ i ] , <NUM_LIT> ) ; return modified_in_p ( addr , set_insn ) != <NUM_LIT> ; } return false ;


<s> const TargetRegisterClass & RC = * MRI -> getRegClass ( VirtReg ) ; TII -> storeRegToStackSlot ( * MBB , Before , VirtReg , Kill , FI , & RC , TRI ) ;


<s> ind = XEXP ( op , <NUM_LIT> ) ; if ( reload_completed && ( LABEL_REF_P ( ind ) || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , <NUM_LIT> ) ; if ( wb_level > <NUM_LIT> && ( GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC || ( wb_level > <NUM_LIT> && ( GET_CODE ( ind ) == PRE_INC || GET_CODE ( ind ) == POST_DEC ) ) ) ) return arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ; if ( wb_level > <NUM_LIT> && ( GET_CODE ( ind ) == POST_MODIFY || GET_CODE ( ind ) == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( ind , <NUM_LIT> ) ) ) ind = XEXP ( ind , <NUM_LIT> ) ; int factor = MIN ( GET_MODE_SIZE ( GET_MODE ( op ) ) , <NUM_LIT> ) ; if ( GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , <NUM_LIT> ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , <NUM_LIT> ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , <NUM_LIT> ) ) && IN_RANGE ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) , - <NUM_LIT> * factor , <NUM_LIT> * factor ) && ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) & ( factor - <NUM_LIT> ) ) == <NUM_LIT> ) return TRUE ; return FALSE ;


<s> if ( dbr_sequence_length ( ) == <NUM_LIT> ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) return <STR_LIT> ;


<s> bool sh_promote_prototypes ( tree type ) { if ( TARGET_HITACHI ) return <NUM_LIT> ; if ( ! type ) return <NUM_LIT> ; return ! sh_attr_renesas_p ( type ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * IsFast ) const { bool Allow = allowsMisalignedMemoryAccessesImpl ( VT . getSizeInBits ( ) , AddrSpace , Alignment , Flags , IsFast ) ;

if ( Allow && IsFast && Subtarget -> hasUnalignedDSAccessEnabled ( ) && ( AddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS || AddrSpace == <ISA_LIT>AS :: REGION_ADDRESS ) ) {


<s> static void mips_init_dfa_post_cycle_insn ( void ) { if ( TUNE_LOONGSON_2EF ) mips_ls2_init_dfa_post_cycle_insn ( ) ;


<s> assert ( Kind >= OpKind :: SwitchSet && <STR_LIT> ) ; SwitchSet = X ;


<s> bool Changed = false ; createStoreGroups ( MBB , SGs ) ; auto Less = [ ] ( const MachineInstr * A , const MachineInstr * B ) -> bool { return getStoreOffset ( A ) < getStoreOffset ( B ) ; } ; for ( auto & G : SGs ) { assert ( G . size ( ) > <NUM_LIT> && <STR_LIT> ) ; llvm :: sort ( G . begin ( ) , G . end ( ) , Less ) ; Changed |= processStoreGroup ( G ) ; }


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ;


<s> auto & TM = TPC . getTM < <ISA_LIT>TargetMachine > ( ) ; TM . resetSubtarget ( & MF ) ;


<s> static inline uint64_t decodeAdvSIMDModImmType2 ( uint8_t Imm ) {


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterInfo & TRI = * MRI . getTargetRegisterInfo ( ) ; const TargetRegisterClass & RC = * MRI . getRegClass ( DstReg ) ;

assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> case CODE_FOR_return : break ; } if ( seen_insn ) worklist . safe_push ( insn_bb_t ( insn , block ) ) ; else map -> get_or_insert ( block ) = insn ; seen_insn = true ;


<s> if ( In . Flags . isInConsecutiveRegsLast ( ) ) fail ( DL , DAG , <STR_LIT> ) ; InVals . push_back ( In . Used ? DAG . getNode ( <STR_LIT> , DL , In . VT , DAG . getTargetConstant ( InVals . size ( ) , DL , <STR_LIT> ) ) : DAG . getUNDEF ( In . VT ) ) ; MFI -> addParam ( In . VT ) ; } if ( IsVarArg ) { MVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; unsigned VarargVreg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( PtrVT ) ) ; MFI -> setVarargBufferVreg ( VarargVreg ) ;

Chain = DAG . getCopyToReg ( Chain , DL , VarargVreg , DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetConstant ( Ins . size ( ) , DL , <STR_LIT> ) ) ) ;


<s> if ( mips_split_p [ symbol_type ] ) { addr = gen_rtx_HIGH ( Pmode , mips_unspec_address ( addr , symbol_type ) ) ; addr = mips_force_temporary ( temp , addr ) ;

base = mips_force_temporary ( temp , gen_rtx_PLUS ( Pmode , addr , base ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Args ; for ( unsigned i = <NUM_LIT> , e = VecVT . getVectorNumElements ( ) ; i != e ; ++ i ) { Args . push_back ( DAG . getNode ( <STR_LIT> , DL , EltVT , Vector , DAG . getConstant ( i , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ) ; } return DAG . getNode ( <STR_LIT> , DL , VecVT , Args ) ;


<s> machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return false ; if ( code == GE || code == GT ) max_p = true ;

else if ( code == LE || code == LT ) max_p = false ;


<s> else if ( REG_P ( src ) && REGNO ( src ) == MD_REG_FIRST ) { mips_emit_move ( mips_subword ( dest , false ) , mips_subword ( src , false ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_mfhidi_ti ( mips_subword ( dest , true ) , src ) ) ; else emit_insn ( gen_mfhisi_di ( mips_subword ( dest , true ) , src ) ) ; } else { low_dest = mips_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { mips_emit_move ( mips_subword ( dest , true ) , mips_subword ( src , true ) ) ; mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; } else { mips_emit_move ( low_dest , mips_subword ( src , false ) ) ; mips_emit_move ( mips_subword ( dest , true ) , mips_subword ( src , true ) ) ;


<s> unsigned BN = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BitTracker :: RegisterRef RS = MI -> getOperand ( <NUM_LIT> ) ; unsigned F , W ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! BT . has ( RS . Reg ) || ! HBS :: getSubregMask ( RS , F , W , MRI ) ) return false ; MachineBasicBlock & B = * MI -> getParent ( ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; const BitTracker :: BitValue & V = SC [ F + BN ] ; if ( V . Type == BitTracker :: BitValue :: Ref && V . RefI . Reg != RS . Reg ) { const TargetRegisterClass * TC = MRI . getRegClass ( V . RefI . Reg ) ; unsigned P = std :: numeric_limits < unsigned > :: max ( ) ; BitTracker :: RegisterRef RR ( V . RefI . Reg , <NUM_LIT> ) ; if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; RR . Sub = <STR_LIT> ; if ( P >= <NUM_LIT> ) { P -= <NUM_LIT> ; RR . Sub = <STR_LIT> ; } } else if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; } if ( P != std :: numeric_limits < unsigned > :: max ( ) ) { unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( RR . Reg , <NUM_LIT> , RR . Sub ) . addImm ( P ) ;

HBS :: replaceReg ( RD . Reg , NewR , MRI ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < <ISA_LIT>ImageArgs . size ( ) ; i ++ ) { if ( <ISA_LIT>ImageArgs [ i ] == symStr ) { return i ; }


<s> unsigned NumEls = Op . getValueType ( ) . getVectorNumElements ( ) ; MVT ElemVT = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( SDValue ScalarV = getSplatValue ( Op . getNode ( ) ) ) { MVT LegalResVT = <STR_LIT> ( ElemVT , <NUM_LIT> ) ; auto AVL = DAG . getConstant ( NumEls , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , LegalResVT , Op . getOperand ( <NUM_LIT> ) , AVL ) ; }


<s> bool <ISA_LIT>Subtarget :: enableSubRegLiveness ( ) const { return EnableSubRegLiveness ;


<s> <ISA_LIT>OutgoingValueHandler ( MachineIRBuilder & B , MachineRegisterInfo & MRI , MachineInstrBuilder MIB , CCAssignFn * AssignFn ) : <ISA_LIT>ValueHandler ( false , B , MRI , AssignFn ) , MIB ( MIB ) {


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! <ISA_LIT>FI -> globalBaseRegSet ( ) ) return ; MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned V0 , V1 , V2 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC = ( const TargetRegisterClass * ) & <STR_LIT> ; V0 = RegInfo . createVirtualRegister ( RC ) ;

V1 = RegInfo . createVirtualRegister ( RC ) ;


<s> void push ( NodeAddr < DefNode * > DA ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( Reg == <NUM_LIT> ) continue ; MI -> getOperand ( OpNo + i ) . setReg ( get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ) ; }


<s> Chain = DAG . getCopyFromReg ( Chain , DL , Val . getLocReg ( ) , Val . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain ;


<s> const char * getPassName ( ) const override {


<s> if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ; if ( Bytes <= <NUM_LIT> ) return <NUM_LIT> ;


<s> MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( <STR_LIT> , true ) ) ; MBB . erase ( PrevMBBI ) ; return true ; } } if ( MBBI != MBB . end ( ) ) { MachineBasicBlock :: iterator NextMBBI = llvm :: next ( MBBI ) ; if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( Mode , true ) ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; return true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( Mode , true ) ) ; if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; return true ; } } } else { if ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) return false ; <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; unsigned Offset = <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PrevMBBI = prior ( MBBI ) ; if ( Mode == <STR_LIT> && isMatchingDecrement ( PrevMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { MI -> getOperand ( <NUM_LIT> ) . setImm ( <STR_LIT> ( <STR_LIT> , true , Offset ) ) ; MBB . erase ( PrevMBBI ) ; return true ; } }


Builder . buildInstr ( <STR_LIT> ) . addMBB ( & NewDestBB ) ;


<s> unsigned <ISA_LIT>AsmParser :: getReg ( int RC , int RegNo ) {

return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ;


<s> std :: vector < std :: string > alb_r6 ( Alb op , Imm16 a ) { return D ( op , a , <STR_LIT> ) ;


<s> AU . addPreserved < LiveIntervals > ( ) ; AU . addPreservedID ( LiveVariablesID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool llvm :: getMinCTASm ( const Function & F , unsigned & x ) {

return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MINNCTAPERSM ] , x ) ) ;


<s> if ( e > <NUM_LIT> ) { std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>elTarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterAsmStreamer ( The<ISA_LIT>Target , create<ISA_LIT>AsmStreamer ) ;

TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ;


<s> NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; STI = & NewSTI ; SetupMachineFunction ( MF ) ; emitFunctionBody ( ) ; return false ;


return ( unsigned short ) ( ( __v8hi ) __A ) [ __N & <NUM_LIT> ] ;


<s> addPass ( create<ISA_LIT>PrologEpilogPass ( ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) {

addPass ( create<ISA_LIT>Peephole ( ) ) ;


<s> bool invert = InvertFPCondCode ( ( <STR_LIT> ) cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ) ;

return DAG . getNode ( ( invert ? <STR_LIT> : <STR_LIT> ) , DL , True . getValueType ( ) , True , False , Cond ) ;


<s> bool detectRoundChange ( ) const { return DetectRoundChange ;


<s> AU . addRequired < LegacyDivergenceAnalysis > ( ) ; AU . addRequired < MemoryDependenceWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ;


<s> Invert = false ; return Opcode ; } CC = <STR_LIT> ( CC , Mode == CmpMode :: Int ) ; if ( unsigned Opcode = getVectorComparison ( CC , Mode ) ) {


<s> MCSymbol * Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Major , Ctx ) ) ; } else { MCSymbol * Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Major , Ctx ) ) ; Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Minor , Ctx ) ) ; Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( ISA . Stepping , Ctx ) ) ;


<s> return ( int32x4_t ) __builtin_aarch64_sqrdmulhv4si ( __a , __b ) ;


<s> <ISA_LIT>AsmBackend ( Triple :: OSType OSType ) : MCAsmBackend ( <STR_LIT> ) , OSType ( OSType ) {


<s> num_bytes = ( mode == BLKmode ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ;


<s> HOST_WIDE_INT size ; size = ( cfun -> machine -> local_vars_size + cfun -> machine -> callee_saved_reg_size ) ; if ( TARGET_XBPF ) { int regno ; int fp_offset = - cfun -> machine -> local_vars_size ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || ( cfun -> calls_alloca && regno == STACK_POINTER_REGNUM ) ) { rtx mem ; if ( ! IN_RANGE ( fp_offset , - <NUM_LIT> - <NUM_LIT> , <NUM_LIT> ) ) break ; else { mem = gen_frame_mem ( DImode , plus_constant ( DImode , hard_frame_pointer_rtx , fp_offset - <NUM_LIT> ) ) ; emit_move_insn ( mem , gen_rtx_REG ( DImode , regno ) ) ; fp_offset -= <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFixedLengthVectorMLoadToSVE ( SDValue Op , SelectionDAG & DAG ) const { auto Load = cast < MaskedLoadSDNode > ( Op ) ; if ( Load -> getExtensionType ( ) != <STR_LIT> :: NON_EXTLOAD ) return SDValue ( ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT ) ; SDValue Mask = convertFixedMaskToScalableVector ( Load -> getMask ( ) , DAG ) ; SDValue PassThru ; bool IsPassThruZeroOrUndef = false ; if ( Load -> getPassThru ( ) -> isUndef ( ) ) { PassThru = DAG . getUNDEF ( ContainerVT ) ; IsPassThruZeroOrUndef = true ; } else { if ( ContainerVT . isInteger ( ) ) PassThru = DAG . getConstant ( <NUM_LIT> , DL , ContainerVT ) ; else PassThru = DAG . getConstantFP ( <NUM_LIT> , DL , ContainerVT ) ; if ( isZerosVector ( Load -> getPassThru ( ) . getNode ( ) ) ) IsPassThruZeroOrUndef = true ; } auto NewLoad = DAG . getMaskedLoad ( ContainerVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getOffset ( ) , Mask , PassThru , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) , Load -> getAddressingMode ( ) , Load -> getExtensionType ( ) ) ; if ( ! IsPassThruZeroOrUndef ) { SDValue OldPassThru = convertToScalableVector ( DAG , ContainerVT , Load -> getPassThru ( ) ) ; NewLoad = DAG . getSelect ( DL , ContainerVT , Mask , NewLoad , OldPassThru ) ;


<s> if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Location . set ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; else { DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; }


<s> SDValue Val = isNEONModifiedImm ( SplatBits . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VmovVT , VT . is128BitVector ( ) , VMOVModImm ) ; if ( Val . getNode ( ) ) { SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ; } uint64_t NegatedImm = ( SplatBits . getZExtValue ( ) ^ ( ( <NUM_LIT> << SplatBitSize ) - <NUM_LIT> ) ) ; Val = isNEONModifiedImm ( NegatedImm , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VmovVT , VT . is128BitVector ( ) , VMVNModImm ) ; if ( Val . getNode ( ) ) { SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ; } } } unsigned NumElts = VT . getVectorNumElements ( ) ; bool isOnlyLowElement = true ; bool usesOnlyOneValue = true ; bool isConstant = true ; SDValue Value ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . getOpcode ( ) == <STR_LIT> ) continue ; if ( i > <NUM_LIT> ) isOnlyLowElement = false ; if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ;

if ( ! Value . getNode ( ) ) Value = V ;


<s> static const TargetAsmInfo * createTargetAsmInfo ( const Target & T , const StringRef & TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new <ISA_LIT>DarwinTargetAsmInfo ( TheTriple ) ; case Triple :: MinGW32 : case Triple :: MinGW64 : case Triple :: Cygwin : return new <ISA_LIT>COFFTargetAsmInfo ( TheTriple ) ; case Triple :: Win32 : return new <ISA_LIT>WinTargetAsmInfo ( TheTriple ) ; default :

return new <ISA_LIT>ELFTargetAsmInfo ( TheTriple ) ;


<s> Stream . EnterSubblock ( bitc :: METADATA_BLOCK_ID , <NUM_LIT> ) ; SmallVector < uint64_t , <NUM_LIT> > Record ; writeMetadataStrings ( VE . getMDStrings ( ) , Record ) ; writeMetadataRecords ( VE . getNonMDStrings ( ) , Record ) ; Stream . ExitBlock ( ) ;


<s> assert ( ! mustPreserveAnalysisID ( LiveIntervalsID ) && <STR_LIT> ) ; MRI . leaveSSA ( ) ; for ( unsigned i = <NUM_LIT> , e = MRI . getNumVirtRegs ( ) ; i < e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( MRI . use_nodbg_empty ( Reg ) ) continue ; if ( HasArgumentDef ( Reg , MRI ) ) continue ; BuildMI ( Entry , Entry . begin ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) , Reg ) ; Changed = true ; }

for ( auto MII = Entry . begin ( ) , MIE = Entry . end ( ) ; MII != MIE ; ) {


<s> if ( OpNo > <NUM_LIT> ) O << <STR_LIT> ; printRegOperand ( <STR_LIT> , O , MRI ) ;

if ( OpNo == <NUM_LIT> ) O << <STR_LIT> ;


<s> ExpandPseudo :: ExpandPseudo ( MachineFunction & MF_ ) : MF ( MF_ ) , TII ( * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ) , RegInfo ( TII . getRegisterInfo ( ) ) , MRI ( MF . getRegInfo ( ) ) {


<s> SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Inp = Op , Res ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_v : case InlineAsm :: Constraint_m : if ( SelectAddrFI ( Inp , Res ) ) OutOps . push_back ( Res ) ; else OutOps . push_back ( Inp ) ; break ; }

OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ) ;


<s> return <STR_LIT> ; case <STR_LIT> : assert ( SymA . isData ( ) ) ; return <STR_LIT> ; case FK_Data_4 : if ( SymA . isFunction ( ) ) return <STR_LIT> ; if ( SymA . isGlobal ( ) ) return <STR_LIT> ; if ( auto Section = static_cast < const MCSectionWasm * > ( getFixupSection ( Fixup . getValue ( ) ) ) ) { if ( Section -> getKind ( ) . isText ( ) ) return <STR_LIT> ; else if ( ! Section -> isWasmData ( ) ) return <STR_LIT> ; } return IsLocRel ? <STR_LIT> : <STR_LIT> ; case FK_Data_8 : if ( SymA . isFunction ( ) ) return <STR_LIT> ; if ( SymA . isGlobal ( ) ) llvm_unreachable ( <STR_LIT> ) ; if ( auto Section = static_cast < const MCSectionWasm * > ( getFixupSection ( Fixup . getValue ( ) ) ) ) { if ( Section -> getKind ( ) . isText ( ) ) return <STR_LIT> ; else if ( ! Section -> isWasmData ( ) ) llvm_unreachable ( <STR_LIT> ) ; } assert ( SymA . isData ( ) ) ; return <STR_LIT> ; default :


<s> } assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( VT != <STR_LIT> ) return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; unsigned CastOpc ; unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CastOpc = <STR_LIT> ; Opc = <STR_LIT> ; break ; case <STR_LIT> :


<s> Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI64Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; } } Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ;


<s> static <ISA_LIT>ABIInfo S32 ( ) { return <ISA_LIT>ABIInfo ( <STR_LIT> ) ;


<s> bool isCSRSystemRegister ( ) const { return isSystemRegister ( ) ;


<s> case CallingConv :: C : case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; case CallingConv :: <ISA_LIT>_INTR : if ( Ins . empty ( ) ) return Chain ; report_fatal_error ( <STR_LIT> ) ; }


<s> gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = <NUM_LIT> ; unsigned int actual_versions = <NUM_LIT> ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= <NUM_LIT> ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - <NUM_LIT> ) ) ; default_decl = ( * fndecls ) [ <NUM_LIT> ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( ix86_builtins [ ( int ) IX86_BUILTIN_CPU_INIT ] , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ;


<s> SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Stores ) ; if ( SN -> isIndexed ( ) ) { SDValue RetOps [ ] = { TF , Stores [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , dl ) ; } return TF ; } assert ( SN -> isUnindexed ( ) && <STR_LIT> ) ; assert ( Value . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value ) ; SDValue FPHalfs = DAG . getConstantFP ( <NUM_LIT> , dl , <STR_LIT> ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , FPHalfs , FPHalfs ) ; Value = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Value ) ; MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; int FrameIdx = FrameInfo -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FrameIdx ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FIdx = DAG . getFrameIndex ( FrameIdx , PtrVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( StoreChain ) ; Ops . push_back ( DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) ) ; Ops . push_back ( Value ) ; Ops . push_back ( FIdx ) ; SmallVector < EVT , <NUM_LIT> > ValueVTs ; ValueVTs . push_back ( <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( ValueVTs ) ; StoreChain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , Ops , <STR_LIT> , PtrInfo ) ; SmallVector < SDValue , <NUM_LIT> > Loads , LoadChains ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned Offset = <NUM_LIT> * i ; SDValue Idx = DAG . getConstant ( Offset , dl , FIdx . getValueType ( ) ) ; Idx = DAG . getNode ( <STR_LIT> , dl , FIdx . getValueType ( ) , FIdx , Idx ) ; Loads . push_back ( DAG . getLoad ( <STR_LIT> , dl , StoreChain , Idx , PtrInfo . getWithOffset ( Offset ) , false , false , false , <NUM_LIT> ) ) ; LoadChains . push_back ( Loads [ i ] . getValue ( <NUM_LIT> ) ) ; } StoreChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadChains ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Idx = DAG . getConstant ( i , dl , BasePtr . getValueType ( ) ) ; Idx = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , Idx ) ;

Stores . push_back ( DAG . getTruncStore ( StoreChain , dl , Loads [ i ] , Idx , SN -> getPointerInfo ( ) . getWithOffset ( i ) , <STR_LIT> , SN -> isNonTemporal ( ) , SN -> isVolatile ( ) , <NUM_LIT> , SN -> getAAInfo ( ) ) ) ;


<s> if ( JUMP_P ( insn ) && INSN_CODE ( insn ) == CODE_FOR_return ) return <STR_LIT> ; if ( NONDEBUG_INSN_P ( insn ) && INSN_CODE ( insn ) < <NUM_LIT> && ( GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT || asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> ) ) return <STR_LIT> ;


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , false , true , true ) ;


<s> if ( interrupt_handler ) { bool use_movml = false ; if ( TARGET_SH2A ) { unsigned int count = <NUM_LIT> ; for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) count ++ ; else break ; if ( count == LAST_BANKED_REG - FIRST_BANKED_REG + <NUM_LIT> ) use_movml = true ; } if ( sh_cfun_resbank_handler_p ( ) ) ; else if ( use_movml ) { rtx x , mem , reg , set ; rtx sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_blockage ( ) ) ; x = gen_movml_push_banked ( sp_reg ) ; x = emit_frame_insn ( x ) ; for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) { mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp_reg , i * <NUM_LIT> ) ) ; reg = gen_rtx_REG ( SImode , i ) ; add_reg_note ( x , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } set = gen_rtx_SET ( sp_reg , plus_constant ( Pmode , sp_reg , - <NUM_LIT> ) ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , set ) ; emit_insn ( gen_blockage ( ) ) ; }

else for ( int i = FIRST_BANKED_REG ; i <= LAST_BANKED_REG ; i ++ ) if ( TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ;


<s> if ( Function * F = dyn_cast < Function > ( Callee . getCallee ( ) ) ) R -> setCallingConv ( F -> getCallingConv ( ) ) ;


<s> bool aarch64_sve_dup_immediate_p ( rtx x ) { rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ;

if ( val & <NUM_LIT> ) return IN_RANGE ( val , - <NUM_LIT> , <NUM_LIT> ) ;


<s> static bool compare_diff_p ( rtx_insn * insn ) {

RTX_CODE cond = compare_condition ( insn ) ;


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } AssemblerOptions . back ( ) -> setReorder ( ) ; getTargetStreamer ( ) . emitDirectiveSetReorder ( ) ; Parser . Lex ( ) ; return false ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> bool hasPerfMon ( ) const { return HasPerfMon ;


<s> unsigned Opcode = N -> getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { EVT OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT . is256BitVector ( ) || OpVT . is128BitVector ( ) ) return Subtarget -> hasVLX ( ) ; return true ; }


<s> bool <ISA_LIT>InstrInfo :: verifyInstruction ( const MachineInstr * MI , StringRef & ErrInfo ) const { uint16_t Opcode = MI -> getOpcode ( ) ; int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opcode , AMDGPU :: OpName :: src0 ) ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opcode , AMDGPU :: OpName :: src1 ) ; int Src2Idx = AMDGPU :: getNamedOperandIdx ( Opcode , AMDGPU :: OpName :: src2 ) ; if ( isVOP1 ( Opcode ) || isVOP2 ( Opcode ) || isVOP3 ( Opcode ) || isVOPC ( Opcode ) ) { unsigned ConstantBusCount = <NUM_LIT> ; unsigned SGPRUsed = AMDGPU :: NoRegister ; for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isUse ( ) && ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) { if ( ! MO . isImplicit ( ) && MO . getReg ( ) == AMDGPU :: EXEC ) ++ ConstantBusCount ; if ( MO . getReg ( ) == AMDGPU :: M0 || MO . getReg ( ) == AMDGPU :: VCC || ( ! MO . isImplicit ( ) && ( AMDGPU :: SGPR_32RegClass . contains ( MO . getReg ( ) ) || AMDGPU :: SGPR_64RegClass . contains ( MO . getReg ( ) ) ) ) ) { if ( SGPRUsed != MO . getReg ( ) ) { ++ ConstantBusCount ; SGPRUsed = MO . getReg ( ) ; } } } if ( isLiteralConstant ( MO ) ) ++ ConstantBusCount ; } if ( ConstantBusCount > <NUM_LIT> ) { ErrInfo = <STR_LIT> ; return false ; } } if ( Src1Idx != - <NUM_LIT> && ( isVOP2 ( Opcode ) || isVOPC ( Opcode ) ) ) { const MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( Src1 . isImm ( ) ) { ErrInfo = <STR_LIT> ; return false ; } } if ( isVOP3 ( Opcode ) ) { if ( Src0Idx != - <NUM_LIT> && isLiteralConstant ( MI -> getOperand ( Src0Idx ) ) ) { ErrInfo = <STR_LIT> ; return false ; } if ( Src1Idx != - <NUM_LIT> && isLiteralConstant ( MI -> getOperand ( Src1Idx ) ) ) { ErrInfo = <STR_LIT> ; return false ; } if ( Src2Idx != - <NUM_LIT> && isLiteralConstant ( MI -> getOperand ( Src2Idx ) ) ) { ErrInfo = <STR_LIT> ; return false ; }


<s> <ISA_LIT>VLIWPacketizer ( ) : MachineFunctionPass ( ID ) {


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveFPLRX ( SMLoc L ) { int64_t Offset ; if ( parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveFPLRX ( Offset ) ;


<s> return GISel -> getRegBankInfo ( ) ;


<s> assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget -> hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = SrcVector == V1 && cast < ConstantSDNode > ( Current . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == i ; } if ( ! CanFold ) return SDValue ( ) ; assert ( V1 . getNode ( ) && <STR_LIT> ) ;

if ( V1 . getSimpleValueType ( ) != <STR_LIT> ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , <STR_LIT> , V1 ) ;


<s> case HImode : return ( INTVAL ( op ) % <NUM_LIT> ) == <NUM_LIT> && INTVAL ( op ) < <NUM_LIT> ; case SImode : case SFmode : return ( INTVAL ( op ) % <NUM_LIT> ) == <NUM_LIT> && INTVAL ( op ) < <NUM_LIT> ;


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { return new <ISA_LIT>FastISel ( FuncInfo , LibInfo ) ;


<s> CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ;

return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ;


<s> const MachineOperand & DispSpec = MI -> getOperand ( Op + <NUM_LIT> ) ; bool HasBaseReg = BaseReg . getReg ( ) != <NUM_LIT> ; if ( HasBaseReg && Modifier && ! strcmp ( Modifier , <STR_LIT> ) && BaseReg . getReg ( ) == <STR_LIT> ) HasBaseReg = false ; bool HasParenPart = IndexReg . getReg ( ) || HasBaseReg ; if ( DispSpec . isImm ( ) ) { int DispVal = DispSpec . getImm ( ) ; if ( DispVal || ! HasParenPart ) O << DispVal ; } else { assert ( DispSpec . isGlobal ( ) || DispSpec . isCPI ( ) || DispSpec . isJTI ( ) || DispSpec . isSymbol ( ) ) ; printSymbolOperand ( MI -> getOperand ( Op + <NUM_LIT> ) ) ; } if ( HasParenPart ) { assert ( IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; O << '(' ; if ( HasBaseReg ) printOperand ( MI , Op , Modifier ) ; if ( IndexReg . getReg ( ) ) { O << ',' ;

printOperand ( MI , Op + <NUM_LIT> , Modifier ) ;


<s> MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , false ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , TmpReg , true ) ) llvm_unreachable ( <STR_LIT> ) ; ArgVT = DestVT ; Arg = TmpReg ; break ; } case CCValAssign :: BCvt : { llvm_unreachable ( <STR_LIT> ) ; break ; } } unsigned ArgReg ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) { ArgReg = NextFPR ++ ; if ( CC != CallingConv :: Fast ) ++ NextGPR ; } else ArgReg = NextGPR ++ ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ArgReg ) . addReg ( Arg ) ;


<s> if ( dst & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) dst |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; if ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; else DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: CreateImm ( bit ) ) ; if ( ! Dis -> tryAddingSymbolicOperand ( Inst , dst << <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: CreateImm ( dst ) ) ;


<s> if ( hasShortDelaySlot ) emitRR ( <STR_LIT> , <STR_LIT> , <STR_LIT> , IDLoc , STI ) ;

else emitRRI ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> , IDLoc , STI ) ;


<s> ++ It ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( LL ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( AND ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( NOR ) , StoreVal ) . addReg ( ZERO ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else {


<s> uint16_t VendorNameSize = VendorName . size ( ) + <NUM_LIT> ; uint16_t ArchNameSize = ArchName . size ( ) + <NUM_LIT> ; unsigned DescSZ = sizeof ( VendorNameSize ) + sizeof ( ArchNameSize ) + sizeof ( Major ) + sizeof ( Minor ) + sizeof ( Stepping ) + VendorNameSize + ArchNameSize ; convertIsaVersionV2 ( Major , Minor , Stepping , TargetID -> isSramEccOnOrAny ( ) , TargetID -> isXnackOnOrAny ( ) ) ;

EmitNote ( ElfNote :: NoteNameV2 , MCConstantExpr :: create ( DescSZ , getContext ( ) ) , ELF :: NT_AMD_HSA_ISA_VER<ISA_LIT>ON , [ & ] ( MCELFStreamer & OS ) {


<s> return ( RegNo == ( unsigned ) - <NUM_LIT> ) ;


<s> for ( rn = <NUM_LIT> ; rn < FIRST_PSEUDO_REGISTER ; rn ++ ) if ( class_contents [ rclass ] [ <NUM_LIT> ] & ( <NUM_LIT> << rn ) ) if ( ! m32c_hard_regno_mode_ok ( rn , to ) ) return false ;

if ( to == QImode ) return ( class_contents [ rclass ] [ <NUM_LIT> ] & <NUM_LIT> ) == <NUM_LIT> ;


<s> case AMDGPU :: S_LOAD_DWORDX4_SGPR : { if ( NewOpcode == N -> getMachineOpcode ( ) ) { NewOpcode = AMDGPU :: BUFFER_LOAD_DWORDX4_ADDR64 ; } if ( fitsRegClass ( DAG , N -> getOperand ( <NUM_LIT> ) , AMDGPU :: SReg_64RegClassID ) ) { return N ; } ConstantSDNode * Offset = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; const SDValue Zero64 = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ptr ( DAG . getMachineNode ( AMDGPU :: S_MOV_B64 , DL , <STR_LIT> , Zero64 ) , <NUM_LIT> ) ; MachineSDNode * RSrc = wrapAddr64Rsrc ( DAG , DL , Ptr ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( SDValue ( RSrc , <NUM_LIT> ) ) ;

Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) , false ) ; addPass ( create<ISA_LIT>Peephole ( ) ) ; printAndVerify ( <STR_LIT> ) ; if ( EnableGenInsert ) addPass ( create<ISA_LIT>GenInsert ( ) , false ) ;

if ( EnableEarlyIf ) addPass ( create<ISA_LIT>EarlyIfConversion ( ) , false ) ;


<s> DenseSet < const GlobalVariable * > Others ; for ( unsigned i = <NUM_LIT> , e = GV -> getNumOperands ( ) ; i != e ; ++ i ) DiscoverDependentGlobals ( GV -> getOperand ( i ) , Others ) ; for ( const GlobalVariable * GV : Others ) VisitGlobalVariableForEmission ( GV , Order , Visited , Visiting ) ; Order . push_back ( GV ) ; Visited . insert ( GV ) ; Visiting . erase ( GV ) ;


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool NoExecStack ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter , RelaxAll , NoExecStack ) ; return S ;


<s> static DecodeStatus DecodeSPR_8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) {

if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> unsigned VmcntLo = getBitMask ( getVmcntBitShiftLo ( ) , getVmcntBitWidthLo ( ) ) ; unsigned Expcnt = getBitMask ( getExpcntBitShift ( ) , getExpcntBitWidth ( ) ) ; unsigned Lgkmcnt = getBitMask ( getLgkmcntBitShift ( ) , getLgkmcntBitWidth ( ) ) ; unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt ; if ( Version . Major < <NUM_LIT> ) return Waitcnt ; unsigned VmcntHi = getBitMask ( getVmcntBitShiftHi ( ) , getVmcntBitWidthHi ( ) ) ; return Waitcnt | VmcntHi ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getAddressComputationCost ( Type * Ty , ScalarEvolution * SE , const SCEV * Ptr ) { const unsigned NumVectorInstToHideOverhead = <NUM_LIT> ; if ( Ty -> isVectorTy ( ) && SE ) { if ( ! BaseT :: isStridedAccess ( Ptr ) ) return NumVectorInstToHideOverhead ; if ( ! BaseT :: getConstantStrideStep ( SE , Ptr ) ) return <NUM_LIT> ; }

return BaseT :: getAddressComputationCost ( Ty , SE , Ptr ) ;


<s> auto * And1C = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! And1C ) return false ; APInt MaskVal = And1C -> getAPIntValue ( ) ; unsigned MaskLZ = MaskVal . countLeadingZeros ( ) ; if ( ! MaskLZ || ( VT == <STR_LIT> && MaskLZ == <NUM_LIT> ) ) return false ; if ( VT == <STR_LIT> && MaskLZ >= <NUM_LIT> ) { MaskLZ -= <NUM_LIT> ; MaskVal = MaskVal . trunc ( <NUM_LIT> ) ; } SDValue And0 = And -> getOperand ( <NUM_LIT> ) ; APInt HighZeros = APInt :: getHighBitsSet ( MaskVal . getBitWidth ( ) , MaskLZ ) ; APInt NegMaskVal = MaskVal | HighZeros ;

unsigned MinWidth = NegMaskVal . getMinSignedBits ( ) ;


<s> SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; if ( VecVT . isFixedLengthVector ( ) ) { MVT ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Res = splatPartsI64WithVL ( DL , ContainerVT , SDValue ( ) , Lo , Hi , VL , DAG ) ; return convertFromScalableVector ( VecVT , Res , DAG , Subtarget ) ; } if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ;

if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Lo , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ;


<s> <ISA_LIT>AsmLexer ( const Target & T , const MCRegisterInfo & MRI , const MCAsmInfo & MAI ) : MCTargetAsmLexer ( T ) , AsmInfo ( MAI ) , tentativeIsValid ( false ) {


<s> bool decrement = * code == mag_comparisons [ i ] [ <NUM_LIT> ] ; if ( ! increment && ! decrement ) continue ; if ( ( increment && rhs == HOST_WIDE_INT_MAX ) || ( decrement && rhs == HOST_WIDE_INT_MIN ) ) break ; new_rhs = rhs + ( increment ? <NUM_LIT> : - <NUM_LIT> ) ; if ( loongarch_integer_cost ( new_rhs ) < loongarch_integer_cost ( rhs ) ) { * op1 = GEN_INT ( new_rhs ) ; * code = mag_comparisons [ i ] [ increment ] ; } break ; } } } loongarch_extend_comparands ( * code , op0 , op1 ) ; * op0 = force_reg ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = force_reg ( word_mode , * op1 ) ;


<s> static void LookThroughSetCC ( SDValue & LHS , SDValue & RHS , <STR_LIT> CC , unsigned & <ISA_LIT>CC ) { if ( isNullConstant ( RHS ) && CC == <STR_LIT> && ( ( ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) || ( LHS . getOpcode ( ) == <STR_LIT> && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) && isOneConstant ( LHS . getOperand ( <NUM_LIT> ) ) && isNullConstant ( LHS . getOperand ( <NUM_LIT> ) ) ) { SDValue CMPCC = LHS . getOperand ( <NUM_LIT> ) ; <ISA_LIT>CC = cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; LHS = CMPCC . getOperand ( <NUM_LIT> ) ;

RHS = CMPCC . getOperand ( <NUM_LIT> ) ;


<s> int EltNo = SV -> getSplatIndex ( ) ; int NumElems = SrcVT . getVectorNumElements ( ) ; unsigned Size = SrcVT . getSizeInBits ( ) ; assert ( ( ( Size == <NUM_LIT> && NumElems > <NUM_LIT> ) || Size == <NUM_LIT> ) && <STR_LIT> ) ; if ( Size == <NUM_LIT> ) { unsigned Idx = ( EltNo >= NumElems / <NUM_LIT> ) ? NumElems / <NUM_LIT> : <NUM_LIT> ; V1 = Extract128BitVector ( V1 , DAG . getConstant ( Idx , <STR_LIT> ) , DAG , dl ) ; if ( Idx > <NUM_LIT> ) EltNo -= NumElems / <NUM_LIT> ; } EVT EltVT = SrcVT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) V1 = PromoteSplati8i16 ( V1 , DAG , EltNo ) ;


<s> if ( logical_operand ( op2 , mode ) ) emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_XOR ( mode , op1 , op2 ) ) ) ; else emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_PLUS ( mode , op1 , negate_rtx ( mode , op2 ) ) ) ) ; return scratch ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {


<s> return VNx2DImode ; case E_SImode : return VNx4SImode ; case E_HImode : return VNx8HImode ; case E_QImode : return VNx16QImode ;


<s> for ( ; I != E ; ++ I ) { if ( MemSDNode * M = dyn_cast < MemSDNode > ( * I ) ) { if ( getBasePtrIndex ( M ) == I . getOperandNo ( ) ) return true ;


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } else NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) { if ( NumBytes ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ;

MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> CopyPropagation ( DataFlowGraph & dfg ) : MDT ( dfg . getDT ( ) ) , DFG ( dfg ) , L ( dfg . getMF ( ) . getRegInfo ( ) , dfg ) {


<s> if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;


<s> printSymbolLo ( MI , OpNo , O ) ; O << '(' ;

if ( MI -> getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ;


<s> std :: vector < std :: string > mul_y0_r6 ( Mul3 op , Ax a ) { return D ( op , <STR_LIT> , <STR_LIT> , R ( a ) ) ;


<s> if ( ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( AM . BaseOffs ) ) return false ; switch ( AM . Scale ) { case <NUM_LIT> : return true ; case <NUM_LIT> : return true ; case <NUM_LIT> : if ( AM . HasBaseReg ) { return false ;


<s> static SDValue LowerFGETSIGN ( SDValue Op , SelectionDAG & DAG ) { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getValueType ( ) . getSimpleVT ( ) ;

SDValue xFGETSIGN = DAG . getNode ( <STR_LIT> , dl , VT , N0 , DAG . getConstant ( <NUM_LIT> , VT ) ) ;


<s> explicit <ISA_LIT>SEDAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OL ) : <ISA_LIT>DAGToDAGISel ( TM , OL ) {


<s> unsigned IntVal ; if ( NumString . getAsInteger ( <NUM_LIT> , IntVal ) ) return - <NUM_LIT> ; if ( IntVal > <NUM_LIT> ) return - <NUM_LIT> ;


<s> if ( I -> second . empty ( ) ) Prune . push_back ( I ) ; } for ( unsigned i = <NUM_LIT> , n = Prune . size ( ) ; i < n ; ++ i ) IFMap . erase ( Prune [ i ] ) ;


<s> legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : { SDValue Src0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != <STR_LIT> ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT , Src0 . getNode ( ) -> isDivergent ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == <STR_LIT> ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == <STR_LIT> ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , <NUM_LIT> > Ops = { Src0 , Src1 , Src2 } ; for ( unsigned I = <NUM_LIT> , N = Node -> getNumOperands ( ) ; I != N ; ++ I ) Ops . push_back ( Node -> getOperand ( I ) ) ; Ops . push_back ( ImpDef . getValue ( <NUM_LIT> ) ) ; return DAG . getMachineNode ( Opcode , SDLoc ( Node ) , Node -> getVTList ( ) , Ops ) ; } default : break ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue Res = DAG . getNode ( GenericOpc , DL , VT , LHS , RHS ) ; return DAG . getMergeValues ( { Res , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } , DL ) ; } auto MatchGeneric = [ & ] ( SDValue N0 , SDValue N1 , bool Negate ) { SDValue Ops [ ] = { N0 , N1 } ; SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) ) ; if ( SDNode * GenericAddSub = DAG . getNodeIfExists ( GenericOpc , VTs , Ops ) ) { SDValue Op ( N , <NUM_LIT> ) ; if ( Negate ) Op = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Op ) ; DCI . CombineTo ( GenericAddSub , Op ) ; } } ; MatchGeneric ( LHS , RHS , false ) ; MatchGeneric ( RHS , LHS , <STR_LIT> == N -> getOpcode ( ) ) ; return combineAddOrSubToADCOrSBB ( IsSub , DL , VT , LHS , RHS , DAG , true ) ;


<s> case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128ToCall ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , true ) ; case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , false ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , true ) ; case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG , false ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddressELF ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ;

case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ;


<s> } if ( Imm == FloatToBits ( <NUM_LIT> ) || Imm == FloatToBits ( - <NUM_LIT> ) || Imm == FloatToBits ( <NUM_LIT> ) || Imm == FloatToBits ( - <NUM_LIT> ) || Imm == FloatToBits ( <NUM_LIT> ) || Imm == FloatToBits ( - <NUM_LIT> ) || Imm == FloatToBits ( <NUM_LIT> ) || Imm == FloatToBits ( - <NUM_LIT> ) ) { O << BitsToFloat ( Imm ) ; return ;


<s> return new <ISA_LIT>LowerModuleLDS ( ) ;


<s> return __builtin_mve_vminq_uv4si ( __a , __b ) ;


<s> for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ;


<s> bool rs6000_keep_leaf_when_profiled ( void ) { return TARGET_PROFILE_KERNEL ;


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {


<s> const SCEV * Diff = SE -> getMinusSCEV ( LSCEV , B . BaseSCEV ) ; if ( const auto * CDiff = dyn_cast < SCEVConstant > ( Diff ) ) { B . Elements . push_back ( BucketElement ( CDiff , MemI ) ) ; FoundBucket = true ;


<s> static bool moxie_reg_ok_for_base_p ( const_rtx reg , bool strict_p ) { int regno = REGNO ( reg ) ; if ( strict_p ) return HARD_REGNO_OK_FOR_BASE_P ( regno ) || HARD_REGNO_OK_FOR_BASE_P ( reg_renumber [ regno ] ) ;

else return ! HARD_REGISTER_NUM_P ( regno ) || HARD_REGNO_OK_FOR_BASE_P ( regno ) ;


<s> TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0 ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1 ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src2 ) } ; int SelIdx [ ] = { TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0_sel ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1_sel ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src2_sel ) } ; int NegIdx [ ] = { TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0_neg ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1_neg ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src2_neg ) } ; int AbsIdx [ ] = { TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src0_abs ) , TII -> getOperandIdx ( Opcode , AMDGPU :: OpName :: src1_abs ) , - <NUM_LIT> } ; std :: vector < unsigned > Consts ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { int SrcIdx = OperandIdx [ j ] ; if ( SrcIdx < <NUM_LIT> ) break ; if ( RegisterSDNode * Reg = dyn_cast < RegisterSDNode > ( Ops [ SrcIdx - <NUM_LIT> ] ) ) { if ( Reg -> getReg ( ) == AMDGPU :: ALU_CONST ) { ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Ops [ SelIdx [ j ] - <NUM_LIT> ] ) ; Consts . push_back ( Cst -> getZExtValue ( ) ) ; } } }

for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {


<s> return MCDisassembler :: Fail ; } SrcC = decodeCField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , SrcC , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ;


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , object :: mach :: CPUSubtype<ISA_LIT> st ) : <ISA_LIT>AsmBackend ( T , TT ) , Subtype ( st ) {


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {


<s> <ISA_LIT>TargetStreamer :: ~ <ISA_LIT>TargetStreamer ( ) {


<s> return ( int8x8_t ) __builtin_neon_vabdsv8qi ( __a , __b ) ;


<s> static MCDisassembler :: DecodeStatus DecodeS9Operand ( MCInst & Inst , unsigned InsnS9 , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( <NUM_LIT> & InsnS9 ) ) ) ; return MCDisassembler :: Success ;


<s> Value * <ISA_LIT>IREmitter :: visitVRSHRs ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { if ( SDValue Elt = getShuffleScalarElt ( Op , i , DAG , <NUM_LIT> ) ) { Elts . push_back ( Elt ) ; continue ; }


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; break ;


bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;


<s> bool hasStandaloneRem ( EVT VT ) const override { return HasStandaloneRem ;


<s> if ( CacheLineSize . getNumOccurrences ( ) > <NUM_LIT> ) return CacheLineSize ;

unsigned Directive = ST -> getCPUDirective ( ) ;


<s> bool isGPRCalleeSavedArea2Frame ( int fi ) const { if ( fi < <NUM_LIT> || fi >= ( int ) GPRCS2Frames . size ( ) ) return false ;


<s> MachineBasicBlock * NewMBB = emitBlockAfter ( MBB ) ; NewMBB -> splice ( NewMBB -> begin ( ) , MBB , MI , MBB -> end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ;


<s> for ( offset -= <NUM_LIT> ; offset >= <NUM_LIT> ; offset -= <NUM_LIT> , rn -- ) { rtx dst = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; insn = emit_move_insn ( dst , gen_rtx_REG ( SImode , rn ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } } } if ( csky_can_use_pushpop ( reg_mask ) ) emit_csky_regs_push ( reg_mask ) ; else if ( reg_size ) { int sreg = - <NUM_LIT> , ereg = - <NUM_LIT> ; bool stm_p = csky_can_use_ldstm ( reg_mask , & sreg , & ereg ) ; int stm_regs = stm_p ? ereg - sreg + <NUM_LIT> : <NUM_LIT> ; int stm_size = stm_regs * <NUM_LIT> ; expand_csky_stack_adjust ( - reg_size ) ; if ( reg_size > stm_size ) { int offset = reg_size - <NUM_LIT> ; int regno = <NUM_LIT> ; for ( ; regno > ereg ; regno -- ) if ( reg_mask & ( <NUM_LIT> << regno ) ) { rtx dst = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; rtx insn = emit_insn ( gen_movsi ( dst , gen_rtx_REG ( SImode , regno ) ) ) ;


<s> if ( loongarch_symbolic_constant_p ( base , & type ) ) {

if ( IMM12_INT ( offset ) && loongarch_symbol_insns ( type , MAX_MACHINE_MODE ) > <NUM_LIT> ) return true ;


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ;


<s> static inline int getMClassFlagsMask ( StringRef Flags , bool hasThumb2DSP ) { if ( Flags . empty ( ) ) return <NUM_LIT> | ( int ) hasThumb2DSP ;

return StringSwitch < int > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> SmallVector < Metadata * , <NUM_LIT> > All ; for ( auto MD : NamedMD -> operands ( ) ) for ( const auto & Op : MD -> operands ( ) ) if ( std :: find ( All . begin ( ) , All . end ( ) , Op . get ( ) ) == All . end ( ) ) All . push_back ( Op . get ( ) ) ; NamedMD -> eraseFromParent ( ) ; NamedMD = M . getOrInsertNamedMetadata ( Name ) ; for ( const auto & MD : All ) NamedMD -> addOperand ( MDNode :: get ( M . getContext ( ) , MD ) ) ; return true ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( pass_by_reference ( NULL , TYPE_MODE ( type ) , type , false ) ) { tree ptrtype = build_pointer_type ( type ) ; tree addr = std_gimplify_va_arg_expr ( valist , ptrtype , pre_p , post_p ) ; return build_va_arg_indirect_ref ( addr ) ; }

if ( ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) ? int_size_in_bytes ( type ) > <NUM_LIT> : TYPE_ALIGN ( type ) > <NUM_LIT> * BITS_PER_UNIT ) {


<s> MatchAny = MatchZero = false ; break ; } MatchAny &= isUndefInRange ( Mask , ( i * Scale ) + <NUM_LIT> , Scale - <NUM_LIT> ) ; MatchZero &= isUndefOrZeroInRange ( Mask , ( i * Scale ) + <NUM_LIT> , Scale - <NUM_LIT> ) ; } if ( MatchAny || MatchZero ) { assert ( MatchZero && <STR_LIT> ) ; unsigned SrcSize = std :: max ( <NUM_LIT> , NumDstElts * MaskEltSize ) ; MVT ScalarTy = MaskVT . isInteger ( ) ? MaskVT . getScalarType ( ) : <STR_LIT> ( MaskEltSize ) ; SrcVT = <STR_LIT> ( ScalarTy , SrcSize / MaskEltSize ) ; if ( SrcVT . getSizeInBits ( ) != MaskVT . getSizeInBits ( ) ) V1 = extractSubVector ( V1 , <NUM_LIT> , DAG , DL , SrcSize ) ; Shuffle = unsigned ( MatchAny ? <STR_LIT> : <STR_LIT> ) ; if ( SrcVT . getVectorNumElements ( ) != NumDstElts ) Shuffle = getOpcode_EXTEND_VECTOR_INREG ( Shuffle ) ; DstVT = <STR_LIT> ( Scale * MaskEltSize ) ; DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) {


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( STI ) {


return isMovWSymbol ( { <ISA_LIT>MCExpr :: VK_ABS_G1_NC , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC , <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC } ) ;


<s> <ISA_LIT>BSel ( ) : MachineFunctionPass ( ID ) {


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Immed ) const { if ( <ISA_LIT>NoLegalImmediate ) return Immed >= - <NUM_LIT> && Immed < <NUM_LIT> ;

return TargetLowering :: isLegalICmpImmediate ( Immed ) ;


<s> SMLoc ExprLoc = getLexer ( ) . getLoc ( ) ; if ( ! getLexer ( ) . is ( AsmToken :: Hash ) ) return Error ( ExprLoc , <STR_LIT> ) ; getLexer ( ) . Lex ( ) ; const MCExpr * Val ; if ( getParser ( ) . parseExpression ( Val ) ) return Error ( ExprLoc , <STR_LIT> ) ; int64_t Res ; if ( Val -> evaluateAsAbsolute ( Res ) ) if ( Res < <NUM_LIT> || Res > <NUM_LIT> ) return Error ( ExprLoc , <STR_LIT> ) ; std :: unique_ptr < <ISA_LIT>Operand > CntOp = <STR_LIT> ( Val , ExprLoc , getLexer ( ) . getLoc ( ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . eatToEndOfStatement ( ) ; Operands . push_back ( <STR_LIT> ( getLexer ( ) . getTok ( ) . getString ( ) , getLexer ( ) . getLoc ( ) ) ) ;


<s> EnqueueExitsPass ( ) : MachineFunctionPass ( ID ) {


<s> static <ISA_LIT>Operand * CreateConstant ( int value , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Immediate ) ; Op -> Imm . Val = MCConstantExpr :: create ( value , Ctx ) ; Op -> StartLoc = S ;


<s> SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPSCR , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RMODE , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> MCAsmParser & Parser = getParser ( ) ; const MCExpr * Value ; if ( getParser ( ) . parseExpression ( Value ) ) return true ; getParser ( ) . getStreamer ( ) . emitGPRel32Value ( Value ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; return false ;


<s> } fntype_callee = TREE_TYPE ( CALL_EXPR_FN ( exp_callee ) ) ; if ( decl_callee ) { decl_callee = TREE_TYPE ( decl_callee ) ; } else { decl_callee = fntype_callee ; while ( FUNCTION_TYPE != TREE_CODE ( decl_callee ) && METHOD_TYPE != TREE_CODE ( decl_callee ) ) { decl_callee = TREE_TYPE ( decl_callee ) ; } } if ( cfun -> machine -> is_interrupt || cfun -> machine -> is_signal || cfun -> machine -> is_naked || avr_naked_function_p ( decl_callee ) ) { return false ; } return true ;


<s> bool OutgoingValueHandler :: handleSplit ( SmallVectorImpl < Register > & VRegs , ArrayRef < CCValAssign > ArgLocs , unsigned ArgLocsStartIndex , Register ArgsReg , const EVT & VT ) { MIRBuilder . buildUnmerge ( VRegs , ArgsReg ) ; setLeastSignificantFirst ( VRegs ) ; if ( ! assignVRegs ( VRegs , ArgLocs , ArgLocsStartIndex , VT ) ) return false ; return true ;


<s> return ( __m256 ) __builtin_ia32_cvtpd2ps512_mask ( ( __v8df ) __A , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 ) __U , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;

if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm << <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ;


<s> return __builtin_aarch64_smaxv8qi ( __a , __b ) ;


<s> if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) return readonly_data_section ; else return data_section ; } else { if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) return readonly_data_section ; else return data_section ; }


<s> bool R600InstrInfo :: usesTextureCache ( const MachineInstr * MI ) const { const R600MachineFunctionInfo * MFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < R600MachineFunctionInfo > ( ) ; return ( MFI -> ShaderType == ShaderType :: COMPUTE && usesVertexCache ( MI -> getOpcode ( ) ) ) || usesTextureCache ( MI -> getOpcode ( ) ) ;


<s> static unsigned int rs6000_hard_regno_nregs_hook ( unsigned int regno , machine_mode mode ) {

return rs6000_hard_regno_nregs [ mode ] [ regno ] ;


<s> bool <ISA_LIT>FastISel :: SelectFPExt ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2Base ( ) || ! Subtarget -> hasFP64 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ;


<s> bool inMicro<ISA_LIT>Mode ( ) const { return InMicro<ISA_LIT>Mode ;


<s> static void x86_print_call_or_nop ( FILE * file , const char * target ) { if ( flag_nop_mcount ) fprintf ( file , <STR_LIT> ASM_BYTE <STR_LIT> ) ; else fprintf ( file , <STR_LIT> , target ) ;


<s> if ( sscanf ( arg , HOST_WIDE_INT_PRINT_DEC , & s390_stack_guard ) != <NUM_LIT> ) return false ; if ( exact_log2 ( s390_stack_guard ) == - <NUM_LIT> ) error ( <STR_LIT> ) ; return true ; case OPT_mstack_size_ : if ( sscanf ( arg , HOST_WIDE_INT_PRINT_DEC , & s390_stack_size ) != <NUM_LIT> ) return false ; if ( exact_log2 ( s390_stack_size ) == - <NUM_LIT> ) error ( <STR_LIT> ) ; return true ; case OPT_mtune_ : return s390_handle_arch_option ( arg , & s390_tune , & s390_tune_flags ) ; case OPT_mwarn_framesize_ : return sscanf ( arg , HOST_WIDE_INT_PRINT_DEC , & s390_warn_framesize ) == <NUM_LIT> ; default : return true ; }


<s> Register Address = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator I ( MI ) ; if ( Subtarget . has<ISA_LIT>32r6 ( ) || Subtarget . has<ISA_LIT>64r6 ( ) ) { Register BitcastW = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( BitcastW ) . addUse ( StoreVal ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Tmp ) . addUse ( BitcastW ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm ) ; } else { Register Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Tmp ) . addUse ( StoreVal ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ;


<s> unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! align ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;

else Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> << align ) ) ;


<s> if ( Offset . is ( AsmToken :: Integer ) ) { parseSingleInteger ( false , Operands ) ; } else { Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Offset . getLoc ( ) , Offset . getEndLoc ( ) , <STR_LIT> { <NUM_LIT> } ) ) ;


<s> for ( auto & MO : FirstI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ;

if ( SecondI . readsRegister ( R , TRI ) ) return true ;


<s> bool <ISA_LIT>ExpandPseudo :: expandLoadAddress ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { MachineFunction * MF = MBB . getParent ( ) ; unsigned SecondOpcode ; unsigned FlagsHi ; if ( MF -> getTarget ( ) . isPositionIndependent ( ) ) {

const auto & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> int Op32 = <STR_LIT> ( Opcode ) ; if ( Op32 == - <NUM_LIT> ) return false ;

return pseudoToMCOpcode ( Op32 ) != - <NUM_LIT> ;


<s> void printdwordmem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printMemReference ( MI , OpNo , O ) ;


<s> OS << <STR_LIT> ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) OS . write_hex ( ( Value & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ) >> ( i * <NUM_LIT> ) ) ;


<s> machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return <NUM_LIT> ;


<s>
rtx
note
;
int
v8
=
<NUM_LIT>
;
if
(
!
far
&&
insn
&&
INSN_ADDRESSES_SET_P
(
)
)
{
int
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
<
<NUM_LIT>
||
delta
>=
<NUM_LIT>
)
v8
=
<NUM_LIT>
;
}
switch
(
mode
)
{
case
E_CCmode
:
case
E_CCNZmode
:
case
E_CCCmode
:
case
E_CCVmode
:
labelno
=
<STR_LIT>
;
if
(
v8
)
labelno
=
<STR_LIT>
;
break
;
case
E_CCXmode
:
case
E_CCXNZmode
:
case
E_CCXCmode
:
case
E_CCXVmode
:
labelno
=
<STR_LIT>
;
gcc_assert
(
!
v8
)
;
break
;
case
E_CCFPmode
:
case
E_CCFPEmode
:
{
static
char
v9_fcc_labelno
[
]
=
<STR_LIT>
;
v9_fcc_labelno
[
<NUM_LIT>
]
=
REGNO
(
cc_reg
)
SPARC_FIRST_V9_FCC_REG
+
'0'
;
labelno
=
v9_fcc_labelno
;
if
(
v8
)
{
gcc_assert
(
REGNO
(
cc_reg
)
==
SPARC_FCC_REG
)
;
labelno
=
<STR_LIT>
;
}
}
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
*
labelno
&&
insn
&&
(
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
)
)
{
strcpy
(
p
,
(
(
profile_probability
::
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XINT
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note
,
<NUM_LIT>
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(
)
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far
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<STR_LIT>
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<STR_LIT>
)
;
p
+=
<NUM_LIT>
;
spaces
-=
<NUM_LIT>
;
}
}
else
labelno
=
<STR_LIT>
;
if
(
spaces
>
<NUM_LIT>
)
*
p
++
=
'\t'
;
else
*
p
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=
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;
strcpy
(
p
,
labelno
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;
p
=
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if
(
far
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{
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(
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<STR_LIT>
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if
(
annul
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final_sequence
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p
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]
=
'6'
;
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+=
<NUM_LIT>
;
}
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
label
+
'0'
;


<s> Changed |= enableSC1Bit ( MI ) ; break ; case <STR_LIT> : Changed |= enableSC0Bit ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } }


<s> for ( unsigned I : CSRs ) { BuildMI ( MBB , MBBI , DL , * Insn ) . addReg ( I , IsSave ? RegState :: Undef : RegState :: Define ) . addReg ( Basereg ) . addImm ( Adjust + Idx ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << ( IsSave ? <STR_LIT> : <STR_LIT> ) << TRI -> getName ( I ) << ( IsSave ? <STR_LIT> : <STR_LIT> ) << ( TRI -> isVirtualRegister ( Basereg ) ? <STR_LIT> : TRI -> getName ( Basereg ) ) << <STR_LIT> << ( Adjust + Idx ) << <STR_LIT> ) ;


<s> static bool aarch64_evpc_dup ( struct expand_vec_perm_d * d ) { rtx out = d -> target ; rtx in0 ; HOST_WIDE_INT elt ; machine_mode vmode = d -> vmode ; rtx lane ; if ( d -> vec_flags == VEC_SVE_PRED || d -> perm . encoding ( ) . encoded_nelts ( ) != <NUM_LIT> || ! d -> perm [ <NUM_LIT> ] . is_constant ( & elt ) ) return false ; if ( d -> vec_flags == VEC_SVE_DATA && elt >= <NUM_LIT> * GET_MODE_UNIT_SIZE ( vmode ) ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & The<ISA_LIT>Target32 , & The<ISA_LIT>Target64 } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ;

TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ;


<s> CallGraph & CG = getAnalysis < CallGraph > ( ) ; CallGraphNode * ECN = CG . getExternalCallingNode ( ) ; MarkIndirectlyCalledFunctions ( M ) ; if ( ECN ) {


<s> Inst . addOperand ( MCOperand :: createReg ( getMSA128Reg ( ) ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Elt = Op . getOperand ( i ) ; if ( Elt . getOpcode ( ) != <STR_LIT> || Elt . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) != VT . getVectorElementType ( ) ) return false ; if ( ! V0 . getNode ( ) ) { V0 = Elt . getOperand ( <NUM_LIT> ) ; V0NumElts = V0 . getValueType ( ) . getVectorNumElements ( ) ; } if ( Elt . getOperand ( <NUM_LIT> ) == V0 ) { Mask [ i ] = ( cast < ConstantSDNode > ( Elt -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; continue ; } else if ( ! V1 . getNode ( ) ) { V1 = Elt . getOperand ( <NUM_LIT> ) ; } if ( Elt . getOperand ( <NUM_LIT> ) == V1 ) {

unsigned Lane = cast < ConstantSDNode > ( Elt -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> static const auto ValidMinMaxTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; } static const TypeConversionCostTblEntry VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost


<s> bool <ISA_LIT>RegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & ) const { return true ;


<s> static __inline unsigned long long sh_media_MCMPEQ_L ( unsigned long long mm , unsigned long long mn ) { typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MCMPEQ_L ( ( v2si ) mm , ( v2si ) mn ) ;


<s> return false ; } ; if ( ! CanShrinkOp ( LHS ) && ! CanShrinkOp ( RHS ) ) return false ; IRBuilder < > Builder ( Mul ) ; auto * MulTy = cast < VectorType > ( Op -> getType ( ) ) ; unsigned NumElts = MulTy -> getNumElements ( ) ; SmallVector < int , <NUM_LIT> > EvenMask ( NumElts / <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > OddMask ( NumElts / <NUM_LIT> ) ; for ( int i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i != e ; ++ i ) { EvenMask [ i ] = i * <NUM_LIT> ; OddMask [ i ] = i * <NUM_LIT> + <NUM_LIT> ; } Value * NewMul = Builder . CreateMul ( Mul -> getOperand ( <NUM_LIT> ) , Mul -> getOperand ( <NUM_LIT> ) ) ; Value * EvenElts = Builder . CreateShuffleVector ( NewMul , NewMul , EvenMask ) ; Value * OddElts = Builder . CreateShuffleVector ( NewMul , NewMul , OddMask ) ; Value * MAdd = Builder . CreateAdd ( EvenElts , OddElts ) ; SmallVector < int , <NUM_LIT> > ConcatMask ( NumElts ) ; std :: iota ( ConcatMask . begin ( ) , ConcatMask . end ( ) , <NUM_LIT> ) ; Value * Zero = Constant :: getNullValue ( MAdd -> getType ( ) ) ; Value * Concat = Builder . CreateShuffleVector ( MAdd , Zero , ConcatMask ) ; Mul -> replaceAllUsesWith ( Concat ) ; Mul -> eraseFromParent ( ) ; return true ;


<s> Value * v = Cexpr -> getOperand ( <NUM_LIT> ) -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr -> getOperand ( <NUM_LIT> ) ) ; aggBuffer -> addZeros ( <NUM_LIT> ) ; break ; } } llvm_unreachable ( <STR_LIT> ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; } case Type :: FloatTyID : case Type :: DoubleTyID : { const ConstantFP * CFP = dyn_cast < ConstantFP > ( CPV ) ; const Type * Ty = CFP -> getType ( ) ; if ( Ty == Type :: getFloatTy ( CPV -> getContext ( ) ) ) { float float32 = ( float ) CFP -> getValueAPF ( ) . convertToFloat ( ) ; ConvertFloatToBytes ( ptr , float32 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else if ( Ty == Type :: getDoubleTy ( CPV -> getContext ( ) ) ) { double float64 = CFP -> getValueAPF ( ) . convertToDouble ( ) ; ConvertDoubleToBytes ( ptr , float64 ) ; aggBuffer -> addBytes ( ptr , <NUM_LIT> , Bytes ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } break ; } case Type :: PointerTyID : { if ( const GlobalValue * GVar = dyn_cast < GlobalValue > ( CPV ) ) { aggBuffer -> addSymbol ( GVar , GVar ) ; } else if ( const ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( CPV ) ) { const Value * v = Cexpr -> stripPointerCasts ( ) ; aggBuffer -> addSymbol ( v , Cexpr ) ; } unsigned int s = TD -> getTypeAllocSize ( CPV -> getType ( ) ) ; aggBuffer -> addZeros ( s ) ; break ; } case Type :: ArrayTyID : case Type :: VectorTyID : case Type :: StructTyID : { if ( isa < ConstantArray > ( CPV ) || isa < ConstantVector > ( CPV ) || isa < ConstantStruct > ( CPV ) || isa < ConstantDataSequential > ( CPV ) ) { int ElementSize = TD -> getTypeAllocSize ( CPV -> getType ( ) ) ; bufferAggregateConstant ( CPV , aggBuffer ) ; if ( Bytes > ElementSize ) aggBuffer -> addZeros ( Bytes - ElementSize ) ; } else if ( isa < ConstantAggregateZero > ( CPV ) ) aggBuffer -> addZeros ( Bytes ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; }


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; } if ( Subtarget -> hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; } if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( Subtarget -> hasSSE41 ( ) ) { if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleAsInsertPS ( Op , V1 , V2 , Mask , DAG ) ) return V ; if ( ! isSingleSHUFPSMask ( Mask ) ) if ( SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BlendPerm ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ;

if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 ) ;


<s> emit_move_insn ( value4word , new_val ) ; } else { if ( NDS32_EXT_DSP_P ( ) ) { rtx tmp = gen_reg_rtx ( SImode ) ; convert_move ( tmp , value , true ) ; emit_insn ( gen_insvsi_internal ( tmp , gen_int_mode ( <NUM_LIT> , SImode ) , tmp ) ) ; emit_insn ( gen_pkbbsi_1 ( value4word , tmp , tmp ) ) ; } else { rtx tmp1 , tmp2 , tmp3 , tmp4 ; tmp1 = expand_binop ( SImode , and_optab , value , gen_int_mode ( <NUM_LIT> , SImode ) , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; tmp2 = expand_binop ( SImode , ashl_optab , tmp1 , gen_int_mode ( <NUM_LIT> , SImode ) , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; tmp3 = expand_binop ( SImode , ior_optab , tmp1 , tmp2 , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; tmp4 = expand_binop ( SImode , ashl_optab , tmp3 , gen_int_mode ( <NUM_LIT> , SImode ) , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_insn ( gen_iorsi3 ( value4word , tmp3 , tmp4 ) ) ; } } return value4word ;


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case FK_Data_2 : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_8 : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_4 : default :


<s> void <ISA_LIT>DeadRegisterDefinitions :: processMachineBasicBlock ( MachineBasicBlock & MBB ) { const MachineFunction & MF = * MBB . getParent ( ) ; for ( MachineInstr & MI : MBB ) { if ( usesFrameIndex ( MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( MI . definesRegister ( <STR_LIT> ) || MI . definesRegister ( <STR_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } if ( atomicBarrierDroppedOnZero ( MI . getOpcode ( ) ) || atomicReadDroppedOnZero ( MI . getOpcode ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ; for ( int I = <NUM_LIT> , E = Desc . getNumDefs ( ) ; I != E ; ++ I ) { MachineOperand & MO = MI . getOperand ( I ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( Reg ) || ( ! MO . isDead ( ) && ! MRI -> use_nodbg_empty ( Reg ) ) ) continue ; assert ( ! MO . isImplicit ( ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I << <STR_LIT> ; MI . print ( dbgs ( ) ) ) ; if ( MI . isRegTiedToUseOperand ( I ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } const TargetRegisterClass * RC = TII -> getRegClass ( Desc , I , TRI , MF ) ; unsigned NewReg ; if ( RC == nullptr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } else if ( RC -> contains ( <STR_LIT> ) ) NewReg = <STR_LIT> ; else if ( RC -> contains ( <STR_LIT> ) ) NewReg = <STR_LIT> ; else {


<s> mode = alpha_compute_xfloating_mode_arg ( code , ALPHA_FPRM_CHOP ) ; out_operands [ <NUM_LIT> ] = GEN_INT ( mode ) ; noperands = <NUM_LIT> ; break ; case FLOAT_TRUNCATE : mode = alpha_compute_xfloating_mode_arg ( code , alpha_fprm ) ; out_operands [ <NUM_LIT> ] = GEN_INT ( mode ) ; noperands = <NUM_LIT> ; break ; default : break ; } alpha_emit_xfloating_libcall ( func , operands [ <NUM_LIT> ] , out_operands , noperands , gen_rtx_fmt_e ( orig_code , GET_MODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] ) ) ;


<s> if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> for ( int RegisterIndex = <STR_LIT> ; RegisterIndex <= <STR_LIT> ; ++ RegisterIndex ) { if ( ! MRI . isPhysRegUsed ( RegisterIndex ) && ! ( std :: find ( UsedRegisters . begin ( ) , UsedRegisters . end ( ) , RegisterIndex ) != UsedRegisters . end ( ) ) ) { return RegisterIndex ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMovePRegSingleOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( ( ( OpNo == <NUM_LIT> ) || ( OpNo == <NUM_LIT> ) ) && <STR_LIT> ) ; MCOperand Op = MI . getOperand ( OpNo ) ; assert ( Op . isReg ( ) && <STR_LIT> ) ; switch ( Op . getReg ( ) ) { default :


<s> ResTys . push_back ( EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ) ; } if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT . getVectorElementType ( ) , NumVecs ) ; Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } SDValue SuperReg ; SDValue V0 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) { if ( is64BitVector ) SuperReg = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; } else { SDValue V2 = N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( Vec0Idx + <NUM_LIT> ) ; if ( is64BitVector ) SuperReg = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; else SuperReg = SDValue ( createQuadQRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; } Ops . push_back ( SuperReg ) ; Ops . push_back ( getI32Imm ( Lane , dl ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes [ OpcodeIndex ] ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( VLdLn ) , { MemOp } ) ; if ( ! IsLoad ) { ReplaceNode ( N , VLdLn ) ; return ; }

SuperReg = SDValue ( VLdLn , <NUM_LIT> ) ;


<s> SDValue V = M < Size ? V1 : V2 ; if ( V . getOpcode ( ) != <STR_LIT> ) continue ; SDValue Input = V . getOperand ( M % Size ) ; if ( Input . getOpcode ( ) == <STR_LIT> || <STR_LIT> ( Input ) ) Zeroable [ i ] = true ;


<s> switch ( code ) { case CONST_INT : * total = mcore_const_costs ( x , outer_code ) ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : * total = <NUM_LIT> ; return true ; case AND : * total = COSTS_N_INSNS ( mcore_and_cost ( x ) ) ; return true ; case IOR : * total = COSTS_N_INSNS ( mcore_ior_cost ( x ) ) ; return true ; case DIV : case UDIV : case MOD : case UMOD : case FLOAT : case FIX : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ;


<s> getImm ( ) -> print ( OS ) ; break ; case MemBarrierOpt : OS << <STR_LIT> << MemBOptToString ( getMemBarrierOpt ( ) ) << <STR_LIT> ; break ; case Memory : OS << <STR_LIT> << <STR_LIT> << getMemBaseRegNum ( ) ; if ( getMemOffsetIsReg ( ) ) { OS << <STR_LIT> << getMemOffsetRegNum ( ) ; if ( getMemOffsetRegShifted ( ) ) { OS << <STR_LIT> << getMemShiftType ( ) ; OS << <STR_LIT> << * getMemShiftAmount ( ) ; } } else { OS << <STR_LIT> << * getMemOffset ( ) ; } if ( getMemOffsetIsReg ( ) ) OS << <STR_LIT> ; if ( getMemPreindexed ( ) ) OS << <STR_LIT> ; if ( getMemPostindexed ( ) ) OS << <STR_LIT> ; if ( getMemNegative ( ) ) OS << <STR_LIT> ; if ( getMemWriteback ( ) ) OS << <STR_LIT> ; OS << <STR_LIT> ; break ; case ProcIFlags : { OS << <STR_LIT> ; unsigned IFlags = getProcIFlags ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) OS << <STR_LIT> ( <NUM_LIT> << i ) ; OS << <STR_LIT> ; break ; } case Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case RegisterList : case DPRRegisterList : case SPRRegisterList : { OS << <STR_LIT> ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( SmallVectorImpl < unsigned > :: const_iterator I = RegList . begin ( ) , E = RegList . end ( ) ; I != E ; ) { OS << * I ; if ( ++ I < E ) OS << <STR_LIT> ; }


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>TargetMachine & tm , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TM ( tm ) , TII ( tii ) {

StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ;


<s> PhiEntry ( const VNInfo * Phi , unsigned PredIdx , LaneBitmask DefinedLanes ) : Phi ( Phi ) , PredIdx ( PredIdx ) , DefinedLanes ( DefinedLanes ) {


<s> unsigned Subo = ( size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned Even = MRI . getSubReg ( Reg , Sube ) ; unsigned Odd = MRI . getSubReg ( Reg , Subo ) ;

O << getRegisterName ( Even ) << <STR_LIT> << getRegisterName ( Odd ) ;