<s> CallingConv :: ID CC = B . getMF ( ) . getFunction ( ) . getCallingConv ( ) ; const bool IsShader = <STR_LIT> ( CC ) ; const bool IsWaveEnd = ( IsShader && MFI -> returnsVoid ( ) ) || <STR_LIT> ( CC ) ; if ( IsWaveEnd ) { B . buildInstr ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; return true ; } unsigned ReturnOpc = IsShader ? <STR_LIT> : <STR_LIT> ; auto Ret = B . buildInstrNoInsert ( ReturnOpc ) ; if ( ! FLI . CanLowerReturn ) insertSRetStores ( B , Val -> getType ( ) , VRegs , FLI . DemoteRegister ) ; else if ( ! lowerReturnVal ( B , Val , VRegs , Ret ) ) return false ; B . insertInstr ( Ret ) ;


<s> void UseNode :: linkToDef ( NodeId Self , NodeAddr < DefNode * > DA ) { Ref . RD = DA . Id ; Ref . Sib = DA . Addr -> getReachedUse ( ) ;


<s> op0 = copy_to_mode_reg ( tmode , op0 ) ; if ( ! BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG ) { rtx temp = gen_reg_rtx ( tmode ) ; rtx sel = swap_selector_for_mode ( tmode ) ; rtx vperm = gen_rtx_UNSPEC ( tmode , gen_rtvec ( <NUM_LIT> , op0 , op0 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( temp , vperm ) ) ; emit_insn ( gen_rtx_SET ( addr , temp ) ) ; } else emit_insn ( gen_rtx_SET ( addr , op0 ) ) ; } else { if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , smode ) ) op0 = copy_to_mode_reg ( smode , op0 ) ; if ( op1 == const0_rtx ) addr = gen_rtx_MEM ( tmode , op2 ) ; else { op1 = copy_to_mode_reg ( mode1 , op1 ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op2 , op1 ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) {

unsigned Size = getSizeInBits ( MI . getOperand ( i ) . getReg ( ) , MRI , * TRI ) ;


<s> case 'x' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) ) return true ; Register Reg = MI -> getOperand ( OpNo ) . getReg ( ) ; if ( <ISA_LIT>InstrInfo :: isVRRegister ( Reg ) ) Reg = <STR_LIT> + ( Reg - <STR_LIT> ) ; else if ( <ISA_LIT>InstrInfo :: isVFRegister ( Reg ) ) Reg = <STR_LIT> + ( Reg - <STR_LIT> ) ; const char * RegName ; RegName = <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; RegName = <ISA_LIT>RegisterInfo :: stripRegisterPrefix ( RegName ) ; O << RegName ; return false ; } } printOperand ( MI , OpNo , O ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( ( STI . isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ) , ( STI . isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ) , <STR_LIT> , ( STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) , Subtarget ( STI ) , RI ( STI . getTargetTriple ( ) ) {


<s> if ( ! ResVT . isSimple ( ) ) return SDValue ( ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; if ( SrcVT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; unsigned SrcEltSize = SrcVT . getVectorElementType ( ) . getSizeInBits ( ) ; unsigned ElementCount = SrcVT . getVectorNumElements ( ) ; SrcVT = <STR_LIT> ( <STR_LIT> ( SrcEltSize * <NUM_LIT> ) , ElementCount ) ; SDLoc DL ( N ) ; Src = DAG . getNode ( N -> getOpcode ( ) , DL , SrcVT , Src ) ; EVT LoVT , HiVT ; SDValue Lo , Hi ; unsigned NumElements = ResVT . getVectorNumElements ( ) ; assert ( ! ( NumElements & <NUM_LIT> ) && <STR_LIT> ) ; LoVT = HiVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ResVT . getVectorElementType ( ) , NumElements / <NUM_LIT> ) ; EVT InNVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT . getVectorElementType ( ) , LoVT . getVectorNumElements ( ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getIntPtrConstant ( InNVT . getVectorNumElements ( ) ) ) ; Lo = DAG . getNode ( N -> getOpcode ( ) , DL , LoVT , Lo ) ; Hi = DAG . getNode ( N -> getOpcode ( ) , DL , HiVT , Hi ) ;

return DAG . getNode ( <STR_LIT> , DL , ResVT , Lo , Hi ) ;


<s> if ( MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , SrcVT . getSizeInBits ( ) / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( LoMask ) ; return true ; } if ( isUndefOrInRange ( HiMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( LoMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { int OffsetHiMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) OffsetHiMask [ i ] = ( HiMask [ i ] < <NUM_LIT> ? HiMask [ i ] : HiMask [ i ] - <NUM_LIT> ) ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , SrcVT . getSizeInBits ( ) / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( OffsetHiMask ) ; return true ; } return false ; } return false ; } if ( MaskScalarSizeInBits != <NUM_LIT> && MaskScalarSizeInBits != <NUM_LIT> ) return false ; bool FloatDomain = SrcVT . isFloatingPoint ( ) ; if ( FloatDomain && ! Subtarget . hasAVX ( ) ) return false ; if ( SrcVT . is256BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) FloatDomain = true ; if ( is128BitLaneCrossingShuffleMask ( MaskEltVT , Mask ) ) { if ( Subtarget . hasAVX2 ( ) && SrcVT . is256BitVector ( ) && Mask . size ( ) == <NUM_LIT> ) { Shuffle = <STR_LIT> ; ShuffleVT = ( FloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( Mask ) ; return true ; } if ( Subtarget . hasAVX512 ( ) && SrcVT . is512BitVector ( ) && Mask . size ( ) == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( FloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( RepeatedMask ) ; return true ;


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const { return Subtarget . getJumpTableEncoding ( ) ;


<s> e . add_output_operand ( dest , mode ) ; if ( mask ) e . add_input_operand ( mask , GET_MODE ( mask ) ) ; else e . add_all_one_mask_operand ( mask_mode ) ; e . add_vundef_operand ( mode ) ; e . add_input_operand ( src , GET_MODE ( src ) ) ;

if ( len ) e . add_input_operand ( len , Pmode ) ;


<s> case LENGTH_TABLE_NONE : gcc_unreachable ( ) ; case LENGTH_TABLE_ADD : if ( GET_MODE ( operands [ <NUM_LIT> ] ) == QImode ) return h8300_binary_length ( insn , & addb_length_table ) ; else if ( GET_MODE ( operands [ <NUM_LIT> ] ) == HImode ) return h8300_binary_length ( insn , & addw_length_table ) ; else if ( GET_MODE ( operands [ <NUM_LIT> ] ) == SImode ) return h8300_binary_length ( insn , & addl_length_table ) ; gcc_unreachable ( ) ; case LENGTH_TABLE_LOGICB : return h8300_binary_length ( insn , & logicb_length_table ) ; case LENGTH_TABLE_MOVB : return h8300_move_length ( operands , & movb_length_table ) ; case LENGTH_TABLE_MOVW : return h8300_move_length ( operands , & movw_length_table ) ; case LENGTH_TABLE_MOVL : return h8300_move_length ( operands , & movl_length_table ) ; case LENGTH_TABLE_MOVA : return h8300_mova_length ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; case LENGTH_TABLE_MOVA_ZERO : return h8300_mova_length ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , const0_rtx ) ;


<s> addPass ( new InstructionSelect ( ) ) ; return false ;


<s> virtual ~ <ISA_LIT>65816Section ( ) {


<s> static bool isHReg ( unsigned Reg ) { return <STR_LIT> . contains ( Reg ) ;


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ;


<s> case LABEL_REF : case CONST_INT : case HIGH : return true ; case CONST : if ( flag_pic && pic_address_needs_scratch ( x ) ) return false ; return legitimate_constant_p ( x ) ; case SYMBOL_REF : return ! flag_pic && legitimate_constant_p ( x ) ; default : return false ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; clearResources ( ) ;


<s> GrpCount = <NUM_LIT> ; LastFPdOpCycleIdx = UINT_MAX ; LastEmittedMI = nullptr ;

LLVM_DEBUG ( CurGroupDbg = <STR_LIT> ; ) ;


<s> BTFDebug :: BTFDebug ( AsmPrinter * AP ) : DebugHandlerBase ( AP ) , OS ( * Asm -> OutStreamer ) , SkipInstruction ( false ) , LineInfoGenerated ( false ) , SecNameOff ( <NUM_LIT> ) , ArrayIndexTypeId ( <NUM_LIT> ) , MapDefNotCollected ( true ) {


<s> const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return false ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ;

return new Darwin<ISA_LIT>AsmBackend ( T , TT , CS ) ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : case <STR_LIT> : return Op ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( strlen ( sep ) + strlen ( type ) + strlen ( name ) + pos > max ) { fprintf ( file , indent ) ; return fprintf ( file , <STR_LIT> , type , name ) ;


<s> const AMDGPUOperand & Op = ( ( AMDGPUOperand & ) * Operands [ i ] ) ; if ( Op . isRegKind ( ) && Op . hasModifiers ( ) ) return true ; if ( Op . isImm ( ) && ( Op . getImmTy ( ) == AMDGPUOperand :: ImmTyOMod || Op . getImmTy ( ) == AMDGPUOperand :: ImmTyClamp ) ) return true ; } return false ;


<s> if ( mutex -> depth == <NUM_LIT> ) { mutex -> owner = <NUM_LIT> ; if ( InterlockedDecrement ( & mutex -> counter ) >= <NUM_LIT> ) return ReleaseSemaphore ( mutex -> sema , <NUM_LIT> , NULL ) ? <NUM_LIT> : <NUM_LIT> ; }


<s> Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ; for ( unsigned int i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) { AttributeItemType item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag , <NUM_LIT> ) ; switch ( item . Type ) {

case AttributeItemType :: NumericAttribute :


<s> Res = <NUM_LIT> ; std :: string Text = Tok . getString ( ) . str ( ) ; if ( Text . size ( ) > <NUM_LIT> ) { return true ; } std :: transform ( Text . begin ( ) , Text . end ( ) , Text . begin ( ) , [ ] ( unsigned char C ) { return std :: tolower ( C ) ; } ) ; for ( char Letter : Text ) { signed char Converted = hexToChar ( Letter ) ; if ( Converted == - <NUM_LIT> ) {


<s> TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beAsmBackend ) ; if ( sys :: IsLittleEndianHost ) { TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ;

TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ;


<s> static void ix86_default_align ( struct gcc_options * opts ) { if ( opts -> x_align_loops == <NUM_LIT> ) { opts -> x_align_loops = processor_target_table [ ix86_tune ] . align_loop ; align_loops_max_skip = processor_target_table [ ix86_tune ] . align_loop_max_skip ; } if ( opts -> x_align_jumps == <NUM_LIT> ) { opts -> x_align_jumps = processor_target_table [ ix86_tune ] . align_jump ; align_jumps_max_skip = processor_target_table [ ix86_tune ] . align_jump_max_skip ; } if ( opts -> x_align_functions == <NUM_LIT> ) { opts -> x_align_functions = processor_target_table [ ix86_tune ] . align_func ; }


<s> void AMDGPUDAGToDAGISel :: SelectMUBUF ( SDValue Addr , SDValue & Ptr , SDValue & VAddr , SDValue & SOffset , SDValue & Offset , SDValue & Offen , SDValue & Idxen , SDValue & Addr64 , SDValue & GLC , SDValue & SLC , SDValue & TFE ) const { SDLoc DL ( Addr ) ; GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; TFE = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N2 ; VAddr = N3 ; } else { VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; } if ( isLegalMUBUFImmOffset ( C1 ) ) { Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return ; } else if ( isUInt < <NUM_LIT> > ( C1 -> getZExtValue ( ) ) ) { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = SDValue ( CurDAG -> getMachineNode ( AMDGPU :: S_MOV_B32 , DL , <STR_LIT> , CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; VAddr = N1 ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return ; } VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> SmallVectorImpl < MachineInstr * > & getInsts ( ) {


<s> TYPE_SATURATING ( * node ) = sat_p ; TYPE_UNSIGNED ( * node ) = UNSIGNED_FIXED_POINT_MODE_P ( mode ) ; TYPE_IBIT ( * node ) = GET_MODE_IBIT ( mode ) ; TYPE_FBIT ( * node ) = GET_MODE_FBIT ( mode ) ; TYPE_PRECISION ( * node ) = GET_MODE_BITSIZE ( mode ) ;


<s> auto Op2 = MI . getOperand ( <NUM_LIT> ) ; unsigned LoadOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned StoreOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; buildMI ( MBB , MBBI , LoadOpcode ) . add ( Op1 ) . add ( Op2 ) ;

buildMI ( MBB , MBBI , ArithOpcode ) . add ( Op1 ) . add ( Op1 ) . add ( Op2 ) ;


<s> if ( reg_classes_intersect_p ( to , GENERAL_REGS ) || reg_classes_intersect_p ( from , GENERAL_REGS ) ) { reg_class_t rclass = from ; if ( ! reg_classes_intersect_p ( to , GENERAL_REGS ) ) rclass = to ; if ( rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS ) ret = ( rs6000_memory_move_cost ( mode , rclass , false ) + rs6000_memory_move_cost ( mode , GENERAL_REGS , false ) ) ; else if ( rclass == CR_REGS ) ret = <NUM_LIT> ; else if ( ( rs6000_cpu == PROCESSOR_POWER6 || rs6000_cpu == PROCESSOR_POWER7 || rs6000_cpu == PROCESSOR_POWER8 || rs6000_cpu == PROCESSOR_POWER9 ) && reg_classes_intersect_p ( rclass , LINK_OR_CTR_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; else ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; } else if ( VECTOR_MEM_VSX_P ( mode ) && reg_classes_intersect_p ( to , VSX_REGS ) && reg_classes_intersect_p ( from , VSX_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( FIRST_FPR_REGNO , mode ) ; else if ( reg_classes_intersect_p ( to , from ) ) ret = ( FLOAT128_2REG_P ( mode ) ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode , from , GENERAL_REGS ) ) ; if ( TARGET_DEBUG_COST ) { if ( dbg_cost_ctrl == <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , ret , GET_MODE_NAME ( mode ) , reg_class_names [ from ] , reg_class_names [ to ] ) ; dbg_cost_ctrl -- ; } return ret ;


<s> char pattern [ <NUM_LIT> ] ; if ( TARGET_RELAX_HINT ) snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ) ; else snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ) ;

output_asm_insn ( pattern , operands ) ;


<s> if ( itype == NT_MACRO ) { do ( void ) cpp_get_token ( pfile ) ; while ( -- idx > <NUM_LIT> ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = altivec_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __pixel_keyword ) ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; expand_bool_pixel = __pixel_keyword ; rid_code = RID_MAX ; } else if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; expand_bool_pixel = __bool_keyword ; rid_code = RID_MAX ; } else if ( ident ) rid_code = ( enum rid ) ( ident -> rid_code ) ; } if ( rid_code == RID_UNSIGNED || rid_code == RID_LONG || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || rid_code == RID_FLOAT || ( rid_code == RID_DOUBLE && TARGET_VSX ) || ( rid_code == rid_int128 ( ) && TARGET_VADDUQM ) ) { expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = altivec_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __pixel_keyword ) ) expand_bool_pixel = __pixel_keyword ; else if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_pixel = __bool_keyword ; else { do tok = cpp_peek_token ( pfile , idx ++ ) ; while ( tok -> type == CPP_PADDING ) ; ident = altivec_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __pixel_keyword ) ) expand_bool_pixel = __pixel_keyword ; else if ( ident == C_CPP_HASHNODE ( __bool_keyword ) ) expand_bool_pixel = __bool_keyword ; } }

else if ( TARGET_VADDUQM && ( ident == C_CPP_HASHNODE ( __int128_type ) || ident == C_CPP_HASHNODE ( __uint128_type ) ) ) expand_this = C_CPP_HASHNODE ( __vector_keyword ) ;


<s> PM . add ( create<ISA_LIT>BranchSelectionPass ( ) ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags Flags , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ;

return VT . bitsGT ( <STR_LIT> ) && Align % <NUM_LIT> == <NUM_LIT> ;


<s> if ( frame_pointer_needed ) mask |= <NUM_LIT> << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= <NUM_LIT> << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > <NUM_LIT> ) mask |= <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & <NUM_LIT> || thumb_force_lr_save ( ) ) mask |= ( <NUM_LIT> << LR_REGNUM ) ; if ( ( mask & <NUM_LIT> ) == <NUM_LIT> && ( ( mask & <NUM_LIT> ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( <NUM_LIT> << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= <NUM_LIT> << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= <NUM_LIT> ) { for ( reg = LAST_ARG_REGNUM + <NUM_LIT> ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( <NUM_LIT> << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= <NUM_LIT> << LAST_LO_REGNUM ; } }


<s> if ( N -> Flags & GepNode :: Root ) { Roots . push_back ( N ) ; continue ; }


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Size ) ) ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rn |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned op = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned length = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( op ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } for ( unsigned i = <NUM_LIT> ; i < length ; ++ i ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rn + i ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> bool SPRRegs = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; bool DPRRegs = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ; unsigned Binary = <NUM_LIT> ; if ( SPRRegs || DPRRegs ) { unsigned RegNo = CTX . getRegisterInfo ( ) . getEncodingValue ( Reg ) ; unsigned NumRegs = ( MI . getNumOperands ( ) - Op ) & <NUM_LIT> ; Binary |= ( RegNo & <NUM_LIT> ) << <NUM_LIT> ; if ( SPRRegs ) Binary |= NumRegs ; else Binary |= NumRegs * <NUM_LIT> ; } else { for ( unsigned I = Op , E = MI . getNumOperands ( ) ; I < E ; ++ I ) {

unsigned RegNo = CTX . getRegisterInfo ( ) . getEncodingValue ( MI . getOperand ( I ) . getReg ( ) ) ;


<s> const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; auto * EHInfo = MF . getWasmEHFuncInfo ( ) ; for ( auto & MBB : MF ) for ( auto & MI : MBB ) { if ( ! MI . isCall ( ) ) continue ; MachineOperand & CalleeOp = MI . getOperand ( <NUM_LIT> ) ; if ( ! CalleeOp . isGlobal ( ) || CalleeOp . getGlobal ( ) -> getName ( ) != <STR_LIT> ) continue ; Changed = true ; auto InsertPt = std :: next ( MachineBasicBlock :: iterator ( MI ) ) ; while ( InsertPt != MBB . end ( ) && InsertPt -> isLabel ( ) ) ++ InsertPt ; MachineInstr * Rethrow = nullptr ; if ( EHInfo -> hasThrowUnwindDest ( & MBB ) ) Rethrow = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( EHInfo -> getThrowUnwindDest ( & MBB ) ) ; else Rethrow = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; MBB . erase ( std :: next ( MachineBasicBlock :: iterator ( Rethrow ) ) , MBB . end ( ) ) ; SmallVector < MachineBasicBlock * , <NUM_LIT> > NonPadSuccessors ; for ( auto * Succ : MBB . successors ( ) ) if ( ! Succ -> isEHPad ( ) ) NonPadSuccessors . push_back ( Succ ) ; EraseBBsAndChildren ( NonPadSuccessors ) ;


<s> MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } if ( ! MemOpChains . empty ( ) ) { Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; } SDValue InFlag ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , dl , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ; assert ( G && <STR_LIT> ) ; Callee = DAG . getGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , <NUM_LIT> ) ; std :: vector < SDValue > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto & Reg : RegsToPass ) { Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; } const uint32_t * Mask ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; Mask = TRI -> getCallPreservedMask ( CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( InFlag . getNode ( ) ) { Ops . push_back ( InFlag ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag , dl ) ; if ( ! Ins . empty ( ) ) { InFlag = Chain . getValue ( <NUM_LIT> ) ; } return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , dl , DAG , InVals ) ;


<s> static bool isMOVLMask ( ArrayRef < int > Mask , EVT VT ) { if ( VT . getVectorElementType ( ) . getSizeInBits ( ) < <NUM_LIT> ) return false ; if ( ! VT . is128BitVector ( ) ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( ! isUndefOrEqual ( Mask [ <NUM_LIT> ] , NumElts ) ) return false ;

for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ;


<s> void <ISA_LIT>AsmPrinter :: printPCLabel ( const MachineInstr * MI , int OpNum , raw_ostream & O ) { int Id = ( int ) MI -> getOperand ( OpNum ) . getImm ( ) ; O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << Id ;


<s> int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned Opc ; switch ( DstTy . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; if ( isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , dl , Value , StackSlot , PseudoSourceValue :: getFixedStack ( SSFI ) , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) } ; Value = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize ) ; StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; } SDValue Ops [ ] = { Chain , Value , StackSlot } ; SDValue FIST = DAG . getNode ( Opc , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; return std :: make_pair ( FIST , StackSlot ) ;


<s> return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , isBranch , Offset , Width ) ;


<s> return LT . first * <NUM_LIT> * AmortizationCost ; } if ( Ty -> isVectorTy ( ) && Ty -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) && Ty -> getVectorNumElements ( ) < <NUM_LIT> ) { unsigned NumVecElts = Ty -> getVectorNumElements ( ) ; unsigned NumVectorizableInstsToAmortize = NumVecElts * <NUM_LIT> ; return NumVectorizableInstsToAmortize * NumVecElts * <NUM_LIT> ;


<s> CalleeFn = dyn_cast < Function > ( G -> getGlobal ( ) ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const Function * Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; const Module * M = Fn -> getParent ( ) ; const char * CalleeName = E -> getSymbol ( ) ; CalleeFn = M -> getFunction ( CalleeName ) ; } if ( ! CalleeFn ) return false ; return CalleeFn -> hasFnAttribute ( Attribute :: ReturnsTwice ) ;


<s> static bool ia64_cannot_force_const_mem ( rtx x ) {

return tls_symbolic_operand_type ( x ) != <NUM_LIT> ;


<s> return OpToFold . isFI ( ) && ( TII -> isMUBUF ( UseMI ) || TII -> isFLATScratch ( UseMI ) ) && OpNo == <STR_LIT> ( UseMI . getOpcode ( ) , <STR_LIT> :: vaddr ) ;


<s> assert ( ImageTy -> getOpcode ( ) == <STR_LIT> ) ;

ImageTypeDescriptor TD ( SampledTy , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) , ImageTy -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> if ( ! func_optimize ) func_optimize = optimization_default_node ; memset ( & func_options , <NUM_LIT> , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; cur_tree = arm_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; if ( cur_tree == NULL_TREE ) ret = false ; new_optimize = build_optimization_node ( & func_options ) ;

DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = cur_tree ;


<s> if ( Op . isImm ( ) ) { int64_t Imm = Op . getImm ( ) * <NUM_LIT> + <NUM_LIT> ; O << <STR_LIT> ; if ( Imm >= <NUM_LIT> ) O << '+' ;


<s> unsigned FP8Reg = is31 ? <STR_LIT> : <STR_LIT> ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned BPReg = HasBP ? ( unsigned ) RegInfo -> getBaseRegister ( MF ) : FPReg ; unsigned BP8Reg = HasBP ? ( unsigned ) <STR_LIT> : FPReg ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) for ( MachineBasicBlock :: iterator MBBI = BI -> end ( ) ; MBBI != BI -> begin ( ) ; ) { -- MBBI ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) continue ; switch ( MO . getReg ( ) ) { case <STR_LIT> : MO . setReg ( FPReg ) ; break ; case <STR_LIT> : MO . setReg ( FP8Reg ) ; break ; case <STR_LIT> : MO . setReg ( BPReg ) ; break ; case <STR_LIT> : MO . setReg ( BP8Reg ) ; break ;


<s> Addr . setOffsetReg ( constrainOperandRegClass ( II , Addr . getOffsetReg ( ) , II . getNumDefs ( ) + Idx + <NUM_LIT> ) ) ; if ( Addr . getOffsetReg ( ) ) { assert ( Addr . getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; bool IsSigned = Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ; MIB . addReg ( Addr . getReg ( ) ) ; MIB . addReg ( Addr . getOffsetReg ( ) ) ; MIB . addImm ( IsSigned ) ; MIB . addImm ( Addr . getShift ( ) != <NUM_LIT> ) ; } else MIB . addReg ( Addr . getReg ( ) ) . addImm ( Offset ) ; }

if ( MMO ) MIB . addMemOperand ( MMO ) ;


<s> bool hasC0VirtReg ( ) const { return C0VirtReg != <NUM_LIT> ;


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return true ; case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: Minus : case AsmToken :: Plus : if ( isParenExpr ) Result = getParser ( ) . parseParenExpression ( Res , S ) ; else Result = ( getParser ( ) . parseExpression ( Res ) ) ; while ( getLexer ( ) . getKind ( ) == AsmToken :: RParen ) Parser . Lex ( ) ;


<s> SMLoc getStartLoc ( ) const override {


<s> static DecodeStatus DecodeBranchTarget26 ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ;

Inst . addOperand ( MCOperand :: CreateImm ( BranchOffset ) ) ;


<s> case AsmToken :: Identifier : StringRef poss = Parser . getTok ( ) . getString ( ) ; if ( poss . equals_lower ( <STR_LIT> ) ) { Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; } else if ( poss . equals_lower ( <STR_LIT> ) ) { Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; } else if ( poss . equals_lower ( <STR_LIT> ) ) { Variant = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA ; } if ( Variant != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; }


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> :


<s> numRegs = MFI -> getNumRegistersForClass ( <STR_LIT> ) ; if ( numRegs > <NUM_LIT> ) { regDefs += <STR_LIT> ; regDefs += utostr ( numRegs ) ; regDefs += <STR_LIT> ; } for ( <ISA_LIT>ParamManager :: param_iterator i = PM . local_begin ( ) , e = PM . local_end ( ) ; i != e ; ++ i ) { regDefs += <STR_LIT> ; regDefs += utostr ( PM . getParamSize ( * i ) ) ; regDefs += <STR_LIT> ; regDefs += PM . getParamName ( * i ) ; regDefs += <STR_LIT> ; } OutStreamer . EmitRawText ( Twine ( regDefs ) ) ; const MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << FrameInfo -> getNumObjects ( ) << <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = FrameInfo -> getNumObjects ( ) ; i != e ; ++ i ) { DEBUG ( dbgs ( ) << <STR_LIT> << FrameInfo -> getObjectSize ( i ) << <STR_LIT> ) ; if ( FrameInfo -> getObjectSize ( i ) > <NUM_LIT> ) { std :: string def = <STR_LIT> ; def += utostr ( FrameInfo -> getObjectAlignment ( i ) ) ; def += <STR_LIT> ; def += <STR_LIT> ; def += utostr ( i ) ; def += <STR_LIT> ; def += utostr ( FrameInfo -> getObjectSize ( i ) ) ; def += <STR_LIT> ; def += <STR_LIT> ;

OutStreamer . EmitRawText ( Twine ( def ) ) ;


<s> addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) {

addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) {


<s> bool IsStrict = Op -> isStrictFPOpcode ( ) ; unsigned OpNo = IsStrict ? <NUM_LIT> : <NUM_LIT> ; SDValue Src = Op . getOperand ( OpNo ) ; SDValue Chain = IsStrict ? Op -> getOperand ( <NUM_LIT> ) : DAG . getEntryNode ( ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( SDValue Extract = vectorizeExtractedCast ( Op , DAG , Subtarget ) ) return Extract ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) return lowerINT_TO_FP_vXi64 ( Op , DAG , Subtarget ) ; return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; bool UseSSEReg = isScalarFPTypeInSSEReg ( VT ) ; if ( SrcVT == <STR_LIT> && UseSSEReg ) return Op ; if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { VT , <STR_LIT> } , { Chain , Ext } ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ext ) ;


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { SDValue Src = LHS . getOperand ( <NUM_LIT> ) ; if ( Src != RHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ;

const ConstantSDNode * CLHS = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> GenericToNVVM ( ) : ModulePass ( ID ) {


<s> return ( __m128i ) __builtin_ia32_cvtpd2uqq128_mask ( ( __v2df ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) __U ) ;


<s> DIType * Ty = dyn_cast < DIType > ( MDN ) ; generateOffsetReloc ( MI , ORSym , Ty , GVar -> getName ( ) ) ; } else if ( GVar && ! GVar -> hasInitializer ( ) && GVar -> hasExternalLinkage ( ) && GVar -> getSection ( ) == <STR_LIT> ) { MCSymbol * ORSym = OS . getContext ( ) . createTempSymbol ( ) ; OS . EmitLabel ( ORSym ) ;


<s> if ( CanDown && DU . Defs [ SR1 ] ) CanDown = false ; if ( CanUp && DU . Defs [ SR2 ] ) CanUp = false ; } if ( Failure || ( ! CanUp && ! CanDown ) ) continue ; MachineOperand * SrcT = ( MinX == CI . TrueX ) ? Src1 : Src2 ; MachineOperand * SrcF = ( MinX == CI . FalseX ) ? Src1 : Src2 ; MachineBasicBlock :: iterator At = CanDown ? Def2 : Def1 ; ML . push_back ( MuxInfo ( At , DR , PR , SrcT , SrcF , Def1 , Def2 ) ) ; } for ( MuxInfo & MX : ML ) { unsigned MxOpc = getMuxOpcode ( * MX . SrcT , * MX . SrcF ) ; if ( ! MxOpc ) continue ; MachineBasicBlock & B = * MX . At -> getParent ( ) ; const DebugLoc & DL = B . findDebugLoc ( MX . At ) ; auto NewMux = BuildMI ( B , MX . At , DL , HII -> get ( MxOpc ) , MX . DefR ) . addReg ( MX . PredR ) . add ( * MX . SrcT ) . add ( * MX . SrcF ) ; NewMux -> clearKillInfo ( ) ; B . erase ( MX . Def1 ) ; B . erase ( MX . Def2 ) ; Changed = true ; } LivePhysRegs LPR ( * HRI ) ; LPR . addLiveOuts ( B ) ; auto IsLive = [ & LPR , this ] ( unsigned Reg ) -> bool { for ( MCSubRegIterator S ( Reg , HRI , true ) ; S . isValid ( ) ; ++ S ) if ( LPR . contains ( * S ) ) return true ; return false ; } ; for ( auto I = B . rbegin ( ) , E = B . rend ( ) ; I != E ; ++ I ) { if ( I -> isDebugInstr ( ) ) continue ; for ( MachineOperand & Op : I -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; assert ( Op . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ;

bool Live = IsLive ( Op . getReg ( ) ) ;


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = count_if ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( Subtarget . hasSSE3 ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; } if ( Subtarget . hasAVX ( ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; }

if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ;


<s> void EmitByte ( unsigned char C , raw_ostream & OS ) const {


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( J -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( J -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> isBranch ( ) ) { if ( J -> isIndirectBranch ( ) ) { if ( ReturnMBB . hasAddressTaken ( ) ) OtherReference = true ; } else for ( unsigned i = <NUM_LIT> ; i < J -> getNumOperands ( ) ; ++ i ) if ( J -> getOperand ( i ) . isMBB ( ) && J -> getOperand ( i ) . getMBB ( ) == & ReturnMBB ) OtherReference = true ; } else if ( ! J -> isTerminator ( ) && ! J -> isDebugValue ( ) ) break ; if ( J == ( * PI ) -> begin ( ) ) break ; -- J ; } if ( ( * PI ) -> canFallThrough ( ) && ( * PI ) -> isLayoutSuccessor ( & ReturnMBB ) ) OtherReference = true ; if ( ! OtherReference && BlockChanged ) { PredToRemove . push_back ( * PI ) ;


<s> static bool SelectMSA3OpIntrinsic ( MachineInstr & MI , unsigned Opcode , MachineIRBuilder & MIRBuilder , const <ISA_LIT>Subtarget & ST ) { assert ( ST . hasMSA ( ) && <STR_LIT> ) ; if ( ! MIRBuilder . buildInstr ( Opcode ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . constrainAllUses ( MIRBuilder . getTII ( ) , * ST . getRegisterInfo ( ) , * ST . getRegBankInfo ( ) ) ) return false ; MI . eraseFromParent ( ) ; return true ;


<s> case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : ExtVT = Subtarget . canExtendTo512DQ ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; ExtVT = Subtarget . canExtendTo512BW ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; } V1 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; SDValue Shuffle = DAG . getVectorShuffle ( ExtVT , DL , V1 , V2 , Mask ) ; int NumElems = VT . getVectorNumElements ( ) ; if ( ( Subtarget . hasBWI ( ) && ( NumElems >= <NUM_LIT> ) ) || ( Subtarget . hasDQI ( ) && ( NumElems < <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , ExtVT ) , Shuffle , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Shuffle ) ;


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( <STR_LIT> ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForNode ( CallConv , true , isVarArg ) ) ;


<s> void printS10ImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { short value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( ( value >= - ( <NUM_LIT> << <NUM_LIT> ) && value <= ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) && <STR_LIT> ) ; O << value ;


<s> return DAG . getNode ( <STR_LIT> , dl , Ty , getZero ( dl , <STR_LIT> , DAG ) ) ; } if ( Ty . isInteger ( ) ) return DAG . getConstant ( <NUM_LIT> , dl , Ty ) ; if ( Ty . isFloatingPoint ( ) ) return DAG . getConstantFP ( <NUM_LIT> , dl , Ty ) ;


<s> bool <ISA_LIT>AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { if ( ! isInt < <NUM_LIT> > ( Value ) ) { llvm_unreachable ( <STR_LIT> ) ; }

return Value == <NUM_LIT> || ! isInt < <NUM_LIT> > ( Value ) ;


<s> const auto & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; assert ( ( flag != MachineInstr :: FrameSetup || std :: all_of ( MBB . begin ( ) , MBBI , [ ] ( MachineBasicBlock :: iterator check ) { return - <NUM_LIT> == check -> findRegisterUseOperandIdx ( PACStack :: MaskReg ) && - <NUM_LIT> == check -> findRegisterDefOperandIdx ( PACStack :: MaskReg ) && ! check -> killsRegister ( PACStack :: MaskReg ) ; } ) ) && <STR_LIT> ) ; assert ( ( flag != MachineInstr :: FrameSetup || ! MBB . isLiveIn ( PACStack :: MaskReg ) ) && <STR_LIT> ) ; ( MBBI == MBB . end ( ) ? BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ) . addReg ( PACStack :: MaskReg , RegState :: Define ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( flag ) ; ( MBBI == MBB . end ( ) ? BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ) . addReg ( PACStack :: MaskReg , RegState :: Define ) . addUse ( PACStack :: CR ) . setMIFlag ( flag ) ; ( MBBI == MBB . end ( ) ? BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( PACStack :: MaskReg ) . addImm ( <NUM_LIT> ) . setMIFlag ( flag ) ; ( MBBI == MBB . end ( ) ? BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ) . addReg ( PACStack :: MaskReg , RegState :: Define ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( flag ) ;


<s> static inline ChildIteratorType child_begin ( NodeRef N ) { return N -> G -> Edges . lower_bound ( N ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getNumberOfRegisters ( bool Vec ) const {


<s> ELFSegment * exidx_seg = elfSegmentTable ( ) . produce ( llvm :: ELF :: PT_<ISA_LIT>_EXIDX , llvm :: ELF :: PF_R ) ; exidx_seg -> append ( m_pEXIDX ) ; }


<s> unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { StackMapOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) { PatchPointOpers Opers ( & MI ) ; return Opers . getNumPatchBytes ( ) ; } else { return get ( Opcode ) . getSize ( ) ; }


<s> fprintf ( file , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < size ; i ++ ) { register int c = p [ i ] ; if ( c < <NUM_LIT> ) c += <NUM_LIT> ; fprintf ( file , <STR_LIT> , c ) ; if ( i < size - <NUM_LIT> ) putc ( ',' , file ) ;


<s> CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; MFI . setCVBytesOfCalleeSavedRegisters ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MVT VT = <STR_LIT> ; if ( <STR_LIT> . contains ( Reg ) ) VT = STI . hasBWI ( ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; unsigned Align = TRI -> getSpillAlignment ( * RC ) ; assert ( SpillSlotOffset < <NUM_LIT> && <STR_LIT> ) ; SpillSlotOffset = - alignTo ( - SpillSlotOffset , Align ) ; SpillSlotOffset -= Size ; int SlotIndex = MFI . CreateFixedSpillStackObject ( Size , SpillSlotOffset ) ;


<s> } DEBUG ( errs ( ) << <STR_LIT> ) ; return TargetTransformInfo ( BasicTTIImpl ( this , F ) ) ; } ) ;


<s> if ( reload_completed && ! frame_pointer_needed ) { ia64_compute_frame_size ( get_frame_size ( ) ) ; return ( current_frame_info . total_size == <NUM_LIT> && current_frame_info . n_spilled == <NUM_LIT> && current_frame_info . r [ reg_save_b0 ] == <NUM_LIT> && current_frame_info . r [ reg_save_pr ] == <NUM_LIT> && current_frame_info . r [ reg_save_ar_pfs ] == <NUM_LIT> && current_frame_info . r [ reg_save_ar_unat ] == <NUM_LIT> && current_frame_info . r [ reg_save_ar_lc ] == <NUM_LIT> ) ; } return <NUM_LIT> ;


return isNullConstant ( Elt ) || isNullFPConstant ( Elt ) ;


<s> MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( * Def , FI ) ) return false ; } else { return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else return false ; assert ( FI != INT_MAX ) ; if ( ! MFI . isFixedObjectIndex ( FI ) ) return false ; return Offset == MFI . getObjectOffset ( FI ) && Bytes == MFI . getObjectSize ( FI ) ;


<s> else { section * s ; char buf [ <NUM_LIT> ] ; snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE , NULL ) ; switch_to_section ( s ) ; assemble_align ( POINTER_SIZE ) ; assemble_aligned_integer ( POINTER_BYTES , symbol ) ;


<s> if ( Load1 -> getOperand ( <NUM_LIT> ) != Load2 -> getOperand ( <NUM_LIT> ) ) return false ; if ( Load1 -> getOperand ( <NUM_LIT> ) == Load2 -> getOperand ( <NUM_LIT> ) && Load1 -> getOperand ( <NUM_LIT> ) == Load2 -> getOperand ( <NUM_LIT> ) ) { if ( cast < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return false ; SDValue Op2 = Load1 -> getOperand ( <NUM_LIT> ) ; if ( ! isa < RegisterSDNode > ( Op2 ) || cast < RegisterSDNode > ( Op2 ) -> getReg ( ) != <NUM_LIT> ) return <NUM_LIT> ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( <NUM_LIT> ) ) ) {

Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ;


<s> void <ISA_LIT>GenInsert :: findRemovableRegisters ( unsigned VR , IFRecord IF , RegisterSet & RMs ) const { RegisterSet Regs [ <NUM_LIT> ] ; unsigned S = <NUM_LIT> ; Regs [ S ] . insert ( VR ) ; while ( ! Regs [ S ] . empty ( ) ) { unsigned OtherS = <NUM_LIT> - S ; Regs [ OtherS ] . clear ( ) ; for ( unsigned R = Regs [ S ] . find_first ( ) ; R ; R = Regs [ S ] . find_next ( R ) ) { Regs [ S ] . remove ( R ) ; if ( R == IF . SrcR || R == IF . InsR ) continue ;

if ( ! findNonSelfReference ( R ) ) continue ;


<s> unsigned SelectionBits = CurrentSwitchSet & R . Switch -> Value ; if ( SelectionBits && SelectionBits != R . Selection ) { if ( ErrorMessage . empty ( ) ) ErrorMessage = <STR_LIT> + Switch . str ( ) + <STR_LIT> + R . Switch -> Name . str ( ) ; continue ; } } } if ( ! IsGroup && ! Value . empty ( ) ) { if ( SwValue & CurrentSwitchSet || std :: find ( Switches . begin ( ) , Switches . end ( ) , SwPtr -> Name ) != Switches . end ( ) ) { return <STR_LIT> ; } if ( Value == <STR_LIT> ) { Switches . push_back ( SwPtr -> Name ) ; return <STR_LIT> ; } else if ( Value == <STR_LIT> ) { CurrentSwitchSet |= SwValue ; Switches . push_back ( SwPtr -> Name ) ; return <STR_LIT> ; } return <STR_LIT> ; } if ( IsGroup ) { if ( Value . empty ( ) ) return <STR_LIT> ; unsigned ItemValue ; std :: string LCValue = Value . lower ( ) ; bool Found = false ; for ( auto V : SwPtr -> Values ) if ( V . Name . equals_lower ( LCValue ) ) { ItemValue = V . Value ; Found = true ; break ; } if ( ! Found ) { if ( ! Value . getAsInteger ( <NUM_LIT> , ItemValue ) ) { unsigned Shift = <NUM_LIT> ; unsigned Mask = SwValue ; while ( Mask && ( ( Mask & <NUM_LIT> ) == <NUM_LIT> ) ) { ++ Shift ; Mask >>= <NUM_LIT> ; } ItemValue <<= Shift ; } } if ( ItemValue & ~ SwPtr -> Value ) return <STR_LIT> ; if ( ItemValue & CurrentSwitchSet ) return <STR_LIT> ; CurrentSwitchSet |= ItemValue ; Switches . push_back ( SwPtr -> Name ) ; return <STR_LIT> ; } if ( SwValue & CurrentSwitchSet ) return <STR_LIT> ; CurrentSwitchSet |= SwValue ; Switches . push_back ( SwPtr -> Name ) ; return <STR_LIT> ; } if ( IsGroup ) { for ( auto SwVal : SwPtr -> Values ) { if ( SwVal . Name . equals_lower ( Switch ) ) { assert ( SubTargetInfo ) ; if ( ! SwPtr -> fitsTargetFeatures ( SubTargetInfo -> getFeatureBits ( ) ) ) { UnsupportedCPU = SwPtr ; continue ; } if ( Type != <ISA_LIT>II :: OpType :: Invalid ) { if ( ( SwPtr -> OpType & getTypeCode ( Type ) ) == <NUM_LIT> ) { UnapplicableType = SwPtr ; continue ; } } if ( IsSuffix && ( SwPtr -> Options & OptMayBeSuffix ) == <NUM_LIT> ) return <STR_LIT> + Switch . str ( ) + <STR_LIT> ; if ( SwVal . Value & CurrentSwitchSet ) return <STR_LIT> ; CurrentSwitchSet |= SwVal . Value ; Switches . push_back ( SwPtr -> Name ) ; return <STR_LIT> ;


<s> static void nios2_handle_custom_fpu_insn_option ( int fpu_insn_index ) { int param = N2FPU_N ( fpu_insn_index ) ; if ( param >= <NUM_LIT> && param <= <NUM_LIT> ) nios2_register_custom_code ( param , CCS_FPU , fpu_insn_index ) ; else if ( param != - <NUM_LIT> ) error ( <STR_LIT> , N2FPU_NAME ( fpu_insn_index ) , param ) ;


<s> return new <ISA_LIT>PassConfig ( * this , PM ) ;


words = ( ( ( mode != BLKmode ) ? ( int ) GET_MODE_SIZE ( mode ) : int_size_in_bytes ( type ) ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;


<s> unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc ; if ( NeedAlign <= HasAlign ) StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcR , getKillRegState ( IsKill ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ;

return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD ;


<s> case IES_RPAREN : case IES_REGISTER : case IES_OFFSET : State = IES_PLUS ; IC . pushOperator ( IC_PLUS ) ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg ; } else { if ( IndexReg ) return regsUseUpError ( ErrMsg ) ; IndexReg = TmpReg ; Scale = <NUM_LIT> ; } } break ; }


<s> ValueBit ( Kind K = Variable ) : V ( SDValue ( nullptr , <NUM_LIT> ) ) , Idx ( UINT32_MAX ) , K ( K ) {


<s> for ( SmallVectorImpl < ValueType > :: const_iterator I = Objs . begin ( ) ; I != Objs . end ( ) ; ++ I ) HasHazard |= updateDefsUses ( * I , MI . mayStore ( ) ) ; return HasHazard ; } HasHazard = MI . mayStore ( ) && ( OrigSeenLoad || OrigSeenStore ) ;

HasHazard |= MI . mayLoad ( ) || OrigSeenStore ;


<s> static MachineInstr * getReturnInstr ( MachineBasicBlock * blk ) { MachineBasicBlock :: reverse_iterator iter = blk -> rbegin ( ) ; if ( iter != blk -> rend ( ) ) { MachineInstr * instr = & ( * iter ) ; if ( instr -> getOpcode ( ) == AMDGPU :: RETURN ) { return instr ; } } return NULL ;


<s> return ( Mode >> <NUM_LIT> ) & <NUM_LIT> ;


<s> Register ModSrc = stripAnySourceMods ( OrigSrc , MRI ) ; auto Const = B . buildFConstant ( S64 , BitsToDouble ( <NUM_LIT> ) ) ; Register Min = MRI . createGenericVirtualRegister ( S64 ) ; const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( MFI -> getMode ( ) . IEEE ) B . buildFMinNumIEEE ( Min , Fract , Const , Flags ) ; else B . buildFMinNum ( Min , Fract , Const , Flags ) ; Register CorrectedFract = Min ; if ( ! MI . getFlag ( MachineInstr :: FmNoNans ) ) { auto IsNan = B . buildFCmp ( CmpInst :: FCMP_ORD , S1 , ModSrc , ModSrc , Flags ) ; CorrectedFract = B . buildSelect ( S64 , IsNan , ModSrc , Min , Flags ) . getReg ( <NUM_LIT> ) ; } auto NegFract = B . buildFNeg ( S64 , CorrectedFract , Flags ) ;

B . buildFAdd ( Dst , OrigSrc , NegFract , Flags ) ;


<s> ptr -> x_ix86_dump_tunes = opts -> x_ix86_dump_tunes ; ptr -> x_ix86_force_align_arg_pointer = opts -> x_ix86_force_align_arg_pointer ; ptr -> x_ix86_force_drap = opts -> x_ix86_force_drap ; ptr -> x_ix86_incoming_stack_boundary_arg = opts -> x_ix86_incoming_stack_boundary_arg ; ptr -> x_ix86_pmode = opts -> x_ix86_pmode ; ptr -> x_ix86_preferred_stack_boundary_arg = opts -> x_ix86_preferred_stack_boundary_arg ; ptr -> x_ix86_recip_name = opts -> x_ix86_recip_name ; ptr -> x_ix86_regparm = opts -> x_ix86_regparm ; ptr -> x_ix86_section_threshold = opts -> x_ix86_section_threshold ; ptr -> x_ix86_sse2avx = opts -> x_ix86_sse2avx ; ptr -> x_ix86_stack_protector_guard = opts -> x_ix86_stack_protector_guard ; ptr -> x_ix86_stringop_alg = opts -> x_ix86_stringop_alg ; ptr -> x_ix86_tls_dialect = opts -> x_ix86_tls_dialect ; ptr -> x_ix86_tune_ctrl_string = opts -> x_ix86_tune_ctrl_string ; ptr -> x_ix86_tune_memcpy_strategy = opts -> x_ix86_tune_memcpy_strategy ; ptr -> x_ix86_tune_memset_strategy = opts -> x_ix86_tune_memset_strategy ; ptr -> x_ix86_tune_no_default = opts -> x_ix86_tune_no_default ; ptr -> x_ix86_veclibabi_type = opts -> x_ix86_veclibabi_type ; gcc_assert ( ptr -> arch == ix86_arch ) ;

gcc_assert ( ptr -> schedule == ix86_schedule ) ;


<s> if ( cc1 == <STR_LIT> || cc1 == <STR_LIT> ) { <STR_LIT> tmp = cc0 ; cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; <STR_LIT> NTOperator = is64BitFP ? <STR_LIT> : <STR_LIT> ; unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; SDValue OnesOrZeroesF = DAG . getNode ( NTOperator , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , <STR_LIT> ) ) ; SDValue OnesOrZeroesI = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue ANDed = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesI , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;

SDValue OneBitOfTruth = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ANDed ) ;


<s> operands [ <NUM_LIT> ] = NULL ; operands [ <NUM_LIT> ] = XEXP ( x , <NUM_LIT> ) ; return compute_a_shift_length ( operands , GET_CODE ( x ) ) / <NUM_LIT> ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; bool UseImm = false ; if ( const auto * CFP = dyn_cast < ConstantFP > ( RHS ) ) if ( CFP -> isZero ( ) && ! CFP -> isNegative ( ) ) UseImm = true ; Register LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return false ; if ( UseImm ) { unsigned Opc = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( LHSReg ) ; return true ; }

Register RHSReg = getRegForValue ( RHS ) ;


<s> unsigned getShiftedImmShift ( ) const { assert ( Kind == k_ShiftedImm && <STR_LIT> ) ;


<s> bool avoidQuadLdStPairs ( ) const { return AvoidQuadLdStPairs ;


<s> <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , std :: move ( TAB ) , OS , std :: move ( Emitter ) ) ;

if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ;


<s> State . PrefixSaved = <NUM_LIT> ; State . PrefixPass = false ;


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) { return createELFStreamer ( Context , std :: move ( MAB ) , OS , std :: move ( Emitter ) , RelaxAll ) ;


<s> return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> else lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; return DAG . getMergeValues ( Ops , <NUM_LIT> , DL ) ;


<s> uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

SDValue ArgN = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , MFI -> getVarargBufferVreg ( ) , PtrVT ) ;


<s> case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; Offset = <NUM_LIT> ; Stride = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOpnd = <NUM_LIT> ; NumRegs = <NUM_LIT> ; return true ; case <STR_LIT> :


<s> uint64_t <ISA_LIT>FrameLowering :: getBasePointerSaveOffset ( ) const {


<s> if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size - STACK_CHECK_PROTECT ) ; } else if ( size > <NUM_LIT> ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == <NUM_LIT> ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= <NUM_LIT> && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;


<s> SeparatorString = <STR_LIT> ; CommentColumn = <NUM_LIT> ; CommentString = <STR_LIT> ; LabelSuffix = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; LinkerPrivateGlobalPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; AssemblerDialect = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; Data8bitsDirective = <STR_LIT> ;


<s> return __builtin_loongson_psubd_u ( s , t ) ;


<s> Register DstReg = Dst . getReg ( ) ; unsigned Size = RBI . getSizeInBits ( DstReg , * MRI , TRI ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; if ( DstRB -> getID ( ) == <STR_LIT> ) { const TargetRegisterClass * RC = TRI . getBoolRC ( ) ; unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , RC == & <STR_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; if ( Src0 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src0 . getReg ( ) ) ) MRI -> setRegClass ( Src0 . getReg ( ) , RC ) ; if ( Src1 . isUndef ( ) && ! MRI -> getRegClassOrNull ( Src1 . getReg ( ) ) ) MRI -> setRegClass ( Src1 . getReg ( ) , RC ) ; return RBI . constrainGenericRegister ( DstReg , * RC , * MRI ) ; } if ( DstRB -> getID ( ) == <STR_LIT> ) { unsigned InstOpc = getLogicalBitOpcode ( I . getOpcode ( ) , Size > <NUM_LIT> ) ; I . setDesc ( TII . get ( InstOpc ) ) ; I . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , true , true , false , true ) ) ;

return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ;


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_LO16 : OS << <STR_LIT> ; break ; } SRE -> getSymbol ( ) . print ( OS , MAI ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ;


<s> BBInfo [ CPEBB -> getNumber ( ) ] . Size -= Size ; if ( CPEBB -> empty ( ) ) { BBInfo [ CPEBB -> getNumber ( ) ] . Size = <NUM_LIT> ; CPEBB -> setLogAlignment ( <NUM_LIT> ) ;

} else CPEBB -> setLogAlignment ( getCPELogAlign ( * CPEBB -> begin ( ) ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerThreadPointer ( const SDLoc & DL , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue TPHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted , TPLo ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else { SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; }

const MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ;


<s> getDirectBrEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {

const MCOperand & MO = MI . getOperand ( OpNo ) ;


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( Register :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( Register :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { succ0 = next_real_insn ( insn ) ; if ( arc_hazard ( insn , succ0 ) ) { emit_insn_before ( gen_nopv ( ) , succ0 ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) {


<s> auto It = EvexToVex256Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex256Table . end ( ) ) NewOpc = It -> second ; } else if ( IsEVEX_V128 ) { auto It = EvexToVex128Table . find ( MI . getOpcode ( ) ) ; if ( It != EvexToVex128Table . end ( ) ) NewOpc = It -> second ; } if ( ! NewOpc ) return false ; auto isHiRegIdx = [ ] ( unsigned Reg ) { if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return true ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return true ; return false ; } ; for ( const MachineOperand & MO : MI . explicit_operands ( ) ) {


<s> static bool rs6000_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type ) ;


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I8 : RTLIB :: UREM_I8 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I16 : RTLIB :: UREM_I16 ;

else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I32 : RTLIB :: UREM_I32 ;


<s> bool AllowFusion = ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ; if ( ! AllowFusion ) return false ; Opnd2 = Opnd1 ; Opnd1 = Opnd0 . getOperand ( <NUM_LIT> ) ; Opnd0 = Opnd0 . getOperand ( <NUM_LIT> ) ; return true ;


<s> auto Res = llvm :: make_unique < <ISA_LIT>Operand > ( Token ) ; Res -> Tok . Data = Str . data ( ) ; Res -> Tok . Length = Str . size ( ) ;


<s> case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } SmallVector < SDValue , <NUM_LIT> > Ops ; for ( const SDValue & V : PN -> ops ( ) ) { if ( ! ToPromote . count ( V . getNode ( ) ) && V . getValueType ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V ) ) { SDValue ReplOpOps [ ] = { ISR . getOperand ( <NUM_LIT> ) , V , ISR . getOperand ( <NUM_LIT> ) } ; SDNode * ReplOp = CurDAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , SDLoc ( V ) , ISR . getNode ( ) -> getVTList ( ) , ReplOpOps ) ; Ops . push_back ( SDValue ( ReplOp , <NUM_LIT> ) ) ; } else { Ops . push_back ( V ) ; } } SmallVector < EVT , <NUM_LIT> > NewVTs ; SDVTList VTs = PN -> getVTList ( ) ; for ( unsigned i = <NUM_LIT> , ie = VTs . NumVTs ; i != ie ; ++ i ) if ( VTs . VTs [ i ] == <STR_LIT> ) NewVTs . push_back ( <STR_LIT> ) ; else NewVTs . push_back ( VTs . VTs [ i ] ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( PN -> dump ( CurDAG ) ) ; CurDAG -> SelectNodeTo ( PN , NewOpcode , CurDAG -> getVTList ( NewVTs ) , Ops ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( PN -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( N -> dump ( CurDAG ) ) ;


<s> ls = emit_conditional_move ( ls , NE , op , const0_rtx , Pmode , ls , const0_rtx , Pmode , <NUM_LIT> ) ; emit_insn ( gen_subsi3 ( result , op , ls ) ) ; return result ; } else if ( to_as == ADDR_SPACE_EA && from_as == ADDR_SPACE_GENERIC ) { rtx result , ls ; ls = gen_const_mem ( DImode , gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ) ; set_mem_align ( ls , <NUM_LIT> ) ; result = gen_reg_rtx ( EAmode ) ; ls = force_reg ( EAmode , convert_modes ( EAmode , DImode , ls , <NUM_LIT> ) ) ; op = force_reg ( Pmode , op ) ; ls = emit_conditional_move ( ls , NE , op , const0_rtx , Pmode , ls , const0_rtx , EAmode , <NUM_LIT> ) ; op = force_reg ( EAmode , convert_modes ( EAmode , Pmode , op , <NUM_LIT> ) ) ; if ( EAmode == SImode ) emit_insn ( gen_addsi3 ( result , op , ls ) ) ; else emit_insn ( gen_adddi3 ( result , op , ls ) ) ; return result ; } else gcc_unreachable ( ) ;


<s> SmallVector < Type * , <NUM_LIT> > Types ; for ( const Value * Op : Args ) { Type * OpTy = Op -> getType ( ) ; assert ( VF == <NUM_LIT> || ! OpTy -> isVectorTy ( ) ) ; Types . push_back ( VF == <NUM_LIT> ? OpTy : FixedVectorType :: get ( OpTy , VF ) ) ; } if ( VF > <NUM_LIT> && ! RetTy -> isVoidTy ( ) ) RetTy = FixedVectorType :: get ( RetTy , VF ) ; unsigned ScalarizationCost = std :: numeric_limits < unsigned > :: max ( ) ; if ( RetVF > <NUM_LIT> || VF > <NUM_LIT> ) { ScalarizationCost = <NUM_LIT> ; if ( ! RetTy -> isVoidTy ( ) ) ScalarizationCost += getScalarizationOverhead ( cast < VectorType > ( RetTy ) , true , false ) ; ScalarizationCost += getOperandsScalarizationOverhead ( Args , VF ) ; } IntrinsicCostAttributes Attrs ( ICA . getID ( ) , RetTy , Types , FMF , ScalarizationCost , I ) ; return getIntrinsicInstrCost ( Attrs , CostKind ) ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; unsigned NElts = LT . second . isVector ( ) ? LT . second . getVectorNumElements ( ) : <NUM_LIT> ; <STR_LIT> SLT = LT . second . getScalarType ( ) . SimpleTy ; if ( SLT == <STR_LIT> ) return LT . first * NElts * get64BitInstrCost ( CostKind ) ; if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> ) NElts = ( NElts + <NUM_LIT> ) / <NUM_LIT> ; unsigned InstRate = getQuarterRateInstrCost ( CostKind ) ;


<s> TargetLoweringObjectFileMachO :: Initialize ( Ctx , TM ) ;

LSDASection = getMachOSection ( <STR_LIT> , <STR_LIT> , <NUM_LIT> , SectionKind :: getReadOnlyWithRel ( ) ) ;


<s> static bool rs6000_output_addr_const_extra ( FILE * file , rtx x ) { if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_TOCREL :

gcc_checking_assert ( GET_CODE ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == SYMBOL_REF && REG_P ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) && REGNO ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == TOC_REGISTER ) ;


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Uses . count ( DstReg ) || Defs . count ( SrcReg ) ) return false ; MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugValue ( ) ) ++ I ;


<s> unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ;

addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ArgumentMove ( ) { return new <ISA_LIT>ArgumentMove ( ) ;


<s> const TargetRegisterClass * R600InstrInfo :: getIndirectAddrStoreRegClass ( unsigned SourceReg ) const { return & AMDGPU :: R600_TReg32RegClass ;


<s> void setPrintedStatus ( bool status ) { SectionPrinted = status ;


<s> for ( unsigned i = <NUM_LIT> ; i < Priv -> Subscopes . size ( ) ; i ++ ) { delete Priv -> Subscopes [ i ] ;


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : { SDValue AR_PFSVal , Copy ; switch ( Op . getNumOperands ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; abort ( ) ; case <NUM_LIT> : AR_PFSVal = DAG . getCopyFromReg ( Op . getOperand ( <NUM_LIT> ) , dl , VirtGPR , <STR_LIT> ) ; AR_PFSVal = DAG . getCopyToReg ( AR_PFSVal . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , AR_PFSVal ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AR_PFSVal ) ; case <NUM_LIT> : { MVT ArgVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned ArgReg = ArgVT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; AR_PFSVal = DAG . getCopyFromReg ( Op . getOperand ( <NUM_LIT> ) , dl , VirtGPR , <STR_LIT> ) ; Copy = DAG . getCopyToReg ( AR_PFSVal . getValue ( <NUM_LIT> ) , dl , ArgReg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; AR_PFSVal = DAG . getCopyToReg ( Copy . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , AR_PFSVal , Copy . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AR_PFSVal , AR_PFSVal . getValue ( <NUM_LIT> ) ) ; } } return SDValue ( ) ;


<s> BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && ( ! TT . isOSAIX ( ) || STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char L = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! L || L == <NUM_LIT> || L == <NUM_LIT> || L == <NUM_LIT> || L == <NUM_LIT> ) { O << <STR_LIT> ; if ( L != <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; if ( L == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , STI , O ) ; printAnnotation ( O , Annot ) ; return ; } }

if ( ! printAliasInstr ( MI , Address , STI , O ) ) printInstruction ( MI , Address , STI , O ) ;


<s> bool isSImm12Lsb0 ( ) const { return isBareSimmNLsb0 < <NUM_LIT> > ( ) ;


<s> static bool arm_macro_fusion_p ( void ) {


<s> return getNumCoveredRegs ( getSubRegIndexLaneMask ( SubReg ) ) ;


<s> rtx op0 = frv_read_argument ( call , <NUM_LIT> ) ; rtx op1 = frv_read_argument ( call , <NUM_LIT> ) ; target = frv_legitimize_target ( icode , target ) ; op0 = frv_legitimize_argument ( icode , <NUM_LIT> , op0 ) ; op1 = frv_legitimize_argument ( icode , <NUM_LIT> , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCExpr * Expr = getImm ( ) ;


<s> break ; case <STR_LIT> : InnerEndSymbol = MI -> getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; break ; default : break ; } if ( InnerEndSymbol && InnerEndSymbol == MI -> getPreInstrSymbol ( ) ) { InnerHwlpEndOffset = Offset ; } unsigned Size = TII -> getInstSizeInBytes ( * MI ) ; if ( Size == <NUM_LIT> ) { Size = <NUM_LIT> ; } Offset += Size ; MachineInstr * Next = MI -> getNextNode ( ) ; if ( ! Next ) { Next = & MI -> getParent ( ) -> getNextNode ( ) -> front ( ) ; } MI = Next ; } assert ( isUInt < <NUM_LIT> > ( StartOffset ) && <STR_LIT> ) ; assert ( isUInt < <NUM_LIT> > ( EndOffset ) && <STR_LIT> ) ; MCSymbol * LastInstrSymbol = LastInstr -> getPreInstrSymbol ( ) ; if ( ! LastInstrSymbol ) { LastInstrSymbol = MF . getContext ( ) . createLinkerPrivateTempSymbol ( ) ; LastInstr -> setPreInstrSymbol ( MF , LastInstrSymbol ) ; } DebugLoc DL = HwlpSetup -> getDebugLoc ( ) ; int64_t LoopNum = Changed ? <NUM_LIT> : <NUM_LIT> ; if ( HwlpSetup -> getOpcode ( ) == <STR_LIT> ) { Register count = HwlpSetup -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( StartOffset == <NUM_LIT> ) { BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addReg ( count ) . addSym ( LastInstrSymbol ) ; } else { BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addReg ( count ) ; BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addMBB ( LoopHeader ) ; BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addSym ( LastInstrSymbol ) ; } } else { int64_t count = HwlpSetup -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( StartOffset == <NUM_LIT> && EndOffset < <NUM_LIT> ) { BuildMI ( * Preheader , HwlpSetup , DL , TII -> get ( <STR_LIT> ) ) . addImm ( LoopNum ) . addImm ( count ) . addSym ( LastInstrSymbol ) ;


<s> assert ( ( Kind == k_MemoryRegImmImm || Kind == k_MemoryZeroImmImm ) && <STR_LIT> ) ; return Mem . Index ;


<s> MCAsmParserExtension :: Initialize ( parser ) ;

setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ;


<s> bool s390_logical_operator_ok_p ( rtx * operands ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) return rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || ( ! reload_completed && rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( ! IdVal ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; std :: unique_ptr < <ISA_LIT>Operand > op ( static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) . release ( ) ) ) ; Operands . pop_back ( ) ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( IdVal ) ) { int64_t Imm ;

if ( IdVal -> EvaluateAsAbsolute ( Imm ) ) IdVal = MCConstantExpr :: Create ( Imm , getContext ( ) ) ;


<s> <ISA_LIT>Operand :: Ptr <ISA_LIT>AsmParser :: defaultSMEMOffset ( ) const { return <ISA_LIT>Operand :: CreateImm ( this , <NUM_LIT> , SMLoc ( ) , <ISA_LIT>Operand :: ImmTyOffset ) ;


<s> bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ;

MI . setDesc ( TII -> get ( getConcreteOpcode ( MI . getOpcode ( ) ) ) ) ;


<s> virtual unsigned GPR2AlignEncode ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const {


<s> NumVGPR ( <NUM_LIT> ) , NumSGPR ( <NUM_LIT> ) , Priority ( <NUM_LIT> ) , FloatMode ( <NUM_LIT> ) , Priv ( <NUM_LIT> ) , DX10Clamp ( <NUM_LIT> ) , DebugMode ( <NUM_LIT> ) , IEEEMode ( <NUM_LIT> ) , ScratchSize ( <NUM_LIT> ) , FlatUsed ( false ) , VCCUsed ( false ) , CodeLen ( <NUM_LIT> ) {


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned Res = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ;

assert ( ( Res & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> return gen_call_visitor { l , Args } ;


<s>
OS
<<
<STR_LIT>
;
uint64_t
Mask
=
<NUM_LIT>
;
for
(
unsigned
i
=
<NUM_LIT>
;
i
<
(
sizeof
(
ErrorInfo
)
*
<NUM_LIT>
<NUM_LIT>
)
;
++
i
)
{
if
(
ErrorInfo
&
Mask
)
OS
<<
' '
<<
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
Mask
<<=
<NUM_LIT>
;


<s> static bool isPALIGNRMask ( ArrayRef < int > Mask , MVT VT , const <ISA_LIT>Subtarget * Subtarget ) { if ( ( VT . is128BitVector ( ) && ! Subtarget -> hasSSSE3 ( ) ) || ( VT . is256BitVector ( ) && ! Subtarget -> hasInt256 ( ) ) || VT . is512BitVector ( ) ) return false ;

return isAlignrMask ( Mask , VT , false ) ;


<s> void emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const override {


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ;


uint32_t Inst = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> bool isGOTPLDpc ( MachineInstr & Instr ) { if ( Instr . getOpcode ( ) != <STR_LIT> ) return false ;

const MachineOperand & LoadedAddressReg = Instr . getOperand ( <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { auto * N = cast < JumpTableSDNode > ( Op ) ; SDValue GA = DAG . getTargetJumpTable ( N -> getIndex ( ) , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , GA ) ;


<s> assert ( Kind == Memory && <STR_LIT> ) ;


<s> MCRelocationInfo * llvm :: create<ISA_LIT>_64MachORelocationInfo ( MCContext & Ctx ) {

return new <ISA_LIT>_64MachORelocationInfo ( Ctx ) ;


<s> emitARM64WinUnwindCode ( Win64EH :: UOP_SaveFPLR , - <NUM_LIT> , Offset ) ;


<s> struct auxv { long a_type ; long a_val ; } * auxp ; argc = __libc_stack_end [ <NUM_LIT> ] ; argv = ( char * * ) __libc_stack_end + <NUM_LIT> ; envp = argv + argc + <NUM_LIT> ; while ( * envp ++ ) continue ; for ( auxp = ( struct auxv * ) envp ; auxp -> a_type != <NUM_LIT> ; ++ auxp ) if ( auxp -> a_type == which ) return auxp -> a_val ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ! MFI . hasCalls ( ) && ! MRI . isPhysRegUsed ( <STR_LIT> ) && ! MRI . isPhysRegUsed ( <STR_LIT> ) && ! hasFP ( MF ) ;


<s> parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures ( ) ) ) ; AssemblerOptions . push_back ( make_unique < <ISA_LIT>AssemblerOptions > ( getAvailableFeatures ( ) ) ) ;

getTargetStreamer ( ) . updateABIInfo ( * this ) ;


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ReplaceBITCASTResults ( N , Results , DAG ) ; return ; case <STR_LIT> : case <STR_LIT> :

assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; default : return false ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( TrueReg ) . addReg ( FalseReg ) . addReg ( CondReg ) ; updateValueMap ( Select , ResultReg ) ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) { pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; } seh_cfa_adjust_cfa ( asm_out_file , seh , pat ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = single_set ( insn ) ; seh_cfa_offset ( asm_out_file , seh , pat ) ; handled_one = true ; break ; default :


<s> } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; }


selectVSplatUimm5 ( SDValue N , SDValue & Imm ) const {


<s> Addr . setReg ( Reg ) ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { auto * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } if ( int64_t ( TmpOffset ) >= <NUM_LIT> ) { Addr . setOffset ( TmpOffset ) ; if ( computeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; } Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const auto * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { if ( Addr . isSet ( ) ) { return false ; } Addr . setKind ( Address :: FrameIndexBase ) ; Addr . setFI ( SI -> second ) ; return true ; } break ; } case Instruction :: Add : { const Value * LHS = U -> getOperand ( <NUM_LIT> ) ; const Value * RHS = U -> getOperand ( <NUM_LIT> ) ; if ( isa < ConstantInt > ( LHS ) ) std :: swap ( LHS , RHS ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( RHS ) ) { uint64_t TmpOffset = Addr . getOffset ( ) + CI -> getSExtValue ( ) ; if ( int64_t ( TmpOffset ) >= <NUM_LIT> ) { Addr . setOffset ( TmpOffset ) ; return computeAddress ( LHS , Addr ) ; } } Address Backup = Addr ; if ( computeAddress ( LHS , Addr ) && computeAddress ( RHS , Addr ) ) return true ; Addr = Backup ; break ; } case Instruction :: Sub : { const Value * LHS = U -> getOperand ( <NUM_LIT> ) ; const Value * RHS = U -> getOperand ( <NUM_LIT> ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( RHS ) ) { int64_t TmpOffset = Addr . getOffset ( ) - CI -> getSExtValue ( ) ; if ( TmpOffset >= <NUM_LIT> ) { Addr . setOffset ( TmpOffset ) ; return computeAddress ( LHS , Addr ) ; } } break ; } }


<s> assert ( MBBI != MBB . begin ( ) && <STR_LIT> ) ; assert ( std :: prev ( MBBI ) -> isBarrier ( ) && <STR_LIT> <STR_LIT> ) ; assert ( std :: prev ( MBBI ) -> isTerminator ( ) && <STR_LIT> ) ;

const TargetInstrInfo * TII = ST -> getInstrInfo ( ) ;


<s> const struct d_target_info_spec handlers [ ] = {

{ <STR_LIT> , pa_d_handle_target_float_abi } , { <STR_LIT> , pa_d_handle_target_object_format } , { NULL , NULL } , } ;


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( RegNo ) && <STR_LIT> ) ;


<s> continue ; } if ( I -> getOpcode ( ) != <STR_LIT> ) return false ; auto * Idx = dyn_cast < ConstantSDNode > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Idx ) return false ; SDValue Src = I -> getOperand ( <NUM_LIT> ) ; DenseMap < SDValue , APInt > :: iterator M = SrcOpMap . find ( Src ) ; if ( M == SrcOpMap . end ( ) ) { VT = Src . getValueType ( ) ; if ( ! SrcOpMap . empty ( ) && VT != SrcOpMap . begin ( ) -> first . getValueType ( ) ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ;

APInt EltCount = APInt :: getZero ( NumElts ) ;


<s> Modified |= fixupFPReturnAndCall ( * F , & M , Subtarget ) ; FPParamVariant V = whichFPParamVariantNeeded ( * F ) ; if ( V != NoSig ) { Modified = true ; createFPFnStub ( F , & M , V , Subtarget ) ;


<s> assert ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> ) ; assert ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> hsa_fns . hsa_region_get_info_fn ( region , HSA_REGION_INFO_SEGMENT , & segment ) ; if ( HSA_REGION_SEGMENT_GLOBAL != segment ) return HSA_STATUS_SUCCESS ; hsa_region_global_flag_t flags ; hsa_fns . hsa_region_get_info_fn ( region , HSA_REGION_INFO_GLOBAL_FLAGS , & flags ) ; if ( flags & HSA_REGION_GLOBAL_FLAG_KERNARG ) { kernargs_region = region ; return HSA_STATUS_INFO_BREAK ;


<s> if ( IsExtended ) return false ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: minConstant ( MI , <NUM_LIT> ) <= <NUM_LIT> && <ISA_LIT>MCInstrInfo :: minConstant ( MI , <NUM_LIT> ) >= <NUM_LIT> && <ISA_LIT>MCInstrInfo :: isIntRegForSubInst ( DstReg ) ) return <STR_LIT> ; break ; case <STR_LIT> : if ( IsExtended ) return false ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( <STR_LIT> == DstReg || <STR_LIT> == DstReg ) && <ISA_LIT>MCInstrInfo :: isIntRegForSubInst ( Src1Reg ) && <ISA_LIT>MCInstrInfo :: minConstant ( MI , <NUM_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Src1Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> == Src1Reg || <STR_LIT> == Src1Reg ) return <STR_LIT> ;


<s> const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; const RegisterBank * DstBank = OpdMapper . getInstrMapping ( ) . getOperandMapping ( <NUM_LIT> ) . BreakDown [ <NUM_LIT> ] . RegBank ; if ( DstBank == & <STR_LIT> ) { if ( Ty == S32 ) return true ; return false ; } Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OffsetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register WidthReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; ApplyRegBankMapping ApplyBank ( * this , MRI , & <STR_LIT> ) ; GISelObserverWrapper Observer ( & ApplyBank ) ; MachineIRBuilder B ( MI ) ; B . setChangeObserver ( Observer ) ; auto OffsetMask = B . buildConstant ( S32 , maskTrailingOnes < unsigned > ( <NUM_LIT> ) ) ;

auto ClampOffset = B . buildAnd ( S32 , OffsetReg , OffsetMask ) ;


<s> switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; if ( AM . BaseOffs && ! ( Subtarget -> getFeatureBits ( ) [ <STR_LIT> ] && AddrSpace == LOCAL_VECTOR ) ) return false ; break ; case <NUM_LIT> :

if ( AM . HasBaseReg || AM . BaseOffs ) return false ;


<s> void <ISA_LIT>RepoMCAsmInfo :: anchor ( ) {


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> MachineBasicBlock * MBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ;

if ( MBB == MI . getParent ( ) -> getNextNode ( ) ) MI . eraseFromParent ( ) ;


<s> void AMDGPUInstPrinter :: printDSOffset ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { uint16_t Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm != <NUM_LIT> ) { O << <STR_LIT> ; printU16ImmDecOperand ( MI , OpNo , O ) ;


<s> fix = minipool_fix_head ; while ( fix ) { Mfix * ftmp ; Mfix * fdel ; Mfix * last_added_fix ; Mfix * last_barrier = NULL ; Mfix * this_fix ; while ( fix && BARRIER_P ( fix -> insn ) ) fix = fix -> next ; if ( fix == NULL ) break ; last_added_fix = NULL ; for ( ftmp = fix ; ftmp ; ftmp = ftmp -> next ) { if ( BARRIER_P ( ftmp -> insn ) ) { if ( ftmp -> address >= minipool_vector_head -> max_address ) break ; last_barrier = ftmp ; } else if ( ( ftmp -> minipool = add_minipool_forward_ref ( ftmp ) ) == NULL ) break ; last_added_fix = ftmp ; } if ( last_barrier != NULL ) { for ( fdel = last_barrier -> next ; fdel && fdel != ftmp ; fdel = fdel -> next ) { fdel -> minipool -> refcount -- ; fdel -> minipool = NULL ; } ftmp = last_barrier ; } else { HOST_WIDE_INT max_address ; gcc_assert ( ftmp ) ; max_address = minipool_vector_head -> max_address ; if ( ftmp -> address < max_address ) max_address = ftmp -> address + <NUM_LIT> ; last_barrier = create_fix_barrier ( last_added_fix , max_address ) ; } assign_minipool_offsets ( last_barrier ) ;


<s> return std :: make_unique < ExportClustering > ( ) ;


<s> bool supportsPackedMode ( unsigned Opcode , EVT IdiomVT ) { bool IsPackedOp = isPackedVectorType ( IdiomVT ) ; bool IsMaskOp = isMaskType ( IdiomVT ) ; switch ( Opcode ) { default : return false ; case <STR_LIT> : return true ; return IsPackedOp && ! IsMaskOp ; }