<s> if ( ( ( Offset < <NUM_LIT> ) || ( Offset & ( ScaleFactor - <NUM_LIT> ) ) ) && ! isInt < <NUM_LIT> > ( Offset ) ) ImmediateOffsetNeedsLowering = true ; else if ( Offset > <NUM_LIT> && ! ( Offset & ( ScaleFactor - <NUM_LIT> ) ) && ! isUInt < <NUM_LIT> > ( Offset / ScaleFactor ) ) ImmediateOffsetNeedsLowering = true ; if ( ! ImmediateOffsetNeedsLowering && Addr . getOffset ( ) && Addr . getOffsetReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( Addr . isRegBase ( ) && Addr . getOffsetReg ( ) && ! Addr . getReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( ( ImmediateOffsetNeedsLowering || Addr . getOffsetReg ( ) ) && Addr . isFIBase ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . getFI ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( ResultReg ) ; } if ( RegisterOffsetNeedsLowering ) { unsigned ResultReg = <NUM_LIT> ; if ( Addr . getReg ( ) ) { if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitAddSub_rx ( true , <STR_LIT> , Addr . getReg ( ) , Addr . getOffsetReg ( ) , Addr . getExtendType ( ) , Addr . getShift ( ) ) ; else ResultReg = emitAddSub_rs ( true , <STR_LIT> , Addr . getReg ( ) , Addr . getOffsetReg ( ) , <STR_LIT> , Addr . getShift ( ) ) ; } else { if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , Addr . getShift ( ) , true ) ; else if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , Addr . getShift ( ) , false ) ; else ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , Addr . getShift ( ) ) ; } if ( ! ResultReg ) return false ; Addr . setReg ( ResultReg ) ; Addr . setOffsetReg ( <NUM_LIT> ) ; Addr . setShift ( <NUM_LIT> ) ; Addr . setExtendType ( <STR_LIT> ) ; }


<s> JTI -> Initialize ( MF , IsPIC ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ;

for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ;


<s> if ( df_regs_ever_live_p ( TILEGX_LINK_REGNUM ) || crtl -> calls_eh_return ) FRP ( frame_emit_store ( TILEGX_LINK_REGNUM , TILEGX_LINK_REGNUM , stack_pointer_rtx , stack_pointer_rtx , <NUM_LIT> ) ) ; if ( total_size == <NUM_LIT> ) { if ( flag_pic && crtl -> uses_pic_offset_table ) load_pic_register ( false ) ; return ; } cfa = stack_pointer_rtx ; if ( frame_pointer_needed ) { fp_copy_regno = next_scratch_regno -- ; insn = FRP ( emit_move_insn ( gen_rtx_REG ( word_mode , fp_copy_regno ) , gen_lowpart ( word_mode , hard_frame_pointer_rtx ) ) ) ; add_reg_note ( insn , REG_CFA_REGISTER , NULL_RTX ) ; insn = FRP ( emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , hard_frame_pointer_rtx ) ; cfa = hard_frame_pointer_rtx ; REGNO_POINTER_ALIGN ( HARD_FRAME_POINTER_REGNUM ) = STACK_BOUNDARY ; sp_copy_regno = HARD_FRAME_POINTER_REGNUM ; } else if ( ! tilegx_current_function_is_leaf ( ) ) { sp_copy_regno = next_scratch_regno -- ; emit_move_insn ( gen_rtx_REG ( Pmode , sp_copy_regno ) , stack_pointer_rtx ) ; } if ( tilegx_current_function_is_leaf ( ) ) { emit_sp_adjust ( - total_size , & next_scratch_regno , ! frame_pointer_needed , NULL_RTX ) ; } else { rtx chain_addr = gen_rtx_REG ( Pmode , next_scratch_regno -- ) ; rtx size_rtx = GEN_INT ( - ( total_size - UNITS_PER_WORD ) ) ; if ( add_operand ( size_rtx , Pmode ) ) { rtx p = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , size_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , chain_addr , p ) ) ; emit_sp_adjust ( - total_size , & next_scratch_regno , ! frame_pointer_needed , NULL_RTX ) ;


<s> MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else { LoLoop . Start = ExpandLoopStart ( LoLoop ) ; RemoveDeadBranch ( LoLoop . Start ) ; LoLoop . End = ExpandLoopEnd ( LoLoop ) ; RemoveDeadBranch ( LoLoop . End ) ; if ( LoLoop . IsTailPredicationLegal ( ) ) ConvertVPTBlocks ( LoLoop ) ; for ( auto * I : LoLoop . ToRemove ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; I -> eraseFromParent ( ) ; } for ( auto * I : LoLoop . BlockMasksToRecompute ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; recomputeVPTBlockMask ( * I ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; } } PostOrderLoopTraversal DFS ( LoLoop . ML , * MLI ) ; DFS . ProcessLoop ( ) ;

const SmallVectorImpl < MachineBasicBlock * > & PostOrder = DFS . getOrder ( ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return IsINC ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> :


<s> return new <ISA_LIT>WinCOFFStreamer ( Context , MAB , * Emitter , OS ) ;


<s> <ISA_LIT>ControlFlowFinalizer ( TargetMachine & tm ) : MachineFunctionPass ( ID ) {


<s> else { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; const MCSymbolRefExpr * Dot = MCSymbolRefExpr :: create ( DotSym , OutContext ) ; OutStreamer . EmitLabel ( DotSym ) ; OutStreamer . EmitInstruction ( MCInstBuilder ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addExpr ( Dot ) , STI ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T ) : TargetAsmBackend ( ) , TheTarget ( T ) {


<s> return isGFX10Plus ( STI ) ? getGfx10PlusBufferFormatInfo ( Format ) : getGfx9BufferFormatInfo ( Format ) ;


<s> while ( v & ( <NUM_LIT> << msb ) ) -- msb ; while ( v & ( <NUM_LIT> << lsb ) ) ++ lsb ; for ( unsigned int i = lsb ; i <= msb ; ++ i ) { if ( v & ( <NUM_LIT> << i ) ) return <NUM_LIT> ; } return <NUM_LIT> ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> static unsigned getNextSVEVectorRegister ( unsigned Reg ) { if ( Reg == <STR_LIT> ) return <STR_LIT> ;


<s> auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( AMXCast -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Builder . CreateSExt ( Col , Builder . getInt64Ty ( ) ) } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; AMXCast -> replaceAllUsesWith ( NewInst ) ; AMXCast -> eraseFromParent ( ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ; if ( ! II ) return false ; Prepare ( AMXCast -> getType ( ) ) ; Value * Row = II -> getOperand ( <NUM_LIT> ) ; Value * Col = II -> getOperand ( <NUM_LIT> ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Builder . CreateSExt ( Col , Builder . getInt64Ty ( ) ) , Src } ; Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ;

Value * NewInst = Builder . CreateLoad ( AMXCast -> getType ( ) , AllocaAddr ) ;


<s> for ( auto & LR : interferenceGraph ) { if ( LR -> contains ( MI ) ) {


<s> SDValue EltNo = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( EltNo ) ) return SDValue ( ) ; EVT OriginalVT = InVec . getValueType ( ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; EVT BCVT = InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! BCVT . isVector ( ) || BCVT . getVectorNumElements ( ) != OriginalVT . getVectorNumElements ( ) ) return SDValue ( ) ; InVec = InVec . getOperand ( <NUM_LIT> ) ; } EVT CurrentVT = InVec . getValueType ( ) ; if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = CurrentVT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getNumOperands ( ) > <NUM_LIT> && InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;

if ( LdNode . getOpcode ( ) == <STR_LIT> ) {


<s> return { nullptr , MCSymbolRefExpr :: VariantKind :: VK_Invalid } ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) {


<s> SDValue VAList = DAG . getLoad ( getPointerTy ( ) , dl , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , V , <NUM_LIT> ) ;

SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , VAList , DAG . getConstant ( VT . getSizeInBits ( ) , getPointerTy ( ) ) ) ;


<s> bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= ExpandMI ( MBB , MBBI ) ; MBBI = NMBBI ; } return Modified ;


<s> MCDisassembler ( STI ) , fMode ( mode ) {


<s> if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ;

return ( VT1 . getSizeInBits ( ) > VT2 . getSizeInBits ( ) ) ;


<s> RefFlags |= <ISA_LIT>MCExpr :: VK_TPREL ; break ; case TLSModel :: LocalDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_DTPREL ; break ; case TLSModel :: GeneralDynamic : RefFlags |= <ISA_LIT>MCExpr :: VK_TLSDESC ; break ; } } else if ( PlatformFlag == <STR_LIT> ) { RefFlags |= <ISA_LIT>MCExpr :: VK_SEC ; } else { RefFlags |= <ISA_LIT>MCExpr :: VK_ABS ; } if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGE ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_PAGEOFF ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G3 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G2 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G1 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_G0 ; else if ( FragmentFlag == <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_HI12 ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) RefFlags |= <ISA_LIT>MCExpr :: VK_NC ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;


<s> temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( temp ) , GEN_INT ( c & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IOR ( SImode , copy_rtx ( temp ) , GEN_INT ( c & <NUM_LIT> ) ) ) ) ; break ; case E_DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == <NUM_LIT> , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != <NUM_LIT> , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> <NUM_LIT> ) ) ; c = ( ( c & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; emit_move_insn ( lo , GEN_INT ( c ) ) ; }

else rs6000_emit_set_long_const ( dest , c ) ;


<s> else IsValid = isInt < <NUM_LIT> > ( Imm ) ;

return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;


<s> * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : * total = COSTS_N_INSNS ( <NUM_LIT> + <NUM_LIT> ) ; return true ; case DIV : * total = COSTS_N_INSNS ( <NUM_LIT> - <NUM_LIT> ) ; return true ; default : return false ; }


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ;


<s> seen_vector_label = true ; gcc_assert ( vector_neutered ) ; vector_neutered = false ; } else if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_nvptx_barsync : gcc_assert ( ! vector_neutered && ! worker_neutered ) ; break ; default : break ; } if ( insn != BB_END ( bb ) ) insn = NEXT_INSN ( insn ) ; else if ( JUMP_P ( insn ) && single_succ_p ( bb ) && ! seen_vector_jump && ! seen_worker_jump ) { bb = single_succ ( bb ) ; insn = BB_HEAD ( bb ) ; } else break ; } gcc_assert ( ! ( vector_jump && ! seen_vector_jump ) ) ; gcc_assert ( ! ( worker_jump && ! seen_worker_jump ) ) ;

if ( seen_vector_label || seen_worker_label ) {


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI1 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg ) ; MI1 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI2 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ;

MI2 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> return new <ISA_LIT>Disassembler :: <ISA_LIT>_64Disassembler ;


<s> case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return LowerSymbolOperand ( MO , Offset ) ; case MachineOperand :: MO_Metadata :


<s> bool <ISA_LIT>II :: getDefaultSwitches ( StringRef Mnemonic , SlotParser Slot , OpType Type , unsigned & CurrentSwitchSet , const std :: vector < std :: string > & Switches ) { assert ( Slot != SlotParser :: Unknown ) ; assert ( SubTargetInfo ) ; bool Changed = false ; if ( const InstructionInfo * Info = getSwitchesForMnemonic ( Mnemonic , Slot ) ) { auto Sws = getApplicableSwitches ( Info , SubTargetInfo -> getFeatureBits ( ) , Type ) ; for ( auto SwPtr : Sws ) {

if ( ( ( SwPtr -> Default ) & ~ PrintFlagMask ) == <NUM_LIT> ) continue ;


<s> static const LdStNInstrDesc * getLdStNInstrDesc ( unsigned Opcode ) { unsigned Idx ;

for ( Idx = <NUM_LIT> ; Idx != array_lengthof ( LdStNInstInfo ) ; ++ Idx ) if ( LdStNInstInfo [ Idx ] . Opcode == Opcode ) return & LdStNInstInfo [ Idx ] ;


<s> bool <ISA_LIT>TargetLowering :: shouldReduceLoadWidth ( SDNode * Load , <STR_LIT> ExtTy , EVT NewVT ) const {

SDValue BasePtr = cast < LoadSDNode > ( Load ) -> getBasePtr ( ) ;


<s> for ( unsigned Op : { G_ADD , G_SUB , G_MUL } ) for ( auto Ty : { s1 , s8 , s16 , s32 } ) setAction ( { Op , Ty } , Legal ) ; for ( unsigned Op : { G_SDIV , G_UDIV } ) { for ( auto Ty : { s8 , s16 } ) setAction ( { Op , Ty } , Custom ) ; if ( ST . hasDivideIn<ISA_LIT>Mode ( ) ) setAction ( { Op , s32 } , Legal ) ; else setAction ( { Op , s32 } , Libcall ) ; } for ( unsigned Op : { G_SEXT , G_ZEXT } ) { setAction ( { Op , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { Op , <NUM_LIT> , Ty } , Legal ) ; } setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; setAction ( { G_CONSTANT , s32 } , Legal ) ; if ( ! ST . useSoftFloat ( ) && ST . hasVFP2 ( ) ) { setAction ( { G_FADD , s32 } , Legal ) ; setAction ( { G_FADD , s64 } , Legal ) ; setAction ( { G_LOAD , s64 } , Legal ) ; setAction ( { G_STORE , s64 } , Legal ) ;


<s> PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( isUncondBranchOpcode ( Opc ) ) { MI -> setDesc ( get ( getMatchingCondBranchOpcode ( Opc ) ) ) ;

MachineInstrBuilder ( * MI -> getParent ( ) -> getParent ( ) , MI ) . addImm ( Pred [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ;


<s> if ( And -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * AndC = dyn_cast < ConstantSDNode > ( And -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndC || ! AndC -> getAPIntValue ( ) . isPowerOf2 ( ) ) return SDValue ( ) ; SDValue X = And -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; } else { assert ( CC == <STR_LIT> && <STR_LIT> ) ; } if ( Op1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * OrC = dyn_cast < ConstantSDNode > ( Op1 -> getOperand ( <NUM_LIT> ) ) ; if ( ! OrC ) return SDValue ( ) ; SDValue Y = Op1 -> getOperand ( <NUM_LIT> ) ; if ( Op0 != Y ) return SDValue ( ) ; APInt OrCI = OrC -> getAPIntValue ( ) ; unsigned Heuristic = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( OrCI . countPopulation ( ) > Heuristic ) return SDValue ( ) ; APInt KnownZero , KnownOne ; DAG . computeKnownBits ( Y , KnownZero , KnownOne ) ; if ( ( OrCI & KnownZero ) != OrCI ) return SDValue ( ) ; SDValue V = Y ; SDLoc dl ( X ) ; EVT VT = X . getValueType ( ) ; unsigned BitInX = AndC -> getAPIntValue ( ) . logBase2 ( ) ; if ( BitInX != <NUM_LIT> ) { X = DAG . getNode ( <STR_LIT> , dl , VT , X , DAG . getConstant ( BitInX , dl , VT ) ) ;


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } if ( Constraint [ <NUM_LIT> ] == '{' ) { if ( Constraint [ <NUM_LIT> ] == 'r' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; } if ( Constraint [ <NUM_LIT> ] == 'f' ) { if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; if ( VT == <STR_LIT> ) return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; return parseRegisterNumber ( Constraint , & <STR_LIT> , <STR_LIT> ) ; } }

return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false , false ) ;


<s> } for ( unsigned i = <NUM_LIT> ; i != NumLaneElts / <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( NewImm % NumLaneElts + NumElts + l ) ; NewImm /= NumLaneElts ; } if ( NumLaneElts == <NUM_LIT> ) NewImm = Imm ; }


<s> if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; else BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; break ; } } unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; bool TryFold = false ; if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; } assert ( RC && <STR_LIT> ) ; if ( TryFold ) { unsigned NewVReg = <NUM_LIT> ; unsigned FoldedOpc = canFoldIntoCSel ( MRI , TrueReg , & NewVReg ) ; if ( FoldedOpc ) { CC = <STR_LIT> ( CC ) ; TrueReg = FalseReg ; } else FoldedOpc = canFoldIntoCSel ( MRI , FalseReg , & NewVReg ) ; if ( FoldedOpc ) { FalseReg = NewVReg ; Opc = FoldedOpc ; MRI . clearKillFlags ( NewVReg ) ;


<s> if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode , x , GEN_INT ( offset ) ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( <NUM_LIT> , x ) ) ;


<s> void cr16_expand_prologue ( void ) { rtx insn ; cr16_compute_frame ( ) ; cr16_compute_save_regs ( ) ; if ( ( current_frame_info . total_size + current_frame_info . reg_size ) == <NUM_LIT> ) return ; if ( current_frame_info . last_reg_to_save != - <NUM_LIT> ) { insn = emit_insn ( gen_push_for_prologue ( GEN_INT ( current_frame_info . reg_size ) ) ) ; cr16_create_dwarf_for_multi_push ( insn ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( current_frame_info . total_size > <NUM_LIT> ) {


<s> unsigned ScratchReg ; ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

MIB . addReg ( ScratchReg , RegState :: Define | RegState :: Dead | RegState :: EarlyClobber ) ;


<s> OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ;


<s> static bool scaleOffset ( unsigned Opc , int64_t & Offset ) { unsigned OffsetStride = getOffsetStride ( Opc ) ; if ( OffsetStride == <NUM_LIT> ) return false ; if ( Offset % OffsetStride != <NUM_LIT> ) return false ; Offset /= OffsetStride ; return true ;


<s> <ISA_LIT>AbstractMemberAccessPass ( <ISA_LIT>TargetMachine * TM ) : TM ( TM ) {


<s> unsigned int getPLT0Size ( ) const { return m_PLT0Size ;


<s> static const <ISA_LIT>FloatMCExpr * createConstantFPSingle ( const APFloat & Flt , MCContext & Ctx ) { return create ( VK_<ISA_LIT>_SINGLE_PREC_FLOAT , Flt , Ctx ) ;


<s> static bool isPSHUFDMask ( ArrayRef < int > Mask , EVT VT ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) return ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ; return false ;


<s> const TargetRegisterClass * const * <ISA_LIT>RegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = {

& <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ;


<s> SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue <ISA_LIT>cc ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ;

return DAG . getMergeValues ( Ops , dl ) ;


<s> for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ; codes [ i ] . value = trunc_int_for_mode ( codes [ i ] . value , mode ) ; x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; } }


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const {


<s> Register getImplicitBufferPtrUserSGPR ( ) const {

return ArgInfo . ImplicitBufferPtr . getRegister ( ) ;


<s> for ( const MCPhysReg * CSR = TRI -> getCalleeSavedRegs ( MI -> getParent ( ) -> getParent ( ) ) ; * CSR ; ++ CSR ) { unsigned CalleeSavedReg = * CSR ; if ( MI -> modifiesRegister ( CalleeSavedReg , TRI ) ) return true ; }


<s> case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : return true ; } return false ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueValue = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseValue = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; EVT TrueType = TrueValue . getValueType ( ) ; EVT FalseType = FalseValue . getValueType ( ) ; if ( TrueType != FalseType ) { llvm_unreachable ( <STR_LIT> ) ;


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {

return new <ISA_LIT>ELFStreamer ( S , STI ) ;


<s> bool <ISA_LIT>BaseRegisterInfo :: cannotEliminateFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI . adjustsStack ( ) ) return true ;


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ;

unsigned RegNum = MRI -> getDwarfRegNum ( Reg , true ) ;


<s> void <ISA_LIT>InstPrinter :: printMemSrcPostIncOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { printMemSrcOperand ( MI , OpNo , O , Modifier , false , true ) ;


<s> void <ISA_LIT>InstPrinter :: printX2 ( const MCInst * , unsigned , raw_ostream & ) {


<s> return true ; } if ( inClass ( <STR_LIT> , DestReg , DestRC ) && inClass ( <STR_LIT> , SrcReg , SrcRC ) ) { if ( inClass ( <STR_LIT> , DestReg , DestRC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; else BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } if ( inClass ( <STR_LIT> , DestReg , DestRC ) && inClass ( <STR_LIT> , SrcReg , SrcRC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } if ( inClass ( <STR_LIT> , DestReg , DestRC ) && inClass ( <STR_LIT> , SrcReg , SrcRC ) ) {


<s> return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( ) { initializeEnvironment ( ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( DisableMemOps ) UseMemOps = false ; else if ( EnableMemOps ) UseMemOps = true ; else UseMemOps = false ; if ( EnableIEEERndNear ) ModeIEEERndNear = true ; else ModeIEEERndNear = false ;

UseBSBScheduling = hasV60TOps ( ) && EnableBSBSched ;


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - <NUM_LIT> ;

SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ;


<s> unsigned Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg ; computeIndirectRegAndOffset ( Dst , Reg , Off ) ; MachineInstr * MovRel = BuildMI ( * MBB . getParent ( ) , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Define ) . addReg ( Val ) . addReg ( Dst , RegState :: Implicit ) ; LoadM0 ( MI , MovRel , Off ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectBITCAST_TO_LOHI ( SDNode * N ) { SDLoc Dl ( N ) ; auto VT = N -> getValueType ( <NUM_LIT> ) ; auto V = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget -> hasFPUv2DoubleFloat ( ) ) return false ;

SDValue V1 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , Dl , VT , V ) , <NUM_LIT> ) ;


<s> addPass ( create<ISA_LIT>Z80PostRAPass ( ) ) ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ;


<s> parm ; parm = TREE_CHAIN ( parm ) ) { if ( DECL_RTL ( parm ) == <NUM_LIT> || GET_CODE ( DECL_RTL ( parm ) ) == MEM ) return <NUM_LIT> ; if ( DECL_INCOMING_RTL ( parm ) == <NUM_LIT> || GET_CODE ( DECL_INCOMING_RTL ( parm ) ) == MEM ) return <NUM_LIT> ; }


<s> addRegisterClass ( <STR_LIT> , & AMDGPU :: R600_Reg128RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: R600_Reg32RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: R600_Reg64RegClass ) ; addRegisterClass ( <STR_LIT> , & AMDGPU :: R600_Reg64RegClass ) ; computeRegisterProperties ( ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setCondCodeAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Custom ) ;


<s> MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( std :: next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; NewWaterList . insert ( OrigBB ) ; computeBlockSize ( OrigBB ) ; computeBlockSize ( NewBB ) ;


<s> auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits ) ; if ( bitmap_empty_p ( fpubits ) ) return <STR_LIT> ; for ( unsigned int i = <NUM_LIT> ; i < ARRAY_SIZE ( all_fpus ) ; i ++ ) {

arm_initialize_isa ( cand_fpubits , all_fpus [ i ] . isa_bits ) ;


<s> for ( member = OVL_CURRENT ( member ) ; member ; member = OVL_NEXT ( member ) ) { if ( TREE_CODE ( member ) != FUNCTION_DECL ) continue ; if ( DECL_PURE_VIRTUAL_P ( member ) ) continue ; if ( ! DECL_VIRTUAL_P ( member ) ) continue ; if ( lookup_attribute ( attribute_name , DECL_ATTRIBUTES ( member ) ) ) { print_node_brief ( stderr , <STR_LIT> , ctype , <NUM_LIT> ) ; fprintf ( stderr , <STR_LIT> , attribute_name ) ; print_node_brief ( stderr , <STR_LIT> , member , <NUM_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; return true ; } } } } print_node_brief ( stderr , <STR_LIT> , ctype , <NUM_LIT> ) ; fprintf ( stderr , <STR_LIT> , attribute_name ) ; return false ;


<s> unsigned DescSZ = sizeof ( VendorNameSize ) + sizeof ( ArchNameSize ) + sizeof ( Major ) + sizeof ( Minor ) + sizeof ( Stepping ) + VendorNameSize + ArchNameSize ; Emit<ISA_LIT>Note ( MCConstantExpr :: create ( DescSZ , getContext ( ) ) , ElfNote :: NT_<ISA_LIT>_HSA_ISA , [ & ] ( MCELFStreamer & OS ) { OS . EmitIntValue ( VendorNameSize , <NUM_LIT> ) ; OS . EmitIntValue ( ArchNameSize , <NUM_LIT> ) ; OS . EmitIntValue ( Major , <NUM_LIT> ) ; OS . EmitIntValue ( Minor , <NUM_LIT> ) ; OS . EmitIntValue ( Stepping , <NUM_LIT> ) ; OS . EmitBytes ( VendorName ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitBytes ( ArchName ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; } ) ;


<s> gen_il = gen_avx2_interleave_lowv32qi ; gen_ih = gen_avx2_interleave_highv32qi ; break ; case V64QImode : himode = V32HImode ; gen_il = gen_avx512bw_interleave_lowv64qi ; gen_ih = gen_avx512bw_interleave_highv64qi ; break ; default : gcc_unreachable ( ) ; } op2_l = op2_h = op2 ; switch ( code ) { case MULT : op2_l = gen_reg_rtx ( qimode ) ; op2_h = gen_reg_rtx ( qimode ) ; emit_insn ( gen_il ( op2_l , op2 , op2 ) ) ; emit_insn ( gen_ih ( op2_h , op2 , op2 ) ) ; op1_l = gen_reg_rtx ( qimode ) ; op1_h = gen_reg_rtx ( qimode ) ; emit_insn ( gen_il ( op1_l , op1 , op1 ) ) ; emit_insn ( gen_ih ( op1_h , op1 , op1 ) ) ; full_interleave = qimode == V16QImode ; break ; case ASHIFT : case LSHIFTRT : uns_p = true ; case ASHIFTRT : op1_l = gen_reg_rtx ( himode ) ; op1_h = gen_reg_rtx ( himode ) ; ix86_expand_sse_unpack ( op1_l , op1 , uns_p , false ) ; ix86_expand_sse_unpack ( op1_h , op1 , uns_p , true ) ; full_interleave = true ; break ; default : gcc_unreachable ( ) ; } res_l = expand_simple_binop ( himode , code , op1_l , op2_l , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; res_h = expand_simple_binop ( himode , code , op1_h , op2_h , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; gcc_assert ( res_l && res_h ) ; d . target = dest ; d . op0 = gen_lowpart ( qimode , res_l ) ; d . op1 = gen_lowpart ( qimode , res_h ) ; d . vmode = qimode ; d . nelt = GET_MODE_NUNITS ( qimode ) ; d . one_operand_p = false ; d . testing_p = false ; if ( full_interleave ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) d . perm [ i ] = i * <NUM_LIT> ; } else { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) d . perm [ i ] = i * <NUM_LIT> + ( ( i & <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : ( i & <NUM_LIT> ) == <NUM_LIT> ? - <NUM_LIT> : <NUM_LIT> ) ; }

ok = ix86_expand_vec_perm_const_1 ( & d ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ;


<s> return arc_predicate_delay_insns ( ) ;


<s> static Reloc :: Model getEffectiveRelocModel ( bool JIT , Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) || JIT ) return Reloc :: Static ;


<s> setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ; Instrumentation . reset ( Create<ISA_LIT>AsmInstrumentation ( Options , Parser . getContext ( ) , STI ) ) ;


<s> else if ( CONSTANT_CLASS_P ( exp ) && ! reloc ) return readonly_data_section ;

else if ( TARGET_SOM && TREE_CODE ( exp ) == VAR_DECL && DECL_ONE_ONLY ( exp ) && ! DECL_WEAK ( exp ) ) return som_one_only_data_section ;


<s> return __builtin_mve_vmvnq_m_n_sv4si ( __arm_vuninitializedq_s32 ( ) , __imm , __p ) ;


<s> rtx tmp ; gcc_assert ( GET_MODE ( op ) != V2DImode && GET_MODE ( op ) != V2DFmode ) ; tmp = CONST_VECTOR_ELT ( op , elt ) ;

if ( GET_MODE ( op ) == V4SFmode ) tmp = gen_lowpart ( SImode , tmp ) ;


<s> unsigned ResultReg = createResultReg ( RC ) ; const TargetInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addImm ( Imm ) ) ; else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg ;


<s> split_const ( x , & base , & offset ) ;

if ( GET_CODE ( base ) == SYMBOL_REF || GET_CODE ( base ) == LABEL_REF ) {


<s> Symbol -> setExternal ( false ) ; AssignSection ( Symbol , getCurrentSection ( ) . first ) ; const MCExpr * Value = MCSymbolRefExpr :: create ( Start , getContext ( ) ) ;


<s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( <STR_LIT> ) ; if ( hasFP ( MF ) ) SavedRegs . set ( <STR_LIT> ) ;


<s> SDValue Nest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = ( PtrVT == <STR_LIT> ) ; Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = Trmp ; Args . push_back ( Entry ) ;

Entry . Node = DAG . getConstant ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ;


<s> if ( ! TII -> mayBeNewStore ( MI ) ) return false ; MachineOperand & MO = MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; return ( MO . isReg ( ) && RegDefs . count ( MO . getReg ( ) ) != <NUM_LIT> ) ;


<s> if ( TT . getOS ( ) == Triple :: AIX ) return false ; return FullRegNamesWithPercent || FullRegNames ;


<s> targetm . target_option . pragma_parse = aarch64_pragma_target_parse ; targetm . resolve_overloaded_builtin = aarch64_resolve_overloaded_builtin ;

targetm . check_builtin_call = aarch64_check_builtin_call ;


<s> for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( ToErase ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ToErase -> dump ( ) ) ; ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { Register dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Opcode == <STR_LIT> ) dst = TRI -> getSubReg ( dst , <STR_LIT> ) ; if ( dst != src ) continue ; ToErase = & MI ; RedundantMovElemNum ++ ; Eliminated = true ;


<s> SDValue InpV = Op . getOperand ( <NUM_LIT> ) ; MVT ElemTy = ty ( InpV ) . getVectorElementType ( ) ; if ( ElemTy == <STR_LIT> && Subtarget . isHVXVectorType ( ResTy ) ) return extendHvxVectorPred ( InpV , SDLoc ( Op ) , ty ( Op ) , false , DAG ) ; return Op ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI != NULL ) return isSignOrZeroExtended ( * SrcMI , SignExt , Depth ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Depth >= MAX_DEPTH ) return false ; unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> ) { E = MI . getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( MI . getOperand ( I ) . isReg ( ) ) { Register SrcReg = MI . getOperand ( I ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI == NULL || ! isSignOrZeroExtended ( * SrcMI , SignExt , Depth + <NUM_LIT> ) ) return false ; } else return false ; } return true ; } case <STR_LIT> : case <STR_LIT> : { if ( Depth >= MAX_DEPTH ) return false ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; Register SrcReg1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( ! Register :: isVirtualRegister ( SrcReg1 ) || ! Register :: isVirtualRegister ( SrcReg2 ) ) return false ;


return ( __m256i ) __builtin_ia32_pmovzxwd256_mask ( ( __v8hi ) __A , ( __v8si ) _mm256_setzero_si256 ( ) , ( __mmask8 ) __U ) ;


<s> unsigned Occupancy = MFI -> getOccupancy ( ) ; MaxNumVGPRs = ST -> getMaxNumVGPRs ( MF ) ; MaxNumSGPRs = ST -> getMaxNumSGPRs ( MF ) ; MaxNumVGPRs = std :: min ( ST -> getMaxNumVGPRs ( Occupancy ) , MaxNumVGPRs ) ; MaxNumSGPRs = std :: min ( ST -> getMaxNumSGPRs ( Occupancy , true ) , MaxNumSGPRs ) ; CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; RegsUsed . resize ( <STR_LIT> . getNumRegs ( ) + TRI -> getEncodingValue ( <STR_LIT> ) / <NUM_LIT> + <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; unsigned StallCycles = collectCandidates ( MF ) ; NumStallsDetected += StallCycles ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << StallCycles << <STR_LIT> <STR_LIT> << MF . getName ( ) << '\n' ) ; Candidates . sort ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto C : Candidates ) C . dump ( this ) ; dbgs ( ) << <STR_LIT> ) ; unsigned CyclesSaved = <NUM_LIT> ; while ( ! Candidates . empty ( ) ) { Candidate C = Candidates . back ( ) ; unsigned LocalCyclesSaved = tryReassign ( C ) ; CyclesSaved += LocalCyclesSaved ; if ( VerifyStallCycles > <NUM_LIT> && ! verifyCycles ( MF , StallCycles , CyclesSaved ) ) report_fatal_error ( <STR_LIT> ) ; Candidates . pop_back ( ) ; if ( LocalCyclesSaved ) { removeCandidates ( C . Reg ) ; computeStallCycles ( C . Reg , <STR_LIT> , - <NUM_LIT> , true ) ; Candidates . sort ( ) ;


<s> } } else { ImmInstrInfo III ; unsigned Opc = MI . getOpcode ( ) ; bool ConvertibleImmForm = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( ! instrHasImmForm ( MI , III , true ) && ! ConvertibleImmForm ) return nullptr ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) return nullptr ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; i ++ ) { MachineOperand & MO = MI . getOperand ( i ) ; SeenIntermediateUse = false ; if ( MO . isReg ( ) && MO . isUse ( ) && ! MO . isImplicit ( ) ) { MachineBasicBlock :: reverse_iterator E = MI . getParent ( ) -> rend ( ) , It = MI ; It ++ ; unsigned Reg = MI . getOperand ( i ) . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) Reg = Reg - <STR_LIT> + <STR_LIT> ; for ( ; It != E ; ++ It ) { if ( It -> modifiesRegister ( Reg , & getRegisterInfo ( ) ) ) { switch ( It -> getOpcode ( ) ) { default : break ;


<s> x = orig_x ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && REGNO ( XEXP ( x , <NUM_LIT> ) ) == PIC_OFFSET_TABLE_REGNUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST ) { HOST_WIDE_INT offset = <NUM_LIT> ; y = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( y ) == PLUS && GET_CODE ( XEXP ( y , <NUM_LIT> ) ) == CONST_INT ) { offset = INTVAL ( XEXP ( y , <NUM_LIT> ) ) ; y = XEXP ( y , <NUM_LIT> ) ; }

if ( GET_CODE ( y ) == UNSPEC && ( XINT ( y , <NUM_LIT> ) == UNSPEC_GOTOFF || XINT ( y , <NUM_LIT> ) == UNSPEC_PLTOFF ) ) return plus_constant ( Pmode , XVECEXP ( y , <NUM_LIT> , <NUM_LIT> ) , offset ) ;


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override {


<s> bool <ISA_LIT>MCInstrInfo :: isExtended ( MCInstrInfo const & MCII , MCInst const & MCI ) { uint64_t const F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; return ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ; unsigned Idx = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , DL , F . getCallingConv ( ) ) ; Idx ++ ; }

if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & Symbol = MI . getOperand ( <NUM_LIT> ) ; MachineBasicBlock * NewMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; NewMBB -> setLabelMustBeEmitted ( ) ; MF -> insert ( ++ MBB . getIterator ( ) , NewMBB ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addDisp ( Symbol , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( NewMBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addMBB ( NewMBB , <STR_LIT> ) ; NewMBB -> splice ( NewMBB -> end ( ) , & MBB , std :: next ( MBBI ) , MBB . end ( ) ) ; NewMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( NewMBB ) ; LivePhysRegs LiveRegs ;

computeAndAddLiveIns ( LiveRegs , * NewMBB ) ;


<s> case V8DF_FTYPE_PCV8DF_V8DF_UQI : case V2DI_FTYPE_PCV2DI_V2DI_UQI : case V4DI_FTYPE_PCV4DI_V4DI_UQI : case V8DI_FTYPE_PCV8DI_V8DI_UQI : case V64QI_FTYPE_PCV64QI_V64QI_UDI : case V32HI_FTYPE_PCV32HI_V32HI_USI : case V32QI_FTYPE_PCV32QI_V32QI_USI : case V16QI_FTYPE_PCV16QI_V16QI_UHI : case V16HI_FTYPE_PCV16HI_V16HI_UHI : case V8HI_FTYPE_PCV8HI_V8HI_UQI : switch ( icode ) { case CODE_FOR_avx512f_loadv16sf_mask : case CODE_FOR_avx512f_loadv16si_mask : case CODE_FOR_avx512f_loadv8df_mask : case CODE_FOR_avx512f_loadv8di_mask : case CODE_FOR_avx512vl_loadv8sf_mask : case CODE_FOR_avx512vl_loadv8si_mask : case CODE_FOR_avx512vl_loadv4df_mask : case CODE_FOR_avx512vl_loadv4di_mask : case CODE_FOR_avx512vl_loadv4sf_mask : case CODE_FOR_avx512vl_loadv4si_mask : case CODE_FOR_avx512vl_loadv2df_mask : case CODE_FOR_avx512vl_loadv2di_mask : case CODE_FOR_avx512bw_loadv64qi_mask : case CODE_FOR_avx512vl_loadv32qi_mask : case CODE_FOR_avx512vl_loadv16qi_mask : case CODE_FOR_avx512bw_loadv32hi_mask : case CODE_FOR_avx512vl_loadv16hi_mask : case CODE_FOR_avx512vl_loadv8hi_mask : aligned_mem = true ; break ; default : break ; } case V64QI_FTYPE_PCCHAR_V64QI_UDI : case V32QI_FTYPE_PCCHAR_V32QI_USI : case V16QI_FTYPE_PCCHAR_V16QI_UHI : case V32HI_FTYPE_PCSHORT_V32HI_USI : case V16HI_FTYPE_PCSHORT_V16HI_UHI : case V8HI_FTYPE_PCSHORT_V8HI_UQI : case V16SI_FTYPE_PCINT_V16SI_UHI : case V8SI_FTYPE_PCINT_V8SI_UQI : case V4SI_FTYPE_PCINT_V4SI_UQI : case V8DI_FTYPE_PCINT64_V8DI_UQI : case V4DI_FTYPE_PCINT64_V4DI_UQI : case V2DI_FTYPE_PCINT64_V2DI_UQI : case V8DF_FTYPE_PCDOUBLE_V8DF_UQI : case V4DF_FTYPE_PCDOUBLE_V4DF_UQI : case V2DF_FTYPE_PCDOUBLE_V2DF_UQI : case V16SF_FTYPE_PCFLOAT_V16SF_UHI : case V8SF_FTYPE_PCFLOAT_V8SF_UQI : case V4SF_FTYPE_PCFLOAT_V4SF_UQI : case V8HF_FTYPE_PCFLOAT16_V8HF_UQI : nargs = <NUM_LIT> ; klass = load ; memory = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( nargs <= ARRAY_SIZE ( xops ) ) ; if ( klass == store ) { arg = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op = expand_normal ( arg ) ; gcc_assert ( target == <NUM_LIT> ) ; if ( memory ) { op = ix86_zero_extend_to_Pmode ( op ) ; target = gen_rtx_MEM ( tmode , op ) ; unsigned int align = get_pointer_alignment ( arg ) ; if ( aligned_mem && align < GET_MODE_ALIGNMENT ( tmode ) ) align = GET_MODE_ALIGNMENT ( tmode ) ; if ( MEM_ALIGN ( target ) < align ) set_mem_align ( target , align ) ; } else target = force_reg ( tmode , op ) ; arg_adjust = <NUM_LIT> ; } else { arg_adjust = <NUM_LIT> ; if ( optimize || target == <NUM_LIT> || ! register_operand ( target , tmode ) || GET_MODE ( target ) != tmode ) target = gen_reg_rtx ( tmode ) ; } for ( i = <NUM_LIT> ; i < nargs ; i ++ ) { machine_mode mode = insn_p -> operand [ i + <NUM_LIT> ] . mode ; arg = CALL_EXPR_ARG ( exp , i + arg_adjust ) ; op = expand_normal ( arg ) ; if ( i == memory ) { op = ix86_zero_extend_to_Pmode ( op ) ; op = gen_rtx_MEM ( mode , op ) ; unsigned int align = get_pointer_alignment ( arg ) ; if ( aligned_mem && align < GET_MODE_ALIGNMENT ( mode ) ) align = GET_MODE_ALIGNMENT ( mode ) ; if ( MEM_ALIGN ( op ) < align ) set_mem_align ( op , align ) ;


<s> rtx aarch64_simd_gen_const_vector_dup ( machine_mode mode , HOST_WIDE_INT val ) {

rtx c = gen_int_mode ( val , GET_MODE_INNER ( mode ) ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) {

if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ;


<s> I ++ ) { ( * I ) -> eraseFromParent ( ) ; }


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , LLT MemTy , MachinePointerInfo & MPO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ;

return MIRBuilder . buildLoad ( Res , Addr , * MMO ) ;


<s> static bool bpf_rtx_costs ( rtx x ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) {


<s> bool isDXReg ( ) const { return Kind == Memory && getMemBaseReg ( ) == <STR_LIT> && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> ;


<s> FunctionType * NewType = nullptr ; for ( Use & U : F . uses ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << * U . getUser ( ) << <STR_LIT> ) ; if ( auto * BC = dyn_cast < BitCastOperator > ( U . getUser ( ) ) ) { if ( auto * DestType = dyn_cast < FunctionType > ( BC -> getDestTy ( ) -> getPointerElementType ( ) ) ) { if ( ! NewType ) { NewType = DestType ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NewType << <STR_LIT> ) ; } else if ( NewType != DestType ) { errs ( ) << <STR_LIT> <STR_LIT> << F . getName ( ) << <STR_LIT> ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DestType << <STR_LIT> ) ;


<s> rtx fnaddr , mem , a_tramp ; const int tramp_code_sz = <NUM_LIT> ; rtx temp = convert_memory_address ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ; emit_block_move ( gen_rtx_MEM ( BLKmode , temp ) , assemble_trampoline_template ( ) , GEN_INT ( tramp_code_sz ) , BLOCK_OP_NORMAL ) ;


<s> CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , getPointerTy ( ) , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget -> hasSSE3 ( ) ) { Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ; } else { SDValue S2F = DAG . getBitcast ( <STR_LIT> , Sub ) ; SDValue Shuffle = getTargetShuffleNode ( <STR_LIT> , dl , <STR_LIT> , S2F , <NUM_LIT> , DAG ) ;

Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Shuffle ) , Sub ) ;


<s> pass_arc_predicate_delay_insns ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_arc_predicate_delay_insns , ctxt ) {


<s> if ( IsCMN ( LHSDef , CC ) ) { I . getOperand ( <NUM_LIT> ) . setReg ( LHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DidFold = true ; } else if ( IsCMN ( RHSDef , CC ) ) { I . getOperand ( <NUM_LIT> ) . setReg ( RHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DidFold = true ; } if ( DidFold ) { static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is32Bit = ( MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ) ; auto ImmFns = selectArithImmed ( I . getOperand ( <NUM_LIT> ) ) ; unsigned Opc = OpcTable [ Is32Bit ] [ ImmFns . hasValue ( ) ] ; Register ZReg = Is32Bit ? <STR_LIT> : <STR_LIT> ; auto CmpMI = MIRBuilder . buildInstr ( Opc , { ZReg } , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; if ( ImmFns ) { for ( auto & RenderFn : * ImmFns ) RenderFn ( CmpMI ) ; } else { CmpMI . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ; emitCSetForICMP ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getPredicate ( ) , MIRBuilder ) ;


<s> static bool is<ISA_LIT>LogicalCmp ( SDValue Op ) { unsigned Opc = Op . getNode ( ) -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && Opc == <STR_LIT> ) return true ; return false ;


<s> <ISA_LIT>_64PLT :: <ISA_LIT>_64PLT ( LDSection & pSection , <ISA_LIT>_64GOTPLT & pGOTPLT , const LinkerConfig & pConfig ) : <ISA_LIT>PLT ( pSection , pConfig , <NUM_LIT> ) , m_GOTPLT ( pGOTPLT ) {


<s> case <STR_LIT> : return MCSymbolRefExpr :: VK_TLSGD ; case <STR_LIT> : return MCSymbolRefExpr :: VK_TPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_GOTTPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return ( GA -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS || GA -> getAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS ) && ! shouldEmitGOTReloc ( GA -> getGlobal ( ) ) ;


<s> case 'o' : case 'v' : default : return true ; case 'm' :

if ( ! SelectAddr ( Op . getNode ( ) , Op , Op0 , Op1 ) ) return true ;


<s> bool LeftoverBytes = ( NumRegs * RegSizeInBytes > ByValSizeInBytes ) ; unsigned I = <NUM_LIT> ; for ( ; I < NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getPointerAdd ( DL , Arg , OffsetInBytes ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , DL , <STR_LIT> ) ) ;

if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ;


<s> <ISA_LIT>ompactSelectionDAGInfo :: <ISA_LIT>ompactSelectionDAGInfo ( const <ISA_LIT>ompactTargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) {


<s> void <ISA_LIT>InstPrinter :: printSelectionControl ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {

if ( OpNo < MI -> getNumOperands ( ) ) {


<s> ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT> : nullptr ; AssemblerDialect = <NUM_LIT> ; if ( T . getOS ( ) == llvm :: Triple :: FreeBSD || ( T . getOS ( ) == llvm :: Triple :: NetBSD && ! is64Bit ) || ( T . getOS ( ) == llvm :: Triple :: OpenBSD && ! is64Bit ) ) UseIntegratedAssembler = true ;


<s> static rtx or1k_function_value ( const_tree valtype , const_tree , bool ) {

return gen_rtx_REG ( TYPE_MODE ( valtype ) , RV_REGNUM ) ;


<s> AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < MachineModuleInfoWrapperPass > ( ) ;


<s> std :: vector < std :: string > retd ( ) {


<s> static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return createTupleImpl ( CurDAG , Regs , RegClassIDs [ NF - <NUM_LIT> ] , <STR_LIT> ) ;


<s> unsigned getSGPREncodingGranule ( ) const { return <STR_LIT> :: getSGPREncodingGranule ( this ) ;


<s> if ( TARGET_SIMD && ( mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V2DImode || mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == V2SFmode || mode == V4SFmode || mode == V2DFmode || mode == V1DFmode ) ) return true ; return false ;


<s> for ( unsigned SUNum : DAG -> BottomUpIndex2SU ) { SUnit * SU = & DAG -> SUnits [ SUNum ] ; bool hasSuccessor = false ; if ( CurrentColoring [ SU -> NodeNum ] <= ( int ) DAGSize ) continue ; for ( SDep & SuccDep : SU -> Succs ) { SUnit * Succ = SuccDep . getSUnit ( ) ; if ( SuccDep . isWeak ( ) || Succ -> NodeNum >= DAGSize ) continue ; hasSuccessor = true ;


<s> fma_node :: fma_node ( fma_node * parent , du_chain * chain ) { memset ( this , <NUM_LIT> , sizeof ( * this ) ) ; this -> m_parent = parent ; this -> m_children = new std :: list < fma_node * > ;


<s> for ( NodeVect :: iterator I = Cs . begin ( ) , E = Cs . end ( ) ; I != E ; ++ I ) recalculatePlacementRec ( * I , NCM , Loc ) ; } BasicBlock * LB = recalculatePlacement ( Node , NCM , Loc ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << Node << '\n' ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;

return CE -> getValue ( ) >= - ( <NUM_LIT> << ( BitWidth - <NUM_LIT> ) ) && CE -> getValue ( ) < ( <NUM_LIT> << ( BitWidth - <NUM_LIT> ) ) ;


<s> int Src1ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src1_modifiers ) ; int Src2ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src2_modifiers ) ; MI . RemoveOperand ( Src2ModIdx ) ; MI . RemoveOperand ( Src1ModIdx ) ;


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ;

MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> if ( ! CInfo . Metadata ) report_fatal_error ( <STR_LIT> ) ; CInfo . AccessIndex = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ; CInfo . Base = Call -> getArgOperand ( <NUM_LIT> ) ; CInfo . RecordAlignment = DL -> getABITypeAlignment ( CInfo . Base -> getType ( ) -> getPointerElementType ( ) ) ; return true ; } if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { CInfo . Kind = <ISA_LIT>PreserveUnionAI ; CInfo . Metadata = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; if ( ! CInfo . Metadata ) report_fatal_error ( <STR_LIT> ) ; CInfo . AccessIndex = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ; CInfo . Base = Call -> getArgOperand ( <NUM_LIT> ) ; CInfo . RecordAlignment = DL -> getABITypeAlignment ( CInfo . Base -> getType ( ) -> getPointerElementType ( ) ) ; return true ; } if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { CInfo . Kind = <ISA_LIT>PreserveStructAI ;


<s> unsigned llvm :: <ISA_LIT>GetLastSlot ( ) { return <STR_LIT> ;


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Width = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLT Ty = MRI . getType ( Src ) ; assert ( ( Ty == LLT :: scalar ( <NUM_LIT> ) || Ty == LLT :: scalar ( <NUM_LIT> ) ) && <STR_LIT> ) ; Register ShiftSrc ; int64_t ShiftImm ; if ( ! mi_match ( Src , MRI , m_OneNonDBGUse ( m_any_of ( m_GAShr ( m_Reg ( ShiftSrc ) , m_ICst ( ShiftImm ) ) , m_GLShr ( m_Reg ( ShiftSrc ) , m_ICst ( ShiftImm ) ) ) ) ) ) return false ; if ( ShiftImm < <NUM_LIT> || ShiftImm + Width > Ty . getSizeInBits ( ) ) return false ; MatchInfo = [ = ] ( MachineIRBuilder & B ) {

auto Cst1 = B . buildConstant ( Ty , ShiftImm ) ;


<s> if ( MBBI == BeginMBBI ) return EndMBBI ; MachineBasicBlock :: iterator PrevMBBI = std :: prev ( MBBI ) ; while ( PrevMBBI -> isDebugInstr ( ) && PrevMBBI != BeginMBBI ) -- PrevMBBI ;

Offset = isIncrementOrDecrement ( * PrevMBBI , Reg , Pred , PredReg ) ;


<s> continue ; } legalizeOpWithMove ( MI , Idx ) ; } } if ( MI -> getOpcode ( ) == AMDGPU :: REG_SEQUENCE ) { const TargetRegisterClass * RC = NULL , * SRC = NULL , * VRC = NULL ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; i += <NUM_LIT> ) { if ( ! MI -> getOperand ( i ) . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MI -> getOperand ( i ) . getReg ( ) ) ) continue ; const TargetRegisterClass * OpRC = MRI . getRegClass ( MI -> getOperand ( i ) . getReg ( ) ) ; if ( RI . hasVGPRs ( OpRC ) ) { VRC = OpRC ; } else { SRC = OpRC ; } } if ( VRC || ! RI . isSGPRClass ( getOpRegClass ( * MI , <NUM_LIT> ) ) ) { if ( ! VRC ) { assert ( SRC ) ; VRC = RI . getEquivalentVGPRClass ( SRC ) ; } RC = VRC ; } else { RC = SRC ; } for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; i += <NUM_LIT> ) { if ( ! MI -> getOperand ( i ) . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MI -> getOperand ( i ) . getReg ( ) ) ) continue ;

unsigned DstReg = MRI . createVirtualRegister ( RC ) ;


<s> NumBytes &= ~ ThisVal ; assert ( <STR_LIT> ( ThisVal ) != - <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) . addImm ( ( unsigned ) Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ; BaseReg = DestReg ; }


<s> BTFDebug :: BTFDebug ( AsmPrinter * AP ) : DebugHandlerBase ( AP ) , OS ( * Asm -> OutStreamer ) , SkipInstruction ( false ) , LineInfoGenerated ( false ) , SecNameOff ( <NUM_LIT> ) , ArrayIndexTypeId ( <NUM_LIT> ) { addString ( <STR_LIT> ) ;


<s> __i1 = __i1 << <NUM_LIT> | ( unsigned char ) __b4 ; __i0 = ( unsigned char ) __b3 ; __i0 = __i0 << <NUM_LIT> | ( unsigned char ) __b2 ;

__i0 = __i0 << <NUM_LIT> | ( unsigned char ) __b1 ;


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool Negated , MCContext & Ctx ) {

return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr , Negated ) ;


<s> case MCK__HASH_0 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__HASH_8 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__HASH_16 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK_ModImm : if ( Op . isImm ( ) ) { const MCExpr * SOExpr = Op . getImm ( ) ; int64_t Value ; if ( ! SOExpr -> evaluateAsAbsolute ( Value ) ) return Match_Success ; assert ( ( Value >= std :: numeric_limits < int32_t > :: min ( ) && Value <= std :: numeric_limits < uint32_t > :: max ( ) ) && <STR_LIT> ) ; } break ; case MCK_rGPR : if ( hasV8Ops ( ) && Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) return Match_Success ;


<s> else FrameReg = TRI -> getFrameRegister ( MF ) ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) ; const <ISA_LIT>MachineFunctionInfo * MMFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; bool HasFP = hasFP ( MF ) ; if ( TRI -> hasBasePointer ( MF ) ) { assert ( HasFP && <STR_LIT> ) ; if ( FI < <NUM_LIT> ) { return Offset + SlotSize ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI . getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else if ( TRI -> needsStackRealignment ( MF ) ) { if ( FI < <NUM_LIT> ) { return Offset + SlotSize ; } else { assert ( ( - ( Offset + StackSize ) ) % MFI . getObjectAlignment ( FI ) == <NUM_LIT> ) ; return Offset + StackSize ; } } else { if ( ! HasFP ) return Offset + StackSize ; Offset += SlotSize ; int TailCallReturnAddrDelta = MMFI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) Offset -= TailCallReturnAddrDelta ; }


<s> void setStackAlignBasePhysReg ( unsigned R ) {


<s> unsigned int i ; unsigned int count = ( high - low ) + <NUM_LIT> ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ;

XVECEXP ( vector , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , ( count - <NUM_LIT> ) * UNITS_PER_WORD ) ) ;


<s> if ( VT . isFloatingPoint ( ) ) { assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ; if ( ScalarSize == <NUM_LIT> ) Const = ConstantFP :: get ( Type :: getFloatTy ( C ) , Val . bitsToFloat ( ) ) ; else Const = ConstantFP :: get ( Type :: getDoubleTy ( C ) , Val . bitsToDouble ( ) ) ;

} else Const = Constant :: getIntegerValue ( Type :: getIntNTy ( C , ScalarSize ) , Val ) ;


<s> MachineOperand SrcRegOpnd = PseudoMI . getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII . get ( st_opc ) ) . add ( SrcRegOpnd ) . addImm ( <NUM_LIT> ) . addReg ( basePtr , false ) . addImm ( offset ) . addReg ( <STR_LIT> ) ; if ( SrcRegOpnd . getReg ( ) != <STR_LIT> ) { BuildMI ( MBB , II , DL , TII . get ( st_opc ) ) . add ( SrcRegOpnd ) . addImm ( <NUM_LIT> ) . addReg ( basePtr , false ) . addImm ( offset ) . addReg ( <STR_LIT> ) ; } } break ; case <STR_LIT> :


<s> int64_t Value = ConstExpr -> getValue ( ) ;

return ( Value != <NUM_LIT> ) && ( ( Value & ~ <NUM_LIT> ) == <NUM_LIT> ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitializeDirectXTarget ( ) { RegisterTargetMachine < DirectXTargetMachine > X ( getTheDirectXTarget ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performMinMaxCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned Opc = N -> getOpcode ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && VT != <STR_LIT> && ( ( VT != <STR_LIT> && VT != <STR_LIT> ) || Subtarget -> hasMin3Max3_16 ( ) ) ) { if ( Op0 . getOpcode ( ) == Opc && Op0 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op1 ) ; } if ( Op1 . getOpcode ( ) == Opc && Op1 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; } } if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , true ) ) return Med3 ; } if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , false ) ) return Med3 ; }

if ( ( ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) ) && ( VT == <STR_LIT> || VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> has16BitInsts ( ) ) ) && Op0 . hasOneUse ( ) ) {


<s> WasmPEI ( ) : MachineFunctionPass ( ID ) { initializeWasmPEIPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> rtx tmp = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_fmt_ee ( GTU , Pmode , avl , const0_rtx ) ) ) ; return tmp ; }


<s> static bool CC_<ISA_LIT>_AAPCS_Custom_f64 ( unsigned & ValNo , EVT & ValVT , EVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { if ( ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ; if ( LocVT == <STR_LIT> && ! f64AssignAAPCS ( ValNo , ValVT , LocVT , LocInfo , State , false ) ) return false ;


<s> static int getEquivalentCallShort ( int Opcode ) { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ;

assert ( VA . isRegLoc ( ) && <STR_LIT> ) ;


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) {

if ( ! RM . hasValue ( ) ) return Reloc :: Static ;


<s> for ( auto I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; I = Next ) { MachineInstr & MI = * I ; Next = std :: next ( I ) ; if ( SpillToAGPR && TII -> isVGPRSpill ( MI ) ) { unsigned FIOp = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vaddr ) ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; Register VReg = TII -> getNamedOperand ( MI , <STR_LIT> :: vdata ) -> getReg ( ) ; if ( FuncInfo -> allocateVGPRSpillToAGPR ( MF , FI , TRI -> isAGPR ( MRI , VReg ) ) ) { NewReservedRegs = true ; if ( ! RS ) RS . reset ( new RegScavenger ( ) ) ; RS -> enterBasicBlock ( MBB ) ; TRI -> eliminateFrameIndex ( MI , <NUM_LIT> , FIOp , RS . get ( ) ) ; SpillFIs . set ( FI ) ; continue ; } } if ( ! TII -> isSGPRSpill ( MI ) || ! TRI -> spillSGPRToVGPR ( ) ) continue ; int FI = TII -> getNamedOperand ( MI , <STR_LIT> :: addr ) -> getIndex ( ) ; assert ( MFI . getStackID ( FI ) == TargetStackID :: SGPRSpill ) ; if ( FuncInfo -> allocateSGPRSpillToVGPR ( MF , FI ) ) { NewReservedRegs = true ; bool Spilled = TRI -> eliminateSGPRToVGPRSpillFrameIndex ( MI , FI , nullptr ) ; ( void ) Spilled ; assert ( Spilled && <STR_LIT> ) ; SpillFIs . set ( FI ) ; }


<s> const <ISA_LIT>Subtarget & getSubtarget ( ) const {


<s> Inst . addOperand ( MCOperand :: createImm ( crm ) ) ; bool ValidNamed ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; ( void ) <STR_LIT> ( ) . toString ( pstate_field , Dis -> getSubtargetInfo ( ) . getFeatureBits ( ) , ValidNamed ) ; return ValidNamed ? Success : Fail ;


<s> Units &= RG . Units ; return * this ;


<s> bool UndefUppers = UpperElts > <NUM_LIT> && isUndefInRange ( Mask , NumSrcElts , UpperElts ) ; MVT ConcatVT = <STR_LIT> ( VT . getScalarType ( ) , NumElts * <NUM_LIT> ) ; SDValue Src = DAG . getNode ( <STR_LIT> , DL , ConcatVT , V1 , V2 ) ; MVT SrcSVT = <STR_LIT> ( SrcEltBits ) ; MVT SrcVT = <STR_LIT> ( SrcSVT , NumSrcElts ) ; Src = DAG . getBitcast ( SrcVT , Src ) ; return getAVX512TruncNode ( DL , VT , Src , Subtarget , DAG , ! UndefUppers ) ; } return SDValue ( ) ;


<s> for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , <NUM_LIT> ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable ( ) ;


<s> return & * I ; } ++ NumCmpTermRejs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; return nullptr ; } for ( MachineBasicBlock :: iterator B = MBB -> begin ( ) ; I != B ; ) { -- I ; assert ( ! I -> isTerminator ( ) && <STR_LIT> ) ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) || ! isUInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumImmRangeRejs ; return nullptr ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> :


<s> <ISA_LIT>LDBackend :: <ISA_LIT>LDBackend ( const LinkerConfig & pConfig , <ISA_LIT>GNUInfo * pInfo ) : GNULDBackend ( pConfig , pInfo ) , m_pRelocator ( NULL ) , m_pGOT ( NULL ) , m_pGOTPLT ( NULL ) , m_pPLT ( NULL ) , m_pRelaDyn ( NULL ) , m_pRelaPLT ( NULL ) , m_pDynamic ( NULL ) , m_pGOTSymbol ( NULL ) , m_CopyRel ( llvm :: ELF :: R_HEX_COPY ) {


<s> void addFGR32AsmRegOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ;

Register BaseReg = TRI -> getBaseRegister ( ) ;


<s> b = ( __vector unsigned char ) vec_splats ( __m2 ) ; c = vec_adds ( a , b ) ; return ( __m64 ) ( ( __vector long long ) c ) [ <NUM_LIT> ] ;


<s>
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printMBBReference
(
*
C
.
LB
)
<<
<STR_LIT>
)
;
std
::
vector
<
PhiInfo
>
Phis
;
for
(
auto
&
I
:
*
C
.
LB
)
{
if
(
!
I
.
isPHI
(
)
)
break
;
unsigned
PR
=
getDefReg
(
&
I
)
;
if
(
isConst
(
PR
)
)
continue
;
bool
BadUse
=
false
,
GoodUse
=
false
;
for
(
const
MachineOperand
&
MO
:
MRI
->
use_operands
(
PR
)
)
{
const
MachineInstr
*
UseI
=
MO
.
getParent
(
)
;
if
(
UseI
->
getParent
(
)
!=
C
.
LB
)
{
BadUse
=
true
;
break
;
}
if
(
isBitShuffle
(
UseI
,
PR
)
||
isStoreInput
(
UseI
,
PR
)
)
GoodUse
=
true
;
}
if
(
BadUse
||
!
GoodUse
)
continue
;
Phis
.
push_back
(
PhiInfo
(
I
,
*
C
.
LB
)
)
;
}
LLVM_DEBUG
(
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
&
I
:
Phis
)
{
dbgs
(
)
<<
' '
<<
printReg
(
I
.
DefR
,
HRI
)
<<
<STR_LIT>
<<
printReg
(
I
.
PR
.
Reg
,
HRI
,
I
.
PR
.
Sub
)
<<
<STR_LIT>
<<
I
.
PB
->
getNumber
(
)
<<
','
<<
printReg
(
I
.
LR
.
Reg
,
HRI
,
I
.
LR
.
Sub
)
<<
<STR_LIT>
<<
I
.
LB
->
getNumber
(
)
<<
')'
;
}


<s> if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ;

else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode ) ) return true ;


<s> assert ( SubTargetInfo ) ; bool Changed = false ; if ( const InstructionInfo * Info = getSwitchesForMnemonic ( Mnemonic , Slot ) ) { auto Sws = getApplicableSwitches ( Info , SubTargetInfo -> getFeatureBits ( ) , Type ) ; for ( auto SwPtr : Sws ) { if ( ( ( SwPtr -> Default ) & ~ PrintFlagMask ) == <NUM_LIT> ) continue ; if ( std :: find ( Switches . begin ( ) , Switches . end ( ) , SwPtr -> Name ) != Switches . end ( ) ) continue ; if ( ! meetsDependencies ( CurrentSwitchSet , SwPtr , Sws ) ) continue ; CurrentSwitchSet |= ( SwPtr -> Default ) & ~ PrintFlagMask ; Changed = true ; }


<s> if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = <NUM_LIT> ; return Result ;


<s> void <ISA_LIT>JITInfo :: relocate ( void * Function , MachineRelocation * MR , unsigned NumRelocs , unsigned char * GOTBase ) { for ( unsigned i = <NUM_LIT> ; i != NumRelocs ; ++ i , ++ MR ) { void * RelocPos = ( char * ) Function + MR -> getMachineCodeOffset ( ) ; intptr_t ResultPtr = ( intptr_t ) MR -> getResultPointer ( ) ; switch ( ( <STR_LIT> ) MR -> getRelocationType ( ) ) { case <STR_LIT> : { ResultPtr = ResultPtr - ( intptr_t ) RelocPos - <NUM_LIT> - MR -> getConstantVal ( ) ; * ( ( unsigned * ) RelocPos ) += ( unsigned ) ResultPtr ; break ; }


<s> return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ;

Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ;


<s> operands [ <NUM_LIT> ] = GEN_INT ( n_bytes % <NUM_LIT> ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; } return <STR_LIT> ; case <NUM_LIT> : operands [ <NUM_LIT> ] = GEN_INT ( n_bytes - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( n_bytes % <NUM_LIT> ) ; if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; } return <STR_LIT> ; case <NUM_LIT> : operands [ <NUM_LIT> ] = GEN_INT ( n_bytes - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) { if ( n_bytes % <NUM_LIT> >= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; } return <STR_LIT> ; case <NUM_LIT> : operands [ <NUM_LIT> ] = GEN_INT ( n_bytes - <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( n_bytes % <NUM_LIT> != <NUM_LIT> ) output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; default : gcc_unreachable ( ) ;


<s> unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ;


<s> static const unsigned RegClassIDs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;

return createTupleImpl ( CurDAG , Regs , RegClassIDs [ NF - <NUM_LIT> ] , <STR_LIT> ) ;


<s> } ( * targetm . asm_out . internal_label ) ( file , <STR_LIT> , labelno ) ; if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) == TFmode ) { REAL_VALUE_TYPE rv ; long k [ <NUM_LIT> ] ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , x ) ; REAL_VALUE_TO_TARGET_LONG_DOUBLE ( rv , k ) ; if ( TARGET_64BIT ) { if ( TARGET_MINIMAL_TOC ) fputs ( DOUBLE_INT_ASM_OP , file ) ; else fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; return ; } else { if ( TARGET_MINIMAL_TOC ) fputs ( <STR_LIT> , file ) ; else fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; return ; } } else if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) == DFmode ) { REAL_VALUE_TYPE rv ; long k [ <NUM_LIT> ] ; REAL_VALUE_FROM_CONST_DOUBLE ( rv , x ) ; REAL_VALUE_TO_TARGET_DOUBLE ( rv , k ) ; if ( TARGET_64BIT ) { if ( TARGET_MINIMAL_TOC ) fputs ( DOUBLE_INT_ASM_OP , file ) ; else fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; return ; } else { if ( TARGET_MINIMAL_TOC ) fputs ( <STR_LIT> , file ) ; else fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> , k [ <NUM_LIT> ] & <NUM_LIT> ) ; return ; } } else if ( GET_CODE ( x ) == CONST_DOUBLE && GET_MODE ( x ) == SFmode ) {


<s> return Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getMetadata ( ) ) ;


<s> OutStreamer -> PushSection ( ) ; MCSectionELF * M = OutContext . getELFSection ( <STR_LIT> + std :: string ( Symbol ) , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_EXECINSTR ) ; OutStreamer -> SwitchSection ( M , nullptr ) ; OutStreamer -> EmitValueToAlignment ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ; TS . emitDirectiveSetNo<ISA_LIT>16 ( ) ; TS . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; std :: string x = <STR_LIT> + std :: string ( Symbol ) ; MCSymbolELF * Stub = cast < MCSymbolELF > ( OutContext . getOrCreateSymbol ( StringRef ( x ) ) ) ; TS . emitDirectiveEnt ( * Stub ) ; MCSymbol * MType = OutContext . getOrCreateSymbol ( <STR_LIT> + Twine ( Symbol ) ) ; OutStreamer -> EmitSymbolAttribute ( MType , MCSA_ELF_TypeFunction ) ; OutStreamer -> EmitLabel ( Stub ) ; assert ( TM . getRelocationModel ( ) != Reloc :: PIC_ && <STR_LIT> ) ; TS . emitDirectiveSetReorder ( ) ; EmitInstrRegRegReg ( * STI , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; EmitSwapFPIntParams ( * STI , Signature -> ParamSig , LE , true ) ; EmitJal ( * STI , MSymbol ) ; EmitSwapFPIntRetval ( * STI , Signature -> RetSig , LE ) ; EmitInstrReg ( * STI , <STR_LIT> , <STR_LIT> ) ; MCSymbol * Tmp = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( Tmp ) ; const MCSymbolRefExpr * E = MCSymbolRefExpr :: create ( Stub , OutContext ) ; const MCSymbolRefExpr * T = MCSymbolRefExpr :: create ( Tmp , OutContext ) ; const MCExpr * T_min_E = MCBinaryExpr :: createSub ( T , E , OutContext ) ; OutStreamer -> emitELFSize ( Stub , T_min_E ) ; TS . emitDirectiveEnd ( x ) ; OutStreamer -> PopSection ( ) ;


<s> return - <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; bool HasMemOp4 = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; if ( HasMemOp4 ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> :


<s> int Size = Mask . size ( ) ; int LaneSize = Size / <NUM_LIT> ; if ( ! Subtarget . hasAVX2 ( ) ) { bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] / LaneSize ) ] = true ; if ( ! LaneUsed [ <NUM_LIT> ] || ! LaneUsed [ <NUM_LIT> ] ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > InLaneMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { int & M = InLaneMask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( ( ( M % Size ) / LaneSize ) != ( i / LaneSize ) ) M = ( M % LaneSize ) + ( ( i / LaneSize ) * LaneSize ) + Size ; } assert ( ! is128BitLaneCrossingShuffleMask ( VT , InLaneMask ) && <STR_LIT> ) ; MVT PVT = VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Flipped = DAG . getBitcast ( PVT , V1 ) ; Flipped = DAG . getVectorShuffle ( PVT , DL , Flipped , DAG . getUNDEF ( PVT ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; Flipped = DAG . getBitcast ( VT , Flipped ) ; return DAG . getVectorShuffle ( VT , DL , V1 , Flipped , InLaneMask ) ;


<s> if ( addPass ( & MachineSchedulerID ) ) printAndVerify ( <STR_LIT> ) ; addPass ( & StackSlotColoringID ) ; printAndVerify ( <STR_LIT> ) ;


<s> int64_t Imm = C -> getSExtValue ( ) ; SDLoc DL ( N ) ; if ( ( Imm >= - <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { Base = CurDAG -> getTargetConstant ( Imm , DL , Ty ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , Ty ) ; return true ; } if ( ( ( Imm % <NUM_LIT> ) == <NUM_LIT> ) && ( Imm >= - <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { Base = CurDAG -> getTargetConstant ( Imm / <NUM_LIT> , DL , Ty ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , Ty ) ; return true ;


<s> continue ; } if ( Op == <STR_LIT> ) { const SDValue & TruncInput = Arg . getOperand ( <NUM_LIT> ) ; if ( TruncInput . getOpcode ( ) == <STR_LIT> && cast < VTSDNode > ( TruncInput . getOperand ( <NUM_LIT> ) ) -> getVT ( ) == Arg . getValueType ( ) ) { Arg = TruncInput . getOperand ( <NUM_LIT> ) ; continue ; } } break ; } int FI = INT_MAX ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { unsigned VR = cast < RegisterSDNode > ( Arg . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( VR ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( VR ) ; if ( ! Def ) return false ; if ( ! Flags . isByVal ( ) ) { if ( ! TII -> isLoadFromStackSlot ( * Def , FI ) ) return false ; } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; } } else if ( LoadSDNode * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else if ( Arg . getOpcode ( ) == <STR_LIT> && Flags . isByVal ( ) ) { FrameIndexSDNode * FINode = cast < FrameIndexSDNode > ( Arg ) ; FI = FINode -> getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; assert ( FI != INT_MAX ) ; if ( ! MFI . isFixedObjectIndex ( FI ) ) return false ; if ( Offset != MFI . getObjectOffset ( FI ) ) return false ; if ( VA . getLocVT ( ) . getSizeInBits ( ) > Arg . getValueType ( ) . getSizeInBits ( ) ) { if ( Flags . isZExt ( ) != MFI . isObjectZExt ( FI ) || Flags . isSExt ( ) != MFI . isObjectSExt ( FI ) ) { return false ; }


<s> if ( Kind == KindTy :: Immediate ) return isVTypeImm ( <NUM_LIT> ) ;


<s> for ( unsigned i = memOpsEnd , e = memOps . size ( ) ; i != e ; ++ i ) { if ( memOps [ i ] . Position < insertPos && memOps [ i ] . isKill ) { unsigned Reg = memOps [ i ] . Reg ; KilledRegs . insert ( Reg ) ; Killer [ Reg ] = i ; } } SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { unsigned Reg = memOps [ i ] . Reg ; if ( UnavailRegs . count ( Reg ) ) return ; bool isKill = memOps [ i ] . isKill || KilledRegs . count ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; } MachineBasicBlock :: iterator Loc = memOps [ insertAfter ] . MBBI ; ++ Loc ; if ( ! MergeOps ( MBB , Loc , Offset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Regs ) ) return ; Merges . push_back ( prior ( Loc ) ) ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { if ( Regs [ i - memOpsBegin ] . second ) { unsigned Reg = Regs [ i - memOpsBegin ] . first ; if ( KilledRegs . count ( Reg ) ) { unsigned j = Killer [ Reg ] ; memOps [ j ] . MBBI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; memOps [ j ] . isKill = false ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; StringRef Arch = Parser . getTok ( ) . getString ( ) ; SMLoc ArchLoc = Parser . getTok ( ) . getLoc ( ) ; Lex ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) return Error ( ArchLoc , <STR_LIT> + Arch + <STR_LIT> ) ; if ( parseToken ( AsmToken :: EndOfStatement ) ) return true ; getTargetStreamer ( ) . emitObjectArch ( ID ) ;


<s> if ( mode == SImode ) fn = gen_store_conditional_si ; else if ( mode == DImode ) fn = gen_store_conditional_di ;

if ( PPC405_ERRATUM77 ) emit_insn ( gen_memory_barrier ( ) ) ;


<s> if ( const auto * F = dyn_cast < Function > ( GV ) ) { if ( F -> getSectionPrefix ( ) != Caller -> getSectionPrefix ( ) ) return false ; } if ( ! TM . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , GV ) ) return false ; return true ;


<s> operands [ n ] = operands [ n + <NUM_LIT> ] ; operands [ n + <NUM_LIT> ] = tem ; }


<s> case <STR_LIT> : ResultPtr = ( ResultPtr & <NUM_LIT> ) >> <NUM_LIT> ; * ( ( unsigned * ) RelocPos ) |= ( unsigned ) ResultPtr ; break ; case <STR_LIT> : ResultPtr = ResultPtr >> <NUM_LIT> ; if ( ( ( ( intptr_t ) ( MR -> getResultPointer ( ) ) & <NUM_LIT> ) >> <NUM_LIT> ) == <NUM_LIT> ) { ResultPtr += <NUM_LIT> ; } * ( ( unsigned * ) RelocPos ) |= ( unsigned ) ResultPtr ; break ; case <STR_LIT> : { int Addend = * ( ( unsigned * ) RelocPos ) & <NUM_LIT> ; ResultPtr = ( ResultPtr + Addend ) & <NUM_LIT> ;

* ( ( unsigned * ) RelocPos ) &= <NUM_LIT> ;


<s> assert ( Kind == k_Token && <STR_LIT> ) ;


<s> assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ;

CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;


<s> static SDValue LowerSCALAR_TO_VECTOR ( SDValue Op , SelectionDAG & DAG ) { SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( Op0 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = cast < ConstantSDNode > ( Op0 . getNode ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ConstVecValues ; EVT VT ; size_t n_copies ; switch ( Op . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; case <STR_LIT> : n_copies = <NUM_LIT> ; VT = <STR_LIT> ; break ; } SDValue CValue = DAG . getConstant ( CN -> getZExtValue ( ) , VT ) ; for ( size_t j = <NUM_LIT> ; j < n_copies ; ++ j ) ConstVecValues . push_back ( CValue ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , & ConstVecValues [ <NUM_LIT> ] , ConstVecValues . size ( ) ) ;


<s>
dbgs
(
)
<<
<STR_LIT>
;
for
(
std
::
pair
<
<ISA_LIT>ScheduleBlock
*
,
<ISA_LIT>ScheduleBlockLinkKind
>
S
:
Succs
)
{
if
(
S
.
second
==
<STR_LIT>
)
dbgs
(
)
<<
<STR_LIT>
;
S
.
first
->
printDebug
(
false
)
;
}
if
(
Scheduled
)
{
dbgs
(
)
<<
<STR_LIT>
<<
LiveInPressure
[
DAG
->
getSGPRSetID
(
)
]
<<
' '
<<
LiveInPressure
[
DAG
->
getVGPRSetID
(
)
]
<<
'\n'
;
dbgs
(
)
<<
<STR_LIT>
<<
LiveOutPressure
[
DAG
->
getSGPRSetID
(
)
]
<<
' '
<<
LiveOutPressure
[
DAG
->
getVGPRSetID
(
)
]
<<
<STR_LIT>
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
LiveInRegs
)
dbgs
(
)
<<
printVRegOrUnit
(
Reg
,
DAG
->
getTRI
(
)
)
<<
' '
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
LiveOutRegs
)
dbgs
(
)
<<
printVRegOrUnit
(
Reg
,
DAG
->
getTRI
(
)
)
<<
' '
;
}
dbgs
(
)
<<
<STR_LIT>
;
if
(
!
Scheduled
)
{
for
(
SUnit
*
SU
:
SUnits
)
{
SU
->
dump
(
DAG
)
;
}
}
else
{
for
(
SUnit
*
SU
:
SUnits
)
{
SU
->
dump
(
DAG
)
;
}
}


<s> bool <ISA_LIT>FixupHwLoops :: fixupLoopInstrs ( MachineFunction & MF ) { unsigned InstOffset = <NUM_LIT> ; DenseMap < const MachineBasicBlock * , unsigned > BlockToInstOffset ; const <ISA_LIT>InstrInfo * HII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; for ( const MachineBasicBlock & MBB : MF ) { if ( MBB . getAlignment ( ) ) { int ByteAlign = ( <NUM_LIT> << MBB . getAlignment ( ) ) - <NUM_LIT> ; InstOffset = ( InstOffset + ByteAlign ) & ~ ( ByteAlign ) ; } BlockToInstOffset [ & MBB ] = InstOffset ; for ( const MachineInstr & MI : MBB ) InstOffset += HII -> getSize ( MI ) ; } bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { InstOffset = BlockToInstOffset [ & MBB ] ; MachineBasicBlock :: iterator MII = MBB . begin ( ) ; MachineBasicBlock :: iterator MIE = MBB . end ( ) ; while ( MII != MIE ) { unsigned InstSize = HII -> getSize ( * MII ) ; if ( MII -> isMetaInstruction ( ) ) { ++ MII ; continue ; } if ( isHardwareLoop ( * MII ) ) { assert ( MII -> getOperand ( <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ; MachineBasicBlock * TargetBB = MII -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned Diff = AbsoluteDifference ( InstOffset , BlockToInstOffset [ TargetBB ] ) ; if ( Diff > MaxLoopRange ) { useExtLoopInstr ( MF , MII ) ; MII = MBB . erase ( MII ) ; Changed = true ; } else { ++ MII ; } } else { ++ MII ;


<s> switch ( TLInfo . getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Kernel : case CodeModel :: Small : return true ; default : return false ;


<s> void <ISA_LIT>Section :: anchor ( ) {


<s> SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! <ISA_LIT>SubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ;


<s> if ( Family == <NUM_LIT> || Family == <NUM_LIT> ) { if ( Family == <NUM_LIT> ) Family += ( EAX >> <NUM_LIT> ) & <NUM_LIT> ; Model += ( ( EAX >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; }


<s> bool <ISA_LIT>Subtarget :: useConstantIslands ( ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>16ConstantIslands << <STR_LIT> ) ; return <ISA_LIT>16ConstantIslands ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerToPredicatedOp ( SDValue Op , SelectionDAG & DAG , unsigned NewOp ) const { EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isScalableVector ( ) && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isScalableVector ( ) && <STR_LIT> ) ; auto PredTy = VT . getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorElementCount ( ) ) ; SDValue Mask = getPTrue ( DAG , DL , PredTy , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Mask } ; Operands . append ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; return DAG . getNode ( NewOp , DL , VT , Operands ) ;