<s> UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; CondBranches . push_back ( I ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto NewTBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( OldBranchCode == BranchCode && TBB == NewTBB ) continue ; if ( TBB == NewTBB && ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) ) { BranchCode = <STR_LIT> ; } else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) {

if ( NewTBB != ( FBB ? FBB : getFallThroughMBB ( & MBB , TBB ) ) ) return true ;


<s> virtual void initializePass ( ) override {


<s> static std :: unique_ptr < <ISA_LIT>Operand > createACCReg ( unsigned Index , StringRef Str , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { return CreateReg ( Index , Str , RegKind_ACC , RegInfo , S , E , Parser ) ;


Inst . addOperand ( MCOperand :: createImm ( Value + Offset ) ) ;


<s> if ( Element . getTag ( ) == dwarf :: DW_TAG_subrange_type ) { TypeNo = TypeNo << <STR_LIT> ; TypeNo = TypeNo | <STR_LIT> ; DISubrange SubRange = DISubrange ( Element . getGV ( ) ) ; Dimension [ i ] = SubRange . getHi ( ) - SubRange . getLo ( ) + <NUM_LIT> ; Aux [ <NUM_LIT> + i * <NUM_LIT> + <NUM_LIT> ] = Dimension [ i ] ; Aux [ <NUM_LIT> + i * <NUM_LIT> + <NUM_LIT> ] = Dimension [ i ] >> <NUM_LIT> ; size = size * Dimension [ i ] ; } } HasAux = true ; Aux [ <NUM_LIT> ] = size ; Aux [ <NUM_LIT> ] = size >> <NUM_LIT> ; DIType BaseType = CTy . getTypeDerivedFrom ( ) ; PopulateDebugInfo ( BaseType , TypeNo , HasAux , Aux , TypeName ) ; break ; } case dwarf :: DW_TAG_union_type : case dwarf :: DW_TAG_structure_type : { DICompositeType CTy = DICompositeType ( Ty . getGV ( ) ) ; TypeNo = TypeNo << <STR_LIT> ; if ( Ty . getTag ( ) == dwarf :: DW_TAG_structure_type ) TypeNo = TypeNo | <STR_LIT> ; else TypeNo = TypeNo | <STR_LIT> ; CTy . getName ( TypeName ) ; unsigned size = CTy . getSizeInBits ( ) / <NUM_LIT> ; HasAux = true ;


<s> int Base = ( int ) fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( CPURegsTable [ Reg ] ) ) ; Inst . addOperand ( MCOperand :: createReg ( CPURegsTable [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler :: Success ;


<s> void <ISA_LIT>MCCodeEmitter :: EmitByte ( unsigned int Byte , raw_ostream & OS ) const { OS . write ( ( uint8_t ) Byte & <NUM_LIT> ) ;


<s> void setSRetReturnReg ( unsigned Reg ) {


<s> std :: ostringstream o ; o << getTagName ( PREFIX_SYMBOL ) << <STR_LIT> << num << <STR_LIT> ;


<s> if ( ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) || ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) ) { const MCInstrDesc & MCID = MI . getDesc ( ) ;

if ( MCID . TSFlags & <STR_LIT> && MO . isDead ( ) ) continue ;


<s> CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ;


<s> <ISA_LIT>HazardRecognizer ( const <ISA_LIT>InstrInfo * tii , const TargetSchedModel * SM ) : TII ( tii ) , SchedModel ( SM ) { Reset ( ) ;


<s> if ( mode == V16QImode ) lvx = gen_altivec_lvx_v16qi ( dest_exp , src_exp ) ; else if ( mode == V8HImode ) lvx = gen_altivec_lvx_v8hi ( dest_exp , src_exp ) ; else if ( mode == V8HFmode ) lvx = gen_altivec_lvx_v8hf ( dest_exp , src_exp ) ; else if ( mode == V4SImode ) lvx = gen_altivec_lvx_v4si ( dest_exp , src_exp ) ;

else if ( mode == V4SFmode ) lvx = gen_altivec_lvx_v4sf ( dest_exp , src_exp ) ;


<s> RC = & <STR_LIT> ; switch ( I -> getOpcode ( ) ) { case Instruction :: LShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: AShr : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; case Instruction :: Shl : OpReg = <STR_LIT> ; OpImm = <STR_LIT> ; break ; default : return false ; } } else { return false ; } EVT VT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( VT == <STR_LIT> || ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; if ( ConstantInt * CI = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) { unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( MBB , DL , TII . get ( OpImm ) , ResultReg ) . addReg ( Op0Reg ) . addImm ( CI -> getZExtValue ( ) & <NUM_LIT> ) ; UpdateValueMap ( I , ResultReg ) ; return true ; } unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ;

TII . copyRegToReg ( * MBB , MBB -> end ( ) , CReg , Op1Reg , RC , RC ) ;


<s> int NumElts = Mask . size ( ) ; int NumV2Elements = count_if ( Mask , [ NumElts ] ( int M ) { return M >= NumElts ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; if ( SDValue V = lowerShuffleWithUndefHalf ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV8F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> :

return lowerV8I64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ;


<s> const MachineOperand & MO = MI -> getOperand ( I ) ; OutMI . addOperand ( LowerOperand ( MO ) ) ; }

OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , Kind ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned RegNo = getReg ( ) ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) RegNo = getGR32FromGR64 ( RegNo ) ;

Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ;


<s> if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ;

if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 , getUndefRegState ( SrcIsUndef ) ) ;


<s> SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackIndex ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; FR = DAG . getZExtOrTrunc ( FR , DL , getPointerMemTy ( DAG . getDataLayout ( ) ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> } if ( MI . getOpcode ( ) != AMDGPU :: COPY || ! TargetRegisterInfo :: isVirtualRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) || ! TargetRegisterInfo :: isVirtualRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; const TargetRegisterClass * DstRC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DstRC == & AMDGPU :: VReg_1RegClass && TRI -> getCommonSubClass ( SrcRC , & AMDGPU :: SGPR_64RegClass ) ) { I1Defs . push_back ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: V_CNDMASK_B32_e64 ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; } else if ( TRI -> getCommonSubClass ( DstRC , & AMDGPU :: SGPR_64RegClass ) && SrcRC == & AMDGPU :: VReg_1RegClass ) { BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: V_CMP_NE_I32_e64 ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ;


<s> for ( Value * V : WorkList ) { Instruction * Inst = cast < Instruction > ( V ) ; IRBuilder < > Builder ( Inst ) ; switch ( Inst -> getOpcode ( ) ) { case Instruction :: Load : { Type * VecPtrTy = VectorTy -> getPointerTo ( AS . PRIVATE_ADDRESS ) ; Value * Ptr = Inst -> getOperand ( <NUM_LIT> ) ; Value * Index = calculateVectorIndex ( Ptr , GEPVectorIdx ) ; Value * BitCast = Builder . CreateBitCast ( Alloca , VecPtrTy ) ; Value * VecValue = Builder . CreateLoad ( BitCast ) ; Value * ExtractElement = Builder . CreateExtractElement ( VecValue , Index ) ; Inst -> replaceAllUsesWith ( ExtractElement ) ; Inst -> eraseFromParent ( ) ; break ; } case Instruction :: Store : { Type * VecPtrTy = VectorTy -> getPointerTo ( AS . PRIVATE_ADDRESS ) ; Value * Ptr = Inst -> getOperand ( <NUM_LIT> ) ; Value * Index = calculateVectorIndex ( Ptr , GEPVectorIdx ) ; Value * BitCast = Builder . CreateBitCast ( Alloca , VecPtrTy ) ; Value * VecValue = Builder . CreateLoad ( BitCast ) ; Value * NewVecValue = Builder . CreateInsertElement ( VecValue , Inst -> getOperand ( <NUM_LIT> ) , Index ) ; Builder . CreateStore ( NewVecValue , BitCast ) ; Inst -> eraseFromParent ( ) ; break ; } case Instruction :: BitCast : case Instruction :: AddrSpaceCast : break ; default : llvm_unreachable ( <STR_LIT> ) ; } }


<s> default : llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_MachineBasicBlock : report_fatal_error ( <STR_LIT> ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : report_fatal_error ( <STR_LIT> ) ; return ; case MachineOperand :: MO_ExternalSymbol : AddrSym = GetExternalSymbolSymbol ( Addr . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_GlobalAddress : AddrSym = getSymbol ( Addr . getGlobal ( ) ) ; break ; } MCOperand RegLR = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand RegS0 = MCOperand :: createReg ( <STR_LIT> ) ; MCOperand RegS12 = MCOperand :: createReg ( <STR_LIT> ) ;

MCSymbol * GetTLSLabel = OutContext . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ;


<s> UseMemOps = DisableMemOps ? false : EnableMemOps ; ModeIEEERndNear = EnableIEEERndNear ; UseBSBScheduling = hasV60TOps ( ) && EnableBSBSched ; ParseSubtargetFeatures ( CPUString , FS ) ; if ( OverrideLongCalls . getPosition ( ) ) UseLongCalls = OverrideLongCalls ; FeatureBitset Features = getFeatureBits ( ) ; if ( <ISA_LIT>DisableDuplex ) setFeatureBits ( Features . set ( <STR_LIT> , false ) ) ; setFeatureBits ( <ISA_LIT>_MC :: completeHVXFeatures ( Features ) ) ;


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return MatchOperand_ParseFail ; if ( Prefix == <STR_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Int ) || ! ( <NUM_LIT> <= Int && Int <= <NUM_LIT> ) ) return MatchOperand_ParseFail ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; int64_t Temp ; if ( getParser ( ) . parseAbsoluteExpression ( Temp ) || ! ( <NUM_LIT> <= Temp && Temp <= <NUM_LIT> ) ) return MatchOperand_ParseFail ; const int shift = i * <NUM_LIT> + <NUM_LIT> ; Int += ( Temp << shift ) ; } if ( getLexer ( ) . isNot ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; } else { Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Int ) ) return MatchOperand_ParseFail ; if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= DppCtrl :: ROW_SHL0 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= DppCtrl :: ROW_SHR0 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> <= Int && Int <= <NUM_LIT> ) { Int |= DppCtrl :: ROW_ROR0 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_SHL1 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_ROL1 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_SHR1 ; } else if ( Prefix == <STR_LIT> && <NUM_LIT> == Int ) { Int = DppCtrl :: WAVE_ROR1 ; } else if ( Prefix == <STR_LIT> ) { if ( Int == <NUM_LIT> ) { Int = DppCtrl :: BCAST15 ; } else if ( Int == <NUM_LIT> ) {


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; return true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( <STR_LIT> ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Op = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Op ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Subtarget . hasP9Vector ( ) ? <STR_LIT> : <STR_LIT> ; NewMIs . push_back ( addFrameReference ( BuildMI ( MF , DL , get ( Opc ) , DestReg ) , FrameIdx ) ) ; NonRI = true ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> unsigned getSGPRAllocGranule ( ) const {


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ LblOperand ] . OperandType != MCOI :: OPERAND_PCREL ) return - <NUM_LIT> ;

int64_t Imm = Inst . getOperand ( LblOperand ) . getImm ( ) ;


<s> static bool pa_print_operand_punct_valid_p ( unsigned char code ) {


<s> } case <STR_LIT> : I -> eraseFromParent ( ) ; break ; } I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) { return <NUM_LIT> ; } -- I ; switch ( I -> getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : { MachineInstr * predSet = findFirstPredicateSetterFrom ( MBB , I ) ; clearFlag ( * predSet , <NUM_LIT> , MO_FLAG_PUSH ) ; I -> eraseFromParent ( ) ; MachineBasicBlock :: iterator CfAlu = FindLastAluClause ( MBB ) ; if ( CfAlu == MBB . end ( ) ) break ; assert ( CfAlu -> getOpcode ( ) == <STR_LIT> ) ; CfAlu -> setDesc ( get ( <STR_LIT> ) ) ; break ; } case <STR_LIT> : I -> eraseFromParent ( ) ; break ; } return <NUM_LIT> ;


<s> return <ISA_LIT>ProcFamily == CortexM3 ;


<s> __arm_stc ( const unsigned int __coproc , const unsigned int __CRd , void * __p ) { return __builtin_arm_stc ( __coproc , __CRd , __p ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( ( VT == <STR_LIT> && Subtarget . hasSSE2 ( ) ) || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSE41 ( ) ) ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue V ; bool First = true ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { bool IsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ! IsNonZero ) continue ; if ( First ) { First = false ; if ( NumZero || <NUM_LIT> != i ) V = getZeroVector ( VT , Subtarget , DAG , dl ) ; else { assert ( <NUM_LIT> == i && <STR_LIT> ) ; V = DAG . getAnyExtOrTrunc ( Op . getOperand ( i ) , dl , <STR_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ;


<s> if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned NumBytes = AFI -> getLocalStackSize ( ) ; if ( MFI -> hasCalls ( ) || hasFP ( MF ) || NumBytes > <NUM_LIT> ) return false ; return true ;


<s> const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( MI , IsSelfLoop ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; if ( MCID . getOpcode ( ) == <STR_LIT> ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsDef ( true ) ; MIB -> getOperand ( <NUM_LIT> ) . setIsDead ( true ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) MIB . add ( HasCC ? t1CondCodeOp ( CCDead ) : condCodeOp ( ) ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ;

bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ;


<s> if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) || isAAPCS16_ABI ( ) ) stackAlignment = <NUM_LIT> ; SupportsTailCall = ! isThumb ( ) || hasV8MBaselineOps ( ) ; if ( isTargetMachO ( ) && isTargetIOS ( ) && getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) SupportsTailCall = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ; if ( isRWPI ( ) ) ReserveR9 = true ; switch ( <ISA_LIT>ProcFamily ) { case Others : case CortexA5 : break ; case CortexA7 : LdStMultipleTiming = DoubleIssue ; break ; case CortexA8 : LdStMultipleTiming = DoubleIssue ; break ;


<s> MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , Next , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * TLSBaseAddrReg ) . addReg ( is64Bit ? <STR_LIT> : <STR_LIT> ) ; return Copy ;


<s> static const unsigned SpillOffsTab [ ] [ <NUM_LIT> ] = { { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> } } ; RegSpillOffsets . grow ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = array_lengthof ( SpillOffsTab ) ; i != e ; ++ i ) RegSpillOffsets [ SpillOffsTab [ i ] [ <NUM_LIT> ] ] = SpillOffsTab [ i ] [ <NUM_LIT> ] ;


<s> PM . add ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) PM . add ( createThumb2ITBlockPass ( ) ) ; return true ;


<s> bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : getSymbol ( MO . getGlobal ( ) ) -> print ( O , MAI ) ; break ; case MachineOperand :: MO_BlockAddress : { MCSymbol * BA = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; O << BA -> getName ( ) ; break ; } case MachineOperand :: MO_ConstantPoolIndex : O << getDataLayout ( ) . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; if ( MO . getOffset ( ) ) O << <STR_LIT> << MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> CONSTEXPR inc_dec_base ( bool pat_p ) : m_pat_p ( pat_p ) {


<s> if ( ! isGPRMem ( ) ) return false ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ;

return Memory . OffsetRegNum == <NUM_LIT> && Memory . OffsetImm == nullptr && ( alignOK || Memory . Alignment == Alignment ) ;


<s> tree base = get_inner_reference ( t , & bitsize , & bitpos , & var_off , & mode , & sign , & reverse , & vol ) ; if ( TREE_CODE ( base ) == MEM_REF ) { return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( base ) ) ) ; } if ( TREE_CODE ( t ) == COMPONENT_REF ) { const tree op = TREE_OPERAND ( t , <NUM_LIT> ) ; if ( TREE_CODE ( op ) == COMPONENT_REF ) return is_attr_preserve_access ( op ) ; const tree container = DECL_CONTEXT ( TREE_OPERAND ( t , <NUM_LIT> ) ) ; return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( container ) ) ; } else if ( TREE_CODE ( t ) == ADDR_EXPR ) return is_attr_preserve_access ( TREE_OPERAND ( t , <NUM_LIT> ) ) ; return false ;


<s> static void emitRegUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned Reg , int NumBytes , bool IsAdd , const <ISA_LIT>InstrInfo * TII ) { unsigned Opc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII -> get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( NumBytes ) ;


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; Register Reg = <STR_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> static void sh_file_start ( void ) { default_file_start ( ) ; fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; if ( TARGET_ELF ) fprintf ( asm_out_file , <STR_LIT> , TEXT_SECTION_ASM_OP ) ; else data_section ( ) ; if ( TARGET_LITTLE_ENDIAN ) fputs ( <STR_LIT> , asm_out_file ) ; if ( ! TARGET_ELF ) { if ( TARGET_SHCOMPACT ) fputs ( <STR_LIT> , asm_out_file ) ;


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , bool Fast , raw_ostream & Out ) { PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , Fast ) ) ; return false ;


<s> switch ( set2 -> base ) { case ISA_BASE_LA64V100 : return ( set1 -> base == ISA_BASE_LA64V100 ) ; default : gcc_unreachable ( ) ; }


<s> return MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , getContext ( ) ) ;


<s> if ( ! current_function_is_leaf ) all = true ; for ( i = REG_CC - <NUM_LIT> ; i > REG_P7 ; i -- ) if ( all || regs_ever_live [ i ] || ( ! leaf_function_p ( ) && call_used_regs [ i ] ) ) { if ( i == REG_A0 || i == REG_A1 ) { rtx mem = gen_rtx_MEM ( PDImode , postinc1 ) ; MEM_VOLATILE_P ( mem ) = <NUM_LIT> ; emit_move_insn ( gen_rtx_REG ( PDImode , i ) , mem ) ; } else emit_move_insn ( gen_rtx_REG ( SImode , i ) , postinc ) ;


return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> Ret += <STR_LIT> ; Ret += <STR_LIT> ;


<s> return ( ( bytes + PARM_BOUNDARY / <NUM_LIT> - <NUM_LIT> ) & ( - PARM_BOUNDARY / <NUM_LIT> ) ) ;


<s> else if ( FP_REGNO_P ( regno ) ) { if ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) && GET_MODE_UNIT_SIZE ( mode ) <= TARGET_FP_REG_SIZE ) return true ; } return false ;


<s> assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ; if ( StoreNode -> isTruncatingStore ( ) || StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ;


<s> case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ;

case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ;


<s> getReadTimeStampCounter ( Op . getNode ( ) , DL , <STR_LIT> , DAG , Subtarget , Results ) ; return DAG . getMergeValues ( Results , DL ) ;


<s> if ( TARGET_HARD_FLOAT ) { count = <NUM_LIT> ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += <NUM_LIT> ) { if ( ( ! df_regs_ever_live_p ( regno ) || call_used_regs [ regno ] ) && ( ! df_regs_ever_live_p ( regno + <NUM_LIT> ) || call_used_regs [ regno + <NUM_LIT> ] ) ) { if ( count > <NUM_LIT> ) { if ( count == <NUM_LIT> && ! arm_arch6 ) count ++ ; saved += count * <NUM_LIT> ; } count = <NUM_LIT> ;


<s> return __builtin_mve_vcreateq_sv2di ( __a , __b ) ;


<s> OperandMatchResultTy parseFP32 ( OperandVector & Operands ) {

return parseRegister ( Operands , RegFP , <STR_LIT> , FP32Reg ) ;


<s> if ( V -> getType ( ) == Type :: FloatTy ) { unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; }


<s> static HOST_WIDE_INT round_frame_size ( HOST_WIDE_INT size ) {

return ( ( size + STACK_BOUNDARY / BITS_PER_UNIT - <NUM_LIT> ) & - STACK_BOUNDARY / BITS_PER_UNIT ) ;


<s> MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( Type == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; unsigned SrcNOps = <NUM_LIT> ; if ( FusedOpcode == <STR_LIT> || FusedOpcode == <STR_LIT> ) SrcNOps = <NUM_LIT> ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ; for ( unsigned I = <NUM_LIT> ; I < SrcNOps ; I ++ ) MIB . add ( Compare . getOperand ( I ) ) ; MIB . add ( CCMask ) ; if ( Type == <STR_LIT> ) { MIB . add ( Target ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ;


<s> return Op . getOpcode ( ) == <STR_LIT> && isNullConstant ( Op . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getDataLayout ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ;

} else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) {


<s> bool is<ISA_LIT>64 = TheTriple . getArch ( ) == Triple :: ppc64 ; MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( is<ISA_LIT>64 ) ; else MAI = new <ISA_LIT>LinuxMCAsmInfo ( is<ISA_LIT>64 ) ; MachineLocation Dst ( MachineLocation :: VirtualFP ) ; MachineLocation Src ( <STR_LIT> , <NUM_LIT> ) ; MAI -> addInitialFrameState ( <NUM_LIT> , Dst , Src ) ; return MAI ;


<s> unsigned const16 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ;

if ( status != MCDisassembler :: Success ) return status ;


<s> void emitLocalEntry ( MCSymbol * S , const MCExpr * LocalOffset ) override {


<s> static unsigned int sparc_min_arithmetic_precision ( void ) {


<s> unsigned <ISA_LIT>RegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC , const MachineFunction & MF ) const { for ( unsigned Reg : * RC ) if ( MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) ) return Reg ;


<s> return ( uint8x16_t ) __builtin_neon_vminuv16qi ( ( int8x16_t ) __a , ( int8x16_t ) __b ) ;


<s> if ( Subtarget -> isFPOnlySP ( ) && VT == <STR_LIT> ) { FalseVal = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , FalseVal ) ; TrueVal = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , TrueVal ) ; SDValue TrueLow = TrueVal . getValue ( <NUM_LIT> ) ; SDValue TrueHigh = TrueVal . getValue ( <NUM_LIT> ) ; SDValue FalseLow = FalseVal . getValue ( <NUM_LIT> ) ; SDValue FalseHigh = FalseVal . getValue ( <NUM_LIT> ) ; SDValue Low = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseLow , TrueLow , <ISA_LIT>cc , CCR , Cmp ) ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FalseHigh , TrueHigh , <ISA_LIT>cc , CCR , duplicateCmp ( Cmp , DAG ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Low , High ) ;


<s> Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsHigh = <STR_LIT> ( Reg ) ; MI . setDesc ( get ( IsHigh ? HighOpcode : LowOpcode ) ) ;

if ( IsHigh && ConvertHigh ) MI . getOperand ( <NUM_LIT> ) . setImm ( uint32_t ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ;


<s> pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( pat ) != SET || SET_DEST ( pat ) != pc_rtx ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == LABEL_REF ) { label = & SET_SRC ( pat ) ; } else if ( GET_CODE ( SET_SRC ( pat ) ) == IF_THEN_ELSE ) { if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) == LABEL_REF ) label = & XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) == LABEL_REF ) label = & XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; else continue ; } else continue ; if ( get_attr_length ( insn ) <= <NUM_LIT> ) continue ; cfun_frame_layout . save_return_addr_p = <NUM_LIT> ; if ( ! flag_pic ) { new_literal = <NUM_LIT> ; rtx mem = force_const_mem ( Pmode , * label ) ; rtx_insn * set_insn = emit_insn_before ( gen_rtx_SET ( temp_reg , mem ) , insn ) ;


<s> if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } unsigned prfop = MCE -> getValue ( ) ; if ( prfop > <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = <STR_LIT> ( MCE -> getValue ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreatePrefetch ( prfop , PRFM ? PRFM -> Name : <STR_LIT> , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PRFM = <STR_LIT> ( Tok . getString ( ) ) ; if ( ! PRFM ) { TokError ( <STR_LIT> ) ;


<s> Align Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getAlignValue ( ) ; auto * Ty = cast < FixedVectorType > ( Input -> getType ( ) ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ;

Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ;


<s> printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ;


<s> void <ISA_LIT>InstPrinter :: printAbsAddrOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {

O << ( int ) MI -> getOperand ( OpNo ) . getImm ( ) * <NUM_LIT> ;


<s> <ISA_LIT>ReplacePhysRegs ( ) : MachineFunctionPass ( ID ) {


<s> SDValue AMDGPUTargetLowering :: LowerSDIV ( SDValue Op , SelectionDAG & DAG ) const { EVT OVT = Op . getValueType ( ) . getScalarType ( ) ;

if ( OVT == <STR_LIT> ) return LowerSDIV64 ( Op , DAG ) ;


<s> <ISA_LIT>ObjectWriter :: <ISA_LIT>ObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( true , OSABI , ELF :: EM_S390 , true ) {


<s> std :: string llvm :: getSurfaceName ( const llvm :: Value & val ) {

assert ( val . hasName ( ) && <STR_LIT> ) ;


<s> cmp = gen_rtx_fmt_ee ( code , VOIDmode , pc_rtx , const0_rtx ) ; if ( boolean_operator ( cmp , VOIDmode ) ) { if ( op0 == const0_rtx ) { op0 = op1 ; op1 = const0_rtx ; } if ( op1 != const0_rtx ) { op0 = expand_binop ( SImode , sub_optab , op0 , op1 , <NUM_LIT> , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; op1 = const0_rtx ; } } else if ( branch_operator ( cmp , VOIDmode ) ) { if ( op0 == const0_rtx ) { op0 = op1 ; op1 = const0_rtx ; switch ( code ) {


<s> unsigned getMaskedMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace ) {


<s> char * p ; int first = <NUM_LIT> ; if ( live_regs_mask & ( <NUM_LIT> << SP_REGNUM ) ) { unsigned HOST_WIDE_INT stack_adjust ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; gcc_assert ( stack_adjust == <NUM_LIT> || stack_adjust == <NUM_LIT> ) ; if ( stack_adjust && arm_arch5t && TARGET_ARM ) sprintf ( instr , <STR_LIT> , conditional ) ; else { if ( stack_adjust ) live_regs_mask |= <NUM_LIT> << <NUM_LIT> ; sprintf ( instr , <STR_LIT> , conditional ) ; } } else if ( IS_INTERRUPT ( func_type ) ) sprintf ( instr , <STR_LIT> , conditional ) ; else sprintf ( instr , <STR_LIT> , conditional ) ; p = instr + strlen ( instr ) ; for ( reg = <NUM_LIT> ; reg <= SP_REGNUM ; reg ++ ) if ( live_regs_mask & ( <NUM_LIT> << reg ) ) { int l = strlen ( reg_names [ reg ] ) ; if ( first ) first = <NUM_LIT> ; else { memcpy ( p , <STR_LIT> , <NUM_LIT> ) ; p += <NUM_LIT> ; } memcpy ( p , <STR_LIT> , <NUM_LIT> ) ; memcpy ( p + <NUM_LIT> , reg_names [ reg ] , l ) ; p += l + <NUM_LIT> ; } if ( live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ) { sprintf ( p , <STR_LIT> , first ? <STR_LIT> : <STR_LIT> , return_reg ) ; if ( IS_INTERRUPT ( func_type ) ) strcat ( p , <STR_LIT> ) ; } else strcpy ( p , <STR_LIT> ) ; } output_asm_insn ( instr , & operand ) ; if ( really_return && func_type != ARM_FT_INTERWORKED && ( live_regs_mask & ( <NUM_LIT> << LR_REGNUM ) ) != <NUM_LIT> ) { return <STR_LIT> ; } } if ( really_return ) { switch ( ( int ) ARM_FUNC_TYPE ( func_type ) ) { case ARM_FT_ISR : case ARM_FT_FIQ : sprintf ( instr , <STR_LIT> , conditional ) ; break ; case ARM_FT_INTERWORKED : gcc_assert ( arm_arch5t || arm_arch4t ) ; sprintf ( instr , <STR_LIT> , conditional ) ; break ; case ARM_FT_EXCEPTION : sprintf ( instr , <STR_LIT> , conditional ) ; break ; default : if ( IS_CMSE_ENTRY ( func_type ) ) { if ( ! TARGET_HAVE_FPCXT_CMSE ) { if ( TARGET_INT_SIMD ) snprintf ( instr , sizeof ( instr ) , <STR_LIT> , conditional ) ; else snprintf ( instr , sizeof ( instr ) , <STR_LIT> , conditional ) ; output_asm_insn ( instr , & operand ) ; if ( TARGET_HARD_FLOAT ) { output_asm_insn ( <STR_LIT> , & operand ) ; output_asm_insn ( <STR_LIT> , & operand ) ; output_asm_insn ( <STR_LIT> , & operand ) ; output_asm_insn ( <STR_LIT> , & operand ) ; output_asm_insn ( <STR_LIT> , & operand ) ; output_asm_insn ( <STR_LIT> , & operand ) ; output_asm_insn ( <STR_LIT> , & operand ) ; output_asm_insn ( <STR_LIT> , & operand ) ; } } snprintf ( instr , sizeof ( instr ) , <STR_LIT> ) ; }

else if ( arm_arch5t || arm_arch4t ) sprintf ( instr , <STR_LIT> , conditional ) ;


<s> bool isConstantSplat ( SDValue Op , APInt & SplatVal ) { APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( Op , Op . getScalarValueSizeInBits ( ) , UndefElts , EltBits , true , false ) ) { int SplatIndex = - <NUM_LIT> ; for ( int i = <NUM_LIT> , e = EltBits . size ( ) ; i != e ; ++ i ) { if ( UndefElts [ i ] ) continue ;

if ( <NUM_LIT> <= SplatIndex && EltBits [ i ] != EltBits [ SplatIndex ] ) {


<s> static bool ix86_check_avx_upper_register ( const_rtx exp ) { if ( SUBREG_P ( exp ) ) exp = SUBREG_REG ( exp ) ; return ( REG_P ( exp ) && ( VALID_AVX256_REG_OR_OI_MODE ( GET_MODE ( exp ) ) || VALID_AVX512F_REG_OR_XI_MODE ( GET_MODE ( exp ) ) ) ) ;


<s> assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return emitSelectPseudo ( MI , BB ) ; case <STR_LIT> : return emitBuildPairF64Pseudo ( MI , BB ) ; case <STR_LIT> :


printOperand ( MI , opNum + <NUM_LIT> , O ) ;


<s> if ( GET_CODE ( part ) == SET ) RTX_FRAME_RELATED_P ( part ) = <NUM_LIT> ; XVECEXP ( note , <NUM_LIT> , i + <NUM_LIT> ) = part ; } } else { for ( i = XVECLEN ( x , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { part = XVECEXP ( x , <NUM_LIT> , i ) ; if ( GET_CODE ( part ) == SET ) RTX_FRAME_RELATED_P ( part ) = <NUM_LIT> ; } } }

else if ( GET_CODE ( x ) == SET && GET_MODE ( SET_DEST ( x ) ) == DImode ) note = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , frame_subreg_note ( x , <NUM_LIT> ) , frame_subreg_note ( x , UNITS_PER_WORD ) ) ) ;


<s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;


<s> if ( ! memOpsHaveSameBasePtr ( FirstLdSt , BaseOps1 , SecondLdSt , BaseOps2 ) ) return false ; const MachineOperand * FirstDst = nullptr ; const MachineOperand * SecondDst = nullptr ; if ( ( isMUBUF ( FirstLdSt ) && isMUBUF ( SecondLdSt ) ) || ( isMTBUF ( FirstLdSt ) && isMTBUF ( SecondLdSt ) ) || ( isFLAT ( FirstLdSt ) && isFLAT ( SecondLdSt ) ) ) { const unsigned MaxGlobalLoadCluster = <NUM_LIT> ; if ( NumLoads > MaxGlobalLoadCluster ) return false ; FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdata ) ; if ( ! FirstDst ) FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: vdst ) ; SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdata ) ; if ( ! SecondDst ) SecondDst = getNamedOperand ( SecondLdSt , <STR_LIT> :: vdst ) ; } else if ( isSMRD ( FirstLdSt ) && isSMRD ( SecondLdSt ) ) {

FirstDst = getNamedOperand ( FirstLdSt , <STR_LIT> :: sdst ) ;


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MustSaveTOC ) continue ; if ( isCalleeSavedCR ( Reg ) && ! Subtarget . is32BitELFABI ( ) ) continue ; if ( Reg == <STR_LIT> ) { CR2Spilled = true ; CSIIndex = i ; continue ; } else if ( Reg == <STR_LIT> ) { CR3Spilled = true ; continue ; } else if ( Reg == <STR_LIT> ) { CR4Spilled = true ; continue ; } else { if ( CR2Spilled || CR3Spilled || CR4Spilled ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } if ( CSI [ i ] . isSpilledToReg ( ) ) { DebugLoc DL ; NumPEReloadVSR ++ ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( CSI [ i ] . getDstReg ( ) , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && ! MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) TII . loadRegFromStackSlotNoUpd ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; else TII . loadRegFromStackSlot ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB . begin ( ) && <STR_LIT> ) ; } } if ( AtStart ) I = MBB . begin ( ) ; else { I = BeforeI ; ++ I ; } } if ( CR2Spilled || CR3Spilled || CR4Spilled ) { assert ( Subtarget . is32BitELFABI ( ) && <STR_LIT> ) ; bool is31 = needsFP ( * MF ) ; restoreCRs ( is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; }


<s> int NonInlineUseOpNo = - <NUM_LIT> ; MachineRegisterInfo :: use_iterator NextUse ; for ( MachineRegisterInfo :: use_iterator Use = MRI -> use_begin ( Dst . getReg ( ) ) , E = MRI -> use_end ( ) ; Use != E ; Use = NextUse ) { NextUse = std :: next ( Use ) ; MachineInstr * UseMI = Use -> getParent ( ) ; unsigned OpNo = Use . getOperandNo ( ) ; if ( OpToFold . isImm ( ) && tryConstantFoldOp ( * MRI , TII , UseMI , & OpToFold ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * UseMI << '\n' ) ; NextUse = MRI -> use_begin ( Dst . getReg ( ) ) ; FoldList . clear ( ) ; continue ; } if ( isInlineConstantIfFolded ( TII , * UseMI , OpNo , OpToFold ) ) { foldOperand ( OpToFold , UseMI , OpNo , FoldList , CopiesToReplace ) ; } else if ( frameIndexMayFold ( TII , * UseMI , OpNo , OpToFold ) ) { foldOperand ( OpToFold , UseMI , OpNo , FoldList , CopiesToReplace ) ; } else { if ( ++ NumLiteralUses == <NUM_LIT> ) { NonInlineUse = & * Use ; NonInlineUseOpNo = OpNo ; } } }


return hasPostRAScheduler ( OptLevel ) ;


<s> StringRef getPassName ( ) const override {


<s> unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op1 ) ; } SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , VTs , Op0 , Op1 ) ; return SDValue ( Sub . getNode ( ) , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , Op1 ) ;


<s> <ISA_LIT>BasicMCBuilder ( <ISA_LIT>BasicMCBuilder & B ) : Opcode ( B . Opcode ) , Format ( B . Format ) , NumOps ( B . NumOps ) , Disasm ( B . Disasm ) , SP ( B . SP ) {


<s> mode == SImode ? <NUM_LIT> : <NUM_LIT> ) ; if ( max && operator && GET_CODE ( x ) == CONST_INT ) { if ( unsigned_condition ( operator ) != operator ) max >>= <NUM_LIT> ; if ( max != ( INTVAL ( x ) & max ) && INTVAL ( x ) != <NUM_LIT> ) return <NUM_LIT> ; }


<s> bool isImmSExti64i8 ( ) const { if ( ! isImm ( ) ) return false ;

const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> FunctionPass * llvm :: createX87FPRegKillInserterPass ( ) { return new FPRegKiller ( ) ;


<s> MemberType = Members [ Loc ] . Type ; MemberOffset = HasBitField ? Members [ Loc ] . Offset & <NUM_LIT> : Members [ Loc ] . Offset ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OL ) : SelectionDAGISel ( tm , OL ) , Subtarget ( tm . getSubtarget ( ) ) {


<s> static bool castRequiresQueuePtr ( const AddrSpaceCastInst * ASC , const <ISA_LIT>AS & AS ) { return castRequiresQueuePtr ( ASC -> getSrcAddressSpace ( ) , AS ) ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & F ) const override {


<s> getExclusiveOperation ( Size , Ord , isThumb2 , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; } MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( scratch ) . addImm ( <NUM_LIT> ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( loopMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB -> addSuccessor ( exitMBB ) ;


<s> case <STR_LIT> : case <STR_LIT> : Valid = ( isUInt < <NUM_LIT> > ( v ) || v == - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Valid = isUInt < <NUM_LIT> > ( v ) ; break ; case <STR_LIT> : case <STR_LIT> : Valid = ( v == <NUM_LIT> ) ; break ; } if ( ! Valid ) return false ; } unsigned cmpReg1 , cmpOp2 = <NUM_LIT> ; cmpReg1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( secondReg ) { cmpOp2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( cmpReg1 == cmpOp2 ) return false ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( secondReg && ! TargetRegisterInfo :: isPhysicalRegister ( cmpOp2 ) ) { MachineInstr * def = MRI . getVRegDef ( cmpOp2 ) ; if ( def -> getOpcode ( ) == TargetOpcode :: COPY ) return false ; } } ++ II ; for ( MachineBasicBlock :: iterator localII = II ; localII != end ; ++ localII ) { if ( localII -> isDebugValue ( ) ) continue ; if ( ! commonChecksToProhibitNewValueJump ( optLocation , localII ) ) return false ; if ( localII -> modifiesRegister ( pReg , TRI ) || localII -> readsRegister ( pReg , TRI ) ) return false ; if ( localII -> modifiesRegister ( cmpReg1 , TRI ) || ( secondReg && localII -> modifiesRegister ( cmpOp2 , TRI ) ) ) return false ; } return true ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MII ) : InstrInfo ( MII ) {


<s> fpu_name = ( ptr -> x_arm_fpu_index == TARGET_FPU_auto ? <STR_LIT> : all_fpus [ ptr -> x_arm_fpu_index ] . name ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , TARGET_THUMB2_P ( flags ) ? <STR_LIT> :


<s> inline vector unsigned int vec_vsubuws ( vector unsigned int a1 , vector unsigned int a2 ) { return ( vector unsigned int ) __builtin_altivec_vsubuws ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) return false ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> bool <ISA_LIT>AnnotateUniformValues :: isClobberedInFunction ( LoadInst * Load ) { SetVector < BasicBlock * > Checklist ; BasicBlock * Start = Load -> getParent ( ) ; Checklist . insert ( Start ) ; const Value * Ptr = Load -> getPointerOperand ( ) ; const Loop * L = LI -> getLoopFor ( Start ) ; if ( L ) { const Loop * P = L ; do { L = P ; P = P -> getParentLoop ( ) ; } while ( P ) ; Checklist . insert ( L -> block_begin ( ) , L -> block_end ( ) ) ; Start = L -> getHeader ( ) ; } DFS ( Start , Checklist ) ; for ( auto & BB : Checklist ) { BasicBlock :: iterator StartIt = ( ! L && ( BB == Load -> getParent ( ) ) ) ? BasicBlock :: iterator ( Load ) : BB -> end ( ) ; if ( MDR -> getPointerDependencyFrom ( MemoryLocation ( Ptr ) , true , StartIt , BB , Load ) . isClobber ( ) ) return true ; } return false ;


<s> static MachineInstr * getContinueInstr ( MachineBasicBlock * blk ) { MachineBasicBlock :: reverse_iterator iter = blk -> rbegin ( ) ; if ( iter != blk -> rend ( ) ) { MachineInstr * instr = & ( * iter ) ; if ( instr -> getOpcode ( ) == AMDGPU :: CONTINUE ) { return instr ; } } return NULL ;


<s> bool hasFP64Denormals ( const Function & F ) const { return FP64FP16Denormals ;


<s> const DataLayout & DL = MF . getDataLayout ( ) ; return MF . getContext ( ) . getOrCreateSymbol ( Twine ( DL . getPrivateGlobalPrefix ( ) ) + Twine ( MF . getFunctionNumber ( ) ) + <STR_LIT> ) ;


<s> unsigned <ISA_LIT>BaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) && Accesses . size ( ) == <NUM_LIT> ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; }


<s> static void rl78_option_override ( void ) { flag_omit_frame_pointer = <NUM_LIT> ; flag_no_function_cse = <NUM_LIT> ; flag_split_wide_types = <NUM_LIT> ; init_machine_status = rl78_init_machine_status ; if ( TARGET_ALLREGS ) { int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) fixed_regs [ i ] = <NUM_LIT> ; } if ( TARGET_ES0 && strcmp ( lang_hooks . name , <STR_LIT> ) && strcmp ( lang_hooks . name , <STR_LIT> ) && strcmp ( lang_hooks . name , <STR_LIT> ) && strcmp ( lang_hooks . name , <STR_LIT> ) && strcmp ( lang_hooks . name , <STR_LIT> ) ) error ( <STR_LIT> ) ; if ( TARGET_SAVE_MDUC_REGISTERS && ! ( TARGET_G13 || RL78_MUL_G13 ) ) warning ( <NUM_LIT> , <STR_LIT> ) ; switch ( rl78_cpu_type ) { case CPU_UNINIT :


<s> } if ( ! Found ) { std :: string name = PAN :: getUdataSectionName ( UDATASections_ . size ( ) ) ; Found = get<ISA_LIT>DataSection ( name . c_str ( ) , UDATA ) ; } Found -> Items . push_back ( GV ) ;

Found -> setSize ( Found -> getSize ( ) + ValSize ) ;


<s> switch ( sm ) { case PTX_ISA_SM30 : return PTX_VERSION_3_0 ; case PTX_ISA_SM35 : return PTX_VERSION_3_1 ; case PTX_ISA_SM53 : return PTX_VERSION_4_2 ; case PTX_ISA_SM70 : return PTX_VERSION_6_0 ; case PTX_ISA_SM75 : return PTX_VERSION_6_3 ; case PTX_ISA_SM80 : return PTX_VERSION_7_0 ; default :


<s> unsigned NextReg , NextRegNum , NextRegWidth ; if ( ! Parse<ISA_LIT>Register ( NextRegKind , NextReg , NextRegNum , NextRegWidth , Tokens ) ) return <STR_LIT> ; if ( NextRegWidth != <NUM_LIT> ) return <STR_LIT> ; if ( NextRegKind != RegKind ) return <STR_LIT> ; if ( ! AddNextRegisterToList ( Reg , RegWidth , RegKind , NextReg ) ) return <STR_LIT> ; } if ( ! trySkipToken ( AsmToken :: RBrac ) ) return <STR_LIT> ; if ( isRegularReg ( RegKind ) ) Reg = getRegularReg ( RegKind , RegNum , RegWidth ) ;


<s> return Kind == k_PostIndexRegister && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( PostIdxReg . RegNum ) ;


<s> } if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> } } if ( MaskTy == <STR_LIT> && VT == <STR_LIT> && ( Subtarget -> hasAVX2 ( ) || Subtarget -> hasAVX ( ) ) ) { Mask = DAG . getNode ( <STR_LIT> , dl , VT , Mask ) ; DCI . AddToWorklist ( Mask . getNode ( ) ) ; return DAG . getNode ( N -> getOpcode ( ) , dl , VT , Mask , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } return SDValue ( ) ;


<s> IterationCountDCE ( LoLoop ) ; MachineBasicBlock :: iterator InsertPt = LoLoop . StartInsertPt ; MachineInstr * Start = LoLoop . Start ; MachineBasicBlock * MBB = LoLoop . StartInsertBB ; unsigned Opc = LoLoop . getStartOpcode ( ) ; MachineOperand & Count = LoLoop . getLoopStartOperand ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPt , Start -> getDebugLoc ( ) , TII -> get ( Opc ) ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return SDValue ( ) ;


<s> return * get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCRegisterInfo & mri , MCContext & ctx ) : MCII ( mcii ) , MRI ( mri ) , Ctx ( ctx ) {


<s> sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; mainMBB -> addSuccessor ( sinkMBB ) ; sinkMBB -> addLiveIn ( <STR_LIT> ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ;


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const {


<s> sysctl ( l1_line_name , <NUM_LIT> , & l1_line , & len , NULL , <NUM_LIT> ) ; sysctl ( l2_size_name , <NUM_LIT> , & l2_sizekb , & len , NULL , <NUM_LIT> ) ; l1_assoc = <NUM_LIT> ;


<s> void <ISA_LIT>MCExpr :: AddValueSymbols ( MCAssembler * Asm ) const { AddValueSymbolsImpl ( getSubExpr ( ) , Asm ) ;


<s> if ( isToken ( Kind ) ) { lex ( ) ; return true ; }


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; const Function * F = nullptr ; if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; F = cast < Function > ( GV ) ; Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , <NUM_LIT> , CallConv , ArgLocs , CCInfo , true , isVarArg ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; unsigned AI , AE ; bool HasStackArgs = false ; for ( AI = <NUM_LIT> , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) { CCValAssign & VA = ArgLocs [ AI ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ AI ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ;


<s> <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , true ) {


<s> int16_t <ISA_LIT>InstrInfo :: getFMAOpIdxInfo ( unsigned Opcode ) const { for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( FMAOpIdxInfo ) ; I ++ ) if ( FMAOpIdxInfo [ I ] [ InfoArrayIdxFMAInst ] == Opcode ) return I ; return - <NUM_LIT> ;


<s> SDValue getAddrLocal ( NodeTy * N , EVT Ty , SelectionDAG & DAG , bool IsN32OrN64 ) const { SDLoc DL ( N ) ; unsigned GOTFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ; unsigned LoFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , LoFlag ) ) ;

return DAG . getNode ( <STR_LIT> , DL , Ty , Load , Lo ) ;


<s> e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; bool is_inthandler = fkind != SUBROUTINE ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; bool all = ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE || ( is_inthandler && ! crtl -> is_leaf ) ) ; int ndregs = all ? <NUM_LIT> : n_dregs_to_save ( is_inthandler , false ) ; int npregs = all ? <NUM_LIT> : n_pregs_to_save ( is_inthandler , false ) ; int n = ndregs + npregs ; int i ; if ( all || stack_frame_needed_p ( ) ) n += <NUM_LIT> ; else { if ( must_save_fp_p ( ) ) n ++ ; if ( must_save_rets_p ( ) ) n ++ ; }


<s> FunctionType * FTy = getType ( M -> getContext ( ) , IntrID , Tys ) ; Function * F = cast < Function > ( M -> getOrInsertFunction ( getName ( IntrID , Tys ) , FTy ) ) ; AttributeList AS = getAttributes ( M -> getContext ( ) , static_cast < <STR_LIT> > ( IntrID ) ) ; F -> setAttributes ( AS ) ; return F ;


<s> if ( VT . isVector ( ) ) { NewVT = VT ; NumElements = VT . getVectorNumElements ( ) ; } Result = DAG . getBuildVector ( NewVT , DL , makeArrayRef ( Slots , NumElements ) ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - <ISA_LIT>AS :: CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } SDValue LoweredLoad ; if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ; assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ; SDValue NewLoad = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , Ptr , LoadNode -> getPointerInfo ( ) , MemVT , LoadNode -> getAlignment ( ) , LoadNode -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , NewLoad , DAG . getValueType ( MemVT ) ) ; SDValue MergedValues [ <NUM_LIT> ] = { Res , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { return SDValue ( ) ; } const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>FrameLowering * TFL = getSubtarget ( ) -> getFrameLowering ( ) ; unsigned StackWidth = TFL -> getStackWidth ( MF ) ; Ptr = stackPtrToRegIndex ( Ptr , StackWidth , DAG ) ; if ( VT . isVector ( ) ) { unsigned NumElemVT = VT . getVectorNumElements ( ) ; EVT ElemVT = VT . getVectorElementType ( ) ; SDValue Loads [ <NUM_LIT> ] ; assert ( NumElemVT <= <NUM_LIT> ) ; assert ( NumElemVT >= StackWidth && <STR_LIT> <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElemVT ; ++ i ) {


<s> if ( InsertIndices . size ( ) > <NUM_LIT> ) return SDValue ( ) ; InsertIndices . push_back ( i ) ; continue ; } SDValue ExtractedFromVec = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; SDValue ExtIdx = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( ExtIdx ) ) return SDValue ( ) ; int Idx = getUnderlyingExtractedFromVec ( ExtractedFromVec , ExtIdx ) ; if ( ExtractedFromVec . getValueType ( ) != VT ) return SDValue ( ) ; if ( ! VecIn1 . getNode ( ) ) VecIn1 = ExtractedFromVec ; else if ( VecIn1 != ExtractedFromVec ) { if ( ! VecIn2 . getNode ( ) ) VecIn2 = ExtractedFromVec ; else if ( VecIn2 != ExtractedFromVec ) return SDValue ( ) ; } if ( ExtractedFromVec == VecIn1 ) Mask [ i ] = Idx ; else if ( ExtractedFromVec == VecIn2 ) Mask [ i ] = Idx + NumElems ;


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED , rtx pic_reg ) { rtx l1 , labelno , pic_tmp , pic_rtx ; if ( crtl -> uses_pic_offset_table == <NUM_LIT> || TARGET_SINGLE_PIC_BASE ) return ; gcc_assert ( flag_pic ) ; if ( pic_reg == NULL_RTX ) pic_reg = cfun -> machine -> pic_reg ; if ( TARGET_VXWORKS_RTP ) { pic_rtx = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; emit_insn ( gen_pic_load_addr_32bit ( pic_reg , pic_rtx ) ) ; emit_insn ( gen_rtx_SET ( pic_reg , gen_rtx_MEM ( Pmode , pic_reg ) ) ) ; pic_tmp = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; emit_insn ( gen_pic_offset_arm ( pic_reg , pic_reg , pic_tmp ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ;


<s> if ( ! get<ISA_LIT>Subtarget ( ) . use<ISA_LIT>PostRAScheduler ( getOptLevel ( ) ) ) { addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) == CodeGenOpt :: None ) ) ; } if ( get<ISA_LIT>Subtarget ( ) . hasMethodCache ( ) ) { addPass ( create<ISA_LIT>FunctionSplitterPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; } addPass ( create<ISA_LIT>DelaySlotKillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>EnsureAlignmentPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>BypassFromPMLPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return true ;


<s> if ( addPass ( TailDuplicateID ) != & NoPassID ) printAndVerify ( <STR_LIT> ) ;


<s> unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createImm ( cop ) ) ; Inst . addOperand ( MCOperand :: createImm ( opc1 ) ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; }

Inst . addOperand ( MCOperand :: createImm ( CRm ) ) ;


<s> O << <STR_LIT> ; } else if ( MO . isImm ( ) ) { int ImmValue = MO . getImm ( ) ; if ( ImmValue < getMinValue ( MII . TSFlags ) || ImmValue > getMaxValue ( MII . TSFlags ) ) O << <STR_LIT> ;


<s> <ISA_LIT>FunctionInfo & AFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( const MachineBasicBlock & MBB : MF ) { memset ( LOHInfos , <NUM_LIT> , sizeof ( LOHInfos ) ) ; for ( const MachineBasicBlock * Succ : MBB . successors ( ) ) { for ( const auto & LI : Succ -> liveins ( ) ) { int RegIdx = mapRegToGPRIndex ( LI . PhysReg ) ; if ( RegIdx >= <NUM_LIT> ) LOHInfos [ RegIdx ] . OneUser = true ; } } for ( const MachineInstr & MI : instructionsWithoutDebug ( MBB . rbegin ( ) , MBB . rend ( ) ) ) { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( canDefBePartOfLOH ( MI ) ) { const MachineOperand & Def = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; assert ( Def . isReg ( ) && Def . isDef ( ) && <STR_LIT> ) ; assert ( Op . isReg ( ) && Op . isUse ( ) && <STR_LIT> ) ; int DefIdx = mapRegToGPRIndex ( Def . getReg ( ) ) ; int OpIdx = mapRegToGPRIndex ( Op . getReg ( ) ) ; if ( DefIdx >= <NUM_LIT> && OpIdx >= <NUM_LIT> && handleMiddleInst ( MI , LOHInfos [ DefIdx ] , LOHInfos [ OpIdx ] ) ) continue ; } break ; case <STR_LIT> : const MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; int Idx = mapRegToGPRIndex ( Op0 . getReg ( ) ) ; if ( Idx >= <NUM_LIT> ) { handleADRP ( MI , AFI , LOHInfos [ Idx ] ) ; continue ; }


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_TEAK_CALL_IMM18 ; break ; case <STR_LIT> : Type = ELF :: R_TEAK_REL7 ; break ; case <STR_LIT> : Type = ELF :: R_TEAK_PTR_IMM16 ; break ; case <STR_LIT> : Type = ELF :: R_TEAK_BKREP_REG ; break ; case <STR_LIT> : Type = ELF :: R_TEAK_BKREP_R6 ; break ; } return Type ;


<s> const AttributeSet & Attrs = Func -> getAttributes ( ) ; if ( ! Attrs . isEmpty ( ) && ! Func -> isVarArg ( ) ) { unsigned InRegCount = <NUM_LIT> ; unsigned Idx = <NUM_LIT> ; for ( FunctionType :: param_iterator I = FTy -> param_begin ( ) , E = FTy -> param_end ( ) ; I != E ; ++ I , ++ Idx ) if ( Attrs . hasAttribute ( Idx , Attribute :: InReg ) ) InRegCount += ( TD -> getTypeSizeInBits ( * I ) + <NUM_LIT> ) / <NUM_LIT> ; if ( InRegCount > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } break ; } case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: Fast : NestReg = <STR_LIT> ; break ; } SDValue OutChains [ <NUM_LIT> ] ; SDValue Addr , Disp ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Disp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPtr , Addr ) ; const unsigned char MOV32ri = <NUM_LIT> ; const unsigned char N86Reg = TRI -> getEncodingValue ( NestReg ) & <NUM_LIT> ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( MOV32ri | N86Reg , <STR_LIT> ) , Trmp , MachinePointerInfo ( TrmpAddr ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Nest , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; const unsigned char JMP = <NUM_LIT> ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , DAG . getConstant ( JMP , <STR_LIT> ) , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trmp , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;

OutChains [ <NUM_LIT> ] = DAG . getStore ( Root , dl , Disp , Addr , MachinePointerInfo ( TrmpAddr , <NUM_LIT> ) , false , false , <NUM_LIT> ) ;


<s> if ( ( <ISA_LIT>InstrInfo :: isVMEM ( * MI ) || <ISA_LIT>InstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasNSAtoVMEMBug ( ) && checkNSAtoVMEMHazard ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( checkFPAtomicToDenormModeHazard ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasNoDataDepHazard ( ) ) return NoHazard ; if ( <ISA_LIT>InstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( <ISA_LIT>InstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( <ISA_LIT>InstrInfo :: isMAI ( * MI ) && checkMAIHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( MI -> mayLoadOrStore ( ) && checkMAILdStHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;


<s> return SramEccSetting == TargetIDSetting :: On || SramEccSetting == TargetIDSetting :: Any ;


<s> DOTGraphTraits ( bool IsSimple = false ) : DefaultDOTGraphTraits ( IsSimple ) {


<s> bool <ISA_LIT>TTIImpl :: shouldBuildLookupTables ( ) { return false ;


<s> else if ( IDVal == <STR_LIT> ) return ParseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return ParseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return ParseDirectiveCode ( DirectiveID . getLoc ( ) ) ;

else if ( IDVal == <STR_LIT> ) return ParseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ;


<s> SmallVector < unsigned , <NUM_LIT> > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; <STR_LIT> ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , <NUM_LIT> , <NUM_LIT> , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <= RegsLeft ) { unsigned FirstVal = ValNo ; for ( unsigned j = <NUM_LIT> ; j < Parts ; j ++ ) {

unsigned Reg = State . AllocateReg ( RegList , NbRegs ) ;


<s> static SDValue LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc , <ISA_LIT>CC = ~ <NUM_LIT> ; LookThroughSetCC ( LHS , RHS , CC , <ISA_LIT>CC ) ; SDValue CompareFlag ; if ( LHS . getValueType ( ) == <STR_LIT> ) { EVT VTs [ ] = { LHS . getValueType ( ) , <STR_LIT> } ;

SDValue Ops [ <NUM_LIT> ] = { LHS , RHS } ;


<s> if ( info2 . demand_p ( DEMAND_NONZERO_AVL ) ) return info1 . demand_p ( DEMAND_AVL ) && ! info1 . demand_p ( DEMAND_NONZERO_AVL ) && info1 . has_avl_reg ( ) ; }

else return info1 . demand_p ( DEMAND_AVL ) && info1 . has_avl_reg ( ) ;


<s> for ( LiveInterval :: iterator I = LI . begin ( ) , E = LI . end ( ) ; I != E ; ++ I ) { LiveRange :: Segment & LR = * I ; if ( ! LR . start . isRegister ( ) ) return false ; if ( ! LR . end . isRegister ( ) && ! LR . end . isDead ( ) ) return false ; }


<s> } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( VT == <STR_LIT> ) { SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ;

if ( NewOp . getNode ( ) ) return NewOp ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getAllVGPRRegMask ( ) const {


<s> unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( size == <NUM_LIT> ) { if ( align == <NUM_LIT> ) return MCDisassembler :: Fail ; align = <NUM_LIT> ; } else { if ( size == <NUM_LIT> ) { align *= <NUM_LIT> ; } else { size = <NUM_LIT> << size ; align *= <NUM_LIT> * size ; } } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> * inc ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> unsigned MaxA = MFI . getMaxAlignment ( ) ;

if ( MaxA <= getStackAlignment ( ) ) return false ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( NumMemOps > <NUM_LIT> ) { AdvanceRS ( MBB , MemOps ) ; unsigned Scratch = RS -> FindUnusedReg ( & <STR_LIT> ) ; RS -> forward ( prior ( MBBI ) ) ; Merges . clear ( ) ; MergeLDR_STR ( MBB , <NUM_LIT> , CurrBase , CurrOpc , CurrSize , CurrPred , CurrPredReg , Scratch , MemOps , Merges ) ; for ( unsigned i = <NUM_LIT> , e = Merges . size ( ) ; i < e ; ++ i ) if ( MergeBaseUpdateLSMultiple ( MBB , Merges [ i ] , Advance , MBBI ) ) ++ NumMerges ; NumMerges += Merges . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumMemOps ; ++ i ) if ( ! MemOps [ i ] . Merged ) if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ i ] . MBBI , TII , Advance , MBBI ) ) ++ NumMerges ; RS -> skipTo ( prior ( MBBI ) ) ; } else if ( NumMemOps == <NUM_LIT> ) { if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ <NUM_LIT> ] . MBBI , TII , Advance , MBBI ) ) { ++ NumMerges ; RS -> forward ( prior ( MBBI ) ) ; } } CurrBase = <NUM_LIT> ; CurrOpc = - <NUM_LIT> ; CurrSize = <NUM_LIT> ; CurrPred = <STR_LIT> ; CurrPredReg = <NUM_LIT> ; if ( NumMemOps ) { MemOps . clear ( ) ; NumMemOps = <NUM_LIT> ; } if ( ! Advance && ! isMemOp && MBBI != E ) { ++ Position ; ++ MBBI ; } } } return NumMerges > <NUM_LIT> ;


<s> std :: pair < SDValue , SDValue > <ISA_LIT>TargetLowering :: lowerTLSCall ( SDValue Op , SDLoc dl , SelectionDAG & DAG ) const { Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ;


<s> EmitAllAutos ( M ) ; printLibcallDecls ( ) ;


<s> case <STR_LIT> : Value = - <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } DebugLoc DL = Orig -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addOperand ( Orig -> getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; } else { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MBB . insert ( I , MI ) ; } MachineInstr * NewMI = std :: prev ( I ) ;

NewMI -> substituteRegister ( Orig -> getOperand ( <NUM_LIT> ) . getReg ( ) , DestReg , SubIdx , TRI ) ;


<s> static rtx riscv_force_address ( rtx x , enum machine_mode mode ) { if ( ! riscv_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ;


<s> case <STR_LIT> : { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ; }


<s> if ( parseToken ( AsmToken :: Comma ) ) return addErrorSuffix ( <STR_LIT> ) ;

getParser ( ) . getStreamer ( ) . EmitValueToAlignment ( Size ) ;


<s> if ( in_p ) { if ( REGCLASS_HAS_FP_REG ( rclass ) && immediate_operand ( ( x ) , mode ) && ! ( ( fp_zero_operand ( x ) || fp_one_operand ( x ) ) && mode == SFmode ) ) switch ( mode ) { case E_SFmode : sri -> icode = CODE_FOR_reload_insf__frn ; return NO_REGS ; case E_DFmode : sri -> icode = CODE_FOR_reload_indf__frn ; return NO_REGS ; case E_SImode : return FPUL_REGS ; default : abort ( ) ; } if ( rclass == FPUL_REGS && ( ( REG_P ( x ) && ( REGNO ( x ) == MACL_REG || REGNO ( x ) == MACH_REG || REGNO ( x ) == T_REG ) ) || GET_CODE ( x ) == PLUS ) ) return GENERAL_REGS ; if ( rclass == FPUL_REGS && immediate_operand ( x , mode ) ) { if ( satisfies_constraint_I08 ( x ) || fp_zero_operand ( x ) ) return GENERAL_REGS ; else if ( mode == SFmode ) return FP_REGS ; sri -> icode = CODE_FOR_reload_insi__i_fpul ; return NO_REGS ; } if ( rclass == FPSCR_REGS && ( ( REG_P ( x ) && REGNO ( x ) >= FIRST_PSEUDO_REGISTER ) || ( MEM_P ( x ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) ) ) return GENERAL_REGS ; } if ( ( ( REGCLASS_HAS_FP_REG ( rclass ) && ( REG_P ( x ) && ( GENERAL_OR_AP_REGISTER_P ( REGNO ( x ) ) || ( FP_REGISTER_P ( REGNO ( x ) ) && mode == SImode && TARGET_FMOVD ) ) ) ) || ( REGCLASS_HAS_GENERAL_REG ( rclass ) && REG_P ( x ) && FP_REGISTER_P ( REGNO ( x ) ) ) ) && ( mode == SFmode || mode == SImode ) ) return FPUL_REGS ; if ( ( rclass == FPUL_REGS || ( REGCLASS_HAS_FP_REG ( rclass ) && mode == SImode ) ) && ( MEM_P ( x ) || ( REG_P ( x ) && ( REGNO ( x ) >= FIRST_PSEUDO_REGISTER || REGNO ( x ) == T_REG || system_reg_operand ( x , VOIDmode ) ) ) ) ) { if ( rclass == FPUL_REGS ) return GENERAL_REGS ; return NO_REGS ; } if ( ( rclass == MAC_REGS || rclass == PR_REGS ) && REG_P ( x ) && ! GENERAL_REGISTER_P ( REGNO ( x ) ) && rclass != REGNO_REG_CLASS ( REGNO ( x ) ) ) return GENERAL_REGS ; if ( rclass == FPUL_REGS && true_regnum ( x ) == - <NUM_LIT> ) return GENERAL_REGS ;

if ( ( mode == QImode || mode == HImode ) && rclass != R0_REGS && satisfies_constraint_Sdd ( x ) && sh_disp_addr_displacement ( x ) <= sh_max_mov_insn_displacement ( mode , false ) ) return R0_REGS ;


<s> unsigned getCurPacketSize ( ) const {


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> static const char Nops32Bit [ <NUM_LIT> ] [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; static const char Nops16Bit [ <NUM_LIT> ] [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const char ( * Nops ) [ <NUM_LIT> ] = STI -> getFeatureBits ( ) [ <STR_LIT> ] ? Nops16Bit : Nops32Bit ; uint64_t MaxNopLength = ( uint64_t ) getMaximumNopSize ( * STI ) ; do { const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OS << '\x66' ;

const uint8_t Rest = ThisNopLength - Prefixes ;


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , SDLoc dl ) {

SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ;


<s> assert ( ! WroteStrtab ) ; std :: vector < char > Strtab ; StrtabBuilder . finalizeInOrder ( ) ;

Strtab . resize ( StrtabBuilder . getSize ( ) ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) : MCII ( MCII ) , Ctx ( Ctx ) {


<s> return process_sti_stu < stu > ( val , b , sz ) ;


<s> if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( ( MAYBE_MASK_CLASS_P ( class1 ) != MAYBE_MASK_CLASS_P ( class2 ) ) && ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ;

if ( ( SSE_CLASS_P ( class1 ) && ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) || ( SSE_CLASS_P ( class2 ) && ! TARGET_INTER_UNIT_MOVES_TO_VEC ) ) return true ;


<s> if ( Opc == G_SEXT ) return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;

if ( Opc == G_ZEXT ) return Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> return new <ISA_LIT>InsertWaitcnts ( ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> bool <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( IfConverterID ) ;


<s> if ( VT == <STR_LIT> ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; } if ( VT != <STR_LIT> ) { SDValue Hi16 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Hi16 ) ; } else { X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; } SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , DL , VTs , Lo , Hi ) . getValue ( <NUM_LIT> ) ; SDValue Setnp = getSETCC ( <STR_LIT> , Flags , DL , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Setnp ) ;


<s> SDValue Op0 = And . getOperand ( <NUM_LIT> ) ; SDValue Op1 = And . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue Src , BitNo ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( isOneConstant ( Op0 . getOperand ( <NUM_LIT> ) ) ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) { KnownBits Known = DAG . computeKnownBits ( Op0 ) ; if ( Known . countMinLeadingZeros ( ) < BitWidth - AndBitWidth ) return SDValue ( ) ; } Src = Op1 ; BitNo = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) {

Src = AndLHS . getOperand ( <NUM_LIT> ) ;


<s> static TargetLoweringObjectFile * createTLOF ( const Triple & TT ) { if ( TT . isOSBinFormatMachO ( ) ) return new <ISA_LIT>_MachoTargetObjectFile ( ) ; return new <ISA_LIT>_ELFTargetObjectFile ( ) ;


<s> int PossibleAluOpIdx = Offset + <NUM_LIT> ; int PossibleBaseIdx = Offset + <NUM_LIT> ; int PossibleDestIdx = Offset + <NUM_LIT> ; if ( <ISA_LIT>Operand * PossibleAluOp = static_cast < <ISA_LIT>Operand * > ( Operands [ PossibleAluOpIdx ] . get ( ) ) ) if ( PossibleAluOp -> isImm ( ) ) if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( PossibleAluOp -> getImm ( ) ) ) Modifies = LPAC :: modifiesOp ( ConstExpr -> getValue ( ) ) ;

return Modifies && Operands [ PossibleBaseIdx ] -> isReg ( ) && Operands [ PossibleDestIdx ] -> isReg ( ) && Operands [ PossibleBaseIdx ] -> getReg ( ) == Operands [ PossibleDestIdx ] -> getReg ( ) ;


<s> return ( __m128i ) __builtin_ia32_psrlv8hi_mask ( ( __v8hi ) __A , ( __v8hi ) __B , ( __v8hi ) _mm_setzero_hi ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> static ScheduleDAGInstrs * createMinRegScheduler ( MachineSchedContext * C ) { return new GCNIterativeScheduler ( C , GCNIterativeScheduler :: SCHEDULE_MINREGFORCED ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) return new Darwin<ISA_LIT>_32AsmBackend ( T , MRI , CPU ) ; if ( TheTriple . isOSWindows ( ) && ! TheTriple . isOSBinFormatELF ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , false , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ;

return new ELF<ISA_LIT>_32AsmBackend ( T , OSABI , CPU ) ;


<s> else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , <NUM_LIT> ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; else {


<s> do { rtx r = gen_rtx_REG ( SImode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * <NUM_LIT> ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; }

while ( ++ align_words < GP_ARG_NUM_REG && -- n_units != <NUM_LIT> ) ;


<s> return Kind == KindTy :: Immediate ;


<s> inline void setSym ( std :: string str ) {


<s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch = <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; else Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;


<s> int ret = <NUM_LIT> ; switch ( DEFAULT_ABI ) { default : abort ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? <NUM_LIT> : <NUM_LIT> ; break ;


<s> if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ; SDValue Z = Cmp . getOperand ( <NUM_LIT> ) ; EVT ZVT = Z . getValueType ( ) ; if ( auto * ConstantX = dyn_cast < ConstantSDNode > ( X ) ) { if ( ( IsSub && CC == <STR_LIT> && ConstantX -> isNullValue ( ) ) || ( ! IsSub && CC == <STR_LIT> && ConstantX -> isAllOnesValue ( ) ) ) { SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , ZVT ) ; SDVTList <ISA_LIT>SubVTs = DAG . getVTList ( ZVT , <STR_LIT> ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , <ISA_LIT>SubVTs , Zero , Z ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Neg . getNode ( ) , <NUM_LIT> ) ) ; } if ( ( IsSub && CC == <STR_LIT> && ConstantX -> isNullValue ( ) ) || ( ! IsSub && CC == <STR_LIT> && ConstantX -> isAllOnesValue ( ) ) ) { SDValue One = DAG . getConstant ( <NUM_LIT> , DL , ZVT ) ; SDValue Cmp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Z , One ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Cmp1 ) ; } } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , ZVT ) ; SDValue Cmp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Z , One ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , VTs , X , DAG . getConstant ( - <NUM_LIT> , DL , VT ) , Cmp1 ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , VTs , X , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Cmp1 ) ;


<s> Error ( FnStartLoc , <STR_LIT> ) ; return true ; } FnStartLoc = L ; getTargetStreamer ( ) . emitFnStart ( ) ;


<s> const <ISA_LIT>CCState * <ISA_LIT>State = static_cast < <ISA_LIT>CCState * > ( & State ) ; static const MCPhysReg F32Regs [ ] = { <STR_LIT> , <STR_LIT> } ; static const MCPhysReg FloatVectorIntRegs [ ] = { <STR_LIT> , <STR_LIT> } ; if ( ArgFlags . isByVal ( ) ) return true ; if ( ArgFlags . isInReg ( ) && ! Subtarget . isLittle ( ) ) { if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExtUpper ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExtUpper ; else LocInfo = CCValAssign :: AExtUpper ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; bool isVectorFloat = <ISA_LIT>State -> WasOriginalArgVectorFloat ( ValNo ) ; if ( ValVT == <STR_LIT> && isVectorFloat ) { if ( ArgFlags . isSplit ( ) ) { Reg = State . AllocateReg ( FloatVectorIntRegs ) ; if ( Reg == <STR_LIT> ) State . AllocateReg ( <STR_LIT> ) ; else if ( Reg == <NUM_LIT> ) State . AllocateReg ( <STR_LIT> ) ; } else { Reg = State . AllocateReg ( IntRegs ) ; } } else if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs ) ; State . AllocateReg ( IntRegs ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs ) ; State . AllocateReg ( IntRegs ) ; } else {


<s> return __builtin_ia32_vcvtph2pd512_mask_round ( __A , _mm512_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> if ( Bits == <NUM_LIT> || Bits > <NUM_LIT> ) return <NUM_LIT> ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ;


<s> AU . addRequired < GISelKnownBitsAnalysis > ( ) ;

AU . addPreserved < GISelKnownBitsAnalysis > ( ) ;