<s> break ; } if ( I -> hasRegisterImplicitUseOperand ( <STR_LIT> ) ) continue ; if ( Size > <NUM_LIT> && ( I -> getNumImplicitOperands ( ) > ( I -> isCopy ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ) continue ; MovX = & * I ; } if ( ! MovX ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MovT << * MovX << * MovY ) ; for ( unsigned I = <NUM_LIT> ; I < Size ; ++ I ) { TargetInstrInfo :: RegSubRegPair X1 , Y1 ; X1 = getSubRegForIndex ( X , Xsub , I ) ; Y1 = getSubRegForIndex ( Y , Ysub , I ) ; MachineBasicBlock & MBB = * MovT . getParent ( ) ; auto MIB = BuildMI ( MBB , MovX -> getIterator ( ) , MovT . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( X1 . Reg , <NUM_LIT> , X1 . SubReg ) . addDef ( Y1 . Reg , <NUM_LIT> , Y1 . SubReg ) . addReg ( Y1 . Reg , <NUM_LIT> , Y1 . SubReg ) . addReg ( X1 . Reg , <NUM_LIT> , X1 . SubReg ) . getInstr ( ) ; if ( MovX -> hasRegisterImplicitUseOperand ( <STR_LIT> ) ) { MIB -> removeOperand ( MIB -> getNumExplicitOperands ( ) ) ; MIB -> copyImplicitOps ( * MBB . getParent ( ) , * MovX ) ; } } MovX -> eraseFromParent ( ) ; dropInstructionKeepingImpDefs ( * MovY ) ; MachineInstr * Next = & * std :: next ( MovT . getIterator ( ) ) ; if ( T . isVirtual ( ) && MRI -> use_nodbg_empty ( T ) ) { dropInstructionKeepingImpDefs ( MovT ) ; } else { Xop . setIsKill ( false ) ; for ( int I = MovT . getNumImplicitOperands ( ) - <NUM_LIT> ; I >= <NUM_LIT> ; -- I ) { unsigned OpNo = MovT . getNumExplicitOperands ( ) + I ; const MachineOperand & Op = MovT . getOperand ( OpNo ) ; if ( Op . isKill ( ) && TRI -> regsOverlap ( X , Op . getReg ( ) ) ) MovT . removeOperand ( OpNo ) ; } } return Next ; } return nullptr ;


<s> if ( PreOp ) return LPAC :: makePreOp ( AluCode ) ; if ( PostOp ) return LPAC :: makePostOp ( AluCode ) ;


<s> if ( Mask [ i ] < <NUM_LIT> ) continue ; int UnpackIdx = i / Scale ; if ( ( UnpackIdx % <NUM_LIT> == <NUM_LIT> ) != ( Mask [ i ] < Size ) ) return SDValue ( ) ; SmallVectorImpl < int > & VMask = ( UnpackIdx % <NUM_LIT> == <NUM_LIT> ) ? V1Mask : V2Mask ; VMask [ ( UnpackIdx / <NUM_LIT> ) * Scale + i % Scale + ( UnpackLo ? <NUM_LIT> : Size / <NUM_LIT> ) ] = Mask [ i ] % Size ; } if ( ( NumLoInputs == <NUM_LIT> || NumHiInputs == <NUM_LIT> ) && ! isNoopShuffleMask ( V1Mask ) && ! isNoopShuffleMask ( V2Mask ) ) return SDValue ( ) ; V1 = DAG . getVectorShuffle ( VT , DL , V1 , DAG . getUNDEF ( VT ) , V1Mask ) ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Mask ) ; V1 = DAG . getBitcast ( UnpackVT , V1 ) ; V2 = DAG . getBitcast ( UnpackVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getNode ( UnpackLo ? <STR_LIT> : <STR_LIT> , DL , UnpackVT , V1 , V2 ) ) ; } ; int OrigNumElements = VT . getVectorNumElements ( ) ; int OrigScalarSize = VT . getScalarSizeInBits ( ) ; for ( int ScalarSize = <NUM_LIT> ; ScalarSize >= OrigScalarSize ; ScalarSize /= <NUM_LIT> ) { int Scale = ScalarSize / OrigScalarSize ; int NumElements = OrigNumElements / Scale ; MVT UnpackVT = <STR_LIT> ( <STR_LIT> ( ScalarSize ) , NumElements ) ; if ( SDValue Unpack = TryUnpack ( UnpackVT , Scale ) ) return Unpack ;


<s> virtual void InitToTextSection ( ) {


<s> if ( C <= <NUM_LIT> && ( ( C & <NUM_LIT> ) == <NUM_LIT> ) ) return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , SP , CurDAG -> getTargetConstant ( C / <NUM_LIT> , <STR_LIT> ) , Chain ) ; if ( Subtarget -> isThumb1Only ( ) ) { return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , SP , Size , Chain ) ; } else if ( Subtarget -> isThumb2 ( ) ) { if ( isC && Predicate_t2_so_imm ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else if ( isC && Predicate_imm0_4095 ( Size . getNode ( ) ) ) { SDValue Ops [ ] = { SP , CurDAG -> getTargetConstant ( C , <STR_LIT> ) , Chain } ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , VT , <STR_LIT> , Ops , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { SP , Size , getI32Imm ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) , Chain } ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RelocID = <STR_LIT> ; break ; case <STR_LIT> : RelocID = <STR_LIT> ; break ; }

MCE . addRelocation ( GetRelocation ( MO , RelocID ) ) ;


<s> if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; int Scale = <NUM_LIT> / NumLaneElts ; if ( Subtarget -> hasSSSE3 ( ) ) { MVT AlignVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * NumLanes ) ; Lo = DAG . getBitcast ( AlignVT , Lo ) ; Hi = DAG . getBitcast ( AlignVT , Hi ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , AlignVT , Hi , Lo , DAG . getConstant ( Rotation * Scale , DL , <STR_LIT> ) ) ) ; } assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; int LoByteShift = <NUM_LIT> - Rotation * Scale ; int HiByteShift = Rotation * Scale ; Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; SDValue LoShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( LoByteShift , DL , <STR_LIT> ) ) ; SDValue HiShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( HiByteShift , DL , <STR_LIT> ) ) ;

return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoShift , HiShift ) ) ;


<s> bool NPEnginePassConfig :: addPreISel ( ) { return false ;


<s> <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Alignment ) ;

unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ;


<s> unsigned NumSubRegs = RegSize / <NUM_LIT> ; assert ( NumSubRegs % <NUM_LIT> == <NUM_LIT> && NumSubRegs <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumSubRegs ; Idx += <NUM_LIT> ) { Register CurRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurRegLo ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx ) ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurRegHi ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx + <NUM_LIT> ) ) ; ReadlanePieces . push_back ( CurRegLo ) ; ReadlanePieces . push_back ( CurRegHi ) ; Register CurReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurReg ) . addReg ( CurRegLo ) . addImm ( <STR_LIT> ) . addReg ( CurRegHi ) . addImm ( <STR_LIT> ) ; Register NewCondReg = MRI . createVirtualRegister ( BoolXExecRC ) ; auto Cmp = BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , NewCondReg ) . addReg ( CurReg ) ; if ( NumSubRegs <= <NUM_LIT> ) Cmp . addReg ( VRsrc ) ; else Cmp . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx , <NUM_LIT> ) ) ; if ( CondReg == <STR_LIT> ) CondReg = NewCondReg ; else { Register AndReg = MRI . createVirtualRegister ( BoolXExecRC ) ;

BuildMI ( LoopBB , I , DL , TII . get ( AndOpc ) , AndReg ) . addReg ( CondReg ) . addReg ( NewCondReg ) ;


<s> return anyTypeToString ( static_cast < unsigned > ( Type ) ) ;


return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , false , true , true ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } if ( MI -> hasOneMemOperand ( ) ) MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ;


<s> <ISA_LIT>AnnotateControlFlow ( ) : FunctionPass ( ID ) {


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return <STR_LIT> ;


<s> if ( model != TLSModel :: LocalExec ) llvm_unreachable ( <STR_LIT> ) ; SDValue TPHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPHi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi ) ; SDValue TPLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue TP = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted , TPLo ) ;

<ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ;


<s> static inline void desc_br_mem ( unsigned char brmask , struct unw_state_record * sr ) { int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( brmask & <NUM_LIT> ) { set_reg ( sr -> curr . reg + UNW_REG_B1 + i , UNW_WHERE_SPILL_HOME , sr -> region_start + sr -> region_len - <NUM_LIT> , <NUM_LIT> ) ; sr -> any_spills = <NUM_LIT> ; } brmask >>= <NUM_LIT> ; }


<s> return ( __m512i ) __builtin_ia32_pternlogq512_mask ( ( __v8di ) __A , ( __v8di ) __B , ( __v8di ) __C , ( unsigned char ) __imm , ( __mmask8 ) __U ) ;


<s> bool <ISA_LIT>NaClRewritePass :: ApplyStackSFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { TraceLog ( <STR_LIT> , MBB , MBBI ) ; assert ( Is64Bit ) ; MachineInstr & MI = * MBBI ; if ( ! IsStackChange ( MI , TRI ) ) return false ; if ( IsPushPop ( MI ) ) return false ; if ( MI . getDesc ( ) . isCall ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DestReg == <STR_LIT> || DestReg == <STR_LIT> ) ; unsigned NewOpc = <NUM_LIT> ; switch ( Opc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NewOpc ) { BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Opc = <STR_LIT> ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { return true ; }

assert ( Opc != <STR_LIT> && <STR_LIT> ) ;


<s> SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ;

return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops , <NUM_LIT> ) ;


<s> static inline void invertBccCondition ( MachineInstr * MI ) { assert ( MI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> getObjectOffset ( FI ) ;


<s> StringRef getPassName ( ) const override {


<s> break ; case <STR_LIT> : if ( SelectMoveImmediate ( N ) ) return ; break ; case <STR_LIT> : if ( SelectConditionalBranch ( N ) ) return ; break ; }


<s> static SDValue getLegalSplat ( SelectionDAG & DAG , SDValue V , int EltNo ) { MVT VT = V . getSimpleValueType ( ) ; SDLoc dl ( V ) ; if ( VT . is128BitVector ( ) ) { V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo } ; V = DAG . getVectorShuffle ( <STR_LIT> , dl , V , DAG . getUNDEF ( <STR_LIT> ) , & SplatMask [ <NUM_LIT> ] ) ; } else if ( VT . is256BitVector ( ) ) { int SplatMask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo , EltNo + <NUM_LIT> , EltNo + <NUM_LIT> , EltNo + <NUM_LIT> , EltNo + <NUM_LIT> } ; V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; V = DAG . getVectorShuffle ( <STR_LIT> , dl , V , DAG . getUNDEF ( <STR_LIT> ) , & SplatMask [ <NUM_LIT> ] ) ; } else llvm_unreachable ( <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , V ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> <ISA_LIT>WasmObjectWriter :: <ISA_LIT>WasmObjectWriter ( bool Is64Bit , bool IsEmscripten ) : MCWasmObjectTargetWriter ( Is64Bit , IsEmscripten ) {


<s> MachineInstr & MI = * I ; if ( TII -> isFLAT ( MI ) ) NeedFlat = true ; if ( I -> modifiesRegister ( <STR_LIT> , TRI ) ) ExecModified = true ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : ++ Depth ; If ( MI ) ; break ; case <STR_LIT> : Else ( MI , ExecModified ) ; break ; case <STR_LIT> : Break ( MI ) ; break ; case <STR_LIT> : IfBreak ( MI ) ; break ; case <STR_LIT> : ElseBreak ( MI ) ; break ; case <STR_LIT> : ++ Depth ; Loop ( MI ) ; break ; case <STR_LIT> : if ( -- Depth == <NUM_LIT> && HaveKill ) { HaveKill = false ; } EndCf ( MI ) ; break ; case <STR_LIT> : if ( Depth == <NUM_LIT> ) { if ( skipIfDead ( MI , * NextBB ) ) { NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; } } else HaveKill = true ; Kill ( MI ) ; break ; case <STR_LIT> : Branch ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( indirectSrc ( MI ) ) { NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; Next = MBB . end ( ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( indirectDst ( MI ) ) { NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; Next = MBB . end ( ) ; } break ; case <STR_LIT> : { assert ( ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( BI != -- MF . end ( ) || I != MBB . getFirstTerminator ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB . addSuccessor ( EmptyMBBAtEnd ) ; BuildMI ( * BI , I , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( EmptyMBBAtEnd ) ; I -> eraseFromParent ( ) ; } break ; } } } } if ( NeedFlat && MFI -> IsKernel ) { if ( NeedFlat ) MFI -> setHasFlatInstructions ( true ) ; }


<s> BasicBlock * <ISA_LIT>CommonGEP :: recalculatePlacementRec ( GepNode * Node , NodeChildrenMap & NCM , NodeToValueMap & Loc ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Node << '\n' ) ; NodeChildrenMap :: iterator CF = NCM . find ( Node ) ; if ( CF != NCM . end ( ) ) { NodeVect & Cs = CF -> second ; for ( GepNode * C : Cs ) recalculatePlacementRec ( C , NCM , Loc ) ; } BasicBlock * LB = recalculatePlacement ( Node , NCM , Loc ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Node << '\n' ) ; return LB ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>Target ( <ISA_LIT>_COMPUTE_1_0 ) , <ISA_LIT>Version ( <ISA_LIT>_VERSION_2_0 ) , SupportsDouble ( false ) , SupportsFMA ( true ) , Is64Bit ( is64Bit ) { std :: string TARGET = CPU ; if ( TARGET . empty ( ) ) TARGET = <STR_LIT> ; ParseSubtargetFeatures ( TARGET , FS ) ;


<s> unsigned char OpFlags = Subtarget . ClassifyGlobalReference ( GV , TM ) ; const unsigned char MO_NC = <STR_LIT> ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; } else if ( TM . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; } else { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags | <STR_LIT> ) ; unsigned char LoFlags = OpFlags | <STR_LIT> | MO_NC ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , LoFlags ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; } MBB . erase ( MI ) ; return true ;


<s> EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( SrcVT == <STR_LIT> ) return false ; unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( DestVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) ;


<s> bool <ISA_LIT>Operand :: isSMRDOffset ( ) const {

return isImm ( ) && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> std :: vector < const SUnit * > makeGCNILPScheduler ( ArrayRef < const SUnit * > BotRoots , const ScheduleDAG & DAG ) { GCNILPScheduler S ;

return S . schedule ( BotRoots , DAG ) ;


<s> for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += NumLaneElts ) { for ( unsigned i = <NUM_LIT> , j = l ; i != NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ l + i ] ; int BitI1 = Mask [ l + i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) ) return false ; if ( V2IsSplat ) { if ( ! isUndefOrEqual ( BitI1 , NumElts ) ) return false ;


<s> if ( MRI -> isLiveIn ( R1 . Reg ) ) return false ; if ( MRI -> isLiveIn ( R2 . Reg ) ) return false ; LiveInterval & L1 = LIS -> getInterval ( R1 . Reg ) ; LiveInterval & L2 = LIS -> getInterval ( R2 . Reg ) ; if ( L2 . empty ( ) ) return false ; bool Overlap = L1 . overlaps ( L2 ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Overlap ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << PrintReg ( R1 . Reg , TRI , R1 . Sub ) << <STR_LIT> << L1 << <STR_LIT> << PrintReg ( R2 . Reg , TRI , R2 . Sub ) << <STR_LIT> << L2 << <STR_LIT> ) ; if ( R1 . Sub || R2 . Sub ) return false ; if ( Overlap ) return false ; if ( ! isIntraBlocks ( L1 ) && ! isIntraBlocks ( L2 ) ) return false ; MRI -> replaceRegWith ( R2 . Reg , R1 . Reg ) ; typedef DenseMap < VNInfo * , VNInfo * > ValueInfoMap ; ValueInfoMap VM ; for ( LiveInterval :: iterator I = L2 . begin ( ) , E = L2 . end ( ) ; I != E ; ++ I ) { VNInfo * NewVN , * OldVN = I -> valno ; ValueInfoMap :: iterator F = VM . find ( OldVN ) ; if ( F == VM . end ( ) ) { NewVN = L1 . getNextValue ( I -> valno -> def , LIS -> getVNInfoAllocator ( ) ) ; VM . insert ( std :: make_pair ( OldVN , NewVN ) ) ; } else { NewVN = F -> second ; } L1 . addSegment ( LiveRange :: Segment ( I -> start , I -> end , NewVN ) ) ; } while ( L2 . begin ( ) != L2 . end ( ) ) L2 . removeSegment ( * L2 . begin ( ) ) ; updateKillFlags ( R1 . Reg ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << L1 << <STR_LIT> ) ;


<s> return mips_function_value_1 ( valtype , fn_decl_or_type , VOIDmode ) ;


<s> static inline int vec_any_nle ( vec_float4 a , vec_float4 b ) { return ( ( int ) ( spu_extract ( spu_gather ( spu_cmpgt ( a , b ) ) , <NUM_LIT> ) != <NUM_LIT> ) ) ;


<s> static const char * detect_processor_freebsd ( void ) { return <STR_LIT> ;


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , bool Fast , raw_ostream & Out ) {

PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , Fast ) ) ;


<s> unsigned getWavesPerWorkGroup ( const FeatureBitset & Features , unsigned FlatWorkGroupSize ) { return alignTo ( FlatWorkGroupSize , getWavefrontSize ( Features ) ) / getWavefrontSize ( Features ) ;


<s> R600MCCodeEmitter ( const MCInstrInfo & mcii , const MCRegisterInfo & mri , const MCSubtargetInfo & sti ) : MCII ( mcii ) , MRI ( mri ) , STI ( sti ) {


<s> idx = <NUM_LIT> ; } if ( Op0 -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Source = Op0 -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ; EVT SVT = Source -> getValueType ( <NUM_LIT> ) ; if ( ! SVT . isVector ( ) || SVT . getVectorNumElements ( ) != VT . getVectorNumElements ( ) * <NUM_LIT> ) return SDValue ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc dl ( N ) ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( idx ) { SDValue HalfIdx = DAG . getConstant ( NumElements , dl , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Source , HalfIdx ) ;


<s> Register ArgsAddrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

auto MIB = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( ArgsAddrReg ) . addFrameIndex ( FuncInfo -> getVarArgsStackIndex ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> } MVT WideVT = <STR_LIT> ( WideEltVT , WidenVecLen ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; SDValue ExtractElt = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , ExtractElementIdx ) ; SDValue ShiftRight = DAG . getNode ( <STR_LIT> , DL , XLenVT , ExtractElt , ExtractBitIdx ) ; return DAG . getNode ( <STR_LIT> , DL , XLenVT , ShiftRight , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; } } MVT WideVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; return DAG . getNode ( <STR_LIT> , DL , EltVT , Vec , Idx ) ; } MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } if ( ! isNullConstant ( Idx ) ) {

SDValue VL = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ;


<s> static int msp430_muldiv_costs ( rtx src , rtx dst , bool speed , rtx outer_rtx , machine_mode outer_mode ) { enum rtx_code outer_code = GET_CODE ( outer_rtx ) ; const struct msp430_multlib_costs * cost_p ; cost_p = ( msp430_use_16bit_hwmult ( ) ? & cycle_cost_multlib_32bit : & cycle_cost_multlib_16bit ) ; int factor = <NUM_LIT> ; int mode_factor = <NUM_LIT> ; if ( outer_mode == SImode ) mode_factor = <NUM_LIT> ; else if ( outer_mode == PSImode ) mode_factor = <NUM_LIT> ; else if ( outer_mode == DImode ) mode_factor = <NUM_LIT> ; if ( ! speed ) { if ( outer_code != MULT ) factor = <NUM_LIT> ; else if ( ( ( msp430_use_16bit_hwmult ( ) && outer_mode != DImode ) || msp430_use_32bit_hwmult ( ) || msp430_use_f5_series_hwmult ( ) ) ) factor = <NUM_LIT> ; else factor = <NUM_LIT> ; return factor * mode_factor * msp430_costs ( src , dst , speed , outer_rtx ) ; } if ( outer_code != MULT || ! msp430_has_hwmult ( ) || ( outer_mode == DImode && msp430_use_16bit_hwmult ( ) ) ) { factor = ( outer_code == MULT ? <NUM_LIT> : <NUM_LIT> ) ; return factor * mode_factor * msp430_costs ( src , dst , speed , outer_rtx ) ; } switch ( outer_mode ) { case E_QImode : case E_HImode : return cost_p -> mulhi + ( <NUM_LIT> * msp430_costs ( src , dst , speed , outer_rtx ) ) ; case E_PSImode : factor = <NUM_LIT> ; case E_SImode : return factor * ( cost_p -> mulsi + ( <NUM_LIT> * msp430_costs ( src , dst , speed , outer_rtx ) ) ) ;


<s> ContainedTys = & PointeeTy ; NumContainedTys = <NUM_LIT> ; setSubclassData ( AddrSpace ) ;


<s> for ( unsigned Opc = <NUM_LIT> ; Opc < <STR_LIT> ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Custom ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; setOperationAction ( <STR_LIT> , Ty , Legal ) ; if ( Ty == <STR_LIT> || Ty == <STR_LIT> ) { setOperationAction ( <STR_LIT> , Ty , Legal ) ;


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getBFTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {

const MCOperand MO = MI . getOperand ( OpIdx ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeRelCondBrTarget ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( Fixup ) , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } assert ( MO . isImm ( ) ) ; auto target = MO . getImm ( ) ;

<STR_LIT> :: adjustBranchTarget ( target ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> size = <NUM_LIT> ; left = reg_class_contents [ rclass ] ; if ( hard_reg_set_intersect_p ( left , reg_class_contents [ ( int ) FCC_REGS ] ) ) { if ( loongarch_hard_regno_mode_ok ( FCC_REG_FIRST , mode ) ) size = MIN ( size , <NUM_LIT> ) ; left &= ~ reg_class_contents [ FCC_REGS ] ;


<s> if ( MFI . hasCalls ( ) ) return true ; return frameTriviallyRequiresSP ( MFI ) ;


<s> assert ( MO . isReg ( ) ) ; switch ( MO . getReg ( ) ) { case <STR_LIT> : return <NUM_LIT> ;


<s> void <ISA_LIT>DAGToDAGISel :: EmitSpecialCodeForMain ( MachineBasicBlock * BB , MachineFrameInfo * MFI ) { const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; if ( Subtarget -> isTargetCygMing ( ) ) {

unsigned CallOp = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;


return ( ( qword ) ( vec_perm ( av , vec_sra ( av , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) ) ;


<s> if ( BracCount -- != <NUM_LIT> ) { ErrMsg = <STR_LIT> ; return true ; } State = IES_RBRAC ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg ;


<s> switch ( c ) { case 'G' : return ( GET_MODE_CLASS ( GET_MODE ( value ) ) == MODE_FLOAT && value == CONST0_RTX ( GET_MODE ( value ) ) ) ; case 'H' : return ( GET_MODE ( value ) == VOIDmode && zap_mask ( CONST_DOUBLE_LOW ( value ) ) && zap_mask ( CONST_DOUBLE_HIGH ( value ) ) ) ; default :


<s> getAddrMode3OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; if ( ! MO . isReg ( ) ) { unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ;

MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ;


<s> if ( op1 == const0_rtx && ( cond == EQ || cond == NE || cond == LT || cond == GE ) && ( GET_CODE ( op0 ) == PLUS || GET_CODE ( op0 ) == MINUS || GET_CODE ( op0 ) == NEG || GET_CODE ( op0 ) == AND || GET_CODE ( op0 ) == IOR || GET_CODE ( op0 ) == XOR || GET_CODE ( op0 ) == NOT || GET_CODE ( op0 ) == ASHIFT || GET_CODE ( op0 ) == REG || GET_CODE ( op0 ) == MULT ) ) return CCZNmode ; return CCmode ;


<s> unsigned RegOpsNum = isMem ( MI , <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( SrcOpIdx1 != CommuteAnyOperandIndex && ( SrcOpIdx1 < <NUM_LIT> || SrcOpIdx1 > RegOpsNum ) ) return false ; if ( SrcOpIdx2 != CommuteAnyOperandIndex && ( SrcOpIdx2 < <NUM_LIT> || SrcOpIdx2 > RegOpsNum ) ) return false ; if ( SrcOpIdx1 == CommuteAnyOperandIndex || SrcOpIdx2 == CommuteAnyOperandIndex ) { unsigned CommutableOpIdx1 = SrcOpIdx1 ; unsigned CommutableOpIdx2 = SrcOpIdx2 ; if ( SrcOpIdx1 == SrcOpIdx2 ) CommutableOpIdx2 = RegOpsNum ; else if ( SrcOpIdx2 == CommuteAnyOperandIndex ) CommutableOpIdx2 = SrcOpIdx1 ; unsigned Op2Reg = MI -> getOperand ( CommutableOpIdx2 ) . getReg ( ) ; for ( CommutableOpIdx1 = RegOpsNum ; CommutableOpIdx1 > <NUM_LIT> ; CommutableOpIdx1 -- ) { if ( Op2Reg != MI -> getOperand ( CommutableOpIdx1 ) . getReg ( ) ) break ; } if ( CommutableOpIdx1 == <NUM_LIT> ) return false ; if ( ! fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , CommutableOpIdx1 , CommutableOpIdx2 ) ) return false ; }

return getFMA3OpcodeToCommuteOperands ( MI , SrcOpIdx1 , SrcOpIdx2 ) != <NUM_LIT> ;


<s> if ( II . getNumDefs ( ) >= <NUM_LIT> ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addReg ( Op1 ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 ) . addReg ( Op1 ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; } return ResultReg ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) == MI . getParent ( ) -> getNextNode ( ) ) MI . eraseFromParent ( ) ;


<s> int16x8x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x8_t ) __builtin_aarch64_get_qregxiv8hi ( __o , <NUM_LIT> ) ;


<s> if ( SOPKOpc == - <NUM_LIT> ) return ; if ( SOPKOpc == <STR_LIT> || SOPKOpc == <STR_LIT> ) { bool HasUImm ; if ( isKImmOrKUImmOperand ( Src1 , HasUImm ) ) { if ( ! HasUImm ) { SOPKOpc = ( SOPKOpc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } MI . setDesc ( TII -> get ( SOPKOpc ) ) ; } return ; } const MCInstrDesc & NewDesc = TII -> get ( SOPKOpc ) ;

if ( ( TII -> sopkIsZext ( SOPKOpc ) && isKUImmOperand ( Src1 ) ) || ( ! TII -> sopkIsZext ( SOPKOpc ) && isKImmOperand ( Src1 ) ) ) {


<s> SDValue rbit = DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , rbit ) ;


<s> return ( __m128d ) __builtin_ia32_minpd_mask ( ( __v2df ) __A , ( __v2df ) __B , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DL ( <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; LLT SrcTy = MRI . getType ( Src ) ; assert ( SrcTy == LLT :: scalar ( <NUM_LIT> ) ) ; auto One = Builder . buildConstant ( DstTy , <NUM_LIT> ) ; auto Zero = Builder . buildConstant ( DstTy , <NUM_LIT> ) ; Builder . buildSelect ( Dst , Src , One , Zero ) ; MI . eraseFromParent ( ) ; return true ;


<s> if ( MI -> readsRegister ( PredR ) && ( Cond != HII -> isPredicatedTrue ( MI ) ) ) continue ; } for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; RegisterRef RR = Op ; if ( RR . Reg == PredR ) { PredValid = false ; continue ; } if ( RR . Reg != RD . Reg ) continue ; if ( RR . Sub == RD . Sub ) return MI ; if ( RR . Sub == <NUM_LIT> || RD . Sub == <NUM_LIT> ) return <NUM_LIT> ; }


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ;

return Value >= <NUM_LIT> && Value < <NUM_LIT> ;


<s> } safe_inc_pos ( ) ; const char * stanza_name = match_to_right_bracket ( ) ; if ( ! stanza_name ) { diag ( pos , <STR_LIT> ) ; return PC_PARSEFAIL ; } curr_bif_stanza = stanza_name_to_stanza ( stanza_name ) ; if ( linebuf [ pos ] != ']' ) { diag ( pos , <STR_LIT> ) ; return PC_PARSEFAIL ; } safe_inc_pos ( ) ; consume_whitespace ( ) ;

if ( linebuf [ pos ] != '\n' && pos != LINELEN - <NUM_LIT> ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) {


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_int4 ) ( a ) , vec_splat ( ( vec_int4 ) ( si_from_int ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> if ( MBB -> canFallThrough ( ) ) return true ; for ( MachineBasicBlock * PB : MBB -> predecessors ( ) ) if ( PB -> isLayoutSuccessor ( MBB ) && PB -> canFallThrough ( ) ) return true ;


<s> void <ISA_LIT>MCCodeEmitter :: expandFunctionCall ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { MCInst TmpInst ; MCOperand Func ; Register Ra ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> void EmitInstrWithMacroNoAT ( const MachineInstr * MI ) ; private : bool emitPseudoExpansionLowering ( MCStreamer & OutStreamer , const MachineInstr * MI ) ; bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) ; const MachineConstantPool * MCP ; bool InConstantPool ; bool UsingConstantPools ; public : const <ISA_LIT>Subtarget * Subtarget ; const <ISA_LIT>FunctionInfo * <ISA_LIT>FI ; <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( <NUM_LIT> ) , InConstantPool ( false ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ;


<s> else if ( TARGET_C31 ) c4x_cpu_version = <NUM_LIT> ; else if ( TARGET_C32 ) c4x_cpu_version = <NUM_LIT> ; else if ( TARGET_C33 ) c4x_cpu_version = <NUM_LIT> ; else if ( TARGET_C40 ) c4x_cpu_version = <NUM_LIT> ; else if ( TARGET_C44 ) c4x_cpu_version = <NUM_LIT> ; else c4x_cpu_version = <NUM_LIT> ; if ( c4x_cpu_version_string ) { const char * p = c4x_cpu_version_string ; if ( * p == 'c' || * p == 'C' ) p ++ ; c4x_cpu_version = atoi ( p ) ; } target_flags &= ~ ( C30_FLAG | C31_FLAG | C32_FLAG | C33_FLAG | C40_FLAG | C44_FLAG ) ;


<s> unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Val == <STR_LIT> ) { O << <STR_LIT> ; return ; } const <STR_LIT> * Reg = <STR_LIT> ( Val ) ;

if ( Reg && Reg -> Writeable && Reg -> haveFeatures ( STI . getFeatureBits ( ) ) ) O << Reg -> Name ;


<s> Register DestReg = MRI -> createVirtualRegister ( SuperRC ) ; unsigned MergedOffset = std :: min ( CI . Offset , Paired . Offset ) ; auto MIB = BuildMI ( * MBB , InsertBefore , DL , TII -> get ( Opcode ) , DestReg ) ; AddressRegs Regs = getRegs ( Opcode , * TII ) ; if ( Regs . VAddr ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; MachineInstr * New = MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( CI . CPol ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( combineKnownAdjacentMMOs ( CI , Paired ) ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ;

const auto * Dest1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveEven ( SMLoc L ) { if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return false ; const MCSection * Section = getStreamer ( ) . getCurrentSectionOnly ( ) ; if ( ! Section ) {

getStreamer ( ) . InitSections ( false ) ;


<s> void printi16mem ( const MCInst * MI , unsigned OpNo ) {


<s> if ( * cum < <NUM_LIT> && <NUM_LIT> < * cum + ALPHA_ARG_SIZE ( mode , type , named ) ) words = <NUM_LIT> - * cum ;


<s> crtl -> uses_pic_offset_table = <NUM_LIT> ; return tilepro_got_rtx ( ) ; } temp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( temp , tilepro_got_symbol ( ) ) ;


<s> } else { IntegerTypes = <STR_LIT> ; } StringRef CapTypes = <STR_LIT> ; StringRef PurecapOptions = <STR_LIT> ; if ( FS . contains ( <STR_LIT> ) ) { if ( TT . isArch64Bit ( ) ) CapTypes = <STR_LIT> ; else CapTypes = <STR_LIT> ; <STR_LIT> ABI = <STR_LIT> ( Options . MCOptions . getABIName ( ) ) ; if ( ABI != <STR_LIT> && <STR_LIT> ( ABI ) ) PurecapOptions = <STR_LIT> ; } return ( <STR_LIT> + CapTypes + IntegerTypes + <STR_LIT> + PurecapOptions ) . str ( ) ;


<s> if ( Subtarget -> isELFv2ABI ( ) && ! MF -> getRegInfo ( ) . use_empty ( <STR_LIT> ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; MCSymbol * GlobalEntryLabel = <ISA_LIT>FI -> getGlobalEPSymbol ( ) ; OutStreamer -> EmitLabel ( GlobalEntryLabel ) ; const MCSymbolRefExpr * GlobalEntryLabelExp = MCSymbolRefExpr :: create ( GlobalEntryLabel , OutContext ) ; if ( TM . getCodeModel ( ) != CodeModel :: Large ) { MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , GlobalEntryLabelExp , OutContext ) ; const MCExpr * TOCDeltaHi = <ISA_LIT>MCExpr :: createHa ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = <ISA_LIT>MCExpr :: createLo ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaLo ) ) ; } else { MCSymbol * TOCOffset = <ISA_LIT>FI -> getTOCOffsetSymbol ( ) ; const MCExpr * TOCOffsetDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCOffset , OutContext ) , GlobalEntryLabelExp , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCOffsetDeltaExpr ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ;


<s> addPass ( create<ISA_LIT>LowerControlFlowPass ( ) ) ; addPass ( create<ISA_LIT>DebuggerInsertNopsPass ( ) ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( getMemScale ( ) ) ) ; Inst . addOperand ( MCOperand :: createReg ( getMemIndexReg ( ) ) ) ; addExpr ( Inst , getMemDisp ( ) ) ;

Inst . addOperand ( MCOperand :: createReg ( getMemSegReg ( ) ) ) ;


<s> initialize<ISA_LIT>AvoidSFBPassPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( unsigned HwMode ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , HwMode ) {


<s> gcc_assert ( FLOAT128_IEEE_P ( s_mode ) && TARGET_POWERPC64 ) ; if ( MEM_P ( src ) ) { rtx mem = ( WORDS_BIG_ENDIAN ? adjust_address ( src , DImode , <NUM_LIT> ) : adjust_address ( src , DImode , <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( dest_di , mem ) ) ; } else { unsigned int r = reg_or_subregno ( src ) ; if ( INT_REGNO_P ( r ) ) shift_reg = gen_rtx_REG ( DImode , r + ( BYTES_BIG_ENDIAN == <NUM_LIT> ) ) ; else { gcc_assert ( VSX_REGNO_P ( r ) ) ; if ( s_mode == KFmode ) emit_insn ( gen_signbitkf2_dm2 ( dest_di , src ) ) ; else emit_insn ( gen_signbittf2_dm2 ( dest_di , src ) ) ; }


<s> unsigned R = getRelaxedOpcodeArith ( Op ) ;


<s> * len = <NUM_LIT> ; return ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> ) ; default : if ( INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) break ; case <NUM_LIT> : * len = <NUM_LIT> ; return ( <STR_LIT> CR_TAB <STR_LIT> ) ; } } else if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) ) fatal_insn ( <STR_LIT> , insn ) ;

out_shift_with_cnt ( <STR_LIT> , insn , operands , len , <NUM_LIT> ) ;


<s> bool <ISA_LIT>LowerI1Copies :: runOnMachineFunction ( MachineFunction & TheMF ) { if ( TheMF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: Selected ) ) return false ; MF = & TheMF ; MRI = & MF -> getRegInfo ( ) ; DT = & getAnalysis < MachineDominatorTree > ( ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; ST = & MF -> getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; IsWave32 = ST -> isWave32 ( ) ; if ( IsWave32 ) { ExecReg = <STR_LIT> ; MovOp = <STR_LIT> ; AndOp = <STR_LIT> ; OrOp = <STR_LIT> ; XorOp = <STR_LIT> ; AndN2Op = <STR_LIT> ; OrN2Op = <STR_LIT> ; } else {


<s> EVT VT = V128Reg . getValueType ( ) ; unsigned WideSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT NarrowTy = <STR_LIT> ( EltTy , WideSize / <NUM_LIT> ) ;

return DAG . getTargetExtractSubreg ( <STR_LIT> , SDLoc ( V128Reg ) , NarrowTy , V128Reg ) ;


<s> __o = __builtin_aarch64_ld2v4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ;


<s> case <STR_LIT> : if ( ! isWQM ) { if ( ! ST -> hasCaymanISA ( ) && ! branchStackContains ( CFStack :: FIRST_NON_WQM_PUSH ) ) Item = CFStack :: FIRST_NON_WQM_PUSH ; else if ( CurrentEntries > <NUM_LIT> && ST -> getGeneration ( ) > <ISA_LIT>Subtarget :: EVERGREEN && ! ST -> hasCaymanISA ( ) && ! branchStackContains ( CFStack :: FIRST_NON_WQM_PUSH_W_FULL_ENTRY ) ) Item = CFStack :: FIRST_NON_WQM_PUSH_W_FULL_ENTRY ; else Item = CFStack :: SUB_ENTRY ; } else Item = CFStack :: ENTRY ;


<s> if ( GET_CODE ( address ) == REG && REGNO ( address ) == LR_REGNO ) SET_REGNO ( address , GPR_FIRST + <NUM_LIT> ) ; } } } frv_pack_insns ( ) ; memset ( frv_nops , <NUM_LIT> , sizeof ( frv_nops ) ) ; last_call = NULL ; for ( insn = get_insns ( ) ; insn ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( CALL_P ( insn ) || ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE && CALL_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ) ) last_call = insn ; if ( ! NOTE_P ( insn ) || NOTE_KIND ( insn ) != NOTE_INSN_CALL_ARG_LOCATION ) continue ; if ( NEXT_INSN ( last_call ) == insn ) continue ; SET_NEXT_INSN ( PREV_INSN ( insn ) ) = NEXT_INSN ( insn ) ; SET_PREV_INSN ( NEXT_INSN ( insn ) ) = PREV_INSN ( insn ) ; SET_PREV_INSN ( insn ) = last_call ; SET_NEXT_INSN ( insn ) = NEXT_INSN ( last_call ) ; SET_PREV_INSN ( NEXT_INSN ( insn ) ) = insn ; SET_NEXT_INSN ( PREV_INSN ( insn ) ) = insn ;


<s> llvm :: cast < GOTPLTEntry > ( * it ++ ) . setValue ( <NUM_LIT> ) ; llvm :: cast < GOTPLTEntry > ( * it ++ ) . setValue ( <NUM_LIT> ) ;

for ( ; it != end ( ) ; ++ it ) llvm :: cast < GOTPLTEntry > ( * it ) . setValue ( pltAddr ) ;


<s> case <STR_LIT> : if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; break ; case <STR_LIT> : NegateOperand = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( MemVT == <STR_LIT> ) NewOpc = <STR_LIT> ; else return false ; break ; } LoadSDNode * LoadNode = nullptr ; SDValue InputChain ; if ( ! isFusableLoadOpStorePattern ( StoreNode , StoredVal , CurDAG , LoadNode , InputChain ) ) return false ; SDValue Operand = StoredVal . getOperand ( <NUM_LIT> ) ; auto * OperandC = dyn_cast < ConstantSDNode > ( Operand ) ; if ( ! OperandC ) return false ; auto OperandV = OperandC -> getAPIntValue ( ) ; if ( NegateOperand ) OperandV = - OperandV ; if ( OperandV . getMinSignedBits ( ) > <NUM_LIT> ) return false ; Operand = CurDAG -> getTargetConstant ( OperandV , DL , MemVT ) ; SDValue Base , Disp ; if ( ! selectBDAddr20Only ( StoreNode -> getBasePtr ( ) , Base , Disp ) ) return false ; SDValue Ops [ ] = { Base , Disp , Operand , InputChain } ;

MachineSDNode * Result = CurDAG -> getMachineNode ( NewOpc , DL , <STR_LIT> , <STR_LIT> , Ops ) ;


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasVarSizedObjects ( ) ) { return - <NUM_LIT> ; } if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; Register IgnoredFrameReg ;

Offset = TFL -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) ;


<s> return ; } if ( ! ST . isVGPRSpillingEnabled ( MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) . getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( SpillSize ) ;

BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getFrameOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunction * MFI = MF . getInfo < <ISA_LIT>MachineFunction > ( ) ; unsigned OpCode = MFI -> getMode ( ) . FP32Denormals ? ( unsigned ) <STR_LIT> : ( unsigned ) <STR_LIT> ; SDValue fr = DAG . getNode ( OpCode , DL , FltVT , fqneg , fb , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ; fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ; jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ;

SDValue Div = DAG . getNode ( <STR_LIT> , DL , VT , iq , jq ) ;


<s> unsigned Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCOperand & Op1 = Inst . getOperand ( <NUM_LIT> ) ; if ( Op1 . isExpr ( ) ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addExpr ( Op1 . getExpr ( ) ) ) ; return false ;


<s> for ( auto DispSizePair = std :: next ( BlockingStoresDispSizeMap . begin ( ) ) ; DispSizePair != BlockingStoresDispSizeMap . end ( ) ; ++ DispSizePair ) { int64_t CurrDisp = DispSizePair -> first ; unsigned CurrSize = DispSizePair -> second ; if ( CurrDisp + CurrSize <= PrevDisp + PrevSize ) {


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ;

assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ;


<s> float16x4x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv4hf ( ( const __builtin_aarch64_simd_hf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float16x4_t ) __builtin_aarch64_get_dregciv4hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float16x4_t ) __builtin_aarch64_get_dregciv4hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float16x4_t ) __builtin_aarch64_get_dregciv4hf ( __o , <NUM_LIT> ) ; return ret ;


<s> bool hasHRESET ( ) const { return HasHRESET ;


<s> bool hasFFBH ( ) const { return ( getGeneration ( ) >= EVERGREEN ) ;


<s> matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; } if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ; SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) + Name . size ( ) ) ; getLexer ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createReg ( RegNo , S , E , isRV64 ( ) ) ) ; } if ( HadParens ) { getParser ( ) . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , getLoc ( ) , isRV64 ( ) ) ) ;


<s> return makeLibCall ( DAG , Call , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) , false , SDLoc ( Op ) ) . first ;


<s> SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; if ( V1 -> getOpcode ( ) != <STR_LIT> || V2 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return SDValue ( ) ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ;

if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return SDValue ( ) ;


<s> if ( V2 . getOpcode ( ) != <STR_LIT> || ! VT . isInteger ( ) || VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; unsigned Shift = <NUM_LIT> ; while ( ( <NUM_LIT> << Shift ) < NumElems ) { if ( SVOp -> getMaskElt ( <NUM_LIT> << Shift ) == <NUM_LIT> ) break ; Shift += <NUM_LIT> ; if ( Shift > <NUM_LIT> ) return SDValue ( ) ; } unsigned Mask = ( <NUM_LIT> << Shift ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { int EltIdx = SVOp -> getMaskElt ( i ) ; if ( ( i & Mask ) != <NUM_LIT> && EltIdx != - <NUM_LIT> ) return SDValue ( ) ; if ( ( i & Mask ) == <NUM_LIT> && ( unsigned ) EltIdx != ( i >> Shift ) ) return SDValue ( ) ; } unsigned NBits = VT . getVectorElementType ( ) . getSizeInBits ( ) << Shift ; MVT NeVT = <STR_LIT> ( NBits ) ; MVT NVT = <STR_LIT> ( NeVT , NumElems >> Shift ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NVT ) ) return SDValue ( ) ; unsigned SignificantBits = NVT . getSizeInBits ( ) >> Shift ; if ( V1 . getOpcode ( ) == <STR_LIT> && V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) == SignificantBits ) { SDValue V = V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; ConstantSDNode * CIdx = dyn_cast < ConstantSDNode > ( V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( CIdx && CIdx -> getZExtValue ( ) == <NUM_LIT> && ( ! <STR_LIT> ( V . getNode ( ) ) || ! V . hasOneUse ( ) ) ) { MVT FullVT = V . getSimpleValueType ( ) ; MVT V1VT = V1 . getSimpleValueType ( ) ; if ( FullVT . getSizeInBits ( ) > V1VT . getSizeInBits ( ) ) { unsigned Ratio = FullVT . getSizeInBits ( ) / V1VT . getSizeInBits ( ) ; MVT SubVecVT = <STR_LIT> ( FullVT . getVectorElementType ( ) , FullVT . getVectorNumElements ( ) / Ratio ) ; V = DAG . getNode ( <STR_LIT> , DL , SubVecVT , V , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } V1 = DAG . getNode ( <STR_LIT> , DL , V1VT , V ) ; } } return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , NVT , V1 ) ) ;


<s> DenseMap < unsigned , unsigned > SwizzleRemap ; BuildVector = CompactSwizzlableVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = dyn_cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ; if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [ Idx ] , <STR_LIT> ) ; } SwizzleRemap . clear ( ) ; BuildVector = ReorganizeVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {


<s> int OpClassID = Desc . OpInfo [ Op . getResNo ( ) ] . RegClass ; if ( OpClassID != - <NUM_LIT> ) { return TRI . getRegClass ( OpClassID ) ; } switch ( Op . getMachineOpcode ( ) ) { case AMDGPU :: COPY_TO_REGCLASS : OpClassID = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( isVSrc ( OpClassID ) ) return getRegClassForNode ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; return TRI . getRegClass ( OpClassID ) ; case AMDGPU :: EXTRACT_SUBREG : { int SubIdx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;

const TargetRegisterClass * SuperClass = getRegClassForNode ( DAG , Op . getOperand ( <NUM_LIT> ) ) ;


<s> MachineLoop * LoopRep = MLI -> getLoopFor ( MBB ) ; if ( ! LoopRep ) return false ;

MachineBasicBlock * LoopHeader = LoopRep -> getHeader ( ) ;


<s> void <ISA_LIT>65816TargetAsmStreamer :: EmitKeepDirective ( StringRef filename ) { OS << indent ;


<s> unsigned OffsetScaled = <NUM_LIT> ; while ( OffsetScaled < ObjSizeScaled ) { if ( ObjSizeScaled - OffsetScaled >= <NUM_LIT> ) { SDValue AddrNode = DAG . getMemBasePlusOffset ( Ptr , TypeSize :: Fixed ( OffsetScaled * <NUM_LIT> ) , dl ) ; SDValue St = DAG . getMemIntrinsicNode ( OpCode2 , dl , DAG . getVTList ( <STR_LIT> ) , { Chain , TagSrc , AddrNode } , <STR_LIT> , MF . getMachineMemOperand ( BaseMemOperand , OffsetScaled * <NUM_LIT> , <NUM_LIT> * <NUM_LIT> ) ) ; OffsetScaled += <NUM_LIT> ; OutChains . push_back ( St ) ; continue ; } if ( ObjSizeScaled - OffsetScaled > <NUM_LIT> ) { SDValue AddrNode = DAG . getMemBasePlusOffset ( Ptr , TypeSize :: Fixed ( OffsetScaled * <NUM_LIT> ) , dl ) ; SDValue St = DAG . getMemIntrinsicNode ( OpCode1 , dl , DAG . getVTList ( <STR_LIT> ) , { Chain , TagSrc , AddrNode } , <STR_LIT> , MF . getMachineMemOperand ( BaseMemOperand , OffsetScaled * <NUM_LIT> , <NUM_LIT> ) ) ;


<s> return ; case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : { assert ( SDValue ( N , <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ; if ( ! LoadNode -> isVolatile ( ) || LoadNode -> getMemoryVT ( ) != <STR_LIT> ) { return ; } SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; SDValue Pair = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) ) ; Results . append ( { Pair , Result . getValue ( <NUM_LIT> ) } ) ; return ; } case <STR_LIT> : ReplaceExtractSubVectorResults ( N , Results , DAG ) ; return ; case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : { SDLoc DL ( N ) ; auto Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; auto V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Op2 , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , VT , V ) ) ; return ; } case <STR_LIT> : { SDLoc DL ( N ) ; auto Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) { unsigned Idx = dyn_cast < ConstantSDNode > ( NewBldVec [ i ] . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( isUnmovable [ Idx ] ) continue ; std :: swap ( NewBldVec [ Idx ] , NewBldVec [ i ] ) ; std :: swap ( RemapSwizzle [ i ] , RemapSwizzle [ Idx ] ) ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FramePointerSaveIndex ( <NUM_LIT> ) , ReturnAddrSaveIndex ( <NUM_LIT> ) , BasePointerSaveIndex ( <NUM_LIT> ) , HasSpills ( false ) , HasNonRISpills ( false ) , SpillsCR ( false ) , SpillsVRSAVE ( false ) , LRStoreRequired ( false ) , MinReservedArea ( <NUM_LIT> ) , TailCallSPDelta ( <NUM_LIT> ) , HasFastCall ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgsStackOffset ( <NUM_LIT> ) , VarArgsNumGPR ( <NUM_LIT> ) , VarArgsNumFPR ( <NUM_LIT> ) , CRSpillFrameIndex ( <NUM_LIT> ) {


<s> return __builtin_mve_vrndaq_m_fv8hf ( __arm_vuninitializedq_f16 ( ) , __a , __p ) ;


<s> MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ;


<s> else emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op0 ) ) ; elt &= <NUM_LIT> ; elt *= <NUM_LIT> ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , gen_lowpart ( V4HImode , t0 ) , force_reg ( SImode , GEN_INT ( elt ) ) ) ) ;

emit_move_insn ( d -> target , gen_lowpart ( V8QImode , t1 ) ) ;


<s> assert ( getGeneration ( ) <= NORTHERN_ISLANDS ) ;


<s> continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> ) ; NewLoc . Block = & MF . front ( ) ; NewLoc . InsertionPt = & * NewLoc . Block -> begin ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NewLoc . InsertionPt ) ; FixupLocsForFn . emplace_back ( NewLoc ) ; continue ; } if ( IsLiveIn || UnsafeCount > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> ) ; FixupLocsForFn . emplace_back ( NewLoc ) ; continue ; } assert ( UnsafeCount == <NUM_LIT> && ! IsLiveIn && <STR_LIT> <STR_LIT> ) ; SmallPtrSetIterator < MachineInstr * > It = llvm :: find_if ( AllDefs , IsUnsafe ) ; assert ( It != AllDefs . end ( ) && <STR_LIT> ) ; MachineInstr * DefMI = * It ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( MOp . getReg ( ) , TRI ) << <STR_LIT> << * DefMI ) ; MachineBasicBlock :: iterator DefIt = DefMI ; ++ DefIt ; if ( DefIt != DefMI -> getParent ( ) -> end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * DefMI << <STR_LIT> << * DefIt ) ; NewLoc . Block = DefIt -> getParent ( ) ; NewLoc . InsertionPt = & * DefIt ; }


<s> const RegisterBank & EltRB = * RBI . getRegBank ( EltReg , MRI , TRI ) ; const RegisterBank & DstRB = * RBI . getRegBank ( Dst , MRI , TRI ) ; if ( EltRB != DstRB ) return false ; if ( any_of ( make_range ( I . operands_begin ( ) + <NUM_LIT> , I . operands_end ( ) ) , [ & MRI ] ( const MachineOperand & Op ) { return ! getOpcodeDef ( TargetOpcode :: G_IMPLICIT_DEF , Op . getReg ( ) , MRI ) ;


<s> void <ISA_LIT>InstPrinter :: printExtendedRegister ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) ; printArithExtend ( MI , OpNum + <NUM_LIT> , STI , O ) ;


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstant = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;


<s> rtx value = PATTERN ( producer ) ; rtx op = PATTERN ( consumer ) ; rtx early_op ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , <NUM_LIT> , <NUM_LIT> ) ; value = XEXP ( value , <NUM_LIT> ) ; if ( GET_CODE ( op ) == COND_EXEC ) op = COND_EXEC_CODE ( op ) ; if ( GET_CODE ( op ) == PARALLEL ) op = XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ; op = XEXP ( op , <NUM_LIT> ) ; early_op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( early_op ) != REG ) early_op = XEXP ( early_op , <NUM_LIT> ) ;

return ! reg_overlap_mentioned_p ( value , early_op ) ;


<s> int bs0 , bs1 , p , len ; if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) return <STR_LIT> ;

for ( bs0 = <NUM_LIT> ; bs0 < HOST_BITS_PER_WIDE_INT ; bs0 ++ ) if ( ( mask & ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << bs0 ) ) != <NUM_LIT> ) break ;


<s> if ( flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) ) return false ; } else gcc_assert ( use_rsqrt_p ( mode ) ) ; machine_mode mmsk = mode_for_int_vector ( mode ) . require ( ) ; rtx xmsk = gen_reg_rtx ( mmsk ) ; if ( ! recp ) emit_insn ( gen_rtx_SET ( xmsk , gen_rtx_NEG ( mmsk , gen_rtx_EQ ( mmsk , src , CONST0_RTX ( mode ) ) ) ) ) ; rtx xdst = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_rsqrte_type ( mode ) ) ( xdst , src ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? <NUM_LIT> : <NUM_LIT> ; if ( ( recp && flag_mrecip_low_precision_sqrt ) || ( ! recp && flag_mlow_precision_sqrt ) ) iterations -- ; rtx x1 = gen_reg_rtx ( mode ) ; while ( iterations -- ) { rtx x2 = gen_reg_rtx ( mode ) ; emit_set_insn ( x2 , gen_rtx_MULT ( mode , xdst , xdst ) ) ; emit_insn ( ( * get_rsqrts_type ( mode ) ) ( x1 , src , x2 ) ) ; if ( iterations > <NUM_LIT> ) emit_set_insn ( xdst , gen_rtx_MULT ( mode , xdst , x1 ) ) ; }


<s> if ( M . getModuleFlag ( <STR_LIT> ) ) FeatureFlagsAnd |= ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_IBT ; if ( M . getModuleFlag ( <STR_LIT> ) ) FeatureFlagsAnd |= ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_SHSTK ; if ( FeatureFlagsAnd ) { if ( ! TT . isArch32Bit ( ) && ! TT . isArch64Bit ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; int WordSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; emitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> emitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> emitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> emitIntValue ( FeatureFlagsAnd , <NUM_LIT> ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override {


<s> SDValue Arg = isFNEG ( DAG , N ) ; if ( ! Arg ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT VT = Arg . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; SDLoc DL ( N ) ; if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && Arg -> getFlags ( ) . hasNoSignedZeros ( ) && Subtarget . hasAnyFMA ( ) ) { SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; SDValue NewNode = DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Zero ) ; return DAG . getBitcast ( OrigVT , NewNode ) ; }

bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ;


<s> } auto InsertUsesDefs = [ & ] ( RegList & Regs , RegisterSet & UsesDefs ) { for ( unsigned Reg : Regs ) for ( MCSubRegIterator Subreg ( Reg , TRI , true ) ; Subreg . isValid ( ) ; ++ Subreg ) UsesDefs . insert ( * Subreg ) ; } ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const <ISA_LIT>TargetLowering * PTLI = TM . getTargetLowering ( ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; const std :: string FuncName = Func -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getTempdataLabel ( FuncName ) ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> , * MBB . getParent ( ) ) ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) {

unsigned opcode = ( SrcReg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> Type = ELF :: R_LANAI_21 ; break ; case <STR_LIT> : Type = ELF :: R_LANAI_21_F ; break ; case <STR_LIT> : Type = ELF :: R_LANAI_25 ; break ; case <STR_LIT> : case FK_Data_4 : Type = ELF :: R_LANAI_32 ; break ; case <STR_LIT> : Type = ELF :: R_LANAI_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_LANAI_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_LANAI_NONE ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return Type ;


<s> if ( Subtarget . hasPAuth ( ) ) MI . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: InternalRead ) ; MI . setMIFlag ( MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createNegateRAState ( nullptr ) ) ; BuildMI ( MBB , MBBPAC , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; if ( Subtarget . hasPAuth ( ) && MBBAUT != MBB . end ( ) && MBBAUT -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , MBBAUT , DL , TII -> get ( ShouldSignReturnAddrWithAKey ? <STR_LIT> : <STR_LIT> ) ) . copyImplicitOps ( * MBBAUT ) ;


<s> return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; }


<s> return new <ISA_LIT>PostLegalizerCombiner ( IsOptNone ) ;


<s> if ( ! II ) return false ; if ( isAMXCast ( II ) ) return false ; if ( II -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) return true ; for ( Value * V : II -> args ( ) ) { if ( V -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) return true ; }


<s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) {


<s> Value * <ISA_LIT>IREmitter :: visitINC ( const SDNode * N ) { Value * Op0 = visit ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Constant * Initializer = Constant :: getAllOnesValue ( Op0 -> getType ( ) ) ; Value * Op1 = Initializer -> stripInBoundsConstantOffsets ( ) ; StringRef BaseName = getInstructionName ( N ) ; if ( BaseName . empty ( ) ) { BaseName = getBaseValueName ( Op0 -> getName ( ) ) ; } if ( BaseName . empty ( ) ) { BaseName = getBaseValueName ( Op1 -> getName ( ) ) ; }

StringRef Name = getIndexedValueName ( BaseName ) ;


<s> void <ISA_LIT>PassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableRDFOpt ) addPass ( create<ISA_LIT>RDFOpt ( ) ) ; if ( ! Disable<ISA_LIT>CFGOpt ) addPass ( create<ISA_LIT>CFGOptimizer ( ) , false ) ;

if ( ! DisableAModeOpt ) addPass ( create<ISA_LIT>OptAddrMode ( ) , false ) ;


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( SrcReg ) ; unsigned DstReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( * MBB , MI , DL , TII -> get ( Opcode ) , DstReg ) . addReg ( SrcReg ) ; MI . eraseFromParent ( ) ;


<s> if ( ! DefMI -> isFullCopy ( ) ) return VReg ; VReg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == TargetOpcode :: COPY_TO_REGCLASS ) return ; if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ;


<s> return lowerV2F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4F32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I16Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ;


<s> swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == <NUM_LIT> ? d -> nelt : <NUM_LIT> ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) odd = <NUM_LIT> ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , <NUM_LIT> ) ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) {

unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * <NUM_LIT> + odd ) & mask ;


<s> if ( crtl -> calls_eh_return ) return true ;


<s> bool dst_aligned = MEM_ALIGN ( operands [ <NUM_LIT> ] ) >= BITS_PER_WORD ; unsigned int interleave_factor = ( src_aligned || dst_aligned ) ? <NUM_LIT> : <NUM_LIT> ; HOST_WIDE_INT bytes_per_iter = ( src_aligned || dst_aligned ) ? <NUM_LIT> : <NUM_LIT> ; if ( length > <NUM_LIT> ) arm_block_move_unaligned_loop ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , interleave_factor , bytes_per_iter ) ; else arm_block_move_unaligned_straight ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , interleave_factor ) ; } else { if ( length > <NUM_LIT> ) arm_block_move_unaligned_loop ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , <NUM_LIT> , <NUM_LIT> ) ; else arm_block_move_unaligned_straight ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , <NUM_LIT> ) ; } return <NUM_LIT> ;


<s> static SDValue LowerShiftParts ( SDValue Op , SelectionDAG & DAG ) { SDValue Lo , Hi ;

DAG . getTargetLoweringInfo ( ) . expandShiftParts ( Op . getNode ( ) , Lo , Hi , DAG ) ;


<s> bool <ISA_LIT>TargetLowering :: hasInlineStackProbe ( MachineFunction & MF ) const { if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ;


<s> O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg ( ) ) << <STR_LIT> ; if ( <STR_LIT> ( MO3 . getImm ( ) ) ) { if ( MO2 . getReg ( ) == <NUM_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> << TRI -> getAsmName ( MO2 . getReg ( ) ) ;


<s> } if ( Offs < <NUM_LIT> ) Offs = - Offs ; if ( AM . BaseGV == nullptr && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isUInt < <NUM_LIT> > ( Offs ) ) { return true ;


<s> vmvn_p8 ( poly8x8_t a ) { poly8x8_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align ( <NUM_LIT> ) , true ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const {

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ;


<s> BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else return true ; Cond [ <NUM_LIT> ] . setImm ( BranchCode ) ; }


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; addFullAddress ( MIB , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; if ( MMO ) MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return true ; } } unsigned ValReg = getRegForValue ( Val ) ; if ( ValReg == <NUM_LIT> ) return false ;


<s> bool arc_legitimate_pc_offset_p ( rtx addr ) { if ( GET_CODE ( addr ) != CONST ) return false ;


<s> AMDGPUPeepholeOpt :: ~ AMDGPUPeepholeOpt ( ) {


<s> SubIdx1 = <NUM_LIT> ; } BuildMI ( MBB , InsertBefore , DebugLoc ( ) , MCID ) . addReg ( SrcReg0 , getKillRegState ( IsKill ) , SubIdx0 ) . addReg ( SrcReg1 , getKillRegState ( IsKill ) , SubIdx1 ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( IS_VFP_REGNUM ( regno ) ) { if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) return <NUM_LIT> + regno - FIRST_VFP_REGNUM ; else return <NUM_LIT> + ( regno - FIRST_VFP_REGNUM ) / <NUM_LIT> ; } if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return <NUM_LIT> + regno - FIRST_IWMMXT_GR_REGNUM ;

if ( IS_IWMMXT_REGNUM ( regno ) ) return <NUM_LIT> + regno - FIRST_IWMMXT_REGNUM ;


<s> EVT OpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpVT . is256BitVector ( ) || OpVT . is128BitVector ( ) ) return Subtarget -> hasVLX ( ) ; return true ; } return false ;


<s> BuildMI ( LoopBB , I , DL , TII -> get ( TargetOpcode :: PHI ) , PhiExec ) . addReg ( InitSaveExecReg ) . addMBB ( & OrigBB ) . addReg ( NewExec ) . addMBB ( & LoopBB ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , getUndefRegState ( IdxReg . isUndef ( ) ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CondReg ) . addReg ( CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , <NUM_LIT> , IdxReg . getSubReg ( ) ) ; if ( UseGPRIdxMode ) { unsigned IdxReg ; if ( Offset == <NUM_LIT> ) { IdxReg = CurrentIdxReg ; } else { IdxReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , IdxReg ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ; } MachineInstr * SetIdx = BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IdxReg , RegState :: Kill ) ; SetIdx -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; } else { if ( Offset == <NUM_LIT> ) { BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CurrentIdxReg , RegState :: Kill ) ; } else { BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ;


<s> for ( NodeId N : DefQ ) { auto TA = DFG . addr < DefNode * > ( N ) ; bool IsPhi = TA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ; if ( ! IsPhi && ! PRI . alias ( RefRR , TA . Addr -> getRegRef ( DFG ) ) ) continue ; Defs . insert ( TA . Id ) ; Owners . insert ( TA . Addr -> getOwner ( DFG ) . Id ) ; } auto Block = [ this ] ( NodeAddr < InstrNode * > IA ) -> MachineBasicBlock * { if ( IA . Addr -> getKind ( ) == NodeAttrs :: Stmt ) return NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) -> getParent ( ) ; assert ( IA . Addr -> getKind ( ) == NodeAttrs :: Phi ) ; NodeAddr < PhiNode * > PA = IA ; NodeAddr < BlockNode * > BA = PA . Addr -> getOwner ( DFG ) ; return BA . Addr -> getCode ( ) ; } ; auto Less = [ & Block , this ] ( NodeId A , NodeId B ) -> bool { if ( A == B ) return false ; auto OA = DFG . addr < InstrNode * > ( A ) , OB = DFG . addr < InstrNode * > ( B ) ; MachineBasicBlock * BA = Block ( OA ) , * BB = Block ( OB ) ; if ( BA != BB ) return MDT . dominates ( BB , BA ) ; bool StmtA = OA . Addr -> getKind ( ) == NodeAttrs :: Stmt ; bool StmtB = OB . Addr -> getKind ( ) == NodeAttrs :: Stmt ; if ( StmtA ) { if ( ! StmtB ) return true ; MachineInstr * CA = NodeAddr < StmtNode * > ( OA ) . Addr -> getCode ( ) ; MachineInstr * CB = NodeAddr < StmtNode * > ( OB ) . Addr -> getCode ( ) ; if ( CA == CB ) return A < B ; return MDT . dominates ( CB , CA ) ; } else { if ( StmtB ) return false ;


<s> MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ;

for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ;


<s> unsigned getNumFixupKinds ( ) const override {


<s> } if ( SDWA9EncValues :: SRC_SGPR_MIN <= Val && Val <= ( isGFX10Plus ( ) ? SDWA9EncValues :: SRC_SGPR_MAX_GFX10 : SDWA9EncValues :: SRC_SGPR_MAX_<ISA_LIT> ) ) { return createSRegOperand ( getSgprClassId ( Width ) , Val - SDWA9EncValues :: SRC_SGPR_MIN ) ; } if ( SDWA9EncValues :: SRC_TTMP_MIN <= Val && Val <= SDWA9EncValues :: SRC_TTMP_MAX ) { return createSRegOperand ( getTtmpClassId ( Width ) , Val - SDWA9EncValues :: SRC_TTMP_MIN ) ; } const unsigned SVal = Val - SDWA9EncValues :: SRC_SGPR_MIN ; if ( INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX ) return decodeIntImmed ( SVal ) ; if ( INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX ) return decodeFPImmed ( Width , SVal ) ; return decodeSpecialReg32 ( SVal ) ;

} else if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) {


<s> if ( CC == CallingConv :: GHC ) return NULL ;

return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask ;


<s> return ; } if ( ! global ) { fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> ) ; }


<s> return ParseMemoryOperand ( Operands , <NUM_LIT> , false ) ;


<s> DCRegisterSema * create<ISA_LIT>DCRegisterSema ( StringRef TT , const MCRegisterInfo & MRI , const MCInstrInfo & MII ) { return new <ISA_LIT>RegisterSema ( MRI , MII ) ;


<s> MVT InVT = In . getSimpleValueType ( ) ; MVT VTElt = VT . getVectorElementType ( ) ; MVT InVTElt = InVT . getVectorElementType ( ) ; SDLoc dl ( Op ) ; if ( ( InVTElt == <STR_LIT> ) && ( ( ( Subtarget -> hasBWI ( ) && Subtarget -> hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget -> hasBWI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) <= <NUM_LIT> ) ) || ( ( Subtarget -> hasDQI ( ) && Subtarget -> hasVLX ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) || ( ( Subtarget -> hasDQI ( ) && VT . is512BitVector ( ) && VTElt . getSizeInBits ( ) >= <NUM_LIT> ) ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) {

if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( In . getOpcode ( ) , dl , VT , In . getOperand ( <NUM_LIT> ) ) ;


<s> if ( ! register_operand ( output , mode ) ) output = gen_reg_rtx ( mode ) ; if ( TARGET_Z196 && ( mode == SImode || mode == DImode ) ) do_const_opt = ( is_weak && CONST_INT_P ( cmp ) ) ; if ( do_const_opt ) { const int very_unlikely = REG_BR_PROB_BASE / <NUM_LIT> - <NUM_LIT> ; rtx cc = gen_rtx_REG ( CCZmode , CC_REGNUM ) ; skip_cs_label = gen_label_rtx ( ) ; emit_move_insn ( btarget , const0_rtx ) ; if ( CONST_INT_P ( cmp ) && INTVAL ( cmp ) == <NUM_LIT> ) { rtvec lt = rtvec_alloc ( <NUM_LIT> ) ; RTVEC_ELT ( lt , <NUM_LIT> ) = gen_rtx_SET ( cc , gen_rtx_COMPARE ( CCZmode , mem , cmp ) ) ;

RTVEC_ELT ( lt , <NUM_LIT> ) = gen_rtx_SET ( output , mem ) ;


<s> ix86_compute_frame_layout ( & frame ) ; return frame . to_allocate == <NUM_LIT> && frame . nregs == <NUM_LIT> ;


<s> AllowDollarAtStartOfIdentifier = ( AssemblerDialect == AD_HLASM ) ; AllowHashAtStartOfIdentifier = ( AssemblerDialect == AD_HLASM ) ; DotIsPC = ( AssemblerDialect == AD_ATT ) ; StarIsPC = ( AssemblerDialect == AD_HLASM ) ; EmitGNUAsmStartIndentationMarker = ( AssemblerDialect == AD_ATT ) ; AllowAtInName = ( AssemblerDialect == AD_HLASM ) ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ;

ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createInvalid ( SMLoc StartLoc , SMLoc EndLoc ) { return std :: make_unique < <ISA_LIT>Operand > ( KindInvalid , StartLoc , EndLoc ) ;


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const {


<s> virtual void RecordRelocation ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , uint64_t & FixedValue ) {


<s> static unsigned getADDriOpcode ( int64_t Imm ) { return <STR_LIT> ;


<s> if ( ! Subtarget -> is64Bit ( ) ) return false ; unsigned GPRCnt = <NUM_LIT> ; unsigned FPRCnt = <NUM_LIT> ; unsigned Idx = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { ++ Idx ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SwiftSelf ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SwiftError ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : ++ GPRCnt ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasSSE1 ( ) ) return false ; ++ FPRCnt ; break ;


<s> int i ; msp430x = true ; for ( i = ARRAY_SIZE ( msp430_mcu_names ) ; i -- ; ) if ( strcasecmp ( msp430_mcu_names [ i ] , target_mcu ) == <NUM_LIT> ) { msp430x = false ;


<s> static SDValue concat128BitVectors ( SDValue V1 , SDValue V2 , EVT VT , unsigned NumElems , SelectionDAG & DAG , SDLoc dl ) {

SDValue V = insert128BitVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> , DAG , dl ) ;


<s> <ISA_LIT>BranchRelaxation ( ) : MachineFunctionPass ( ID ) {


<s> BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateImm ( Mask ) ) ; BICInst . addOperand ( MCOperand :: CreateImm ( Pred ) ) ; BICInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ;

BICInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> return new <ISA_LIT>ExpandISEL ( ) ;


<s> const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI , Paired ) ; Register DestReg = MRI -> createVirtualRegister ( SuperRC ) ; unsigned MergedOffset = std :: min ( CI . Offset , Paired . Offset ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; MachineInstr * New = BuildMI ( * MBB , InsertBefore , DL , TII -> get ( Opcode ) , DestReg ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sbase ) ) . addImm ( MergedOffset ) . addImm ( CI . CPol ) . addMemOperand ( combineKnownAdjacentMMOs ( CI , Paired ) ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: sdst ) ; const auto * Dest1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: sdst ) ;

BuildMI ( * MBB , InsertBefore , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ;


<s> return ( TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! isTargetDarwin ( ) && ! isTargetWindows ( ) ;


<s> if ( ! MFI -> hasVarSizedObjects ( ) && ! MFI -> hasOpaqueSPAdjustment ( ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned BaseReg = TRI -> getBaseRegister ( ) ; for ( unsigned R : ClobberSet ) if ( BaseReg == R ) return true ;


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { int BOpc = <STR_LIT> ; int BccOpc = <STR_LIT> ; assert ( TBB && <STR_LIT> ) ; int regPos = <NUM_LIT> ; if ( ! Cond . empty ( ) && Cond [ <NUM_LIT> ] . isImm ( ) && Cond [ <NUM_LIT> ] . getImm ( ) == <NUM_LIT> ) { BccOpc = <STR_LIT> ; regPos = <NUM_LIT> ; } if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) { MachineBasicBlock * NewTBB , * NewFBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineInstr * Term = MBB . getFirstTerminator ( ) ; if ( isPredicated ( Term ) && ! AnalyzeBranch ( MBB , NewTBB , NewFBB , Cond , false ) ) { MachineBasicBlock * NextBB = std :: next ( MachineFunction :: iterator ( & MBB ) ) ; if ( NewTBB == NextBB ) {


<s> for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { DL = II -> getDebugLoc ( ) ; if ( ! DL . isUnknown ( ) ) return DL ; } } return DL ;


<s> assert ( res && <STR_LIT> ) ; ( void ) res ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _blsr_u64 ( unsigned long long __X ) {


<s> auto & TD = DAG . getDataLayout ( ) ; EVT PTy = getPointerTy ( TD ) ; unsigned EntrySize = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) -> getEntrySize ( TD ) ; Index = DAG . getNode ( <STR_LIT> , DL , PTy , Index , DAG . getConstant ( EntrySize , DL , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Index , Table ) ; EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( DAG . getMachineFunction ( ) ) , MemVT , false , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; if ( ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) || ABI . IsN64 ( ) ) {

Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Addr , getPICJumpTableRelocBase ( Table , DAG ) ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ; case <STR_LIT> : case <STR_LIT> : return TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ;


<s> unsigned NumDefCFAOffsets = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Instrs . size ( ) ; i != e ; ++ i ) { const MCCFIInstruction & Inst = Instrs [ i ] ; switch ( Inst . getOperation ( ) ) { default : return <NUM_LIT> ; case MCCFIInstruction :: OpDefCfaRegister : { HasFP = true ; if ( * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) != ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) return <NUM_LIT> ; memset ( SavedRegs , <NUM_LIT> , sizeof ( SavedRegs ) ) ; StackAdjust = <NUM_LIT> ; SavedRegIdx = <NUM_LIT> ; InstrOffset += MoveInstrSize ; break ; } case MCCFIInstruction :: OpDefCfaOffset : { StackSize = std :: abs ( Inst . getOffset ( ) ) / StackDivide ; ++ NumDefCFAOffsets ; break ; } case MCCFIInstruction :: OpOffset : { if ( SavedRegIdx == CU_NUM_SAVED_REGS ) return CU :: UNWIND_MODE_DWARF ; unsigned Reg = * MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; SavedRegs [ SavedRegIdx ++ ] = Reg ; StackAdjust += OffsetSize ; InstrOffset += PushInstrSize ( Reg ) ; break ; } } } StackAdjust /= StackDivide ; if ( HasFP ) { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust ) return CU :: UNWIND_MODE_DWARF ; uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame ( ) ; if ( RegEnc == ~ <NUM_LIT> ) return CU :: UNWIND_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_MODE_BP_FRAME ; CompactUnwindEncoding |= ( StackAdjust & <NUM_LIT> ) << <NUM_LIT> ; CompactUnwindEncoding |= RegEnc & CU :: UNWIND_BP_FRAME_REGISTERS ; } else { SubtractInstrIdx += InstrOffset ; ++ StackAdjust ; if ( ( StackSize & <NUM_LIT> ) == StackSize ) { CompactUnwindEncoding |= CU :: UNWIND_MODE_STACK_IMMD ; CompactUnwindEncoding |= ( StackSize & <NUM_LIT> ) << <NUM_LIT> ;


<s> int TypeLengthIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: TypeLength ) ; BrigType BT = static_cast < BrigType > ( MI -> getOperand ( TypeLengthIdx ) . getImm ( ) ) ;

if ( ! isNaturalAlignment ( BT , Align ) ) O << <STR_LIT> << formatDec ( Align ) << <STR_LIT> ;


<s> assert ( ! isImmTy ( ImmTyNone ) || ! hasModifiers ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( Imm . Val ) ) ; setImmKindNone ( ) ;


<s> return new <ISA_LIT>FastISel ( funcInfo ) ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT SetCCResultType = TLI . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; if ( Opcode == <STR_LIT> && ! TLI . isOperationLegal ( <STR_LIT> , VT ) ) { SDValue Sub = DAG . getNode ( <STR_LIT> , DL , VT , X , Y ) ; SDValue Cmp = DAG . getSetCC ( DL , SetCCResultType , X , Y , <STR_LIT> ) ; if ( SetCCResultType == VT && DAG . ComputeNumSignBits ( Cmp ) == VT . getScalarSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Sub ) ; return DAG . getSelect ( DL , VT , Cmp , Sub , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; }


<s> vld1_dup_u32 ( const uint32_t * __a ) { return vdup_n_u32 ( * __a ) ;


<s> Base = N . getOperand ( <NUM_LIT> ) ; OffImm = N . getOperand ( <NUM_LIT> ) ; if ( ! GAN ) return true ; const GlobalValue * GV = GAN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; const DataLayout * DL = TLI -> getDataLayout ( ) ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; if ( Alignment == <NUM_LIT> && Ty -> isSized ( ) && ! Subtarget -> isTargetDarwin ( ) ) Alignment = DL -> getABITypeAlignment ( Ty ) ; if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ;

if ( Base . getOpcode ( ) == <STR_LIT> ) {


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { unsigned Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt32Immediate ( RHS , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( ( int ) Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm >> <NUM_LIT> ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; } Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt32Immediate ( RHS , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else { short SImm ; if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( ( int ) SImm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) { SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> ) ) , <NUM_LIT> ) ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Xor , getI64Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; }


<s> auto const BBEnd = Begin -> getParent ( ) -> end ( ) ; auto const BottomMI = End == BBEnd ? std :: prev ( End ) : End ; auto AfterBottomMI = std :: next ( BottomMI ) ; if ( AfterBottomMI == BBEnd || & * AfterBottomMI != UPTracker . getLastTrackedMI ( ) ) { UPTracker . reset ( * BottomMI ) ;


<s> unsigned <ISA_LIT>TargetLowering :: GetAlignedArgumentStackSize ( unsigned StackSize , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( TM . getRegisterInfo ( ) ) ; const TargetFrameLowering & TFI = * TM . getFrameLowering ( ) ; unsigned StackAlignment = TFI . getStackAlignment ( ) ; uint64_t AlignMask = StackAlignment - <NUM_LIT> ; int64_t Offset = StackSize ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ; } else {

Offset = ( ( ~ AlignMask ) & Offset ) + StackAlignment + ( StackAlignment - SlotSize ) ;


<s> return false ; case InlineAsm :: Constraint_A : OutOps . push_back ( Op ) ; return false ; default :


<s> bool isBDAddr32Disp20 ( ) const { return isMemDisp20 ( BDMem , ADDR32Reg ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_VectorListAllLanes ) ; Op -> VectorList . RegNum = RegNum ; Op -> VectorList . Count = Count ; Op -> VectorList . isDoubleSpaced = isDoubleSpaced ;


<s> <ISA_LIT>MachineFunctionInfo :: <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {


<s> if ( VT == <STR_LIT> ) return <NUM_LIT> ; return TargetLowering :: getNumRegistersForInlineAsm ( Context , VT ) ;


<s> Worklist . push_back ( N ) ; Worklist . push_back ( User ) ; if ( SDNode :: hasPredecessorHelper ( N , Visited , Worklist ) || SDNode :: hasPredecessorHelper ( User , Visited , Worklist ) ) return false ; return true ;