<s> m68hc11_split_move ( gen_rtx_MEM ( GET_MODE ( to ) , reg ) , from , scratch ) ; if ( code == POST_DEC ) emit_insn ( gen_addhi3 ( reg , reg , GEN_INT ( offset ) ) ) ; return ; } if ( ( autoinc_to != autoinc_from && autoinc_to != CONST && autoinc_from != CONST ) || ( autoinc_to != CONST && reg_mentioned_p ( XEXP ( XEXP ( to , <NUM_LIT> ) , <NUM_LIT> ) , from ) && ! IS_STACK_PUSH ( to ) ) ) { code = GET_CODE ( XEXP ( to , <NUM_LIT> ) ) ; reg = XEXP ( XEXP ( to , <NUM_LIT> ) , <NUM_LIT> ) ; offset = GET_MODE_SIZE ( GET_MODE ( to ) ) ; if ( code == PRE_DEC || code == POST_DEC ) offset = - offset ; if ( code == PRE_DEC || code == PRE_INC ) emit_insn ( gen_addhi3 ( reg , reg , GEN_INT ( offset ) ) ) ; m68hc11_split_move ( gen_rtx_MEM ( GET_MODE ( to ) , reg ) , from , scratch ) ; if ( code == POST_DEC || code == POST_INC ) emit_insn ( gen_addhi3 ( reg , reg , GEN_INT ( offset ) ) ) ; return ; } if ( autoinc_from != CONST && reg_mentioned_p ( XEXP ( XEXP ( from , <NUM_LIT> ) , <NUM_LIT> ) , to ) && ! IS_STACK_PUSH ( to ) ) { code = GET_CODE ( XEXP ( from , <NUM_LIT> ) ) ; reg = XEXP ( XEXP ( from , <NUM_LIT> ) , <NUM_LIT> ) ; offset = GET_MODE_SIZE ( GET_MODE ( from ) ) ; if ( code == PRE_DEC || code == POST_DEC ) offset = - offset ; if ( code == PRE_DEC || code == PRE_INC ) emit_insn ( gen_addhi3 ( reg , reg , GEN_INT ( offset ) ) ) ; m68hc11_split_move ( to , gen_rtx_MEM ( GET_MODE ( from ) , reg ) , scratch ) ; if ( code == POST_DEC || code == POST_INC ) emit_insn ( gen_addhi3 ( reg , reg , GEN_INT ( offset ) ) ) ; return ; } } if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) mode = SImode ; else if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) mode = HImode ; else mode = QImode ; if ( TARGET_M6812 && IS_STACK_PUSH ( to ) && reg_mentioned_p ( gen_rtx_REG ( HImode , HARD_SP_REGNUM ) , from ) ) { if ( mode == SImode ) { offset = <NUM_LIT> ; } else if ( mode == HImode ) { offset = <NUM_LIT> ; } else offset = <NUM_LIT> ; } low_to = m68hc11_gen_lowpart ( mode , to ) ;

high_to = m68hc11_gen_highpart ( mode , to ) ;


<s> if ( NeedsPadding ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addExpr ( Sym ) . addReg ( <NUM_LIT> ) ) ; const MCSymbol * TlsGetAddr = Ctx . getOrCreateSymbol ( <STR_LIT> ) ; if ( NeedsPadding ) { if ( ! UseGot ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; } if ( UseGot ) { const MCExpr * Expr = MCSymbolRefExpr :: create ( TlsGetAddr , MCSymbolRefExpr :: VK_GOTPCREL , Ctx ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addExpr ( Expr ) . addReg ( <NUM_LIT> ) ) ; } else { EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( TlsGetAddr , MCSymbolRefExpr :: VK_PLT , Ctx ) ) ) ; } } else { if ( SRVK == MCSymbolRefExpr :: VK_TLSGD && ! UseGot ) { EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( Sym ) . addReg ( <NUM_LIT> ) ) ; } else { EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addExpr ( Sym ) . addReg ( <NUM_LIT> ) ) ; } const MCSymbol * TlsGetAddr = Ctx . getOrCreateSymbol ( <STR_LIT> ) ;


<s> return ! STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasXMM ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ; InstOps . push_back ( SrcPtr ) ; InstOps . push_back ( DAG . getConstant ( ArgSize , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( ArgMode , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( Align , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , & InstOps [ <NUM_LIT> ] , InstOps . size ( ) , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ;

Chain = VAARG . getValue ( <NUM_LIT> ) ;


<s> printf ( <STR_LIT> , mcu_name [ i ] , i == n_mcus - <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( i && ! strcmp ( mcu_name [ i ] , mcu_name [ i - <NUM_LIT> ] ) ) {


<s> MVT WideVT = ExtVT ; if ( ! ExtVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) { NumElts *= <NUM_LIT> / ExtVT . getSizeInBits ( ) ; InVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; In = DAG . getNode ( <STR_LIT> , DL , InVT , DAG . getUNDEF ( InVT ) , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; WideVT = <STR_LIT> ( ExtVT . getVectorElementType ( ) , NumElts ) ; } SDValue One = DAG . getConstant ( <NUM_LIT> , DL , WideVT ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , WideVT ) ; SDValue SelectedVal = DAG . getSelect ( DL , WideVT , In , One , Zero ) ; if ( VT != ExtVT ) { WideVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SelectedVal = DAG . getNode ( <STR_LIT> , DL , WideVT , SelectedVal ) ; } if ( WideVT != VT ) SelectedVal = DAG . getNode ( <STR_LIT> , DL , VT , SelectedVal , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return SelectedVal ;


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned Idx = <NUM_LIT> ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getMaskedMemoryOpCost ( unsigned Opcode , Type * Src , Align Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind ) { if ( ! isa < ScalableVectorType > ( Src ) ) return BaseT :: getMaskedMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; return LT . first * <NUM_LIT> ;


<s> a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT> ] ) ;


<s> func_iterator func_begin ( ) { return mFuncs . begin ( ) ;


<s> if ( MOI . getOrdering ( ) == AtomicOrdering :: Acquire || MOI . getOrdering ( ) == AtomicOrdering :: AcquireRelease || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent || MOI . getFailureOrdering ( ) == AtomicOrdering :: Acquire || MOI . getFailureOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) { Changed |= CC -> insertWait ( MI , MOI . getScope ( ) , MOI . getOrderingAddrSpace ( ) , isAtomicRet ( * MI ) ? <STR_LIT> : <STR_LIT> , MOI . getIsCrossAddressSpaceOrdering ( ) , Position :: AFTER ) ; Changed |= CC -> insertAcquire ( MI , MOI . getScope ( ) , MOI . getOrderingAddrSpace ( ) , Position :: AFTER ) ;


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ;

return Value >= <NUM_LIT> && Value < <NUM_LIT> ;


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ; EmitAlignment ( F -> getAlignment ( ) , F ) ; EmitFunctionBodyStart ( ) ; EmitFunctionHeader ( ) ; MachineFunction :: const_iterator MBB ; for ( MBB = MF . begin ( ) ; MBB != MF . end ( ) ; ++ MBB ) { OutStreamer . EmitRawText ( NewLine ) ; printMBBInfo ( MBB ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( ! NoNans ) return SDValue ( ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; } } switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : { SDValue Cmeq ; if ( IsZero ) Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; else Cmeq = DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cmeq ) ; } case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , LHS , RHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> : if ( IsZero ) return DAG . getNode ( <STR_LIT> , dl , VT , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RHS , LHS ) ; case <STR_LIT> :


<s> ReplaceLDSUseImpl LDSUseReplacer { M } ; return LDSUseReplacer . replaceLDSUse ( ) ;


<s> if ( ! NeedWait ) return false ; if ( Counts . Named . EXP == <NUM_LIT> ) ExpInstrTypesSeen = <NUM_LIT> ; BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WAITCNT ) ) . addImm ( ( Counts . Named . VM & <NUM_LIT> ) | ( ( Counts . Named . EXP & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Counts . Named . LGKM & <NUM_LIT> ) << <NUM_LIT> ) ) ; LastOpcodeType = OTHER ; return true ;


return ( __m128 ) __builtin_ia32_cvtdq2ps ( ( __v4si ) __A ) ;


<s> bool x86_extended_reg_mentioned_p ( rtx insn ) {

return for_each_rtx ( & PATTERN ( insn ) , extended_reg_mentioned_1 , NULL ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; }

if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) {


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> MCSection * getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const override { return DataSection ;


<s> ApplyRegBankMapping ( MachineRegisterInfo & MRI_ , const RegisterBank * RB ) : MRI ( MRI_ ) , NewBank ( RB ) {


<s> return StringSwitch < unsigned > ( Name ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_TYPE ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_SIZE ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_LENGTH ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_OFFSET ) . Default ( IOK_INVALID ) ;


<s> CUMULATIVE_ARGS args_so_far_v ; cumulative_args_t args_so_far ; if ( ! fun ) return false ; fntype = fun ; if ( ! TYPE_P ( fun ) ) fntype = TREE_TYPE ( fun ) ; if ( ( ! incoming && ! prototype_p ( fntype ) ) || stdarg_p ( fntype ) ) return true ; INIT_CUMULATIVE_INCOMING_ARGS ( args_so_far_v , fntype , NULL_RTX ) ; args_so_far = pack_cumulative_args ( & args_so_far_v ) ; if ( incoming ) { gcc_assert ( DECL_P ( fun ) ) ; result = DECL_RESULT ( fun ) ; } else result = TREE_TYPE ( fntype ) ; if ( result && aggregate_value_p ( result , fntype ) ) { if ( ! TYPE_P ( result ) ) result = TREE_TYPE ( result ) ; result = build_pointer_type ( result ) ; rs6000_parm_needs_stack ( args_so_far , result ) ; } if ( incoming ) {


<s> return new <ISA_LIT>StackTagging ( MergeInit ) ;


<s> return true ; } else if ( ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) {

Base = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( CurDAG -> getEntryNode ( ) ) , AMDGPU :: ZERO , <STR_LIT> ) ;


<s> SmallString < <NUM_LIT> > EHSecName ( Prefix ) ; if ( FnSecName != <STR_LIT> ) { EHSecName += FnSecName ; } const MCSymbolELF * Group = FnSection . getGroup ( ) ; if ( Group ) Flags |= ELF :: SHF_GROUP ; MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , true , FnSection . getUniqueID ( ) , static_cast < const MCSymbolELF * > ( FnSection . getBeginSymbol ( ) ) ) ; assert ( EHSection && <STR_LIT> ) ; SwitchSection ( EHSection ) ;


<s> MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; getParser ( ) . getStreamer ( ) . EmitInstruction ( Inst , getSTI ( ) ) ; return false ;


<s> const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( Src ) == S64 ) ; auto Trunc = B . buildIntrinsicTrunc ( S64 , Src ) ; const auto Zero = B . buildFConstant ( S64 , <NUM_LIT> ) ; const auto One = B . buildFConstant ( S64 , <NUM_LIT> ) ; auto Lt0 = B . buildFCmp ( CmpInst :: FCMP_OGT , S1 , Src , Zero ) ; auto NeTrunc = B . buildFCmp ( CmpInst :: FCMP_ONE , S1 , Src , Trunc ) ; auto And = B . buildAnd ( S1 , Lt0 , NeTrunc ) ; auto Add = B . buildSelect ( S64 , And , One , Zero ) ; B . buildFAdd ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Trunc , Add ) ;


<s> bool <ISA_LIT>InstructionSelector :: isRegInFprb ( Register Reg , MachineRegisterInfo & MRI ) const { return RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) == <STR_LIT> ;


<s> assert ( VAddr0Idx != - <NUM_LIT> ) ; assert ( SrsrcIdx != - <NUM_LIT> ) ; assert ( SrsrcIdx > VAddr0Idx ) ; if ( DimIdx == - <NUM_LIT> ) return true ; unsigned Dim = Inst . getOperand ( DimIdx ) . getImm ( ) ; const <STR_LIT> * DimInfo = <STR_LIT> ( Dim ) ; bool IsNSA = SrsrcIdx - VAddr0Idx > <NUM_LIT> ; unsigned VAddrSize = IsNSA ? SrsrcIdx - VAddr0Idx : <STR_LIT> ( getMRI ( ) , Desc , VAddr0Idx ) / <NUM_LIT> ; unsigned AddrSize = BaseOpcode -> NumExtraArgs + ( BaseOpcode -> Gradients ? DimInfo -> NumGradients : <NUM_LIT> ) + ( BaseOpcode -> Coordinates ? DimInfo -> NumCoords : <NUM_LIT> ) + ( BaseOpcode -> LodOrClampOrMip ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! IsNSA ) { if ( AddrSize > <NUM_LIT> ) AddrSize = <NUM_LIT> ; else if ( AddrSize > <NUM_LIT> ) AddrSize = <NUM_LIT> ; } return VAddrSize == AddrSize ;


<s> LiveInterval & LI = LIS -> getInterval ( Reg ) ; for ( MCRegister PhysReg : RegClassInfo . getOrder ( MRI -> getRegClass ( Reg ) ) ) { if ( ! MRI -> isPhysRegUsed ( PhysReg ) && Matrix -> checkInterference ( LI , PhysReg ) == LiveRegMatrix :: IK_Free ) { Matrix -> assign ( LI , PhysReg ) ; assert ( PhysReg != <NUM_LIT> ) ; RegsToRewrite . push_back ( Reg ) ; return true ; } }


<s> return thumb_base_register_rtx_p ( x , QImode , strict_p ) ;


<s> MachineOperand & FIOp = MI -> getOperand ( FIOperandNum ) ; int Index = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { spillSGPR ( MI , Index , RS ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { restoreSGPR ( MI , Index , RS ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand * VData = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ; buildSpillLoadStore ( MI , <STR_LIT> , Index , VData -> getReg ( ) , VData -> isKill ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) -> getReg ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) -> getReg ( ) , TII -> getNamedOperand ( * MI , <STR_LIT> :: offset ) -> getImm ( ) , * MI -> memoperands_begin ( ) , RS ) ; MFI -> addToSpilledVGPRs ( getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ) ; MI -> eraseFromParent ( ) ; break ; }


<s> <ISA_LIT>AsmBackendDarwin ( const Target & T , const Triple & TT , MachO :: CPUSubType<ISA_LIT> st ) : <ISA_LIT>AsmBackend ( T , TT , true ) , Subtype ( st ) {


<s> auto & QST = MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const auto & QII = * QST . getInstrInfo ( ) ; if ( IsTop ) { for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( Packet [ i ] , SU , QII ) ) return false ; } else { for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) if ( hasDependence ( SU , Packet [ i ] , QII ) ) return false ; }


<s> if ( CanCommute ) { if ( CommuteIdx0 == OpNo ) CommuteOpNo = CommuteIdx1 ; else if ( CommuteIdx1 == OpNo ) CommuteOpNo = CommuteIdx0 ; } if ( CanCommute && ( ! MI -> getOperand ( CommuteIdx0 ) . isReg ( ) || ! MI -> getOperand ( CommuteIdx1 ) . isReg ( ) ) ) return false ; if ( ! CanCommute || ! TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ) return false ; if ( ! TII -> isOperandLegal ( * MI , CommuteOpNo , OpToFold ) ) { if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( OpToFold -> isImm ( ) || OpToFold -> isFI ( ) || OpToFold -> isGlobal ( ) ) ) { MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0 ; MachineOperand & OtherOp = MI -> getOperand ( OtherIdx ) ; if ( ! OtherOp . isReg ( ) || ! TII -> getRegisterInfo ( ) . isVGPR ( MRI , OtherOp . getReg ( ) ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isDef ( ) ) ; unsigned MaybeCommutedOpc = MI -> getOpcode ( ) ; int Op32 = <STR_LIT> ( MaybeCommutedOpc ) ; FoldList . push_back ( FoldCandidate ( MI , CommuteOpNo , OpToFold , true , Op32 ) ) ; return true ; } TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ; return false ; } FoldList . push_back ( FoldCandidate ( MI , CommuteOpNo , OpToFold , true ) ) ;


<s> assert ( isPowerOf2_32 ( TyWidth ) && <STR_LIT> ) ;


<s> if ( isUncheckedLoadOrStoreOpcode ( UseI -> getOpcode ( ) ) ) { unsigned OpIdx = TII -> getLoadStoreImmIdx ( UseI -> getOpcode ( ) ) - <NUM_LIT> ; if ( UseI -> getOperand ( OpIdx ) . isReg ( ) && UseI -> getOperand ( OpIdx ) . getReg ( ) == TaggedReg ) { UseI -> getOperand ( OpIdx ) . ChangeToFrameIndex ( FI ) ; UseI -> getOperand ( OpIdx ) . setTargetFlags ( <STR_LIT> ) ; } } else if ( UseI -> isCopy ( ) && Register :: isVirtualRegister ( UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) {

uncheckUsesOf ( UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI ) ;


<s> bool <ISA_LIT>InvISelDAG :: SelectAddrMode6Offset ( SDNode * Op , SDValue N , SDValue & Offset ) { return true ;


<s> if ( ! Ty ) return nullptr ; TypeName = Ty -> getName ( ) ; } uint64_t AccessIndex ; uint32_t ArgIndex = ( Kind == <ISA_LIT>PreserveUnionAI ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! getAccessIndex ( Call -> getArgOperand ( ArgIndex ) , AccessIndex ) ) return nullptr ; AccessIndices . push_back ( AccessIndex ) ; if ( TypeName . size ( ) ) { TypeNameIndex = AccessIndices . size ( ) - <NUM_LIT> ; LastTypeName = TypeName ; TypeMeta = MDN ; } Kind = AIChain [ Call ] . second ; Call = AIChain [ Call ] . first ;


<s> } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs / <NUM_LIT> ) ) return false ; } else if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ; } else llvm_unreachable ( <STR_LIT> ) ; if ( AM . Scale == <NUM_LIT> ) return true ; if ( AM . Scale == <NUM_LIT> && AM . HasBaseReg ) return true ; return false ; case <ISA_LIT>AS :: PRIVATE_ADDRESS : return isLegalMUBUFAddressingMode ( AM ) ; case <ISA_LIT>AS :: LOCAL_ADDRESS : case <ISA_LIT>AS :: REGION_ADDRESS : if ( ! isUInt < <NUM_LIT> > ( AM . BaseOffs ) ) return false ;


<s> NodeSet getAllReachedUses ( RegisterRef RefRR , NodeAddr < DefNode * > DefA ) { return getAllReachedUses ( RefRR , DefA , NoRegs ) ;


<s> Attribute A = MF . getFunction ( ) -> getFnAttribute ( ShaderTypeAttribute ) ; if ( A . isStringAttribute ( ) ) { StringRef Str = A . getValueAsString ( ) ; if ( Str . getAsInteger ( <NUM_LIT> , ShaderType ) ) llvm_unreachable ( <STR_LIT> ) ; }


<s> <ISA_LIT>OptimizeMathLibCalls ( <ISA_LIT>TargetMachine & TM_ ) : FunctionPass ( ID ) , TM ( TM_ ) {


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( DL ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) , RI ( STI . getTargetTriple ( ) ) {


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ;


<s> void <ISA_LIT>InstPrinter :: printAddrMode7Operand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; O << markup ( <STR_LIT> ) << <STR_LIT> ;


<s> dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired ( ) ) { MIB . addReg ( Reg2 , getDefRegState ( true ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx + <NUM_LIT> ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ; } MIB . addReg ( Reg1 , getDefRegState ( true ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ;


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( Subtarget . isTargetGNUAEABI ( ) || Subtarget . isTargetMuslAEABI ( ) ) this -> Options . EABIVersion = EABI :: GNU ;

else this -> Options . EABIVersion = EABI :: EABI5 ;


<s> MachineFunction * MF = MBB -> getParent ( ) ; for ( auto i = scc_begin ( MF ) , ie = scc_end ( MF ) ;


<s> int64_t Value = ConstExpr -> getValue ( ) ;

return ( ( Value & ~ <NUM_LIT> ) == <NUM_LIT> ) ;


<s> LastOpcodeType = OTHER ; LastInstWritesM0 = false ; ReturnsVoid = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ; memset ( & UsedRegs , <NUM_LIT> , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , <NUM_LIT> , sizeof ( DefinedRegs ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ;

for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ;


<s> case MOV_EBP : ++ NumMovEBPInstructions ; break ; case MOV_ESP : ++ NumMovESPInstructions ; break ; case LEA_ESI : ++ NumLeaESIInstructions ; break ;

case LEA_EDI : ++ NumLeaEDIInstructions ; break ;


<s> ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( p -> label ) ) ;

output_asm_insn ( <STR_LIT> , & p -> value ) ;


<s> bool aarch64_is_extend_from_extract ( machine_mode mode , rtx mult_imm , rtx extract_imm ) { HOST_WIDE_INT mult_val , extract_val ; if ( ! CONST_INT_P ( mult_imm ) || ! CONST_INT_P ( extract_imm ) ) return false ; mult_val = INTVAL ( mult_imm ) ;


<s> PM . add ( create<ISA_LIT>FixupHwLoops ( ) ) ; } PM . add ( create<ISA_LIT>ExpandPredSpillCode ( get<ISA_LIT>TargetMachine ( ) ) ) ;

PM . add ( create<ISA_LIT>SplitTFRCondSets ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> SMLoc S ; bool Result = true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) Parser . Lex ( ) ; switch ( getLexer ( ) . getKind ( ) ) { default : return true ; case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Integer :


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ;


<s> if ( VT == <STR_LIT> ) return LowerFROUND32 ( Op , DAG ) ;

if ( VT == <STR_LIT> ) return LowerFROUND64 ( Op , DAG ) ;


<s> if ( ! Subtarget -> hasSSSE3orAVX ( ) || ( VT == <STR_LIT> && ! Subtarget -> hasAVX2 ( ) ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) { SDValue Mask = N1 . getOperand ( <NUM_LIT> ) ; SDValue X = N1 . getOperand ( <NUM_LIT> ) ; SDValue Y ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( N0 . getOperand ( <NUM_LIT> ) == Mask ) Y = N0 . getOperand ( <NUM_LIT> ) ; if ( ! Y . getNode ( ) ) return SDValue ( ) ; if ( Mask . getOpcode ( ) != <STR_LIT> || X . getOpcode ( ) != <STR_LIT> || Y . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Mask = Mask . getOperand ( <NUM_LIT> ) ; EVT MaskVT = Mask . getValueType ( ) ; if ( Mask . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; switch ( cast < ConstantSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return SDValue ( ) ; } SDValue SraC = Mask . getOperand ( <NUM_LIT> ) ; unsigned SraAmt = cast < ConstantSDNode > ( SraC ) -> getZExtValue ( ) ; unsigned EltBits = MaskVT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; DebugLoc DL = N -> getDebugLoc ( ) ; X = X . getOperand ( <NUM_LIT> ) ; Y = Y . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) == <STR_LIT> && Y . getOperand ( <NUM_LIT> ) == X && <STR_LIT> ( Y . getOperand ( <NUM_LIT> ) . getNode ( ) ) && X . getValueType ( ) == MaskVT && X . getValueType ( ) == Y . getValueType ( ) && ( EltBits == <NUM_LIT> || EltBits == <NUM_LIT> || EltBits == <NUM_LIT> ) ) { SDValue Sign = DAG . getNode ( <STR_LIT> , DL , MaskVT , X , Mask . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Sign ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( * this ) , TLInfo ( TM , * this ) { ParseSubtargetFeatures ( CPU , FS ) ;

InstrItins = getInstrItineraryForCPU ( CPU ) ;


<s> return false ; } if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> && TNS == <NUM_LIT> && MLI -> getLoopFor ( TB ) == L ) ; bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) JB = FB ; FB = nullptr ; } } else { if ( FSB == TB ) JB = TB ; TB = nullptr ;


<s> default : assert ( false && <STR_LIT> ) ; break ; } MachineBasicBlock :: iterator Next ; for ( I = Prev ? Prev -> getIterator ( ) : MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MaskMI = * I ; switch ( MaskMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : combineMasks ( MaskMI ) ; break ;


<s> for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size ) return SDValue ( ) ; MaskOps . push_back ( Mask [ i ] < Size ? AllOnes : Zero ) ; } SDValue V1Mask = DAG . getBuildVector ( VT , DL , MaskOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V1Mask ) ; V2 = DAG . getNode ( <STR_LIT> , DL , VT , V1Mask , V2 ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = Helper [ RV ] ; AttributeList A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeList :: FunctionIndex , Attribute :: NoInline ) ; FunctionCallee F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & I ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( & I ) ) { FunctionType * FT = CI -> getFunctionType ( ) ; Function * F_ = CI -> getCalledFunction ( ) ; if ( needsFPReturnHelper ( * FT ) && ! ( F_ && isIntrinsicInline ( F_ ) ) ) { Modified = true ; F . addFnAttr ( <STR_LIT> ) ; } if ( F_ && ! isIntrinsicInline ( F_ ) ) { if ( needsFPReturnHelper ( * F_ ) ) { Modified = true ;


<s> static Target The<ISA_LIT>beTarget ;


<s> case Instruction :: Xor : case Instruction :: Mul : case Instruction :: FCmp : return false ; case Instruction :: ICmp : case Instruction :: Add : return ScalarBits < <NUM_LIT> && ( ScalarBits * cast < VectorType > ( Ty ) -> getNumElements ( ) ) % <NUM_LIT> == <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; } return false ;


<s> else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) || Flag . isSwiftSelf ( ) || Flag . isSwiftError ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( Callee && ! computeCallAddress ( Callee , Addr ) ) return false ; if ( Subtarget -> isTargetWindows ( ) && Addr . getGlobalValue ( ) && Addr . getGlobalValue ( ) -> hasExternalWeakLinkage ( ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; if ( RegInfo -> isAnyArgRegReserved ( * MF ) ) RegInfo -> emitReservedArgRegCallError ( * MF ) ; MachineInstrBuilder MIB ;

if ( Subtarget -> useSmallAddressing ( ) ) {


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> insn = emit_insn ( gen_gpr_save ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; }


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , false ) {


<s> RegisterMCAsmInfoFn C ( The<ISA_LIT>32Target , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn D ( The<ISA_LIT>64Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>32Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>32Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstrInfo ) ;

TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>32Target , create<ISA_LIT>MCRegisterInfo ) ;


<s> SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; }

if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ;


<s> assert ( Pred . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned CCValid = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned CCMask = Pred [ <NUM_LIT> ] . getImm ( ) ; assert ( CCMask > <NUM_LIT> && CCMask < <NUM_LIT> && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MI . setDesc ( get ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ;


<s> } if ( ! validateMIMGR128 ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGD16 ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGDataSize ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGAtomicDMask ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGGatherDMask ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; }


<s> } return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Shift ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ;

return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> const char * name = LABEL_NAME ( insn ) ; PUT_CODE ( insn , NOTE ) ; NOTE_KIND ( insn ) = NOTE_INSN_DELETED_LABEL ; NOTE_DELETED_LABEL_NAME ( insn ) = name ; } merge_bb = <NUM_LIT> ; continue ; } case <NUM_LIT> : case <NUM_LIT> : if ( ! NONDEBUG_INSN_P ( insn ) ) break ; rtx_insn * prev , * pprev ; rtx * patp , pat , cond ; bool annulled ; annulled = false ; prev = PREV_INSN ( insn ) ; pprev = PREV_INSN ( prev ) ; if ( pprev && NEXT_INSN ( NEXT_INSN ( pprev ) ) == NEXT_INSN ( insn ) && JUMP_P ( prev ) && get_attr_cond ( prev ) == COND_USE ) { if ( ! INSN_ANNULLED_BRANCH_P ( prev ) ) break ; annulled = true ; } patp = & PATTERN ( insn ) ; pat = * patp ; cond = arc_get_ccfsm_cond ( statep , INSN_FROM_TARGET_P ( insn ) ) ; if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { pat = conditionalize_nonjump ( pat , cond , insn , annulled ) ; } else if ( simplejump_p ( insn ) ) { patp = & SET_SRC ( pat ) ; pat = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , * patp , pc_rtx ) ; } else if ( JUMP_P ( insn ) && ANY_RETURN_P ( PATTERN ( insn ) ) ) { pat = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , pat , pc_rtx ) ; pat = gen_rtx_SET ( VOIDmode , pc_rtx , pat ) ; } else gcc_unreachable ( ) ; validate_change ( insn , patp , pat , <NUM_LIT> ) ; if ( ! apply_change_group ( ) ) gcc_unreachable ( ) ; if ( JUMP_P ( insn ) ) { rtx_insn * next = next_nonnote_insn ( insn ) ; if ( GET_CODE ( next ) == BARRIER ) delete_insn ( next ) ; if ( statep -> state == <NUM_LIT> ) continue ; } break ;


<s> if ( InVT == <STR_LIT> && ResVT == <STR_LIT> ) { SDNode * U64 = DAG . getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ; SDNode * In64 = DAG . getMachineNode ( TargetOpcode :: INSERT_SUBREG , DL , <STR_LIT> , SDValue ( U64 , <NUM_LIT> ) , In , SubReg32 ) ; SDValue Out64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( In64 , <NUM_LIT> ) ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Out64 , Shift32 ) ; SDValue Out = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shift ) ;


<s> <ISA_LIT>MachineFunctionInfo :: <ISA_LIT>MachineFunctionInfo ( const MachineFunction & MF ) : <ISA_LIT>MachineFunction ( MF ) , TIDReg ( <STR_LIT> ) , ScratchRSrcReg ( <STR_LIT> ) , ScratchWaveOffsetReg ( <STR_LIT> ) , PrivateSegmentBufferUserSGPR ( <STR_LIT> ) , DispatchPtrUserSGPR ( <STR_LIT> ) , QueuePtrUserSGPR ( <STR_LIT> ) , KernargSegmentPtrUserSGPR ( <STR_LIT> ) , DispatchIDUserSGPR ( <STR_LIT> ) , FlatScratchInitUserSGPR ( <STR_LIT> ) , PrivateSegmentSizeUserSGPR ( <STR_LIT> ) , GridWorkGroupCountXUserSGPR ( <STR_LIT> ) , GridWorkGroupCountYUserSGPR ( <STR_LIT> ) , GridWorkGroupCountZUserSGPR ( <STR_LIT> ) , WorkGroupIDXSystemSGPR ( <STR_LIT> ) , WorkGroupIDYSystemSGPR ( <STR_LIT> ) , WorkGroupIDZSystemSGPR ( <STR_LIT> ) , WorkGroupInfoSystemSGPR ( <STR_LIT> ) , PrivateSegmentWaveByteOffsetSystemSGPR ( <STR_LIT> ) , P<ISA_LIT>nputAddr ( <NUM_LIT> ) , ReturnsVoid ( true ) , MaximumWorkGroupSize ( <NUM_LIT> ) , DebuggerReservedVGPRCount ( <NUM_LIT> ) , DebuggerWorkGroupIDStackObjectIndices ( { { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ) , DebuggerWorkItemIDStackObjectIndices ( { { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ) , LDSWaveSpillSize ( <NUM_LIT> ) , P<ISA_LIT>nputEna ( <NUM_LIT> ) , NumUserSGPRs ( <NUM_LIT> ) , NumSystemSGPRs ( <NUM_LIT> ) , HasSpilledSGPRs ( false ) , HasSpilledVGPRs ( false ) , HasNonSpillStackObjects ( false ) , HasFlatInstructions ( false ) , NumSpilledSGPRs ( <NUM_LIT> ) , NumSpilledVGPRs ( <NUM_LIT> ) , PrivateSegmentBuffer ( false ) , DispatchPtr ( false ) , QueuePtr ( false ) , DispatchID ( false ) , KernargSegmentPtr ( false ) , FlatScratchInit ( false ) , GridWorkgroupCountX ( false ) , GridWorkgroupCountY ( false ) , GridWorkgroupCountZ ( false ) , WorkGroupIDX ( false ) , WorkGroupIDY ( false ) , WorkGroupIDZ ( false ) , WorkGroupInfo ( false ) , PrivateSegmentWaveByteOffset ( false ) , WorkItemIDX ( false ) , WorkItemIDY ( false ) , WorkItemIDZ ( false ) { const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const Function * F = MF . getFunction ( ) ;


<s> void <ISA_LIT>PostRASchedStrategy :: leaveMBB ( ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * MBB ) << <STR_LIT> ; ) ;

advanceTo ( MBB -> getFirstTerminator ( ) ) ;


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ;

int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ;


SDValue ShufPS = lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , CastV1 , CastV2 , DAG ) ;


<s> MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { SplitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( MI ) ;


<s> case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) {

FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> else if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( XEXP ( x , <NUM_LIT> ) ) , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( legitimate_constant_pool_address_p ( x ) ) { if ( TARGET_AIX && ( ! TARGET_ELF || ! TARGET_MINIMAL_TOC ) ) { rtx contains_minus = XEXP ( x , <NUM_LIT> ) ; rtx minus , symref ; const char * name ;

while ( GET_CODE ( XEXP ( contains_minus , <NUM_LIT> ) ) != MINUS ) contains_minus = XEXP ( contains_minus , <NUM_LIT> ) ;


<s> else if ( Tok . getString ( ) == <STR_LIT> ) return parseSetMacroDirective ( ) ; else if ( Tok . getString ( ) == <STR_LIT> ) return parseSetNoMacroDirective ( ) ; return true ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) { if ( ! MRI -> getRegClassOrNull ( Reg ) ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; } return true ; } default :

return selectImpl ( I , * CoverageInfo ) ;


<s> SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Op = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Op ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> if ( MMO -> getAlignment ( ) < <NUM_LIT> ) return false ; } if ( MI -> getNumOperands ( ) > <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return false ; if ( MI -> getNumOperands ( ) > <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return false ; int Opcode = MI -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> :

return MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ;


<s> case XOR : { rtx op0 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; rtx op1 = XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; if ( GET_CODE ( op0 ) != REG || sparc_check_64 ( op0 , insn ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( GET_CODE ( op1 ) == CONST_INT ) return INTVAL ( op1 ) >= <NUM_LIT> ; return ( GET_CODE ( op1 ) == REG && sparc_check_64 ( op1 , insn ) == <NUM_LIT> ) ; } case LSHIFTRT : return GET_MODE ( SET_SRC ( pat ) ) == SImode ; case CONST_DOUBLE : return ! ( CONST_DOUBLE_LOW ( SET_SRC ( pat ) ) & <NUM_LIT> ) ; case CONST_INT : return ! ( INTVAL ( SET_SRC ( pat ) ) & <NUM_LIT> ) ; case ASHIFTRT : case SIGN_EXTEND : return - ( GET_MODE ( SET_SRC ( pat ) ) == SImode ) ;


<s> return makeArrayRef ( <STR_LIT> . begin ( ) , ST . getMaxNumVGPRs ( MF ) ) ;


<s> AllocatedReg ( const TargetRegisterClass * RC , unsigned Reg ) : RC ( RC ) , Reg ( Reg ) {


<s> } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetFeature ( <STR_LIT> ) ;


<s> uint64_t SizeInBits = DL -> getTypeSizeInBits ( SI -> getValueOperand ( ) -> getType ( ) ) ; assert ( ( ( SizeInBits & <NUM_LIT> ) || ( SizeInBits >> <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ;

return ( unsigned ) SizeInBits >> <NUM_LIT> ;


<s> ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; return ret ;


<s> last = adjust_address ( op , QImode , width / BITS_PER_UNIT - <NUM_LIT> ) ; if ( TARGET_BIG_ENDIAN ) * left = first , * right = last ; else * left = last , * right = first ;


<s> MachineBasicBlock * Bottom = Loop -> getHeader ( ) ; for ( MachineBasicBlock * MBB : Loop -> blocks ( ) ) if ( MBB -> getNumber ( ) > Bottom -> getNumber ( ) ) Bottom = MBB ;


<s> enum rtx_code code ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; if ( code == GE || code == GEU || code == LE || code == LEU || code == NE ) { gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) ; PUT_CODE ( operands [ <NUM_LIT> ] , reverse_condition ( code ) ) ;


<s> bool <ISA_LIT>MCAsmStreamer :: EmitValueToOffset ( const MCExpr * Offset , unsigned char Value ) { return false ;


<s> BuildVector = ReorganizeVector ( DAG , BuildVector , SwizzleRemap ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned Idx = cast < ConstantSDNode > ( Swz [ i ] ) -> getZExtValue ( ) ; if ( SwizzleRemap . find ( Idx ) != SwizzleRemap . end ( ) ) Swz [ i ] = DAG . getConstant ( SwizzleRemap [ Idx ] , DL , <STR_LIT> ) ; } return BuildVector ;


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT . getSimpleVT ( ) , Legal ) ;

setIndexedStoreAction ( im , VT . getSimpleVT ( ) , Legal ) ;


<s> void addUnsignedOffset_b8s2Operands ( MCInst & Inst , unsigned N ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) >> <NUM_LIT> ) ) ; return ; } const MCSymbolRefExpr * SR = cast < MCSymbolRefExpr > ( Imm . Val ) ; Inst . addOperand ( MCOperand :: createExpr ( SR ) ) ;


<s> <ISA_LIT>SEInstrInfo :: <ISA_LIT>SEInstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>InstrInfo ( tm , tm . getRelocationModel ( ) == Reloc :: PIC_ ? <STR_LIT> : <STR_LIT> ) , RI ( * tm . getSubtargetImpl ( ) ) , IsN64 ( tm . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_N64 ( ) ) {


<s> <ISA_LIT>WinCOFFTargetStreamer ( MCStreamer & S ) : <ISA_LIT>TargetStreamer ( S ) {


<s> <ISA_LIT>AddressSanitizer ( const MCSubtargetInfo * & STI ) : <ISA_LIT>AsmInstrumentation ( STI ) , RepPrefix ( false ) , OrigSPOffset ( <NUM_LIT> ) {


<s> if ( r0 ) { rtx r1 = gen_reg_rtx ( SImode ) ; mask = gen_reg_rtx ( TImode ) ; emit_move_insn ( mask , GEN_INT ( - <NUM_LIT> ) ) ; emit_insn ( gen_rotqby_ti ( s0 , s0 , r0 ) ) ; emit_insn ( gen_rotqby_ti ( s1 , s1 , r0 ) ) ; if ( GET_CODE ( r0 ) == CONST_INT ) r1 = GEN_INT ( INTVAL ( r0 ) & <NUM_LIT> ) ; else emit_insn ( gen_andsi3 ( r1 , r0 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_shlqby_ti ( mask , mask , r1 ) ) ; emit_insn ( gen_selb ( s0 , s1 , s0 , mask ) ) ; } } } else if ( GET_CODE ( src ) == SUBREG ) { rtx r = SUBREG_REG ( src ) ; gcc_assert ( REG_P ( r ) && SCALAR_INT_MODE_P ( GET_MODE ( r ) ) ) ; s0 = gen_reg_rtx ( TImode ) ; if ( GET_MODE_SIZE ( GET_MODE ( r ) ) < GET_MODE_SIZE ( TImode ) ) emit_insn ( gen_rtx_SET ( VOIDmode , s0 , gen_rtx_ZERO_EXTEND ( TImode , r ) ) ) ; else emit_move_insn ( s0 , src ) ; } else { gcc_assert ( REG_P ( src ) && GET_MODE ( src ) == TImode ) ; s0 = gen_reg_rtx ( TImode ) ; emit_move_insn ( s0 , src ) ; } if ( start ) emit_insn ( gen_rotlti3 ( s0 , s0 , GEN_INT ( start ) ) ) ; if ( <NUM_LIT> - width ) s0 = expand_shift ( RSHIFT_EXPR , TImode , s0 , <NUM_LIT> - width , s0 , unsignedp ) ;


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> static bool ok_for_max_constant ( HOST_WIDE_INT val ) {

if ( rx_max_constant_size == <NUM_LIT> || rx_max_constant_size == <NUM_LIT> ) return true ;


return ( int64x2_t ) __builtin_neon_vreinterpretv2div2di ( ( int64x2_t ) __a ) ;


<s> unsigned int max_common_align ; max_common_align = TARGET_64BIT ? <NUM_LIT> : ( size >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( align > max_common_align ) {

warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> , align / BITS_PER_UNIT , name , max_common_align / BITS_PER_UNIT ) ;


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) : MCInstPrinter ( MAI , MII , MRI ) {

setAvailableFeatures ( STI . getFeatureBits ( ) ) ;


<s> Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) return DCI . CombineTo ( N , Cond , SDValue ( ) ) ; return Cond ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool isFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier = true ; break ; } } if ( isFastMultiplier ) { APInt Diff = TrueC -> getAPIntValue ( ) - FalseC -> getAPIntValue ( ) ; Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , <STR_LIT> ) , Cond ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; if ( Diff != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( Diff , Cond . getValueType ( ) ) ) ; if ( FalseC -> getAPIntValue ( ) != <NUM_LIT> ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; if ( N -> getNumValues ( ) == <NUM_LIT> ) return DCI . CombineTo ( N , Cond , SDValue ( ) ) ; return Cond ; } } }


<s> break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; case <STR_LIT> : UOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; isCond = true ; break ; } unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; ImmBranches . push_back ( ImmBranch ( I , MaxOffs , isCond , UOpc ) ) ; } if ( Opc == <STR_LIT> ) continue ; for ( unsigned op = <NUM_LIT> , e = I -> getNumOperands ( ) ; op != e ; ++ op ) if ( I -> getOperand ( op ) . isCPI ( ) ) { unsigned Bits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool NegOk = false ; unsigned LongFormBits = <NUM_LIT> ; unsigned LongFormScale = <NUM_LIT> ; unsigned LongFormOpcode = <NUM_LIT> ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; LongFormOpcode = <STR_LIT> ; LongFormBits = <NUM_LIT> ; LongFormScale = <NUM_LIT> ; break ; case <STR_LIT> : Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; NegOk = true ; break ; } unsigned CPI = I -> getOperand ( op ) . getIndex ( ) ; MachineInstr * CPEMI = CPEMIs [ CPI ] ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ;

unsigned LongFormMaxOffs = ( ( <NUM_LIT> << LongFormBits ) - <NUM_LIT> ) * LongFormScale ;


<s> void rs6000_cpu_cpp_builtins ( cpp_reader * pfile ) { rs6000_target_modify_macros ( true , rs6000_isa_flags , rs6000_builtin_mask_calculate ( ) ) ; if ( TARGET_FRE ) builtin_define ( <STR_LIT> ) ; if ( TARGET_FRES ) builtin_define ( <STR_LIT> ) ; if ( TARGET_FRSQRTE ) builtin_define ( <STR_LIT> ) ; if ( TARGET_FRSQRTES ) builtin_define ( <STR_LIT> ) ; if ( TARGET_EXTRA_BUILTINS && cpp_get_options ( pfile ) -> lang != CLK_ASM ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; if ( ! flag_iso ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; init_vector_keywords ( ) ; cpp_get_callbacks ( pfile ) -> macro_to_expand = rs6000_macro_to_expand ; } } if ( ( ! ( TARGET_HARD_FLOAT && ( TARGET_FPRS || TARGET_E500_DOUBLE ) ) ) || ( TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_DOUBLE_FLOAT ) ) builtin_define ( <STR_LIT> ) ; if ( rs6000_cpu == PROCESSOR_PPC405 ) builtin_define ( <STR_LIT> ) ; if ( TARGET_NO_LWSYNC ) builtin_define ( <STR_LIT> ) ; if ( TARGET_EXTRA_BUILTINS ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } builtin_define ( <STR_LIT> ) ; RS6000_CPU_CPP_ENDIAN_BUILTINS ( ) ; if ( TARGET_LONG_DOUBLE_128 ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } switch ( TARGET_CMODEL ) { case CMODEL_MEDIUM : builtin_define ( <STR_LIT> ) ; break ; case CMODEL_LARGE : builtin_define ( <STR_LIT> ) ; break ; default : break ; } switch ( rs6000_current_abi ) { case ABI_V4 : builtin_define ( <STR_LIT> ) ; break ; case ABI_AIX :


<s> continue ; } if ( TREE_CODE ( b_arg_type ) == INTEGER_TYPE && TREE_CODE ( in_type ) == INTEGER_TYPE ) { match_type ++ ; continue ; } if ( POINTER_TYPE_P ( b_arg_type ) && POINTER_TYPE_P ( in_type ) && ! ( TYPE_QUALS ( TREE_TYPE ( in_type ) ) & ~ TYPE_QUALS ( TREE_TYPE ( b_arg_type ) ) ) && ( TYPE_QUALS ( TREE_TYPE ( b_arg_type ) ) & ~ TYPE_QUALS ( TREE_TYPE ( in_type ) ) ) ) { tree qual_in_type = build_qualified_type ( TREE_TYPE ( in_type ) , TYPE_QUALS ( TREE_TYPE ( b_arg_type ) ) ) ;

if ( lang_hooks . types_compatible_p ( qual_in_type , TREE_TYPE ( b_arg_type ) ) ) {


<s> for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) { Changed |= convertToHardwareLoop ( * I ) ; } if ( Changed ) { return Changed ; } CountValue * TripCount = getTripCount ( L ) ; if ( TripCount == <NUM_LIT> ) { return false ; } if ( containsInvalidInstruction ( L ) ) { return false ; } MachineBasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( Preheader == <NUM_LIT> ) { return false ; } MachineBasicBlock :: iterator InsertPos = Preheader -> getFirstTerminator ( ) ; MachineBasicBlock * LastMBB = L -> getExitingBlock ( ) ; if ( LastMBB == <NUM_LIT> ) { return false ; } MachineBasicBlock :: iterator LastI = LastMBB -> getFirstTerminator ( ) ; MachineBasicBlock * LoopStart = L -> getTopBlock ( ) ; if ( L -> getLoopLatch ( ) != LastMBB ) { LoopStart = L -> getLoopLatch ( ) ; if ( ! LastMBB -> isSuccessor ( LoopStart ) ) { return false ; } } DEBUG ( dbgs ( ) << <STR_LIT> ; L -> dump ( ) ) ; if ( TripCount -> isReg ( ) ) { MachineFunction * MF = LastMBB -> getParent ( ) ; const TargetRegisterClass * RC = MF -> getRegInfo ( ) . getRegClass ( TripCount -> getReg ( ) ) ; unsigned CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CountReg ) . addReg ( TripCount -> getReg ( ) ) ; if ( TripCount -> isNeg ( ) ) { unsigned CountReg1 = CountReg ; CountReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CountReg ) . addReg ( CountReg1 ) ; } BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ; } else { assert ( TripCount -> isImm ( ) && <STR_LIT> ) ; int64_t CountImm = TripCount -> getImm ( ) ; BuildMI ( * Preheader , InsertPos , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( LoopStart ) . addImm ( CountImm ) ; }


<s> void <ISA_LIT>TargetAsmStreamer :: emitCCTopData ( StringRef Name ) { OS << <STR_LIT> ;


<s> if ( NWaves == <NUM_LIT> ) return getLocalMemorySize ( ) ; unsigned WorkGroupSize = getFlatWorkGroupSizes ( F ) . second ;

unsigned WorkGroupsPerCu = getMaxWorkGroupsPerCU ( WorkGroupSize ) ;


<s> DECL_ARTIFICIAL ( space ) = <NUM_LIT> ; DECL_IGNORED_P ( space ) = <NUM_LIT> ; ofs = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , integer_type_node ) ; DECL_FIELD_CONTEXT ( ofs ) = record ; TREE_CHAIN ( ofs ) = space ; base = build_decl ( FIELD_DECL , get_identifier ( <STR_LIT> ) , ptr_type_node ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI ) {

return new <ISA_LIT>Disassembler ( STI , T . createMCRegInfo ( <STR_LIT> ) ) ;


<s> assert ( ! isUnknown ( ) && ! Other . isUnknown ( ) && <STR_LIT> ) ; return getSEWLMULRatio ( ) == Other . getSEWLMULRatio ( ) ;


<s> SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; unsigned StoreAddrReg = ( PtrVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StoreAddr , Offset ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , StoreAddrReg , StoreAddr ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( StoreAddrReg , PtrVT ) ) ;


<s> for ( int i = <NUM_LIT> ; i < RHS_depth ; i ++ ) { RHS_name = RHS_name + <STR_LIT> ; } z3 :: expr condition = implies ( variables . find ( LHS_name ) -> second , variables . find ( RHS_name ) -> second ) ; func_solver . add ( condition ) ; return ;


<s> if ( NewV == nullptr ) continue ; SmallVector < Use * , <NUM_LIT> > Uses ; for ( Use & U : V -> uses ( ) ) Uses . push_back ( & U ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> << * NewV << <STR_LIT> ) ; for ( Use * U : Uses ) { if ( isa < LoadInst > ( U -> getUser ( ) ) || ( isa < StoreInst > ( U -> getUser ( ) ) && U -> getOperandNo ( ) == <NUM_LIT> ) ) { U -> set ( NewV ) ; } else if ( isa < Instruction > ( U -> getUser ( ) ) ) { if ( Instruction * I = dyn_cast < Instruction > ( V ) ) {

BasicBlock :: iterator InsertPos = std :: next ( I -> getIterator ( ) ) ;


<s> if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) Kern [ <STR_LIT> ] = getWorkGroupDimensions ( Node ) ; if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) Kern [ <STR_LIT> ] = getWorkGroupDimensions ( Node ) ; if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) { Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( getTypeName ( cast < ValueAsMetadata > ( Node -> getOperand ( <NUM_LIT> ) ) -> getType ( ) , mdconst :: extract < ConstantInt > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) , true ) ; } if ( Func . hasFnAttribute ( <STR_LIT> ) ) { Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( Func . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . str ( ) , true ) ;


return ( uint32x4_t ) __builtin_neon_vrsqrtev4si ( ( int32x4_t ) __a ) ;


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI , bool RelaxAll ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB , OS , Emitter , STI ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; S -> EmitBundleAlignMode ( MIPS_NACL_BUNDLE_ALIGN ) ;


<s> static bool selectCCOpsAreFMaxCompatible ( SDValue Cmp , SDValue Result ) { if ( Cmp == Result ) return true ; ConstantFPSDNode * CCmp = dyn_cast < ConstantFPSDNode > ( Cmp ) ; ConstantFPSDNode * CResult = dyn_cast < ConstantFPSDNode > ( Result ) ; if ( CCmp && CResult && Cmp . getValueType ( ) == <STR_LIT> && Result . getValueType ( ) == <STR_LIT> ) { bool Lossy ; APFloat CmpVal = CCmp -> getValueAPF ( ) ; CmpVal . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & Lossy ) ; return CResult -> getValueAPF ( ) . bitwiseIsEqual ( CmpVal ) ; }

return Result -> getOpcode ( ) == <STR_LIT> && Result -> getOperand ( <NUM_LIT> ) == Cmp ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) {


<s> const Constant * GV = MO . getGlobal ( ) ; if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) if ( ! GA -> isInterposable ( ) ) GV = GA -> getAliasee ( ) ; if ( const Function * F = dyn_cast < Function > ( GV ) ) { if ( ! F -> doesNotThrow ( ) ) Effects = true ; if ( F -> doesNotAccessMemory ( ) ) return ; if ( F -> onlyReadsMemory ( ) ) { Read = true ; return ; } } } Write = true ; Read = true ;


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) { assert ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) && <STR_LIT> ) ; MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ;

return static_cast < <ISA_LIT>TargetStreamer & > ( TS ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>PeepholeSDWAPass ( ) { return new <ISA_LIT>PeepholeSDWA ( ) ;


<s> return <NUM_LIT> - TFI -> hasFP ( MF ) ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) {


<s> if ( Subtarget . hasV4TOps ( ) ) { if ( TII . isConstExtended ( & MI ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; TII . immediateExtend ( & MI ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { unsigned ResReg = HEXAGON_RESERVED_REG_1 ; if ( ! MFI . hasVarSizedObjects ( ) && TII . isValidOffset ( MI . getOpcode ( ) , ( FrameSize + Offset ) ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( getStackRegister ( ) , false , false , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( FrameSize + Offset ) ; } else if ( ! TII . isValidOffset ( <STR_LIT> , Offset ) ) { BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addImm ( Offset ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addReg ( FrameReg ) . addReg ( ResReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ResReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else { BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , ResReg ) . addReg ( FrameReg ) . addImm ( Offset ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ResReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } } } else { unsigned dstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , dstReg ) . addImm ( Offset ) ; BuildMI ( * MI . getParent ( ) , II , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , dstReg ) . addReg ( FrameReg ) . addReg ( dstReg ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( dstReg , false , false , true ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } } else { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } }


<s> ~ <ISA_LIT>HazardRecognizer ( ) override {


<s> FunctionPass * llvm :: create<ISA_LIT>PreAMXConfigPass ( ) {

return new <ISA_LIT>PreAMXConfigPass ( ) ;


<s> NumEntries = array_lengthof ( Offsets ) ; return Offsets ; } bool assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const override ; bool needsAligna ( const MachineFunction & MF ) const ; const MachineInstr * getAlignaInstr ( const MachineFunction & MF ) const ; void insertCFIInstructions ( MachineFunction & MF ) const ; private : typedef std :: vector < CalleeSavedInfo > CSIVect ; void expandAlloca ( MachineInstr * AI , const <ISA_LIT>InstrInfo & TII , unsigned SP , unsigned CF ) const ; void insertPrologueInBlock ( MachineBasicBlock & MBB , bool PrologueStubs ) const ; void insertEpilogueInBlock ( MachineBasicBlock & MBB ) const ; void insertAllocframe ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertPt , unsigned NumBytes ) const ; bool insertCSRSpillsInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const <ISA_LIT>RegisterInfo & HRI , bool & PrologueStubs ) const ; bool insertCSRRestoresInBlock ( MachineBasicBlock & MBB , const CSIVect & CSI , const <ISA_LIT>RegisterInfo & HRI ) const ; void updateEntryPaths ( MachineFunction & MF , MachineBasicBlock & SaveB ) const ; bool updateExitPaths ( MachineBasicBlock & MBB , MachineBasicBlock & RestoreB , BitVector & DoneT , BitVector & DoneF , BitVector & Path ) const ; void insertCFIInstructionsAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator At ) const ; void adjustForCalleeSavedRegsSpillCall ( MachineFunction & MF ) const ;

bool expandCopy ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const ;


<s> if ( hasFiniArray ( ) ) stronglyReference ( <STR_LIT> , <STR_LIT> <STR_LIT> ) ; for ( const auto & TableEntry : Context . getSymbols ( ) ) { if ( TableEntry . getKey ( ) != <STR_LIT> && TableEntry . getKey ( ) != <STR_LIT> ) continue ; stronglyReference ( <STR_LIT> , <STR_LIT> <STR_LIT> ) ;


<s> FrameIdx = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getCRSpillFrameIndex ( ) ; return true ;


<s> static bool CC_<ISA_LIT>O32_FP32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { static const MCPhysReg F64Regs [ ] = { <STR_LIT> , <STR_LIT> } ; return CC_<ISA_LIT>O32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , F64Regs ) ;


<s> return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ;

Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> doFMAF32AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF32 ( ) && ( FMAContractLevel == <NUM_LIT> ) ; doFMAF64AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF64 ( ) && ( FMAContractLevel == <NUM_LIT> ) ; allowFMA = ( FMAContractLevel >= <NUM_LIT> ) || UseFMADInstruction ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState ArgCCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; ArgCCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>32 ) ; unsigned NumBytes = ArgCCInfo . getNextStackOffset ( ) ; for ( auto & Arg : Outs ) { if ( ! Arg . Flags . isByVal ( ) ) continue ; report_fatal_error ( <STR_LIT> ) ; } Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , CLI . DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SDValue StackPtr ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; SDValue ArgValue = OutVals [ I ] ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ArgValue ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; report_fatal_error ( <STR_LIT> ) ; } } SDValue Glue ; for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; } if ( isa < GlobalAddressSDNode > ( Callee ) ) { Callee = lowerGlobalAddress ( Callee , DAG ) ; } else if ( isa < ExternalSymbolSDNode > ( Callee ) ) { Callee = lowerExternalSymbol ( Callee , DAG ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto & Reg : RegsToPass ) Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , CallConv ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; if ( Glue . getNode ( ) ) Ops . push_back ( Glue ) ;

SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;


<s> static DecodeStatus DecodeGPRSeqPairsClassRegisterClass ( MCInst & Inst , unsigned RegClassID , unsigned RegNo , uint64_t Addr , const MCDisassembler * Decoder ) { if ( RegNo & <NUM_LIT> ) return Fail ;

unsigned Reg = <ISA_LIT>MCRegisterClasses [ RegClassID ] . getRegister ( RegNo / <NUM_LIT> ) ;


<s> void <ISA_LIT>RegisterInfo :: lowerVRSAVESpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> HOST_WIDE_INT base = offset & ~ ( GET_MODE_SIZE ( mode ) < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ;

if ( mode == TImode || mode == TFmode || ( offset & ( GET_MODE_SIZE ( mode ) - <NUM_LIT> ) ) != <NUM_LIT> ) base = ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ;


<s> void asm_output_name ( FILE * file , const char * name ) { ASM_OUTPUT_LABEL ( asm_out_file , name ) ;


<s> rtx src = op [ <NUM_LIT> ] ; if ( avr_mem_flash_p ( src ) || avr_mem_flash_p ( dest ) ) { return avr_out_lpm ( insn , op , plen ) ; } if ( register_operand ( dest , VOIDmode ) ) { if ( register_operand ( src , VOIDmode ) ) { if ( true_regnum ( dest ) > true_regnum ( src ) ) { avr_asm_len ( <STR_LIT> , op , plen , - <NUM_LIT> ) ; if ( AVR_HAVE_MOVW ) return avr_asm_len ( <STR_LIT> , op , plen , <NUM_LIT> ) ; else return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , op , plen , <NUM_LIT> ) ; } else { if ( AVR_HAVE_MOVW ) avr_asm_len ( <STR_LIT> , op , plen , - <NUM_LIT> ) ; else avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; return avr_asm_len ( <STR_LIT> , op , plen , <NUM_LIT> ) ; } } else if ( CONSTANT_P ( src ) ) { return avr_out_reload_inpsi ( op , NULL_RTX , plen ) ; } else if ( MEM_P ( src ) ) return avr_out_load_psi ( insn , op , plen ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: CommonLinkage : llvm_unreachable ( <STR_LIT> ) ; } assert ( LinkageAttr != MCSA_Invalid && <STR_LIT> ) ; MCSymbolAttr VisibilityAttr = MCSA_Invalid ; if ( ! TM . getIgnoreXCOFFVisibility ( ) ) { switch ( GV -> getVisibility ( ) ) { case GlobalValue :: DefaultVisibility : break ; case GlobalValue :: HiddenVisibility : VisibilityAttr = MAI -> getHiddenVisibilityAttr ( ) ; break ; case GlobalValue :: ProtectedVisibility : VisibilityAttr = MAI -> getProtectedVisibilityAttr ( ) ; break ; } } OutStreamer -> emitXCOFFSymbolLinkageWithVisibility ( GVSym , LinkageAttr , VisibilityAttr ) ;


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend64 < N > ( Imm ) ) ) ;


<s> return ( * cast < msgpack :: MapNode > ( HSAMetadataRoot . get ( ) ) ) [ Key ] ;


<s> <ISA_LIT>Disassembler :: <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) {


<s> last != NULL && ! NOTE_INSN_BASIC_BLOCK_P ( last ) && ! stops_p [ INSN_UID ( last ) ] ; last = PREV_INSN ( last ) ) if ( INSN_P ( last ) && recog_memoized ( last ) >= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ;


<s> static void vms_asm_out_destructor ( rtx symbol , int priority ATTRIBUTE_UNUSED ) {


<s> assert ( <ISA_LIT>MCInstrInfo :: isBundle ( HMB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; * Addend = <NUM_LIT> ; * Extended = false ; * CurrentBundle = & MI ; * CurrentIndex = <NUM_LIT> ; size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;

EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Last , HMB , HMI ) ) ;


<s> inline static const char * AddrModeToString ( AddrMode addrmode ) { switch ( addrmode ) { case AddrModeNone : return <STR_LIT> ; case AddrMode1 : return <STR_LIT> ; case AddrMode2 : return <STR_LIT> ; case AddrMode3 : return <STR_LIT> ; case AddrMode4 : return <STR_LIT> ; case AddrMode5 : return <STR_LIT> ; case AddrMode6 : return <STR_LIT> ; case AddrModeT1_1 : return <STR_LIT> ; case AddrModeT1_2 : return <STR_LIT> ; case AddrModeT1_4 : return <STR_LIT> ; case AddrModeT1_s : return <STR_LIT> ; case AddrModeT2_i12 : return <STR_LIT> ; case AddrModeT2_i8 : return <STR_LIT> ; case AddrModeT2_so : return <STR_LIT> ; case AddrModeT2_pc : return <STR_LIT> ; case AddrModeT2_i8s4 : return <STR_LIT> ; case AddrMode_i12 : return <STR_LIT> ;


<s> bool isu1_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false ) ;


<s> void <ISA_LIT>PassConfig :: addOptimizedRegAlloc ( ) {

insertPass ( & llvm :: TwoAddressInstructionPassID , & llvm :: RegisterCoalescerID ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCTPOP ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue InpVal = Op . getOperand ( <NUM_LIT> ) ;

if ( isa < ConstantSDNode > ( InpVal ) ) {


<s> return new <ISA_LIT>16TargetLowering ( TM , STI ) ;


<s> BuildMI ( MBB , I , DL , TII -> get ( XorOp ) , DstReg ) . addReg ( ExecReg ) . addImm ( - <NUM_LIT> ) ; } return ; } unsigned PrevMaskedReg = <NUM_LIT> ; unsigned CurMaskedReg = <NUM_LIT> ; if ( ! PrevConstant ) { if ( CurConstant && CurVal ) { PrevMaskedReg = PrevReg ; } else { PrevMaskedReg = createLaneMaskReg ( * MF ) ; BuildMI ( MBB , I , DL , TII -> get ( AndN2Op ) , PrevMaskedReg ) . addReg ( PrevReg ) . addReg ( ExecReg ) ; } } if ( ! CurConstant ) { if ( PrevConstant && PrevVal ) { CurMaskedReg = CurReg ; } else { CurMaskedReg = createLaneMaskReg ( * MF ) ; BuildMI ( MBB , I , DL , TII -> get ( AndOp ) , CurMaskedReg ) . addReg ( CurReg ) . addReg ( ExecReg ) ; } } if ( PrevConstant && ! PrevVal ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( CurMaskedReg ) ; } else if ( CurConstant && ! CurVal ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( PrevMaskedReg ) ; } else if ( PrevConstant && PrevVal ) { BuildMI ( MBB , I , DL , TII -> get ( OrN2Op ) , DstReg ) . addReg ( CurMaskedReg ) . addReg ( ExecReg ) ;


<s> Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; return DAG . getBitcast ( DstVT , Res ) ; } if ( SrcVT . is512BitVector ( ) && Subtarget . hasInt256 ( ) ) { Lo = DAG . getBitcast ( <STR_LIT> , Lo ) ; Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; Res = DAG . getBitcast ( <STR_LIT> , Res ) ; Res = DAG . getVectorShuffle ( <STR_LIT> , DL , Res , Res , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( DstVT . is256BitVector ( ) ) return DAG . getBitcast ( DstVT , Res ) ; EVT PackedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PackedSVT , NumElems ) ; Res = DAG . getBitcast ( PackedVT , Res ) ; return truncateVectorCompareWithPACKSS ( DstVT , Res , DL , DAG , Subtarget ) ; } assert ( SrcVT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ;

EVT PackedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PackedSVT , NumElems / <NUM_LIT> ) ;


<s> rtx op0 , op1 , target ; mips_emit_compare ( & code , & op0 , & op1 , TARGET_MIPS16 ) ;

target = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) , gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) , pc_rtx ) ;


<s> const MachineOperand * Src2Mods = getNamedOperand ( * MI , AMDGPU :: OpName :: src2_modifiers ) ; if ( ( Src0Mods && Src0Mods -> getImm ( ) ) || ( Src1Mods && Src1Mods -> getImm ( ) ) || ( Src2Mods && Src2Mods -> getImm ( ) ) ) return nullptr ; unsigned Reg = MI -> getOperand ( Src0Idx ) . getReg ( ) ; unsigned SubReg = MI -> getOperand ( Src0Idx ) . getSubReg ( ) ; MI -> getOperand ( Src0Idx ) . ChangeToImmediate ( MI -> getOperand ( Src1Idx ) . getImm ( ) ) ; MI -> getOperand ( Src1Idx ) . ChangeToRegister ( Reg , false ) ; MI -> getOperand ( Src1Idx ) . setSubReg ( SubReg ) ; } else { MI = TargetInstrInfo :: commuteInstruction ( MI , NewMI ) ;


<s> } } if ( cfun -> machine -> funtype && ( TREE_CODE ( cfun -> machine -> funtype ) == FUNCTION_TYPE || TREE_CODE ( cfun -> machine -> funtype ) == METHOD_TYPE ) && stdarg_p ( cfun -> machine -> funtype ) ) { has_varargs = true ; cfun -> machine -> has_call_with_varargs = true ; } vec = rtvec_alloc ( nargs + <NUM_LIT> + ( has_varargs ? <NUM_LIT> : <NUM_LIT> ) ) ; pat = gen_rtx_PARALLEL ( VOIDmode , vec ) ; if ( has_varargs ) { rtx this_arg = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_move_insn ( this_arg , stack_pointer_rtx ) ; else emit_move_insn ( this_arg , stack_pointer_rtx ) ; XVECEXP ( pat , <NUM_LIT> , nargs + <NUM_LIT> ) = gen_rtx_USE ( VOIDmode , this_arg ) ; } int i ; rtx arg ; for ( i = <NUM_LIT> , arg = cfun -> machine -> call_args ; arg ; arg = XEXP ( arg , <NUM_LIT> ) , i ++ ) { rtx this_arg = XEXP ( arg , <NUM_LIT> ) ; XVECEXP ( pat , <NUM_LIT> , i ) = gen_rtx_USE ( VOIDmode , this_arg ) ; } rtx tmp_retval = retval ; t = gen_rtx_CALL ( VOIDmode , address , const0_rtx ) ; if ( retval != NULL_RTX ) { if ( ! nvptx_register_operand ( retval , GET_MODE ( retval ) ) ) tmp_retval = gen_reg_rtx ( GET_MODE ( retval ) ) ; t = gen_rtx_SET ( VOIDmode , tmp_retval , t ) ; } XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) = t ; if ( ! REG_P ( callee ) && ( decl_type == NULL_TREE || ( external_decl && TYPE_ARG_TYPES ( decl_type ) == NULL_TREE ) ) ) { rtx * slot = declared_libfuncs_htab -> find_slot ( callee , INSERT ) ; if ( * slot == NULL ) { * slot = callee ;

write_func_decl_from_insn ( func_decls , retval , pat , callee ) ;


<s> InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isTargetNaCl ( ) ) { StaticCtorSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_INIT_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_FINI_ARRAY , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseAccessReg ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Percent ) ) return MatchOperand_NoMatch ; Register Reg ; if ( parseRegister ( Reg , RegAccess , nullptr ) ) return MatchOperand_ParseFail ;

Operands . push_back ( <ISA_LIT>Operand :: createAccessReg ( Reg . Num , Reg . StartLoc , Reg . EndLoc ) ) ;


<s> bool sawStore = false ; if ( slot == MBB . begin ( ) ) return MBB . end ( ) ; if ( slot -> getOpcode ( ) == <STR_LIT> || slot -> getOpcode ( ) == <STR_LIT> ) return MBB . end ( ) ; if ( slot -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator J = slot ; -- J ; if ( J -> getOpcode ( ) == <STR_LIT> || J -> getOpcode ( ) == <STR_LIT> ) { slot -> setDesc ( TM . getInstrInfo ( ) -> get ( <STR_LIT> ) ) ; return J ; } } if ( slot -> isCall ( ) ) insertCallDefsUses ( slot , RegDefs , RegUses ) ; else insertDefsUses ( slot , RegDefs , RegUses ) ; bool done = false ; MachineBasicBlock :: iterator I = slot ; while ( ! done ) { done = ( I == MBB . begin ( ) ) ; if ( ! done ) -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isPosition ( ) || I -> hasDelaySlot ( ) || I -> isBundledWithSucc ( ) ) break ; if ( delayHasHazard ( I , sawLoad , sawStore , RegDefs , RegUses ) ) { insertDefsUses ( I , RegDefs , RegUses ) ;


<s> break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; if ( TRI -> isVGPR ( MBB . getParent ( ) -> getRegInfo ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Opcode = <STR_LIT> ( Opcode ) ; BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else { BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addImm ( <NUM_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; } break ; } case <STR_LIT> : { const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; int64_t KillVal = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( KillVal == <NUM_LIT> || KillVal == - <NUM_LIT> ) ; if ( Op . isImm ( ) ) { int64_t Imm = Op . getImm ( ) ; assert ( Imm == <NUM_LIT> || Imm == - <NUM_LIT> ) ; if ( Imm == KillVal ) BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; break ; } unsigned Opcode = KillVal ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( Op ) ; break ; } default :


<s> SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . createTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: createAdd ( Base , Expr , Ctx ) ; } const MCExpr * Sym = nullptr ; if ( AllowTLS && getLexer ( ) . is ( AsmToken :: Colon ) ) { Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; StringRef Name = Parser . getTok ( ) . getString ( ) ; if ( Name == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_TLSGD ; else if ( Name == <STR_LIT> ) Kind = MCSymbolRefExpr :: VK_TLSLDM ; else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } StringRef Identifier = Parser . getTok ( ) . getString ( ) ; Sym = MCSymbolRefExpr :: create ( Ctx . getOrCreateSymbol ( Identifier ) , Kind , Ctx ) ; Parser . Lex ( ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;

if ( AllowTLS ) Operands . push_back ( <ISA_LIT>Operand :: createImmTLS ( Expr , Sym , StartLoc , EndLoc ) ) ;


<s> if ( Op . getValueType ( ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) return LowerFP64_TO_INT ( Op , DAG , true ) ; return SDValue ( ) ;


<s> if ( ! ImmInRange ( MI , Entry ) ) return false ;

if ( ! isMMSourceRegister ( MI -> getOperand ( <NUM_LIT> ) ) || ! isMMThreeBitGPRegister ( MI -> getOperand ( <NUM_LIT> ) ) ) return false ;


<s> CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask1 = DAG . getLoad ( SrcVT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , SrcVT , Op1 , Mask1 ) ; if ( SrcVT . bitsGT ( VT ) ) { SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit ) ; SignBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SignBit , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } CV . clear ( ) ; if ( VT == <STR_LIT> ) { CV . push_back ( ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , ~ ( <NUM_LIT> << <NUM_LIT> ) ) ) ) ) ;


<s> MCInst TmpInst = MI ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LowerLargeShift ( TmpInst ) ; break ; case <STR_LIT> : case <STR_LIT> : LowerDextDins ( TmpInst ) ; } uint32_t Binary = getBinaryCodeForInstr ( TmpInst , Fixups ) ; unsigned Opcode = TmpInst . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; if ( STI . getFeatureBits ( ) & <STR_LIT> ) { int NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups ) ; } } const MCInstrDesc & Desc = MCII . get ( TmpInst . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; if ( ! Size ) llvm_unreachable ( <STR_LIT> ) ;

EmitInstruction ( Binary , Size , OS ) ;


<s> case E_SImode : case E_DImode : case E_TImode : return true ; case E_SFmode : case E_DFmode : return true ; case E_TFmode : return TARGET_HAS_XFLOATING_LIBS ; default : return false ; }


<s> void <ISA_LIT>ScoreboardHazardRecognizer :: EmitInstruction ( SUnit * SU ) { const MCInstrDesc * MCID = DAG -> getInstrDesc ( SU ) ; if ( ! MCID ) return ;

ScoreboardHazardRecognizer :: EmitInstruction ( SU ) ;


<s> case AsmToken :: Error : SetError ( Lexer -> getErrLoc ( ) , Lexer -> getErr ( ) ) ; return lexedToken ; case AsmToken :: Identifier : { unsigned regID = MatchRegisterName ( lexedToken . getString ( ) . lower ( ) ) ; if ( regID ) return AsmToken ( AsmToken :: Register , lexedToken . getString ( ) , static_cast < int64_t > ( regID ) ) ; return lexedToken ;


<s> std :: pair < Value * , Value * > <ISA_LIT>LowerAMXType :: getShape ( IntrinsicInst * II , unsigned OpNo ) { Value * Row = nullptr , * Col = nullptr ; switch ( II -> getIntrinsicID ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : {

Row = II -> getArgOperand ( <NUM_LIT> ) ;


<s> const Function & Fn = MF . getFunction ( ) ; const bool IsWin64CC = STI . isCallingConvWin64 ( Fn . getCallingConv ( ) ) ;

return Is64Bit && ! IsWin64CC && ! Fn . hasFnAttribute ( Attribute :: NoRedZone ) ;


<s> O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm ( ) * <NUM_LIT> ;


<s> InstructionSelector * llvm :: create<ISA_LIT>InstructionSelector ( <ISA_LIT>Subtarget & Subtarget , <ISA_LIT>RegisterBankInfo & RBI ) { return new <ISA_LIT>InstructionSelector ( Subtarget , RBI ) ;


<s> <ISA_LIT>IntrinsicElimination ( ) : FunctionPass ( ID ) {


<s> SmallVector < SDValue , <NUM_LIT> > OpInputs ; if ( ! resolveTargetShuffleInputs ( Op , OpInputs , OpMask , TLO . DAG ) ) return false ; if ( llvm :: any_of ( OpInputs , [ VT ] ( SDValue V ) { return VT != V . getValueType ( ) ; } ) ) return false ; int NumSrcs = OpInputs . size ( ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) if ( ! DemandedElts [ i ] ) OpMask [ i ] = SM_SentinelUndef ; if ( isUndefInRange ( OpMask , <NUM_LIT> , NumElts ) ) { KnownUndef . setAllBits ( ) ; return TLO . CombineTo ( Op , TLO . DAG . getUNDEF ( VT ) ) ; } if ( isUndefOrZeroInRange ( OpMask , <NUM_LIT> , NumElts ) ) { KnownZero . setAllBits ( ) ; return TLO . CombineTo ( Op , getZeroVector ( VT . getSimpleVT ( ) , Subtarget , TLO . DAG , SDLoc ( Op ) ) ) ; } for ( int Src = <NUM_LIT> ; Src != NumSrcs ; ++ Src ) if ( isSequentialOrUndefInRange ( OpMask , <NUM_LIT> , NumElts , Src * NumElts ) ) return TLO . CombineTo ( Op , OpInputs [ Src ] ) ; for ( int Src = <NUM_LIT> ; Src != NumSrcs ; ++ Src ) { int Lo = Src * NumElts ; APInt SrcElts = APInt :: getNullValue ( NumElts ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) if ( DemandedElts [ i ] ) { int M = OpMask [ i ] - Lo ; if ( <NUM_LIT> <= M && M < NumElts ) SrcElts . setBit ( M ) ; } APInt SrcUndef , SrcZero ; if ( SimplifyDemandedVectorElts ( OpInputs [ Src ] , SrcElts , SrcUndef , SrcZero , TLO , Depth + <NUM_LIT> ) ) return true ; } for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( OpMask [ i ] == SM_SentinelUndef ) KnownUndef . setBit ( i ) ; if ( OpMask [ i ] == SM_SentinelZero ) KnownZero . setBit ( i ) ; } return false ;


<s> SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewOp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewWOp = DAG . getNode ( N -> getOpcode ( ) , DL , <STR_LIT> , NewOp0 , NewOp1 ) ; SDValue NewRes = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewWOp , DAG . getValueType ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewRes ) ;


<s> KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: urem ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 ; Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; Known = KnownBits :: udiv ( Known . trunc ( <NUM_LIT> ) , Known2 . trunc ( <NUM_LIT> ) ) ; Known = Known . sext ( BitWidth ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleTZ = Known2 . trunc ( <NUM_LIT> ) . countMaxTrailingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleTZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : { KnownBits Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned PossibleLZ = Known2 . trunc ( <NUM_LIT> ) . countMaxLeadingZeros ( ) ; unsigned LowBits = Log2_32 ( PossibleLZ ) + <NUM_LIT> ; Known . Zero . setBitsFrom ( LowBits ) ; break ; } case <STR_LIT> : Known . Zero . setLowBits ( <NUM_LIT> ) ; break ; case <STR_LIT> : { unsigned IntNo = Op . getConstantOperandVal ( <NUM_LIT> ) ; switch ( IntNo ) {


<s> Ordered [ <NUM_LIT> ] = ExpInstrTypesSeen == <NUM_LIT> ; Ordered [ <NUM_LIT> ] = false ; Counters Counts = WaitCounts ; bool NeedWait = false ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Required . Array [ i ] <= WaitedOn . Array [ i ] ) continue ; NeedWait = true ; if ( Ordered [ i ] ) { unsigned Value = LastIssued . Array [ i ] - Required . Array [ i ] ; Counts . Array [ i ] = std :: min ( Value , WaitCounts . Array [ i ] ) ; } else Counts . Array [ i ] = <NUM_LIT> ; WaitedOn . Array [ i ] = LastIssued . Array [ i ] - Counts . Array [ i ] ; } if ( ! NeedWait ) return false ; if ( Counts . Named . EXP == <NUM_LIT> ) ExpInstrTypesSeen = <NUM_LIT> ; BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ( Counts . Named . VM & <NUM_LIT> ) | ( ( Counts . Named . EXP & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Counts . Named . LGKM & <NUM_LIT> ) << <NUM_LIT> ) ) ;


<s> DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( DefMI ) TruncSize = <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( ! DefMI ) continue ; int64_t imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; else if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; } if ( TruncSize == - <NUM_LIT> ) continue ; if ( DefMI -> isPHI ( ) ) { bool CheckFail = false ; for ( unsigned i = <NUM_LIT> , e = DefMI -> getNumOperands ( ) ; i < e ; i += <NUM_LIT> ) { MachineOperand & opnd = DefMI -> getOperand ( i ) ; if ( ! opnd . isReg ( ) ) { CheckFail = true ; break ; } MachineInstr * PhiDef = MRI -> getVRegDef ( opnd . getReg ( ) ) ; if ( ! PhiDef || PhiDef -> isPHI ( ) || ! TruncSizeCompatible ( TruncSize , PhiDef -> getOpcode ( ) ) ) { CheckFail = true ; break ;