<s> case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; assert ( NumVecs == <NUM_LIT> && <STR_LIT> ) ; break ; } EVT ResTy ; if ( NumVecs == <NUM_LIT> ) ResTy = VT ; else { unsigned ResTyElts = ( NumVecs == <NUM_LIT> ) ? <NUM_LIT> : NumVecs ; if ( ! is64BitVector ) ResTyElts *= <NUM_LIT> ; ResTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , ResTyElts ) ; } std :: vector < EVT > ResTys ; ResTys . push_back ( ResTy ) ; if ( isUpdating ) ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDValue Pred = getAL ( CurDAG , dl ) ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; bool IsImmUpdate = isPerfectIncrement ( Inc , VT , NumVecs ) ; if ( ( NumVecs <= <NUM_LIT> ) && ! IsImmUpdate ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && ! isVLDfixed ( Opc ) ) || ! IsImmUpdate ) Ops . push_back ( IsImmUpdate ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ;

assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ;


<s> bool TargetOperandInfo :: isPreserving ( const MachineInstr & In , unsigned OpNum ) const { return TII . isPredicated ( In ) ;


<s> MOVToLEAPass ( ) : MachineFunctionPass ( ID ) {


<s> <ISA_LIT>BSel ( ) : MachineFunctionPass ( & ID ) {


<s> if ( ! EnableBasePointer ) return false ; if ( needsStackRealignment ( MF ) && ( MFI -> hasVarSizedObjects ( ) || ! TFI -> hasReservedCallFrame ( MF ) ) ) return true ; if ( AFI -> isThumbFunction ( ) && MFI -> hasVarSizedObjects ( ) ) { if ( AFI -> isThumb2Function ( ) && MFI -> getLocalFrameSize ( ) < <NUM_LIT> ) return false ; return true ; } return false ;


<s> bool AMDGPUPeepholeOpt :: doFinalization ( Module & M ) { return false ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_OPENRISC , true ) {


<s> const MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; Register Base = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & CDef = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & VDef = MI -> getOperand ( <NUM_LIT> ) ; int64_t OffsetImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( <NUM_LIT> <= OffsetImm && OffsetImm < <NUM_LIT> ) ; auto Offset = static_cast < uint16_t > ( OffsetImm ) ; Offset &= <NUM_LIT> ; Register Src = TRI . getSubReg ( Base , <STR_LIT> ) ;

auto LDC = Builder . buildInstr ( <STR_LIT> ) . add ( CDef ) . addImm ( <NUM_LIT> ) ;


<s> if ( name [ i ] == '6' && name [ i + <NUM_LIT> ] == '4' ) return true ;


<s> } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; } else { R1 = Addr ; R2 = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; } return true ;


<s> static bool CC_<ISA_LIT> ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { if ( ArgFlags . isByVal ( ) ) { assert ( ( ArgFlags . getByValSize ( ) > <NUM_LIT> ) && <STR_LIT> ) ; unsigned Offset = State . AllocateStack ( ArgFlags . getByValSize ( ) , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ;


<s> case VK_<ISA_LIT>_TLS_IE_LO10 : case VK_<ISA_LIT>_TLS_IE_LD : case VK_<ISA_LIT>_TLS_IE_LDX : case VK_<ISA_LIT>_TLS_IE_ADD : case VK_<ISA_LIT>_TLS_LE_HIX22 : case VK_<ISA_LIT>_TLS_LE_LOX10 : break ; } fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

addNEONi8ReplicateOperands ( Inst , true ) ;


<s> int RoundMode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( RoundMode == ( int ) RoundingMode :: TowardPositive ) Opc = <STR_LIT> ; else if ( RoundMode == ( int ) RoundingMode :: TowardNegative ) Opc = <STR_LIT> ; else return false ; B . buildInstr ( Opc ) . addDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent ( ) ; return true ;


<s> } else { assert ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; ImmOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) ImmOffset <<= <NUM_LIT> ; RegOffset = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( isUInt < <NUM_LIT> > ( ImmOffset ) ) { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( ImmOffset ) ; ImmOffset = <NUM_LIT> ; } } unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord0 = RegOffset ; unsigned DWord1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint64_t RsrcDataFormat = getDefaultRsrcDataFormat ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord2 ) . addImm ( RsrcDataFormat & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord3 ) . addImm ( RsrcDataFormat >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , SRsrc ) . addReg ( DWord0 ) . addImm ( <STR_LIT> ) . addReg ( DWord1 ) . addImm ( <STR_LIT> ) . addReg ( DWord2 ) . addImm ( <STR_LIT> ) . addReg ( DWord3 ) . addImm ( <STR_LIT> ) ; MI -> setDesc ( get ( NewOpcode ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( SRsrc ) ; } else { MI -> getOperand ( <NUM_LIT> ) . ChangeToRegister ( SRsrc , false ) ; } MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( ImmOffset ) ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> } if ( Opc == <NUM_LIT> ) return false ; SDValue Ops [ ] = { A , B , Acc , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ; CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } else if ( N -> getOpcode ( ) == <STR_LIT> && SearchSignedMulLong ( SDValue ( N , <NUM_LIT> ) , & Opc , A , B , false ) ) { if ( Opc == <NUM_LIT> ) return false ;

SDValue Ops [ ] = { A , B , getAL ( CurDAG , dl ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) } ;


<s> if ( RVVVectorBitsMax < ( int ) ZvlLen ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= RVVVectorBitsMin && <STR_LIT> <STR_LIT> ) ;

unsigned Max = std :: max ( RVVVectorBitsMin , RVVVectorBitsMax ) ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( create<ISA_LIT>AbstractMemberAccess ( & get<ISA_LIT>TargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( ) ;


<s> } else if ( ST -> hasQPX ( ) && Val -> getScalarType ( ) -> isFloatingPointTy ( ) ) { if ( Index == <NUM_LIT> ) return <NUM_LIT> ; return Cost ; } unsigned LHSPenalty = <NUM_LIT> ; if ( ISD == <STR_LIT> ) LHSPenalty += <NUM_LIT> ; if ( ISD == <STR_LIT> || ISD == <STR_LIT> ) return LHSPenalty + Cost ; return Cost ;


<s> bool <ISA_LIT>ExpandPseudo :: expandLoadLocalAddress ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { return expandAuipcInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , <STR_LIT> ) ;


<s> ArgDescriptor ( unsigned Val = <NUM_LIT> , unsigned Mask = ~ <NUM_LIT> , bool IsStack = false , bool IsSet = false ) : Reg ( Val ) , Mask ( Mask ) , IsStack ( IsStack ) , IsSet ( IsSet ) {


<s> CopyPropagation ( DataFlowGraph & dfg ) : MDT ( dfg . getDT ( ) ) , DFG ( dfg ) , L ( dfg . getMF ( ) . getRegInfo ( ) , dfg ) , Trace ( false ) {


<s> static bool aarch64_rtx_costs_wrapper ( rtx x , machine_mode mode , int outer , int param , int * cost , bool speed ) { bool result = aarch64_rtx_costs ( x , mode , outer , param , cost , speed ) ;

if ( dump_file && ( dump_flags & TDF_DETAILS ) ) {


<s> unsigned <ISA_LIT>TargetLowering :: getFunctionAlignment ( const Function * ) const { return <NUM_LIT> ;


<s> if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isAllOnes ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isAllOnes ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ;


<s> if ( ! Op . isReg ( ) || ! Op . readsReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; assert ( ! Op . getSubReg ( ) && <STR_LIT> ) ; for ( MCRegUnitIterator Units ( Reg , TRI ) ; Units . isValid ( ) ; ++ Units ) UsedRegUnits . set ( * Units ) ; }


<s> void <ISA_LIT>InstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & DestBB , MachineBasicBlock & RestoreBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { assert ( RS && <STR_LIT> ) ; assert ( MBB . empty ( ) && <STR_LIT> ) ; assert ( MBB . pred_size ( ) == <NUM_LIT> ) ; MachineFunction * MF = MBB . getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( ! isInt < <NUM_LIT> > ( BrOffset ) ) report_fatal_error ( <STR_LIT> ) ;

Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> void llvm :: addPredicatedMveVpredNOp ( MachineInstrBuilder & MIB , unsigned Cond ) {


<s> SDNode * Load = CurDAG -> getMachineNode ( Opc , DL , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , DL , VT , SuperReg ) ) ; unsigned ChainIdx = NumVecs ; ReplaceUses ( SDValue ( N , ChainIdx ) , SDValue ( Load , <NUM_LIT> ) ) ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> return BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( foldImm ( I . getOperand ( <NUM_LIT> ) , MRI ) ) . constrainAllUses ( TII , TRI , RBI ) ;


<s> Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } if ( ! <STR_LIT> ( Imm , RegSize ) ) return <NUM_LIT> ; unsigned ResultReg = fastEmitInst_ri ( Opc , RC , LHSReg , <STR_LIT> ( Imm , RegSize ) ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> && ISDOpc != <STR_LIT> ) { uint64_t Mask = ( RetVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , Mask ) ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallVector < std :: pair < MachineOperand * , <STR_LIT> > , <NUM_LIT> > OperandsToUpdate ; bool isSafe = false ; I = CmpInstr ; E = CmpInstr -> getParent ( ) -> end ( ) ; while ( ! isSafe && ++ I != E ) { const MachineInstr & Instr = * I ; for ( unsigned IO = <NUM_LIT> , EO = Instr . getNumOperands ( ) ; ! isSafe && IO != EO ; ++ IO ) { const MachineOperand & MO = Instr . getOperand ( IO ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { isSafe = true ; break ; } if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { isSafe = true ; break ; } <STR_LIT> CC = ( <STR_LIT> ) Instr . getOperand ( IO - <NUM_LIT> ) . getImm ( ) ; if ( Sub ) { <STR_LIT> NewCC = getSwappedCondition ( CC ) ; if ( NewCC == <STR_LIT> ) return false ; if ( SrcReg2 != <NUM_LIT> && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 && Sub -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg ) OperandsToUpdate . push_back ( std :: make_pair ( & ( ( * I ) . getOperand ( IO - <NUM_LIT> ) ) , NewCC ) ) ; } else switch ( CC ) { default : isSafe = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } } }


<s> if ( SDNode :: hasPredecessorHelper ( N , Visited , Worklist ) || SDNode :: hasPredecessorHelper ( User , Visited , Worklist ) ) return false ; return true ;


<s> bool <ISA_LIT>16TargetLowering :: isEligibleForTailCallOptimization ( const CCState & CCInfo , unsigned NextStackOffset , const <ISA_LIT>FunctionInfo & FI ) const { return false ;


<s> ImmBranch ( MachineInstr * mi , unsigned maxdisp , bool cond , int ubr ) : MI ( mi ) , MaxDisp ( maxdisp ) , isCond ( cond ) , UncondBr ( ubr ) {


<s> else if ( DATA_REG_P ( operands [ <NUM_LIT> ] ) && INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) >= - <NUM_LIT> ) return <STR_LIT> ; else if ( INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> && INTVAL ( operands [ <NUM_LIT> ] ) >= - <NUM_LIT> ) return <STR_LIT> ;


<s> MachineIRBuilder & B = Helper . MIRBuilder ; MachineRegisterInfo & MRI = * B . getMRI ( ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_ADDRSPACE_CAST : return legalizeAddrSpaceCast ( MI , MRI , B ) ; case TargetOpcode :: G_FRINT : return legalizeFrint ( MI , MRI , B ) ; case TargetOpcode :: G_FCEIL : return legalizeFceil ( MI , MRI , B ) ; case TargetOpcode :: G_FREM : return legalizeFrem ( MI , MRI , B ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C_TRUNC : return legalizeIntrinsicTrunc ( MI , MRI , B ) ; case TargetOpcode :: G_<ISA_LIT>TOFP : return legalizeITOFP ( MI , MRI , B , true ) ; case TargetOpcode :: G_UITOFP : return legalizeITOFP ( MI , MRI , B , false ) ; case TargetOpcode :: G_FPTO<ISA_LIT> : return legalizeFPTOI ( MI , MRI , B , true ) ; case TargetOpcode :: G_FPTOUI : return legalizeFPTOI ( MI , MRI , B , false ) ; case TargetOpcode :: G_FMINNUM : case TargetOpcode :: G_FMAXNUM : case TargetOpcode :: G_FMINNUM_IEEE : case TargetOpcode :: G_FMAXNUM_IEEE : return legalizeMinNumMaxNum ( Helper , MI ) ; case TargetOpcode :: G_EXTRACT_VECTOR_ELT : return legalizeExtractVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_INSERT_VECTOR_ELT : return legalizeInsertVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return legalizeShuffleVector ( MI , MRI , B ) ; case TargetOpcode :: G_F<ISA_LIT>N : case TargetOpcode :: G_FCOS : return legalizeSinCos ( MI , MRI , B ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeGlobalValue ( MI , MRI , B ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : return legalizeLoad ( Helper , MI ) ;


<s> static bool needsAggressiveScheduling ( unsigned Directive ) { switch ( Directive ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


__asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ;


<s> <ISA_LIT>IncomingValueAssigner ( CCAssignFn * AssignFn_ , CCAssignFn * AssignFnVarArg_ ) : IncomingValueAssigner ( AssignFn_ , AssignFnVarArg_ ) {


<s> createUnpackShuffleMask ( VT , Unpckh , false , false ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckh ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckl ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckl ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckh ) ;

if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckh ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 ) ;


<s> void addMRSOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( Subtarget . hasAVX ( ) && N -> getOpcode ( ) == <STR_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ;

if ( TLI . isTypeLegal ( VT ) && TLI . isTypeLegal ( In . getValueType ( ) ) ) if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( StringRef TT ) { Triple TheTriple ( TT ) ; if ( ( TheTriple . getArch ( ) == Triple :: mips ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) IsLittleEndian = false ;

if ( ( TheTriple . getArch ( ) == Triple :: mips64el ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) {


<s> OpcodeRevFilter ( int opc1 , int opc2 ) : Opc1 ( opc1 ) , Opc2 ( opc2 ) {


<s> case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasP9Altivec ( ) ) { switch ( IntrinsicID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; } isDot = true ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = true ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; isDot = true ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) { CompareOpc = <NUM_LIT> ; isDot = true ; } else return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasVSX ( ) ) { switch ( IntrinsicID ) { case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; } isDot = true ; } else return false ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : CompareOpc = <NUM_LIT> ; break ; case <STR_LIT> : if ( Subtarget . hasP8Altivec ( ) ) CompareOpc = <NUM_LIT> ; else return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasP9Altivec ( ) ) switch ( IntrinsicID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoRVC ( ) {


<s> if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;


<s> if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts * Scale , SM_SentinelUndef ) ; for ( unsigned i = <NUM_LIT> ; i != Scale ; ++ i ) { if ( UndefElts [ i ] ) continue ; int VecIdx = Scale * Idx + i ; ShuffleMask [ VecIdx ] = EltBits [ i ] . isNullValue ( ) ? SM_SentinelZero : VecIdx ;


<s> * loop_reg = copy_addr_to_reg ( XEXP ( mem , <NUM_LIT> ) ) ; * loop_mem = change_address ( mem , BLKmode , * loop_reg ) ;

set_mem_align ( * loop_mem , MIN ( ( HOST_WIDE_INT ) MEM_ALIGN ( mem ) , length * BITS_PER_UNIT ) ) ;


<s> inline SDValue getSmallIPtrImm ( unsigned Imm ) {

return CurDAG -> getTargetConstant ( Imm , <ISA_LIT>tli . getPointerTy ( ) ) ;


<s> assert ( Size <= <NUM_LIT> && <STR_LIT> ) ;

for ( int i = ( Size - <NUM_LIT> ) * <NUM_LIT> ; i >= <NUM_LIT> ; i -= <NUM_LIT> ) EmitByte ( ( Val >> i ) & <NUM_LIT> , CurByte , OS ) ;


<s> bool isVarArg = FTy -> isVarArg ( ) ; Type * RetTy = I -> getType ( ) ; MVT RetVT ; if ( RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeLegal ( RetTy , RetVT ) && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> && RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , isVarArg , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true , isVarArg ) ) ; if ( RVLocs . size ( ) >= <NUM_LIT> && RetVT != <STR_LIT> ) return false ; } SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < unsigned , <NUM_LIT> > ArgRegs ; SmallVector < MVT , <NUM_LIT> > ArgVTs ; SmallVector < <STR_LIT> , <NUM_LIT> > ArgFlags ; unsigned arg_size = CS . arg_size ( ) ; Args . reserve ( arg_size ) ; ArgRegs . reserve ( arg_size ) ; ArgVTs . reserve ( arg_size ) ; ArgFlags . reserve ( arg_size ) ; for ( ImmutableCallSite :: arg_iterator i = CS . arg_begin ( ) , e = CS . arg_end ( ) ; i != e ; ++ i ) { if ( IntrMemName && e - i <= <NUM_LIT> ) break ; <STR_LIT> Flags ; unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: SwiftSelf ) || CS . paramHasAttr ( AttrInd , Attribute :: SwiftError ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ;


<s> str += <NUM_LIT> ; } parse_res = aarch64_parse_extension ( str , & isa_flags ) ; if ( parse_res == AARCH64_PARSE_OK ) { aarch64_isa_flags = isa_flags ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG :

error ( <STR_LIT> , pragma_or_attr , str ) ;


<s> if ( ReturnAddrIndex == <NUM_LIT> ) { uint64_t SlotSize = TD -> getPointerSize ( ) ;

ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , true ) ;


<s> case <STR_LIT> : if ( ST -> hasMVEFloatOps ( ) ) continue ; break ; default : break ; } if ( IsMasked ( & I ) ) { auto * VecTy = getVectorType ( Int ) ; unsigned Lanes = VecTy -> getNumElements ( ) ; unsigned ElementWidth = VecTy -> getScalarSizeInBits ( ) ; unsigned MaxWidth = TTI -> getRegisterBitWidth ( true ) ; if ( Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth ) return false ; MaskedInsts . push_back ( cast < IntrinsicInst > ( & I ) ) ; continue ; } for ( const Use & U : Int -> args ( ) ) { if ( isa < VectorType > ( U -> getType ( ) ) ) return false ; } } } if ( ! ActiveLaneMask ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }


<s> bool isT2SOImmNot ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ;

return <STR_LIT> ( Value ) == - <NUM_LIT> && <STR_LIT> ( ~ Value ) != - <NUM_LIT> ;


<s> MachineInstr & UseMI = * I -> getParent ( ) ; unsigned OpNo = <NUM_LIT> ; switch ( UseMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : OpNo = I . getOperandNo ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool doesNotRet , bool & isTailCall , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { isTailCall = false ; switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; bool Is64Bit = Subtarget -> is64Bit ( ) ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } SDValue Val ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) CopyVT = <STR_LIT> ; SDValue Ops [ ] = { Chain , InFlag } ; Chain = SDValue ( DAG . getMachineNode ( <STR_LIT> , dl , CopyVT , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) , <NUM_LIT> ) ; Val = Chain . getValue ( <NUM_LIT> ) ;

if ( CopyVT != VA . getValVT ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write16 ( nopEncoding ) ; if ( Count & <NUM_LIT> ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? <ISA_LIT>v6T2_NopEncoding : <ISA_LIT>v4_NopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ;


<s> if ( ( orig [ i ] == 'W' || orig [ i ] == 'L' ) && equiv [ i ] == 'Q' ) continue ; if ( ( orig [ i ] == '1' || orig [ i ] == '3' ) && equiv [ i ] == '6' ) continue ; if ( ( orig [ i ] == '6' || orig [ i ] == '2' ) && equiv [ i ] == '4' ) continue ; return FALSE ; }


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ShortenInstPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ElimComparePass ( get<ISA_LIT>TargetMachine ( ) ) ) ;

addPass ( create<ISA_LIT>LongBranchPass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> val = expand_simple_binop ( SImode , ASHIFT , val , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } mem = rs6000_pre_atomic_barrier ( mem , model ) ; label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , <NUM_LIT> ) ) ; emit_load_locked ( mode , retval , mem ) ; x = val ; if ( mask ) x = rs6000_mask_atomic_subword ( retval , val , mask ) ; cond = gen_reg_rtx ( CCmode ) ; emit_store_conditional ( mode , cond , mem , x ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ;


<s> if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ; if ( Op . size ( ) >= <NUM_LIT> && Op . isAligned ( Align ( <NUM_LIT> ) ) ) return <STR_LIT> ;


<s> bool Thumb2ITBlockPass :: MoveCopyOutOfITBlock ( MachineInstr * MI , <STR_LIT> CC , <STR_LIT> OCC , SmallSet < unsigned , <NUM_LIT> > & Defs , SmallSet < unsigned , <NUM_LIT> > & Uses ) { if ( ! isCopy ( MI ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( Uses . count ( DstReg ) || Defs . count ( SrcReg ) ) return false ;


<s> NumBytes += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameLowering :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && GuaranteedTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask ) & ~ AlignMask ; }


<s> if ( ! <STR_LIT> ( & F ) ) continue ; Changed |= processUsedLDS ( M , & F ) ; } UsedList . clear ( ) ; return Changed ;


<s> SDLoc DL ( Addr ) ; if ( ! GLC . getNode ( ) ) GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( ! SLC . getNode ( ) ) SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; TFE = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N2 ; VAddr = N3 ; } else { VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; } if ( isLegalMUBUFImmOffset ( C1 ) ) { Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; } if ( isUInt < <NUM_LIT> > ( C1 -> getZExtValue ( ) ) ) { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ;


<s> for ( SUnit :: const_succ_iterator I = SU -> Succs . begin ( ) , E = SU -> Succs . end ( ) ; I != E ; ++ I ) { SUnit & Succ = * I -> getSUnit ( ) ;


<s> static DecodeStatus DecodeMemEVA ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( Insn >> <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler :: Success ;


<s> IntermediateVT = RegisterVT ; NumIntermediates = VT . getFixedSizeInBits ( ) < RegisterVT . getFixedSizeInBits ( ) ? VT . getVectorNumElements ( ) : divideCeil ( VT . getSizeInBits ( ) , RegisterVT . getSizeInBits ( ) ) ; return NumIntermediates ;


<s> addAssemblyEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool Verbose , raw_ostream & Out ) {

PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , OptLevel , Verbose ) ) ;


<s> unsigned PredDefs = countPredicateDefs ( FP . SplitB ) ; if ( FP . JoinB ) { TotalPh = computePhiCost ( FP . JoinB , FP ) ; PredDefs += countPredicateDefs ( FP . JoinB ) ; } else { if ( FP . TrueB && FP . TrueB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . TrueB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } if ( FP . FalseB && FP . FalseB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * SB = * FP . FalseB -> succ_begin ( ) ; TotalPh += computePhiCost ( SB , FP ) ; PredDefs += countPredicateDefs ( SB ) ; } } DEBUG ( dbgs ( ) << <STR_LIT> << TotalPh << <STR_LIT> ) ; if ( TotalIn + TotalPh >= SizeLimit + Spare ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << PredDefs << <STR_LIT> ) ; if ( PredDefs > <NUM_LIT> ) return false ;


<s> PM . add ( createBasicTargetTransformInfoPass ( getTargetLowering ( ) ) ) ;

PM . add ( create<ISA_LIT>TargetTransformInfoPass ( this ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) {


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) { initAsmInfo ( ) ;


<s> case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return false ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : printSymbolOperand ( * this , MO , O ) ; if ( Subtarget -> isPICStyleRIPRel ( ) ) O << <STR_LIT> ; return false ; case MachineOperand :: MO_Register : O << '(' ; printOperand ( * this , MI , OpNo , O ) ; O << ')' ; return false ; } case 'c' : switch ( MO . getType ( ) ) { default : printOperand ( * this , MI , OpNo , O ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ExternalSymbol : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_GlobalAddress : printSymbolOperand ( * this , MO , O ) ; break ; } return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( * this , MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( * this , MO , ExtraCode [ <NUM_LIT> ] , O ) ; printOperand ( * this , MI , OpNo , O ) ;


<s> return parseRegister ( Operands , RegGR , <STR_LIT> , ADDR64Reg ) ;


<s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( ) const { return * get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) ;


<s> else { switch ( code ) { case EQ : op = inverted ? <STR_LIT> : <STR_LIT> ; break ; case NE : op = inverted ? <STR_LIT> : <STR_LIT> ; break ; case LT : op = inverted ? <STR_LIT> : <STR_LIT> ; break ; case GE : op = inverted ? <STR_LIT> : <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } } sprintf ( result , <STR_LIT> , op , isfp ? <STR_LIT> : <STR_LIT> , inverted ? <NUM_LIT> : <NUM_LIT> ) ;


<s> switch ( mai . getAssemblerDialect ( ) ) { case <NUM_LIT> : PrintBytes = PrintAsEncoded ; break ; case <NUM_LIT> : PrintBytes = PrintCallAsBytes ; break ;

case <NUM_LIT> : PrintBytes = PrintAllAsBytes ; break ;


<s> static const struct PrefixEntry { const char * Spelling ; <ISA_LIT>MCExpr :: VariantKind VariantKind ; uint8_t SupportedFormats ; } PrefixEntries [ ] = { { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 , COFF | ELF | MACHO } , { <STR_LIT> , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 , COFF | ELF | MACHO } , } ; StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; const auto & Prefix = llvm :: find_if ( PrefixEntries , [ & IDVal ] ( const PrefixEntry & PE ) { return PE . Spelling == IDVal ; } ) ; if ( Prefix == std :: end ( PrefixEntries ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } uint8_t CurrentFormat ; switch ( getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ) { case MCObjectFileInfo :: IsMachO : CurrentFormat = MACHO ; break ; case MCObjectFileInfo :: IsELF : CurrentFormat = ELF ; break ; case MCObjectFileInfo :: IsCOFF : CurrentFormat = COFF ;


<s> return <ISA_LIT>Reg32PressureLimit ; } if ( RC == & <STR_LIT> ) { return <ISA_LIT>Reg64PressureLimit ; } return <NUM_LIT> ;


<s> TargetRegistry :: RegisterMCSymbolizer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Symbolizer ) ;


<s> SDLoc DL ( N ) ; auto * TrueC = dyn_cast < ConstantSDNode > ( LHS ) ; auto * FalseC = dyn_cast < ConstantSDNode > ( RHS ) ; if ( ! TrueC || ! FalseC ) return SDValue ( ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS . getValueType ( ) ) ) return SDValue ( ) ; bool NeedsCondInvert = false ; if ( TrueC -> getAPIntValue ( ) . ult ( FalseC -> getAPIntValue ( ) ) && ( Cond . getOpcode ( ) == <STR_LIT> || ( Cond . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ) ) ) { NeedsCondInvert = true ; std :: swap ( TrueC , FalseC ) ; } if ( FalseC -> getAPIntValue ( ) == <NUM_LIT> && TrueC -> getAPIntValue ( ) . isPowerOf2 ( ) ) { if ( NeedsCondInvert ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( <NUM_LIT> , DL , Cond . getValueType ( ) ) ) ; Cond = DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , Cond ) ; unsigned ShAmt = TrueC -> getAPIntValue ( ) . logBase2 ( ) ; return DAG . getNode ( <STR_LIT> , DL , LHS . getValueType ( ) , Cond , DAG . getConstant ( ShAmt , DL , <STR_LIT> ) ) ; } if ( FalseC -> getAPIntValue ( ) + <NUM_LIT> == TrueC -> getAPIntValue ( ) ) { if ( NeedsCondInvert ) Cond = DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , DAG . getConstant ( <NUM_LIT> , DL , Cond . getValueType ( ) ) ) ; Cond = DAG . getNode ( <STR_LIT> , DL , FalseC -> getValueType ( <NUM_LIT> ) , Cond ) ; return DAG . getNode ( <STR_LIT> , DL , Cond . getValueType ( ) , Cond , SDValue ( FalseC , <NUM_LIT> ) ) ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { uint64_t Diff = TrueC -> getZExtValue ( ) - FalseC -> getZExtValue ( ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) Diff = ( unsigned ) Diff ; bool isFastMultiplier = false ; if ( Diff < <NUM_LIT> ) { switch ( ( unsigned char ) Diff ) { default : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : isFastMultiplier = true ; break ; } } if ( isFastMultiplier ) {

APInt Diff = TrueC -> getAPIntValue ( ) - FalseC -> getAPIntValue ( ) ;


<s> static inline float getFPImmFloat ( unsigned Imm ) { union { uint32_t I ; float F ; } FPUnion ; uint8_t Sign = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; FPUnion . I = <NUM_LIT> ; FPUnion . I |= Sign << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; FPUnion . I |= ( Exp & <NUM_LIT> ) << <NUM_LIT> ;


<s> static SDValue PXLowerADD ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; SDNodeTreeBuilder b ( Op , & DAG ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { return GENLowerADD ( Op , DAG ) ; } else if ( VT == <STR_LIT> ) { std :: string mask = <STR_LIT> ; for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) mask += <STR_LIT> ;

SDValue Mask = b . Constant ( mask , <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldSplitVectorType ( EVT VT ) const {

return VT . getScalarType ( ) . bitsLE ( <STR_LIT> ) ;


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override {

MachineFunction & MF = MIRBuilder . getMF ( ) ;


<s> sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( syscallMBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( sinkMBB ) ; BB = syscallMBB ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ElemSize , dl , <STR_LIT> ) ) ;

SDValue EXT = DAG . getNode ( <STR_LIT> , dl , ByteVT , Op0 , Op1 , Op2 ) ;


<s> case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 :


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> BlockInformation ( ) : IsRetired ( false ) , SccNum ( INVALIDSCCNUM ) {


<s> if ( ConstVal -> isOne ( ) ) return getPTrue ( DAG , dl , VT , <STR_LIT> ) ; } SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; SplatVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatVal , DAG . getValueType ( <STR_LIT> ) ) ; SDValue ID = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ID , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , SplatVal ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default :


<s> REAL_VALUE_TO_TARGET_DOUBLE ( value , bits ) ; return ( ( uint64_t ) ( unsigned long ) bits [ <NUM_LIT> ] << ( uint64_t ) <NUM_LIT> ) | ( uint64_t ) ( unsigned long ) bits [ <NUM_LIT> ] ; } else if ( GET_MODE ( x ) == SFmode ) { long bits ; REAL_VALUE_TO_TARGET_SINGLE ( value , bits ) ; return ( unsigned long ) bits ; }


<s> void <ISA_LIT>InstPrinter :: printClamp ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {

<ISA_LIT>InstPrinter :: printIfSet ( MI , OpNo , O , <STR_LIT> ) ;


<s> void function_builder :: register_function_group ( const function_group_info & group ) { ( * group . shape ) -> build ( * this , group ) ;


<s> short <ISA_LIT>InstrInfo :: getPseudoInstrPair ( const MachineInstr & MI ) const {

return <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> ) ;


<s> if ( prepareBaseForDispFormChain ( Bucket , Form ) ) MadeChange |= rewriteLoadStores ( L , Bucket , BBChanged , Form ) ; }

if ( MadeChange ) for ( auto * BB : BBChanged ) DeleteDeadPHIs ( BB ) ;


<s> bool isSplitCSR ( ) const { return IsSplitCSR ;


<s> void addShifterOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: enableAggressiveFMAFusion ( EVT VT ) const { return true ;


<s> if ( reg >= REG_B0 && reg <= REG_B2 ) return PREDICATE_B_REGS ; if ( A_REGNO_P ( reg ) ) return NONPREDICATE_A_REGS ; if ( call_used_or_fixed_reg_p ( reg ) ) return CALL_USED_B_REGS ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue RetValue = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; }


for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ;


<s> case <STR_LIT> : return DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ; case <STR_LIT> : return DAG . getConstantFP ( APFloat ( APFloat :: IEEEhalf ( ) , <STR_LIT> ) , SL , VT ) ; case <STR_LIT> : return DAG . getConstantFP ( APFloat ( APFloat :: IEEEdouble ( ) , <STR_LIT> ) , SL , VT ) ;


<s> if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( RC -> hasType ( <STR_LIT> ) ) { Opcode = <STR_LIT> ;

} else if ( RC -> hasType ( <STR_LIT> ) ) {


<s> for ( unsigned Op : { G_UADDE } ) { setAction ( { Op , s32 } , Legal ) ; setAction ( { Op , <NUM_LIT> , s1 } , Legal ) ; } for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_GEP , <NUM_LIT> , Ty } , WidenScalar ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , NarrowScalar ) ; setAction ( { G_ZEXT , s32 } , Legal ) ; setAction ( { G_SEXT , s32 } , Legal ) ;


<s> if ( S == MCDisassembler :: Success ) { DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; Inst . addOperand ( MCOperand :: CreateImm ( Op2 ) ) ; } return S ;


<s> assert ( ScalarDef && <STR_LIT> ) ; while ( ScalarDef -> getOpcode ( ) == TargetOpcode :: COPY ) { ScalarDef = MRI . getVRegDef ( ScalarDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( ScalarDef && <STR_LIT> ) ; } assert ( ScalarDef -> getOpcode ( ) == TargetOpcode :: G_CONSTANT ) ;

Idxs . push_back ( ScalarDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ) ;


<s> if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , N -> getDebugLoc ( ) , <STR_LIT> , AM . Disp , <NUM_LIT> ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , <NUM_LIT> ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . BlockAddr ) Disp = CurDAG -> getBlockAddress ( AM . BlockAddr , <STR_LIT> , true , <NUM_LIT> ) ;

else Disp = CurDAG -> getTargetConstant ( AM . Disp , <STR_LIT> ) ;


<s> return <NUM_LIT> ; case <NUM_LIT> : if ( NumOps >= <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumOps == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && ( Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> || Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ) return <NUM_LIT> ;


<s> void <ISA_LIT>PostRewrite :: selectSELRMux ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI , unsigned LowOpcode , unsigned HighOpcode ) { Register DestReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DestIsHigh = <STR_LIT> ( DestReg ) ; bool Src1IsHigh = <STR_LIT> ( Src1Reg ) ; bool Src2IsHigh = <STR_LIT> ( Src2Reg ) ; if ( DestReg != Src1Reg && DestReg != Src2Reg ) { if ( DestIsHigh != Src1IsHigh ) { BuildMI ( * MBBI -> getParent ( ) , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , getRegState ( MBBI -> getOperand ( <NUM_LIT> ) ) ) ; MBBI -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; Src1Reg = DestReg ; Src1IsHigh = DestIsHigh ; } else if ( DestIsHigh != Src2IsHigh ) { BuildMI ( * MBBI -> getParent ( ) , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) , getRegState ( MBBI -> getOperand ( <NUM_LIT> ) ) ) ; MBBI -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ;


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT> ; } } bool <ISA_LIT>MCAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OW -> write8 ( <NUM_LIT> ) ; return true ; } MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ;

return new <ISA_LIT>MCAsmBackend ( OSABI ) ;


<s> } if ( bytes > <NUM_LIT> ) return ; for ( unsigned i = <NUM_LIT> , e = Desc . getNumOperands ( ) ; i < e ; ++ i ) { if ( ! <STR_LIT> ( Desc , i ) ) continue ; const MCOperand & Op = MI . getOperand ( i ) ; if ( getLitEncoding ( Op , Desc . OpInfo [ i ] , STI ) != <NUM_LIT> ) continue ; int64_t Imm = <NUM_LIT> ; if ( Op . isImm ( ) ) Imm = Op . getImm ( ) ; else if ( Op . isExpr ( ) ) { if ( const auto * C = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ) Imm = C -> getValue ( ) ; } else if ( ! Op . isExpr ( ) ) llvm_unreachable ( <STR_LIT> ) ;

for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) {


<s> intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) RetAddr ) ; assert ( isStub && <STR_LIT> <STR_LIT> ) ; * ( intptr_t * ) RetAddr = ( intptr_t ) ( NewVal - RetAddr - <NUM_LIT> ) ; if ( isStub ) { intptr_t diff = NewVal - RetAddr + <NUM_LIT> ; if ( diff >= - <NUM_LIT> && diff <= <NUM_LIT> ) { * ( unsigned char * ) ( RetAddr - <NUM_LIT> ) = <NUM_LIT> ; * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = diff & <NUM_LIT> ; } else { * ( intptr_t * ) ( RetAddr - <NUM_LIT> ) = NewVal ; ( ( unsigned char * ) RetAddr ) [ <NUM_LIT> ] = ( <NUM_LIT> | ( <NUM_LIT> << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ) ; } sys :: ValgrindDiscardTranslations ( ( void * ) ( RetAddr - <NUM_LIT> ) , <NUM_LIT> ) ; ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] = <NUM_LIT> ;


<s> void emitTCEntry ( const MCSymbol & S ) override {

Streamer . EmitSymbolValue ( & S , <NUM_LIT> ) ;


<s> if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + <STR_LIT> + Twine ( stackSize ) ) ;


<s> return D ( <STR_LIT> , <STR_LIT> , MemR ( b , bs ) ) ;


<s> return false ; case <STR_LIT> : { Type * RetTy = II -> getCalledFunction ( ) -> getReturnType ( ) ; MVT VT ; if ( ! isTypeSupported ( RetTy , VT ) ) return false ; unsigned SrcReg = getRegForValue ( II -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; unsigned DestReg = createResultReg ( & <STR_LIT> ) ; if ( DestReg == <NUM_LIT> ) return false ; if ( VT == <STR_LIT> ) { if ( Subtarget -> has<ISA_LIT>32r2 ( ) ) { emitInst ( <STR_LIT> , DestReg ) . addReg ( SrcReg ) ; updateValueMap ( II , DestReg ) ; return true ; } else { unsigned TempReg [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { TempReg [ i ] = createResultReg ( & <STR_LIT> ) ; if ( TempReg [ i ] == <NUM_LIT> ) return false ; } emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; updateValueMap ( II , DestReg ) ; return true ; } } else if ( VT == <STR_LIT> ) { if ( Subtarget -> has<ISA_LIT>32r2 ( ) ) { unsigned TempReg = createResultReg ( & <STR_LIT> ) ;

emitInst ( <STR_LIT> , TempReg ) . addReg ( SrcReg ) ;


<s> if ( hasFP ( MF ) ) { MRI -> setPhysRegUsed ( <STR_LIT> ) ; MRI -> setPhysRegUsed ( <STR_LIT> ) ; } if ( RegInfo -> hasBasePointer ( MF ) ) MRI -> setPhysRegUsed ( RegInfo -> getBaseRegister ( ) ) ; unsigned NumGPRSpilled = <NUM_LIT> ; unsigned NumFPRSpilled = <NUM_LIT> ; bool ExtraCSSpill = false ; bool CanEliminateFrame = true ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; i += <NUM_LIT> ) { assert ( CSRegs [ i + <NUM_LIT> ] && <STR_LIT> ) ; const unsigned OddReg = CSRegs [ i ] ; const unsigned EvenReg = CSRegs [ i + <NUM_LIT> ] ; assert ( ( <STR_LIT> . contains ( OddReg ) && <STR_LIT> . contains ( EvenReg ) ) ^ ( <STR_LIT> . contains ( OddReg ) && <STR_LIT> . contains ( EvenReg ) ) && <STR_LIT> ) ; const bool OddRegUsed = MRI -> isPhysRegUsed ( OddReg ) ; const bool EvenRegUsed = MRI -> isPhysRegUsed ( EvenReg ) ; if ( ! OddRegUsed && ! EvenRegUsed ) { if ( <STR_LIT> . contains ( OddReg ) ) { UnspilledCSGPRs . push_back ( OddReg ) ; UnspilledCSGPRs . push_back ( EvenReg ) ;


<s> static bool isBswapIntrinsicCall ( const Value * V ) { if ( const Instruction * I = dyn_cast < Instruction > ( V ) ) if ( auto * CI = dyn_cast < CallInst > ( I ) ) if ( auto * F = CI -> getCalledFunction ( ) ) if ( F -> getIntrinsicID ( ) == <STR_LIT> ) return true ; return false ;


<s> void <ISA_LIT>DAGToDAGISel :: InstructionSelect ( ) {


<s> case <STR_LIT> : return Perform<ISA_LIT>LoadCombine ( N , DCI ) ; } return SDValue ( ) ;


<s> addPass ( create<ISA_LIT>LongBranchPass ( ) ) ; addPass ( create<ISA_LIT>HazardSchedule ( ) ) ;

addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ;


<s> static void __attribute__ ( ( format ( printf , <NUM_LIT> , <NUM_LIT> ) ) ) ovld_diag ( int diagpos , const char * fmt , ... ) { va_list args ; int real_line , real_pos ; real_line_pos ( diagpos , & real_line , & real_pos ) ; fprintf ( stderr , <STR_LIT> , ovld_path , real_line , real_pos ) ;


<s> return ( float32x2_t ) __builtin_neon_vrsqrtsv2sf ( __a , __b ) ;


<s> if ( <STR_LIT> ( * InsertBefore ) ) Value = InsertBefore -> getOperand ( <NUM_LIT> ) . getCImm ( ) ; else Value = cimm ( * C , <NUM_LIT> ) ; unsigned RegConst = MRI -> createVirtualRegister ( & <STR_LIT> ) ; InsertBefore = BuildMI ( * MBB , * InsertBefore , InsertBefore -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , RegConst ) . addCImm ( Value ) ; Use . ChangeToRegister ( RegConst , false , false , true ) ;


<s> assert ( SatWidth <= DstElementWidth && <STR_LIT> ) ; if ( DstVT . isScalableVector ( ) ) return SDValue ( ) ; EVT SrcElementVT = SrcVT . getVectorElementType ( ) ; if ( SrcElementVT == <STR_LIT> && ( ! Subtarget -> hasFullFP16 ( ) || DstElementWidth > <NUM_LIT> ) ) { MVT F32VT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; SrcVal = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , F32VT , SrcVal ) ; SrcVT = F32VT ; SrcElementVT = <STR_LIT> ; SrcElementWidth = <NUM_LIT> ; } else if ( SrcElementVT != <STR_LIT> && SrcElementVT != <STR_LIT> && SrcElementVT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; if ( SrcElementWidth == DstElementWidth && SrcElementWidth == SatWidth ) return DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT . getScalarType ( ) ) ) ; if ( SrcElementWidth < SatWidth || SrcElementVT == <STR_LIT> ) return SDValue ( ) ; EVT IntVT = SrcVT . changeVectorElementTypeToInteger ( ) ; SDValue NativeCvt = DAG . getNode ( Op . getOpcode ( ) , DL , IntVT , SrcVal , DAG . getValueType ( IntVT . getScalarType ( ) ) ) ; SDValue Sat ; if ( Op . getOpcode ( ) == <STR_LIT> ) {

SDValue MinC = DAG . getConstant ( APInt :: getSignedMaxValue ( SatWidth ) . sext ( SrcElementWidth ) , DL , IntVT ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectVectorSHL ( MachineInstr & I , MachineRegisterInfo & MRI ) const { assert ( I . getOpcode ( ) == TargetOpcode :: G_SHL ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; unsigned Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; unsigned Opc = <NUM_LIT> ; if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineIRBuilder MIB ( I ) ; auto UShl = MIB . buildInstr ( Opc , { DstReg } , { Src1Reg , Src2Reg } ) ;

constrainSelectedInstRegOperands ( * UShl , TII , TRI , RBI ) ;


<s> return ( int8x8_t ) __builtin_aarch64_addhnv8hi ( __a , __b ) ;


<s> Value = <STR_LIT> ( ~ Value & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Value ) ) ;


<s> void MetadataStreamerV3 :: emitKernelAttrs ( const Function & Func , msgpack :: MapDocNode Kern ) { if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) Kern [ <STR_LIT> ] = getWorkGroupDimensions ( Node ) ; if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) Kern [ <STR_LIT> ] = getWorkGroupDimensions ( Node ) ; if ( auto Node = Func . getMetadata ( <STR_LIT> ) ) { Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( getTypeName ( cast < ValueAsMetadata > ( Node -> getOperand ( <NUM_LIT> ) ) -> getType ( ) , mdconst :: extract < ConstantInt > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) , true ) ; } if ( Func . hasFnAttribute ( <STR_LIT> ) ) {

Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( Func . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . str ( ) , true ) ;


<s> if ( ! ST . hasFlatInstOffsets ( ) ) return false ; if ( ST . hasFlatSegmentOffsetBug ( ) && AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS ) return false ; unsigned N = <STR_LIT> ( ST , Signed ) ; return Signed ? isIntN ( N , Offset ) : isUIntN ( N , Offset ) ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadCopies ; for ( MachineBasicBlock & MBB : * MF ) { LF . initialize ( MBB ) ; for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( DstReg ) || MRI -> getRegClass ( DstReg ) != & <STR_LIT> ) continue ; if ( MRI -> use_empty ( DstReg ) ) { DeadCopies . push_back ( & MI ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MRI -> setRegClass ( DstReg , & <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) continue ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) || ! isLaneMaskReg ( SrcReg ) ) { assert ( TII -> getRegisterInfo ( ) . getRegSizeInBits ( SrcReg , * MRI ) == <NUM_LIT> ) ; unsigned TmpReg = createLaneMaskReg ( * MF ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( TmpReg ) ; SrcReg = TmpReg ; } MachineBasicBlock * PostDomBound = & MBB ; for ( MachineInstr & Use : MRI -> use_instructions ( DstReg ) ) { PostDomBound = PDT -> findNearestCommonDominator ( PostDomBound , Use . getParent ( ) ) ; } unsigned FoundLoopLevel = LF . findLoop ( PostDomBound ) ; if ( FoundLoopLevel ) { SSAUpdater . Initialize ( DstReg ) ; SSAUpdater . AddAvailableValue ( & MBB , DstReg ) ; LF . addLoopEntries ( FoundLoopLevel , SSAUpdater ) ;

buildMergeLaneMasks ( MBB , MI , DL , DstReg , SSAUpdater . GetValueInMiddleOfBlock ( & MBB ) , SrcReg ) ;


<s> MachineBasicBlock & NewMBB = * MF . CreateMachineBasicBlock ( ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( & MBB ) ) , & NewMBB ) ; if ( Br ) { assert ( Br -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & Succ && <STR_LIT> ) ; Br -> getOperand ( <NUM_LIT> ) . setMBB ( & NewMBB ) ; if ( ! UncondBr ) { MachineBasicBlock & OldLayoutSucc = * std :: next ( MachineFunction :: iterator ( & NewMBB ) ) ; assert ( MBB . isSuccessor ( & OldLayoutSucc ) && <STR_LIT> <STR_LIT> ) ; auto BrBuilder = BuildMI ( & MBB , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( & OldLayoutSucc ) ; UncondBr = & * BrBuilder ; } if ( ! NewMBB . isLayoutSuccessor ( & Succ ) ) { SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII . insertBranch ( NewMBB , & Succ , nullptr , Cond , Br -> getDebugLoc ( ) ) ; } } else { assert ( ! UncondBr && <STR_LIT> ) ;

assert ( NewMBB . isLayoutSuccessor ( & Succ ) && <STR_LIT> <STR_LIT> ) ;


<s> } if ( max_index != - <NUM_LIT> ) { if ( max_index != last_index ) { tmp = ready [ max_index ] ; ready [ max_index ] = ready [ last_index ] ; ready [ last_index ] = tmp ; if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> , INSN_UID ( ready [ last_index ] ) ) ; } else if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> , INSN_UID ( ready [ last_index ] ) ) ; } if ( verbose > <NUM_LIT> ) { fprintf ( file , <STR_LIT> , s390_sched_state ) ; for ( i = last_index ; i >= <NUM_LIT> ; i -- ) { unsigned int sched_mask ; rtx_insn * insn = ready [ i ] ; if ( recog_memoized ( insn ) < <NUM_LIT> ) continue ; sched_mask = s390_get_sched_attrmask ( insn ) ; fprintf ( file , <STR_LIT> , INSN_UID ( insn ) , s390_sched_score ( insn ) ) ; ( ( M ) & sched_mask ) ? # ATTR : <STR_LIT> ) ; PRINT_SCHED_ATTR ( S390_SCHED_ATTR_MASK_CRACKED , cracked ) ; PRINT_SCHED_ATTR ( S390_SCHED_ATTR_MASK_EXPANDED , expanded ) ; PRINT_SCHED_ATTR ( S390_SCHED_ATTR_MASK_ENDGROUP , endgroup ) ; PRINT_SCHED_ATTR ( S390_SCHED_ATTR_MASK_GROUPALONE , groupalone ) ; if ( s390_tune >= PROCESSOR_2964_Z13 ) { unsigned int unit_mask , m = <NUM_LIT> ; int units , j ; unit_mask = s390_get_unit_mask ( insn , & units ) ; fprintf ( file , <STR_LIT> ) ; for ( j = <NUM_LIT> ; j < units ; j ++ , m <<= <NUM_LIT> ) if ( m & unit_mask ) fprintf ( file , <STR_LIT> , j ) ; fprintf ( file , <STR_LIT> ) ;


<s> unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ;


<s> OptionalArgs . push_back ( emitEHLSDA ( Builder , & F ) ) ; } else if ( Personality == EHPersonality :: MSVC_<ISA_LIT>SEH ) { OptionalArgs . push_back ( SehLongjmpUnwind . getCallee ( ) ) ; OptionalArgs . push_back ( State ) ; if ( UseStackGuard ) OptionalArgs . push_back ( Cookie ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } SmallVector < Value * , <NUM_LIT> > Args ; Args . push_back ( Builder . CreateBitCast ( Call . getArgOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ) ; Args . push_back ( Builder . getInt32 ( OptionalArgs . size ( ) ) ) ; Args . append ( OptionalArgs . begin ( ) , OptionalArgs . end ( ) ) ; CallBase * NewCall ; if ( auto * CI = dyn_cast < CallInst > ( & Call ) ) { CallInst * NewCI = Builder . CreateCall ( SetJmp3 , Args , OpBundles ) ;

NewCI -> setTailCallKind ( CI -> getTailCallKind ( ) ) ;


<s> <ISA_LIT>IncomingValueHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI ) : IncomingValueHandler ( MIRBuilder , MRI ) , DL ( MIRBuilder . getMF ( ) . getDataLayout ( ) ) {


<s> static bool csky_can_use_ldstm ( int mask , int * br , int * er ) { int regno ; int begin_reg = <NUM_LIT> , end_reg = <NUM_LIT> ; int count = <NUM_LIT> ; if ( ! TARGET_MULTIPLE_STLD ) return false ;


<s> unsigned I1 = ! ( J1 ^ S ) ; unsigned I2 = ! ( J2 ^ S ) ; unsigned tmp = ( Val & ~ <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ;

if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( imm32 ) ) ;


<s> const MachineBasicBlock * getMBB ( ) const { return MBB ;


<s> void <ISA_LIT>PreAllocationFixups :: EnterScope ( MachineBasicBlock * MBB ) {

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << '\n' ) ;


<s> Idx -= <NUM_LIT> * ( j / <NUM_LIT> ) ; if ( Idx < <NUM_LIT> || Idx >= <NUM_LIT> ) return SDValue ( ) ; } if ( SHFIndices [ i ] == - <NUM_LIT> ) SHFIndices [ i ] = Idx ; if ( ! ( Idx == - <NUM_LIT> || Idx == SHFIndices [ i ] ) ) return SDValue ( ) ; } } APInt Imm ( <NUM_LIT> , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { int Idx = SHFIndices [ i ] ; if ( Idx == - <NUM_LIT> ) Idx = <NUM_LIT> ; Imm <<= <NUM_LIT> ; Imm |= Idx & <NUM_LIT> ;


<s> static SDValue combine<ISA_LIT>ShufflesRecursively ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { return combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , <STR_LIT> , false , true , DAG , Subtarget ) ;


<s> SDValue Value , Overflow ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; unsigned BaseOp = <NUM_LIT> ; SDLoc DL ( Op ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } if ( BaseOp ) { SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; Value = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS ) ; Overflow = Value . getValue ( <NUM_LIT> ) ; }

return std :: make_pair ( Value , Overflow ) ;


<s> __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ;


<s> if ( REG_P ( a ) ) reg_a = REGNO ( a ) ; while ( GET_CODE ( b ) == SUBREG ) b = SUBREG_REG ( b ) ; if ( REG_P ( b ) ) reg_b = REGNO ( b ) ; return reg_a != reg_b ;


<s> const unsigned * Reg = <ISA_LIT>64IntRegs + <NUM_LIT> ; int FOOffset ; if ( IsRegLoc ) { Reg = std :: find ( <ISA_LIT>64IntRegs , <ISA_LIT>64IntRegs + <NUM_LIT> , VA . getLocReg ( ) ) ; FOOffset = ( Reg - <ISA_LIT>64IntRegs ) * <NUM_LIT> - <NUM_LIT> * <NUM_LIT> ; } else FOOffset = VA . getLocMemOffset ( ) ; unsigned NumRegs = ( Flags . getByValSize ( ) + <NUM_LIT> ) / <NUM_LIT> ; unsigned LastFI = MFI -> CreateFixedObject ( NumRegs * <NUM_LIT> , FOOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( LastFI , PtrTy ) ; InVals . push_back ( FIN ) ; for ( unsigned I = <NUM_LIT> ; ( Reg != <ISA_LIT>64IntRegs + <NUM_LIT> ) && ( I < NumRegs ) ; ++ Reg , ++ I ) { unsigned VReg = AddLiveIn ( MF , * Reg , <STR_LIT> ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , FIN , DAG . getConstant ( I * <NUM_LIT> , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , dl , DAG . getRegister ( VReg , <STR_LIT> ) , StorePtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; OutChains . push_back ( Store ) ; }


<s> if ( ! Op0 . isUndef ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( ! Op1 . isUndef ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op1 ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;

return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Val ) ;


<s> break ; case OPCODE_IS_NOT_ZERO : MO . setImm ( OPCODE_IS_ZERO ) ; break ; default : return true ; } MachineOperand & MO2 = Cond [ <NUM_LIT> ] ; switch ( MO2 . getReg ( ) ) { case AMDGPU :: PRED_SEL_ZERO : MO2 . setReg ( AMDGPU :: PRED_SEL_ONE ) ; break ; case AMDGPU :: PRED_SEL_ONE : MO2 . setReg ( AMDGPU :: PRED_SEL_ZERO ) ; break ; default : return true ;


<s> static inline bool isThumbImmShiftedVal ( unsigned V ) {

V = ( ~ <NUM_LIT> << getThumbImmValShift ( V ) ) & V ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Operands ; if ( ParseRegister ( RegNo , Operands ) ) return true ;


<s> Field U6Field = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( U6Field ) ) ;

Field CCField = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> CCAssignFn * RetCC = getReturnCC ( CallConv ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ;


<s> void <ISA_LIT>InstructionSelector :: renderLogicalImm32 ( MachineInstrBuilder & MIB , const MachineInstr & I , int OpIdx ) const { assert ( I . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ;

uint64_t CstVal = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ;


<s> TargetLoweringBase :: LegalizeTypeAction <ISA_LIT>TargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT . isFixedLengthVector ( ) ) { MVT EltVT = VT . getVectorElementType ( ) ;

if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) return TypeWidenVector ;


<s> MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> return __builtin_ia32_vcvtdq2ph512_mask_round ( ( __v16si ) __B , _mm256_setzero_ph ( ) , __A , __C ) ;


<s> TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ; MRI . constrainRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRC ) ; unsigned AddrMode = ( MCID . TSFlags & <STR_LIT> ) ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , MCID ) . addReg ( NewReg , RegState :: Define ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Offset ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . cloneMemRefs ( * MI ) ; case <STR_LIT> : if ( MI -> mayLoad ( ) ) { return BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , MCID ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addReg ( NewReg , RegState :: Define ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Offset ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . cloneMemRefs ( * MI ) ; } else { return BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , MCID ) . addReg ( NewReg , RegState :: Define ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Offset ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . cloneMemRefs ( * MI ) ; } default : llvm_unreachable ( <STR_LIT> ) ; }


<s> return __aarch64_vget_lane_any ( __a , __b ) ;


<s> if ( sibthunk_p ) goto epilogue_done ; } if ( ( ! SMALL_INT ( first_offset ) && cfun -> machine -> frame_info . gmask && ( ( TARGET_ARC700 && ! optimize_size ) ? first_offset <= <NUM_LIT> : satisfies_constraint_C2a ( GEN_INT ( first_offset ) ) ) ) || ( MUST_SAVE_RETURN_ADDR && ! SMALL_INT ( ( cfun -> machine -> frame_info . reg_size + first_offset ) >> <NUM_LIT> ) && cfun -> machine -> frame_info . gmask ) ) { frame_stack_add ( first_offset ) ; first_offset = <NUM_LIT> ; } if ( MUST_SAVE_RETURN_ADDR ) { rtx ra = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; int ra_offs = cfun -> machine -> frame_info . reg_size + first_offset ; rtx addr = plus_constant ( Pmode , stack_pointer_rtx , ra_offs ) ; if ( ! SMALL_INT ( ra_offs >> <NUM_LIT> ) && ! cfun -> machine -> frame_info . gmask && ( ( TARGET_ARC700 && ! optimize_size ) ? ra_offs <= <NUM_LIT> : satisfies_constraint_C2a ( GEN_INT ( ra_offs ) ) ) ) { size_to_deallocate -= ra_offs - first_offset ; first_offset = <NUM_LIT> ; frame_stack_add ( ra_offs ) ; ra_offs = <NUM_LIT> ; addr = stack_pointer_rtx ; } if ( ra_offs && ! cfun -> machine -> frame_info . gmask && ( SMALL_INT ( ra_offs ) || ! SMALL_INT ( ra_offs >> <NUM_LIT> ) ) ) { addr = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , addr ) ; first_offset = <NUM_LIT> ; size_to_deallocate -= cfun -> machine -> frame_info . reg_size ; } else if ( ! ra_offs && size_to_deallocate == UNITS_PER_WORD ) { addr = gen_rtx_POST_INC ( Pmode , addr ) ; size_to_deallocate = <NUM_LIT> ; }

frame_move_inc ( ra , gen_frame_mem ( Pmode , addr ) , stack_pointer_rtx , addr ) ;


<s> <ISA_LIT>ConstantPoolValue :: <ISA_LIT>ConstantPoolValue ( const GlobalValue * gv , <STR_LIT> modifier ) : MachineConstantPoolValue ( gv -> getType ( ) ) , GV ( gv ) , Modifier ( modifier ) {


<s> } if ( Options . isReorder ( ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Options . setNomacro ( ) ;


<s> bool hasDivideInThumbMode ( ) const { return HasHardwareDivideInThumb ;


<s> static bool classof ( const DiagnosticInfo * DI ) {

return DI -> getKind ( ) == getKindID ( ) ;


<s> Register AndReg = MRI -> createVirtualRegister ( BoolRC ) ; And = BuildMI ( MBB , & MI , DL , TII -> get ( AndOpc ) , AndReg ) . addReg ( Exec ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( LV ) LV -> replaceKillInstruction ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI , * And ) ; Or = BuildMI ( MBB , & MI , DL , TII -> get ( OrOpc ) , Dst ) . addReg ( AndReg ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( LIS ) LIS -> createAndComputeVirtRegInterval ( AndReg ) ; } else { Or = BuildMI ( MBB , & MI , DL , TII -> get ( OrOpc ) , Dst ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;

if ( LV ) LV -> replaceKillInstruction ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI , * Or ) ;


<s> return AMDGPUMCInstLower :: <ISA_LIT> ;


<s> int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( x & ( ( unsigned short ) <NUM_LIT> << i ) ) break ; return i ;


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( false && <STR_LIT> ) ; }


<s> std :: pair < SDValue , SDValue > <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForStrcmp ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src1 , SDValue Src2 , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { SDVTList VTs = DAG . getVTList ( Src1 . getValueType ( ) , <STR_LIT> , <STR_LIT> ) ; SDValue Unused = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Src2 , Src1 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue CCReg = Unused . getValue ( <NUM_LIT> ) ; Chain = Unused . getValue ( <NUM_LIT> ) ; return std :: make_pair ( addIPMSequence ( DL , CCReg , DAG ) , Chain ) ;


<s> SDValue CondReg = DAG . getCopyFromReg ( Chain , dl , CCReg , <STR_LIT> ) ; CondReg = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , CondReg ) ; CondReg = DAG . getCopyFromReg ( CondReg , dl , <STR_LIT> , <STR_LIT> ) ; SDValue Cst = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CondReg , Cst ) ;


<s> OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ;

OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

return getFrameLowering ( MF ) -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; } } } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && isa < ConstantSDNode > ( RHS ) ) { if ( ( cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) >> <NUM_LIT> == <NUM_LIT> ) && isa < LoadSDNode > ( LHS ) ) { if ( cast < LoadSDNode > ( LHS ) -> getExtensionType ( ) == <STR_LIT> && cast < LoadSDNode > ( LHS ) -> getMemoryVT ( ) == <STR_LIT> && LHS . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { int16_t ValueofRHS = cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ; if ( ValueofRHS < <NUM_LIT> && isLegalArithImmed ( - ValueofRHS ) ) {

SDValue SExt = DAG . getNode ( <STR_LIT> , dl , LHS . getValueType ( ) , LHS , DAG . getValueType ( <STR_LIT> ) ) ;


<s> __builtin_aarch64_st1v4si ( ( __builtin_aarch64_simd_si * ) a , b ) ;


<s> int m32c_hard_regno_ok ( int regno , machine_mode mode ) { return m32c_hard_regno_nregs_1 ( regno , mode ) != <NUM_LIT> ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; uint64_t Offset = getImplicitParameterOffset ( MF , Param ) ; SDValue Ptr = lowerKernArgParameterPtr ( DAG , DL , DAG . getEntryNode ( ) , Offset ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , PtrInfo , Alignment , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> if ( LHS . getValueType ( ) . getVectorElementType ( ) . isInteger ( ) ) { assert ( LHS . getValueType ( ) == RHS . getValueType ( ) ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; return EmitVectorComparison ( LHS , RHS , <ISA_LIT>CC , false , Op . getValueType ( ) , dl , DAG ) ; } assert ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> || LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , Op . getValueType ( ) , dl , DAG ) ; if ( ! Cmp . getNode ( ) ) return SDValue ( ) ; if ( CC2 != <STR_LIT> ) {

SDValue Cmp2 = EmitVectorComparison ( LHS , RHS , CC2 , NoNaNs , Op . getValueType ( ) , dl , DAG ) ;


<s> Cost = vectorCostAdjustment ( Cost , Opcode , Src , nullptr ) ; bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsQPXType = ST -> hasQPX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || * Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && * Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ; if ( IsVSXType || ( ST -> hasVSX ( ) && IsAltivecType ) ) return Cost ; if ( TLI -> allowsMisalignedMemoryAccesses ( LT . second , <NUM_LIT> ) ) return Cost ;


<s> bool <ISA_LIT>GOT :: isGOTFull ( ) const {

uint64_t gotCount = <ISA_LIT>GOT0Num + m_MultipartList . back ( ) . m_LocalNum + m_MultipartList . back ( ) . m_GlobalNum ;


<s> if ( ! KindRes ) return true ; unsigned ElementWidth = KindRes -> second ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( Reg , RegKind :: NeonVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , S , getContext ( ) ) ) ;

return tryParseVectorIndex ( Operands ) == MatchOperand_ParseFail ;


<s> vec_st ( ( vec_uchar16 ) ( a ) , <NUM_LIT> , ( vector unsigned char * ) ( imm ) ) ;


<s> MachineInstr * MI ; bool defInDifferentBlock = ! isBeingScheduled ( DefMI -> getParent ( ) ) ; if ( defInDifferentBlock ) { MachineBasicBlock :: iterator InsertIt = DefMI ; if ( DefMI -> isPHI ( ) ) InsertIt = DefMBB -> getFirstNonPHI ( ) ; else ++ InsertIt ; MI = BuildMI ( * DefMI -> getParent ( ) , InsertIt , dl , TII -> get ( TargetOpcode :: COPY ) , vnew ) . addReg ( reg ) ; } else { MI = BuildMI ( MF , dl , TII -> get ( TargetOpcode :: COPY ) , vnew ) . addReg ( reg ) ; } SUnit * SU = new SUnit ( MI , SUnits . size ( ) + CopySUs . size ( ) ) ; SU -> OrigNode = SU ; if ( ! defInDifferentBlock ) { CopySUs . push_back ( SU ) ; Sequence . push_back ( SU ) ; } CAState -> addXccSplit ( reg , vnew , side , MI ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const {

return StackOffset :: getFixed ( ResolveFrameIndexReference ( MF , FI , FrameReg , <NUM_LIT> ) ) ;


<s> case 'K' : case 'N' : case 'G' : case 'L' : case 'M' : return C_Immediate ; case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } else if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'Y' : switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'z' : case '0' : return C_Register ; case 'i' : case 'm' : case 'k' : case 't' : case '2' : return C_RegisterClass ; }


<s> SDValue PassThru = ExtendToType ( N -> getPassThru ( ) , WideDataVT , DAG ) ; assert ( Mask . getSimpleValueType ( ) . getScalarType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT WideMaskVT = <STR_LIT> ( <STR_LIT> , NumEltsInWideVec ) ; Mask = ExtendToType ( Mask , WideMaskVT , DAG , true ) ; SDValue NewLoad = DAG . getMaskedLoad ( WideDataVT , dl , N -> getChain ( ) , N -> getBasePtr ( ) , Mask , PassThru , N -> getMemoryVT ( ) , N -> getMemOperand ( ) , N -> getExtensionType ( ) , N -> isExpandingLoad ( ) ) ; SDValue Exract = DAG . getNode ( <STR_LIT> , dl , VT , NewLoad . getValue ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;

SDValue RetOps [ ] = { Exract , NewLoad . getValue ( <NUM_LIT> ) } ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( Attribute :: Naked ) ) return false ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> machine_mode mode = GET_MODE ( mem ) ; HOST_WIDE_INT offset = GET_MODE_SIZE ( mode ) ; rtx addr = plus_constant ( Pmode , XEXP ( mem , <NUM_LIT> ) , offset ) ; return adjust_automodify_address ( mem , mode , addr , offset ) ;


<s> <ISA_LIT>AAResult ( <ISA_LIT>AAResult && Arg ) : AAResultBase ( std :: move ( Arg ) ) , DL ( Arg . DL ) {


<s> unsigned <ISA_LIT>Subtarget :: getMispredictionPenalty ( ) const { return SchedModel . MispredictPenalty ;


<s> SDVTList VTList = DAG . getVTList ( VT , <STR_LIT> ) ; if ( Offset ) Ptr = DAG . getNode ( <STR_LIT> , DL , BasePtrVT , Ptr , DAG . getConstant ( Offset , BasePtrVT ) ) ; SDValue Ops [ ] = { Chain , Ptr , Src } ;

return DAG . getMemIntrinsicNode ( Opc , DL , VTList , Ops , MemVT , LD -> getMemOperand ( ) ) ;


<s> bool hasRegisterAlias ( const MachineFunction * MF , Register Reg ) { return RegisterAliasTable . find ( MF ) != RegisterAliasTable . end ( ) && RegisterAliasTable [ MF ] . find ( Reg ) != RegisterAliasTable [ MF ] . end ( ) ;


<s> } else { uint64_t total_size = <NUM_LIT> ; if ( const ConstantStruct * CS = dyn_cast < ConstantStruct > ( Init ) ) total_size = DL . getStructLayout ( cast < StructType > ( CS -> getType ( ) ) ) -> getSizeInBytes ( ) ; else if ( const ConstantArray * CA = dyn_cast < ConstantArray > ( Init ) ) total_size = DL . getTypeAllocSize ( CA -> getType ( ) -> getElementType ( ) ) * CA -> getNumOperands ( ) ; else return false ; val_vec_type Vals ( total_size , <NUM_LIT> ) ; if ( fillGenericConstant ( DL , Init , Vals , <NUM_LIT> ) == false ) return false ; cs_vals_ [ static_cast < const void * > ( Init ) ] = Vals ; TmpVal = std :: move ( Vals ) ; } union { uint8_t c [ <NUM_LIT> ] ; uint16_t s ; } test_buf ; uint16_t test_val = <NUM_LIT> ; if ( DL . isLittleEndian ( ) ) <STR_LIT> :: write16le ( test_buf . c , test_val ) ;

else <STR_LIT> :: write16be ( test_buf . c , test_val ) ;


<s> BlackfinInstrInfo :: BlackfinInstrInfo ( BlackfinSubtarget & ST ) : TargetInstrInfoImpl ( BlackfinInsts , array_lengthof ( BlackfinInsts ) ) , RI ( ST , * this ) , Subtarget ( ST ) {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( fg ) ) ; return res ;


<s> OperandMatchResultTy Res = parseIntWithPrefix ( Prefix , Value ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ConvertResult && ! ConvertResult ( Value ) ) {


<s> if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } const RegisterBank * OpBank = RBI . getRegBank ( MO . getReg ( ) , MRI , TRI ) ; if ( ! OpBank ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } if ( PrevOpBank && OpBank != PrevOpBank ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } PrevOpBank = OpBank ; }


<s> OS << <STR_LIT> << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ;


<s> AMDGPU770Device :: ~ AMDGPU770Device ( ) {


<s> SDLoc dl ( Op ) ; BuildVectorSDNode * C = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! C -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs ) || EltTy . getSizeInBits ( ) < SplatBitSize ) return SDValue ( ) ; if ( ( SplatValue != <NUM_LIT> ) && ( SplatValue . isPowerOf2 ( ) || ( - SplatValue ) . isPowerOf2 ( ) ) ) { unsigned lg2 = SplatValue . countTrailingZeros ( ) ; SDValue Sz = DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , <STR_LIT> ) ;

SDValue SGN = getTargetVShiftNode ( <STR_LIT> , dl , VT , N0 , Sz , DAG ) ;


<s> if ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) return new <ISA_LIT>AddressSanitizer64 ( STI ) ; }

return new <ISA_LIT>AsmInstrumentation ( ) ;


<s> if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , <NUM_LIT> ) ) return false ; } return true ;


<s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {


<s> SDLoc dl ( N ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue FixConv = DAG . getNode ( <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( C , dl , <STR_LIT> ) ) ; if ( IntBits < FloatBits ) FixConv = DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , FixConv ) ;


<s> fputs ( <STR_LIT> , file ) ; return ; } if ( code == 'y' && STACK_TOP_P ( x ) ) { fputs ( <STR_LIT> , file ) ; return ; } if ( code == 'w' ) msize = <NUM_LIT> ; else if ( code == 'b' ) msize = <NUM_LIT> ; else if ( code == 'k' ) msize = <NUM_LIT> ; else if ( code == 'q' ) msize = <NUM_LIT> ; else if ( code == 'h' ) msize = <NUM_LIT> ; else if ( code == 'x' ) msize = <NUM_LIT> ; else if ( code == 't' ) msize = <NUM_LIT> ; else if ( code == 'g' ) msize = <NUM_LIT> ; else msize = GET_MODE_SIZE ( GET_MODE ( x ) ) ; regno = REGNO ( x ) ; if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM || regno == FPSR_REG ) { output_operand_lossage ( <STR_LIT> , reg_names [ regno ] ) ; return ; } else if ( regno == FLAGS_REG ) { output_operand_lossage ( <STR_LIT> ) ; return ; } if ( code == 'V' ) { if ( GENERAL_REGNO_P ( regno ) ) msize = GET_MODE_SIZE ( word_mode ) ; else error ( <STR_LIT> ) ; } duplicated = code == 'd' && TARGET_AVX ; switch ( msize ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : if ( GENERAL_REGNO_P ( regno ) && msize > GET_MODE_SIZE ( word_mode ) ) warning ( <NUM_LIT> , <STR_LIT> ) ; case <NUM_LIT> : if ( LEGACY_INT_REGNO_P ( regno ) ) putc ( msize > <NUM_LIT> && TARGET_64BIT ? 'r' : 'e' , file ) ; case <NUM_LIT> : normal : reg = hi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_reg_name ) ) goto normal ; if ( ! ANY_QI_REGNO_P ( regno ) ) error ( <STR_LIT> ) ; reg = qi_reg_name [ regno ] ; break ; case <NUM_LIT> : if ( regno >= ARRAY_SIZE ( qi_high_reg_name ) ) goto normal ; reg = qi_high_reg_name [ regno ] ; break ; case <NUM_LIT> : case <NUM_LIT> : if ( SSE_REGNO_P ( regno ) ) { gcc_assert ( ! duplicated ) ; putc ( msize == <NUM_LIT> ? 'y' : 'z' , file ) ; reg = hi_reg_name [ regno ] + <NUM_LIT> ; break ; } goto normal ; default : gcc_unreachable ( ) ; }


<s> unsigned getCalleeSavedFrameSize ( ) { return CalleeSavedFrameSize ;


<s> addPass ( create<ISA_LIT>AddMissingPrototypes ( ) ) ; addPass ( create<ISA_LIT>LowerGlobalDtors ( ) ) ; addPass ( create<ISA_LIT>FixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeReturned ( ) ) ; checkSanityForEHAndSjLj ( TM ) ; if ( ! WasmEnableEmEH && ! WasmEnableEH ) { addPass ( createLowerInvokePass ( ) ) ; addPass ( createUnreachableBlockEliminationPass ( ) ) ; } if ( WasmEnableEmEH || WasmEnableEmSjLj || WasmEnableSjLj ) addPass ( create<ISA_LIT>LowerEmscriptenEHSjLj ( ) ) ; addPass ( createIndirectBrExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ;