<s> addLeaRegOffset ( MIB , leaInReg , true , - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : addLeaRegOffset ( MIB , leaInReg , true , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : { unsigned Src2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill2 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned leaInReg2 = <NUM_LIT> ; MachineInstr * InsMI2 = <NUM_LIT> ; if ( Src == Src2 ) { addRegReg ( MIB , leaInReg , true , leaInReg , false ) ; } else { leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) ; InsMI2 = BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) . addReg ( leaInReg2 ) . addReg ( Src2 , getKillRegState ( isKill2 ) ) . addImm ( <STR_LIT> ) ; addRegReg ( MIB , leaInReg , true , leaInReg2 , true ) ; } if ( LV && isKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , InsMI2 ) ; break ; } } MachineInstr * NewMI = MIB ; MachineInstr * ExtMI = BuildMI ( * MFI , MBBI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( Dest , RegState :: Define | getDeadRegState ( isDead ) ) . addReg ( leaOutReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ;


<s> break ; case ARM_FT_EXCEPTION : asm_fprintf ( f , <STR_LIT> ) ; break ; } if ( IS_NAKED ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; if ( IS_VOLATILE ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; if ( IS_NESTED ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; if ( IS_STACKALIGN ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ;

if ( IS_CMSE_ENTRY ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ;


<s> Changed = true ; auto InsertPt = std :: next ( MachineBasicBlock :: iterator ( MI ) ) ; while ( InsertPt != MBB . end ( ) && InsertPt -> isLabel ( ) ) ++ InsertPt ; MachineInstr * Rethrow = nullptr ; if ( EHInfo -> hasThrowUnwindDest ( & MBB ) ) Rethrow = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( EHInfo -> getThrowUnwindDest ( & MBB ) ) ; else Rethrow = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; MBB . erase ( std :: next ( MachineBasicBlock :: iterator ( Rethrow ) ) , MBB . end ( ) ) ; for ( auto * Succ : MBB . successors ( ) ) if ( ! Succ -> isEHPad ( ) ) EraseBBAndChildren ( Succ ) ; }


<s> if ( ! readInstruction16 ( Bytes , Address , Size , insn16 ) ) { return Fail ; } DecodeStatus Result = decodeInstruction ( DecoderTable16 , instr , insn16 , Address , this , STI ) ; if ( Result != Fail ) { Size = <NUM_LIT> ;


<s> IsTexFail = true ; } SDLoc DL ( TexFailCtrlConst ) ; * TFE = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ; Value &= ~ ( uint64_t ) <NUM_LIT> ;

* LWE = DAG . getTargetConstant ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __lwpval32 ( unsigned int __data2 , unsigned int __data1 , unsigned int __flags ) {


<s> <ISA_LIT>ModuleExportPass ( <ISA_LIT>TargetMachine & tm , StringRef filename , ArrayRef < std :: string > roots , bool SerializeAll ) : PMLModuleExportPass ( ID , tm , filename , roots , SerializeAll ) { initialize<ISA_LIT>CallGraphBuilderPass ( * PassRegistry :: getPassRegistry ( ) ) ; setPMLInstrInfo ( new <ISA_LIT>PMLInstrInfo ( tm ) ) ;


<s> if ( Kind . isMergeableConst16 ( ) ) return MergeableConst16Section ;

assert ( ( Kind . isReadOnly ( ) || Kind . isReadOnlyWithRel ( ) ) && <STR_LIT> ) ;


<s> if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return false ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return false ; if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return false ; Opnd0 = LHS ; Opnd1 = RHS ;


<s> auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const <ISA_LIT>Evaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ; ConstGeneration ImmG ( BT , HII , MRI ) ; Changed |= visitBlock ( Entry , ImmG , AIG ) ; RegisterSet ARE ;

RedundantInstrElimination RIE ( BT , HII , MRI ) ;


<s> if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && ( isLoadTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) ) { unsigned TstOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; OpReg = constrainOperandRegClass ( TII . get ( TstOpc ) , OpReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TstOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( CCMode ) . addReg ( <STR_LIT> ) ; fastEmitBranch ( FBB , DbgLoc ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; fastEmitBranch ( Target , DbgLoc ) ; return true ; } unsigned CmpReg = getRegForValue ( BI -> getCondition ( ) ) ; if ( CmpReg == <NUM_LIT> ) return false ; unsigned TstOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; CmpReg = constrainOperandRegClass ( TII . get ( TstOpc ) , CmpReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TstOpc ) ) . addReg ( CmpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; }


<s> void <ISA_LIT>AsmPrinter :: printThumbAddrModeS2Operand ( const MachineInstr * MI , int Op , raw_ostream & O ) {

printThumbAddrModeRI5Operand ( MI , Op , O , <NUM_LIT> ) ;


<s> Value * <ISA_LIT>IREmitter :: visitPCMPGTM ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> bool hasFlatAddressSpace ( ) const { return FlatAddressSpace ;


<s> auto CalleeCC = CLI . CallConv ; auto IsVarArg = CLI . IsVarArg ; auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; auto CallerCC = Caller . getCallingConv ( ) ; if ( Caller . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) return false ; if ( Caller . hasFnAttribute ( <STR_LIT> ) ) return false ; if ( IsVarArg ) return false ; if ( CCInfo . getNextStackOffset ( ) != <NUM_LIT> ) return false ; for ( auto & VA : ArgLocs ) if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; auto IsCallerStructRet = Caller . hasStructRetAttr ( ) ; auto IsCalleeStructRet = Outs . empty ( ) ? false : Outs [ <NUM_LIT> ] . Flags . isSRet ( ) ; if ( IsCallerStructRet || IsCalleeStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; if ( GV -> hasExternalWeakLinkage ( ) ) return false ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ;

if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ;


<s> std :: map < const PredicatedBlock * , unsigned > getSuccessors ( ) const { return std :: map < const PredicatedBlock * , unsigned > ( Successors . begin ( ) , Successors . end ( ) ) ;


<ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM ) , DL ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> :


<s> if ( first < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , str ) ; return ; } int last = decode_reg_name ( dash + <NUM_LIT> ) ; if ( last < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash = '-' ; if ( first > last ) { warning ( <NUM_LIT> , <STR_LIT> , str , dash + <NUM_LIT> ) ; return ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; Register DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstR ) || ! <STR_LIT> . contains ( SrcR ) ) return false ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , It , DL , HII . get ( TargetOpcode :: COPY ) , TmpR ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ;

BuildMI ( B , It , DL , HII . get ( TargetOpcode :: COPY ) , DstR ) . addReg ( TmpR , RegState :: Kill ) ;


<s> if ( ResTy == MatchOperand_ParseFail ) return true ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Dollar : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseAnyRegister ( Operands ) != MatchOperand_NoMatch ) return false ; StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E , * this ) ) ; return false ; } default : { DEBUG ( dbgs ( ) << <STR_LIT> ) ; const MCExpr * Expr ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( Expr , S , E , * this ) ) ; return false ; } }


<s> int carry = <NUM_LIT> ; if ( TARGET_QMATH && <NUM_LIT> ) debug_rtx ( insn ) ; split_quadword_operands ( insn , MINUS , operands , low , <NUM_LIT> ) ; if ( TARGET_QMATH ) { if ( operands [ <NUM_LIT> ] == const0_rtx && low [ <NUM_LIT> ] == const0_rtx ) { if ( ( MEM_P ( low [ <NUM_LIT> ] ) && GET_CODE ( XEXP ( low [ <NUM_LIT> ] , <NUM_LIT> ) ) == POST_INC ) || ( MEM_P ( operands [ <NUM_LIT> ] ) && GET_CODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) == POST_INC ) ) fatal_insn ( <STR_LIT> , insn ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , low ) ; return <STR_LIT> ; } gcc_assert ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; gcc_assert ( rtx_equal_p ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] ) ) ; if ( low [ <NUM_LIT> ] == const1_rtx ) output_asm_insn ( <STR_LIT> , low ) ; else output_asm_insn ( <STR_LIT> , low ) ; return <STR_LIT> ;


<s> NodeAddr ( const NodeAddr < S > & NA ) : Addr ( static_cast < T > ( NA . Addr ) ) , Id ( NA . Id ) {


<s> const static MCFixupKindInfo InfosBE [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;

assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;


<s> if ( ! xstormy16_below100_or_register ( in , QImode ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! xstormy16_below100_or_register ( out , QImode ) ) out = gen_reg_rtx ( QImode ) ; emit_insn ( gen_andqi3_internal ( out , in , val ) ) ; if ( out != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [ <NUM_LIT> ] , out ) ; return ; }

if ( ! REG_P ( in ) ) in = copy_to_mode_reg ( QImode , in ) ;


<s> else if ( fcode >= S390_OVERLOADED_BUILTIN_OFFSET ) return bflags_overloaded_builtin [ fcode - S390_BUILTIN_MAX ] ;


<s> FOR_EACH_SUBRTX_PTR ( iter , array , loc , ALL ) { rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { rtx addr = XEXP ( * loc , <NUM_LIT> ) ; rtx * x = & addr ; while ( GET_CODE ( * x ) == PLUS ) { int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx u = XEXP ( * x , i ) ; if ( GET_CODE ( u ) == ZERO_EXTEND ) u = XEXP ( u , <NUM_LIT> ) ; if ( GET_CODE ( u ) == UNSPEC && XINT ( u , <NUM_LIT> ) == UNSPEC_TP ) { addr_space_t as = DEFAULT_TLS_SEG_REG ; * x = XEXP ( * x , <NUM_LIT> - i ) ;

* loc = replace_equiv_address_nv ( * loc , addr , true ) ;


<s> int InstrSizeDiff = - TII -> getInstSizeInBytes ( OldBranch ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NextMBB = & * std :: next ( MBB ) ; assert ( MBB -> isSuccessor ( NextMBB ) && <STR_LIT> ) ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( MI -> getOperand ( <NUM_LIT> ) ) ; TII -> reverseBranchCondition ( Cond ) ; MI = BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( NextMBB ) . add ( Cond [ <NUM_LIT> ] ) ; InstrSizeDiff += TII -> getInstSizeInBytes ( * MI ) ; ++ MI ; } MI = BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) ; InstrSizeDiff += TII -> getInstSizeInBytes ( * MI ) ; OldBranch . eraseFromParent ( ) ; for ( int i = MBB -> getNumber ( ) + <NUM_LIT> , e = BlockOffsets . size ( ) ; i < e ; ++ i ) { BlockOffsets [ i ] += InstrSizeDiff ; } MBBStartOffset += InstrSizeDiff ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getIndirectAddrRegClass ( ) const {


<s> return StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , <STR_LIT> ) ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedLoad ( Node ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOp ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; }

SDNode * ResNode = SelectCode ( Node ) ;


<s> bool Result = MIB . constrainAllUses ( TII , TRI , RBI ) ; if ( ResVReg . isValid ( ) && ResVReg != MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , ResVReg ) . addUse ( MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_BitfieldDescriptor ) ; Op -> Bitfield . LSB = LSB ;


<s> FunctionPass * llvm :: create<ISA_LIT>MIPeepholeOptPass ( ) {


<s> if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; } else { Base = N . getOperand ( <NUM_LIT> ) ; } return true ; } else if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { assert ( ! cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) && <STR_LIT> ) ; Disp = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; assert ( Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> || Disp . getOpcode ( ) == <STR_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; return true ; } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) ) { APInt LHSKnownZero , LHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( <NUM_LIT> ) , APInt :: getAllOnesValue ( N . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( ( int ) imm & <NUM_LIT> , <STR_LIT> ) ;


<s> TREE_STATIC ( decl ) = <NUM_LIT> ; if ( USE_HIDDEN_LINKONCE && ! TARGET_XCOFF ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; ASM_WEAKEN_DECL ( asm_out_file , decl , name , <NUM_LIT> ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ;

targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ;


<s> return TokError ( Str ) ; } createSysAlias ( AT -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> ) { const <STR_LIT> * TLBI = <STR_LIT> ( Op ) ; if ( ! TLBI ) return TokError ( <STR_LIT> ) ; else if ( ! TLBI -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( <STR_LIT> + std :: string ( TLBI -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( TLBI -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str ) ; } createSysAlias ( TLBI -> Encoding , Operands , S ) ; } else if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { const <STR_LIT> * PRCTX = <STR_LIT> ( Op ) ; if ( ! PRCTX ) return TokError ( <STR_LIT> ) ; else if ( ! PRCTX -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) { std :: string Str ( Mnemonic . upper ( ) + std :: string ( PRCTX -> Name ) + <STR_LIT> ) ; setRequiredFeatureString ( PRCTX -> getRequiredFeatures ( ) , Str ) ; return TokError ( Str ) ; } uint16_t PRCTX_Op2 = Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : Mnemonic == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; assert ( PRCTX_Op2 && <STR_LIT> ) ; createSysAlias ( PRCTX -> Encoding << <NUM_LIT> | PRCTX_Op2 , Operands , S ) ; } Lex ( ) ; bool ExpectRegister = ( Op . lower ( ) . find ( <STR_LIT> ) == StringRef :: npos ) ; bool HasRegister = false ; if ( parseOptionalToken ( AsmToken :: Comma ) ) {

if ( Tok . isNot ( AsmToken :: Identifier ) || parseRegister ( Operands ) ) return TokError ( <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && Subtarget . hasSSE2 ( ) ) { PM . add ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; ShouldPrint = true ; } if ( Subtarget . hasAVX ( ) && UseVZeroUpper ) {

PM . add ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ;


<s> Result . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>FrameLowering :: needsSPWriteback ( const MachineFunction & MF , const MachineFrameInfo & MFI ) const {


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseOptionalOpr ( OperandVector & Operands ) { OperandMatchResultTy res ; for ( const OptionalOperand & Op : <ISA_LIT>OptionalOperandTable ) { if ( Op . IsBit ) { res = parseNamedBit ( Op . Name , Operands , Op . Type ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyOMod<ISA_LIT> ) { res = parseOModOperand ( Operands ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTySdwaDstSel || Op . Type == <ISA_LIT>Operand :: ImmTySdwaSrc0Sel || Op . Type == <ISA_LIT>Operand :: ImmTySdwaSrc1Sel ) { res = parseSDWASel ( Operands , Op . Name , Op . Type ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTySdwaDstUnused ) { res = parseSDWADstUnused ( Operands ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyOpSel || Op . Type == <ISA_LIT>Operand :: ImmTyOpSelHi || Op . Type == <ISA_LIT>Operand :: ImmTyNegLo || Op . Type == <ISA_LIT>Operand :: ImmTyNegHi ) { res = parseOperandArrayWithPrefix ( Op . Name , Operands , Op . Type , Op . ConvertResult ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyDim ) { res = parseDim ( Operands ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyCPol ) { res = parseCPol ( Operands ) ; } else { res = parseIntWithPrefix ( Op . Name , Operands , Op . Type , Op . ConvertResult ) ;

if ( Op . Type == <ISA_LIT>Operand :: ImmTyBLGP && res == MatchOperand_NoMatch ) {


<s> if ( fillGenericConstant ( DL , CDA -> getElementAsConstant ( i ) , Vals , Offset ) == false ) return false ; Offset += DL . getTypeAllocSize ( CDA -> getElementAsConstant ( i ) -> getType ( ) ) ; } return true ;


<s> static void nios2_emit_stack_limit_check ( int size ) { rtx sum = NULL_RTX ; if ( GET_CODE ( stack_limit_rtx ) == SYMBOL_REF ) { sum = gen_rtx_REG ( Pmode , TEMP_REG_NUM ) ; emit_move_insn ( sum , plus_constant ( Pmode , stack_limit_rtx , size ) ) ; } else if ( ! REG_P ( stack_limit_rtx ) ) sorry ( <STR_LIT> ) ;

else if ( size == <NUM_LIT> ) sum = stack_limit_rtx ;


<s> return isStoreToStackSlot ( MI , FrameIndex ) ;


<s> ThumbMCInstrAnalysis ( const MCInstrInfo * Info ) : <ISA_LIT>MCInstrAnalysis ( Info ) {


<s> MCInst TmpInst ; HasLiteral = false ; const auto SavedBytes = Bytes ;

if ( decodeInstruction ( Table , TmpInst , Inst , Address , this , STI ) ) {


<s> if ( lowerIntrinsics ( M ) ) return PreservedAnalyses :: none ( ) ; return PreservedAnalyses :: all ( ) ;


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ;


<s> const MachineOperand * Src2 = TII -> getNamedOperand ( MI , AMDGPU :: OpName :: src2 ) ; if ( Src2 ) return false ; const MachineOperand * Src1 = TII -> getNamedOperand ( MI , AMDGPU :: OpName :: src1 ) ; const MachineOperand * Src1Mod = TII -> getNamedOperand ( MI , AMDGPU :: OpName :: src1_modifiers ) ; if ( Src1 && ( ! isVGPR ( Src1 , TRI , MRI ) || ( Src1Mod && Src1Mod -> getImm ( ) != <NUM_LIT> ) ) ) return false ;

const MachineOperand * Src0Mod = TII -> getNamedOperand ( MI , AMDGPU :: OpName :: src0_modifiers ) ;


<s> return isConstantImm ( ) && isInt < Bits > ( getConstantImm ( ) - Offset ) ;


<s> unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; break ; } case CmpInst :: ICMP_NE : { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( <STR_LIT> ) . addReg ( TempReg ) ; break ; } case CmpInst :: ICMP_UGT : { emitInst ( <STR_LIT> , ResultReg ) . addReg ( RightReg ) . addReg ( LeftReg ) ; break ; } case CmpInst :: ICMP_ULT : { emitInst ( <STR_LIT> , ResultReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; break ; } case CmpInst :: ICMP_UGE : { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; break ; } case CmpInst :: ICMP_ULE : { unsigned TempReg = createResultReg ( & <STR_LIT> ) ; emitInst ( <STR_LIT> , TempReg ) . addReg ( RightReg ) . addReg ( LeftReg ) ; emitInst ( <STR_LIT> , ResultReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; break ; } case CmpInst :: ICMP_SGT : { emitInst ( <STR_LIT> , ResultReg ) . addReg ( RightReg ) . addReg ( LeftReg ) ; break ; } case CmpInst :: ICMP_SLT : { emitInst ( <STR_LIT> , ResultReg ) . addReg ( LeftReg ) . addReg ( RightReg ) ; break ;


<s> case <STR_LIT> : { return allocateCCRegs ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , & <STR_LIT> , <NUM_LIT> ) ; } default :


<s> SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned Opc = Cond . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( Cond . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) ) {

if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Cond -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ;


<s> static bool tilepro_legitimate_address_p ( machine_mode ARG_UNUSED ( mode ) , rtx x , bool strict ) { if ( GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; switch ( GET_CODE ( x ) ) { case POST_INC : case POST_DEC : if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) return false ; x = XEXP ( x , <NUM_LIT> ) ; break ; case POST_MODIFY : if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) return false ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != PLUS ) return false ; if ( ! rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) return false ; if ( ! satisfies_constraint_I ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) return false ; x = XEXP ( x , <NUM_LIT> ) ; break ; case REG : break ;


<s> return ( ShiftOpc ) ( Op & <NUM_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createExpr ( getTLSReg ( ) ) ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

AU . addRequired < DominatorTreeWrapperPass > ( ) ;


<s> StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; SDValue Chain = Store -> getChain ( ) ; if ( ( Store -> getAddressSpace ( ) == <STR_LIT> || Store -> getAddressSpace ( ) == <STR_LIT> ) && Store -> getValue ( ) . getValueType ( ) . isVector ( ) ) { return SplitVectorStore ( Op , DAG ) ; } EVT MemVT = Store -> getMemoryVT ( ) ; if ( Store -> getAddressSpace ( ) == <STR_LIT> && MemVT . bitsLT ( <STR_LIT> ) ) { unsigned Mask = <NUM_LIT> ; if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } SDValue BasePtr = Store -> getBasePtr ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;

SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; }

return DAG . getFrameIndex ( ReturnAddrIndex , getPointerTy ( ) ) ;


<s> case <NUM_LIT> : DecodedValue = - <NUM_LIT> ; break ; default : DecodedValue = SignExtend32 < <NUM_LIT> > ( Insn ) ; break ; }

Inst . addOperand ( MCOperand :: CreateImm ( DecodedValue * <NUM_LIT> ) ) ;


LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << IterCnt << '\n' ; ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI ) : MCInstPrinter ( MAI ) {


<s> mode = GET_MODE ( mem ) ; addr = XEXP ( mem , <NUM_LIT> ) ; gcc_assert ( register_operand ( addr , DImode ) ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; if ( val != const0_rtx ) val = emit_insxl ( mode , val , addr ) ; wdst = gen_reg_rtx ( DImode ) ;

if ( mode == QImode ) gen = gen_atomic_exchangeqi_1 ;


<s> if ( GOAlign > Csect -> getAlignment ( ) ) Csect -> setAlignment ( GOAlign ) ; } ; for ( const auto & G : M . globals ( ) ) { if ( isSpecialLLVMGlobalArrayToSkip ( & G ) ) continue ; if ( isSpecialLLVMGlobalArrayForStaticInit ( & G ) ) { if ( FormatIndicatorAndUniqueModId . empty ( ) ) { std :: string UniqueModuleId = getUniqueModuleId ( & M ) ; if ( UniqueModuleId . compare ( <STR_LIT> ) != <NUM_LIT> ) FormatIndicatorAndUniqueModId = <STR_LIT> + UniqueModuleId . substr ( <NUM_LIT> ) ; else FormatIndicatorAndUniqueModId = <STR_LIT> + llvm :: itostr ( sys :: Process :: getProcessId ( ) ) + <STR_LIT> + llvm :: itostr ( time ( nullptr ) ) ; } emitSpecialLLVMGlobal ( & G ) ;


<s> unsigned <ISA_LIT>CodeEmitter :: getMachineSoImmOpValue ( unsigned SoImm ) { int SoImmVal = <STR_LIT> ( SoImm ) ; assert ( SoImmVal != - <NUM_LIT> && <STR_LIT> ) ; unsigned Binary = ( <STR_LIT> ( ( unsigned ) SoImmVal ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= <STR_LIT> ( ( unsigned ) SoImmVal ) ; return Binary ;


<s> switch_to_section ( darwin_sections [ picbase_thunk_section ] ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; DECL_WEAK ( decl ) = <NUM_LIT> ; } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; }


<s> printNamedBit ( MI , OpNo , O , <STR_LIT> ) ;


<s> if ( flag_pic ) x = legitimize_pic_address ( oldx , mode , NULL_RTX ) ; if ( TARGET_SHMEDIA ) return x ; if ( ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && mode == DFmode ) || ( TARGET_SH2E && mode == SFmode ) ) return x ; if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && BASE_REGISTER_RTX_P ( XEXP ( x , <NUM_LIT> ) ) ) { struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ; if ( adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { rtx sum = expand_binop ( Pmode , add_optab , XEXP ( x , <NUM_LIT> ) , adj . offset_adjust , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; return gen_rtx_PLUS ( Pmode , sum , adj . mov_disp ) ; } } return x ;


<s> } else if ( InputID == <STR_LIT> ) { LI -> getImplicitArgPtr ( InputReg , MRI , MIRBuilder ) ; } else { MIRBuilder . buildUndef ( InputReg ) ; } if ( OutgoingArg -> isRegister ( ) ) { ArgRegs . emplace_back ( OutgoingArg -> getRegister ( ) , InputReg ) ; if ( ! CCInfo . AllocateReg ( OutgoingArg -> getRegister ( ) ) ) report_fatal_error ( <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } const ArgDescriptor * OutgoingArg ; const TargetRegisterClass * ArgRC ; LLT ArgTy ; std :: tie ( OutgoingArg , ArgRC , ArgTy ) = CalleeArgInfo -> getPreloadedValue ( <STR_LIT> ) ; if ( ! OutgoingArg ) std :: tie ( OutgoingArg , ArgRC , ArgTy ) = CalleeArgInfo -> getPreloadedValue ( <STR_LIT> ) ; if ( ! OutgoingArg ) std :: tie ( OutgoingArg , ArgRC , ArgTy ) = CalleeArgInfo -> getPreloadedValue ( <STR_LIT> ) ; if ( ! OutgoingArg ) return false ; auto WorkitemIDX = CallerArgInfo . getPreloadedValue ( <STR_LIT> ) ; auto WorkitemIDY = CallerArgInfo . getPreloadedValue ( <STR_LIT> ) ; auto WorkitemIDZ = CallerArgInfo . getPreloadedValue ( <STR_LIT> ) ; const ArgDescriptor * IncomingArgX = std :: get < <NUM_LIT> > ( WorkitemIDX ) ; const ArgDescriptor * IncomingArgY = std :: get < <NUM_LIT> > ( WorkitemIDY ) ; const ArgDescriptor * IncomingArgZ = std :: get < <NUM_LIT> > ( WorkitemIDZ ) ; const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; const bool NeedWorkItemIDX = ! Info . CB -> hasFnAttr ( <STR_LIT> ) ; const bool NeedWorkItemIDY = ! Info . CB -> hasFnAttr ( <STR_LIT> ) ; const bool NeedWorkItemIDZ = ! Info . CB -> hasFnAttr ( <STR_LIT> ) ; Register InputReg ; if ( IncomingArgX && ! IncomingArgX -> isMasked ( ) && CalleeArgInfo -> WorkItemIDX && NeedWorkItemIDX ) { InputReg = MRI . createGenericVirtualRegister ( S32 ) ; LI -> loadInputValue ( InputReg , MIRBuilder , IncomingArgX , std :: get < <NUM_LIT> > ( WorkitemIDX ) , std :: get < <NUM_LIT> > ( WorkitemIDX ) ) ;


<s> unsigned Bits = Ty . getSizeInBits ( ) ;

unsigned Pow2Bits = <NUM_LIT> << Log2_32_Ceil ( Bits ) ;


<s> GetJumpTableSymbol ( const MachineOperand & MO ) const { SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << Printer . MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { default : return false ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = true ; Info . align = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = true ; Info . align = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; if ( Intrinsic == <STR_LIT> ) Info . memVT = getValueType ( I . getType ( ) ) ; else if ( Intrinsic == <STR_LIT> ) Info . memVT = getValueType ( I . getType ( ) ) ; else Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ;


<s> unsigned DecodedVal = <NUM_LIT> - Val ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DecodedVal > <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> if ( getParser ( ) . parseAbsoluteExpression ( Tmp ) ) { return true ; } Ret = static_cast < uint32_t > ( Tmp ) ; return false ;


<s> if ( ( GET_CODE ( op0 ) == NEG || GET_CODE ( op0 ) == ABS ) && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) return CCAPmode ; if ( GET_CODE ( op0 ) == PLUS && GET_CODE ( XEXP ( op0 , <NUM_LIT> ) ) == CONST_INT && CONST_OK_FOR_K ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ) ) return CCAPmode ; if ( ( GET_CODE ( op0 ) == PLUS || GET_CODE ( op0 ) == MINUS || GET_CODE ( op1 ) == NEG ) && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) return CCLmode ; if ( GET_CODE ( op0 ) == AND ) { enum machine_mode ccmode ; ccmode = s390_tm_ccmode ( XEXP ( op0 , <NUM_LIT> ) , op1 , <NUM_LIT> ) ; if ( ccmode != VOIDmode ) { return ccmode == CCTmode ? CCZmode : ccmode ; } } if ( register_operand ( op0 , HImode ) && GET_CODE ( op1 ) == CONST_INT && ( INTVAL ( op1 ) == - <NUM_LIT> || INTVAL ( op1 ) == <NUM_LIT> ) ) return CCT3mode ; if ( register_operand ( op0 , QImode ) && GET_CODE ( op1 ) == CONST_INT && ( INTVAL ( op1 ) == - <NUM_LIT> || INTVAL ( op1 ) == <NUM_LIT> ) ) return CCT3mode ; return CCZmode ; case LE : case LT : case GE : case GT : if ( ( GET_CODE ( op0 ) == NEG || GET_CODE ( op0 ) == ABS ) && GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) return CCAPmode ; if ( GET_CODE ( op0 ) == PLUS && GET_CODE ( XEXP ( op0 , <NUM_LIT> ) ) == CONST_INT && CONST_OK_FOR_K ( INTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ) ) { if ( INTVAL ( XEXP ( ( op0 ) , <NUM_LIT> ) ) < <NUM_LIT> ) return CCANmode ; else return CCAPmode ; } case UNORDERED : case ORDERED : case UNEQ : case UNLE : case UNLT : case UNGE : case UNGT :


<s> I != E ; ++ I ) { if ( Offset < I -> Offset ) { MemOps . insert ( I , MemOpQueueEntry ( Offset , Reg , isKill , Position , MBBI ) ) ; ++ NumMemOps ; Advance = true ; break ; } else if ( Offset == I -> Offset ) { break ; } } } } } } if ( MBBI -> isDebugValue ( ) ) { ++ MBBI ; if ( MBBI == E ) TryMerge = true ; } else if ( Advance ) { ++ Position ; ++ MBBI ; if ( MBBI == E ) TryMerge = true ; } else TryMerge = true ; if ( TryMerge ) { if ( NumMemOps > <NUM_LIT> ) { AdvanceRS ( MBB , MemOps ) ; unsigned Scratch = RS -> FindUnusedReg ( <STR_LIT> ) ; RS -> forward ( prior ( MBBI ) ) ; Merges . clear ( ) ; MergeLDR_STR ( MBB , <NUM_LIT> , CurrBase , CurrOpc , CurrSize , CurrPred , CurrPredReg , Scratch , MemOps , Merges ) ; for ( unsigned i = <NUM_LIT> , e = Merges . size ( ) ; i < e ; ++ i ) if ( MergeBaseUpdateLSMultiple ( MBB , Merges [ i ] , Advance , MBBI ) ) ++ NumMerges ; NumMerges += Merges . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumMemOps ; ++ i ) if ( ! MemOps [ i ] . Merged ) if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ i ] . MBBI , TII , Advance , MBBI ) ) ++ NumMerges ; RS -> skipTo ( prior ( MBBI ) ) ; } else if ( NumMemOps == <NUM_LIT> ) { if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ <NUM_LIT> ] . MBBI , TII , Advance , MBBI ) ) { ++ NumMerges ; RS -> forward ( prior ( MBBI ) ) ; } } CurrBase = <NUM_LIT> ; CurrOpc = - <NUM_LIT> ; CurrSize = <NUM_LIT> ; CurrPred = <STR_LIT> ; CurrPredReg = <NUM_LIT> ; if ( NumMemOps ) { MemOps . clear ( ) ; NumMemOps = <NUM_LIT> ; } if ( ! Advance && ! isMemOp && MBBI != E ) { ++ Position ; ++ MBBI ;


<s> bool <ISA_LIT>TTIImpl :: isLegalToVectorizeStoreChain ( unsigned ChainSizeInBytes , unsigned Alignment , unsigned AddrSpace ) const {


<s> } break ; case <STR_LIT> : case <STR_LIT> : ++ NumLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : ++ NumSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } break ; case <STR_LIT> : ++ NumVLDMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } break ; case <STR_LIT> : ++ NumVSTMGened ; switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI ) : MCInstPrinter ( MAI ) {


<s> std :: tie ( CondReg , Inverted ) = getCondOrInverseInReg ( TestMBB , TestPos , TestLoc , Cond , CondRegs ) ; MachineBasicBlock & JmpMBB = * JmpI . getParent ( ) ; insertTest ( JmpMBB , JmpI . getIterator ( ) , JmpI . getDebugLoc ( ) , CondReg ) ;

JmpI . getOperand ( <NUM_LIT> ) . setImm ( Inverted ? <STR_LIT> : <STR_LIT> ) ;


<s> break ; } if ( CanDown && DU . Defs [ SR1 ] ) CanDown = false ; if ( CanUp && DU . Defs [ SR2 ] ) CanUp = false ; } if ( Failure || ( ! CanUp && ! CanDown ) ) continue ; MachineOperand * SrcT = ( MinX == CI . TrueX ) ? Src1 : Src2 ; MachineOperand * SrcF = ( MinX == CI . FalseX ) ? Src1 : Src2 ; MachineBasicBlock :: iterator At = CanDown ? Def2 : Def1 ; ML . push_back ( MuxInfo ( At , DR , PR , SrcT , SrcF , Def1 , Def2 ) ) ; } for ( unsigned I = <NUM_LIT> , N = ML . size ( ) ; I < N ; ++ I ) { MuxInfo & MX = ML [ I ] ; MachineBasicBlock & B = * MX . At -> getParent ( ) ; DebugLoc DL = MX . At -> getDebugLoc ( ) ; unsigned MxOpc = getMuxOpcode ( * MX . SrcT , * MX . SrcF ) ; if ( ! MxOpc ) continue ; BuildMI ( B , MX . At , DL , HII -> get ( MxOpc ) , MX . DefR ) . addReg ( MX . PredR ) . addOperand ( * MX . SrcT ) . addOperand ( * MX . SrcF ) ; B . erase ( MX . Def1 ) ; B . erase ( MX . Def2 ) ; Changed = true ; } return Changed ;


<s> static SDValue splitVectorStore ( StoreSDNode * Store , SelectionDAG & DAG ) { SDValue StoredVal = Store -> getValue ( ) ; assert ( ( StoredVal . getValueType ( ) . is256BitVector ( ) || StoredVal . getValueType ( ) . is512BitVector ( ) ) && <STR_LIT> ) ; if ( ! Store -> isSimple ( ) ) return SDValue ( ) ; SDLoc DL ( Store ) ; SDValue Value0 , Value1 ; std :: tie ( Value0 , Value1 ) = splitVector ( StoredVal , DAG , DL ) ; unsigned HalfOffset = Value0 . getValueType ( ) . getStoreSize ( ) ; SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , TypeSize :: Fixed ( HalfOffset ) , DL ) ; SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Store -> getOriginalAlign ( ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ch1 = DAG . getStore ( Store -> getChain ( ) , DL , Value1 , Ptr1 , Store -> getPointerInfo ( ) . getWithOffset ( HalfOffset ) , Store -> getOriginalAlign ( ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ch0 , Ch1 ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T ) : TargetAsmBackend ( ) {


<s> unsigned Pos = Left ? i + Shift : i ; unsigned Low = Left ? i : i + Shift ; unsigned Len = Scale - Shift ; if ( ! isSequentialOrUndefInRange ( Mask , Pos , Len , Low + MaskOffset ) ) return - <NUM_LIT> ; } int ShiftEltBits = ScalarSizeInBits * Scale ; bool ByteShift = ShiftEltBits > <NUM_LIT> ; Opcode = Left ? ( ByteShift ? <STR_LIT> : <STR_LIT> ) : ( ByteShift ? <STR_LIT> : <STR_LIT> ) ; int ShiftAmt = Shift * ScalarSizeInBits / ( ByteShift ? <NUM_LIT> : <NUM_LIT> ) ; Scale = ByteShift ? Scale / <NUM_LIT> : Scale ; MVT ShiftSVT = <STR_LIT> ( ScalarSizeInBits * Scale ) ; ShiftVT = ByteShift ? <STR_LIT> ( <STR_LIT> , SizeInBits / <NUM_LIT> ) : <STR_LIT> ( ShiftSVT , Size / Scale ) ; return ( int ) ShiftAmt ; } ; unsigned MaxWidth = ( ( SizeInBits == <NUM_LIT> ) && ! Subtarget . hasBWI ( ) ? <NUM_LIT> : <NUM_LIT> ) ; for ( int Scale = <NUM_LIT> ; Scale * ScalarSizeInBits <= MaxWidth ; Scale *= <NUM_LIT> ) for ( int Shift = <NUM_LIT> ; Shift != Scale ; ++ Shift ) for ( bool Left : { true , false } ) if ( CheckZeros ( Shift , Scale , Left ) ) { int ShiftAmt = MatchShift ( Shift , Scale , Left ) ; if ( <NUM_LIT> < ShiftAmt ) return ShiftAmt ;


<s> <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; if ( ! FPSI ) { int FPOffset = <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( Is<ISA_LIT>64 , isMachoABI ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset ) ; FI -> setFramePointerSaveIndex ( FPSI ) ;


<s> bool <ISA_LIT>Subtarget :: hasBooleanRegs ( ) const { return BooleanRegs ;


<s> return ( ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] && ! fixed_regs [ regno ] ) || ( regno == RETURN_ADDR_REGNO && ( df_regs_ever_live_p ( regno ) || ! crtl -> is_leaf ) ) || ( regno == PIC_OFFSET_TABLE_REGNUM && must_reload_pic_reg_p ( ) ) ) ;


<s> for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { Function & F = * I ; if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) ) FuncsToClone . push_back ( & F ) ; }


<s> return new <ISA_LIT>LowerControlFlow ( ) ;


<s> if ( crtl -> is_leaf && ! sh_pr_n_sets ( ) ) return hard_reg ; else return gen_frame_mem ( Pmode , return_address_pointer_rtx ) ; } return NULL_RTX ;


<s> CounterPropagateAddr ( * Clause . first , CfCount ) ; MachineBasicBlock * BB = Clause . first -> getParent ( ) ; BuildMI ( BB , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( CfCount ) ; for ( unsigned i = <NUM_LIT> , e = Clause . second . size ( ) ; i < e ; ++ i ) { BB -> splice ( InsertPos , BB , Clause . second [ i ] ) ; }

CfCount += <NUM_LIT> * Clause . second . size ( ) ;


<s> if ( Kind != k_Memory ) return false ; if ( Memory . BaseRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . BaseRegNum ) ) return false ;

if ( Memory . OffsetRegNum && ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Memory . OffsetRegNum ) ) return false ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> unsigned int i , nelt , which ; bool ret ; d . vmode = vmode ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = true ; memcpy ( d . perm , sel , nelt ) ; for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) {


<s> int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; Out . EmitBundleLock ( false ) ; EmitBICMask ( Out , Reg , Pred , <NUM_LIT> ) ;

Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ;

MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


<s> ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ;

MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . add ( Src ) ;


<s> case TargetTransformInfo :: CacheLevel :: L1D : return <NUM_LIT> * <NUM_LIT> ; case TargetTransformInfo :: CacheLevel :: L2D : return <NUM_LIT> * <NUM_LIT> ; }


<s> } if ( isSEHInstruction ( MI ) ) return true ; auto Next = std :: next ( MI . getIterator ( ) ) ; return Next != MBB -> end ( ) && Next -> isCFIInstruction ( ) ;


<s> virtual BitVector getReservedRegs ( const MachineFunction & MF ) const { assert ( ! <STR_LIT> ) ; return BitVector ( ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emit<ISA_LIT>AbiFlags ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ;

MCContext & Context = MCA . getContext ( ) ;


<s> void <ISA_LIT>Cloner :: reportError ( string ErrorString , vector < string > & Values ) { unsigned ValCount = Values . size ( ) ; string TargetString ; for ( unsigned i = <NUM_LIT> ; i < ValCount ; ++ i ) { TargetString = <STR_LIT> ; TargetString += ( ( char ) i + '0' ) ; ErrorString . replace ( ErrorString . find ( TargetString ) , TargetString . length ( ) , Values [ i ] ) ;


<s> got_entry = getTarget ( ) . getGOT ( ) . create ( ) ; getTarget ( ) . getGOT ( ) . create ( ) -> setValue ( <NUM_LIT> ) ; helper_DynRel_init ( NULL , * got_entry , <NUM_LIT> , llvm :: ELF :: R_386_TLS_DTPMOD32 , * this ) ;


<s> unsigned VisitedIndex = <NUM_LIT> ; while ( VisitedIndex < PHIs . size ( ) ) { MachineInstr * VisitedPHI = PHIs [ VisitedIndex ] ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = VisitedPHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register RegOp = VisitedPHI -> getOperand ( PHIOp ) . getReg ( ) ;

if ( ! Register :: isVirtualRegister ( RegOp ) ) return false ;


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) {

TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target , create<ISA_LIT>Disassembler ) ;


<s> unsigned i = SwzCandidate [ Depth ] ; for ( ; i < <NUM_LIT> ; i ++ ) { SwzCandidate [ Depth ] = ( R600InstrInfo :: BankSwizzle ) i ; if ( recursiveFitsFPLimitation ( IGSrcs , SwzCandidate , Depth + <NUM_LIT> ) ) return true ; } SwzCandidate [ Depth ] = R600InstrInfo :: ALU_VEC_012 ; return false ;


<s> switch ( Opcode ) { default : return NULL ; case <STR_LIT> : return <STR_LIT> ;


<s> virtual void EmitBytes ( StringRef Data ) { EmitDataMappingSymbol ( ) ; MCELFStreamer :: EmitBytes ( Data ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> <STR_LIT> <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) {


<s> static unsigned selectSGPRVectorRegClassID ( unsigned NumVectorElts ) { switch ( NumVectorElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> <ISA_LIT>CA53ErratumStub :: <ISA_LIT>CA53ErratumStub ( const uint32_t * pData , size_t pSize , const char * pName , const_fixup_iterator pBegin , const_fixup_iterator pEnd ) : m_pData ( pData ) , m_Name ( pName ) , m_Size ( pSize ) { for ( const_fixup_iterator it = pBegin , ie = pEnd ; it != ie ; ++ it ) { addFixup ( * * it ) ;


<s> MI -> getOperand ( <NUM_LIT> ) . setImm ( Control ) ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) { if ( ( Control & GPRControlBit [ I ] ) == <NUM_LIT> ) { unsigned Reg = <STR_LIT> [ I ] ; MI -> addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; } } if ( ! NoFloat && ( Control & <NUM_LIT> ) != <NUM_LIT> ) { for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) { unsigned Reg = <STR_LIT> [ I ] ; MI -> addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; } }


<s> switch ( ObjectVT . getSimpleVT ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( firstGPR < <NUM_LIT> ) NeededGPRs = <NUM_LIT> ; else NeededStackSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( firstGPR < <NUM_LIT> ) NeededGPRs = <NUM_LIT> ; else if ( firstGPR == <NUM_LIT> ) { NeededGPRs = <NUM_LIT> ;


<s> const MCExpr * Expr = NULL ; if ( DispOp . isImm ( ) ) { if ( FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 && FixupKind != FK_PCRel_4 ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } Expr = MCConstantExpr :: Create ( DispOp . getImm ( ) , Ctx ) ; } else { Expr = DispOp . getExpr ( ) ; } if ( ( FixupKind == FK_Data_4 || FixupKind == MCFixupKind ( <STR_LIT> ) ) && StartsWithGlobalOffsetTable ( Expr ) ) { assert ( ImmOffset == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ;


<s> MachineInstr * AndN2 = BuildMI ( MBB , & MI , DL , TII -> get ( Andn2TermOpc ) , Exec ) . addReg ( Exec ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MachineInstr * Branch = BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( LIS ) { LIS -> ReplaceMachineInstrInMaps ( MI , * AndN2 ) ; LIS -> InsertMachineInstrInMaps ( * Branch ) ;


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;

else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> while ( ! Q . empty ( ) ) { if ( Count ++ >= Limit ) break ; Instruction * U = dyn_cast < Instruction > ( Q . pop_front_val ( ) ) ; if ( ! U || U -> getParent ( ) || ! C . Used . count ( U ) ) continue ; bool Changed = false ; for ( Rule & R : Rules ) { Value * W = R ( U , C . Ctx ) ; if ( ! W ) continue ; Changed = true ; C . record ( W ) ; C . replace ( U , W ) ; Q . push_back ( C . Root ) ; break ; } if ( ! Changed ) {

for ( Value * Op : U -> operands ( ) ) Q . push_back ( Op ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> uint8_t llvmRegnums [ ] = { ALL_REGS <NUM_LIT> } ; uint8_t llvmRegnum = llvmRegnums [ reg ] ;

mcInst . addOperand ( MCOperand :: createReg ( llvmRegnum ) ) ;


<s> MBBs . clear ( ) ; MBBs . resize ( NumBlocks ) ; Terminators . clear ( ) ; Terminators . reserve ( NumBlocks ) ; BlockPosition Position ( Log2 ( MF -> getAlignment ( ) ) ) ; for ( unsigned I = <NUM_LIT> ; I < NumBlocks ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; MBBInfo & Block = MBBs [ I ] ; Block . Alignment = MBB -> getAlignment ( ) ; MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; MachineBasicBlock :: iterator End = MBB -> end ( ) ; while ( MI != End && ! MI -> isTerminator ( ) ) { Block . Size += getInstSizeInBytes ( * MI , TII ) ; ++ MI ;


<s> SDLoc DL ( N ) ; EVT VT8Bit = VT . is64BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N0 ) ;

SDValue N2 = DAG . getNode ( <STR_LIT> , DL , VT8Bit , N1 ) ;


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( IsVarArg ) report_fatal_error ( <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . getLocVT ( ) == Subtarget . getXLenVT ( ) && <STR_LIT> ) ; SDValue ArgValue ; if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) {

InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ;


<s> unsigned Rn = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rd == Rm || Rm == Rn || Rd == Rn ) return MCDisassembler :: Fail ; if ( ! DecodeGPR64commonRegisterClass ( Inst , Rd , Addr , Decoder ) || ! DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) || ! DecodeGPR64commonRegisterClass ( Inst , Rd , Addr , Decoder ) || ! DecodeGPR64RegisterClass ( Inst , Rn , Addr , Decoder ) || ! DecodeGPR64RegisterClass ( Inst , Rm , Addr , Decoder ) ) return MCDisassembler :: Fail ; return MCDisassembler :: Success ;


<s> static bool m68k_save_reg ( unsigned int regno , bool interrupt_handler ) { if ( flag_pic && regno == PIC_REG ) { if ( crtl -> saves_all_registers ) return true ; if ( crtl -> uses_pic_offset_table ) return true ; if ( crtl -> uses_const_pool ) return true ; } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; ; i ++ ) {

unsigned int test = EH_RETURN_DATA_REGNO ( i ) ;


<s> SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Identifier ; AsmToken Tok = getLexer ( ) . getTok ( ) ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; if ( Identifier . consume_back ( <STR_LIT> ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; if ( Sym -> isVariable ( ) ) { const MCExpr * V = Sym -> getVariableValue ( false ) ; if ( ! isa < MCSymbolRefExpr > ( V ) ) { getLexer ( ) . UnLex ( Tok ) ; return MatchOperand_NoMatch ; } Res = V ; } else Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; MCBinaryExpr :: Opcode Opcode ; switch ( getLexer ( ) . getKind ( ) ) { default : Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success ; case AsmToken :: Plus : Opcode = MCBinaryExpr :: Add ; break ; case AsmToken :: Minus : Opcode = MCBinaryExpr :: Sub ; break ; } const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success ;


<s> bool <ISA_LIT>65816DAGToDAGISel :: SelectAbs ( SDValue N , SDValue & R1 ) { <ISA_LIT>_LOG ( <STR_LIT> ) ; return false ;


<s> MCStreamer * S = llvm :: createAsmStreamer ( Ctx , OS , isVerboseAsm , useCFI , useDwarfDirectory , InstPrint , CE , TAB , ShowInst ) ;

new <ISA_LIT>TargetAsmStreamer ( * S , OS ) ;


<s> while ( MBB -> succ_size ( ) ) MBB -> removeSuccessor ( * MBB -> succ_begin ( ) ) ;


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : SelectMoveImmediate ( N ) ; return ; case <STR_LIT> : SelectConditionalBranch ( N ) ; return ; } SelectCode ( N ) ;


<s> const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( TRI -> getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ;

return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , VT ) ;


<s> bool loongarch_small_data_pattern_p ( rtx op ) { return loongarch_small_data_pattern_1 ( op ) ;


<s> <ISA_LIT>ConstantPoolSymbol :: <ISA_LIT>ConstantPoolSymbol ( Type * Ty , const char * S , unsigned PCAdjust , <STR_LIT> Modifier , bool AddCurrentAddress ) : <ISA_LIT>ConstantPoolValue ( Ty , <STR_LIT> , PCAdjust , Modifier , AddCurrentAddress ) , S ( strdup ( S ) ) {


<s> StringRef ( ReflectList [ i ] ) . split ( NameValList , ',' ) ; for ( unsigned j = <NUM_LIT> , ej = NameValList . size ( ) ; j != ej ; ++ j ) { SmallVector < StringRef , <NUM_LIT> > NameValPair ; NameValList [ j ] . split ( NameValPair , '=' ) ; assert ( NameValPair . size ( ) == <NUM_LIT> && <STR_LIT> ) ; std :: stringstream ValStream ( NameValPair [ <NUM_LIT> ] ) ; int Val ; ValStream >> Val ; assert ( ( ! ( ValStream . fail ( ) ) ) && <STR_LIT> ) ; VarMap [ NameValPair [ <NUM_LIT> ] ] = Val ;


<s> bool NextIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i + <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( ! ThisIsNonZero && ! NextIsNonZero ) continue ; SDValue Elt ; if ( ThisIsNonZero ) { if ( NumZero || NextIsNonZero ) Elt = DAG . getZExtOrTrunc ( Op . getOperand ( i ) , dl , <STR_LIT> ) ; else Elt = DAG . getAnyExtOrTrunc ( Op . getOperand ( i ) , dl , <STR_LIT> ) ; } if ( NextIsNonZero ) { SDValue NextElt = Op . getOperand ( i + <NUM_LIT> ) ; if ( i == <NUM_LIT> && NumZero ) NextElt = DAG . getZExtOrTrunc ( NextElt , dl , <STR_LIT> ) ; else NextElt = DAG . getAnyExtOrTrunc ( NextElt , dl , <STR_LIT> ) ; NextElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NextElt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( ThisIsNonZero ) Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NextElt , Elt ) ; else Elt = NextElt ; }


<s> CountValueType getType ( ) const { return Kind ;


<s> bool fit = INTVAL ( XEXP ( x , <NUM_LIT> ) ) <= MAX_LD_OFFSET ( mode ) ; if ( fit ) { if ( reg_equiv_address ( REGNO ( XEXP ( x , <NUM_LIT> ) ) ) != <NUM_LIT> ) { int regno = REGNO ( XEXP ( x , <NUM_LIT> ) ) ; rtx mem = mk_memloc ( x , regno ) ; push_reload ( XEXP ( mem , <NUM_LIT> ) , NULL_RTX , & XEXP ( mem , <NUM_LIT> ) , NULL , POINTER_REGS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ( enum reload_type ) addr_type ) ; if ( avr_log . legitimize_reload_address ) avr_edump ( <STR_LIT> , POINTER_REGS , XEXP ( mem , <NUM_LIT> ) , NULL_RTX ) ; push_reload ( mem , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_POINTER_REGS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; if ( avr_log . legitimize_reload_address ) avr_edump ( <STR_LIT> , BASE_POINTER_REGS , mem , NULL_RTX ) ; return x ; } } else if ( ! ( frame_pointer_needed && XEXP ( x , <NUM_LIT> ) == frame_pointer_rtx ) ) { push_reload ( x , NULL_RTX , px , NULL , POINTER_REGS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ;


<s> case CONST_INT : case CONST_WIDE_INT : if ( reg_class_subset_p ( GENERAL_REGS , rclass ) && legitimate_reload_constant_p ( op ) ) return GENERAL_REGS ; else if ( reg_class_subset_p ( ADDR_REGS , rclass ) && legitimate_reload_constant_p ( op ) ) return ADDR_REGS ; else if ( reg_class_subset_p ( FP_REGS , rclass ) && legitimate_reload_fp_constant_p ( op ) ) return FP_REGS ; else if ( reg_class_subset_p ( VEC_REGS , rclass ) && legitimate_reload_vector_constant_p ( op ) ) return VEC_REGS ; return NO_REGS ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> bool isSoloInstruction ( MachineInstr * MI ) override { if ( TII -> isVector ( * MI ) ) return true ;

if ( ! TII -> isALUInstr ( MI -> getOpcode ( ) ) ) return true ;


<s> if ( ! Modifier || strcmp ( Modifier , <STR_LIT> ) ) O << '#' ; O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isMemOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; uint64_t Offset = MO . getOffset ( ) ; if ( ! Modifier || strcmp ( Modifier , <STR_LIT> ) ) O << ( isMemOp ? '&' : '#' ) ; if ( Offset ) O << '(' << Offset << '+' ; O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; if ( Offset ) O << ')' ; return ; } case MachineOperand :: MO_ExternalSymbol : {


<s> bool <ISA_LIT>StoreWidening :: instrAliased ( InstrGroup & Stores , const MachineInstr * MI ) {

for ( auto & I : MI -> memoperands ( ) ) if ( instrAliased ( Stores , * I ) ) return true ;


<s> continue ; } if ( MFI . isVRegStackified ( OldReg ) ) { InsertPt = findStartOfTree ( MO , MRI , MFI ) ; continue ; } if ( MI . isInlineAsm ( ) ) { unsigned LocalId = getLocalId ( Reg2Local , CurLocal , OldReg ) ; MI . untieRegOperand ( MI . getOperandNo ( & MO ) ) ; MO . ChangeToImmediate ( LocalId ) ; continue ; } unsigned LocalId = getLocalId ( Reg2Local , CurLocal , OldReg ) ; const TargetRegisterClass * RC = MRI . getRegClass ( OldReg ) ; unsigned NewReg = MRI . createVirtualRegister ( RC ) ; unsigned Opc = getLocalGetOpcode ( RC ) ; InsertPt = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII -> get ( Opc ) , NewReg ) . addImm ( LocalId ) ; MO . setReg ( NewReg ) ; MFI . stackifyVReg ( NewReg ) ; Changed = true ; } if ( <STR_LIT> ( MI ) ) { MRI . replaceRegWith ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent ( ) ; Changed = true ; } } } MFI . setNumLocals ( CurLocal - MFI . getParams ( ) . size ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I < E ; ++ I ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( I ) ; auto RL = Reg2Local . find ( Reg ) ; if ( RL == Reg2Local . end ( ) || RL -> second < MFI . getParams ( ) . size ( ) ) continue ; MFI . setLocal ( RL -> second - MFI . getParams ( ) . size ( ) , typeForRegClass ( MRI . getRegClass ( Reg ) ) ) ; Changed = true ; } for ( const MachineBasicBlock & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { if ( MI . isDebugInstr ( ) || MI . isLabel ( ) ) continue ; for ( const MachineOperand & MO : MI . explicit_operands ( ) ) { assert ( ( ! MO . isReg ( ) || MRI . use_empty ( MO . getReg ( ) ) || MFI . isVRegStackified ( MO . getReg ( ) ) ) && <STR_LIT> ) ; } } }


<s> DiagnosticLineInfo * create<ISA_LIT>DiagLineInfo ( const mcld :: Target & pTarget , const std :: string & pTriple ) { return new DWARFLineInfo ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , Register Reg , EVT VT , const SDLoc & SL , bool RawReg ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ;

MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;


<s> static DecodeStatus decodeFLPMX ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { if ( decodeFRd ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> } } else if ( isRegisterStore ( * MI ) ) { int ValOpIdx = AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: val ) ; AMDGPU :: getNamedOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: dst ) ; unsigned RegIndex = MI -> getOperand ( RegOpIdx ) . getImm ( ) ; unsigned Channel = MI -> getOperand ( ChanOpIdx ) . getImm ( ) ; unsigned Address = calculateIndirectAddress ( RegIndex , Channel ) ; unsigned OffsetReg = MI -> getOperand ( OffsetOpIdx ) . getReg ( ) ; if ( OffsetReg == AMDGPU :: INDIRECT_BASE_ADDR ) { buildMovInstr ( MBB , MI , getIndirectAddrRegClass ( ) -> getRegister ( Address ) , MI -> getOperand ( ValOpIdx ) . getReg ( ) ) ; } else { buildIndirectWrite ( MBB , MI , MI -> getOperand ( ValOpIdx ) . getReg ( ) , calculateIndirectAddress ( RegIndex , Channel ) , OffsetReg ) ; } } else { return false ; } MBB -> erase ( MI ) ; return true ;


<s> if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || <STR_LIT> . contains ( DstReg , SrcReg ) || ( <STR_LIT> . contains ( DstReg ) && <STR_LIT> . contains ( SrcReg ) ) ) { Opc = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , get ( Opc ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; }


<s> if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } return <NUM_LIT> ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( new <ISA_LIT>ExecutionDepsFix ( ) ) ;

if ( UseVZeroUpper ) addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const uint32_t * RegMask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; if ( Subtarget -> is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( F -> getTarget ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TII -> getGlobalBaseReg ( F ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ;


<s> assert ( N -> getOpcode ( ) == <STR_LIT> ) ; if ( N -> getNumOperands ( ) != <NUM_LIT> && N -> getNumOperands ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { SDValue Arg = N -> getOperand ( i ) ;

if ( Arg . getOpcode ( ) == <STR_LIT> ) continue ;


<s> unsigned FirstOpcode = FirstMI ? FirstMI -> getOpcode ( ) : static_cast < unsigned > ( <STR_LIT> ) ; unsigned SecondOpcode = SecondMI . getOpcode ( ) ;

if ( ST . hasFuseAES ( ) ) switch ( SecondOpcode ) {


<s> Ops . push_back ( CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , Triple :: OSType _OSType ) : <ISA_LIT>AsmBackend ( T , TT ) , OSType ( _OSType ) {


<s> bool isVectorReg ( ) const { return Kind == k_Register && Reg . isVector ;


<s> virtual const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const {


<s> static bool hasSMRDSignedImmOffset ( const MCSubtargetInfo & ST ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> SDValue Load = DAG . getLoad ( ValTy , dl , Chain , Base , MemOp ) ; SDValue Thru = cast < MaskedLoadSDNode > ( MaskN ) -> getPassThru ( ) ; if ( isUndef ( Thru ) ) return Load ; SDValue VSel = DAG . getNode ( <STR_LIT> , dl , ValTy , Mask , Load , Thru ) ; return DAG . getMergeValues ( { VSel , Load . getValue ( <NUM_LIT> ) } , dl ) ; } unsigned StoreOpc = <STR_LIT> ; SDValue Value = cast < MaskedStoreSDNode > ( MaskN ) -> getValue ( ) ; SDValue Offset0 = DAG . getTargetConstant ( <NUM_LIT> , dl , ty ( Base ) ) ; if ( MaskN -> getAlign ( ) . value ( ) % HwLen == <NUM_LIT> ) { SDValue Store = getInstr ( StoreOpc , dl , <STR_LIT> , { Mask , Base , Offset0 , Value , Chain } , DAG ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Store . getNode ( ) ) , { MemOp } ) ; return Store ; } auto StoreAlign = [ & ] ( SDValue V , SDValue A ) { SDValue Z = getZero ( dl , ty ( V ) , DAG ) ; SDValue LoV = getInstr ( <STR_LIT> , dl , ty ( V ) , { V , Z , A } , DAG ) ; SDValue HiV = getInstr ( <STR_LIT> , dl , ty ( V ) , { Z , V , A } , DAG ) ; return std :: make_pair ( LoV , HiV ) ; } ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; MVT BoolTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue MaskV = DAG . getNode ( <STR_LIT> , dl , ByteTy , Mask ) ; VectorPair Tmp = StoreAlign ( MaskV , Base ) ; VectorPair MaskU = { DAG . getNode ( <STR_LIT> , dl , BoolTy , Tmp . first ) , DAG . getNode ( <STR_LIT> , dl , BoolTy , Tmp . second ) } ; VectorPair ValueU = StoreAlign ( Value , Base ) ; SDValue Offset1 = DAG . getTargetConstant ( HwLen , dl , <STR_LIT> ) ; SDValue StoreLo = getInstr ( StoreOpc , dl , <STR_LIT> , { MaskU . first , Base , Offset0 , ValueU . first , Chain } , DAG ) ;

SDValue StoreHi = getInstr ( StoreOpc , dl , <STR_LIT> , { MaskU . second , Base , Offset1 , ValueU . second , Chain } , DAG ) ;


<s> if ( ! MCE ) return true ; int64_t Val = MCE -> getValue ( ) ; if ( Val & <NUM_LIT> ) return false ; return ( Val >= - ( <NUM_LIT> << <NUM_LIT> ) && Val <= ( <NUM_LIT> << <NUM_LIT> ) ) ;


<s> if ( isVZIP_v_undef_Mask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V1 ) . getValue ( WhichResult ) ; } unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , <STR_LIT> ) ) ) ;


<s> bool <ISA_LIT>InstrInfo :: mayBeNewStore ( const MachineInstr & MI ) const { if ( MI . mayStore ( ) && ! Subtarget . useNewValueStores ( ) ) return false ; const uint64_t F = MI . getDesc ( ) . TSFlags ;


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ;

return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , NULL , <NUM_LIT> , NULL , <NUM_LIT> ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> unsigned vreg = RegInfo . createVirtualRegister ( entry -> RC ) ; RegInfo . addLiveIn ( preg , vreg ) ; * argreg = preg ; return DAG . getCopyFromReg ( Chain , dl , vreg , VT ) ;


<s> vmull_n_u32 ( uint32x2_t a , uint32_t b ) { uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result ;


<s> static __inline qword si_mpyhhau ( qword a , qword b , qword c ) { return ( ( qword ) ( vec_add ( vec_mule ( ( vec_ushort8 ) ( a ) , ( vec_ushort8 ) ( b ) ) , ( vec_uint4 ) ( c ) ) ) ) ;


<s> if ( static_cast < <ISA_LIT>TargetMachine * > ( TM ) -> getSubtargetImpl ( ) -> isVLIWEnabled ( ) ) { addPass ( create<ISA_LIT>VLIWPacketizer ( ) ) ; }


<s> if ( GET_CODE ( x ) != REG ) return <NUM_LIT> ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) {

MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;


<s> static void moxie_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum = ( * cum < MOXIE_R6 ? * cum + ( ( <NUM_LIT> + MOXIE_FUNCTION_ARG_SIZE ( arg . mode , arg . type ) ) / <NUM_LIT> ) : * cum ) ;


<s> RegisterAggr ( const TargetRegisterInfo & tri ) : ExpAliasUnits ( tri . getNumRegUnits ( ) ) , CheckUnits ( false ) , TRI ( tri ) {


<s> SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) { if ( ValVT . isVector ( ) && ValVT . getVectorElementType ( ) == <STR_LIT> ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getBitcast ( VA . getLocVT ( ) , ValToCopy ) ; assert ( VA . getLocInfo ( ) != CCValAssign :: FPExt && <STR_LIT> ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; }


<s> return false ; } TM = & MF . getTarget ( ) ; if ( ! TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . padShortFunctions ( ) ) return false ; TII = TM -> getInstrInfo ( ) ; ReturnBBs . clear ( ) ; VisitedBBs . clear ( ) ; findReturns ( MF . begin ( ) ) ; bool MadeChange = false ; MachineBasicBlock * MBB ; unsigned int Cycles = <NUM_LIT> ; for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ; NumBBsPadded ++ ; MadeChange = true ; }


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) , false , true ) ;


<s> static bool isTransformable ( const MachineInstr * MI ) { unsigned Opc = MI -> getOpcode ( ) ; return Opc != getTransformOpcode ( Opc ) ;


<s> for ( RNVector :: reverse_iterator OI = Order . rbegin ( ) , OE = Order . rend ( ) ; OI != OE ; ++ OI ) { gatherPredicates ( * OI ) ; Visited . insert ( ( * OI ) -> getEntry ( ) ) ; analyzeLoops ( * OI ) ;


<s> static DecodeStatus DecodeMVEVCVTt1fp ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Qd = ( ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned Qm = ( ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned imm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeVCVTImmOperand ( Inst , imm6 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S ;


<s> const <ISA_LIT>Subtarget & ST = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performBitcastCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : return performSelectCCCombine ( N , DCI . DAG ) ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ;


<s> TypeNo = TypeNo << <STR_LIT> ; if ( Ty . getTag ( ) == dwarf :: DW_TAG_structure_type ) TypeNo = TypeNo | <STR_LIT> ; else TypeNo = TypeNo | <STR_LIT> ; CTy . getName ( TagName ) ; std :: string UniqueSuffix = <STR_LIT> + Ty . getGV ( ) -> getNameStr ( ) . substr ( <NUM_LIT> ) ;


<s> assert ( Cond . size ( ) == <NUM_LIT> && Cond [ <NUM_LIT> ] . isImm ( ) ) ; if ( Cond [ <NUM_LIT> ] . getImm ( ) == COND_REVERSE_NEGATIVE ) { MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Cond [ <NUM_LIT> ] . getReg ( ) ) ) cond_reg = MRI . createVirtualRegister ( MRI . getRegClass ( Cond [ <NUM_LIT> ] . getReg ( ) ) ) ; else cond_reg = Cond [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( cond_reg , RegState :: Define ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( BRIG_TYPE_B1 ) ; } break ; case COND_REVERSE_NEGATIVE : cond_reg = GenerateBranchCondReversion ( MBB , Cond [ <NUM_LIT> ] , this , DL ) ; break ; case COND_REVERSE_POSITIVE : case COND_IRREVERSIBLE : break ; } unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( BRIG_WIDTH_1 ) . addReg ( cond_reg ) . addMBB ( TBB ) . addImm ( BRIG_TYPE_B1 ) ;


<s> assert ( Kind == KindAccessReg && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateImm ( AccessReg ) ) ;


<s> SDValue Base = LD -> getBasePtr ( ) ; SDValue Offset = LD -> getOffset ( ) ; SDNode * OffsetNode = Offset . getNode ( ) ; int32_t Val = cast < ConstantSDNode > ( OffsetNode ) -> getSExtValue ( ) ; EVT LoadedVT = LD -> getMemoryVT ( ) ; unsigned Opcode = <NUM_LIT> ; <STR_LIT> ExtType = LD -> getExtensionType ( ) ; bool IsZeroExt = ( ExtType == <STR_LIT> || ExtType == <STR_LIT> ) ; bool HasVecOffset = false ; if ( LoadedVT == <STR_LIT> ) { if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> ) { if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> ) { if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; else Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> ) { if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; else Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { HasVecOffset = true ; bool Aligned = isAlignedMemNode ( LD ) ; if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = Aligned ? <STR_LIT> : <STR_LIT> ; else Opcode = Aligned ? <STR_LIT> : <STR_LIT> ; } else if ( LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> || LoadedVT == <STR_LIT> ) { if ( HST -> useHVXOps ( ) ) { bool Aligned = isAlignedMemNode ( LD ) ; HasVecOffset = true ; if ( HII -> isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = Aligned ? <STR_LIT> : <STR_LIT> ; else Opcode = Aligned ? <STR_LIT> : <STR_LIT> ; } } else llvm_unreachable ( <STR_LIT> ) ; if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && IsZeroExt ) { SelectIndexedLoadZeroExtend64 ( LD , Opcode , dl ) ; return ; } if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && ExtType == <STR_LIT> ) { SelectIndexedLoadSignExtend64 ( LD , Opcode , dl ) ;


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_CCR ) && <STR_LIT> ) ;


<s> explicit <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> bool hasVInstructions ( ) const { return HasStdExtV || HasStdExtZve32x ;


<s> void BlackfinAsmPrinter :: printMemoryOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { printOperand ( MI , opNum , O ) ;

if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ;


<s> bool <ISA_LIT>TargetLowering :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const {

assert ( SrcAS != DestAS && <STR_LIT> ) ;


<s> offset = cfun -> machine -> callee_save_size - UNITS_PER_WORD ; } else { if ( frame_pointer_needed ) emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; offset = cfun -> machine -> current_frame_size - UNITS_PER_WORD ; } if ( crtl -> calls_eh_return ) emit_insn ( gen_blockage ( ) ) ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; ++ regno ) { if ( xtensa_call_save_reg ( regno ) ) { rtx x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; offset -= UNITS_PER_WORD ; emit_move_insn ( gen_rtx_REG ( SImode , regno ) , gen_frame_mem ( SImode , x ) ) ; } } if ( cfun -> machine -> current_frame_size > <NUM_LIT> ) { if ( frame_pointer_needed || cfun -> machine -> current_frame_size > <NUM_LIT> || cfun -> machine -> current_frame_size <= <NUM_LIT> ) { if ( cfun -> machine -> current_frame_size <= <NUM_LIT> ) offset = cfun -> machine -> current_frame_size ; else offset = cfun -> machine -> callee_save_size ; emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( offset ) ) ) ; } else { rtx tmp_reg = gen_rtx_REG ( Pmode , A9_REG ) ; emit_move_insn ( tmp_reg , GEN_INT ( cfun -> machine -> current_frame_size ) ) ;


<s> static void rs6000_set_default_type_attributes ( tree type ) { if ( rs6000_default_long_calls && ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) ) TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ;


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ;


<s> else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) { rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return <NUM_LIT> ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; return ( use_ldrd && offset > - <NUM_LIT> && offset < <NUM_LIT> && ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: SaveC0 ( SDValue Chain , const SDLoc & DL , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; auto * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue GetC0Ops [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue GetC0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GetC0Ops ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned C0VirtReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

SDValue C0VirtRegNode = DAG . getCopyToReg ( Chain , DL , C0VirtReg , GetC0 ) ;


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , int opNum , raw_ostream & O ) { const MCOperand & Op1 = MI -> getOperand ( opNum + <NUM_LIT> ) ; if ( ! Op1 . isImm ( ) || Op1 . getImm ( ) != <NUM_LIT> ) printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> auto & Refs = RefM [ BA . Id ] ; MachineDomTreeNode * N = MDT . getNode ( BA . Addr -> getCode ( ) ) ; assert ( N ) ; for ( auto I : * N ) {

MachineBasicBlock * SB = I -> getBlock ( ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator Position , const DebugLoc & DL , MCRegister DestinationRegister , MCRegister SourceRegister , bool KillSource ) const { if ( ! <STR_LIT> . contains ( DestinationRegister , SourceRegister ) ) {


<s> static void LowerSubReg32_Op0 ( MCInst & OutMI , unsigned NewOpc ) { OutMI . setOpcode ( NewOpc ) ; lower_subreg32 ( & OutMI , <NUM_LIT> ) ;


<s> for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; I ++ ) { if ( I -> hasNestAttr ( ) ) return true ; } return false ;


initialize<ISA_LIT>MIPeepholePass ( PR ) ;


<s> static void arm_elf_asm_destructor ( rtx symbol , int priority ) {

arm_elf_asm_cdtor ( symbol , priority , false ) ;


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; if ( ! isOneConstant ( N -> getOperand ( <NUM_LIT> ) ) || LHS -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; <STR_LIT> NewCC = <STR_LIT> ( <STR_LIT> ( LHS -> getConstantOperandVal ( <NUM_LIT> ) ) ) ; SDLoc DL ( N ) ; return getSETCC ( NewCC , LHS -> getOperand ( <NUM_LIT> ) , DL , DAG ) ;


return ( __m128 ) __builtin_ia32_vcvtneebf162ps128 ( ( const __v8bf * ) __A ) ;


<s> if ( Opcode == <STR_LIT> && ( RxSBG [ I ] . Mask & <NUM_LIT> ) == <NUM_LIT> ) if ( auto * Load = dyn_cast < LoadSDNode > ( Op0 . getNode ( ) ) ) if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return nullptr ; if ( Opcode == <STR_LIT> && detectOrAndInsertion ( Op0 , RxSBG [ I ] . Mask ) ) { Opcode = <STR_LIT> ; if ( Subtarget -> hasMiscellaneousExtensions ( ) ) Opcode = <STR_LIT> ; } SDValue Ops [ <NUM_LIT> ] = { convertTo ( DL , <STR_LIT> , Op0 ) , convertTo ( DL , <STR_LIT> , RxSBG [ I ] . Input ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Start , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . End , DL , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Rotate , DL , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( Opcode , DL , <STR_LIT> , Ops ) ;

return convertTo ( DL , VT , SDValue ( N , <NUM_LIT> ) ) . getNode ( ) ;


<s> std :: unique_ptr < PBQPRAConstraint > <ISA_LIT>Subtarget :: getCustomPBQPConstraints ( ) const {

return balanceFPOps ( ) ? llvm :: make_unique < A57ChainingConstraint > ( ) : nullptr ;


<s> unsigned NewDMaskVal = <NUM_LIT> ; unsigned OrigLoadIdx = <NUM_LIT> ; for ( unsigned SrcIdx = <NUM_LIT> ; SrcIdx < <NUM_LIT> ; ++ SrcIdx ) { const unsigned Bit = <NUM_LIT> << SrcIdx ; if ( ! ! ( DMaskVal & Bit ) ) { if ( ! ! DemandedElts [ OrigLoadIdx ] ) NewDMaskVal |= Bit ; OrigLoadIdx ++ ; } } if ( DMaskVal != NewDMaskVal ) Args [ DMaskIdx ] = ConstantInt :: get ( DMask -> getType ( ) , NewDMaskVal ) ; } unsigned NewNumElts = DemandedElts . countPopulation ( ) ; if ( ! NewNumElts ) return UndefValue :: get ( II . getType ( ) ) ; if ( II . getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> && NewNumElts == <NUM_LIT> ) return nullptr ; if ( NewNumElts >= VWidth && DemandedElts . isMask ( ) ) { if ( DMaskIdx >= <NUM_LIT> ) II . setArgOperand ( DMaskIdx , Args [ DMaskIdx ] ) ; return nullptr ; } SmallVector < Type * , <NUM_LIT> > OverloadTys ; if ( ! <STR_LIT> ( II . getCalledFunction ( ) , OverloadTys ) ) return nullptr ; Module * M = II . getParent ( ) -> getParent ( ) -> getParent ( ) ; Type * EltTy = IIVTy -> getElementType ( ) ; Type * NewTy = ( NewNumElts == <NUM_LIT> ) ? EltTy : FixedVectorType :: get ( EltTy , NewNumElts ) ; OverloadTys [ <NUM_LIT> ] = NewTy ;

Function * NewIntrin = <STR_LIT> ( M , II . getIntrinsicID ( ) , OverloadTys ) ;


<s> FunctionPass * llvm :: createFalkorMarkStridedAccessesPass ( ) { return new FalkorMarkStridedAccessesLegacy ( ) ;


<s> auto EHType = MF . getTarget ( ) . getMCAsmInfo ( ) -> getExceptionHandlingType ( ) ; return EHType == ExceptionHandling :: Wasm && MF . getFunction ( ) . hasPersonalityFn ( ) && MF . getFrameInfo ( ) . hasCalls ( ) ;


<s> inline unsigned int normalizeFI ( int fi ) const { unsigned norm = fi - OffsetFIs ; assert ( ( fi >= <NUM_LIT> && norm < NumFIs ) && <STR_LIT> ) ; return norm ;


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { return false ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool Is64Bit ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI , Is64Bit ) ;

return createELFObjectWriter ( MOTW , OS , true ) ;


<s> return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ;


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; while ( I -> isDebugValue ( ) ) { if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; }

if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ;


<s> static inline bool isMatchingDecrement ( MachineInstr * MI , unsigned Base , unsigned Bytes , <STR_LIT> Pred , unsigned PredReg ) { unsigned MyPredReg = <NUM_LIT> ;

return ( MI && MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) == Bytes && getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; printOperand ( MI , OpNo , O ) ;


return ( Attributes & <ISA_LIT>FMA3KMergeMasked ) != <NUM_LIT> ;


<s> int ir0_reg_operand ( rtx op , enum machine_mode mode ) {

return c4x_arn_reg_operand ( op , mode , IR0_REGNO ) ;


<s> Offset = Addr ; return true ; } } else { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( Predicate_immSExt16 ( CN ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } if ( ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) && Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue LoVal = Addr . getOperand ( <NUM_LIT> ) ;

if ( dyn_cast < ConstantPoolSDNode > ( LoVal . getOperand ( <NUM_LIT> ) ) ) {


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ;

for ( MachineFunction :: iterator I = F . begin ( ) ; I != F . end ( ) ; ++ I ) Changed |= runOnMachineBasicBlock ( * I ) ;


<s> unsigned FrameReg = GetFrameReg ( Ctx , Out ) ; if ( Ctx . getRegisterInfo ( ) && FrameReg != <STR_LIT> ) { RestoreReg ( Out , LocalFrameReg ) ; Out . EmitCFIRestoreState ( ) ;

if ( FrameReg == <STR_LIT> ) Out . EmitCFIAdjustCfaOffset ( - <NUM_LIT> ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) {