<s> if ( Op0 . isUndef ( ) && Op1 . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; if ( Op0 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ;

else if ( Op1 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ;


<s> AU . addRequired < MachineModuleInfo > ( ) ; AU . addRequired < DwarfWriter > ( ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionNoPIC ( ) {


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; if ( <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) return ( Reg - <STR_LIT> ) % <NUM_LIT> == <NUM_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const {


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { bool Is64 = TT . is<ISA_LIT>64 ( ) ; return create<ISA_LIT>MachObjectWriter ( Is64 , ( Is64 ? MachO :: CPU_TYPE_POWERPC64 : MachO :: CPU_TYPE_POWERPC ) , MachO :: CPU_SUBTYPE_POWERPC_ALL ) ;


<s> if ( ! AMOrNone ) return true ; ExtAddrMode AM = * AMOrNone ; if ( AM . ScaledReg != <STR_LIT> ) { switch ( AM . Scale ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; default : ErrInfo = <STR_LIT> ; return false ; } } if ( ! isInt < <NUM_LIT> > ( AM . Displacement ) ) { ErrInfo = <STR_LIT> <STR_LIT> ; return false ;


<s> for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) ) continue ;


<s> const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ; const TargetRegisterClass * IdxRC = MRI . getRegClass ( Idx -> getReg ( ) ) ; assert ( Idx -> getReg ( ) != <STR_LIT> ) ; if ( ! TII -> getRegisterInfo ( ) . isSGPRClass ( IdxRC ) ) return false ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addOperand ( * Idx ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addOperand ( * Idx ) . addImm ( Offset ) ; }


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> auto Result = tryParseRegister ( RegNo , StartLoc , EndLoc ) ; if ( Result != MatchOperand_Success ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ;

int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ;


<s> static rsqrte_type get_rsqrte_type ( machine_mode mode ) { switch ( mode ) { case DFmode : return gen_aarch64_rsqrtedf ; case SFmode : return gen_aarch64_rsqrtesf ; case V2DFmode : return gen_aarch64_rsqrtev2df ; case V2SFmode : return gen_aarch64_rsqrtev2sf ;

case V4SFmode : return gen_aarch64_rsqrtev4sf ;


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode || mode == V8HFmode || mode == V4BFmode || mode == V8BFmode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) ) return true ; if ( TARGET_INT_SIMD && ( mode == V4UQQmode || mode == V4QQmode || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode || mode == V2HAmode ) ) return true ;

if ( TARGET_HAVE_MVE && ( VALID_MVE_SI_MODE ( mode ) || VALID_MVE_PRED_MODE ( mode ) ) ) return true ;


return ( getGeneration ( ) >= EVERGREEN ) ;


<s> return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasPreallocatedCall ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || ( isWin64Prologue ( MF ) && MFI . hasCopyImplyingStackAdjustment ( ) ) ) ;


do { \ char buf [ <NUM_LIT> ] ; \ fputs ( integer_asm_op ( UNITS_PER_LONG , TRUE ) , ( FILE ) ) ; \ ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , ( VALUE ) ) ; \ assemble_name ( ( FILE ) , buf ) ; \ fputc ( '\n' , ( FILE ) ) ; \ }


<s> static Value * CheckAndCreateOffsetAdd ( Value * X , Value * Y , Value * GEP , IRBuilder < > & Builder ) { auto FixSummands = [ & Builder ] ( FixedVectorType * & VT , Value * & NonVectorVal ) { ConstantInt * Const ; if ( ( Const = dyn_cast < ConstantInt > ( NonVectorVal ) ) && VT -> getElementType ( ) != NonVectorVal -> getType ( ) ) { unsigned TargetElemSize = VT -> getElementType ( ) -> getPrimitiveSizeInBits ( ) ; uint64_t N = Const -> getZExtValue ( ) ; if ( N < ( unsigned ) ( <NUM_LIT> << ( TargetElemSize - <NUM_LIT> ) ) ) { NonVectorVal = Builder . CreateVectorSplat ( VT -> getNumElements ( ) , Builder . getIntN ( TargetElemSize , N ) ) ; return ; } } NonVectorVal = Builder . CreateVectorSplat ( VT -> getNumElements ( ) , NonVectorVal ) ; } ; FixedVectorType * XElType = dyn_cast < FixedVectorType > ( X -> getType ( ) ) ; FixedVectorType * YElType = dyn_cast < FixedVectorType > ( Y -> getType ( ) ) ; if ( XElType && ! YElType ) { FixSummands ( XElType , Y ) ; YElType = cast < FixedVectorType > ( Y -> getType ( ) ) ; } else if ( YElType && ! XElType ) { FixSummands ( YElType , X ) ; XElType = cast < FixedVectorType > ( X -> getType ( ) ) ; } if ( XElType != YElType ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( XElType -> getElementType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) { Constant * ConstX = dyn_cast < Constant > ( X ) ; Constant * ConstY = dyn_cast < Constant > ( Y ) ; if ( ! ConstX || ! ConstY ) return nullptr ; unsigned TargetElemSize = <NUM_LIT> / XElType -> getNumElements ( ) ;

for ( unsigned i = <NUM_LIT> ; i < XElType -> getNumElements ( ) ; i ++ ) {


<s> static SDValue combineFMinNumFMaxNum ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( Subtarget . useSoftFloat ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ( ( Subtarget . hasSSE1 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasSSE2 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) ) return SDValue ( ) ; if ( ! VT . isVector ( ) && DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; EVT SetCCType = DAG . getTargetLoweringInfo ( ) . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; auto MinMaxOp = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MinOrMax = DAG . getNode ( MinMaxOp , DL , VT , Op1 , Op0 ) ;

SDValue IsOp0Nan = DAG . getSetCC ( DL , SetCCType , Op0 , Op0 , <STR_LIT> ) ;


<s> static SDValue lowerMSASplatImm ( SDValue Op , unsigned ImmOp , SelectionDAG & DAG , bool IsSigned = false ) {

auto * CImm = cast < ConstantSDNode > ( Op -> getOperand ( ImmOp ) ) ;


<s> unsigned Opc = <NUM_LIT> ; switch ( Orig -> getOpcode ( ) ) { default : break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) ; Emitted = true ; } break ; } } if ( ! Emitted ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; }


<s> void addMemOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> void printf80mem ( const MachineInstr * MI , unsigned OpNo ) { O << <STR_LIT> ;


<s> if ( is_defn ) write_fn_proto_1 ( s , false , name , decl , force_public ) ; write_fn_proto_1 ( s , is_defn , name , decl , force_public ) ; if ( replaced_dots ) XDELETE ( replaced_dots ) ;


<s> getThumbBLTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ;

return encodeThumbBLOffset ( MO . getImm ( ) ) ;


<s> if ( UseInst -> getOpcode ( ) == Instruction :: PtrToInt ) return false ; if ( LoadInst * LI = dyn_cast < LoadInst > ( UseInst ) ) { if ( LI -> isVolatile ( ) ) return false ; continue ; } if ( StoreInst * <ISA_LIT> = dyn_cast < StoreInst > ( UseInst ) ) { if ( <ISA_LIT> -> isVolatile ( ) ) return false ; if ( <ISA_LIT> -> getPointerOperand ( ) != Val ) return false ; } else if ( AtomicRMWInst * RMW = dyn_cast < AtomicRMWInst > ( UseInst ) ) { if ( RMW -> isVolatile ( ) ) return false ; } else if ( AtomicCmpXchgInst * CAS = dyn_cast < AtomicCmpXchgInst > ( UseInst ) ) { if ( CAS -> isVolatile ( ) ) return false ; } if ( ICmpInst * ICmp = dyn_cast < ICmpInst > ( UseInst ) ) {

if ( ! binaryOpIsDerivedFromSameAlloca ( BaseAlloca , Val , ICmp , <NUM_LIT> , <NUM_LIT> ) ) return false ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Vd = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = ( Val & <NUM_LIT> ) / <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs - <NUM_LIT> ) ; ++ i ) { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ++ Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } return S ;


<s> static __inline__ void _mm_free ( void * __aligned_ptr ) { if ( __aligned_ptr ) free ( ( ( void * * ) __aligned_ptr ) [ - <NUM_LIT> ] ) ;


<s> const Triple & TT = TM -> getTargetTriple ( ) ;

const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ;


<s> else { if ( support_relaxed_compatible_p ( block_info . reaching_out , block_info . local_dem ) ) return true ; return false ; } } else { gcc_assert ( block_info . reaching_out . unknown_p ( ) ) ; return false ;


<s> bool enableClusterStores ( ) const override { return true ;


<s> if ( std :: holds_alternative < slice > ( * val ) ) { std :: get < builder > ( * rv ) . add_from_builder ( std :: get < slice > ( * val ) . b ) ; return rv ; } else { std :: get < builder > ( * rv ) . add_chunk ( stslice { val } ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , false ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ; if ( SDValue V = combineIncDecVector ( N , DAG ) ) return V ; if ( SDValue V = combineSubToSubus ( N , DAG , Subtarget ) ) return V ;

return combineAddOrSubToADCOrSBB ( N , DAG ) ;


<s> ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_MPY0 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = ( CPU == <STR_LIT> || CPU == <STR_LIT> || CPU == <STR_LIT> ) ? UnitsAndLanes ( CVI_SHIFT , <NUM_LIT> ) : UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ; ( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1 , <NUM_LIT> ) ;

( * TUL ) [ <STR_LIT> ] = UnitsAndLanes ( CVI_NONE , <NUM_LIT> ) ;


<s> SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasAVX ( ) ) || ( VT . is512BitVector ( ) && Subtarget . useAVX512Regs ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; Opcode = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , VT , ExOp ) ; } auto SplitAndExtendInReg = [ & ] ( unsigned SplitSize ) { unsigned NumVecs = VT . getSizeInBits ( ) / SplitSize ; unsigned NumSubElts = SplitSize / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; unsigned IROpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i != NumVecs ; ++ i , Offset += NumSubElts ) { SDValue SrcVec = DAG . getNode ( <STR_LIT> , DL , InSubVT , N0 , DAG . getIntPtrConstant ( Offset , DL ) ) ; SrcVec = ExtendVecSize ( DL , SrcVec , SplitSize ) ; SrcVec = DAG . getNode ( IROpc , DL , SubVT , SrcVec ) ; Opnds . push_back ( SrcVec ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , Opnds ) ; } ; if ( ! Subtarget . hasAVX ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) ) return SplitAndExtendInReg ( <NUM_LIT> ) ;

if ( ! Subtarget . useAVX512Regs ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) ) return SplitAndExtendInReg ( <NUM_LIT> ) ;


<s> void <ISA_LIT>Subtarget :: AutoDetectSubtargetFeatures ( ) { unsigned EAX = <NUM_LIT> , EBX = <NUM_LIT> , ECX = <NUM_LIT> , EDX = <NUM_LIT> ; union { unsigned u [ <NUM_LIT> ] ; char c [ <NUM_LIT> ] ; } text ; if ( GetCpuIDAndInfo ( <NUM_LIT> , & EAX , text . u + <NUM_LIT> , text . u + <NUM_LIT> , text . u + <NUM_LIT> ) ) return ; GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) HasCMov = true ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = MMX ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE1 ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE2 ; if ( ECX & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE41 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE42 ;

bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ;


<s> static __inline vec_double2 spu_nand ( vec_double2 a , vec_double2 b ) { return ( ( vec_double2 ) ( si_nand ( ( qword ) ( a ) , ( qword ) ( b ) ) ) ) ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;

cum -> nbytes += ( mode != BLKmode ? ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) & - UNITS_PER_WORD : ( int_size_in_bytes ( type ) + UNITS_PER_WORD - <NUM_LIT> ) & - UNITS_PER_WORD ) ;


<s> explicit <ISA_LIT>ReFunc ( ) : ModulePass ( ID ) {


<s> enum FCInstr instr ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: PREDICATED_BREAK : instr = FC_BREAK_PREDICATE ; break ; case AMDGPU :: CONTINUE : instr = FC_CONTINUE ; break ; case AMDGPU :: IF_PREDICATE_SET : instr = FC_IF_PREDICATE ; break ; case AMDGPU :: ELSE : instr = FC_ELSE ; break ; case AMDGPU :: ENDIF : instr = FC_ENDIF ; break ; case AMDGPU :: ENDLOOP : instr = FC_ENDLOOP ; break ; case AMDGPU :: WHILELOOP :


<s> if ( isInlinableIntLiteral ( Literal ) ) return true ; uint16_t Val = static_cast < uint16_t > ( Literal ) ; return Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> ;


<s> B . setInstr ( MI ) ; const LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MRI . getType ( Src ) == S64 ) ; auto Trunc = B . buildIntrinsicTrunc ( S64 , Src ) ; const auto Zero = B . buildFConstant ( S64 , <NUM_LIT> ) ; const auto One = B . buildFConstant ( S64 , <NUM_LIT> ) ; auto Lt0 = B . buildFCmp ( CmpInst :: FCMP_OGT , S1 , Src , Zero ) ; auto NeTrunc = B . buildFCmp ( CmpInst :: FCMP_ONE , S1 , Src , Trunc ) ;

auto And = B . buildAnd ( S1 , Lt0 , NeTrunc ) ;


<s> void AMDGPUStructurizeCFG :: analyzeLoops ( RegionNode * N ) { if ( N -> isSubRegion ( ) ) { BasicBlock * Exit = N -> getNodeAs < Region > ( ) -> getExit ( ) ; if ( Visited . count ( Exit ) ) Loops [ Exit ] = N -> getEntry ( ) ; } else { BasicBlock * BB = N -> getNodeAs < BasicBlock > ( ) ; BranchInst * Term = cast < BranchInst > ( BB -> getTerminator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Term -> getNumSuccessors ( ) ; i != e ; ++ i ) { BasicBlock * Succ = Term -> getSuccessor ( i ) ; if ( Visited . count ( Succ ) ) Loops [ Succ ] = BB ; }


<s> <STR_LIT> CC = <STR_LIT> ( MI ) ; if ( CC == <STR_LIT> ) return JumpKind :: Invalid ; switch ( CC ) { default : return JumpKind :: Invalid ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return JumpKind :: ELG ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return JumpKind :: AB ; case <STR_LIT> :


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ; V1 = DAG . getNode ( <STR_LIT> , dl , VecVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , dl , VecVT , V2 ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) Ops . push_back ( DAG . getUNDEF ( EltVT ) ) ; else Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , ShuffleMask [ i ] < ( int ) NumElts ? V1 : V2 , DAG . getConstant ( ShuffleMask [ i ] & ( NumElts - <NUM_LIT> ) , dl , <STR_LIT> ) ) ) ; } SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( ShuffleMask , VT ) ) return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( Op , DAG ) ; if ( VT == <STR_LIT> ) if ( SDValue NewOp = LowerVECTOR_SHUFFLEv8i8 ( Op , ShuffleMask , DAG ) ) return NewOp ;


<s> virtual void completeType ( BTFDebug & BDebug ) {


<s> if ( CSI . empty ( ) && ! needsFP ( MF ) ) { return ; } unsigned MinGPR = <STR_LIT> ; unsigned MinG8R = <STR_LIT> ; unsigned MinFPR = <STR_LIT> ; unsigned MinVR = <STR_LIT> ; bool HasGPSaveArea = false ; bool HasG8SaveArea = false ; bool HasFPSaveArea = false ; bool HasCRSaveArea = false ; bool HasVRSAVESaveArea = false ; bool HasVRSaveArea = false ; SmallVector < CalleeSavedInfo , <NUM_LIT> > GPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > G8Regs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > FPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > VRegs ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RC = CSI [ i ] . getRegClass ( ) ; if ( RC == <STR_LIT> ) { HasGPSaveArea = true ; GPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinGPR ) { MinGPR = Reg ; } } else if ( RC == <STR_LIT> ) { HasG8SaveArea = true ; G8Regs . push_back ( CSI [ i ] ) ; if ( Reg < MinG8R ) { MinG8R = Reg ; } } else if ( RC == <STR_LIT> ) { HasFPSaveArea = true ; FPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( RC == <STR_LIT> || RC == <STR_LIT> ) { } else if ( RC == <STR_LIT> ) { HasVRSAVESaveArea = true ; } else if ( RC == <STR_LIT> ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> static bool riscv_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_SAVE_RESTORE ) return false ; if ( cfun -> machine -> naked_p ) return false ; return true ;


<s> bool hasNullExportTarget ( ) const {


<s> const char * pic_name = reg_names [ REGNO ( pic_offset_table_rtx ) ] ; int align ; text_section ( ) ; align = floor_log2 ( FUNCTION_BOUNDARY / BITS_PER_UNIT ) ; if ( align > <NUM_LIT> ) ASM_OUTPUT_ALIGN ( asm_out_file , align ) ; ASM_OUTPUT_LABEL ( asm_out_file , pic_helper_symbol_name ) ; if ( flag_delayed_branch ) fprintf ( asm_out_file , <STR_LIT> , pic_name , pic_name ) ;

else fprintf ( asm_out_file , <STR_LIT> , pic_name , pic_name ) ;


<s> explicit <ISA_LIT>AtomicExpandPass ( const <ISA_LIT>TargetMachine * TM ) : FunctionPass ( ID ) , TM ( TM ) {


<s> static MCInstPrinter * createMCInstPrinter ( const Triple & , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { assert ( SyntaxVariant == <NUM_LIT> && <STR_LIT> ) ;

return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> Stream . EmitRecord ( bitc :: MODULE_CODE_VERSION , ArrayRef < unsigned > { <NUM_LIT> } ) ;


<s> if ( Imm == <NUM_LIT> ) return false ; for ( RepeatWidth = RegWidth ; RepeatWidth > <NUM_LIT> ; RepeatWidth /= <NUM_LIT> ) { uint64_t RepeatMask = RepeatWidth == <NUM_LIT> ? - <NUM_LIT> : ( <NUM_LIT> << RepeatWidth ) - <NUM_LIT> ; uint64_t ReplicatedMask = Imm & RepeatMask ; if ( ReplicatedMask == <NUM_LIT> ) continue ; bool IsReplicatedMask = true ; for ( unsigned i = RepeatWidth ; i < RegWidth ; i += RepeatWidth ) { if ( ( ( Imm >> i ) & RepeatMask ) != ReplicatedMask ) { IsReplicatedMask = false ; break ; } } if ( ! IsReplicatedMask ) continue ; Rotation = countTrailingZeros ( Imm ) ; if ( Rotation == <NUM_LIT> ) { Rotation = RegWidth == <NUM_LIT> ? CountLeadingOnes_64 ( Imm ) : CountLeadingOnes_32 ( Imm ) ; Rotation = RepeatWidth - Rotation ; } uint64_t ReplicatedOnes = ReplicatedMask ; if ( Rotation != <NUM_LIT> && Rotation != <NUM_LIT> ) ReplicatedOnes = ( ReplicatedMask >> Rotation ) | ( ( ReplicatedMask << ( RepeatWidth - Rotation ) ) & RepeatMask ) ; if ( ! isMask_64 ( ReplicatedOnes ) ) continue ; Num1s = CountTrailingOnes_64 ( ReplicatedOnes ) ; break ; } if ( RepeatWidth == <NUM_LIT> || Num1s == RepeatWidth ) return false ; uint32_t N = RepeatWidth == <NUM_LIT> ; uint32_t ImmR = RepeatWidth - Rotation ; uint32_t ImmS = Num1s - <NUM_LIT> ;


<s> switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> unsigned FixedObject = IsWin64 ? alignTo ( AFI -> getVarArgsGPRSize ( ) , <NUM_LIT> ) : <NUM_LIT> ;

unsigned FPAdjust = isTargetDarwin ( MF ) ? <NUM_LIT> : AFI -> getCalleeSavedStackSize ( MF . getFrameInfo ( ) ) ;


<s> const Align ABITypeAlign = DL . getABITypeAlign ( ArgTy ) ; if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ; return std :: min ( ABITypeAlign , DL . getStackAlignment ( ) ) ;


<s> bool isSVEFPImmZero ( ) const { return Kind == k_FPImm && ( getFPImm ( ) == ( unsigned ) - <NUM_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printMEMriOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { const MCOperand & MO0 = MI -> getOperand ( OpNo ) ;

const MCOperand & MO1 = MI -> getOperand ( OpNo + <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : return TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ; case <STR_LIT> : case <STR_LIT> : return hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : { const Function & F = MF . getFunction ( ) ; if ( F . getCallingConv ( ) == CallingConv :: Mono ) return true ; }


<s> bool isU12Imm ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> assert ( ( Binary & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned UBit = ( Binary >> <NUM_LIT> ) & <NUM_LIT> ; return <NUM_LIT> | ( UBit << <NUM_LIT> ) | ( Binary & <NUM_LIT> ) ;


<s> int NewOpcode ; if ( RC == & <STR_LIT> ) NewOpcode = QII -> GetDotNewPredOp ( MI , MBPI ) ; else NewOpcode = QII -> GetDotNewOp ( MI ) ;

MI -> setDesc ( QII -> get ( NewOpcode ) ) ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> Options . LoadSizes = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ;

Options . MaxNumLoads = TLI -> getMaxExpandSizeMemcmp ( OptSize ) ;


<s> void <ISA_LIT>MachineFunction :: anchor ( ) {


<s> bool <ISA_LIT>IndirectThunks :: runOnMachineFunction ( MachineFunction & MF ) { LLVM_DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ;

auto & MMI = getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ;


<s> return isImmTy ( ImmTyOffset ) && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ;


<s> if ( PBBInfo . Exit . isUnknown ( ) || ! PBBInfo . Exit . hasCompatibleVTYPE ( Require , false ) ) return true ; MachineInstr * DefMI = MRI -> getVRegDef ( InReg ) ; if ( ! DefMI || ( DefMI -> getOpcode ( ) != <STR_LIT> && DefMI -> getOpcode ( ) != <STR_LIT> && DefMI -> getOpcode ( ) != <STR_LIT> ) ) return true ; VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( ! DefInfo . hasSameAVL ( PBBInfo . Exit ) || ! DefInfo . hasSameVTYPE ( PBBInfo . Exit ) ) return true ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( tm , * this ) {


<s> if ( ! validateLdsDirect ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateSOPLiteral ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateVOP3Literal ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateConstantBusLimitations ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateEarlyClobberLimitations ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateIntClampSupported ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ;


<s> switch ( Opcode ) { case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ;


<s> static bool tryAddingSymbolicOperand ( uint64_t Address , int32_t Value , bool isBranch , uint64_t InstSize , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ;

return Dis -> tryAddingSymbolicOperand ( MI , ( uint32_t ) Value , Address , isBranch , <NUM_LIT> , InstSize ) ;


<s> bool isSameRegisterClass ( unsigned Reg1 , unsigned Reg2 ) { return <STR_LIT> . contains ( Reg1 , Reg2 ) || <STR_LIT> . contains ( Reg1 , Reg2 ) ;


<s> EVT PtrVT = getTargetLowering ( ) -> getPointerTy ( * TM . getDataLayout ( ) ) ; Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , PtrVT ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , Addr , <STR_LIT> ) ; return true ; }

if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) {


<s> void <ISA_LIT>ExceptionInfo :: print ( raw_ostream & OS , const Module * ) const { for ( auto * WE : TopLevelExceptions ) WE -> print ( OS ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) {

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( ! <STR_LIT> ( V1 ) && ! isScalarLoadToVector ( V1 ) ) return false ; if ( <STR_LIT> ( V2 ) || WillBeConstantPoolLoad ( V2 ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i ) ) return false ;

for ( unsigned i = NumElems / <NUM_LIT> ; i != NumElems ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + NumElems ) ) return false ;


<s> if ( TARGET_64BIT || TARGET_ALIGN_DOUBLE ) return computed ; if ( TARGET_IAMCU ) return iamcu_alignment ( type , computed ) ;

mode = TYPE_MODE ( strip_array_types ( type ) ) ;


<s> <ISA_LIT>MCChecker :: <ISA_LIT>MCChecker ( <ISA_LIT>MCChecker const & Other , MCSubtargetInfo const & STI , bool CopyReportErrors ) : Context ( Other . Context ) , MCB ( Other . MCB ) , RI ( Other . RI ) , MCII ( Other . MCII ) , STI ( STI ) , ReportErrors ( CopyReportErrors ? Other . ReportErrors : false ) {


<s> unsigned getPointerSize ( ) const { return <NUM_LIT> ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : CalleeSavedFrameSize ( <NUM_LIT> ) , ReturnAddrIndex ( <NUM_LIT> ) {


<s> if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , IDLoc , Instructions ) ) return true ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : GlobalBaseReg ( <NUM_LIT> ) , VarArgsFrameOffset ( <NUM_LIT> ) , SRetReturnReg ( <NUM_LIT> ) {


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ;

if ( SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true ) ) return LD ;


<s> return ArgInfo . QueuePtr . getRegister ( ) ;


<s> assert ( ( Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm || Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm || Kind == k_MemoryRegImm || Kind == k_MemoryZeroImm ) && <STR_LIT> ) ;


<s> if ( Catch -> getNextNode ( ) != Extract ) EHPad -> insert ( Catch -> getNextNode ( ) , Extract -> removeFromParent ( ) ) ; Register ExnReg = Catch -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto * ThenMBB = MF . CreateMachineBasicBlock ( ) ; auto * ElseMBB = MF . CreateMachineBasicBlock ( ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( EHPad ) ) , ElseMBB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( ElseMBB ) ) , ThenMBB ) ; ThenMBB -> splice ( ThenMBB -> end ( ) , EHPad , Extract , EHPad -> end ( ) ) ; ThenMBB -> transferSuccessors ( EHPad ) ; EHPad -> addSuccessor ( ThenMBB ) ; EHPad -> addSuccessor ( ElseMBB ) ; DebugLoc DL = Extract -> getDebugLoc ( ) ; const char * CPPExnSymbol = MF . createExternalSymbolName ( <STR_LIT> ) ; BuildMI ( EHPad , DL , TII . get ( <STR_LIT> ) ) . addMBB ( ThenMBB ) . addExternalSymbol ( CPPExnSymbol ) . addReg ( ExnReg ) ; BuildMI ( EHPad , DL , TII . get ( <STR_LIT> ) ) . addMBB ( ElseMBB ) ; if ( TerminatePads . count ( EHPad ) ) { Function * ClangCallTerminateFn = MF . getFunction ( ) . getParent ( ) -> getFunction ( <STR_LIT> ) ; assert ( ClangCallTerminateFn && <STR_LIT> ) ; Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( ElseMBB , DL , TII . get ( <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) ; BuildMI ( ElseMBB , DL , TII . get ( <STR_LIT> ) ) . addGlobalAddress ( ClangCallTerminateFn ) . addReg ( Reg ) ; BuildMI ( ElseMBB , DL , TII . get ( <STR_LIT> ) ) ; } else { BuildMI ( ElseMBB , DL , TII . get ( <STR_LIT> ) ) . addReg ( ExnReg ) ; if ( EHInfo -> hasEHPadUnwindDest ( EHPad ) ) ElseMBB -> addSuccessor ( EHInfo -> getEHPadUnwindDest ( EHPad ) ) ; }


<s> case PowerPCCC :: PL : return <STR_LIT> ; case PowerPCCC :: VS : return <STR_LIT> ; case PowerPCCC :: VC : return <STR_LIT> ; case PowerPCCC :: HI : return <STR_LIT> ; case PowerPCCC :: LS : return <STR_LIT> ; case PowerPCCC :: GE : return <STR_LIT> ; case PowerPCCC :: LT : return <STR_LIT> ; case PowerPCCC :: GT : return <STR_LIT> ;

case PowerPCCC :: LE : return <STR_LIT> ;


<s> if ( align > <NUM_LIT> ) ASM_OUTPUT_ALIGN ( asm_out_file , align ) ; ASM_OUTPUT_LABEL ( asm_out_file , pic_helper_symbol_name ) ; if ( flag_delayed_branch ) fprintf ( asm_out_file , <STR_LIT> , pic_name , pic_name ) ; else fprintf ( asm_out_file , <STR_LIT> , pic_name , pic_name ) ; pic_helper_emitted_p = true ;


<s> PendingBA -> setLastFragment ( CF ) ; PendingBA = nullptr ; if ( isa_and_nonnull < MCDataFragment > ( CF ) ) OS . insert ( new MCDataFragment ( ) ) ; MCSection * Sec = OS . getCurrentSectionOnly ( ) ;

if ( AlignBoundary . value ( ) > Sec -> getAlignment ( ) ) Sec -> setAlignment ( AlignBoundary ) ;


<s> <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset , TRI ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) { if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ; bool HighRegsUsed = false ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) >= <STR_LIT> ) { HighRegsUsed = true ; break ; } if ( ! HighRegsUsed ) MergeInstr = MBB . end ( ) ; else return false ; } } if ( MergeInstr != MBB . end ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MergeInstr ) ; MBB . erase ( MergeInstr ) ; } unsigned NewOpc = getUpdatingLSMultipleOpcode ( Opcode , Mode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned OpNum = <NUM_LIT> , e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . add ( MI -> getOperand ( OpNum ) ) ; MIB . setMemRefs ( MI -> memoperands ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; MBB . erase ( MBBI ) ; return true ;


<s> } if ( ParseDirectiveMajorMinor ( Major , Minor ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; if ( ParseAsAbsoluteExpression ( Stepping ) ) return TokError ( <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: String ) ) return TokError ( <STR_LIT> ) ; VendorName = getLexer ( ) . getTok ( ) . getStringContents ( ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ;


<s> return ( __m128i ) __builtin_ia32_punpckhqdq128 ( ( __v2di ) __A , ( __v2di ) __B ) ;


<s> SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; bool IsFSHR = Op . getOpcode ( ) == <STR_LIT> ; if ( VT . isVector ( ) ) { assert ( Subtarget . hasVBMI2 ( ) && <STR_LIT> ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( isConstantSplat ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . getZExtValue ( ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ;

if ( VT == <STR_LIT> ) Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ;


<s> else return <STR_LIT> ; } else { if ( TARGET_BIG_ENDIAN ) return <STR_LIT> ; else return <STR_LIT> ; } } if ( INTVAL ( in0_idx0 ) != INTVAL ( in0_idx1 ) && INTVAL ( in1_idx0 ) != INTVAL ( in1_idx1 ) ) { if ( INTVAL ( in0_idx0 ) == <NUM_LIT> ) { if ( TARGET_BIG_ENDIAN ) return <STR_LIT> ; else return <STR_LIT> ; } else { if ( TARGET_BIG_ENDIAN ) return <STR_LIT> ; else return <STR_LIT> ; } } gcc_unreachable ( ) ;


<s> void BRIGDwarfStreamer :: Finish ( ) { MCELFStreamer :: Finish ( ) ; dwarfStream -> flush ( ) ;


<s> int FI = MFI . CreateFixedObject ( ValVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; SDValue Val ; <STR_LIT> ExtType ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : case CCValAssign :: Indirect : case CCValAssign :: BCvt : ExtType = <STR_LIT> ; break ; }

Val = DAG . getExtLoad ( ExtType , DL , LocVT , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) , ValVT ) ;


<s> } } } if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; } unsigned Bits = VT . getSizeInBits ( ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ; if ( SumC -> getSExtValue ( ) == Bits && ShAmt1Op1 == ShAmt0 ) return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; } } else if ( ConstantSDNode * ShAmt1C = dyn_cast < ConstantSDNode > ( ShAmt1 ) ) { ConstantSDNode * ShAmt0C = dyn_cast < ConstantSDNode > ( ShAmt0 ) ; if ( ShAmt0C && ShAmt0C -> getSExtValue ( ) + ShAmt1C -> getSExtValue ( ) == Bits ) return DAG . getNode ( Opc , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 . getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShAmt0 ) ) ; }


<s> } assert ( ! ( ( Undef1 || Zero1 ) && ( Undef2 || Zero2 ) ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > Unpckl , Unpckh ; createUnpackShuffleMask ( VT , Unpckl , true , IsUnary ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckl ) ) { UnpackOpcode = <STR_LIT> ; V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } createUnpackShuffleMask ( VT , Unpckh , false , IsUnary ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckh ) ) { UnpackOpcode = <STR_LIT> ; V2 = ( Undef2 ? DAG . getUNDEF ( VT ) : ( IsUnary ? V1 : V2 ) ) ; V1 = ( Undef1 ? DAG . getUNDEF ( VT ) : V1 ) ; return true ; } if ( IsUnary && ( Zero1 || Zero2 ) ) { if ( ( Subtarget . hasSSE41 ( ) || VT == <STR_LIT> || VT == <STR_LIT> ) && isSequentialOrUndefOrZeroInRange ( TargetMask , <NUM_LIT> , NumElts , <NUM_LIT> ) ) return false ; bool MatchLo = true , MatchHi = true ; for ( int i = <NUM_LIT> ; ( i != NumElts ) && ( MatchLo || MatchHi ) ; ++ i ) { int M = TargetMask [ i ] ; if ( ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero1 ) || ( ( ( i & <NUM_LIT> ) == <NUM_LIT> ) && Zero2 ) || ( M == SM_SentinelUndef ) ) continue ; MatchLo &= ( M == Unpckl [ i ] ) ; MatchHi &= ( M == Unpckh [ i ] ) ; } if ( MatchLo || MatchHi ) { UnpackOpcode = MatchLo ? <STR_LIT> : <STR_LIT> ; V2 = Zero2 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; V1 = Zero1 ? getZeroVector ( VT , Subtarget , DAG , DL ) : V1 ; return true ; } } if ( ! IsUnary ) { ShuffleVectorSDNode :: commuteMask ( Unpckl ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckl ) ) { UnpackOpcode = <STR_LIT> ; std :: swap ( V1 , V2 ) ; return true ; } ShuffleVectorSDNode :: commuteMask ( Unpckh ) ; if ( isTargetShuffleEquivalent ( TargetMask , Unpckh ) ) {


<s> if ( MO2 . getImm ( ) ) { O << <STR_LIT> << ( MO2 . getImm ( ) << <NUM_LIT> ) ; } O << <STR_LIT> << markup ( <STR_LIT> ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateSysReg ( StringRef Str , SMLoc S , uint32_t MRSReg , uint32_t MSRReg , uint32_t PStateField , MCContext & Ctx ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_SysReg , Ctx ) ; Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . MRSReg = MRSReg ;


<s> void processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , MCValue & Target , uint64_t & Value , bool & IsResolved ) { switch ( Fixup . getKind ( ) ) { case <STR_LIT> : case <STR_LIT> : { if ( Value != <NUM_LIT> ) { IsResolved = true ; } } break ; }


<s> bool <ISA_LIT>Operand :: isPCD ( ) const { return isMemOp ( ) && MemOp . Op == <STR_LIT> :: RegIndirectDisplacement && MemOp . OuterReg == <STR_LIT> ;


<s> vmlsl_n_u32 ( uint64x2_t a , uint32x2_t b , uint32_t c ) { uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> return parseRegister ( Operands , RegGR , <STR_LIT> , ADDR64Reg ) ;


<s> return getDefRegState ( R . isDef ( ) ) | getImplRegState ( R . isImplicit ( ) ) | getKillRegState ( R . isKill ( ) ) | getDeadRegState ( R . isDead ( ) ) | getUndefRegState ( R . isUndef ( ) ) | getInternalReadRegState ( R . isInternalRead ( ) ) | ( R . isDebug ( ) ? RegState :: Debug : <NUM_LIT> ) ;


<s> case <STR_LIT> : { Register Reg = PushOp . getReg ( ) ; if ( Is64Bit && Store -> getOpcode ( ) == <STR_LIT> ) { Register UndefReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , UndefReg ) ; BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( UndefReg ) . add ( PushOp ) . addImm ( <STR_LIT> ) ; } bool SlowPUSHrmm = STI -> isAtom ( ) || STI -> isSLM ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup , Reg ) ) ) { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) ; unsigned NumOps = DefMov -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) Push -> addOperand ( DefMov -> getOperand ( i ) ) ; DefMov -> eraseFromParent ( ) ; } else { PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . addReg ( Reg ) . getInstr ( ) ; }


<s> CurBB = BB ; const Function * F = CurDAG -> getMachineFunction ( ) . getFunction ( ) ; OptForSize = F -> hasFnAttr ( Attribute :: OptimizeForSize ) ; DEBUG ( BB -> dump ( ) ) ; if ( OptLevel != CodeGenOpt :: None ) PreprocessForRMW ( ) ; PreprocessForFPConvert ( ) ; DOUT << <STR_LIT> ; Indent = <NUM_LIT> ;


<s> LLT SrcTy = MRI . getType ( Src ) ; unsigned NewOpc = MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; auto Tmp = B . buildInstr ( NewOpc , { DstTy } , { Src } ) ;

B . buildUMin ( Dst , Tmp , B . buildConstant ( DstTy , SrcTy . getSizeInBits ( ) ) ) ;


<s> BuildMI ( MBB , MI , DL , * ReplInstrMCID [ <NUM_LIT> ] , ZipDest [ <NUM_LIT> ] ) . addReg ( StReg [ <NUM_LIT> ] ) . addReg ( StReg [ <NUM_LIT> ] ) ; BuildMI ( MBB , MI , DL , * ReplInstrMCID [ <NUM_LIT> ] , ZipDest [ <NUM_LIT> ] ) . addReg ( StReg [ <NUM_LIT> ] , StRegKill [ <NUM_LIT> ] ) . addReg ( StReg [ <NUM_LIT> ] , StRegKill [ <NUM_LIT> ] ) ; BuildMI ( MBB , MI , DL , * ReplInstrMCID [ <NUM_LIT> ] , ZipDest [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) ; BuildMI ( MBB , MI , DL , * ReplInstrMCID [ <NUM_LIT> ] , ZipDest [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) ; BuildMI ( MBB , MI , DL , * ReplInstrMCID [ <NUM_LIT> ] , ZipDest [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) ; BuildMI ( MBB , MI , DL , * ReplInstrMCID [ <NUM_LIT> ] , ZipDest [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) ; BuildMI ( MBB , MI , DL , * ReplInstrMCID [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) . addReg ( AddrReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , * ReplInstrMCID [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) . addReg ( ZipDest [ <NUM_LIT> ] ) . addReg ( AddrReg ) . addImm ( <NUM_LIT> ) ; break ; } ++ NumModifiedInstr ; return true ;


<s> LLVM_DUMP_METHOD void <ISA_LIT>ConstantPoolValue :: dump ( ) const {


<s> size_t i ; HOST_WIDE_INT builtin_mask = rs6000_builtin_mask ; tree int_ftype_int_v2sf_v2sf = build_function_type_list ( integer_type_node , integer_type_node , V2SF_type_node , V2SF_type_node , NULL_TREE ) ; tree pcfloat_type_node = build_pointer_type ( build_qualified_type ( float_type_node , TYPE_QUAL_CONST ) ) ; tree v2sf_ftype_long_pcfloat = build_function_type_list ( V2SF_type_node , long_integer_type_node , pcfloat_type_node , NULL_TREE ) ; tree void_ftype_v2sf_long_pcfloat = build_function_type_list ( void_type_node , V2SF_type_node , long_integer_type_node , pcfloat_type_node , NULL_TREE ) ; def_builtin ( <STR_LIT> , v2sf_ftype_long_pcfloat , PAIRED_BUILTIN_LX ) ; def_builtin ( <STR_LIT> , void_ftype_v2sf_long_pcfloat , PAIRED_BUILTIN_STX ) ; d = bdesc_paired_preds ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_paired_preds ) ; ++ i , d ++ ) { tree type ; HOST_WIDE_INT mask = d -> mask ; if ( ( mask & builtin_mask ) != mask ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , d -> name ) ; continue ;


<s> return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ;

if ( Kind . isMergeable1ByteCString ( ) ) return false ;


<s> unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Type = MachO :: <ISA_LIT>_RELOC_HALF ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; const MCSymbolData * A_SD = & Asm . getSymbolData ( * A ) ; if ( ! A_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; uint32_t Value = Writer -> getSymbolAddress ( A_SD , Layout ) ; uint32_t Value2 = <NUM_LIT> ; uint64_t SecAddr = Writer -> getSectionAddress ( A_SD -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { const MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; Type = MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ;

Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ;


<s> if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; TLSModel :: Model model = DAG . getTarget ( ) . getTLSModel ( GV ) ; switch ( model ) { case TLSModel :: GeneralDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , PtrVT ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , PtrVT ) ; case TLSModel :: LocalDynamic : return LowerToTLSLocalDynamicModel ( GA , DAG , PtrVT , Subtarget -> is64Bit ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , PtrVT , model , Subtarget -> is64Bit ( ) , DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; } llvm_unreachable ( <STR_LIT> ) ; } if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; SDLoc DL ( Op ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ;

unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( ! TARGET_SIMD ) return false ; machine_mode vmode ; scalar_int_mode imode ; unsigned HOST_WIDE_INT ival ; if ( CONST_DOUBLE_P ( x ) && SCALAR_FLOAT_MODE_P ( mode ) ) { if ( ! aarch64_reinterpret_float_as_int ( x , & ival ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; imode = int_mode_for_mode ( mode ) . require ( ) ; } else if ( CONST_INT_P ( x ) && is_a < scalar_int_mode > ( mode , & imode ) ) ival = INTVAL ( x ) ; else return false ; int width = GET_MODE_BITSIZE ( imode ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; vmode = aarch64_simd_container_mode ( imode , width ) ; rtx v_op = aarch64_simd_gen_const_vector_dup ( vmode , ival ) ;

return aarch64_simd_valid_immediate ( v_op , NULL ) ;


<s> assert ( VT . isVector ( ) && InVT . isVector ( ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( Subtarget . hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ;

SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ;


<s> SmallVector < SDValue , <NUM_LIT> > MaskOps ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] >= <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size ) return SDValue ( ) ; MaskOps . push_back ( Mask [ i ] < Size ? AllOnes : Zero ) ; } SDValue V1Mask = DAG . getBuildVector ( VT , DL , MaskOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V1Mask ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; V2 = DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , DAG . getBitcast ( MaskVT , V1Mask ) , DAG . getBitcast ( MaskVT , V2 ) ) ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ;


<s> uint64_t getPC24DBLBPPEncoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> , <NUM_LIT> , false ) ;


<s> CallInst * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; Function * Callee = Call -> getCalledFunction ( ) ; if ( ! Callee || ( Callee -> getName ( ) != NVVM_REFLECT_FUNCTION && Callee -> getIntrinsicID ( ) != <STR_LIT> ) ) continue ; assert ( Call -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; const Value * Str = Call -> getArgOperand ( <NUM_LIT> ) ; if ( const CallInst * ConvCall = dyn_cast < CallInst > ( Str ) ) { Str = ConvCall -> getArgOperand ( <NUM_LIT> ) ; } assert ( isa < ConstantExpr > ( Str ) && <STR_LIT> ) ; const ConstantExpr * GEP = cast < ConstantExpr > ( Str ) ;

const Value * Sym = GEP -> getOperand ( <NUM_LIT> ) ;


<s> SDValue Upper = CurDAG -> getConstant ( UpperVal , DL , VT ) ; if ( Op0 . getNode ( ) ) Upper = CurDAG -> getNode ( Opcode , DL , VT , Op0 , Upper ) ; Upper = SDValue ( Select ( Upper . getNode ( ) ) , <NUM_LIT> ) ; SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ;

SDValue Or = CurDAG -> getNode ( Opcode , DL , VT , Upper , Lower ) ;


<s> MCSubtargetInfo const & <ISA_LIT>MCCodeEmitter :: getSubtargetInfo ( ) const { return MST ;


<s> static bool regIsPICBase ( unsigned BaseReg , const MachineRegisterInfo & MRI ) { if ( ! Register :: isVirtualRegister ( BaseReg ) ) return false ; bool isPICBase = false ; for ( MachineRegisterInfo :: def_instr_iterator I = MRI . def_instr_begin ( BaseReg ) , E = MRI . def_instr_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = & * I ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , <ISA_LIT>Subtarget & STI , <ISA_LIT>RegisterBankInfo & RBI ) : STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , {


<s> if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V1 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V1 , Mask , Subtarget , DAG ) ) return Rotate ; SmallVector < int , <NUM_LIT> > MutableMask ( Mask . begin ( ) , Mask . end ( ) ) ; return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , MutableMask , Subtarget , DAG ) ; } assert ( llvm :: any_of ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ) && <STR_LIT> <STR_LIT> ) ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BitBlend ; if ( SDValue Unpack = lowerShuffleAsPermuteAndUnpack ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Unpack ; if ( ! IsBlendSupported && Subtarget . hasSSSE3 ( ) ) {


<s> case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; } SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Sum = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Cond , DL , <STR_LIT> ) , SDValue ( Sum . getNode ( ) , <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , Sum , SetCC ) ;


<s> for ( Value * Op : I -> operands ( ) ) if ( ! isa < LoadInst > ( Op ) && ! isa < ConstantInt > ( Op ) ) ExtCost ++ ;


return ( __m64 ) __result [ <NUM_LIT> ] ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_VIDEOCORE , false ) {


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> const Function & F = MF -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return ; emit<ISA_LIT>Nops ( * OutStreamer , Num , Subtarget ) ; return ; }

auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ;


<s> case IES_LSHIFT : case IES_RSHIFT : case IES_PLUS : case IES_MINUS : case IES_NOT : case IES_MULTIPLY : case IES_DIVIDE : case IES_MOD : case IES_LPAREN : case IES_LBRAC :


<s> return ( timode_p == ! ! TARGET_64BIT && TARGET_STV && TARGET_SSE2 && optimize > <NUM_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) {

RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> unsigned Rn = CTX . getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; unsigned Imm5 = MO1 . getImm ( ) ;

return ( ( Imm5 & <NUM_LIT> ) << <NUM_LIT> ) | Rn ;


<s> void avr_fix_inputs ( rtx * op , unsigned opmask , unsigned rmask ) {

avr_fix_operands ( op , NULL , opmask , rmask ) ;


<s> uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = <STR_LIT> ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> Register AVLReg = Require . getAVLReg ( ) ; if ( ! AVLReg . isVirtual ( ) ) return true ; MachineInstr * PHI = MRI -> getVRegDef ( AVLReg ) ; if ( ! PHI || PHI -> getOpcode ( ) != <STR_LIT> || PHI -> getParent ( ) != & MBB ) return true ; for ( unsigned PHIOp = <NUM_LIT> , NumOps = PHI -> getNumOperands ( ) ; PHIOp != NumOps ; PHIOp += <NUM_LIT> ) { Register InReg = PHI -> getOperand ( PHIOp ) . getReg ( ) ; MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ;

const BlockData & PBBInfo = BlockInfo [ PBB -> getNumber ( ) ] ;


<s> if ( ! N . hasOneUse ( ) || ! U -> hasOneUse ( ) ) return false ; SDNode * CCUser = * U -> use_begin ( ) ; SDNode * CCRegUser = nullptr ;

if ( CCUser -> getOpcode ( ) == <STR_LIT> || cast < RegisterSDNode > ( CCUser -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) == <STR_LIT> ) {


<s> poly_uint64 bytepos ; if ( ! wide_bytepos . to_uhwi ( & bytepos ) || pieces . length ( ) + field_info . pieces . length ( ) > MAX_PIECES ) return DOESNT_MATTER ; gcc_assert ( ! field_info . pieces . is_empty ( ) ) ; for ( unsigned int i = <NUM_LIT> ; i < field_info . pieces . length ( ) ; ++ i ) { piece p = field_info . pieces [ i ] ; p . offset += bytepos ; add_piece ( p ) ; } }

return pieces . is_empty ( ) ? NO_ABI_IDENTITY : IS_PST ;


<s> lowerLongBranchLUi ( MI , OutMI ) ; return true ; case <STR_LIT> : lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> ) ; return true ;


<s> if ( ( RegIndex != <NUM_LIT> ) && ( ( int ) Options . getATRegNum ( ) == RegIndex ) ) { if ( RegIndex == <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; else Warning ( Loc , Twine ( <STR_LIT> ) + Twine ( RegIndex ) + <STR_LIT> + Twine ( RegIndex ) + <STR_LIT> ) ;


<s> assert ( PI < <STR_LIT> :: NUM_PERSONALITY_INDEX && <STR_LIT> ) ;

EmitByte ( <STR_LIT> :: EHT_COMPACT | PI ) ;


<s> DecodeStatus Result = decodeInstruction ( Table , MI , Insn , Address , this , STI ) ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MI . insert ( MI . begin ( ) , MCOperand :: createReg ( <STR_LIT> ) ) ; const MCOperand & Imm4Op = MI . getOperand ( <NUM_LIT> ) ; assert ( Imm4Op . isImm ( ) && <STR_LIT> ) ; MI . addOperand ( Imm4Op ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MI . insert ( MI . begin ( ) , MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : MI . insert ( MI . begin ( ) + <NUM_LIT> , MCOperand :: createReg ( <STR_LIT> ) ) ; break ; } if ( Result != MCDisassembler :: Fail ) return Result ; } return MCDisassembler :: Fail ;


<s> if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SUBREG ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && CONST_OK_FOR_ADD ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) return <NUM_LIT> ; if ( TARGET_SHMEDIA ) switch ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ) { case CONST :


<s> CC = ITBlock . getITCC ( ) ; if ( CC == <NUM_LIT> ) CC = <STR_LIT> ; if ( ITBlock . instrInITBlock ( ) ) ITBlock . advanceITState ( ) ; else if ( VPTBlock . instrInVPTBlock ( ) ) { CC = VPTBlock . getVPTPred ( ) ; VPTBlock . advanceVPTState ( ) ; } const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; MCInst :: iterator I = MI . begin ( ) ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( OpInfo [ i ] . isPredicate ( ) ) { if ( CC != <STR_LIT> && ! <ISA_LIT>Insts [ MI . getOpcode ( ) ] . isPredicable ( ) ) Check ( S , SoftFail ) ; I -> setImm ( CC ) ; ++ I ; if ( CC == <STR_LIT> ) I -> setReg ( <NUM_LIT> ) ; else I -> setReg ( <STR_LIT> ) ;


<s> switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) - STI -> isTargetDarwin ( ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> extern __inline float __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtsbh_ss ( __bfloat16 __A ) { union { float a ; unsigned int b ; } __tmp ; __tmp . b = ( ( unsigned int ) ( __A ) ) << <NUM_LIT> ;


<s> PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & <ISA_LIT>ExpandCondsets :: ID , <NUM_LIT> , false , false ) ; Registry . registerPass ( * PI , true ) ;


<s> return std :: make_pair ( LocalSizeY , LocalSizeZ ) ; } assert ( IsAMDGCN ) ; Function * DispatchPtrFn = <STR_LIT> ( Mod , <STR_LIT> ) ; CallInst * DispatchPtr = Builder . CreateCall ( DispatchPtrFn , { } ) ; DispatchPtr -> addAttribute ( AttributeList :: ReturnIndex , Attribute :: NoAlias ) ; DispatchPtr -> addAttribute ( AttributeList :: ReturnIndex , Attribute :: NonNull ) ; DispatchPtr -> addDereferenceableAttr ( AttributeList :: ReturnIndex , <NUM_LIT> ) ; Type * I32Ty = Type :: getInt32Ty ( Mod -> getContext ( ) ) ; Value * CastDispatchPtr = Builder . CreateBitCast ( DispatchPtr , PointerType :: get ( I32Ty , AS . CONSTANT_ADDRESS ) ) ; Value * GEPXY = Builder . CreateConstInBoundsGEP1_64 ( CastDispatchPtr , <NUM_LIT> ) ; LoadInst * LoadXY = Builder . CreateAlignedLoad ( GEPXY , <NUM_LIT> ) ; Value * GEPZU = Builder . CreateConstInBoundsGEP1_64 ( CastDispatchPtr , <NUM_LIT> ) ; LoadInst * LoadZU = Builder . CreateAlignedLoad ( GEPZU , <NUM_LIT> ) ; MDNode * MD = MDNode :: get ( Mod -> getContext ( ) , None ) ; LoadXY -> setMetadata ( LLVMContext :: MD_invariant_load , MD ) ; LoadZU -> setMetadata ( LLVMContext :: MD_invariant_load , MD ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , MemStart , ExprEnd ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } else { SMLoc LParenLoc = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) || getLexer ( ) . is ( AsmToken :: Comma ) ) { } else { SMLoc ExprEnd ; if ( getParser ( ) . parseParenExpression ( Disp , ExprEnd ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { if ( SegReg == <NUM_LIT> ) return <STR_LIT> ( getPointerWidth ( ) , Disp , LParenLoc , ExprEnd ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , MemStart , ExprEnd ) ; } Parser . Lex ( ) ; } } unsigned BaseReg = <NUM_LIT> , IndexReg = <NUM_LIT> , Scale = <NUM_LIT> ; SMLoc IndexLoc , BaseLoc ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc StartLoc , EndLoc ; BaseLoc = Parser . getTok ( ) . getLoc ( ) ; if ( ParseRegister ( BaseReg , StartLoc , EndLoc ) ) return nullptr ; if ( BaseReg == <STR_LIT> || BaseReg == <STR_LIT> ) { Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return nullptr ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) {


<s> return ( __a - ( __b * __aarch64_vget_lane_any ( __c , __lane ) ) ) ;


assert ( isCRBitMask ( ) && <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isConditionalStore ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> auto RegMask = Prev -> getOperand ( <NUM_LIT> ) ; auto & RegClass = Is64Bit ? <STR_LIT> : <STR_LIT> ; for ( auto Candidate : RegClass ) { if ( ! RegMask . clobbersPhysReg ( Candidate ) ) continue ; bool IsDef = false ; for ( const MachineOperand & MO : Prev -> implicit_operands ( ) ) { if ( MO . isReg ( ) && MO . isDef ( ) && ( TRI -> isSubRegisterEq ( MO . getReg ( ) , Candidate ) || TRI -> isSuperRegister ( MO . getReg ( ) , Candidate ) ) ) { IsDef = true ; break ; } } if ( IsDef ) continue ; Regs [ FoundRegs ++ ] = Candidate ; if ( FoundRegs == ( unsigned ) NumPops ) break ; }

if ( FoundRegs == <NUM_LIT> ) return false ;


<s> SDValue CondRes = Op . getOperand ( <NUM_LIT> ) ; SDValue CCNode = CondRes . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue ( ) ;

SDValue BrCode = DAG . getConstant ( GetFPBranchCodeFromCond ( CC ) , <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> break ; default : return true ; } return printAsmRegInClass ( MO , RC , <STR_LIT> , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; unsigned AltName = <STR_LIT> ; const TargetRegisterClass * RegClass ; if ( <STR_LIT> . contains ( Reg ) ) { RegClass = & <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg ) ) { RegClass = & <STR_LIT> ; } else { RegClass = & <STR_LIT> ; AltName = <STR_LIT> ; }

return printAsmRegInClass ( MO , RegClass , AltName , O ) ;


<s> O << '(' ; printOperand ( MI , OpNo + <NUM_LIT> , O ) ;


<s> int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) { rtx sub = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( GET_CODE ( sub ) == USE ) { sub = XEXP ( sub , <NUM_LIT> ) ; if ( GET_CODE ( sub ) == UNSPEC && XINT ( sub , <NUM_LIT> ) == UNSPEC_TOC ) return ret ; } } } else if ( crtl -> has_bb_partition && NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) ret = <NUM_LIT> ; }


<s> if ( op == EQ || op == NE || op == GTU || op == LEU || op == LT || op == GE ) return CC_NZmode ; gcc_assert ( op == GEU || op == LTU || op == GT || op == LE ) ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) break ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; int UpdateOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) UpdateOffset = - UpdateOffset ; if ( ! IsPairedInsn && ( UpdateOffset > <NUM_LIT> || UpdateOffset < - <NUM_LIT> ) ) break ; if ( IsPairedInsn ) { int Scale = getMemScale ( MemMI ) ; if ( UpdateOffset % Scale != <NUM_LIT> ) break ; int ScaledOffset = UpdateOffset / Scale ; if ( ScaledOffset > <NUM_LIT> || ScaledOffset < - <NUM_LIT> ) break ; } if ( ! Offset || Offset == UpdateOffset ) return true ; break ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & ctx , <ISA_LIT>AsmPrinter & asmprinter ) : Ctx ( ctx ) , AsmPrinter ( asmprinter ) {


<s> __vector signed int c ; __vector signed int zero = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ;

a = ( __vector signed short ) vec_splats ( __m1 ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> const MCRegisterClass * RC_out = ( VectorList . Count == <NUM_LIT> ) ? & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] : & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; unsigned I , E = RC_out -> getNumRegs ( ) ; for ( I = <NUM_LIT> ; I < E ; I ++ ) if ( RC_in -> getRegister ( I ) == VectorList . RegNum ) break ; assert ( I < E && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( RC_out -> getRegister ( I ) ) ) ;


<s> const TargetSelectionDAGInfo * getSelectionDAGInfo ( ) const override {


<s> label = gen_label_rtx ( ) ; rtx tmp = gen_rtx_fmt_ee ( UNORDERED , VOIDmode , flag , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; } if ( GET_MODE ( set_dst ) != mode ) { gcc_assert ( mode == CCAmode || mode == CCCmode || mode == CCOmode || mode == CCPmode || mode == CCSmode || mode == CCZmode ) ;

set_dst = gen_rtx_REG ( mode , FLAGS_REG ) ;


<s> return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( LT . second != TLI -> getValueType ( DL , SrcVTy ) . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_Alternate , SrcVTy , <NUM_LIT> , <NUM_LIT> ) + getShuffleCost ( TTI :: SK_Alternate , MaskTy , <NUM_LIT> , <NUM_LIT> ) ; else if ( LT . second . getVectorNumElements ( ) > NumElem ) { VectorType * NewMaskTy = VectorType :: get ( MaskTy -> getVectorElementType ( ) , LT . second . getVectorNumElements ( ) ) ; Cost += getShuffleCost ( TTI :: SK_InsertSubvector , NewMaskTy , <NUM_LIT> , MaskTy ) ;


<s> assert ( MinI != LL . end ( ) ) ; IFRecordWithRegSet M = * MinI ; LL . clear ( ) ; RegisterSet Us ; const MachineInstr * DefI = MRI -> getVRegDef ( I -> first ) ; getInstrUses ( DefI , Us ) ; bool Accept = false ; if ( SelectAll0 ) { bool All0 = true ; for ( unsigned R = Us . find_first ( ) ; R ; R = Us . find_next ( R ) ) { if ( UseC [ R ] == <NUM_LIT> ) continue ; All0 = false ; break ; } Accept = All0 ; } else if ( SelectHas0 ) { bool Has0 = false ; for ( unsigned R = Us . find_first ( ) ; R ; R = Us . find_next ( R ) ) { if ( UseC [ R ] != <NUM_LIT> ) continue ; Has0 = true ; break ; } Accept = Has0 ; } if ( Accept ) LL . push_back ( M ) ; } AllRMs . clear ( ) ; for ( IFMapType :: iterator I = IFMap . begin ( ) ; I != End ; ++ I ) { const IFListType & LL = I -> second ; if ( ! LL . empty ( ) ) AllRMs . insert ( LL [ <NUM_LIT> ] . second ) ; } for ( IFMapType :: iterator I = IFMap . begin ( ) ; I != End ; ++ I ) { IFListType & LL = I -> second ; if ( LL . empty ( ) ) continue ; unsigned SR = LL [ <NUM_LIT> ] . first . SrcR , IR = LL [ <NUM_LIT> ] . first . InsR ; if ( AllRMs [ SR ] || AllRMs [ IR ] ) LL . clear ( ) ; } pruneEmptyLists ( ) ;


<s> const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return <NUM_LIT> ; if ( SC -> BeginGroup ) { if ( CurrGroupSize ) return <NUM_LIT> - CurrGroupSize ; return - <NUM_LIT> ; }


<s> if ( MDs . empty ( ) ) return ; for ( const Metadata * MD : MDs ) { if ( IndexPos ) IndexPos -> push_back ( Stream . GetCurrentBitNo ( ) ) ; if ( const MDNode * N = dyn_cast < MDNode > ( MD ) ) { assert ( N -> isResolved ( ) && <STR_LIT> ) ; switch ( N -> getMetadataID ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Metadata :: CLASS ## Kind : \ if ( MDAbbrevs ) \ write ## CLASS ( cast < CLASS > ( N ) , Record , \ ( * MDAbbrevs ) [ MetadataAbbrev :: CLASS ## AbbrevID ] ) ; \ else \ write ## CLASS ( cast < CLASS > ( N ) , Record , CLASS ## Abbrev ) ; \ continue ; } } writeValueAsMetadata ( cast < ValueAsMetadata > ( MD ) , Record ) ; }


<s> case <STR_LIT> : isSigned = false ; LC = RTLIB :: UDIVREM_I128 ; break ; } SDLoc dl ( Op ) ; SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; assert ( ArgVT . isInteger ( ) && ArgVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue StackPtr = DAG . CreateStackTemporary ( ArgVT , <NUM_LIT> ) ; Entry . Node = StackPtr ; InChain = DAG . getStore ( InChain , dl , Op -> getOperand ( i ) , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Ty = PointerType :: get ( ArgTy , <NUM_LIT> ) ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , static_cast < EVT > ( <STR_LIT> ) . getTypeForEVT ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) , <NUM_LIT> ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ;

return DAG . getBitcast ( VT , CallInfo . first ) ;


<s> uint32_t rot_imm = ( imm >> rot ) | ( imm << ( ( <NUM_LIT> - rot ) & <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( rot_imm ) ) ;


<s> case RECORD_TYPE : return ( qualifiers | <NUM_LIT> ) ; case UNION_TYPE : case QUAL_UNION_TYPE : return ( qualifiers | <NUM_LIT> ) ; case ENUMERAL_TYPE : return ( qualifiers | <NUM_LIT> ) ; case VOID_TYPE : return ( qualifiers | <NUM_LIT> ) ; case INTEGER_TYPE : if ( TREE_TYPE ( type ) != <NUM_LIT> ) break ; if ( TYPE_PRECISION ( type ) <= CHAR_TYPE_SIZE ) return ( qualifiers | ( TYPE_UNSIGNED ( type ) ? <NUM_LIT> : <NUM_LIT> ) ) ; else if ( TYPE_PRECISION ( type ) <= SHORT_TYPE_SIZE ) return ( qualifiers | ( TYPE_UNSIGNED ( type ) ? <NUM_LIT> : <NUM_LIT> ) ) ; else if ( TYPE_PRECISION ( type ) <= INT_TYPE_SIZE ) return ( qualifiers | ( TYPE_UNSIGNED ( type ) ? <NUM_LIT> : <NUM_LIT> ) ) ; else return ( qualifiers | ( TYPE_UNSIGNED ( type ) ? <NUM_LIT> : <NUM_LIT> ) ) ; case REAL_TYPE : if ( TREE_TYPE ( type ) != <NUM_LIT> ) break ; if ( TYPE_PRECISION ( type ) == FLOAT_TYPE_SIZE ) return ( qualifiers | <NUM_LIT> ) ; else return ( qualifiers | <NUM_LIT> ) ; case COMPLEX_TYPE :


<s> Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , HiReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , LoReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ReadAgainReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( HiReg ) . addReg ( ReadAgainReg ) . addMBB ( LoopMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; MI . eraseFromParent ( ) ; return DoneMBB ;


<s> SDValue PtrLo = DAG -> getTargetExtractSubreg ( AMDGPU :: sub0 , DL , <STR_LIT> , Ptr ) ; SDValue PtrHi = DAG -> getTargetExtractSubreg ( AMDGPU :: sub1 , DL , <STR_LIT> , Ptr ) ; if ( RsrcDword1 ) PtrHi = SDValue ( DAG -> getMachineNode ( AMDGPU :: S_OR_B32 , DL , <STR_LIT> , PtrHi , DAG -> getConstant ( RsrcDword1 , <STR_LIT> ) ) , <NUM_LIT> ) ; SDValue DataLo = DAG -> getTargetConstant ( RsrcDword2And3 & APInt :: getAllOnesValue ( <NUM_LIT> ) . getZExtValue ( ) , <STR_LIT> ) ; SDValue DataHi = DAG -> getTargetConstant ( RsrcDword2And3 >> <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { PtrLo , PtrHi , DataLo , DataHi } ;

return SDValue ( DAG -> getMachineNode ( AMDGPU :: <ISA_LIT>_BUFFER_RSRC , DL , <STR_LIT> , Ops ) , <NUM_LIT> ) ;


<s> bool isOffsetS13 ( ) const { return ( isImmTy ( ImmTyOffset ) || isImmTy ( ImmTyInstOffset ) ) && isInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> break ; case CR16_REGP_REL : cost += <NUM_LIT> ; case CR16_REG_REL : cost += <NUM_LIT> ; if ( address . disp ) cost -= <NUM_LIT> ; break ; case CR16_INDEX_REGP_REL : cost += <NUM_LIT> ; if ( address . disp ) cost -= <NUM_LIT> ; default : break ; } if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> , cost ) ; debug_rtx ( addr ) ;


<s> } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; unsigned shift ; if ( U ) shift = <STR_LIT> ( <STR_LIT> , imm , ShOp ) ;

else shift = <STR_LIT> ( <STR_LIT> , imm , ShOp ) ;


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = mips_epilogue . cfa_restores ;


<s> assert ( Kind == k_InstSyncBarrierOpt && <STR_LIT> ) ;


<s> if ( FeatureKind == <STR_LIT> ) Error ( ExtLoc , <STR_LIT> + Name ) ; for ( const auto & Extension : Extensions ) { if ( Extension . Kind != FeatureKind ) continue ; if ( Extension . Features . none ( ) ) report_fatal_error ( <STR_LIT> + Name ) ; if ( ( getAvailableFeatures ( ) & Extension . ArchCheck ) != Extension . ArchCheck ) { Error ( ExtLoc , <STR_LIT> + Name + <STR_LIT> <STR_LIT> ) ; return false ; } MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ STI . getFeatureBits ( ) & Extension . Features ) : ( STI . getFeatureBits ( ) & Extension . Features ) ; uint64_t Features = ComputeAvailableFeatures ( STI . ToggleFeature ( ToggleFeatures ) ) ; setAvailableFeatures ( Features ) ; return false ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) { if ( InstrumentSandboxingCFI ) removeCall64m ( MF ) ; addBoundChecks ( MF ) ; return <NUM_LIT> ;


<s> void PolynomialMultiplyRecognize :: cleanupLoopBody ( BasicBlock * LoopB ) { for ( auto & I : * LoopB ) if ( Value * SV = SimplifyInstruction ( & I , DL , & TLI , & DT ) ) I . replaceAllUsesWith ( SV ) ;

for ( auto I = LoopB -> begin ( ) , N = I ; I != LoopB -> end ( ) ; I = N ) {


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , <STR_LIT> , <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZ , false ) ; break ; case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> : setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , RealTimeProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , MicroControllerProfile , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> : setAttributeItem ( CPU_arch_profile , ApplicationProfile , false ) ; setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; setAttributeItem ( MPextension_use , Allowed , false ) ; setAttributeItem ( Virtualization_use , AllowTZVirtualization , false ) ; break ; case <STR_LIT> : setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; setAttributeItem ( WMMX_arch , AllowWMMXv1 , false ) ; break ; case <STR_LIT> :


<s> static bool isMOVSLDUPMask ( ArrayRef < int > Mask , EVT VT , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasSSE3 ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ;

if ( ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) || ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) ) return false ;


<s> rtx return_reg ; int only_popret_RA = ( save_regs [ RETURN_ADDRESS_REGNUM ] && ( sum_regs == UNITS_PER_WORD ) ) ; return_reg = gen_rtx_REG ( Pmode , RETURN_ADDRESS_REGNUM ) ; if ( frame_pointer_needed ) emit_move_insn ( stack_pointer_rtx , frame_pointer_rtx ) ; if ( size_for_adjusting_sp > <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( size_for_adjusting_sp ) ) ) ; if ( crx_interrupt_function_p ( ) ) emit_jump_insn ( gen_interrupt_return ( ) ) ; else if ( last_reg_to_save == - <NUM_LIT> ) emit_jump_insn ( gen_indirect_jump_return ( ) ) ; else if ( only_popret_RA ) emit_jump_insn ( gen_popret_RA_return ( ) ) ;

else emit_jump_insn ( gen_pop_and_popret_return ( GEN_INT ( sum_regs ) ) ) ;


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } unsigned SoImm = MO . getImm ( ) ; unsigned Encoded = <STR_LIT> ( SoImm ) ; assert ( Encoded != ~ <NUM_LIT> && <STR_LIT> ) ; return Encoded ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> for ( unsigned ShiftVal = <NUM_LIT> ; ShiftVal < Size ; ShiftVal += PlatRegSize ) {

APInt Chunk = Val . ashr ( ShiftVal ) . sextOrTrunc ( PlatRegSize ) ;


default : llvm_unreachable ( <STR_LIT> ) ;


<s> } } else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) { switch ( mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) {

switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) {


<s> if ( GET_CODE ( x ) == ZERO_EXTRACT || GET_CODE ( x ) == ZERO_EXTEND || GET_CODE ( x ) == SIGN_EXTEND ) x = XEXP ( x , <NUM_LIT> ) ; if ( MEM_P ( x ) ) continue ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) return true ; else if ( BINARY_P ( x ) && ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) || CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) ) { rtx stride = ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ? XEXP ( x , <NUM_LIT> ) : XEXP ( x , <NUM_LIT> ) ) ; if ( INTVAL ( stride ) < MAX_PREFETCH_STRIDE ) return true ; } } } return false ;


<s> if ( ( Mnemonic == <STR_LIT> && isThumb ( ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) return Mnemonic ; if ( Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) { unsigned CC = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( CC != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; PredicationCode = CC ; } } if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) {


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSLDM : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ;

case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ;


<s> inline static const char * IFlagsToString ( unsigned val ) { switch ( val ) { default : llvm_unreachable ( <STR_LIT> ) ; case F : return <STR_LIT> ; case I : return <STR_LIT> ; case A : return <STR_LIT> ; }


<s> this -> L = L ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ST -> hasV8_1MMainlineOps ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations ( Preheader ) ; if ( ! Setup ) {

if ( ! Preheader -> getSinglePredecessor ( ) ) return false ;


<s> list -> quick_push ( b ) ; for ( unsigned ix = <NUM_LIT> ; ix ; ix -- ) { vec < edge , va_gc > * edges = dir > <NUM_LIT> ? b -> succs : b -> preds ; size_t offset = ( dir > <NUM_LIT> ? offsetof ( edge_def , dest ) : offsetof ( edge_def , src ) ) ; edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , edges ) {

basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ;


<s> if ( SYMBOL_REF_ZDA_P ( x ) ) fprintf ( file , <STR_LIT> ) ; else if ( SYMBOL_REF_SDA_P ( x ) ) fprintf ( file , <STR_LIT> ) ; else if ( SYMBOL_REF_TDA_P ( x ) ) fprintf ( file , <STR_LIT> ) ; else gcc_unreachable ( ) ; break ; case 'R' : switch ( GET_CODE ( x ) ) { case REG : fprintf ( file , reg_names [ REGNO ( x ) + <NUM_LIT> ] ) ; break ; case MEM : x = XEXP ( adjust_address ( x , SImode , <NUM_LIT> ) , <NUM_LIT> ) ; print_operand_address ( file , x ) ; if ( GET_CODE ( x ) == CONST_INT ) fprintf ( file , <STR_LIT> ) ; break ; default : break ; } break ; case 'S' : { if ( GET_CODE ( x ) == MEM && ep_memory_operand ( x , GET_MODE ( x ) , FALSE ) ) fputs ( <STR_LIT> , file ) ; break ; } case 'T' : { if ( GET_CODE ( x ) == MEM && ep_memory_operand ( x , GET_MODE ( x ) , TRUE ) ) fputs ( <STR_LIT> , file ) ; break ; } case 'W' : switch ( GET_MODE ( x ) ) { default : gcc_unreachable ( ) ; case QImode : fputs ( <STR_LIT> , file ) ; break ; case HImode : fputs ( <STR_LIT> , file ) ; break ; case SImode : fputs ( <STR_LIT> , file ) ; break ; case SFmode : fputs ( <STR_LIT> , file ) ; break ; } break ; case '.' : fputs ( reg_names [ <NUM_LIT> ] , file ) ; break ; case 'z' : if ( GET_CODE ( x ) == REG ) fputs ( reg_names [ REGNO ( x ) ] , file ) ; else { gcc_assert ( x == const0_rtx ) ; fputs ( reg_names [ <NUM_LIT> ] , file ) ; } break ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> else if ( Instruction * LogicI = dyn_cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( CmpInst * CI0 = dyn_cast < CmpInst > ( LogicI -> getOperand ( <NUM_LIT> ) ) ) if ( isa < CmpInst > ( LogicI -> getOperand ( <NUM_LIT> ) ) ) OpTy = CI0 -> getOperand ( <NUM_LIT> ) -> getType ( ) ; if ( OpTy != nullptr ) {


<s> return new <ISA_LIT>ExpandPseudo ( ) ;


<s> assert ( Op . getNumOperands ( ) == <NUM_LIT> && VT == Op . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Amt = Op . getOperand ( <NUM_LIT> ) ; EVT AmtVT = Amt . getValueType ( ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , AmtVT , DAG . getConstant ( BitWidth , AmtVT ) , Amt ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , Hi , Amt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp1 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp2 , Tmp3 ) ; SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ;

SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ;


<s> return false ; } if ( ! Section ) { getStreamer ( ) . InitSections ( ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; }


<s> if ( GET_MODE_CLASS ( GET_MODE ( x ) ) != MODE_VECTOR_FLOAT ) return false ; x0 = CONST_VECTOR_ELT ( x , <NUM_LIT> ) ; if ( ! CONST_DOUBLE_P ( x0 ) ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r0 , x0 ) ; for ( i = <NUM_LIT> ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) { xi = CONST_VECTOR_ELT ( x , i ) ; if ( ! CONST_DOUBLE_P ( xi ) ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( ri , xi ) ;

if ( ! REAL_VALUES_EQUAL ( r0 , ri ) ) return false ;


<s> header |= HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE ; header |= HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE ; header |= HSA_PACKET_TYPE_KERNEL_DISPATCH << HSA_PACKET_HEADER_TYPE ; __atomic_store_n ( ( uint32_t * ) dispatch_packet , header | ( dispatch_packet -> setup << <NUM_LIT> ) , __ATOMIC_RELEASE ) ; if ( debug ) fprintf ( stderr , <STR_LIT> ) ; hsa_fns . hsa_queue_store_write_index_relaxed_fn ( queue , index + <NUM_LIT> ) ; hsa_fns . hsa_signal_store_relaxed_fn ( queue -> doorbell_signal , index ) ; while ( hsa_fns . hsa_signal_wait_relaxed_fn ( signal , HSA_SIGNAL_CONDITION_LT , <NUM_LIT> , <NUM_LIT> , HSA_WAIT_STATE_ACTIVE ) != <NUM_LIT> ) { usleep ( <NUM_LIT> ) ; gomp_print_output ( kernargs , false ) ;


<s> return __builtin_mve_vaddq_n_fv8hf ( __a , __b ) ;


<s> if ( ! TARGET_FAST_INDIRECT_CALLS ) fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' , asm_out_file ) ; return true ;


<s> } else { Chain = CurDAG -> getCopyToReg ( Chain , dl , <STR_LIT> , Addr , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = SDValue ( CurDAG -> getTargetNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Chain , InFlag ) , <NUM_LIT> ) ; } InFlag = Chain . getValue ( <NUM_LIT> ) ; ReplaceUses ( Op . getValue ( <NUM_LIT> ) , Chain ) ; ReplaceUses ( Op . getValue ( <NUM_LIT> ) , InFlag ) ;


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const {


<s> AI . isValid ( ) ; ++ AI ) if ( RegSet . count ( * AI ) ) return true ;


<s> return ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) ) || ( VT == <STR_LIT> && Subtarget . hasStdExtD ( ) ) ;


<s> alpha_pre_atomic_barrier ( mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_load_locked ( DImode , scratch , mem ) ; width = GEN_INT ( GET_MODE_BITSIZE ( mode ) ) ; mask = GEN_INT ( mode == QImode ? <NUM_LIT> : <NUM_LIT> ) ; emit_insn ( gen_extxl ( dest , scratch , width , addr ) ) ; if ( oldval == const0_rtx ) { emit_move_insn ( cond , const0_rtx ) ; x = gen_rtx_NE ( DImode , dest , const0_rtx ) ; } else { x = gen_rtx_EQ ( DImode , dest , oldval ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cond , x ) ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; } emit_unlikely_jump ( x , label2 ) ; emit_insn ( gen_mskxl ( cond , scratch , mask , addr ) ) ;

if ( newval != const0_rtx ) emit_insn ( gen_iordi3 ( cond , cond , newval ) ) ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( ST -> getTargetLowering ( ) ) {