<s> int FI = SI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( SI -> getOperand ( <NUM_LIT> ) . getReg ( ) != FIReg || MFI -> isFixedObjectIndex ( FI ) || MFI -> getObjectSize ( FI ) != <NUM_LIT> ) continue ; if ( SI -> getOperand ( <NUM_LIT> ) . isDef ( ) ) break ; if ( SI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << I -> getOperand ( <NUM_LIT> ) . getIndex ( ) << <STR_LIT> ) ; EraseInstr . push_back ( I ) ; } EraseInstr . push_back ( SI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> ) ; FrameRelocate . push_back ( std :: make_pair ( FI , StackOffset ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> << StackOffset << <STR_LIT> ) ; StackOffset -= <NUM_LIT> ; StackAdjust += <NUM_LIT> ; break ; } } } for ( MachineRegisterInfo :: livein_iterator LI = LII ; LI != LIE ; ++ LI ) { for ( MachineBasicBlock :: iterator I = MIB ; I != MIE ; ++ I ) { if ( I -> definesRegister ( LI -> first ) ) break ; if ( I -> getOpcode ( ) != <STR_LIT> || I -> getNumOperands ( ) != <NUM_LIT> || ! I -> getOperand ( <NUM_LIT> ) . isFI ( ) || ! I -> getOperand ( <NUM_LIT> ) . isReg ( ) || I -> getOperand ( <NUM_LIT> ) . getIndex ( ) < <NUM_LIT> ) continue ; if ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) == LI -> first ) { int FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; <ISA_LIT>FI -> recordLiveIn ( FI ) ; int FILoc = <NUM_LIT> ; switch ( LI -> first ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FILoc = - <NUM_LIT> ; break ; case <STR_LIT> : FILoc = - <NUM_LIT> ; break ; case <STR_LIT> : FILoc = - <NUM_LIT> ; break ; case <STR_LIT> : FILoc = - <NUM_LIT> ; break ; case <STR_LIT> : FILoc = - <NUM_LIT> ; break ; case <STR_LIT> : FILoc = - <NUM_LIT> ; break ;


<s> return ( __m64 ) __builtin_arm_wrorh ( ( __v4hi ) __m , __count ) ;


<s> const MachineInstr * L2 = * Entry . second . begin ( ) ; const MachineInstr * L1 = Entry . first ; if ( ! MDT -> dominates ( L2 , L1 ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * L2 << '\n' << * L1 << '\n' ) ; continue ;


<s> case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: PreserveMost : case CallingConv :: CXX_FAST_TLS : case CallingConv :: Swift : if ( Subtarget -> isTargetWindows ( ) && IsVarArg ) return CC_<ISA_LIT>_Win64_VarArg ; if ( ! Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_AAPCS ; return IsVarArg ? CC_<ISA_LIT>_DarwinPCS_VarArg : CC_<ISA_LIT>_DarwinPCS ; case CallingConv :: Win64 : return IsVarArg ? CC_<ISA_LIT>_Win64_VarArg : CC_<ISA_LIT>_AAPCS ; case CallingConv :: Mono : if ( Subtarget -> isTargetDarwin ( ) ) return CC_<ISA_LIT>_Mono_DarwinPCS ; else if ( Subtarget -> isTargetWindows ( ) ) report_fatal_error ( <STR_LIT> ) ; else return CC_<ISA_LIT>_Mono_AAPCS ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const {


<s> return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: getNegatedExpression ( SDValue Op , SelectionDAG & DAG , bool LegalOperations , bool ForCodeSize , NegatibleCost & Cost , unsigned Depth ) const { if ( SDValue Arg = isFNEG ( DAG , Op . getNode ( ) , Depth ) ) { Cost = NegatibleCost :: Cheaper ; return DAG . getBitcast ( Op . getValueType ( ) , Arg ) ; } EVT VT = Op . getValueType ( ) ; EVT SVT = VT . getScalarType ( ) ; unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == <STR_LIT> || SVT == <STR_LIT> ) || ! isOperationLegal ( <STR_LIT> , VT ) ) break ; SmallVector < SDValue , <NUM_LIT> > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; bool NegA = ! ! NewOps [ <NUM_LIT> ] ; bool NegB = ! ! NewOps [ <NUM_LIT> ] ; bool NegC = ! ! NewOps [ <NUM_LIT> ] ;

unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerDIV_Windows ( SDValue Op , SelectionDAG & DAG , bool Signed ) const { assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue DBZCHK = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return LowerWindowsDIVLibCall ( Op , DAG , Signed , DBZCHK ) ;


<s> unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ; Value &= <NUM_LIT> ;


<s> <ISA_LIT>CP ( DataFlowGraph & G ) : CopyPropagation ( G ) {


<s> LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = <NUM_LIT> ; unsigned Exec = ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( Exec ) ; if ( ! ( GlobalFlags & StateWWM ) && LowerToCopyInstrs . empty ( ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; MachineInstr * MI = BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , LiveMaskReg ) . addReg ( Exec ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ;


<s> case E_DImode : case E_SFmode : case E_DFmode : if ( ! reload_in_progress && ! reload_completed && ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) src = copy_to_mode_reg ( mode , src ) ; break ; default :


<s> Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Imm ) ) ;


<s> SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ; SDValue CvtHi = DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , Hi ) ; SDValue CvtLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ; SDValue LdExp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CvtHi , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LdExp , CvtLo ) ;


<s> CCState CCInfo ( CallingConv , isVarArg , getTargetMachine ( ) , RVLocs ) ; CCInfo . AnalyzeCallResult ( TheCall , RetCC_<ISA_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > ResultVals ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; ResultVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } ResultVals . push_back ( Chain ) ; return DAG . getNode ( <STR_LIT> , dl , TheCall -> getVTList ( ) , & ResultVals [ <NUM_LIT> ] , ResultVals . size ( ) ) . getNode ( ) ;


<s> switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> - FPDiff ; case <STR_LIT> : return <NUM_LIT> - FPDiff ; case <STR_LIT> :


<s> if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( term ) == PLUS && ( CONST_INT_P ( XEXP ( term , <NUM_LIT> ) ) || GET_CODE ( XEXP ( term , <NUM_LIT> ) ) == CONST_DOUBLE ) ) term = XEXP ( term , <NUM_LIT> ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , <NUM_LIT> ) != UNSPEC_GOTPCREL && XINT ( term , <NUM_LIT> ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , <NUM_LIT> , <NUM_LIT> ) ; }

return ix86_delegitimize_address ( x ) ;


<s> assert ( Kind == Token && <STR_LIT> ) ; return Tok ;


<s> Value = ( Value & <NUM_LIT> ) >> <NUM_LIT> ;

ldi :: fixup ( Size , Fixup , Value , Ctx ) ;


<s> machine_mode result_mode = GET_MODE ( dest ) ; if ( result_mode != compare_mode ) return false ; if ( code == UNGE || code == UNGT || code == UNLE || code == UNLT ) { code = reverse_condition_maybe_unordered ( code ) ; std :: swap ( true_cond , false_cond ) ; } bool max_p ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code == LT ) max_p = false ; else return false ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) && ! HONOR_NANS ( compare_mode ) && ! HONOR_SIGNED_ZEROS ( compare_mode ) ) max_p = ! max_p ; else return false ;

rs6000_emit_minmax ( dest , max_p ? SMAX : SMIN , op0 , op1 ) ;


<s> for ( ConstMIOperands MO ( & MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) ) continue ; unsigned R = MO -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) == & <STR_LIT> ) PredDefs ++ ; }


<s> <ISA_LIT>Operand ( KindTy K , SMLoc Start , SMLoc End ) : Kind ( K ) , StartLoc ( Start ) , EndLoc ( End ) {


<s> Old . ChangeToImmediate ( Fold . ImmToFold ) ; return true ; } MachineOperand * New = Fold . OpToFold ; if ( TargetRegisterInfo :: isVirtualRegister ( Old . getReg ( ) ) && TargetRegisterInfo :: isVirtualRegister ( New -> getReg ( ) ) ) { Old . substVirtReg ( New -> getReg ( ) , New -> getSubReg ( ) , TRI ) ; return true ; }


<s> <ISA_LIT>AsmInstrumentation :: <ISA_LIT>AsmInstrumentation ( const MCSubtargetInfo & STI ) : STI ( STI ) , InitialFrameReg ( <NUM_LIT> ) {


<s> if ( MO . isExpr ( ) ) { MCFixupKind FixupKind = static_cast < MCFixupKind > ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } assert ( MO . isImm ( ) ) ; auto Target = MO . getImm ( ) ;

<STR_LIT> :: adjustBranchTarget ( Target ) ;


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ;


<s> Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return NULL ; }

return CurDAG -> getMachineNode ( Opcode , N -> getDebugLoc ( ) , VT , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , LD -> getChain ( ) ) ;


<s> <ISA_LIT>ShiftExpand ( ) : FunctionPass ( ID ) {


<s> EVT getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const override { return <STR_LIT> ;


<s> return ( __m256i ) __builtin_ia32_pbroadcastw256_gpr_mask ( __A , ( __v16hi ) _mm256_setzero_si256 ( ) , __M ) ;


<s> if ( SelectVOP3ModsImpl ( In , Src , Mods , false ) ) { SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ; return true ; } return false ;


<s> case 'd' : if ( CONST_INT_P ( op ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( op ) ) ; else output_operand_lossage ( <STR_LIT> , letter ) ; break ; case 'm' : if ( CONST_INT_P ( op ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( op ) - <NUM_LIT> ) ; else output_operand_lossage ( <STR_LIT> , letter ) ; break ; case 'y' : if ( CONST_INT_P ( op ) ) { int val = exact_log2 ( INTVAL ( op ) ) ; if ( val != - <NUM_LIT> ) fprintf ( file , <STR_LIT> , val ) ; else output_operand_lossage ( <STR_LIT> , letter ) ; } else output_operand_lossage ( <STR_LIT> , letter ) ; break ; case 'h' : if ( code == HIGH ) op = XEXP ( op , <NUM_LIT> ) ; mips_print_operand_reloc ( file , op , SYMBOL_CONTEXT_LEA , mips_hi_relocs ) ; break ; case 'R' : mips_print_operand_reloc ( file , op , SYMBOL_CONTEXT_LEA , mips_lo_relocs ) ; break ; case 'C' : mips_print_int_branch_condition ( file , code , letter ) ; break ; case 'N' : mips_print_int_branch_condition ( file , reverse_condition ( code ) , letter ) ; break ; case 'F' : mips_print_float_branch_condition ( file , code , letter ) ; break ; case 'W' : mips_print_float_branch_condition ( file , reverse_condition ( code ) , letter ) ; break ; case 'T' : case 't' : { int truth = ( code == NE ) == ( letter == 'T' ) ; fputc ( <STR_LIT> [ truth * <NUM_LIT> + ST_REG_P ( REGNO ( XEXP ( op , <NUM_LIT> ) ) ) ] , file ) ; } break ; case 'Y' : if ( code == CONST_INT && UINTVAL ( op ) < ARRAY_SIZE ( mips_fp_conditions ) ) fputs ( mips_fp_conditions [ UINTVAL ( op ) ] , file ) ; else output_operand_lossage ( <STR_LIT> , letter ) ; break ; case 'Z' : if ( ISA_HAS_8CC || ISA_HAS_CCF ) { mips_print_operand ( file , op , <NUM_LIT> ) ; fputc ( ',' , file ) ; } break ; case 'q' : if ( code == REG && MD_REG_P ( REGNO ( op ) ) ) fprintf ( file , <STR_LIT> ) ; else if ( code == REG && DSP_ACC_REG_P ( REGNO ( op ) ) ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] [ <NUM_LIT> ] ) ; else output_operand_lossage ( <STR_LIT> , letter ) ; break ; default : switch ( code ) { case REG : { unsigned int regno = REGNO ( op ) ; if ( ( letter == 'M' && TARGET_LITTLE_ENDIAN ) || ( letter == 'L' && TARGET_BIG_ENDIAN ) || letter == 'D' ) regno ++ ; else if ( letter && letter != 'z' && letter != 'M' && letter != 'L' ) output_operand_lossage ( <STR_LIT> , letter ) ;

if ( COP0_REG_P ( regno ) ) fprintf ( file , <STR_LIT> , & reg_names [ regno ] [ <NUM_LIT> ] ) ;


<s> } if ( ElemTy . isPointerTy ( ) ) { return true ; } if ( ElemTy . isFloatTy ( ) || ElemTy . isDoubleTy ( ) ) { return true ;


<s> insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ; return insn ;


<s> } if ( RanOutOfSGPRs ) Ctx . emitError ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i != e ; ++ i , Offset += <NUM_LIT> ) { unsigned SubReg = NumSubRegs > <NUM_LIT> ? getPhysRegSubReg ( Value , & <STR_LIT> , i ) : Value ; BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . addReg ( SubReg , getDefRegState ( IsLoad ) ) . addReg ( ScratchRsrcReg ) . addReg ( SOffset ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( Value , RegState :: Implicit | getDefRegState ( IsLoad ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; }


<s> bool <ISA_LIT>AsmPrinter :: UseReadOnlyJumpTables ( ) const {


<s> static bool isSimpleShift ( SDValue N , unsigned & ShiftVal ) { ConstantSDNode * Shift = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ;


<s> static void vms_pragma_pointer_size ( cpp_reader * ARG_UNUSED ( dummy ) ) { if ( flag_vms_pointer_size == VMS_POINTER_SIZE_NONE ) return ; handle_pragma_pointer_size ( <STR_LIT> ) ;


<s> void <ISA_LIT>FlagsCopyLoweringPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> MI = Temp ; MBB . erase ( II ) ; break ; } case <STR_LIT> : { Register NewReg ; if ( STI . hasE2 ( ) ) { NewReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , NewReg ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { NewReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , NewReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NewReg , RegState :: Define ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define ) . addReg ( NewReg , getKillRegState ( true ) ) . addReg ( NewReg , getKillRegState ( true ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( NewReg ) . addImm ( <NUM_LIT> ) ; } MI = BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NewReg , getKillRegState ( true ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . getInstr ( ) ; MBB . erase ( II ) ; break ; } } int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) . getFixed ( ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) report_fatal_error ( <STR_LIT> ) ; bool FrameRegIsKill = false ; MachineBasicBlock :: iterator NewII ( MI ) ; if ( ! IsLegalOffset ( TII , MI , Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; assert ( Offset >= <NUM_LIT> ) ; Register ScratchReg = TII -> movImm ( MBB , NewII , DL , Offset ) ; BuildMI ( MBB , NewII , DL , TII -> get ( STI . hasE2 ( ) ? <STR_LIT> : <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( FrameReg ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ;


<s> if ( Op != <STR_LIT> ) Scratch = ( Scratch & ~ <NUM_LIT> ) | Reader . readBits ( <NUM_LIT> ) ; if ( Op != <STR_LIT> ) { bool DA = ( Op != <STR_LIT> ) && Reader . readBits ( <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) {


<s> int CFGStructurizer < PassT > :: getSCCNum ( BlockT * srcBlk ) { BlockInfo * srcBlkInfo = blockInfoMap [ srcBlk ] ; return srcBlkInfo ? srcBlkInfo -> sccNum : INVALIDSCCNUM ;


<s> for ( ; B != E ; ++ B ) if ( ! B -> isDebugValue ( ) ) return B ;


<s> return ! MI . isPseudo ( ) && ! MI . isMetaInstruction ( ) ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseImmediate ( OperandVector & Operands ) { SMLoc S = getLoc ( ) ; SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * Res ; switch ( getLexer ( ) . getKind ( ) ) { default :


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> } if ( entity == EPIPHANY_MSW_ENTITY_AND ) { gcc_assert ( mode >= <NUM_LIT> && mode <= <NUM_LIT> ) ; if ( mode == <NUM_LIT> ) emit_move_insn ( MACHINE_FUNCTION ( cfun ) -> and_mask , gen_int_mode ( <NUM_LIT> , SImode ) ) ; return ; } else if ( entity == EPIPHANY_MSW_ENTITY_OR ) { gcc_assert ( mode >= <NUM_LIT> && mode <= <NUM_LIT> ) ; if ( mode == <NUM_LIT> ) emit_move_insn ( MACHINE_FUNCTION ( cfun ) -> or_mask , GEN_INT ( <NUM_LIT> ) ) ; return ; } else if ( entity == EPIPHANY_MSW_ENTITY_CONFIG ) { gcc_assert ( mode >= <NUM_LIT> && mode <= <NUM_LIT> ) ; rtx save = get_hard_reg_initial_val ( SImode , CONFIG_REGNUM ) ; if ( mode == <NUM_LIT> ) emit_insn ( gen_save_config ( save ) ) ; return ; } fp_mode = ( enum attr_fp_mode ) mode ; src = NULL_RTX ; switch ( fp_mode ) { case FP_MODE_CALLER : gcc_assert ( entity > EPIPHANY_MSW_ENTITY_CONFIG ) ; src = get_hard_reg_initial_val ( SImode , CONFIG_REGNUM ) ; mask = MACHINE_FUNCTION ( cfun ) -> and_mask ; break ; case FP_MODE_ROUND_UNKNOWN : MACHINE_FUNCTION ( cfun ) -> unknown_mode_sets ++ ; mask = MACHINE_FUNCTION ( cfun ) -> and_mask ; break ; case FP_MODE_ROUND_NEAREST : if ( entity == EPIPHANY_MSW_ENTITY_TRUNC ) return ; mask = MACHINE_FUNCTION ( cfun ) -> and_mask ; break ; case FP_MODE_ROUND_TRUNC : if ( entity == EPIPHANY_MSW_ENTITY_NEAREST ) return ; mask = MACHINE_FUNCTION ( cfun ) -> and_mask ; break ; case FP_MODE_INT : mask = MACHINE_FUNCTION ( cfun ) -> or_mask ; break ; case FP_MODE_NONE : default : gcc_unreachable ( ) ; } save_cc = gen_reg_rtx ( CCmode ) ; cc_reg = gen_rtx_REG ( CCmode , CC_REGNUM ) ; emit_move_insn ( save_cc , cc_reg ) ;


<s> <ISA_LIT>BaseInstrInfo :: <ISA_LIT>BaseInstrInfo ( ) : TargetInstrInfoImpl ( <ISA_LIT>Insts , array_lengthof ( <ISA_LIT>Insts ) ) {


<s> * no_add_attrs = true ; } else if ( ! VOID_TYPE_P ( TREE_TYPE ( TREE_TYPE ( decl ) ) ) ) { error ( <STR_LIT> , name ) ; * no_add_attrs = true ;


<s> I . setOpcode ( Opcode ) ; I . addOperand ( MCOperand :: createReg ( Reg ) ) ; OutStreamer -> emitInstruction ( I , STI ) ;


<s> } auto CanPair = [ & ] ( Reduction & R , BinOpChain * PMul0 , BinOpChain * PMul1 ) { if ( ! PMul0 -> AreSymmetrical ( PMul1 ) ) return false ; for ( unsigned x = <NUM_LIT> ; x < PMul0 -> LHS . size ( ) ; x += <NUM_LIT> ) { auto * Ld0 = dyn_cast < LoadInst > ( PMul0 -> LHS [ x ] ) ; auto * Ld1 = dyn_cast < LoadInst > ( PMul1 -> LHS [ x ] ) ; auto * Ld2 = dyn_cast < LoadInst > ( PMul0 -> RHS [ x ] ) ; auto * Ld3 = dyn_cast < LoadInst > ( PMul1 -> RHS [ x ] ) ; if ( ! Ld0 || ! Ld1 || ! Ld2 || ! Ld3 ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << * Ld0 << <STR_LIT> << <STR_LIT> << * Ld1 << <STR_LIT> << <STR_LIT> << * Ld2 << <STR_LIT> << <STR_LIT> << * Ld3 << <STR_LIT> ) ; if ( AreSequentialLoads ( Ld0 , Ld1 , PMul0 -> VecLd ) ) { if ( AreSequentialLoads ( Ld2 , Ld3 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; R . AddMulPair ( PMul0 , PMul1 ) ; return true ; } else if ( AreSequentialLoads ( Ld3 , Ld2 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMul1 -> Exchange = true ; R . AddMulPair ( PMul0 , PMul1 ) ; return true ; } } else if ( AreSequentialLoads ( Ld1 , Ld0 , PMul0 -> VecLd ) && AreSequentialLoads ( Ld2 , Ld3 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMul0 -> Exchange = true ; R . AddMulPair ( PMul1 , PMul0 ) ; return true ; } } return false ; } ; OpChainList & Muls = R . getMuls ( ) ; const unsigned Elems = Muls . size ( ) ; SmallPtrSet < const Instruction * , <NUM_LIT> > Paired ; for ( unsigned i = <NUM_LIT> ; i < Elems ; ++ i ) { BinOpChain * PMul0 = static_cast < BinOpChain * > ( Muls [ i ] . get ( ) ) ;

if ( Paired . count ( PMul0 -> Root ) ) continue ;


<s> BlockInformation ( ) : isRetired ( false ) , sccNum ( INVALIDSCCNUM ) {


<s> void <ISA_LIT>MCAsmStreamer :: EmitCommonSymbol ( MCSymbol * Symbol , uint64_t Size , unsigned ByteAlignment ) {


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; Register mainDstReg = MRI . createVirtualRegister ( RC ) ; Register fallDstReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( thisMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( fallMBB ) ; thisMBB -> addSuccessor ( mainMBB ) ; thisMBB -> addSuccessor ( fallMBB ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) , mainDstReg ) . addImm ( - <NUM_LIT> ) ; BuildMI ( mainMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) ; mainMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( fallMBB , DL , TII -> get ( <STR_LIT> ) ) ; BuildMI ( fallMBB , DL , TII -> get ( TargetOpcode :: COPY ) , fallDstReg ) . addReg ( <STR_LIT> ) ; fallMBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( mainDstReg ) . addMBB ( mainMBB ) . addReg ( fallDstReg ) . addMBB ( fallMBB ) ;


<s> case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; }


<s> const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const DebugLoc & DL = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; uint64_t CalleePopAmount = IsDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; if ( ! hasReservedCallFrame ( MF ) ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ; assert ( isUInt < <NUM_LIT> > ( Amount ) && <STR_LIT> ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register SPReg = MFI -> getStackPtrOffsetReg ( ) ;

unsigned Op = IsDestroy ? <STR_LIT> : <STR_LIT> ;


<s> const MachineOperand & Op0 = MI . getOperand ( <NUM_LIT> ) ; if ( ! Op0 . isReg ( ) || Reg != Op0 . getReg ( ) ) return None ; if ( Opcode == <STR_LIT> ) Sign = - <NUM_LIT> ; else if ( Opcode != <STR_LIT> ) return None ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ;

Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ;


<s> unsigned Vd = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vd |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned Vm = ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Vm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned op = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . setOpcode ( <STR_LIT> ) ; } if ( hasFullFP16 ) { if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else {


<s> if ( GET_MODE ( arg ) != mode && register_operand ( arg , VOIDmode ) && GET_MODE_SIZE ( GET_MODE ( arg ) ) == GET_MODE_SIZE ( mode ) ) return simplify_gen_subreg ( mode , arg , GET_MODE ( arg ) , <NUM_LIT> ) ;


<s> uint64_t Value = CE -> getValue ( ) ; Inst . addOperand ( MCOperand :: createImm ( ( ~ Value >> Shift ) & <NUM_LIT> ) ) ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> static void ix86_init_platform_type_builtins ( void ) {


<s> unsigned Reg0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Reg0 != Reg1 ) return false ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const TargetInstrDesc & NewTID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewTID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewTID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( TID . hasOptionalDef ( ) ) { unsigned NumOps = TID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , true , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewTID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewTID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = TID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && TID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( SkipPred && TID . OpInfo [ i ] . isPredicate ( ) ) continue ; MIB . addOperand ( MI -> getOperand ( i ) ) ; } DOUT << <STR_LIT> << * MI << <STR_LIT> << * MIB ; MBB . erase ( MI ) ; ++ Num2Addrs ; return true ;


<s> <ISA_LIT>SinglePathInfo :: <ISA_LIT>SinglePathInfo ( const <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , STC ( tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( tm . getInstrInfo ( ) ) ) , Root ( <NUM_LIT> ) {


<s> if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Root = I ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask , Load , PassThru ) ; } Root -> replaceAllUsesWith ( Load ) ;


<s> if ( GET_CODE ( dst ) != REG || REGNO ( dst ) != FLAGS_REG || GET_MODE ( dst ) != CCZmode ) return false ; rtx op1 = XEXP ( src , <NUM_LIT> ) ; rtx op2 = XEXP ( src , <NUM_LIT> ) ; if ( op2 != CONST0_RTX ( GET_MODE ( op2 ) ) ) return false ; if ( GET_CODE ( op1 ) != IOR ) return false ; op2 = XEXP ( op1 , <NUM_LIT> ) ; op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( ! SUBREG_P ( op1 ) || ! SUBREG_P ( op2 ) || GET_MODE ( op1 ) != SImode || GET_MODE ( op2 ) != SImode || ( ( SUBREG_BYTE ( op1 ) != <NUM_LIT> || SUBREG_BYTE ( op2 ) != GET_MODE_SIZE ( SImode ) ) && ( SUBREG_BYTE ( op2 ) != <NUM_LIT> || SUBREG_BYTE ( op1 ) != GET_MODE_SIZE ( SImode ) ) ) ) return false ; op1 = SUBREG_REG ( op1 ) ; op2 = SUBREG_REG ( op2 ) ;

if ( op1 != op2 || ! REG_P ( op1 ) || GET_MODE ( op1 ) != DImode ) return false ;


<s> int count = GET_MODE_SIZE ( mode ) / <NUM_LIT> ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , <NUM_LIT> ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + <NUM_LIT> : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ;

else if ( TREE_CODE ( valtype ) == VECTOR_TYPE && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ;


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; return N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64Bit ) , DataLayout ( Subtarget . getTargetDataString ( ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> default : break ; case <STR_LIT> : case <STR_LIT> : return & Target . getSymA ( ) -> getSymbol ( ) . AliasedSymbol ( ) ; } return NULL ;


<s> return isRegIdx ( ) && RegIdx . Kind & RegKind_HWRegs && RegIdx . Index <= <NUM_LIT> ;


<s> bool hasV67OpsOnly ( ) const { return get<ISA_LIT>ArchVersion ( ) == <STR_LIT> :: V67 ;


<s> std :: swap ( N0 , N1 ) ; } if ( N0 == N1 ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ;

return DAG . getNode ( Opcode , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , N00 , N1 ) , DAG . getNode ( <STR_LIT> , DL , VT , N01 , N1 ) ) ;


<s> assert ( Op && <STR_LIT> ) ; if ( ! Op -> isReg ( ) ) return nullptr ; unsigned Reg = Op -> getReg ( ) ;

if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return nullptr ;


<s> MachineBasicBlock :: iterator J = std :: next ( I ) ; if ( J != MBB -> end ( ) && J -> getOpcode ( ) == FalseTermOpc && J -> getOperand ( <NUM_LIT> ) . isReg ( ) && J -> getOperand ( <NUM_LIT> ) . getReg ( ) == SaveExecReg ) { SaveExecReg = J -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , OSType , true ) ;


<s> x = expand_binop ( DImode , xor_optab , x , y , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; y = const0_rtx ; } if ( reload_completed ) gcc_assert ( scratch != NULL && GET_MODE ( scratch ) == SImode ) ; else scratch = gen_rtx_SCRATCH ( SImode ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; set = gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ;

emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ;


<s> } const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ; if ( featureBits [ <STR_LIT> ] && ( coproc != <NUM_LIT> ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( coproc ) ) ; Inst . addOperand ( MCOperand :: createImm ( CRd ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : imm = <STR_LIT> ( U ? <STR_LIT> : <STR_LIT> , imm ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : imm |= U << <NUM_LIT> ; LLVM_FALLTHROUGH ; default : Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ;


<s> SDValue Clz = DAG . getNode ( <STR_LIT> , dl , VT , Cmp -> getOperand ( <NUM_LIT> ) ) ; SDValue Trunc = DAG . getZExtOrTrunc ( Clz , dl , <STR_LIT> ) ; SDValue Scc = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Trunc , DAG . getConstant ( Log2b , dl , VT ) ) ;

return DAG . getZExtOrTrunc ( Scc , dl , ExtTy ) ;


<s> HSACodeObject :: note_iterator HSACodeObject :: notes_end ( ) const { return const_varsize_item_iterator < ELFNote > ( ) ;


<s> else if ( VT == <STR_LIT> ) { std :: string mask = <STR_LIT> ; for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) mask += <STR_LIT> ; SDValue Mask = b . Constant ( mask , <STR_LIT> ) ; MVT DoubleVT = <STR_LIT> ; SDValue Ah = b . AND ( Mask , b . BITCAST ( Op0 , <STR_LIT> ) ) ; SDValue Bh = b . AND ( Mask , b . BITCAST ( Op1 , <STR_LIT> ) ) ;

SDValue R = b . DoOp ( DoubleVT , b . AND ( b . BITCAST ( Op0 , <STR_LIT> ) , b . NOT ( Ah ) ) , b . AND ( b . BITCAST ( Op1 , <STR_LIT> ) , b . NOT ( Bh ) ) ) ;


<s> LLVMContext * Context = & MF -> getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; unsigned ConstAlign = MF -> getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF -> getConstantPool ( ) -> getConstantPoolIndex ( CPV , ConstAlign ) ; unsigned TempReg = MF -> getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; Opc = Subtarget -> isThumb ( ) ? <STR_LIT> : UseGOT_PREL ? <STR_LIT> : <STR_LIT> ; DestReg = constrainOperandRegClass ( TII . get ( Opc ) , DestReg , <NUM_LIT> ) ;

MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addReg ( TempReg ) . addImm ( <ISA_LIT>PCLabelIndex ) ;


<s> return ( int8_t ) __builtin_aarch64_sqmovnhi ( __a ) ;


<s> break ; case CC_NONE : if ( cc_status . value1 || cc_status . value2 ) { HARD_REG_SET regs_used ; HARD_REG_SET regs_set ; CLEAR_HARD_REG_SET ( regs_used ) ; if ( cc_status . value1 && ! CONSTANT_P ( cc_status . value1 ) ) { find_all_hard_regs ( cc_status . value1 , & regs_used ) ; } if ( cc_status . value2 && ! CONSTANT_P ( cc_status . value2 ) ) { find_all_hard_regs ( cc_status . value2 , & regs_used ) ; } find_all_hard_reg_sets ( insn , & regs_set , false ) ; if ( hard_reg_set_intersect_p ( regs_used , regs_set ) ) { CC_STATUS_INIT ; } } break ; case CC_SET_N : CC_STATUS_INIT ; break ; case CC_SET_ZN : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) { cc_status . flags |= CC_NO_OVERFLOW ; cc_status . value1 = SET_DEST ( set ) ; } break ; case CC_SET_VZN : CC_STATUS_INIT ; break ; case CC_SET_CZN : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) { cc_status . value1 = SET_DEST ( set ) ; cc_status . flags |= CC_OVERFLOW_UNUSABLE ; } break ; case CC_COMPARE : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) cc_status . value1 = SET_SRC ( set ) ; break ; case CC_CLOBBER : CC_STATUS_INIT ; break ;


<s> const TypeSize & TySize = Ty -> getPrimitiveSizeInBits ( ) ; if ( TySize . isScalable ( ) && TySize . getKnownMinSize ( ) > <NUM_LIT> ) return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool isGFX11 ( const MCSubtargetInfo & STI ) { return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> if ( is_wakeup_func ( ) ) fprintf ( outfile , <STR_LIT> ) ; fprintf ( outfile , <STR_LIT> ) ; } fprintf ( outfile , <STR_LIT> , cfun -> machine -> framesize_regs ) ; fprintf ( outfile , <STR_LIT> , cfun -> machine -> framesize_locals ) ; fprintf ( outfile , <STR_LIT> , cfun -> machine -> framesize_outgoing ) ; fprintf ( outfile , <STR_LIT> , cfun -> machine -> framesize ) ; fprintf ( outfile , <STR_LIT> , msp430_initial_elimination_offset ( ARG_POINTER_REGNUM , FRAME_POINTER_REGNUM ) ) ; fprintf ( outfile , <STR_LIT> , msp430_initial_elimination_offset ( FRAME_POINTER_REGNUM , STACK_POINTER_REGNUM ) ) ; n = <NUM_LIT> ; fprintf ( outfile , <STR_LIT> ) ; for ( r = <NUM_LIT> ; r < ARG_POINTER_REGNUM ; r ++ ) if ( cfun -> machine -> need_to_save [ r ] ) {

fprintf ( outfile , <STR_LIT> , reg_names [ r ] ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return ST . hasDLInsts ( ) ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: KILL ) , getCRFromCRBit ( SrcReg ) ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ;

BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) ) ;


<s> O << <STR_LIT> << getMsgName ( MsgId ) ; if ( msgRequiresOp ( MsgId ) ) { O << <STR_LIT> << getMsgOpName ( MsgId , OpId ) ; if ( msgSupportsStream ( MsgId , OpId ) ) { O << <STR_LIT> << StreamId ; } } O << ')' ; } else if ( encodeMsg ( MsgId , OpId , StreamId ) == Imm16 ) { O << <STR_LIT> << MsgId << <STR_LIT> << OpId << <STR_LIT> << StreamId << ')' ; } else { O << Imm16 ; }


<s> Builder . addExtension ( PassManagerBuilder :: EP_ModuleOptimizerEarly , [ ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { PM . add ( create<ISA_LIT>LowerIntrinsicsPass ( ) ) ; } ) ;


<s> const MCExpr * <ISA_LIT>ELFMCAsmInfo :: getExprForPersonalitySymbol ( const MCSymbol * Sym , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & dwarf :: DW_EH_PE_pcrel ) {

MCContext & Ctx = Streamer . getContext ( ) ;


<s> for ( unsigned R : RegSet ) { if ( ! Register :: isVirtualRegister ( R ) ) { assert ( Register :: isPhysicalRegister ( R ) ) ;


<s> if ( TT . isOSBinFormatMachO ( ) ) return std :: make_unique < TargetLoweringObjectFileMachO > ( ) ; if ( TT . isOSWindows ( ) ) return std :: make_unique < TargetLoweringObjectFileCOFF > ( ) ; return std :: make_unique < <ISA_LIT>ElfTargetObjectFile > ( ) ;


<s> SDValue X = SetCC -> getOperand ( <NUM_LIT> ) ; SDValue Y = SetCC -> getOperand ( <NUM_LIT> ) ; EVT OpVT = X . getValueType ( ) ; unsigned OpSize = OpVT . getSizeInBits ( ) ; if ( ! OpVT . isScalarInteger ( ) || OpSize < <NUM_LIT> ) return SDValue ( ) ; bool IsOrXorXorCCZero = isNullConstant ( Y ) && X . getOpcode ( ) == <STR_LIT> && X . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && X . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ; if ( isNullConstant ( Y ) && ! IsOrXorXorCCZero ) return SDValue ( ) ; auto IsVectorBitCastCheap = [ ] ( SDValue X ) { X = peekThroughBitcasts ( X ) ; return isa < ConstantSDNode > ( X ) || X . getValueType ( ) . isVector ( ) || X . getOpcode ( ) == <STR_LIT> ; } ; if ( ( ! IsVectorBitCastCheap ( X ) || ! IsVectorBitCastCheap ( Y ) ) && ! IsOrXorXorCCZero ) return SDValue ( ) ; EVT VT = SetCC -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( SetCC ) ; bool HasAVX = Subtarget . hasAVX ( ) ; if ( ( OpSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || ( OpSize == <NUM_LIT> && HasAVX ) || ( OpSize == <NUM_LIT> && Subtarget . useAVX512Regs ( ) ) ) { bool HasPT = Subtarget . hasSSE41 ( ) ; EVT VecVT = <STR_LIT> ; EVT CmpVT = <STR_LIT> ; if ( OpSize == <NUM_LIT> ) VecVT = CmpVT = <STR_LIT> ; if ( OpSize == <NUM_LIT> ) { if ( Subtarget . hasBWI ( ) ) { VecVT = <STR_LIT> ; CmpVT = <STR_LIT> ;


<s> int arx_reg_operand ( rtx op , enum machine_mode mode ) { if ( mode != VOIDmode && mode != GET_MODE ( op ) ) return <NUM_LIT> ; if ( GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; return REG_P ( op ) && ( ! reload_completed || IS_ADDR_REG ( op ) ) ;


<s> cur_pos ++ ; } else { fprintf ( stream , <STR_LIT> , c ) ; cur_pos += <NUM_LIT> ; } if ( cur_pos > <NUM_LIT> && i + <NUM_LIT> < len ) { cur_pos = <NUM_LIT> ; fprintf ( stream , <STR_LIT> ) ; }


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ;

if ( ! isCondBranch ( I ) && ! isUncondBranch ( I ) ) return <NUM_LIT> ;


<s> bool FoundLoad = false ; SmallVector < SDValue , <NUM_LIT> > ChainOps ; SmallVector < const SDNode * , <NUM_LIT> > LoopWorklist ; SmallPtrSet < const SDNode * , <NUM_LIT> > Visited ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) { SDValue Op = Chain . getOperand ( i ) ; if ( Op == Load . getValue ( <NUM_LIT> ) ) { FoundLoad = true ; ChainOps . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; continue ; } LoopWorklist . push_back ( Op . getNode ( ) ) ; ChainOps . push_back ( Op ) ; } if ( ! FoundLoad ) return false ; if ( ! LoopWorklist . empty ( ) ) { const unsigned int Max = <NUM_LIT> ; if ( SDNode :: hasPredecessorHelper ( Load . getNode ( ) , Visited , LoopWorklist , Max , true ) ) return false ; } InputChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Chain ) , <STR_LIT> , ChainOps ) ;


<s> if ( Subtarget . hasAVX ( ) ) { SDValue Op ( N , <NUM_LIT> ) ; if ( TLI . isTypeLegal ( VT ) && TLI . isTypeLegal ( In . getValueType ( ) ) ) if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; }


<s> static MCSubtargetInfo * create<ISA_LIT>Z80MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>Z80MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> const MCSection * <ISA_LIT>MCSymbolRefExpr :: FindAssociatedSection ( ) const { return Symbol -> isDefined ( ) ? & Symbol -> getSection ( ) : NULL ;


<s> if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; } if ( Hi . getOpcode ( ) == <STR_LIT> && Hi . getOperand ( <NUM_LIT> ) == Lo && isa < ConstantSDNode > ( Hi . getOperand ( <NUM_LIT> ) ) && Hi . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo ) ; return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , Hi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ;


<s> for ( auto & MI : MBB ) { if ( ! MI . isCall ( ) ) continue ; const MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; if ( ! MO . isGlobal ( ) ) continue ; const Function * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) continue ; if ( F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find ( <STR_LIT> ) != StringRef :: npos || F -> getName ( ) . find_first_of ( <STR_LIT> ) == StringRef :: npos ) continue ; unsigned CalleeStkArity = F -> arg_size ( ) > CCRegisteredArgs ? F -> arg_size ( ) - CCRegisteredArgs : <NUM_LIT> ; if ( HipeLeafWords - <NUM_LIT> > CalleeStkArity ) MoreStackForCalls = std :: max ( MoreStackForCalls , ( HipeLeafWords - <NUM_LIT> - CalleeStkArity ) * SlotSize ) ; } } MaxStack += MoreStackForCalls ; } if ( MaxStack > Guaranteed ) { MachineBasicBlock * stackCheckMBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * incStackMBB = MF . CreateMachineBasicBlock ( ) ; for ( const auto & LI : PrologueMBB . liveins ( ) ) { stackCheckMBB -> addLiveIn ( LI ) ; incStackMBB -> addLiveIn ( LI ) ; } MF . push_front ( incStackMBB ) ; MF . push_front ( stackCheckMBB ) ; unsigned ScratchReg , SPReg , PReg , SPLimitOffset ; unsigned LEAop , CMPop , CALLop ; SPLimitOffset = getHiPELiteral ( HiPELiteralsMD , <STR_LIT> ) ; if ( Is64Bit ) { SPReg = <STR_LIT> ; PReg = <STR_LIT> ; LEAop = <STR_LIT> ; CMPop = <STR_LIT> ;


<s> argmap_entry ( <STR_LIT> _VT , TargetRegisterClass * _RC ) : VT ( _VT ) , RC ( _RC ) , loc ( _RC -> begin ( ) ) {


<s> bool hasZeroCycleZeroingFPWorkaround ( ) const {


<s> HasAES = false ; HasFXSR = false ; HasXSAVE = false ; HasXSAVEOPT = false ; HasXSAVEC = false ; HasXSAVES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasLWP = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasVPOPCNTDQ = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ;


<s> BlackfinTargetMachine :: BlackfinTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) {


<s> return __builtin_mve_vrndq_m_fv8hf ( __arm_vuninitializedq_f16 ( ) , __a , __p ) ;


<s> if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; unsigned Half = NumElts / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = i / NumElts ; else WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += Half ) { unsigned Idx = WhichResult ; for ( unsigned k = <NUM_LIT> ; k < Half ; ++ k ) { int MIdx = M [ i + j + k ] ;

if ( MIdx >= <NUM_LIT> && ( unsigned ) MIdx != Idx ) return false ;


<s> MachineInstr * Add = BuildMI ( * BB , & I , DL , TII . get ( Opc ) , DstReg ) . addDef ( UnusedCarry , RegState :: Dead ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Add , TII , TRI , RBI ) ; } assert ( ! Sub && <STR_LIT> ) ; const TargetRegisterClass & RC = IsSALU ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & HalfRC = IsSALU ? <STR_LIT> : <STR_LIT> ; MachineOperand Lo1 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Lo2 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Hi1 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; MachineOperand Hi2 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , HalfRC , <STR_LIT> ) ) ; Register DstLo = MRI -> createVirtualRegister ( & HalfRC ) ; Register DstHi = MRI -> createVirtualRegister ( & HalfRC ) ; if ( IsSALU ) { BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstLo ) . add ( Lo1 ) . add ( Lo2 ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . add ( Hi1 ) . add ( Hi2 ) ; } else { const TargetRegisterClass * CarryRC = TRI . getWaveMaskRegClass ( ) ; Register CarryReg = MRI -> createVirtualRegister ( CarryRC ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstLo ) . addDef ( CarryReg ) . add ( Lo1 ) . add ( Lo2 ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addc = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . addDef ( MRI -> createVirtualRegister ( CarryRC ) , RegState :: Dead ) . add ( Hi1 ) . add ( Hi2 ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; if ( ! constrainSelectedInstRegOperands ( * Addc , TII , TRI , RBI ) ) return false ; } BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstLo ) . addImm ( <STR_LIT> ) . addReg ( DstHi ) . addImm ( <STR_LIT> ) ; if ( ! RBI . constrainGenericRegister ( DstReg , RC , * MRI ) ) return false ;


<s> NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint64_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; } else if ( NumBytes >= <NUM_LIT> * <NUM_LIT> ) { continue ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoad ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = VecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( Tys , NumResultVecs + <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ; Ops . push_back ( Inc ) ; for ( unsigned i = AddrOpIdx + <NUM_LIT> ; i < N -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } MemIntrinsicSDNode * MemInt = cast < MemIntrinsicSDNode > ( N ) ; SDValue UpdN = DAG . getMemIntrinsicNode ( NewOpc , N -> getDebugLoc ( ) , SDTys , Ops . data ( ) , Ops . size ( ) , MemInt -> getMemoryVT ( ) , MemInt -> getMemOperand ( ) ) ; std :: vector < SDValue > NewResults ; for ( unsigned i = <NUM_LIT> ; i < NumResultVecs ; ++ i ) {

NewResults . push_back ( SDValue ( UpdN . getNode ( ) , i ) ) ;


<s> if ( ! MFI . isVRegStackified ( Reg ) ) { unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( Reg ) ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( CopyLocalOpc ) , NewReg ) . addReg ( Reg ) ; MO . setReg ( NewReg ) ;


<s> case E_TImode : return V1TImode ; case E_DImode : return V2DImode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; default : ; } if ( TARGET_PAIRED_FLOAT && mode == SFmode ) return V2SFmode ;


<s> if ( isPackedVectorType ( DataVT ) ) return splitPackedLoadStore ( Op , CDAG ) ;

return legalizePackedAVL ( Op , CDAG ) ;


<s> std :: vector < <ISA_LIT>Exception * > & getSubExceptions ( ) {


<s> while ( * loc ) loc = & XEXP ( * loc , <NUM_LIT> ) ; * loc = cfa_restores ;

RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;


<s> mem_1 = operands [ <NUM_LIT> ] ; mem_2 = operands [ <NUM_LIT> ] ; reg_1 = operands [ <NUM_LIT> ] ; reg_2 = operands [ <NUM_LIT> ] ; } if ( MEM_VOLATILE_P ( mem_1 ) || MEM_VOLATILE_P ( mem_2 ) ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem_1 ) < <NUM_LIT> * BITS_PER_UNIT ) return false ; extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; if ( base_1 == NULL_RTX || offset_1 == NULL_RTX ) return false ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; if ( base_2 == NULL_RTX || offset_2 == NULL_RTX ) return false ; if ( ! rtx_equal_p ( base_1 , base_2 ) ) return false ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; msize = GET_MODE_SIZE ( mode ) ; if ( offval_1 != ( offval_2 + msize ) && offval_2 != ( offval_1 + msize ) ) return false ; if ( load ) { if ( reg_mentioned_p ( reg_1 , mem_1 ) ) return false ;

if ( offval_1 > offval_2 && reg_mentioned_p ( reg_2 , mem_2 ) ) return false ;


<s> explicit <ISA_LIT>InterleavedAccessGroup ( Instruction * I , ArrayRef < ShuffleVectorInst * > Shuffs , ArrayRef < unsigned > Ind , const unsigned F , const <ISA_LIT>Subtarget & STarget , IRBuilder < > & B ) : Inst ( I ) , Shuffles ( Shuffs ) , Indices ( Ind ) , Factor ( F ) , Subtarget ( STarget ) , DL ( Inst -> getModule ( ) -> getDataLayout ( ) ) , Builder ( B ) {


<s> if ( ! VT . isVector ( ) ) return <STR_LIT> ;

return VT . changeVectorElementTypeToInteger ( ) ;


<s> MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: const_iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) emitInstruction ( * I ) ; } } while ( MCE . finishFunction ( MF ) ) ; return false ;


<s> bool <ISA_LIT>InstrInfo :: isNewValueJump ( unsigned Opcode ) const { return isNewValue ( Opcode ) && get ( Opcode ) . isBranch ( ) && isPredicated ( Opcode ) ;


if ( ! isMemory ( ) || ! Memory . OffsetRegNum || Memory . isNegative || Memory . Alignment != <NUM_LIT> ) return false ;


<s> return __builtin_mve_vcmpneq_n_uv4si ( __a , __b ) ;


<s> for ( const SDep & PI : Dst -> Preds ) {

if ( PI . getLatency ( ) != <NUM_LIT> ) continue ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const {


<s> PowerPCIREmitter :: PowerPCIREmitter ( Decompiler * TheDec , raw_ostream & InfoOut , raw_ostream & ErrOut ) : IREmitter ( TheDec , InfoOut , ErrOut ) {


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter ) : MCELFStreamer ( Context , MAB , OS , Emitter ) { RegInfoRecord = new <ISA_LIT>RegInfoRecord ( this , Context ) ;

<ISA_LIT>OptionRecords . push_back ( std :: unique_ptr < <ISA_LIT>RegInfoRecord > ( RegInfoRecord ) ) ;


<s> SDLoc SL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue K0 = DAG . getConstantFP ( BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) , SL , <STR_LIT> ) ; SDValue K1 = DAG . getConstantFP ( BitsToDouble ( UINT64_C ( <NUM_LIT> ) ) , SL , <STR_LIT> ) ;

SDValue Mul = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Trunc , K0 ) ;


<s> if ( Is<ISA_LIT>64 ) { DivOp = Signed ? <STR_LIT> : <STR_LIT> ; ZeroReg = <STR_LIT> ; SubOp = <STR_LIT> ; } else { DivOp = Signed ? <STR_LIT> : <STR_LIT> ; ZeroReg = <STR_LIT> ; SubOp = <STR_LIT> ; } bool UseTraps = useTraps ( ) ; unsigned Opcode = Inst . getOpcode ( ) ; bool isDiv = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isRem = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( RtOp . isImm ( ) ) { unsigned ATReg = getATReg ( IDLoc ) ; if ( ! ATReg ) return true ; if ( ImmValue == <NUM_LIT> ) { if ( UseTraps ) TOut . emitRRI ( <STR_LIT> , ZeroReg , ZeroReg , <NUM_LIT> , IDLoc , STI ) ; else TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ; return false ; } if ( isRem && ( ImmValue == <NUM_LIT> || ( Signed && ( ImmValue == - <NUM_LIT> ) ) ) ) { TOut . emitRRR ( <STR_LIT> , RdReg , ZeroReg , ZeroReg , IDLoc , STI ) ; return false ; } else if ( isDiv && ImmValue == <NUM_LIT> ) { TOut . emitRRR ( <STR_LIT> , RdReg , RsReg , <STR_LIT> , IDLoc , STI ) ; return false ; } else if ( isDiv && Signed && ImmValue == - <NUM_LIT> ) { TOut . emitRRR ( SubOp , RdReg , ZeroReg , RsReg , IDLoc , STI ) ; return false ; } else { if ( loadImmediate ( ImmValue , ATReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , Inst . getLoc ( ) , Out , STI ) ) return true ; TOut . emitRR ( DivOp , RsReg , ATReg , IDLoc , STI ) ; TOut . emitR ( isDiv ? <STR_LIT> : <STR_LIT> , RdReg , IDLoc , STI ) ; return false ; } return true ; } if ( RtReg == <STR_LIT> || RtReg == <STR_LIT> ) {


<s> bool <ISA_LIT>AsmParser :: MatchInstruction ( const SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCInst & Inst ) { <ISA_LIT>Operand & Op0 = * ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ; assert ( Op0 . Kind == <ISA_LIT>Operand :: Token && <STR_LIT> ) ; const StringRef & Mnemonic = Op0 . getToken ( ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { Inst = MCInst ( ) ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> M = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , Lo40Set ) ; SDValue I = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getSelectCC ( DL , M , Zero , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Zero , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue N = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; SDValue OneSubExp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One , E ) ; SDValue B = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OneSubExp , Zero ) ; B = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , B , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SigSetHigh = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue D = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SigSetHigh , B ) ; SDValue D0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , D , B ) ; SDValue D1 = DAG . getSelectCC ( DL , D0 , SigSetHigh , One , Zero , <STR_LIT> ) ; D = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , D , D1 ) ; SDValue V = DAG . getSelectCC ( DL , E , One , D , N , <STR_LIT> ) ; SDValue VLow3 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue V0 = DAG . getSelectCC ( DL , VLow3 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , One , Zero , <STR_LIT> ) ; SDValue V1 = DAG . getSelectCC ( DL , VLow3 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , One , Zero , <STR_LIT> ) ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V0 , V1 ) ; V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V , V1 ) ;

V = DAG . getSelectCC ( DL , E , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , V , <STR_LIT> ) ;


<s> rtx ( * gen_fn ) ( rtx , rtx , rtx , rtx , rtx ) ; if ( ! ( cmp = gen_conditional_move ( GET_CODE ( operands [ <NUM_LIT> ] ) , cmp_mode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ) return <NUM_LIT> ; one_tmp = gen_reg_rtx ( SImode ) ; zero_tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( one_tmp , const_true_rtx ) ) ; emit_insn ( gen_movsi ( zero_tmp , const0_rtx ) ) ; gen_fn = ( cmp_mode == SImode ? gen_movsicc_internal0 : gen_movsicc_internal1 ) ;

emit_insn ( gen_fn ( dest , XEXP ( cmp , <NUM_LIT> ) , one_tmp , zero_tmp , cmp ) ) ;


<s> MO . setIsKill ( true ) ; } else if ( RC -> getID ( ) == <STR_LIT> ) { unsigned Opc = <STR_LIT> ; addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) , DestReg ) , FrameIdx ) ; } else { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlign ( ) >= Alignment ) || RI . canRealignStack ( MF ) ;

unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>32Target ( ) , & getThe<ISA_LIT>32LETarget ( ) , & getThe<ISA_LIT>64Target ( ) , & getThe<ISA_LIT>64LETarget ( ) } ) { RegisterMCAsmInfoFn C ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ;

TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ;


<s> ca -> regs += ( <NUM_LIT> + CRIS_FUNCTION_ARG_SIZE ( mode , type ) ) / <NUM_LIT> ;


<s> CellMapType ResMap ; bool Eval = ME . evaluate ( MI , Map , ResMap ) ; if ( Trace && Eval ) { for ( unsigned i = <NUM_LIT> , n = MI . getNumOperands ( ) ; i < n ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; RegisterRef RU ( MO ) ; dbgs ( ) << <STR_LIT> << PrintReg ( RU . Reg , & ME . TRI , RU . Sub ) << <STR_LIT> << ME . getCell ( RU , Map ) << <STR_LIT> ; } dbgs ( ) << <STR_LIT> ; for ( const std :: pair < unsigned , RegisterCell > & P : ResMap ) { RegisterRef RD ( P . first ) ; dbgs ( ) << <STR_LIT> << PrintReg ( P . first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; }


<s> auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < <NUM_LIT> ; } ; assert ( std :: is_sorted ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , Comp ) ) ; return std :: binary_search ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , CallSym , Comp ) ;


<s> void setJumpTableEntryInfo ( int Idx , unsigned Size , MCSymbol * PCRelSym ) { if ( ( unsigned ) Idx >= JumpTableEntryInfo . size ( ) ) JumpTableEntryInfo . resize ( Idx + <NUM_LIT> ) ; JumpTableEntryInfo [ Idx ] = std :: make_pair ( Size , PCRelSym ) ;


<s> if ( const ConstantInt * Op1C = dyn_cast < ConstantInt > ( Op1 ) ) { if ( unsigned CompareImmOpc = <ISA_LIT>ChooseCmpImmediateOpcode ( VT , Op1C ) ) { BuildMI ( MBB , DL , TII . get ( CompareImmOpc ) ) . addReg ( Op0Reg ) . addImm ( Op1C -> getSExtValue ( ) ) ; return true ; } } unsigned CompareOpc = <ISA_LIT>ChooseCmpOpcode ( VT ) ;

if ( CompareOpc == <NUM_LIT> ) return false ;


<s> static DecodeStatus DecodeFP32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {

return decodeRegisterClass ( Inst , RegNo , <STR_LIT> ) ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {


<s> assert ( isBundle ( MCI ) ) ; auto Flags = MCI . getOperand ( <NUM_LIT> ) . getImm ( ) ;

return ( Flags & memStoreReorderEnabledMask ) != <NUM_LIT> ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm , unsigned UncondBr ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , TM ( tm ) , UncondBrOpc ( UncondBr ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getInstSyncBarrierOpt ( ) ) ) ) ;


<s> if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> needsAsyncDwarfUnwindInfo ( ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , <NUM_LIT> ) ) ;

BuildMI ( MBB , MBBI , DL , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameDestroy ) ;


<s> unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , * TRI ) ; LLT LoadTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register PtrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( PtrReg ) ; unsigned AS = PtrTy . getAddressSpace ( ) ; unsigned PtrSize = PtrTy . getSizeInBits ( ) ; const ValueMapping * ValMapping ; const ValueMapping * PtrMapping ; const RegisterBank * PtrBank = getRegBank ( PtrReg , MRI , * TRI ) ; if ( PtrBank == & <STR_LIT> && <ISA_LIT>TargetLowering :: isFlatGlobalAddrSpace ( AS ) ) { if ( isScalarLoadLegal ( MI ) ) { ValMapping = <STR_LIT> ( <STR_LIT> , Size ) ; PtrMapping = <STR_LIT> ( <STR_LIT> , PtrSize ) ; } else { ValMapping = <STR_LIT> ( <STR_LIT> , Size ) ; unsigned PtrBankID = Subtarget . useFlatForGlobal ( ) ? <STR_LIT> : <STR_LIT> ; PtrMapping = <STR_LIT> ( PtrBankID , PtrSize ) ; ValMapping = <STR_LIT> ( <STR_LIT> , LoadTy ) ; } } else { ValMapping = <STR_LIT> ( <STR_LIT> , LoadTy ) ; PtrMapping = <STR_LIT> ( <STR_LIT> , PtrSize ) ; } OpdsMapping [ <NUM_LIT> ] = ValMapping ; OpdsMapping [ <NUM_LIT> ] = PtrMapping ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( OpdsMapping ) , MI . getNumOperands ( ) ) ;


<s> SimpleShape ( ) : Shape ( SK_Simple ) , Inner ( nullptr ) {


<s> static SDValue combineLoopMAddPattern ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue MulOp = N -> getOperand ( <NUM_LIT> ) ; SDValue Phi = N -> getOperand ( <NUM_LIT> ) ; if ( MulOp . getOpcode ( ) != <STR_LIT> ) std :: swap ( MulOp , Phi ) ; if ( MulOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ShrinkMode Mode ; if ( ! canReduceVMulWidth ( MulOp . getNode ( ) , DAG , Mode ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; unsigned VectorSize = VT . getVectorNumElements ( ) * <NUM_LIT> ; if ( VectorSize < <NUM_LIT> || VectorSize > RegSize ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ;

SDValue N1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ;


<s> gcc_assert ( CONST_INT_P ( shift_amount ) ) ; const int shift_amount_i = INTVAL ( shift_amount ) & <NUM_LIT> ; if ( shift_amount_i == <NUM_LIT> ) return true ; return ( ashl_lshr_seq [ shift_amount_i ] . clobbers_t & ASHL_CLOBBERS_T ) != <NUM_LIT> ;


<s> static void microblaze_elf_asm_init_sections ( void ) { sdata2_section = get_unnamed_section ( SECTION_WRITE , output_section_asm_op , SDATA2_SECTION_ASM_OP ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Immediate , S , E ) ; Op -> Imm . Val = Val ;


<s> for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <STR_LIT> , false ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) {

for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ;


<s> if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , VReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else emitThumbRegPlusImmediate ( MBB , II , dl , VReg , FrameReg , Offset , TII , * this ) ; MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( VReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; SDValue Denominator = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Denominator . getValueType ( ) != <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; SDValue Div = SDValue ( DAG . getMachineNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Denominator ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Div ) ;


<s> int pdp10_starting_frame_offset ( ) { return <NUM_LIT> ;


<s> unsigned Directive = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; if ( Directive != <STR_LIT> && Directive != <STR_LIT> && Directive != <STR_LIT> && Directive != <STR_LIT> ) { assert ( TM . getInstrInfo ( ) && <STR_LIT> ) ;

return new <ISA_LIT>HazardRecognizer970 ( TM ) ;


<s> const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSDarwin ( ) ) return new Darwin<ISA_LIT>AsmBackend ( T ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; bool IsLittleEndian = TT . getArch ( ) == Triple :: ppc64le ;

return new ELF<ISA_LIT>AsmBackend ( T , IsLittleEndian ? <STR_LIT> : <STR_LIT> , OSABI ) ;


<s> offset = cfun -> machine -> frame . arg_pointer_offset ; break ; default : gcc_unreachable ( ) ; }

if ( to == HARD_FRAME_POINTER_REGNUM ) offset -= cfun -> machine -> frame . hard_frame_pointer_offset ;


<s> if ( ! Layout ) return false ; MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ; const MCSymbolRefExpr * Sym = Value . getSymA ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Sym -> getKind ( ) ; if ( Modifier != MCSymbolRefExpr :: VK_None ) return false ; if ( Kind == VK_<ISA_LIT>_PM ) { Modifier = MCSymbolRefExpr :: VK_<ISA_LIT>_PM ; } Sym = MCSymbolRefExpr :: create ( & Sym -> getSymbol ( ) , Modifier , Context ) ; Result = MCValue :: get ( Sym , Value . getSymB ( ) , Value . getConstant ( ) ) ; } return true ;


<s> static const char * sparc_mangle_type ( const_tree type ) { if ( ! TARGET_64BIT && TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return <STR_LIT> ;


<s> <ISA_LIT>VectorRegMerger ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TII ( nullptr ) {


<s> Clause . first -> getOperand ( <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; CounterPropagateAddr ( * Clause . first , CfCount ) ; MachineBasicBlock * BB = Clause . first -> getParent ( ) ;

BuildMI ( BB , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( CfCount ) ;


<s> if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ;


<s> QDst . insert ( QDst . end ( ) , QSrc . begin ( ) , QSrc . end ( ) ) ;


<s> unsigned Offset = Fn . getCallingConv ( ) == CallingConv :: <ISA_LIT>_CS ? <NUM_LIT> : <NUM_LIT> ; const GCNSubtarget & Subtarget = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned EncodedOffset = <STR_LIT> ( Subtarget , Offset ) ; BuildMI ( MBB , I , DL , LoadDwordX4 , ScratchRsrcReg ) . addReg ( Rsrc01 ) . addImm ( EncodedOffset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) . addMemOperand ( MMO ) ; } else if ( ST . isMesaGfxShader ( Fn ) || ( PreloadedScratchRsrcReg == <STR_LIT> ) ) { assert ( ! ST . isAmdHsaOrMesa ( Fn ) ) ; const MCInstrDesc & SMovB32 = TII -> get ( <STR_LIT> ) ; Register Rsrc2 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; Register Rsrc3 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; uint64_t Rsrc23 = TII -> getScratchRsrcWords23 ( ) ; if ( MFI -> hasImplicitBufferPtr ( ) ) { Register Rsrc01 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; if ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) { const MCInstrDesc & Mov64 = TII -> get ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , Mov64 , Rsrc01 ) . addReg ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } else { const MCInstrDesc & LoadDwordX2 = TII -> get ( <STR_LIT> ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; auto MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , LoadDwordX2 , Rsrc01 ) . addReg ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; MF . getRegInfo ( ) . addLiveIn ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) ; MBB . addLiveIn ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) ;


<s> } EndCf ( MI ) ; break ; case <STR_LIT> : if ( Depth == <NUM_LIT> ) { if ( skipIfDead ( MI , * NextBB ) ) { NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; } } else HaveKill = true ; Kill ( MI ) ; break ; case <STR_LIT> : Branch ( MI ) ; break ; case <STR_LIT> : { assert ( ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( BI != -- MF . end ( ) || I != MBB . getFirstTerminator ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB . addSuccessor ( EmptyMBBAtEnd ) ; BuildMI ( * BI , I , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( EmptyMBBAtEnd ) ;


<s> vector_insn_info ( ) : vl_vtype_info ( ) , m_state ( UNINITIALIZED ) , m_demands { false } , m_insn ( nullptr ) {


<s> fprintf ( asm_out_file , <STR_LIT> ) ;


return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> bool <ISA_LIT>InstructionSelector :: selectTurnIntoCOPY ( MachineInstr & I , MachineRegisterInfo & MRI , const unsigned DstReg , const TargetRegisterClass * DstRC , const unsigned SrcReg , const TargetRegisterClass * SrcRC ) const { if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ;


<s> static int tilegx_mode_rep_extended ( machine_mode mode , machine_mode mode_rep ) { if ( mode == SImode && mode_rep == DImode ) return SIGN_EXTEND ; return UNKNOWN ;


<s> Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc = NeedAlign <= HasAlign ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcR , getKillRegState ( IsKill ) ) . cloneMemRefs ( * MI ) ;


<s> void <ISA_LIT>InstrInfo :: addSCCDefUsersToVALUWorklist ( MachineInstr & SCCDefInst , SetVectorType & Worklist ) const { for ( MachineInstr & MI : make_range ( MachineBasicBlock :: iterator ( SCCDefInst ) , SCCDefInst . getParent ( ) -> end ( ) ) ) { if ( MI . findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ) return ;

if ( MI . findRegisterUseOperandIdx ( <STR_LIT> ) != - <NUM_LIT> ) Worklist . insert ( & MI ) ;


<s> if ( flag_vect_cost_model ) { int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; stmt_cost += rs6000_adjust_vect_cost_per_stmt ( kind , stmt_info ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( vinfo , stmt_info ) ) count *= <NUM_LIT> ; retval = ( unsigned ) ( count * stmt_cost ) ;


<s> case CPOP : OS << * getConstpoolOp ( ) ; break ; case Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case RegisterSeq : OS << <STR_LIT> ; OS << RegName ( getRegSeq ( ) . first ) << <STR_LIT> << RegName ( getRegSeq ( ) . second ) << <STR_LIT> ; break ; case RegisterList : OS << <STR_LIT> ; OS << RegName ( getRegList ( ) . List1From ) << <STR_LIT> << RegName ( getRegList ( ) . List1To ) << <STR_LIT> ; OS << RegName ( getRegList ( ) . List2From ) << <STR_LIT> << RegName ( getRegList ( ) . List2To ) << <STR_LIT> ;

OS << RegName ( getRegList ( ) . List3From ) << <STR_LIT> << RegName ( getRegList ( ) . List3To ) << <STR_LIT> ;


<s> int <ISA_LIT>TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != <NUM_LIT> && AM . Scale != <NUM_LIT> ; return - <NUM_LIT> ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) , & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getThe<ISA_LIT>BETarget ( ) , & getTheThumbLETarget ( ) , & getTheThumbBETarget ( ) } ) TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; for ( Target * T : { & getThe<ISA_LIT>LETarget ( ) , & getTheThumbLETarget ( ) } ) { TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>LEAsmBackend ) ; } for ( Target * T : { & getThe<ISA_LIT>BETarget ( ) , & getTheThumbBETarget ( ) } ) { TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ;

TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>BEAsmBackend ) ;


<s> if ( ! NONJUMP_INSN_P ( insn ) ) continue ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) continue ; start_sequence ( ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx mem = XEXP ( pat , i ) ; if ( MEM_P ( mem ) ) { tree expr = MEM_EXPR ( mem ) ; if ( ! expr ) continue ; if ( TREE_CODE ( expr ) == MEM_REF && TREE_CODE ( TREE_OPERAND ( expr , <NUM_LIT> ) ) == SSA_NAME ) { gimple * def_stmt = SSA_NAME_DEF_STMT ( TREE_OPERAND ( expr , <NUM_LIT> ) ) ; if ( def_stmt && is_gimple_assign ( def_stmt ) ) expr = gimple_assign_rhs1 ( def_stmt ) ; } if ( is_attr_preserve_access ( expr ) ) { auto_vec < unsigned int , <NUM_LIT> > accessors ;

tree container = bpf_core_compute ( expr , & accessors ) ;


<s> NodeAddr < RefNode * > NA ; NodeId Start = RA . Id ; while ( true ) { NA = getNextRelated ( IA , RA ) ; if ( NA . Id == <NUM_LIT> || NA . Id == Start ) break ;


<s> imported [ ( int ) code ] = <NUM_LIT> ; strcpy ( str , import_string ) ;

memcpy ( str + MILLI_START , milli_names [ ( int ) code ] , <NUM_LIT> ) ;


<s> SmallVector < unsigned , <NUM_LIT> > ImpDefs ; for ( unsigned i = memOpsBegin ; i < memOpsEnd ; ++ i ) { unsigned Reg = memOps [ i ] . Reg ; bool isKill = memOps [ i ] . isKill || KilledRegs . count ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , isKill ) ) ; for ( MIOperands MO ( memOps [ i ] . MBBI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isDef ( ) || ! MO -> isImplicit ( ) || MO -> isDead ( ) ) continue ; unsigned DefReg = MO -> getReg ( ) ; if ( std :: find ( ImpDefs . begin ( ) , ImpDefs . end ( ) , DefReg ) == ImpDefs . end ( ) ) ImpDefs . push_back ( DefReg ) ; } }

MachineBasicBlock :: iterator Loc = memOps [ insertAfter ] . MBBI ;


<s> return ! Stack . empty ( ) && Stack . back ( ) . first == BB ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ; Op -> StartLoc = S ; Op -> EndLoc = S ; Op -> IsRV64 = IsRV64 ;


<s> return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectPostStore ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; SmallVector < EVT , <NUM_LIT> > ResTys ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( RegSeq ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) ;

Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ;


<s> OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ;

OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOC , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( SuccID == S -> getID ( ) ) return ; } if ( Succ -> isHighLatencyBlock ( ) ) ++ NumHighLatencySuccessors ; Succs . push_back ( Succ ) ; assert ( none_of ( Preds , [ = ] ( <ISA_LIT>ScheduleBlock * P ) { return SuccID == P -> getID ( ) ; } ) && <STR_LIT> ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) {

CodePointerSize = CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( DecodeRegListOperand16 ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset << <NUM_LIT> ) ) ; return MCDisassembler :: Success ;


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> ) return LowerINT_TO_FP64 ( Op , DAG , true ) ; return SDValue ( ) ;


<s> SDValue WidthMinus1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( NumBits - <NUM_LIT> , dl , ElemTy ) ) ; SDValue CTLZ = DAG . getNode ( <STR_LIT> , dl , VT , LSB ) ; return DAG . getNode ( <STR_LIT> , dl , VT , WidthMinus1 , CTLZ ) ; } SDValue Bits ; if ( ElemTy == <STR_LIT> ) { SDValue FF = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , FF ) ; } else { SDValue One = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , ElemTy ) ) ;

Bits = DAG . getNode ( <STR_LIT> , dl , VT , LSB , One ) ;


<s> switch ( Modifier ) { case MCSymbolRefExpr :: VK_GOT : return <STR_LIT> ; case MCSymbolRefExpr :: VK_WASM_TBREL : assert ( SymA . isFunction ( ) ) ; return <STR_LIT> ; case MCSymbolRefExpr :: VK_WASM_MBREL : assert ( SymA . isData ( ) ) ; return is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; case MCSymbolRefExpr :: VK_WASM_TYPEINDEX : return <STR_LIT> ; default : break ; } switch ( unsigned ( Fixup . getKind ( ) ) ) { case <STR_LIT> : if ( SymA . isFunction ( ) ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( SymA . isFunction ( ) ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( SymA . isGlobal ( ) ) return <STR_LIT> ; if ( SymA . isFunction ( ) ) return <STR_LIT> ; if ( SymA . isEvent ( ) ) return <STR_LIT> ; if ( SymA . isTable ( ) ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : assert ( SymA . isData ( ) ) ; return <STR_LIT> ; case FK_Data_4 : if ( SymA . isFunction ( ) ) return <STR_LIT> ;


<s> return ( pInst & ~ get_mask ( <NUM_LIT> ) ) | ( pOff & get_mask ( <NUM_LIT> ) ) ;


<s> machine_mode pred_mode = aarch64_sve_pred_mode ( mode ) ; rtx ptrue = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_sve_ld1rq ( mode , dest , src , ptrue ) ) ;


<s> void addT2SOImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> __v16qu result ; const __v16qu zeros = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( __N < <NUM_LIT> ) if ( __builtin_constant_p ( __N ) ) result = vec_sld ( zeros , ( __v16qu ) __A , ( <NUM_LIT> - __N ) ) ; else { __v16qu shift = vec_splats ( ( unsigned char ) ( __N * <NUM_LIT> ) ) ; result = vec_sro ( ( __v16qu ) __A , shift ) ; result = vec_slo ( ( __v16qu ) __A , shift ) ;


<s> ApplyFunctionEntry ( ApplyFunctionType pFunc , const char * pName , size_t pSize = <NUM_LIT> ) : func ( pFunc ) , name ( pName ) , size ( pSize ) {


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; const TargetMachine & TM = getTargetMachine ( ) ; bool IsRO = isReadOnly ( GV ) ; if ( TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) && ! Subtarget -> genExecuteOnly ( ) ) if ( SDValue V = promoteToConstantPool ( GV , DAG , PtrVT , dl ) ) return V ; if ( isPositionIndependent ( ) ) { bool UseGOT_PREL = ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , UseGOT_PREL ? <STR_LIT> : <NUM_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result ; } else if ( Subtarget -> isROPI ( ) && IsRO ) { SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ;

} else if ( Subtarget -> isRWPI ( ) && ! IsRO ) {


<s> const MCInstrDesc & Desc = MI -> getDesc ( ) ; switch ( Desc . getOpcode ( ) ) { default : return <NUM_LIT> ; case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : return <NUM_LIT> ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; }


<s> <STR_LIT> AM = ( Opcode == <STR_LIT> ) ? cast < LoadSDNode > ( Op ) -> getAddressingMode ( ) : cast < StoreSDNode > ( Op ) -> getAddressingMode ( ) ; int RHSC ; if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { OffImm = ( ( AM == <STR_LIT> ) || ( AM == <STR_LIT> ) ) ? CurDAG -> getTargetConstant ( RHSC , SDLoc ( N ) , <STR_LIT> ) : CurDAG -> getTargetConstant ( - RHSC , SDLoc ( N ) , <STR_LIT> ) ; return true ;


<s> if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ;

const Function & F = MF . getFunction ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , bool little , const <ISA_LIT>TargetMachine & _TM ) :

<ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , IsLittle ( little ) , TM ( _TM ) , TargetTriple ( TT ) , TSInfo ( ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( initializeSubtargetDependencies ( CPU , FS , TM ) ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( TM , * this ) ) {


<s> bool <ISA_LIT>Subtarget :: isPositionIndependent ( ) const {


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) { return MCAsmBackend :: getFixupKindInfo ( Kind ) ; } assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;

return Infos [ Kind - FirstTargetFixupKind ] ;


<s> static unsigned encodeVFPRm ( const MachineInstr & MI , unsigned OpIdx ) { unsigned RegM = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; bool isSPVFP = <STR_LIT> -> contains ( RegM ) ; RegM = get<ISA_LIT>RegisterNumbering ( RegM ) ; if ( ! isSPVFP ) { Binary |= ( RegM & <NUM_LIT> ) ;

Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ;


<s> } , [ = ] ( MachineInstrBuilder & MIB ) { if ( SOffset ) MIB . addReg ( SOffset ) ; else MIB . addImm ( <NUM_LIT> ) ;

} , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> SDValue Result = DAG . getTargetExternalSymbol ( Sym , getPointerTy ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> } else { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( Hi ) ) ; } if ( ! Shift ) return Result ; if ( ( unsigned ) ( Imm & <NUM_LIT> ) == Remainder ) { SDValue Ops [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Shift ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } if ( Imm ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Shift ) , getI32Imm ( <NUM_LIT> - Shift ) ) ; } if ( ( Hi = ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ) {

Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Hi ) ) ;


<s> bool isImm ( ) const { return Kind == k_Immediate ;


<s> if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; Modified = false ; for ( MachineLoop * I : LI ) for ( MachineLoop * L : depth_first ( I ) ) if ( L -> isInnermost ( ) ) runOnLoop ( * L , Fn ) ; return Modified ;


<s> bool <ISA_LIT>DAGToDAGISel :: canUseBlockOperation ( StoreSDNode * Store , LoadSDNode * Load ) const { if ( Load -> getMemoryVT ( ) != Store -> getMemoryVT ( ) ) return false ; if ( Load -> isVolatile ( ) || Store -> isVolatile ( ) ) return false ; if ( Load -> isInvariant ( ) ) return true ; const Value * V1 = Load -> getMemOperand ( ) -> getValue ( ) ; const Value * V2 = Store -> getMemOperand ( ) -> getValue ( ) ; if ( ! V1 || ! V2 ) return false ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ;

int64_t End1 = Load -> getSrcValueOffset ( ) + Size ;