<s> if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && reg_set_p ( SET_DEST ( PATTERN ( insn ) ) , dep ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( dep_type == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - <NUM_LIT> ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( dep_type == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + <NUM_LIT> ; else * cost = insn_default_latency ( dep ) ; }


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << MF . getName ( ) << '\n' ) ; releaseMemory ( ) ;

auto & MDT = getAnalysis < MachineDominatorTree > ( ) ;


<s> Type * PtrTy = Ptr -> getType ( ) ; Type * ElemTy = PtrTy -> getPointerElementType ( ) ; IRBuilder < > Builder ( & I ) ; if ( ElemTy == v16i8 ) { Value * BitCast = Builder . CreateBitCast ( Ptr , PointerType :: get ( v4i32 , PtrTy -> getPointerAddressSpace ( ) ) ) ; LoadInst * Load = Builder . CreateLoad ( BitCast ) ; SmallVector < std :: pair < unsigned , MDNode * > , <NUM_LIT> > MD ; I . getAllMetadataOtherThanDebugLoc ( MD ) ; for ( unsigned i = <NUM_LIT> , e = MD . size ( ) ; i != e ; ++ i ) { Load -> setMetadata ( MD [ i ] . first , MD [ i ] . second ) ; }

Value * BitCastLoad = Builder . CreateBitCast ( Load , I . getType ( ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; if ( Op == <STR_LIT> ) Ops = { Chain , Dst , LenAdj , Byte } ; else Ops = { Chain , Dst , Src , LenAdj } ; return DAG . getNode ( Op , DL , VTs , Ops ) ;


<s> if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } }


<s> uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SDValue T = DAG . getConstant ( Value16 , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , T ) ; return DAG . getNode ( <STR_LIT> , dl , VT , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } case <STR_LIT> : { SDValue T = DAG . getConstant ( unsigned ( SplatBits ) , VT . getVectorElementType ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , T , T , T , T ) ;


<s> StringRef getPassName ( ) const override {


<s> auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( & NewDestBB ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << * AllocaTy << <STR_LIT> << * VectorTy << '\n' ) ; for ( std :: vector < Value * > :: iterator I = WorkList . begin ( ) , E = WorkList . end ( ) ; I != E ; ++ I ) { Instruction * Inst = cast < Instruction > ( * I ) ; IRBuilder < > Builder ( Inst ) ; switch ( Inst -> getOpcode ( ) ) { case Instruction :: Load : { Value * Ptr = Inst -> getOperand ( <NUM_LIT> ) ; Value * Index = calculateVectorIndex ( Ptr , GEPVectorIdx ) ; Value * BitCast = Builder . CreateBitCast ( Alloca , VectorTy -> getPointerTo ( <NUM_LIT> ) ) ; Value * VecValue = Builder . CreateLoad ( BitCast ) ; Value * ExtractElement = Builder . CreateExtractElement ( VecValue , Index ) ; Inst -> replaceAllUsesWith ( ExtractElement ) ; Inst -> eraseFromParent ( ) ; break ; } case Instruction :: Store : { Value * Ptr = Inst -> getOperand ( <NUM_LIT> ) ; Value * Index = calculateVectorIndex ( Ptr , GEPVectorIdx ) ; Value * BitCast = Builder . CreateBitCast ( Alloca , VectorTy -> getPointerTo ( <NUM_LIT> ) ) ; Value * VecValue = Builder . CreateLoad ( BitCast ) ; Value * NewVecValue = Builder . CreateInsertElement ( VecValue , Inst -> getOperand ( <NUM_LIT> ) , Index ) ; Builder . CreateStore ( NewVecValue , BitCast ) ; Inst -> eraseFromParent ( ) ; break ; } case Instruction :: BitCast : case Instruction :: AddrSpaceCast : break ; default : Inst -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; }


<s> i != e && ! DefDesc . OpInfo [ i ] . isPredicate ( ) ; ++ i ) NewMI . addOperand ( DefMI -> getOperand ( i ) ) ; unsigned CondCode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Invert ) NewMI . addImm ( getOppositeCondition ( LPCC :: CondCode ( CondCode ) ) ) ; else NewMI . addImm ( CondCode ) ; NewMI . copyImplicitOps ( MI ) ; FalseReg . setImplicit ( ) ; NewMI . addOperand ( FalseReg ) ; NewMI -> tieOperands ( <NUM_LIT> , NewMI -> getNumOperands ( ) - <NUM_LIT> ) ; SeenMIs . insert ( NewMI ) ; SeenMIs . erase ( DefMI ) ; if ( DefMI -> getParent ( ) != MI . getParent ( ) ) NewMI -> clearKillInfo ( ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) {


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;


<s> static std :: string computeDataLayout ( const Triple & TT ) {


<s> uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler :: Success ;


<s> if ( ! ( x & <NUM_LIT> ) ) continue ; if ( ( x & ( x + <NUM_LIT> ) ) == <NUM_LIT> ) { if ( first_bit != NULL ) * first_bit = i ; if ( last_bit != NULL ) * last_bit = ( i + exact_log2 ( x ^ ( x >> <NUM_LIT> ) ) ) & <NUM_LIT> ; return true ; } }


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; DataSection = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION , SectionKind :: getDataRel ( ) ) ; BSSSection = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: XCORE_SHF_DP_SECTION , SectionKind :: getBSS ( ) ) ; MergeableConst4Section = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst4 ( ) ) ; MergeableConst8Section = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst8 ( ) ) ; MergeableConst16Section = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_MERGE | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getMergeableConst16 ( ) ) ; TLSDataSection = DataSection ; TLSBSSSection = BSSSection ; ReadOnlySection = Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: XCORE_SHF_CP_SECTION , SectionKind :: getReadOnlyWithRel ( ) ) ; DataRelSection = DataRelLocalSection = DataSection ; DataRelROSection = DataRelROLocalSection = ReadOnlySection ;


<s> static bool IsVPRDefinedOrKilledByBlock ( MachineBasicBlock :: iterator Iter , MachineBasicBlock :: iterator End ) {

for ( ; Iter != End ; ++ Iter ) if ( Iter -> definesRegister ( <STR_LIT> ) || Iter -> killsRegister ( <STR_LIT> ) ) return true ;


<s> storeToStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , int Offset , DebugLoc dl ) const { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; Offset /= <NUM_LIT> ; bool isU6 = isImmU6 ( Offset ) ; if ( ! isU6 && ! isImmU16 ( Offset ) ) report_fatal_error ( <STR_LIT> + Twine ( Offset ) ) ;


<s> return __builtin_aarch64_frintnv2df ( __a ) ;


<s> ScheduleDAGMI * DAG = new ScheduleDAGMI ( C , ST . use<ISA_LIT>PostRASchedStrategy ( ) ? std :: make_unique < <ISA_LIT>PostRASchedStrategy > ( C ) : std :: make_unique < PostGenericScheduler > ( C ) , true ) ; return DAG ;


<s> Op -> Kind = k_MemoryReg ; Op -> Mem . Base = Base ; Op -> Mem . OffsetReg = offsetReg ; Op -> Mem . Off = nullptr ;


<s> static bool dep_between_memop_and_curr ( rtx memop ) { rtx load_reg ; int opno ; gcc_assert ( GET_CODE ( memop ) == SET ) ; if ( ! REG_P ( SET_DEST ( memop ) ) ) return false ; load_reg = SET_DEST ( memop ) ; for ( opno = <NUM_LIT> ; opno < recog_data . n_operands ; opno ++ ) { rtx operand = recog_data . operand [ opno ] ;

if ( REG_P ( operand ) && reg_overlap_mentioned_p ( load_reg , operand ) ) return true ;


<s> rtx alpha_use_linkage ( rtx linkage ATTRIBUTE_UNUSED , tree cfundecl ATTRIBUTE_UNUSED , int lflag ATTRIBUTE_UNUSED , int rflag ATTRIBUTE_UNUSED ) {


<s> RegNo = <NUM_LIT> ; const AsmToken & TokPercent = Parser . getTok ( ) ; assert ( TokPercent . is ( AsmToken :: Percent ) && <STR_LIT> ) ; StartLoc = TokPercent . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; RegNo = MatchRegisterName ( Tok . getString ( ) ) ; if ( RegNo == <NUM_LIT> && Tok . getString ( ) == <STR_LIT> ) { RegNo = <STR_LIT> ; EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return false ; getParser ( ) . Lex ( ) ; const AsmToken & IntTok = Parser . getTok ( ) ; if ( IntTok . isNot ( AsmToken :: Integer ) ) return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; switch ( IntTok . getIntVal ( ) ) { case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; case <NUM_LIT> : RegNo = <STR_LIT> ; break ; default : return Error ( IntTok . getLoc ( ) , <STR_LIT> ) ; } if ( getParser ( ) . Lex ( ) . isNot ( AsmToken :: RParen ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; EndLoc = Tok . getLoc ( ) ; Parser . Lex ( ) ; return false ; } if ( RegNo == <NUM_LIT> ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ;


<s> const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ;

if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - <NUM_LIT> ) {


<s> <ISA_LIT>FiMalkrz ( ) : MachineFunctionPass ( ID ) {


<s> for ( NodeAddr < RefNode * > RA : IA . Addr -> members ( DFG ) ) {

if ( ! LiveNodes . count ( RA . Id ) ) WorkQ . insert ( RA . Id ) ;


<s> MachineInstr * OpMI = MRI . getVRegDef ( Reg ) ; return get<ISA_LIT>VectorSplatScalar ( * OpMI , MRI ) ;


<s> return __builtin_aarch64_uqaddv4hi_uuu ( __a , __b ) ;


<s> StringRef Name = getIndexedValueName ( BaseName ) ; Instruction * Res = dyn_cast < Instruction > ( IRB -> CreateSub ( Op0 , Op1 , Name ) ) ; Res -> setDebugLoc ( N -> getDebugLoc ( ) ) ; VisitMap [ N ] = Res ;


<s> if ( ( * iptr & <NUM_LIT> ) == <NUM_LIT> ) break ; } if ( i == NOFFSETS ) return ~ <NUM_LIT> ; iptr += SIGN_EXTEND ( GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) | GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | GET_FIELD ( * iptr , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> , <NUM_LIT> ) ; fixup_plabel [ <NUM_LIT> ] = ( unsigned int ) iptr + <NUM_LIT> ;

fixup_plabel [ <NUM_LIT> ] = got [ - <NUM_LIT> ] ;


<s> MVT PartVT = <STR_LIT> ( VecTy . getVectorElementType ( ) , OpsPerWord ) ; for ( unsigned i = <NUM_LIT> ; i != VecLen ; i += OpsPerWord ) { SDValue W = buildVector32 ( Values . slice ( i , OpsPerWord ) , dl , PartVT , DAG ) ; Words . push_back ( DAG . getBitcast ( <STR_LIT> , W ) ) ; } } else { Words . assign ( Values . begin ( ) , Values . end ( ) ) ; } unsigned NumWords = Words . size ( ) ; bool IsSplat = true , IsUndef = true ; SDValue SplatV ; for ( unsigned i = <NUM_LIT> ; i != NumWords && IsSplat ; ++ i ) { if ( isUndef ( Words [ i ] ) ) continue ; IsUndef = false ; if ( ! SplatV . getNode ( ) ) SplatV = Words [ i ] ; else if ( SplatV != Words [ i ] ) IsSplat = false ; } if ( IsUndef ) return DAG . getUNDEF ( VecTy ) ; if ( IsSplat ) { assert ( SplatV . getNode ( ) ) ; auto * IdxN = dyn_cast < ConstantSDNode > ( SplatV . getNode ( ) ) ; if ( IdxN && IdxN -> isNullValue ( ) ) return getZero ( dl , VecTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , SplatV ) ; } SmallVector < ConstantInt * , <NUM_LIT> > Consts ( VecLen ) ; bool AllConst = getBuildVectorConstInts ( Values , VecTy , DAG , Consts ) ; if ( AllConst ) { ArrayRef < Constant * > Tmp ( ( Constant * * ) Consts . begin ( ) , ( Constant * * ) Consts . end ( ) ) ; Constant * CV = ConstantVector :: get ( Tmp ) ; unsigned Align = HwLen ; SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , VecTy , Align ) , DAG ) ; return DAG . getLoad ( VecTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Align ) ; } assert ( <NUM_LIT> * Words . size ( ) == Subtarget . getVectorLength ( ) ) ; SDValue HalfV0 = getInstr ( <STR_LIT> , dl , VecTy , { } , DAG ) ; SDValue HalfV1 = getInstr ( <STR_LIT> , dl , VecTy , { } , DAG ) ; SDValue S = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;

for ( unsigned i = <NUM_LIT> ; i != NumWords / <NUM_LIT> ; ++ i ) {


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA ) return ; <STR_LIT> :: IsaVersion ISA = <STR_LIT> :: getIsaVersion ( getSTI ( ) -> getFeatureBits ( ) ) ;

getTargetStreamer ( ) . EmitDirectiveHSACodeObjectVersion ( <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( MEM_P ( x ) ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) != CONST_INT ) return <NUM_LIT> ;

if ( ( INTVAL ( x ) & <NUM_LIT> ) != <NUM_LIT> ) return <NUM_LIT> ;


<s> APInt UndefBits ( CstSizeInBits , <NUM_LIT> ) ; APInt MaskBits ( CstSizeInBits , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumCstElts ; ++ i ) { Constant * COp = C -> getAggregateElement ( i ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return false ; unsigned BitOffset = i * CstEltSizeInBits ; if ( isa < UndefValue > ( COp ) ) { UndefBits . setBits ( BitOffset , BitOffset + CstEltSizeInBits ) ; continue ; } MaskBits . insertBits ( cast < ConstantInt > ( COp ) -> getValue ( ) , BitOffset ) ; } for ( unsigned i = <NUM_LIT> ; i != NumMaskElts ; ++ i ) {

unsigned BitOffset = i * MaskEltSizeInBits ;


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { static const MCPhysReg GPRList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( GPRList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ;


<s> return __builtin_mve_vrev64q_fv8hf ( __a ) ;


<s> return __builtin_aarch64_fcvtzsv2df ( __a , __b ) ;


<s> if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT> && ( isLong ? Cnt - <NUM_LIT> : Cnt ) < ElementBits ) ;


<s> static <ISA_LIT>Operand * CreateExtend ( <STR_LIT> ExtOp , unsigned Val , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Extend , Ctx ) ; Op -> Extend . Val = <STR_LIT> ( ExtOp , Val ) ;


<s> <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) { EVT PtrTy = getPointerTy ( ) ; int Size = Flags . getByValSize ( ) ; unsigned NumRegs = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned FrameIdx = MFI -> CreateFixedObject ( <NUM_LIT> * NumRegs , VA . getLocMemOffset ( ) , false ) ; SDValue FrameIdxN = DAG . getFrameIndex ( FrameIdx , PtrTy ) ; InVals . push_back ( FrameIdxN ) ; continue ; } else if ( VA . isRegLoc ( ) ) { MVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } else { assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ;


<s> bool <ISA_LIT>MCInst :: hasNewValue ( ) const { const uint64_t F = MCID -> TSFlags ;

return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>_64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>_32Target , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>_64Target , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>_32Target , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>_64Target , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>_32Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>_64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_32Target , create<ISA_LIT>_32AsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>_64Target , create<ISA_LIT>_64AsmBackend ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>_32Target , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>_64Target , createMCStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>_32Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>_64Target , create<ISA_LIT>MCInstPrinter ) ;

TargetRegistry :: RegisterMCRelocationInfo ( The<ISA_LIT>_32Target , create<ISA_LIT>MCRelocationInfo ) ;


<s> bool BigStack = ( RS && estimateStackSize ( MF ) >= TII . estimateRSStackLimit ( MF ) ) || MFI -> hasVarSizedObjects ( ) || ( MFI -> adjustsStack ( ) && ! hasReservedCallFrame ( MF ) ) ; if ( ! BigStack ) return ; const uint16_t * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; uint16_t ExtraReg = <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) {

if ( <STR_LIT> . contains ( CSRegs [ i ] ) && ! MF . getRegInfo ( ) . isPhysRegUsed ( CSRegs [ i ] ) ) {


<s> UP . PartialOptSizeThreshold = <NUM_LIT> ;


<s> default : return NULL ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DL , TII -> get ( AMDGPU :: S_OR_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) . addReg ( Reg ) ;


<s> case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Nand , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Max , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: Min , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMax , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicMinMaxOp ( MBB , MBBI , AtomicRMWInst :: UMin , true , <NUM_LIT> , NextMBBI ) ; case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ;


<s> bool isInstSeg ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < <NUM_LIT> ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < <NUM_LIT> ; i ++ ) {


<s> A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , nullptr ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & Inst ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { const Value * V = CI -> getCalledValue ( ) ; Type * T = nullptr ; if ( V ) T = V -> getType ( ) ; PointerType * PFT = nullptr ; if ( T ) PFT = dyn_cast < PointerType > ( T ) ; FunctionType * FT = nullptr ;

if ( PFT ) FT = dyn_cast < FunctionType > ( PFT -> getElementType ( ) ) ;


<s> bool AMDGPUSubtarget :: hasVertexCache ( ) const {


<s> arg1 = args [ <NUM_LIT> ] ; if ( ( TREE_CODE ( arg0 ) == INTEGER_CST && TREE_CODE ( arg1 ) == INTEGER_CST ) || TARGET_MUL32_HIGH ) return fold_build2 ( MULT_EXPR , unsigned_intDI_type_node , fold_convert ( unsigned_intDI_type_node , arg0 ) , fold_convert ( unsigned_intDI_type_node , arg1 ) ) ; break ; default : internal_error ( <STR_LIT> ) ; break ; } return NULL ;


<s> static SDValue combineShiftRightArithmetic ( SDNode * N , SelectionDAG & DAG ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N0 . getValueType ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( VT . isVector ( ) || N1 . getOpcode ( ) != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || N0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 . getOperand ( <NUM_LIT> ) ; APInt ShlConst = ( cast < ConstantSDNode > ( N01 ) ) -> getAPIntValue ( ) ; APInt SarConst = ( cast < ConstantSDNode > ( N1 ) ) -> getAPIntValue ( ) ; EVT CVT = N1 . getValueType ( ) ; if ( SarConst . isNegative ( ) ) return SDValue ( ) ; for ( MVT SVT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { unsigned ShiftSize = SVT . getSizeInBits ( ) ; if ( ShiftSize >= Size || ShlConst != Size - ShiftSize ) continue ; SDLoc DL ( N ) ;

SDValue NN = DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getValueType ( SVT ) ) ;


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI , bool RelaxAll , bool NoExecStack ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB , OS , Emitter , STI ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; if ( NoExecStack ) S -> getAssembler ( ) . setNoExecStack ( true ) ;

S -> EmitBundleAlignMode ( MIPS_NACL_BUNDLE_ALIGN ) ;


<s> bool opCanUseLiteralConstant ( unsigned OpType ) const {

return OpType >= <STR_LIT> && OpType <= <STR_LIT> ;


<s> struct machine_function * p = ggc_cleared_alloc < machine_function > ( ) ; p -> ret_reg_mode = VOIDmode ;


<s> MCNumEmitted += <NUM_LIT> ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandAddTPRel ( MI , OS , Fixups , STI ) ; MCNumEmitted += <NUM_LIT> ; return ; } switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write ( OS , Bits , <STR_LIT> ) ; break ; } }


<s> for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) , Call ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC , false , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( VA . needsCustom ( ) ) { if ( ! VA . isRegLoc ( ) ) return false ; if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; if ( RegVT == <STR_LIT> ) { if ( ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ;


<s> return ci . getSite ( ) -> isInSCC ( ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( ! skipFunction ( MF . getFunction ( ) ) ) { initialize ( MF ) ; return processAtomicInsts ( ) ; }


<s> isEligibleForTailCallOptimization ( const <ISA_LIT>CC & <ISA_LIT>CCInfo , unsigned NextStackOffset , const <ISA_LIT>FunctionInfo & FI ) const { if ( ! Enable<ISA_LIT>TailCalls ) return false ; if ( <ISA_LIT>CCInfo . hasByValArg ( ) || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ;


<s> void printlea32mem ( const MachineInstr * MI , unsigned OpNo ) { O << <STR_LIT> ; printLeaMemReference ( MI , OpNo ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI . definesRegister ( DestReg ) && <STR_LIT> ) ; bool IsPrimed = <STR_LIT> . contains ( DestReg ) ; Register Reg = <STR_LIT> + ( DestReg - ( IsPrimed ? <STR_LIT> : <STR_LIT> ) ) * <NUM_LIT> ; bool IsLittleEndian = Subtarget . isLittleEndian ( ) ; emitAccSpillRestoreInfo ( MBB , IsPrimed , true ) ; addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , Reg ) , FrameIndex , IsLittleEndian ? <NUM_LIT> : <NUM_LIT> ) ;

addFrameReference ( BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , Reg + <NUM_LIT> ) , FrameIndex , IsLittleEndian ? <NUM_LIT> : <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>GlobalRegistry :: getScalarOrVectorBitWidth ( const <ISA_LIT>Type * Type ) const { assert ( Type && <STR_LIT> ) ; if ( Type -> getOpcode ( ) == <STR_LIT> ) { auto EleTypeReg = Type -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Type = get<ISA_LIT>TypeForVReg ( EleTypeReg ) ; } if ( Type -> getOpcode ( ) == <STR_LIT> || Type -> getOpcode ( ) == <STR_LIT> ) return Type -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Type -> getOpcode ( ) == <STR_LIT> ) return <NUM_LIT> ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> bool hasFastSHLDRotate ( ) const { return HasFastSHLDRotate ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {

Subtarget = static_cast < <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) ;


<s> case <STR_LIT> : Val = performSHLCombine ( N , DAG , DCI , Subtarget ) ; break ; case <STR_LIT> : return performSRACombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSRLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVSELECTCombine ( N , DAG ) ; case <STR_LIT> : Val = performXORCombine ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : Val = performSETCCCombine ( N , DAG ) ; break ; } if ( Val . getNode ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ; N -> printrWithDepth ( dbgs ( ) , & DAG ) ; dbgs ( ) << <STR_LIT> ; Val . getNode ( ) -> printrWithDepth ( dbgs ( ) , & DAG ) ; dbgs ( ) << <STR_LIT> ) ; return Val ; } return <ISA_LIT>TargetLowering :: PerformDAGCombine ( N , DCI ) ;


<s> } assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * Paired . I -> memoperands_begin ( ) ; MachineInstr * New = MIB . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; unsigned SubRegIdx0 , SubRegIdx1 ; std :: tie ( SubRegIdx0 , SubRegIdx1 ) = getSubRegIdxs ( CI , Paired ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Dest1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ;

moveInstsAfter ( Copy1 , CI . InstsToMove ) ;


return isSCSrcB32 ( ) || isLiteralImm ( <STR_LIT> ) || isExpr ( ) ;


<s> return new <ISA_LIT>LowerEmscriptenEHSjLj ( DoEH , DoSjLj ) ;


<s> } else if ( NumElts == <NUM_LIT> ) { SDValue StoreVal0 = OutVals [ <NUM_LIT> ] ; SDValue StoreVal1 = OutVals [ <NUM_LIT> ] ; if ( NeedExtend ) { StoreVal0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreVal0 ) ; StoreVal1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreVal1 ) ; } SDValue Ops [ ] = { Chain , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , StoreVal0 , StoreVal1 } ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , EltVT , MachinePointerInfo ( ) ) ; } else { unsigned VecSize = <NUM_LIT> ; if ( OutVals [ <NUM_LIT> ] . getValueSizeInBits ( ) == <NUM_LIT> ) VecSize = <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; EVT VecVT = EVT :: getVectorVT ( F -> getContext ( ) , EltVT , VecSize ) ; unsigned PerStoreOffset = TD . getTypeAllocSize ( VecVT . getTypeForEVT ( F -> getContext ( ) ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += VecSize ) { SDValue StoreVal ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getConstant ( Offset , dl , <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ; EVT ExtendedVT = ( NeedExtend ) ? <STR_LIT> : OutVals [ <NUM_LIT> ] . getValueType ( ) ; StoreVal = OutVals [ i ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( VecSize == <NUM_LIT> ) { Opc = <STR_LIT> ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; } Chain = DAG . getMemIntrinsicNode ( Opc , dl , DAG . getVTList ( <STR_LIT> ) , Ops , EltVT , MachinePointerInfo ( ) ) ; Offset += PerStoreOffset ; } }


<s> bool <ISA_LIT>DAGToDAGISel :: selectAddrRi ( SDValue Addr , SDValue & Base , SDValue & Offset , SDValue & AluOp ) { return selectAddrRiSpls ( Addr , Base , Offset , AluOp , true ) ;


assert ( Kind == k_SysReg && <STR_LIT> ) ;


<s> return getJumpTableBaseAddr ( MR -> getJumpTableIndex ( ) ) ; case <STR_LIT> : case <STR_LIT> : return getConstantPoolEntryAddr ( MR -> getConstantPoolIndex ( ) ) ; case <STR_LIT> : { <ISA_LIT>ConstantPoolValue * ACPV = ( <ISA_LIT>ConstantPoolValue * ) MR -> getConstantVal ( ) ; assert ( ( ! ACPV -> hasModifier ( ) && ! ACPV -> mustAddCurrentAddress ( ) ) && <STR_LIT> ) ;

intptr_t Addr = ( intptr_t ) ( MR -> getResultPointer ( ) ) ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> case CASE_VFMA_SPLATS ( FNMSUB ) : case CASE_VFMA_OPCODE_LMULS ( FMACC , VV ) : case CASE_VFMA_OPCODE_LMULS ( FMSAC , VV ) : case CASE_VFMA_OPCODE_LMULS ( FNMACC , VV ) : case CASE_VFMA_OPCODE_LMULS ( FNMSAC , VV ) : case CASE_VFMA_OPCODE_LMULS ( MADD , VX ) : case CASE_VFMA_OPCODE_LMULS ( NMSUB , VX ) : case CASE_VFMA_OPCODE_LMULS ( MACC , VX ) : case CASE_VFMA_OPCODE_LMULS ( NMSAC , VX ) : case CASE_VFMA_OPCODE_LMULS ( MACC , VV ) : case CASE_VFMA_OPCODE_LMULS ( NMSAC , VV ) : { assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ( OpIdx1 == <NUM_LIT> || OpIdx2 == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Opc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMACC , FMADD ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMADD , FMACC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMSAC , FMSUB ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FMSUB , FMSAC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMACC , FNMADD ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMADD , FNMACC ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMSAC , FNMSUB ) CASE_VFMA_CHANGE_OPCODE_SPLATS ( FNMSUB , FNMSAC ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FMACC , FMADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FMSAC , FMSUB , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FNMACC , FNMADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( FNMSAC , FNMSUB , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MACC , MADD , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MADD , MACC , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSAC , NMSUB , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSUB , NMSAC , VX ) CASE_VFMA_CHANGE_OPCODE_LMULS ( MACC , MADD , VV ) CASE_VFMA_CHANGE_OPCODE_LMULS ( NMSAC , NMSUB , VV ) } auto & WorkingMI = cloneIfNew ( MI ) ;


<s> return <ISA_LIT>ABIInfo ( <STR_LIT> ) ;


<s> rtx dest ; int dest_uid ; rtx pat = PATTERN ( branch ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; dest = SET_SRC ( pat ) ;

if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , <NUM_LIT> ) ;


<s> static bool shouldConvert ( const Constant * Cst ) { if ( isa < const UndefValue > ( Cst ) ) return false ; if ( Cst -> isZeroValue ( ) ) return false ; if ( Stress ) return true ; if ( Cst -> getType ( ) -> isVectorTy ( ) ) return false ; return isConstantUsingVectorTy ( Cst -> getType ( ) ) ;


<s> for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) Dec = & MI ; else if ( MI . getOpcode ( ) == <STR_LIT> ) End = & MI ; else if ( MI . getDesc ( ) . isCall ( ) ) Revert = true ; if ( ! Dec ) continue ; if ( MI . mayLoad ( ) || MI . mayStore ( ) ) Revert = MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; } if ( Dec && End && Revert ) break ; } if ( Start || Dec || End ) { if ( ! Start || ! Dec || ! End ) report_fatal_error ( <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Changed ; } if ( ! End -> getOperand ( <NUM_LIT> ) . isMBB ( ) || End -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getHeader ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( ! BBUtils -> isBBInRange ( End , ML -> getHeader ( ) , <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Revert = true ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Start << <STR_LIT> << * Dec << <STR_LIT> << * End ) ; Expand ( ML , Start , Dec , End , Revert ) ; return true ;


<s> std :: pair < int , int > Res = { - <NUM_LIT> , - <NUM_LIT> } ; switch ( VectorKind ) { case RegKind :: NeonVector : Res = StringSwitch < std :: pair < int , int >> ( Suffix . lower ( ) ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Default ( { - <NUM_LIT> , - <NUM_LIT> } ) ; break ; case RegKind :: SVEPredicateVector : case RegKind :: SVEDataVector : case RegKind :: Matrix : Res = StringSwitch < std :: pair < int , int >> ( Suffix . lower ( ) ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Case ( <STR_LIT> , { <NUM_LIT> , <NUM_LIT> } ) . Default ( { - <NUM_LIT> , - <NUM_LIT> } ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) {

RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ;

if ( flags & FLAG_PREFETCH_MEMORY ) return true ;


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ;

int64_t ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ;


<s> const DataLayout * getDataLayout ( ) const override {


<s> rtx call [ <NUM_LIT> ] ; rtx insn ; gcc_assert ( INTVAL ( cookie ) == <NUM_LIT> ) ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , flag ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( <NUM_LIT> , call ) ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ;


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetMachO ( ) && ! Subtarget -> isThumb1Only ( ) ;

UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ;


<s> int MemOpStart = <STR_LIT> ( MCID . TSFlags ) ; if ( MemOpStart == - <NUM_LIT> ) return None ; MemOpStart += <STR_LIT> ( MCID ) ; const MCOperand & SegReg = Inst . getOperand ( MemOpStart + <STR_LIT> ) ; const MCOperand & BaseReg = Inst . getOperand ( MemOpStart + <STR_LIT> ) ; const MCOperand & IndexReg = Inst . getOperand ( MemOpStart + <STR_LIT> ) ; const MCOperand & ScaleAmt = Inst . getOperand ( MemOpStart + <STR_LIT> ) ;

const MCOperand & Disp = Inst . getOperand ( MemOpStart + <STR_LIT> ) ;


<s> uint64_t Rsrc = TII -> getDefaultRsrcDataFormat ( ) | APInt :: getAllOnesValue ( <NUM_LIT> ) . getZExtValue ( ) ; SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . buildRSRC ( * CurDAG , DL , Ptr , <NUM_LIT> , Rsrc ) , <NUM_LIT> ) ;


<s> unsigned getVarArgsFrameIndex ( ) const {


<s> int * reg = & pcum -> reg ; machine_mode mode = arg . mode ;

int param_size = csky_num_arg_regs ( mode , arg . type , pcum -> is_stdarg ) ;


<s> std :: vector < CallInst * > PreserveDITypeCalls ; for ( auto & F : M ) { for ( auto & BB : F ) { for ( auto & I : BB ) { auto * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; const auto * GV = dyn_cast < GlobalValue > ( Call -> getCalledOperand ( ) ) ; if ( ! GV ) continue ; if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { if ( ! Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ) report_fatal_error ( <STR_LIT> ) ; PreserveDITypeCalls . push_back ( Call ) ; } } } } if ( PreserveDITypeCalls . empty ( ) ) return false ; std :: string BaseName = <STR_LIT> ; int Count = <NUM_LIT> ; for ( auto Call : PreserveDITypeCalls ) { const ConstantInt * Flag = dyn_cast < ConstantInt > ( Call -> getArgOperand ( <NUM_LIT> ) ) ; assert ( Flag ) ;

uint64_t FlagValue = Flag -> getValue ( ) . getZExtValue ( ) ;


<s> bool <ISA_LIT>ATTAsmParser :: ParseDirective ( AsmToken DirectiveID ) {

StringRef IDVal = DirectiveID . getIdentifier ( ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ; CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp ) ; if ( std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) && std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) ) { modifyCmp ( HeadCmpMI , HeadCmpInfo ) ; modifyCmp ( TrueCmpMI , TrueCmpInfo ) ; Changed = true ; } } else if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { bool adjustHeadCond = ( HeadImm < TrueImm ) ; if ( HeadCmp == <STR_LIT> ) { adjustHeadCond = ! adjustHeadCond ; } if ( adjustHeadCond ) { Changed |= adjustTo ( HeadCmpMI , HeadCmp , TrueCmpMI , TrueImm ) ;


<s> LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , rr ) \ LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , rr_REV ) \ LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , rm ) \ LLVM_EXPAND_INSTR_SIZES ( MNEMONIC , mr ) \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : \ case <STR_LIT> ## <NUM_LIT> : LLVM_EXPAND_ADC_SBB_INSTR ( ADC ) return FlagArithMnemonic :: ADC ; LLVM_EXPAND_ADC_SBB_INSTR ( SBB ) return FlagArithMnemonic :: SBB ;

LLVM_EXPAND_INSTR_SIZES ( RCL , rCL ) LLVM_EXPAND_INSTR_SIZES ( RCL , r1 ) LLVM_EXPAND_INSTR_SIZES ( RCL , ri ) return FlagArithMnemonic :: RCL ;


<s> static void aarch64_emit_atomic_load_op ( enum aarch64_atomic_load_op_code code , machine_mode mode , rtx dst , rtx src , rtx mem , rtx model ) { typedef rtx ( * aarch64_atomic_load_op_fn ) ( rtx , rtx , rtx , rtx ) ; const aarch64_atomic_load_op_fn plus [ ] = { gen_aarch64_atomic_loadaddqi , gen_aarch64_atomic_loadaddhi , gen_aarch64_atomic_loadaddsi , gen_aarch64_atomic_loadadddi } ; const aarch64_atomic_load_op_fn eor [ ] = { gen_aarch64_atomic_loadeorqi , gen_aarch64_atomic_loadeorhi , gen_aarch64_atomic_loadeorsi , gen_aarch64_atomic_loadeordi } ; const aarch64_atomic_load_op_fn ior [ ] = { gen_aarch64_atomic_loadsetqi , gen_aarch64_atomic_loadsethi , gen_aarch64_atomic_loadsetsi , gen_aarch64_atomic_loadsetdi } ; const aarch64_atomic_load_op_fn bic [ ] = { gen_aarch64_atomic_loadclrqi , gen_aarch64_atomic_loadclrhi , gen_aarch64_atomic_loadclrsi , gen_aarch64_atomic_loadclrdi } ; aarch64_atomic_load_op_fn gen ; int idx = <NUM_LIT> ; switch ( mode ) { case E_QImode : idx = <NUM_LIT> ; break ; case E_HImode : idx = <NUM_LIT> ; break ; case E_SImode : idx = <NUM_LIT> ; break ;

case E_DImode : idx = <NUM_LIT> ; break ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ;


<s> if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ;

unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ;


<s> BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; } else { unsigned Opc = ABI . GetPtrAdduOp ( ) ; if ( Amount < <NUM_LIT> ) { Opc = ABI . GetPtrSubuOp ( ) ;


<s> assert ( <ISA_LIT>VType :: isValidSEW ( SEW ) && <STR_LIT> ) ; <ISA_LIT>VSEW ElementWidth = static_cast < <ISA_LIT>VSEW > ( Log2_32 ( SEW / <NUM_LIT> ) ) ; <ISA_LIT>VLMUL Multiplier = static_cast < <ISA_LIT>VLMUL > ( VLMul ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) ; if ( VLIndex >= <NUM_LIT> ) { Register DestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . addReg ( DestReg , RegState :: Define | RegState :: Dead ) . addReg ( MI . getOperand ( VLIndex ) . getReg ( ) ) ; } else MIB . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MIB . addImm ( <ISA_LIT>VType :: encodeVTYPE ( Multiplier , ElementWidth , true , false ) ) ;

MI . getOperand ( SEWIndex ) . setImm ( - <NUM_LIT> ) ;


return __builtin_mve_vcvtnq_m_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __p ) ;


<s> wr = ( wr << <NUM_LIT> ) | ( wr & <NUM_LIT> ) ; } wr = ( wr << <NUM_LIT> ) | ( wr & <NUM_LIT> ) ; return wr ;


<s> Inst . addOperand ( MCOperand :: createReg ( GPReg ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( SaveLocation ) ) ; } getStreamer ( ) . emitInstruction ( Inst , STI ) ; forbidModuleDirective ( ) ;


<s> DebugLoc DL = Insert -> getDebugLoc ( ) ; TIDReg = RI . findUnusedRegister ( MF -> getRegInfo ( ) , & <STR_LIT> ) ; if ( TIDReg == <STR_LIT> ) return TIDReg ; if ( ! <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && WorkGroupSize > WavefrontSize ) { unsigned TIDIGXReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_X ) ; unsigned TIDIGYReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Y ) ; unsigned TIDIGZReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: WORKGROUP_ID_Z ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( * MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; for ( unsigned Reg : { TIDIGXReg , TIDIGYReg , TIDIGZReg } ) { if ( ! Entry . isLiveIn ( Reg ) ) Entry . addLiveIn ( Reg ) ; } RS -> enterBasicBlock ( Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; }

BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( <NUM_LIT> ) . addReg ( TIDReg ) ;


<s> case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerABS ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> :


<s> RegisterTarget < Triple :: xtensa > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const {

if ( Subtarget . isDarwinABI ( ) ) return Subtarget . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_RegMask :


<s> SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; bool IsF128 = ( VT == <STR_LIT> ) ; assert ( VT . isFloatingPoint ( ) && VT != <STR_LIT> && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) && <STR_LIT> ) ; bool IsFakeVector = ! VT . isVector ( ) && ! IsF128 ; MVT LogicVT = VT ; if ( IsFakeVector ) LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned EltBits = VT . getScalarSizeInBits ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignMask ( EltBits ) ; const fltSemantics & Sem = SelectionDAG :: EVTToAPFloatSemantics ( VT ) ;

SDValue Mask = DAG . getConstantFP ( APFloat ( Sem , MaskElt ) , dl , LogicVT ) ;


<s> return __builtin_aarch64_clzv2si ( __a ) ;


<s> unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ;

if ( ! IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << <STR_LIT> << ( unsigned int ) TH ;


<s> set_optab_libfunc ( udiv_optab , SImode , <STR_LIT> ) ; set_optab_libfunc ( udiv_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( smod_optab , SImode , <STR_LIT> ) ; set_optab_libfunc ( smod_optab , DImode , <STR_LIT> ) ; set_optab_libfunc ( umod_optab , SImode , <STR_LIT> ) ; set_optab_libfunc ( umod_optab , DImode , <STR_LIT> ) ;


<s> O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> return ( __m256i ) __builtin_ia32_pmovsqd512_mask ( ( __v8di ) __A , ( __v8si ) _mm256_undefined_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && Subtarget . hasFP64 ( ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; return ; } unsigned BeginIdx = <NUM_LIT> ; unsigned SubRegs = <NUM_LIT> ; int Spacing = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && ! Subtarget . hasFP64 ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ;


<s> return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


<s> return ( int8x16_t ) __builtin_aarch64_ashlv16qi ( __a , __b ) ;


<s> OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case Token :

OS << <STR_LIT> << getToken ( ) << <STR_LIT> ;


<s> if ( Index == <NUM_LIT> && Val -> isIntOrIntVectorTy ( ) ) Cost += <NUM_LIT> ; return Cost ; } return BaseT :: getVectorInstrCost ( Opcode , Val , Index ) ;


<s> size_t Start = <NUM_LIT> , Next = Mask . find ( '_' ) ; StringRef Flags = <STR_LIT> ; std :: string SpecReg = Mask . slice ( Start , Next ) . lower ( ) ; if ( Next != StringRef :: npos ) Flags = Mask . slice ( Next + <NUM_LIT> , Mask . size ( ) ) ; unsigned FlagsVal = <NUM_LIT> ; if ( SpecReg == <STR_LIT> ) { FlagsVal = StringSwitch < unsigned > ( Flags ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> ) { if ( ! Flags . empty ( ) ) return MatchOperand_NoMatch ; else FlagsVal = <NUM_LIT> ; } } else if ( SpecReg == <STR_LIT> || SpecReg == <STR_LIT> ) { if ( Flags == <STR_LIT> ) Flags = <STR_LIT> ; for ( int i = <NUM_LIT> , e = Flags . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( Flags . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( FlagsVal == ~ <NUM_LIT> || ( FlagsVal & Flag ) ) return MatchOperand_NoMatch ; FlagsVal |= Flag ; } } else return MatchOperand_NoMatch ; if ( SpecReg == <STR_LIT> ) FlagsVal |= <NUM_LIT> ;


<s> if ( getParser ( ) . parseExpression ( Expression ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;

Operands . push_back ( <STR_LIT> ( Expression , S , E ) ) ;


<s> emitRRX ( Opcode , Reg0 , Reg1 , MCOperand :: createReg ( Reg2 ) , IDLoc , STI ) ;


<s> unsigned <ISA_LIT>ParamManager :: addArgumentParam ( unsigned AS , const Argument & Arg , const StringRef ParamName ) { unsigned Param = addParam ( ( AS == <STR_LIT> ) ? <ISA_LIT>_PARAM_TYPE_ARGUMENT : <ISA_LIT>_PARAM_TYPE_KERNARG , Arg . getType ( ) , ParamName ) ;

AllParams . find ( Param ) -> second . Arg = & Arg ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) {

if ( ( M [ i ] >= <NUM_LIT> && ( unsigned ) M [ i ] != i + WhichResult ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + <NUM_LIT> ] != i + WhichResult ) ) return false ;


<s> break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TOC_LO ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ; break ; } if ( MO . getTargetFlags ( ) == <STR_LIT> ) RefKind = MCSymbolRefExpr :: VK_PLT ; const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; const <ISA_LIT>Subtarget * Subtarget = & ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) ; const TargetMachine & TM = Printer . TM ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Symbol , RefKind , Ctx ) ; if ( Subtarget -> isSecurePlt ( ) && TM . isPositionIndependent ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC && MO . getTargetFlags ( ) == <STR_LIT> ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Ctx ) , Ctx ) ; if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; if ( MO . getTargetFlags ( ) & <STR_LIT> ) { const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MCExpr * PB = MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , PB , Ctx ) ;


<s> bool hasFfl1 ( ) const { return HasFfl1 ;


<s> if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( RunFree ) { if ( Imm . getBitWidth ( ) <= <NUM_LIT> && ( isShiftedMask_32 ( Imm . getZExtValue ( ) ) || isShiftedMask_32 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; if ( ST -> is<ISA_LIT>64 ( ) && ( isShiftedMask_64 ( Imm . getZExtValue ( ) ) || isShiftedMask_64 ( ~ Imm . getZExtValue ( ) ) ) ) return TTI :: TCC_Free ; } if ( UnsignedFree && isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( ShiftedFree && ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Free ; } return <ISA_LIT>TTIImpl :: getIntImmCost ( Imm , Ty ) ;


<s> void AMDGPUInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) {


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> const MCConstantExpr * Value = dyn_cast_or_null < MCConstantExpr > ( Expr ) ; if ( check ( ! Value , L , <STR_LIT> ) ) return true ; Out = Value -> getValue ( ) ; return false ;


<s> assert ( rsym != NULL && <STR_LIT> ) ; if ( config ( ) . isCodeStatic ( ) ) return ; assert ( pSection . getLink ( ) != NULL ) ; if ( ( pSection . getLink ( ) -> flag ( ) & llvm :: ELF :: SHF_ALLOC ) == <NUM_LIT> ) return ; if ( rsym -> isLocal ( ) ) scanLocalReloc ( pReloc , pLinker , pModule , pSection ) ; else scanGlobalReloc ( pReloc , pLinker , pModule , pSection ) ;

if ( rsym -> isUndef ( ) && ! rsym -> isDyn ( ) && ! rsym -> isWeak ( ) && ! rsym -> isNull ( ) ) issueUndefRef ( pReloc , pSection , pInput ) ;


<s> SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; const GlobalValue * GV = N -> getGlobal ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( UseGOT ) { SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <NUM_LIT> ) ; SDValue Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , Addr ) , <NUM_LIT> ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load , TPReg ) ; } SDValue AddrHi = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrAdd = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue AddrLo = DAG . getTargetGlobalAddress ( GV , DL , Ty , <NUM_LIT> , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; SDValue TPReg = DAG . getRegister ( <STR_LIT> , XLenVT ) ;

SDValue MNAdd = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , TPReg , AddrAdd ) , <NUM_LIT> ) ;


<s> return Create ( VK_AARCH64_ABS_G0_NC , Expr , Ctx ) ;


<s> return <STR_LIT> ; } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) ) ) return <STR_LIT> ; if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && is64Bit ( ) ) return <STR_LIT> ; return <STR_LIT> ;


<s> MCELFObjectTargetWriter * MOTW = new AMDGPUELFObjectWriter ( ) ;

return createELFObjectWriter ( MOTW , OS , true ) ;


<s> if ( isV9 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ;

Data64bitsDirective = ( isV9 ) ? <STR_LIT> : nullptr ;


<s> int direct_return ( void ) { if ( reload_completed ) { if ( cfun -> static_chain_decl == <NUM_LIT> && ( spu_saved_regs_size ( ) + get_frame_size ( ) + crtl -> outgoing_args_size + crtl -> args . pretend_args_size == <NUM_LIT> ) && crtl -> is_leaf ) return <NUM_LIT> ;


<s> void <ISA_LIT>AsmPrinter :: NaClAlignIndirectJumpTargets ( MachineFunction & MF ) { if ( MachineJumpTableInfo * JtInfo = MF . getJumpTableInfo ( ) ) { const std :: vector < MachineJumpTableEntry > & JT = JtInfo -> getJumpTables ( ) ;

for ( unsigned I = <NUM_LIT> ; I < JT . size ( ) ; ++ I ) {


<s> case 'v' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ;


<s> void <ISA_LIT>InstPrinter :: printImmediate64 ( uint64_t Imm , raw_ostream & O ) { int64_t <ISA_LIT>mm = static_cast < int64_t > ( Imm ) ; if ( <ISA_LIT>mm >= - <NUM_LIT> && <ISA_LIT>mm <= <NUM_LIT> ) { O << <ISA_LIT>mm ; return ; } if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( <NUM_LIT> ) ) O << <STR_LIT> ; else if ( Imm == DoubleToBits ( - <NUM_LIT> ) ) O << <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;


<s> MachineBasicBlock & FirstBB = * MIRBuilder . getMF ( ) . getBlockNumbered ( <NUM_LIT> ) ; MIRBuilder . setInsertPt ( FirstBB , FirstBB . instr_end ( ) ) ; SmallVector < ArrayRef < Register > , <NUM_LIT> > VRegArgs ; SmallVector < SmallVector < Register , <NUM_LIT> > , <NUM_LIT> > ToInsert ; for ( const Argument & Arg : CF -> args ( ) ) { if ( MIRBuilder . getDataLayout ( ) . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ToInsert . push_back ( { MIRBuilder . getMRI ( ) -> createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ) ; VRegArgs . push_back ( ToInsert . back ( ) ) ; } FunctionLoweringInfo FuncInfo ; lowerFormalArguments ( MIRBuilder , * CF , VRegArgs , FuncInfo ) ; MIRBuilder . setInsertPt ( OldBB , OldII ) ;


<s> } if ( HAS_NATIVE_OPERANDS ( TargetFlags ) ) { MachineOperand & FlagOp = getFlagOp ( MI , Operand , Flag ) ; if ( Flag == MO_FLAG_NOT_LAST ) { clearFlag ( MI , Operand , MO_FLAG_LAST ) ; } else if ( Flag == MO_FLAG_MASK ) { clearFlag ( MI , Operand , Flag ) ; } else { FlagOp . setImm ( <NUM_LIT> ) ; } } else { MachineOperand & FlagOp = getFlagOp ( MI , Operand ) ; FlagOp . setImm ( FlagOp . getImm ( ) | ( Flag << ( NUM_MO_FLAGS * Operand ) ) ) ;


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return ( IsS11_0_Offset ( Offset . getNode ( ) ) ) ; } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> if ( ! enableMachineScheduler ( ) ) return false ; if ( disablePostRAScheduler ( ) ) return false ; return ! isThumb1Only ( ) ;


<s> IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Store = tryCreateMaskedScatterOffset ( I , Ptr , Builder ) ; if ( ! Store ) Store = tryCreateMaskedScatterBase ( I , Ptr , Builder ) ; if ( ! Store ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: copyRegToReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , unsigned SrcReg , const TargetRegisterClass * DestRC , const TargetRegisterClass * SrcRC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ;


return ( uint16x4_t ) __builtin_neon_vmvnv4hi ( ( int16x4_t ) __a ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitString ( const Twine & Str ) {


<s> uint8_t BitG = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitH = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t EncVal = BitA ; EncVal <<= <NUM_LIT> ; EncVal |= BitB ; EncVal <<= <NUM_LIT> ; EncVal |= BitC ; EncVal <<= <NUM_LIT> ; EncVal |= BitD ; EncVal <<= <NUM_LIT> ; EncVal |= BitE ; EncVal <<= <NUM_LIT> ; EncVal |= BitF ; EncVal <<= <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printBDVAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) {

printAddress ( & MAI , MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) , MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) , O ) ;


<s> return false ; case ELF :: R_<ISA_LIT>_REL24 : unsigned Other = cast < MCSymbolELF > ( Sym ) . getOther ( ) << <NUM_LIT> ;

return ( Other & ELF :: STO_<ISA_LIT>64_LOCAL_MASK ) != <NUM_LIT> ;


<s> MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; MCSTI = & NewSTI ; STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SetupMachineFunction ( MF ) ; emitFunctionBody ( ) ;


<s> get_list_of < IntrinsicInst , <NUM_LIT> > ( & firstBB ) , get_list_of < IntrinsicInst , <NUM_LIT> > ( & secondBB ) } ; vector < Instruction * > selectItrin [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) selectItrin [ i ] = extractIntrinFromList ( itrin [ i ] , intrinId ) ; assert ( selectItrin [ <NUM_LIT> ] . size ( ) == selectItrin [ <NUM_LIT> ] . size ( ) && <STR_LIT> ) ; return createPhiInstruction ( selectItrin , { firstBBLoc , secondBBLoc } , builder , after ) ;


<s> unsigned imm = Val << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; tryAddingPcLoadReferenceComment ( Address , ( Address & ~ <NUM_LIT> ) + imm + <NUM_LIT> , Decoder ) ; return MCDisassembler :: Success ;


<s> if ( STI . hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ;

if ( STI . hasLoadStoreOnCond2 ( ) && getConditionalLoadImmediate ( Opcode ) ) return true ;


<s> assert ( GV && <STR_LIT> ) ; const MCExpr * E = MCSymbolRefExpr :: Create ( Mang -> getSymbol ( GV ) , ( Subtarget -> isTargetDarwin ( ) ? MCSymbolRefExpr :: VK_None : MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 ) , OutContext ) ;


<s> static bool sparc_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_FLAT ) return false ; return ! ( optimize > <NUM_LIT> && crtl -> is_leaf && only_leaf_regs_used ( ) ) ;


<s> rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { loongarch_rewrite_small_data_1 ( & XEXP ( * loc , <NUM_LIT> ) ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const {

SmallVector < CCValAssign , <NUM_LIT> > RVLocs ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TM ( tm ) { StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getBaseRegister ( ) const { return <STR_LIT> ;


<s> if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) aarch64_adjust_sve_callee_save_base ( mode , base_rtx , anchor_reg , offset , ptrue ) ; else if ( GP_REGNUM_P ( regno ) && ( ! offset . is_constant ( & const_offset ) || const_offset >= <NUM_LIT> ) ) { gcc_assert ( known_eq ( start_offset , <NUM_LIT> ) ) ; poly_int64 fp_offset = cfun -> machine -> frame . below_hard_fp_saved_regs_size ; if ( hard_fp_valid_p ) base_rtx = hard_frame_pointer_rtx ; else { if ( ! anchor_reg ) { anchor_reg = gen_rtx_REG ( Pmode , STACK_CLASH_SVE_CFA_REGNUM ) ; emit_insn ( gen_add3_insn ( anchor_reg , base_rtx , gen_int_mode ( fp_offset , Pmode ) ) ) ; } base_rtx = anchor_reg ; } offset -= fp_offset ; } mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; bool need_cfa_note_p = ( base_rtx != stack_pointer_rtx ) ; if ( ! aarch64_sve_mode_p ( mode ) && ( regno2 = aarch64_next_callee_save ( regno + <NUM_LIT> , limit ) ) <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && known_eq ( GET_MODE_SIZE ( mode ) , cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine -> frame . reg_offset [ regno ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset += GET_MODE_SIZE ( mode ) ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; if ( aarch64_emit_cfi_for_reg_p ( regno2 ) ) { if ( need_cfa_note_p ) aarch64_add_cfa_expression ( insn , reg2 , stack_pointer_rtx , sp_offset + GET_MODE_SIZE ( mode ) ) ; else RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } regno = regno2 ; } else if ( mode == VNx2DImode && BYTES_BIG_ENDIAN ) { insn = emit_insn ( gen_aarch64_pred_mov ( mode , mem , ptrue , reg ) ) ; need_cfa_note_p = true ; } else if ( aarch64_sve_mode_p ( mode ) ) insn = emit_insn ( gen_rtx_SET ( mem , reg ) ) ;

else insn = emit_move_insn ( mem , reg ) ;


<s> <ISA_LIT>IREmitter :: <ISA_LIT>IREmitter ( Decompiler * TheDec , raw_ostream & InfoOut , raw_ostream & ErrOut ) : IREmitter ( TheDec , InfoOut , ErrOut ) {


<s> unsigned long int mask ; unsigned long int first ; unsigned long int last ; int i ; static char buff [ <NUM_LIT> ] ; if ( count <= ( TARGET_LONG_CALLS ? <NUM_LIT> : <NUM_LIT> ) ) { error ( <STR_LIT> , count ) ; return NULL ; } gcc_assert ( GET_CODE ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) ) == PLUS ) ; gcc_assert ( GET_CODE ( XEXP ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) , <NUM_LIT> ) ) == REG ) ; gcc_assert ( GET_CODE ( XEXP ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) , <NUM_LIT> ) ) == CONST_INT ) ; stack_bytes = INTVAL ( XEXP ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) , <NUM_LIT> ) ) ; stack_bytes += ( count - ( TARGET_LONG_CALLS ? <NUM_LIT> : <NUM_LIT> ) ) * <NUM_LIT> ; if ( stack_bytes != <NUM_LIT> ) { error ( <STR_LIT> , stack_bytes ) ; return NULL ; } mask = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < count - ( TARGET_LONG_CALLS ? <NUM_LIT> : <NUM_LIT> ) ; i ++ ) { rtx vector_element = XVECEXP ( op , <NUM_LIT> , i ) ; gcc_assert ( GET_CODE ( vector_element ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( vector_element ) ) == REG ) ; gcc_assert ( register_is_ok_for_epilogue ( SET_SRC ( vector_element ) , SImode ) ) ; mask |= <NUM_LIT> << REGNO ( SET_SRC ( vector_element ) ) ; } for ( first = <NUM_LIT> ; first < <NUM_LIT> ; first ++ ) { if ( mask & ( <NUM_LIT> << first ) ) break ;


<s> AM . IndexReg = N ; AM . Scale = <NUM_LIT> ; return false ; } return true ; } AM . BaseType = <ISA_LIT>ISelAddressMode :: RegBase ;


<s> switch ( VA . getLocInfo ( ) ) { default : MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; break ; case CCValAssign :: LocInfo :: SExt : case CCValAssign :: LocInfo :: ZExt : case CCValAssign :: LocInfo :: AExt : { auto Copy = MIRBuilder . buildCopy ( LLT { VA . getLocVT ( ) } , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg , Copy ) ; break ; }


<s> if ( ! PtrAdd || ! isWorthFoldingIntoExtendedReg ( * PtrAdd , MRI ) ) return None ; MachineInstr * OffsetInst = getDefIgnoringCopies ( PtrAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ;

return selectExtendedSHL ( Root , PtrAdd -> getOperand ( <NUM_LIT> ) , OffsetInst -> getOperand ( <NUM_LIT> ) , SizeInBytes , false ) ;


<s> EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Mask . getValueType ( ) . getSizeInBits ( ) ) ; VMask = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> :


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>BaseRegisterInfo & tri , const <ISA_LIT>Subtarget & sti ) : ScoreboardHazardRecognizer ( ItinData ) , TII ( tii ) , TRI ( tri ) , STI ( sti ) , LastMI ( <NUM_LIT> ) , ITBlockSize ( <NUM_LIT> ) {


<s> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: UsrOverflowMutation > ( ) ) ; addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: BankConflictMutation > ( ) ) ;


<s> Register Reg = Op . getReg ( ) ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return true ;


<s> unsigned OpcA = FirstMI . getOpcode ( ) ; unsigned OpcB = MI . getOpcode ( ) ; if ( OpcA == OpcB ) return ! <ISA_LIT>InstrInfo :: isPreLdSt ( FirstMI ) ; bool IsValidLdStrOpc , PairIsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( OpcA , & IsValidLdStrOpc ) ; assert ( IsValidLdStrOpc && <STR_LIT> ) ; if ( NonSExtOpc == getMatchingNonSExtOpcode ( OpcB , & PairIsValidLdStrOpc ) ) {

Flags . setSExtIdx ( NonSExtOpc == ( unsigned ) OpcA ? <NUM_LIT> : <NUM_LIT> ) ;


<s> if ( ! GV ) return false ; ConstantArray * GA = dyn_cast < ConstantArray > ( GV -> getInitializer ( ) ) ; if ( ! GA || GA -> getNumOperands ( ) == <NUM_LIT> ) return false ; Function * InitOrFiniKernel = createInitOrFiniKernelFunction ( M , IsCtor ) ;

IRBuilder < > IRB ( InitOrFiniKernel -> getEntryBlock ( ) . getTerminator ( ) ) ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } return Reserved ;


<s> ConstantSDNode * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ; if ( MaskC ) MaskInReg = DAG . getTargetConstant ( MaskC -> getSExtValue ( ) , dl , MaskVT ) ; else { EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Mask . getValueType ( ) . getSizeInBits ( ) ) ; MaskInReg = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> ) Src = getZeroVector ( Op . getValueType ( ) , Subtarget , DAG , dl ) ;

SDValue Ops [ ] = { Src , MaskInReg , Base , Scale , Index , Disp , Segment , Chain } ;


<s> static bool isRepeatedTargetShuffleMask ( unsigned LaneSizeInBits , MVT VT , ArrayRef < int > Mask , SmallVectorImpl < int > & RepeatedMask ) { return isRepeatedTargetShuffleMask ( LaneSizeInBits , VT . getScalarSizeInBits ( ) , Mask , RepeatedMask ) ;


<s> case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RELAX ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_ALIGN ; }


<s> return ( int8x16_t ) __builtin_neon_vclzv16qi ( __a ) ;


<s> if ( I -> isBundle ( ) ) { MachineBasicBlock :: instr_iterator II = I . getInstrIterator ( ) ; ++ II ; for ( ; II != MBB . instr_end ( ) && II -> isInsideBundle ( ) ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; if ( II -> isImplicitDef ( ) ) continue ; if ( hasHazard ( MBB , II ) ) return true ; } return false ; } assert ( ! I -> isKill ( ) && ! I -> hasDelaySlot ( ) ) ; const <ISA_LIT>InstrInfo * TII = PDSF . TII ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( I -> mayLoad ( ) ) { sawLoad = true ; if ( sawStore ) return true ; } if ( I -> mayStore ( ) ) { if ( sawStore ) return true ; sawStore = true ;


<s> return signedIntDivRemHelper ( Op , DAG , <STR_LIT> ) ;


<s> static rtx gen_frame_store ( rtx reg , rtx frame_reg , int offset ) { return gen_frame_set ( reg , frame_reg , offset , true ) ;


<s> case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } } switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> :


<s> assert ( Offset == <NUM_LIT> ) ; Optional < int > FI ; Register VAddr = Root . getReg ( ) ; if ( const MachineInstr * RootDef = MRI . getVRegDef ( Root . getReg ( ) ) ) { if ( isBaseWithConstantOffset ( Root , MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI . getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI . getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || signBitIsZero ( LHS , MRI ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; } } Register SOffset = FI . hasValue ( ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( FI . hasValue ( ) ) MIB . addFrameIndex ( FI . getValue ( ) ) ; else MIB . addReg ( VAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( SOffset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } } } ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode3 ( SDValue N , SDValue & Base , SDValue & Offset , SDValue & Opc ) { if ( N . getOpcode ( ) == <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) { Base = N ; if ( N . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ;


<s> const char * b = * ( const char * const * ) vb ; while ( * a && * b ) { if ( ISALPHA ( * a ) && ISDIGIT ( * b ) ) return - <NUM_LIT> ; if ( ISDIGIT ( * a ) && ISALPHA ( * b ) ) return <NUM_LIT> ; if ( * a != * b ) return * a - * b ;


<s> return ! arc_legitimate_constant_p ( mode , x ) ;


<s> <ISA_LIT>RedundantCopyElimination ( ) : MachineFunctionPass ( ID ) {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( ( STI . isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ) , ( STI . isTarget64BitLP64 ( ) ? <STR_LIT> : <STR_LIT> ) , <STR_LIT> , ( STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) , Subtarget ( STI ) , RI ( STI . getTargetTriple ( ) ) {


<s> MachineInstr * <ISA_LIT>CFGStructurizer :: insertInstrBefore ( MachineBasicBlock :: iterator I , int NewOpcode ) {


<s> int iq2000_save_fp_regs = ( MAX_ARGS_IN_REGISTERS - cum -> fp_arg_words - iq2000_fp_off ) ; if ( iq2000_save_gp_regs < <NUM_LIT> ) iq2000_save_gp_regs = <NUM_LIT> ; if ( iq2000_save_fp_regs < <NUM_LIT> ) iq2000_save_fp_regs = <NUM_LIT> ; * pretend_size = ( ( iq2000_save_gp_regs * UNITS_PER_WORD ) + ( iq2000_save_fp_regs * UNITS_PER_FPREG ) ) ; if ( ! ( no_rtl ) ) { if ( cum -> arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off ) { rtx ptr , mem ;

ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , - ( iq2000_save_gp_regs * UNITS_PER_WORD ) ) ;


<s> void <ISA_LIT>InstrInfo :: movImm16 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { assert ( isInt < <NUM_LIT> > ( Val ) && <STR_LIT> ) ; uint64_t Hi6 = ( ( Val + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; uint64_t Lo10 = SignExtend64 < <NUM_LIT> > ( Val ) ;

BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Hi6 ) . setMIFlag ( Flag ) ;


<s> if ( TARGET_HITACHI && ! TARGET_NOMACSAVE ) { call_used_regs [ MACH_REG ] = <NUM_LIT> ; call_used_regs [ MACL_REG ] = <NUM_LIT> ; } for ( int regno = FIRST_GENERAL_REG ; regno <= LAST_GENERAL_REG ; regno ++ ) if ( ! fixed_regs [ regno ] && call_used_regs [ regno ] ) SET_HARD_REG_BIT ( reg_class_contents [ SIBCALL_REGS ] , regno ) ; call_used_regs [ FPSCR_MODES_REG ] = <NUM_LIT> ;


<s> CodePointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ;


<s> default : return false ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ; bool CmpLHSIsKill = hasTrivialKill ( CmpLHS ) ; unsigned CmpRHSReg = getRegForValue ( CmpRHS ) ; bool CmpRHSIsKill = hasTrivialKill ( CmpRHS ) ; if ( ! LHSReg || ! RHSReg || ! CmpLHS || ! CmpRHS ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg ; if ( Subtarget -> hasAVX512 ( ) ) { const TargetRegisterClass * VR128X = & <STR_LIT> ; const TargetRegisterClass * VK1 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , VK1 , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned ImplicitDefReg = createResultReg ( VR128X ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; unsigned MovOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned MovReg = fastEmitInst_rrrr ( MovOpcode , VR128X , RHSReg , RHSIsKill , CmpReg , true , ImplicitDefReg , true , LHSReg , LHSIsKill ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( MovReg ) ; } else if ( Subtarget -> hasAVX ( ) ) { const TargetRegisterClass * VR128 = & <STR_LIT> ; unsigned CmpOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BlendOpcode = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned VBlendReg = fastEmitInst_rrr ( BlendOpcode , VR128 , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CmpReg , true ) ; ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( VBlendReg ) ; } else { const TargetRegisterClass * VR128 = & <STR_LIT> ;

unsigned CmpReg = fastEmitInst_rri ( Opc [ <NUM_LIT> ] , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ;


<s> return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;


<s> tree name ; switch ( data_area ) { case DATA_AREA_SDA : name = get_identifier ( <STR_LIT> ) ; break ; case DATA_AREA_TDA : name = get_identifier ( <STR_LIT> ) ; break ; case DATA_AREA_ZDA : name = get_identifier ( <STR_LIT> ) ; break ; default : return ; } DECL_ATTRIBUTES ( decl ) = tree_cons ( name , NULL , DECL_ATTRIBUTES ( decl ) ) ;


<s> static machine_mode pa_c_mode_for_suffix ( char suffix ) { if ( HPUX_LONG_DOUBLE_LIBRARY ) { if ( suffix == 'q' ) return TFmode ; } return VOIDmode ;


<s> static DecodeStatus DecodeGBR32ShortRegister ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) {

if ( RegNo > <NUM_LIT> ) RegNo += <NUM_LIT> ;


<s> bool Src0IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; Register SrcReg1 = MUL -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( Register :: isVirtualRegister ( ResultReg ) ) MRI . constrainRegClass ( ResultReg , RC ) ; if ( Register :: isVirtualRegister ( SrcReg0 ) ) MRI . constrainRegClass ( SrcReg0 , RC ) ; if ( Register :: isVirtualRegister ( SrcReg1 ) ) MRI . constrainRegClass ( SrcReg1 , RC ) ; if ( Register :: isVirtualRegister ( VR ) ) MRI . constrainRegClass ( VR , RC ) ; MachineInstrBuilder MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) . addReg ( SrcReg1 , getKillRegState ( Src1IsKill ) ) . addReg ( VR ) ; InsInstrs . push_back ( MIB ) ; return MUL ;


<s> static bool needsMMLEByteOrder ( unsigned Kind ) { return Kind >= <STR_LIT> && Kind < <STR_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Flags = MI . getFlags ( ) ; LLT Ty = B . getMRI ( ) -> getType ( Dst ) ; auto K = B . buildFConstant ( Ty , numbers :: log2e ) ; auto Mul = B . buildFMul ( Ty , Src , K , Flags ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ;


<s> explicit <ISA_LIT>MCExpr ( <ISA_LIT>ExprKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {


<s> unsigned Idx = isPairedLdSt ( MI ) || <ISA_LIT>InstrInfo :: isPreLdSt ( MI ) ? <NUM_LIT> : <NUM_LIT> ; return MI . getOperand ( Idx ) ;


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , true , OSABI ) ;


<s> return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> static bool aarch64_function_value_regno_p ( const unsigned int regno ) { if ( regno == R0_REGNUM || regno == R1_REGNUM ) return true ; if ( regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS ) return TARGET_FLOAT ; return false ;


<s> void <ISA_LIT>TargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( TII -> isVOP3 ( MI . getOpcode ( ) ) ) { TII -> legalizeOperandsVOP3 ( MRI , MI ) ; if ( const MCOperandInfo * OpInfo = MI . getDesc ( ) . OpInfo ) { unsigned Opc = MI . getOpcode ( ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; for ( auto I : { <STR_LIT> ( Opc , <STR_LIT> :: src0 ) , <STR_LIT> ( Opc , <STR_LIT> :: src1 ) } ) { if ( I == - <NUM_LIT> ) break ; MachineOperand & Op = MI . getOperand ( I ) ; if ( ( OpInfo [ I ] . RegClass != llvm :: <STR_LIT> && OpInfo [ I ] . RegClass != llvm :: <STR_LIT> ) || ! Register :: isVirtualRegister ( Op . getReg ( ) ) || ! TRI -> isAGPR ( MRI , Op . getReg ( ) ) ) continue ; auto * Src = MRI . getUniqueVRegDef ( Op . getReg ( ) ) ; if ( ! Src || ! Src -> isCopy ( ) || ! TRI -> isSGPRReg ( MRI , Src -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; auto * RC = TRI -> getRegClassForReg ( MRI , Op . getReg ( ) ) ; auto * NewRC = TRI -> getEquivalentVGPRClass ( RC ) ; MRI . setRegClass ( Op . getReg ( ) , NewRC ) ;


<s> scalar_int_mode libval_mode = smallest_int_mode_for_size ( <NUM_LIT> * GET_MODE_BITSIZE ( mode ) ) ; rtx libval = emit_library_call_value ( libfunc , NULL_RTX , LCT_CONST , libval_mode , op0 , mode , op1 , mode ) ; rtx quotient = simplify_gen_subreg ( mode , libval , libval_mode , <NUM_LIT> ) ; rtx remainder = simplify_gen_subreg ( mode , libval , libval_mode , GET_MODE_SIZE ( mode ) ) ; gcc_assert ( quotient ) ; gcc_assert ( remainder ) ;


<s> case MachineOperand :: MO_Register : { if ( IsATT ) O << '%' ; O << <ISA_LIT>ATTInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return ; } case MachineOperand :: MO_Immediate : if ( IsATT ) O << '$' ; O << MO . getImm ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_GlobalAddress : { switch ( MI -> getInlineAsmDialect ( ) ) { case InlineAsm :: AD_ATT : O << '$' ; break ; case InlineAsm :: AD_Intel : O << <STR_LIT> ; break ; } PrintSymbolOperand ( MO , O ) ;


<s> static const TargetRegisterClass * getAnyAGPRClassForBitWidth ( unsigned BitWidth ) { if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ;


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) {

return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> unsigned Op = Bead & <NUM_LIT> ; switch ( Op ) { case <STR_LIT> : assert ( ( Ext == <STR_LIT> ) && <STR_LIT> ) ; break ; case <STR_LIT> : Builder . addBits ( <NUM_LIT> , Ext ) ; break ; case <STR_LIT> : Builder . addBits ( <NUM_LIT> , Ext ) ; break ; case <STR_LIT> : Builder . addBits ( <NUM_LIT> , Ext ) ; break ; case <STR_LIT> : Builder . addBits ( <NUM_LIT> , Ext ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op != <STR_LIT> ) Builder . skipBits ( <NUM_LIT> ) ; if ( Op != <STR_LIT> && Op != <STR_LIT> ) Builder . skipBits ( <NUM_LIT> ) ; break ; case <STR_LIT> : Builder . skipBits ( <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Builder . skipBits ( <NUM_LIT> ) ; break ; case <STR_LIT> : Builder . skipBits ( <NUM_LIT> ) ; break ; case <STR_LIT> : Builder . skipBits ( <NUM_LIT> ) ; break ; default :


<s> for ( unsigned i = <NUM_LIT> ; i != HwLen / Rep ; ++ i ) { for ( unsigned j = <NUM_LIT> ; j != Rep ; ++ j ) Mask . push_back ( i + Offset ) ; } SDValue ShuffV = DAG . getVectorShuffle ( ByteTy , dl , ByteVec , Undef , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , ResTy , ShuffV ) ; } unsigned Rep = <NUM_LIT> / ResLen ; for ( unsigned r = <NUM_LIT> ; r != HwLen / ResLen ; ++ r ) { for ( unsigned i = <NUM_LIT> ; i != ResLen ; ++ i ) { for ( unsigned j = <NUM_LIT> ; j != Rep ; ++ j ) Mask . push_back ( Offset + i * BitBytes ) ; } } SDValue Zero = getZero ( dl , <STR_LIT> , DAG ) ; SDValue ShuffV = DAG . getVectorShuffle ( ByteTy , dl , ByteVec , Undef , Mask ) ;

SDValue W0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { ShuffV , Zero } ) ;


<s> unsigned InUseReg = MI . getOperand ( OpNo ) . getReg ( ) ; MI . getOperand ( OpNo ) . ChangeToImmediate ( Imm ) ; if ( empty ( MI . implicit_operands ( ) ) ) return ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; int UseOpIdx = MI . findRegisterUseOperandIdx ( InUseReg , false , TRI ) ; if ( UseOpIdx >= <NUM_LIT> ) {

MachineOperand & MO = MI . getOperand ( UseOpIdx ) ;


<s> unsigned FPDiff = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> - FPDiff ;


<s> int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; OffImm = CurDAG -> getTargetConstant ( RHSC , dl , <STR_LIT> ) ;


<s> if ( ! isLoadInst ( MCInstD ) ) return false ; switch ( getSlotOpCode ( MCInstD ) ) { case LD_TNSR : case LD_TNSR_LOW :