<s> uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , false , DestMBB , MIB ) ; I . eraseFromParent ( ) ; return true ; } if ( C == <NUM_LIT> && Pred == CmpInst :: ICMP_SLT ) { uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , true , DestMBB , MIB ) ; I . eraseFromParent ( ) ; return true ; } } if ( ! VRegAndVal ) { std :: swap ( RHS , LHS ) ; VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; LHSMI = getDefIgnoringCopies ( LHS , MRI ) ; } if ( ! VRegAndVal || VRegAndVal -> Value != <NUM_LIT> ) { if ( ! emitIntegerCompare ( CCMI -> getOperand ( <NUM_LIT> ) , CCMI -> getOperand ( <NUM_LIT> ) , CCMI -> getOperand ( <NUM_LIT> ) , MIB ) ) return false ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC ) . addMBB ( DestMBB ) ; I . eraseFromParent ( ) ; return true ; } if ( tryOptAndIntoCompareBranch ( LHSMI , VRegAndVal -> Value , Pred , DestMBB , MIB ) ) { I . eraseFromParent ( ) ; return true ; } const RegisterBank & RB = * RBI . getRegBank ( LHS , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) return false ; if ( Pred != CmpInst :: ICMP_NE && Pred != CmpInst :: ICMP_EQ ) return false ; const unsigned CmpWidth = MRI . getType ( LHS ) . getSizeInBits ( ) ; unsigned CBOpc = <NUM_LIT> ;

if ( CmpWidth <= <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT> : <STR_LIT> ) ;


<s> void <ISA_LIT>TargetWinCOFFStreamer :: emitARM64WinUnwindCode ( unsigned UnwindCode , int Reg , int Offset ) { auto & S = getStreamer ( ) ; WinEH :: FrameInfo * CurFrame = S . EnsureValidWinFrameInfo ( SMLoc ( ) ) ; if ( ! CurFrame ) return ; auto Inst = WinEH :: Instruction ( UnwindCode , nullptr , Reg , Offset ) ;

if ( InEpilogCFI ) CurFrame -> EpilogMap [ CurrentEpilog ] . push_back ( Inst ) ;


<s> unsigned Flags = cast < ConstantSDNode > ( Node -> getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegDef : case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Clobber : case InlineAsm :: Kind_Mem : { for ( ; NumVals ; -- NumVals , ++ i ) { } break ;


<s> Mode = TargetSubtargetInfo :: ANTIDEP_NONE ;

return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ;


<s> return isImmediate < <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> if ( Opcode == <STR_LIT> && ( RxSBG [ I ] . Mask & <NUM_LIT> ) == <NUM_LIT> ) if ( LoadSDNode * Load = dyn_cast < LoadSDNode > ( Op0 . getNode ( ) ) ) if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return <NUM_LIT> ; if ( Opcode == <STR_LIT> && detectOrAndInsertion ( Op0 , RxSBG [ I ] . Mask ) ) Opcode = <STR_LIT> ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { convertTo ( SDLoc ( N ) , <STR_LIT> , Op0 ) , convertTo ( SDLoc ( N ) , <STR_LIT> , RxSBG [ I ] . Input ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Start , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . End , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Rotate , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , <STR_LIT> , Ops ) ; return convertTo ( SDLoc ( N ) , VT , SDValue ( N , <NUM_LIT> ) ) . getNode ( ) ;


<s> return <STR_LIT> ( getPointerWidth ( ) , Val , Start , End , Size ) ; } InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; if ( ! getLexer ( ) . is ( AsmToken :: LBrac ) ) return CreateMemForInlineAsm ( <NUM_LIT> , Val , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , Identifier , Info ) ; Parser . Lex ( ) ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( SM . getSym ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getBaseReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getIndexReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ;


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , MCSubtargetInfo const & STI ) { return new <ISA_LIT>TargetELFStreamer ( S , STI ) ;


<s> assert ( Encoding == DW_EH_PE_absptr && <STR_LIT> ) ; return MCSymbolRefExpr :: create ( TM . getSymbol ( GV , Mang ) , MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET2 , getContext ( ) ) ;


<s> } case <STR_LIT> : if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base . Reg . getNode ( ) == <NUM_LIT> ) { AM . BaseType = <ISA_LIT>ISelAddressMode :: FrameIndexBase ; AM . Base . FrameIndex = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; return false ; } break ; case <STR_LIT> : { <ISA_LIT>ISelAddressMode Backup = AM ; if ( ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) && ! MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM ) ) return false ; AM = Backup ;


<s> MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; MachineInstr * PtrAdd = getOpcodeDef ( TargetOpcode :: G_PTR_ADD , Root . getReg ( ) , MRI ) ; if ( ! PtrAdd || ! isWorthFoldingIntoExtendedReg ( * PtrAdd , MRI ) ) return None ; MachineOperand & LHS = PtrAdd -> getOperand ( <NUM_LIT> ) ; MachineOperand & RHS = PtrAdd -> getOperand ( <NUM_LIT> ) ; MachineInstr * OffsetInst = getDefIgnoringCopies ( RHS . getReg ( ) , MRI ) ;

auto ExtendedShl = selectExtendedSHL ( Root , LHS , OffsetInst -> getOperand ( <NUM_LIT> ) , SizeInBytes , true ) ;


<s> if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) / <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Memory . OffsetImm ) ) ;


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , false , true , true ) ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizeFMad ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B ) const { LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( Ty . isScalar ( ) ) ; MachineFunction & MF = B . getMF ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) && ! MFI -> getMode ( ) . FP32Denormals ) return true ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) && ! MFI -> getMode ( ) . FP64FP16Denormals ) return true ; MachineIRBuilder HelperBuilder ( MI ) ;


<s> bool IsTrivialInst ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : return true ;


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GO ) ; if ( ! GVA ) return false ; if ( GVA -> hasSection ( ) ) { StringRef Section = GVA -> getSection ( ) ; if ( Section == <STR_LIT> || Section == <STR_LIT> ) return true ;


<s> SmallVector < SmallVector < LiveInterval * , <NUM_LIT> > , <NUM_LIT> > Assignments ( SortedIntervals . size ( ) ) ; BitVector UsedColors ( SortedIntervals . size ( ) ) ; bool Changed = false ; for ( size_t i = <NUM_LIT> , e = SortedIntervals . size ( ) ; i < e ; ++ i ) { LiveInterval * LI = SortedIntervals [ i ] ; unsigned Old = LI -> reg ; size_t Color = i ; const TargetRegisterClass * RC = MRI -> getRegClass ( Old ) ; if ( ! MRI -> isLiveIn ( Old ) ) for ( unsigned C : UsedColors . set_bits ( ) ) { if ( MRI -> getRegClass ( SortedIntervals [ C ] -> reg ) != RC ) continue ; for ( LiveInterval * OtherLI : Assignments [ C ] ) if ( ! OtherLI -> empty ( ) && OtherLI -> overlaps ( * LI ) ) goto continue_outer ; Color = C ; break ; continue_outer : ; } unsigned New = SortedIntervals [ Color ] -> reg ; SlotMapping [ i ] = New ; Changed |= Old != New ; UsedColors . set ( Color ) ; Assignments [ Color ] . push_back ( LI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TargetRegisterInfo :: virtReg2Index ( LI -> reg ) << <STR_LIT> << TargetRegisterInfo :: virtReg2Index ( New ) << <STR_LIT> ) ; } if ( ! Changed ) return false ;


<s> void <ISA_LIT>InstrInfo :: setExecutionDomain ( MachineInstr & MI , unsigned Domain ) const { assert ( Domain > <NUM_LIT> && Domain < <NUM_LIT> && <STR_LIT> ) ; uint16_t dom = ( MI . getDesc ( ) . TSFlags >> <STR_LIT> ) & <NUM_LIT> ; assert ( dom && <STR_LIT> ) ; const uint16_t * table = lookup ( MI . getOpcode ( ) , dom , ReplaceableInstrs ) ; if ( ! table ) { assert ( ( Subtarget . hasAVX2 ( ) || Domain < <NUM_LIT> ) && <STR_LIT> ) ; table = lookup ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX2 ) ; } if ( ! table ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; table = lookupAVX512 ( MI . getOpcode ( ) , dom , ReplaceableInstrsAVX512 ) ; if ( table && Domain == <NUM_LIT> && table [ <NUM_LIT> ] == MI . getOpcode ( ) ) Domain = <NUM_LIT> ; } if ( ! table ) {

assert ( ( Subtarget . hasDQI ( ) || Domain >= <NUM_LIT> ) && <STR_LIT> ) ;


<s> op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( code , mode , dst , src ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ;

emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , op , clob ) ) ) ;


<s> inline bool isVPUInst ( const MCInstrDesc & MCInstD ) {

return getInstrType ( MCInstD ) == <ISA_LIT>II :: TypeVPU ;


<s> if ( vsx_const -> all_bytes_same ) return <NUM_LIT> ; if ( vsx_const -> all_half_words_same ) { unsigned short h_word = vsx_const -> half_words [ <NUM_LIT> ] ; short sign_h_word = ( ( h_word & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( EASY_VECTOR_15 ( sign_h_word ) ) return <NUM_LIT> ; } unsigned int word = vsx_const -> words [ <NUM_LIT> ] ; int sign_word = ( ( word & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( EASY_VECTOR_15 ( sign_word ) ) return <NUM_LIT> ; return vsx_const -> words [ <NUM_LIT> ] ;


<s> return __builtin_mve_vcmpltq_sv8hi ( __a , __b ) ;


<s> bool shouldAvoidImmediateInstFormsForSize ( SDNode * N ) const { uint32_t UseCount = <NUM_LIT> ; if ( ! OptForSize ) return false ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; ( UI != UE ) && ( UseCount < <NUM_LIT> ) ; ++ UI ) { SDNode * User = * UI ; if ( User -> isMachineOpcode ( ) ) { UseCount ++ ; continue ; } if ( User -> getOpcode ( ) == <STR_LIT> && User -> getOperand ( <NUM_LIT> ) . getNode ( ) == N ) { UseCount ++ ;


<s> MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = FFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) && ! needsFP ( MF ) ) { return ; } unsigned MinGPR = <STR_LIT> ; unsigned MinG8R = <STR_LIT> ; unsigned MinFPR = <STR_LIT> ; unsigned MinVR = <STR_LIT> ; bool HasGPSaveArea = false ; bool HasG8SaveArea = false ; bool HasFPSaveArea = false ; bool HasCRSaveArea = false ; bool HasVRSAVESaveArea = false ; bool HasVRSaveArea = false ; SmallVector < CalleeSavedInfo , <NUM_LIT> > GPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > G8Regs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > FPRegs ; SmallVector < CalleeSavedInfo , <NUM_LIT> > VRegs ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> -> contains ( Reg ) ) { HasGPSaveArea = true ; GPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinGPR ) { MinGPR = Reg ; } } else if ( <STR_LIT> -> contains ( Reg ) ) { HasG8SaveArea = true ; G8Regs . push_back ( CSI [ i ] ) ; if ( Reg < MinG8R ) { MinG8R = Reg ; } } else if ( <STR_LIT> -> contains ( Reg ) ) { HasFPSaveArea = true ; FPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( <STR_LIT> -> contains ( Reg ) || <STR_LIT> -> contains ( Reg ) ) { } else if ( <STR_LIT> -> contains ( Reg ) ) { HasVRSAVESaveArea = true ; } else if ( <STR_LIT> -> contains ( Reg ) ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) {

int FI = FPRegs [ i ] . getFrameIdx ( ) ;


<s> return new R600ClauseMergePass ( TM ) ;


<s> if ( Src . isReg ( ) && Src . getReg ( ) == <STR_LIT> ) return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> bool <ISA_LIT>DAGToDAGISel :: canUseBlockOperation ( StoreSDNode * Store , LoadSDNode * Load ) const { if ( Load -> getMemoryVT ( ) != Store -> getMemoryVT ( ) ) return false ; if ( Load -> isVolatile ( ) || Store -> isVolatile ( ) ) return false ; if ( Load -> isInvariant ( ) && Load -> isDereferenceable ( ) ) return true ; const Value * V1 = Load -> getMemOperand ( ) -> getValue ( ) ; const Value * V2 = Store -> getMemOperand ( ) -> getValue ( ) ; if ( ! V1 || ! V2 ) return false ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ;

int64_t End1 = Load -> getSrcValueOffset ( ) + Size ;


<s> TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; unsigned LiveMaskReg = <NUM_LIT> ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( <STR_LIT> ) ; if ( ! ( GlobalFlags & StateWWM ) ) return ! LiveMaskQueries . empty ( ) ; } else { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ;

if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) {


<s> MF = ML . getHeader ( ) -> getParent ( ) ;


<s> O << markup ( <STR_LIT> ) << <STR_LIT> ; printRegName ( O , MO1 . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ;

O << <STR_LIT> << markup ( <STR_LIT> ) ;


<s> void VLIWResourceModel :: savePacket ( ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerImplicitParameter ( SelectionDAG & DAG , EVT VT , const SDLoc & DL , unsigned DwordOffset ) const { unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ;

assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ;


<s> if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( Op0 . getValueType ( ) == <STR_LIT> && ( ( isa < ConstantSDNode > ( Op0 ) && ! cast < ConstantSDNode > ( Op0 ) -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) || ( isa < ConstantSDNode > ( Op1 ) && ! cast < ConstantSDNode > ( Op1 ) -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) ) && ! DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) && ! Subtarget . isAtom ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , <STR_LIT> , Op1 ) ; }

SDVTList VTs = DAG . getVTList ( Op0 . getValueType ( ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: matchLoadInAddress ( LoadSDNode * N , <ISA_LIT>ISelAddressMode & AM ) {


<s> CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: Static ) return Result ;

SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ;


<s> Br . MaxDisp = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; } BBInfo [ MBB -> getNumber ( ) ] . Size += <NUM_LIT> ; adjustBBOffsetsAfter ( MBB ) ; HasFarJump = true ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getGatherNode ( Opc , Op , DAG , Base , Index , Scale , Chain , Subtarget ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Mask = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Scale = Op . getOperand ( <NUM_LIT> ) ; return getMGatherNode ( Opc , Op , DAG , Src , Mask , Base , Index , Scale , Chain , Subtarget ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Opc ; switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Base = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ;


<s> DAG . computeKnownBits ( Op , KnownZero , KnownOne ) ; return ( VT . getSizeInBits ( ) - KnownZero . countLeadingOnes ( ) ) <= <NUM_LIT> ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = FuncInfo . EHRegNodeFrameIndex ; int EHRegSize = MFI -> getObjectSize ( FI ) ; if ( RestoreSP ) { addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) , <STR_LIT> , true , - EHRegSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } unsigned UsedReg ; int EHRegOffset = getFrameIndexReference ( MF , FI , UsedReg ) ; int EndOffset = - EHRegOffset - EHRegSize ; FuncInfo . EHRegNodeEndOffset = EndOffset ; if ( UsedReg == FramePtr ) { unsigned ADDri = getADDriOpcode ( false , EndOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( ADDri ) , FramePtr ) . addReg ( FramePtr ) . addImm ( EndOffset ) . setMIFlag ( MachineInstr :: FrameSetup ) -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; assert ( EndOffset >= <NUM_LIT> && <STR_LIT> ) ;


<s> <ISA_LIT>ISelAddressMode ( ) : BaseType ( RegBase ) , Disp ( <NUM_LIT> ) , GV ( <NUM_LIT> ) , CP ( <NUM_LIT> ) , BlockAddr ( <NUM_LIT> ) , ES ( <NUM_LIT> ) , JT ( - <NUM_LIT> ) , Align ( <NUM_LIT> ) {


<s> const MCOperand & MO1 = MI -> getOperand ( Op ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op , O ) ; return ; } const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; unsigned IdxMode = <STR_LIT> ( MO3 . getImm ( ) ) ;

assert ( IdxMode != <STR_LIT> && <STR_LIT> ) ;


<s> void <ISA_LIT>Subtarget :: resetSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) { if ( isTargetIOS ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( TargetABI == <ISA_LIT>_ABI_UNKNOWN ) { switch ( TargetTriple . getEnvironment ( ) ) { case Triple :: Android : case Triple :: EABI : case Triple :: EABIHF : case Triple :: GNUEABI : case Triple :: GNUEABIHF : TargetABI = <ISA_LIT>_ABI_AAPCS ; break ; default : if ( ( isTargetIOS ( ) && isMClass ( ) ) || ( TargetTriple . isOSBinFormatMachO ( ) && TargetTriple . getOS ( ) == Triple :: UnknownOS ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; else TargetABI = <ISA_LIT>_ABI_APCS ; break ; } } if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 | ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; break ; case StrictAlign : AllowsUnalignedMem = false ; break ; case NoStrictAlign : AllowsUnalignedMem = true ; break ; } switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ? true : false ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; }


<s> const DataLayout & DL = DAG . getDataLayout ( ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ;

MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ;


<s> if ( ! MO . isReg ( ) ) return false ; Register Reg = MO . getReg ( ) ; if ( ! TRI -> isVGPR ( * MRI , Reg ) ) return false ;

if ( Register :: isPhysicalRegister ( Reg ) ) return false ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineFunction :: iterator I = Func . begin ( ) , E = Func . end ( ) ; I != E ; ++ I ) processBasicBlock ( Func , I ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; return true ;


<s> if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ;

RegMap [ Stack [ -- StackTop ] ] = ~ <NUM_LIT> ;


<s> vmvnq_s32 ( int32x4_t a ) { int32x4_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> static bool CC_<ISA_LIT>32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { static const unsigned RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ;


return ( float32x4_t ) __builtin_neon_vreinterpretv4sfv8hi ( __a ) ;


<s> <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFFrame . getCalleeSavedInfo ( ) ; bool HasFP = hasFP ( MF ) ; DebugLoc DL ; int64_t SPOffsetFromCFA = - <STR_LIT> ; if ( ZFI -> getLowSavedGPR ( ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int64_t Offset = SPOffsetFromCFA + RegSpillOffsets [ Reg ] ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> Ox ++ ; } MB . addReg ( DefOp . getReg ( ) , getRegState ( DefOp ) , DefOp . getSubReg ( ) ) ; MB . addReg ( PredOp . getReg ( ) , PredOp . isUndef ( ) ? RegState :: Undef : <NUM_LIT> , PredOp . getSubReg ( ) ) ; while ( Ox < NP ) { MachineOperand & MO = MI . getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) MB . add ( MO ) ; Ox ++ ; } MachineFunction & MF = * B . getParent ( ) ; MachineInstr :: mmo_iterator I = MI . memoperands_begin ( ) ; unsigned NR = std :: distance ( I , MI . memoperands_end ( ) ) ; MachineInstr :: mmo_iterator MemRefs = MF . allocateMemRefsArray ( NR ) ;

for ( unsigned i = <NUM_LIT> ; i < NR ; ++ i ) MemRefs [ i ] = * I ++ ;


<s> return '@' + utostr ( TargetRegisterInfo :: virtReg2Index ( RegNo ) + NumArgs ) ;


<s> void <ISA_LIT>InstructionSelector :: renderNegateImm ( MachineInstrBuilder & MIB , const MachineInstr & MI , int OpIdx ) const {

assert ( MI . getOpcode ( ) == TargetOpcode :: G_CONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ;


<s> if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; assert ( ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == <NUM_LIT> ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned RA = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; MFI . setReturnAddressIsTaken ( true ) ; unsigned Reg = MF . addLiveIn ( RA , getRegClassFor ( VT ) ) ; return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , SDLoc ( Op ) , Reg , VT ) ;


<s> AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> param_iterator local_end ( ) const { return LocalParams . end ( ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ;


<s> Field H = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; Field G = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; auto DecodeRegisterOrImm = [ & Inst , Address , Decoder ] ( Field RegNum , Field Value ) { if ( <NUM_LIT> == RegNum ) {

Inst . addOperand ( MCOperand :: createImm ( Value ) ) ;


<s> HasVFPv4 = false ; HasV8FP = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; IsMClass = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumRegs = MI . getNumOperands ( ) - Desc . getNumOperands ( ) ; return ( NumRegs / <NUM_LIT> ) + ( NumRegs % <NUM_LIT> ) + <NUM_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : {

unsigned NumRegs = MI . getNumOperands ( ) - Desc . getNumOperands ( ) + <NUM_LIT> ;


<s> unsigned Depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; MakeLibCallOptions CallOptions ; return makeLibCall ( DAG , RTLIB :: RETURN_ADDRESS , Op . getValueType ( ) , { DAG . getConstant ( Depth , DL , <STR_LIT> ) } , CallOptions , DL ) . first ;


<s> case <STR_LIT> : return instCombineSVECmpNE ( IC , II ) ; case <STR_LIT> : return instCombineRDFFR ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVELast ( IC , II ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : return instCombineSVECntElts ( IC , II , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEPTest ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVEVectorMul ( IC , II ) ; case <STR_LIT> : return instCombineSVEVectorFAdd ( IC , II ) ; case <STR_LIT> : return instCombineSVEVectorBinOp ( IC , II ) ; case <STR_LIT> : return instCombineSVETBL ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return instCombineSVEUnpack ( IC , II ) ; case <STR_LIT> : return instCombineSVETupleGet ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVEZip ( IC , II ) ; case <STR_LIT> : return instCombineLD1GatherIndex ( IC , II ) ; case <STR_LIT> : return instCombineST1ScatterIndex ( IC , II ) ; case <STR_LIT> : return instCombineSVELD1 ( IC , II , DL ) ; case <STR_LIT> : return instCombineSVEST1 ( IC , II , DL ) ; case <STR_LIT> : return instCombineSVESDIV ( IC , II ) ;


<s> if ( s390_preserve_fpr_arg_p ( regnum ) && ! cfun_fpr_save_p ( regnum ) ) { rtx reg = gen_rtx_REG ( DFmode , regnum ) ; add_reg_note ( insn , REG_CFA_NO_RESTORE , reg ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( addr , reg ) ) ;


<s> void LinearizedRegion :: initLiveOut ( RegionMRT * Region , const MachineRegisterInfo * MRI , const TargetRegisterInfo * TRI , PHILinearize & PHIInfo ) {

storeLiveOuts ( Region , MRI , TRI , PHIInfo ) ;


<s> FunctionPass * llvm :: createNEONPreAllocPass ( ) { return new NEONPreAllocPass ( ) ;


<s> <ISA_LIT>IndirectThunks ( ) : MachineFunctionPass ( ID ) {


<s> bool <ISA_LIT>FixSGPRCopies :: isVGPRToSGPRCopy ( const TargetRegisterClass * SrcRC , const TargetRegisterClass * DstRC , const <ISA_LIT>RegisterInfo & TRI ) const { return TRI . isSGPRClass ( DstRC ) && TRI . hasVGPRs ( SrcRC ) ;


<s> bool useCheriExactEquals ( ) const { return UseCheriExactEquals ;


<s> case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ;

case <STR_LIT> : return LowerMUL ( Op , DAG ) ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ;


<s> unsigned DDomain = DefMI . getDesc ( ) . TSFlags & <STR_LIT> ; if ( DDomain == <STR_LIT> ) { unsigned DefClass = DefMI . getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - <NUM_LIT> && DefCycle <= <NUM_LIT> ) ;


<s> case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = get<ISA_LIT>ConditionCode ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; unsigned Opc = <STR_LIT> ( CC ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ;


<s> SDValue B = DAG -> getNode ( <STR_LIT> , dl , <STR_LIT> , DAG -> getConstant ( <STR_LIT> , <STR_LIT> ) , A , Constant ( immInByte * <NUM_LIT> , <STR_LIT> ) ) ; return B ;


<s> SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; }


<s> int64_t CarryInVal = MI . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> ; bool Success ; MachineInstr * Load ; Register LHS ; MachineOperand Addr = MachineOperand :: CreateReg ( <NUM_LIT> , false ) ; unsigned Opcode ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Success = mi_match ( Dst , MRI , m_GAdd ( m_Reg ( LHS ) , m_all_of ( m_MInstr ( Load ) , m_FoldedLdAbs ( MI , Addr , AA ) ) ) ) ; Opcode = <STR_LIT> ; } else { Success = mi_match ( Dst , MRI , m_GSub ( m_Reg ( LHS ) , m_all_of ( m_MInstr ( Load ) , m_FoldedLdAbs ( MI , Addr , AA ) ) ) ) ; Opcode = <STR_LIT> ; } if ( Success ) { Register CIn = Builder . buildInstr ( <STR_LIT> , { S1 } , { CarryInVal } ) . getReg ( <NUM_LIT> ) ; auto Instr = Builder . buildInstr ( Opcode ) . addDef ( Dst ) . addDef ( MRI . createGenericVirtualRegister ( S1 ) ) . addDef ( MRI . createGenericVirtualRegister ( S1 ) ) . addUse ( LHS ) . add ( Addr ) . addUse ( CIn ) . cloneMemRefs ( * Load ) ; if ( ! constrainSelectedInstRegOperands ( * Instr , TII , TRI , RBI ) ) llvm_unreachable ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } Register Idx ; if ( MI . getOpcode ( ) == <STR_LIT> ) { Success = mi_match ( Dst , MRI , m_GAdd ( m_Reg ( LHS ) , m_all_of ( m_MInstr ( Load ) , m_FoldedLdIdx ( MI , Addr , Idx , AA ) ) ) ) ; Opcode = <STR_LIT> ; } else { Success = mi_match ( Dst , MRI , m_GSub ( m_Reg ( LHS ) , m_all_of ( m_MInstr ( Load ) , m_FoldedLdIdx ( MI , Addr , Idx , AA ) ) ) ) ; Opcode = <STR_LIT> ; } if ( Success ) { Register CIn = Builder . buildInstr ( <STR_LIT> , { S1 } , { CarryInVal } ) . getReg ( <NUM_LIT> ) ; auto Instr = Builder . buildInstr ( Opcode ) . addDef ( Dst ) . addDef ( MRI . createGenericVirtualRegister ( S1 ) ) . addDef ( MRI . createGenericVirtualRegister ( S1 ) ) . addUse ( LHS ) . add ( Addr ) . addUse ( Idx ) . addUse ( CIn ) . cloneMemRefs ( * Load ) ; if ( ! constrainSelectedInstRegOperands ( * Instr , TII , TRI , RBI ) ) llvm_unreachable ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; }


<s> MachineInstr * Def = RDA -> getMIOperand ( LoLoop . Start , isDo ( LoLoop . Start ) ? <NUM_LIT> : <NUM_LIT> ) ; if ( ! Def ) {


<s> if ( CurrentState == FunctionStart ) {

auto & TOut = reinterpret_cast < <ISA_LIT>TargetStreamer & > ( * Out . getTargetStreamer ( ) ) ;


<s> EVT OffsVT = <STR_LIT> ; SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , OffsVT ) ; switch ( N . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_report_error ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_report_error ( <STR_LIT> <STR_LIT> ) ; case <STR_LIT> : if ( N . hasOneUse ( ) ) { SDValue Op0 = N . getOperand ( <NUM_LIT> ) ; switch ( Op0 . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Base = Op0 ; Index = Zero ; return true ; case <STR_LIT> : { GlobalAddressSDNode * GSDN = cast < GlobalAddressSDNode > ( Op0 ) ; GlobalValue * GV = GSDN -> getGlobal ( ) ; if ( GV -> getAlignment ( ) == <NUM_LIT> ) { Base = Op0 ; Index = Zero ; return true ;


<s> Op = AND ; break ; case <STR_LIT> : Op = XOR ; break ; case <STR_LIT> : Op = ADD ; break ; } Val = getAtomicLoadArithTargetConstant ( CurDAG , dl , Op , NVT , Val ) ; bool isUnOp = ! Val . getNode ( ) ; bool isCN = Val . getNode ( ) && ( Val . getOpcode ( ) == <STR_LIT> ) ; unsigned Opc = <NUM_LIT> ; switch ( NVT . SimpleTy ) { default : return nullptr ; case <STR_LIT> : if ( isCN ) Opc = AtomicOpcTbl [ Op ] [ ConstantI8 ] ; else Opc = AtomicOpcTbl [ Op ] [ I8 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI16 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI16 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I16 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI32 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI32 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I32 ] ; break ; case <STR_LIT> : Opc = AtomicOpcTbl [ Op ] [ I64 ] ; if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI64 ] ;

else if ( i64immSExt32 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ ConstantI64 ] ;


<s> CONSTEXPR svtbl2_impl ( ) : quiet < multi_vector_function > ( <NUM_LIT> ) {


<s> BlockPredication ( Function & Func ) : F ( & Func ) {


<s> assert ( ( Modifier == nullptr || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { printRegName ( O , MO . getReg ( ) ) ; return ; } if ( MO . isImm ( ) ) {


<s> if ( GSD -> getAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS ) return <ISA_LIT>TargetLowering :: LowerGlobalAddress ( MFI , Op , DAG ) ; SDLoc DL ( GSD ) ; const GlobalValue * GV = GSD -> getGlobal ( ) ; EVT PtrVT = Op . getValueType ( ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , GSD -> getOffset ( ) + <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , GA ) ;


<s> Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_SGPR_32 ( unsigned Val ) const {

return createSRegOperand ( <STR_LIT> , Val ) ;


<s> ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( Start , Next ) ; if ( Mnemonic == <STR_LIT> ) Mnemonic = <STR_LIT> ; Operands . push_back ( <STR_LIT> ( Mnemonic , NameLoc ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ;


<s> if ( ! Memory . OffsetImm ) return true ; int64_t Val = Memory . OffsetImm -> getValue ( ) ;

return Val >= <NUM_LIT> && Val <= <NUM_LIT> && ( Val % <NUM_LIT> ) == <NUM_LIT> ;


<s> AHi = DAG . getVectorShuffle ( VT , dl , A , A , ShufMask ) ; BHi = DAG . getVectorShuffle ( VT , dl , B , B , ShufMask ) ; AHi = DAG . getBitcast ( ExVT , AHi ) ; BHi = DAG . getBitcast ( ExVT , BHi ) ; AHi = DAG . getNode ( <STR_LIT> , dl , ExVT , AHi , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; BHi = DAG . getNode ( <STR_LIT> , dl , ExVT , BHi , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; } SDValue RLo = DAG . getNode ( <STR_LIT> , dl , ExVT , ALo , BLo ) ; SDValue RHi = DAG . getNode ( <STR_LIT> , dl , ExVT , AHi , BHi ) ; RLo = DAG . getNode ( <STR_LIT> , dl , ExVT , RLo , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; RHi = DAG . getNode ( <STR_LIT> , dl , ExVT , RHi , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RLo , RHi ) ; } if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && ! Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; static const int UnpackMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Aodds = DAG . getVectorShuffle ( VT , dl , A , A , UnpackMask ) ; SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A , B ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Aodds , Bodds ) ; Evens = DAG . getBitcast ( VT , Evens ) ; Odds = DAG . getBitcast ( VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Ahi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , A , <NUM_LIT> , DAG ) ; SDValue Bhi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , B , <NUM_LIT> , DAG ) ;


<s> return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; default : return true ;


<s> case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; case ( <STR_LIT> ) : return <STR_LIT> ; default : return nullptr ;


<s> <STR_LIT> :: src0 , <STR_LIT> :: src1 , <STR_LIT> :: src2 } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { int OperandIdx = TII -> getOperandIdx ( MI -> getOpcode ( ) , Ops [ i ] ) ; if ( OperandIdx < <NUM_LIT> ) continue ;

unsigned Src = MI -> getOperand ( OperandIdx ) . getReg ( ) ;


<s> if ( Op != TargetOpcode :: COPY && ! MI . isPHI ( ) ) return false ;

return getRegBank ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) == & <STR_LIT> ;


return ( __m256d ) __builtin_ia32_cvtdq2pd256 ( ( __v4si ) __A ) ;


<s> unsigned OldDefReg = DefOp . getReg ( ) ; auto * DefRC = MRI -> getRegClass ( OldDefReg ) ; unsigned UnhardenedReg = MRI -> createVirtualRegister ( DefRC ) ; DefOp . setReg ( UnhardenedReg ) ; unsigned HardenedReg = hardenValueInRegister ( UnhardenedReg , MBB , std :: next ( MI . getIterator ( ) ) , Loc ) ; MRI -> replaceRegWith ( OldDefReg , HardenedReg ) ; ++ NumPostLoadRegsHardened ; return HardenedReg ;


<s> for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) processBasicBlock ( * I ) ; if ( FnHasLiveInYmm ) addDirtySuccessor ( MF . front ( ) ) ; while ( ! DirtySuccessors . empty ( ) ) { MachineBasicBlock & MBB = * DirtySuccessors . back ( ) ; DirtySuccessors . pop_back ( ) ; BlockState & BBState = BlockStates [ MBB . getNumber ( ) ] ; if ( BBState . FirstUnguardedCall != MBB . end ( ) ) insertVZeroUpper ( BBState . FirstUnguardedCall , MBB ) ; if ( BBState . ExitState == PASS_THROUGH ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) addDirtySuccessor ( * * SI ) ; }


<s> bool isPseudoJumpSymbol ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ;

return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ;


<s> return ( int32x4_t ) __builtin_neon_vrshlsv4si ( __a , __b ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorLoadToRVV ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; auto * Load = cast < LoadSDNode > ( Op ) ; assert ( allowsMemoryAccessForAlignment ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , Load -> getMemoryVT ( ) , * Load -> getMemOperand ( ) ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue NewLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , { Load -> getChain ( ) , Load -> getBasePtr ( ) , VL } , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Result = convertFromScalableVector ( VT , NewLoad , DAG , Subtarget ) ;

return DAG . getMergeValues ( { Result , Load -> getChain ( ) } , DL ) ;


<s> } const MCSymbolRefExpr * SR = cast < MCSymbolRefExpr > ( Imm . Val ) ; Inst . addOperand ( MCOperand :: createExpr ( SR ) ) ;


<s> ByValArgInfo ( ) : FirstIdx ( <NUM_LIT> ) , NumRegs ( <NUM_LIT> ) , Address ( <NUM_LIT> ) {


<s> std :: vector < PhiInfo > Phis ; for ( auto & I : * C . LB ) { if ( ! I . isPHI ( ) ) break ; unsigned PR = getDefReg ( & I ) ; if ( isConst ( PR ) ) continue ; bool BadUse = false , GoodUse = false ; for ( const MachineOperand & MO : MRI -> use_operands ( PR ) ) { const MachineInstr * UseI = MO . getParent ( ) ; if ( UseI -> getParent ( ) != C . LB ) {


<s> SDValue DestBB = Op . getOperand ( <NUM_LIT> ) ; TheBit = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TheBit , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue A64CMP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TheBit , DAG . getConstant ( <NUM_LIT> , TheBit . getValueType ( ) ) , DAG . getCondCode ( <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , A64CMP , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , DestBB ) ;


return isCortexA53 ( ) || isCortexA57 ( ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL , bool UseScalable ) const { unsigned VecSize = UseScalable ? Subtarget -> getMinSVEVectorSizeInBits ( ) : <NUM_LIT> ; return std :: max < unsigned > ( <NUM_LIT> , ( DL . getTypeSizeInBits ( VecTy ) + <NUM_LIT> ) / VecSize ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , STI ( STI ) {


<s> rtx mask = gen_reg_rtx ( TImode ) ; rtx offset ; if ( GET_CODE ( ops [ <NUM_LIT> ] ) == CONST_INT ) offset = GEN_INT ( INTVAL ( ops [ <NUM_LIT> ] ) * GET_MODE_SIZE ( imode ) ) ; else { offset = gen_reg_rtx ( SImode ) ; emit_insn ( gen_mulsi3 ( offset , ops [ <NUM_LIT> ] , GEN_INT ( GET_MODE_SIZE ( imode ) ) ) ) ; } emit_insn ( gen_cpat ( mask , stack_pointer_rtx , offset , GEN_INT ( GET_MODE_SIZE ( imode ) ) ) ) ;

emit_insn ( gen_shufb ( ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] , mask ) ) ;


<s> if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( ContainerVT ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue NeutralElem = DAG . getNeutralElement ( BaseOpc , DL , VecEltVT , SDNodeFlags ( ) ) ;

SDValue IdentitySplat = lowerScalarSplat ( NeutralElem , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ;


<s> unsigned <ISA_LIT>AsmParser :: getConstantBusLimit ( unsigned Opcode ) const { if ( ! isGFX10Plus ( ) ) return <NUM_LIT> ; switch ( Opcode ) { case <STR_LIT> :


<s> printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , getRegisterName ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


return __builtin_arm_tmovmskb ( ( __v8qi ) __A ) ;


<s> return bitc :: RMW_NAND ; case AtomicRMWInst :: Or : return bitc :: RMW_OR ; case AtomicRMWInst :: Xor : return bitc :: RMW_XOR ; case AtomicRMWInst :: Max : return bitc :: RMW_MAX ; case AtomicRMWInst :: Min : return bitc :: RMW_MIN ; case AtomicRMWInst :: UMax : return bitc :: RMW_UMAX ; case AtomicRMWInst :: UMin :


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( RM == Reloc :: Default ) { RM = Reloc :: Static ; } if ( CM == CodeModel :: Default ) { CM = CodeModel :: Small ; } if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) report_fatal_error ( <STR_LIT> ) ;

X -> initMCCodeGenInfo ( RM , CM , OL ) ;


<s> if ( GET_CODE ( pat ) == USE || GET_CODE ( pat ) == CLOBBER ) continue ; if ( ( GET_CODE ( pat ) == UNSPEC && XINT ( pat , <NUM_LIT> ) == <NUM_LIT> ) || GET_CODE ( insn ) == CODE_LABEL ) { if ( b ) while ( bundle_pos < <NUM_LIT> ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } if ( GET_CODE ( insn ) != CODE_LABEL ) b = bundle + INTVAL ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; else b = <NUM_LIT> ; bundle_pos = <NUM_LIT> ; continue ; } else if ( GET_CODE ( pat ) == UNSPEC_VOLATILE && XINT ( pat , <NUM_LIT> ) == <NUM_LIT> ) { int t = INTVAL ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; if ( b ) while ( bundle_pos < t ) { emit_insn_before ( gen_nop_type ( b -> t [ bundle_pos ] ) , insn ) ; bundle_pos ++ ; } continue ; } if ( bundle_pos == <NUM_LIT> ) b = <NUM_LIT> ; if ( b && INSN_P ( insn ) ) { t = ia64_safe_type ( insn ) ; if ( asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) { while ( bundle_pos < <NUM_LIT> ) {


emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_SIGN_EXTEND ( extend_mode , sign_reg ) ) ) ;


<s> RegisterAsmInfo < <ISA_LIT>LinuxTargetAsmInfo > Y ( TheCell<ISA_LIT>Target ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( tm , * this ) , TM ( tm ) {


<s> virtual ~ <ISA_LIT>Disassembler ( ) {


<s> rtx base = NULL_RTX ; switch ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case LABEL_REF : case SYMBOL_REF : base = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case LABEL_REF : case SYMBOL_REF : base = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; default : gcc_unreachable ( ) ; } if ( round_constant ) offset = ( ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ) ; switch ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ) { case PLUS : if ( offset < <NUM_LIT> ) { offset = - offset ; sep = <STR_LIT> ; }


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ;

return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: parseComma ( ) {

if ( check ( getTok ( ) . isNot ( AsmToken :: Comma ) , getLoc ( ) , <STR_LIT> ) ) return true ;


<s> static int s390_non_addr_reg_read_p ( rtx reg , rtx_insn * insn ) { return reg_referenced_p ( reg , PATTERN ( insn ) ) && ! reg_used_in_mem_p ( REGNO ( reg ) , PATTERN ( insn ) ) ;


<s> SDLoc DL ( V ) ; SDValue Trunc [ <NUM_LIT> ] = { V . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , V . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , V . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , V . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) } ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) if ( Trunc [ I ] . getValueType ( ) == <STR_LIT> ) Trunc [ I ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trunc [ I ] ) ; SDValue Concat0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trunc [ <NUM_LIT> ] , Trunc [ <NUM_LIT> ] ) ; SDValue Concat1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trunc [ <NUM_LIT> ] , Trunc [ <NUM_LIT> ] ) ; SDValue Trunc0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Concat0 ) ; SDValue Trunc1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Concat1 ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Trunc0 , Trunc1 ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVASTART_SAVE_XMM_REGS ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> <ISA_LIT>Operand :: <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ;


<s> SmallVector < Type * , <NUM_LIT> > Types = { Ty , Op1 -> getType ( ) } ; SmallVector < Value * , <NUM_LIT> > Args { Op1 , Op2 } ;

Function * Intrinsic = <STR_LIT> ( F -> getParent ( ) , IntID , Types ) ;


<s> <ISA_LIT>MCAsmInfoELF :: ~ <ISA_LIT>MCAsmInfoELF ( ) {


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { MachineFunction * MF = BB -> getParent ( ) ; unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ;

return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ;


<s> assert ( Kind == Memory && <STR_LIT> ) ;


<s> const auto & MLI = getAnalysis < MachineLoopInfo > ( ) ;

const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ;


<s> case memory_order_acquire : return MemorySemantics :: Acquire ; case memory_order_release : return MemorySemantics :: Release ; case memory_order_acq_rel :

return MemorySemantics :: AcquireRelease ;


<s> return TTI :: TCC_Basic ; } if ( auto * VTy = dyn_cast < FixedVectorType > ( Src ) ) { unsigned NumElem = VTy -> getNumElements ( ) ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace , CostKind ) ; int SplitCost = getScalarizationOverhead ( VTy , DemandedElts , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; return NumElem * Cost + SplitCost ;


<s> return false ; } case DIV : { if ( ! TARGET_HAS_DIV ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( speed ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATE : { if ( ! speed ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case ZERO_EXTRACT : if ( TARGET_HAS_BMX ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } return false ; case SIGN_EXTEND : { if ( MEM_P ( XEXP ( x , <NUM_LIT> ) ) ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case MEM : { rtx addr = XEXP ( x , <NUM_LIT> ) ; * total = nios2_address_cost ( addr , mode , ADDR_SPACE_GENERIC , speed ) ; if ( outer_code == SET && opno == <NUM_LIT> ) ; else if ( outer_code == SET || outer_code == SIGN_EXTEND || outer_code == ZERO_EXTEND ) { if ( speed ) * total += COSTS_N_INSNS ( <NUM_LIT> ) ; } else * total += COSTS_N_INSNS ( speed ? <NUM_LIT> : <NUM_LIT> ) ; return true ; }


<s> if ( SrcVT . isVector ( ) ) { if ( SrcVT . getVectorElementType ( ) == <STR_LIT> ) { MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , IntegerVT , Op . getOperand ( <NUM_LIT> ) ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget -> is64Bit ( ) ) { return Op ;


<s> Register DestPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurrDestReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , DestPhiReg ) . addUse ( OpDestReg ) . addMBB ( TpEntry ) . addUse ( CurrDestReg ) . addMBB ( TpLoopBody ) ; Register LoopCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingLoopIterationsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , LoopCounterPhiReg ) . addUse ( TotalIterationsReg ) . addMBB ( TpEntry ) . addUse ( RemainingLoopIterationsReg ) . addMBB ( TpLoopBody ) ; Register PredCounterPhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register RemainingElementsReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , PredCounterPhiReg ) . addUse ( ElementCountReg ) . addMBB ( TpEntry ) . addUse ( RemainingElementsReg ) . addMBB ( TpLoopBody ) ; Register VccrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , VccrReg ) . addUse ( PredCounterPhiReg ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) , RemainingElementsReg ) . addUse ( PredCounterPhiReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) . addReg ( <NUM_LIT> ) ; Register SrcValueReg ; if ( IsMemcpy ) { SrcValueReg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( TpLoopBody , Dl , TII -> get ( <STR_LIT> ) ) . addDef ( CurrSrcReg ) . addDef ( SrcValueReg ) . addReg ( SrcPhiReg ) . addImm ( <NUM_LIT> ) . addImm ( <STR_LIT> ) . addUse ( VccrReg ) ;


<s> if ( AddrReg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( AddrReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ;

const IndirectBrInst * IB = cast < IndirectBrInst > ( I ) ;


<s> void <ISA_LIT>TypeRewriter :: visitCallInst ( CallInst & I ) { IRBuilder < > Builder ( & I ) ; SmallVector < Value * , <NUM_LIT> > Args ; SmallVector < Type * , <NUM_LIT> > Types ; bool NeedToReplace = false ; Function * F = I . getCalledFunction ( ) ; std :: string Name = F -> getName ( ) . str ( ) ; for ( unsigned i = <NUM_LIT> , e = I . getNumArgOperands ( ) ; i != e ; ++ i ) { Value * Arg = I . getArgOperand ( i ) ; if ( Arg -> getType ( ) == v16i8 ) { Args . push_back ( Builder . CreateBitCast ( Arg , i128 ) ) ; Types . push_back ( i128 ) ; NeedToReplace = true ; Name = Name + <STR_LIT> ; } else if ( Arg -> getType ( ) -> isVectorTy ( ) && Arg -> getType ( ) -> getVectorNumElements ( ) == <NUM_LIT> && Arg -> getType ( ) -> getVectorElementType ( ) == Type :: getInt32Ty ( I . getContext ( ) ) ) { Type * ElementTy = Arg -> getType ( ) -> getVectorElementType ( ) ; std :: string TypeName = <STR_LIT> ; InsertElementInst * Def = dyn_cast < InsertElementInst > ( Arg ) ; assert ( Def ) ; Args . push_back ( Def -> getOperand ( <NUM_LIT> ) ) ; Types . push_back ( ElementTy ) ; std :: string VecTypeName = <STR_LIT> + TypeName ;

Name = Name . replace ( Name . find ( VecTypeName ) , VecTypeName . length ( ) , TypeName ) ;


<s> static bool arm_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) ) && ( nelems >= <NUM_LIT> && nelems <= <NUM_LIT> ) ) return true ; return false ;


<s> int Imm = SignExtend32 < <NUM_LIT> > ( Insn ) ; Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ; return MCDisassembler :: Success ;


<s> unsigned getNumNamedVarArgParams ( ) const { return NumNamedVarArgParams ;


<s> bool <ISA_LIT>TargetLowering :: hasBitPreservingFPLogic ( EVT VT ) const { return ( VT == <STR_LIT> && Subtarget . hasStdExtZfh ( ) ) || ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) ) || ( VT == <STR_LIT> && Subtarget . hasStdExtD ( ) ) ;


<s> Operands . push_back ( <STR_LIT> ( Name , NameLoc ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( parseOperand ( Operands ) ) return true ; while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( parseOperand ( Operands ) ) return true ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: intRegClass ( unsigned Size ) const { return & <STR_LIT> ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; int D8SpillFI = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) if ( CSI [ i ] . getReg ( ) == <STR_LIT> ) { D8SpillFI = CSI [ i ] . getFrameIdx ( ) ; break ; } bool isThumb = AFI -> isThumbFunction ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opc ) , <STR_LIT> ) . addFrameIndex ( D8SpillFI ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NextReg = <STR_LIT> ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ;


<s> const char * output_move_strictqi ( rtx * operands ) { if ( operands [ <NUM_LIT> ] == const0_rtx && ( ( TARGET_68020 || TARGET_COLDFIRE ) || ! ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && MEM_VOLATILE_P ( operands [ <NUM_LIT> ] ) ) ) ) return <STR_LIT> ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsFlagSetting = false ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : switch ( MIOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ( MIOpc == <STR_LIT> || MIOpc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; MachineBasicBlock :: iterator I ( DefMI ) , E ( MI ) ; for ( I = std :: next ( I ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , TRI ) || I -> readsRegister ( <STR_LIT> , TRI ) ) return false ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( DefMI . print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI . print ( dbgs ( ) ) ) ; NewCmp = convertToFlagSetting ( DefMI , IsFlagSetting ) ; NewBr = convertToCondBr ( MI ) ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsFlagSetting = false ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : switch ( MIOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ( MIOpc == <STR_LIT> || MIOpc == <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; MachineBasicBlock :: iterator I ( DefMI ) , E ( MI ) ; for ( I = std :: next ( I ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , TRI ) || I -> readsRegister ( <STR_LIT> , TRI ) ) return false ; }


<s> bool restrictIT ( ) const { return RestrictIT ;


<s> if ( Reg == - <NUM_LIT> ) { Error ( BaseRegTok . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> return false ; } ; for ( GlobalVariable & GV : Mod -> globals ( ) ) { if ( GV . getAddressSpace ( ) != <ISA_LIT>AS :: LOCAL_ADDRESS ) continue ; if ( visitUsers ( & GV , & GV ) ) { UsedLDS . insert ( & GV ) ; Stack . clear ( ) ; continue ; } while ( ! Stack . empty ( ) ) { const Constant * C = Stack . pop_back_val ( ) ; if ( visitUsers ( & GV , C ) ) { UsedLDS . insert ( & GV ) ; Stack . clear ( ) ; break ; } } } const DataLayout & DL = Mod -> getDataLayout ( ) ; SmallVector < std :: pair < uint64_t , Align > , <NUM_LIT> > AllocatedSizes ; AllocatedSizes . reserve ( UsedLDS . size ( ) ) ; for ( const GlobalVariable * GV : UsedLDS ) { Align Alignment = DL . getValueOrABITypeAlignment ( GV -> getAlign ( ) , GV -> getValueType ( ) ) ; uint64_t AllocSize = DL . getTypeAllocSize ( GV -> getValueType ( ) ) ; if ( GV -> hasExternalLinkage ( ) && AllocSize == <NUM_LIT> ) { LocalMemLimit = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ) ; return false ; } AllocatedSizes . emplace_back ( AllocSize , Alignment ) ; } llvm :: sort ( AllocatedSizes , [ ] ( std :: pair < uint64_t , Align > LHS , std :: pair < uint64_t , Align > RHS ) { return LHS . second < RHS . second ; } ) ;


<s> TargetName = std :: string ( CPU . empty ( ) ? <STR_LIT> : CPU ) ; ParseSubtargetFeatures ( TargetName , FS ) ; if ( PTXVersion == <NUM_LIT> ) { PTXVersion = <NUM_LIT> ; }


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - <NUM_LIT> ) { Register Reg = MI . getOperand ( OpNo ) . getReg ( ) ; if ( Reg . isVirtual ( ) ) return MRI . getRegClass ( Reg ) ;


<s> pass_handle_trap_shadows ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_handle_trap_shadows , ctxt ) {


<s> DenseMap < const Function * , bool > seenMap ; for ( Module :: const_iterator FI = M . begin ( ) , FE = M . end ( ) ; FI != FE ; ++ FI ) { const Function * F = & * FI ; if ( F -> getAttributes ( ) . hasFnAttribute ( <STR_LIT> ) ) { emitDeclaration ( F , O ) ; continue ; } if ( F -> isDeclaration ( ) ) { if ( F -> use_empty ( ) ) continue ; if ( F -> getIntrinsicID ( ) ) continue ; emitDeclaration ( F , O ) ; continue ; }

for ( const User * U : F -> users ( ) ) {


loongarch_cpu_cache [ CPU_NATIVE ] . l1d_size = ( <NUM_LIT> << ( ( l1_szword & <NUM_LIT> ) >> <NUM_LIT> ) ) * ( ( l1_szword & <NUM_LIT> ) + <NUM_LIT> ) * ( <NUM_LIT> << ( ( l1_szword & <NUM_LIT> ) >> <NUM_LIT> ) ) >> <NUM_LIT> ;


<s> static bool addToListsIfDependent ( MachineInstr & MI , DenseSet < unsigned > & RegDefs , DenseSet < unsigned > & PhysRegUses , SmallVectorImpl < MachineInstr * > & Insts ) { for ( MachineOperand & Use : MI . operands ( ) ) { if ( Use . isReg ( ) && ( ( Use . readsReg ( ) && RegDefs . count ( Use . getReg ( ) ) ) || ( Use . isDef ( ) && RegDefs . count ( Use . getReg ( ) ) ) || ( Use . isDef ( ) && TargetRegisterInfo :: isPhysicalRegister ( Use . getReg ( ) ) && PhysRegUses . count ( Use . getReg ( ) ) ) ) ) { Insts . push_back ( & MI ) ; addDefsUsesToList ( MI , RegDefs , PhysRegUses ) ;


<s> if ( ix86_find_max_used_stack_alignment ( stack_alignment , stack_realign ) ) { stack_realign = incoming_stack_boundary < stack_alignment ; if ( ! stack_realign ) { crtl -> max_used_stack_slot_alignment = incoming_stack_boundary ; crtl -> stack_alignment_needed = incoming_stack_boundary ; crtl -> preferred_stack_boundary = incoming_stack_boundary ; } } else { if ( crtl -> drap_reg ) { basic_block bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; if ( ! REGNO_REG_SET_P ( DF_LR_IN ( bb ) , REGNO ( crtl -> drap_reg ) ) ) { crtl -> drap_reg = NULL_RTX ; crtl -> need_drap = false ; } } else cfun -> machine -> no_drap_save_restore = true ; frame_pointer_needed = false ; stack_realign = false ; crtl -> max_used_stack_slot_alignment = incoming_stack_boundary ; crtl -> stack_alignment_needed = incoming_stack_boundary ; crtl -> stack_alignment_estimated = incoming_stack_boundary ; if ( crtl -> preferred_stack_boundary > incoming_stack_boundary ) crtl -> preferred_stack_boundary = incoming_stack_boundary ; df_finish_pass ( true ) ; df_scan_alloc ( NULL ) ; df_scan_blocks ( ) ; df_compute_regs_ever_live ( true ) ; df_analyze ( ) ; if ( flag_var_tracking ) { df_ref ref , next ; for ( ref = DF_REG_USE_CHAIN ( HARD_FRAME_POINTER_REGNUM ) ;


<s> void create_regs_rtx ( ) { ix_reg = gen_rtx ( REG , HImode , HARD_X_REGNUM ) ; iy_reg = gen_rtx ( REG , HImode , HARD_Y_REGNUM ) ; d_reg = gen_rtx ( REG , HImode , HARD_D_REGNUM ) ; da_reg = gen_rtx ( REG , QImode , HARD_A_REGNUM ) ;

m68hc11_soft_tmp_reg = gen_rtx ( REG , HImode , SOFT_TMP_REGNUM ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_SINT ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> ) return Op ; return DAG . getLoad ( Op . getValueType ( ) , Op . getDebugLoc ( ) , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> } ; if ( ! Op . hasOneUse ( ) ) return <NUM_LIT> ; if ( isSupportedExtend ( Op ) ) return <NUM_LIT> ; unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) if ( ConstantSDNode * ShiftCst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { uint64_t Shift = ShiftCst -> getZExtValue ( ) ; if ( isSupportedExtend ( Op . getOperand ( <NUM_LIT> ) ) ) return ( Shift <= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; if ( ( VT == <STR_LIT> && Shift <= <NUM_LIT> ) || ( VT == <STR_LIT> && Shift <= <NUM_LIT> ) ) return <NUM_LIT> ; }


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> bool <ISA_LIT>InstrInfo :: mayBeCurLoad ( const MachineInstr * MI ) const { auto & HST = MI -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const uint64_t F = MI -> getDesc ( ) . TSFlags ;


<s> static bool isSHUFPMask ( const SmallVectorImpl < int > & Mask , EVT VT ) { int NumElems = VT . getVectorNumElements ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ;


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) {

Subtarget = & funcInfo . MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> dfa_state_size = state_size ( ) ; temp_dfa_state = xmalloc ( dfa_state_size ) ; prev_cycle_state = xmalloc ( dfa_state_size ) ; }

dfa_pre_cycle_insn = make_insn_raw ( gen_pre_cycle ( ) ) ;


<s> initialize<ISA_LIT>CopyElisionPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> gcc_assert ( XINT ( unspec , <NUM_LIT> ) == UNSPEC_MOV_PCREL_STEP3 ) ; opnds [ <NUM_LIT> ] = got_rtx ; if ( XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) == text_label_rtx ) opnds [ <NUM_LIT> ] = XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ; else { gcc_assert ( XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) == text_label_rtx ) ; opnds [ <NUM_LIT> ] = XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ; } opnds [ <NUM_LIT> ] = XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ;

if ( GET_CODE ( opnds [ <NUM_LIT> ] ) != SYMBOL_REF ) return ;


<s> return getFeatureBits ( ) [ <STR_LIT> ] ;


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , STI ) ; if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>AppleInstPrinter ( MAI , MII , MRI , STI ) ; return nullptr ;


<s> const uint8_t * Beads = <STR_LIT> ( MI -> getOpcode ( ) ) ; assert ( * Beads ) ; const uint8_t EncEAk [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; for ( const uint8_t Pat : EncEAk ) {


<s> } unsigned ABIAlignment = getTargetData ( ) -> getABITypeAlignment ( ST -> getMemoryVT ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( ST -> getAlignment ( ) >= ABIAlignment ) { return SDValue ( ) ; } SDValue Chain = ST -> getChain ( ) ; SDValue BasePtr = ST -> getBasePtr ( ) ; SDValue Value = ST -> getValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( ST -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = Value ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue StoreLow = DAG . getTruncStore ( Chain , dl , Low , BasePtr , ST -> getPointerInfo ( ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue StoreHigh = DAG . getTruncStore ( Chain , dl , High , HighAddr , ST -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreLow , StoreHigh ) ; } Type * IntPtrTy = getTargetData ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = BasePtr ; Args . push_back ( Entry ) ; Entry . Node = Value ; Args . push_back ( Entry ) ;

std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , true , DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , Args , DAG , dl ) ;


<s> static inline bool hasVLOp ( uint64_t TSFlags ) { return TSFlags & HasVLOpMask ;


<s> if ( MI -> isEHLabel ( ) || MI -> isCFIInstruction ( ) ) return true ; if ( MI -> isInlineAsm ( ) && ! ScheduleInlineAsm ) return true ; if ( isSchedBarrier ( MI ) ) return true ;

if ( HII -> isSolo ( MI ) ) return true ;


<s> return STI . isOSWindows ( ) && ! STI . isTargetWin64 ( ) ;


<s> case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : return F -> getAttributes ( ) . hasParamAttribute ( A -> getArgNo ( ) , Attribute :: InReg ) || F -> getAttributes ( ) . hasParamAttribute ( A -> getArgNo ( ) , Attribute :: ByVal ) ; default : return false ; }


<s> RHS_LO = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , HalfVT , RHS ) ; RHS_HI = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , HalfVT , RHS ) ; } LO = DAG . getNode ( Opc , dl , HalfVT , LHS_LO , RHS_LO ) ; HI = DAG . getNode ( Opc , dl , HalfVT , LHS_HI , RHS_HI ) ; Res = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , VT , DAG . getUNDEF ( VT ) , LO ) ; Res = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , VT , Res , HI ) ;


<s> int GCNHazardRecognizer :: checkDivFMasHazards ( MachineInstr * DivFMas ) { const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ;

const int DivFMasWaitStates = <NUM_LIT> ;


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( V ) ;


<s> const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) ) ; return ResultReg ;


<s> static bool isVLPreservingConfig ( const MachineInstr & MI ) { if ( MI . getOpcode ( ) != <STR_LIT> ) return false ;

assert ( <STR_LIT> == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ;

TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>leTarget ( ) , create<ISA_LIT>Disassembler ) ;


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override {


<s> void <ISA_LIT>InstPrinter :: printU8ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printUImmOperand < <NUM_LIT> > ( MI , OpNum , O ) ;


<s> CLI . setChain ( CurDAG -> getRoot ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * CurDAG -> getContext ( ) ) , CurDAG -> getExternalSymbol ( <STR_LIT> , TLI -> getPointerTy ( DL ) ) , std :: move ( Args ) ) ;

const TargetLowering & TLI = CurDAG -> getTargetLoweringInfo ( ) ;


<s> unsigned Opc = MI . getOpcode ( ) ; return ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ;


<s> else if ( ! strcmp ( argv [ i ] , <STR_LIT> ) ) { version ( argv [ <NUM_LIT> ] ) ; return <NUM_LIT> ; } else if ( ! strcmp ( argv [ i ] , <STR_LIT> ) ) debug = true ; else if ( argv [ i ] [ <NUM_LIT> ] == '-' ) { usage ( argv [ <NUM_LIT> ] ) ; return <NUM_LIT> ; } else { kernel_arg = i ; break ; } } if ( ! kernel_arg ) { usage ( argv [ <NUM_LIT> ] ) ; return <NUM_LIT> ; } int kernel_argc = argc - kernel_arg ; char * * kernel_argv = & argv [ kernel_arg ] ; init_device ( ) ; load_image ( kernel_argv [ <NUM_LIT> ] ) ; size_t args_size = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < kernel_argc ; i ++ ) args_size += strlen ( kernel_argv [ i ] ) + <NUM_LIT> ; struct kernargs * kernargs = device_malloc ( sizeof ( * kernargs ) , kernargs_region ) ; struct argdata { int64_t argv_data [ kernel_argc ] ; char strings [ args_size ] ; } * args = device_malloc ( sizeof ( struct argdata ) , kernargs_region ) ; size_t heap_size = <NUM_LIT> * <NUM_LIT> * <NUM_LIT> ; struct heap * heap = device_malloc ( heap_size , heap_region ) ; XHSA ( hsa_fns . hsa_memory_assign_agent_fn ( heap , device , HSA_ACCESS_PERMISSION_RW ) , <STR_LIT> ) ;


<s> ieee128_mangling_gcc_8_1 = true ; lang_hooks . set_decl_assembler_name ( decl ) ; old_name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; SET_DECL_ASSEMBLER_NAME ( decl , save_asm_name ) ; ieee128_mangling_gcc_8_1 = false ; if ( strcmp ( name , old_name ) != <NUM_LIT> ) { fprintf ( stream , <STR_LIT> , old_name ) ;

fprintf ( stream , <STR_LIT> , old_name , name ) ;


<s> case <STR_LIT> : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performADDCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ;


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2v2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregoiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregoiv2di ( __o , <NUM_LIT> ) ; return ret ;


<s> if ( CallConv == CallingConv :: <ISA_LIT>_BUILTIN ) { CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>_BUILTIN ) ; } else { analyzeReturnValues ( Ins , CCInfo , Subtarget . hasTinyEncoding ( ) ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ;

InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> uint64_t Hi = Bytes [ Offset ] ; uint64_t Lo = Bytes [ Offset + <NUM_LIT> ] ; uint64_t Word = ( Hi << <NUM_LIT> ) | Lo ; Buffer [ I ] = Word ; LLVM_DEBUG ( errs ( ) << format ( <STR_LIT> , ( unsigned ) Word , Buffer . size ( ) ) ) ;


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rdm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rdm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

} else if ( Inst . getOpcode ( ) == <STR_LIT> ) {


<s> errs ( ) << <STR_LIT> << CPI << <STR_LIT> << ( void * ) MCE . getCurrentPCValue ( ) << <STR_LIT> ; if ( const Function * F = dyn_cast < Function > ( C ) ) errs ( ) << F -> getName ( ) ; else errs ( ) << * C ; errs ( ) << '\n' ; } ) ; switch ( C -> getValueID ( ) ) { default : { llvm_unreachable ( <STR_LIT> ) ; break ; } case Value :: GlobalVariableVal : { emitGlobalAddress ( static_cast < const GlobalValue * > ( C ) , <STR_LIT> , isa < Function > ( C ) , false ) ; emitWordLE ( <NUM_LIT> ) ; break ; } case Value :: ConstantIntVal : { const ConstantInt * CI = static_cast < const ConstantInt * > ( C ) ; uint32_t Val = * ( uint32_t * ) CI -> getValue ( ) . getRawData ( ) ;


<s> if ( VT == <STR_LIT> && <ISA_LIT>SubTarget -> useCRBits ( ) ) { unsigned ImmReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CI -> isZero ( ) ? <STR_LIT> : <STR_LIT> ) , ImmReg ) ; return ImmReg ; } if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; if ( UseSExt && isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getSExtValue ( ) ) ; return ImmReg ; } else if ( ! UseSExt && isUInt < <NUM_LIT> > ( CI -> getZExtValue ( ) ) ) { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitExternalGlobal ( const GlobalVariable * GV ) { std :: string Name = getGlobalLinkName ( GV ) ; if ( TM . getRelocationModel ( ) != Reloc :: Static ) { if ( GV -> hasHiddenVisibility ( ) ) HiddenGVStubs . insert ( Name ) ; else GVStubs . insert ( Name ) ; printSuffixedName ( Name , <STR_LIT> ) ; return ; }


<s> case <STR_LIT> : return PerformLOADCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : return PerformZExtCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( Opc == <STR_LIT> || Opc == TargetOpcode :: COPY ) { assert ( DefI -> getOperand ( <NUM_LIT> ) . isDef ( ) && DefI -> getOperand ( <NUM_LIT> ) . isUse ( ) ) ; RegisterSubReg PR = DefI -> getOperand ( <NUM_LIT> ) ; G2P . insert ( std :: make_pair ( Reg , PR ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PrintRegister ( PR , * TRI ) << '\n' ) ; return PR ; } MachineBasicBlock & B = * DefI -> getParent ( ) ; DebugLoc DL = DefI -> getDebugLoc ( ) ; const TargetRegisterClass * PredRC = & <STR_LIT> ; Register NewPR = MRI -> createVirtualRegister ( PredRC ) ; if ( isConvertibleToPredForm ( DefI ) ) { MachineBasicBlock :: iterator DefIt = DefI ;

BuildMI ( B , std :: next ( DefIt ) , DL , TII -> get ( TargetOpcode :: COPY ) , NewPR ) . addReg ( Reg . R , <NUM_LIT> , Reg . S ) ;


<s> case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getZExtValue ( ) == <NUM_LIT> ) || ( C -> getZExtValue ( ) == <NUM_LIT> ) ) weight = CW_Constant ; } break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'N' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) weight = CW_Constant ; } break ; case 'G' : case 'C' : if ( dyn_cast < ConstantFP > ( CallOperandVal ) ) { weight = CW_Constant ; } break ; case 'e' :


<s> if ( Ops . size ( ) != <NUM_LIT> ) return NULL ; unsigned OpNum = Ops [ <NUM_LIT> ] ; bool isFloat = false ; MachineInstr * NewMI = NULL ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( OpNum == <NUM_LIT> ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } break ; case <STR_LIT> : isFloat = true ; case <STR_LIT> : if ( OpNum == <NUM_LIT> ) {

unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain ;


<s> default : dbgs ( ) << <STR_LIT> << reg << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> default : break ; } unsigned CC ; CC = ITBlock . getITCC ( ) ; if ( CC == <NUM_LIT> ) CC = <STR_LIT> ; if ( ITBlock . instrInITBlock ( ) ) ITBlock . advanceITState ( ) ; const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; MCInst :: iterator I = MI . begin ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( I == MI . end ( ) ) break ; if ( OpInfo [ i ] . isPredicate ( ) ) { if ( CC != <STR_LIT> && ! <ISA_LIT>Insts [ MI . getOpcode ( ) ] . isPredicable ( ) ) Check ( S , SoftFail ) ; I = MI . insert ( I , MCOperand :: createImm ( CC ) ) ; ++ I ; if ( CC == <STR_LIT> ) MI . insert ( I , MCOperand :: createReg ( <NUM_LIT> ) ) ; else MI . insert ( I , MCOperand :: createReg ( <STR_LIT> ) ) ; return S ; } } I = MI . insert ( I , MCOperand :: createImm ( CC ) ) ; ++ I ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ;

if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> <ISA_LIT>Mode ( const <STR_LIT> & Mode ) { IEEE = Mode . IEEE ; DX10Clamp = Mode . DX10Clamp ;


<s> DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ;


<s> Function * F = Function :: Create ( Ty , GlobalValue :: ExternalLinkage , Name , M ) ; if ( ! F -> hasFnAttribute ( <STR_LIT> ) ) { llvm :: AttrBuilder B ; B . addAttribute ( <STR_LIT> , <STR_LIT> ) ; F -> addFnAttrs ( B ) ; } if ( ! F -> hasFnAttribute ( <STR_LIT> ) ) { llvm :: AttrBuilder B ; B . addAttribute ( <STR_LIT> , F -> getName ( ) ) ; F -> addFnAttrs ( B ) ; } return F ;


<s> return ( int32x4_t ) __builtin_neon_vreinterpretv4siti ( ( __builtin_neon_ti ) __a ) ;


<s> if ( ResTy == MatchOperand_ParseFail ) return true ; switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Dollar : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( ! tryParseRegisterOperand ( Operands , Mnemonic ) ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Dollar ) ) return true ; Parser . Lex ( ) ; if ( tryParseRegisterOperand ( Operands , Mnemonic ) ) return true ; if ( ! getLexer ( ) . is ( AsmToken :: RParen ) ) return true ; S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . ParseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Minus :


<s> case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ExternalSymbol : if ( TM . getRelocationModel ( ) != Reloc :: Static ) { O << <STR_LIT> << MAI -> getGlobalPrefix ( ) << MO . getSymbolName ( ) << <STR_LIT> ; return ; } O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; return ; case MachineOperand :: MO_GlobalAddress :


if ( ix86_function_regparm ( TREE_TYPE ( function ) , function ) < <NUM_LIT> ) return true ;


<s> if ( ! Reg -> isReg ( ) || ! Reg -> isDef ( ) ) return nullptr ; MachineOperand * ResMO = nullptr ; for ( MachineOperand & UseMO : MRI -> use_nodbg_operands ( Reg -> getReg ( ) ) ) { if ( ! isSameReg ( UseMO , * Reg ) ) return nullptr ; if ( ! ResMO ) {


<s> Module * Mod = IRB -> GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; FunctionType * FT = FunctionType :: get ( Type :: getPrimitiveType ( Mod -> getContext ( ) , Type :: VoidTyID ) , false ) ; Twine TgtAddr ( Tgt ) ; AttributeSet AS ; AS = AS . addAttribute ( Mod -> getContext ( ) , AttributeSet :: FunctionIndex , <STR_LIT> , TgtAddr . str ( ) ) ; Value * Proto = Mod -> getOrInsertFunction ( FName , FT , AS ) ; IRB -> CreateCall ( dyn_cast < Value > ( Proto ) ) ;


<s> void <ISA_LIT>DAGToDAGISel :: transferMemOperands ( SDNode * N , SDNode * Result ) {

MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ;


<s> const unsigned DstR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( SrcR1 == <NUM_LIT> || SrcR1 != DstR ) && ( SrcR2 == <NUM_LIT> || SrcR2 != DstR ) ) return ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ) return ; int addrr_opcode , addri_opcode ; switch ( opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : addrr_opcode = <STR_LIT> ; addri_opcode = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; MachineInstr * NewMI = nullptr ; const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; if ( SrcR1 != <NUM_LIT> && SrcR2 != <NUM_LIT> ) { const MachineOperand & Src1 = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; const MachineOperand & Src2 = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI . getDebugLoc ( ) , TII -> get ( addrr_opcode ) ) . add ( Dst ) . add ( Src1 ) . add ( Src2 ) ; MFI -> insert ( I , NewMI ) ; DEBUG ( NewMI -> dump ( ) ; ) ; } if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { const MachineOperand & SrcR = MI . getOperand ( SrcR1 == DstR ? <NUM_LIT> : <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI . getDebugLoc ( ) , TII -> get ( addri_opcode ) ) . add ( Dst ) . add ( SrcR ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> SmallVector < const MachineMemOperand * , <NUM_LIT> > Accesses ; if ( MI . mayStore ( ) && hasStoreToStackSlot ( MI , Accesses ) && Accesses . size ( ) == <NUM_LIT> ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false ;


<s> BasicBlock * OrigBB = ConvertedInst -> getParent ( ) ; BasicBlock * NewBB = ConvertedInst -> getParent ( ) -> splitBasicBlock ( ConvertedInst , <STR_LIT> ) ; BasicBlock * LoopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , NewBB ) ; OrigBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , LoopBB ) ; IRBuilder < > Builder ( OrigBB -> getTerminator ( ) ) ; unsigned SrcAS = cast < PointerType > ( SrcAddr -> getType ( ) ) -> getAddressSpace ( ) ; unsigned DstAS = cast < PointerType > ( DstAddr -> getType ( ) ) -> getAddressSpace ( ) ;

SrcAddr = Builder . CreateBitCast ( SrcAddr , Builder . getInt8PtrTy ( SrcAS ) ) ;


<s> return ( CC == CallingConv :: Fast || CC == CallingConv :: GHC || CC == CallingConv :: HiPE || CC == CallingConv :: HHVM ) ;