<s> } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = Subtarget . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && ! Subtarget . hasFP64 ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( SrcReg == <STR_LIT> ) { copyFromCPSR ( MBB , I , DestReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { copyToCPSR ( MBB , I , SrcReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ; return ; } else if ( SrcReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( DestReg ) ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . add ( predOps ( <STR_LIT> ) ) ;


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T ) : <ISA_LIT>AsmBackend ( T ) {


<s> packet_group -> insns [ packet_group -> num_insns ++ ] = insn ; frv_packet . insns [ frv_packet . num_insns ++ ] = insn ;

frv_registers_update ( PATTERN ( insn ) ) ;


<s> if ( GET_MODE_SIZE ( m1 ) == GET_MODE_SIZE ( m2 ) ) return <NUM_LIT> ; if ( m1 == QImode || m2 == QImode ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success ;


<s> for ( auto & MI : Split ) { for ( auto & MO : MI . explicit_uses ( ) ) { if ( ! MO . isReg ( ) || Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; if ( MachineInstr * Def = MRI . getUniqueVRegDef ( MO . getReg ( ) ) ) if ( Def -> getParent ( ) == & MBB ) MFI . unstackifyVReg ( MO . getReg ( ) ) ; }


<s> void emitGlobalVariable ( const GlobalVariable * GV ) override {


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { if ( GA -> getAddressSpace ( ) != <ISA_LIT>AS :: GLOBAL_ADDRESS ) return false ;

return TargetLowering :: isOffsetFoldingLegal ( GA ) ;


<s> ConstantSDNode * AndRHS = cast < ConstantSDNode > ( Op1 ) ; uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } if ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS ; RHS = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , LHS . getValueType ( ) ) ; } } if ( LHS . getNode ( ) ) { bool Invert = false ; if ( LHS . getOpcode ( ) == <STR_LIT> && isAllOnes ( LHS . getOperand ( <NUM_LIT> ) ) ) { Invert = true ; LHS = LHS . getOperand ( <NUM_LIT> ) ; } if ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; if ( LHS . getValueType ( ) != RHS . getValueType ( ) ) RHS = DAG . getNode ( <STR_LIT> , dl , LHS . getValueType ( ) , RHS ) ;

SDValue BT = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ;


<s> Optional < StringRef > MetadataStreamerV3 :: getAccessQualifier ( StringRef AccQual ) const { return StringSwitch < Optional < StringRef >> ( AccQual ) . Case ( <STR_LIT> , StringRef ( <STR_LIT> ) ) . Case ( <STR_LIT> , StringRef ( <STR_LIT> ) ) . Case ( <STR_LIT> , StringRef ( <STR_LIT> ) ) . Default ( None ) ;


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) {


<s> const <ISA_LIT>RegisterInfo & TRI = ST . getInstrInfo ( ) -> getRegisterInfo ( ) ; unsigned Reg = R -> getReg ( ) ; if ( TRI . isPhysicalRegister ( Reg ) ) return ! TRI . isSGPRReg ( MRI , Reg ) ; if ( MRI . isLiveIn ( Reg ) ) { if ( ! TRI . isSGPRReg ( MRI , Reg ) ) return true ; else if ( ! <STR_LIT> ( FLI -> Fn -> getCallingConv ( ) ) ) return true ; return false ; } const Value * V = FLI -> getValueFromVirtualReg ( Reg ) ; if ( V ) return KDA -> isDivergent ( V ) ; assert ( Reg == FLI -> DemoteRegister || isCopyFromRegOfInlineAsm ( N ) ) ; return ! TRI . isSGPRReg ( MRI , Reg ) ; } break ; case <STR_LIT> : { const LoadSDNode * L = cast < LoadSDNode > ( N ) ; unsigned AS = L -> getAddressSpace ( ) ; return AS == <ISA_LIT>AS :: PRIVATE_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ; } break ; case <STR_LIT> : return true ; break ; case <STR_LIT> : { } return <STR_LIT> ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; case <STR_LIT> : return <STR_LIT> ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; case <STR_LIT> :


<s> if ( unsignedp ) { import_milli ( remU ) ; return output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( SImode , <STR_LIT> ) ) ; }


<s> int nios2_emit_move_sequence ( rtx * operands , machine_mode mode ) { rtx to = operands [ <NUM_LIT> ] ; rtx from = operands [ <NUM_LIT> ] ; if ( ! register_operand ( to , mode ) && ! reg_or_0_operand ( from , mode ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; from = copy_to_mode_reg ( mode , from ) ; } if ( GET_CODE ( from ) == SYMBOL_REF || GET_CODE ( from ) == LABEL_REF || ( GET_CODE ( from ) == CONST && GET_CODE ( XEXP ( from , <NUM_LIT> ) ) != UNSPEC ) ) from = nios2_legitimize_constant_address ( from ) ; operands [ <NUM_LIT> ] = to ; operands [ <NUM_LIT> ] = from ; return <NUM_LIT> ;


<s> ST = TM . getSubtargetImpl ( ) ; GR = ST -> get<ISA_LIT>GlobalRegistry ( ) ; TII = ST -> getInstrInfo ( ) ; MMI = & getAnalysis < MachineModuleInfoWrapperPass > ( ) . getMMI ( ) ; setBaseInfo ( M ) ; numberRegistersGlobally ( M ) ; processOtherInstrs ( M ) ;


<s> RegisterRef RR = Op ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return false ; if ( isRefInMap ( RR , Defs , Exec_Then ) ) return false ; if ( Op . isDef ( ) && isRefInMap ( RR , Uses , Exec_Then ) ) return false ;


<s> BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( <ISA_LIT>FI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & <STR_LIT> : & <STR_LIT> ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = <NUM_LIT> ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = <NUM_LIT> ; J < <NUM_LIT> ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , <ISA_LIT>FI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ;


<s> void emitDefCFAOffsets ( MachineBasicBlock & MBB , const DebugLoc & dl , const <ISA_LIT>BaseInstrInfo & TII , bool HasFP ) { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CFAOffset = <NUM_LIT> ; for ( auto & Info : Insts ) { if ( HasFP && ! Info . BeforeFPSet ) return ; CFAOffset += Info . SPAdjust ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , CFAOffset ) ) ; BuildMI ( MBB , std :: next ( Info . I ) , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; }


<s> bool <ISA_LIT>InstrInfo :: isLegalVSrcOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( MO . isReg ( ) ) return isLegalRegOperand ( MRI , OpInfo , MO ) ; assert ( MO . isImm ( ) || MO . isTargetIndex ( ) || MO . isFI ( ) ) ; return true ;


<s> uint64_t Sign = Imm . lshr ( <NUM_LIT> ) . getZExtValue ( ) & <NUM_LIT> ; int64_t Exp = ( Imm . lshr ( <NUM_LIT> ) . getSExtValue ( ) & <NUM_LIT> ) - <NUM_LIT> ; uint64_t Mantissa = Imm . getZExtValue ( ) & <NUM_LIT> ;

if ( Mantissa & <NUM_LIT> ) return - <NUM_LIT> ;


<s> __builtin_aarch64_st1v8hi ( ( __builtin_aarch64_simd_hi * ) a , b ) ;


<s> BaseTAI :: AlignmentIsInBytes = false ; BaseTAI :: LCOMMDirective = <STR_LIT> ;


<s> assert ( <ISA_LIT>MCInstrInfo :: isBundle ( Inst ) ) ; bool PreviousIsExtender = false ; for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( Inst ) ) { auto const & Inst = * I . getInst ( ) ; if ( ! PreviousIsExtender ) {

if ( isInstRelaxable ( Inst ) ) return true ;


<s> shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . c [ si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b ) ) ) ) & <NUM_LIT> ] = <NUM_LIT> ;


<s> rtx toload = gen_rtx_CONST ( VOIDmode , gen_rtx_PLUS ( Pmode , stack_limit_rtx , GEN_INT ( size ) ) ) ; emit_insn ( gen_elf_high ( tmp_reg , toload ) ) ; emit_insn ( gen_elf_low ( tmp_reg , tmp_reg , toload ) ) ; emit_insn ( gen_cond_trap ( LTU , stack_reg , tmp_reg , const0_rtx ) ) ; } else warning ( <NUM_LIT> , <STR_LIT> ) ; } if ( copy_reg ) { if ( copy_off != <NUM_LIT> ) emit_insn ( gen_add3_insn ( copy_reg , stack_reg , GEN_INT ( copy_off ) ) ) ; else emit_move_insn ( copy_reg , stack_reg ) ; } if ( size > <NUM_LIT> ) { if ( get_last_insn ( ) == NULL_RTX ) emit_note ( NOTE_INSN_DELETED ) ; insn = emit_move_insn ( tmp_reg , todec ) ; try_split ( PATTERN ( insn ) , insn , <NUM_LIT> ) ; todec = tmp_reg ;


<s> auto * T = dyn_cast < IntegerType > ( V -> getType ( ) ) ; if ( ! T ) return false ; unsigned BW = T -> getBitWidth ( ) ; APInt K0 ( BW , <NUM_LIT> ) , K1 ( BW , <NUM_LIT> ) ; computeKnownBits ( V , K0 , K1 , DL ) ; return K0 . countLeadingOnes ( ) >= IterCount ;


<s> } if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return MaskCost + NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; InstructionCost ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; auto * ResultTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / Factor ) ; InstructionCost NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; InstructionCost NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + MaskCost + NumOfUnfoldedLoads * MemOpCost + NumOfMoves ; return Cost ; } assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; static const CostTblEntry AVX512InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedStoreTbl , Factor , VT ) ) return MaskCost + NumOfMemOps * MemOpCost + Entry -> Cost ; unsigned NumOfSources = Factor ; InstructionCost ShuffleCost = getShuffleCost ( TTI :: SK_PermuteTwoSrc , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfShufflesPerStore = NumOfSources - <NUM_LIT> ;

unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / <NUM_LIT> ;


<s> tree node ; if ( GET_CODE ( call_ref ) != SYMBOL_REF ) return call_ref ; call_name = XSTR ( call_ref , <NUM_LIT> ) ; if ( * call_name == '.' ) { while ( * call_name == '.' ) call_name ++ ;


<s> if ( TREE_CODE ( valtype ) != RECORD_TYPE ) return <NUM_LIT> ; i = <NUM_LIT> ; for ( field = TYPE_FIELDS ( valtype ) ; field != <NUM_LIT> ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( cxx17_empty_base_field_p ( field ) ) { * has_cxx17_empty_base = true ; continue ; } if ( DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD ( field ) ) { * has_cxx_zero_width_bf = true ; continue ; } if ( ! SCALAR_FLOAT_TYPE_P ( TREE_TYPE ( field ) ) ) return <NUM_LIT> ;

if ( i == <NUM_LIT> ) return <NUM_LIT> ;


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; MVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = ( Subtarget -> isThumb ( ) || Subtarget -> useThumbBacktraces ( ) ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , NULL , <NUM_LIT> ) ;


<s> Binary |= getMachineOpValue ( MI , MO ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; unsigned ShiftAmt = MI . getOperand ( OpIdx ) . getImm ( ) ; if ( TID . Opcode == <STR_LIT> ) { assert ( ShiftAmt != <NUM_LIT> && <STR_LIT> ) ; if ( ShiftAmt == <NUM_LIT> ) ShiftAmt = <NUM_LIT> ; } assert ( ShiftAmt < <NUM_LIT> && <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertShift ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return insertMul ( MI , MBB ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const <ISA_LIT>InstrInfo & TII = ( const <ISA_LIT>InstrInfo & ) * MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * FallThrough = MBB -> getFallThrough ( ) ; if ( FallThrough != nullptr ) { BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( FallThrough ) ; } MachineBasicBlock * trueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * falseMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator I ;


<s> if ( Subtarget . hasInt256 ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( InVT ) ) return SDValue ( ) ; SDLoc DL ( N ) ; auto ExtendVecSize = [ & DAG ] ( const SDLoc & DL , SDValue N , unsigned Size ) { EVT InVT = N . getValueType ( ) ; EVT OutVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InVT . getScalarType ( ) , Size / InVT . getScalarSizeInBits ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ( Size / InVT . getSizeInBits ( ) , DAG . getUNDEF ( InVT ) ) ; Opnds [ <NUM_LIT> ] = N ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) {

SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ;


<s> BlockSet Queue = Entries ; while ( ! Queue . empty ( ) ) { Block * Curr = * ( Queue . begin ( ) ) ; Queue . remove ( * Queue . begin ( ) ) ; if ( ! contains ( InnerBlocks , Curr ) ) { InnerBlocks . insert ( Curr ) ; Blocks . remove ( Curr ) ; for ( const auto & iter : Curr -> BranchesIn ) Queue . insert ( iter ) ; } } assert ( ! InnerBlocks . empty ( ) ) ; for ( const auto & Curr : InnerBlocks ) { for ( const auto & iter : Curr -> BranchesOut ) {


<s> return matcher . Matches ( instruction ) ; } ; auto iter = std :: find_if ( table . begin ( ) , table . end ( ) , matches_instruction ) ; if ( iter == table . end ( ) ) { return Matcher < V > :: AllMatcher ( [ ] ( V & v , u16 opcode , u16 ) { return v . undefined ( opcode ) ; } ) ; } else { auto other = std :: find_if ( iter + <NUM_LIT> , table . end ( ) , matches_instruction ) ; ASSERT ( other == table . end ( ) ) ; return * iter ; }


<s> Opc = IsDirect ? <STR_LIT> : <STR_LIT> ; ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : Opc = IsDirect ? <STR_LIT> : <STR_LIT> ; ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : Opc = IsDirect ? <STR_LIT> : <STR_LIT> ; ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : Opc = IsDirect ? <STR_LIT> : <STR_LIT> ; ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : Opc = IsDirect ? <STR_LIT> : <STR_LIT> ; ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : Opc = IsDirect ? <STR_LIT> : <STR_LIT> ; ResultReg = createResultReg ( & <STR_LIT> ) ; break ; case <STR_LIT> : Opc = IsDirect ? <STR_LIT> : <STR_LIT> ; ResultReg = createResultReg ( & <STR_LIT> ) ; break ; default : return false ; } } SmallVector < unsigned , <NUM_LIT> > Args ; for ( unsigned i = <NUM_LIT> , e = Call -> getNumArgOperands ( ) ; i < e ; ++ i ) { Value * V = Call -> getArgOperand ( i ) ; <STR_LIT> ArgTy = getSimpleType ( V -> getType ( ) ) ; if ( ArgTy == <STR_LIT> ) return false ; const AttributeList & Attrs = Call -> getAttributes ( ) ; if ( Attrs . hasParamAttribute ( i , Attribute :: ByVal ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftSelf ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftError ) || Attrs . hasParamAttribute ( i , Attribute :: InAlloca ) || Attrs . hasParamAttribute ( i , Attribute :: Nest ) ) return false ; unsigned Reg ; if ( Attrs . hasParamAttribute ( i , Attribute :: SExt ) ) Reg = getRegForSignedValue ( V ) ; else if ( Attrs . hasParamAttribute ( i , Attribute :: ZExt ) ) Reg = getRegForUnsignedValue ( V ) ; else Reg = getRegForValue ( V ) ; if ( Reg == <NUM_LIT> ) return false ; Args . push_back ( Reg ) ; } auto MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; if ( ! IsVoid ) MIB . addReg ( ResultReg , RegState :: Define ) ; if ( IsDirect ) MIB . addGlobalAddress ( Func ) ; else MIB . addReg ( getRegForValue ( Call -> getCalledValue ( ) ) ) ; for ( unsigned ArgReg : Args ) MIB . addReg ( ArgReg ) ; if ( ! IsVoid ) updateValueMap ( Call , ResultReg ) ;


<s> return MBBInfos [ MBB -> getNumber ( ) ] . get ( ) ;


<s> SDValue Tmp = b . XOR ( A1 , A2 ) ; return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , b . XOR ( Tmp , b . SHL < <NUM_LIT> > ( b . AND ( b . NOT ( A1 ) , A2 ) ) ) , Tmp ) ; }


<s> void <ISA_LIT>TargetMachine :: addAnalysisPasses ( PassManagerBase & PM ) {


<s> return __builtin_mve_vcmpleq_sv8hi ( __a , __b ) ;


<s> if ( ( getInstClass ( MBBI -> getOpcode ( ) , * TII ) != InstClass ) || ( getInstSubclass ( MBBI -> getOpcode ( ) , * TII ) != InstSubclass ) ) { if ( MBBI -> hasUnmodeledSideEffects ( ) ) { return false ; } if ( MBBI -> mayLoadOrStore ( ) && ( ! memAccessesCanBeReordered ( * CI . I , * MBBI , AA ) || ! canMoveInstsAcrossMemOp ( * MBBI , InstsToMove , AA ) ) ) { InstsToMove . push_back ( & * MBBI ) ; addDefsUsesToList ( * MBBI , RegDefsToMove , PhysRegUsesToMove ) ; continue ; } addToListsIfDependent ( * MBBI , RegDefsToMove , PhysRegUsesToMove , InstsToMove ) ; continue ; } if ( MBBI -> hasOrderedMemoryRef ( ) ) return false ; int Swizzled = <STR_LIT> ( MBBI -> getOpcode ( ) , <STR_LIT> :: swz ) ; if ( Swizzled != - <NUM_LIT> && MBBI -> getOperand ( Swizzled ) . getImm ( ) ) return false ; if ( addToListsIfDependent ( * MBBI , RegDefsToMove , PhysRegUsesToMove , InstsToMove ) ) continue ; if ( & * MBBI == & * Paired . I ) { if ( canMoveInstsAcrossMemOp ( * MBBI , InstsToMove , AA ) ) { if ( CI . InstClass != MIMG ) offsetsCanBeCombined ( CI , * STM , Paired , true ) ; return true ;


<s> for ( MachineInstr & MI : make_range ( std :: next ( MachineBasicBlock :: reverse_iterator ( SCCUseInst ) ) , SCCUseInst -> getParent ( ) -> rend ( ) ) ) { if ( MI . modifiesRegister ( <STR_LIT> , & RI ) ) break ;

if ( MI . definesRegister ( <STR_LIT> , & RI ) ) {


<s> } else { Register TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; RS -> setRegUsed ( TmpVGPR ) ; unsigned PerVGPR = <NUM_LIT> ; unsigned NumVGPRs = ( NumSubRegs + ( PerVGPR - <NUM_LIT> ) ) / PerVGPR ; int64_t VGPRLanes = ( <NUM_LIT> << std :: min ( PerVGPR , NumSubRegs ) ) - <NUM_LIT> ; for ( unsigned Offset = <NUM_LIT> ; Offset < NumVGPRs ; ++ Offset ) { buildSGPRSpillLoadStore ( MI , Index , Offset , EltSize , TmpVGPR , VGPRLanes , RS , true ) ; for ( unsigned i = Offset * PerVGPR , e = std :: min ( ( Offset + <NUM_LIT> ) * PerVGPR , NumSubRegs ) ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : Register ( getSubReg ( SuperReg , SplitParts [ i ] ) ) ; bool LastSubReg = ( i + <NUM_LIT> == e ) ; auto MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SubReg ) . addReg ( TmpVGPR , getKillRegState ( LastSubReg ) ) . addImm ( i ) ;

if ( NumSubRegs > <NUM_LIT> && i == <NUM_LIT> ) MIB . addReg ( SuperReg , RegState :: ImplicitDefine ) ;


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; EVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( VT . isVector ( ) ) { MVT XORVT = VT . getSizeInBits ( ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , XORVT , DAG . getNode ( <STR_LIT> , dl , XORVT , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , XORVT , Mask ) ) ) ; } else {

return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , Mask ) ;


<s> return Subtarget -> hasSVE ( ) && Subtarget -> getMinSVEVectorSizeInBits ( ) >= <NUM_LIT> ;


__builtin_aarch64_st1v8hi ( ( __builtin_aarch64_simd_hi * ) a , b ) ;


<s> if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; }


<s> default : break ; case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; } if ( tlsOpNo != <NUM_LIT> ) { const MCOperand & MO = MI . getOperand ( tlsOpNo ) ; uint64_t op = getMachineOpValue ( MI , MO , Fixups , STI ) ;

assert ( op == <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; return InputIdx * EltSize / <NUM_LIT> != OutputIdx * EltSize / <NUM_LIT> ;


<s> if ( auto * ConstAVL = dyn_cast < ConstantSDNode > ( AVL ) ) { LegalAVL = CDAG . getConstant ( ( ConstAVL -> getZExtValue ( ) + <NUM_LIT> ) / <NUM_LIT> , <STR_LIT> ) ; } else { auto ConstOne = CDAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; auto PlusOne = CDAG . getNode ( <STR_LIT> , <STR_LIT> , { AVL , ConstOne } ) ; LegalAVL = CDAG . getNode ( <STR_LIT> , <STR_LIT> , { PlusOne , ConstOne } ) ; } }

SDValue AnnotatedLegalAVL = CDAG . annotateLegalAVL ( LegalAVL ) ;


<s> return tryParseRegister ( RegNo , StartLoc , EndLoc ) != MatchOperand_Success ;


<s> bool Modified = false ; for ( std :: list < CombineInfo > & MergeList : MergeableInsts ) { if ( MergeList . size ( ) < <NUM_LIT> ) continue ; bool OptimizeListAgain = false ; if ( ! optimizeInstsWithSameBaseAddr ( MergeList , OptimizeListAgain ) ) { MergeList . clear ( ) ; continue ; } if ( ! OptimizeListAgain ) MergeList . clear ( ) ; OptimizeAgain |= OptimizeListAgain ; Modified = true ; }


<s> isThumb ( false ) , hasThumb2 ( false ) , ArgRegsSaveSize ( <NUM_LIT> ) , HasStackFrame ( false ) , RestoreSPFromFP ( false ) , LRSpilledForFarJump ( false ) , FramePtrSpillOffset ( <NUM_LIT> ) , GPRCS1Offset ( <NUM_LIT> ) , GPRCS2Offset ( <NUM_LIT> ) , DPRCSOffset ( <NUM_LIT> ) , GPRCS1Size ( <NUM_LIT> ) , GPRCS2Size ( <NUM_LIT> ) , DPRCSSize ( <NUM_LIT> ) , NumAlignedDPRCS2Regs ( <NUM_LIT> ) , JumpTableUId ( <NUM_LIT> ) , PICLabelUId ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , HasITBlocks ( false ) , GlobalBaseReg ( <NUM_LIT> ) {


<s> bool isISA3_1 ( ) const { return IsISA3_1 ;


<s> static machine_mode counter_mode ( rtx count_exp ) { if ( GET_MODE ( count_exp ) != VOIDmode ) return GET_MODE ( count_exp ) ; if ( ! CONST_INT_P ( count_exp ) ) return Pmode ;

if ( TARGET_64BIT && ( INTVAL ( count_exp ) & ~ <NUM_LIT> ) ) return DImode ;


<s> extern __inline __m128d __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_load_pd ( double const * __P ) { return * ( __m128d * ) __P ;


<s> return isMovWSymbol ( { <ISA_LIT>MCExpr :: VK_ABS_G3 , <ISA_LIT>MCExpr :: VK_PREL_G3 } ) ;


<s> Register ValVReg = VA . getLocInfo ( ) != CCValAssign :: LocInfo :: FPExt ? extendRegister ( Arg . Regs [ <NUM_LIT> ] , VA , MaxSize ) : Arg . Regs [ <NUM_LIT> ] ; const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBytes ( ) > Size ) Size = RegTy . getSizeInBytes ( ) ;

assignValueToAddress ( ValVReg , Addr , Size , MPO , VA ) ;


<s> unsigned CmpR1 = <NUM_LIT> , CmpR2 = <NUM_LIT> ; const MachineInstr * CmpI = MRI -> getVRegDef ( PR ) ; while ( CmpI -> getOpcode ( ) == <STR_LIT> ) CmpI = MRI -> getVRegDef ( CmpI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int Mask = <NUM_LIT> , Val = <NUM_LIT> ; bool OkCI = TII -> analyzeCompare ( * CmpI , CmpR1 , CmpR2 , Mask , Val ) ; if ( ! OkCI ) return ; if ( CmpR1 && MRI -> getRegClass ( CmpR1 ) != DoubleRC ) CmpR1 = <NUM_LIT> ; if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; typedef std :: vector < unsigned > UVect ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; unsigned R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) {

const MachineInstr * UseI = I -> getParent ( ) ;


<s> } else if ( Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> || Inst . Opc == <STR_LIT> ) { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ) ; } else { emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ; } SrcReg = DestReg ; }


<s> TargetIRAnalysis <ISA_LIT>BaseTargetMachine :: getTargetIRAnalysis ( ) {

return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } ) ;


<s> NextMII = std :: next ( MII ) ; MachineInstr * MI = & * MII ; if ( MI -> isBundle ( ) || MI -> isTransient ( ) ) continue ;


<s> Shuffle = <STR_LIT> ; ShuffleVT = ( FloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( Mask ) ; return true ; } if ( Subtarget . hasAVX512 ( ) && SrcVT . is512BitVector ( ) && Mask . size ( ) == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { Shuffle = <STR_LIT> ; ShuffleVT = ( FloatDomain ? <STR_LIT> : <STR_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( RepeatedMask ) ; return true ; } } return false ; } if ( FloatDomain && MaskScalarSizeInBits == <NUM_LIT> ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , Mask . size ( ) ) ; PermuteImm = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) continue ; assert ( ( ( M / <NUM_LIT> ) == ( i / <NUM_LIT> ) ) && <STR_LIT> ) ; PermuteImm |= ( M & <NUM_LIT> ) << i ; } return true ; } SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( ! is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) return false ; SmallVector < int , <NUM_LIT> > WordMask = RepeatedMask ; if ( MaskScalarSizeInBits == <NUM_LIT> ) scaleShuffleMask ( <NUM_LIT> , RepeatedMask , WordMask ) ; Shuffle = ( FloatDomain ? <STR_LIT> : <STR_LIT> ) ; ShuffleVT = ( FloatDomain ? <STR_LIT> : <STR_LIT> ) ;

ShuffleVT = <STR_LIT> ( ShuffleVT , SrcVT . getSizeInBits ( ) / <NUM_LIT> ) ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , uint8_t _OSABI ) : <ISA_LIT>AsmBackend ( T , TT ) , OSABI ( _OSABI ) {


<s> std :: string Func1 = addPrefix ( Func ) ; std :: string tag = getTagName ( AUTOS_SECTION ) ;


<s> void addImm0_31Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;


<s> static inline bool getMemDoShift ( unsigned Imm ) { return ( Imm & <NUM_LIT> ) != <NUM_LIT> ;


<s> if ( ! Op . isReg ( ) ) continue ; RegisterRef RR = Op ; if ( ! TargetRegisterInfo :: isVirtualRegister ( RR . Reg ) ) return false ; ReferenceMap & Map = Op . isDef ( ) ? Defs : Uses ; if ( Op . isDef ( ) && Op . isUndef ( ) ) { assert ( RR . Sub && <STR_LIT> ) ; RR . Sub = <NUM_LIT> ; } addRefToMap ( RR , Map , Exec ) ; } } if ( isRefInMap ( RT , Defs , Exec_Then ) || isRefInMap ( RT , Uses , Exec_Else ) ) return false ; RegisterRef RD = MD ; bool CanUp = canMoveOver ( TfrI , Defs , Uses ) ; bool CanDown = canMoveOver ( * DefI , Defs , Uses ) ; if ( DefI -> mayLoad ( ) || DefI -> mayStore ( ) ) if ( ! canMoveMemTo ( * DefI , TfrI , true ) ) CanDown = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( CanUp ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( CanDown ? <STR_LIT> : <STR_LIT> ) ) ;

MachineBasicBlock :: iterator PastDefIt = std :: next ( DefIt ) ;


<s> case <STR_LIT> : { unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) + MI . getDesc ( ) . getNumImplicitUses ( ) ; return MI . getNumOperands ( ) == NumOps ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; }


<s> MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent ( ) ; return BB ;


<s> vpmin_u32 ( uint32x2_t a , uint32x2_t b ) { return ( uint32x2_t ) __builtin_aarch64_uminpv2si ( ( int32x2_t ) a , ( int32x2_t ) b ) ;


<s> static __inline void sh_media_FTRV_S ( const void * mtrxg , const void * fvh , void * fvf ) { typedef float v16sf __attribute__ ( ( mode ( V16SF ) ) ) ; typedef float v4sf __attribute__ ( ( mode ( V4SF ) ) ) ; v16sf mtrx = * ( v16sf * ) mtrxg ;


<s> EmitProgramInfo<ISA_LIT> ( MF ) ; } DisasmLines . clear ( ) ; HexLines . clear ( ) ; DisasmLineMaxLen = <NUM_LIT> ; EmitFunctionBody ( ) ; if ( isVerbose ( ) ) { MCSectionELF * CommentSection = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; OutStreamer -> SwitchSection ( CommentSection ) ; if ( STM . getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { OutStreamer -> emitRawComment ( <STR_LIT> , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . CodeLen ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumSGPR ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumVGPR ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . FloatMode ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . IEEEMode ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . ScratchSize ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . LDSSize ) + <STR_LIT> , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . SGPRBlocks ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . VGPRBlocks ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumSGPRsForWavesPerEU ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumVGPRsForWavesPerEU ) , false ) ;

OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . ReservedVGPRFirst ) , false ) ;


<s> const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; int WaitStatesNeeded = <NUM_LIT> ; for ( const MachineOperand & Def : VALU -> defs ( ) ) { WaitStatesNeeded = std :: max ( WaitStatesNeeded , checkVALUHazardsHelper ( Def , MRI ) ) ; } return WaitStatesNeeded ;


<s> void <ISA_LIT>DAGToDAGISel :: PreprocessTrunc ( SDNode * Node , SelectionDAG :: allnodes_iterator & I ) { ConstantSDNode * MaskN = dyn_cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( ! MaskN ) return ; SDValue BaseV = Node -> getOperand ( <NUM_LIT> ) ; if ( BaseV . getOpcode ( ) == <STR_LIT> ) { unsigned IntNo = cast < ConstantSDNode > ( BaseV -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; uint64_t MaskV = MaskN -> getZExtValue ( ) ; if ( ! ( ( IntNo == <STR_LIT> && MaskV == <NUM_LIT> ) || ( IntNo == <STR_LIT> && MaskV == <NUM_LIT> ) || ( IntNo == <STR_LIT> && MaskV == <NUM_LIT> ) ) ) return ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( ) ; dbgs ( ) << '\n' ) ; I -- ; CurDAG -> ReplaceAllUsesWith ( SDValue ( Node , <NUM_LIT> ) , BaseV ) ; I ++ ; CurDAG -> DeleteNode ( Node ) ; return ; } if ( BaseV . getOpcode ( ) != <STR_LIT> ) return ; unsigned match_load_op = <NUM_LIT> ; switch ( MaskN -> getZExtValue ( ) ) { default : return ; case <NUM_LIT> : match_load_op = <STR_LIT> ; break ; case <NUM_LIT> : match_load_op = <STR_LIT> ; break ; case <NUM_LIT> : match_load_op = <STR_LIT> ; break ; } const RegisterSDNode * RegN = dyn_cast < RegisterSDNode > ( BaseV . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( ! RegN || ! Register :: isVirtualRegister ( RegN -> getReg ( ) ) ) return ; unsigned AndOpReg = RegN -> getReg ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( AndOpReg ) << '\n' ) ; MachineBasicBlock * MBB = FuncInfo -> MBB ; MachineInstr * MII = nullptr ; for ( auto & MI : * MBB ) { for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; ++ i ) { const MachineOperand & MOP = MI . getOperand ( i ) ;

if ( ! MOP . isReg ( ) || ! MOP . isDef ( ) ) continue ;


<s> return isMemOp ( ) && MemOp . Op == <STR_LIT> :: RegPostIncrement && <STR_LIT> . contains ( MemOp . OuterReg ) ;


<s> DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; MI . clear ( ) ; }

return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>BaseTargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Width = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = Width = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> :


<s> rtx src = operands [ <NUM_LIT> ] ; rtx val ; if ( GET_CODE ( dest ) == SUBREG ) alter_subreg ( & dest ) ; if ( GET_CODE ( src ) == SUBREG ) alter_subreg ( & src ) ; start_sequence ( ) ; if ( GET_CODE ( dest ) == REG ) { int dregno = REGNO ( dest ) ; if ( GET_CODE ( src ) == REG ) { int sregno = REGNO ( src ) ; int reverse = ( dregno == sregno + <NUM_LIT> ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operand_subword ( dest , reverse , TRUE , mode ) , operand_subword ( src , reverse , TRUE , mode ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operand_subword ( dest , ! reverse , TRUE , mode ) , operand_subword ( src , ! reverse , TRUE , mode ) ) ) ; } else if ( GET_CODE ( src ) == CONST_INT || GET_CODE ( src ) == CONST_DOUBLE ) { rtx words [ <NUM_LIT> ] ; split_double ( src , & words [ <NUM_LIT> ] , & words [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operand_subword ( dest , <NUM_LIT> , TRUE , mode ) , words [ <NUM_LIT> ] ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operand_subword ( dest , <NUM_LIT> , TRUE , mode ) , words [ <NUM_LIT> ] ) ) ;


<s> if ( CallerF . hasFnAttribute ( <STR_LIT> ) ) return false ; if ( canGuaranteeTCO ( CalleeCC , getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ) return CalleeCC == CallerCC ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( getEffectiveCallingConv ( CalleeCC , isVarArg ) , getEffectiveCallingConv ( CallerCC , CallerF . isVarArg ( ) ) , MF , C , Ins , CCAssignFnForReturn ( CalleeCC , isVarArg ) , CCAssignFnForReturn ( CallerCC , CallerF . isVarArg ( ) ) ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ;

if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ;


<s> uint64_t imm = SignExtend64 < <NUM_LIT> > ( tmp ) ; MI . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> PROMOTE_MODE ( mode , * punsignedp , type ) ;


<s> vrsqrteq_u32 ( uint32x4_t a ) { uint32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result ;


<s> int ar5_mem_operand ( rtx op , enum machine_mode mode ) {

return c4x_arn_mem_operand ( op , mode , AR5_REGNO ) ;


<s> else if ( rclass == ALTIVEC_REGS || rclass == VSX_REGS ) return ALTIVEC_REGS ; else return NO_REGS ; } if ( IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) && TARGET_P9_VECTOR && ( rclass == ALTIVEC_REGS || rclass == VSX_REGS ) ) return ALTIVEC_REGS ; } return NO_REGS ; } if ( mode_supports_vmx_dform ( mode ) || mode_supports_dq_form ( mode ) ) return rclass ; if ( rclass == VSX_REGS && ( mode == SFmode || GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ) return FLOAT_REGS ; if ( VECTOR_UNIT_ALTIVEC_P ( mode ) || VECTOR_MEM_ALTIVEC_P ( mode ) || mode == V1TImode ) return ALTIVEC_REGS ; return rclass ; } if ( is_constant || GET_CODE ( x ) == PLUS ) { if ( reg_class_subset_p ( GENERAL_REGS , rclass ) ) return GENERAL_REGS ; if ( reg_class_subset_p ( BASE_REGS , rclass ) ) return BASE_REGS ; return NO_REGS ; } if ( rclass == GEN_OR_FLOAT_REGS ) { if ( mode == OOmode ) return VSX_REGS ; if ( mode == XOmode ) return FLOAT_REGS ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) return GENERAL_REGS ;


<s> bool gate ( function * ) final override {

return ( TARGET_AVX && TARGET_SSE_PARTIAL_REG_DEPENDENCY && TARGET_SSE_MATH && optimize && optimize_function_for_speed_p ( cfun ) ) ;


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return N -> setNodeId ( - <NUM_LIT> ) ; switch ( N -> getOpcode ( ) ) { case <STR_LIT> : return SelectConstant ( N ) ; case <STR_LIT> : return SelectConstantFP ( N ) ; case <STR_LIT> : return SelectFrameIndex ( N ) ; case <STR_LIT> : return SelectBitcast ( N ) ; case <STR_LIT> : return SelectSHL ( N ) ; case <STR_LIT> : return SelectLoad ( N ) ; case <STR_LIT> : return SelectStore ( N ) ; case <STR_LIT> : return SelectZeroExtend ( N ) ; case <STR_LIT> : return SelectIntrinsicWChain ( N ) ; case <STR_LIT> : return SelectIntrinsicWOChain ( N ) ; }


<s> MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; const TargetRegisterClass * GPRC = & <STR_LIT> ; Register Reg = MF . getRegInfo ( ) . createVirtualRegister ( GPRC ) ;

Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQRegPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops ) ;


<s> HighBitsOf32BitAddress = YamlMFI . HighBitsOf32BitAddress ; IsEntryFunction = YamlMFI . IsEntryFunction ; NoSignedZerosFPMath = YamlMFI . NoSignedZerosFPMath ; MemoryBound = YamlMFI . MemoryBound ;


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelDyn ( ) const {

assert ( m_pRelDyn != NULL && <STR_LIT> ) ;


<s> std :: string LowerCase = Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ; RefKind = StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( LowerCase ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_PREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_PAGE_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_PAGE_LO15 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_SECREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_SECREL_HI12 ) . Default ( <ISA_LIT>MCExpr :: VK_INVALID ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_INVALID ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: Colon , <STR_LIT> ) ) return true ;


<s> SDLoc dl ( N ) ; MVT IntScalar = <STR_LIT> ( VT . getScalarSizeInBits ( ) ) ; MVT IntVT = <STR_LIT> ( IntScalar , VT . getVectorNumElements ( ) ) ; SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , IntVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , IntVT , N -> getOperand ( <NUM_LIT> ) ) ; unsigned IntOpcode = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; case <STR_LIT> : IntOpcode = <STR_LIT> ; break ; } SDValue IntOp = DAG . getNode ( IntOpcode , dl , IntVT , Op0 , Op1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , IntOp ) ; }


<s> return isThumb ( ) && getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> else if ( arg_num <= LAST_ARG_REGNUM ) { ret = gen_rtx_REG ( xmode , arg_num ) ; debstr = reg_names [ arg_num ] ; } else { ret = NULL_RTX ; debstr = <STR_LIT> ; }

if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , arg_num , GET_MODE_NAME ( mode ) , named , GET_MODE_SIZE ( mode ) , debstr ) ;


<s> static __inline qword si_from_ullong ( unsigned long long l ) { union { qword q ;


<s> int NewOp = MI . getOpcode ( ) ; if ( isPredicated ( NewOp ) && isPredicatedNew ( NewOp ) ) { NewOp = <STR_LIT> ( NewOp ) ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! HST . getFeatureBits ( ) [ <STR_LIT> ] ) { switch ( NewOp ) { case <STR_LIT> : NewOp = <STR_LIT> ; break ; case <STR_LIT> :


<s> void <ISA_LIT>InstrInfo :: insertOutlinerPrologue ( MachineBasicBlock & MBB , MachineFunction & MF , const MachineOutlinerInfo & MInfo ) const {


<s> MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; const MCSymbol * Symbol ; switch ( MOTy ) { case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = Mang -> getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: Create ( Symbol , Kind , * Ctx ) ; if ( ! Offset ) return MCOperand :: CreateExpr ( MCSym ) ; assert ( Offset > <NUM_LIT> ) ;

const MCConstantExpr * OffsetExpr = MCConstantExpr :: Create ( Offset , * Ctx ) ;


<s> KnownOne &= Mask ; return ; } if ( Op . getOpcode ( ) == <STR_LIT> ) { APInt KZ2 ( KnownZero . getBitWidth ( ) , <NUM_LIT> ) ; APInt KO2 ( KnownOne . getBitWidth ( ) , <NUM_LIT> ) ;

computeKnownBits ( DAG , Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne ) ;


<s> Triple TheTriple ( TT ) ; switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MCStreamer * S = createMachOStreamer ( Ctx , MAB , OS , Emitter , false ) ; new <ISA_LIT>TargetStreamer ( * S ) ; return S ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return create<ISA_LIT>WinCOFFStreamer ( Ctx , MAB , * Emitter , OS ) ; case Triple :: ELF :

return create<ISA_LIT>ELFStreamer ( Ctx , MAB , OS , Emitter , false , NoExecStack , TheTriple . getArch ( ) == Triple :: thumb ) ;


<s> TBB = FBB = nullptr ; Cond . clear ( ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return false ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = <NUM_LIT> ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ;

if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) {


<s> void ix86_expand_sse2_abs ( rtx target , rtx input ) { machine_mode mode = GET_MODE ( target ) ; rtx tmp0 , tmp1 , x ; switch ( mode ) { case V4SImode :

tmp0 = expand_simple_binop ( mode , ASHIFTRT , input , GEN_INT ( GET_MODE_UNIT_BITSIZE ( mode ) - <NUM_LIT> ) , NULL , <NUM_LIT> , OPTAB_DIRECT ) ;


<s> fputs ( <STR_LIT> , f ) ; assemble_name ( f , IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( cfun -> decl ) ) ) ; fputc ( '\n' , f ) ;


<s> int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; MII = MBB -> erase ( MI ) ; continue ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned DestLo = QTM . getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; unsigned DestHi = QTM . getRegisterInfo ( ) -> getSubReg ( DestReg , <STR_LIT> ) ; int32_t LowWord = ( ImmValue & <NUM_LIT> ) ; int32_t HighWord = ( ImmValue >> <NUM_LIT> ) & <NUM_LIT> ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestHi ) . addImm ( HighWord ) ; MII = MBB -> erase ( MI ) ; continue ; } ++ MII ; } } return true ;


<s> for ( auto U : UsesToProcess ) { MachineInstr * UseMI = U -> getParent ( ) ; foldOperand ( OpToFold , UseMI , U . getOperandNo ( ) , FoldList , CopiesToReplace ) ; } } MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; for ( MachineInstr * Copy : CopiesToReplace ) Copy -> addImplicitDefUseOperands ( * MF ) ; for ( FoldCandidate & Fold : FoldList ) { if ( updateOperand ( Fold , * TII , * TRI , * ST ) ) { if ( Fold . isReg ( ) ) { assert ( Fold . OpToFold && Fold . OpToFold -> isReg ( ) ) ; MRI -> clearKillFlags ( Fold . OpToFold -> getReg ( ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << static_cast < int > ( Fold . UseOpNo ) << <STR_LIT> << * Fold . UseMI << '\n' ) ; tryFoldInst ( TII , Fold . UseMI ) ; } else if ( Fold . isCommuted ( ) ) {

TII -> commuteInstruction ( * Fold . UseMI , false ) ;


<s> addr = plus_constant ( Pmode , stack_pointer_rtx , epiphany_stack_offset - ( HOST_WIDE_INT ) UNITS_PER_WORD ) ; epiphany_emit_save_restore ( <NUM_LIT> , current_frame_info . small_threshold , addr , <NUM_LIT> ) ; if ( current_frame_info . first_slot >= <NUM_LIT> ) { machine_mode mode = ( current_frame_info . first_slot_size == UNITS_PER_WORD ? word_mode : DImode ) ; off = GEN_INT ( - current_frame_info . first_slot_offset ) ; mem = gen_frame_mem ( BLKmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , off ) ) ; frame_insn ( gen_stack_adjust_str ( gen_frame_mem ( mode , stack_pointer_rtx ) , gen_rtx_REG ( mode , current_frame_info . first_slot ) , off , mem ) ) ; addr = plus_constant ( Pmode , addr , current_frame_info . first_slot_offset ) ; } } epiphany_emit_save_restore ( current_frame_info . small_threshold , FIRST_PSEUDO_REGISTER , addr , <NUM_LIT> ) ; if ( current_frame_info . need_fp ) frame_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; if ( current_frame_info . last_slot >= <NUM_LIT> ) { rtx ip , mem2 , note ; rtx_insn * insn ;


<s> APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs ) ) return SplatValue . isAllOnesValue ( ) ; return false ;


<s> } if ( AllConst ) { uint64_t Val = <NUM_LIT> ; unsigned W = ElemTy . getSizeInBits ( ) ; uint64_t Mask = ( <NUM_LIT> << W ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Num ; ++ i ) Val = ( Val << W ) | ( Consts [ Num - <NUM_LIT> - i ] -> getZExtValue ( ) & Mask ) ; SDValue V0 = DAG . getConstant ( Val , dl , <STR_LIT> ) ; return DAG . getBitcast ( VecTy , V0 ) ; } MVT HalfTy = <STR_LIT> ( ElemTy , Num / <NUM_LIT> ) ; SDValue L = ( ElemTy == <STR_LIT> ) ? Elem [ <NUM_LIT> ] : buildVector32 ( Elem . take_front ( Num / <NUM_LIT> ) , dl , HalfTy , DAG ) ; SDValue H = ( ElemTy == <STR_LIT> ) ? Elem [ <NUM_LIT> ] : buildVector32 ( Elem . drop_front ( Num / <NUM_LIT> ) , dl , HalfTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , { H , L } ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << * Operand << '\n' ) ;

SDWAOperands [ & MI ] = std :: move ( Operand ) ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( ( mode == BLKmode || GET_MODE_CLASS ( mode ) != MODE_COMPLEX_INT || GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) && cum -> arg_words < MAX_ARGS_IN_REGISTERS ) { int words ; if ( mode == BLKmode ) words = ( ( int_size_in_bytes ( type ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; else words = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( words + cum -> arg_words <= MAX_ARGS_IN_REGISTERS ) return <NUM_LIT> ; return ( MAX_ARGS_IN_REGISTERS - cum -> arg_words ) * UNITS_PER_WORD ; } else if ( mode == DImode && cum -> arg_words == MAX_ARGS_IN_REGISTERS - <NUM_LIT> ) return UNITS_PER_WORD ; return <NUM_LIT> ;


<s> emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) . addImm ( <NUM_LIT> ) ; updateValueMap ( II , DestReg ) ; return true ; } else { unsigned TempReg [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { TempReg [ i ] = createResultReg ( & <STR_LIT> ) ; if ( TempReg [ i ] == <NUM_LIT> ) return false ; } emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ; emitInst ( <STR_LIT> , TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg [ <NUM_LIT> ] ) . addReg ( TempReg [ <NUM_LIT> ] ) ; updateValueMap ( II , DestReg ) ; return true ;


<s> return __builtin_mve_vcmpeqq_n_v16qi ( ( int8x16_t ) __a , ( int8_t ) __b ) ;


<s> BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ;


<s> MCOperand <ISA_LIT>Disassembler :: decodeOperand_AReg_256 ( unsigned Val ) const { return createRegOperand ( <STR_LIT> , Val & <NUM_LIT> ) ;


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {


<s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex ;


<s> } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = <STR_LIT> ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = <STR_LIT> ; return true ; } if ( VT != <STR_LIT> ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , false ) ) return false ;


<s> if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC > - <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ;

if ( Base . getOpcode ( ) == <STR_LIT> ) {


<s> bool <ISA_LIT>InstrInfo :: moveTo ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & Target , MachineBasicBlock :: iterator & Source , SmallVectorImpl < MachineOperand > * Pred , bool Negate ) const { if ( Target -> isBundle ( ) ) return false ; if ( Target -> getOpcode ( ) == <STR_LIT> ) { Source = MBB . insert ( Target , MBB . remove ( Source ) ) ; MBB . erase ( Target ) ; if ( Pred ) { PredicateInstruction ( & * Source , * Pred ) ; } if ( Negate ) { NegatePredicate ( & * Source ) ; }


return __builtin_neon_vrndav8hf ( __a ) ;


<s> auto Reg = StackReg . drop_front ( StackOp . size ( ) ) ; unsigned long long ParsedRegNo = <NUM_LIT> ; if ( ! Reg . empty ( ) && getAsUnsignedInteger ( Reg , <NUM_LIT> , ParsedRegNo ) ) return Error ( <STR_LIT> , StackRegTok ) ; unsigned RegNo = static_cast < unsigned > ( ParsedRegNo ) ; if ( StackOp == <STR_LIT> ) { auto RegType = ParseRegType ( TypePrefix ) ; GetType ( StackTypes , RegNo ) = RegType ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , StackRegTok . getLoc ( ) , StackRegTok . getEndLoc ( ) , <STR_LIT> { RegNo , RegType } ) ) ; } else if ( StackOp == <STR_LIT> ) { auto RegType = GetType ( StackTypes , RegNo ) ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , StackRegTok . getLoc ( ) , StackRegTok . getEndLoc ( ) , <STR_LIT> { RegNo , RegType } ) ) ; } else if ( StackOp == <STR_LIT> ) { } else { return Error ( <STR_LIT> , StackRegTok ) ; } Parser . Lex ( ) ; } else {

return Error ( <STR_LIT> , Lexer . getTok ( ) ) ;


<s> MCStreamer * <ISA_LIT>TargetMachine :: createMCStreamerToAsm ( MCContext & Context , std :: unique_ptr < formatted_raw_ostream > FOut , MCInstPrinter * InstPrinter , MCCodeEmitter * MCE , MCAsmBackend * MAB ) {

MCStreamer * S = new <ISA_LIT>MCAsmStreamer ( Context , std :: move ( FOut ) , Options . MCOptions . AsmVerbose , InstPrinter , Options . MCOptions . ShowMCInst ) ;


<s> SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectT2AddrModeImm7 ( SDValue N , SDValue & Base , SDValue & OffImm ) { if ( N . getOpcode ( ) == <STR_LIT> || CurDAG -> isBaseWithConstantOffset ( N ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> << Shift , - <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ;

OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ;


return F != Colors . end ( ) ? F -> second : ColorKind :: None ;


<s> case <ISA_LIT>ABIInfo :: ABI :: N64 : return <STR_LIT> ; case <ISA_LIT>ABIInfo :: ABI :: EABI : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( V -> getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) ) return false ; ConstantSDNode * CN = cast < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) ;

return CurDAG -> MaskedValueIsZero ( V -> getOperand ( <NUM_LIT> ) , CN -> getAPIntValue ( ) ) ;


<s> assert ( TII -> isLegalFLATOffset ( NewOffset , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) && <STR_LIT> ) ; FIOp -> ChangeToRegister ( BaseReg , false ) ; OffsetOp -> setImm ( NewOffset ) ; return ; } MachineOperand * SOffset = TII -> getNamedOperand ( MI , <STR_LIT> :: soffset ) ; assert ( SOffset -> isImm ( ) && SOffset -> getImm ( ) == <NUM_LIT> ) ; assert ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( NewOffset ) && <STR_LIT> ) ; FIOp -> ChangeToRegister ( BaseReg , false ) ;


<s> void emitRRI ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , int16_t Imm , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { emitRRX ( Opcode , Reg0 , Reg1 , MCOperand :: createImm ( Imm ) , IDLoc , Instructions ) ;


<s> uint32_t Reg = RI -> getRegClass ( <STR_LIT> ) . getRegister ( RI -> getEncodingValue ( getReg ( ) ) ) ;

Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ;


<s> <ISA_LIT>ISelAddressMode AM ; if ( MatchAddress ( N , AM ) ) return false ; EVT VT = N . getValueType ( ) ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) {

if ( ! AM . Base_Reg . getNode ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ;


<s> switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : break ; } llvm_unreachable ( <STR_LIT> ) ;


<s> NodeOrdering ( ) : LastNum ( <NUM_LIT> ) {


<s> return ( ( vec_ushort8 ) spu_splats ( <NUM_LIT> ) ) ;


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<s> if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && RHS . getOpcode ( ) == <STR_LIT> ) if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) == <NUM_LIT> && RHS . hasOneUse ( ) ) { SDValue addV = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , RHS . getValueType ( ) , LHS , RHS . getOperand ( <NUM_LIT> ) ) ;

return DAG . getSetCC ( SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , addV . getValueType ( ) ) , CC ) ;


<s> return frame_pointer_needed || regs_ever_live [ REG_FP ] ;


<s> case CONST : return sparc_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : return sparc_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) ) || sparc_cannot_force_const_mem ( mode , XEXP ( x , <NUM_LIT> ) ) ; case UNSPEC : return true ;


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { Pred . push_back ( MO ) ; Found = true ; } }


<s> MVT VT = Op . getSimpleValueType ( ) ; switch ( VT . SimpleTy ) { default : break ; case <STR_LIT> : case <STR_LIT> :


<s> return Reg . isVirtual ( ) && MRI -> getRegClass ( Reg ) == & <STR_LIT> ;


<s> bool <ISA_LIT>SinglePathInfo :: isEnabled ( const MachineFunction & MF ) { return isRoot ( MF ) || isReachable ( MF ) || isMaybe ( MF ) ;


<s> switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; } return Val ;


<s> unsigned Opc = I -> second . first ; unsigned Index = I -> second . second & TB_INDEX_MASK ; bool FoldedLoad = I -> second . second & TB_FOLDED_LOAD ; bool FoldedStore = I -> second . second & TB_FOLDED_STORE ; const MCInstrDesc & MCID = get ( Opc ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetRegisterClass * RC = getRegClass ( MCID , Index , & RI , MF ) ; unsigned NumDefs = MCID . NumDefs ; std :: vector < SDValue > AddrOps ; std :: vector < SDValue > BeforeOps ; std :: vector < SDValue > AfterOps ; DebugLoc dl = N -> getDebugLoc ( ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = <NUM_LIT> ; if ( FoldedLoad ) { EVT VT = * RC -> vt_begin ( ) ; std :: pair < MachineInstr :: mmo_iterator , MachineInstr :: mmo_iterator > MMOs = MF . extractLoadMemRefs ( cast < MachineSDNode > ( N ) -> memoperands_begin ( ) , cast < MachineSDNode > ( N ) -> memoperands_end ( ) ) ; if ( ! ( * MMOs . first ) && RC == & <STR_LIT> && ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isUnalignedMemAccessFast ( ) ) return false ; unsigned Alignment = RC -> getSize ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;

bool isAligned = ( * MMOs . first ) && ( * MMOs . first ) -> getAlignment ( ) >= Alignment ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ;

Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitEndFunc ( ) { Streamer . EmitIntValue ( <STR_LIT> , sizeof ( uint64_t ) ) ;


<s> } SDValue Lower = CurDAG -> getConstant ( LowerVal , DL , VT ) ; SDValue Or = CurDAG -> getNode ( Opcode , DL , VT , Upper , Lower ) ; ReplaceUses ( Node , Or . getNode ( ) ) ; CurDAG -> RemoveDeadNode ( Node ) ; SelectCode ( Or . getNode ( ) ) ;


<s> } } else if ( ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { if ( OpNum == <NUM_LIT> ) { unsigned InReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( InReg , false , false , isKill ) , FrameIndex ) ; } else { unsigned OutReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( OutReg , true , false , false , isDead ) , FrameIndex ) ; } } else if ( Opc == <STR_LIT> ) { if ( OpNum == <NUM_LIT> ) { unsigned InReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( InReg , false , false , isKill ) , FrameIndex ) ; } else { unsigned OutReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = addFrameReference ( BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( OutReg , true , false , false , isDead ) , FrameIndex ) ; } } else if ( Opc == <STR_LIT> ) { if ( OpNum == <NUM_LIT> ) { unsigned InReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ;


<s> static bool xstormy16_mode_dependent_address_p ( const_rtx x , addr_space_t as ATTRIBUTE_UNUSED ) {

if ( LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) && ! LEGITIMATE_ADDRESS_CONST_INT_P ( x , <NUM_LIT> ) ) return true ;


<s> assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; if ( Imm > <NUM_LIT> ) { Imm = ( SignExtend64 < <NUM_LIT> > ( Imm ) & <NUM_LIT> ) ; } Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success ;


<s> return ( size > <NUM_LIT> || size == <NUM_LIT> ) ;


<s> static bool aarch64_base_register_rtx_p ( rtx x , bool strict_p ) {

if ( ! strict_p && GET_CODE ( x ) == SUBREG && contains_reg_of_mode [ GENERAL_REGS ] [ GET_MODE ( SUBREG_REG ( x ) ) ] ) x = SUBREG_REG ( x ) ;


<s> virtual bool isCondCode ( ) const { return Kind == KindCondCode ;


<s> case 'R' : return C_Memory ; } } if ( Constraint == <STR_LIT> ) return C_Memory ;

return TargetLowering :: getConstraintType ( Constraint ) ;


<s> MVT Op0VT = Op0 . getValueType ( ) ; if ( Op0VT . getSimpleVT ( ) == <STR_LIT> && simpleVT == <STR_LIT> ) { unsigned maskHigh = <NUM_LIT> ; unsigned maskLow = <NUM_LIT> ;

SDValue shufMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( maskHigh , <STR_LIT> ) , DAG . getConstant ( maskLow , <STR_LIT> ) , DAG . getConstant ( maskHigh , <STR_LIT> ) , DAG . getConstant ( maskLow , <STR_LIT> ) ) ;


<s> Op -> Mem . Base = <NUM_LIT> ; Op -> Mem . IndexReg = <NUM_LIT> ; Op -> Mem . Index = Index ;


<s> return ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ;


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VT != <STR_LIT> || Subtarget . hasP8Altivec ( ) ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue X = Op . getOperand ( <NUM_LIT> ) ;

SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , VT ) ;


<s> if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ;


<s> <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( <STR_LIT> ) ; else { Register HighPartReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , HighPartReg ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; if ( Subtarget -> isGVIndirectSymbol ( GV ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addGlobalAddress ( GV ) . addReg ( HighPartReg ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( HighPartReg ) . addGlobalAddress ( GV ) ; } } return DestReg ;


<s> } if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( TT . length ( ) > <NUM_LIT> ) { size_t DarwinPos = TT . find ( <STR_LIT> ) ; if ( DarwinPos != std :: string :: npos ) { if ( isdigit ( TT [ DarwinPos + <NUM_LIT> ] ) ) DarwinVers = atoi ( & TT [ DarwinPos + <NUM_LIT> ] ) ; else DarwinVers = <NUM_LIT> ;


<s> static rtx h8300_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; static const char * const hand_list [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> , } ; rtx result = NULL_RTX ; const char * fname ;


<s> copyState ( <ISA_LIT>HazardRecognizer * Incoming ) { CurrGroupSize = Incoming -> CurrGroupSize ; DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ; CriticalResourceIdx = Incoming -> CriticalResourceIdx ; LastFPdOpCycleIdx = Incoming -> LastFPdOpCycleIdx ;


<s> break ; } case A2_andp : createHalfInstr ( A2_and , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_and , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_orp : createHalfInstr ( A2_or , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_or , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_xorp : createHalfInstr ( A2_xor , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_xor , MI , PairMap , isub_hi ) ; Split = true ; break ; case L2_loadrd_io : case L2_loadrd_pi : case S2_storerd_io : case S2_storerd_pi : splitMemRef ( MI , PairMap ) ; Split = true ; break ; case A2_tfrpi : case CONST64 : splitImmediate ( MI , PairMap ) ; Split = true ; break ; case A2_combineii : case A4_combineir : case A4_combineii : case A4_combineri : case A2_combinew : splitCombine ( MI , PairMap ) ; Split = true ; break ; case A2_sxtw : splitExt ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p : case S2_asr_i_p : case S2_lsr_i_p : splitShift ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p_or : splitAslOr ( MI , PairMap ) ; Split = true ; break ; default : llvm_unreachable ( <STR_LIT> ) ; return false ; }


<s> } else { assert ( BI -> isConditional ( ) && BI -> getNumSuccessors ( ) == <NUM_LIT> && <STR_LIT> ) ; Value * Cond = BI -> getCondition ( ) ; BasicBlock * TrueBlk = BI -> getSuccessor ( <NUM_LIT> ) ; BasicBlock * FalseBlk = BI -> getSuccessor ( <NUM_LIT> ) ; InsertPredicate ( TrueBlk , Cond ) ; InsertPredicate ( FalseBlk , Cond , <NUM_LIT> ) ; }


<s> unsigned HOST_WIDE_INT const2 = <NUM_LIT> ; if ( ! CONST_INT_P ( XEXP ( op0 , <NUM_LIT> ) ) ) return false ; const1 = UINTVAL ( XEXP ( op0 , <NUM_LIT> ) ) ; if ( ! CONST_INT_P ( XEXP ( op1 , <NUM_LIT> ) ) || ~ UINTVAL ( XEXP ( op1 , <NUM_LIT> ) ) != const1 ) return false ; if ( GET_CODE ( XEXP ( op0 , <NUM_LIT> ) ) == ASHIFT && CONST_INT_P ( XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ) ) { const2 = UINTVAL ( XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ) ; * sub0 = XEXP ( XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ; } else * sub0 = XEXP ( op0 , <NUM_LIT> ) ; if ( const2 >= GET_MODE_BITSIZE ( GET_MODE ( op0 ) ) ) return false ; * sub1 = XEXP ( op1 , <NUM_LIT> ) ;


<s> unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Mask = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> const MCBinaryExpr * Sub = MCBinaryExpr :: createSub ( Sym1 , Sym2 , * Ctx ) ; return MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( Kind , Sub , * Ctx ) ) ;


<s> if ( base_cost <= <NUM_LIT> ) base_cost = get_attr_length ( insn ) ; } pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) { set = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( set ) != SET || GET_CODE ( XEXP ( set , <NUM_LIT> ) ) == COMPARE ) set = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( set ) != SET || GET_CODE ( XEXP ( set , <NUM_LIT> ) ) == COMPARE ) return <NUM_LIT> ; } else { set = pat ; if ( GET_CODE ( set ) != SET ) return <NUM_LIT> ; } dest = XEXP ( set , <NUM_LIT> ) ; src = XEXP ( set , <NUM_LIT> ) ; mode = GET_MODE ( dest ) ; base_cost += pdp11_addr_cost ( dest , mode , ADDR_SPACE_GENERIC , speed ) ; op = GET_CODE ( src ) ;


<s> bool SeenDef = false ; for ( unsigned j = <NUM_LIT> , e = Iter -> getNumOperands ( ) ; j != e ; ++ j ) { MachineOperand & MO = Iter -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { if ( MO . isUse ( ) ) return false ; SeenDef = true ; } } if ( SeenDef ) return true ; ++ Iter ; while ( Iter != E && Iter -> isDebugValue ( ) ) ++ Iter ; } if ( Iter == E ) { for ( MachineBasicBlock :: succ_iterator SI = MBB . succ_begin ( ) , SE = MBB . succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; return true ; } MachineBasicBlock :: iterator B = MBB . begin ( ) ; Iter = I ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Iter == B ) return ! MBB . isLiveIn ( <STR_LIT> ) ; -- Iter ; while ( Iter != B && Iter -> isDebugValue ( ) ) -- Iter ;


<s> Thumb1InstrInfo :: Thumb1InstrInfo ( const <ISA_LIT>Subtarget & STI ) : RI ( * this , STI ) {


<s> unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( is32Bit ) return MCDisassembler :: Fail ; status = DecodeDataRegsRegisterClass ( Inst , s1_d , Address , Decoder ) ; if ( status == MCDisassembler :: Success ) status = DecodeDataRegsRegisterClass ( Inst , s1_d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; return MCDisassembler :: Success ;


<s> unsigned NumElts = VecVTy -> getNumElements ( ) ; auto * SubVecTy = FixedVectorType :: get ( VecTy -> getScalarType ( ) , NumElts / Factor ) ; if ( NumElts % Factor == <NUM_LIT> && TLI -> isLegalInterleavedAccessType ( SubVecTy , DL ) ) return Factor * TLI -> getNumInterleavedAccesses ( SubVecTy , DL ) ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ;


<s> static MCRelocationInfo * create<ISA_LIT>ElfRelocation ( const Triple & TheTriple , MCContext & Ctx ) { return createMCRelocationInfo ( TheTriple , Ctx ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; EVT OpVT = Op . getValueType ( ) ; if ( ! OpVT . is128BitVector ( ) ) { EVT VT128 = EVT :: getVectorVT ( * Context , OpVT . getVectorElementType ( ) , OpVT . getVectorNumElements ( ) / <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT128 , Op . getOperand ( <NUM_LIT> ) ) ; return Insert128BitVector ( DAG . getUNDEF ( OpVT ) , Op , <NUM_LIT> , DAG , dl ) ; } if ( OpVT == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;

SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd5 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPREven6 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned GPROdd6 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( RC != <STR_LIT> && RC != <STR_LIT> ) return RC -> getRawAllocationOrder ( MF ) ; if ( HintType == <STR_LIT> ) { if ( isPhysicalRegister ( HintReg ) && getRegisterPairEven ( HintReg , MF ) == <NUM_LIT> ) return RC -> getRawAllocationOrder ( MF ) ; if ( ! TFI -> hasFP ( MF ) ) { if ( ! STI . isR9Reserved ( ) ) return makeArrayRef ( GPREven1 ) ; else return makeArrayRef ( GPREven4 ) ; } else if ( FramePtr == <STR_LIT> ) { if ( ! STI . isR9Reserved ( ) ) return makeArrayRef ( GPREven2 ) ; else return makeArrayRef ( GPREven5 ) ; } else { if ( ! STI . isR9Reserved ( ) ) return makeArrayRef ( GPREven3 ) ; else return makeArrayRef ( GPREven6 ) ; } } else if ( HintType == <STR_LIT> ) { if ( isPhysicalRegister ( HintReg ) && getRegisterPairOdd ( HintReg , MF ) == <NUM_LIT> ) return RC -> getRawAllocationOrder ( MF ) ; if ( ! TFI -> hasFP ( MF ) ) { if ( ! STI . isR9Reserved ( ) ) return makeArrayRef ( GPROdd1 ) ; else return makeArrayRef ( GPROdd4 ) ;


<s> <ISA_LIT>ELFWriterInfo :: ~ <ISA_LIT>ELFWriterInfo ( ) {


<s> bool FoldAsMAD = tryAddToFoldList ( FoldList , MI , OpNo , OpToFold , TII ) ; if ( FoldAsMAD ) { MI -> untieRegOperand ( OpNo ) ; return true ; } MI -> setDesc ( TII -> get ( Opc ) ) ; } if ( Opc == <STR_LIT> && OpToFold -> isImm ( ) ) { MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; FoldList . push_back ( FoldCandidate ( MI , OpNo , OpToFold ) ) ; return true ; } if ( isUseMIInFoldList ( FoldList , MI ) ) return false ; unsigned CommuteOpNo = OpNo ; unsigned CommuteIdx0 = TargetInstrInfo :: CommuteAnyOperandIndex ; unsigned CommuteIdx1 = TargetInstrInfo :: CommuteAnyOperandIndex ; bool CanCommute = TII -> findCommutedOpIndices ( * MI , CommuteIdx0 , CommuteIdx1 ) ; if ( CanCommute ) { if ( CommuteIdx0 == OpNo ) CommuteOpNo = CommuteIdx1 ; else if ( CommuteIdx1 == OpNo ) CommuteOpNo = CommuteIdx0 ; } if ( CanCommute && ( ! MI -> getOperand ( CommuteIdx0 ) . isReg ( ) || ! MI -> getOperand ( CommuteIdx1 ) . isReg ( ) ) ) return false ; if ( ! CanCommute || ! TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ) return false ;

if ( ! TII -> isOperandLegal ( * MI , CommuteOpNo , OpToFold ) ) {


<s> <ISA_LIT>ConstantIslands ( ) : MachineFunctionPass ( ID ) {


<s> NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; assert ( ! Src . isUndef ( ) && <STR_LIT> ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ;

MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . add ( Src ) ;


<s> case CONST_VECTOR : { * special = SH_CONST_VECTOR ; return <NUM_LIT> ; } case VEC_DUPLICATE : if ( CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; else if ( REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_MODE_INNER ( GET_MODE ( op ) ) == GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == TRUNCATE && REG_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) && GET_MODE_INNER ( GET_MODE ( op ) ) == GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) return <NUM_LIT> ; else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == VEC_SELECT ) return rtx_is_swappable_p ( XEXP ( op , <NUM_LIT> ) , special ) ; else return <NUM_LIT> ; case VEC_SELECT : if ( REG_P ( XEXP ( op , <NUM_LIT> ) ) && GET_MODE_INNER ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) == GET_MODE ( op ) && GET_CODE ( ( parallel = XEXP ( op , <NUM_LIT> ) ) ) == PARALLEL && XVECLEN ( parallel , <NUM_LIT> ) == <NUM_LIT> && CONST_INT_P ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) ) { * special = SH_EXTRACT ; return <NUM_LIT> ; } else if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == VEC_CONCAT && ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == V4DFmode || GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == V4DImode ) && GET_CODE ( ( parallel = XEXP ( op , <NUM_LIT> ) ) ) == PARALLEL && XVECLEN ( parallel , <NUM_LIT> ) == <NUM_LIT> && CONST_INT_P ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) && CONST_INT_P ( XVECEXP ( parallel , <NUM_LIT> , <NUM_LIT> ) ) ) { * special = SH_XXPERMDI ; return <NUM_LIT> ; } else if ( v2df_reduction_p ( op ) ) return <NUM_LIT> ; else return <NUM_LIT> ; case UNSPEC : { int val = XINT ( op , <NUM_LIT> ) ; switch ( val ) { default : break ;


<s> MachineBasicBlock * MBB = BA . Addr -> getCode ( ) ; for ( auto SB : MBB -> successors ( ) ) { auto SBA = Func . Addr -> findBlock ( SB , * this ) ; for ( NodeAddr < InstrNode * > IA : SBA . Addr -> members_if ( IsPhi , * this ) ) { for ( auto U : IA . Addr -> members_if ( IsUseForBA , * this ) ) { NodeAddr < PhiUseNode * > PUA = U ; RegisterRef RR = PUA . Addr -> getRegRef ( ) ;

linkRefUp < UseNode * > ( IA , PUA , DefM [ RR ] ) ;


<s> return for_each_rtx ( & op , mips_small_data_pattern_1 , <NUM_LIT> ) ;


<s> return ( StackSize / <NUM_LIT> ) << <NUM_LIT> ;


<s> else return <NUM_LIT> ; case ADDRESS_CONST_INT : if ( SMALL_INT ( x ) ) return <NUM_LIT> ; else return <NUM_LIT> ; case ADDRESS_REG_INDEX : return <NUM_LIT> ; case ADDRESS_SYMBOLIC : case ADDRESS_SYMBOLIC_TXT_REL : case ADDRESS_GOTOFF : return <NUM_LIT> ; case ADDRESS_TLS :


<s> if ( isRegPair ( Reg ) ) getSubRegs ( Reg , Set ) ; else Set [ Reg ] = true ;


<s> if ( TARGET_16BIT ) fputs ( <STR_LIT> , asm_out_file ) ; darwin_file_start ( ) ; if ( X86_FILE_START_VERSION_DIRECTIVE ) fputs ( <STR_LIT> , asm_out_file ) ; if ( X86_FILE_START_FLTUSED ) fputs ( <STR_LIT> , asm_out_file ) ; if ( ix86_asm_dialect == ASM_INTEL ) fputs ( <STR_LIT> , asm_out_file ) ;


<s> ClusterDAG :: ~ ClusterDAG ( ) { for ( std :: vector < SUnit * > :: iterator I = CopySUs . begin ( ) , E = CopySUs . end ( ) ; I != E ; ++ I ) delete * I ;


<s> ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; if ( const char * bzeroEntry = V && V -> isNullValue ( ) ? Subtarget . getBZeroEntry ( ) : nullptr ) { EVT IntPtr = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = DAG . getTargetLoweringInfo ( ) . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; SDValue InFlag ; EVT AVT ; SDValue Count ; ConstantSDNode * ValC = dyn_cast < ConstantSDNode > ( Src ) ; unsigned BytesLeft = <NUM_LIT> ; bool TwoRepStos = false ; if ( ValC ) { unsigned ValReg ; uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; switch ( Align & <NUM_LIT> ) { case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; break ; case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ;


<s> if ( InstMaskEnd == <NUM_LIT> - RLAmt ) { SDValue Ops [ ] = { ExtendToInt64 ( Base , dl ) , ExtendToInt64 ( V , dl ) , getI32Imm ( RLAmt , dl ) , getI32Imm ( InstMaskStart , dl ) } ; return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } if ( InstCnt ) * InstCnt += <NUM_LIT> ; unsigned RLAmt2 = MaskStart ;

unsigned RLAmt1 = ( <NUM_LIT> + RLAmt - RLAmt2 ) % <NUM_LIT> ;


<s> unsigned FinalDstReg = <STR_LIT> ; unsigned DstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool Is32Bit = isInt < <NUM_LIT> > ( ImmValue ) || isUInt < <NUM_LIT> > ( ImmValue ) ; unsigned FinalOpcode = Inst . getOpcode ( ) ; if ( DstReg == SrcReg ) { ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; FinalDstReg = DstReg ; DstReg = ATReg ; } if ( ! loadImmediate ( ImmValue , DstReg , <STR_LIT> , Is32Bit , false , Inst . getLoc ( ) , Instructions ) ) { switch ( FinalOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ; break ; case ( <STR_LIT> ) : FinalOpcode = <STR_LIT> ;


<s> std :: string FullFS = FS ; if ( OptLevel >= CodeGenOpt :: Default ) {

if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isValidForTie ( static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ) ) return Match_Success ;


<s> unsigned Kind ; unsigned ErrorInfo ; SmallVector < std :: pair < unsigned , std :: string > , <NUM_LIT> > MapAndConstraints ; switch ( MatchInstructionImpl ( Operands , Kind , Inst , MapAndConstraints , ErrorInfo , false ) ) { default : break ; case Match_Success : Out . EmitInstruction ( Inst ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ;


<s> for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) {


<s> O << <STR_LIT> ; printMemReference ( MI , OpNo , O ) ;


<s> HasHazard |= RegDU . update ( Candidate , <NUM_LIT> , Candidate . getNumOperands ( ) ) ; return HasHazard ;


<s> } if ( regno <= <NUM_LIT> ) return regno ; if ( FP_REGNO_P ( regno ) ) return regno - FIRST_FPR_REGNO + <NUM_LIT> ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + <NUM_LIT> ; if ( regno == LR_REGNO ) return <NUM_LIT> ; if ( regno == CTR_REGNO ) return <NUM_LIT> ; if ( regno == CA_REGNO ) return <NUM_LIT> ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + <NUM_LIT> ; if ( regno == VRSAVE_REGNO ) return <NUM_LIT> ; if ( regno == VSCR_REGNO ) return <NUM_LIT> ; if ( regno == FRAME_POINTER_REGNUM ) return <NUM_LIT> ; if ( regno == ARG_POINTER_REGNUM ) return <NUM_LIT> ;

if ( regno == <NUM_LIT> ) return <NUM_LIT> ;


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ;


<s> bool R600InstrInfo :: usesAddressRegister ( MachineInstr * MI ) const {

return MI -> findRegisterUseOperandIdx ( AMDGPU :: AR_X ) != - <NUM_LIT> ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> StringRef getPassName ( ) const override {


<s> const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ;

const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ;


<s> static MCDisassembler * create<ISA_LIT>_64Disassembler ( const Target & T , const MCSubtargetInfo & STI ) { return new <ISA_LIT>Disassembler :: <ISA_LIT>GenericDisassembler ( STI , MODE_64BIT ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateFPImm ( unsigned Val , SMLoc S , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_FPImm , Ctx ) ; Op -> FPImm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op ;


<s> default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_AGPR ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } }


<s> unsigned LMul = <NUM_LIT> << static_cast < unsigned > ( VLMUL ) ; OS << <STR_LIT> << LMul ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned LMul = <NUM_LIT> << ( <NUM_LIT> - static_cast < unsigned > ( VLMUL ) ) ; OS << <STR_LIT> << LMul ;


<s> return Create ( VK_AARCH64_ABS_G3 , Expr , Ctx ) ;


<s> auto & Func = MF . getFunction ( ) ; auto Kern = getHSAKernelProps ( MF , ProgramInfo ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; assert ( Func . getCallingConv ( ) == CallingConv :: <ISA_LIT>_KERNEL || Func . getCallingConv ( ) == CallingConv :: SPIR_KERNEL ) ; auto Kernels = getRootMetadata ( <STR_LIT> ) . getArray ( true ) ; { Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( Func . getName ( ) ) ;

Kern [ <STR_LIT> ] = Kern . getDocument ( ) -> getNode ( ( Twine ( Func . getName ( ) ) + Twine ( <STR_LIT> ) ) . str ( ) , true ) ;


<s> TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterELFStreamer ( getThe<ISA_LIT>Target ( ) , createMCStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Target ( ) , createMCAsmTargetStreamer ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {

const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | MO_NC ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ; } else if ( TM . getCodeModel ( ) == CodeModel :: Tiny ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags ) ; } else { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags | <STR_LIT> ) ; unsigned char LoFlags = OpFlags | <STR_LIT> | MO_NC ; if ( Subtarget . isTargetILP32 ( ) ) { unsigned Reg32 = TRI -> getSubReg ( Reg , <STR_LIT> ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addDef ( Reg32 , RegState :: Dead ) . addUse ( Reg , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , LoFlags ) . addMemOperand ( * MI . memoperands_begin ( ) ) . addDef ( Reg , RegState :: Implicit ) ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) {


<s> bool <ISA_LIT>TargetLowering :: isHWFalseValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> getValueAPF ( ) . isZero ( ) ;