<s> if ( KindA == NodeAttrs :: Use && KindB == NodeAttrs :: Def ) return true ; if ( KindA == NodeAttrs :: Def && KindB == NodeAttrs :: Use ) return false ; return A . Id < B . Id ; } ; llvm :: sort ( DRNs , UsesFirst ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> ; for ( NodeAddr < RefNode * > RA : DRNs ) { if ( trace ( ) ) dbgs ( ) << <STR_LIT> << PrintNode < RefNode * > ( RA , DFG ) << '\n' ; if ( DFG . IsUse ( RA ) ) DFG . unlinkUse ( RA , true ) ; else if ( DFG . IsDef ( RA ) ) DFG . unlinkDef ( RA , true ) ; } for ( NodeAddr < InstrNode * > IA : DINs ) { NodeAddr < BlockNode * > BA = IA . Addr -> getOwner ( DFG ) ; BA . Addr -> removeMember ( IA , DFG ) ; if ( ! DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) continue ; MachineInstr * MI = NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> << * MI ;


<s> SDValue InpVal = Op . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( InpVal ) ) { uint64_t V = cast < ConstantSDNode > ( InpVal ) -> getZExtValue ( ) ; return DAG . getTargetConstant ( countPopulation ( V ) , dl , <STR_LIT> ) ; }

SDValue PopOut = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InpVal ) ;


<s> static nodes_iterator nodes_begin ( const GraphType & G ) {


<s> Base = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N . getNode ( ) ) , N . getValueType ( ) , Base , OffImm ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>Subtarget & st , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( st ) , TII ( tii ) {


<s> assert ( IsUnscaled == TII -> isUnscaledLdSt ( * StoreI ) && <STR_LIT> ) ; assert ( LoadSize <= StoreSize && <STR_LIT> ) ; int UnscaledLdOffset = IsUnscaled ? getLdStOffsetOp ( * LoadI ) . getImm ( ) : getLdStOffsetOp ( * LoadI ) . getImm ( ) * LoadSize ; int UnscaledStOffset = IsUnscaled ? getLdStOffsetOp ( * StoreI ) . getImm ( ) : getLdStOffsetOp ( * StoreI ) . getImm ( ) * StoreSize ; int Width = LoadSize * <NUM_LIT> ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; unsigned DestReg = IsStoreXReg ? TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt , TRI ) ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> explicit <ISA_LIT>DeadRegisterDefinitions ( ) : MachineFunctionPass ( ID ) {


<s> Info . True = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Info . False = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! ( Info . LHS == Info . True && Info . RHS == Info . False ) && ! ( Info . LHS == Info . False && Info . RHS == Info . True ) ) return false ; switch ( Info . Pred ) { case CmpInst :: FCMP_FALSE :


<s> if ( ! riscv_split_symbol_type ( sym_type ) ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ( ! TARGET_STRICT_ALIGN || GET_MODE_BITSIZE ( mode ) > GET_MODE_ALIGNMENT ( mode ) ) ) return false ; return true ;


<s> insn_length = get_attr_length ( insn ) ; long_jump_p = ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ? true : false ; r5_p = ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ? true : false ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ;


<s> assert ( ! SU -> NumPredsLeft ) ; std :: vector < SUnit * > :: iterator I = llvm :: find ( TopReadySUs , SU ) ; if ( I == TopReadySUs . end ( ) ) { dbgs ( ) << <STR_LIT> ; llvm_unreachable ( nullptr ) ; } TopReadySUs . erase ( I ) ; releaseSuccessors ( SU , true ) ; if ( HasLowLatencyNonWaitedParent [ NodeNum2Index [ SU -> NodeNum ] ] ) HasLowLatencyNonWaitedParent . assign ( SUnits . size ( ) , <NUM_LIT> ) ; if ( DAG -> IsLowLatencySU [ SU -> NodeNum ] ) { for ( SDep & Succ : SU -> Succs ) { std :: map < unsigned , unsigned > :: iterator I = NodeNum2Index . find ( Succ . getSUnit ( ) -> NodeNum ) ; if ( I != NodeNum2Index . end ( ) ) HasLowLatencyNonWaitedParent [ I -> second ] = <NUM_LIT> ; }


<s> rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk ) ) ; if ( aarch64_bti_enabled ( ) ) emit_insn ( gen_bti_c ( ) ) ; reload_completed = <NUM_LIT> ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , EP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , EP1_REGNUM ) ; if ( vcall_offset == <NUM_LIT> ) aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - <NUM_LIT> ) ) == <NUM_LIT> ) ; addr = this_rtx ; if ( delta != <NUM_LIT> ) { if ( delta >= - <NUM_LIT> && delta < <NUM_LIT> ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_offset ( Pmode , this_rtx , this_rtx , delta , temp1 , temp0 , false ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - <NUM_LIT> && vcall_offset < <NUM_LIT> * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ;

funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ;


<s> void <ISA_LIT>Subtarget :: SetJITMode ( ) {


<s> bool Clone = true ; unsigned Opc = Orig -> getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { switch ( Opc ) { default : break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; }


<s> bool nds32_n7_last_load_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { if ( post_update_insn_p ( producer ) ) return false ; rtx last_def_reg = extract_nth_access_reg ( producer , - <NUM_LIT> ) ; if ( last_def_reg == NULL_RTX ) return false ;

gcc_assert ( REG_P ( last_def_reg ) || GET_CODE ( last_def_reg ) == SUBREG ) ;


<s> static std :: string computeDataLayout ( const Triple & TT ) { if ( TT . isArch64Bit ( ) ) return <STR_LIT> ; assert ( TT . isArch32Bit ( ) && <STR_LIT> ) ;


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && isWorthFoldingADDlow ( N ) ) { GlobalAddressSDNode * GAN = dyn_cast < GlobalAddressSDNode > ( N . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Base = N . getOperand ( <NUM_LIT> ) ; OffImm = N . getOperand ( <NUM_LIT> ) ; if ( ! GAN ) return true ; const GlobalValue * GV = GAN -> getGlobal ( ) ; unsigned Alignment = GV -> getAlignment ( ) ; const DataLayout * DL = TLI -> getDataLayout ( ) ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; if ( Alignment == <NUM_LIT> && Ty -> isSized ( ) ) Alignment = DL -> getABITypeAlignment ( Ty ) ; if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ;

Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ;


<s> <ISA_LIT>GenericDisassembler :: ~ <ISA_LIT>GenericDisassembler ( ) {


<s> unsigned NumOps = Desc . getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) CurOp += <NUM_LIT> ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> && Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) CurOp += <NUM_LIT> ;

else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ;


<s> rtx rhs = SET_SRC ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) ; if ( GET_CODE ( rhs ) == UNSPEC && XINT ( rhs , <NUM_LIT> ) == UNSPEC_PIC_BASE ) return TRUE ;

if ( GET_CODE ( rhs ) == MEM && GET_CODE ( XEXP ( rhs , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( rhs , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_PIC_BASE ) return TRUE ;


<s> <ISA_LIT>Operand & Operand = static_cast < <ISA_LIT>Operand & > ( * Operands . front ( ) ) ; StartLoc = Operand . getStartLoc ( ) ; EndLoc = Operand . getEndLoc ( ) ; return false ;


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : Results . push_back ( DAG . getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> else if ( TARGET_EMBEDDED_DATA ) { mergeable_constant_section ( mode , align , <NUM_LIT> ) ; } else {

if ( GET_MODE_SIZE ( mode ) <= ( unsigned ) mips_section_threshold && mips_section_threshold > <NUM_LIT> ) named_section ( <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( Imm + <NUM_LIT> ) ) ; return Success ;


<s> bool isPICBase = false ; for ( MachineRegisterInfo :: def_instr_iterator I = MRI . def_instr_begin ( BaseReg ) , E = MRI . def_instr_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = & * I ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase && <STR_LIT> ) ;


<s> const uint32_t UB = getScoreUB ( T ) ; if ( Count < UB && UB - Count > LB ) return true ; Count = ~ <NUM_LIT> ;


<s> static bool ia64_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) && ( ( mode1 == XFmode || mode1 == XCmode || mode1 == RFmode ) == ( mode2 == XFmode || mode2 == XCmode || mode2 == RFmode ) ) && ( mode1 == BImode ) == ( mode2 == BImode ) ) ;


<s> } Defs . clear ( ) ; Uses . clear ( ) ; TrackDefUses ( MI , Defs , Uses , TRI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; MachineInstr * LastITMI = MI ; MachineBasicBlock :: iterator InsertPos = MIB ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = llvm :: getITInstrPredicate ( NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else {

if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) {


<s> unsigned R = I . first ; if ( isLoopRegister ( R ) && Defs . count ( R ) > <NUM_LIT> && ( <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCB ) || <ISA_LIT>MCInstrInfo :: isOuterLoop ( MCB ) ) ) { reportError ( <STR_LIT> <STR_LIT> ) ; return false ; } if ( SoftDefs . count ( R ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; reportErrorRegisters ( BadR ) ; return false ; } if ( ! <ISA_LIT>MCInstrInfo :: isPredReg ( RI , R ) && Defs [ R ] . size ( ) > <NUM_LIT> ) { PredSet & PM = Defs [ R ] ; if ( PM . count ( Unconditional ) ) { unsigned UsrR = <STR_LIT> ; unsigned BadR = RI . isSubRegister ( <STR_LIT> , R ) ? UsrR : R ; reportErrorRegisters ( BadR ) ; return false ; } for ( const auto & J : PM ) { PredSense P = J ; if ( PM . count ( P ) > <NUM_LIT> ) { reportErrorRegisters ( R ) ; return false ; } P . second = ! P . second ; if ( PM . count ( P ) && PM . size ( ) > <NUM_LIT> ) { reportErrorRegisters ( R ) ;


<s> <ISA_LIT>Symbolizer ( MCContext & Ctx , std :: unique_ptr < MCRelocationInfo > && RelInfo , void * disInfo ) : MCSymbolizer ( Ctx , std :: move ( RelInfo ) ) , DisInfo ( disInfo ) {


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { unsigned Reg = I . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } else { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;

TII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , I . getFrameIdx ( ) , RC , TRI ) ;


<s> rtx x1 , x2 ; if ( mips_split_64bit_move_p ( mem , reg ) ) mips_split_64bit_move ( mem , reg ) ; else emit_move_insn ( mem , reg ) ; x1 = mips_frame_set ( mips_subword ( mem , <NUM_LIT> ) , mips_subword ( reg , <NUM_LIT> ) ) ; x2 = mips_frame_set ( mips_subword ( mem , <NUM_LIT> ) , mips_subword ( reg , <NUM_LIT> ) ) ; mips_set_frame_expr ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , x1 , x2 ) ) ) ;


<s> uint64_t op2 = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t crm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t pstate_field = ( op1 << <NUM_LIT> ) | op2 ; Inst . addOperand ( MCOperand :: createImm ( pstate_field ) ) ; Inst . addOperand ( MCOperand :: createImm ( crm ) ) ;


<s> const <ISA_LIT>SelectionDAGInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> static inline <ISA_LIT>TargetStreamer :: SymbolIndex getTombstoneKey ( ) {

return { nullptr , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid } ;


<s> virtual ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const { return createVLIWMachineSched ( C ) ;


<s> unsigned TmpReg = MRI -> createVirtualRegister ( PS -> RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , TmpReg ) . addReg ( <STR_LIT> ) ; auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , PredStateReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( TRI -> getRegSizeInBits ( * PS -> RC ) - <NUM_LIT> ) ; ShiftI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted ;


<s> bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . isUndef ( ) ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) NonConstIdx . push_back ( idx ) ; else { Immediate |= cast < ConstantSDNode > ( In ) -> getZExtValue ( ) << idx ; HasConstElts = true ; } if ( SplatIdx == - <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( SplatIdx ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; SDValue DstVec ; SDValue Imm ; if ( Immediate ) { MVT ImmVT = <STR_LIT> ( std :: max ( ( int ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; }

else if ( HasConstElts ) Imm = DAG . getConstant ( <NUM_LIT> , dl , VT ) ;


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const {

if ( DarwinDirective == <STR_LIT> || DarwinDirective == <STR_LIT> ) Mode = TargetSubtargetInfo :: ANTIDEP_ALL ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU , bool isLittle ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MachO :: CPUSubType<ISA_LIT> CS = StringSwitch < MachO :: CPUSubType<ISA_LIT> > ( TheTriple . getArchName ( ) ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V4T ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V5TEJ ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6 ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V6M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7EM ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7K ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7M ) . Cases ( <STR_LIT> , <STR_LIT> , MachO :: CPU_SUBTYPE_<ISA_LIT>_V7S ) . Default ( MachO :: CPU_SUBTYPE_<ISA_LIT>_V7 ) ; return new Darwin<ISA_LIT>AsmBackend ( T , TT , CS ) ; }


<s> unsigned Width0 = ( * MIa . memoperands_begin ( ) ) -> getSize ( ) ; unsigned Width1 = ( * MIb . memoperands_begin ( ) ) -> getSize ( ) ; if ( offsetsDoNotOverlap ( Width0 , Offset0 , Width1 , Offset1 ) ) { return true ;


<s> static void emitNonLazySymbolPointer ( MCStreamer & OutStreamer , MCSymbol * StubLabel , MachineModuleInfoImpl :: StubValueTy & MCSym ) { OutStreamer . emitLabel ( StubLabel ) ; OutStreamer . emitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;

else OutStreamer . emitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutStreamer . getContext ( ) ) , <NUM_LIT> ) ;


<s> static void pa_output_function_prologue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { ASM_OUTPUT_LABEL ( file , XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , file ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , actual_fsize ) ; if ( crtl -> is_leaf ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; if ( rp_saved ) fputs ( <STR_LIT> , file ) ; if ( frame_pointer_needed ) fputs ( <STR_LIT> , file ) ; if ( gr_saved ) fprintf ( file , <STR_LIT> , gr_saved + <NUM_LIT> ) ;

if ( fr_saved ) fprintf ( file , <STR_LIT> , fr_saved + <NUM_LIT> ) ;


<s> switch ( MI -> getDesc ( ) . getOpcode ( ) ) { default :


<s> MachineInstr * MI = & * It ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstHi = HRI . getSubReg ( DstR , <STR_LIT> ) ; unsigned DstLo = HRI . getSubReg ( DstR , <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && <STR_LIT> ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool Is128B = HST . useHVXDblOps ( ) ; auto * RC = ! Is128B ? & <STR_LIT> : & <STR_LIT> ; unsigned Size = RC -> getSize ( ) ; unsigned NeedAlign = RC -> getAlignment ( ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned LoadOpc ; if ( NeedAlign <= HasAlign ) LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ;

else LoadOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr * MIa , MachineInstr * MIb , AliasAnalysis * AA ) const { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; assert ( MIa && MIa -> mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb && MIb -> mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( getLdStBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getLdStBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB ) { int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; } } return false ;


<s> if ( Op . isImm ( ) ) O << formatImm ( Op . getImm ( ) ) ; else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> EVT VT = Op . getValueType ( ) ; SDValue ff1 = DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , ff1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( TARGET_AM33 || mode1 == mode2 || ( GET_MODE_SIZE ( mode1 ) <= <NUM_LIT> && GET_MODE_SIZE ( mode2 ) <= <NUM_LIT> ) ) return true ; return false ;


<s> while ( ! getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { OperandMode Mode = OperandMode_Default ; if ( IsMIMG && isGFX10 ( ) && Operands . size ( ) == <NUM_LIT> ) Mode = OperandMode_NSA ; OperandMatchResultTy Res = parseOperand ( Operands , Name , Mode ) ; if ( getLexer ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ; switch ( Res ) { case MatchOperand_Success : break ; case MatchOperand_ParseFail : Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; while ( ! getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { Parser . Lex ( ) ; } return true ; case MatchOperand_NoMatch : Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; while ( ! getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { Parser . Lex ( ) ; } return true ; } }


<s> static SDValue performSRACombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { EVT Ty = N -> getValueType ( <NUM_LIT> ) ; if ( ( Ty != <STR_LIT> ) && ( ( Ty != <STR_LIT> ) || ! Subtarget -> hasDSPR2 ( ) ) ) return SDValue ( ) ; return performDSPShiftCombine ( <STR_LIT> , N , Ty , DAG , Subtarget ) ;


<s> return <STR_LIT> ; case GT : return <STR_LIT> ; case GTU : return <STR_LIT> ; case LT : return <STR_LIT> ; case LTU : return <STR_LIT> ; case GE : return <STR_LIT> ; case GEU : return <STR_LIT> ; case LE : return <STR_LIT> ;


<s> case <STR_LIT> : assert ( ( Subtarget . systemSupportsUnalignedAccess ( ) || cast < MemSDNode > ( Node ) -> getMemoryVT ( ) . getSizeInBits ( ) / <NUM_LIT> <= cast < MemSDNode > ( Node ) -> getAlignment ( ) ) && <STR_LIT> ) ; break ; } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( ResNode == nullptr || ResNode == Node ) DEBUG ( Node -> dump ( CurDAG ) ) ; else DEBUG ( ResNode -> dump ( CurDAG ) ) ;


<s> TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> if ( M . getModuleFlag ( <STR_LIT> ) ) FeatureFlagsAnd |= ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_SHSTK ; if ( FeatureFlagsAnd ) { if ( ! TT . isArch32Bit ( ) && ! TT . isArch64Bit ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; int WordSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; EmitAlignment ( WordSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( FeatureFlagsAnd , <NUM_LIT> ) ; EmitAlignment ( WordSize == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ;


<s> Op -> VectorIndex . Val = Idx ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> AM . BaseType = <ISA_LIT>ISelAddressMode :: RegBase ; AM . Base . Reg = N ; return false ;


<s> } } ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI -> getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ;

if ( ! TII . isLegalFLATOffset ( Offset . getValue ( ) , AddrSpace , Signed ) ) return Default ;


<s> void CastHandler :: ProcessFunction ( ) { LLVMContext & Cxt = Func -> getContext ( ) ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ;

TargetIdxTy = GetTargetIndexType ( DL , Cxt ) ;


<s> if ( Name == <STR_LIT> ) { enableArchExtFeature ( <STR_LIT> , ExtLoc ) ; enableArchExtFeature ( <STR_LIT> , ExtLoc ) ; } if ( enableArchExtFeature ( Name , ExtLoc ) ) return false ; return Error ( ExtLoc , <STR_LIT> + Name ) ;


<s> } if ( EltSizeInBytes != <NUM_LIT> ) { unsigned LaneTmp1 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( ShiftOp ) , LaneTmp1 ) . addReg ( LaneReg ) . addImm ( EltLog2Size ) ; LaneReg = LaneTmp1 ; } unsigned WdTmp1 = RegInfo . createVirtualRegister ( VecRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , WdTmp1 ) . addReg ( SrcVecReg ) . addReg ( SrcVecReg ) . addReg ( LaneReg , <NUM_LIT> , SubRegIdx ) ; unsigned WdTmp2 = RegInfo . createVirtualRegister ( VecRC ) ; if ( IsFP ) { BuildMI ( * BB , MI , DL , TII -> get ( InsveOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addImm ( <NUM_LIT> ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * BB , MI , DL , TII -> get ( InsertOp ) , WdTmp2 ) . addReg ( WdTmp1 ) . addReg ( SrcValReg ) . addImm ( <NUM_LIT> ) ; } unsigned LaneTmp2 = RegInfo . createVirtualRegister ( GPRRC ) ; BuildMI ( * BB , MI , DL , TII -> get ( Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ) , LaneTmp2 ) . addReg ( Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ) . addReg ( LaneReg ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( WdTmp2 ) . addReg ( WdTmp2 ) . addReg ( LaneTmp2 , <NUM_LIT> , SubRegIdx ) ; MI -> eraseFromParent ( ) ;


<s> bool R600InstrInfo :: isTransOnly ( unsigned Opcode ) const { return ( get ( Opcode ) . TSFlags & <STR_LIT> ) ;


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) return <STR_LIT> ; else return <STR_LIT> ; } else { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) return <STR_LIT> ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) {

SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM ) , DL ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ) :


<s> cond_code = GET_CODE ( condition_rtx ) ; cr = XEXP ( condition_rtx , <NUM_LIT> ) ; signedp = GET_MODE ( cr ) == CCmode ; isel_func = ( mode == SImode ? ( signedp ? gen_isel_cc_si : gen_isel_ccuns_si ) : ( signedp ? gen_isel_cc_di : gen_isel_ccuns_di ) ) ; switch ( cond_code ) { case LT : case GT : case LTU : case GTU : case EQ : break ; default : { std :: swap ( false_cond , true_cond ) ; PUT_CODE ( condition_rtx , reverse_condition ( cond_code ) ) ; } break ;


<s> if ( ! T ) return false ; KnownBits Known ( T -> getBitWidth ( ) ) ;


<s> ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeSet :: ReturnIndex , DL , F ) ; FuncReturnHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ;

return handleAssignments ( MIRBuilder , AssignFn , RetInfo , RetHandler ) ;


<s> int32_t Imm = MI -> getOperand ( OpNo ) . getImm ( ) ;

O << Imm << '(' << BitsToFloat ( Imm ) << ')' ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) , TSInfo ( * TM . getDataLayout ( ) ) {


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * QFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDValue Addr = DAG . getFrameIndex ( QFI -> getVarArgsFrameIndex ( ) , <STR_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Addr , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> void pa_asm_output_aligned_local ( FILE * stream , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { switch_to_section ( bss_section ) ; fprintf ( stream , <STR_LIT> , align / BITS_PER_UNIT ) ; fprintf ( stream , <STR_LIT> , LOCAL_ASM_OP ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> ) ;


<s> case <STR_LIT> : { if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( NewInt ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isSVR4ABI ( ) || TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue NewNode = LowerVAARG ( SDValue ( N , <NUM_LIT> ) , DAG , <ISA_LIT>SubTarget ) ; Results . push_back ( NewNode ) ; Results . push_back ( NewNode . getValue ( <NUM_LIT> ) ) ; } return ; } case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue FPreg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPreg , FPreg ) ) ; return ; } case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return ; Results . push_back ( LowerFP_TO_INT ( SDValue ( N , <NUM_LIT> ) , DAG , dl ) ) ; return ; }


<s> unsigned IndirectBaseReg = <STR_LIT> . getRegister ( getIndirectIndexBegin ( * MBB -> getParent ( ) ) ) ;

return BuildMI ( * MBB , I , DL , get ( <STR_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg ) . addImm ( <NUM_LIT> ) ;


<s> Instruction * MVEGatherScatterLowering :: tryCreateMaskedGatherBaseWB ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; auto * Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ;

if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) } ) ;


<s> AAAMDFlatWorkGroupSize ( const IRPosition & IRP , Attributor & A ) : Base ( IRP , <NUM_LIT> ) {


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> EVT SrcVT = Src . getValueType ( ) ; EVT SrcSVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = SrcVT . getVectorNumElements ( ) ; if ( SrcSVT == <STR_LIT> || ! isa < ConstantSDNode > ( Idx ) ) return SDValue ( ) ; SDValue SrcBC = peekThroughBitcasts ( Src ) ; if ( <STR_LIT> == SrcBC . getOpcode ( ) ) { SDValue SrcOp = SrcBC . getOperand ( <NUM_LIT> ) ; if ( SrcOp . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , SrcOp ) ; } if ( SrcBC . getOpcode ( ) == <STR_LIT> && SrcBC . hasOneUse ( ) ) { auto * MemIntr = cast < MemIntrinsicSDNode > ( SrcBC ) ; unsigned SrcBCWidth = SrcBC . getScalarValueSizeInBits ( ) ; if ( MemIntr -> getMemoryVT ( ) . getSizeInBits ( ) == SrcBCWidth && VT . getSizeInBits ( ) == SrcBCWidth ) { SDValue Load = DAG . getLoad ( VT , dl , MemIntr -> getChain ( ) , MemIntr -> getBasePtr ( ) , MemIntr -> getPointerInfo ( ) , MemIntr -> getAlignment ( ) , MemIntr -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( MemIntr , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return Load ; } } if ( <STR_LIT> == Src . getOpcode ( ) && SrcVT . is128BitVector ( ) && isNullConstant ( Idx ) ) { Src = extract128BitVector ( Src . getOperand ( <NUM_LIT> ) , <NUM_LIT> , DAG , dl ) ; Src = DAG . getBitcast ( SrcVT , Src ) ; return DAG . getNode ( N -> getOpcode ( ) , dl , VT , Src , Idx ) ; } SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ;

if ( ! getTargetShuffleInputs ( SrcBC , Ops , Mask , DAG ) ) return SDValue ( ) ;


<s> printIntelMemReference ( MI , OpNo , O ) ; return false ; } if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'H' : printMemReference ( MI , OpNo , O , <STR_LIT> ) ; return false ; case 'P' : printMemReference ( MI , OpNo , O , <STR_LIT> ) ;


<s> std :: vector < CalleeSavedInfo > C<ISA_LIT> ; const MCPhysReg * CSRegs = MRI . getCalleeSavedRegs ( ) ; for ( unsigned I = <NUM_LIT> ; CSRegs [ I ] ; ++ I ) { MCRegister Reg = CSRegs [ I ] ; if ( SavedRegs . test ( Reg ) ) { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , <STR_LIT> ) ; int JunkFI = MFI . CreateStackObject ( TRI -> getSpillSize ( * RC ) , TRI -> getSpillAlign ( * RC ) , true ) ; C<ISA_LIT> . push_back ( CalleeSavedInfo ( Reg , JunkFI ) ) ; } } if ( ! C<ISA_LIT> . empty ( ) ) { for ( MachineBasicBlock * SaveBlock : SaveBlocks ) insertCSRSaves ( * SaveBlock , C<ISA_LIT> , LIS ) ; assert ( SaveBlocks . size ( ) == <NUM_LIT> && <STR_LIT> ) ; updateLiveness ( MF , C<ISA_LIT> ) ; for ( MachineBasicBlock * RestoreBlock : RestoreBlocks ) insertCSRRestores ( * RestoreBlock , C<ISA_LIT> , LIS ) ; return true ; }


<s> MachineInstr * CMPI = MRI -> getVRegDef ( CndReg ) ; if ( CMPI -> getParent ( ) != & BB ) return false ; for ( MachineOperand & MO : CMPI -> operands ( ) ) if ( MO . isReg ( ) && ! Register :: isVirtualRegister ( MO . getReg ( ) ) ) return false ; return true ; } return false ; } ; auto isEligibleForMoveCmp = [ ] ( MachineBasicBlock & BB ) { return BB . succ_size ( ) == <NUM_LIT> ; } ; if ( ! isEligibleBB ( MBB ) ) return false ; unsigned NumPredBBs = MBB . pred_size ( ) ; if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock * TmpMBB = * MBB . pred_begin ( ) ; if ( isEligibleBB ( * TmpMBB ) ) { PredMBB = TmpMBB ; MBBtoMoveCmp = nullptr ; return true ; } } else if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock :: pred_iterator PI = MBB . pred_begin ( ) ; MachineBasicBlock * Pred1MBB = * PI ; MachineBasicBlock * Pred2MBB = * ( PI + <NUM_LIT> ) ; if ( isEligibleBB ( * Pred1MBB ) && isEligibleForMoveCmp ( * Pred2MBB ) ) { } else if ( isEligibleBB ( * Pred2MBB ) && isEligibleForMoveCmp ( * Pred1MBB ) ) { std :: swap ( Pred1MBB , Pred2MBB ) ; }


<s> static SDValue lowerAddSub ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { MVT VT = Op . getSimpleValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return lowerAddSubToHorizontalOp ( Op , DAG , Subtarget ) ; if ( VT . getScalarType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return splitVectorIntBinary ( Op , DAG ) ; assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return splitVectorIntBinary ( Op , DAG ) ;


<s> bool isDynAllocFI ( int FI ) const { return DynAllocFI && DynAllocFI == FI ;


<s> assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned RegEnum = <NUM_LIT> ; switch ( OpInfo [ <NUM_LIT> ] . RegClass ) { case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeVFPRd ( insn , false ) ) ; break ; case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeVFPRd ( insn , true ) ) ; break ; case <STR_LIT> : RegEnum = getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> :


<s> { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } } ; for ( std :: pair < unsigned , unsigned > jumpSlot : jumpSlots ) {

if ( ! ( jumpSlot . first & Summary . branchInsts [ <NUM_LIT> ] -> Core . getUnits ( ) ) ) continue ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; BI -> dump ( ) ; ) ; if ( BI -> getOpcode ( ) == <STR_LIT> ) { MI = BI ; continue ; } if ( MI ) { for ( auto & MO : BI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) return ; } } if ( ! MI ) return ;

MI -> setDesc ( HII -> get ( <STR_LIT> ) ) ;


<s> <ISA_LIT>Z80TargetMachine :: <ISA_LIT>Z80TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> ) , FrameLowering ( * this ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this ) {


<s> SelectionDAG & DAG = CLI . DAG ; const SDLoc DL = CLI . DL ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto Layout = MF . getDataLayout ( ) ; CallingConv :: ID CallConv = CLI . CallConv ; if ( ! CallingConvSupported ( CallConv ) ) fail ( DL , DAG , <STR_LIT> <STR_LIT> ) ; if ( CLI . IsPatchPoint ) fail ( DL , DAG , <STR_LIT> ) ; SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ; if ( Ins . size ( ) > <NUM_LIT> ) fail ( DL , DAG , <STR_LIT> ) ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; for ( unsigned i = <NUM_LIT> ; i < Outs . size ( ) ; ++ i ) { const <STR_LIT> & Out = Outs [ i ] ; SDValue & OutVal = OutVals [ i ] ; EVT VT = OutVal . getValueType ( ) ; if ( Out . Flags . isNest ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInAlloca ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInConsecutiveRegs ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInConsecutiveRegsLast ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isByVal ( ) && Out . Flags . getByValSize ( ) != <NUM_LIT> ) Chain = DAG . getNode ( <STR_LIT> , DL , VT , OutVal ) ; } bool IsVarArg = CLI . IsVarArg ; unsigned NumFixedArgs = CLI . NumFixedArgs ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; if ( IsVarArg ) { for ( SDValue Arg : make_range ( OutVals . begin ( ) + NumFixedArgs , OutVals . end ( ) ) ) { EVT VT = Arg . getValueType ( ) ; assert ( VT != <STR_LIT> && <STR_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; unsigned Offset = CCInfo . AllocateStack ( Layout . getTypeAllocSize ( Ty ) , Layout . getABITypeAlignment ( Ty ) ) ; CCInfo . addLoc ( CCValAssign :: getMem ( ArgLocs . size ( ) , VT . getSimpleVT ( ) , Offset , VT . getSimpleVT ( ) , CCValAssign :: Full ) ) ;


<s> if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = LSHIFTRT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; } shifted_val = value << shift ; alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , shifted_val , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = LSHIFTRT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : return ELF :: R_<ISA_LIT>_32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ; case FK_Data_Add_1 : return ELF :: R_<ISA_LIT>_ADD8 ; case FK_Data_Add_2 : return ELF :: R_<ISA_LIT>_ADD16 ; case FK_Data_Add_4 : return ELF :: R_<ISA_LIT>_ADD32 ; case FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ; case FK_Data_Add_6b : return ELF :: R_<ISA_LIT>_SET6 ; case FK_Data_Sub_1 : return ELF :: R_<ISA_LIT>_SUB8 ; case FK_Data_Sub_2 : return ELF :: R_<ISA_LIT>_SUB16 ; case FK_Data_Sub_4 : return ELF :: R_<ISA_LIT>_SUB32 ; case FK_Data_Sub_8 : return ELF :: R_<ISA_LIT>_SUB64 ; case FK_Data_Sub_6b : return ELF :: R_<ISA_LIT>_SUB6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ;


<s> return MatchOperand_Success ; } unsigned Reg = matchRegisterNameAlias ( Name , RegKind :: Matrix ) ; if ( ! Reg ) return MatchOperand_NoMatch ; size_t DotPosition = Name . find ( '.' ) ; assert ( DotPosition != StringRef :: npos && <STR_LIT> ) ; StringRef Head = Name . take_front ( DotPosition ) ; StringRef Tail = Name . drop_front ( DotPosition ) ; StringRef RowOrColumn = Head . take_back ( ) ; MatrixKind Kind = StringSwitch < MatrixKind > ( RowOrColumn ) . Case ( <STR_LIT> , MatrixKind :: Row ) . Case ( <STR_LIT> , MatrixKind :: Col ) . Default ( MatrixKind :: Tile ) ; const auto & KindRes = parseVectorKind ( Tail , RegKind :: Matrix ) ; if ( ! KindRes ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; }

unsigned ElementWidth = KindRes -> second ;


<s> if ( GET_CODE ( obj ) == SUBREG ) obj = SUBREG_REG ( obj ) ; machine_mode mode = GET_MODE ( obj ) ;


<s> unsigned RetOpcode = MBBI -> getOpcode ( ) ;

return RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ;


<s> std :: bitset < <NUM_LIT> > Zeroable ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { SDValue Elt = Op -> getOperand ( i ) ; Zeroable [ i ] = ( Elt . getOpcode ( ) == <STR_LIT> || <STR_LIT> ( Elt ) ) ; } assert ( Zeroable . size ( ) - Zeroable . count ( ) > <NUM_LIT> && <STR_LIT> ) ; SDValue FirstNonZero ; unsigned FirstNonZeroIdx ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Elt = Op -> getOperand ( i ) ; if ( Elt . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; MVT VT = Elt . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; if ( ! FirstNonZero . getNode ( ) ) { FirstNonZero = Elt ; FirstNonZeroIdx = i ; } } assert ( FirstNonZero . getNode ( ) && <STR_LIT> ) ; SDValue V1 = FirstNonZero . getOperand ( <NUM_LIT> ) ; MVT VT = V1 . getSimpleValueType ( ) ; SDValue Elt ; unsigned EltMaskIdx , EltIdx ; int Mask [ <NUM_LIT> ] ; for ( EltIdx = <NUM_LIT> ; EltIdx < <NUM_LIT> ; ++ EltIdx ) { if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) {

SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ;


<s> ~ <ISA_LIT>AsmBackend ( ) override {


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNum , SMLoc & StartLoc , SMLoc & EndLoc ) { std :: unique_ptr < <ISA_LIT>Operand > Op = parseRegister ( ) ; if ( Op != <NUM_LIT> ) RegNum = Op -> getReg ( ) ; return ( Op == <NUM_LIT> ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget -> getRegisterInfo ( ) ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; MVT PtrVT = getPointerTy ( DL , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; PointerType * PtrTy = PointerType :: get ( Ty , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg ) , PtrVT ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ; SDValue PtrOffset = DAG . getUNDEF ( PtrVT ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ;

unsigned Align = DL . getABITypeAlignment ( Ty ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFLT_ROUNDS_ ( SDValue Op , SelectionDAG & DAG ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const TargetFrameInfo & TFI = * TM . getFrameInfo ( ) ; unsigned StackAlignment = TFI . getStackAlignment ( ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , StackAlignment , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ;

SDValue Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , StackSlot ) ;


<s> builder . quick_push ( const1_rtx ) ;


<s> addPass ( create<ISA_LIT>CFGStackify ( ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( getVectorIndex ( ) ) ) ;


<s> AAPointerInfo :: OffsetAndSize OAS ( <STR_LIT> :: QUEUE_PTR_OFFSET , <NUM_LIT> ) ; return funcRetrievesImplicitKernelArg ( A , OAS ) ;


<s> unsigned tmpReg = GuardsReg ; int bitpos = TRI -> getS0Index ( predReg ) ; assert ( bitpos > <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) ) . addFrameIndex ( fi ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . addReg ( tmpReg ) . addImm ( bitpos ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) ; InsertedInstrs ++ ; uint32_t or_bitmask = <NUM_LIT> << bitpos ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , PRTmp ) ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) ; assert ( isUInt < <NUM_LIT> > ( or_bitmask ) ;

BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , tmpReg ) . addReg ( PRTmp ) . addImm ( <NUM_LIT> ) . addReg ( tmpReg ) . addImm ( or_bitmask ) ;


<s> MCInst MCB ; MCB . setOpcode ( <STR_LIT> ) ; MCB . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugInstr ( ) && ! MII -> isImplicitDef ( ) ) <ISA_LIT>LowerToMC ( MCII , & * MII , MCB , * this ) ; } else { <ISA_LIT>LowerToMC ( MCII , MI , MCB , * this ) ; } const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ;

if ( MI -> isBundle ( ) && HII . getBundleNoShuf ( * MI ) ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ;


<s> XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; tmp = gen_rtx_SET ( gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; for ( i = <NUM_LIT> ; i < count ; i ++ ) { reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( gen_frame_mem ( DFmode , plus_constant ( Pmode , stack_pointer_rtx , i * <NUM_LIT> ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , i + <NUM_LIT> ) = tmp ; } par = emit_insn ( par ) ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ;

RTX_FRAME_RELATED_P ( par ) = <NUM_LIT> ;


<s> unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; if ( Outs [ <NUM_LIT> ] . Flags . isZExt ( ) || Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) { SrcReg = <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; } }


<s> int hppa_can_use_return_insn_p ( void ) {

return ( reload_completed && ( compute_frame_size ( get_frame_size ( ) , <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) && ! regs_ever_live [ <NUM_LIT> ] && ! frame_pointer_needed ) ;


<s> SmallVector < int , <NUM_LIT> > ScaledMask ; int Scale = NumSrcElts / Mask . size ( ) ; scaleShuffleMask < int > ( Scale , Mask , ScaledMask ) ; Mask = std :: move ( ScaledMask ) ; } else if ( ( Mask . size ( ) % NumSrcElts ) == <NUM_LIT> ) { int ExtractIdx = ( int ) N -> getConstantOperandVal ( <NUM_LIT> ) ; int Scale = Mask . size ( ) / NumSrcElts ; int Lo = Scale * ExtractIdx ; int Hi = Scale * ( ExtractIdx + <NUM_LIT> ) ; for ( int i = <NUM_LIT> , e = ( int ) Mask . size ( ) ; i != e ; ++ i ) if ( i < Lo || Hi <= i ) Mask [ i ] = SM_SentinelUndef ; SmallVector < int , <NUM_LIT> > WidenedMask ; while ( Mask . size ( ) > NumSrcElts && canWidenShuffleElements ( Mask , WidenedMask ) ) Mask = std :: move ( WidenedMask ) ; } } if ( Mask . size ( ) != NumSrcElts ) return SDValue ( ) ; int SrcIdx = Mask [ N -> getConstantOperandVal ( <NUM_LIT> ) ] ; SDLoc dl ( N ) ; if ( SrcIdx == SM_SentinelUndef ) return DAG . getUNDEF ( VT ) ; if ( SrcIdx == SM_SentinelZero ) return VT . isFloatingPoint ( ) ? DAG . getConstantFP ( <NUM_LIT> , dl , VT ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue SrcOp = Ops [ SrcIdx / Mask . size ( ) ] ; SrcIdx = SrcIdx % Mask . size ( ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( ( SrcIdx == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || Subtarget . hasSSE41 ( ) ) ) { assert ( SrcSVT == VT && <STR_LIT> ) ; SrcOp = DAG . getBitcast ( SrcVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , SrcSVT , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ; } if ( ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) ) || ( SrcVT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) {

assert ( VT . getSizeInBits ( ) >= SrcSVT . getSizeInBits ( ) && <STR_LIT> ) ;


<s> SDValue AMDGPUTargetLowering :: Lower<ISA_LIT>GN_EXTEND_INREG ( SDValue Op , SelectionDAG & DAG ) const { EVT ExtraVT = cast < VTSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ScalarVT = VT . getScalarType ( ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned NElts = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Args ; DAG . ExtractVectorElements ( Src , Args , <NUM_LIT> , NElts ) ; SDValue VTOp = DAG . getValueType ( ExtraVT . getScalarType ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NElts ; ++ I ) Args [ I ] = DAG . getNode ( <STR_LIT> , DL , ScalarVT , Args [ I ] , VTOp ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , Args ) ;


<s> if ( COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( mode == OOmode ) return ( TARGET_MMA && VSX_REGNO_P ( regno ) && ( regno & <NUM_LIT> ) == <NUM_LIT> ) ; if ( mode == XOmode ) return ( TARGET_MMA && FP_REGNO_P ( regno ) && ( regno & <NUM_LIT> ) == <NUM_LIT> ) ; if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & <NUM_LIT> ) == <NUM_LIT> ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || mode == TImode || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = FCRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> SplatSize = <NUM_LIT> ; Val = <NUM_LIT> ; } EVT CanonicalVT = VTys [ SplatSize - <NUM_LIT> ] ; return DAG . getBitcast ( ReqVT , DAG . getConstant ( Val , dl , CanonicalVT ) ) ;


static const char * S [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;


<s> auto I = MBB . getLastNonDebugInstr ( ) ; if ( I != MBB . end ( ) ) { if ( ( Subtarget -> hardenSlsRet ( ) && isSimpleReturn ( * I ) ) || ( Subtarget -> hardenSlsIJmp ( ) && isIndirectBranchOrTailCall ( * I ) ) ) { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; }


return TargetTriple . isOSBinFormatELF ( ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> if ( ! MI -> getOperand ( Op ) . isImm ( ) ) return false ; Imm = MI -> getOperand ( Op ) . getImm ( ) ;


<s> return __builtin_mve_vcvtpq_uv8hi ( __a ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> const TargetRegisterClass & RC = <STR_LIT> ; const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) ISRDataRegFI [ I ] = MF . getFrameInfo ( ) . CreateStackObject ( TRI . getSpillSize ( RC ) , TRI . getSpillAlignment ( RC ) , false ) ;


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'A' : return C_Memory ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ;


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) switch ( N -> getOperand ( i ) . getNode ( ) -> getOpcode ( ) ) {


<s> return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; static const int Mask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ;

SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT> ) , & Mask [ <NUM_LIT> ] ) ) ;


<s> if ( rs >= <NUM_LIT> ) break ; for ( re = rs + <NUM_LIT> ; re < <NUM_LIT> && ! call_used_regs [ PR_REG ( re ) ] ; re ++ ) continue ; if ( out_state == <NUM_LIT> ) { fputs ( <STR_LIT> , asm_out_file ) ;


<s> unsigned getFlatAddressSpace ( ) const { if ( IsGraphicsShader ) return - <NUM_LIT> ; return ST -> hasFlatAddressSpace ( ) ? <ISA_LIT>AS :: FLAT_ADDRESS : <ISA_LIT>AS :: UNKNOWN_ADDRESS_SPACE ;


<s> EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) ) return false ;

unsigned VTSize = VT . getSimpleVT ( ) . getSizeInBits ( ) ;


<s> if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isInt < <NUM_LIT> > ( Imm ) ;

return IsValid && ( ( IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) ;


<s> case MachineOperand :: MO_ConstantPoolIndex : O << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; case MachineOperand :: MO_BlockAddress : O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Size ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ; State . addLoc ( It ) ; } PendingMembers . clear ( ) ; return true ; } else if ( LocVT != <STR_LIT> ) RegList = SRegList ; for ( auto Reg : RegList ) State . AllocateReg ( Reg ) ;


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case GLOBAL_ID : case CONSTANT_ID : case RAW_UAV_ID : case ARENA_UAV_ID : break ; case LDS_ID : if ( usesHardware ( <STR_LIT> ) ) { return DEFAULT_LDS_ID ; } break ; case SCRATCH_ID : if ( usesHardware ( <STR_LIT> ) ) { return DEFAULT_SCRATCH_ID ; } break ; case GDS_ID : assert ( <NUM_LIT> && <STR_LIT> ) ; if ( usesHardware ( <STR_LIT> ) ) { return DEFAULT_GDS_ID ; } break ; } ; return <NUM_LIT> ;


<s> bool isDSPControlWrite = false ; if ( isReadOrWriteToDSPReg ( MI , isDSPControlWrite ) ) { if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != ( <NUM_LIT> << <NUM_LIT> ) ) return None ; else if ( isDSPControlWrite ) {

return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ;


<s> Waitcnt = encodeVmcnt ( Version , Waitcnt , Vmcnt ) ; Waitcnt = encodeExpcnt ( Version , Waitcnt , Expcnt ) ; Waitcnt = encodeLgkmcnt ( Version , Waitcnt , Lgkmcnt ) ;


<s> stack_info . reload_completed = <NUM_LIT> ; return ggc_cleared_alloc < machine_function > ( ) ;


<s> return QUAL_TYPE ( TI ) ; case OImode : return arm_simd_intOI_type_node ; case EImode : return arm_simd_intEI_type_node ; case CImode : return arm_simd_intCI_type_node ; case XImode : return arm_simd_intXI_type_node ; case HFmode : return arm_simd_floatHF_type_node ; case SFmode : return float_type_node ; case DFmode : return double_type_node ; default : gcc_unreachable ( ) ; }


<s> _mm_cvtt_roundss_si64 ( __m128 __A , const int __R ) { return ( long long ) __builtin_ia32_vcvttss2si64 ( ( __v4sf ) __A , __R ) ;


<s> if ( WidenedMask [ <NUM_LIT> ] == <NUM_LIT> && IsHighZero ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , getZeroVector ( VT , Subtarget , DAG , DL ) , LoV , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( SDValue Blend = lowerShuffleAsBlend ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( ! IsLowZero && ! IsHighZero ) { bool OnlyUsesV1 = isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { if ( ! isa < LoadSDNode > ( peekThroughBitcasts ( V1 ) ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } } if ( Subtarget . hasVLX ( ) ) { if ( WidenedMask [ <NUM_LIT> ] < <NUM_LIT> && WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> ) { unsigned PermMask = ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) | ( ( WidenedMask [ <NUM_LIT> ] % <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getConstant ( PermMask , DL , <STR_LIT> ) ) ; } } } assert ( ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> || IsLowZero ) && ( WidenedMask [ <NUM_LIT> ] >= <NUM_LIT> || IsHighZero ) && <STR_LIT> ) ; unsigned PermMask = <NUM_LIT> ; PermMask |= IsLowZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; PermMask |= IsHighZero ? <NUM_LIT> : ( WidenedMask [ <NUM_LIT> ] << <NUM_LIT> ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V1 = DAG . getUNDEF ( VT ) ; if ( ( PermMask & <NUM_LIT> ) != <NUM_LIT> && ( PermMask & <NUM_LIT> ) != <NUM_LIT> ) V2 = DAG . getUNDEF ( VT ) ;


<s> int arm_address_offset_is_imm ( rtx_insn * insn ) { rtx mem , addr ; extract_insn_cached ( insn ) ; if ( REG_P ( recog_data . operand [ <NUM_LIT> ] ) ) return <NUM_LIT> ;

mem = recog_data . operand [ <NUM_LIT> ] ;


if ( ! WasmDisableExplicitLocals ) addPass ( create<ISA_LIT>DebugFixup ( ) ) ;


<s> getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'd' : case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Subtarget -> isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget -> isGP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , nullptr ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( ( VT == <STR_LIT> ) && ( ! Subtarget -> isSingleFloat ( ) ) ) { if ( Subtarget -> isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'x' :


<s> rtx tmp_reg ; rtx tp_reg = gen_rtx_REG ( Pmode , TP_REGNUM ) ; rtx pat , insns , reg0 ; int relax_group_id = nds32_alloc_relax_group_id ( ) ; if ( GET_CODE ( x ) == SYMBOL_REF ) switch ( SYMBOL_REF_TLS_MODEL ( x ) ) { case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : if ( SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_GLOBAL_DYNAMIC ) pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TLSGD ) ; else pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TLSLD ) ; pat = gen_rtx_CONST ( SImode , pat ) ; reg0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; insns = emit_call_insn ( gen_tls_desc ( pat , GEN_INT ( relax_group_id ) ) ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insns ) , pic_offset_table_rtx ) ; RTL_CONST_CALL_P ( insns ) = <NUM_LIT> ; tmp_reg = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp_reg , reg0 ) ; x = tmp_reg ; break ; case TLS_MODEL_INITIAL_EXEC : pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TLSIE ) ; tmp_reg = gen_reg_rtx ( SImode ) ; pat = gen_rtx_CONST ( SImode , pat ) ; emit_insn ( gen_tls_ie ( tmp_reg , pat , GEN_INT ( relax_group_id ) ) ) ; if ( flag_pic ) emit_use ( pic_offset_table_rtx ) ; x = gen_rtx_PLUS ( Pmode , tmp_reg , tp_reg ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp_reg = gen_reg_rtx ( SImode ) ; pat = gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , x ) , UNSPEC_TLSLE ) ; pat = gen_rtx_CONST ( SImode , pat ) ; emit_insn ( gen_tls_le ( tmp_reg , pat , GEN_INT ( relax_group_id ) ) ) ; x = gen_rtx_PLUS ( Pmode , tmp_reg , tp_reg ) ; break ; default : gcc_unreachable ( ) ; } else if ( GET_CODE ( x ) == CONST ) { rtx base , addend ; split_const ( x , & base , & addend ) ; if ( SYMBOL_REF_TLS_MODEL ( base ) == TLS_MODEL_LOCAL_EXEC ) {


<s> bool hasLegacyGeometry ( ) const { return getGeneration ( ) < GFX11 ;


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr ) ;


<s> MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI . getObjectSize ( FrameIndex ) ; MFI . setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % <NUM_LIT> ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI . CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ;

addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) , UnwindHelpFI ) . addImm ( - <NUM_LIT> ) ;


<s> if ( Tok . is ( AsmToken :: Integer ) ) { Save = Tok . getIntVal ( ) ; SaveIsReg = false ; Parser . Lex ( ) ; } else return reportParseError ( <STR_LIT> ) ; } else Save = getGPR ( Save ) ; if ( ! eatComma ( <STR_LIT> ) ) return true ;


<s> if ( ( unsigned ) Format >= ( array_lengthof ( FuncPtrs ) - <NUM_LIT> ) ) { DEBUG ( errs ( ) << <STR_LIT> ) ; return <NUM_LIT> ; } return new <ISA_LIT>BasicMCBuilder ( Opcode , Format , <ISA_LIT>Insts [ Opcode ] . getNumOperands ( ) ) ;


return ( int ) __builtin_ia32_vcvttsd2si32 ( ( __v2df ) __A , __R ) ;


<s> getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { if ( IsPICCall || ! GlobalOrExternal ) { unsigned T9Reg = IsN64 ? <STR_LIT> : <STR_LIT> ; RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ; } else Ops . push_back ( Callee ) ;

<ISA_LIT>TargetLowering :: getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ;


<s> void <ISA_LIT>InstPrinter :: printVectorListThreeAllLanes ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << uid << '_' << uid2 ; return OutContext . GetOrCreateSymbol ( Name . str ( ) ) ;


<s> <ISA_LIT>Combiner :: <ISA_LIT>Combiner ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>CombinerPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> bool hasSwiftAsyncContext ( ) const {


<s> if ( ! UnusedCarry . isValid ( ) ) report_fatal_error ( <STR_LIT> ) ; return BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) ;


<s> return selectBDAddr ( <STR_LIT> , Addr , Base , Disp ) ;


<s> case <STR_LIT> : return decodeBR ( insn ) ; case <STR_LIT> : return decodeBRI ( insn ) ; case <STR_LIT> : return decodeBSRL ( insn ) ; case <STR_LIT> : return decodeBSRLI ( insn ) ; case <STR_LIT> : return decodeRSUBK ( insn ) ; case <STR_LIT> : return decodeFADD ( insn ) ; case <STR_LIT> : return decodeGET ( insn ) ; case <STR_LIT> : return decodeGETD ( insn ) ; case <STR_LIT> : return decodeIDIV ( insn ) ; case <STR_LIT> : return decodeLBU ( insn ) ; case <STR_LIT> : return decodeLHU ( insn ) ; case <STR_LIT> : return decodeLW ( insn ) ; case <STR_LIT> : return decodeSB ( insn ) ; case <STR_LIT> : return decodeSH ( insn ) ; case <STR_LIT> : return decodeSW ( insn ) ; case <STR_LIT> : return decodeMFS ( insn ) ; case <STR_LIT> : return decodeOR ( insn ) ; case <STR_LIT> : return decodeXOR ( insn ) ; case <STR_LIT> : return decodeANDN ( insn ) ; case <STR_LIT> : return decodeRTSD ( insn ) ; default : return opcode ; }


<s> InstructionCost MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case <STR_LIT> : if ( LT . second != <STR_LIT> ) return ( Cost + <NUM_LIT> ) * LT . first ; return LT . first * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Cost + <NUM_LIT> ) * LT . first ; case <STR_LIT> : if ( isa < FixedVectorType > ( Ty ) && ! Ty -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Cost + <NUM_LIT> ) * LT . first ; return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; }


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( AdjustSPLabel , - StackSize ) ) ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; unsigned S1 = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ;

MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , S1 , - <NUM_LIT> ) ) ;


<s> Register R = Op . getReg ( ) ; if ( ! R . isVirtual ( ) ) continue ;

if ( DefReg != <NUM_LIT> ) return <NUM_LIT> ;


<s> const TargetInstrDesc & II = TII . get ( MachineInstOpcode ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addFPImm ( FPImm ) ) ;


<s> for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) reg_alloc_order [ i ] = gnu_abi_reg_alloc_order [ i ] ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) call_used_regs [ i ] = <NUM_LIT> ; for ( i = MMIX_RESERVED_GNU_ARG_0_REGNUM ; i < MMIX_RESERVED_GNU_ARG_0_REGNUM + MMIX_MAX_ARGS_IN_REGS ; i ++ ) fixed_regs [ i ] = <NUM_LIT> ;


<s> codes [ i ] . code = PLUS ; codes [ i ] . value = CONST_LOW_PART ( value ) ; } else { i = mips_build_integer ( codes , high ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>CodePrinterPass ( raw_ostream & o , <ISA_LIT>TargetMachine & tm , bool fast ) { return new <ISA_LIT>AsmPrinter ( o , tm , tm . getTargetAsmInfo ( ) , fast ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo & TRI = * MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; MachineIRBuilder Builder ( MBB , MBB . begin ( ) ) ; int64_t StackSize = MFI . getStackSize ( ) ; if ( isISR ( MF ) ) StackSize += <NUM_LIT> ; if ( StackSize ) offsetSP ( Builder , - StackSize ) ; if ( ! hasFP ( MF ) ) return ; auto MBBI = std :: find_if_not ( Builder . getInsertPt ( ) , MBB . end ( ) , [ ] ( const MachineInstr & MI ) { return MI . getFlag ( MachineInstr :: FrameSetup ) ;


<s> Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ;


<s> LDSGlobals . erase ( std :: remove_if ( LDSGlobals . begin ( ) , LDSGlobals . end ( ) , [ & ] ( GlobalVariable * GV ) { return shouldIgnorePointerReplacement ( GV ) ; } ) , LDSGlobals . end ( ) ) ; return LDSGlobals ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; return ; case <STR_LIT> : Results . push_back ( ExpandBIT_CONVERT ( N , DAG ) ) ; return ; case <STR_LIT> : case <STR_LIT> : { SDValue Res = ExpandSRx ( N , DAG , Subtarget ) ; if ( Res . getNode ( ) ) Results . push_back ( Res ) ;


<s> break ; case AsmToken :: Identifier : { OperandInfoTy Msg ( ID_UNKNOWN_ ) ; OperandInfoTy Operation ( OP_UNKNOWN_ ) ; int64_t StreamId = STREAM_ID_DEFAULT_ ; if ( parseSendMsgConstruct ( Msg , Operation , StreamId ) ) return MatchOperand_ParseFail ; do { if ( ! ( ( ID_INTERRUPT <= Msg . Id && Msg . Id <= ID_GS_DONE ) || Msg . Id == ID_SYSMSG ) ) { if ( Msg . IsSymbolic ) Error ( S , <STR_LIT> ) ; else Error ( S , <STR_LIT> ) ; break ; } Imm16Val = ( Msg . Id << ID_SHIFT_ ) ; if ( Msg . Id == ID_GS || Msg . Id == ID_GS_DONE ) { if ( ! ( OP_GS_FIRST_ <= Operation . Id && Operation . Id < OP_GS_LAST_ ) ) { if ( Operation . IsSymbolic ) Error ( S , <STR_LIT> ) ; else Error ( S , <STR_LIT> ) ; break ; } if ( Operation . Id == OP_GS_NOP && Msg . Id != ID_GS_DONE ) { Error ( S , <STR_LIT> ) ; break ; } Imm16Val |= ( Operation . Id << OP_SHIFT_ ) ; }


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; } } else { assert ( Subtarget . hasIndexHalfRegs ( ) && <STR_LIT> ) ; bool NeedEX = false ; for ( unsigned * Reg : { & DstReg , & SrcReg } ) { switch ( * Reg ) { case <STR_LIT> : * Reg = <STR_LIT> ; NeedEX = true ; break ; case <STR_LIT> : * Reg = <STR_LIT> ; NeedEX = true ; break ; } } unsigned ExOpc = <STR_LIT> ; if ( NeedEX ) { if ( MI != MBB . begin ( ) && std :: prev ( MI ) -> getOpcode ( ) == ExOpc ) { std :: prev ( MI ) -> eraseFromParent ( ) ; } else { MachineInstr & ExMI = * BuildMI ( MBB , MI , DL , get ( ExOpc ) ) ; for ( unsigned Reg : { <STR_LIT> , <STR_LIT> } ) ExMI . findRegisterUseOperand ( Reg ) -> setIsUndef ( ) ; } } BuildMI ( MBB , MI , DL , get ( <STR_LIT> . contains ( DstReg , SrcReg ) ? <STR_LIT> : <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( NeedEX ) { BuildMI ( MBB , MI , DL , get ( ExOpc ) ) ; } } return ; } if ( DstReg == <STR_LIT> ) { assert ( ( <STR_LIT> . contains ( SrcReg ) || SrcReg == <STR_LIT> ) && <STR_LIT> ) ; if ( SrcReg == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: ImplicitDefine ) . addReg ( SrcReg , RegState :: ImplicitKill ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( SrcReg == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: ImplicitDefine ) . addReg ( SrcReg , RegState :: ImplicitKill ) ; return ; } if ( SrcReg == <STR_LIT> ) { assert ( ( <STR_LIT> . contains ( DstReg ) || DstReg == <STR_LIT> ) && <STR_LIT> ) ; if ( DstReg == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: ImplicitDefine ) . addReg ( SrcReg , RegState :: ImplicitKill ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) ; if ( DstReg == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DstReg , RegState :: ImplicitDefine ) . addReg ( SrcReg , RegState :: ImplicitKill ) ;


<s> void addMEMrrOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> return getCMOV ( SDLoc ( Op ) , VT , SelectTrue , SelectFalse , <ISA_LIT>cc , CCR , OverflowCmp , DAG ) ; } if ( Cond . getOpcode ( ) == <STR_LIT> && Cond . hasOneUse ( ) ) { const ConstantSDNode * CMOVTrue = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CMOVFalse = dyn_cast < ConstantSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) ; if ( CMOVTrue && CMOVFalse ) { unsigned CMOVTrueVal = CMOVTrue -> getZExtValue ( ) ; unsigned CMOVFalseVal = CMOVFalse -> getZExtValue ( ) ; SDValue True ; SDValue False ; if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( ) ) { EVT VT = Op . getValueType ( ) ;

SDValue <ISA_LIT>cc = Cond . getOperand ( <NUM_LIT> ) ;


<s> static rtx riscv_adjust_libcall_cfi_epilogue ( ) { rtx dwarf = NULL_RTX ; rtx adjust_sp_rtx , reg ; int saved_size = cfun -> machine -> frame . save_libcall_adjustment ; adjust_sp_rtx = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( saved_size ) ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , adjust_sp_rtx , dwarf ) ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST - <NUM_LIT> ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { reg = gen_rtx_REG ( SImode , regno ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } return dwarf ;


<s> Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ;

for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) {


<s> if ( LD . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , LD ) ; if ( ( Size == <NUM_LIT> && NumElem <= <NUM_LIT> ) || ( Size == <NUM_LIT> && NumElem < <NUM_LIT> ) ) return SDValue ( ) ; return PromoteSplat ( SVOp , DAG ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG , dl ) ; if ( NewOp . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , NewOp ) ; } else if ( ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasSSE2 ( ) ) ) ) { if ( <STR_LIT> ( V2 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG , dl ) ; if ( NewOp . getNode ( ) ) { EVT NewVT = NewOp . getValueType ( ) ; if ( isCommutedMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT , true , false ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } else if ( <STR_LIT> ( V1 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG , dl ) ; if ( NewOp . getNode ( ) ) { EVT NewVT = NewOp . getValueType ( ) ; if ( isMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } } return SDValue ( ) ;


<s> * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ;

if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ;


<s> SDValue <ISA_LIT>TargetLowering :: EmitTest ( SDValue Op , unsigned <ISA_LIT>CC , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; bool NeedCF = false ; bool NeedOF = false ; switch ( <ISA_LIT>CC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedCF = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedOF = true ; break ; default : break ; } if ( Op . getResNo ( ) == <NUM_LIT> && ! NeedOF && ! NeedCF ) { unsigned Opcode = <NUM_LIT> ; unsigned NumOperands = <NUM_LIT> ; switch ( Op . getNode ( ) -> getOpcode ( ) ) { case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ) { if ( C -> getAPIntValue ( ) == <NUM_LIT> ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> getAPIntValue ( ) . isAllOnesValue ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( Opcode != <NUM_LIT> ) { const MVT * VTs = DAG . getNodeValueTypes ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != NumOperands ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue New = DAG . getNode ( Opcode , dl , VTs , <NUM_LIT> , & Ops [ <NUM_LIT> ] , NumOperands ) ; DAG . ReplaceAllUsesWith ( Op , New ) ; return SDValue ( New . getNode ( ) , <NUM_LIT> ) ; } } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , Op . getValueType ( ) ) ) ;


<s> else if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ; else { lib = xmalloc ( strlen ( name ) + <NUM_LIT> ) ; strcpy ( lib , <STR_LIT> ) ; strcat ( lib , name ) ; lib_path = locate_lib ( lib , search_dirs ) ; if ( lib_path ) return lib_path ; } fprintf ( stderr , <STR_LIT> , name , name , name ) ;


<s> const uint32_t * getNoPreservedMask ( ) const override {


<s> NewPointeeTy = Inst -> getValueOperand ( ) -> getType ( ) ; } else if ( const auto * Inst = dyn_cast < GetElementPtrInst > ( User ) ) { NewPointeeTy = Inst -> getSourceElementType ( ) ; } if ( NewPointeeTy ) { if ( NewPointeeTy -> isOpaquePointerTy ( ) ) return TypedPointerType :: get ( classifyPointerType ( User ) , V -> getType ( ) -> getPointerAddressSpace ( ) ) ; if ( ! PointeeTy ) PointeeTy = NewPointeeTy ; else if ( PointeeTy != NewPointeeTy ) PointeeTy = Type :: getInt8Ty ( V -> getContext ( ) ) ;


ret . val [ <NUM_LIT> ] = ( uint16x8_t ) __builtin_aarch64_get_qregciv8hi ( __o , <NUM_LIT> ) ;


return ( __m256 ) __builtin_ia32_rcp14ps256_mask ( ( __v8sf ) __A , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> TOut . emitRRX ( <STR_LIT> , ATReg , <STR_LIT> , MCOperand :: createExpr ( GotExpr ) , IDLoc , STI ) ; } else { TOut . emitRRX ( <STR_LIT> , ATReg , <STR_LIT> , MCOperand :: createExpr ( GotExpr ) , IDLoc , STI ) ; } } else { const MCExpr * HiSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * HiExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , HiSym , getContext ( ) ) ; if ( isABI_O32 ( ) || isABI_N32 ( ) ) { TOut . emitRX ( <STR_LIT> , ATReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , STI ) ; } else { const MCExpr * HighestSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * HighestExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HIGHEST , HighestSym , getContext ( ) ) ; const MCExpr * HigherSym = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; const <ISA_LIT>MCExpr * HigherExpr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HIGHER , HigherSym , getContext ( ) ) ; TOut . emitRX ( <STR_LIT> , ATReg , MCOperand :: createExpr ( HighestExpr ) , IDLoc , STI ) ; TOut . emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( HigherExpr ) , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , ATReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; TOut . emitRRX ( <STR_LIT> , ATReg , ATReg , MCOperand :: createExpr ( HiExpr ) , IDLoc , STI ) ;


<s> if ( max_skip ) { while ( nbytes + max_skip >= <NUM_LIT> ) { start = NEXT_INSN ( start ) ; if ( ( JUMP_P ( start ) && asm_noperands ( PATTERN ( start ) ) < <NUM_LIT> ) || CALL_P ( start ) ) njumps -- , isjump = true ; else isjump = false ; nbytes -= ix86_min_insn_size ( start ) ; } } continue ; } min_size = ix86_min_insn_size ( insn ) ; nbytes += min_size ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn ) , min_size ) ; if ( ( JUMP_P ( insn ) && asm_noperands ( PATTERN ( insn ) ) < <NUM_LIT> ) || CALL_P ( insn ) ) njumps ++ ; else continue ; while ( njumps > <NUM_LIT> ) { start = NEXT_INSN ( start ) ;


<s> Register ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; return ResultReg ; } } } unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VT = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ;


<s> bool <ISA_LIT>ompactDAGToDAGISel :: SelectADDRrli ( SDValue Addr , SDValue & R1 , SDValue & Offset ) { return false ;


<s> SchedModel = smodel ; CurrCycle = <NUM_LIT> ; IssueCount = <NUM_LIT> ; CriticalPathLength = DAG -> getBBSize ( ) / SchedModel -> getIssueWidth ( ) ; if ( DAG -> getBBSize ( ) < <NUM_LIT> ) CriticalPathLength >>= <NUM_LIT> ; else {


<s> if ( reg_addr [ m ] . scalar_in_vmx_p ) { fprintf ( stderr , <STR_LIT> , spaces , <STR_LIT> ) ; spaces = <NUM_LIT> ; } else spaces += sizeof ( <STR_LIT> ) - <NUM_LIT> ; fuse_extra_p = ( ( reg_addr [ m ] . fusion_gpr_ld != CODE_FOR_nothing ) || reg_addr [ m ] . fused_toc ) ; if ( ! fuse_extra_p ) { for ( rc = <NUM_LIT> ; rc < N_RELOAD_REG ; rc ++ ) { if ( rc != RELOAD_REG_ANY ) { if ( reg_addr [ m ] . fusion_addi_ld [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addi_ld [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addi_st [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addis_ld [ rc ] != CODE_FOR_nothing || reg_addr [ m ] . fusion_addis_st [ rc ] != CODE_FOR_nothing ) { fuse_extra_p = true ; break ; } } } } if ( fuse_extra_p ) { fprintf ( stderr , <STR_LIT> , spaces , <STR_LIT> ) ; spaces = <NUM_LIT> ; for ( rc = <NUM_LIT> ; rc < N_RELOAD_REG ; rc ++ ) { if ( rc != RELOAD_REG_ANY ) { char load , store ; if ( reg_addr [ m ] . fusion_addis_ld [ rc ] != CODE_FOR_nothing ) load = 'l' ; else if ( reg_addr [ m ] . fusion_addi_ld [ rc ] != CODE_FOR_nothing ) load = 'L' ; else load = '-' ; if ( reg_addr [ m ] . fusion_addis_st [ rc ] != CODE_FOR_nothing ) store = 's' ; else if ( reg_addr [ m ] . fusion_addi_st [ rc ] != CODE_FOR_nothing ) store = 'S' ; else store = '-' ; if ( load == '-' && store == '-' ) spaces += <NUM_LIT> ;


<s> static bool arm_cxx_guard_mask_bit ( void ) {


<s> vmvn_p8 ( poly8x8_t __a ) { return ( poly8x8_t ) ~ ( ( int8x8_t ) __a ) ;


<s> unsigned CC = <ISA_LIT>CondCodeFromString ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> ) ) ; if ( CC != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; PredicationCode = CC ; } } if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; ProcessorIMod = IMod ; } } if ( isMnemonicVPTPredicable ( Mnemonic , ExtraToken ) && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) { unsigned CC = <ISA_LIT>VectorCondCodeFromString ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> ) ) ; if ( CC != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; VPTPredicationCode = CC ; } return Mnemonic ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { ITMask = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) ) ; Mnemonic = Mnemonic . slice ( <NUM_LIT> , <NUM_LIT> ) ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { ITMask = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) ) ; Mnemonic = Mnemonic . slice ( <NUM_LIT> , <NUM_LIT> ) ; }

else if ( Mnemonic . startswith ( <STR_LIT> ) ) {


<s> if ( getConstantValue ( N -> getOperand ( <NUM_LIT> ) , LHSVal ) && getConstantValue ( N -> getOperand ( <NUM_LIT> ) , RHSVal ) ) { SDLoc SL ( N ) ; uint32_t K = Negate ? ( - LHSVal & <NUM_LIT> ) | ( - RHSVal << <NUM_LIT> ) : ( LHSVal & <NUM_LIT> ) | ( RHSVal << <NUM_LIT> ) ;

return DAG . getMachineNode ( <STR_LIT> , SL , N -> getValueType ( <NUM_LIT> ) , DAG . getTargetConstant ( K , SL , <STR_LIT> ) ) ;


<s> ParseSubtargetFeatures ( CPU , CPU , FS ) ; return * this ;


<s> void addAlignedMemory64Operands ( MCInst & Inst , unsigned N ) const { addAlignedMemoryOperands ( Inst , N ) ;


<s> if ( VT . isVector ( ) ) return false ; if ( ! Subtarget . hasBMI ( ) ) return false ;

if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ;


<s> unsigned J2 = ( Val >> <NUM_LIT> ) & <NUM_LIT> ; unsigned I1 = ! ( J1 ^ S ) ; unsigned I2 = ! ( J2 ^ S ) ; unsigned tmp = ( Val & ~ <NUM_LIT> ) | ( I1 << <NUM_LIT> ) | ( I2 << <NUM_LIT> ) ; int imm32 = SignExtend32 < <NUM_LIT> > ( tmp << <NUM_LIT> ) ; if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + imm32 + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm32 ) ) ;


<s> CCState CCInfo ( CFlags . CallConv , CFlags . IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; const unsigned LinkageSize = Subtarget . getFrameLowering ( ) -> getLinkageSize ( ) ; const bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; const EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const unsigned PtrByteSize = Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ; CCInfo . AllocateStack ( LinkageSize , PtrByteSize ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_AIX ) ; const unsigned MinParameterSaveAreaSize = <NUM_LIT> * PtrByteSize ; const unsigned NumBytes = std :: max ( LinkageSize + MinParameterSaveAreaSize , CCInfo . getNextStackOffset ( ) ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SDValue CallSeqStart = Chain ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; const SDValue StackPtr = Is<ISA_LIT>64 ? DAG . getRegister ( <STR_LIT> , <STR_LIT> ) : DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ) { CCValAssign & VA = ArgLocs [ I ++ ] ; SDValue Arg = OutVals [ VA . getValNo ( ) ] ; if ( ! VA . isRegLoc ( ) && ! VA . isMemLoc ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { switch ( VA . getLocInfo ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } if ( VA . isMemLoc ( ) ) { SDValue PtrOff = DAG . getConstant ( VA . getLocMemOffset ( ) , dl , StackPtr . getValueType ( ) ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; continue ; } assert ( VA . isRegLoc ( ) && VA . needsCustom ( ) && CFlags . IsVarArg && VA . getValVT ( ) . isFloatingPoint ( ) && VA . getLocVT ( ) . isInteger ( ) && <STR_LIT> ) ;

SDValue ArgAsInt = DAG . getBitcast ( <STR_LIT> ( VA . getValVT ( ) . getSizeInBits ( ) ) , Arg ) ;


<s> if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; unsigned BlockElts = M [ <NUM_LIT> ] + <NUM_LIT> ; if ( M [ <NUM_LIT> ] < <NUM_LIT> ) BlockElts = BlockSize / EltSz ; if ( BlockSize <= EltSz || BlockSize != BlockElts * EltSz ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { if ( M [ i ] < <NUM_LIT> ) continue ; if ( ( unsigned ) M [ i ] != ( i - i % BlockElts ) + ( BlockElts - <NUM_LIT> - i % BlockElts ) ) return false ; } return true ;


<s> void <ISA_LIT>TargetStreamer :: emitFnStart ( ) {


<s> case <STR_LIT> : return true ; } if ( isCallIndirect ( MI ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = MI . getOperand ( getCalleeOpNo ( MI ) ) ; assert ( MO . isGlobal ( ) ) ; const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ;


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ;


<s> else fprintf ( stream , <STR_LIT> , value ) ; jump_tables_size ++ ;


<s> size_t AMDGPUDevice :: getMaxNumCBs ( ) const { if ( usesHardware ( <STR_LIT> ) ) { return HW_MAX_NUM_CB ;