<s> const std :: string CPU ( STI . getCPU ( ) . str ( ) ) ; auto F = ElfFlagsByCpuStr . find ( CPU ) ;

assert ( F != ElfFlagsByCpuStr . end ( ) && <STR_LIT> ) ;


<s> } else mode = word_mode ; startbit = intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - <NUM_LIT> ) & - BITS_PER_WORD ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > <NUM_LIT> && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = <NUM_LIT> ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= <NUM_LIT> ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ;


<s> MFI -> setHasSpilledSGPRs ( ) ; unsigned Opcode = getSGPRSpillSaveOpcode ( RC -> getSize ( ) ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) ; return ; } if ( ! ST . isVGPRSpillingEnabled ( MFI ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ;

unsigned Opcode = getVGPRSpillSaveOpcode ( RC -> getSize ( ) ) ;


<s> uws -> bytes_left = <NUM_LIT> ; } else uws -> bytes_left -- ; b = ( uws -> data >> <NUM_LIT> ) & <NUM_LIT> ; uws -> data <<= <NUM_LIT> ;


<s> return __builtin_mve_vcmpcsq_v4si ( __a , __b ) ;


<s> int64_t Value = ( - Op2 -> getAPIntValue ( ) ) . getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Value ) || Subtarget . hasInterlockedAccess1 ( ) ) NegSrc2 = DAG . getConstant ( Value , DL , MemVT ) ; } else if ( Subtarget . hasInterlockedAccess1 ( ) ) NegSrc2 = DAG . getNode ( <STR_LIT> , DL , MemVT , DAG . getConstant ( <NUM_LIT> , DL , MemVT ) , Src2 ) ; if ( NegSrc2 . getNode ( ) ) return DAG . getAtomic ( <STR_LIT> , DL , MemVT , Node -> getChain ( ) , Node -> getBasePtr ( ) , NegSrc2 , Node -> getMemOperand ( ) ) ; return Op ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , HasDistinctOps ( false ) , HasLoadStoreOnCond ( false ) , HasHighWord ( false ) , HasFPExtension ( false ) , HasPopulationCount ( false ) , HasMessageSecurityAssist3 ( false ) , HasMessageSecurityAssist4 ( false ) , HasResetReferenceBitsMultiple ( false ) , HasFastSerialization ( false ) , HasInterlockedAccess1 ( false ) , HasMiscellaneousExtensions ( false ) , HasExecutionHint ( false ) , HasLoadAndTrap ( false ) , HasTransactionalExecution ( false ) , HasProcessorAssist ( false ) , HasDFPZonedConversion ( false ) , HasEnhancedDAT2 ( false ) , HasVector ( false ) , HasLoadStoreOnCond2 ( false ) , HasLoadAndZeroRightmostByte ( false ) , HasMessageSecurityAssist5 ( false ) , HasDFPPackedConversion ( false ) , HasMiscellaneousExtensions2 ( false ) , HasGuardedStorage ( false ) , HasMessageSecurityAssist7 ( false ) , HasMessageSecurityAssist8 ( false ) , HasVectorEnhancements1 ( false ) , HasVectorPackedDecimal ( false ) , HasInsertReferenceBitsMultiple ( false ) , HasMiscellaneousExtensions3 ( false ) , HasMessageSecurityAssist9 ( false ) , HasVectorEnhancements2 ( false ) , HasVectorPackedDecimalEnhancement ( false ) , HasEnhancedSort ( false ) , HasDeflateConversion ( false ) , HasVectorPackedDecimalEnhancement2 ( false ) , HasNNPAssist ( false ) , HasBEAREnhancement ( false ) , HasResetDATProtection ( false ) , HasProcessorActivityInstrumentation ( false ) , HasSoftFloat ( false ) , TargetTriple ( TT ) , SpecialRegisters ( initializeSpecialRegisters ( ) ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this ) ) {


<s> } if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( Is32VSXLoad || Is64VSXLoad ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) return false ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) {

insertNamedMCOperand ( MI , MCOperand :: createImm ( <NUM_LIT> ) , <STR_LIT> :: op_sel ) ;


<s> unsigned s3 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned const9 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s3 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ;

Inst . addOperand ( MCOperand :: createImm ( const9 ) ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( Reg == <STR_LIT> ) { report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; } if ( Subtarget -> getGeneration ( ) == <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS && Subtarget -> getRegisterInfo ( ) -> regsOverlap ( Reg , <STR_LIT> ) ) { report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; } switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return Reg ; break ; case <STR_LIT> : case <STR_LIT> : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return Reg ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {

return MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ;


<s> if ( SrcIdx == SM_SentinelZero ) return VT . isFloatingPoint ( ) ? DAG . getConstantFP ( <NUM_LIT> , dl , VT ) : DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue SrcOp = Ops [ SrcIdx / Mask . size ( ) ] ; SrcOp = DAG . getBitcast ( SrcVT , SrcOp ) ; SrcIdx = SrcIdx % Mask . size ( ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && ( ( SrcIdx == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) || Subtarget . hasSSE41 ( ) ) ) { assert ( SrcSVT == VT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , SrcSVT , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ; } if ( ( SrcVT == <STR_LIT> && Subtarget . hasSSE2 ( ) ) || ( SrcVT == <STR_LIT> && Subtarget . hasSSE41 ( ) ) ) { assert ( VT . getSizeInBits ( ) >= SrcSVT . getSizeInBits ( ) && <STR_LIT> ) ; unsigned OpCode = ( SrcVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( OpCode , dl , <STR_LIT> , SrcOp , DAG . getIntPtrConstant ( SrcIdx , dl ) ) ;

return DAG . getZExtOrTrunc ( ExtOp , dl , VT ) ;


<s> case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVDUPLANECombine ( N , DCI ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> :

case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ;


<s> setISALevelAndRevisionFromPredicates ( P ) ; setGPRSizeFromPredicates ( P ) ; setCPR1SizeFromPredicates ( P ) ; setASESetFromPredicates ( P ) ;


<s> static SDValue Expand64BitShift ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ;

if ( ST -> isThumb1Only ( ) ) return SDValue ( ) ;


<s> void WasmPEI :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < StackProtector > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> void <ISA_LIT>ScoreboardHazardRecognizer :: EmitInstruction ( SUnit * SU ) { const MCInstrDesc * MCID = DAG -> getInstrDesc ( SU ) ; if ( ! MCID ) return ; ScoreboardHazardRecognizer :: EmitInstruction ( SU ) ;


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Custom ) ;


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; unsigned ElementBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ;


<s> static EVT getMemVTFromNode ( LLVMContext & Ctx , SDNode * Root ) { if ( isa < MemSDNode > ( Root ) ) return cast < MemSDNode > ( Root ) -> getMemoryVT ( ) ; const unsigned Opcode = Root -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) return EVT ( ) ; const unsigned IntNo = cast < ConstantSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo != <STR_LIT> ) return EVT ( ) ; return getPackedVectorTypeFromPredicateType ( Ctx , Root -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ) ;


<s> return __builtin_aarch64_reduc_smax_scal_v8qi ( __a ) ;


<s> for ( Function & F : M ) for ( auto & BB : F ) for ( auto & I : BB ) { if ( ToBeDeleted ) { ToBeDeleted -> eraseFromParent ( ) ; ToBeDeleted = nullptr ; } auto * Call = dyn_cast < CallInst > ( & I ) ; if ( ! Call ) continue ; auto * GV = dyn_cast < GlobalValue > ( Call -> getCalledOperand ( ) ) ;


<s> IsThumb = false ; return ; case MCAF_Code64 : return ; case MCAF_SubsectionsViaSymbols : return ; }


<s> if ( size == <NUM_LIT> && aligned_p && GET_CODE ( x ) == CONST_INT && INTVAL ( x ) < INT_MIN ) { fprintf ( asm_out_file , <STR_LIT> HOST_WIDE_INT_PRINT_HEX <STR_LIT> , INTVAL ( x ) ) ;


<s> bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( ( Unsafe || ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) ) ) { if ( CLHS -> isExactlyValue ( <NUM_LIT> ) ) {

if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ;


<s> if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerVectorShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ;


<s> <ISA_LIT>CA53Erratum843419Stub :: <ISA_LIT>CA53Erratum843419Stub ( const uint32_t * pData , size_t pSize , const char * pName , const_fixup_iterator pBegin , const_fixup_iterator pEnd ) : <ISA_LIT>CA53ErratumStub ( pData , pSize , pName , pBegin , pEnd ) {


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> case Type :: DoubleTyID : return <STR_LIT> ; case Type :: VectorTyID : { auto VecTy = cast < VectorType > ( Ty ) ; auto ElTy = VecTy -> getElementType ( ) ; auto NumElements = VecTy -> getVectorNumElements ( ) ; return ( Twine ( getTypeName ( ElTy , Signed ) ) + Twine ( NumElements ) ) . str ( ) ; } default :


<s> assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ;


<s> if ( <STR_LIT> ( DstMO . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( LHSMO . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( RHSMO . getReg ( ) ) < <NUM_LIT> && <STR_LIT> ( AccMO . getReg ( ) ) < <NUM_LIT> && DstMO . getReg ( ) == AccMO . getReg ( ) ) { MachineOperand Lhs ( LHSMO ) ; MachineOperand Rhs ( RHSMO ) ; MachineOperand Src ( AccMO ) ;


<s> static int getContinueNzeroOpcode ( int oldOpcode ) { switch ( oldOpcode ) { case AMDGPU :: JUMP : return AMDGPU :: CONTINUE_LOGICALNZ_i32 ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; } ; return - <NUM_LIT> ;


<s> breakPartialRegDependency ( MachineBasicBlock :: iterator MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( MI -> killsRegister ( Reg , TRI ) ) return ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned Opc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI -> addRegisterKilled ( Reg , TRI , true ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI -> addRegisterKilled ( Reg , TRI , true ) ;


<s> void <ISA_LIT>MCCodeEmitter :: emitBitsWithParity ( raw_ostream & OS , uint16_t Bits ) {

uint16_t Encoding = getEncodingWithParity ( Bits ) ;


<s> void frv_expand_builtin_va_start ( tree valist , rtx nextarg ) { tree t ; int num = cfun -> args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS ; nextarg = gen_rtx_PLUS ( Pmode , virtual_incoming_args_rtx , GEN_INT ( UNITS_PER_WORD * num ) ) ; if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> , cfun -> args_info , num ) ; debug_rtx ( nextarg ) ; } t = build ( MODIFY_EXPR , TREE_TYPE ( valist ) , valist , make_tree ( ptr_type_node , nextarg ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ;


<s> MCSymbol * GVSym = getSymbol ( GV ) ; const Constant * C = GV -> getInitializer ( ) ; unsigned Align = ( unsigned ) DL . getPreferredTypeAlignmentShift ( C -> getType ( ) ) ; getTargetStreamer ( ) . emitCCTopData ( GVSym -> getName ( ) ) ; switch ( GV -> getLinkage ( ) ) { case GlobalValue :: AppendingLinkage : report_fatal_error ( <STR_LIT> ) ; case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : case GlobalValue :: ExternalLinkage : case GlobalValue :: CommonLinkage : emitArrayBound ( GVSym , GV ) ; OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_Global ) ; if ( GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) || GV -> hasCommonLinkage ( ) ) OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_Weak ) ; LLVM_FALLTHROUGH ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; default : llvm_unreachable ( <STR_LIT> ) ; } EmitAlignment ( Align > <NUM_LIT> ? Align : <NUM_LIT> , GV ) ; if ( GV -> isThreadLocal ( ) ) { report_fatal_error ( <STR_LIT> ) ; } unsigned Size = DL . getTypeAllocSize ( C -> getType ( ) ) ; if ( MAI -> hasDotTypeDotSizeDirective ( ) ) { OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_ELF_TypeObject ) ; OutStreamer -> emitELFSize ( cast < MCSymbolELF > ( GVSym ) , MCConstantExpr :: create ( Size , OutContext ) ) ; } OutStreamer -> EmitLabel ( GVSym ) ; EmitGlobalConstant ( DL , C ) ;

if ( Size < <NUM_LIT> ) OutStreamer -> EmitZeros ( <NUM_LIT> - Size ) ;


<s> initialize<ISA_LIT>FoldOperandsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> void addAlignedMemory16Operands ( MCInst & Inst , unsigned N ) const {


<s> case ABI_AIX : ret = ( TARGET_32BIT ) ? <NUM_LIT> : <NUM_LIT> ; break ; case ABI_ELFv2 : gcc_assert ( ! TARGET_32BIT ) ;


<s> c = ( __v4sf ) vec_cmpeq ( a , b ) ; c = vec_nor ( c , c ) ;

return ( ( __m128 ) vec_sel ( ( __v4sf ) __A , c , mask ) ) ;


<s> initialize<ISA_LIT>GenPredicatePass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> static const unsigned Regs01 [ ] = { LC0 , SA0 , LC1 , SA1 } ; static const unsigned Regs1 [ ] = { LC1 , SA1 } ; auto CheckRegs = IsInnerHWLoop ? makeArrayRef ( Regs01 , array_lengthof ( Regs01 ) ) : makeArrayRef ( Regs1 , array_lengthof ( Regs1 ) ) ; for ( unsigned R : CheckRegs ) if ( MI -> modifiesRegister ( R , TRI ) ) return true ;


<s> case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ;


<s> return ( CachePolicy >> <NUM_LIT> ) & <NUM_LIT> ;


if ( FpABI == FpABIKind :: XX ) return ( uint8_t ) <STR_LIT> ;


<s> switch ( pa_cpu ) { case PROCESSOR_700 : return <NUM_LIT> ; case PROCESSOR_7100 : return <NUM_LIT> ; case PROCESSOR_7100LC : return <NUM_LIT> ; case PROCESSOR_7200 : return <NUM_LIT> ; case PROCESSOR_7300 : return <NUM_LIT> ;

case PROCESSOR_8000 : return <NUM_LIT> ;


<s> } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ;

SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ;


<s> emitIfBreak ( MI ) ; break ; case <STR_LIT> : emitLoop ( MI ) ; break ; case <STR_LIT> : MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; break ; case <STR_LIT> : SplitBB = emitEndCf ( MI ) ; break ; default : assert ( false && <STR_LIT> ) ; break ; } MachineBasicBlock :: iterator Next ; for ( I = Prev ? Prev -> getIterator ( ) : MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MaskMI = * I ; switch ( MaskMI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : combineMasks ( MaskMI ) ; break ; default :


<s> BuildDAG ( const Region & R , GCNIterativeScheduler & _Sch ) : Sch ( _Sch ) { auto BB = R . Begin -> getParent ( ) ; Sch . BaseClass :: startBlock ( BB ) ;

Sch . BaseClass :: enterRegion ( BB , R . Begin , R . End , R . NumRegionInstrs ) ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FramePointerSaveIndex ( <NUM_LIT> ) , ReturnAddrSaveIndex ( <NUM_LIT> ) , BasePointerSaveIndex ( <NUM_LIT> ) , HasSpills ( false ) , HasNonRISpills ( false ) , SpillsCR ( false ) , SpillsVRSAVE ( false ) , LRStoreRequired ( false ) , MinReservedArea ( <NUM_LIT> ) , TailCallSPDelta ( <NUM_LIT> ) , HasFastCall ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgsStackOffset ( <NUM_LIT> ) , VarArgsNumGPR ( <NUM_LIT> ) , VarArgsNumFPR ( <NUM_LIT> ) , CRSpillFrameIndex ( <NUM_LIT> ) {


<s> EmitMoveRegReg ( false , Reg32 , Reg32 , Out ) ;


<s> if ( ! Subtarget -> inMicro<ISA_LIT>Mode ( ) || ! Subtarget -> has<ISA_LIT>32r2 ( ) || Subtarget -> has<ISA_LIT>32r6 ( ) ) return false ; <ISA_LIT>II = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; bool Modified = false ;

MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const {

if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ;


<s> Code32Directive = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UseDataRegionDirectives = false ; WeakRefDirective = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseIntegratedAssembler = true ;


<s> bool <ISA_LIT>ExpandCondsets :: splitInBlock ( MachineBasicBlock & B , std :: set < unsigned > & UpdRegs ) { bool Changed = false ; MachineBasicBlock :: iterator I , E , NextI ; for ( I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { NextI = std :: next ( I ) ; if ( isCondset ( * I ) ) Changed |= split ( * I , UpdRegs ) ; }


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) , TSInfo ( ) {


<s> static SDValue EmitTailCallStoreRetAddr ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue RetAddrFrIdx , EVT PtrVT , unsigned SlotSize , int FPDiff , const SDLoc & dl ) {


<s> if ( GET_CODE ( countop ) == CONST_INT ) { int count = INTVAL ( countop ) ; if ( count > signpos ) { int offset = ( count & ~ signpos ) / <NUM_LIT> ; count = count & signpos ; ops [ <NUM_LIT> ] = dataop = adjust_address ( dataop , QImode , offset ) ; } if ( code == EQ || code == NE ) { if ( count == <NUM_LIT> ) { output_asm_insn ( <STR_LIT> , ops ) ; return code == EQ ? PLUS : MINUS ; }


<s> fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ; break ; case SYMBOL_REF : output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; break ; case CONST : { rtx plus = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( plus , <NUM_LIT> ) ) == SYMBOL_REF && CONST_INT_P ( XEXP ( plus , <NUM_LIT> ) ) ) { output_addr_const ( file , XEXP ( plus , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , INTVAL ( XEXP ( plus , <NUM_LIT> ) ) , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else abort ( ) ; } break ; default : abort ( ) ;


<s> return MI -> getOperand ( TII -> getOperandIdx ( MI -> getOpcode ( ) , <STR_LIT> :: Enabled ) ) . getImm ( ) ;


<s> static MachineBasicBlock :: iterator findIncDecAfter ( MachineBasicBlock :: iterator MBBI , Register Reg , <STR_LIT> Pred , Register PredReg , int & Offset , const TargetRegisterInfo * TRI ) { Offset = <NUM_LIT> ; MachineBasicBlock & MBB = * MBBI -> getParent ( ) ; MachineBasicBlock :: iterator EndMBBI = MBB . end ( ) ; MachineBasicBlock :: iterator NextMBBI = std :: next ( MBBI ) ; while ( NextMBBI != EndMBBI ) { while ( NextMBBI != EndMBBI && NextMBBI -> isDebugInstr ( ) ) ++ NextMBBI ; if ( NextMBBI == EndMBBI ) return EndMBBI ; unsigned Off = isIncrementOrDecrement ( * NextMBBI , Reg , Pred , PredReg ) ; if ( Off ) { Offset = Off ; return NextMBBI ;


<s> } else if ( type == long_long_unsigned_type_node || type == long_long_integer_type_node ) error ( <STR_LIT> <STR_LIT> ) ; else if ( type == double_type_node ) error ( <STR_LIT> ) ; } switch ( altivec_type ) { case 'v' : unsigned_p = TYPE_UNSIGNED ( type ) ; switch ( mode ) { case TImode : result = ( unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node ) ; break ; case DImode : result = ( unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node ) ; break ; case SImode : result = ( unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node ) ; break ; case HImode : result = ( unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node ) ; break ; case QImode : result = ( unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node ) ; break ; case SFmode : result = V4SF_type_node ; break ; case DFmode : result = V2DF_type_node ; break ; case V4SImode : case V8HImode : case V16QImode : case V4SFmode : case V2DImode : case V2DFmode : result = type ; default : break ; } break ; case 'b' : switch ( mode ) { case DImode : case V2DImode : result = bool_V2DI_type_node ; break ; case SImode : case V4SImode : result = bool_V4SI_type_node ; break ;

case HImode : case V8HImode : result = bool_V8HI_type_node ; break ;


<s> __rv . __o = __builtin_neon_vld2_dupv4hi ( ( const __builtin_neon_hi * ) __a ) ;


<s> if ( auto * LI = dyn_cast < LoadInst > ( & I ) ) if ( LI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; if ( auto * AI = dyn_cast < AtomicRMWInst > ( & I ) ) if ( AI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; if ( auto * AI = dyn_cast < AtomicCmpXchgInst > ( & I ) ) if ( AI -> isAtomic ( ) ) return MachineMemOperand :: MOVolatile ; return MachineMemOperand :: MONone ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; assert ( ( Subtarget -> isTargetLinux ( ) || Subtarget -> isTargetDarwin ( ) ) && <STR_LIT> ) ; assert ( Op . getNode ( ) -> getNumOperands ( ) == <NUM_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; unsigned Align = Op . getConstantOperandVal ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT ArgVT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getTargetData ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! getTargetMachine ( ) . Options . UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> getFnAttributes ( ) . hasNoImplicitFloatAttr ( ) ) && Subtarget -> hasSSE1 ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ; InstOps . push_back ( SrcPtr ) ; InstOps . push_back ( DAG . getConstant ( ArgSize , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( ArgMode , <STR_LIT> ) ) ; InstOps . push_back ( DAG . getConstant ( Align , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( getPointerTy ( ) , <STR_LIT> ) ; SDValue VAARG = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , & InstOps [ <NUM_LIT> ] , InstOps . size ( ) , <STR_LIT> , MachinePointerInfo ( SV ) , <NUM_LIT> , false , true , true ) ;

Chain = VAARG . getValue ( <NUM_LIT> ) ;


<s> MachineRegisterInfo & RI = MF . getRegInfo ( ) ; unsigned MaxAlign = calculateMaxStackAlignment ( FFI ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ; RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) MaxAlign = std :: max ( MaxAlign , RI . getRegClass ( RegNum ) -> getAlignment ( ) ) ; FFI -> setMaxAlignment ( MaxAlign ) ;


<s> return ( __m128d ) __builtin_ia32_compressdf128_mask ( ( __v2df ) __A , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> int <ISA_LIT>FrameInfo :: getFrameIndexOffset ( const MachineFunction & MF , int FI ) const { unsigned FrameReg ;

return getFrameIndexReference ( MF , FI , FrameReg ) ;


<s> BuildMI ( MBB , J , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; ++ FilledSlots ; Changed = true ; }


<s> if ( FrameRegUpdate && * FrameRegUpdate ) LoopSize -= LoopSize % <NUM_LIT> ; MachineInstr * LoopI = BuildMI ( * MBB , InsertI , DL , TII -> get ( ZeroData ? <STR_LIT> : <STR_LIT> ) ) . addDef ( SizeReg ) . addDef ( BaseReg ) . addImm ( LoopSize ) . addReg ( BaseReg ) . setMemRefs ( CombinedMemRefs ) ; if ( FrameRegUpdate ) LoopI -> setFlags ( FrameRegUpdateFlags ) ; int64_t ExtraBaseRegUpdate = FrameRegUpdate ? ( * FrameRegUpdate - FrameRegOffset . getBytes ( ) - Size ) : <NUM_LIT> ; if ( LoopSize < Size ) { assert ( FrameRegUpdate ) ;

assert ( Size - LoopSize == <NUM_LIT> ) ;


TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff ) ;


<s> static DecodeStatus DecodeBranchImmInstruction ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned pred = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( pred == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; imm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ;


<s> poly8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ;


<s> case <ISA_LIT>Subtarget :: N64 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: EABI : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> rtx mem = gen_rtx_MEM ( GET_MODE ( operands [ <NUM_LIT> ] ) , copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ; MEM_COPY_ATTRIBUTES ( mem , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = mem ; } return <NUM_LIT> ; } operands [ <NUM_LIT> ] = force_reg ( QImode , operands [ <NUM_LIT> ] ) ; { rtx res = gen_reg_rtx ( QImode ) ; switch ( code ) { case AND : emit_insn ( gen_andqi3_1 ( res , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; break ; case IOR : emit_insn ( gen_iorqi3_1 ( res , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ;


<s> static bool tilegx_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { return ! IN_RANGE ( int_size_in_bytes ( type ) , <NUM_LIT> , TILEGX_NUM_RETURN_REGS * UNITS_PER_WORD ) ;


if ( ( <NUM_LIT> << sparc_cpu ) & ( ( <NUM_LIT> << PROCESSOR_SUPERSPARC ) | ( <NUM_LIT> << PROCESSOR_HYPERSPARC ) | ( <NUM_LIT> << PROCESSOR_SPARCLITE86X ) ) ) return <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printModImmOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { MCOperand Op = MI -> getOperand ( OpNum ) ; if ( Op . isExpr ( ) ) return printOperand ( MI , OpNum , STI , O ) ; unsigned Bits = Op . getImm ( ) & <NUM_LIT> ; unsigned Rot = ( Op . getImm ( ) & <NUM_LIT> ) >> <NUM_LIT> ;


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; assert ( VA . getLocInfo ( ) == CCValAssign :: Full && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


<s> if ( <STR_LIT> == R ) continue ; if ( <STR_LIT> == R ) SoftDefs . insert ( R ) ; else if ( isPredicateRegister ( R ) && <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) ) LatePreds . insert ( R ) ; else Defs [ R ] . insert ( PredSense ( PredReg , isTrue ) ) ; } for ( unsigned i = <NUM_LIT> ; i < MCID . getNumDefs ( ) ; ++ i ) { unsigned R = MCI . getOperand ( i ) . getReg ( ) , S = <STR_LIT> ; if ( R == <STR_LIT> ) R = <STR_LIT> ; if ( <ISA_LIT>MCInstrInfo :: IsReverseVecRegPair ( R ) ) ReversePairs . insert ( R ) ; for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ; SRI . isValid ( ) ; ++ SRI ) { if ( MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) continue ; if ( R == * SRI ) { if ( S == R ) continue ; else S = R ;


<s> LocalMemLimit = ST . getLocalMemorySize ( ) ; if ( LocalMemLimit == <NUM_LIT> ) return false ; const DataLayout & DL = Mod -> getDataLayout ( ) ; CurrentLocalMemUsage = <NUM_LIT> ; for ( GlobalVariable & GV : Mod -> globals ( ) ) { if ( GV . getType ( ) -> getAddressSpace ( ) != AS . LOCAL_ADDRESS ) continue ; for ( const User * U : GV . users ( ) ) { const Instruction * Use = dyn_cast < Instruction > ( U ) ; if ( ! Use ) continue ; if ( Use -> getParent ( ) -> getParent ( ) == & F ) { unsigned Align = GV . getAlignment ( ) ; if ( Align == <NUM_LIT> ) Align = DL . getABITypeAlignment ( GV . getValueType ( ) ) ; uint64_t AllocSize = DL . getTypeAllocSize ( GV . getValueType ( ) ) ; CurrentLocalMemUsage = alignTo ( CurrentLocalMemUsage , Align ) ; CurrentLocalMemUsage += AllocSize ; break ; } }


<s> AU . addRequired < MemorySSAWrapperPass > ( ) ; AU . setPreservesAll ( ) ;


<s> CalleeAmt *= - <NUM_LIT> ; unsigned StackReg = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ADDInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned LISInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ORIInstr = is64Bit ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = I ; DebugLoc dl = MI -> getDebugLoc ( ) ; if ( isInt < <NUM_LIT> > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & <NUM_LIT> ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) ) . addReg ( StackReg ) . addReg ( StackReg ) . addReg ( TmpReg ) ;


<s> const <ISA_LIT>GOT & <ISA_LIT>GNULDBackend :: getGOT ( ) const { assert ( m_pGOT != NULL ) ; return * m_pGOT ;


<s> case <STR_LIT> : { if ( getTargetMachine ( ) . getOptLevel ( ) > CodeGenOpt :: None ) return performMinMaxCombine ( N , DCI ) ; break ; } case <STR_LIT> : return performFMACombine ( N , DCI ) ; case <STR_LIT> : { if ( SDValue Widended = widenLoad ( cast < LoadSDNode > ( N ) , DCI ) ) return Widended ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performZeroExtendCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : return performRcpCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performCvtF32UByteNCombine ( N , DCI ) ; case <STR_LIT> : return performFMed3Combine ( N , DCI ) ; case <STR_LIT> : return performCvtPkRTZCombine ( N , DCI ) ; case <STR_LIT> : return performClampCombine ( N , DCI ) ; case <STR_LIT> : { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDLoc SL ( N ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT EltVT = Src . getValueType ( ) ;

if ( EltVT == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ;


<s> if ( ( ( from ) == FRAME_POINTER_REGNUM ) && ( ( to ) == STACK_POINTER_REGNUM ) ) return ( ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : <NUM_LIT> ) ; else if ( ( ( from ) == ARG_POINTER_REGNUM ) && ( ( to ) == FRAME_POINTER_REGNUM ) ) return ( current_frame_info . reg_size + current_frame_info . var_size ) ;

else if ( ( ( from ) == ARG_POINTER_REGNUM ) && ( ( to ) == STACK_POINTER_REGNUM ) ) return ( current_frame_info . reg_size + current_frame_info . var_size + ( ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : <NUM_LIT> ) ) ;


<s> MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> if ( call_used_regs [ i ] > <NUM_LIT> ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) MMX_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; if ( ! TARGET_SSE ) for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) SSE_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) FLOAT_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; if ( ! TARGET_AVX512F ) { for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ;


<s> const LegalizerInfo * <ISA_LIT>Subtarget :: getLegalizerInfo ( ) const {


<s> unsigned SrcLo = HRI . getSubReg ( SrcR , <STR_LIT> ) ; unsigned SrcHi = HRI . getSubReg ( SrcR , <STR_LIT> ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool Is128B = HST . useHVXDblOps ( ) ; auto * RC = ! Is128B ? & <STR_LIT> : & <STR_LIT> ; unsigned Size = RC -> getSize ( ) ; unsigned NeedAlign = RC -> getAlignment ( ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc ; if ( NeedAlign <= HasAlign ) StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcLo , getKillRegState ( IsKill ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; if ( NeedAlign <= MinAlign ( HasAlign , Size ) ) StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; else StoreOpc = ! Is128B ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( Size ) . addReg ( SrcHi , getKillRegState ( IsKill ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; B . erase ( It ) ; return true ;


<s> if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ;

return ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {

addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } break ; } case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } break ; } case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ;


<s> ExtExpr ( Register RS , bool NG , unsigned SH ) : Rs ( RS ) , S ( SH ) , Neg ( NG ) {


<s> const struct real_value * rv = CONST_DOUBLE_REAL_VALUE ( operand ) ; gcc_assert ( GET_MODE ( operand ) == SFmode ) ;

REAL_VALUE_TO_TARGET_SINGLE ( * rv , value ) ;


<s> return instAccessReg ( MI -> uses ( ) , Reg , SubReg , TRI ) ;


<s> SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; if ( CC == <STR_LIT> ) { if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return MaterializeSETB ( DL , NewEFLAGS , DAG ) ; } } if ( CC == <STR_LIT> ) return MaterializeSETB ( DL , EFLAGS , DAG ) ;

if ( SDValue Flags = combineSetCCEFLAGS ( EFLAGS , CC , DAG ) ) {


<s> if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = ( bytes + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) mode = type_natural_mode ( type , cum , false ) ; if ( TARGET_64BIT && ( cum ? cum -> call_abi : ix86_abi ) == MS_ABI ) arg = function_arg_ms_64 ( cum , mode , omode , named , bytes ) ; else if ( TARGET_64BIT ) arg = function_arg_64 ( cum , mode , omode , type , named ) ; else arg = function_arg_32 ( cum , mode , omode , type , bytes , words ) ;


<s> WidenedMask . assign ( Mask . size ( ) / <NUM_LIT> , <NUM_LIT> ) ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; i += <NUM_LIT> ) { if ( Mask [ i ] == SM_SentinelUndef && Mask [ i + <NUM_LIT> ] == SM_SentinelUndef ) { WidenedMask [ i / <NUM_LIT> ] = SM_SentinelUndef ; continue ; } if ( Mask [ i ] == SM_SentinelUndef && Mask [ i + <NUM_LIT> ] >= <NUM_LIT> && Mask [ i + <NUM_LIT> ] % <NUM_LIT> == <NUM_LIT> ) { WidenedMask [ i / <NUM_LIT> ] = Mask [ i + <NUM_LIT> ] / <NUM_LIT> ; continue ; } if ( Mask [ i + <NUM_LIT> ] == SM_SentinelUndef && Mask [ i ] >= <NUM_LIT> && Mask [ i ] % <NUM_LIT> == <NUM_LIT> ) { WidenedMask [ i / <NUM_LIT> ] = Mask [ i ] / <NUM_LIT> ; continue ; }

if ( Mask [ i ] == SM_SentinelZero || Mask [ i + <NUM_LIT> ] == SM_SentinelZero ) {


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitCMN ( MachineOperand & LHS , MachineOperand & RHS , MachineIRBuilder & MIRBuilder ) const {

MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ;


<s> int regno ; if ( reload_completed && ! c4x_assembler_function_p ( ) && ! c4x_interrupt_function_p ( ) && ! current_function_calls_alloca && ! current_function_args_size && ! ( optimize < <NUM_LIT> ) && ! get_frame_size ( ) ) { for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno >= <NUM_LIT> ; regno -- ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] && ( regno != AR3_REGNO ) ) return <NUM_LIT> ;


<s> SDValue PackedOp = Op . getOperand ( <NUM_LIT> ) ; EVT OutVT = Op . getValueType ( ) ; EVT InVT = PackedOp . getValueType ( ) ;

unsigned ToBits = OutVT . getVectorElementType ( ) . getSizeInBits ( ) ;


if ( strcmp ( <STR_LIT> , cris_tune_str ) == <NUM_LIT> ) cris_tune = <NUM_LIT> ;


<s> if ( isAllOnes ( Mask ) ) return Op ; if ( MaskVT . bitsGT ( Mask . getValueType ( ) ) ) { EVT newMaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , MaskVT . getSizeInBits ( ) ) ; VMask = DAG . getBitcast ( MaskVT , DAG . getNode ( <STR_LIT> , dl , newMaskVT , Mask ) ) ; } else { EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Mask . getValueType ( ) . getSizeInBits ( ) ) ; VMask = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ;


<s> nextarg = gen_rtx_PLUS ( Pmode , virtual_incoming_args_rtx , GEN_INT ( UNITS_PER_WORD * num ) ) ; if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> , crtl -> args . info , num ) ;


<s> if ( ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = RHS -> getSExtValue ( ) ;

if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Log2_32 ( Size ) ) ) return false ;


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override {


if ( INTVAL ( ma ) == MASK_ANY ) return INVALID_ATTRIBUTE ;


<s> FuncReturnHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder & MIB , CCAssignFn * AssignFn ) : ValueHandler ( MIRBuilder , MRI , AssignFn ) , MIB ( MIB ) {


<s> if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> , false ) ; Type = A_SD -> isExternal ( ) ? ( unsigned ) MachO :: GENERIC_RELOC_SECTDIFF : ( unsigned ) MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: GENERIC_RELOC_SECTDIFF || Type == MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( <NUM_LIT> << <NUM_LIT> ) | ( MachO :: GENERIC_RELOC_PAIR << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ; MRE . r_word1 = Value2 ; Writer -> addRelocation ( nullptr , Fragment -> getParent ( ) , MRE ) ; } else { if ( FixupOffset > <NUM_LIT> ) { FixedValue = OriginalFixedValue ; return false ; } } MachO :: any_relocation_info MRE ; MRE . r_word0 = ( ( FixupOffset << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ;


<s> assert ( ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX2 ( ) || Domain < <NUM_LIT> ) && <STR_LIT> ) ; table = lookupAVX2 ( MI -> getOpcode ( ) , dom ) ; } assert ( table && <STR_LIT> ) ;

MI -> setDesc ( get ( table [ Domain - <NUM_LIT> ] ) ) ;


<s> return flag_pic != <NUM_LIT> ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return true ; else return flag_pic != <NUM_LIT> ; case CONST : return sparc_cannot_force_const_mem ( XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : return sparc_cannot_force_const_mem ( XEXP ( x , <NUM_LIT> ) ) || sparc_cannot_force_const_mem ( XEXP ( x , <NUM_LIT> ) ) ;


<s> if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ;

return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override {


<s> return __builtin_ia32_vec_ext_v2di ( ( __v2di ) __X , __N ) ;


<s> const MCOperand & IndexReg = MI -> getOperand ( Op + <STR_LIT> ) ; const MCOperand & DispSpec = MI -> getOperand ( Op + <STR_LIT> ) ; const MCOperand & SegReg = MI -> getOperand ( Op + <STR_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <STR_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! BaseReg . getReg ( ) ) ) O << formatImm ( DispVal ) ; } else {

assert ( DispSpec . isExpr ( ) && <STR_LIT> ) ;


<s> high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ; high = riscv_force_temporary ( temp , high , FALSE ) ; reg = riscv_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) , FALSE ) ; }

return plus_constant ( Pmode , reg , offset ) ;


<s> if ( MI . isCall ( ) ) { if ( doesNotReturn ( MI ) ) return true ;

for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ;


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ;


<s> if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V1 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V1 , Mask , Subtarget , DAG ) ) return Rotate ; SmallVector < int , <NUM_LIT> > MutableMask ( Mask . begin ( ) , Mask . end ( ) ) ; return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , MutableMask , Subtarget , DAG ) ; } assert ( llvm :: any_of ( Mask , [ ] ( int M ) { return M >= <NUM_LIT> && M < <NUM_LIT> ; } ) && <STR_LIT> <STR_LIT> ) ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BitBlend ;

if ( SDValue V = lowerVectorShuffleAsByteShiftMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ;


<s> return __builtin_ia32_rcpph128_mask ( __B , _mm_setzero_ph ( ) , __A ) ;


<s> if ( Cmp == APFloat :: cmpGreaterThan ) return SDValue ( ) ; EVT VT = K0 -> getValueType ( <NUM_LIT> ) ; if ( Subtarget -> enableDX10Clamp ( ) ) { if ( K1 -> isExactlyValue ( <NUM_LIT> ) && K0 -> isExactlyValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; }

if ( VT == <STR_LIT> || ( VT == <STR_LIT> && ! Subtarget -> hasMed3_16 ( ) ) ) return SDValue ( ) ;


<s> if ( ! TPC ) return false ; const TargetMachine & TM = TPC -> getTM < TargetMachine > ( ) ; bool Changed = false ; for ( auto * U : F . users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( ! CI ) continue ; Function * Caller = CI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( TM , * Caller ) ; Changed |= ST . makeLIDRangeMetadata ( CI ) ; }


<s> <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & st ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) , ST ( st ) {


<s> assert ( CPI < MCP -> getConstants ( ) . size ( ) && <STR_LIT> ) ; unsigned Align = MCP -> getConstants ( ) [ CPI ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; return Log2_32 ( Align ) ;


<s> if ( Subtarget . isAIXABI ( ) ) report_fatal_error ( <STR_LIT> ) ;


<s> SDValue AddcOp0 = AddcNode -> getOperand ( <NUM_LIT> ) ; SDValue AddcOp1 = AddcNode -> getOperand ( <NUM_LIT> ) ; if ( AddcOp0 . getNode ( ) == AddcOp1 . getNode ( ) ) return SDValue ( ) ; assert ( AddcNode -> getNumValues ( ) == <NUM_LIT> && AddcNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && AddcNode -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( AddcOp0 -> getOpcode ( ) != <STR_LIT> && AddcOp0 -> getOpcode ( ) != <STR_LIT> && AddcOp1 -> getOpcode ( ) != <STR_LIT> && AddcOp1 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDNode * AddeNode = AddcNode -> getGluedUser ( ) ; if ( AddeNode == NULL ) return SDValue ( ) ; if ( AddeNode -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( AddeNode -> getNumOperands ( ) == <NUM_LIT> && AddeNode -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue AddeOp0 = AddeNode -> getOperand ( <NUM_LIT> ) ; SDValue AddeOp1 = AddeNode -> getOperand ( <NUM_LIT> ) ; if ( AddeOp0 . getNode ( ) == AddeOp1 . getNode ( ) ) return SDValue ( ) ; bool IsLeftOperandMUL = false ; SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ;

if ( MULOp == SDValue ( ) ) return SDValue ( ) ;


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ;


<s> case MCSymbolRefExpr :: VK_None : break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ;


<s> else Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;


<s> t = unw_decode_uleb128 ( & dp ) ; UNW_DEC_EPILOGUE ( B2 , t , ( code & <NUM_LIT> ) , arg ) ; return dp ;


<s> if ( GENERAL_REGNO_P ( regno ) && ! call_really_used_regs [ regno ] && cfun_gpr_save_slot ( regno ) == SAVE_SLOT_NONE ) return false ; return true ;


<s> if ( isPowerOf2_32 ( ~ Imm ) ) { NewImm = countTrailingOnes ( Imm ) ; Opc = <STR_LIT> ; } else if ( <STR_LIT> ( ~ Imm , ST . hasInv2PiInlineImm ( ) ) ) { NewImm = ~ Imm ; Opc = <STR_LIT> ; } } else if ( Opc == <STR_LIT> ) { if ( isPowerOf2_32 ( Imm ) ) { NewImm = countTrailingZeros ( Imm ) ; Opc = <STR_LIT> ; } else if ( <STR_LIT> ( ~ Imm , ST . hasInv2PiInlineImm ( ) ) ) { NewImm = ~ Imm ; Opc = <STR_LIT> ; } } else if ( Opc == <STR_LIT> ) { if ( <STR_LIT> ( ~ Imm , ST . hasInv2PiInlineImm ( ) ) ) { NewImm = ~ Imm ; Opc = <STR_LIT> ; } } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && SrcImm == Src0 ) { if ( ! TII -> commuteInstruction ( MI , false , <NUM_LIT> , <NUM_LIT> ) ) NewImm = <NUM_LIT> ; } if ( NewImm != <NUM_LIT> ) { if ( Register :: isVirtualRegister ( Dest -> getReg ( ) ) && SrcReg -> isReg ( ) ) { MRI . setRegAllocationHint ( Dest -> getReg ( ) , <NUM_LIT> , SrcReg -> getReg ( ) ) ; MRI . setRegAllocationHint ( SrcReg -> getReg ( ) , <NUM_LIT> , Dest -> getReg ( ) ) ; return true ; } if ( SrcReg -> isReg ( ) && SrcReg -> getReg ( ) == Dest -> getReg ( ) ) { MI . setDesc ( TII -> get ( Opc ) ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { Src0 -> ChangeToImmediate ( NewImm ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Dest -> getReg ( ) , false ) ; MI . tieOperands ( <NUM_LIT> , <NUM_LIT> ) ; } else { SrcImm -> setImm ( NewImm ) ; }


<s> ScalarTargetTransformInfo :: PopcntHwSupport <ISA_LIT>ScalarTargetTransformImpl :: getPopcntHwSupport ( unsigned TyWidth ) const { assert ( isPowerOf2_32 ( TyWidth ) && <STR_LIT> ) ;

const <ISA_LIT>Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> else if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret |= IX86_CALLCVT_STDCALL ; else if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret |= IX86_CALLCVT_FASTCALL ; else if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret |= IX86_CALLCVT_THISCALL ; if ( ( ret & ( IX86_CALLCVT_THISCALL | IX86_CALLCVT_FASTCALL ) ) == <NUM_LIT> ) { if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret |= IX86_CALLCVT_REGPARM ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) ret |= IX86_CALLCVT_SSEREGPARM ; } if ( IX86_BASE_CALLCVT ( ret ) != <NUM_LIT> ) return ret ;


<s> virtual ~ <ISA_LIT>PostRASchedStrategy ( ) {


<s> bool onOffset ( const MCExpr * Val , SMLoc OffsetLoc , StringRef ID , const InlineAsmIdentifierInfo & IDInfo , bool ParsingInlineAsm , StringRef & ErrMsg ) { PrevState = State ; switch ( State ) { default : ErrMsg = <STR_LIT> ; return true ; case IES_PLUS : case IES_INIT : case IES_LBRAC : if ( setSymRef ( Val , ID , ErrMsg ) ) return true ;


<s> SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;

SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr ; return true ;


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedGather ( Type * Ty , MaybeAlign Alignment ) { if ( ! EnableMaskedGatherScatters || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( isa < VectorType > ( Ty ) ) return false ; unsigned EltWidth = Ty -> getScalarSizeInBits ( ) ; return ( ( EltWidth == <NUM_LIT> && ( ! Alignment || Alignment >= <NUM_LIT> ) ) || ( EltWidth == <NUM_LIT> && ( ! Alignment || Alignment >= <NUM_LIT> ) ) || EltWidth == <NUM_LIT> ) ;


<s> MVT SVT = Vec . getSimpleValueType ( ) . getScalarType ( ) ; MVT VT = <STR_LIT> ( SVT , WideNumElts ) ;

return widenSubVector ( VT , Vec , ZeroNewElements , Subtarget , DAG , dl ) ;


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ;

TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>V9Target ( ) , create<ISA_LIT>Disassembler ) ;


<s> SDLoc DL ( Op ) ; SDValue X = ( Op . getValueType ( ) == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasR2 ) Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Const1 , X ) ; else { SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; } if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res ) ; SDValue LowX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LowX , Res ) ;


<s> bool move_check ( rtx operands [ ] , enum machine_mode mode ) { return true ;


<s> SDNode * ResNode = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; return NULL ; } case <STR_LIT> : { SDValue Zero ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Zero , Zero } ; SDNode * ResNode = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; return NULL ; } case <STR_LIT> : { SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , Ops , <NUM_LIT> ) ; }


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; }


addPass ( create<ISA_LIT>HardwareLoops ( ) ) ;


<s> while ( ! WorkList . empty ( ) ) { Value * Curr = WorkList . back ( ) ; WorkList . pop_back ( ) ; User * CurrUser = dyn_cast < User > ( Curr ) ; if ( CurrUser && ! isa < CallInst > ( Curr ) ) for ( auto & Op : CurrUser -> operands ( ) ) if ( Defs . insert ( Op ) . second ) WorkList . push_back ( Op ) ;


<s> x . v = ( vec_uchar16 ) ( count ) ; x . i [ <NUM_LIT> ] = cnt = <NUM_LIT> - ( x . i [ <NUM_LIT> ] & ~ <NUM_LIT> ) ; x . v = vec_splat ( x . v , <NUM_LIT> ) ;

mask = ( cnt & <NUM_LIT> ) ? vec_splat_u8 ( <NUM_LIT> ) : vec_splat_u8 ( - <NUM_LIT> ) ;


<s> const char * origstr = XSTR ( x , <NUM_LIT> ) ; const char * str ; str = ( * targetm . strip_name_encoding ) ( origstr ) ; assemble_name ( file , str ) ; if ( ! current_function_uses_pic_offset_table ) output_operand_lossage ( <STR_LIT> ) ;


<s> rtx mem ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; fn ( gen_rtx_REG ( mode , regno ) , mem ) ;


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( bool Is64Bit , uint8_t OSABI , bool HasRelocationAddend , raw_pwrite_stream & OS ) {

auto MOTW = llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( Is64Bit , OSABI , HasRelocationAddend ) ;


<s> if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; } } bool isFP = Op1 . getValueType ( ) . getSimpleVT ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , isFP , Op0 , Op1 , DAG ) ; if ( <ISA_LIT>CC == <STR_LIT> ) return SDValue ( ) ; SDValue EFLAGS = EmitCmp ( Op0 , Op1 , <ISA_LIT>CC , DAG ) ; EFLAGS = ConvertCmpIfNecessary ( EFLAGS , DAG ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> ) , EFLAGS ) ;


<s> ArrayRef < MCPhysReg > ArgVGPRs = makeArrayRef ( <STR_LIT> . begin ( ) , <NUM_LIT> ) ; unsigned RegIdx = CCInfo . getFirstUnallocated ( ArgVGPRs ) ; if ( RegIdx == ArgVGPRs . size ( ) ) { int64_t Offset = CCInfo . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; return ArgDescriptor :: createStack ( Offset , Mask ) ; } unsigned Reg = ArgVGPRs [ RegIdx ] ; Reg = CCInfo . AllocateReg ( Reg ) ; assert ( Reg != <STR_LIT> ) ;

MachineFunction & MF = CCInfo . getMachineFunction ( ) ;


<s> RegDefsUses :: RegDefsUses ( TargetMachine & TM ) : TRI ( * TM . getRegisterInfo ( ) ) , Defs ( TRI . getNumRegs ( ) , false ) , Uses ( TRI . getNumRegs ( ) , false ) {


<s> pregs . clear ( ) ; for ( auto succ : SuccMBBs ) { for ( unsigned i = <NUM_LIT> ; i < UnavailPredRegs . size ( ) ; i ++ ) { if ( succ -> getMBB ( ) -> isLiveIn ( UnavailPredRegs [ i ] ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( UnavailPredRegs [ i ] ) << <STR_LIT> << succ -> getMBB ( ) -> getNumber ( ) << <STR_LIT> ) ; pregs . push_back ( UnavailPredRegs [ i ] ) ;


<s> off_t i ; for ( i = <NUM_LIT> ; ; i ++ ) { if ( orig [ i ] == '\0' && equiv [ i ] == '\0' ) return TRUE ; if ( orig [ i ] == '\0' || equiv [ i ] == '\0' ) return FALSE ; if ( orig [ i ] != equiv [ i ] ) { if ( ( orig [ i ] == 'W' || orig [ i ] == 'L' ) && equiv [ i ] == 'Q' ) continue ; if ( ( orig [ i ] == '1' || orig [ i ] == '3' ) && equiv [ i ] == '6' ) continue ;


<s> unsigned <ISA_LIT>InstrInfo :: getFSOpcode ( unsigned OpcCJE ) { switch ( OpcCJE ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const std :: string & sec_name = PAN :: getFrameSectionName ( FnName ) ;


<s> DebugLoc DL = Op . getDebugLoc ( ) ;

const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ;


<s> if ( is<ISA_LIT>64 ( ) ) addRegG8RCOperands ( Inst , N ) ;


<s> if ( ! COffs || COffs -> getZExtValue ( ) != <NUM_LIT> ) return false ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; SDValue Ops [ ] = { Base , getAL ( CurDAG , SDLoc ( N ) ) , CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) , Chain } ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ) ;


<s> if ( type == bool_short_type_node ) return <STR_LIT> ; if ( type == pixel_type_node ) return <STR_LIT> ; if ( type == bool_int_type_node ) return <STR_LIT> ; if ( type == bool_long_type_node ) return <STR_LIT> ; if ( TARGET_FLOAT128_TYPE ) { if ( type == ieee128_float_type_node ) return <STR_LIT> ;

if ( type == ibm128_float_type_node ) return <STR_LIT> ;


<s> EVT EltTy = UnpkOp -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) ) return Src ; APInt Mask = C -> getAPIntValue ( ) . trunc ( EltTy . getSizeInBits ( ) ) ; Dup = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Mask . zextOrTrunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , UnpkOp , Dup ) ; return DAG . getNode ( Opc , DL , N -> getValueType ( <NUM_LIT> ) , And ) ; } SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT MemVT ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerIS_FPCLASS ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; MVT ResultVT = Op . getSimpleValueType ( ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; auto CNode = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; unsigned Check = CNode -> getZExtValue ( ) ; unsigned TDCMask = <NUM_LIT> ; if ( Check & fcSNan ) TDCMask |= <STR_LIT> | <STR_LIT> ; if ( Check & fcQNan ) TDCMask |= <STR_LIT> | <STR_LIT> ; if ( Check & fcPosInf ) TDCMask |= <STR_LIT> ; if ( Check & fcNegInf ) TDCMask |= <STR_LIT> ; if ( Check & fcPosNormal ) TDCMask |= <STR_LIT> ; if ( Check & fcNegNormal ) TDCMask |= <STR_LIT> ; if ( Check & fcPosSubnormal ) TDCMask |= <STR_LIT> ;

if ( Check & fcNegSubnormal ) TDCMask |= <STR_LIT> ;


<s> * body_cost = cost [ vect_body ] ; * epilogue_cost = cost [ vect_epilogue ] ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> if ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) == PARALLEL && GET_CODE ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) == UNSPEC && XINT ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_EXECUTE ) return XVECEXP ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; return NULL_RTX ;


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Z ( TheARM64leTarget ) ;

RegisterMCAsmParser < <ISA_LIT>AsmParser > W ( TheARM64beTarget ) ;


<s> bool UseFastISel = false ; UseFastISel |= STI . isTargetMachO ( ) && ! STI . isThumb1Only ( ) ; UseFastISel |= STI . isTargetLinux ( ) && ! STI . isThumb ( ) ; UseFastISel |= STI . isTargetNaCl ( ) && ! STI . isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new <ISA_LIT>FastISel ( funcInfo , libInfo ) ; }


<s> MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , cmpInst ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( reg ) ;

lastCheck -> insert ( CI , copyMoveM ) ;


<s> SDValue LoadLinkSP = DAG . getLoad ( PtrVT , dl , Chain , StackPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( LoadLinkSP . getValue ( <NUM_LIT> ) , dl , SP , SaveSP ) ; return DAG . getStore ( Chain , dl , LoadLinkSP , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , getDataLayoutString ( TT ) , TT , CPU , computeFSAdditions ( FS , OL , TT ) , Options , getEffectiveRelocModel ( TT , RM ) , getEffective<ISA_LIT>CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , TargetABI ( computeTargetABI ( TT , Options ) ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> const DataLayout * getDataLayout ( ) const override { return & DL ;


<s> static void removeUseSoftFloat ( Function & F ) { AttrBuilder B ; DEBUG ( errs ( ) << <STR_LIT> ) ; B . addAttribute ( <STR_LIT> , <STR_LIT> ) ; F . removeAttributes ( AttributeList :: FunctionIndex , B ) ;

if ( F . hasFnAttribute ( <STR_LIT> ) ) {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( ) {


<s> } else if ( Op . isFPImm ( ) ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; assert ( OpNo < Desc . getNumOperands ( ) && <STR_LIT> ) ; assert ( Desc . TSFlags == <NUM_LIT> && <STR_LIT> ) ; const MCOperandInfo & Info = Desc . OpInfo [ OpNo ] ; if ( Info . OperandType == <STR_LIT> ) { O << toString ( APFloat ( float ( Op . getFPImm ( ) ) ) ) ; } else { assert ( Info . OperandType == <STR_LIT> ) ; O << toString ( APFloat ( Op . getFPImm ( ) ) ) ; } } else { assert ( ( OpNo < MII . get ( MI -> getOpcode ( ) ) . getNumOperands ( ) || ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) ) && <STR_LIT> <STR_LIT> ) ; assert ( Op . isExpr ( ) && <STR_LIT> ) ;

Op . getExpr ( ) -> print ( O , & MAI ) ;


<s> EVT CmpVT = Op0 . getValueType ( ) ; if ( CmpVT . isFloatingPoint ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op0 , Op1 ) ; assert ( ( CmpVT == <STR_LIT> || CmpVT == <STR_LIT> || CmpVT == <STR_LIT> || CmpVT == <STR_LIT> ) && <STR_LIT> ) ; if ( CmpVT == <STR_LIT> && ! Subtarget . isAtom ( ) && ! DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) { ConstantSDNode * COp0 = dyn_cast < ConstantSDNode > ( Op0 ) ; ConstantSDNode * COp1 = dyn_cast < ConstantSDNode > ( Op1 ) ; if ( ( COp0 && ! COp0 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) || ( COp1 && ! COp1 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue In = Op0 . getOperand ( <NUM_LIT> ) ;

unsigned EffBits = In . getScalarValueSizeInBits ( ) - DAG . ComputeNumSignBits ( In ) + <NUM_LIT> ;


<s> TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; if ( ! OptForSize && ST -> isTinyCore ( ) ) IsConst64Disabled = true ; for ( MachineBasicBlock & MBB : MF ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( MBB ) ; for ( MachineBasicBlock :: iterator MI = MBB . begin ( ) , End = MBB . end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ;

if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ;


<s> return <ISA_LIT>AsmPrinter :: emitInstruction ( MI ) ; case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : { MCSymbol * BeginOfSled = OutContext . createTempSymbol ( ) ; MCSymbol * EndOfSled = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( BeginOfSled ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( EndOfSled , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addExpr ( MCSymbolRefExpr :: create ( OutContext . getOrCreateSymbol ( <STR_LIT> ) , OutContext ) ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; OutStreamer -> emitLabel ( EndOfSled ) ; recordSled ( BeginOfSled , * MI , SledKind :: FUNCTION_ENTER ) ; break ; } case TargetOpcode :: PATCHABLE_RET : { unsigned RetOpcode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MCInst RetInst ; RetInst . setOpcode ( RetOpcode ) ; for ( const auto & MO : make_range ( std :: next ( MI -> operands_begin ( ) ) , MI -> operands_end ( ) ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , * this ) ) RetInst . addOperand ( MCOp ) ; } bool IsConditional ; if ( RetOpcode == <STR_LIT> ) { IsConditional = true ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { break ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { IsConditional = false ; } else { EmitToStreamer ( * OutStreamer , RetInst ) ; break ; } MCSymbol * FallthroughLabel ; if ( IsConditional ) { FallthroughLabel = OutContext . createTempSymbol ( ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addImm ( <STR_LIT> ( static_cast < <STR_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addExpr ( MCSymbolRefExpr :: create ( FallthroughLabel , OutContext ) ) ) ; RetInst = MCInst ( ) ; RetInst . setOpcode ( <STR_LIT> ) ; } OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; MCSymbol * BeginOfSled = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( BeginOfSled ) ; EmitToStreamer ( * OutStreamer , RetInst ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const GCNSubtarget & ST = MBB . getParent ( ) -> getSubtarget < GCNSubtarget > ( ) ; if ( ST . hasNoSdstCMPX ( ) ) Opcode = <STR_LIT> ( Opcode ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; if ( TRI -> isVGPR ( MBB . getParent ( ) -> getRegInfo ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Opcode = <STR_LIT> ( Opcode ) ; BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else { auto I = BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) ) ; if ( ! ST . hasNoSdstCMPX ( ) ) I . addReg ( <STR_LIT> , RegState :: Define ) ; I . addImm ( <NUM_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; I . addImm ( <NUM_LIT> ) ; } return true ; } case <STR_LIT> : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; int64_t KillVal = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( KillVal == <NUM_LIT> || KillVal == - <NUM_LIT> ) ; if ( Op . isImm ( ) ) { int64_t Imm = Op . getImm ( ) ; assert ( Imm == <NUM_LIT> || Imm == - <NUM_LIT> ) ; if ( Imm == KillVal ) { BuildMI ( MBB , & MI , DL , TII -> get ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , Exec ) . addImm ( <NUM_LIT> ) ; return true ; }


<s> <ISA_LIT>InstructionBuffer ( TIt Start , TIt End ) : Buffer ( Start , End ) {


<s> void <ISA_LIT>TargetStreamer :: emitNop ( SMLoc IDLoc , const MCSubtargetInfo * STI ) { if ( isMicro<ISA_LIT> ( STI ) ) emitRR ( <STR_LIT> , <STR_LIT> , <STR_LIT> , IDLoc , STI ) ; else emitRRI ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> , IDLoc , STI ) ;


<s> if ( ! isUnary ) { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + k ) ) return false ; } else { for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i += <NUM_LIT> ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + k ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + k ) ) return false ;


<s> unsigned Start = <NUM_LIT> ; unsigned End = NumSectionElts / <NUM_LIT> ; for ( unsigned s = <NUM_LIT> ; s < NumSections ; ++ s ) { for ( unsigned i = Start ; i != End ; ++ i ) { ShuffleMask . push_back ( i ) ; ShuffleMask . push_back ( i + NumSectionElts ) ; } Start += NumSectionElts ;


<s> break ; case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingMembers . begin ( ) ; It != PendingMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingMembers . clear ( ) ; return true ; } unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; if ( LocVT == <STR_LIT> && State . getNextStackOffset ( ) == <NUM_LIT> ) { unsigned RegIdx = State . getFirstUnallocated ( RegList ) ; for ( auto & It : PendingMembers ) { if ( RegIdx >= RegList . size ( ) ) It . convertToMem ( State . AllocateStack ( Size , Size ) ) ; else It . convertToReg ( State . AllocateReg ( RegList [ RegIdx ++ ] ) ) ;


<s> bool selectBDXAddr20Only128 ( SDValue Addr , SDValue & Base , SDValue & Disp , SDValue & Index ) { return selectBDXAddr ( <STR_LIT> , <STR_LIT> , Addr , Base , Disp , Index ) ;


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ;

if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;


<s> unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ;

assert ( Value <= <NUM_LIT> && <STR_LIT> ) ;


<s> case <STR_LIT> : return performSubCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return performAddCarrySubCarryCombine ( N , DCI ) ; case <STR_LIT> : return performFAddCombine ( N , DCI ) ; case <STR_LIT> : return performFSubCombine ( N , DCI ) ; case <STR_LIT> : return performSetCCCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) >= AfterLegalizeDAG && getTargetMachine ( ) . getOptLevel ( ) > CodeGenOpt :: None ) return performMinMaxCombine ( N , DCI ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performZeroExtendCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performCvtF32UByteNCombine ( N , DCI ) ; case <STR_LIT> : return performFMed3Combine ( N , DCI ) ; case <STR_LIT> : return performCvtPkRTZCombine ( N , DCI ) ; case <STR_LIT> : { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDLoc SL ( N ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT EltVT = Src . getValueType ( ) ; if ( EltVT == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Ext ) ;


<s> MachineInstr * MI = MBB . getFirstTerminator ( ) ; if ( isConditionalBranch ( MI -> getOpcode ( ) ) && ! isBlockInRange ( MI , getDestBlock ( MI ) , getBranchDisplacementBits ( MI -> getOpcode ( ) ) ) ) { fixupConditionalBranch ( MI ) ; ++ NumRelaxed ; Changed = true ; } } return Changed ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; BuildMI ( * MBB , & MI , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( <STR_LIT> ) . addReg ( LdI . BaseReg ) . addImm ( <NUM_LIT> ) ; MachineOperand & BaseOpnd = MI . getOperand ( LdI . BaseRegIdx ) ; BaseOpnd . setReg ( ScratchReg ) ; if ( LdI . IsPrePost ) { DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( ScratchReg , TRI ) << '\n' ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( ScratchReg ) ; BuildMI ( * MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , DL , TII -> get ( <STR_LIT> ) , LdI . BaseReg ) . addReg ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; } for ( int I = <NUM_LIT> , E = OldCollisions . size ( ) ; I != E ; ++ I ) if ( OldCollisions [ I ] == & MI ) { std :: swap ( OldCollisions [ I ] , OldCollisions [ E - <NUM_LIT> ] ) ; OldCollisions . pop_back ( ) ; break ; } TagMap [ NewTag ] . push_back ( & MI ) ; ++ NumCollisionsAvoided ; Fixed = true ;


<s> offset = frame -> cop0_sp_offset - size ; if ( ! cfun -> machine -> keep_interrupts_masked_p ) { mem = gen_frame_mem ( word_mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; mips_emit_move ( mem , gen_rtx_REG ( word_mode , K1_REG_NUM ) ) ; offset -= UNITS_PER_WORD ; } emit_insn ( gen_cop0_move ( gen_rtx_REG ( SImode , K1_REG_NUM ) , gen_rtx_REG ( SImode , COP0_STATUS_REG_NUM ) ) ) ; if ( ! cfun -> machine -> keep_interrupts_masked_p ) emit_insn ( gen_lshrsi3 ( gen_rtx_REG ( SImode , K0_REG_NUM ) , gen_rtx_REG ( SImode , K0_REG_NUM ) , GEN_INT ( CAUSE_IPL ) ) ) ; mem = gen_frame_mem ( word_mode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; mips_emit_move ( mem , gen_rtx_REG ( word_mode , K1_REG_NUM ) ) ; offset -= UNITS_PER_WORD ; if ( ! cfun -> machine -> keep_interrupts_masked_p ) emit_insn ( gen_insvsi ( gen_rtx_REG ( SImode , K1_REG_NUM ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( SR_IPL ) , gen_rtx_REG ( SImode , K0_REG_NUM ) ) ) ; if ( ! cfun -> machine -> keep_interrupts_masked_p ) emit_insn ( gen_insvsi ( gen_rtx_REG ( SImode , K1_REG_NUM ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( SR_EXL ) , gen_rtx_REG ( SImode , GP_REG_FIRST ) ) ) ; else emit_insn ( gen_insvsi ( gen_rtx_REG ( SImode , K1_REG_NUM ) , GEN_INT ( <NUM_LIT> ) , GEN_INT ( SR_IE ) , gen_rtx_REG ( SImode , GP_REG_FIRST ) ) ) ; } else { rtx insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; mips_frame_barrier ( ) ; size -= step1 ; } mips_for_each_saved_acc ( size , mips_save_reg ) ; mips_for_each_saved_gpr_and_fpr ( size , mips_save_reg ) ; } } if ( size > <NUM_LIT> ) { if ( SMALL_OPERAND ( - size ) ) RTX_FRAME_RELATED_P ( emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ) ) = <NUM_LIT> ; else { mips_emit_move ( MIPS_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( size ) ) ; if ( TARGET_MIPS16 ) { gcc_assert ( frame_pointer_needed ) ; mips_emit_move ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; emit_insn ( gen_sub3_insn ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ; mips_emit_move ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; } else emit_insn ( gen_sub3_insn ( stack_pointer_rtx , stack_pointer_rtx , MIPS_PROLOGUE_TEMP ( Pmode ) ) ) ;

mips_set_frame_expr ( gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - size ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


return static_cast < T > ( ptr ( N ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isDef ( ) ) continue ; if ( MO . getReg ( ) != <STR_LIT> ) continue ; assert ( LiveCPSR && <STR_LIT> ) ; if ( MO . isKill ( ) ) {


<s> if ( ! Memory . OffsetImm ) return true ; if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) { int64_t Val = CE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) ; }


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> virtual void EmitInstruction ( const MCInst & Inst ) { if ( InstPrinter ) InstPrinter -> printInst ( & Inst , OS , <STR_LIT> ) ; else Inst . print ( OS , & MAI ) ; EmitEOL ( ) ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> for ( auto * RC : SpillRCs ) { if ( ! needToReserveScavengingSpillSlots ( MF , HRI , RC ) ) continue ; unsigned Num = <NUM_LIT> ; switch ( RC -> getID ( ) ) { case <STR_LIT> : Num = NumberScavengerSlots ; break ; case <STR_LIT> : Num = <NUM_LIT> ; break ; } unsigned S = HRI . getSpillSize ( * RC ) , A = HRI . getSpillAlignment ( * RC ) ; for ( unsigned i = <NUM_LIT> ; i < Num ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( S , A ) ;

RS -> addScavengingFrameIndex ( NewFI ) ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;


<s> unsigned AS = GV -> getAddressSpace ( ) ; return AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ;


<s> unsigned ADDiu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( Amount == <NUM_LIT> ) return ; if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ;


<s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C ) const override { return ReadOnlySection ;


<s> case <ISA_LIT>InstrInfo :: ALU_VEC_021_SCL_122 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case <ISA_LIT>InstrInfo :: ALU_VEC_102_SCL_221 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case <ISA_LIT>InstrInfo :: ALU_VEC_120_SCL_212 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case <ISA_LIT>InstrInfo :: ALU_VEC_201 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ;


<s> case MachineOperand :: MO_Immediate : llvm_report_error ( <STR_LIT> ) ; return ; case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; return ; case MachineOperand :: MO_JumpTableIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ExternalSymbol : if ( TM . getRelocationModel ( ) != Reloc :: Static ) { std :: string Name ( TAI -> getGlobalPrefix ( ) ) ; Name += MO . getSymbolName ( ) ; GVStubs . insert ( Name ) ; O << <STR_LIT> << Name << <STR_LIT> ; return ; } O << TAI -> getGlobalPrefix ( ) << MO . getSymbolName ( ) ; return ;

case MachineOperand :: MO_GlobalAddress : {


<s> int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) return true ; gcc_assert ( ! op_true == ! op_false ) ; if ( ! op_true || ! ix86_valid_mask_cmp_mode ( cmp_mode ) ) return false ; if ( op_false == CONST0_RTX ( mode ) || op_true == CONST0_RTX ( mode ) || ( INTEGRAL_MODE_P ( mode ) && ( op_true == CONSTM1_RTX ( mode ) || op_false == CONSTM1_RTX ( mode ) ) ) ) return false ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_TTMP ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } else if ( Is == IS_SGPR ) { switch ( RegWidth ) { default : return - <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


return ( __m128i ) __builtin_ia32_pmovzxwd128_mask ( ( __v8hi ) __A , ( __v4si ) _mm_setzero_si128 ( ) , ( __mmask8 ) __U ) ;


<s> SDLoc dl ( N ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) , Op -> getOperand ( <NUM_LIT> ) ) ; } return SDValue ( ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; RelooperAlgorithm R ; std :: map < const BasicBlock * , Block * > BB2B ; std :: map < const Block * , const BasicBlock * > B2BB ; for ( const BasicBlock & BB : F ) { Block * B = new Block ( BB . getName ( ) . str ( ) . data ( ) , nullptr ) ; R . AddBlock ( B ) ; assert ( BB2B . find ( & BB ) == BB2B . end ( ) && <STR_LIT> ) ; assert ( B2BB . find ( B ) == B2BB . end ( ) && <STR_LIT> ) ; BB2B [ & BB ] = B ; B2BB [ B ] = & BB ; } for ( Block * B : R . Blocks ) {


<s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {


<s> GCNTargetMachine :: GCNTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , TargetOptions Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) {


<s> if ( Info . IsFixed ) return AssignFn ( ValNo , ValVT , LocVT , LocInfo , Info . Flags , State ) ; return AssignFnVarArg ( ValNo , ValVT , LocVT , LocInfo , Info . Flags , State ) ;


<s> MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( OutContext , * TM . getTargetData ( ) ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; SmallString < <NUM_LIT> > Str2 ; raw_svector_ostream OS2 ( Str2 ) ; emitDeclarations ( M , OS2 ) ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) printModuleLevelGV ( I , OS2 ) ; OS2 << '\n' ; OutStreamer . EmitRawText ( OS2 . str ( ) ) ; return false ;


<s> MCAsmLexer & Lexer = getLexer ( ) ; if ( Lexer . isNot ( Kind ) ) { return Error ( Lexer . getLoc ( ) , <STR_LIT> ) ; }

Operands . push_back ( std :: unique_ptr < MCParsedAsmOperand > ( <ISA_LIT>Operand :: CreateToken ( Lexer . getTok ( ) . getString ( ) , Lexer . getLoc ( ) ) ) ) ;


<s> auto * F = CGN -> getFunction ( ) ; if ( ! F || F -> isDeclaration ( ) || <STR_LIT> ( F ) ) continue ; AddressTakenFunctions . insert ( CGN ) ;