<s> MVT OpVT = VT ; unsigned NumBits = VT . getSizeInBits ( ) ; SDLoc dl ( Op ) ; if ( VT . isVector ( ) && Subtarget -> hasAVX512 ( ) ) return LowerVectorCTLZ_AVX512 ( Op , DAG ) ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { OpVT = <STR_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ;

Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ;


<s> uint64_t Binary = getBinaryCodeForInstr ( HMB , Fixups , STI ) | getPacketBits ( HMB ) ;

assert ( HMB . getDesc ( ) . getSize ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( Ty -> isHalfTy ( ) ) return AtomicExpansionKind :: None ; if ( ! Ty -> isFloatTy ( ) && ( ! Subtarget -> hasGFX90AInsts ( ) || ! Ty -> isDoubleTy ( ) ) ) return AtomicExpansionKind :: CmpXChg ; unsigned AS = RMW -> getPointerAddressSpace ( ) ; if ( ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) && Subtarget -> hasAtomicFaddInsts ( ) ) { if ( Subtarget -> hasGFX940Insts ( ) ) return AtomicExpansionKind :: None ; if ( RMW -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) != <STR_LIT> ) return AtomicExpansionKind :: CmpXChg ; if ( Subtarget -> hasGFX90AInsts ( ) ) { if ( Ty -> isFloatTy ( ) && AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; auto S<ISA_LIT>D = RMW -> getSyncScopeID ( ) ; if ( S<ISA_LIT>D == SyncScope :: System || S<ISA_LIT>D == RMW -> getContext ( ) . getOrInsertSyncScopeID ( <STR_LIT> ) ) return AtomicExpansionKind :: CmpXChg ; return ReportUnsafeHWInst ( AtomicExpansionKind :: None ) ; } if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; return RMW -> use_empty ( ) ? ReportUnsafeHWInst ( AtomicExpansionKind :: None ) : AtomicExpansionKind :: CmpXChg ; } if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS && Subtarget -> hasLDSFPAtomicAdd ( ) ) { if ( ! Ty -> isDoubleTy ( ) ) return AtomicExpansionKind :: None ; if ( fpModeMatchesGlobalFPAtomicMode ( RMW ) ) return AtomicExpansionKind :: None ; return RMW -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ? ReportUnsafeHWInst ( AtomicExpansionKind :: None ) : AtomicExpansionKind :: CmpXChg ;


<s> unsigned getSRetReturnReg ( ) const { return SRetReturnReg ;


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return - <NUM_LIT> ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = MatchRegisterName ( lowerCase ) ; if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - <NUM_LIT> ; Parser . Lex ( ) ; return Entry -> getValue ( ) ; }


<s> SMLoc End ; if ( Parser . parseExpression ( Val , End ) ) return error ( <STR_LIT> , Lexer . getTok ( ) ) ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Id . getLoc ( ) , Id . getEndLoc ( ) , <STR_LIT> { Val } ) ) ; if ( checkForP2AlignIfLoadStore ( Operands , Name ) ) return true ; } break ; } case AsmToken :: Minus : Parser . Lex ( ) ; if ( Lexer . is ( AsmToken :: Integer ) ) { parseSingleInteger ( true , Operands ) ; if ( checkForP2AlignIfLoadStore ( Operands , Name ) ) return true ; } else if ( Lexer . is ( AsmToken :: Real ) ) { if ( parseSingleFloat ( true , Operands ) ) return true ; } else if ( ! parseSpecialFloatMaybe ( true , Operands ) ) { } else { return error ( <STR_LIT> , Lexer . getTok ( ) ) ; } break ; case AsmToken :: Integer : parseSingleInteger ( false , Operands ) ; if ( checkForP2AlignIfLoadStore ( Operands , Name ) ) return true ; break ; case AsmToken :: Real : { if ( parseSingleFloat ( false , Operands ) ) return true ; break ; } case AsmToken :: LCurly : { Parser . Lex ( ) ; auto Op = make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Tok . getLoc ( ) , Tok . getEndLoc ( ) ) ; if ( ! Lexer . is ( AsmToken :: RCurly ) ) for ( ; ; ) { Op -> BrL . List . push_back ( Lexer . getTok ( ) . getIntVal ( ) ) ; expect ( AsmToken :: Integer , <STR_LIT> ) ; if ( ! isNext ( AsmToken :: Comma ) ) break ; } expect ( AsmToken :: RCurly , <STR_LIT> ) ; Operands . push_back ( std :: move ( Op ) ) ; break ; } default : return error ( <STR_LIT> , Tok ) ; } if ( Lexer . isNot ( AsmToken :: EndOfStatement ) ) { if ( expect ( AsmToken :: Comma , <STR_LIT> ) ) return true ; }


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: spirv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;

RegisterTarget < Triple :: spirv64 > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> switch ( Reg ) { default : llvm_unreachable ( <STR_LIT> ) ; return false ; case <STR_LIT> : case <STR_LIT> :


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> const MachineInstr * PtrBaseDef = getDefIgnoringCopies ( PtrBase , * MRI ) ; if ( PtrBaseDef -> getOpcode ( ) != <STR_LIT> ) return None ; Register PtrBaseSrc = getSrcRegIgnoringCopies ( PtrBaseDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( ! PtrBaseSrc ) return None ; const RegisterBank * BaseRB = RBI . getRegBank ( PtrBaseSrc , * MRI , TRI ) ; if ( BaseRB -> getID ( ) != <STR_LIT> ) return None ; Register SAddr = PtrBaseSrc ;

Register PtrBaseOffset = PtrBaseDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


AND_COMPL_HARD_REG_SET ( operand_reg_set , reg_class_contents [ ( int ) MD_REGS ] ) ;


<s> return __builtin_aarch64_sqshlv8hi ( __a , __b ) ;


<s> n = n % <NUM_LIT> ; } wlength += h8300_asm_insn_count ( info . shift1 ) * n ; return <NUM_LIT> * wlength ; case SHIFT_ROT_AND : { int m = GET_MODE_BITSIZE ( mode ) - n ; gcc_assert ( info . shift1 ) ; if ( info . shift2 != NULL ) { wlength += h8300_asm_insn_count ( info . shift2 ) * ( m / <NUM_LIT> ) ; m = m % <NUM_LIT> ; } wlength += h8300_asm_insn_count ( info . shift1 ) * m ; switch ( mode ) { case E_QImode : wlength += <NUM_LIT> ; break ; case E_HImode : wlength += <NUM_LIT> ; break ; case E_SImode : wlength += <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } return <NUM_LIT> * wlength ; } case SHIFT_LOOP : if ( info . shift2 != NULL ) { wlength += <NUM_LIT> + h8300_asm_insn_count ( info . shift2 ) ; if ( n % <NUM_LIT> ) wlength += h8300_asm_insn_count ( info . shift1 ) ; }


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> call_used_regs [ VRSAVE_REGNO ] = <NUM_LIT> ; } if ( TARGET_ALTIVEC || TARGET_VSX ) global_regs [ VSCR_REGNO ] = <NUM_LIT> ; if ( TARGET_ALTIVEC_ABI ) { for ( i = FIRST_ALTIVEC_REGNO ; i < FIRST_ALTIVEC_REGNO + <NUM_LIT> ; ++ i ) call_used_regs [ i ] = <NUM_LIT> ; if ( TARGET_XCOFF && ! rs6000_aix_extabi ) for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i < FIRST_ALTIVEC_REGNO + <NUM_LIT> ; ++ i ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; }


<s> if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) { if ( GET_MODE ( x ) == DImode && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> ) return <NUM_LIT> ; return - <NUM_LIT> ; } if ( ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return SH_DYNAMIC_SHIFT_COST ; value = INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ; if ( GET_CODE ( x ) == ASHIFTRT ) {


<s> static void rs6000_eliminate_indexed_memrefs ( rtx operands [ <NUM_LIT> ] ) { if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! REG_P ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) && ! legitimate_constant_pool_address_p ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , GET_MODE ( operands [ <NUM_LIT> ] ) , false ) ) operands [ <NUM_LIT> ] = replace_equiv_address ( operands [ <NUM_LIT> ] , copy_addr_to_reg ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ;


<s> } MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; unsigned OppositeBranchOpcode = TII -> getOppositeBranchOpc ( Opcode ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> end ( ) ) && BMI -> isUnconditionalBranch ( ) ) { unsigned BMITargetOperand = branchTargetOperand ( BMI ) ; MachineBasicBlock * NewDest = BMI -> getOperand ( BMITargetOperand ) . getMBB ( ) ; if ( isBBInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; MI -> setDesc ( TII -> get ( OppositeBranchOpcode ) ) ; BMI -> getOperand ( BMITargetOperand ) . setMBB ( DestBB ) ; MI -> getOperand ( TargetOperand ) . setMBB ( NewDest ) ; return true ; } } } if ( NeedSplit ) { splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; if ( MI -> getNumExplicitOperands ( ) == <NUM_LIT> ) { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( NextBB ) ; } else { BuildMI ( MBB , DebugLoc ( ) , TII -> get ( OppositeBranchOpcode ) ) . addMBB ( NextBB ) ; } Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ; adjustBBOffsetsAfter ( MBB ) ;


<s> return ( uint32x4_t ) __builtin_neon_vdup_lanev4si ( ( int32x2_t ) __a , __b ) ;


<s> InstrExec . clear ( ) ; assert ( FlowQ . empty ( ) ) ; propagate ( MF ) ; bool Changed = rewrite ( MF ) ; DEBUG ( { dbgs ( ) << <STR_LIT> << Changed << <STR_LIT> ; if ( Changed ) MF . print ( dbgs ( ) , <NUM_LIT> ) ; } ) ; return Changed ;


<s> unsigned Opc = MI . getOpcode ( ) ; unsigned PredOpc = HII -> getCondOpcode ( Opc , ! Cond ) ; MachineInstrBuilder MB = BuildMI ( B , Where , DL , HII -> get ( PredOpc ) ) ; unsigned Ox = <NUM_LIT> , NP = MI . getNumOperands ( ) ; while ( Ox < NP ) { MachineOperand & MO = MI . getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) break ;


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == SrcRC ) { unsigned Opc ; if ( DestRC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( DestRC == & <STR_LIT> ) { Opc = <STR_LIT> ; } else { return false ; } BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg ) ; return true ; }


<s> unsigned size ( ) const { return Insts . size ( ) ;


<s> Memory . clear ( ) ; BlockNodes . clear ( ) ;


<s> bool <ISA_LIT>AsmParser :: MatchAndEmitInstruction ( SMLoc Loc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { MCInst Inst ;

unsigned MatchResult = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ;


<s> PM . add ( createAMDGPUTargetTransformInfoPass ( this ) ) ;


<s> int regno ; int start_reg = <NUM_LIT> , end_reg = <NUM_LIT> ; for ( regno = start_reg ; regno <= end_reg && ( gmask & ( <NUM_LIT> << regno ) ) ; ) regno ++ ; end_reg = regno - <NUM_LIT> ; if ( regno - start_reg >= <NUM_LIT> - ( crtl -> is_leaf == <NUM_LIT> ) ) { frame -> millicode_start_reg = <NUM_LIT> ;

frame -> millicode_end_reg = regno - <NUM_LIT> ;


<s> auto FB = getFeatureBits ( ) ; if ( ! FB [ <STR_LIT> ] ) return true ; const MCRegisterInfo * MRI = getMRI ( ) ; const MCRegisterClass & VGRP32 = MRI -> getRegClass ( <STR_LIT> ) ; const MCRegisterClass & AGRP32 = MRI -> getRegClass ( <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = Inst . getNumOperands ( ) ; I != E ; ++ I ) { const MCOperand & Op = Inst . getOperand ( I ) ; if ( ! Op . isReg ( ) ) continue ; unsigned Sub = MRI -> getSubReg ( Op . getReg ( ) , <STR_LIT> ) ;


<s> ClusterDAG ( MachineFunction & MF , const MachineLoopInfo & MLI , const MachineDominatorTree & MDT , AliasAnalysis * AA , AssignmentState * state ) : RegionScheduler ( MF , MLI , MDT ) , FUSched ( NULL ) , TRI ( MF . getTarget ( ) . getRegisterInfo ( ) ) , AA ( AA ) , CAState ( state ) {


EmitToStreamer ( * OutStreamer , LoweredMI ) ;


<s> DEBUG ( HazardRec -> dumpState ( ) ; ) ;


<s> const char * fpu_name ; fpu_name = ( ptr -> x_arm_fpu_index == TARGET_FPU_auto ? <STR_LIT> : all_fpus [ ptr -> x_arm_fpu_index ] . name ) ;

fprintf ( file , <STR_LIT> , indent , <STR_LIT> , TARGET_THUMB2_P ( flags ) ? <STR_LIT> :


<s> hashval_t toc_hasher :: hash ( toc_hash_struct * thc ) { return rs6000_hash_constant ( thc -> key ) ^ thc -> key_mode ;


<s> bool function_instance :: reads_global_state_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_READ_FPCR ) return true ;

return flags & ( CP_READ_MEMORY | CP_READ_CSR ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , DwarfFlavour ) ; return X ;


<s> MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , NewMBB ) ; return NewMBB ;


<s> if ( TREE_PUBLIC ( default_decl ) == <NUM_LIT> ) { char * ifunc_name = make_unique_name ( default_decl , <STR_LIT> , true ) ; symtab -> change_decl_assembler_name ( ifunc_alias_decl , get_identifier ( ifunc_name ) ) ; XDELETEVEC ( ifunc_name ) ; } resolver_name = make_unique_name ( default_decl , <STR_LIT> , false ) ; type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; decl = build_fn_decl ( resolver_name , type ) ; decl_name = get_identifier ( resolver_name ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = <NUM_LIT> ; DECL_ARTIFICIAL ( decl ) = <NUM_LIT> ; DECL_IGNORED_P ( decl ) = <NUM_LIT> ; TREE_PUBLIC ( decl ) = <NUM_LIT> ; DECL_UNINLINABLE ( decl ) = <NUM_LIT> ; DECL_EXTERNAL ( decl ) = <NUM_LIT> ; DECL_EXTERNAL ( ifunc_alias_decl ) = <NUM_LIT> ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = <NUM_LIT> ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = <NUM_LIT> ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_ARTIFICIAL ( t ) = <NUM_LIT> ; DECL_IGNORED_P ( t ) = <NUM_LIT> ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , profile_count :: uninitialized ( ) ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( ifunc_alias_decl != NULL ) ; DECL_ATTRIBUTES ( ifunc_alias_decl ) = make_attribute ( <STR_LIT> , resolver_name , DECL_ATTRIBUTES ( ifunc_alias_decl ) ) ; cgraph_node :: create_same_body_alias ( ifunc_alias_decl , decl ) ; XDELETEVEC ( resolver_name ) ;


<s> <ISA_LIT>_64GOTEntry * got_entry = pParent . getSymGOTMap ( ) . lookUp ( * pReloc . symInfo ( ) ) ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & STI , MCAsmParser & , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) {

const Triple & TheTriple = STI . getTargetTriple ( ) ;


<s> if ( TARGET_BPF_CORE ) btf_ext_init ( ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned type = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Shift = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ;


<s> unsigned CC = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regX = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned regY = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( SltOpc ) ) . addReg ( regX ) . addReg ( regY ) ; BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CC ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ; return BB ;


<s> int i ; rtx op = * op_ptr ; enum rtx_code code = GET_CODE ( op ) ; if ( GET_CODE ( op ) == CONST_VECTOR ) { int units = GET_MODE_NUNITS ( GET_MODE ( op ) ) ; rtx_vector_builder builder ( GET_MODE ( op ) , units , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < units / <NUM_LIT> ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i + units / <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < units / <NUM_LIT> ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i ) ) ; * op_ptr = builder . build ( ) ; } else { int j ;

const char * fmt = GET_RTX_FORMAT ( code ) ;


<s> unsigned Alignment = TLI . getDataLayout ( ) -> getABITypeAlignment ( FV -> getType ( ) ) ; SDValue PoolAddr = getConstantPoolItemAddress ( DL , FV ) ; return CurDAG -> getLoad ( DestType , DL , CurDAG -> getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , true , Alignment ) . getNode ( ) ;


<s> void <ISA_LIT>ELFStreamer :: EmitPad ( int64_t Offset ) {


OutStreamer -> emitDataRegion ( MCDR_DataRegionEnd ) ;


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( AlwaysInline || ( Align & <NUM_LIT> ) != <NUM_LIT> || ! ConstantSize ) return SDValue ( ) ; uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( SizeVal < <NUM_LIT> || ( SizeVal % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; const char * SpecialMemcpyName = <STR_LIT> ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ;

CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getTargetExternalSymbol ( SpecialMemcpyName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ;


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeFloatZero ( const ConstantFP * CF ) { MVT VT ; if ( ! isTypeLegal ( CF -> getType ( ) , VT ) ) return false ; unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = <STR_LIT> ; }


<s> SmallVector < MachineOperand , <NUM_LIT> > aCond ; auto Term = MBB . getFirstTerminator ( ) ; if ( Term != MBB . end ( ) && isPredicated ( * Term ) && ! analyzeBranch ( MBB , NewTBB , NewFBB , aCond , false ) && MachineFunction :: iterator ( NewTBB ) == ++ MBB . getIterator ( ) ) { reverseBranchCondition ( aCond ) ; removeBranch ( MBB ) ; return insertBranch ( MBB , TBB , nullptr , aCond , DL ) ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addReg ( RO . getReg ( ) , Flags ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> result = gen_reg_rtx ( HImode ) ; if ( GET_CODE ( op ) == SYMBOL_REF || ( GET_CODE ( op ) == REG && REGNO ( op ) >= FIRST_PSEUDO_REGISTER ) ) tmp = gen_rtx_raw_SUBREG ( HImode , op , <NUM_LIT> ) ; else tmp = simplify_subreg ( HImode , op , SImode , <NUM_LIT> ) ; gcc_assert ( tmp != NULL_RTX ) ; emit_move_insn ( result , tmp ) ; return result ; } else if ( to_bits > from_bits ) { result = gen_reg_rtx ( SImode ) ;

emit_move_insn ( rl78_subreg ( HImode , result , SImode , <NUM_LIT> ) , op ) ;


<s> <ISA_LIT>16RegisterInfo :: <ISA_LIT>16RegisterInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>RegisterInfo ( ST ) {


<s> bool isMaskArithmetic ( SDValue Op ) { switch ( Op . getOpcode ( ) ) {


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> static enum ptx_version default_ptx_version_option ( void ) { enum ptx_version first = first_ptx_version_supporting_sm ( ( enum ptx_isa ) ptx_isa_option ) ; enum ptx_version res = first ;


<s> if ( isa < PHINode > ( In ) || ( To != Block . end ( ) && isa < PHINode > ( * To ) ) ) return false ; if ( ! mayHaveNonDefUseDependency ( In ) ) return true ; bool MayWrite = In . mayWriteToMemory ( ) ; auto MaybeLoc = getLocOrNone ( In ) ; auto From = In . getIterator ( ) ; if ( From == To ) return true ; bool MoveUp = ( To != Block . end ( ) && To -> comesBefore ( & In ) ) ; auto Range = MoveUp ? std :: make_pair ( To , From ) : std :: make_pair ( std :: next ( From ) , To ) ; for ( auto It = Range . first ; It != Range . second ; ++ It ) { const Instruction & I = * It ; if ( llvm :: is_contained ( Ignore , & I ) ) continue ; if ( auto * II = dyn_cast < IntrinsicInst > ( & I ) ) { if ( II -> getIntrinsicID ( ) == <STR_LIT> ) continue ; } if ( I . mayThrow ( ) ) return false ; if ( auto * CB = dyn_cast < CallBase > ( & I ) ) { if ( ! CB -> hasFnAttr ( Attribute :: WillReturn ) ) return false ; if ( ! CB -> hasFnAttr ( Attribute :: NoSync ) ) return false ; } if ( I . mayReadOrWriteMemory ( ) ) { auto MaybeLocI = getLocOrNone ( I ) ; if ( MayWrite || I . mayWriteToMemory ( ) ) { if ( ! MaybeLoc || ! MaybeLocI ) return false ;

if ( ! AA . isNoAlias ( * MaybeLoc , * MaybeLocI ) ) return false ;


<s> bool isNEONi32splat ( ) const { if ( isNEONByteReplicate ( <NUM_LIT> ) ) return false ; if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; unsigned Value = CE -> getValue ( ) ;


<s> if ( isUsedAsMemCpySource ( & Arg , OtherUse ) && ! OtherUse ) Bonus += <NUM_LIT> ; } LLVM_DEBUG ( if ( Bonus ) dbgs ( ) << <STR_LIT> << Bonus << <STR_LIT> ; ) ; return Bonus ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const {


<s> unsigned NumNonZero = <NUM_LIT> ; uint64_t NonZeros = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumOperands ; ++ i ) { SDValue SubVec = Op . getOperand ( i ) ; if ( SubVec . isUndef ( ) ) continue ; if ( <STR_LIT> ( SubVec . getNode ( ) ) ) ++ NumZero ; else { assert ( i < sizeof ( NonZeros ) * CHAR_BIT ) ; NonZeros |= ( uint64_t ) <NUM_LIT> << i ; ++ NumNonZero ; } } if ( NumNonZero <= <NUM_LIT> ) { SDValue Vec = NumZero ? getZeroVector ( ResVT , Subtarget , DAG , dl ) : DAG . getUNDEF ( ResVT ) ; if ( ! NumNonZero ) return Vec ; unsigned Idx = countTrailingZeros ( NonZeros ) ; SDValue SubVec = Op . getOperand ( Idx ) ; unsigned SubVecNumElts = SubVec . getSimpleValueType ( ) . getVectorNumElements ( ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Vec , SubVec , DAG . getIntPtrConstant ( Idx * SubVecNumElts , dl ) ) ; } if ( NumOperands > <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( ResVT . getVectorElementType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; ArrayRef < SDUse > Ops = Op -> ops ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( <NUM_LIT> , NumOperands / <NUM_LIT> ) ) ;

SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops . slice ( NumOperands / <NUM_LIT> ) ) ;


<s> MaskOK = Mask . isIntN ( N00 . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) ) ; } if ( MaskOK && Mask != <NUM_LIT> ) { SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N00 , DAG . getConstant ( Mask , DL , VT ) ) ; } } if ( auto * N1BV = dyn_cast < BuildVectorSDNode > ( N1 ) ) if ( auto * N1SplatC = N1BV -> getConstantSplatNode ( ) ) { assert ( N0 . getValueType ( ) . isVector ( ) && <STR_LIT> ) ;

if ( N1SplatC -> getAPIntValue ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N0 ) ;


<s> SDValue BCSrc = Src . getOperand ( <NUM_LIT> ) ; if ( BCSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BCSrc ) ; }

if ( SDValue V = combineVectorSignBitsTruncation ( N , DL , DAG , Subtarget ) ) return V ;


<s> <ISA_LIT>64elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> if ( Imm == <NUM_LIT> ) return MCDisassembler :: Fail ;

return decodeUImmOperand < N > ( Inst , Imm , Address , Decoder ) ;


<s> static <ISA_LIT>Operand CreateImm ( MCValue Val ) { <ISA_LIT>Operand Res ;


<s> return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT , Subtarget -> hasAVX ( ) ) || isSHUFPMask ( Mask , VT , Subtarget -> hasAVX ( ) , true ) ) ; }


<s> if ( GET_MODE ( bytes_rtx ) != VOIDmode && GET_MODE ( bytes_rtx ) != Pmode ) bytes_rtx = convert_to_mode ( Pmode , bytes_rtx , <NUM_LIT> ) ;

emit_library_call ( m32r_function_symbol ( <STR_LIT> ) , LCT_NORMAL , VOIDmode , <NUM_LIT> , dest_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ;


<s> bool trySubst ( Stream & os , const <ISA_LIT>LibFunc :: Param & p ) { int const subst = findSubst ( p ) ; if ( subst < <NUM_LIT> ) return false ;

if ( subst == <NUM_LIT> ) os << <STR_LIT> ;


<s> return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> bool rs6000_overloaded_builtin_p ( enum rs6000_builtins fncode ) {

return ( rs6000_builtin_info [ ( int ) fncode ] . attr & RS6000_BTC_OVERLOADED ) != <NUM_LIT> ;


<s> if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ( Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } else if ( Prefix . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; Reg = StringSwitch < unsigned long long > ( Prefix ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( ! Reg ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( <STR_LIT> ) ; return std :: make_pair ( Reg , RC ) ; } if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget . isFP64bit ( ) || ! ( Reg % <NUM_LIT> ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ; if ( RC == & <STR_LIT> ) { assert ( Reg % <NUM_LIT> == <NUM_LIT> ) ; Reg >>= <NUM_LIT> ; }

} else if ( Prefix == <STR_LIT> ) RC = TRI -> getRegClass ( <STR_LIT> ) ;


<s> bool debuggerReserveRegs ( ) const { return DebuggerReserveRegs ;


<s> InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> || VT . is64BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT . is128BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else return false ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; ConstantSDNode * OffsetOp = cast < ConstantSDNode > ( LD -> getOffset ( ) ) ; int OffsetVal = ( int ) OffsetOp -> getZExtValue ( ) ; SDLoc dl ( N ) ; SDValue Offset = CurDAG -> getTargetConstant ( OffsetVal , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Offset , Chain } ; SDNode * Res = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , DstVT , <STR_LIT> , Ops ) ; SDValue LoadedVal = SDValue ( Res , <NUM_LIT> ) ; if ( InsertTo64 ) { SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; LoadedVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) , LoadedVal , SubReg ) , <NUM_LIT> ) ; }

ReplaceUses ( SDValue ( N , <NUM_LIT> ) , LoadedVal ) ;


<s> MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ;

Lower<ISA_LIT>MachineInstrToMCInst ( & * I , TmpInst , * this ) ;


<s> switch ( GET_CODE ( op ) ) { case REG : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ; break ; case CONST_INT : i = INTVAL ( op ) ; if ( TARGET_ASM_HEX ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT <STR_LIT> , i ) ;

else fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT <STR_LIT> , i ) ;


<s> aapcs_cp_arg_layout [ i ] . cum_init ( pcum , fntype , libname , fndecl ) ; } } return ; } pcum -> nregs = <NUM_LIT> ; pcum -> iwmmxt_nregs = <NUM_LIT> ; pcum -> can_split = true ; pcum -> named_count = <NUM_LIT> ; pcum -> nargs = <NUM_LIT> ; if ( TARGET_REALLY_IWMMXT && fntype ) { tree fn_arg ; for ( fn_arg = TYPE_ARG_TYPES ( fntype ) ;


<s> return __builtin_mve_vqaddq_n_sv16qi ( __a , __b ) ;


<s> virtual ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> if ( Subtarget . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; O << <STR_LIT> << CPUDirectives [ Directive ] << '\n' ; bool Result = AsmPrinter :: doInitialization ( M ) ; assert ( MMI ) ; TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {

OutStreamer . SwitchSection ( TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ;


<s> extract_insn ( insn ) ; io -> type = ( enum frv_io_type ) INTVAL ( recog_data . operand [ <NUM_LIT> ] ) ;

io -> const_address = INTVAL ( recog_data . operand [ <NUM_LIT> ] ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ;


<s> if ( ! setTargetShuffleZeroElements ( Op , Mask , Inputs ) ) if ( ! getFauxShuffleMask ( Op , Mask , Inputs , DAG ) ) return false ; resolveTargetShuffleInputsAndMask ( Inputs , Mask ) ; return Inputs . size ( ) <= <NUM_LIT> ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( ADDri ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; return ; } if ( NumBytes >= <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( HI22 ( NumBytes ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( LO10 ( NumBytes ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDrr ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return ; } BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( HIX22 ( NumBytes ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( LOX10 ( NumBytes ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDrr ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> if ( ! SrcTy . isSimple ( ) || ! DstTy . isSimple ( ) ) return TargetTransformInfo :: getCastInstrCost ( Opcode , Dst , Src ) ; static const TypeConversionCostTblEntry < <STR_LIT> > AVXConversionTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX ( ) ) { int Idx = ConvertCostTableLookup ( AVXConversionTbl , ISD , DstTy . getSimpleVT ( ) , SrcTy . getSimpleVT ( ) ) ; if ( Idx != - <NUM_LIT> ) return AVXConversionTbl [ Idx ] . Cost ; } return TargetTransformInfo :: getCastInstrCost ( Opcode , Dst , Src ) ;


<s> if ( ! TARGET_32BIT ) return false ;


<s> OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( VFCMPH ) ; OPCODE ( VFCMPHE ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ;


<s> RegEnc |= SDWA9EncValues :: SRC_SGPR_MASK ; } return RegEnc ; } else { const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint32_t Enc = getLitEncoding ( MO , Desc . OpInfo [ OpNo ] , STI ) ; if ( Enc != ~ <NUM_LIT> && Enc != <NUM_LIT> ) { return Enc | SDWA9EncValues :: SRC_SGPR_MASK ;


<s> case ARM_PCS_AAPCS64 : return DFmode ; case ARM_PCS_SIMD : return TFmode ; case ARM_PCS_SVE : if ( aarch64_emit_cfi_for_reg_p ( regno ) ) return VNx2DImode ; return VNx16QImode ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; if ( Intrinsic == <STR_LIT> ) Info . memVT = <STR_LIT> ; else if ( Intrinsic == <STR_LIT> ) Info . memVT = getPointerTy ( ) ; else Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . vol = <NUM_LIT> ; Info . readMem = true ; Info . writeMem = false ; Info . align = <NUM_LIT> ; return true ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const {

return & InstrInfo . getRegisterInfo ( ) ;


<s> Domain = DefMI -> second -> getDesc ( ) . TSFlags & <STR_LIT> ; if ( Domain == <STR_LIT> ) Domain = <STR_LIT> ; } if ( Domain & <STR_LIT> ) { unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DEBUG ( { errs ( ) << <STR_LIT> ; MI -> dump ( ) ; } ) ; AddDefaultPred ( BuildMI ( MBB , * MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ) ; MBB . erase ( MI ) ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; DEBUG ( { errs ( ) << <STR_LIT> ; MI -> dump ( ) ; } ) ; Modified = true ; ++ NumVMovs ; } else { assert ( ( Domain & <STR_LIT> ) && <STR_LIT> ) ;


<s> bool nios2_fpu_insn_enabled ( enum n2fpu_code code ) { return N2FPU_ENABLED_P ( code ) ;


<s> if ( StackBumpBytes >= <NUM_LIT> ) return false ; if ( MFI -> hasVarSizedObjects ( ) ) return false ; if ( RegInfo -> needsStackRealignment ( MF ) ) return false ; if ( canUseRedZone ( MF ) ) return false ; if ( hasVarSizedRegions ( MF ) ) return false ;


<s> const MCExpr * ValueExpr ; if ( Parser . parseExpression ( ValueExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ValueExpr ) ; if ( ! CE ) return Error ( ValueExprLoc , <STR_LIT> ) ; IntegerValue = CE -> getValue ( ) ; } else { if ( Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; StringValue = Parser . getTok ( ) . getStringContents ( ) ; Parser . Lex ( ) ; } if ( Parser . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( Tag == <STR_LIT> ) { StringRef Arch = StringValue ; for ( auto Feature : <ISA_LIT>FeatureKV ) if ( llvm :: <STR_LIT> ( Feature . Key ) ) clearFeatureBits ( Feature . Value , Feature . Key ) ; auto ParseResult = llvm :: <STR_LIT> ( StringValue , true , false ) ; if ( ! ParseResult ) { std :: string Buffer ; raw_string_ostream OutputErrMsg ( Buffer ) ; handleAllErrors ( ParseResult . takeError ( ) , [ & ] ( llvm :: StringError & ErrMsg ) { OutputErrMsg << <STR_LIT> << Arch << <STR_LIT> << ErrMsg . getMessage ( ) ; } ) ; return Error ( ValueExprLoc , OutputErrMsg . str ( ) ) ; } auto & ISAInfo = * ParseResult ; for ( auto Feature : <ISA_LIT>FeatureKV ) if ( ISAInfo -> hasExtension ( Feature . Key ) ) setFeatureBits ( Feature . Value , Feature . Key ) ; if ( ISAInfo -> getXLen ( ) == <NUM_LIT> ) clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; else if ( ISAInfo -> getXLen ( ) == <NUM_LIT> ) setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; else return Error ( ValueExprLoc , <STR_LIT> + Arch ) ; } if ( IsIntegerValue ) getTargetStreamer ( ) . emitAttribute ( Tag , IntegerValue ) ; else { if ( Tag != <STR_LIT> ) { getTargetStreamer ( ) . emitTextAttribute ( Tag , StringValue ) ; } else { std :: vector < std :: string > FeatureVector ; <STR_LIT> ( FeatureVector , getSTI ( ) . getFeatureBits ( ) ) ; unsigned XLen = getFeatureBits ( <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; auto ParseResult = llvm :: <STR_LIT> ( XLen , FeatureVector ) ; if ( ! ParseResult ) { std :: string Buffer ; raw_string_ostream OutputErrMsg ( Buffer ) ; handleAllErrors ( ParseResult . takeError ( ) , [ & ] ( llvm :: StringError & ErrMsg ) { OutputErrMsg << ErrMsg . getMessage ( ) ; } ) ; return Error ( ValueExprLoc , OutputErrMsg . str ( ) ) ; } auto & ISAInfo = * ParseResult ; getTargetStreamer ( ) . emitTextAttribute ( Tag , ISAInfo -> toString ( ) ) ;


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;

Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> + RegNo ) ) ;


<s> return isOperandOfVmullHighP64 ( Op1 ) && isOperandOfVmullHighP64 ( Op2 ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ;


<s> void emitByte ( uint8_t C , unsigned & CurByte , raw_ostream & OS ) const { OS << ( char ) C ; ++ CurByte ;


<s> if ( MFI . getStackID ( Idx ) == TargetStackID :: Default ) { Offset += MFI . getStackSize ( ) ; } switch ( MI -> getOpcode ( ) ) { default : MI -> getOperand ( FIOperandNum ) . ChangeToTargetIndex ( <STR_LIT> , Offset , MI -> getOperand ( FIOperandNum ) . getTargetFlags ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( getFrameRegister ( MF ) , false ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . setImm ( Offset ) ; break ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : expandAddrLostk ( MI ) ; break ; case <STR_LIT> : expandAddrHistk ( MI ) ;


<s> if ( uses . test ( i ) ) return false ; }


<s> crtl -> preferred_stack_boundary = <NUM_LIT> ; crtl -> stack_alignment_needed = <NUM_LIT> ; } stack_alignment_needed = crtl -> stack_alignment_needed / BITS_PER_UNIT ; preferred_alignment = crtl -> preferred_stack_boundary / BITS_PER_UNIT ; gcc_assert ( ! size || stack_alignment_needed ) ; gcc_assert ( preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT ) ; gcc_assert ( preferred_alignment <= stack_alignment_needed ) ; if ( TARGET_SEH ) cfun -> machine -> use_fast_prologue_epilogue = false ; else if ( ! optimize_bb_for_size_p ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) && cfun -> machine -> use_fast_prologue_epilogue_nregs != frame -> nregs ) { int count = frame -> nregs ; struct cgraph_node * node = cgraph_node :: get ( current_function_decl ) ; cfun -> machine -> use_fast_prologue_epilogue_nregs = count ; if ( count ) count = ( count - <NUM_LIT> ) * FAST_PROLOGUE_INSN_COUNT ; if ( node -> frequency < NODE_FREQUENCY_NORMAL || ( flag_branch_probabilities && node -> frequency < NODE_FREQUENCY_HOT ) ) cfun -> machine -> use_fast_prologue_epilogue = false ; else cfun -> machine -> use_fast_prologue_epilogue = ! expensive_function_p ( count ) ; } frame -> save_regs_using_mov = ( TARGET_PROLOGUE_USING_MOVE && cfun -> machine -> use_fast_prologue_epilogue && flag_stack_check != STATIC_BUILTIN_STACK_CHECK ) ; offset = UNITS_PER_WORD ; if ( ix86_static_chain_on_stack ) offset += UNITS_PER_WORD ;

if ( frame_pointer_needed ) offset += UNITS_PER_WORD ;


<s> void GCNPassConfig :: addFastRegAlloc ( FunctionPass * RegAllocPass ) { insertPass ( & PHIEliminationID , & <ISA_LIT>LowerControlFlowID , false ) ;

insertPass ( & <ISA_LIT>LowerControlFlowID , & <ISA_LIT>FixWWMLivenessID , false ) ;


<s> return OFF ; } int64_t Imm = <NUM_LIT> ; while ( true ) { unsigned Mode = <NUM_LIT> ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; for ( unsigned ModeId = ID_MIN ; ModeId <= ID_MAX ; ++ ModeId ) { if ( trySkipId ( IdSymbolic [ ModeId ] ) ) { Mode = <NUM_LIT> << ModeId ; break ; } } if ( Mode == <NUM_LIT> ) { Error ( S , ( Imm == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; break ; } if ( Imm & Mode ) { Error ( S , <STR_LIT> ) ; break ; } Imm |= Mode ; if ( trySkipToken ( AsmToken :: RParen ) ) break ; if ( ! skipToken ( AsmToken :: Comma , <STR_LIT> ) ) break ; }


<s> c = vec_adds ( a , b ) ; return ( __m64 ) ( ( __vector long long ) c ) [ <NUM_LIT> ] ;


<s> FunctionPass * llvm :: create<ISA_LIT>ConditionalCompares ( ) { return new <ISA_LIT>ConditionalCompares ( ) ;


<s> case <ISA_LIT>Subtarget :: N64 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: EABI : return <STR_LIT> ; default : break ; } llvm_unreachable ( <STR_LIT> ) ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MFI , MachineBasicBlock :: iterator & MBBI , LiveVariables * LV ) const {


<s> if ( ImmVal < <NUM_LIT> || ! isUInt < <NUM_LIT> > ( ImmVal ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else { return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , ImmVal , Loc , <ISA_LIT>Operand :: ImmTyHwreg ) ) ; return MatchOperand_Success ;


<s> Ops . push_back ( & II -> getOperandUse ( <NUM_LIT> ) ) ; return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 , Ext2 ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } default :


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> bool useZRegOps ( ) const { return UseZRegOps ;


<s> DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( create<ISA_LIT>MacroFusionDAGMutation ( ) ) ;


<s> addRegisterClass ( VT , & <STR_LIT> ) ; addTypeForNEON ( VT , <STR_LIT> , <STR_LIT> ) ;


<s> unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : return true ; case AARCH64_BUILTIN_SVE : return <STR_LIT> ( loc , arg_loc , subcode , orig_fndecl , nargs , args ) ; } gcc_unreachable ( ) ;


<s> void <ISA_LIT>MachineFunctionInfo :: anchor ( ) {


<s> unsigned getScalarizationOverhead ( Type * Ty , bool Insert , bool Extract ) {


<s> rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( d -> flag & BUILTIN_DESC_SWAP_OPERANDS ) std :: swap ( op0 , op1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ;

target = gen_rtx_SUBREG ( QImode , target , <NUM_LIT> ) ;


<s> const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; uint16_t DestEncoding = TRI -> getEncodingValue ( DestReg ) ; uint16_t SrcEncoding = TRI -> getEncodingValue ( SrcReg ) ; unsigned NumRegs = Indices . size ( ) ; int SubReg = <NUM_LIT> , End = NumRegs , Incr = <NUM_LIT> ; if ( forwardCopyWillClobberTuple ( DestEncoding , SrcEncoding , NumRegs ) ) { SubReg = NumRegs - <NUM_LIT> ; End = - <NUM_LIT> ; Incr = - <NUM_LIT> ; } for ( ; SubReg != End ; SubReg += Incr ) { const MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opcode ) ) ; AddSubReg ( MIB , DestReg , Indices [ SubReg ] , RegState :: Define , TRI ) ; AddSubReg ( MIB , SrcReg , Indices [ SubReg ] , <NUM_LIT> , TRI ) ; AddSubReg ( MIB , SrcReg , Indices [ SubReg ] , getKillRegState ( KillSrc ) , TRI ) ;


<s> phase1_vrs saved_vrs ; _Unwind_Reason_Code pr_result ; entry_vrs -> core . r [ R_PC ] = entry_vrs -> core . r [ R_LR ] ; saved_vrs . core = entry_vrs -> core ; saved_vrs . demand_save_flags = ~ ( _uw ) <NUM_LIT> ; do { if ( get_eit_entry ( ucbp , saved_vrs . core . r [ R_PC ] ) != _URC_OK ) return _URC_FAILURE ; pr_result = ( ( personality_routine ) UCB_PR_ADDR ( ucbp ) ) ( _US_VIRTUAL_UNWIND_FRAME , ucbp , ( void * ) & saved_vrs ) ; } while ( pr_result == _URC_CONTINUE_UNWIND ) ; restore_non_core_regs ( & saved_vrs ) ; if ( pr_result != _URC_HANDLER_FOUND ) {


<s> return MO1 . isIdenticalTo ( MO2 ) && ( ! MO1 . isReg ( ) || ! TargetRegisterInfo :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) , Subtarget ( nullptr ) , OptForMinSize ( false ) , IndirectTlsSegRefs ( false ) {


<s> SDValue newLoad = DAG . getLoad ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Op , load -> getChain ( ) , load -> getBasePtr ( ) , load -> getOffset ( ) , <STR_LIT> , load -> getMemOperand ( ) ) ; SDValue newTrunc = DAG . getZExtOrTrunc ( newLoad , Op , <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { newTrunc , newLoad . getOperand ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , Op ) ;


<s> jobject jobj = env -> NewObject ( cls , cnstr ) ; if ( NULL == jobj ) return nullptr ; jmethodID mid = env -> GetMethodID ( cls , <STR_LIT> , <STR_LIT> ) ; if ( NULL == mid ) return nullptr ; jstring jstr = env -> NewStringUTF ( asmFile . c_str ( ) ) ; if ( NULL == jstr ) return nullptr ; LLVM_DEBUG ( llvm :: dbgs ( ) << <STR_LIT> << strlen ( asmFile . c_str ( ) ) << <STR_LIT> ) ;

env -> CallVoidMethod ( jobj , mid , jstr ) ;


<s> return AMDGPU :: SReg_32RegClass . getRegister ( MFI -> NumUserSGPRs + <NUM_LIT> ) ; case <ISA_LIT>RegisterInfo :: TGID_Y : return AMDGPU :: SReg_32RegClass . getRegister ( MFI -> NumUserSGPRs + <NUM_LIT> ) ; case <ISA_LIT>RegisterInfo :: TGID_Z : return AMDGPU :: SReg_32RegClass . getRegister ( MFI -> NumUserSGPRs + <NUM_LIT> ) ; case <ISA_LIT>RegisterInfo :: SCRATCH_WAVE_OFFSET : if ( MFI -> getShaderType ( ) != ShaderType :: COMPUTE ) return MFI -> ScratchOffsetReg ; return AMDGPU :: SReg_32RegClass . getRegister ( MFI -> NumUserSGPRs + <NUM_LIT> ) ; case <ISA_LIT>RegisterInfo :: SCRATCH_PTR : return AMDGPU :: SGPR2_SGPR3 ; case <ISA_LIT>RegisterInfo :: INPUT_PTR :


<s> uint32_t Sel = SelMO . getImm ( ) ; Emit ( Sel , OS ) ; } else { EmitByte ( <NUM_LIT> , OS ) ; Emit ( ( uint32_t ) <NUM_LIT> , OS ) ; } if ( Reg == AMDGPU :: ALU_LITERAL_X ) { unsigned ImmOpIndex = MI . getNumOperands ( ) - <NUM_LIT> ; MCOperand ImmOp = MI . getOperand ( ImmOpIndex ) ; if ( ImmOp . isFPImm ( ) ) { InlineConstant . f = ImmOp . getFPImm ( ) ;


<s> assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; Type * ScalarType = Val -> getScalarType ( ) ; int RegisterFileMoveCost = <NUM_LIT> ; if ( Index == - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { assert ( isa < FixedVectorType > ( Val ) && <STR_LIT> ) ; Align VecAlign = DL . getPrefTypeAlign ( Val ) ; Align SclAlign = DL . getPrefTypeAlign ( ScalarType ) ; if ( Opcode == Instruction :: ExtractElement ) { return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } if ( Opcode == Instruction :: InsertElement ) { return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Store , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } } if ( Index != - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { if ( Opcode == Instruction :: ExtractElement && ScalarType -> getScalarSizeInBits ( ) == <NUM_LIT> && cast < FixedVectorType > ( Val ) -> getNumElements ( ) > <NUM_LIT> ) return <NUM_LIT> ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned SizeInBits = LT . second . getSizeInBits ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned SubNumElts = NumElts ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> break ; } if ( OverrideNEON && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) return Subtarget -> hasSVE ( ) ; if ( VT . getFixedSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( ! Subtarget -> useSVEForFixedLengthVectors ( ) ) return false ;

if ( VT . getFixedSizeInBits ( ) > Subtarget -> getMinSVEVectorSizeInBits ( ) ) return false ;


<s> Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ; return DAG . getMergeValues ( Ops1 , dl ) ; } else { SDValue Flag ; unsigned Reg = ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Reg , Size , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Flag ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( getTargetMachine ( ) . getRegisterInfo ( ) ) ; unsigned SPReg = RegInfo -> getStackRegister ( ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , SPTy ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { SDLoc DL ( Op ) ; SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , N0 ) ; SDValue Ops [ ] = { N0 , Neg , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Neg . getNode ( ) , <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ; } if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSE41 ( ) ) { SDLoc DL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Src ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , Src , Sub , Src ) ;


<s> F . addFnAttr ( <STR_LIT> , <STR_LIT> ) ; emitExceptionRegistrationRecord ( & F ) ; auto * MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; std :: unique_ptr < WinEHFuncInfo > FuncInfoPtr ; if ( ! MMI ) FuncInfoPtr . reset ( new WinEHFuncInfo ( ) ) ; WinEHFuncInfo & FuncInfo = * ( MMI ? & MMI -> getWinEHFuncInfo ( & F ) : FuncInfoPtr . get ( ) ) ; FuncInfo . EHRegNode = RegNode ; switch ( Personality ) { default : llvm_unreachable ( <STR_LIT> ) ; case EHPersonality :: MSVC_CXX : addCXXStateStores ( F , FuncInfo ) ; break ; case EHPersonality :: MSVC_<ISA_LIT>SEH : addSEHStateStores ( F , FuncInfo ) ;


<s> EVT VT = ExtVal . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return false ; if ( ExtVal -> use_empty ( ) || ! ExtVal -> use_begin ( ) -> isOnlyUserOf ( ExtVal . getNode ( ) ) ) return true ; SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) ) return false ;


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; switch ( IntrinsicID ) { default : return Op ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; if ( SDValue Flags = combineSetCCEFLAGS ( EFLAGS , CC , DAG ) ) { SDValue Cond = DAG . getConstant ( CC , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Cond , Flags ) ;


<s> Value * Row = nullptr , * Col = nullptr ; Use & U = * ( Bitcast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = cast < IntrinsicInst > ( U . getUser ( ) ) ;

std :: tie ( Row , Col ) = getShape ( II , OpNo ) ;


<s> MVT SadVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , SadVecVT , V , Zeros ) ; return DAG . getBitcast ( VT , V ) ; } if ( EltVT == <STR_LIT> ) { SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , DL ) ; SDValue V32 = DAG . getBitcast ( VT , V ) ; SDValue Low = DAG . getNode ( <STR_LIT> , DL , VT , V32 , Zeros ) ; SDValue High = DAG . getNode ( <STR_LIT> , DL , VT , V32 , Zeros ) ; Zeros = getZeroVector ( ByteVecVT , Subtarget , DAG , DL ) ; MVT SadVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; Low = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , Low ) , Zeros ) ; High = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , High ) , Zeros ) ; MVT ShortVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , DAG . getBitcast ( ShortVecVT , Low ) , DAG . getBitcast ( ShortVecVT , High ) ) ; return DAG . getBitcast ( VT , V ) ; } assert ( EltVT == <STR_LIT> && <STR_LIT> ) ; SDValue ShifterV = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( VT , V ) , ShifterV ) ; V = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , DAG . getBitcast ( ByteVecVT , Shl ) , DAG . getBitcast ( ByteVecVT , V ) ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( VT , V ) , ShifterV ) ;


<s> break ; case <STR_LIT> : if ( UnsupportedFPMode ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( NextFGR32 == FGR32ArgRegs . end ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << * NextFGR32 << <STR_LIT> ) ; Allocation . emplace_back ( & <STR_LIT> , * NextFGR32 ++ ) ; if ( NextGPR32 != GPR32ArgRegs . end ( ) ) NextGPR32 ++ ; if ( NextAFGR64 != AFGR64ArgRegs . end ( ) ) NextAFGR64 ++ ; break ; case <STR_LIT> : if ( UnsupportedFPMode ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( NextAFGR64 == AFGR64ArgRegs . end ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << * NextAFGR64 << <STR_LIT> ) ; Allocation . emplace_back ( & <STR_LIT> , * NextAFGR64 ++ ) ; if ( NextGPR32 != GPR32ArgRegs . end ( ) ) NextGPR32 ++ ; if ( NextGPR32 != GPR32ArgRegs . end ( ) ) NextGPR32 ++ ; if ( NextFGR32 != FGR32ArgRegs . end ( ) ) NextFGR32 ++ ; break ; default : DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } for ( const auto & FormalArg : F -> args ( ) ) { unsigned ArgNo = FormalArg . getArgNo ( ) ; unsigned SrcReg = Allocation [ ArgNo ] . Reg ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , Allocation [ ArgNo ] . RC ) ; unsigned ResultReg = createResultReg ( Allocation [ ArgNo ] . RC ) ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ;


<s> bool is16BitMode ( ) const { return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> FixedVectorType * Ty ; if ( I -> getIntrinsicID ( ) == <STR_LIT> ) Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; else Ty = cast < FixedVectorType > ( I -> getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Loop * L = LI -> getLoopFor ( I -> getParent ( ) ) ; if ( L == nullptr ) return nullptr ; GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; Value * Offsets ; Value * BasePtr = decomposeGEP ( Offsets , Ty , GEP , Builder ) ; if ( ! BasePtr ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; DataLayout DT = I -> getParent ( ) -> getParent ( ) -> getParent ( ) -> getDataLayout ( ) ; int TypeScale = computeScale ( DT . getTypeSizeInBits ( GEP -> getOperand ( <NUM_LIT> ) -> getType ( ) ) , DT . getTypeSizeInBits ( GEP -> getType ( ) ) / cast < FixedVectorType > ( GEP -> getType ( ) ) -> getNumElements ( ) ) ;

if ( TypeScale == - <NUM_LIT> ) return nullptr ;


<s> if ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) return true ;


<s> requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ;


<s> void print ( raw_ostream & O ) const override { switch ( Kind ) { case k_None : O << <STR_LIT> ; break ; case k_Token : O << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case k_Register : O << <STR_LIT> << getReg ( ) ; break ; case k_Immediate : O << <STR_LIT> << * getImm ( ) << <STR_LIT> ;


<s> rtx ref = operands [ <NUM_LIT> ] ; rtx base , scratch ; HOST_WIDE_INT offset = <NUM_LIT> ; if ( GET_CODE ( ref ) == SUBREG ) { offset = SUBREG_BYTE ( ref ) ; ref = SUBREG_REG ( ref ) ; } if ( REG_P ( ref ) ) { if ( reg_equiv_mem ( REGNO ( ref ) ) ) { ref = reg_equiv_mem ( REGNO ( ref ) ) ; base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; } else base = reg_equiv_address ( REGNO ( ref ) ) ; } else base = find_replacement ( & XEXP ( ref , <NUM_LIT> ) ) ; if ( GET_CODE ( base ) == MINUS || ( GET_CODE ( base ) == PLUS && ! CONST_INT_P ( XEXP ( base , <NUM_LIT> ) ) ) ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; emit_set_insn ( base_plus , base ) ; base = base_plus ; } else if ( GET_CODE ( base ) == PLUS ) { HOST_WIDE_INT hi , lo ; offset += INTVAL ( XEXP ( base , <NUM_LIT> ) ) ; base = XEXP ( base , <NUM_LIT> ) ; lo = ( offset >= <NUM_LIT> ? ( offset & <NUM_LIT> ) : - ( ( - offset ) & <NUM_LIT> ) ) ; if ( lo == <NUM_LIT> ) lo &= <NUM_LIT> ; hi = ( ( ( ( offset - lo ) & ( HOST_WIDE_INT ) <NUM_LIT> ) ^ ( HOST_WIDE_INT ) <NUM_LIT> ) - ( HOST_WIDE_INT ) <NUM_LIT> ) ; gcc_assert ( hi + lo == offset ) ; if ( hi != <NUM_LIT> ) { rtx base_plus = gen_rtx_REG ( SImode , REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ;

emit_insn ( gen_addsi3 ( base_plus , base , GEN_INT ( hi ) ) ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; } ; for ( ; ; ) { if ( any_isa < MCInst > ( * Iter ) ) { MCInst Inst = any_cast < MCInst & > ( * Iter ) ; StringRef LoopLabel ; if ( isLoopMCInst ( Inst , LoopLabel ) ) { FlushLastFourInstrs ( true ) ; DoNotCompressNextInst = true ; LoopLabels . emplace_back ( std :: move ( LoopLabel ) ) ; flushInstUncompressed ( Inst , Out , STI ) ; } else { LastFourInstrs . buffer . emplace_back ( std :: move ( Inst ) ) ; ++ LastFourInstrs . instCount ; if ( LastFourInstrs . instCount > <NUM_LIT> ) { Inst = PopFirstInst ( ) ; if ( ! DoNotCompressNextInst && maybeCompressInstr ( Inst , false ) ) flushInstCompressed ( Inst , Out , STI ) ; else { flushInstUncompressed ( Inst , Out , STI ) ; DoNotCompressNextInst = false ; } } } } else { MCSymbol * Label = any_cast < MCSymbol * > ( * Iter ) ; assert ( Label ) ; if ( Label -> getName ( ) == LoopLabels . back ( ) ) { FlushLastFourInstrs ( false ) ; bool IsJmpDest = isJmpLabel ( Label ) ; if ( IsJmpDest ) DoNotCompressNextInst = true ; if ( LoopLabels . size ( ) != <NUM_LIT> || IsJmpDest ) PendingLabels . push_back ( Label ) ; else -- Iter ; LoopLabels . pop_back ( ) ; if ( LoopLabels . empty ( ) ) break ; } else LastFourInstrs . buffer . push_back ( Label ) ; } ++ Iter ; }


<s> unsigned PseudoRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned i = <NUM_LIT> , ie = array_lengthof ( PseudoRegs ) ; i != ie ; ++ i ) { unsigned Reg = PseudoRegs [ i ] ; Mask [ Reg / <NUM_LIT> ] &= ~ ( <NUM_LIT> << ( Reg % <NUM_LIT> ) ) ; }


<s> if ( GET_CODE ( high ) != HIGH || GET_CODE ( XEXP ( high , <NUM_LIT> ) ) != CONST ) return false ;

unspec = XEXP ( XEXP ( high , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> return ( unsigned char ) __builtin_ia32_kortestzdi ( __A , __B ) ;


<s> auto & HRI = getRegisterInfo ( ) ; for ( unsigned oper = <NUM_LIT> ; oper < MI -> getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && MO . isDef ( ) ) { const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true ;


<s> assert ( isPowerOf2_32 ( BitWidth ) && BitWidth >= <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( Opc , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( BitWidth / <NUM_LIT> ) - <NUM_LIT> , DL , XLenVT ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Opc = IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Opc = IntNo == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : assert ( Op . getValueType ( ) == XLenVT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return lowerScalarSplat ( Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getSimpleValueType ( ) , DL , DAG , Subtarget ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { SDValue Scalar = Op . getOperand ( <NUM_LIT> ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) { Scalar = DAG . getNode ( <STR_LIT> , DL , XLenVT , Scalar ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Scalar , Op . getOperand ( <NUM_LIT> ) ) ; } assert ( Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno >= <NUM_LIT> ; -- regno ) if ( need_to_save_reg ( regno , <NUM_LIT> ) ) reg_save_size += <NUM_LIT> ;


<s> initSubtargetFeatures ( CPU , FS ) ; return * this ;


<s> <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; default : return - <NUM_LIT> ; } } if ( IsD16Unpacked ) { switch ( NumElts ) { case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return Offen ? <STR_LIT> : <STR_LIT> ; default : return - <NUM_LIT> ; } } switch ( NumElts ) { case <NUM_LIT> : return Offen ? <STR_LIT> :


<s> for ( unsigned i = <NUM_LIT> , e = RegInfo -> getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( RegInfo -> getRegClass ( Reg ) == & <STR_LIT> ) { HasVectorVReg = true ; break ; } } if ( ! HasVectorVReg ) return ; unsigned InVRSAVE = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; unsigned UpdatedVRSAVE = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & EntryBB = * Fn . begin ( ) ; DebugLoc dl ; MachineBasicBlock :: iterator IP = EntryBB . begin ( ) ;

BuildMI ( EntryBB , IP , dl , TII . get ( <STR_LIT> ) , InVRSAVE ) ;


<s> case <STR_LIT> : { unsigned ConstraintID = InlineAsm :: getMemoryConstraintID ( MO . getImm ( ) ) ; switch ( ConstraintID ) { case InlineAsm :: Constraint_ZC : { const <ISA_LIT>Subtarget & Subtarget = MO . getParent ( ) -> getParent ( ) -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . inMicro<ISA_LIT>Mode ( ) ) return <NUM_LIT> ; if ( Subtarget . has<ISA_LIT>32r6 ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; }


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { ds [ i ] = * d ; ds [ i ] . vmode = V32HImode ; ds [ i ] . nelt = <NUM_LIT> ; ds [ i ] . target = gen_reg_rtx ( V32HImode ) ; ds [ i ] . op0 = gen_lowpart ( V32HImode , d -> op0 ) ; ds [ i ] . op1 = gen_lowpart ( V32HImode , d -> op1 ) ; } for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { ds [ i & <NUM_LIT> ] . perm [ i / <NUM_LIT> ] = d -> perm [ i ] / <NUM_LIT> ; if ( i & <NUM_LIT> ) { rperm [ i ] = constm1_rtx ; rperm [ i + <NUM_LIT> ] = GEN_INT ( ( i & <NUM_LIT> ) + ( d -> perm [ i ] & <NUM_LIT> ) ) ; } else { rperm [ i ] = GEN_INT ( ( i & <NUM_LIT> ) + ( d -> perm [ i ] & <NUM_LIT> ) ) ;


<s> int NVOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( LHS , RHS , CC , A64cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , DAG . getConstant ( <NUM_LIT> , VT ) , DAG . getConstant ( <NUM_LIT> , VT ) , A64cc ) ; } <STR_LIT> CondCode , Alternative = <STR_LIT> ; CondCode = FPCCToA64CC ( CC , Alternative ) ; SDValue A64cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue CmpOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , DAG . getCondCode ( CC ) ) ; SDValue A64SELECT_CC = DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , DAG . getConstant ( <NUM_LIT> , VT ) , DAG . getConstant ( <NUM_LIT> , VT ) , A64cc ) ; if ( Alternative != <STR_LIT> ) { A64cc = DAG . getConstant ( Alternative , <STR_LIT> ) ; A64SELECT_CC = DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , DAG . getConstant ( <NUM_LIT> , VT ) , A64SELECT_CC , A64cc ) ; } return A64SELECT_CC ;


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>elDisassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64elTarget ( ) , create<ISA_LIT>elDisassembler ) ;


<s> const Triple & TheTriple = STI . getTargetTriple ( ) ; if ( TheTriple . isOSBinFormatMachO ( ) ) { return new Darwin<ISA_LIT>AsmBackend ( T , TheTriple , MRI ) ; } if ( TheTriple . isOSBinFormatCOFF ( ) ) return new COFF<ISA_LIT>AsmBackend ( T , TheTriple ) ;

assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ;


<s> if ( ! Subtarget . hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : return true ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>PulpHWLoopsPass ( ) ) ;


<s> int64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getSExtValue ( ) ; if ( ( IsSigned && isInt < <NUM_LIT> > ( COffsetVal ) ) || ( ! IsSigned && isUInt < <NUM_LIT> > ( COffsetVal ) ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ; Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ; SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ; return true ;


<s> if ( isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'L' : if ( isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'K' : if ( isUInt < <NUM_LIT> > ( Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'M' : if ( Value > <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'N' : if ( Value > <NUM_LIT> && isPowerOf2_64 ( Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'O' : if ( Value == <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ; case 'P' : if ( isInt < <NUM_LIT> > ( - Value ) ) Result = DAG . getTargetConstant ( Value , dl , TCVT ) ; break ;


<s> SDValue V = V1 ; unsigned Opcode ; int ShiftAmt = matchVectorShuffleAsShift ( ShiftVT , Opcode , VT . getScalarSizeInBits ( ) , Mask , <NUM_LIT> , Zeroable , Subtarget ) ; if ( ShiftAmt < <NUM_LIT> ) { ShiftAmt = matchVectorShuffleAsShift ( ShiftVT , Opcode , VT . getScalarSizeInBits ( ) , Mask , Size , Zeroable , Subtarget ) ; V = V2 ;


<s> loongarch_emit_move ( dest , loongarch_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || ( can_create_pseudo_p ( ) ) ) ) { base = loongarch_force_temporary ( dest , base ) ; loongarch_emit_move ( dest , loongarch_add_offset ( NULL , base , INTVAL ( offset ) ) ) ;


<s> R600ExpandSpecialInstrsPass ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TII ( nullptr ) {


return DAG . getNode ( cmp_code , dl , <STR_LIT> , LHS , RHS ) ;


<s> if ( ExtractVT != <STR_LIT> && ExtractVT != <STR_LIT> ) return SDValue ( ) ; <STR_LIT> BinOp ; SDValue Src = DAG . matchBinOpReduction ( Extract , BinOp , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ; if ( ! Src ) return SDValue ( ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcSVT = SrcVT . getScalarType ( ) ; if ( SrcSVT != ExtractVT || ( SrcVT . getSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue MinPos = Src ; while ( SrcVT . getSizeInBits ( ) > <NUM_LIT> ) { unsigned NumElts = SrcVT . getVectorNumElements ( ) ; unsigned NumSubElts = NumElts / <NUM_LIT> ; SrcVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcSVT , NumSubElts ) ; unsigned SubSizeInBits = SrcVT . getSizeInBits ( ) ; SDValue Lo = extractSubVector ( MinPos , <NUM_LIT> , DAG , DL , SubSizeInBits ) ; SDValue Hi = extractSubVector ( MinPos , NumSubElts , DAG , DL , SubSizeInBits ) ; MinPos = DAG . getNode ( BinOp , DL , SrcVT , Lo , Hi ) ; } assert ( ( ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) || ( SrcVT == <STR_LIT> && ExtractVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Mask ; unsigned MaskEltsBits = ExtractVT . getSizeInBits ( ) ; if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMaxValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getSignedMinValue ( MaskEltsBits ) , DL , SrcVT ) ; else if ( BinOp == <STR_LIT> ) Mask = DAG . getConstant ( APInt :: getAllOnesValue ( MaskEltsBits ) , DL , SrcVT ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ; if ( ExtractVT == <STR_LIT> ) { SDValue Upper = DAG . getVectorShuffle ( SrcVT , DL , MinPos , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , MinPos , Upper ) ; } MinPos = DAG . getBitcast ( <STR_LIT> , MinPos ) ; MinPos = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MinPos ) ; MinPos = DAG . getBitcast ( SrcVT , MinPos ) ; if ( Mask ) MinPos = DAG . getNode ( <STR_LIT> , DL , SrcVT , Mask , MinPos ) ;

return DAG . getNode ( <STR_LIT> , DL , ExtractVT , MinPos , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> if ( ST -> hasNEON ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } return <NUM_LIT> ;


<s> if ( m1 == CCZmode && ( m2 == CCGCmode || m2 == CCGOCmode || m2 == CCNOmode ) ) return m2 ; else if ( m2 == CCZmode && ( m1 == CCGCmode || m1 == CCGOCmode || m1 == CCNOmode ) ) return m1 ; switch ( m1 ) { default : gcc_unreachable ( ) ; case E_CCmode : case E_CCGCmode : case E_CCGOCmode : case E_CCNOmode : case E_CCAmode : case E_CCCmode : case E_CCOmode :


<s> ValueVec RemoveInstrs ; auto GetRootValue = [ & ] ( Value * V ) -> Value * { while ( isa < CastInst > ( V ) ) { RemoveInstrs . push_back ( V ) ; V = cast < User > ( V ) -> getOperand ( <NUM_LIT> ) ; } return V ; } ; Value * Dst = CI -> getOperand ( <NUM_LIT> ) ; Value * Src = CI -> getOperand ( <NUM_LIT> ) ; Value * Size = CI -> getOperand ( <NUM_LIT> ) ;


<s> return sparc_function_value_1 ( valtype , TYPE_MODE ( valtype ) , outgoing ) ;


<s> bool LookupPresent = false ; for ( MachineBasicBlock & MBB : * MF ) { for ( MachineBasicBlock :: iterator mi = MBB . begin ( ) , me = MBB . end ( ) ; mi != me ; mi ++ ) { LookupPresent |= ( <ISA_LIT>II :: isLookup ( ( * mi ) . getDesc ( ) ) || <ISA_LIT>II :: isLookupC ( ( * mi ) . getDesc ( ) ) ) ; } } if ( ! LookupPresent ) { auto firstInst = MF -> getBlockNumbered ( <NUM_LIT> ) -> instr_begin ( ) ; MachineInstr * cacheIns = MF -> CreateMachineInstr ( TII -> get ( <STR_LIT> ) , firstInst -> getDebugLoc ( ) , true ) ;

cacheIns -> addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: createExpr ( Expr ) ;


<s> unsigned TargetMask = LKZ . getZExtValue ( ) ; unsigned InsertMask = RKZ . getZExtValue ( ) ; if ( ( TargetMask | InsertMask ) == <NUM_LIT> ) { unsigned Op0Opc = Op0 . getOpcode ( ) ; unsigned Op1Opc = Op1 . getOpcode ( ) ; unsigned Value , SH = <NUM_LIT> ; TargetMask = ~ TargetMask ; InsertMask = ~ InsertMask ; if ( Op0Opc == <STR_LIT> && Op1Opc == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } } else if ( Op0Opc == <STR_LIT> || Op0Opc == <STR_LIT> ) { if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) {


<s> return HasInvariantFunctionDescriptors ;


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_mask_i64gather_epi32 ( __m128i src , int const * base , __m256i index , __m128i mask , const int scale ) { return ( __m128i ) __builtin_ia32_gatherdiv4si256 ( ( __v4si ) src , base , ( __v4di ) index , ( __v4si ) mask , scale ) ;


<s> Op -> Imm . Val = Val ; Op -> Imm . IsFPImm = IsFPImm ; Op -> Imm . Type = Type ;


<s> EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TargetExpr ) ) ; for ( int8_t I = <NUM_LIT> ; I < NoopsInSledCount ; I ++ ) EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; OutStreamer -> EmitLabel ( Target ) ; if ( ! Subtarget -> isGP64bit ( ) ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } recordSled ( CurSled , MI , Kind ) ;


<s> MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( VT . is256BitVector ( ) && NumElts == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int Elt = N -> getMaskElt ( i ) ;


<s> case E_V8HImode : case E_V4SFmode : case E_V4SImode : case E_V2DFmode : case E_V2DImode : case E_V1TImode : case E_TImode : case E_TFmode : case E_KFmode :

if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return mode_supports_dq_form ( mode ) ;


<s> if ( Amount == <NUM_LIT> ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ;


<s> return TargetTriple . isOSFuchsia ( ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> fputs ( <STR_LIT> , file ) ; } assemble_name ( file , label ) ; fputc ( '\n' , file ) ; if ( flag_pic ) { ASM_GENERATE_INTERNAL_LABEL ( labelpc , <STR_LIT> , labelno ) ; assemble_name ( file , labelpc ) ; fputs ( <STR_LIT> , file ) ; if ( TARGET_THUMB1_ONLY ) { fputs ( <STR_LIT> , file ) ; fputs ( <STR_LIT> , file ) ; } else fputs ( <STR_LIT> , file ) ; } else if ( TARGET_THUMB1_ONLY ) fputs ( <STR_LIT> , file ) ; } if ( TARGET_THUMB1_ONLY ) { if ( mi_delta > <NUM_LIT> ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , label ) ; fputs ( <STR_LIT> , file ) ; asm_fprintf ( file , <STR_LIT> , mi_op , this_regno , this_regno ) ; } else if ( mi_delta != <NUM_LIT> ) { asm_fprintf ( file , <STR_LIT> , mi_op , this_regno , this_regno , mi_delta ) ; } } else { while ( mi_delta != <NUM_LIT> ) { if ( ( mi_delta & ( <NUM_LIT> << shift ) ) == <NUM_LIT> ) shift += <NUM_LIT> ; else {

asm_fprintf ( file , <STR_LIT> , mi_op , this_regno , this_regno , mi_delta & ( <NUM_LIT> << shift ) ) ;


<s> bool <ISA_LIT>FastISel :: isTypeSupported ( Type * Ty , MVT & VT , bool IsVectorAllowed ) { if ( Ty -> isVectorTy ( ) && ! IsVectorAllowed ) return false ; if ( isTypeLegal ( Ty , VT ) ) return true ;

if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return true ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ; return createELFObjectWriter ( MOTW , OS , false ) ;


<s> Parser . Lex ( ) ; const AsmToken & NextTok = Parser . getTok ( ) ; if ( NextTok . isNot ( AsmToken :: Identifier ) ) return true ; Str += <STR_LIT> ; Str += NextTok . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) return true ; } else break ; } if ( getParser ( ) . parseParenExpression ( IdVal , EndLoc ) ) return true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: RParen ) Parser . Lex ( ) ; } else return true ; Res = evaluateRelocExpr ( IdVal , Str ) ; return false ;


<s> DuplicateInstruction . push_back ( after ) ; for ( unsigned op = <NUM_LIT> ; op < after -> getNumOperands ( ) ; op ++ ) {

if ( auto * a = dyn_cast < Instruction > ( after -> getOperand ( op ) ) ) {


return ( __m128i ) __builtin_ia32_pmovusqb512_mask ( ( __v8di ) __A , ( __v16qi ) _mm_setzero_si128 ( ) , __M ) ;


return __builtin_shuffle ( a , ( uint16x4_t ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> static bool arm_memory_load_p ( rtx insn ) { rtx body , lhs , rhs ; ; if ( insn == NULL_RTX || GET_CODE ( insn ) != INSN ) return false ;


<s> return MemoryLocation :: getOrNone ( & I ) ; } ; const BasicBlock & Block = * In . getParent ( ) ; assert ( Block . begin ( ) == To || Block . end ( ) == To || To -> getParent ( ) == & Block ) ; if ( isa < PHINode > ( In ) || ( To != Block . end ( ) && isa < PHINode > ( * To ) ) ) return false ; if ( ! mayBeMemoryDependent ( In ) ) return true ; bool MayWrite = In . mayWriteToMemory ( ) ; auto MaybeLoc = getLocOrNone ( In ) ; auto From = In . getIterator ( ) ; if ( From == To ) return true ; bool MoveUp = ( To != Block . end ( ) && To -> comesBefore ( & In ) ) ; auto Range = MoveUp ? std :: make_pair ( To , From ) : std :: make_pair ( std :: next ( From ) , To ) ; for ( auto It = Range . first ; It != Range . second ; ++ It ) { const Instruction & I = * It ; if ( llvm :: is_contained ( Ignore , & I ) ) continue ; if ( auto * II = dyn_cast < IntrinsicInst > ( & I ) ) { if ( II -> getIntrinsicID ( ) == <STR_LIT> ) continue ; } if ( I . mayThrow ( ) ) return false ; if ( auto * CB = dyn_cast < CallBase > ( & I ) ) { if ( ! CB -> hasFnAttr ( Attribute :: WillReturn ) ) return false ; if ( ! CB -> hasFnAttr ( Attribute :: NoSync ) ) return false ; } if ( I . mayReadOrWriteMemory ( ) ) { auto MaybeLocI = getLocOrNone ( I ) ; if ( MayWrite || I . mayWriteToMemory ( ) ) { if ( ! MaybeLoc || ! MaybeLocI ) return false ; if ( ! AA . isNoAlias ( * MaybeLoc , * MaybeLocI ) ) return false ; }


<s> return create<ISA_LIT>WinCOFFStreamer ( Ctx , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) , RelaxAll , IncrementalLinkerCompatible ) ;


<s> func_fma_steering * fma_forest :: get_globals ( ) {


<s> static rtx_insn * frame_move_insn ( rtx to , rtx from ) { return frame_insn ( gen_rtx_SET ( to , from ) ) ;


<s> if ( i != <NUM_LIT> ) O << <STR_LIT> ; if ( MI -> getOperand ( i ) . isReg ( ) ) printRegName ( O , MI -> getOperand ( i ) . getReg ( ) ) ; else printUImm < <NUM_LIT> > ( MI , i , O ) ; }


<s> int64_t ByteOffset = C -> getSExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( ByteOffset ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sub = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; if ( isDSOffsetLegal ( Sub , ByteOffset , <NUM_LIT> ) ) { unsigned SubOp = Subtarget -> hasAddNoCarry ( ) ? <STR_LIT> : <STR_LIT> ; MachineSDNode * MachineSub = CurDAG -> getMachineNode ( SubOp , DL , <STR_LIT> , Zero , Addr . getOperand ( <NUM_LIT> ) ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( ByteOffset , DL , <STR_LIT> ) ; return true ; } } } } else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { SDLoc DL ( Addr ) ; if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; Base = SDValue ( MovZero , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ; }


<s> case - <NUM_LIT> : if ( TARGET_H8300H || TARGET_H8300S ) * total = <NUM_LIT> + ( outer_code == SET ) ; else * total = <NUM_LIT> ; return true ; } } * total = <NUM_LIT> ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : if ( TARGET_H8300SX ) { * total = <NUM_LIT> ; return true ; } * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : * total = <NUM_LIT> ; return true ; case AND : if ( ! h8300_dst_operand ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) || ! h8300_src_operand ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) ) return false ; * total = COSTS_N_INSNS ( h8300_and_costs ( x ) ) ; return true ; case MOD : case DIV : case UMOD : case UDIV : if ( TARGET_H8300SX ) switch ( GET_MODE ( x ) ) { case QImode : case HImode : * total = COSTS_N_INSNS ( optimize_size ? <NUM_LIT> : <NUM_LIT> ) ; return false ; case SImode : * total = COSTS_N_INSNS ( optimize_size ? <NUM_LIT> : <NUM_LIT> ) ; return false ; default : break ; } * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : if ( TARGET_H8300SX ) switch ( GET_MODE ( x ) ) { case QImode : case HImode : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; case SImode : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; default : break ; } * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( h8sx_binary_shift_operator ( x , VOIDmode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } else if ( h8sx_unary_shift_operator ( x , VOIDmode ) ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } * total = COSTS_N_INSNS ( h8300_shift_costs ( x ) ) ; return true ; case ROTATE : case ROTATERT : if ( GET_MODE ( x ) == HImode ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ;


<s> void addAlignedMemory64or128Operands ( MCInst & Inst , unsigned N ) const { addAlignedMemoryOperands ( Inst , N ) ;


<s> for ( i = <NUM_LIT> ; i < XVECLEN ( parallel , <NUM_LIT> ) ; ++ i ) { const_rtx x ; x = XEXP ( XVECEXP ( parallel , <NUM_LIT> , i ) , <NUM_LIT> ) ;

if ( REG_P ( x ) && REGNO ( x ) == regno ) return true ;


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM , OL ) ;


<s> for ( auto VT : llvm :: reverse ( Sig . Params ) ) if ( popType ( ErrorLoc , VT ) ) return true ; Stack . insert ( Stack . end ( ) , Sig . Returns . begin ( ) , Sig . Returns . end ( ) ) ;


<s> bool <ISA_LIT>TTIImpl :: isLegalBroadcastLoad ( Type * ElementTy , ElementCount NumElements ) const {

return ST -> hasSSE3 ( ) && ! NumElements . isScalable ( ) && NumElements . getFixedValue ( ) == <NUM_LIT> && ElementTy == Type :: getDoubleTy ( ElementTy -> getContext ( ) ) ;


<s> { if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == NOT && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == NOT ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } return false ; } case MULT : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case SIGN_EXTEND : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case ZERO_EXTEND : { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case ZERO_EXTRACT : if ( TARGET_HAS_BMX ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; }


<s> auto DL = it == MBB . end ( ) ? DebugLoc { } : it -> getDebugLoc ( ) ; it = std :: prev ( it , MFI . getCalleeSavedInfo ( ) . size ( ) ) ;

if ( hasFP ( MF ) ) BuildMI ( MBB , it , DL , TTI . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> j ++ ) { if ( j -> isCall ( ) ) { MachineBasicBlock :: iterator p ( llvm :: next ( j ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ControlFlowFinalizer ( ) {

return new <ISA_LIT>ControlFlowFinalizer ( ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ; initializeNVVMReflectPass ( * PassRegistry :: getPassRegistry ( ) ) ;

initializeGenericToNVVMPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> PostGenericScheduler :: initialize ( Dag ) ;


<s> if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) { CC = <STR_LIT> ( CC , true ) ; std :: swap ( TrueVal , FalseVal ) ; } } SDValue <ISA_LIT>cc ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; return getCMOV ( dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp , DAG ) ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ! isFloatingPointZero ( RHS ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swpCmpOps = false ; bool swpVselOps = false ; checkVSELConstraints ( CC , CondCode , swpCmpOps , swpVselOps ) ; if ( CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> || CondCode == <STR_LIT> ) {

if ( swpCmpOps ) std :: swap ( LHS , RHS ) ;


<s> Msg . Loc = getLoc ( ) ; if ( isToken ( AsmToken :: Identifier ) && ( Msg . Id = getMsgId ( getTokenStr ( ) ) ) >= <NUM_LIT> ) { Msg . IsSymbolic = true ; lex ( ) ; } else if ( ! parseExpr ( Msg . Id , <STR_LIT> ) ) { return false ; } if ( trySkipToken ( AsmToken :: Comma ) ) { Op . IsDefined = true ; Op . Loc = getLoc ( ) ;

if ( isToken ( AsmToken :: Identifier ) && ( Op . Id = getMsgOpId ( Msg . Id , getTokenStr ( ) ) ) >= <NUM_LIT> ) {


<s> return ( int32x2_t ) __builtin_aarch64_shsubv2si ( __a , __b ) ;


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI -> getFrameRegister ( ) , VT ) ;


<s> MCStreamer * create<ISA_LIT>ELFStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > && MAB , std :: unique_ptr < MCObjectWriter > && MOW , std :: unique_ptr < MCCodeEmitter > && MCE , bool RelaxAll ) {

return create<ISA_LIT>ELFStreamer ( Context , std :: move ( MAB ) , std :: move ( MOW ) , std :: move ( MCE ) , RelaxAll ) ;