This buffering means that the fetch and decode stages can be more detached from the execution units than is feasible in a more traditional microcoded (or hard-wired) design. As this allows a degree of freedom regarding execution order, it makes some extraction of instruction-level parallelism out of a normal single-threaded program possible (provided that dependencies are checked, etc.).
This buffering facilitates a higher degree of separation between the fetch and decode stages and the execution units in comparison to conventional microcoded (or hard-wired) architectures. It enables some extraction of instruction-level parallelism from typical single-threaded programs, contingent upon dependency verification.