MS Hrishikesh, The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays // ACM SIGARCH Computer Architecture News.
In the article "The Optimal Logic Depth Per Pipeline Stage" by MS Hrishikesh, it was determined that the optimal logic depth for each pipeline stage should be between 6 and 8 FO4 inverter delays. This information is from the ACM SIGARCH Computer Architecture News.