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# From PID to ADRC and back: expressing error-based active disturbance
rejection control schemes as standard industrial 1DOF and 2DOF controllers

Momir Stankovic1, He Ting2, Rafal Madonski
1Military Academy, University of Defence, Belgrade, Serbia
2Energy and Electricity Research Center, Jinan University, Zhuhai, China
∗E-mails<EMAIL_ADDRESS><EMAIL_ADDRESS>

###### Abstract

In this paper, we uncover a new connection between standard PI/PID controllers
and active disturbance rejection control (ADRC), from which we establish
formal conditions of equivalence between the two control schemes. Using the
equivalence, we devise a step-by-step procedure of transitioning from PI/PID
to error-based ADRC. We also show how to go from 1DOF to 2DOF ADRC while
retaining a standard 2DOF PI/PID structure. Both procedures facilitate
expressing error-based ADRC schemes as standard industrial 1DOF and 2DOF
controllers. This allows the designed controller to have the desired
characteristic of ADRC (i.e. strong robustness against internal and external
uncertainties) while still being expressed in a form that is familiar to
industrial practitioners, where PI/PID structures are still the workhorse of
modern control systems. The results of the paper ensure backward compatibility
of future ADRC-based solutions and foster the adoption of active disturbance
rejection-based methods in industrial practice as a viable alternative to
standard controllers. To further support the findings, a set of tests is
conducted in time and frequency domain, followed by a comparative analysis in
FPGA-in-the-loop simulation utilizing a realistic plant model.

Keywords— active disturbance rejection control (ADRC), PI/PID controller,
1DOF/2DOF control structure, equivalence conditions, FPGA-in-the-loop
simulation

1DOF | one degree-of-freedom
---|---
2DOF | two degrees-of-freedom
ADRC | active disturbance rejection control
eADRC | error-based ADRC
ESO | extended state observer
EQ | equivalence
FB | feedback
FPGA | field programmable gate arrays
FIL | FPGA-in-the-loop
HDL | hardware description language
PI | proportional integral
PID | proportional integral derivative
PF | pre-filter
TF | transfer function

$C_{\textrm{EQ}n}$ |  equivalence transfer function for $n\in\left\\{1,2\right\\}$
---|---
$C_{\mathrm{FB}}^{\mathrm{PI}}$ |  feedback transfer function of PI controller
$C_{\mathrm{FB}}^{\mathrm{PID}}$ |  feedback transfer function of PID controller
$C_{\mathrm{FB}}^{\mathrm{A}}$ |  feedback transfer function of eADRC
$C_{\mathrm{FB}}^{\mathrm{A}n}$ |  feedback transfer function for $n\in\left\\{1,2\right\\}$
$C_{\mathrm{PF}}^{\mathrm{PI}}$ |  prefilter transfer function of the PI controller
$C_{\mathrm{PF}}^{\mathrm{PID}}$ |  prefilter transfer function of the PID controller
$C_{\mathrm{PF}}^{\mathrm{A}n}$ |  prefilter transfer function for $n\in\left\\{1,2\right\\}$
$G_{\textrm{P}n}$ |  plant transfer function for $n\in\left\\{1,2\right\\}$
$G_{\textrm{YD}}$ |  transfer function of the disturbance-to-output channel
$G_{\textrm{UN}}$ |  transfer function of the noise-to-control channel
$G_{\textrm{ER}}$ |  transfer function of the reference-to-error channel
$n$ |  system relative order

##  1 Introduction

###  1.1 Background and motivation

There are multiple reasons why so many advanced control algorithms were not
successfully transitioned from academia to industry. This issue is very
complex and part of a larger discussion on bridging the theory vs. practice
gap [1], hence it goes beyond the scope of this work. Here, however, we focus
on one specific reason, which is the simplicity and intuitiveness of PID’s
structure. This reason is often attributed as being one of the key factors
behind PID dominance in the control area and, at the same time, lack thereof
is pointed as the disqualifying drawback of many advanced controllers.

It should be highlighted at this point that it is not our intention to shock
the field control engineer, make him/her leave the comfort zone of PID
control, and force to absorb an entirely new control concept that one has to
learn how to implement and tune. In this work, instead of going against the
current and trying to overcome the popularity, availability, and overall
prevalence of PID (which might be a futile endeavor), we choose a different
path. We take an advanced control solution and devise a full methodology of
transitioning that controller from its original form into a PI/PID-like form
while retaining its ’advanced’ capabilities. We want to address the drawbacks
of standard PI/PID controllers (e.g. limited robustness) by injecting new
features while retaining (as close as possible) the style of PID’s structure
and parameters. The justification for this is simple. Through the process of
’hiding advanced controller in PID clothes’, we want to improve control
performance while keeping the functional simplicity of PI/PID, which will
allow engineers to operate such advanced PID-like controller in a simple,
straightforward, and familiar manner. In short, we want to put a powerful
control algorithm in the hands of floor engineers, and, by mimicking PI/PID,
allow them to straightforwardly set up, commission, and tune the controller,
all in a short time and without knowledge of the advanced control algorithm.

For the purpose of this work, we select active disturbance rejection control
(ADRC) as the example of an advanced controller, for which we will devise,
design, and deploy a transition of its structure to a PI/PID form. What is the
justification behind selecting ADRC? It is a powerful, highly practical,
general-purpose control methodology [2, 3], which can be applied in a variety
of ways, depending on control requirements, availability of certain signals,
computational capabilities of the target hardware, etc. Since its inception,
ADRC has attracted widespread attention among both scholars and practitioners.
Starting with its nonlinear version in [2], which was later streamlined by its
simplified linear form [4], it has found its way into many application
domains. The core principle in ADRC is disturbance rejection, namely
estimating and canceling total disturbance in real-time. As pointed out in
[5], ADRC is the strongest contender to overcome the theory vs. practice gap.
The “paradigm shift” in ADRC, mentioned in [6], is enabled by a combination of
modern control elements with pragmatic, minimal plant modeling, and control
loop tuning efforts. Furthermore, it can also be easily equipped with control
features that can be useful in engineering practice [7]. Finally, the ADRC
methodology is now well-grounded and explained in several languages:
differential equation [8, 9], transfer function [5, 10], and state space [11].
Recent surveys on ADRC [12] document its development over the years and share
successful applications.

The titular expression “From PID to ADRC” is a callback to the seminal work
[2], where the concept of ADRC was first introduced to a larger, English-
speaking audience111Some earlier works on ADRC were mostly in Chinese.. This
expression nicely captures the path of early ADRC development, which was
mostly focused on trying to position ADRC as an enticing alternative to PID
through various analyses, case studies, and even head-to-head comparisons of
field data (some overview papers can be found in [13, 12]). Please notice that
the above-mentioned phrase from [2] is, however, deliberately modified in this
article and reads “From PID to ADRC and back”. As it recently turned out, ADRC
has more in common with standard controllers than initially thought [14, 15].
It seems that the current development of ADRC has shifted and now goes towards
finding connections with classical controllers rather than distancing from
them and claiming superiority. Therefore, motivated by the need to support the
adoption of ADRC in industrial practice and to ensure backward compatibility
of its future applications, we explore those connections in this paper.

###  1.2 Scope, contribution, and structure

The conversion between PID and ADRC has been receiving a lot of attention from
the control community lately. The significance of qualitative comparison of
PID and ADRC, even though studied to date mostly in the academic sphere, can
soon have major practical implications. Even though PID is still the
practitioners’ usual first choice for designing feedback loops, ADRC continues
to emerge as an attractive competitor [16]. It is thus needed to deeply
discuss this subject by looking at the currently available body of work and
emphasizing its missing points. There are of course several challenges when
analyzing the connection between PID and ADRC. One of them is the underlying
control philosophy, which is different for PID (passive, error-centric
control) and ADRC (active, disturbance-centric control). Another is the tuning
methodology, which has to be somehow reconciled as the number of design
parameters for the nominal versions of PID and ADRC is different.

Investigating the relation between ADRC and conventional controllers is not a
new topic in the scientific literature. There exists a body of work that
looked for parameter formulas connecting ADRC with PI/PID [17, 16, 18, 19, 20,
21, 22, 23], tried to derive ADRC tuning rules from the PID parameters [24,
25, 26, 27, 28], or attempted to interpret classic controllers as disturbance
observer-based structures [29, 30]. In this work, however, the scope is
focused on a specific version of ADRC, the so-called error-based ADRC (eADRC),
which has not been previously considered in terms of its equivalence with
PI/PID schemes. Similarly to the most popular output-based ADRC [4], the eADRC
also utilizes a linear observer and a linear state feedback controller,
however, its main input signal is not the system output but the feedback
error. The reasoning behind the specific selection of eADRC is that it is
easily understandable by control practitioners since its structure allows
immediate comparability with existing classical control solutions, including
PI/PID, which are also error-based (in most instances). More detailed
information about the eADRC can be found in [31, 32, 33, 34] with some
successful applications shown in [35, 36, 37, 38].

Therefore, this paper focuses on formally expressing eADRC as a standard
industrial PI/PID controller. Such an equivalence and the procedures
associated with it are verified whether they also hold in experimental
scenarios, here realized in a hardware setup with a field programmable gate
arrays (FPGA) platform. The contributions of this paper are thus as follows.

  * •

Establishing formal conditions of equivalence between the class of PI/PID
controllers and the eADRC scheme.

  * •

Derivation of a step-by-step procedure of transitioning from PI/PID to eADRC.

  * •

Derivation of a step-by-step procedure of transitioning from one degree-of-
freedom (1DOF) to two degrees-of-freedom (2DOF) eADRC while retaining a
standard 2DOF PI/PID structure.

  * •

Reduction of the gap between control system designers and the capabilities of
the FPGA hardware by introducing a relatively simple methodology for control
algorithm implementation, prototyping, and validation.

The newly unraveled connection between standard PI/PID controllers and the two
formal procedures facilitates expressing eADRC schemes as standard industrial
1DOF and 2DOF controllers. This allows the designed controller to have the
desired characteristic of ADRC (i.e. strong robustness against internal and
external uncertainties) while being expressed in a form that is familiar to
industrial practitioners, where PI/PID structures are still dominant. The
results of the paper ensure backward compatibility of future ADRC-based
solutions and foster the adoption of active disturbance rejection-based
methods in industrial practice as a viable alternative to standard
controllers. To the best of our knowledge, such results were not presented in
the literature before and contribute to the current body of knowledge.

##  2 Prerequisites: considered control methods

Before we introduce the control techniques considered in this work, let us
first define the class of systems that these techniques have to govern. Here
we considered the problem of controlling $n$-th order single-input single-
output systems that can be expressed as:

$y^{(n)}=\sum_{i=0}^{n-1}a_{i}\cdot y^{(i)}+b\cdot u(t)+d(t),$ (1)

where $u(t)$ is the control signal, $y(t)$ is the system output, $b$ is the
system uncertain input gain, $d(t)$ is the external disturbance, and $a_{i}$,
for $i=0,1,\ldots,n-1$, are the system uncertain internal parameters. Here we
primarily focus on first- and second-order systems, i.e.
$n\in\left\\{1,2\right\\}$, as they are most commonly considered in
engineering practice.

The considered control objective here is to manipulate the control signal
$u(t)$ in a way that the system output $y(t)$ tracks a reference signal $r(t)$
despite the presence of unmodeled external disturbance $d(t)$ and
uncertainties related to the system parameters ($a_{i}$ and $b$).

######  Remark 1.

We have started with the expression in continuous time domain but throughout
the article $s$-domain will also be used as it offers controller
representation in a compact and easy to implement way. It also aids the
frequency domain analysis (to be shown in Section 4). We assume, without loss
of generality, that the initial values that appear when making Laplace
transformation are equal to zero.

The design of control structures for (1), based on PI/PID controllers and
eADRC controller, will be recalled in the next subsections Section 2.1 and
Section 2.2, respectively. One will notice that we consider both 1DOF and 2DOF
structures. It should be thus reminded that a degree-of-freedom of a control
system is defined as the number of closed-loop transfer functions that can be
adjusted independently [39]. The design of control systems is a multi-
objective problem, hence a 2DOF control system, although more complex,
naturally has advantages over a 1DOF control system [40].

###  2.1 PI/PID controllers

####  2.1.1 2DOF PID

The 2DOF PID controller for the considered plant model (1) can be formulated
as [39, 40]:

$\displaystyle u_{\mathrm{PID}}(t)$
$\displaystyle=K_{\mathrm{P}}\cdot\left[\beta\cdot r(t)-y(t)\right]$
$\displaystyle+K_{\mathrm{I}}\int_{0}^{t}\left[r(\tau)-y(\tau)\right]d\tau$
$\displaystyle+K_{\mathrm{D}}\left(-\frac{dy(t)}{dt}\right),$ (2)

with design parameters $K_{\mathrm{P}}$, $K_{\mathrm{I}}$, $K_{\mathrm{D}}$,
and $\beta$.

In industrial applications, it is often beneficial to introduce low-pass
filters in the reference and output channels to improve system’s step response
and reduce its noise sensitivity. Hence, the Laplace transform of (2),
including reference signal filtered by $F_{\mathrm{R}}(s)$ and system output
filtered by $F_{\mathrm{Y}}(s)$, can take the form222Throughout the paper, to
simplify the analysis and to focus on the behavior of the system in the
steady-state, we assume that the initial values that appear when making
Laplace transformation are equal to zero.:

$\displaystyle u_{\mathrm{PID}}(s)$
$\displaystyle=K_{\mathrm{P}}\cdot\left[\beta\cdot r(s)\cdot
F_{\mathrm{R}}(s)-y(s)\cdot F_{\mathrm{Y}}(s)\right]$
$\displaystyle+\frac{K_{\mathrm{I}}}{s}\cdot\left[r(s)\cdot
F_{\mathrm{R}}(s)-y(s)\cdot F_{\mathrm{Y}}(s)\right]$ $\displaystyle+s\cdot
K_{\mathrm{D}}\cdot\left[-y(s)\cdot F_{\mathrm{Y}}(s)\right].$ (3)

The introduced low-pass filters are commonly of first- or second-order, and
their coefficients can be considered as additional tuning parameters.

######  Remark 2.

A common engineering practice is only to filter the derivative term in the
above equation. In this paper, however, we will use the more general PID form
(3). The transition between the two filtered PID structures can easily be done
utilizing the equivalence shown in [41].

The 2DOF PID transfer function representation from (2) can also be expressed
in an alternative, more compact way:

$u_{\mathrm{PID}}(s)=C_{\mathrm{FB}}^{\mathrm{PID}}(s)\cdot\left[r(s)\cdot
C_{\mathrm{PF}}^{\mathrm{PID}}(s)-y(s)\right],$ (4)

with:

$\displaystyle C_{\mathrm{FB}}^{\mathrm{PID}}(s)$
$\displaystyle=\frac{K_{\mathrm{D}}\cdot s^{2}+K_{\mathrm{P}}\cdot
s+K_{\mathrm{I}}}{s}\cdot F_{\mathrm{Y}}(s),$ (5) $\displaystyle
C_{\mathrm{PF}}^{\mathrm{PID}}(s)$
$\displaystyle=\frac{K_{\mathrm{P}}\cdot\beta\cdot
s+K_{\mathrm{I}}}{K_{\mathrm{D}}\cdot s^{2}+K_{\mathrm{P}}\cdot
s+K_{\mathrm{I}}}\cdot\frac{F_{\mathrm{R}}(s)}{F_{\mathrm{Y}}(s)}.$ (6)

representing the feedback (FB) and pre-filter (PF) transfer functions,
respectively.

The 2DOF PID structure enables separate tuning of disturbance rejection and
reference tracking. When the controller is tasked to give a desired
attenuation of disturbances, the disturbance rejection performance can be
tuned using parameters $K_{\mathrm{P}}$, $K_{\mathrm{I}}$, $K_{\mathrm{D}}$,
and filter $F_{\mathrm{Y}}(s)$. Parameters $\beta$ and filter
$F_{\mathrm{R}}(s)$ can be tuned to give an appropriate reference response.

####  2.1.2 1DOF PID

The 1DOF PID structure, which is the most commonly seen variant of the PID
controller, can be obtained from (4) by simply substituting
$C_{\textrm{PF}}^{\textrm{PID}}(s)=1$, which yields:

$u_{\mathrm{PID}}(s)=C_{\mathrm{FB}}^{\mathrm{PID}}(s)\cdot\overbrace{\left[r(s)-y(s)\right]}^{e(s)},$
(7)

where $e(s)$ is the tracking error in $s$-domain.

In the case of 1DOF PID controller, contrarily to the commentary under (6),
the reference tracking and disturbance rejection performances cannot be tuned
separately using parameters $K_{\mathrm{P}}$, $K_{\mathrm{D}}$,
$K_{\mathrm{I}}$, and $F_{\mathrm{Y}}(s)$.

####  2.1.3 2DOF and 1DOF PI

Typically, in the case of first-order systems (i.e. $n=1$), 2DOF PI control
structure is utilized, which can be considered as a special case of the 2DOF
PID controller but with $K_{\mathrm{D}}=0$ and $F_{\mathrm{Y}}(s)=1$, which
gives:

$u_{\mathrm{PI}}(s)=C_{\mathrm{FB}}^{\mathrm{PI}}(s)\cdot\left[r(s)\cdot
C_{\mathrm{PF}}^{\mathrm{PI}}(s)-y(s)\right],$ (8)

with its pre-filter and feedback transfer functions:

$\displaystyle C_{\mathrm{FB}}^{\mathrm{PI}}(s)$
$\displaystyle=\frac{K_{\mathrm{P}}\cdot s+K_{\mathrm{I}}}{s},$ (9)
$\displaystyle C_{\mathrm{PF}}^{\mathrm{PI}}(s)$
$\displaystyle=\frac{K_{\mathrm{P}}\cdot\beta\cdot
s+K_{\mathrm{I}}}{K_{\mathrm{P}}\cdot s+K_{\mathrm{I}}}\cdot
F_{\mathrm{R}}(s).$ (10)

The 1DOF variant of the 2DOF PI controller can be directly obtained from (8)
assuming $G_{\textrm{PF}}^{\textrm{PI}}(s)=1$, which gives:

$u_{\mathrm{PI}}(s)=C_{\mathrm{FB}}^{\mathrm{PI}}(s)\cdot\overbrace{\left[r(s)-y(s)\right]}^{e(s)}.$
(11)

###  2.2 Error-based ADRC (eADRC)

The error-based ADRC (eADRC) is briefly recalled here with its key design
points. For a more detailed derivation, the reader is referred to [33].

By incorporating the system dynamics (1) into the definition of the tracking
error $e(t)\triangleq r(t)-y(t)$, one can express the controlled system using
its feedback error dynamics:

$e^{(n)}=f_{\textrm{e}}(t)+b_{0}\cdot u(t),$ (12)

where:

$f_{\textrm{e}}(t)=r^{(n)}-\sum_{i=0}^{n-1}a_{i}\cdot
r^{(i)}+\sum_{i=0}^{n-1}a_{i}\cdot e^{(i)}+\Delta{b}\cdot u(t)+d(t),$

is the system’s resultant generalized (total) disturbance and $\Delta{b}$
represents the uncertainty of the input gain.

In the eADRC methodology, the control law for the above system is usually
defined as:

$u(t)=\frac{1}{b_{0}}\cdot\left[\begin{pmatrix}\bm{k}^{\mathrm{T}}&1\end{pmatrix}\cdot\bm{\hat{x}_{\textrm{e}}}\right],$
(13)

where:

$\displaystyle\bm{k}^{\mathrm{T}}$
$\displaystyle=\begin{pmatrix}k_{1}&\cdots&k_{n}\end{pmatrix},$
$\displaystyle\bm{\hat{x}_{\textrm{e}}}$
$\displaystyle=\begin{pmatrix}\hat{x}_{e1}(t)&\cdots&\hat{x}_{en}(t)&\hat{x}_{e(n+1)}(t)\end{pmatrix}^{\mathrm{T}}$
$\displaystyle=\begin{pmatrix}\hat{e}(t)&\cdots&\hat{e}^{(n-1)}&\hat{f_{e}}(t)\end{pmatrix}^{\mathrm{T}},$

are the controller gains vector (to be tuned) and state estimation vector,
respectively. The latter term can be obtained using an extended state observer
(ESO):

$\bm{\dot{\hat{x}}_{\textrm{e}}}=\bm{A}\cdot\bm{\hat{x}_{\textrm{e}}}(t)-\bm{b}\cdot
u(t)+\bm{l}\cdot\left[e(t)-\bm{c}^{\mathrm{T}}\cdot\bm{\hat{x}_{\textrm{e}}}(t)\right],$
(14)

for $\bm{A}=\begin{pmatrix}\bm{0}^{n\times 1}&\bm{I}^{n\times n}\\\
0&\bm{0}^{1\times n}\end{pmatrix},\bm{b}=\begin{pmatrix}\bm{0}^{(n-1)\times
1}\\\ b_{0}\\\ 0\end{pmatrix},\bm{c}=\begin{pmatrix}1\\\ \bm{0}^{1\times
n}\end{pmatrix}$,
and $\bm{l}=\begin{pmatrix}l_{1}&\cdots&l_{n+1}\end{pmatrix}^{\mathrm{T}}$ is
the observer gains vector (to be tuned).

To represent the above control observer-based structure in a transfer function
form, the Laplace transform of (13) is substituted into (14), which gives:

$\bm{\hat{x}}(s)=\left(s\cdot\bm{I}-\bm{A}_{\mathrm{CL}}\right)^{-1}\cdot\bm{l}\cdot
e(s),$ (15)

where
$\bm{A}_{\mathrm{CL}}=\bm{A}-\bm{l}\cdot\bm{c}^{\mathrm{T}}+\frac{1}{b_{0}}\cdot\bm{b}\cdot\begin{pmatrix}\bm{k}^{\mathrm{T}}&1\end{pmatrix}$.

By substituting (15) in the Laplace transform of (14), and eliminating
$\hat{e}(s)$, one arrives at:

$\displaystyle
u(s)=\frac{1}{b_{0}}\cdot\begin{pmatrix}\bm{k}^{\mathrm{T}}&1\end{pmatrix}\left(s\cdot\bm{I}-\bm{A}_{\mathrm{CL}}\right)^{-1}\cdot\bm{l}\cdot
e(s),$ (16)

which can be rewritten as 1DOF control structure:

$u(s)=C_{\mathrm{FB}}^{\mathrm{A}}(s)\cdot e(s).$ (17)

The feedback transfer function $C_{\mathrm{FB}}^{\mathrm{A}}$ is of a general
form :

$C_{\mathrm{FB}}^{\mathrm{A}}(s)=\frac{1}{b_{0}}\cdot\begin{pmatrix}\bm{k}^{\mathrm{T}}&1\end{pmatrix}\frac{\operatorname{adj}\left(s\cdot\bm{I}-\bm{A}_{\mathrm{CL}}\right)}{\operatorname{det}\left(s\cdot\bm{I}-\bm{A}_{\mathrm{CL}}\right)}\cdot\bm{l}.$
(18)

For first- ($n=1$) and second-order ($n=2$) plant models it respectively takes
the forms:

$C_{\mathrm{FB}}^{\mathrm{A1}}(s)=\frac{1}{b_{0}}\cdot\frac{(k_{1}l_{1}+l_{2})\cdot
s+k_{1}l_{2}}{s^{2}+(k_{1}+l_{2})\cdot s},$ (19)
$C_{\mathrm{FB}}^{\mathrm{A2}}(s)=\frac{1}{b_{0}}\cdot\frac{(k_{1}l_{1}+k_{2}l_{2}+l_{3})\cdot
s^{2}+(k_{1}l_{2}+k_{2}l_{3})\cdot s+k_{1}l_{3}}{s^{3}+(k_{2}+l_{1})\cdot
s^{2}+(l_{2}+k_{1}+l_{1}k_{2})\cdot s}.$ (20)

From the above derivations, one can notice that this eADRC has 1DOF control
structure that only contains the feedback transfer function (similarly to 1DOF
PI and 1DOF PID in (11) and (7), respectively). In [31], we have formally
shown that the eADRC does not have an imposed pre-filter transfer function in
the reference channel (as opposed to the classic output-based ADRC [4]). This
has certain benefits, for example, it allows the control designer to freely
choose if one wants to use a pre-filter and, if yes, what kind of pre-filter.

##  3 Main result: establishing conditions of equivalence

In this section, we uncover a new connection between standard PI/PID
controllers and eADRC. By establishing formal conditions of equivalence
between the two control schemes, we devise a step-by-step procedure of
transitioning from PI/PID to error-based ADRC (Section 3.1). We also show how
to go from 1DOF to 2DOF ADRC while retaining a standard 2DOF PI/PID structure
(Section 3.2). Both procedures facilitate expressing error-based ADRC schemes
as standard industrial 1DOF and 2DOF controllers. The results of this section
are collectively visualized in Figure 1.

###  3.1 Transition from PI/PID to eADRC structure

In this section, we want to find out if the eADRC transfer functions for
first-order ($n=1$) and second-order ($n=2$) systems can be represented as PI
and PID transfer functions, respectively, multiplied by an equivalence
transfer function.

We start with first-order case ($n=1$) and write:

$C_{\mathrm{FB}}^{\mathrm{A1}}(s)=C_{\mathrm{FB}}^{\mathrm{PI}}(s)\cdot
C_{\mathrm{EQ1}}(s),$ (21)

where $C_{\mathrm{EQ1}}(s)$ is the equivalence transfer function (to be
found). After a visual comparison of PI and eADRC structures in Section 2, one
can deduce that the equivalence transfer function in this case has to be:

$C_{\mathrm{EQ1}}(s)=\frac{1}{\frac{1}{l_{2}+k_{1}}\cdot s+1},$ (22)

with the PI controller parameters set as:

$K_{\mathrm{P}}=\frac{k_{1}l_{1}+l_{2}}{b_{0}(l_{2}+k_{1})},\quad
K_{\mathrm{I}}=\frac{k_{1}l_{2}}{b_{0}(l_{2}+k_{1})}.$ (23)

In similar manner, we write down the case of second-order plant ($n=2$):

$C_{\mathrm{FB}}^{\mathrm{A2}}(s)=C_{\mathrm{FB}}^{\mathrm{PID}}(s)\cdot
C_{\mathrm{EQ2}}(s),$ (24)

and deduce that the equivalence transfer function $C_{\mathrm{EQ2}}(s)$ in
this case has to take the form:

$C_{\mathrm{EQ2}}(s)=\frac{1}{\frac{1}{(k_{2}l_{1}+l_{2}+k_{1})}\cdot
s^{2}+\frac{k_{2}+l_{1}}{(k_{2}l_{1}+l_{2}+k_{1})}\cdot
s+1}\cdot\frac{1}{F_{\mathrm{Y}}(s)},$ (25)

with PID controller gains set as:

$\displaystyle K_{\mathrm{P}}$
$\displaystyle=\frac{k_{1}l_{1}+k_{2}l_{3}}{b_{0}(k_{2}l_{1}+l_{2}+k_{1})},$
$\displaystyle K_{\mathrm{I}}$
$\displaystyle=\frac{k_{1}l_{3}}{b_{0}(k_{2}l_{1}+l_{2}+k_{1})},$ (26)
$\displaystyle K_{\mathrm{D}}$
$\displaystyle=\frac{k_{1}l_{1}+k_{2}l_{2}+l_{3}}{b_{0}(k_{2}l_{1}+l_{2}+k_{1})}.$

The above procedures enable a relatively simple transition from existing
PI/PID controller to eADRC control structure by adding the appropriate
equivalence transfer function $C_{\mathrm{EQ}}(s)$ in serial with existing
PI/PID controller.

###  3.2 Transition from standard 1DOF eADRC controller to strict 2DOF eADRC
controller

There are two conclusions one can draw when comparing the classic, output-
based ADRC (as defined in [4]) with the error-based ADRC (as defined in [31]):

  * •

Output-based ADRC, as seen in [4], is not a strict 2DOF333The term strict 2DOF
refers to a controller structure consisting of two closed-loop transfer
functions that can be adjusted independently. control structure, which means
that although one can identify two transfer functions in the control system
scheme, these transfer functions cannot be independently tuned (i.e. tuning of
tracking performance and disturbance rejection is intertwined), which is not
in line with the definition of the degree-of-freedom given in [39].

  * •

Error-based ADRC is a 1DOF control structure as only one transfer function
(related to feedback) can be identified in the control system scheme. There is
no transfer function in the reference channel.

Therefore, in this section, we want derive a procedure that will show how to
transition from standard 1DOF eADRC controller to a 2DOF eADRC controller
(with a strict 2DOF structure). In other words, the idea is to propose 2DOF
eADRC structure as a more general controller than 1DOF eADRC, which allows to
obtain the advantages of a 2DOF structure related to the ability to
independently tune of the set-point response and disturbance rejection
performance.

Analyzing the structure of eADRC feedback transfer function for first-order
plant (19), one can notice that it can be alternatively represented as a
following PI controller feedback transfer function
$C_{\mathrm{FB}}^{\textrm{PI}}(s)$ with its output additionally filtered with
a first-order low-pass filter $F_{\mathrm{Y1}}(s)$:

$C_{\mathrm{FB}}^{\mathrm{A1}}(s)=\frac{K_{\mathrm{P}}s+K_{\mathrm{I}}}{s}\cdot
F_{\mathrm{Y1}}(s),$ (27)

where $K_{\mathrm{P}}$, $K_{\mathrm{I}}$ are tuned as in (23) and the filter
has the form $F_{\mathrm{Y1}}(s)\equiv C_{\mathrm{EQ1}}(s)$. Next, based on
the equivalence between eADRC and 2DOF PI structures (already established in
Section 3.1), the appropriate eADRC pre-filter transfer function can be
obtained for the first-order plant model as:

$C_{\mathrm{PF}}^{\mathrm{A1}}(s)=\frac{K_{\mathrm{P}}\beta
s+K_{\mathrm{I}}}{K_{\mathrm{P}}s+K_{\mathrm{I}}}\cdot\frac{F_{\mathrm{R}}(s)}{F_{\mathrm{Y1}}(s)}=C_{\mathrm{PF}}^{\mathrm{PI}}(s)\cdot
C_{\mathrm{EQ1}}^{-1}(s).$ (28)

The two derived transfer functions, related to the pre-filter (28) and the
feedback (27), constitute the desired 2DOF eADRC structure for first-order
systems.

In similar manner, eADRC feedback transfer function for the second-order plant
model can be expressed as:

$C_{\mathrm{FB}}^{\mathrm{A2}}(s)=\frac{K_{\mathrm{D}}s^{2}+K_{\mathrm{P}}s+K_{\mathrm{I}}}{s}\cdot
F_{\mathrm{Y2}}(s),$ (29)

where $K_{\mathrm{P}}$, $K_{\mathrm{I}}$, $K_{\mathrm{D}}$ are tuned as in
(26) and $F_{\mathrm{Y2}}(s)$ is a second-order low-pass filter, defined as:

$F_{\mathrm{Y2}}(s)=\frac{1}{\frac{1}{k_{2}l_{1}+l_{2}+k_{1}}\cdot
s^{2}+\frac{k_{2}+l_{1}}{k_{2}l_{1}+l_{2}+k_{1}}\cdot s+1}.$ (30)

Therefore, based on the structure of 2DOF PID pre-filter (6), the eADRC pre-
filter transfer function can be derived as:

$\displaystyle C_{\mathrm{PF}}^{\mathrm{A2}}(s)$
$\displaystyle=\frac{K_{\mathrm{P}}\beta
s+K_{\mathrm{I}}}{K_{\mathrm{D}}s^{2}+K_{\mathrm{P}}s+K_{\mathrm{I}}}\cdot\frac{F_{\mathrm{R}}(s)}{F_{\mathrm{Y2}}(s)}$
$\displaystyle=C_{\mathrm{PF}}^{\mathrm{PID}}(s)\cdot
C_{\mathrm{EQ2}}^{-1}(s).$ (31)

This, together with (29) constitute the desired 2DOF eADRC structure for
second-order systems.

Finally, after the introduced rearrangements, it should be noticed that now
adjusting filter $F_{\textrm{R}}(s)$ and $\beta$ in (28) and (31) enable
reference response tuning in the proposed 2DOF eADRC controller without
affecting its disturbance rejection performance.

The equivalences between PI/PID and eADRC controllers, obtained in Section
3.1, enable the transition of 1DOF eADRC to 2DOF eADRC structure based on the
2DOF PI/PID structure. The obtained decoupling of tuning of tracking and
disturbance rejection is a highly desirable property in practice, as recently
pointed out in [42, 43]. The graphical representation of the proposed
transitions between PI/PID and eADRC controllers in the 1DOF and 2DOF cases
are shown in Figure 1.

Figure 1: Implementation scheme of PI/PID and eADRC controllers in 1DOF and
2DOF forms. The notation ’1/2’ corresponds to plant relative order
$n=\\{1,2\\}$. A table containing specific equations for all the considered
control schemes can be found in Table 3 in Appendix A1.

##  4 Performance analyses in time and frequency domains

In this section, a comparison between considered PI/PID and eADRC structures
in both 1DOF and 2DOF cases is performed by analyzing system steady-state and
transient performance. The comparison is focused on data-driven analysis of
the controllers’ performance in time and frequency domains, without using
equivalent functions. Detailed mathematical analyses of the considered control
schemes are omitted here as they have already been covered in the literature,
for example in [31, 33].

###  4.1 Testing methodology

For the purpose of the investigation, two generic plant models are introduced,
namely a first-order system model ($n=1$) with time-delay:444Those two
specific plant models were also used [31], where the equivalence between eADRC
and conventional output-based ADRC was discussed. By using the same examples,
one can build on those earlier results, perform comparisons more easily, and
expand the topic of the equivalence of ADRC to other control forms.

$G_{\textrm{P1}}(s)=\frac{1}{s+1}e^{-0.2\textrm{s}},$ (32)

and a normalized second-order system model ($n=2$):

$G_{\textrm{P2}}(s)=\frac{1}{s^{2}+2s+1}.$ (33)

In order to simplify the tuning of eADRC, the so-called ‘bandwidth
parameterization’ is applied. This approach from [4] is the most commonly
utilized tuning technique for ADRC schemes that has been successfully applied
to numerous control scenarios to date [10, 35, 44]. It enables relatively
simple tuning of both controller and observer gains. For the controller, its
gains can be obtained by placing closed-loop controller poles at one common
location $\lambda=-\omega_{\mathrm{CL}}$:

$\displaystyle\left(\lambda+\omega_{\mathrm{CL}}\right)^{n}=\lambda^{n}+k_{n}\lambda^{n-1}+\ldots+k_{2}\lambda+k_{1},$
(34)

and in the same manner, observer gains can be obtained placing observer poles
at location $\lambda=-k_{\mathrm{ESO}}\cdot\omega_{\mathrm{CL}}$:

$\displaystyle\left(\lambda+k_{\mathrm{ESO}}\cdot\omega_{\mathrm{CL}}\right)^{n+1}=\lambda^{n+1}+l_{1}\lambda^{n}+\ldots+l_{n}\lambda+l_{n+1},$
(35)

where $\omega_{\mathrm{CL}}$ is the desired closed-loop system bandwidth and
$k_{\mathrm{ESO}}$ represents the relative factor between the observer and the
control loop bandwidths, both being user-defined design parameters.

To enable a fair comparison between PI/PID and eADRC control schemes, all the
considered controller structures are tuned here to have the same robustness
index $M_{\textrm{s}}$ [45]:

$\displaystyle
M_{\mathrm{s}}=\max_{s>0}\left|\frac{1}{1+G_{\textrm{FB}}(s)G_{\textrm{P}}(s)}\right|.$
(36)

Therefore, for the derived control structures for first-order plant model
(32), $M_{\textrm{s}}=1.55$ is selected by choosing $K_{\textrm{P}}=1$ and
$K_{\textrm{I}}=2.5$ in case of PI, and in case of eADRC
$\omega_{\textrm{CL}}=2.7$rad/s, $K_{\textrm{ESO}}=15$, and, assuming complete
knowledge of the plant input gain, $b_{0}=1$. For the controllers for second-
order plant model (33), $M_{\textrm{s}}=1.45$ is adopted, and it is achieved
by choosing $K_{\textrm{P}}=30$, $K_{\textrm{I}}=27$, $K_{\textrm{D}}=5$,
$F_{\textrm{Y}}(s)=\frac{1}{T_{\textrm{f}}s+1}$ with $T_{\textrm{f}}=0.05$s
(filter coefficient) in case of PID, and in case of eADRC
$\omega_{\textrm{CL}}=4$rad/s, $k_{\textrm{ESO}}=7$, and, assuming complete
knowledge of the plant input gain, also $b_{0}=1$.

It should be noted that the corresponding 1DOF and 2DOF structures have
identical robustness indices $M_{\textrm{s}}$, which means that they have the
same robustness characteristics, regardless of pre-filter
$G_{\textrm{PF}}(s)$, where $C_{\mathrm{PF}}(s)$ is either
$C_{\textrm{PF}}^{\textrm{PI/PID}}(s)$ or $C_{\textrm{PF}}^{\textrm{A}n}(s)$,
depending on the considered plant order ($n\in\left\\{1,2\right\\}$) and the
considered controller type (PI/PID or eADRC). The additional tuning parameters
in the 2DOF structures (included in $G_{\textrm{PF}}(s)$) are set to be the
same for both PI/PID and eADRC controllers. The low-pass reference filter is
fixed as $F_{\textrm{R}}(s)=\frac{1}{0.001s+1}$, and in order to show the
influence of the parameter $\beta$, its two different values are analyzed (for
the first-order plant: $\beta=\left\\{0.7;0.3\right\\}$ and for the second-
order plant: $\beta=\left\\{0.75;0.65\right\\}$).

###  4.2 Steady-state performance analysis

The steady-state performance analyses of disturbance rejection, noise
sensitivity, and reference tracking are conducted in frequency domain, based
on the previously defined transfer function representations of the considered
PI/PID and eADRC structures shown in Figure 1.

The disturbance rejection performance is analyzed based on frequency response
of a following transfer function from disturbance $d(s)$ to output $y(s)$:

$G_{\mathrm{YD}}(s)=\frac{G_{\mathrm{P}n}(s)}{1+C_{\mathrm{FB}}(s)\cdot
G_{\mathrm{P}n}(s)},$ (37)

where the specific form of $G_{\textrm{P}n}(s)$ depends on the considered
plant order ($n\in\left\\{1,2\right\\}$), and $C_{\mathrm{FB}}(s)$ is either
$C_{\textrm{FB}}^{\textrm{PI/PID}}(s)$ or $C_{\textrm{FB}}^{\textrm{A}n}(s)$,
depending on the considered plant order ($n\in\left\\{1,2\right\\}$) and the
considered controller type (PI/PID or eADRC). The obtained disturbance
rejection results are shown in Figure 2, jointly for first- and second-order
plant.

The system noise sensitivity characteristics are obtained based on frequency
response of a following transfer function between measurement noise $n(s)$ (in
the output signal $y(s)$) and control signal $u(s)$:

$G_{\mathrm{UN}}(s)=\frac{-C_{\mathrm{FB}}(s)}{1+C_{\mathrm{FB}}(s)\cdot
G_{\mathrm{P}n}(s)},$ (38)

where the specific form of $G_{\textrm{P}n}(s)$ depends on the considered
plant order ($n\in\left\\{1,2\right\\}$), and $C_{\mathrm{FB}}(s)$ is either
$C_{\textrm{FB}}^{\textrm{PI/PID}}(s)$ or $C_{\textrm{FB}}^{\textrm{A}n}(s)$,
depending on the considered plant order ($n\in\left\\{1,2\right\\}$) and the
considered controller type (PI/PID or eADRC). The obtained noise sensitivity
results are depicted in Figure 3, collectively for first- and second-order
plant.

One can notice that (37) and (38) do not contain pre-filter transfer function
$C_{\textrm{PF}}(s)$, which means that appropriate 1DOF and 2DOF controllers
have the same disturbance rejection capabilities and noise sensitivity in
steady-state, which is additionally confirmed by Figure 2 and Figure 3. On the
other hand, it should be also noted that eADRC controllers enable better
disturbance rejection performances than PI/PID controllers (especially in the
case of second-order plant) and significantly lower level of noise sensitivity
in high frequency range, which is often of interest in the analysis of
influence of the measurement noise on system performance.

In order to compare the performances of steady-state reference tracking,
following transfer functions from reference signal $r(s)$ to tracking error
$e(s)$ are derived, for 1DOF structure as:

$G_{\mathrm{ER}}(s)=1-\frac{C_{\mathrm{FB}}(s)\cdot
G_{\mathrm{P}n}(s)}{1+C_{\mathrm{FB}}(s)\cdot G_{\mathrm{P}n}(s)},$ (39)

and for 2DOF structure as:

$G_{\mathrm{ER}}(s)=1-C_{\mathrm{PF}}(s)\cdot\frac{C_{\mathrm{FB}}(s)\cdot
G_{\mathrm{P}n}(s)}{1+C_{\mathrm{FB}}(s)\cdot G_{\mathrm{P}n}(s)},$ (40)

where the specific form of $G_{\textrm{P}n}(s)$ depends on the considered
plant order ($n\in\left\\{1,2\right\\}$); $C_{\mathrm{FB}}(s)$ is either
$C_{\textrm{FB}}^{\textrm{PI/PID}}(s)$ or $C_{\textrm{FB}}^{\textrm{A}n}(s)$,
depending on the considered plant order ($n\in\left\\{1,2\right\\}$) and the
considered controller type (PI/PID or eADRC); and $C_{\mathrm{PF}}(s)$ is
either $C_{\textrm{PF}}^{\textrm{PI/PID}}(s)$ or
$C_{\textrm{PF}}^{\textrm{A}n}(s)$, depending on the considered plant order
($n\in\left\\{1,2\right\\}$) and the considered controller type (PI/PID or
eADRC).

The frequency responses of $G_{\mathrm{ER}}(s)$ for the considered controllers
are gathered in Figure 4 jointly for first- and second-order plant. It can be
observer that 1DOF structures provide better steady-state reference tracking
performances than the corresponding 2DOF structures, and that decreasing
parameter $\beta$ in 2DOF structure leads to higher reference tracking error
in steady-state. Also, comparing eADRC and PI/PID schemes, it is obvious that
eADRC achieves better performance in both 1DOF and 2DOF cases.

(a) Results for plant model $G_{\textrm{P1}}(s)$. Note: corresponding 1DOF and
2DOF structures have the same transfer function $G_{\mathrm{YD}}(s)$, hence
the frequency responses characteristics overlap.

(b) Results for plant model $G_{\textrm{P2}}(s)$. Note: corresponding 1DOF and
2DOF structures have the same transfer function $G_{\mathrm{YD}}(s)$, hence
the frequency responses characteristics overlap.

Figure 2: Comparative analyses of steady-state disturbance rejection
performances for plant model $G_{\textrm{P1}}(s)$ (a) and $G_{\textrm{P2}}(s)$
(b).

(a) Results for plant model $G_{\textrm{P1}}(s)$ Note: corresponding 1DOF and
2DOF structures have the same transfer function $G_{\mathrm{UN}}(s)$, hence
the frequency responses characteristics overlap.

(b) Results for plant model $G_{\textrm{P2}}(s)$ Note: corresponding 1DOF and
2DOF structures have the same transfer function $G_{\mathrm{UN}}(s)$, hence
the frequency responses characteristics overlap.

Figure 3: Comparative analyses of steady-state measurement noise sensitivity
for plant model $G_{\textrm{P1}}(s)$ (a) and $G_{\textrm{P2}}(s)$ (b).

(a) Results for plant model $G_{\textrm{P1}}(s)$

(b) Results for plant model $G_{\textrm{P2}}(s)$

Figure 4: Comparative analyses of steady-state reference tracking performances
for plant model $G_{\textrm{P1}}(s)$ (a) and $G_{\textrm{P2}}(s)$ (b).

###  4.3 Transient performance analysis

The transient performances of the considered control structures are analyzed
in time-domain using numerical simulations with already established plant
models (32) and (33). Simulations are conducted with a step reference signal
filtered by a low-pass filter $G_{\textrm{f}}(s)=\frac{1}{(0.01s+1)^{2}}$. To
test the robustness of the considered control algorithms against external
disturbance, an unmodeled step disturbance is added from $t\geq 10$s. To test
their noise sensitivity, white noise, with power $P_{\textrm{n}}=1\times
10^{-7}$ and sampling time $T_{\textrm{n}}=0.001$s, is added to the system
output from $t\geq 15$s.

The obtained systems responses and generated corresponding control signals are
presented in Figure 5 for the first-order plant, and in Figure 6 for the
second-order plant. From these figures, it can be noticed that in all the
simulated scenarios, eADRC controllers achieved better reference tracking than
PI/PID controllers, and that 2DOF structures provide responses with lower
overshoots and values of the control signal than 1DOF structures. It can be
also seen that the system response and the associated control signal peak can
be shaped by adjusting parameter $\beta$, where its lower value means lower
overshoot and lower control signal peak. Also, as expected, it is evident that
shaping the reference response does not affect the disturbance rejection
performance and noise sensitivity, which confirms the previously made
conclusion resulting from (37) and (38).

Therefore, it can be concluded that the proposed 2DOF eADRC controller,
derived based on 2DOF PI/PID controller, in comparison with the standard 1DOF
eADRC controller, provides the additional ability to adjust the transient
reference response, while retaining the same noise sensitivity level as well
as disturbance rejection performance in both steady-state and transient
stages.

Figure 5: Comparative analyses of transient performances for plant model
$G_{\textrm{P1}}(s)$: system outputs (left) and control signals (right). Note:
during the disturbance rejection test ($10\textrm{s}\leq t<20\textrm{s}$) and
measurement noise sensitivity test ($15\textrm{s}\leq t\leq 20\textrm{s}$),
the signal plots of the 1DOF and 2DOF structures (in both eADRC and PI cases)
remain the same, hence are indistinguishable in the plots. Figure 6:
Comparative analyses of transient performances for plant model
$G_{\textrm{P2}}(s)$: system outputs (left) and control signals (right). Note:
during the disturbance rejection test ($10\textrm{s}\leq t<20\textrm{s}$) and
measurement noise sensitivity test ($15\textrm{s}\leq t\leq 20\textrm{s}$),
the signal plots of the 1DOF and 2DOF structures (in both eADRC and PI cases)
remain the same, hence are indistinguishable in the plots.

##  5 FPGA-in-the-loop simulations

###  5.1 Lab setup and testing methodology

The goal of this section is to verify whether the discovered equivalence and
procedures hold under experimental test. Due to, FPGA-in-the-loop (FIL)
validation tests of the considered control algorithms are performed. FPGA-
based implementations can be consider as an alternative to commonly used
microprocessor-based implementations for certain applications, especially when
fast signal processing or control of more parallel processes is required [10,
46]. The reasons for the less popular use of FPGA hardware are often the lack
of experience of control designers and engineers in VHDL programming and FPGA
implementation. To reduce the gap between control system designers and the
capabilities of the FPGA hardware, a relatively simple FIL test methodology,
presented in Figure 7, for control algorithm implementation, prototyping, and
validation, based on low cost FPGA chip and MATLAB/Simulink software, is
proposed. The controller hardware description language (HDL) code is generated
using MATLAB/Simulink HDL Code Generation toolbox, based on the controller’s
discrete form realized in a fixed-point representation format of the
controller’s signals and coefficients. Then, following MATLAB/Simulink FIL
wizard, the controller FIL block is formed by choosing the desired FPGA target
platform; in our case, a low-cost Basys 3 board with Xilinx Artix 7 FPGA chip
XC7A35T is used. The generated controller FIL block is included in the control
loop of the plant model realized in MATLAB/Simulink. By starting the
simulation, the controller is implemented in the FPGA chip, and the simulation
is executed, such that the controller FIL block calculations are performed on
the real FPGA hardware. The FIL simulation signal exchanging process is
assured by a micro-USB cable that connects computer USB port and a JTAG port
on the FPGA board.

Figure 7: Methodology of the performed FPGA-in-the-loop simulation tests.

To comparatively analyze performances of the considered control methods, two
following scenarios are prepared:

  * •

’Scenario I’ — In this test, the comparative performance analysis of output
voltage reference tracking is performed using a highly uncertain model of a
DC-DC buck power converter, controlled by 1DOF PID controller (7) (with first-
order filter $F_{\textrm{Y}}(s)=\frac{1}{T_{\textrm{f}}\cdot s+1}$), 1DOF
eADRC controller (20), and 1DOF eADRC controller (obtained from 1DOF PID by
adding equivalence transfer function (25)). To further complicate the control
task and to check the robustness of the applied control, the governed system
is additionally subjected to an unmodeled, nonlinear load disturbance
(depicted in Figure 8(a)). Details of this scenario are described in Section
5.2.

  * •

’Scenario II’ — In this test, the comparative performance analysis of motor
shaft angular speed reference tracking is performed using a highly uncertain
model of DC motor, controlled by 1DOF and 2DOF eADRC controllers. To further
complicate the control task and to check the robustness of the applied
control, the governed system is additionally subjected to an unmodeled,
nonlinear load disturbance (depicted in Figure 8(b)). Details of this scenario
are described in Section 5.3.

(a) External disturbance in ’Scenario I’

(b) External disturbance in ’Scenario II’

Figure 8: User-defined applied external disturbance. To make the test case
realistic, the information about the acting disturbance is not utilized
anywhere in the control design, as to mimic a real-world scenario where the
external disturbance would be unknown.

###  5.2 FIL simulation of ’Scenario I’

The used DC-DC buck power converter model is expressed as a following second-
order system [44]:

$\ddot{y}_{1}=-\frac{1}{C\cdot R}\cdot\dot{y}_{1}-\frac{1}{C\cdot L}\cdot
y_{1}(t)+\frac{V_{\mathrm{in}}}{C\cdot L}\cdot\left[u_{1}(t)+w_{1}(t)\right],$
(41)

where $y_{1}(t)$ represents the system output voltage, $u_{1}(t)$ is the
control signal, $R=50\Omega$ is the load resistance, $C=0.001$F is the filter
capacitance, $L=0.01$H is the filter inductance, $V_{\mathrm{in}}=20$V is the
input DC voltage source, and $w_{1}(t)$ represents the user-defined external
perturbation (shown in Figure 8(a)).

Applying the Euler approximation and substituting $s=(z-1)/T_{\textrm{s}}$ in
(5), (20) and (25), the discrete forms of the considered 1DOF PID controller,
1DOF eADRC controller, and the equivalence transfer functions become:

$\displaystyle C_{\mathrm{FB}}^{\mathrm{PID}}(z)$
$\displaystyle=\frac{K_{\mathrm{D}}z^{2}+(K_{\mathrm{P}}T_{\textrm{s}}-2K_{\mathrm{D}})z+K_{\mathrm{D}}-K_{\mathrm{P}}T_{\textrm{s}}+K_{\mathrm{P}}T^{2}_{s}}{T_{\textrm{f}}z^{2}+(T_{\textrm{s}}-2T_{\textrm{f}})z+T_{\textrm{f}}-T_{\textrm{s}}},$
(42) $\displaystyle C_{\mathrm{FB}}^{\mathrm{A2}}(z)$
$\displaystyle=\frac{T_{\textrm{s}}}{b_{0}}\cdot\frac{M_{2}z^{2}+M_{1}z+M_{0}}{(z^{2}+N_{1}z+N_{0})(z-1)},$
(43) $\displaystyle C_{\mathrm{EQ2}}(z)$
$\displaystyle=\frac{L_{1}z+L_{0}}{P_{2}z^{2}+P_{1}z+P_{0}},$ (44)

respectively, where $T_{\textrm{s}}$ is the sampling time and the coefficients
of (43) and (44) are given in Appendix A2.

######  Remark 3.

Although not the case here for the considered FPGA board, but one may want to
consider checking other, more efficient discrete implementations of eADRC for
applications with low sampling frequencies [47, 48, 49].

The eADRC controller is tuned by choosing $\omega_{\textrm{CL}}=45$rad/s,
$k_{\mathrm{ESO}}=45$, and, assuming complete knowledge of the plant gain,
$b_{0}=V_{\mathrm{in}}/CL$. The PID controller gains are set based on eADRC
parameters using (26), and two different values of the filter parameter
$T_{\textrm{f}}=\left\\{0.005,0.0003\right\\}$, are analyzed. The considered
discrete controllers are realized in high precision 64-bit fixed-point format,
with the sampling time $T_{\textrm{s}}=0.0001$s. The control objective is to
track a reference signal being a square signal filtered by
$G_{\textrm{f1}}(s)=\frac{1}{(0.1s+1)^{2}}$ despite the presence of unmodeled
external perturbation (in Figure 8(a)) and white measurement noise corrupting
the system output (with noise power $P_{\textrm{n}}=1\times 10^{-7}$ and
sampling time $T_{\textrm{n}}=T_{\textrm{s}}$). The obtained FIL simulation
results are presented in Figure 9.

Figure 9: ’Scenario I’: results of FPGA-in-the-loop simulation with systems
outputs (top); tracking errors (middle); control signals (bottom).

It can be seen that the PID controller with added equivalence transfer
function $C_{\mathrm{EQ2}}$, provides practically the same reference tracking
and disturbance rejection performances as the eADRC controller. A slight
difference, visible in the control signals, is a consequence of their fixed-
point FPGA implementations, because ’1DOF PID+$C_{\mathrm{EQ2}}$’ structure is
realized as a serial connection of (42) and (44), while 1DOF eADRC is realized
solely based on (43). Additionally, it is evident that the eADRC-based
controllers enable better disturbance rejection performances than PID
controller with $T_{\textrm{f}}=0.005$. An improvement in the PID disturbance
rejection performance is achieved by decreasing the filter coefficient
($T_{\textrm{f}}=0.0003$), but in that case, a significant increase of the
measurement noise sensitivity becomes evident by observing the control signals
in Figure 9.

A comparison in consumption of most significant FPGA chip resources for the
considered controllers, namely the look up table (LUT), digital signal
processing (DSP) block, and the flip-flop (FF) block is presented in Table 1.
As expected, it can be seen that the 1DOF PID controller requests the least
FPGA resource, and that structure ’1DOF PID+$C_{\mathrm{EQ2}}$’ occupied more
FPGA resources compared to compact 1DOF eADRC controller, due to its
realization form as a serial connection of two discrete transfer functions
(42) and (44), which requires more multiplication and addition operations than
1DOF eADRC discrete transfer function (43). However, it should be noted that
in this case, a relatively low-cost FPGA chip is used, and compared with
industrial FPGA chips, has significantly less resource. Hence, increasing
consumption of resources, although interesting from academic perspective, is
often not considered a major problem in practical industrial applications.

Table 1: ’Scenario I’ — resource occupancy of FPGA chip XC7A35T for the considered controllers. FPGA resource | 1DOF PID | 1DOF eADRC |  1DOF PID+$C_{\mathrm{EQ2}}$ | Available
---|---|---|---|---
LUTs | 750 (3.61%) | 1005 (4.83%) | 2331 (11.21%) | 20800 (100%)
FF blocks | 144 (0.35%) | 216 (0.52%) | 288 (0.69%) | 41600 (100%)
DSP blocks | 43 (47.78%) | 52 (57.78%) | 72 (80%) | 90 (100%)

###  5.3 FIL simulation of ’Scenario II’

The used DC motor model is expressed as a following second-order system [46]:

$\displaystyle\ddot{y}_{2}$
$\displaystyle=-\frac{L_{\textrm{a}}F_{\textrm{e}}+R_{\textrm{a}}J_{\textrm{e}}}{L_{\textrm{a}}J_{\textrm{e}}}\cdot\dot{y}_{2}-\frac{R_{\textrm{a}}F_{\textrm{e}}+k_{\textrm{em}}k_{\textrm{me}}}{L_{\textrm{a}}J_{\textrm{e}}}\cdot
y_{2}(t)$
$\displaystyle+\frac{k_{\textrm{em}}}{L_{\textrm{a}}J_{\textrm{e}}}\cdot\left[u_{2}(t)+w_{2}(t)\right],$
(45)

the where $y_{2}(t)$ represents the system output (DC motor angular speed),
$u_{2}(t)$ is the control signal, $R_{\textrm{a}}=8.9\Omega$ is the motor
armature resistance, $L_{\textrm{a}}=4.5$mH is the armature inductance,
$J_{\textrm{e}}=8e^{-5}$kgm2 is the motor moment of inertia,
$F_{\textrm{e}}=12e^{-5}$kgm2s/rad is the motor viscous friction coefficient,
$k_{\textrm{em}}=0.105$Nm/A is the motor torque constant,
$k_{\textrm{me}}=0.105$Vs/rad is the back electromotive force constant, and
$w_{2}(t)$ represents the user-defined external perturbation (shown in Figure
8(b)).

In the same manner as in previous scenario in Section 5.2, the discrete forms
of the considered controllers are derived by applying Euler approximation.
This means that discrete 1DOF eADRC controller is realized based on (43). In
order to realize 2DOF eADRC controller, discrete form of (31), assuming first-
order filter $F_{\mathrm{R}}(s)=\frac{1}{T_{\textrm{r}}s+1}$, is obtained as:

$C_{\mathrm{PF}}^{\mathrm{A2}}(z)=\frac{H_{3}z^{3}+H_{2}z^{2}+H_{1}z+H_{0}}{Q_{3}z^{3}+Q_{2}z^{2}+Q_{1}z+Q_{0}},$
(46)

with its coefficients given in Appendix A2. Both controllers are implemented
in 64-bit fixed-point format, with sampling period $T_{\textrm{s}}=0.001$s and
tuning parameters $\omega_{\textrm{CL}}=50$rad/s, $k_{\mathrm{ESO}}=12$, and,
assuming complete knowledge of the plant gain,
$b_{0}=k_{em}/(J_{\textrm{e}}L_{\textrm{a}})$. The additional parameters
related to the 2DOF structure are set to $\beta=0.6$, while two different
values of the parameter $T_{\textrm{r}}=\left\\{0.03,0.08\right\\}$ are
analyzed. The control objective is to track a reference trajectory being a
square signal filtered by $G_{\textrm{f2}}(s)=\frac{1}{(0.05s+1)^{2}}$ despite
the presence of external disturbance (in Figure 8(b)) and output measurement
noise (with power $P_{\textrm{n}}=1\times 10^{-5}$ and sampling time
$T_{\textrm{n}}=T_{\textrm{s}}$). The obtained FIL simulation results are
presented in Figure 10.

From the obtained results, it is evident that the proposed 2DOF eADRC
structure enables the realization of the set-point response with desired
overshoot, rise time and control signal peak, without the degradation of
disturbance rejection performance and noise sensitivity. It is shown that
increasing parameter $T_{\textrm{r}}$ in 2DOF eADRC controller decreases the
system overshoot and control signal peak, but it also has the effect of
increasing the rise time, i.e. increases tracking error peaks. Regarding FPGA
resource consumption, one can see in Table 2 that the 2DOF eADRC controller
occupied more FPGA resource than the 1DOF eADRC controller, however it does
not significantly limits its implementation on low-cost FPGA hardware, such as
the used XC7A35T chip.

Figure 10: ’Scenario II’: results of FPGA-in-the-loop simulation with systems outputs (top); tracking errors (middle); control signals (bottom). Table 2: ’Scenario II’ — resource occupancy of FPGA chip XC7A35T for the considered controllers. FPGA resource | 1DOF eADRC | 2DOF eADRC | Available
---|---|---|---
LUTs | 1005 (4.83%) | 3358 (16.14%) | 20800 (100%)
FF blocks | 216 (0.52%) | 432 (1.04%) | 41600 (100%)
DSP blocks | 52 (57.78%) | 69 (76.66%) | 90 (100%)

##  6 Conclusions

In this work, we have derived formal conditions of equivalence between
standard PI/PID controllers and error-based ADRC structures as well as
procedures of going from one structure to another. These procedures facilitate
expressing error-based ADRC schemes as standard industrial 1DOF/2DOF
controllers and allow the designed controller to have desired characteristic
of ADRC (i.e. strong robustness against internal and external uncertainties)
while being expressed in a form familiar in engineering practice, still being
dominated by PI/PID-based control schemes. These results ensure backward
compatibility of future ADRC-based solutions and contribute to the adoption of
active disturbance rejection-based methods in industrial practice as a viable
contender to conventional PI/PID controllers.

The limitation of the proposed methodology of transitioning from error-based
ADRC to PI/PID form is that it seems (at least at the moment) unique to error-
based ADRC and is not directly transferable to other control schemes.

## Appendix

### A1. Implementation _crib sheet_

Table 3 serves as an implementation crib sheet for controller types considered
in this paper. It is prepared for the commonly used first ($n=1$) and second
($n=2$) order systems, containing ready-to-use transfer functions of PI/PID
controllers and eADRC, in both 1DOF and 2DOF forms.

Table 3: Implementation crib sheet for commonly used first ($n=1$) and second
($n=2$) order systems, containing ready-to-use transfer functions of
conventional PI/PID controllers and eADRC, in 1DOF and 2DOF forms. The used
acronym ’TF’ stands for transfer function. Block diagram of the implementation
scheme is in Figure 1.

Controller |  First-order plant model ($n=1$) |  Second-order plant model ($n=2$)
---|---|---
Pre-filter TF | Feedback TF | Pre-filter TF | Feedback TF
1DOF PI/PID | $C_{\textrm{PF}}^{\textrm{PI}}(s)=1$ | $C_{\textrm{FB}}^{\textrm{PI}}(s)=\frac{K_{\mathrm{P}}s+K_{\mathrm{I}}}{s}$ | $C_{\textrm{PF}}^{\textrm{PID}}(s)=1$ | $C_{\textrm{FB}}^{\textrm{PID}}(s)=\frac{K_{\mathrm{D}}s^{2}+K_{\mathrm{P}}s+K_{\mathrm{I}}}{s}F_{\mathrm{Y}}(s)$
1DOF eADRC | $C_{\textrm{PF}}^{\textrm{A1}}(s)=C_{\textrm{PF}}^{\textrm{PI}}(s)C_{\textrm{EQ1}}^{-1}=1$ | $C_{\textrm{FB}}^{\textrm{A1}}(s)=C_{\textrm{FB}}^{\textrm{PI}}(s)C_{\textrm{EQ1}}=\frac{1}{b_{0}}\cdot\frac{(k_{1}l_{1}+l_{2})\cdot s+k_{1}l_{2}}{s^{2}+(k_{1}+l_{2})\cdot s}$ | $C_{\textrm{PF}}^{\textrm{A2}}(s)=C_{\textrm{PF}}^{\textrm{PID}}(s)C_{\textrm{EQ2}}^{-1}=1$ | $C_{\textrm{FB}}^{\textrm{A2}}(s)=C_{\textrm{FB}}^{\textrm{PID}}(s)C_{\textrm{EQ2}}=\frac{1}{b_{0}}\cdot\frac{(k_{1}l_{1}+k_{2}l_{2}+l_{3})\cdot s^{2}+(k_{1}l_{2}+k_{2}l_{3})\cdot s+k_{1}l_{3}}{s^{3}+(k_{2}+l_{1})\cdot s^{2}+(l_{2}+k_{1}+l_{1}k_{2})\cdot s}$
2DOF PI/PID | $C_{\textrm{PF}}^{\textrm{PI}}(s)=\frac{K_{\mathrm{P}}\beta s+K_{\mathrm{I}}}{K_{\mathrm{P}}s+K_{\mathrm{I}}}F_{\mathrm{R}}(s)$ | $C_{\textrm{FB}}^{\textrm{PI}}(s)=\frac{K_{\mathrm{P}}s+K_{\mathrm{I}}}{s}$ | $C_{\textrm{PF}}^{\textrm{PID}}(s)=\frac{K_{\mathrm{P}}\beta s+K_{\mathrm{I}}}{K_{\mathrm{D}}s^{2}+K_{\mathrm{P}}s+K_{\mathrm{I}}}\frac{F_{\mathrm{R}}(s)}{F_{\mathrm{Y}}(s)}$ | $C_{\textrm{FB}}^{\textrm{PID}}(s)=\frac{K_{\mathrm{D}}s^{2}+K_{\mathrm{P}}s+K_{\mathrm{I}}}{s}F_{\mathrm{Y}}(s)$
2DOF eADRC | $C_{\textrm{PF}}^{\textrm{A1}}(s)=C_{\textrm{PF}}^{\textrm{PI}}(s)C_{\textrm{EQ1}}^{-1}=\frac{K_{\mathrm{P}}\beta s+K_{\mathrm{I}}}{K_{\mathrm{P}}s+K_{\mathrm{I}}}\frac{F_{\mathrm{R}}(s)}{F_{\mathrm{Y1}}(s)}$ | $C_{\textrm{FB}}^{\textrm{A1}}(s)=C_{\textrm{FB}}^{\textrm{PI}}(s)C_{\textrm{EQ1}}=\frac{1}{b_{0}}\cdot\frac{(k_{1}l_{1}+l_{2})\cdot s+k_{1}l_{2}}{s^{2}+(k_{1}+l_{2})\cdot s}$ | $C_{\textrm{PF}}^{\textrm{A2}}(s)=C_{\textrm{PF}}^{\textrm{PID}}(s)C_{\textrm{EQ2}}^{-1}=\frac{K_{\mathrm{P}}\beta s+K_{\mathrm{I}}}{K_{\mathrm{D}}s^{2}+K_{\mathrm{P}}s+K_{\mathrm{I}}}\cdot\frac{F_{\mathrm{R}}(s)}{F_{\mathrm{Y2}}(s)}$ | $C_{\textrm{FB}}^{\textrm{A2}}(s)=C_{\textrm{FB}}^{\textrm{PID}}(s)C_{\textrm{EQ2}}=\frac{1}{b_{0}}\cdot\frac{(k_{1}l_{1}+k_{2}l_{2}+l_{3})\cdot s^{2}+(k_{1}l_{2}+k_{2}l_{3})\cdot s+k_{1}l_{3}}{s^{3}+(k_{2}+l_{1})\cdot s^{2}+(l_{2}+k_{1}+l_{1}k_{2})\cdot s}$

### A2. Coefficients of discrete transfer functions

  * •

Coefficients of (43):

$M_{2}=k_{1}l_{1}+k_{2}l_{2}+l_{3}$;

$M_{1}=-2M_{2}+T_{\textrm{s}}\cdot(k_{1}l_{2}+k_{2}l_{3})$;

$M_{0}=M_{2}-T_{\textrm{s}}\cdot\left(k_{1}l_{2}+k_{2}l_{3}\right)+T_{\textrm{s}}^{2}k_{1}l_{3}$;

$N_{1}=T_{\textrm{s}}\cdot\left(k_{2}+l_{1}\right)-2$;

$N_{0}=-N_{1}+T_{\textrm{s}}^{2}\cdot\left(l_{2}+k_{1}+l_{1}k_{2}\right)-1$.

  * •

Coefficients of (44):

$L_{1}=T_{\textrm{s}}T_{\textrm{f}}$;

$L_{0}=-L_{1}+T_{\textrm{s}}^{2}$;

$P_{2}=\frac{1}{k_{2}l_{1}+l_{2}+k_{1}}$;

$P_{1}=P_{2}\cdot\left(T_{\textrm{s}}k_{2}l_{1}-2\right)$;

$P_{0}=P_{2}\cdot\left(T_{\textrm{s}}k_{2}l_{1}+1\right)+T_{\textrm{s}}^{2}$.

  * •

Coefficients of (46):

$H_{3}=\frac{K_{\mathrm{P}}\beta}{k_{2}l_{1}+l_{2}+k_{1}}$;

$H_{2}=-3H_{3}+T_{\textrm{s}}\cdot\frac{K_{\mathrm{P}}\beta+K_{\mathrm{I}}(k_{2}+l_{1})}{k_{2}l_{1}+l_{2}+k_{1}}$;

$H_{1}=3H_{3}-2T_{\textrm{s}}\cdot\frac{K_{\mathrm{P}}\beta+K_{\mathrm{I}}(k_{2}+l_{1})}{k_{2}l_{1}+l_{2}+k_{1}}+T_{\textrm{s}}^{2}K_{\mathrm{P}}\beta\\\
+T_{\textrm{s}}^{2}\cdot\frac{K_{\mathrm{I}}(k_{2}+l+1)}{k_{2}l_{1}+l_{2}+k_{1}}$;

$H_{0}=-H_{3}+T_{\textrm{s}}\cdot\frac{K_{\mathrm{P}}\beta+K_{\mathrm{I}}(k_{2}+l_{1})}{k_{2}l_{1}+l_{2}+k_{1}}-T_{\textrm{s}}^{2}K_{\mathrm{P}}\beta\\\
-T_{\textrm{s}}^{2}\cdot\frac{K_{\mathrm{I}}(k_{2}+l+1)}{k_{2}l_{1}+l_{2}+k_{1}}-T_{\textrm{s}}^{3}K_{\mathrm{I}}$;

$Q_{3}=K_{\mathrm{D}}T_{\textrm{r}}$;

$Q_{2}=-3Q_{3}+T_{\textrm{s}}\cdot\left(K_{\mathrm{D}}+K_{\mathrm{P}}T_{\textrm{r}}\right)$;

$Q_{1}=3Q_{3}-2T_{\textrm{s}}\cdot\left(K_{\mathrm{D}}+K_{\mathrm{P}}T_{\textrm{r}}\right)+T_{\textrm{s}}^{2}\cdot\left(K_{\mathrm{P}}+K_{\mathrm{I}}T_{\textrm{r}}\right)$;

$Q_{0}=-Q_{3}+T_{\textrm{s}}\cdot\left(K_{\mathrm{D}}+K_{\mathrm{P}}T_{\textrm{r}}\right)-T_{\textrm{s}}^{2}\cdot\left(K_{\mathrm{P}}+K_{\mathrm{I}}T_{\textrm{r}}\right)+T_{\textrm{s}}^{3}K_{\mathrm{I}}$.

## Acknowledgments

  * •

This work was supported by the International Foreign Expert Project Fund of
Jinan University under grant number G2021199027L

  * •

This work was supported by the University of Defence in Belgrade under grant
VA-TT/1/21-23.

  * •

There are no relevant financial or non-financial competing interests to
report.

## References

  * [1] Z. Gao and R. Rhinehart, “Theory vs. practice: the challenges from industry,” in American Control Conference, vol. 2, pp. 1341–1349, 2004\.
  * [2] J. Han, “From PID to active disturbance rejection control,” IEEE Transactions on Industrial Electronics, vol. 56, no. 3, pp. 900–906, 2009.
  * [3] G. Herbst, “A simulative study on active disturbance rejection control (ADRC) as a control tool for practitioners,” Electronics, vol. 2, no. 3, pp. 246–279, 2013.
  * [4] Z. Gao, “Scaling and bandwidth-parameterization based controller tuning,” in American Control Conference, vol. 6, pp. 4989–4996, 2003.
  * [5] G. Herbst, “Transfer function analysis and implementation of active disturbance rejection control,” Control Theory and Technology, vol. 19, pp. 19–34, 2021.
  * [6] Z. Gao, “Active disturbance rejection control: a paradigm shift in feedback control system design,” in American Control Conference, 2006.
  * [7] G. Herbst, “Practical active disturbance rejection control: bumpless transfer, rate limitation, and incremental algorithm,” IEEE Transactions on Industrial Electronics, vol. 63, no. 3, pp. 1754–1762, 2016\.
  * [8] M. Nowicki, R. Madonski, and K. Kozlowski, “Disturbance rejection through virtual extension of the system – geometric approach,” IFAC Proceedings Volumes, vol. 47, no. 3, pp. 7723–7728, 2014.
  * [9] M. Nowicki, R. Madonski, and K. Kozlowski, “First look at conditions on applicability of ADRC,” in International Workshop on Robot Motion and Control, pp. 294–299, 2015.
  * [10] M. R. Stankovic, S. M. Manojlovic, S. M. Simic, S. T. Mitrovic, and M. B. Naumovic, “FPGA system-level based design of multi-axis ADRC controller,” Mechatronics, vol. 40, pp. 146–155, 2016.
  * [11] S. Shao and Z. Gao, “On the conditions of exponential stability in active disturbance rejection control based on singular perturbation analysis,” International Journal of Control, vol. 90, no. 10, pp. 2085–2097, 2017.
  * [12] X. Zhang, X. Zhang, W. Xue, and B. Xin, “An overview on recent progress of extended state observers for uncertain systems: methods, theory, and applications,” Advanced Control for Applications, vol. 3, no. 2, 2021.
  * [13] R. Madonski and P. Herman, “Survey on methods of increasing the efficiency of extended state disturbance observers,” ISA Transactions, vol. 56, pp. 18–27, 2015.
  * [14] H. Sira-Ramirez, E. W. Zurita-Bustamante, and C. Huang, “Equivalence among flat filters, dirty derivative-based PID controllers, ADRC, and integral reconstructor-based sliding mode control,” IEEE Transactions on Control Systems Technology, vol. 28, no. 5, pp. 1696–1710, 2020.
  * [15] S. Zhong, Y. Huang, and L. Guo, “A parameter formula connecting PID and ADRC,” Science China Information Sciences, vol. 63, no. 9, 2020.
  * [16] Z. Wu, Z. Gao, D. Li, Y. Chen, and Y. Liu, “On transitioning from PID to ADRC in thermal power plants,” Control Theory and Technology, vol. 19, pp. 3–18, 2021.
  * [17] H. Jin and Z. Gao, “On the notions of normality, locality, and operational stability in ADRC,” Control Theory and Technology, 2023.
  * [18] X. Li, Z. Gao, W. Ai, and S. Tian, “On the equivalence between PID-like controller and LADRC for second-order systems,” in Data Driven Control and Learning Systems Conference, pp. 1003–1008, 2020.
  * [19] H. Sira-Ramirez and E. Zurita-Bustamante, “On the equivalence between ADRC and flat filter based controllers: a frequency domain approach,” Control Engineering Practice, vol. 107, p. 104656, 2021.
  * [20] H. Jin, Y. Chen, and W. Lan, “Replacing PI control with first-order linear ADRC,” in Data Driven Control and Learning Systems Conference, pp. 1097–1101, 2019.
  * [21] H. Jin, J. Song, W. Lan, and Z. Gao, “On the characteristics of ADRC: a PID interpretation,” Science China Information Sciences, vol. 63, no. 10, 2020.
  * [22] S. Ahmad and A. Ali, “Unified disturbance-estimation-based control and equivalence with IMC and PID: case study on a DC–DC boost converter,” IEEE Transactions on Industrial Electronics, vol. 68, no. 6, pp. 5122–5132, 2021.
  * [23] W. Tan, W. Han, and J. Xu, “State-space PID: a missing link between classical and modern control,” IEEE Access, 2022.
  * [24] Z. Wu, Makeximu, J. Yuan, Y. Liu, D. Li, and Y. Chen, “A synthesis method for first-order active disturbance rejection controllers: procedures and field tests,” Control Engineering Practice, vol. 127, p. 105286, 2022.
  * [25] C. Zhao, Y. Xue, and C.-E. Huang, “Tuning ADRC for multi-variable system based on existing PID parameters,” in International Conference on Control, Automation and Systems, pp. 1272–1277, 2016.
  * [26] X. Li, Y. Hu, Z. Gao, W. Ai, and S. Tian, “A PID controller based on ESO and tuning method,” in Data Driven Control and Learning Systems Conference, pp. 1026–1030, 2022.
  * [27] Z.-Y. Nie, Z. Li, Q.-G. Wang, Z. Gao, and J. Luo, “A unifying Ziegler–Nichols tuning method based on active disturbance rejection,” International Journal of Robust and Nonlinear Control, vol. n/a, no. n/a, 2021.
  * [28] S. Zhong, Y. Huang, and L. Guo, “An ADRC-based PID tuning rule,” International Journal of Robust and Nonlinear Control, pp. 1–14, 2021.
  * [29] M. Huba and Z. Gao, “Uncovering disturbance observer and ultra-local plant models in series PI controllers,” Symmetry, vol. 14, no. 4, 2022.
  * [30] M. Huba, “Disturbance observer in PID controllers for first-order time-delayed systems,” IFAC-PapersOnLine, vol. 55, no. 17, pp. 19–24, 2022\.
  * [31] R. Madonski, G. Herbst, and M. Stankovic, “ADRC in output and error form: connection, equivalence, performance,” Control Theory and Technology, vol. 21, pp. 56–71, 2023.
  * [32] M. M. Michalek, “Robust trajectory following without availability of the reference time-derivatives in the control scheme with active disturbance rejection,” in American Control Conference, pp. 1536–1541, 2016.
  * [33] R. Madonski, S. Shao, H. Zhang, Z. Gao, J. Yang, and S. Li, “General error-based active disturbance rejection control for swift industrial implementations,” Control Engineering Practice, vol. 84, pp. 218–229, 2019\.
  * [34] R. Madonski, K. Łakomy, and J. Yang, “Comparative study of output-based and error-based ADRC schemes in application to buck converter-fed DC motor system,” in IEEE Conference on Decision and Control, pp. 2744–2749, 2020\.
  * [35] M. Stankovic, R. Madonski, S. Shao, and D. Mikluc, “On dealing with harmonic uncertainties in the class of active disturbance rejection controllers,” International Journal of Control, vol. 94, no. 10, pp. 2795–2810, 2021\.
  * [36] R. Madonski, M. Ramirez-Neria, M. Stankovic, S. Shao, Z. Gao, J. Yang, and S. Li, “On vibration suppression and trajectory tracking in largely uncertain torsional system: an error-based ADRC approach,” Mechanical Systems and Signal Processing, vol. 134, p. 106300, 2019.
  * [37] T. E. Lechekhab, S. Manojlovic, M. Stankovic, R. Madonski, and S. Simic, “Robust error-based active disturbance rejection control of a quadrotor,” Aircraft Engineering and Aerospace Technology, vol. 93, pp. 89–104, 2021\.
  * [38] A. Ferdjali, M. Stankovic, S. Manojlovic, R. Madonski, D. Bujakovic, and A. Djenadbia, “Systematic design of nonlinear ADRC for laser seeker system with FPGA-based rapid prototyping validation,” Aircraft Engineering and Aerospace Technology, vol. 94, pp. 1087–1099, 2022.
  * [39] I. M. Horowitz, Synthesis of Feedback Systems.  Academic Press, 1963.
  * [40] M. Araki and H. Taguchi, “Two-degree-of-freedom PID controllers,” International Journal of Control, Automation, and Systems, vol. 1, no. 4, pp. 401–411, 2003.
  * [41] M. R. Mataušek and T. B. Šekara, “PID controller frequency-domain tuning for stable, integrating and unstable processes, including dead-time,” Journal of Process Control, vol. 21, no. 1, pp. 17–27, 2011.
  * [42] S. Liu, Y.-L. Zhang, W. Xue, G. Shi, M. Zhu, and D. Li, “Frequency response-based decoupling tuning for feedforward compensation ADRC of distributed parameter systems,” Control Engineering Practice, vol. 126, p. 105265, 2022.
  * [43] T. Huang, G. Hu, Y. Yan, D. Zeng, and Z. Meng, “Combined feedforward and error-based active disturbance rejection control for diesel particulate filter thermal regeneration,” ISA Transactions, 2022.
  * [44] K. Łakomy, R. Madonski, B. Dai, J. Yang, P. Kicki, M. Ansari, and S. Li, “Active disturbance rejection control design with suppression of sensor noise effects in application to DC–DC buck power converter,” IEEE Transactions on Industrial Electronics, vol. 69, no. 1, pp. 816–824, 2021.
  * [45] K. J. Åström and R. M. Murray, Feedback Systems: an Introduction for Scientists and Engineers.  Princeton University Press, 2010.
  * [46] M. Stankovic, M. Naumovic, S. Manojlovic, and S. Simic, “Optimized pure hardware FPGA-based implementation of active disturbance rejection control,” Electrical Engineering, vol. 100, no. 1, pp. 111–121, 2018.
  * [47] G. Herbst and R. Madonski, “Tuning and implementation variants of discrete-time ADRC,” Control Theory and Technology, 2023.
  * [48] G. Herbst, “A minimum-footprint implementation of discrete-time ADRC,” in European Control Conference, pp. 107–112, 2021.
  * [49] G. Herbst and R. Madonski, “Tuning and implementation variants of discrete-time ADRC,” Control Theory and Technology, vol. 21, pp. 72–88, 2023.