Scalable Quantum Error Correction for Surface Codes using FPGA

Namitha Liyanage,
Yue Wu, Alexander Deters and
Lin Zhong
Department of Computer Science,
Yale University,
New Haven, CT

Email : {namitha.liyanage, yue.wu, alex.deters<EMAIL_ADDRESS>
A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than $O(d^3)$. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to $d$,  given $O(d^3)$ parallel computing resources. The decoding time per measurement round decreases as $d$ increases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. We are able to implement $d$ up to 21 with a Xilinx VCU129 FPGA, for which an average decoding time is 11.5 ns per measurement round under phenomenological noise of 0.1%, significantly faster than any existing decoder implementation. Since the decoding time per measurement round of Helios decreases with $d$, Helios can decode a surface code of arbitrarily large $d$ without a growing backlog.

§ INTRODUCTION

The high error rates of quantum devices pose a significant obstacle to the realization of a practical quantum computer.  As a result, the development of effective quantum error correction (QEC) mechanisms is crucial for the successful implementation of a fault-tolerant quantum computer.

One promising approach for QEC is surface codes [1, 2, 3] in which information of a single qubit (called a logical qubit) is redundantly encoded across many physical data qubits, with a set of ancillary qubits interacting with the data qubits.
By periodically measuring the ancillary qubits, one can detect and potentially correct errors in physical qubits.

Once the presence of errors has been detected through the measurement of ancillary qubits, a classical algorithm, or decoder, guesses the underlying error pattern and corrects it accordingly.
The faster errors can be corrected, the more time a quantum computer can spend on useful work.
Due to the error rate of the state-of-the-art qubits, very large surface codes ($d>25$) are necessary to achieve fault-tolerant quantum computing [2, 4, 5]. See <ref> for more background.

As surveyed in <ref>, previously reported decoders capable of decoding errors as fast as measured, or backlog-free, either exploit limited parallelism [6, 7, 8], or sacrifice accuracy [9, 10].
Sparse Blossom
[8] and Fusion Blossom [11] feature an important algorithmic breakthrough in realizing MWPM-based decoders. Fusion Blossom can additionally leverage measurement round-level parallelism to meet the throughput requirement of very large $d$. However, due to their software-based realizations, both Sparse Blossom and Fusion Blossom suffer from decoding time per round longer than that of by orders of magnitude at large $d$ and higher noise level. When used in a quantum computer, the computer would spend most of execution time waiting for error correction.

In this paper we report a distributed Union-Find (UF) decoder (<ref>) and its FPGA implementation called  (<ref>). Given $O(d^3)$ parallel resources, our decoder achieves sublinear average time complexity according to empirical results for $d$ up to 21, the first to the best of our knowledge.
adding more parallel resources will not reduce the time complexity of the decoder, due to the inherent nature of error patterns.
Our decoder is a distributed design of and logically equivalent to the UF decoder first proposed in [12].
We implement the distributed UF decoder with , a scalable architecture for organizing the parallel computation units.
is the first architecture of its kind that can scale to arbitrarily large surface codes by exploiting parallelism at the vertex level of the model graph.
In <ref>, we present experimental validations of the distributed UF decoder and using a VCU129 FPGA board [13] for up to $d=21$.

The decoder's average decoding time per measurement round under a phenomenological noise of 0.1% is 11.5 ns for $d=21$, which is significantly faster than any existing decoder implementation.
Our results successfully demonstrate, for the first time, a decoder design with decreasing average time per measurement round when $d$ increases.
This shows evidence that the decoder can scale to arbitrarily large surface codes without a growing backlog.

In summary, we report the following contributions in this work.

* A distributed algorithm that implements the Union-Find decoder that can exploit parallel computing units to stop decoding time per measurement round from growing with the code distance $d$.

* The architecture and its FPGA-based implementation that realize the distributed Union-Find decoder.

* A set of empirical data based on the FPGA implementation that demonstrate decreasing decoding time per round as $d$ grows and 11.5 ns decoding time per measurement round for $d=21$ under a phenomenological noise of 0.1%.

is open-source and available from [14].

UF decoder avoids the computationally expensive matching procedure by only caring about clusters of syndromes [12].

”UF avoids expensive matching algorithms” sounds weird to me. Isn't MWPM a matching algorithm? Are you saying UF is not a matching algorithm? What is a matching algorithm indeed?
Although it's not able to solve exactly the most likely error pattern due to the lack of the detailed matchings between all pairs of syndromes, union-find decoder tries to output an correction pattern that doesn't contaminate the logical information for most of the time.
Note that there exists cases where union-find decoder fails to output the most likely correction pattern but MWPM decoder succeeds as shown later in sss:suboptimality_union_find_css.
This is why generally union-find decoder has slightly lower accuracy than MWPM decoder <cit.>, causes a slightly higher logical error rate ($9.4\%$) than MWPM decoder ($5.7\%$) under the same condition (physical error rate of $10.0\%$) [16].

Despite the accuracy loss of union-find decoder, it can be easily implemented as a parallel algorithm because the growth of the clusters is essentially in parallel and merging of clusters does not require global synchronization.

Although the parallel implementation of UF decoder is out of the scope of this paper, union-find decoder is a strong competitor in achieving the $O(d^2)$ lower bound for sequential implementation and $O(1)$ for parallel implementation.
The logic flow above is not obvious to me: why is UF more amenable to parallelization than MWPM?

In this work, we look at using UF decoder for XZZX surface code [3], a variant of surface code that offers higher tolerance for biased noise model (physical qubit dominated by one kind of Pauli error) than standard surface code while has the same performance under unbiased noise model.

Such biased noise is very common in the Bosonic qubits, which is a hardware-efficient encoding using Bosonic mode in a cavity <cit.> where bit-flip errors are suppressed and the physical errors are dominated by phase-flip errors.
Prior work for decoding XZZX surface code is limited to using only MWPM decoders. is this true?
This is the first work of using UF decoder for XZZX surface code.

We show that for XZZX surface code, UF decoder and MWPM decoder has the same decoding accuracy under perfect measurement conditions.
We further show that for XZZX surface code under circuit-level noise model, UF decoder performs slightly worse quantify than an MWPM decoder.
We further extend this work to define a criteria such that as long as it is satisfied UF decoder and MWPM decoder will provide the same accuracy irresepctive of XZZX or CSS surface code.

As we show that UF decoder has the same accuracy as MWPM decoder for XZZX surface code, and as UF decoder can be parallelized, we believe our work will help to make real time decoding of large surface code patches possible in future.

§ BACKGROUND

§ DISTRIBUTED UF DECODER DESIGN

Our goal to build a QEC decoder is scalability to the number of qubits.
As surface codes can exponentially reduce logical error rate with respect to $d$, larger surface codes with hundreds or even thousands of qubits are necessary for fault-tolerant quantum computing. Therefore, the average decoding time per measurement round  should not grow with $d$, to avoid exponential backlog for any larger $d$.

We choose the UF decoder for two reasons.
First, it has a much lower time complexity than the MWPM algorithm. Although in general, the UF decoder achieves lower decoding accuracy than MWPM decoders, it is as accurate in many interesting surface codes and noise models [15, 16].
Second, the UF decoder maintains fewer intermediate states, which makes it easier to implement in a distributed manner.
We observe that the Growing stage from line:grow-start to line:grow-end in <ref> operates on each vertex independently without dependencies from other vertices.
A vertex requires only the parity of the cluster it is a part of for the growing stage.
Second, during the merging stage, a vertex only needs to interact with its immediate neighbors (line:merge).

architecture for d=5 surface code for 5 measurement rounds. As d=5 surface code has 12 ancilla qubits of Z-type, contains a 12x5 PE array. PE $n$ indicates PE with $v.id=n$. Not all links from the controller to PEs and  all $v.id$s shown in the figure

The bottom left corner of the PE array shown in <ref>. Only part of the logic and memory inside PE 1 is shown: growth (S3) is per edge and is stored in the PE with lower $id$. grow logic (in brown) calculates the updated growth value. edge_busy (in green) is per adjacent PE and is used to calculate $v.$busy.

§.§ Time Complexity Analysis

We first show the PE coordination complexity and then calculate the overall time complexity based on that.

PE Coordination Complexity The controller's time complexity is contingent upon the implementation of the shared memory for $v.\code{busy}$ and $v.\code{codd}$.
Since both checks involve logical OR operations on individual PE information, the most efficient implementation consists of a logical tree of OR operations, yielding a time complexity of $O(log(d))$.

Worst-case Time Complexity The worst-case time complexity of our distributed UF decoder is $O(d^3log(d))$.
We explain this as follows.
Each stage of our distributed-UF algorithm is $O(1)$ time. Thus the worst case depends on the total number of stages.
In the merging stage, both propagating the $cid$ and calculating the parity uses shared memory-based flooding and convergecast algorithms, each of which requires $O(D)$ merging and checking stages, where $D$ is the cluster diameter.
The maximum possible diameter, $O(d^3)$, occurs when a series of single-vertex clusters merge, creating a chain of clusters with a total diameter of $O(d^3)$.

As coordinating between stages has a complexity of $O(log(d))$, the overall time complexity is $O(d^3log(d))$.

Nevertheless, the worst-case scenario is extremely rare since larger clusters are exponentially less likely to occur. As shown in the empirical results reported in sec:results, the average time grows sublinearly with $d$.

§ ARCHITECTURE

We next describe , the architecture for the distributed UF decoder.

§.§ Overview

organizes PEs and the controller in a custom topology that combines a 3-D grid and a tree as illustrated by <ref> and explained below.

* PEs are organized according to the position of vertices in the model graph they represent. We assign $v.id$ sequentially, starting with 1 from the bottom left corner and continuing in row-major order for each measurement round.
Shared memory S1 ($v.cid$, $v.odd$, $v.parent$ and $v.st\_odd$) and S2 ($v.codd$, $v.$stage, and $v.$busy) are per PE.

* Shared memory S3 ($e.\code{growth}$) is added to the incident PE with the lower $id$.

* A link between every two adjacent PEs to read from each other's S1 and for the one with the higher $id$ to read the other's S4. This results in a network of links in a 3-D grid topology. As a PE represents a vertex in the model graph, a link represents an edge. Broad pink lines in <ref> represent these links.

* The controller is realized as a tree of control nodes (ssec:coordination_tree).
The leaf nodes of the tree contain shared memory S4.

* A link between each PE and the controller for the controller to read from S2 and for the PEs to read from S4. Dashed orange lines in <ref> represent these links.

§.§ Controller

implements the controller as a tree of control nodes to avoid the scalability bottleneck.
The controller requires three pieces of information from each PE: $v.codd$, $v.\code{stage}$ and $v.\code{busy}$.
Each leaf control node of the tree is directly connected with a subset of PEs.
We can consider these PEs as the children of the leaf node.
Each node in the tree gathers vertex information from its children and reports it to the parent.
With information from all vertices, the root control node runs  <ref> and decides whether to advance the stage.

We leave height, branching factor, and the subset of PEs connected to each leaf node as implementation choices.
The necessary requirement is that the controller should not slow down the overall design.

§ FPGA IMPLEMENTATION

We next describe an implementation of targeting a single FPGA.
We choose FPGA for two reasons. It supports massively parallel logic, which is essential as the number of PEs grows proportional to $d^3$ in our distributed UF design.
Moreover, it allows deterministic latency for each operation, which facilitates synchronizing all the PEs.
Our implementation contains approximately 3000 lines of Verilog code, which is publicly available at [14].

§.§ Leveraging global synchronization in FPGA

We leverage global synchronization inside the FPGA to speed up our distributed UF algorithm. Running the FPGA design in a single-clock domain allows us to have all the PEs and the control nodes tightly synchronized.
Notably, we simplify our algorithm as follows.
Firstly, we run the Merging (line:FPGA_merging) and Checking stages (line:FPGA_checking) in parallel within each PE.
The tight synchronization of all PEs guarantees that false negative busy signals do not occur.

Secondly, we reduce the overhead of synchronization by having the controller only coordinate moving to the Growing stage at the beginning of each iteration (line:PE_move_growing). As each PE can perform the Growing stage deterministically in a single cycle, PEs can move to the Merging stage without central coordination (line:PE_move_merging).

Additionally, as the controller deterministically knows the exact stage each PE is in, stage is stored locally and not shared with the controller. Thus the information from the PEs to the controller is limited to two bits, $v.\code{busy}$ and $v.\code{odd}$.

<ref> and <ref> lists the FPGA-oriented algorithm of PE and the controller. The logic at every positive edge is executed in parallel. <ref> shows a minimal diagram of a PE in the FPGA implementation.

FPGA-oriented algorithm for vertex $v$ in the distributed UF decoder.

$v.cid \gets v.id$;
$v.odd  \gets v.m$;
$v.parent \gets v.id$;
$v.st\_odd \gets v.m$

% Stage transition logic

$\code{global\_stage} = $terminate

$\code{global\_stage} = $growing
$v.\code{stage} \gets \code{growing}$

$v.\code{stage} = $growing
$v.\code{stage} \gets \code{merging}$

% Growing logic

$v.\code{stage} = $growing

$e.$growth$<e.w$  $u.cid\neq v.cid$
v.odd  u.odd
$e.$growth$\gets \text{MIN}(e.$growth$+2$, $w$)

v.odd  u.odd
$e.$growth$\gets \text{MIN}(e.$growth$+1$, $w$)

% Merging logic

Let $u$ be $\arg\min_{u \in (v.nb~\cup~\{v\})}(u.cid)$

$v.cid \gets u.cid$

$v.parent \gets u.id$

$v.st\_odd \gets subtree\_parity(v)$

$v.parent = v.id$
$v.odd \gets v.st\_odd$

% Checking logic

$v.\code{busy} \gets \code{true}$

$v.\code{busy} \gets \code{true}$

$v.\code{busy} \gets \code{true}$

$v.\code{busy} \gets \code{false}$

$parity \gets v.m$

$u \in v.\code{child}$
$parity \gets \text{XOR}(parity, u.st\_odd)$

FPGA-oriented controller logic
$\code{global\_stage} \gets \code{growing}$

$\code{global\_stage} \gets \code{merging}$

%Wait until all PEs are in Merging Stage

Wait 2 clock cycles

$\code{global\_stage} \gets \code{terminate}$

$\code{global\_stage} \gets \code{growing}$

Time Complexity
The worst-case time complexity of the FPGA design is $O(d^3)$ in contrast to $O(d^3log(d))$ of the generic distributed UF algorithm.
The $log(d)$ factor in the latter originates from the coordination overhead associated with transitioning between Merging and Checking stages.
However, in the case of FPGA implementation, these two stages—Merging and Checking—are performed concurrently, obviating stage transitions.
This concurrent operation effectively removes the $log(d)$ component.

§.§ Implementation details

We next list the other implementation choices of our design.

Since we only use a single FPGA and evaluate with $d$ up to 21, a single node controller suffices.
The node controller reads busy of each PE, every clock cycle to identify the completion of a stage.

Shared memory:
We implement all shared memories as FPGA registers, i.e., reg in Verilog.
FPGA registers by design guarantee that a read returns the last written value.
In order to ensure that the S4 memory has a single writer, we adjust the PE logic to update growth by implementing a modified compare-and-update operation (line:FPGA_comparenupdate) as shown in <ref>. The PE that houses the S3 memory performs this operation, increasing $e.\code{growth}$ by two when both endpoints of the edge have $v.odd$ set to true.

[language=Verilog, frame=single, basicstyle=]
reg growth;
always@(posedge clk)
if(stage == growing)
growth <= `MIN(growth
+ odd[0] + odd[1], w);

Circuit diagram of grow sub-module and Verilog implementation. This implements the  atomic compare and update operation in line:comparenupdate as part of the PE module. $odd[0]$ and $odd[1]$ represents the $odd$ state of the two incident PEs of the edge.

§.§ Resource Usage

On the VCU129 FPGA development board [18], we are able to support the distributed UF decoder with $d$ up to 21, due to resource limits. <ref> shows the resource usage for various $d$.
While the numbers of vertices and edges grow by $O(d^3)$, resource usage grows faster for the following reasons. First, resource usage by a PE grows due to the increase of bit-width required for $v.id$, and $v.cid$. A PE for $d=21$ with six adjacent PEs requires 200 LUTs and a similar PE for $d=5$ requires only 155 LUTs.
Second, PEs on the surface of the three-dimensional array as shown in <ref> use fewer resources than those inside because the latter have more incident edges. When $d$ increases a higher portion of PEs are inside the array.

We find that LUTs are the most critical resource in the FPGA for our design.
It may be possible to run a design with $d=29$ on a Xilinx VU19 FPGA [19], which currently has the highest number of LUTs among commercially available FPGAs at the time of this writing.
Potentially larger $d$ values can be supported by using a network of FPGAs.

Existing commercial FPGAs like VCU129 often dedicate a lot of silicon to digital signal processing (DSP) units and block RAMs (BRAMs).
However, our design does not use any DSPs because it only requires comparison operators and fixed point additions.
Our design does not use any BRAMs because all communication between PEs is shared memory based, which is implemented using registers.

Therefore, an ideal FPGA designed to run our distributed UF decoder would be simpler than current large FPGAs, as it would only need a large number of LUTs, no DSP units, and a limited amount of BRAM.

Resource usage of on VCU129 FPGA board for selected $d$

$d$     # of LUTs     # of registers

3             970         528
5             6425          2425

9             52111          13754

13             165718          47211
17             448314     122028
21             898715     238939

§ EVALUATION

The main objective of our evaluation is to assess the scalability of our distributed UF implementation. To that end, we first describe our methodology and then show that the latency of our implementation grows sub-linearly with respect to the surface code size $d$.

In addition, we also evaluate the impact of noise and non-identically distributed errors on latency.

§.§ Methodology

For speed, we measure the number of cycles required to decode a syndrome.
To evaluate correctness, we compare the results of our distributed UF decoder with the results from the original UF decoder.
We compare clusters because the original UF decoder and ours only differ in the clustering process.
In the rest of our evaluation, we will focus only on the speed of the distributed UF decoder and not on the accuracy of its results.

Experimental Setup
As our evaluation setup, we use Xilinx VCU129 FPGA development board [13], which is capable of decoding surface codes with $d$ up to 21.

We use a MicroBlaze soft processor core [20] instantiated inside the FPGA to generate the syndromes and transmit them to Helios, which runs on the same FPGA. We ran $10^6$ trials for each error rate and distance.

Noise Model
We use the phenomenological noise model [1] that accounts for errors in both data and ancilla qubits.
As decoding for X-errors and Z-errors are independent and identical, we only focus on decoding X-errors in the evaluation.

To emulate noise, we independently flip the two adjacent stabilizer measurements for each data qubit with a probability of $p$ (the physical error rate) in each measurement round, and we also independently flip each stabilizer measurement with a probability of $p$ except for the first and last measurement rounds.
This is a widely used approach by prior QEC decoders  [7, 9, 21].
We then generate the syndrome from the physical errors and provide it as input to our decoder.

For most of our experiments, we use as default $p=0.001$, like other works [7].
This value is reasonable for surface codes, as $p$ should be sufficiently below the threshold (at least ten times lower) to exponentially reduce errors.
We note that the UF decoder has a threshold of $p=0.024$, calculated by Delfosse and Nickerson [12].

§.§ Decoding Time

We experimentally show how the average time for decoding grows with the size of the surface code.
Additionally, we show the effect of noise on the average time.

Average time

Average decoding time scales sub-linearly with $d$. We measure the average decoding time for 3 different noise levels. (Left) The average decoding time. (Right) The average decoding time per measurement round. The average time per measurement round reducing continuously justifies that our decoder is scalable for large surface codes. We show the distributions separately in <ref>.

To demonstrate the scalability of our algorithm with respect to the size of the surface code, we plot the average time for decoding against the size of the surface code.
In <ref> (left) the y-axis shows the average decoding time in nanoseconds and the x-axis shows the distance ($d$) of the surface code.
We see that for all 3 physical error rates we tested, average decoding time grows sub-linearly with respect to the surface code size, which satisfies the scalability criteria to avoid an exponential backlog.
This implies that the average time to decode a measurement round reduces with increasing $d$ as shown in <ref> (right).

Distribution of decoding time

To understand the growth of decoding time with respect to the code distance, in <ref> we plot the distribution of decoding time for different code distances.
The y-axis shows the decoding time and the x-axis shows the distance ($d$) of the surface code.
The average cycle count is indicated with $\times$.

$T$'s distribution has a small mean & a long tail

$T$ grows with the physical error rate.

$T$ grows with the weight of the edges.

Distribution of decoding time ($T$) with the mean marked with $\times$. Each distribution includes $10^6$ data points. By default $d=13$, $p=0.001$ and is unweighted

The key factor determining the decoding time is the number of iterations of growing and merging the distributed UF decoder requires. The peaks in the probability distribution for each distance in <ref> correspond to the number of iterations. The variation around each peak is caused by the time required to sync $c\_id$ and calculate $odd$.  The number of iterations is related to the size of the largest cluster, which in turn correlates with the size of the longest error chain in the syndrome. As the size of the surface code increases, the probability of a longer error chain also increases, resulting in the probability distribution shifting to the right.

Furthermore, as seen in <ref>, the distribution for each surface code size is right-skewed. For example, for $d=13$, $90\%$ of trials required two iterations or fewer, which were completed within 250 ns. In the same test, $99.99\%$ of trials were completed within 370 ns. Only a very small number of error patterns require long decoding times, corresponding to syndromes with long error chains. Since such syndromes occur rarely and have poor decoding accuracy even if the decoding time is bounded, the impact on accuracy will be minimal.

Effect of physical error rate

To understand the effect of the physical error rate on decoding time, in <ref> we plot the distribution of latency for three different noise levels for $d=13$. The y-axis shows the latency and the x-axis shows the physical error rate.

As the noise level increases, the probability distribution of latency shifts to the right. This is caused by the increased probability of a longer error chain when the physical error rate increases, which in turn requires more iterations to decode. As a result, the average decoding time increases with the physical error rate.

§.§ Non-identically distributed errors

We next analyze the decoding process of a surface code with varying error probabilities for data and measurement qubits. While identically distributed errors are useful for evaluating the decoder's performance, practical implementation of surface codes may have different error probabilities for each qubit. To address this issue, each edge $i$ in the decoding graph is assigned a weight $w_i$ that ranges from 2 to $w_{max}$ and is proportional to $-log(p_i)$, where $p_i$ is the error probability corresponding to edge $i$. $w_{max}$ is a user-specified parameter indicating the resolution of error probabilities.

Noise model :
We assign random error probabilities from a standard normal distribution with a mean of $0.001$ and a standard deviation of $0.0005$.

<ref> shows that the average latency increases as $w_{max}$ increases. When the errors have a higher resolution, more iterations are required for each cluster, leading to an increase in latency. For the unweighted graph with $d=13$, the average decoding time per round of 15 ns  increases to 38 ns when $w_{max}$ increases to 16. Notably, all of these values are significantly faster than the rate of measurement. As a result, decoding non-identically distributed errors can be performed in real-time using distributed UF on Helios.

§.§ Comparison with related work

Our empirical results as shown in <ref> suggest that has a lower asymptotic complexity than any existing MWPM or UF implementation for which asymptotic complexities are available, e.g.,  [22, 12].

Indeed, the empirical results suggest that our decoder has a sub-linear time complexity: the decoding time per round decreases with the number of measurement rounds, which has never been achieved before.
This implies that can support arbitrarily large $d$ as the rate of decoding will always be faster than the rate of measurement.

Das et al [7] calculate an average latency for their AFS decoder based on memory access cycles and assuming a design running at 4 GHz.
As the number of memory access cycles grows quadratically with $d$, the average decoding time per measurement round of AFS grows $O(d^2)$.
Similarly, Ueno et al [10] estimate the decoding time of QECOOL from $d=5$ to $d=13$ based on SPICE-level simulations with a clock frequency of 5 GHz.
For the given range of $d$, the decoding time per measurement round increases quadratically with $d$.
In comparison, the decoding time of decreases per measurement round.

We should like to point out that AFS and QECOOL assume very high clock frequencies, which is key to their estimated low latency.
For example, for $d=11$, AFS and QECOOL respectively report latencies of 42 ns and 8.32 ns per measurement round.
, in contrast, requires 16.2 ns per measurement round with a 100 MHz clock.

To the best of our knowledge, LILLIPUT  [6] is the only hardware decoder in the literature that provides implementation-based results, for $d=5$.
The decoder has an average time of 21 ns per measurement round, which is slightly lower than that of for $d=5$, i.e., 24.5 ns.
However, as analyzed in <ref>, LILLIPUT is not scalable for $d>5$.
Our work, in contrast, has successfully demonstrated the implementation of a $d=21$ surface code on a VCU129 FPGA with 11.5 ns per measurement round.
The architecture of can potentially support larger $d$ using a larger FPGA, for example, $d=29$ for Xilinx VU19P [19], and even larger $d$ using a network of FPGAs.

Our decoder outperforms the two fastest software MWPM decoder, Sparse Blossom [8] and Fusion Blossom [11], by an order of magnitude. According to our evaluation, Sparse Blossom and Fusion Blossom take 160 ns and 295 ns per measurement round, respectively, for $d=13$ and $p=0.1\%$, using a single core of an M1 Max processor. In contrast, Helios achieves an average decoding time of 15 ns per measurement round under the same conditions, which is more than 60 times faster than the current state-of-the-art measurement rate [4].

§ RELATED WORK

High level idea of some decoders

Lazy decoder <cit.> : Corrects easily correctable errors, reducing the information going to the main decoder. Speedups of 10x for UF and 50x for MWPM.

Cryogenic grow decoder [9] : Implements a decoder similar to us(grow and merge) running in superonducting hardware which can decode in less than 400ns. This decoder however sacrifices accuracy for performance by greedily merging non-trivial measurements. In contrast we accurately reproduce the UF algorithm. Threshold 5

QECOOL [10] : Similar to  [9] deocdes at cryogenic levels using message passing between nodes.

There is a large body of literature on fast QEC decoding, e.g., [23, 24, 25, 26]. The most related are solutions that leverage parallel compute resources.

Fowler [22] describes a method for decoding at the rate of measurement ($O(d)$).
The proposed design divides the decoding graph among specialized hardware units arranged in a grid.
Each unit contains a subset of vertices and can independently decode error chains contained within it.
The design is based on the observation that large error patterns spanning multiple units are exponentially rare, so inter-unit communication is not frequently required.
It, however, paradoxically assumes that the number of vertices per unit is “sufficiently large” and  a unit can find an MWPM for its vertices within half the measurement time on average. Not surprisingly, to date, no implementation or empirical data have been reported for this work.
Our approach uses vertex-level parallelism and leverages the same observation that communication between distant vertices is infrequent.

NISQ+[9] and QECOOL[10] parallelize computation at the ancilla level, where all vertices in the decoding graph representing measurements of one ancilla are handled by a single compute unit.
This results in an increase in decoding time per measurement round as $d$ increases.
In contrast, we allocate a processing element per each vertex, which results in decreasing decoding time per measurement round with $d$ at the expense of the number of parallel units growing $O(d^3)$.

Furthermore, they both implement the same greedy decoding algorithm that has much lower accuracy than the UF decoder used in this work.
QECOOL has an accuracy that is approximately four orders of magnitude lower than that of a UF decoder [7] and NISQ+ ignores measurement errors further lowering its accuracy than QECOOL.

Skoric et al. [21], Tan et al. [27] and Wu [11] propose similar methods of using measurement round-level parallelism, in which a decoder waits for a large number of measurement rounds to be completed and then decodes multiple blocks of measurement rounds in parallel.
By using sufficient parallel resources these methods can achieve a rate of decoding faster than the rate of measurement.
However, the latency of such approaches grows with the number of measurement rounds the decoder needs to batch to achieve a throughput equal to the rate of measurement.
In contrast, our approach exploits vertex-level parallelism and completes the decoding of every $d$ round of measurements with an average latency that grows sublinearly with $d$.

Pipelining can be considered a special form of using compute resources in parallel, i.e., in different pipeline stages.

AFS [7] is a UF decoder architected in three pipeline stages.
The authors estimate the decoder will have a 42 ns latency for  $d=11$ surface code, which is $2.4$ times higher than what we report based on implementation and measurement.
The authors assume specialized hardware that is capable of running at 4 GHz and as a result, the decoding latency will be dominated by memory access.
However, no implementation or cycle-accurate simulation is known for this decoder.
Importantly, pipelining is limited in how much parallelism it can leverage: the number of pipeline stages.
In contrast, the parallelism  of our decoder grows along $d^3$, which enables us to achieve a sublinear average case latency.

LILLIPUT [6] is a three-stage look-up-table based decoder similar to AFS.  Look-up-table based decoders can achieve fast decoding but are not scalable beyond $d=5$ as the size of the look-up table grows $O(2^{d^3})$. For $d=7$ surface code with 7 measurement rounds, it would require a memory of $2^{168}$ Bytes, which is infeasible in any foreseeable future.

Sparse Blossom [8], a C++ MWPM implementation, decodes faster than the rate of measurement for $d=17$ on a single CPU core.
However, its decoding time per round grows linearly with $d$ and increases to a few micro-seconds when the noise level increases, making it impractical for real-time decoding for higher noise levels and large surface codes.
Fusion Blossom [11] takes a similar approach to Sparse Blossom and additionally parallelizes the computation at the measurement round level.
By allocating 100 measurement rounds to each core on a 64-core processor, Fusion Blossom can decode up to $d=33$ faster than the measurement rate.
However, both Fusion blossom and Sparse Blossom has a decoding time per round higher than that of by orders of magnitude, which limits their immediate use in quantum computing.

§.§ Multi-FPGA Systems

§.§.§ Non-quantum related applications

Multi-FPGA systems are primarily built for application specific acceleration when the workload can be parallelized or pipelined.
Catapult <cit.> by Microsoft and Argos massive-MIMO testbed <cit.> are two examples of large scale multi-FPGA systems.
Catapult <cit.> containing over 1000 FPGAs uses the tree structure of the existing data center network for connectivity and is used primarily for datacenter acceleration.
Argos architecture is a fat tree structure with daisy chained leaf nodes.
Similar to , Argos also performs computations in a distributed manner to achieve the tight latency requirements in the range of millisecond level needed for massive-MIMO communication.
In contrast, QEC has micro second level latency requirements.

Various other  multi-FPGA designs use torus  <cit.> or ring  <cit.> architectures to interconnect the FPGAs.
Above architectures are commonly used to accelerate machine learning based workloads such as artificial neural networks <cit.>.
As a neural network comprises different layers, individual layers can be mapped to one or more FPGAs making the task suitable for multi-FPGA implementation.

However all these architectures are primarily optimized for throughput and can tolerate higher levels of latency.
Therefore all these designs use gigabit-transceivers.
In contrast, QEC has a tighter latency budget and we use GPIO based interconnects to further reduce the latency.

§.§.§ Quantum Control and Error correction

Due to the tight latency requirements needed for controlling qubits, all existing Quantum computers
<cit.> employ multiple FPGAs.
Raytheon BBN <cit.> uses SATA cables to connect FPGAs together as a daisy chain of two level tree structure.
What is a daisy chain of two level tree structure?
and has a latency of around 200 ns between two directly connected FPGAs.
Their FPGAs are not synced to the same clock and the authors have pointed out that by syncing to the same reference clock, the latency can be reduced by further 100 ns.
What's your point when you describe the BBN system above?
Authors of  <cit.> have built a five qubit code using Raytheon BBN and shows that the latency between error detection and the correction pulse is 590 ns.
Can we write an expected value for our work here?Yes
In contrast our work targets surface code patches spanning hundreds of qubits and use a tree structure to minimize latency overheads.
In contrast to what?
Why don't you use the above as an example to learn how to decribe a related work?

QCCS <cit.> by Zurich Instruments is the most closely related: it employs a two-level tree structure of FPGAs interconnected using GPIO pins routed via the backplane and ARJ45 cables.
What is “the backplane and ARJ45 cables”?
Unlike , there is no separation of control from data paths. In PQSC, the latency between two directly connected FPGAs is 80ns, which is twice the latency of this work.
What is PQSC and how is it related to QCCS?
can also run on the QCCS platform with slightly increased latency.

The control system of Google Sycamore<cit.> also uses a similar architecture containing 36 FPGAs distributed across 4 chassis.
“similar architecture”? Also two-level tree?
The work however does not describe the communication architecture between the FPGAs.

§ CONCLUSION

We describe a distributed design for the Union Find decoder for quantum error-correcting surface codes, along with , a system architecture for its realization.
Our FPGA-based implementation of demonstrates empirically that the average decoding time grows sub-linearly with the $d$. Using a VCU129 FPGA, decodes distance 21 surface codes at an average speed of 11.5 ns per measurement round, the fastest to the best of our knowledge.
is faster and more scalable than any previously reported surface code decoder implementations.
Our results suggest that by leveraging parallel hardware resources, can avoid a growing backlog of measurements for arbitrarily large surface codes.

§ ACKNOWLEDGMENTS

This work was supported in part by Yale University and NSF MRI Award #2216030.

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# Gatemonium: A Voltage-Tunable Fluxonium

William M. Strickland  Bassel Heiba Elfeky  Lukas Baker  Andrea Maiani  Jaewoo
Lee  Ido Levy  Jacob Issokson  Andrei Vrajitoarea  Javad Shabani  Center for
Quantum Information Physics, Department of Physics, New York University, New
York 10003, USA

###### Abstract

We present a new fluxonium qubit design, gatemonium, based on an all
superconductor-semiconductor hybrid platform exhibiting gate voltage
tunability of $E_{J}$. We first show the principle of fluxonium operation in
epitaxial Al/InAs heterostructure where the single Josephson junction can be
controlled using gate voltage control, effectively tuning the weight of the
fictitious phase particle through the ratio of the Josephson energy $E_{J}$ to
the charging energy $E_{C}$. The spectroscopy of the qubit shows tunability
between plasmons to fluxons and their hybrid spectrum. We study two gatemonium
devices with different charging energies and extract inductance of InAs-based
Josephson junctions array. We also discuss future directions implementing a
gate voltage tunable superinductance.

##  I Introduction

Fluxonium qubits have become an incredibly promising alternative to the
conventional transmon for quantum computation using superconducting circuits
[1, 2, 3]. The fluxonium computational states have a suppressed transition
matrix element when biased to near half a flux quantum, maximizing energy
relaxation times [4, 5, 6]. First-order insensitivity to flux noise also
exists at the magnetic ”sweet spot”. Recently, coherence times exceeding 1 ms
[7] and two-qubit gate fidelities exceeding 99.9% have been shown with
fluxonium qubits [8, 9].

Fundamentally, the fluxonium qubit consists of a parallel Josephson junction,
capacitor, and linear inductor. The associated energies are related to
physical parameters in the circuit in the following way: the Josephson energy
$E_{J}=\Phi_{0}I_{C}/2\pi$ for a junction critical current $I_{C}$, the
charging energy $E_{C}=e^{2}/2C$ for a capacitance $C$, and the inductive
energy $E_{L}=(\hbar/2e)^{2}/L$ for an inductance $L$. The magnetic flux
quantum is $\Phi_{0}=h/2e$ with Planck’s constantant $h$ and the electron
charge $e$. The linear inductance is typically implemented by a high kinetic
inductance element, such as an array of Josephson junctions or a disordered
superconductor [10]. The resulting energy spectrum, and relevant qubit
properties such as frequency and anharmonicity, are uniquely defined by these
relative energy scales. For example, circuits with small $E_{L}$ lead to large
phase fluctuations and the energy levels become flat with respect to external
flux, suppressing flux noise dephasing. In contrast, circuits with large
$E_{J}/E_{C}$ have been shown to minimize the transition matrix element near
half flux, leading to an enhanced energy relaxation time. These orthogonal use
cases illustrate an important characteristic of fluxonium qubits that single
mode devices can only protect from dephasing or bit flip errors at once. In
analogy with the classical analogue of a mass in a corrugated potential, it is
useful to think of fluxonium qubits in terms of their “weight”, where the
“heavy” regime is where $E_{J}/E_{C}\gg 1$ and the “light” regime is where
$E_{J}/E_{C}\sim 1$. Alternatively in the light

It may be beneficial in some cases to in-situ tune between the heavy and light
regimes at will, requiring tunability of the energy scales. One such
implementation could be realized by placing a split junction instead of the
single junction, and a global magnetic field [4, 11] or a local flux lines,
which will involve calibrating for cross terms in the mutual inductance
matrix. Alternatively, gate-tunable semiconducting junctions could alleviate
cross-talk due to electric field confinement. In addition, they also can be
used to implement fast two qubit gates between fluxonia [6]. Earlier studies
in InAs nanowire showed tunable $E_{J}$ element in Ref. 12, however coherent
manipulation of the qubit states was not performed.

Figure 1:  $E_{J}$ tuning in the gatemonium qubit: (a) Wavefunctions of the
lowest levels in the gatemonium qubit in the heavy regime with $E_{J}$ = 17
GHz, $E_{L}$ = 2.8 GHz and $E_{C}$ = 0.8 GHz. The external applied flux is
$\Phi=0.48\Phi_{0}$. (b) Qubit frequencies and anharmonicities at zero and
half flux zero, and the anharmonicity $\alpha$ is maximized. As $E_{J}$
decreases (light regime), the spectrum becomes harmonic, as the anharmonicity
goes to zero, the qubit frequency becomes unchanged with flux, and the
frequency approaches $\sqrt{8E_{L}E_{C}}$. (c) Landscape of fluxonium devices
in terms of the relative capacitive, inductive and Josephson energies. The
large $E_{J}/E_{C}$ (heavy) regime where the transition matrix element is
highly suppressed maximizes $T_{1}$ times. Two gatemonium qubits studied in
this paper are also shown.

In this report we introduce a fluxonium-style qubit with voltage-tunable
$E_{J}$ named “gatemonium”, referring to the gatemon qubit, being a gate
voltage tunable transmon [13, 14, 15, 16, 17], shunted by a large inductance
typical in fluxonium. The Josephson junctions in both in the single junction
and, more notably, in the array are constructed from superconductor-
semiconductor (super-semi) hybrid planar junctions. We exploit the in-situ
$E_{J}$ control to tune between the heavy and light fluxonium regimes. We
utilize the tunable $E_{J}$ to manipulate the energy spectrum at will,
presented through one- and two-tone spectroscopy. We also report coherent
manipulation of the plasmon mode observed by Rabi oscillations, as well as
characterization of the $T_{1}$ energy relaxation.

##  II Simulations

The fluxonium Hamiltonian is

$\hat{H}=4E_{C}\hat{n}^{2}-E_{J}\cos(\hat{\phi}-2\pi\frac{\Phi}{\Phi_{0}})+\frac{E_{L}}{2}\left(\hat{\phi}\right)^{2},$

where the number of Cooper pairs $\hat{n}$ and superconducting phase
$\hat{\phi}$ form a pair of conjugated variables [18]. An external flux $\Phi$
applied through the loop tunes the relative depths of local minima. It is
often useful to think of the system’s classical analog, being a particle with
mass $1/8E_{C}$ and position $\varphi$ sitting in the bottom of a parabolic
potential corrugated by a cosine with amplitude $E_{J}$.

One example of the resulting wavefunctions in the phase basis is shown in Fig.
1(a) for $E_{J}/h$ = 12 GHz, $E_{L}/h$ = 2.80 GHz, and $E_{C}/h$ = 800 MHz.
The external flux $\Phi$ is set to $0.48\Phi_{0}$, close to the half flux
degeneracy. The wavefunctions are offset on the y-axis based on their relative
energies and labelled accordingly, with the ground state $|0\rangle$ (blue),
the first excited state $|1\rangle$ (orange), and so on. The potential energy
is shown (gray) with the barrier height between the lowest two wells being
$E_{J}$. One can notice two distinct transitions corresponding to plasmon
modes, with an energy $f_{02}=\sqrt{8E_{J}E_{C}}/h$, dictating transitions
within each well, and fluxon modes, dictating transitions between different
wells, with an energy of $f_{01}=2\pi E_{L}/h$.

The Josephson potential localizes wavefunctions to individual wells, and the
barrier height determines the suppression of the transition matrix element,
influencing energy relaxation times $T_{1}$ inversely through Fermi’s golden
rule. Also interesting is to consider the susceptibility to flux noise through
the derivative of the $|0\rangle$ to $|1\rangle$ transition frequency with
respect to flux $df_{01}/d\Phi$. Alternatively, in the “light” regime, where
$E_{L}\ll E_{J},E_{C}$, the qubit is less sensitive to flux, and hence more
protected from flux noise dephasing. This principle illustrates why it is
advantageous to work at the half flux sweet spot, since the qubit is first-
order insensitive to flux noise. A more detailed description of the error
protection properties of fluxonium can be found in Ref 19.

Relevant to qubit operation, we plot the qubit $f_{01}$ (blue) and
anharmonicity $\alpha$ (red) as a function of $E_{J}$ in Fig. 1(b) at zero
(dark color) and half (light color) flux. The results are obtained for
$E_{L}=$2.8\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$$ and
$E_{C}=$800\text{\,}\mathrm{M}\mathrm{H}\mathrm{z}$$. It can be seen that at
large $E_{J}$, the qubit frequency at half flux approaches very low values,
while the anharmonicity is very large and positive. As $E_{J}$ approaches zero
the qubit spectrum becomes harmonic, leading to a vanishing anharmonicity. In
addition, the qubit becomes less flux tunable, and the frequency approaches a
value set by $\sqrt{8E_{L}E_{C}}$.

To reiterate the importance of different fluxonium parameter regimes, we plot
the landscape of different fluxonium energy regimes in Fig 1(c), adapted from
Ref. 19. While it may be advantageous to be in the heavy regime for bit-flip
protection and the light, so-called “Blochnium” regime [20] for phase flip
protection, we show that with our gatemonium device we are able to tune the
ratio of $E_{J}/E_{C}$ by more than an order of magnitude connecting these two
regimes.

Device | $N_{JJ}$ |  $W_{C}($\text{\,}\mathrm{\SIUnitSymbolMicro}\mathrm{m}$$) |  $E_{L}$ (GHz) |  $E_{C}$ (MHz)
---|---|---|---|---
A | 600 | 75 | 2.80 | 800
B | 400 | 500 | 4.97 | 150
Table 1: Device parameters: Devices A, and B with the number of Josephson
junctions in the array $N_{JJ}$, the width of the capacitor $W_{C}$, the
inductive energy $E_{L}$, and the charging energy $E_{C}$. Figure 2:  Device
optical image and circuit diagram: False-colored optical image of the
gatemonium qubit is shown in (a) consisting of a shunt capacitor with charging
energy $E_{C}$ (purple), a planar Josephson junction with Josephson energy
$E_{J}$ (yellow), and a linear inductance, implemented in the form of a series
of planar Josephson junctions with inductive energy $E_{L}$ (blue). The inset
shows an equivalent circuit diagram. Input and output transmission lines are
inductively coupled to a readout resonator, which is capacitively coupled to
the gatemonium. A zoomed in scanning electron micrograph (SEM) is shown in (b)
of the Josephson junction array, with aluminum islands (blue) connected via
Josephson coupling through InAs weak-links (green). An SEM image of the single
junction before gate deposition is shown in (c) with aluminum leads (yellow)
separated by an InAs weak link (green) and the top gate shaded placement
(red). Figure 3: One- and two-tone spectroscopy One-tone spectra are shown
(a-c) of the transmission across a readout resonator $|S_{21}|$ as a function
of applied external magnetic flux $\Phi/\Phi_{0}$ at different gate voltages.
(a) The gatemonium is in the heavy regime with
$E_{J}=$12.0\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$$, and the dressed
resonator frequency tunes periodically with flux due to coupling with the
plasmon mode. Zooming in to the half flux (inset), one can see multiple
crossings with the qubit $f_{01}$ and $f_{02}$. (b) At
$E_{J}=$4\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$$, the fluxon and plasmon
modes become hybridized and we see $f_{02}$ cross with the readout resonator
near half flux. (c) For $E_{J}=$0.9\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$$
the detuning of the fluxonium mode with the resonator increases, leading to a
less pronounced flux dependence. Two-tone spectra are seen in (d-f). In the
heavy regime $E_{J}=$17.5\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$$ the plasmon
is weakly flux tunable and exhibits an avoided level crossing near half flux
with the fluxon mode. Zooming in to near half flux one can observe the
linearly dispersing fluxon mode, as well as the plasmon mode. (e) For $E_{J}$
= 4.8 GHz the fluxon and plasmon modes are hybridized with $f_{01}$ reaching
$1.5\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$ at half flux and
$6.2\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$ at zero flux. (f) As $E_{J}$
decreases, the gatemonium spectrum becomes harmonic and weakly flux tunable,
where $f_{01}$ is sinusoidal with flux and centered around a value of
$\sqrt{8E_{L}E_{C}}$.

##  III Device design and fabrication

In this report we discuss two devices, A, and B. Their parameters are shown in
Table 1. We show a false-color optical image of Device A in Fig. 2(a) with the
capacitor in purple, the single junction in yellow, the array inductor in
blue, the readout resonator in orange, and the gate in red. The equivalent
circuit diagram shown in the inset. The array is implemented in the form of
600 planar Josephson junctions in series, where a false-color scanning
electron micrograph (SEM) of a nominally identical device is shown in Fig.
2(b). Al islands (blue) 1$\times$5
$\text{\,}\mathrm{\SIUnitSymbolMicro}\mathrm{m}$2 in size are connected
through InAs weak links (green). A false color SEM of the single junction is
shown in Fig. 1(c) before gate deposition, with Al leads in yellow and the
InAs region in green. The top gate electrode used to tune $E_{J}$, shown
schematically in red. The qubit is capacitively coupled to a readout resonator
with a coupling strength of
$g/2\pi=$150\text{\,}\mathrm{M}\mathrm{H}\mathrm{z}$$ as measured from the
minimum detuning of the vacuum Rabi splitting [21]. The readout resonator is a
$\lambda/4$ coplanar waveguide resonators and has internal quality factors of
$5.5\text{\times}{10}^{3}\text{\,}$ measured at low power with the qubit far
detuned, consistent with previous devices that underwent similar device
fabrication [22]. The external quality factor was found to be
$3.8\text{\times}{10}^{3}\text{\,}$ and the frequency was found to be $f_{r}$
= $7.4\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$, leading to a coupling rate to
the feedline of $\kappa/2\pi=$1.8\text{\,}\mathrm{M}\mathrm{H}\mathrm{z}$$.
Readout resonators are inductively coupled to a common feedline. We measure
the complex transmission across the feedline $S_{21}$, as a function of probe
frequency $f_{\mathrm{probe}}$. Not pictured is an external charge line is
coupled to the qubit capacitor. This line and the gate are both used to drive
qubit transitions.

The device chip is mounted in a BeCu sample holder and shielded by aluminum
and mu metal cans. Transmission lines on the chip are bonded to a printed
circuit board using Al wirebonds. The package is mounted at the mixing chamber
plate of a Oxford Instruments Triton, a cryogen-free dilution refrigerator,
with a base temperature of $12\text{\,}\mathrm{m}\mathrm{K}$. Using a coil on
the back of the sample holder we apply a global external magnetic flux through
the loop $\Phi$. A schematic of the wiring is shown in Appendix B.

##  IV Resonator and qubit spectroscopy

In this section we present qubit spectroscopy at different $E_{J}$ values,
representing the light, middle and heavy regimes. The Josephson energy
increases with gate voltage nonmonotonically, which we describe in detail in
Appendix C. First in the heavy regime, with $E_{J}$ = 12 GHz, we measure
$|S_{21}|$ across the readout resonator for $f_{\mathrm{probe}}$ near the
readout resonator frequency. We find that as a function of flux, the resonator
is weakly tuned with flux. This is due mainly to the plasmon modes of the
qubit, as we will see in two tone spectroscopy, dressing the resonator
frequency due to dispersive coupling. Upon zooming in to $\Phi=\Phi_{0}/2$,
one finds multiple avoided crossings of the resonator, being the qubit
$f_{01}$ and $f_{02}$ modes, shown as orange and pink dashed lines
respectively, for $E_{J}=$12.0\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$$,
$E_{L}=$2.80\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$$ and $E_{C}$ = 800 MHz.

As the gate voltage decreases, $E_{J}$ decreases to 4.0 GHz. The resonator now
anticrosses with the $f_{02}$ mode, shown in Fig. 3(b). The consistency of the
fit with the data for different $E_{J}$ values but fixed $E_{L}$ and $E_{C}$
verify that changes in the observed spectra are purely from the gate voltage
changing $E_{J}$. We then tune to the light regime with $E_{J}$ = 0.9 GHz,
where the resonator is now very weakly flux tunable, shown in Fig. 3(c).

The qubit response as a function of flux and gate voltage is directly measured
through two-tone spectroscopy. We apply a drive tone of varying frequency
$f_{\mathrm{drive}}$ and utilize dispersive readout to measure the qubit
response. First in the heavy regime with $E_{J}$ = 17.5 GHz, at zero flux the
qubit frequency is seen to be around 9.2 GHz and is tuned down to 8.7 GHz with
flux, as shown in Fig. 3(d). At zero flux we know the lowest energy fluxonium
mode should be a plasmon mode. Near $\Phi=0.40\Phi_{0}$, one can see this mode
then anticrosses with the fluxon mode, and the fluxon mode continues to
disperse linearly with flux towards low frequency at $\Phi_{0}/2$. It should
be noted that both the slope of this linearly dispersing fluxon mode, and the
coupling between the fluxon and the plasmon mode depends on the ratio of
$E_{J}/E_{L}$. The qubit frequency at half flux in this regime reaches as low
as $f_{01}$ = 75 MHz inferred from the fit.

We then tune to the middle regime, with $E_{J}$ = 4.8 GHz in Fig. 3(e). One
can notice that now the plasmon mode at zero flux is at 6.2 GHz, and tunes
down to 1.5 GHz with flux. The $|0\rangle$ to $|2\rangle$ transition can be
seen to cross with the readout resonator at 7.4 GHz, which yields a one tone
response similar to what was observed in Fig. 1(b). The plasmon and the fluxon
modes in the middle regime are much more strongly coupled as compared to those
in the heavy regime. $E_{J}$ is then decreased to 0.9 GHz, where the qubit
response to flux is nearly sinusoidal, centered around a frequency of $4.23$
GHz. Here the frequency is entirely dominated by $E_{L}$ and $E_{C}$ for very
small $E_{J}$, and the spectrum is purely harmonic with a lowest transition
frequency equal to $\sqrt{8E_{L}E_{C}}$.

Figure 4: Time domain Measurement in Plasmon Regime: Rabi oscillations as a
function of drive frequency and drive power are shown in (a) and (b)
respectively. A fit to the decaying sinusoid is shown in the inset yielding
$T_{2}^{\mathrm{Rabi}}$ = 70 ns. $E_{J}$ is 6.5 GHz.

##  V Plasmon time domain characterization

We employ homodyne detection of the qubit state in a variety of pulsed
measurements on Device B. The qubit gate voltage is such that we are in the
heavy regime with $E_{J}$ = 30 GHz. Looking at the spectrum near zero flux,
the lowest energy transition corresponds to a plasmon transition. $E_{J}$ at
this point is 6.5 GHz.

We apply a short square pulse near the qubit frequency with a width of
$\tau_{\mathrm{Rabi}}$ while applying a weak continuous readout. We find that
as a function of the pulse width, the homodyne detection voltage $V_{H}$
oscillates, corresponding to Rabi oscillations. We see the Rabi frequency
change as a function of drive detuning from the qubit frequency, being 6.5 GHz
in Fig. 4(a). The inset shows a linecut fit to a decaying sinusoid, revealing
the coherence time associated with the Rabi manipulation, being about 66 ns.
We also find the Rabi frequency decrease as we decrease the drive power as
shown in Fig. 4(b). We use this measurement to calibrate the width of a $\pi$
pulse, which drive the qubit from the $|0\rangle$ to the $|1\rangle$ state. We
then perform a $T_{1}$ measurement and find a $T_{1}=90$ ns. This is
consistent with gatemon $T_{1}$ times measured on using a similar fabrication
procedure [17].

We note that in Device B we could not couple to the fluxon modes due to the
much smaller $E_{C}$. It could be possible to utilize a Raman driving
procedure as used in Ref. 5 to couple to the fluxon modes in the heavy regime.
We hope to measure the coherence properties of the fluxon modes in the
gatemonium qubit in a future experiment. In the future it would be worthwhile
to investigate the effect of quasiparticle and phase slip processes of
gatemonium dephasing [23] as well as gate-tuning the Josephson junction array
as well.

##  VI Conclusion

We present an introduction to the gatemonium qubit, along with a detailed
analysis of the qubit spectra at different $E_{J}$ regimes as a function of
flux. The qubit $E_{J}$ is tunable over an order of magnitude, accessing the
light and heavy fluxonium regimes. The inductor was acheived using 600 super-
semi Josephson junctions in series for a
$1\text{\,}\mathrm{\SIUnitSymbolMicro}\mathrm{H}$ inductance. We find the
array of superconductor-semiconductor junctions can be treated as a linear
inductor through a good fit to the data. We measured coherence times from Rabi
oscillations and a $T_{1}$ measurement of the plasmon mode in the heavy regime
and found it corresponds very closely to what has been observed in the past
for gatemon qubits on this platform.

We believe this is an exciting first step to making fluxonium-style qubits on
this material platform. There has been increased interest in using different
types of junction array materials which can lead to higher Josephson plasma
frequencies, possibly for higher operating temperatures and for achieving
larger inductances. While the junction leads in conventional superconductor-
insulator-superconductor junctions effectively form a parallel plate
capacitor, the junction leads in an superconductor junction form a coplanar
capacitor, yielding a reduced Josephson capacitance $C_{J}$ and increases the
Josephson plasma frequency $\omega_{p}=1/\sqrt{L_{J}C_{J}}$ for $L_{J}$ the
Josephson inductance. Since the maximum operating frequency of the array is
enhanced, one can imagine operating qubits at higher temperatures based on
these materials. In addition, the number of Josephson junctions in the array
can be enhanced, since the maximum number of junctions in the array is bounded
from above by the square root of the ratio of $C_{J}$ to the capacitance of
each island to ground $C_{G}$, where both are on the order of 1 fF, as opposed
to conventional superconductor-insulator-superconductor junctions, which
commonly have $C_{J}$ more than 10 fF. In addition, the semiconductor weak-
links in the array can possibly give rise to a voltage tunable superinductance
[24]. For these reasons, a Josephson junction array based on superconductor-
semiconductor hybrid materials may be useful for superconducting qubits,
amplifiers [25], couplers [26, 27, 28, 29] and metamaterials [30] in the
future.

##  VII Acknowledgements

We thank Andrew Higginbottham, Shayam Shankar, Archana Kamal, Maxim Vavilov,
Vlad Manucharyan, Srivatsan Chakram, Peter Schüffelgen, and Charlie Tahan for
fruitful conversations. We acknowledge support from the Army Research Office
agreement W911NF2110303. W.M.S. acknowledges funding from the ARO/LPS QuaCR
Graduate Fellowship. The authors acknowledge MIT Lincoln Laboratory and IARPA
for providing the TWPA used in this work. We also acknowledge MIT LL SQUIL
Foundry for providing qubits that provided insight for calibration of the
fridge thermalization steps.

Figure 5:  Dilution refrigerator wiring diagram

## Appendix A: Materials Growth and Fabrication

The device is based on an InAs 2DEG grown by molecular beam epitaxy capped
with an aluminum layer in-situ. Details of the growth procedure can be found
in Refs. 31, 32, 33. The structure is grown on a semi-insulating, Fe-doped,
$500\text{\,}\mathrm{\SIUnitSymbolMicro}\mathrm{m}$ thick, $2\text{\,}$-inch
diameter, single-side polished InP wafer (AXT Inc.). The oxide is thermally
desorbed under an arsenic overpressure in an ultrahigh vacuum chamber. A
superlattice and graded buffer layer are grown in order to minimize
compressive strain on the active region. The quantum well is formed by a
$4\text{\,}\mathrm{n}\mathrm{m}$ bottom In0.81Ga0.19As barrier, a
$4\text{\,}\mathrm{n}\mathrm{m}$ InAs layer, and a
$10\text{\,}\mathrm{n}\mathrm{m}$ In0.81Ga0.19As top barrier. The wafer is
delta-doped with Si $6\text{\,}\mathrm{n}\mathrm{m}$ below the active region.
The wafer is then cooled to below
$0\text{\,}\mathrm{\SIUnitSymbolDegree}\mathrm{C}$ for the deposition of a
$30\text{\,}\mathrm{n}\mathrm{m}$ thick Al layer, measured by atomic force
microscopy.

The device is fabricated using standard electron beam lithography using
polymethyl methacrylate resist. There are three lithography layers. We first
dice a $7\times$7\text{\,}\mathrm{m}\mathrm{m}^{2}$$ piece of the wafer and
clean successively in dioxolane and isopropyl alcohol. We then define the
microwave circuit and perform a wet chemical etch of the Al and III-V layers
using Transene Type D and a solution of phosphoric acid, hydrogen peroxide,
and deionized water in a volumetric ratio of 1:1:40 respectively. We then
define the Josephson junction by etching a narrow strip in the aluminum layer,
defining two superconducting leads of the Josephson junction separated by
$100\text{\,}\mathrm{n}\mathrm{m}$. We deposit a
$40\text{\,}\mathrm{n}\mathrm{m}$ thick layer of AlOx at
$40\text{\,}\mathrm{\SIUnitSymbolDegree}\mathrm{C}$ by atomic layer
deposition, followed by a $100\text{\,}\mathrm{n}\mathrm{m}$ thick layer of Al
to serve as the top gate to control $E_{J}$. The top gate is defined in a
liftoff step after a sputter deposition of 100 nm of Al.

Figure 6:  Gate voltage tuning of $E_{J}$: (a) The top gate voltage $V_{G}$
tunes the critical current in the Josephson junction, forcing the qubit mode
to undergo an avoided level crossing with the readout resonator. (b) Two tone
spectroscopy revels the qubit $f_{01}$ mode as a function of gate voltage. (c)
We extract $f_{01}$ as a function of gate voltage from the data, and compare
this to simulations of the expected $E_{J}$ for a given $f_{01}$ to map these
values to $E_{J}$.

## Appendix B: Wiring

The chip is mounted on thin copper sample holders and placed in a printed
circuit board (PCB). Transmission lines on the chip are connected to
waveguides on the PCB by aluminum wirebonds. A gold plated Be/Cu cavity with
resonances above 10 GHz encloses the chip, and an Al shield encloses the
sample. Magnetic field is provided by a coil within the Al shield.

The sample is mounted on a cold finger attached to the mixing chamber plate of
a cryogen-free dilution refrigerator with a base temperature of 15 mK. Input
and output lines are connected by copper coaxial cables with SMA connectors.
The input rf signal across the common feedline is attenuated by -76 dB from
room temperature to base temperature. Drive signals are attenuated by -56 dB.
At the mixing chamber plate, the incoming rf signal passes through an Eccosorb
filter and a K&L filter with a DC to 12 GHz pass band. The outgoing signal is
passed through another eccosorb filter and K&L filter, then to two isolators
and a directional coupler before being amplified by a travelling wave
parametric amplifier. The tone used to pump the amplifier is attenuated by -39
dB. The signal is then further amplified by a low noise amplifier at 4 K, and
then amplified and filtered at room temperature. DC signals are supplied by a
voltage source at room temperature and low pass filtered at the mixing chamber
plate. DC and RF are combined by bias tees at base temperature.

We use a vector network analyzer in order to measure one and tone spectroscopy
data. Signal generators are used to supply a continuous wave signal to drive
the qubit for both two tone spectroscopy and for time domain measurements. For
time domain measurements, readout and drive continuous wave signals are mixed
with the output of an arbitrary waveform generator (AWG) using double balanced
mixers. The AWG has a sampling rate of 1 GSa/s. The readout signal is split by
a power divider and supplied to the local oscillator port of an IQ mixer, and
the outgoing, amplified signal is sent to the RF port, where I and Q
quadratures are then recorded using a digitizer with a sampling rate of 500
MSa/s. A schematic of the wiring is shown in Fig. 6.

## Appendix C: Gate voltage tuning of the Josephson energy

The Fermi level in an InAs layer is biased by a gate voltage, tuning the
occupation of current carrying Andreev bound states [34]. The inductance and
qubit frequency are then sensitive to applied gate voltage: for decreasing
gate voltage, the critical current decreases, the inductance increases, and
the qubit frequency decreases.

We show single and two tone spectroscopy as a function of gate voltage in Fig.
5. We see that as the gate voltage is tuned to negative values, the resonator
exhibits an avoided level crossing with the qubit. The minimum detuning of
these two modes yields twice the coupling strength.

In the same gate voltage range we conduct two tone spectroscopy. We find that
for a junction near depletion the qubit undergoes mesoscopic conductance
fluctuations, leading to a nonmonotonic behavior with gate voltage [35, 36].
The plasmon frequency as a function of gate voltage is seen to tune between
9.5 GHz and 5 GHz from -8.5 to -9.4 V. Extracting the qubit frequency from the
two tone data allows us to determine $E_{J}$ as a function of gate voltage. At
zero flux, we are able to calculate the expected $f_{01}$ and match this with
our measured data in order to map the measured qubit frequency to an $E_{J}$
value. We note that due to the coupling of the plasmon and fluxon modes, this
does not follow the conventional plasmon frequency $\sqrt{8E_{J}E_{C}}$.

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