# Wedge-type engineered analog SiOx/Cu/SiOx-Memristive Devices for
Neuromorphic Applications

###### Abstract

This study presents a comprehensive examination of the development of
TiN/SiOx/Cu/SiOx/TiN memristive devices, engineered for neuromorphic
applications using a wedge-type deposition technique and Monte Carlo
simulations. Identifying critical parameters for the desired device
characteristics can be challenging with conventional trial-and-error
approaches, which often obscure the effects of varying layer compositions. By
employing an off-center thermal evaporation method, we created a thickness
gradient of SiOx and Cu on a 4-inch wafer, facilitating detailed resistance
map analysis through semiautomatic measurements. This allows to investigate in
detail the influence of layer composition and thickness on single wafers, thus
keeping every other process condition constant. Combining experimental data
with simulations provides a precise understanding of the layer thickness
distribution and its impact on device performance. Optimizing the SiOx layers
to be below 12.5 nm, coupled with a discontinuous Cu layer with a nominal
thickness lower than 0.6 nm, exhibits analog switching properties with an
Ron/Roff ratio of $>$100, suitable for neuromorphic applications, whereas R
$\times$ A analysis shows no clear signs of filamentary switching. Our
findings highlight the significant role of carefully choosing the SiOx and Cu
thickness in determining the switching behavior and provide insights that
could lead to the more systematic development of high-performance analog
switching components for bio-inspired computing systems.

###### keywords:

SiOx, wedge-type deposition, analog memristive devices, resistive switching

Rouven Lamprecht* Luca Vialetto Tobias Gergs Finn Zahari Richard Marquardt Jan
Trieschmann Hermann Kohlstedt*

R. Lamprecht, R. Marquardt, F. Zahari, H. Kohlstedt
Nanoelectronics, Faculty of Engineering, Kiel University, 24143 Kiel, Germany.
Email Address<EMAIL_ADDRESS><EMAIL_ADDRESS>
H. Kohlstedt
Kiel Nano, Surface and Interface Science KiNSIS, Kiel University, 24118 Kiel,
Germany.
L. Vialetto
Department of Aeronautics and Astronautics, Stanford University, Stanford, CA
94305, USA
T. Gergs, J. Trieschmann
Theoretical Electrical Engineering, Faculty of Engineering, Kiel University,
Germany.

##  1 Introduction

The persistent drive for innovation in the electronics industry has led to an
exponential rise in semiconductor component integration in recent decades,
significantly influenced by advancements in miniaturization and performance
optimization for over fifty years [1, 2, 3]. The rising power demands of
contemporary Information Technology (IT), especially artificial intelligence
(AI)-driven applications in smart grids and the automotive sector, challenge
current CMOS technologies [4]. Bioinspired computing paradigms emerge as a
potential solution to these challenges, encompassing smart sensors to
neuromorphic computing architectures, offering promising long-term prospects
[5, 6]. Memristive devices, emerging as a pivotal component in neuromorphic
computing, have garnered substantial attention in recent years offering the
potential to revolutionize memory storage by enabling in-memory computing as
these devices are mirroring the functionality of biological synapses [7, 8].
These are often realised as two terminal devices in a simple metal-insulator-
metal (MIM) sandwich structure which can change its resistance based on the
history of the applied voltage and current [9]. Although the precise
mechanisms underlying their switching behavior are often not completely
understood, memristive devices can generally be classified based on the type
of mobile species within their switching layer [10]. Valence change memory
(VCM) devices are mostly anion-based devices, whose resistance is changed due
to the migration of corresponding anions (e.g., oxygen) [11]. Electrochemical
metallization (ECM) cells consist of an electrochemically active electrode and
an inert counter-electrode. The application of a voltage across them induces
an electric field, which drives the migration of the mobile species,
accompanying structural changes in the electrolyte. Eventually, conducting
channels (filaments) form, which cause corresponding changes in resistance
[11, 12, 13]. Whereas these filamentary type memristive devices can fulfill
the requirements of binary switching, analog-type components have the benefit
of multilevel switching mimicking synaptic functions [14]. These analog-
switching memristors are gaining prominence in neuromorphic computing due to
their dynamic reconfiguration capabilities, enabling the emulation of
essential synaptic and neuronal functionalities. They facilitate precise
weight modulation, essential for simulating key synaptic functions such as
long-term potentiation, depression, and paired-pulse facilitation, enhancing
the bio-realism and computational efficiency of neuromorphic systems [15, 16].
These devices can be utilized effectively as edge and terminal elements in
artificial neural networks, playing a pivotal role in high-performance,
memristor-based neuromorphic systems and the development of hardware deep
neural networks [17]. Despite the rise of alternative high-k dielectrics, such
as HfO2, SiO2 remains the basic building block of CMOS-technology and thus
silicon (di-)oxide and nitride-based memristors are still the subject of
intensive studies in the field of their memristive properties due to their
accessibility and simplified integration into existing production lines [18,
19]. SiO2-based memristors typically operate with SiO2 serving merely as an
electrolyte to facilitate ion migration in ECM cells [20, 21, 22, 23, 24]. The
utilization of copper in SiO2-based memristors, mainly as an active electrode
material, leverages its high electrical conductivity, excellent ionization
capability, and reversibility. This enables the engineering of high-performing
(filamentary) devices for bipolar switching [25, 26]. However, coppers high
diffusibility into the surrounding Si-based environment is undesirable in CMOS
technology due to the risk of contamination and degradation of the
semiconductor properties, making the use of copper as an electrode material
unappealing. Despite this, the controlled integration of copper in SiOx-based
memristors holds significant potential for advancing memristor technology.
Research has pivoted towards using sub-stoichiometric a-SiOx as an active
layer, which offers improved control over the switching properties, even
without the usage of metal cation migration [27, 28, 29, 30, 31]. Engineering
memristive devices for specific computational frameworks, such as neuromorphic
computing, presents significant challenges. These challenges involve the
meticulous selection of materials [32] and geometrical parameters like layer
thicknesses and active area dimensions, which drastically affect the electric
field strength and current density promoting ion diffusion and thus switching
characteristics [33, 34]. Despite the often limited understanding of these
parameters’ effects, their precise relation to device performance is crucial
for reliability [35, 36] and a systematic approach by wedge-like deposition
has shown to be a promising method to get insight into geometrical effects
[37, 38]. Systematic explorations alongside advancing device technology is
essential for successful development. Experimental efforts can be complemented
by computer-aided simulations. For example, kinetic Monte Carlo (KMC)
simulations may be used to determine spatially resolved film thickness for the
thermal evaporation of relevant material (e.g., SiOx, Cu), offering precise
control and insights into atomistic processes like adsorption and diffusion
[39]. Additionally KMC simulations capability in achieving uniform film
thickness in multi-source thermal evaporation, highlighting its effectiveness
in film uniformity control has been shown previously [40]. The aim of this
work is to establish correlations between the layers thicknesses and the
switching behavior of (analog) switching memristors as well as material
composition. Experimentally measured resistance maps are compared to the
outcome of MC deposition simulations to determine critical layer thicknesses
for obtaining analog-type switching devices. We present a comprehensive
investigation of the engineering process, characteristics and simulations of
memristive device fabrication based on the insertion of copper into silicon
oxide, shedding light on their potential in non-volatile memory and computing
technologies as analog non-volatile memory elements in novel computing
technologies such as neuromorphic computing.

##  2 Methods

###  2.1 Device Fabrication

A specialized thermal evaporation setup was constructed to facilitate wedge-
type deposition via off-center thermal evaporation. The setup can be seen in
Fig. 1 a). The first crucible (C1) is centered under the substrate with a
substrate to crucible distance of h = 210 mm to ensure an as evenly as
possible distributed deposition. The second crucible (C2) is located 60 mm
off-center, which leads to a non-uniform distribution of the evaporated
material across the substrate, resulting in a thickness gradient of deposited
films (wedge). In this work, two setups were used: Setup A: C1 = Cu and C2 =
SiO, resulting in a SiO-wedge; Setup B: C1 = SiO in and C2 = Cu, resulting in
a Cu-wedge.

Figure 1: a) Thermal evaporation system with 2 crucible configuration for off-
center wedge-type deposition. Dimensions: w = 60 mm, h = 210 mm, crucible
size: 30 mm $\times$ 10 mm. b) Device structure of the TiN/SiOx/Cu/SiOx/TiN
memristive devices containing a Cu-island layer sandwiched between SiOx.

The devices were fabricated on 4-inch Si wafers with 400 nm SiO2 (thermally
oxidized) on top, patterned using optical lithography processes. The wafers
are divided into 232 1 $\times$ 1 mm2 cells across the wafer, each containing
23 subcells with six different device areas (A), ranging from 100 to 2500
$\mu$m2, as shown in previous works [41, 42, 43]. The titanium nitride (TiN)
electrodes were deposited in a magnetron sputtering system from a titanium
(Ti)-target in a reactive process atmosphere at a power of 200 W with a gas
flow of 16 sccm N2 and 8 sccm Ar at 1.02 $\cdot$ 10-2 mbar process pressure
and a background pressure of $\sim$ 3 $\cdot$ 10-7 mbar. After the bottom
electrode (BE) deposition, the respective wafer was immediately transferred to
the evaporation system with shortest possible exposure time to the atmosphere.
The switching layer of the devices consisting of silicon oxide (SiOx) and
copper (Cu), was then fabricated via thermal evaporation in the previously
introduced dual crucible configuration. SiOx is evaporated using silicon
monoxide (SiO) granulate from Umicore at a base pressure of 3.2 $\cdot$ 10-6
mbar and a deposition rate of 0.3 Å/s (setup A) and 0.5 Å/s (setup B),
respectively. The discontinuous copper layer in between the SiOx is deposited
at a rate of 0.3 Å/s for both setups. The deposition is controlled by a
thickness monitor containing a gold sensor crystal of Maxtek in a Univex 300
System with an AS 053 high current source of Leybold. The top electrode (TE)
was deposited via magnetron sputtering and structured via lift-off processing
after transferring the wafer back to the sputter system in the shortest
possible time. The device structure is sketched in Fig. 1 b). After device
structuring the samples were encapsulated with 400 nm SiO by thermal
evaporation. A metallization layer (100 nm Ti / 10 nm Au) was subsequently
deposited to enable contacting the devices via contact pads with a semi-
automatic wafer probe station.

###  2.2 Electrical Measurements

The current-voltage measurements ($I$-$V$ characteristics) were carried out
with a semiautomatic measurement system to characterize the SiOx/Cu/SiOx
devices on 4”-wafers. The measurements were made with an HP 4156A parameter
analyzer. The voltage was applied to the top electrode while the bottom
electrode was grounded. During the $I$-$V$ characteristic measurements, the
voltage was swept from 0 V to a positive maximum (forward sweep), then
gradually decreased to a negative maximum, and finally returned to 0 V. For
comparability - if not explicitly described otherwise - the shown measurements
were performed at an electrode size of $A$ = 1225 $\mu$m2. Resistance
wafermaps were measured by calculating the resistance value of one device per
cell using Ohm’s law at a defined voltage (i.e., 0.4 V) in the forward sweep
to illustrate differences in the pristine resistance values. The influence of
a statistical deviation on the underlying $I$-$V$ characteristics was
mitigated by considering mean values, thereby accounting for and reducing the
impact of variability across individual cells. No compliance current or
electro-forming step was needed before or during the measurements.

###  2.3 Material Analysis

The thickness was measured by atomic force microscopy (AFM) measurements with
a SPM SmartSPM‐1000 from AIST-NT. For this, the material was deposited on a
0.25 cm2 Si/SiO2 (400 nm) sample structured by photolithography and a lift-off
step. Non-contact mode measurements were carried out to get information about
the step height of the deposited structure for five positions across the
wafer, 20 mm apart from each other. Since Cu layer thicknesses below 1 nm may
not result in a continuous film, the investigated layers were produced with 20
times the intended deposition time. The resulting thicknesses were then scaled
down proportionally to reflect the actual deposition time used for the
analyzed devices. SiOx thickness measurements were carried out under the same
conditions as in the device fabrication.

###  2.4 Simulation

To disentangle the correlation of deposition parameters and resistive
switching behavior, Monte Carlo simulations of transport and thin film growth
have been performed. Conceptually similar to the approach by Chen et al. [40],
MC transport simulations of evaporated SiO and Cu have been carried out. In
this study, we utilize a reduced variant of an in-house PIC-DSMC plasma
simulation based on the OpenFOAM framework, as described in detail elsewhere
[44, 45, 46, 47]. 3D transport simulations are conducted on an unstructured
mesh depicting the geometry shown in Fig. 1 a). The transport was assumed to
proceed without collisions, so that the simulations resemble a ray tracing
algorithm. The basic scheme was set up as follows: Initially the evaporated
flux $\Gamma$ is estimated from the maximum layer thickness measured over the
wafer. This estimation was iteratively corrected in a few trial runs. Using
the specified flux, the number of simulator particles to be inserted per time
step $\Delta t=0.01\,\mu\text{s}$ was determined. A uniform distribution over
the crucible with area $A=360\,\text{ mm}^{2}$ was assumed. Each simulator
particle represented $w_{\text{sp}}$ physical particles. The locations where
the simulator particles were inserted were randomly distributed over the
crucible following a uniform distribution. Their speed was sampled from a
Maxwell-Boltzmann energy distribution assuming a surface temperature of
$T_{s}=1100\,\text{ K}$, whereas their angular distribution followed a cosine
law [48, 49]. When simulator particles reached the substrate, for each face of
the mesh, the surface evolution is tracked through the surface coverage
fractions $\theta_{i}$ and the accumulation of material $a_{i}$ on the surface
was accounted for. [50]. As an output of the reactor scale model, the
accumulated fluxes of particles were obtained. The corresponding film
thickness is approximated by $t_{i}=a_{i}m_{i}/\rho_{i}$, with mass density
$\rho_{i}$ and atomic/molecular mass $m_{i}$. All relevant physical quantities
and parameters are collected in the Appendix table 1 [51, 52].

##  3 Results

In this section, we compare experimental data with simulated outcomes to
evaluate the accuracy of Monte-Carlo simulations in predicting layer thickness
and material properties during memristive device fabrication at the wafer
level. The experimental and simulated results are analyzed for two key
parameters: layer thickness, resistivity. Furthermore analysis of the distinct
devices on the wafer map examines the impact of varying layer thicknesses and
sputter parameters on the production of devices exhibiting a wide range of
characteristics.

###  3.1 SiOx wedge

The wedge-type (off-center) deposition of the SiO granulate provides a SiOx
layer thickness (t${}_{\mathrm{SiO}_{x}}$) ranging from 11 nm at the center to
19 nm at the edge of the wafer. When thermally evaporating from the centrally
arranged copper crucible, however, there is only a nominal range of 0.7 to
0.85 nm. Both of which agree well with the outcome of Monte-Carlo simulations,
which describe the statistical distribution of deposited SiOx (Fig. 2 b)) and
Cu particles Fig. 2 d)). The experimental and simulated values along the
$x$-axis are shown in Fig. 2 c). Due to the low Cu thickness, it is unlikely
that a complete film is grown and island formation is assumed to dominate [53,
54, 55]. To assess the influence of the thickness-gradient on the switching
characteristics of the devices, resistance values at 0.4 V are considered –
well below the device-specific switching threshold. The results are shown in
Fig. 2 a). The resistance distribution resembles the SiOx thickness
distribution without an obvious impact of the Cu thickness (compare also the
SiOx/Cu ration given in Fig 7, supplementary material). The zoomed region on
the $x$-axis between 0 and 50 mm reveals more detailed resistance values,
encompassing all 23 devices of each cell. Along the $x$-axis, the resistance
decreases from R = 1011 $\Omega$ to R = 102 $\Omega$ until it rises to R = 108
$\Omega$ again. Between x = -50 mm and x = 0 mm the pristine resistance values
are nine orders of magnitude larger.

Figure 2: a) Resistance map of wedge-type deposited TiN/Six/Cu/SiOx/TiN
4”-wafer using setup A (C1: Cu, C2: SiO) with SiOx-thickness gradient
resulting in different memristive switching regions. Zoomed area with more
detailed resolution and marked distinctive regions b) Monte Carlo Simulations
of SiOx thickness/content/stoichiometry? c) Measured and simulated SiOx and Cu
thicknesses along the $x$-axis centerline at y = 0 mm. d) Monte Carlo
Simulations of Cu thickness.

However, the gradual decrease and then sudden increase in resistance along the
$x$-axis of the resistance map shown in 2 a) suggests the involvement of
additional factors, indicating that the observed behavior cannot be attributed
solely to variations in oxide thickness. The interplay between SiOx and Cu in
the switching layer, along with stoichiometry changes and edge effects, may
play a significant role and should be considered. However, these factors are
beyond the scope of this study, which focuses on the combination of
experimental and simulation finding of the impact of the layers’ composition
and thicknesses.

Previous studies have shown that reducing the thickness of the active layer
can massively change the switching behavior of oxide based memristive devices
[56, 57, 58]. Ma et. al showed recently, that even in ultrathin a-SiOx films
(below 3 nm) memristive behavior can be observed [59], but a systematic
analysis of how varying layer thickness affects switching behavior is still
missing. Even though exploring the current transport mechanism itself is out
of scope of this work, the decrease in oxide resistance can be independently
explained by the Poisson-Boltzmann equation (PBE), which describes the
distribution of electrical potential and charge carriers within the oxide
layer, thereby influencing its conductivity [60].

Figure 3: $I-V$ characteristics of TiN/SiOx/Cu/SiOx/TiN devices with varying
thickness of SiOx and Cu. Single and mean curves of devices A-D in regards to
the position on the wafer (see Fig. 2).

Even though the thickness dependent resistance across the wafer is shown and
explained before, the respective $I-V$ characteristics are considered and can
be grouped into 4 different switching behaviors shown in 3 a)-d) for area A,
B, C, and D, depending on the location on the wafer (Zoomed region Fig. 2 a)).
Therefore, the mean behavior of five individual adjacent devices, to ensure
device comparability regarding the layer thicknesses, are depicted in black,
while the characteristics of the single devices are shown in gray to show the
device-to-device variability. In the range of x = 0 mm and x = 50 mm an
opening of the hysteresis associated with a resistance change can be observed
and will be further analyzed later. With a relatively high SiOx thickness of
t${}_{\mathrm{SiO}_{x}}$ $>$ 13 nm and 1 nm $>$ tCu $>$ 0.7 nm (area A) the
devices indicate no memristive hysteresis effects in the applied voltage
region, which is reasonable due to the insulating properties of SiOx films and
the electroforming voltages of typically more than 1.7 V [61, 28]. Lowering
the SiOx thickness below t${}_{\mathrm{SiO}_{x}}$ $<$ 12 nm and tCu = 0.8 nm
(area B) shows an step-like abrupt increase of the current response for
applied voltages above 1 V which is typical for filamentary ECM-cells [13]. In
the negative polarity the observed resistance change cannot be inverted,
indicating a structural change of the morphology, which cannot be reversed and
is therefore considered as a breakdown of the device. With SiOx layer
thickness of roughly t${}_{\mathrm{SiO}_{x}}$ = 11 nm and an estimated copper
thickness of tCu = 0.7 nm (area C) the $I-V$ curves show no resistance change,
possibly due to a highly conductive pathway through the SiOx-matrix but needs
to be investigated in the future. At the right edge of the Wafer with a SiOx
layer thickness of t${}_{\mathrm{SiO}_{x}}$ $<$ 10.6 nm and a copper content
of tCu = 0.7 nm (area D) the characteristics establish a bipolar memristive
hysteresis with very little device-to-device variability. The rectifying
memristive behavior of the device is a desired feature for analog switching
memristive devices [62]. Even though a symmetrical device structure is
designed, a asymmetrical $I-V$ characteristic and bipolar switching features
of the device can be seen, which assumes a non-symmetrical layer structure
possibly due to island formation during Cu deposition. By using wedge-type
depositions of the SiOx and an approximately constant Cu content, particularly
the dependency on the SiOx thickness could be highlighted. A critical
threshold thickness of t${}_{\mathrm{SiO}_{x}}$ $<$ 10.6 nm tCu = 0.7 nm is
found for analog switching devices.

###  3.2 Cu wedge

To get a better insight into the influence of copper regarding the memristive
behavior of the devices, Fig. 4 shows the resistance map with a Cu-wedge by
interchanging the materials of crucible C1 and C2 during thermal evaporation
(setup B, Fig. 1). The resulting resistance wafermap is shown in Fig. 4 a).
Compared to the previous resistance map in Fig. 2 a) the resistance gradient
is less pronounced but still ranges from R = 102 $\Omega$ to R = 108 $\Omega$.
Whereas the left half ($x$-axis -50 to 0 mm) ranges between 102 and 104, the
right half ($x$-axis 0 to 50 mm) has a way more pronounced circular gradient
of 104 to 108.

Kinetic Monte Carlo Simulations in Fig. 4 b) and d) visualize the SiOx and Cu
particle flux and calculated layer thickness on a wafer level. The simulated
SiOx-layer thickness throughout the wafer ranges from 10.4 to 12.5 nm and the
estimated Cu-thickness is simulated to be from 0.5 to 0.9 nm in dependence of
the wafer position. By comparison with the resistance map, the area with a
higher resistance in the right end of the wafer correlates with a lower copper
content. The effect of the Cu thickness on the resistance is shown by the
asymmetrical resistance distribution, which does not fit the radial
distributuin of the SiOx-thickness depicted in Fig. 4 d). In Fig. 4 c), the
layer thicknesses relative to the position on the $x$-axis of the wafer for
SiOx and copper are illustrated. These thicknesses closely align with the
experimental data obtained from separate AFM measurements conducted under
identical conditions to those of the wafer under investigation (Fig. 4 c)).

Figure 4: a) Resistance map of wedge-type deposited TiN/SiOx/Cu/SiOx/TiN
4”-wafer using setup B (C1: SiO, C2: Cu) with a Cu-thickness gradient
resulting in different memristive switching regions. b) Monte Carlo
Simulations of Cu thickness/content/stoichiometry? c) Measured and simulated
SiOx and Cu thicknesses along the $x$-axis centerline at y = 0 mm. d) Monte
Carlo Simulations of SiOx thickness.

Since the thickness of the silicon oxide is chosen in the range of the area D
in Fig. 2 a) and in the memristive switching regime of the SiOx-wedge,
memristive hysteresis appear all over the wafer. Due to the asymmetry in the
resistance map, a copper-content-dependency in the memristive behavior can be
seen in the $I-V$ characteristics, which was not as apparent for a SiOx-wedge.
Therefore, two areas on the wafer were selected for illustration and more
detailed analysis, which are labeled as area E and F in Fig. 4 a).

Figure 5:  $I-V$ characteristics of TiN/SiOx/Cu/SiOx/TiN devices with varying
thickness of SiOx and Cu. Single (15) and mean curves of devices in area E and
F in regards to the position on the wafer (see Fig. 4).

For the $I-V$ characteristics shown in Fig. 5, 15 individual devices from area
E are depicted in grey and the corresponding mean value is shown in black.
Here the nominal thicknesses are t${}_{\mathrm{SiO}_{x}}$ = 11.8 nm and tCu =
0.7 nm. The current in the HRS at Vread = 0.5 V is IHRS = 1.29 $\cdot$ 10-6 A
and switches with Vset = 1.5 V to ILRS = 1.40 $\cdot$ 10-5 A. This corresponds
to a Ron/Roff-ratio of 10.8. The bipolar switching behavior of the devices
display a asymmetry in the hysteresis, which can be explained by the asymmetry
of the device, due to the Cu-island deposition. The devices in area F, which
are located to the right end of the wafer have a nominal SiOx-thickness of
around t${}_{\mathrm{SiO}_{x}}$ = 11.2 nm and a Cu-thickness of tCu = 0.55 nm.
The current in the HRS at Vtread = 0.5 V is IHRS = 9.47 $\cdot$ 10-8 A and
with Vset = 1.5 V rises to ILRS = 1.26 $\cdot$ 10-5 A. The following Ron/Roff-
ratio of 133.1 is 12 times bigger than the one in area E, which leads to the
assumption, that a lower Cu-content changes the resistance of the HRS of the
device, since the LRS current is in the same region. Furthermore the $I-V$
characteristics reveal an analog-like switching behavior with a gradual rise
in conductance, even though there is a more intensive increase in the current
in the range of 0.5 V to 1 V. No initial electro-forming or current compliance
is needed to operate the devices and by applying a negative voltage of Vreset,
the device switches completely back to the HRS. Wedge-type deposition of the
Cu-island layer shows the possibility of fine tuning the properties of the
memristive device in regards of Ron/Roff-ratio. By lowering the Cu-content in
the switching layer from tCu = 0.7 nm to tCu = 0.55 nm, the memory window can
be increased by a factor of 12.

###  3.3 Area dependent/analog switching

By combining the results of electrical measurements and simulation, critical
parameters for an analog-type memristive behavior were deduced, based on Cu-
islands sandwiched between silicon oxide layers. To illustrate the analog
behavior of the device, I-V curves with different maximum voltages (between
0.9 V to 1.6 V) leading to different memristive states are shown in Fig. 6 a).
Since no compliance current or forming is necessary for the switching behavior
of the device and the results of the $I-V$ measurements show no abrupt change
in resistance, it cannot be assumed straightaway that the switching behavior
is filamentary-driven. In contrast, an homogenouse switching effect is
indicated by the area-dependecy of switching shown in Fig. 6 b). For further
analysis and understanding of the current transport mechanism, the area-
dependency of the devices in area F is shown in the R $\times$ A plot in 6 b).
Therefore the mean value of five cells, each containing 23 devices per feature
size, were analyzed and the mean value as well as the standard deviation is
depicted for a voltage of 0.4 V pre (HRS) and post (LRS) switching.

Figure 6: a) Analog set behavior between 0.9 V - 1.6 V in a linear scale,
shows a gradual resistance change in dependence of the applied voltage. b) R
$\times$ A plot showing area dependence of the devices. HRS (black) and LRS
(red) at 0.5 V. Mean value of 5 cells (115 Devices) and standard deviation for
each contact area.

Even if an analog switching behavior can be realized in filamentary-driven
resistive random access memory (RRAM), these are limited in the number of
states by stochastic processes and compatibility with Si-technology [10, 63].
Since the number of states and $I-V$ nonlinearity are of major importance for
the application in neuromorphic systems [64], the reported device properties
are promising for mimicking synaptic behavior. From the graphical analysis of
the $I-V$ characteristics, a filmaentary-driven process is not obvious at
first glance. Since a small rise in the R $\times$ A plot is noteable in the
LRS, an exclusively homogenous current transport cannot be deducted. Therefore
multifilament formation [59, 65], (Cu-)ion migration [66], interface driven
processes [67, 43] as well as coexistance of different processes [68], as
shown in previous works, have to be considered for future investigations of
the memristive switching origin.

##  4 Conclusion

In this work a wedge-type engineered analog TiN/SiOx/Cu/SiOx/TiN memristive
device, well suited for neuromorphic applications, is presented. It was
fabricated by off-center and centered thermal evaporation of SiOx and Cu,
respectively, and vice versa. By fine tuning layer thicknesses, diverse
resistive switching behaviors dependent on the SiOx thickness were realized,
ranging from analog to abrupt transition modes. By Monte Carlo Simulations a
clear correlation between experimental resistance-maps and simulated layer
thicknesses have been drawn. Thickness values for the shown devices have been
quantified with most promising results shown for SiOx thicknesses below 12.5
nm. However, even minor deviations in layer thickness critically impact the
switching properties of the device. This underscores the necessity for precise
fabrication control and indicates that further research in this domain is
essential to optimize device performance. Ron/Roff-ratios of 133 could be
realized by combining a Cu content of less than 0.6 nm with SiOx thicknesses
of less than 12.5 nm. No clear indication for the predominance of filamentary
or homogeneous switching has been found. Hence, further research is necessary
to disentangle the potential coexistence or reveal the true origin. The
findings underscore the pivotal role of carefully choosing the material
properties and parameters during deposition, particularly the SiOx/Cu
thickness ratio. It dictates the device’s switching characteristics,
demonstrating that devices can be engineered to exhibit desired behaviors such
as analog switching suitable for mimicking synaptic functions in neuromorphic
computing systems.

Acknowledgements

Funded by the Deutsche Forschungsgemeinschaft (DFG, German Research
Foundation) – Project-ID 434434223 – SFB 1461

Conflicts of interest

There are no conflicts to declare.

Data Availability Statement

The data that support the findings of this study are available from the
corresponding authors upon reasonable request.

## References

  * [1] M. Mitchell Waldrop,  _Nature_ 2016, , Vol. 530 144.
  * [2] D. Strukov, G. Indiveri, J. Grollier, S. Fusi,  _Nature communications_ 2019, _10_ , 1 4838.
  * [3] G. E. Moore,  _Electronics Magazine_ 1965, , 38 114.
  * [4] J. Shalf,  _Philosophical transactions. Series A, Mathematical, physical, and engineering sciences_ 2020, _378_ , 2166 20190061.
  * [5] A. Mehonic, A. J. Kenyon,  _Nature_ 2022, _604_ , 7905 255.
  * [6] J. Del Ser, E. Osaba, D. Molina, X.-S. Yang, S. Salcedo-Sanz, D. Camacho, S. Das, P. N. Suganthan, C. A. Coello Coello, F. Herrera,  _Swarm and Evolutionary Computation_ 2019, _48_ , 1 220.
  * [7] D. Ielmini, H.-S. P. Wong,  _Nature Electronics_ 2018, _1_ , 6 333.
  * [8] J. Wang, Y. Zhu, L. Zhu, C. Chen, Q. Wan,  _Frontiers in Nanotechnology_ 2022, _4_ 244\.
  * [9] R. Yang, H.-M. Huang, X. Guo,  _Advanced Electronic Materials_ 2019, _5_ , 9 1803849.
  * [10] J. J. Yang, D. B. Strukov, D. R. Stewart,  _Nature nanotechnology_ 2013, _8_ , 1 13.
  * [11] R. Waser, R. Dittmann, G. Staikov, K. Szot,  _Advanced materials (Deerfield Beach, Fla.)_ 2009, _21_ , 25-26 2632.
  * [12] I. Valov, R. Waser, J. R. Jameson, M. N. Kozicki,  _Nanotechnology_ 2011, _22_ , 28 289502.
  * [13] S. Menzel, S. Tappertzhofen, R. Waser, I. Valov,  _Physical chemistry chemical physics : PCCP_ 2013, _15_ , 18 6945.
  * [14] R. Zhang, H. Huang, Q. Xia, C. Ye, X. Wei, J. Wang, L. Zhang, L. Q. Zhu,  _Advanced Electronic Materials_ 2019, _5_ , 5 1800833.
  * [15] Y. Xi, B. Gao, J. Tang, A. Chen, M.-F. Chang, X. S. Hu, J. van der Spiegel, H. Qian, H. Wu,  _Proceedings of the IEEE_ 2021, _109_ , 1 14.
  * [16] W. Zhang, B. Gao, J. Tang, X. Li, W. Wu, H. Qian, H. Wu,  _physica status solidi (RRL) – Rapid Research Letters_ 2019, _13_ , 10 1.
  * [17] S. Choi, J. Yang, G. Wang,  _Advanced materials (Deerfield Beach, Fla.)_ 2020, _32_ , 51 e2004659.
  * [18] V. A. Gritsenko, A. A. Gismatulin, O. M. Orlov,  _Nanobiotechnology Reports_ 2021, _16_ , 6 722.
  * [19] A. Mehonic, A. L. Shluger, D. Gao, I. Valov, E. Miranda, D. Ielmini, A. Bricalli, E. Ambrosi, C. Li, J. J. Yang, Q. Xia, A. J. Kenyon,  _Advanced materials (Deerfield Beach, Fla.)_ 2018, _30_ , 43 e1801187.
  * [20] C.-Y. Liu, P.-W. Sung,  _Japanese Journal of Applied Physics_ 2011, _50_ , 9R 091101.
  * [21] C. Schindler, S. C. P. Thermadam, R. Waser, M. N. Kozicki,  _IEEE Transactions on Electron Devices_ 2007, _54_ , 10 2762.
  * [22] V. Bhatt, S. Chandra,  _Journal of Micromechanics and Microengineering_ 2007, _17_ , 5 1066.
  * [23] B. W. Fowler, Y.-F. Chang, F. Zhou, Y. Wang, P.-Y. Chen, F. Xue, Y.-T. Chen, B. Bringhurst, S. Pozder, J. C. Lee,  _RSC Advances_ 2015, _5_ , 27 21215.
  * [24] N. Ilyas, C. Li, J. Wang, X. Jiang, H. Fu, F. Liu, D. Gu, Y. Jiang, W. Li,  _The journal of physical chemistry letters_ 2022, _13_ , 3 884.
  * [25] S. P. Thermadam, S. K. Bhagat, T. L. Alford, Y. Sakaguchi, M. N. Kozicki, M. Mitkova,  _Thin Solid Films_ 2010, _518_ , 12 3293.
  * [26] W. Chen, R. Fang, M. B. Balaban, W. Yu, Y. Gonzalez-Velo, H. J. Barnaby, M. N. Kozicki,  _Nanotechnology_ 2016, _27_ , 25 255202.
  * [27] J. Yao, Z. Sun, L. Zhong, D. Natelson, J. M. Tour,  _Nano letters_ 2010, _10_ , 10 4105.
  * [28] A. Mehonic, S. Cueff, M. Wojdak, S. Hudziak, O. Jambois, C. Labbé, B. Garrido, R. Rizk, A. J. Kenyon,  _Journal of Applied Physics_ 2012, _111_ , 7 341.
  * [29] Y.-F. Chang, P.-Y. Chen, Y.-T. Chen, F. Xue, Y. Wang, F. Zhou, B. Fowler, J. C. Lee,  _Applied Physics Letters_ 2012, _101_ , 5 052111.
  * [30] Y. Wang, X. Qian, K. Chen, Z. Fang, W. Li, J. Xu,  _Applied Physics Letters_ 2013, _102_ , 4 4105.
  * [31] G. Wang, Y. Yang, J.-H. Lee, V. Abramova, H. Fei, G. Ruan, E. L. Thomas, J. M. Tour,  _Nano letters_ 2014, _14_ , 8 4694.
  * [32] J.-S. Pei, J. P. Wright, M. D. Todd, S. F. Masri, F. Gay-Balmaz,  _Nonlinear Dynamics_ 2015, _80_ , 1-2 457.
  * [33] Z. Wang, M. Yin, T. Zhang, Y. Cai, Y. Wang, Y. Yang, R. Huang,  _Nanoscale_ 2016, _8_ , 29 14015.
  * [34] T. H. Park, S. J. Song, H. J. Kim, S. G. Kim, S. Chung, B. Y. Kim, K. J. Lee, K. M. Kim, B. J. Choi, C. S. Hwang,  _Scientific reports_ 2015, _5_ 15965\.
  * [35] Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie,  _Proceedings of the 47th Design Automation Conference_ ,  ACM Conferences. ACM, New York, NY, 2010.
  * [36] J. Lee, J. Park, S. Jung, H. Hwang,  In _2011 IEEE International Interconnect Technology Conference_. IEEE,  ISBN 978-1-4577-0503-8, 08.05.2011 - 12.05.2011 1–3.
  * [37] A. Petraru, H. Kohlstedt, U. Poppe, R. Waser, A. Solbach, U. Klemradt, J. Schubert, W. Zander, N. A. Pertsev,  _Applied Physics Letters_ 2008, _93_ , 7 856.
  * [38] N. Ruppelt, O. Vavra, H. Sickinger, E. Goldobin, D. Koelle, R. Kleiner, H. Kohlstedt,  _Applied Physics A_ 2014, _116_ , 1 229.
  * [39] P. Zhang, X. Zheng, S. Wu, J. Liu, D. He,  _Vacuum_ 2004, _72_ , 4 405.
  * [40] H. Chen, Y. Gang, C. Wenbin, L. Kaijun, L. Feng,  _Vacuum_ 2010, _85_ , 3 448.
  * [41] S. Park, S. Klett, T. Ivanov, A. Knauer, J. Doell, M. Ziegler,  _Frontiers in Nanotechnology_ 2021, _3_.
  * [42] F. Zahari, F. Schlichting, J. Strobel, S. Dirkmann, J. Cipo, S. Gauter, J. Trieschmann, R. Marquardt, G. Haberfehlner, G. Kothleitner, L. Kienle, T. Mussenbrock, M. Ziegler, H. Kersten, H. Kohlstedt,  _Journal of Vacuum Science & Technology_ 2019, _37_ , 6 189.
  * [43] M. Hansen, M. Ziegler, L. Kolberg, R. Soni, S. Dirkmann, T. Mussenbrock, H. Kohlstedt,  _Scientific reports_ 2015, _5_ 13753\.
  * [44] T. J. Scanlon, E. Roohi, C. White, M. Darbandi, J. M. Reese,  _Computers & Fluids_ 2010, _39_ , 10 2078.
  * [45] J. Trieschmann, T. Mussenbrock,  _Journal of Applied Physics_ 2015, _118_ , 3 015010.
  * [46] J. Trieschmann,  _Contributions to Plasma Physics_ 2018, _58_ , 5 394.
  * [47] J. Trieschmann, A. W. Larsen, T. Mussenbrock, S. B. Korsholm,  _Physics of Plasmas_ 2021, _28_ , 8 082505.
  * [48] L. I. Maissel, R. Glang, P. P. Budenstein,  _Journal of The Electrochemical Society_ 1971, _118_ , 4 114C.
  * [49] J. T. Gudmundsson, A. Anders, A. von Keudell,  _Plasma Sources Science and Technology_ 2022, _31_ , 8 083001.
  * [50] R. Tonneau, P. Moskovkin, A. Pflug, S. Lucas,  _Journal of Physics D: Applied Physics_ 2018, _51_ , 19 195202.
  * [51] William M. Haynes (Ed.),  _CRC Handbook of Chemistry and Physics_ ,  CRC Press, 97th edition edition, 2016.
  * [52] A. Hohl, T. Wieder, P. van Aken, T. Weirich, G. Denninger, M. Vidal, S. Oswald, C. Deneke, J. Mayer, H. Fuess,  _Journal of Non-Crystalline Solids_ 2003, _320_ , 1-3 255.
  * [53] J. Zhou, Y. Kang, D. Chen,  _Surface Science_ 2003, _537_ , 1-3 L429.
  * [54] Zhi Hui Liu, Norman M D Brown, Archibald McKinley,  _Journal of Physics: Condensed Matter_ 1997, _9_ , 1 59.
  * [55] Charles T. Campbell,  _Surface Science Reports_ 1997, _27_ , 1 1.
  * [56] A. V. Emel’yanov, V. A. Demin, I. M. Antropov, G. I. Tselikov, Z. V. Lavrukhina, P. K. Kashkarov,  _Technical Physics_ 2015, _60_ , 1 112.
  * [57] J. Li, Q. Duan, T. Zhang, M. Yin, X. Sun, Y. Cai, L. Li, Y. Yang, R. Huang,  _RSC Advances_ 2017, _7_ , 68 43132.
  * [58] V. M. Mordvintsev, S. E. Kudryavtsev, V. L. Levin,  _Technical Physics_ 2018, _63_ , 11 1629.
  * [59] Z. Ma, J. Ge, W. Chen, X. Cao, S. Diao, Z. Liu, S. Pan,  _ACS applied materials & interfaces_ 2022, _14_ , 18 21207.
  * [60] H. Abunahla, B. Mohammad, D. Homouz, C. J. Okelly,  _IEEE Transactions on Circuits and Systems I: Regular Papers_ 2016, _63_ , 12 2139.
  * [61] Y.-F. Chang, P.-Y. Chen, B. Fowler, Y.-T. Chen, F. Xue, Y. Wang, F. Zhou, J. C. Lee,  _Journal of Applied Physics_ 2012, _112_ , 12 729.
  * [62] R. Islam, H. Li, P.-Y. Chen, W. Wan, H.-Y. Chen, B. Gao, H. Wu, S. Yu, K. Saraswat, H.-S. Philip Wong,  _Journal of Physics D: Applied Physics_ 2019, _52_ , 11 113001.
  * [63] M. Zhao, B. Gao, J. Tang, H. Qian, H. Wu,  _Applied Physics Reviews_ 2020, _7_ , 1 368.
  * [64] M. Ziegler, C. Wenger, E. Chicca, H. Kohlstedt,  _Journal of Applied Physics_ 2018, _124_ , 15 1.
  * [65] K. Kim, J. G. Lim, S. M. Hu, Y. Jeong, J. Kim, S. Lee, J. Y. Kwak, J. Park, G. W. Hwang, K.-S. Lee, S. Park, W.-S. Lee, B.-K. Ju, J. K. Park, I. Kim,  _NPG Asia Materials_ 2023, _15_ , 1 1629.
  * [66] S. P. Thermadam, S. K. Bhagat, T. L. Alford, Y. Sakaguchi, M. N. Kozicki, M. Mitkova,  _Thin Solid Films_ 2010, _518_ , 12 3293.
  * [67] Y. Aoki, C. Wiemann, V. Feyer, H.-S. Kim, C. M. Schneider, H. Ill-Yoo, M. Martin,  _Nature communications_ 2014, _5_ 3473\.
  * [68] S. Roy, B. Chakrabarti, E. Bhattacharya,  _IEEE Transactions on Electron Devices_ 2023, _70_ , 10 5421.

##  5 Appendix

Common |  |  |  |  |
---|---|---|---|---|---
$\rho_{\text{SiO}}$ (g/cm3) |  $\rho_{\text{Cu}}$ (g/cm3) |  $m_{\text{SiO}}$ (amu) |  $m_{\text{Cu}}$ (amu) |  |
2.19 | 8.92 | 44.084 | 63.546 |  |
WM1 |  |  |  |  |
$\Gamma_{\text{SiO}}$ (1/(m2 s)) |  $\Gamma_{\text{Cu}}$ (1/(m2 s)) | $w_{\text{sp, SiO}}$ | $w_{\text{sp, Cu}}$ |  $T_{\text{SiO}}$ (s) |  $T_{\text{Cu}}$ (s)
5.86e20 | 1e21 | 8e9 | 6.97e8 | 180 | 27
WM2 |  |  |  |  |
$\Gamma_{\text{SiO}}$ (1/(m2 s)) |  $\Gamma_{\text{Cu}}$ (1/(m2 s)) | $w_{\text{sp, SiO}}$ | $w_{\text{sp, Cu}}$ |  $T_{\text{SiO}}$ (s) |  $T_{\text{Cu}}$ (s)
3.66e20 | 1e21 | 1e10 | 6.97e8 | 200 | 30
Table 1: Parameters used for in the Monte Carlo transport simulation. Figure
7: WM1: Film thickness ratio for SiO/Cu Figure 8: WM2: Film thickness ratio
for SiO/Cu