11institutetext:  Open University of the Netherlands 22institutetext: Centrum
Wiskunde & Informatica (CWI)
22email<EMAIL_ADDRESS>
# Shuffling posets on trajectories
(technical report)

Luc Edixhoven  0000-0002-6011-9535

###### Abstract

Choreographies describe possible sequences of interactions among a set of
agents. We aim to join two lines of research on choreographies: the use of the
shuffle on trajectories operator to design more expressive choreographic
languages, and the use of models featuring partial orders, to compactly
represent concurrency between agents. Specifically, in this paper, we explore
the application of the shuffle on trajectories operator to individual posets,
and we give a characterisation of shuffles of posets which again yield an
individual poset.

###### Keywords:

Posets Shuffle on trajectories Concurrency

Technical report of a paper to be published in the proceedings of iFM 2023.

##  1 Introduction

Distributed systems are becoming ever more important. However, designing and
implementing them is difficult. The complexity resulting from concurrency and
dependencies among agents makes the process error-prone and debugging non-
trivial. As a consequence, much research has been dedicated to analysing
communication patterns, or protocols, among sets of agents in distributed
systems. Examples of such research goals are to show the presence or absence
of certain safety properties in a given system, to automate such analysis, and
to guarantee the presence of desirable properties by construction.

Part of this research deals with _choreographies_. Choreographies can be used
as global specifications for asynchronously communicating agents, and contain
certain safety properties by construction. As a drawback, choreographic
languages typically have limitations on their expressiveness, since they rely
on grammatical constructs for their safety properties, which exclude some
communication patterns. We have recently shown that the _shuffle on
trajectories_ operator can be used to specify choreographies without
compromising expressiveness [2]. Consequently, it could serve as a basis for
more expressive choreographic languages.

Other recent work on choreographies includes the use of models featuring
partial orders, such as event structures [1] and pomsets [6, 3], to represent
and analyse the behaviour of choreographies. By using a partial order to
explicitly capture causal dependencies between pairs of actions, these models
avoid the exponential blowup from, e.g., parallel composition of finite state
machines.

We aim to join these two lines of research by extending the shuffle on
trajectories operator from words, i.e., totally ordered traces, and languages
to partially ordered traces and sets thereof. In this paper, as a first step,
we explore the application of the shuffle on trajectories operator to
individual partially ordered sets, or posets. The main challenge is that the
resulting behaviour cannot always be represented as one poset and may require
a set of them. In particular, we give a characterisation of shuffles of posets
which again yield an individual poset.

### Outline

We recall the concept and definition of the shuffle on trajectories operator
in Section 2. We briefly discuss posets in Section 3. In Section 4 we discuss
how to apply the shuffle on trajectories operator to posets, and specifically
which shuffles of posets will yield an individual poset as a result. Finally,
we briefly discuss future work in Section 5.

The proofs of Proposition 1 and Lemma 1 can be found in the appendix.

##  2 Shuffle on trajectories

We recall the basic definitions from [2]. The shuffle on trajectories operator
is a powerful variation of the traditional shuffle operator111In concurrency
theory, the shuffle operator is also known as free interleaving, non-
communication merge, or parallel composition., which adds a control trajectory
(or a set thereof) to restrict the permitted orders of interleaving. This
allows for fine-grained control over orderings when shuffling words or
languages. The binary operator was defined — and its properties thoroughly
studied — by Mateescu et al. [4]; a multiary variant was introduced slightly
later [5].

When defined on words, the shuffle on trajectories takes $n$ words and a
_trajectory_ , which is a word over the alphabet $\\{1,\ldots,n\\}$. This
trajectory specifies the exact order of interleaving of the shuffled words: in
Figure 1, the trajectory 1221112112 specifies that the result should first
take a symbol from the first word, then from the second, then again from the
second and so on.

12bananapear Figure 1: The shuffle of ‘banana’ and ‘pear’ over a trajectory
$1221112112$: ‘bpeanaanar’.

Formally, let $w_{1},\ldots,w_{n}$ be finite words over some alphabet and let
$t$ be a finite word over the alphabet $\\{1,\ldots,n\\}$. Let $\varepsilon$
be the empty word. Then:

$\shuffle^{n}_{t}(w_{1},\ldots,w_{n})=\begin{cases}a\shuffle^{n}_{t^{\prime}}(w_{1},\ldots,w_{i}^{\prime},\ldots,w_{n})&\text{if
$t=it^{\prime}$ and $w_{i}=aw_{i}^{\prime}$}\\\ \varepsilon&\text{if
$t=w_{1}=\ldots=w_{n}=\varepsilon$}\end{cases}$

We note that $\shuffle^{n}_{t}(w_{1},\ldots,w_{n})$ is only defined if the
number of occurrences of $i$ in $t$ precisely matches the length of $w_{i}$
for every $i$. We then say that $t$ _fits_ $w_{i}$.

###### Example 1

  * •

$\shuffle^{3}_{121332}(ab,cd,\mathit{ef})=\mathit{acbefd}$, since 121332 fits
every word.

  * •

$\shuffle^{2}_{121}(ab,cd)$ is undefined, since 121 does not fit $cd$.

The shuffle on trajectories operator naturally generalises to languages: the
shuffle of a number of languages on a set (i.e., a language) of trajectories
is defined as the set of all valid shuffles of words in the languages for
which the trajectory fits all the words. Formally:

$\shuffle^{n}_{T}(L_{1},\ldots,L_{n})=\\{\shuffle^{n}_{t}(w_{1},\ldots,w_{n})\mid
t\in T,w_{1}\in L_{1},\ldots,w_{n}\in L_{n}\\}$

As the operator’s arity is clear from its operands, we typically omit it.

##  3 Posets

Partially ordered sets, or posets for short, consist of a set of nodes $E$
(events), and a partial order222Recall that a partial order is reflexive,
transitive and antisymmetric. $\leq$ defining dependencies between pairs of
events — i.e., an event can only fire if all events preceding it in the
partial order have already fired. We write $a<b$ to denote that $a\leq b$ and
$a\neq b$. We write $a\geq b$ resp. $a>b$ to denote that $b\leq a$ resp.
$b<a$. We write $a\not\gtrless b$ to denote that $a\not\leq b$ and $b\not\leq
a$; we then say that $a$ and $b$ are _concurrent_. We occasionally write
$E_{P},\leq_{P}$, $<_{P}$, $\geq_{P}$, $>_{P}$ and $\not\gtrless_{P}$ to
specify that the set of events or relation belongs to poset $P$, but where
this is clear from context we typically omit the subscript.

The behaviour (or language) of a poset $P$, written $L(P)$, is the set of all
maximal traces, i.e., maximal sequences of its events, that abide by $\leq$.
In this sense, posets can be considered a generalisation of words with
concurrency: they feature a fixed set of symbols (events)333There is a
difference between words and posets in the sense that the events in a poset
must be unique, whereas a word may contain duplicate symbols. It would be more
accurate to say that words generalise to _labelled_ posets, or lposets, and
from there to partially ordered _multisets_ , or pomsets. However, in this
paper we focus on posets, where all symbols are thus unique., but they can
allow multiple orderings of them instead of only a single one. Concurrent
events can happen in any order. Consequently, all traces obtained from a trace
in $L(P)$ by swapping adjacent concurrent events must also be in $L(P)$. In
fact, any trace in $L(P)$ can be obtained from any other trace in $L(P)$ in
this fashion.

###### Example 2

For poset $P_{ex}$ in Figure 2, $E=\\{a,b,c,d\\}$ and the partial order
consists of $a\leq a$, $a\leq c$, $a\leq d$, $b\leq b$, $b\leq d$, $c\leq c$
and $d\leq d$. Its language $L(P_{ex})$ consists of the traces $abcd$, $abdc$,
$acbd$, $bacd$, and $badc$.

$P_{ex}=$ $a$$b$$c$$d$ $P_{1}=$ $a$$b$$c$$d$ $P_{2}=$ $e$ $LP_{t_{1}}=$
$1$$1$$1$$1$$2$

$LP_{t_{2}}=$ $1$$1$$1$$1$$2$ $P_{r_{1}}=$ $a$$b$$c$$d$$e$ $P_{r_{2a}}=$
$a$$b$$c$$d$$e$ $P_{r_{2b}}=$ $a$$b$$c$$d$$e$

Figure 2: Graphical representation of a number of posets and lposets, where an
arrow from $a$ to $b$ should be read as $a\leq b$. The partial order is the
reflexive and transitive closure of the dependencies depicted by the arrows.
For the lposets, the labels are shown rather than their events.

We note that the dependencies in a poset can also be observed in its set of
traces. For example, if $a<b$ then $a$ will precede $b$ in every trace, and if
$a\not\gtrless b$ then there will both be traces where $a$ precedes $b$ and
traces where $b$ precedes $a$. Formally, we can extract the following relation
$\leq_{L}$ from a set of traces $L\subseteq E^{*}$:

$\displaystyle\dfrac{\begin{gathered}\exists x,y,z\in E^{*}:xaybz\in L\\\
\forall\hat{x},\hat{y},\hat{z}\in E^{*}:\hat{x}b\hat{y}a\hat{z}\notin
L\end{gathered}}{a\leq_{L}b}\qquad\dfrac{}{a\leq_{L}a}\qquad\dfrac{a\leq_{L}b\leq_{L}c}{a\leq_{L}c}$

We then propose the following:

######  Proposition 1 ()

Let $P=\langle E_{P},\leq_{P}\rangle$ be a poset. Then
${\leq_{L(P)}}={\leq_{P}}$.

To model trajectories, which require duplicate symbols, we must also introduce
_labelled_ posets, or _lposets_. In these, every event is assigned a label,
which is not necessarily unique. Its traces then use these labels instead of
the events.

##  4 Shuffling posets

As a first step towards shuffling posets, we first reinterpret shuffles on
words as posets. In other words: we consider the case where all posets,
including the trajectory, are totally ordered and thus consist of a single
trace. This is shown in Figure 3, which features the shuffle from Figure 1
interpreted as a poset. The traces ‘banana’ and ‘pear’ are present as totally
ordered parts of the poset, and the trajectory adds additional dependencies
between the two, as shown by the vertical (and diagonal) arrows.

$b$$a_{1}$$n_{1}$$a_{2}$$n_{2}$$a_{3}$$p$$e$$a_{4}$$r$

1111112222

Figure 3: The figure on the left shows the shuffle from Figure 1 interpreted
as a shuffle of posets. Indices have been added to duplicate symbols to make
them unique. Some of the arrows are redundant but are kept to illustrate the
general idea. The figure on the right shows the trajectory, 1221112112, as an
lposet.

Generalising this to arbitrary posets and lposets is not trivial, but we have
some knowledge to assist us. Crucially, since we can determine the language of
a poset, it must be so that the result of shuffling posets yields the same
language as the shuffle of the languages of these posets, which is defined in
Section 2:

$L(\shuffle_{P_{t}}(P_{1},\ldots,P_{n}))=\shuffle_{L(P_{t})}(L(P_{1}),\ldots,L(P_{n}))$

If the result is an individual poset, by Proposition 1 it must then be:

$\shuffle_{P_{t}}(P_{1},\ldots,P_{n})=\langle E_{P_{1}}\cup\ldots\cup
E_{P_{n}},\leq_{\shuffle_{L(P_{t})}(L(P_{1}),\ldots,L(P_{n}))}\rangle$

For example, consider $\shuffle_{LP_{t_{1}}}(P_{1},P_{2})$, with $LP_{t_{1}}$,
$P_{1}$ and $P_{2}$ as in Figure 2. $LP_{t_{1}}$ has traces 1121 and 1112,
$P_{1}$ has traces $abcd$, $acbd$ and $cabd$, and $P_{2}$ has a single trace
$e$. Shuffling these languages yields
$L_{1}=\\{abced,acbed,cabed,abcde,\allowbreak acbde,\allowbreak cabde\\}$.
From this we extract $\leq_{L_{1}}$, which contains all the dependencies
present in $P_{1}$ and $P_{2}$ and, additionally, $a\leq_{L_{1}}e$,
$b\leq_{L_{1}}e$ and $c\leq_{L_{1}}e$. This corresponds to poset $P_{r_{1}}$
in Figure 2, which indeed yields the language $L_{1}$.

However, now consider $\shuffle_{LP_{t_{2}}}(P_{1},P_{2})$, again as in Figure
2. $LP_{t_{2}}$ has traces 1211, 1121 and 1112, which yields
$L_{2}=L_{1}\cup\\{abecd,acebd,caebd\\}$. From this we extract $\leq_{L_{2}}$,
which still contains all the dependencies in $P_{1}$ and $P_{2}$, but
otherwise only $a\leq_{L_{2}}e$: the traces $abecd$ and $acebd$ imply that $b$
and $c$ are concurrent with $e$. However, then the trace $aebcd$ should also
be in $L_{2}$, which it is not. We can then conclude from Proposition 1 that
there exists no poset $P$ such that $L(P)=L_{2}$. In fact, $L_{2}$ corresponds
to a set of two posets, namely $P_{r_{2a}}$ and $P_{r_{2b}}$ in Figure 2.

We proceed by giving a characterisation of shuffles of posets for which the
result corresponds to an individual poset. A key insight is that, if the
result must correspond to an individual poset, then any two events which are
concurrent in one of the operands of the shuffle must, in the resulting poset,
have the same relation ($<$, $>$ or $\not\gtrless$) to any third event
originating from another operand:

######  Lemma 1 ()

Let $LP_{t}$ be an lposet and $P_{1},\ldots,P_{n},P$ posets such that
$L(\shuffle_{LP_{t}}(P_{1},\allowbreak\ldots,P_{n}))=L(P)$ and
$L(P)\neq\emptyset$. If $a,b\in E_{P_{i}}$ such that $a\not\gtrless_{P_{i}}b$
and $c\in E_{P_{j}}$ with $i\neq j$, then either $a,b<_{P}c$, or $a,b>_{P}c$,
or $a,b\not\gtrless_{P}c$.

We can then group the events in every $P_{i}$ according to the reflexive and
transitive closure of the concurrency relation $\not\gtrless_{P_{i}}$; two
events which are related in this closure then belong to the same group. Note
that, while the events in a group are partially ordered, the groups of every
$P_{i}$ are, by construction, totally ordered. It follows from Lemma 1 that
two events in the same group, even when not concurrent, must have the same
relation to any event outside of their group in $P$. This in turn implies a
similar condition on the trajectory lposet: any two $i$-labelled events in
$LP_{t}$ that can match two events from the same group of $P_{i}$ must have
the same relation to any $j$-labelled event in $LP_{t}$ (where $j$ is not
necessarily unequal to $i$) that can match an event outside of their group.

Figure 4 shows $P_{r_{1}}$, corresponding to
$\shuffle_{LP_{t_{1}}}(P_{1},P_{2})$, and $LP_{t_{1}}$ (from Figure 2), both
restructured to show the groups of $P_{1}$ and $P_{2}$. This demonstrates an
interesting parallel with Figure 3: both feature horizontal traces with
additional arrows specifying dependencies between components of these traces.
However, in Figure 3 the components consist of individual events, whereas in
Figure 4 the components consist of posets. In this sense, shuffles resulting
in individual posets generalise shuffles on traces.

$a$$b$$c$$d$$e$

11112

Figure 4: The figure on the left shows $P_{r_{1}}$, corresponding to
$\shuffle_{LP_{t_{1}}}(P_{1},P_{2})$ (see Figure 2), restructured to show the
groups of $P_{1}$ and $P_{2}$. An arrow from one group of events to another
should be read as an arrow from all events in the originating group to all
events in the target group. The figure on the right shows the restructured
$LP_{t_{1}}$; the dependencies within groups in $LP_{t_{1}}$ are irrelevant
for the resulting traces.

Concluding, we can then characterise shuffles on posets which result in
individual posets as those where the trajectory lposet is structured along the
operand posets’ groups, as in Figure 4, possibly with dependencies between
different operands’ groups.

##  5 Future work

Now that we have studied shuffles of posets resulting in individual posets,
there are two evident avenues for future work: (1) shuffles of lposets, where
one label may occur multiple times rather than just considering orderings of
unique events and (2) shuffles of posets resulting in sets of posets and
shuffles of sets of posets, where the main challenge may be to minimise the
resulting number of posets.

## References

  * [1] Castellani, I., Dezani-Ciancaglini, M., Giannini, P.: Event structure semantics for multiparty sessions. J. Log. Algebraic Methods Program. 131, 100844 (2023)
  * [2] Edixhoven, L., Jongmans, S.: Balanced-by-construction regular and $\omega$-regular languages. Int. J. Found. Comput. Sci. 34(2&3), 117–144 (2023)
  * [3] Edixhoven, L., Jongmans, S., Proença, J., Cledou, G.: Branching pomsets for choreographies. In: ICE. EPTCS, vol. 365, pp. 37–52 (2022)
  * [4] Mateescu, A., Rozenberg, G., Salomaa, A.: Shuffle on trajectories: Syntactic constraints. Theor. Comput. Sci. 197(1-2), 1–56 (1998)
  * [5] Mateescu, A., Salomaa, K., Yu, S.: On fairness of many-dimensional trajectories. J. Autom. Lang. Comb. 5(2), 145–157 (2000)
  * [6] Tuosto, E., Guanciale, R.: Semantics of global view of choreographies. J. Log. Algebraic Methods Program. 95, 17–40 (2018)

##  Appendix 0.A Proofs from the paper

See 1

###### Proof

  * •

Suppose that $a\leq_{P}b$ for some $a,b\in E_{P}$. Then, since $\leq_{P}$ is a
partial order, either:

    * –

$a=b$, in which case also $a\leq_{L(P)}b$ since $\leq_{L(P)}$ is reflexive; or

    * –

$a\leq_{P}b$ but $a\neq b$, in which case $a$ will precede $b$ in every
(maximal) trace of $P$. Furthermore, $L(P)$ will not be empty, and then
$a\leq_{L(P)}b$ by its first rule.

  * •

Suppose that $a\leq_{L(P)}b$ for some $a,b\in E_{P}$. Then, by definition of
$\leq_{L(P)}$, either:

    * –

$a=b$, in which case also $a\leq_{P}b$ since $\leq_{P}$ is reflexive; or

    * –

(1) $\exists x,y,z\in E_{P}^{*}:xaybz\in L(P)$ and (2)
$\forall\hat{x},\hat{y},\hat{z}\in E_{P}^{*}:\hat{x}b\hat{y}a\hat{z}\notin
L(P)$. Suppose, for the sake of contradiction, that $a\not\leq_{P}b$. Then
either $a>_{P}b$, which contradicts (1), or $a\not\gtrless_{P}b$, which
contradicts (2) since there should then also exist some trace in $L(P)$ in
which $b$ precedes $a$. We can thus conclude that $a\leq_{P}b$.

We note that the transitive rule for $\leq_{L(P)}$ is subsumed by the other
two and does not need to be considered separately. Nevertheless, a
straightforward inductive argument suffices to cover this.

See 1

###### Proof

If no subscript is given, in this proof, $<$ and $\not\gtrless$ refer to
$<_{P}$ and $\not\gtrless_{P}$.

We start by making three observations:

  1. (1)

As noted in Section 3, if $a\not\gtrless_{P_{i}}b$, then there must exist
traces in $L(P_{i})$ such that $a$ occurs before $b$ in one, and after $b$ in
another. Furthermore, since all traces of a poset can be obtained from an
arbitrary one by swapping adjacent concurrent events, there must also exist
traces such that $a$ and $b$ are adjacent to each other, in both orders, e.g.,
$vabw$ and $vbaw$ for some $v,w$.

  2. (2)

The causal relation between two events in $P_{i}$ remains the same in $P$. The
shuffle on trajectories operator does not change the internal order of the
traces of its operands, meaning that, for example if $d$ occurs before $e$ in
every trace of $P_{i}$, then it will also occur before $e$ in every trace of
$P$. Similarly, if $P_{i}$ both contains traces in which $d$ occurs before $e$
and traces in which $d$ occurs after $e$, then so will $P$. In particular,
this means that, since $a\not\gtrless_{P_{i}}b$, also $a\not\gtrless b$.

  3. (3)

If two events are concurrent in $P_{i}$ and can thus be swapped in traces of
$P_{i}$ when adjacent, then they can also be swapped in traces of $P$ when
there are no other events from $P_{i}$ in between them. The shuffle on
trajectories operator does not make any distinction between the corresponding
traces from $P_{i}$. Additionally, we note that this implies that the two
events are concurrent with all events (from other operands) in between.

Consider the relation between $a$, $b$ and $c$ in $P$. As observed in (2),
$a\not\gtrless b$.

  * •

Suppose that $a<c$ and $c<b$. It then follows by transitivity (recall that
$\leq$ is a partial order) that $a<b$, which contradicts $a\not\gtrless b$.
Analogously, we can exclude the case where $b<c$ and $c<a$.

  * •

Suppose that $a<c$ and $b\not\gtrless c$. Then, there must exist a trace
$uavcwbx$ in $L(P)$ for some $u,v,w,x$, i.e., a trace where $a$ occurs before
$c$ and where $b$ occurs after $c$. If $vw$ contains no events from $P_{i}$,
then it follows from $a\not\gtrless b$ and (3) that $L(P)$ must also contain
$ubvcwax$, which contradicts $a<c$. Otherwise, we systematically remove the
events from $P_{i}$ in $vw$:

    * –

Let $d$ be the leftmost event from $P_{i}$ in $vw$ such that $d<b$. Then,
since we must be able to swap adjacent concurrent events in traces of $P_{i}$
until $a$ and $b$ are adjacent (as noted in (1)), $d$ must be concurrent with
all events from $P_{i}$ to the left of it in $avw$ (including $a$). We can
thus swap $d$ with its left neighbour from $P_{i}$ until it has been swapped
with $a$, thus reducing the number of events from $P_{i}$ in $vw$ by 1. We
repeat this until there are no events left in the remainder of $vw$ that fit
this description.

    * –

Analogously, let $e$ be the rightmost event from $P_{i}$ in the remainder of
$vw$ such that $a<e$. Then $e$ must be concurrent with all events from $P_{i}$
to the right of it until at least $b$, so we swap it with its right neighbour
from $RPi$ until it has been swapped with $b$. Again, we repeat this until
there are no events left that fit this description.

    * –

All events from $P_{i}$ remaining in $vw$ must now be concurrent with both $a$
and $b$. We can thus keep swapping $a$ with its right neighbour (or,
alternatively, $b$ with its left neighbour) from $P_{i}$ until there are no
events from $P_{i}$ remaining between $a$ and $b$.

If, at some point, $a$ has passed $c$ and is now to the right of it, then this
contradicts $a<c$. If $a$ remains to the left of $c$ and $b$ to its right,
then we can swap $a$ and $b$ to contradict $a<c$. Otherwise, if $b$ has passed
$c$ and is now to the left of it, then $b$ must be concurrent with all events
to the right of it at least until $c$ (as noted in (3)). We can then swap it
with its right neighbour (from $P$) until it has been swapped with $c$, after
which we can swap it with $a$ to contradict $a<c$.

As all cases lead to a contradiction, we can thus conclude that it is not
possible that $a<c$ and $b\not\gtrless c$. Analogously, we can also exclude
the cases where $c<a$ and $b\not\gtrless c$, where $b<c$ and $a\not\gtrless
c$, and where $c<b$ and $a\not\gtrless c$.

As we have excluded all other cases, this proves that either $a,b<c$, or
$c<a,b$, or $a,b\not\gtrless c$. ∎


# An Open-Source Framework for Rapid Validation of Scientific ASICs ††thanks:
This manuscript has been authored by Fermi Research Alliance, LLC under
Contract No. DE-AC02-07CH11359 with the U.S. Department of Energy, Office of
Science, Office of High Energy Physics. This work was funded by the DOE Office
of Science Research Program for Microelectronics Codesign through the project
“Hybrid Cryogenic Detector Architectures for Sensing and Edge Computing
enabled by new Fabrication Processes” (LAB 21-2491). A. Quinn is with the
Fermi National Accelerator Laboratory, Pine & Kirk St, Batavia, IL 60510
(e-mail: aquinn@fnal.gov).

Adam Quinn  Microelectronics Division
Fermi National Accelerator Laboratory
Batavia, IL
<EMAIL_ADDRESS>
###### Abstract

Spacely is an open-source framework for the post-silicon validation of analog,
digital, and mixed-signal ASICs (Application-Specific Integrated Circuits)
which maximizes the reuse of hardware and software, reducing the time taken to
achieve meaningful test results. Spacely specifically addresses the needs of
small, flexible ASIC design teams commonly found in academia or research
institutions which benefit most from sharing the overhead of test stand
creation between many unique ASIC designs. Spacely is a set of software,
firmware, and design practices. It targets two primary hardware platforms (NI-
PXI and Caribou) as well as offering extensible support for bench instruments.
Spacely provides a high-level Python interface to all test hardware for
accessibility, while also giving more sophisticated teams the opportunity to
integrate custom test firmware. The design principles of Spacely are
presented, along with a demonstrative example of using Spacely to test a pixel
detector readout ASIC.

###### Index Terms:

open-source, validation, ASIC, testbench, Python

##  I Introduction

Modern mixed-signal Application-Specific Integrated Circuits (ASICs) may
contain dozens of co-designed analog and digital blocks which interoperate
through complex, high-speed interfaces which cannot be directly observed from
the outside. They may be extensively reconfigurable and contain millions of
bits of unique state. Validating the operation of these devices and measuring
their performance is inherently challenging, and often requires the
cooperation of experts in a range of domains from noise analysis to digital
synthesis, as well as the use of expensive high-performance test
instrumentation [1]. This challenge is felt most acutely in academic and
research environments where the ASICs under test probe the edge of technical
possibility, and may contain specialized functionality that does not fit
traditional test regimes, such as operation in extreme environments or novel
sensing methods. Research teams also lack the scale and resources of large IC
design companies, and often work on a variety of disparate chip designs
instead of making incremental improvements on a few established product lines,
making it cost-prohibitive to develop extensive customized test solutions.

In such a context, obtaining ASIC test results in a reasonable timeframe
requires streamlining and generalizing the test process to the greatest extent
possible, freeing experts to focus on the unique challenges of their novel
design. An open-source validation framework which maximizes reuse of code and
hardware has the potential to address this challenge, while being within the
financial reach of academic and research institutions. [2]

Open-source and reusable architectures for designing chips have become
prolific in recent years [3] [4], and industrial-quality ASICs have been
demonstrated using fully open-source EDA flows like OpenLane [5]. Yet when it
comes to hardware test automation, ad-hoc in-house solutions and expensive
commercial systems are still dominant [6]. Recently, progress has been made in
developing open-source data acquisition hardware [6] [7] [8] [9] [10] and
software infrastructure [11], however a greater degree of abstraction and
rapid reconfigurability is needed to meet the needs of low-volume, quick-
turnaround research environments.

Figure 1: Spacely Design Principles

Figure 2: The basic structure of the three Spacely code repositories, and key
files found within each. spacely-asic-config, which contains ASIC-specific
code, is a submodule of the core spacely repository. Both spacely and spacely-
asic-config call library functions from py-libs-common. Bolded filenames in
the following sections can be found in this figure.

Spacely is an open-source framework for validating analog, digital, and mixed-
signal scientific ASICs. It can interface to either NI-PXI, a leading
commercial data acquisition system, or to Caribou, an open-source data
acquisition hardware system also developed in the scientific community.
Spacely provides a unified Python environment for setting up instruments,
scripting tests, and analyzing data. Development of this framework adheres to
a set of design principles (Figure 1):

  * •

Non-Expert Use: Any person who can write Python should be able to write ASIC
tests with Spacely, and understand tests that have been written by others.
This is crucial to prevent information from being lost between engineers who
use different tools (i.e. design vs test engineers), and also allows people
such as science domain experts and students to be involved in test.

  * •

Reuse by Design: Design-specific code should be limited to the bare minimum
and kept in a single location so that the user can ”swap in” to a different
ASIC while keeping the vast majority of the spacely code base exactly the
same.

  * •

Tinker Friendly: If the user knows how to perform a task with a snippet of
Python, they should be able to write that snippet and run it easily in the
Spacely environment. If the task is common enough, Spacely should provide a
short shell command to perform it, but the interface should never get in the
user’s way. (For this reason, Spacely eschews GUIs in favor of shells.)

The remaining sections of this paper discuss the core Spacely codebase and
workflow for using Spacely (Sections II and III), Spacely integration with NI-
PXI (Section IV) and Caribou (Section V), and an example of using Spacely to
rapidly validate a scientific ASIC (Section VI).

##  II Spacely Workflow

The Spacely codebase is divided into three mutually-dependent repositories in
order to promote code reuse (see Figure 2).

The main spacely repository contains core code for Spacely’s interactive shell
and for integration with the NI-PXI and Caribou hardware systems described
later, along with various utilities for analyzing and manipulating data that
is collected from the ASIC under test.

The spacely-asic-config repository, a submodule of spacely, contains a
subfolder for every ASIC which is tested using Spacely. This subdirectory
contains all code which is specific to that ASIC, such as settings for the
values of voltage and current biases, or custom routines written to test a
specific block implemented on that ASIC.

Finally, the py-libs-common repository contains instrument drivers and basic
libraries for communication protocols and logging which may have use even
beyond Spacely.

Spacely is designed to be accessible to users of varying levels of
sophistication, from ASIC/FPGA designers to scientists or students who can
write Python but have limited hardware experience. It is possible to fully
test many mixed-signal ASICs simply by writing Python routines in the spacely-
asic-config area. However, as an open-source project, teams with development
experience can also extend py-libs-common to support additional test
instruments or develop custom firmware, depending on the primary hardware
platform.

The sections below give an overview of the steps that must be taken to
validate most ASICs:

###  II-A Select a Primary Hardware Platform

Spacely targets two primary hardware platforms which are used to communicate
with an ASIC. The details of using each of these platforms is presented in
later sections.

NI-PXI is a proprietary test automation platform developed by National
Instruments. In a typical configuration, it consists of a chassis which can
host multiple pluggable ”modules” including FPGAs, power supplies, and bias
generators.

Caribou [8] [9] is an open-source data acquisition platform developed by a
collaboration of universities and research institutions. It is based around a
Xilinx SoC with a Control-and-Readout (CaR) board that supplies current and
voltage supplies, ADCs, DACs, and pulsers.

While NI-PXI is an established platform with commercial heritage, and may
scale more easily to accomodate ASICs with a very high number of I/Os, the
Caribou platform offers a much lower upfront cost and zero ongoing license
fees, and is generally more customizable, and allowing users with RTL
experience to develop custom firmware blocks with industry-standard tools
(Vivado). The Caribou platform also has unique features such as high-speed GTx
links.

The Spacely conceptual framework and design principles can easily be extended
to alternative FPGAs or hardware platforms. However, extending the codebase to
be compatible with these platforms is non-trivial. The author has carried out
significant work to create bitfiles (for NI-PXI) and OS images (for Caribou)
which are made freely available to the Spacely user, but would have to be
replicated for another platform.

ASIC carrier PCBs must be designed to fit the I/O specification of the
selected hardware system. However, considering the flexibility of both
systems, a large degree of PCB design reuse can be expected.

###  II-B Define an ASIC Configuration

The first file that should be written when testing an ASIC with Spacely is
typically spacely-asic-config/MyASIC/MyASIC_Config.py. This file describes the
test hardware setup in a Python format, and specifies everything that should
be initialized when Spacely starts. The format of this file is described in
Spacely Documentation. In general, it defines:

  * •

A list of test instruments that Spacely will control, along with their
appropriate communication interfaces / addresses.

  * •

FPGA bitfiles to be used (for the NI-PXI system)

  * •

Voltage rails and current biases – their nominal values, limit values, and
order of initialization.

###  II-C Write ASIC Test Routines

The second key configuration file, spacely-asic-
config/MyASIC/MyASIC_Routines.py defines test routines which the user wants to
run as Python functions. Any function prefixed by the keyword ”ROUTINE_” can
be called interactively from the main Spacely shell. These routines can
consist of arbitrary Python code, making them extremely flexible, however
Spacely provides convenient idioms to access instrument methods (for example,
changing voltages and currents or taking data from an oscilloscope), send and
receive digital waveforms from the ASIC, and process data.

Figure 3: The core Spacely shell. On startup, Spacely loads the configuration
and routines written for the target ASIC (in this case ”SPROCKET2”) and
prompts the user to initialize appropriate test instruments. Initialization
can also be made automatic with the –defaults flag.

###  II-D Run Tests and Collect Data

When Spacely is run, it references the Master_Config.py file to determine
which ASIC is being targeted. Based on this target specification, it will load
Config and Routines files and initialize the test stand accordingly (Figure
3). (For example, to load the MyASIC_Config.py and MyASIC_Routines.py files,
Master_Config.py would specify TARGET=”MyASIC”). This configuration switch
allows a test engineer to rapidly switch between targeting different ASICs as
necessary.

After initialization, the main Spacely shell is opened. This shell provides
idioms for quickly running routines defined in the loaded Routines file or
monitoring system voltages. It also functions as a Python interpreter,
allowing the user to, for example, change voltage supplies on-the-fly for
quick testing.

When the Spacely shell closes, all test instruments and supplies that were
initialized are automatically turned off.

Figure 4: Verilog-to-Lab flow for using Spacely to test a digital / mixed-
signal ASIC. Responsibility is efficiently divided between design (blue) and
test (green) engineers. sg.pr.run_pattern() is a Spacely provided function
which runs a Glue wave on an ASIC.

##  III Key Features

###  III-A Verilog-to-Lab Flow

Spacely extends the principle of Reuse By Design beyond the realm of test
engineering to ASIC verification. A gap exists between the tools commonly used
for digital ASIC verification or emulation (SystemVerilog testbenches, UVM, or
Cocotb) and those used for test (NI-PXI, logic analyzers, bespoke FPGA
systems), which can create enormous inefficiency and the potential for errors
if the details of an ASIC’s operation and its test conditions are
mistranslated between design and test groups.

Spacely partially bridges these two domains by using Glue Waves. A Glue Wave
is a simple, compressed format for representing arbitrary digital patterns as
a series of integers, in which the binary bits of each integer represent the
values of particular I/Os at a given timestamp. (The name ”Glue” is an
allusion to glue code, which, in software engineering, allows two subsystems
that do not share an API to communicate.) Spacely provides a utility for
generating Glue Waves from Value Change Dump (VCD) files, which are commonly
generated by logic tools, and it provides arbitrary wave generation firmware
for Caribou and NI-PXI that use Glue Waves as both input and output. For
example, in a simple serial interface with a clock (SCK), data-in (SDI), and
data-out (SDO), a digital designer may export the SCK and SDI waves from their
Cocotb testbench, convert the format to a Glue Wave, and send that Glue Wave
to the NI-PXI pattern runner. The pattern runner returns a new Glue Wave which
contains the original SCK and SDI as well as an SDO wave from sampling the
actual ASIC output. The designer can then use tools within Spacely to compare
or graphically present the Glue waves, or extract a logical bitstream from the
wave to verify the ASIC’s correctness.

This process, illustrated in Figure 4, closely involves the digital ASIC
designer in test, ensuring specifications are met. The ASIC test engineer may
focus on the physical test stand design, which is relatively agnostic to the
function of the ASIC. The physical connectivity between the Spacely-driven
wave generator and the ASIC is encoded in an additional configuration file
spacely-asic-config/MyASIC/MyASIC_iospec.txt which contains a simple mapping
of I/O pin numbers to signal names.

For situations where an RTL testbench is not available for a specific
functionality, or when test is driven by a scientist or user rather than a
digital engineer, Spacely also provides utilities to generate glue waves (a)
Natively within Python, as a dictionary containing time-series values for each
signal, or (b) By hand, writing an ASCII file in which signal levels are
represented by 1’s and 0’s. The high productivity and Tinker Friendliness of
Python allows for complex changes to digital control patterns to be made on
the fly.

One caveat to the Glue Wave framework is that feedback is not possible within
a single waveform because the entire waveform is written as a block and cached
by the FPGA prior to receiving the ASIC’s response. However, in practice this
is often not a concern if communication between the ASIC and the test stand
can be separated into transactions. For example, a Glue Wave can be generated
for a SPI read transaction and sent to the ASIC. Then, based on the values of
the data read, Spacely can dynamically generate a new Glue Wave for a SPI
write transaction. In the case where tight feedback coupling is necessary,
custom firmware must be designed. When using Caribou, Spacely provides a
procedure for smoothly integrating this firmware into the test framework,
discussed below.

###  III-B Metadata Tagging

Testing complex mixed-signal ASICs can potentially involve setting dozens or
hundreds of variables, from the levels of voltage and current biases to the
timing of digital control patterns. Recording the values of these variables
and matching them to collected data points is crucial to ensure that results
from testing are provable and repeatable. Spacely simplifies this process by
providing an object-oriented system for metadata tagging through Experiments
and DataFiles.

An Experiment object represents a test routine executed at a particular moment
in time, and metadata attributes can be associated to it with
Experiment.set(”attr”,value). Each experiment contains a collection of
DataFiles, which represent CSV files with arbitrary structure and can also
have metadata attributes set by with DataFile.set(”attr”,value). In the case
where both the experiment and the DataFile have a setting for ”attr”, the
DataFile overrides.

The recommended practice is to write a high-level test routine which defines
the values that each variable will take in a DataFile object, then pass that
DataFile object to a low-level subroutine which will retrieve those variable
values from the DataFile, carry out the appropriate test, and write results
back to the DataFile. The DataFile then serves as an abstract interface
between the two function, and so long as this interface is respected (i.e. no
extra variables are passed along with the DataFile), the DataFile will contain
all the metadata necessary to reproduce the experiment.

When results are written to file, a folder is created with the name of the
Experiment and populated with DataFiles, along with a metadata file which
records the values of metadata for each DataFile and for the experiment as a
whole.

###  III-C Spacely Micro-Shells

In order to support quick experiments, Spacely implements a variety of useful
commands in the shell. In particular, it implements three ”micro-shells” which
can be invoked by typing their name in the main shell. Within each of these
shells, additional commands are available for specific tasks.

The Analysis Shell (ashell) implements basic plotting (histogram, scatter
plot) and data analysis capabilities for DataFiles.

The Glue Converter Shell (gcshell) provides tools for manipulating Glue waves.
The gcshell can be used to plot Glue waves, edit them, change particular bits,
or compare waves against each other.

The I/O Shell (ioshell) provides immediate access to all digital I/Os when
using the NI-PXI hardware. The user can select individual signals and toggle
them manually.

##  IV Spacely Integration with NI-PXI

Spacely integrates with the PXI data acquisition system provided by National
Instruments. NI-PXI power supply and source measurement unit modules (PSUs and
SMUs) are treated as normal voltage/current supplies within the Spacely
framework, and NI FPGAs are used to send arbitrary digital waves to the ASIC
under test.

When the NI-PXI system is used by itself, LabView is used to graphically
create FPGA firmware, which is then compiled to a bitfile either locally or on
NI servers and then flashed to the FPGA. This process requires several LabView
licenses and a lot of processing time, and is generally incompatible with all
three Spacely design principles.

When using Spacely, a single pre-generated bitfile is provided for each
supported FPGA. This bitfile implements a digital arbitrary wave generator,
which can be triggered or stopped using a software API. To communicate with
the ASIC, the Spacely user first generates a Glue Wave in Python, then sends
it to the waveform generator as previously discussed.

Figure 5: Block diagram of the software and firmware used in a Spacely-Caribou
integration.

##  V Spacely Integration with Caribou

Spacely integrates with the Caribou open-source data acquisition platform. The
primary components of Caribou include a ZCU102 Xilinx SoC comprising an
programmable logic fabric (PL) and a processor (PS) running Linux, as well as
the Control-and-Readout (CaR) board, a PCB that provides an array of ADCs,
DACs, and other peripheral devices controlled from the PS over I2C.

Caribou can be used independently of Spacely. In this scenario, a user flashes
an image to the PL, then compiles an instance of Peary, the Caribou system’s
control software (which is also open-source), on the PS. Peary communicates
with the firmware over an AXI bus and controls the CaR board devices using
standard Linux I2C drivers. When integrating with Spacely, the process is
largely the same, with Spacely sending commands to Peary over a TCP/IP
interface as shown in Figure 5, providing a higher level of abstraction and
allowing integration with other test instruments.

Spacely and the ZCU102 can also be used together, independently of the
Control-and-Readout board. In this scenario, the Caribou ADC and DAC channels
are not available, but the digital I/Os of the ZCU102 may be accessed with a
breakout mezzanine.

Unlike NI PXI, there is not one standard firmware bitstream provided for
Spacely-Caribou. Instead, Spacely-Caribou specifies a firmware architecture,
in which all firmware blocks are controlled from a single memory-mapped AXI
bus. A repository of common firmware blocks, spacely-caribou-common-blocks
which all have an AXI peripheral interface, is under development and provided
to the community. Xilinx also provides a rich library of AXI-controlled IP,
including AXI GPIOs and AXI timers. By leveraging these repositories and
Vivado’s automatic connection assistance, a Spacely-Caribou firmware image can
be built simply by dragging and dropping desired blocks into a block diagram,
connecting pins, and synthesizing. Of course, expert users can also contribute
their own firmware blocks.

##  VI Spacely in Practice

Spacely has been used to test ASICs at Fermilab for approximately a year. One
notable example is SPROCKET2, a complex mixed-signal ASIC containing an
experimental ADC. During initial investigation, the ADC displayed substantial
non-linearity in one gain region. Simulation suggested that this could be due
to insufficient settling time in one phase of the ADC’s operation. However,
the ADC was controlled by a complex digital pattern involving ten distinct
signals, so it was unclear where the issue existed.

For this ASIC, the NI-PXI hardware system was used, and the digital control
pattern was generated programmatically as a Python dictionary (eventually
converted into a Glue wave). To debug this issue, the pattern generation was
first parameterized using variable to represent the length of each particular
phase, for example flip1 as shown in Figure 6:

Figure 6: A code snippet from the function that generates the ADC control
pattern for SPROCKET2.

A Spacely Routine was written to vary the lengths of these phases, and record
a full transfer function of the ADC for each variation. For each variation, a
new DataFile was created, and the value of the swept parameter (for example
tflip1) was set as a piece of metadata in that DataFile as shown in Figure 7:

Figure 7: A code snippet from a high-level Spacely routine which creates
DataFiles corresponding to each variation of the selected parameters.

Ultimately, Spacely collected data from 40 transfer functions with $\approx
1,000$ data points each, while the author of this paper went for a coffee that
he very much deserved. When the data collection was complete, the data points
were imported into spacely ashell. The ashell command cancel_linear was used
to remove the linear term from the transfer function, making the nonlinear
terms more obvious, and the mscatter command was used to create a comparative
scatter plot (Figure 8) showing the difference as tflip1 is swept from 1 to
12.

Figure 8: A graph generated using ashell of the transfer function nonlinearity
(ADC codes per mV input) versus tflip1 values from 1 to 12 clock cycles. ”Cryo
R3 XF” refers to the transfer function of Gain Region 3, measured at cryogenic
temperature.

The results (collected and analyzed within Spacely) clearly confirmed that the
length of the flip1 phase has a large effect on the observed nonlinearity.
With tflip1 greater than 5 clock cycles, the primary nonlinear term vanishes,
though a smaller, unrelated nonlinearity persists.

##  VII Conclusion

Spacely provides an open-source, test automation platform for analog, digital,
and mixed-signal ASICs that simplifies the test and analysis process for both
expert and non-expert users.

Within the first year of its use at Fermilab, it has been used in the test of
eight different ASIC designs with diverging interfaces and test
specifications. The use of Spacely has alleviated a testing resource
bottleneck by accelerating the time to get meaningful results: for several
ASICs, key digital functionality was demonstrated within the first day of
testing after receiving the chip. Work is currently underway to expand the
number of Spacely-Caribou test stands in use, and to extend Spacely libraries
to control a larger range of test instruments.

Spacely is a growing open-source project that benefits from community
engagement. Organizations interested in using Spacely in their labs, or in
further developing Spacely code, can find the source code on Github at
https://github.com/SpacelyProject/spacely and documentation at
https://github.com/SpacelyProject/spacely-docs. Spacely is released under an
Apache 2.0 License. Inquiries can be directed to the developers at:
<EMAIL_ADDRESS>
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# Edge AI Empowered Physical Layer Security for 6G NTN: Potential Threats and
Future Opportunities

Hong-fu Chou, Sourabh Solanki, Vu Nguyen Ha, Lin Chen, †Sean Longyu Ma,,
Hayder Al-Hraishawi,, Geoffrey Eappen,, Symeon Chatzinotas,

Corresponding author: Hong-fu Chou Email<EMAIL_ADDRESS>Interdisciplinary Centre for Security, Reliability and Trust (SnT), University
of Luxembourg, Luxembourg
†School of Computer Science, The University of Auckland, New Zealand

###### Abstract

Due to the enormous potential for economic profit offered by artificial
intelligence (AI) servers, the field of cybersecurity has the potential to
emerge as a prominent arena for competition among corporations and governments
on a global scale. One of the prospective applications that stands to gain
from the utilization of AI technology is the advancement in the field of
cybersecurity. To this end, this paper provides an overview of the possible
risks that the physical layer may encounter in the context of 6G Non-
Terrestrial Networks (NTN). With the objective of showcasing the effectiveness
of cutting-edge AI technologies in bolstering physical layer security, this
study reviews the most foreseeable design strategies associated with the
integration of edge AI in the realm of 6G NTN. The findings of this paper
provide some insights and serve as a foundation for future investigations
aimed at enhancing the physical layer security of edge servers/devices in the
next generation of trustworthy 6G telecommunication networks.

###### Index Terms:

6G, NTN, edge AI, edge training, federated learning, deep learning, physical
layer security.

##  I Introduction

The simultaneous development of both artificial intelligence (AI) and edge
computing (EC) [1] is transforming how data is processed, enabling real-time,
localized decision-making and enhancing the efficiency and capabilities of
various applications and industries. In future communication systems, the
integration of AI and EC is expected to be seamless and mutually reinforcing,
where AI and EC complement each other by enabling more efficient data
processing, reducing latency, enhancing privacy, and extending AI capabilities
to the edge of networks. This integration is poised to revolutionize various
industries and applications, from IoT and smart cities to autonomous systems
and telemedicine. Interestingly, by seamlessly integrating AI algorithms with
EC, the concept of Edge Intelligence (EI) emerges. Specifically, EI uses
distributed computing at the network’s periphery to improve service in the
final mile of coverage through the utilization of AI via EC [2]. However,
expanding the boundaries of AI to encompass the network edge presents
significant challenges. These challenges mostly revolve around considerations
related to quality, expense, and security.

The research guidelines in [2] have effectively outlined by categorizing EI
into numerous study ventures, encompassing both “AI for edge” and “AI on edge”
approaches, with the aim of enhancing the quality of experience. In the realm
of EI, security is of paramount importance. One key security aspect involves
leveraging Physical Layer Security (PLS) techniques to fortify the EI network
against eavesdropping and intrusion attempts. Thus, this research study
strives to use and investigate the use cases of EI-empowered PLS in the
context of 6G non-terrestrial networks (NTNs). The concept of PLS has gained
substantial attention as a supplementary measure alongside existing
cryptographic methods at higher network layers. PLS methodologies establish
secure communications at the fundamental physical layer, capitalizing on the
inherent noise and imperfections in wireless communication channels to
intentionally degrade the signal quality received by potential eavesdroppers.
This proactive approach effectively impedes eavesdropping attempts and
safeguards sensitive information within intercepted signals.

However, conventional PLS has limitations including the fact that it relies on
the eavesdropper’s wiretap channel being known in advance and necessitating a
high rate of data to guarantee privacy. The modern techniques revealed for
example that null-space beamforming techniques can be effectively used in
conventional MIMO systems for provisioning of PLS. Therefore, incorporating
PLS with EI emerges as a pivotal avenue of study geared toward enhancing the
security dimension of 6G networks. First, this challenge is solved by the
bottom-up “AI for edge” approach as follows. By establishing a comprehensive
and secure handling resources framework utilizing Signal to Interference and
Noise Ratio (SINR) to effectively identify secure resources, the
aforementioned disadvantage of PLS can be solved by the proposed PLS
architecture corporate with EI presented in the work of [3] to make it more
flexible while designing a key-generating technique in the physical layer that
can handle the loss of reciprocation. Following the thread of this approach,
it is necessary to make a fundamental shift in the architecture of wireless
systems, moving from data-oriented communication to task-oriented
communication, in order to achieve the goal of attaining rapid and credible
information distillation at the edge of the network. Second, more
intriguingly, the top-down decomposition “AI on edge” summarizes the task-
oriented communication and extends its security concerns in [4] major
jeopardized to the edge device by the presence of evasion and Trojan attacks
using adversarial machine learning. The preceding discourse [5] presents the
emergence of secure network design based on EI as a means to offer compelling
substantiation for the feasibility of developing an integrated framework that
is both information-driven and controlled by comprehension, with the goal of
developing and enhancing 6G network security. The authors of the EI network
models conducted by [6] draw inspiration from the field of immunology in order
to develop a quick reaction mechanism for situation awareness across diverse
nodes. This mechanism is designed to counteract attackers that employ actively
evolving assault techniques effectively. Edge AI presents a promising
opportunity for enhancing connected knowledge by enabling the efficient
allocation of transmission resources at the edge of 6G networks. Edge training
and inference [7] possesses the ability to retain privacy while also attaining
the highest level of security and tolerance for faults.

Motivated by the above, the key contribution of this paper lies in its
comprehensive examination of future threats at the physical layer of 6G
networks, within the context of EI network models and edge training modes.
Additionally, we conduct a thorough review of how EI-assisted LPS offers
various research paths aimed at addressing these emerging threats through
well-defined design strategies.

The rest of the paper is structured as follows. In Section II, we discuss the
potential threats to the physical layer of 6G networks under the framework of
EI network models and edge training modes described in [7]. In Section III, we
review how EI-assisted PLS examines research avenues that effectively tackle
these threats by outlining certain design strategies. Finally, the concluding
remarks are presented in Section IV.

##  II Potential Threats to 6G-NTN Physical Layer

The surveys [8] prioritized secure operation within the context of 6G NTNs by
focusing on security metrics from a PLS viewpoint and conducted a comparative
analysis of methods that utilize information-theoretic security techniques,
tactics, and schemes. A comprehensive analysis of current study efforts
dedicated to incorporating PLS into 6G NTN systems, structured according to
three paradigmatic models based on the threats of smart eavesdroppers. An
additional security concern pertains to potential denial-of-service (DoS) and
distributed denial-of-service (DDoS) attacks, wherein adversaries attempt to
disrupt satellite or base-station operations by inundating them with an
excessive volume of spurious messages. Consequently, satellites targeted in
such attacks are compelled to allocate substantial computational resources and
time to process these false messages, thereby diminishing the quality of
service provided to legitimate users. This susceptibility to DOS attacks is
particularly pronounced in the case of LEO satellites due to rather limited
computational resources. In the following, we discuss the potential threats to
the 6G physical layer, summarized in Fig. 1.

Figure 1: Common Attacks to 6G-NTN physical layer

###  II-A Jamming Attacks

Most of the natural attacks in a physical layer can be referred to as
instances when the transmission of valid wireless signals is hindered by the
presence of abnormal or advanced wireless jamming signals. This interference
poses a significant challenge for genuine wireless devices attempting to
decode data sequences. Mallory’s attack as a jammer opts to determine the
sensing threshold for a multicarrier system and selectively interfere with
subcarriers once signals at power ratings exceeding the specified threshold
are detected. In the case of multiple-input multiple-output (MIMO) systems,
reliable channel estimation using pilots and the channel state information
(CSI) are crucial needs for beamforming in MIMO systems which afterward
enables the implementation of precoding techniques. In the event that the CSI
is inaccurately assessed or intentionally manipulated by an adversary known as
Mallory, the precoder could distribute the power in a scattered manner,
leading to possible signal leakage and diminished reliability of the
communication channel. Hence, it is imperative to possess the necessary
capabilities for the identification, localization, and elimination of jammers,
or alternatively, to deploy strategies for mitigating their effects.

###  II-B Spoofing Attacks

The spoofer’s intention is to trick the actual recipient. Spoofing occurs when
a genuine sender of a signal ceases transmitting it to a genuine receiver, at
which point the spoofer begins sending a deceptive signal to the same genuine
recipient by pretending to be the genuine sender. Detection methods and
countermeasures to spoofing attacks are discussed. Attempting to jam the
spoofer in order to avoid such assaults might cause interference with the
other, authentic transceiver in the area due to the scarcity of available
frequency bands in the healthcare domain. To circumvent this issue, the
transmitter can generate a beam to disrupt the spoofing device without
interfering with other transceivers’ communications. To damage the
transmission without really jamming on the other hand, the spoofer needs just
keep sending the transmitter requests again and over. This would cause a
breakdown in communication since both transmitters would be sending the same
signal. It raises some attention to detect spoofing attacks under mobile users
and the frequency-selective fading channels.

###  II-C Backdoor and Adversarial Attacks

Due to its opaque nature, deep neural networks (DNNs) can be tricked into
producing false results via backdoor attacks, in which concealed linkages or
events bypass regular categorization and can be viewed as poisoning attacks.
To attack a target model, attackers can tweak the training dataset, change the
input characteristics, or swap out the labels. This is well-known as a
training stage adversarial attack. In [4], the authors use the first scenario
to show how adversarial attack on task-oriented communications for 6G NTN
networks. The aforementioned phenomenon may be classified as a covert assault,
characterized by its elusive nature since it only targets a possibly limited
subset of training and test samples. This strategy operates by deceiving the
classification process, wherein poisoned test samples in BPSK signal are
misidentified as the intended label in QPSK signal. Moreover, whether it’s
during the gathering of sensing data on the edge device or during sending that
data to the gNode, adversarial attacks can be introduced at the DNN’s input.

###  II-D False Base Station and Impersonation Attack

The unauthorized edge or base station on the periphery of the network could
act as a trusted node and transfer data to other nodes in the network. Replay
by impersonation attacks, in which changed copies of broadcast channels are
rebroadcast, can have catastrophic effects on all network nodes, preventing
them from connecting to the network or forcing them to keep running in a
defective manner. Keys with the properties of mutuality, distinctiveness, and
unpredictability of CSI can be generated using the physical layer key
generation or RF fingerprint approach. Information is transmitted and received
using the same key by both the transmitter and the receiver. However, due to
the dynamic nature of the 6G network, changes in the channel are inevitable
which makes it hard for the device receiving it to tell if a signal is
authentic or not. Therefore, location-based and reverse authentication as an
open research direction can be achieved through the detection of nearby
devices, allowing resistance to these attacks.

##  III Opportunities and Methodologies of EI-aided PLS

Figure 2: A vision of multi-orbit and multi-layer 6G NTN for PLS

With the advent of 6G technology, next-generation multiple access schemes and
multiple antenna techniques emerge the higher dimensional transmission and
drive the application of edge AI. As shown in Fig.2, we present the EI on a
multi-orbit multi-layer NTN as a schematic diagram. The ground station and
edge server transmits via feeder/EI link to LEO, MEO, and GEO satellite. For
the purpose of managing network traffic between user terminals and edge
servers/devices, the ground network is coordinated with network control. The
diverse wireless network of future 6G NTN is enabled by reconfigurable
intelligent surface (RIS), cell-free massive MIMO, AirComp, and massive random
access to comprehend the significance of edge AI and facilitates the
interchange of updates for extremely dimensional frameworks and the adoption
of novel network designs. It is intriguing to examine the current advancements
and explore the possibilities and approaches of edge AI for physical layer
security. In Fig.2, a variety of hackers are illustrated as Eve01 acts as an
attacker satellite, Eve02 acts as a malicious drone and Eve03 acts as a
hacking user. These potential threats can be mitigated and detected by the
following edge AI-empowered PLS design strategies by those green arrows.

###  III-A PLS Design Strategies for Federated Learning

The constraints imposed by restricted bandwidth and privacy for communication
typically render it infeasible to enable all devices at the edge to transmit
their data to a central parameter server for the purpose of centralized
machine learning. The introduction of distributed learning algorithms is
considered advantageous as it allows devices to collaboratively construct a
cohesive learning model through local training and interact with nearby
devices. This leads to federated learning (FL) illustrated in Fig. 3 is seen
as a highly promising paradigm to provide design flexibility and still an open
research direction of the security aspect to elucidate the benefits of edge AI
in relation to PLS concern, for example, the resilience of Byzantine attacks
(i.e., a false edge and impersonation attacks to provide malicious updates to
the central server) With regard to the decentralized blockchain technology for
FL and edge AI for 6G[7], the authors not only provide a concise overview of
the prevailing defensive strategies employed for FL but also a comprehensive
study for EI 6G. Therefore, we distill and summarise the PLS strategies for
edge AI servers as follows:

Figure 3: Edge AI applying federal learning and split deep learning

  * •

To mitigate the backdoor and adversarial attacks, the integration of poison-
awareness detection by features to edge AI and distillability of the edge
model by transfer learning for local edge privacy are crucial. This design
strategy not only assists in verifying an authentic edge server/device but
also enhances the level of privacy of the edge AI model throughout the
communication process. Furthermore, impact-awareness of the edge AI model is
required to delete the training instances at the edge that were tampered with
by malicious users. The impact can be measured by either loss function or
error rate and merging them both.

  * •

As a result of employing the first methodology, the dynamic removal of the
edge node occurs regularly in order to address security concerns. This leads
to a novel framework of federate multitask learning which depicts an outlined
optimization methodology that takes into account the awareness of systems
related to substantial transmission expenses, dawdlers, and tolerance for
defects by using lessons learned from the security concern. This intrigues an
open research topic requires to investigate.

  * •

Trusted execution environment (TEE) is essential to consider the design in FL
for PLS. Static, dynamic, and semi-dynamic trust are measured and profiled by
the metrics of trust function. Leveraging TEE, the authors in [9] offer an
advanced sense of the aforementioned methodologies to proactively protect
privacy by training edge its own data over TEE FL framework and building a TEE
to the layer of edge AI in FL framework.

  * •

For the proactive defense sense, the FoolGold[10] is proposed as an adapting
intelligent methodology for FL by weighting the learning rate of every edge
and learning abnormal gradient iterative updates of edge clusters instead of
specific symptoms and awareness of attacks in order to maintain FL system
performance under a large number of attacks. This approach aims to achieve
equilibrium in dealing with adversaries and serves as a source of inspiration
for the subsequent research topics.

  * •

Novel differential privacy for FL[11] measures the edge privacy to determine
privacy level in relation to additive noise and disclosure of the collection
and analysis of the numerical edge dataset. Beyond a basic static distribution
of power assumption, it is important to note the varying influence of additive
noise on converging and privacy levels. Combining to optimize resource
allocation and edge privacy, further research efforts are necessary to explore
this prospective method, taking into consideration various use cases for PLS
of 6G NTN.

The aforementioned PLS design methodologies can serve as a reliable FL
framework for ensuring the security of 6G NTN based on the architecture of
edge server cooperative inference and co-inference with multiple users[7].
Moreover, it is worth noting that ultra-reliable and low-latency communication
(URLLC) with regard to EI-aided PLS is still an open research challenge of the
tradeoff between security and optimal power/latency. Differential privacy for
FL[11] and FoolGold[10] can be the potential candidates of the remedy that can
be employed to seize this opportunity.

Figure 4: Summary of edge AI empowered PLS

###  III-B Split Deep Learning

Following the design strategy of FL in the PLS sense, the secure model
aggregation concluded in [7] can refer to the PLS mentioned above design
methodologies. In Fig. 3, the authors address that the model split learning of
the secure model aggregation is hence especially appropriate for deep learning
(DL) with a high number of model parameters. In contrast to the data
partition-based training technique, FL necessitates the edge device uploading
of an entire replicated global model at each edge device involved. Despite the
split DL claims that the objective is to maintain privacy while ensuring
computational flexibility, this is achieved by restricting the exchange of
primary information and enabling only edge devices to do basic computing for
the smaller portions of the edge cluster. The challenge of split DL is still
the goal of URLLC with regard to transmission latency within the edge node
with limited computing particularly in the instance of a massive user number
of 6G NTN edge cluster. Therefore, binarized split DL[12] not only reduces the
computation effort for edge device but also provides a methodology to prevent
information leakage during the training process by integrating the strategy of
differential privacy with the interference compensation by offset Laplace
noise. Furthermore, a hybrid split and federal framework is presented in [13]
to analyze the merits based on the case experiment of privacy-awareness and
privacy-oblivious to surpass the split framework. The integration of split
deep learning into the task-oriented joint source-channel coding (JSCC)
framework for 6G NTN holds significant potential. However, further research is
needed to explore the extent of privacy that can be attained in this scenario.
We list but are not limited to several points to investigate further:

  1. 1.

The transition of secrecy rate between edge servers and devices with JSCC can
be examined in the context of differential privacy under an eavesdropping or
aforementioned attack scenario.

  2. 2.

Split DL latency requirement and resilience measurement with fix-point
analysis of task-oriented JSCC framework especially applying binarize scheme
in [12].

  3. 3.

The exploration of various split layers, which are generated in conjunction
with source coding, can be further examined by introducing other design
parameters and privacy level impacts on the reliability of channel coding.

  4. 4.

TEE strategy applies to split DL task-oriented JSCC framework to secure
partial learning process. The privacy level measurement can be discussed to
reveal potential merits.

  5. 5.

Based on the strategies inspired by FoolGold[10], the task-oriented feature
learning enables the potential research direction of malicious feature
learning not only to optimize the resource allocation but also monitor the
malicious activities by sensing the feature vectors in FL framework with edge
split inference.

###  III-C Deep Learning

The previous iteration of edge AI can be directed towards the mobile edge
computing (MEC) network, in light of the rapid advancement of 5G/6G
technology. The evolution is to achieve quicker response times and less power
usage on the edge device, as compared to traditional methods. This is
accomplished by strategically deploying computational access points (CAPs) as
edge servers in close proximity to the data sources. The nearby edge devices
have the capability to delegate a portion of their computing activities to the
nearby CAPs through judicious offloading selections. A secure MEC system for
PLS can be achieved in which a network is susceptible to the presence of a
number of eavesdroppers. These eavesdroppers pose a potential danger to the
process of job offloading. This study proposes an innovative approach that
combines deep reinforcement learning with convex optimization to effectively
determine a suitable remedy for the offloading proportion, while
simultaneously optimizing energy consumption and processing capabilities.
Furthermore, the RIS-aided MEC network for 6G NTN is investigated in [14].
This approach conceals specific contents of the physical layer and offers a
streamlined and efficient means of guaranteeing security at the physical
layer. In addition to facilitating safe transmission, this strategy guarantees
optimal system performance by utilizing deep reinforcement learning techniques
identical to [14]. The physical layer authentication can be beneficial from
edge AI presented in [15] to mitigate spoofing attacks on MEC systems. This
methodology leverages DNNs for the purpose of facilitating multi-user
authentication in order to discern valid edge nodes, hackers, and harmful
nodes without reliance on a predetermined threshold for testing. Furthermore,
multi-user authentication is accomplished by the selection of cross entropy as
the loss function for neural networks and the provision of the vectorization
cost function. The research conducted by [15] demonstrates that the thrilled
experimental findings can be extrapolated to future research endeavors in the
6G NTN environment.

###  III-D Experiment Demonstration

We apply online source code in [12] to exhibit the potential risks in PLS by
demonstrating the privacy leaking impact of the original dataset utilizing
split deep learning. In Fig.5, the convolutional neural networks (CNN) and DNN
are divided into edge server and device separately. The influence of Eves or
hackers on leakage can be assessed using Kullback-Leibler divergence (KL-D)
and shows graphically presented from stimulation at a CNN and DNN split layer
with one localized convolution in the edge device. The learning curve under
information leakage of KL-D is based on training, validation and leakage loss
and is presented in Fig.6 for split CNN and DNN respectively.

Figure 5: The stimulating imagery of privacy measure using split deep learning
in [12]

Figure 6: The accuracy loss and correct ratio using split deep learning in
[12]

##  IV Conclusion

This study offers a comprehensive overview, depicted in Fig. 4, of potential
security risks that possess the capability to inflict damage upon the physical
layer of 6G NTN. The figure illustrates how edge AI-empowered PLS can
facilitate the implementation of protective measures against prospective
risks. The twin rings encircle the main objective of PLS entailing the
deployment of strategic approaches that can be dynamically rotated to defend
against physical layer attacks originating from malicious hackers.
Additionally, we revisit several design methodologies for edge AI that can
effectively prevent these threats. These strategies involve the utilization of
machine learning techniques as well as the implementation of federated
learning approaches for edge nodes of the 6G NTN. The perspectives presented
in this paper offer valuable knowledge and establish a basis for inspiring
research endeavors focused on improving the physical layer security of edge
computing in forthcoming 6G NTN.

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Hong-fu Chou received the M.S. and Ph.D. degree in communication engineering
from National Taiwan University, Taipei, Taiwan in 2006 and 2013,
respectively. He is a Postdoctoral Fellow with the School of Computer Science,
The University of Auckland from 2016 to 2020 and currently with
Interdisciplinary Centre for Security, Reliability and Trust (SnT), University
of Luxembourg.
---
Sourabh Solanki (S’16-M’19) received the B. E. degree in Electronics and
Communication Engineering from Rajiv Gandhi Proudyogiki Vishwavidyalaya,
Bhopal, India, in 2012, the M. Tech. degree in Communication and Signal
Processing, and the Ph.D. degree in Electrical Engineering, both from Indian
Institute of Technology (IIT) Indore,India, in 2015 and 2019, respectively. He
is a Postdoctoral Fellow with Interdisciplinary Centre for Security,
Reliability and Trust (SnT), University of Luxembourg.
---
Vu Nguyen Ha received the Ph.D. degree from the Institut National de la
Recherche Scientifique-Énergie, Matériaux et Télécommunications (INRS-EMT),
Université du Québec, Montréal, Québec, Canada, in 2017. He is currently a
Research Scientist of currently with Interdisciplinary Centre for Security,
Reliability and Trust (SnT), University of Luxembourg.
---
Lin Chen received the B.Eng. and M.Eng. degrees from the Northwestern
Polytechnical University, China, in 2014 and 2017. He is currently pursuing
the Ph.D. degree with the Interdisciplinary Centre for Security, Reliability
and Trust (SnT), University of Luxembourg.
---
Sean Longyu Ma received the M.Eng. degree in integrated circuit engineering
from Shanghai Jiao Tong University, China, in 2016. and the Ph.D. degree in
2023 in computer science with The University of Auckland, New Zealand.,He is a
Lecturer in the School of Computer Science.
---
Hayder Al-Hraishawi (Member, IEEE) received the B.Sc. and M.Sc. degrees in
engineering from the Department of Electrical Engineering with Al-Mustansiriya
University, Baghdad, Iraq, in 2003 and 2006, respectively, and the Ph.D.
degree in electrical engineering from the Department of Electrical and
Computer Engineering, Southern Illinois University Carbondale, USA, in 2017.
He is currently working as a Research Scientist with the Interdisciplinary
Centre, Security, Reliability and Trust, University of Luxembourg.
---
Geoffrey Eappe received the M.S. and Ph.D. degree in Vellore Institute of
Technology University, Indore, India, in 2017 and 2021, respectively. He is a
Postdoctoral Fellow with the Interdisciplinary Centre for Security,
Reliability and Trust (SnT), University of Luxembourg.
---
Symeon Chatzinotas (Fellow, IEEE) is currently Full Professor / Chief
Scientist I and Head of the SIGCOM Research Group at SnT, University of
Luxembourg. He received the M.Eng. degree in telecommunications from the
Aristotle University of Thessaloniki, Thessaloniki, Greece, in 2003, and the
M.Sc. and Ph.D. degrees in electronic engineering from the University of
Surrey, Surrey, U.K., in 2006 and 2009, respectively. He has (co-)authored
more than 400 technical papers in refereed international journals, conferences
and scientific books. He is currently in the editorial board of the IEEE Open
Journal of Vehicular Technology and the International Journal of Satellite
Communications and Networking.
---