# Supplemental Material for
“Strong quantum computational advantage using a superconducting quantum
processor”

Yulin Wu  Hefei National Laboratory for Physical Sciences at the Microscale
and Department of Modern Physics, University of Science and Technology of
China, Hefei 230026, China  Shanghai Branch, CAS Center for Excellence in
Quantum Information and Quantum Physics, University of Science and Technology
of China, Shanghai 201315, China  Shanghai Research Center for Quantum
Sciences, Shanghai 201315, China  Wan-Su Bao  Henan Key Laboratory of Quantum
Information and Cryptography, Zhengzhou 450000, China  Sirui Cao  Fusheng Chen
Ming-Cheng Chen  Hefei National Laboratory for Physical Sciences at the
Microscale and Department of Modern Physics, University of Science and
Technology of China, Hefei 230026, China  Shanghai Branch, CAS Center for
Excellence in Quantum Information and Quantum Physics, University of Science
and Technology of China, Shanghai 201315, China  Shanghai Research Center for
Quantum Sciences, Shanghai 201315, China  Xiawei Chen  Shanghai Branch, CAS
Center for Excellence in Quantum Information and Quantum Physics, University
of Science and Technology of China, Shanghai 201315, China  Tung-Hsun Chung
Hui Deng  Hefei National Laboratory for Physical Sciences at the Microscale
and Department of Modern Physics, University of Science and Technology of
China, Hefei 230026, China  Shanghai Branch, CAS Center for Excellence in
Quantum Information and Quantum Physics, University of Science and Technology
of China, Shanghai 201315, China  Shanghai Research Center for Quantum
Sciences, Shanghai 201315, China  Yajie Du  Shanghai Branch, CAS Center for
Excellence in Quantum Information and Quantum Physics, University of Science
and Technology of China, Shanghai 201315, China  Daojin Fan  Ming Gong  Cheng
Guo  Chu Guo  Shaojun Guo  Lianchen Han  Hefei National Laboratory for
Physical Sciences at the Microscale and Department of Modern Physics,
University of Science and Technology of China, Hefei 230026, China  Shanghai
Branch, CAS Center for Excellence in Quantum Information and Quantum Physics,
University of Science and Technology of China, Shanghai 201315, China
Shanghai Research Center for Quantum Sciences, Shanghai 201315, China  Linyin
Hong  QuantumCTek Co., Ltd., Hefei 230026, China  He-Liang Huang  Hefei
National Laboratory for Physical Sciences at the Microscale and Department of
Modern Physics, University of Science and Technology of China, Hefei 230026,
China  Shanghai Branch, CAS Center for Excellence in Quantum Information and
Quantum Physics, University of Science and Technology of China, Shanghai
201315, China  Shanghai Research Center for Quantum Sciences, Shanghai 201315,
China  Henan Key Laboratory of Quantum Information and Cryptography, Zhengzhou
450000, China  Yong-Heng Huo  Hefei National Laboratory for Physical Sciences
at the Microscale and Department of Modern Physics, University of Science and
Technology of China, Hefei 230026, China  Shanghai Branch, CAS Center for
Excellence in Quantum Information and Quantum Physics, University of Science
and Technology of China, Shanghai 201315, China  Shanghai Research Center for
Quantum Sciences, Shanghai 201315, China  Liping Li  Shanghai Branch, CAS
Center for Excellence in Quantum Information and Quantum Physics, University
of Science and Technology of China, Shanghai 201315, China  Na Li  Shaowei Li
Yuan Li  Futian Liang  Hefei National Laboratory for Physical Sciences at the
Microscale and Department of Modern Physics, University of Science and
Technology of China, Hefei 230026, China  Shanghai Branch, CAS Center for
Excellence in Quantum Information and Quantum Physics, University of Science
and Technology of China, Shanghai 201315, China  Shanghai Research Center for
Quantum Sciences, Shanghai 201315, China  Chun Lin  Shanghai Institute of
Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China  Jin
Lin  Haoran Qian  Hefei National Laboratory for Physical Sciences at the
Microscale and Department of Modern Physics, University of Science and
Technology of China, Hefei 230026, China  Shanghai Branch, CAS Center for
Excellence in Quantum Information and Quantum Physics, University of Science
and Technology of China, Shanghai 201315, China  Shanghai Research Center for
Quantum Sciences, Shanghai 201315, China  Dan Qiao  Shanghai Branch, CAS
Center for Excellence in Quantum Information and Quantum Physics, University
of Science and Technology of China, Shanghai 201315, China  Hao Rong  Hong Su
Lihua Sun  Hefei National Laboratory for Physical Sciences at the Microscale
and Department of Modern Physics, University of Science and Technology of
China, Hefei 230026, China  Shanghai Branch, CAS Center for Excellence in
Quantum Information and Quantum Physics, University of Science and Technology
of China, Shanghai 201315, China  Shanghai Research Center for Quantum
Sciences, Shanghai 201315, China  Liangyuan Wang  Shanghai Branch, CAS Center
for Excellence in Quantum Information and Quantum Physics, University of
Science and Technology of China, Shanghai 201315, China  Shiyu Wang  Dachao Wu
Yu Xu  Hefei National Laboratory for Physical Sciences at the Microscale and
Department of Modern Physics, University of Science and Technology of China,
Hefei 230026, China  Shanghai Branch, CAS Center for Excellence in Quantum
Information and Quantum Physics, University of Science and Technology of
China, Shanghai 201315, China  Shanghai Research Center for Quantum Sciences,
Shanghai 201315, China  Kai Yan  Shanghai Branch, CAS Center for Excellence in
Quantum Information and Quantum Physics, University of Science and Technology
of China, Shanghai 201315, China  Weifeng Yang  QuantumCTek Co., Ltd., Hefei
230026, China  Yang Yang  Shanghai Branch, CAS Center for Excellence in
Quantum Information and Quantum Physics, University of Science and Technology
of China, Shanghai 201315, China  Yangsen Ye  Hefei National Laboratory for
Physical Sciences at the Microscale and Department of Modern Physics,
University of Science and Technology of China, Hefei 230026, China  Shanghai
Branch, CAS Center for Excellence in Quantum Information and Quantum Physics,
University of Science and Technology of China, Shanghai 201315, China
Shanghai Research Center for Quantum Sciences, Shanghai 201315, China
Jianghan Yin  Shanghai Branch, CAS Center for Excellence in Quantum
Information and Quantum Physics, University of Science and Technology of
China, Shanghai 201315, China  Chong Ying  Jiale Yu  Chen Zha  Cha Zhang
Hefei National Laboratory for Physical Sciences at the Microscale and
Department of Modern Physics, University of Science and Technology of China,
Hefei 230026, China  Shanghai Branch, CAS Center for Excellence in Quantum
Information and Quantum Physics, University of Science and Technology of
China, Shanghai 201315, China  Shanghai Research Center for Quantum Sciences,
Shanghai 201315, China  Haibin Zhang  Shanghai Branch, CAS Center for
Excellence in Quantum Information and Quantum Physics, University of Science
and Technology of China, Shanghai 201315, China  Kaili Zhang  Yiming Zhang
Hefei National Laboratory for Physical Sciences at the Microscale and
Department of Modern Physics, University of Science and Technology of China,
Hefei 230026, China  Shanghai Branch, CAS Center for Excellence in Quantum
Information and Quantum Physics, University of Science and Technology of
China, Shanghai 201315, China  Shanghai Research Center for Quantum Sciences,
Shanghai 201315, China  Han Zhao  Shanghai Branch, CAS Center for Excellence
in Quantum Information and Quantum Physics, University of Science and
Technology of China, Shanghai 201315, China  Youwei Zhao  Hefei National
Laboratory for Physical Sciences at the Microscale and Department of Modern
Physics, University of Science and Technology of China, Hefei 230026, China
Shanghai Branch, CAS Center for Excellence in Quantum Information and Quantum
Physics, University of Science and Technology of China, Shanghai 201315, China
Shanghai Research Center for Quantum Sciences, Shanghai 201315, China  Liang
Zhou  QuantumCTek Co., Ltd., Hefei 230026, China  Qingling Zhu  Chao-Yang Lu
Cheng-Zhi Peng  Xiaobo Zhu  Jian-Wei Pan  Hefei National Laboratory for
Physical Sciences at the Microscale and Department of Modern Physics,
University of Science and Technology of China, Hefei 230026, China  Shanghai
Branch, CAS Center for Excellence in Quantum Information and Quantum Physics,
University of Science and Technology of China, Shanghai 201315, China
Shanghai Research Center for Quantum Sciences, Shanghai 201315, China

##  I Quantum processor design and fabrication

We designed a state of the art programmable quantum processor, consists of 66
Transmon Koch  _et al._ (2007) qubits in a two-dimensional array, with another
110 Transmon qubits as couplers for adjustable coupling between neighboring
qubits, as illustrated in Fig. 1 in the main text. The 66 qubits are divided
into 11 groups, with 6 qubits in a group sharing a readout Purcell filter
Jeffrey  _et al._ (2014). Taking advantage of the flip-chip technology, all
qubits and couplers are placed on the same layer, and all readout and control
lines are on the other layer. Each qubit is controlled by an control line
which combines both microwave drive (XY control) and flux bias (Z control),
and capacitively coupled to a quarter wave resonator which is coupled to a
Purcell filter for dispersive readout. The qubit-qubit coupling of nearest-
neighbor qubits are contributed by two parts: direct capacitive coupling and
indirect coupling through the coupler. Each coupler has an individual flux
bias line, with which the effective qubit-qubit coupling strength can be tuned
from $\sim+5\text{MHz}$ to $\sim-50\text{MHz}$ by changing the coupler
frequency. The two-qubit gates are implemented with a coupling strength of
about $10\text{MHz}$.

Our quantum processor consists of two separate chips, the top chip and the
bottom chip. High purity aluminum thin film are grown on sapphire substrate by
molecular beam epitaxy (MBE) for both chips Megrant  _et al._ (2012). Control
and readout circuits are fabricated on the bottom chip using optical
lithography. To suppress crosstalk, airbridges are fabricated to shield
critical circuits Dunsworth  _et al._ (2018). 66 qubits and 110 adjustable
couplers are fabricated on the top chip using an aluminum evaporation and
lift-off process. After dicing and testing, the two separated chips are bonded
together with indium bumps Foxen  _et al._ (2017); Rosenberg  _et al._ (2017).
After chip fabrication, the processor is wire-bounded to a printed circuit
board inside a sample box with gold-plated shielding inside and $\mu-$metal
shielding outside. Finally, the packaged processor is mounted to the cold
plate of a dilution refrigerator and connected to room temperature electronics
through alternators, filters and amplifiers.

##  II Experimental setup

The experimental wiring setup for qubit/coupler controls and frequency-
multiplexed readouts is shown in Fig. S1. The control and readout signals are
generated by digital-to-analog converters (DAC) at room temperature, then
attenuated by a series of attenuators and filtered by several low-pass
filters.

In order to improve the signal-to-noise ratio of the readout signal, we use
the Josephson parametric amplifier (JPA) for the first stage amplification at
base temperature. Then the readout signal is amplified by a high-electron
mobility transistor (HEMT) amplifier at the 4 K stage and further amplified by
a room-temperature amplifiers after getting out of the dilution refrigerator.

The room temperature electronic equipment in this experiment includes 330 DAC
channels, 11 ADC modules, 11 DC channels and 34 microwave source channels.

Figure S1: The schematic diagram of control electronics and wiring. Each qubit
has a XY control line and and a Z control line, which are combined together
via a bias tee before connected to the quantum processor. In the dilution
refrigerator, attenuators and filters are installed at various stages to
reduce noise. Josephson parametric amplifiers (JPA) , high electron mobility
transistors (HEMT) and room-temperature amplifiers are used to amplify the
readout signals. At room temperature, digital-to-analog converters (DAC),
microwave sources and mixers are used to generate pulses for qubit XY control,
readout probing pulses and JPA pump. Qubit Z and coupler control pulses are
also generated by DACs. DC sources are used to provide the flux bias of JPAs.
The readout signals amplified by the room-temperature amplifiers are digitized
and demodulated by ADC modules.

##  III Gate and Readout Calibration

###  III.1 Part1: Rough calibration on 66 qubits

####  III.1.1 Basic Calibration

After cooling down, we perform basic calibrations to determine whether the
processor can work properly, this process involves all 66 qubits, 110
couplers, 66 readout resonators and 11 JPAs. The calibration procedure is
listed bellow.

  * •

Identify the the readout resonator frequency for each qubit, measure the
dispersive frequency shift and measure its dependency with the qubit flux
bias.

  * •

Find a JPA DC bias, pump frequency and pump power configuration that produces
high signal-to-noise ratio for the corresponding readout signals.

  * •

Measure the response of readout resonator versus coupler bias, then bias the
coupler to a safe point where coupling strength of neighboring qubits is
small, $\sim+5$MHz typically.

  * •

Run Rabi experiments to calibrate $\pi$ and $\pi/2$ pulse amplitudes.

  * •

Perform coarse readout calibration to improve readout fidelity by optimizing
readout frequency, length and amplitude.

  * •

Tune coupler bias to minimize the qubit-qubit coupling via $|10\rangle$ \-
$|01\rangle$ swap experiment.

  * •

Perform qubit spectroscopy measurements and extract the mapping between the
qubit bias amplitude and the qubit frequency.

  * •

Measure $T_{1}$, $T_{2}$ versus qubit frequency.

  * •

Measure the step response of the bias control line to characterize the Z pulse
distortion by running a Ramsey experiment Yan  _et al._ (2019).

  * •

Perform XY-crosstalk measurement.

  * •

Synchronise the timing between the qubit microwave drive, qubit bias, and
coupler bias.

As qubit idle frequency arrangement and coupling between qubits are not yet
optimized at this stage, we typically divide the qubits into 2 groups and
couplers into 4 groups for some calibration experiments, calibration for each
group are performed in parallel. Basic calibration results indicates that the
quantum processor can work properly and we proceed to optimize the frequency
arrangement with the coherence and XY-crosstalk data. There are three types of
operating frequencies: idle, interaction and readout. When optimizing the
frequency arrangement, we have to consider the following factors: coherence,
two-level-system (TLS), residual coupling between qubits, XY-crosstalk and Z
pulse distortions.

After the optimal operating frequencies are determined, we proceed to
calibrate and optimize single-qubit gate, readout and two-qubit gate
parameters in parallel.

####  III.1.2 Readout, Single-Qubit Gate and Two-Qubit Gate Calibration

i. Single-Qubit Gate Calibration

The optimized idle frequency arrangement is displayed in Fig. S4(a). We set
all qubit idle frequencies to the target idle frequencies by adjusting qubit
flux biases. Next, we turn off the qubit-qubit coupling by adjusting the
coupler flux bias. Then we fine tune the XY drive pulse amplitudes, pulse
shaping parameters of the cosine-envelop microwave of 25ns length. Finally, we
benckmark the fidelities of single qubit gates with single-qubit cross-entropy
benchmarking (XEB) Arute  _et al._ (2019).

Gate errors of some qubits are still too high($\textgreater 0.3\%$) for the
random quantum circuit benchmarking tasks after this first round of
calibration. For these qubits, we measure XEB gate fidelity versus idle
frequencies around initial idle frequency and choose a new optimal idle
frequency.

After the above calibration procedure, we obtained high fidelity single-qubit
gates with an average XEB pauli error 0.14% when applied simultaneously.
Complete XEB pauli error data of each single-qubit gates are shown in Fig.
S2(a).

ii. Readout Calibration

To improve readout fidelity and reduce readout crosstalk, we set the qubit
readout frequencies to a different frequency arrangement optimized for
readout, which is displayed in Fig. S4(e). At this new frequency setting, we
rerun the basic readout calibrations to optimize readout frequency, length and
amplitude. After this calibration procedure, the readout error is mainly
limited by qubit relaxation. To reduce the influence of the relaxation, we
enhance the effective qubit lifetime by driving the qubit to higher levels
during the readout Elder  _et al._ (2020).

We calibrate the readout fidelities by preparing all qubits at
$|0\rangle(|1\rangle)$ and count the events of successfully identify the
readout result as $|0\rangle(|1\rangle)$. Simultaneous readout error of
$|0\rangle$ and $|1\rangle$ are 3.46% and 6.08% respectively, average readout
fidelity is 95.23%, as shown in Fig. S2(b).

We also compare the fidelity results with that obtained from preparing the
qubits at random bit strings as a sanity check. The results of random bit
string measurement show that identification error of a single qubit has
increased by an average of $0.14\%$ and the 56-qubit state readout fidelity is
lower with a factor of $0.93$. This factor is used to correct the estimated
fidelities in the random quantum circuit benchmarking tasks.

Figure S2: Single-qubit gate pauli error $e_{1}$, two-qubit gate pauli error
$e_{2}$ and readout error $e_{r}$ of the 66 qubits and 110 couplers of the
Zuchongzhi processor. Figure S3: The relaxation time $T_{1}$ and dephasing
time $T_{2}^{*}$ of the 66 qubits of the Zuchongzhi processor. Figure S4: The
typical distribution of 66-qubit parameters over the Zuchongzhi processor.

iii. Two-Qubit Gate Calibration

The two-qubit gate of our experiment, the iSWAP-like gate Arute  _et al._
(2019), is realized by tuning the two qubits from their idle frequencies into
resonance and turning on the coupling. Considering the effects of decoherence
and leakage, we set the total time duration of the iSWAP-like gates to 32ns,
which includes the pulse rise/fall time of 3ns and interaction time of 26ns.
With this setting, we finely calibrate the detuning of the two qubits and the
coupling strength of the corresponding coupler to obtain a full swap from one
qubit to another. After that, we optimize the interaction time in order to
minimize leakage to higher energy levels. We generally perform these
calibration steps iteratively until the parameters converge, typically within
two or three iterations.

After the calibration of iSwap-like gate paramegters, we benchmark gate
performance with XEB. Unlike single qubit gates, iSwap-like gates are
parameterized gates each with four parameters as described by the unitary
model in the main text, with the experimental results of XEB and the generic
unitary model, we learn these parameters through an optimization process to
maximize the overall fidelity of XEB. With the optimized parameters, we fit
the final XEB error and speckle purity benchmarking(SPB) errorArute  _et al._
(2019). We obtained high fidelity two-qubit gates with an average XEB pauli
error 0.76% over all 110 couplers when applied simultaneously, which is shown
in Fig. S2(c).

###  III.2 Part2: Fine-tune on 56 qubits

Figure S5: The qubit interaction frequencies of the 94 two-qubit gate of the
56 selected qubits.

After rough calibrations on 66 qubits, we can estimate the XEB fidelity of a
specific quantum circuit with $n$ qubits and $m$ cycles according to Eq. S4.
For random quantum circuit sampling, as the circuit scale increases its
fidelity decreases, a large number of samples is required to ensure the
uncertainty of the fidelity is much less than the fidelity itself in case of
low fidelity. As a trade-off between number of samples and sampling time, we
only compile our random circuit sampling tasks to a subset of the processor of
up to 56 qubits. We achieved 56-qubit 20-cycle random circuit sampling, an
intractable task for classical simulation, within an acceptable sampling time.

To switch from the 66-qubit pattern to the 56-qubit pattern, we just turn off
the couplings between the selected qubits and the unused qubits. Then, we
recalibrate the readout, single-qubit gate and two-qubit gate parameters. In
addition, for the qubits on which two-qubit XEB pauli error is higher than
1.5%, we sweep their SPB fidelities at a fixed depth of 20 cycles with 70
random circuit instances at different interaction frequencies to optimize the
two-qubit gate fidelities. The best interaction frequencies of the 94 two
qubit gates are illustrated in Fig. S5. Finally, we use per-layer simultaneous
two-qubit gate XEB to benchmark the gate errors Arute  _et al._ (2019).

After all the calibrations and optimizations, the average readout error is
4.52%, the average XEB pauli errors of sinlge-qubit gates and two-qubit gates
are 0.14% and 0.59%, respectively, as illustrated in Fig. 2 in the main text.

###  III.3 Summary of system parameters

The system parameters of our quantum processor are summarized in Table S1.

Parameters |  Median |  Mean |  Stdev. |  Figure
---|---|---|---|---
Qubit maximum frequency (GHz) |  4.811 |  4.809 |  0.096 |  Fig. S4
Qubit idle frequency (GHz) |  4.653 |  4.653 |  0.095 |  Fig. S4
Qubit anharmonicity (MHz) |  -246.5 |  -248.2 |  5.3 |  Fig. S4
Qubit readout frequency (GHz) |  4.400 |  4.083 |  0.492 |  Fig. S4
Readout drive frequency (GHz) |  6.409 |  6.407 |  0.103 |  Fig. S4
$T_{1}$ at idle frequency ($\mu$s) |  30.8 |  30.6 |  7.1 |  Fig. S3
$T_{2}^{*}$ at idle frequency ($\mu$s) |  5.1 |  5.3 |  2.7 |  Fig. S3
66-qubit readout $e_{r}$ (%) |  4.52 |  4.77 |  1.35 |  Fig. S2
66-qubit 1Q XEB $e_{1}$ (%) |  0.14 |  0.14 |  0.05 |  Fig. S2
66-qubit 2Q XEB $e_{2}$ (%) |  0.67 |  0.76 |  0.43 |  Fig. S2
56-qubit readout $e_{r}$ (%) |  4.50 |  4.52 |  1.43 |  Fig. 2(main)
56-qubit 1Q XEB $e_{1}$ (%) |  0.13 |  0.14 |  0.05 |  Fig. 2(main)
56-qubit 2Q XEB $e_{2}$ (%) |  0.53 |  0.59 |  0.20 |  Fig. 2(main)
Table S1: Summary of system parameters.

##  IV Software System

A 66-qubit superconducting quantum processor is a high-dimensional, highly
constrained analogy system with system parameters susceptible to environmental
changes and often drifts with time, to execute high fidelity quantum circuits,
more than 400 DAC, ADC, microwave source and DC source channels need to be
controlled with cutting edge precision. Operating such a complex quantum
system requires considerable advancement in software as compared to operating
small quantum systems. We have developed a software system for intermediate
scale superconducting quantum systems called QOS(Quantum Operating System)
that is capable of operating quantum systems of more than 1000 qubits.

Figure S6: Software architecture. The QOS system consists of four major
modules, the Hardware module , the Kernel module, the Routine module and the
Service module. Other supporting modules are not shown.

The major functionalities of QOS are abstract away hardware details, manage
resources and implement quantum operations. The first two functionalities are
similar to that of a classical computer operating system, the last is unique
to a quantum operating system.

As mentioned before, a large scale quantum processor is a complicated system,
directly managing such a complex system is intractable for experiment users,
the QOS system abstract away system details and manages all the resources for
the user. Resources of a quantum computer system includes hardware and
software. We categorize hardware into two categories, classical hardware and
quantum hardware. Classical hardware includes DAC, ADC, microwave source, DC
source and all other control electronics, quantum hardware includes the
quantum processor and the quantum amplifiers. To mange all the resources, QOS
manages a registry system to represent and keep track of the
settings/configurations of all the resources. The registry is organized in a
tree structure and holds all the settings of the classical hardware, quantum
hardware and software configurations. Each user maintains independent registry
settings for their own experiments. About 20k entries of registry settings are
used to run the quantum processor in this work.

Fig. S6 shows the basic architecture of the the QOS system, it consists of
four major modules, the Hardware module, the Kernel module, the Routine module
and the Service module. Other supporting modules includes the Data Storage
module, the Registry module, the Waveform module and the Utility module etc.
Most of the software components are abstractions of the hardware system
components.

The Hardware module hosts a library of drivers of classical hardware, on top
of this, a hardware abstraction layer(HAL) is introduced to provide an unified
API for the Kernel module to interface with hardware, making upper stream
modules hardware model agnostic and can be adapted to hardware provided by
differ vendors with minimum effort. Mock drivers are also provided to
facilitate off-line testing without real hardware.

Unlike a classical processor, on which all the basic computing units like
logical gates and registers are hardware components, a superconducting quantum
processor is just a physical quantum system, all computing units like quantum
gates and quantum registers have to be implemented by software. The most
essential functionality of a quantum software system is to implement quantum
operations and transform a quantum physical device into a quantum computing
processor. This is done by the Kernel module and makes it the most important
module. The Kernel module is an abstraction of the physical system, including
the quantum processor device and the controlling electronics, it consists of
the following sub-modules, the Quantum Processor(QPU), the Hardware Adapter,
the User and the QThread.

Controlling superconducting qubits to implement high fidelity quantum gates is
a complex task, when the system size scales up, the requirement on software
performance is very demanding. To be scalable, the software system has to be
able parse quantum operations in parallel. Entanglement is an intrinsic
feature of a quantum system, implement parallel operation on an entangled
system is a non trivial task. We use the Actor Model Hewitt  _et al._ (1973)
for the implementation of the kernel module. Each hardware component is
modeled as an actor, called Agent with those representing quantum components
called QAgent in particular, types of agent used in this work are listed
below:

  * •

Transmon, of the QAgent class, each represents a Transmon Koch  _et al._
(2007) type or Transmon type compatible qubit, responsible for managing all
the settings of the qubit and implementing single qubit quantum operations.

  * •

TTG, tunable coupler of the Transmon qubit as used on the Zuchongzhi
processor, responsible for managing all the settings of the coupler and
implementing two qubit quantum operations.

  * •

MuxReadout, represents a multiplexed qubit state readout unit.

  * •

IMPA, represents an impedance matched parameter amplifier Mutus  _et al._
(2014).

  * •

QProcessor, a controlling agent of all the agents, including qubits, couplers,
readouts, amplifiers, hardware manager etc.

  * •

Hardware Adapter, represents one piece of classical hardware, DAC, ADC,
microwave source etc.

  * •

Hardware Manager, a controlling agent of all the classical hardware agents.

  * •

QThread, a software abstraction that represents a quantum thread or quantum
process on a quantum processor.

  * •

User, a software abstraction that is responsible for managing user specific
resources, conducting user transactions like authentication and authorization
etc.

Opcode | Example | Meaning
---|---|---
SET | SET Q01 2 3.14 | Set value of the selected setting entry of index 2 of Q01 to 3.14
CMT | CMT Q01 0 | Commit settings change, waveforms regenerated, caches refreshed etc.
|  | Example: commit settings change of type 0 for Q01
I | I Q01 50 | Idle gate. Example: Q01 idle for time duration 50
X, Y, Z | X2M Q01 | XY gates. Example: -X/2 gate on Q01
X2P, X2M, Y2P, Y2M |  |
H | H Q01 | H gate
XY | XY Q01 0.785 |  $\pi$ rotation around the axis of azimuth 0.785 rad in the XY plane
XY2P, XY2M | XY2P Q01 0.785 |  $+\pi/2$($-\pi/2$) rotation around the axis of azimuth 0.785 rad
| XY2M Q01 0.785 | in the XY plane
X12 | X12 Q01 |  $|1\rangle\leftrightarrow|2\rangle$ driving gate
X23 | X23 Q01 |  $|2\rangle\leftrightarrow|3\rangle$ driving gate
Z | Z Q01 | Z gate on Q01
S, SD | SD Q01 |  $S$, $S^{\dagger}$ gate
T, TD | T Q01 |  $T$, $T^{\dagger}$ gate
RX, RY, RZ | RY Q01 0.785 | Arbitrary rotation around the X, Y or Z axis with the specified angle
RXY | RXY Q01 0.785 3.14 | Q01 rotation of 3.14 rad around the the axis of azimuth angle 0.785
|  | in the XY-plane
AXY | AXY Q01 20 0.75 0.785 -1e6 0.55 | Arbitary XY rotation. Example: Q01 arbitrary rotation around the the axis of
|  | azimuth angle 0.785 in the XY-plane with pulse length 20,
|  | pulse amplitude 0.75, -1e6 detuning and 0.55 DRAG alpha
CZ, CNOT, SWP, ISWP | CZ G0701 | Two qubit gates. Example: CZ gate on coupler G0701
SISWP |  |
CP, FSIM | FSIM G0701 1 | Parameterized two qubit gates, with an index to indicate which
|  | parameter set to use. Example: FSIM gate of index 1 on coupler G0701
DTN | DTN Q01 100 -2e6 0 | Detune Q01 -2e6MHz for a duration 100 at time offset 0
MEASURE, M | M Q01 | Measure qubit Q01
PLS, PLSXY | PLS Q01 1 100 10 0.8 0 0 1 | Put a pulse of a waveform index 1 at time 100 with the specified
|  | parameters for Q01
B | B Q01 R01 | Establish a time barrier between Q01 and R01
SWD, SWA | SWA Q01 0.8 | SET work bias duration, amplitude. The work bias amplitude
|  | determines $f_{01}$
MOV, … | MOV G0701 0 1 | Classical instructions. Example: set value 1 to classical register 0 of G0701
Table S2: Quantum Control Instruction Set (QCIS)

By introducing the concept of agent, we decouple the highly entangle quantum
processor as well as the shared classical controlling electronics into a
collections of separated components, with all the entanglement resolved by the
related agents and transparent to upper stream modules. We use a highly
decentralized architecture for the agents, all agents function concurrently
and directly communicate with each other when necessary. For the only tow
central agents, the QProcessor and the Hardware Manager, they only assume
minimum light weighted functionalities like instruction dispatching and
synchronization to avoid any performance bottle neck. With this architecture,
we can process large scale complex quantum operations in a fully concurrent
manner, pushing software performance to its limits.

Multi-processing or multi-threading is supported through QThread, one can run
multiple experiments concurrently, new experiments can be created and executed
immediately without waiting for previous experiments to finished. When an
experiment is started, typically one QThread is created with a new context
holding a view of the registry and other dynamic settings in each involved
QAgent, exposing only a few selected setting entries to be dynamically set for
parameter sweeping. Tasks of this experiment is configured with settings from
these contexts and executed through time slicing with other QThreads with
round-robin scheduling. Several QThreads operating upon distinct agent sets
can be configured to run simultaneously to save hardware time. A QThread will
go into hibernation after idling for some time to yield resources, and will be
awakened upon arrival of new tasks. Multi-user is also support through user,
multiple users can run experiments concurrently with completely different
settings. QOS works in a server-client mode, a dedicated RPC(Remote Procedure
Call) framework is developed for users to interface with QOS, web service and
cloud service are also supported.

We introduce the Quantum Control Instruction Set(QCIS) for the full control of
a superconducting quantum processor as list in table S2. QCIS offers a unified
API for operating a quantum processor, with QCIS, we can control the
Zuchongzhi system exactly the same way as programming a classical computer.
Program written with QCIS are called QProgram. All experiments in this work
are implemented with this instruction set. As an example, sweep with the
following code snippet executes a tuning of all the iSWAP-like gate related
parameters for a swap experiment on G0701, the TTG QAgent between qubits Q01
and Q07:

⬇

SET G0701 0 30 // set FSIM gate duration to 30*

SET G0701 1 6 // set qubit pulse rise/fall edge duration to 6

SET G0701 2 2 // set coupler pulse rise/fall edge duration to 2

SET G0701 3 -10e6 // set FSIM gate qubit_0 detune to -10e6

SET G0701 4 20e6 // set FSIM gate qubit_1 detune to 20e6

SET G0701 5 15e6 // set coupler coupling strength to 15e6

MOV G0701 0 1 // set value 1 to classical register 0 to indicate that the

// index of the FSIM gate for the following CMT action is 1

CMT G0701 0 // commit settings change, waveforms will be regenerated,

// caches refreshed etc.

X Q07 // X gate on Q07

FSIM G0701 1 // execute the FSIM gate indexed 1 on G0701**

B Q07 Q01 // establish a time barrier before measurement

B Q07 R01 // establish a time barrier before measurement

M Q07 // measure Q07

M Q01 // measure Q01

/*

*: at the creation of QThread, related setting entries are selected and indexed

**: a coupler can implement multiple FSIM gates of different parameters

*/

The following QProgram executes one of the random circuit sampling task in
this work:

⬇

X2P Q01

Y2P Q02

X2P Q03

Y2P Q04

XY2P Q07 0.785398163397448

X2P Q08

Y2P Q09

XY2P Q10 0.785398163397448

X2P Q11

XY2P Q12 0.785398163397448

XY2P Q13 0.785398163397448

X2P Q14

XY2P Q15 0.785398163397448

X2P Q16

XY2P Q17 0.785398163397448

XY2P Q19 0.785398163397448

X2P Q20

XY2P Q21 0.785398163397448

XY2P Q22 0.785398163397448

Y2P Q23

XY2P Q25 0.785398163397448

XY2P Q26 0.785398163397448

// ... 30 lines not shown

XY2P Q61 0.785398163397448

XY2P Q62 0.785398163397448

Y2P Q63

Y2P Q64

FSIM G1003 1

FSIM G1104 1

FSIM G1408 1

FSIM G1509 1

// ... 1809 lines not shown

M Q50

M Q51

M Q52

M Q53

M Q55

M Q56

M Q57

M Q58

M Q59

M Q61

M Q62

M Q63

M Q64

The Routine module is a standard library of quantum experiments, implemented
mainly for bringing up a superconducting quantum processor. Basic routines are
called Samplers. A sampler creates a QThread, provides a task generator for
the QThread which then throttles tasks to QPU to be executed. Measured results
are send back as an asynchronous stream, which can be subscribed by data
handlers to do data processing on the fly. Data handlers could be simple data
saving routines, data visualizers or sophisticated pattern recognition
routines in data analyzers of a calibrator. All samplers except a few special
cases are implemented to run experiments for multiple QAgents in parallel.
Upon samplers, calibrators are build to implement a specific calibration task,
a calibrator builds one or several samplers with parameters like sweep ranges
defined by the specific calibration task, run the sampling tasks, analyze the
sampled data and generate a calibration result CalResult for each of its
calibration target. The calibration results are then validate by one or
several Validators to check whether they are solid. On top of calibrators, a
Calibration Controller manages all the calibrators and schedules then to run
in a specific scheme, collects calibration results from different calibrators,
render results into Calibration Report and update related setting entries
according to the results. The calibration controller can run in several modes,
fully automated run as a directed graph Kelly  _et al._ (2018), run selected
calibrators in a specified series or just run a single calibrator. High
flexibly is provided in calibration mode to meet the needs of experiments, a
calibrator can be triggered to run a partial calibration on a subset of its
responsible agents or run a series of calibration dividing then into subgroups
as opposed to calibrate all agents in parallel. With calibrators and
calibration controller, the bring up/calibration procedure can be largely
automated.

Figure S7: Experiment workflow. The QOS system works in a pipe-lined mode with
back pressure control, together with parallel processing at all pipeline
stages, software overhead is greatly reduced.

As a superconducting quantum system is unstable and its parameters drifts with
time, fast calibration is key to success. Performance is not just crucial for
the kernel, we also designed all the samplers and calibrators with high
performance in mind. We use a pipe-lined workflow for the whole system as show
in FIG. S7 to minimize software processing overhead. As a result, QOS can run
heavy weight experiments like parallel randomized benchmarking on large scale
quantum processor with negligible software time overhead. In this work of 66
qubits and 110 couplers, we can perform one round of routine calibration in
less than one hour, which includes single qubit gate calibration, single qubit
gate XEB fidelity calibration for all the qubits, two qubit gate calibration,
two qubit gate XEB fidelity calibration and learn iSWAP-like gate parameters
for all the couplers. This experiment time consumption will not grow
considerably as it is only limited by hardware time.

##  V Random quantum circuits

In each cycle of the random quantum circuit, single-qubit gates chosen
randomly from $\\{\sqrt{X},\sqrt{Y},\sqrt{W}\\}$ are first applied on all
qubits, and then two-qubit gates, iSWAP-like gate, are applied to pairs of
qubits. There are four types of patterns for two-qubit gate, labeled by A, B,
C and D respectively, which determine which two-qubit gates are executed on
each layer. Different from the single-qubit gates, the four patterns of A, B,
C, and D are implemented in the sequence of ABCDCDAB.

In our experiments, we implement random quantum circuits (RQCs) on the quantum
processor, and evaluate the time consumption of simulating these quantum
circuits on the traditional supercomputer. So far, there are mainly two types
of algorithms for simulating large RQCs: (1) tensor network algorithms Markov
and Shi (2008); Guo  _et al._ (2019); Villalonga  _et al._ (2019, 2020); Huang
_et al._ (2020); Pan and Zhang (2021); Guo  _et al._ (2021) and (2)
Schrödinger-Feynman algorithm (SFA). The time-consuming of the SFA is
significantly connected to the structure of four patterns A, B, C, and D,
which could be regarded as a criteria for designing the structure of RQCs. The
basic procedure of SFA can be summarized as follows: (1) Firstly, cut a
$n$-qubit quantum circuit into two partitions with $n_{1}$ and $n_{2}$ qubits.
(2) Then by summing all simulation paths that are the product of the terms of
the Schmidt decomposition of all cross-partition gates, one could obtain the
output state of the quantum circuit. The computational complexity of the
algorithm is proportional to $(2^{n_{1}}+2^{n_{2}})r^{g}$, where $r$ is the
Schmidt rank, and $g$ is the number of the cross-partition gates. The iSWAP-
like gate used in our scheme has the Schmidt rank of $r=4$. Thus, when
evaluating the runtime of the SFA, one needs to find the optimal cut with
$n_{1}$, $n_{2}$ and $g$ that makes the simulation task to become the easiest.
In addition, for a circuit cut, if the following formations occur, both $r$
and $g$ may be reduced, resulting in a reduction in the computational
complexity of the SFA algorithm:

1) Wedge formation. As shown in Fig. S8, a wedge formation is formed when two
consecutive cross-partition gates share a qubit, which can reduce the Schmidt
decomposition of resulting three-qubit unitary to only four terms.
Equivalently, every wedge reduces a cross-partition gate, and provides a
speedup of a factor of 4.

2) DCD formation. The DCD formation often happens at the boundary.
Specifically, the DCD formation appears when there are three successive two-
qubit gates acting on the qubit pairs $(a,b)$, $(b,c)$ and $(a,b)$, and these
three gates can be fused in one (the two gates on qubit pairs $(a,b)$ can be
fused). A DCD formation provides a speedup of a factor of 4.

3) Formation of iSWAP-like gates at the start and end of the circuit. The
iSWAP-like gate is the product of a iSWAP and controlled phase gate, and the
iSWAP gate can be applied either at the beginning or at the end of the
sequence. We apply this transformation to all iSWAP-like gates at the
beginning (end) of the circuit that affect qubits that are not affected by any
other two-qubit gate before (after) in the circuit. The iSWAP is then applied
to the input (output) qubits and their respective one-qubit gates trivially,
and the bond dimension remaining from this iSWAP-like gate is 2, corresponding
to a controlled phase gate, as opposed to the bond dimension 4 of the original
iSWAP-like gate. Thus, A iSWAP-like gate that appears at the same time in the
cross-partition and the beginning (or end) of the circuit can provide a
speedup of a factor of 2.

Figure S8: Wedge formation. The gate highlighted in blue and green on the cut
line are crosspartition gates. A wedge is formed when two consecutive
crosspartition gates share a qubit.

To ensure the computational complexity and classical hardness with low depth,
the number of cross-partition gates $g$ on the optimal cut should be large
enough, and the four patterns should be carefully designed to avoid the
occurrence of above three formations as much as possible.

Figure S9(a) shows an example of the topology of a quantum processor. The red
dot represents the qubit, and the black line represents the two-qubit gate
between two qubits. These two-qubit gates can be divided into two categories:
${G_{45^{\circ}}}$ and ${G_{135^{\circ}}}$, which are represented as 45 degree
lines (see Fig. S9(b)) and 135 degree lines (see Fig. S9(b)), respectively.
For efficient implementation on the quantum hardware, every two different two-
qubit gates in each pattern should not share the same qubit. Thus, pattern
${G_{45^{\circ}}}$ is split into pattern A and pattern B (see Fig. S9(c)).
Similarly, pattern ${G_{135^{\circ}}}$ is split into pattern C and pattern D
(see Fig. S9(d)). Patterns A, B, C, and D could have different structures, and
once pattern A (or C) is determined, then the structure of pattern B (or D) is
determined. To design the optimal patterns of A, B, C, and D for a specific
quantum processor, a search strategy is proposed as shown below:

(1) Set constraints, including the topology of the processor, the circuit
depth of RQC, the sequence of four patterns (usually ABCDCDAB), and the
maximum permissible number of two-qubit gates in the partition.

(2) Set the structures of patterns of A, B, C, and D.

(3) According to the conditions in (1) and (2), search for the optimal cuts
with the least number of effective crosspartition gates, where the number of
effective crosspartition gates $L$ is determined using the following formula,

$\displaystyle
L=g_{\text{cut}}-g_{\text{wedge}}-g_{\text{DCD}}-\frac{g_{{\text{start,end}}}}{2}$
(S1)

where $g_{\text{cut}}$ is the number of crosspartition gates,
$g_{\text{wedge}}$ is the number of wedge formations, $g_{\text{DCD}}$ is the
number of DCD formations, and $g_{{\text{start,end}}}$ is the number of the
formations of iSWAP-like gates at the start and end of the circuit. Step (3)
outputs the optimal cut and the number of corresponding effective
crosspartition gates, denoted as $\text{Min}_{L}$, which determines the
computational complexity of SFA for simulating the circuit designed with the
set patterns.

Repeat steps (2) and (3) to search for the optimal patterns that have the
maximum $\text{Min}_{L}$. Figure S10 and Figure S11 show the optimal patterns
of A, B, C, and D that we have searched for 56-qubit RQC with 20 cycles and
the corresponding promising cut, respectively.

Figure S9: The relationship of A, B, C, and D patterns. (a) An example of the
topology of a quantum processor. The red dot represents the qubit, and the
black line represents the two-qubit gate between two qubits. (b) These two-
qubit gates can be divided into two categories: ${G_{45^{\circ}}}$ and
${G_{135^{\circ}}}$, which are represented as 45 degree lines and 135 degree
lines, respectively. (c) The pattern ${G_{45^{\circ}}}$ is split into pattern
A and pattern B. (d) The pattern ${G_{135^{\circ}}}$ is split into pattern C
and pattern D. Patterns A, B, C, and D could have different structures, here
we list some examples of pattern C.  Figure S10: Coupler activation patterns
for 56 qubits. Coupler activation pattern for 56 qubits that determines which
qubits are allowed to interact simultaneously in a cycle.  Figure S11: Qubit
ordering and optimal cut for 56-qubit circuit with 20 cycles. This order
determines which qubits are used for $n$ qubits experiments. The green lines
form the optimal cut for 56-qubit circuit with 20 cycles.

##  VI XEB result analysis

###  VI.1 XEB fidelity

For a set of bitstrings $\\{q_{i}\\}$, the cross-entropy benchmarking (XEB)
fidelity is estimated from the ideal probabilities $\\{p_{i}=p_{s}(q_{i})\\}$
as

$F_{l}=\langle Dp\rangle-1$ (S2) $F_{c}=\langle\log(Dp)\rangle+\gamma$ (S3)

where $F_{l}$ is the linear XEB, $F_{c}$ is logarithmic XEB, and
$\gamma\approx 0.577$ is the Euler-Mascheroni constant.

###  VI.2 Prediction of circuit fidelity

As shown in Ref. Arute  _et al._ (2019), the predicted fidelity $F$ could be
calculated from a simple multiplication of individual operation fidelities as

$F{\rm{=}}\prod\limits_{g\in{G_{1}}}{(1-{e_{g}})}\prod\limits_{g\in{G_{2}}}{(1-{e_{g}})}\prod\limits_{q\in
Q}{(1-{e_{q}})}$ (S4)

where $e_{g}$ are the individual gate Pauli errors, $G_{1}$ and $G_{2}$ are
the set of single-qubit gates and two-qubit gates, respectively, $Q$ is the
set of qubits, and $e_{q}$ are the state preparation and measurement errors of
individual qubits.

###  VI.3 Performance of patch circuits and elided circuits

Considering that it is unrealistic to verify the fidelity of the large-scale
quantum circuits on current supercomputer, thus two verifiable quantum
circuits, patch circuits and elided circuits, are introduced to provide
approximate predictions of system performance. In the patch circuits, all two-
qubit gates across the partitions are elided, which is essentially two
disconnected circuits running in parallel. Compared to patch circuits, only a
fraction of the two-qubit gates along the cut during a few early cycles of the
sequence is elided in the elided circuits.

We evaluate the efficacy of using patch circuits and elided circuits for
performance estimation via a direct comparison with full circuits. In Fig.
S12, the XEB fidelities measured by full, patch and elided circuit of systems
from 15 to 56 qubits with 10 cycles are displayed. The fidelities derived from
patch and elided circuits exhibit a consistent exponential decay with system
size, and are in good agreement with the fidelities obtained with the
corresponding full circuits. The average ratio of patch circuit and elided
circuit fidelity to full circuit fidelity over all verification circuits are
found to be 1.05 and 1.10, with a standard deviation of 8% and 9%, dominated
by system fluctuations.

Figure S12: Performance of patch circuits and elided circuits. Patch, elided
and full circuit XEB fidelity from 15 to 56 qubits with 10 cycles, showing
patch and elided circuits yields a fidelity value that is in good agreement
with the one obtained with the corresponding full circuits. Each data point is
averaged over 6 quantum circuit instances.

###  VI.4 Distribution of bitstring probabilities

For a circuit with sufficient depth, the distribution should be consistent
with the theoretical prediction. For the bitstrings with fidelity using linear
XEB, the theoretical PDF for the bitstring probability $p$ is

$P_{l}(x|\hat{F_{l}})=(\hat{F_{l}}x+(1-\hat{F_{l}}))e^{-x}$ (S5)

where $x\equiv Dp$ is bitstring probability scaled by the dimension $D$.

The PDF for logarithmic XEB is

$P_{c}(x|\hat{F_{c}})=(1+\hat{F_{c}}(e^{x}-1))e^{x-e^{x}}$ (S6)

where $x\equiv log(Dp)$.

For our elided quantum circuit with 56 qubits and 20 cycles, we sample around
$1.9\times 10^{7}$ bitstrings from each of 10 instances and calculate the
linear XEB $\hat{F_{l}}$ or logarithmic XEB $\hat{F_{c}}$. Then we calculate
the ideal probability $p$ of each bitstring to check whether it fits the
theoretical curve $P_{l}(x|\hat{F_{l}})$ and $P_{c}(x|\hat{F_{c}})$. The
result of one circuit instance is shown in Fig. S13.

Figure S13: Distribution of bitstring probabilities from a 56-qubit 20 -cycle
circuit. The theoretical curve is computed with the experimental XEB fidelity
and experimental data is counted by histogram. (a) The theoretical curve
$P_{l}(x|\hat{F_{l}})$ and experimental distribution of $Dp$. (b) The
theoretical curve $P_{c}(x|\hat{F_{c}})$ and experimental distribution of
log($Dp$).

We further use Kolmogorov-Smirnov test (K-S test) Lehmann and Romano (2006) to
quantify the agreements between experiment data and theoretical curve. K-S
test quantifies a distance between the empirical cumulative distribution and
the hypothetic cumulative distribution function, denoted as $D_{KS}$. $D_{KS}$
can be converted to $p$-value according to Kolmogorov distribution function.
We use $p$-value to judge whether the hypothesis is good. We use kstest
function in the scipy package Jones  _et al._ (2001) with the null hypothesis
of $F=\hat{F}$. For comparison, we implement KS-test with the null hypothesis
of $F=0$ as well.

We measure the XEB and do KS-test with bitstrings from ten instances combined.
The linear XEB and logarithmic XEB fidelities from the combined bitstrings are
$\hat{F_{l}}=6.60\times 10^{-4}$ and $\hat{F_{c}}=5.80\times 10^{-4}$,
respectively. The KS-test results are shown in table S3. With null hypothesis
of $F=0$, the p-value is around $9.7\times 10^{-11}$. We can reject the null
hypothesis confidently.

| linear XEB | log XEB
---|---|---
hypothesis | $F=\hat{F_{l}}$ | $F=0$ | $F=\hat{F_{c}}$ | $F=0$
$p$-value | 0.23 | $9.7\times 10^{-11}$ | 0.66 | $9.7\times 10^{-11}$
Table S3: Results of combined Kolmogorov-Smirnov test for random circuits with
56-qubit, 20 cycles.

###  VI.5 Statistical uncertainties

We estimate the statistical uncertainty of XEB measurements with standard
error-on-mean formula

$\begin{array}[]{l}\hat{\sigma}_{F_{l}}=D\sqrt{\operatorname{Var}(p)/N_{s}},\\\
\hat{\sigma}_{F_{c}}=\sqrt{\operatorname{Var}(\log Dp)/N_{s}},\end{array}$
(S7)

where Var($x$) is the variance estimator of sample $\\{x_{i}\\}$. We use
inverse-variance weighting to estimate the fidelity and statistical
uncertainty of all nine 56-qubit and 20-cycle random circuits, yields the
results of $\hat{F_{l}}=(6.62\pm 0.72)\times 10^{-4}$ for linear XEB and
$\hat{F_{c}}=(5.82\pm 0.92)\times 10^{-4}$ for logarithmic XEB. The
theoretical prediction of the statistical uncertainty of linear XEB
$\hat{F_{l}}$ and logarithmic XEB $\hat{F_{c}}$ are

$\begin{array}[]{l}\hat{\sigma}_{F_{l}}=\sqrt{\left(1+2F-F^{2}\right)/N_{s}},\\\
\hat{\sigma}_{F_{c}}=\sqrt{\left(\pi^{2}/6-F^{2}\right)/N_{s}},\end{array}$
(S8)

which are calculated as $\hat{\sigma}_{F_{l}}=7.2\times 10^{-5}$ and
$\hat{\sigma}_{F_{c}}=9.2\times 10^{-5}$, respectively, indicating good
agreements between experiment and theory.

We further use bootstrap method to verify the estimate of statistical
uncertainties. For a 56-qubit 20-cycle circuit, we sample bitstrings from
experiment and calculate their ideal probabilities to be the original sample.
We acquire 2500 bootstrap samples from the original one and compute
$F=\hat{F_{l}}$, $F=\hat{F_{c}}$ of every sample. We expect the set of
$F=\hat{F}$ follow Gaussian distribution under the central limit theorem. The
fidelity distribution of bootstrap samples with Gaussian fit are shown in Fig.
S14. We compare the statistical uncertainty obtained from equation (S7),
Gaussian fit and the standard deviation of the bootstrap distribution. The
results are $2.41,2.40,2.36(\times 10^{-4})$ for $\hat{\sigma}_{F_{l}}$ and
$3.09,3.16,3.07(\times 10^{-4})$ for $\hat{\sigma}_{F_{c}}$. It indicates
great consistency within $3\%$ relative difference.

Figure S14: Fidelity distribution of bootstrap samples. (a) Linear XEB
distribution. (b) Log XEB distribution.

##  VII classical simulation

###  VII.1 The efficiency of Schrödinger simulator

In the hybrid SchrödingerFeynman algorithm (SFA) simulator, each path is
simulated using the Schrödinger algorithm (SA). The Schrödinger algorithm is a
full state vector simulator for simulating quantum circuit. It computes all
$2^{n}$ amplitudes, where $n$ is the number of qubits. In this section, we
will test the performance of the Schrödinger simulator.

Following the work in Ref. Arute  _et al._ (2019), gate fusion Smelyanskiy
_et al._ (2016) and single precision arithmetic are used in our simulator. We
simulate quantum circuits on a single node server that has 1536 GB memory and
four CPUs (Intel-Xeon-Gold-6254, 3.1G) with 18 cores each. To compare with the
performance of the Schrödinger simulator in Ref. Arute  _et al._ (2019), we
test random circuits with different sizes at depth 14. The run times are
listed in Table S4. Results show that the performance of our simulator is
basically the same as that of Google Arute  _et al._ (2019).

number of qubits |  | run time in seconds
---
(ours)
| run time in seconds
---
(Google’s Arute  _et al._ (2019))
$30$ | 24 | NA
$32$ | 93 | 111
$33$ | 190 | NA
$34$ | 362 | 473
$36$ | 1836 | 1954
Table S4: Circuit simulation run times using Schrödinger simulator.

###  VII.2 Tensor network simulator

Tensor network contraction (TNC) algorithm translates the task of computing a
single or a branch of amplitudes into contracting a tensor network, where each
tensor corresponds to a quantum gate operation. The complexity of TNC
algorithm is controled by the largest intermediate tensor which appears during
the contraction, which is also related to the tree width of the line graph
corresponding to the tensor network. As a result the ultimate performance of
TNC algorithm is determined by the underlying tensor contract path. In this
work we use the python package cotengra to find an optimal tensor contraction
path, which has been demonstrated to be able to reproduce the state of the art
results in Ref. Huang  _et al._ (2020); Pan and Zhang (2021). For each random
quantum circuit, we repeated the 100 path search procedure to determine the
optimal tensor contraction path and use its corresponding number of floating
point operations for contraction as the estimated computational cost.

In the main text, the modified frugal rejection sampling Arute  _et al._
(2019); Markov  _et al._ (2018) with acceptance probability $1$ is used to
estimate the cost of tensor network algorithm on specific circuits Villalonga
_et al._ (2019); Huang  _et al._ (2020). In Ref. Pan and Zhang (2021), a
subspace sampling trick is proposed, which has been proven to be able to fool
linear XEB. However, it is easy to distinguish this type of sampling, since
some positions in the sampled bitstrings are fixed to 0, such as
$x_{1}x_{2}x_{3}x_{4}00000000$, where $x_{i}$ is a variable bit.

In Ref. Huang  _et al._ (2020); Pan and Zhang (2021), the actual cost of
tensor network contraction using GPU is provided, which could be regard as
reference to estimate the actual cost of our circuit in supercomputer, such as
Summit (Summit has 27,648 GPUs in total, but Fugaku has no GPUs, therefore we
utilize Summit to determine the actual cost). Take the results in Ref. Huang
_et al._ (2020) as an example, it would cost 833.75s to generate one perfect
sample for a tensor network with $6.66\times 10^{18}$ contraction cost using
Summit. Thus, it would cost
$\frac{{1.10\times{{10}^{22}}}}{{6.66\times{{10}^{18}}}}\times
833.75\text{s}{\rm{=}}15.9$ days and
$\frac{{2.08\times{{10}^{24}}}}{{6.66\times{{10}^{18}}}}\times
833.75\text{s}{\rm{=}}8.24$ years to reproduce the same results as the
53-qubit 20-cycle circuit in Ref. Arute  _et al._ (2019) and our 56-qubit
20-cycle circuit using Summit.

###  VII.3 Computational cost estimation of SFA for the sampling task

Here, we estimate the computational cost of simulating 56 qubit full-circuits
using SFA. For the 56-qubit random circuit with 20 cycles, there are 42 gates
cross the cut. The iSWAP-like gate has a Schmidt rank of 4. However, the first
one and last three iSWAP-like gates can be simplified to cphase with a Schmidt
rank of 2. In the case of simulating quantum circuit with $100\%$ fidelity, a
total of $4^{38}\times 2^{4}$ paths must be calculated. By using the technique
of prefix Markov  _et al._ (2018) to optimize the simulator, we set a prefix
of 35 cross gates (a cross gate can be simplified to a cphase gate), thus
requiring $4^{34}\times 2^{1}$ separate runs.

We simulate the quantum circuit for the first 10 prefix values on a single
node server that has 1536 GB memory and four CPUs (Intel-Xeon-Gold-6254, 3.1G)
with 18 cores each. The average execution time for each prefix is 19560
seconds using single core and single thread. Thus, it is estimated that it
will consume $1.06\times 10^{18}$ core (two hyperthreads) hours to simulate
the 56-qubit 20-cycle circuit with 0.0662% fidelity. Table S5 also shows the
extrapolated run times for Google’s 53-qubit 20-cycle circuit Arute  _et al._
(2019) using our SFA simulator ($8.9\times 10^{13}$ core hours).

# of qubits | cycle | number of paths | fidelity | run time (years)
---|---|---|---|---
$53$ | 20 | $4^{31}\times 2^{4}$ | 0.224$\%$ | 1,332
$56$ | 20 |  $4^{38}\times 2^{4}$ (balance) | 0.0662$\%$ | 15,887,738
$56$ | 20 |  $4^{35}\times 2^{6}$ (imbalance) | 0.0662$\%$ | 8,612,623
Table S5: Run times of SFA using 7,630,848 CPU cores (the most powerful
supercomputer Fugaku has a total of 7,630,848 cores).

We note that in the results in Table S5, we also provide a result of using the
imbalance cut shown in Fig. S15, which consumes less time ($5.76\times
10^{17}$ core hours) but consumes more storage space. In addition, we did not
consider the DCD formation in our estimation. The DCD formation appears twice
in our 56-qubit 20-cycle circuit, and also twice in Google’s 53-qubit 20-cycle
circuits. Thus, after considering the simulating speedup by DCD formation, we
have

$\displaystyle\frac{{{T_{56\\_20}}}}{{{T_{53\\_20}}}}=\frac{{\frac{{8612623~{}\text{years}}}{{{4^{2}}}}}}{{\frac{{1332~{}\text{years}}}{{{4^{2}}}}}}\approx
6466$ (S9)

where ${{T_{56\\_20}}}$ and ${{T_{53\\_20}}}$ are the run time of simulating
our 56-qubit 20 cycle circuit and Google’s 53-qubit 20-cycle circuit,
respectively. That is, using the SFA algorithm, the computational cost of
simulating our 56-qubit 20-cycle circuit is about 6466 times that of Google’s
53-qubit 20-cycle circuit.

Figure S15: Imbalance cut. We set the allowed imbalance of two partitions to
20 ($n_{1}-n_{2}\leq 20$), and employ the search strategy in Section IV to
find the optimal cut. The number of qubits in the two partitions are 32 and
24, respectively.

###  VII.4 Classical speedup for imbalanced gates

The iSWAP-like$(\theta,\phi)$ gate has the following Schmidt singular values:

$\displaystyle{\lambda_{1}}$
$\displaystyle=\sqrt{1+2\cdot|cos(\phi/2)cos\theta|+co{s^{2}}\theta},$ (S10)
$\displaystyle{\lambda_{2}}$ $\displaystyle=\sin(\theta),$ (S11)
$\displaystyle{\lambda_{3}}$ $\displaystyle=\sin(\theta),$ (S12)
$\displaystyle{\lambda_{4}}$
$\displaystyle=\sqrt{1-2\cdot|cos(\phi/2)cos\theta|+co{s^{2}}\theta},$ (S13)

We have $\theta\approx\pi/2$ and $\phi\approx\pi/6$ in our experiment, so
${\lambda_{i}}\approx 1,{\kern 1.0pt}{\kern 1.0pt}\forall i\in\\{1,2,3,4\\}$.
When simulating the random circuit sampling with a target fidelity using SFA
simulator, inbalanced iSWAP-like gates can provide acceleration for the
simulation. According to the Ref. Arute  _et al._ (2019), if $100\%$ fidelity
is required, a total of $4^{g}$ paths must be calculated. However, given a
target fidelity, $F$, one need consider only the top $S$ paths with the
highest weight, making

$\displaystyle F=\sum\nolimits_{i=1}^{S}{\frac{{{W_{i}}}}{{{4^{g}}}}},$ (S14)

where
${W_{i}}=\lambda_{{i_{1}}}^{2}\lambda_{{i_{2}}}^{2}\ldots\lambda_{{i_{g}}}^{2}$
is the weight of each path arising from this decomposition. For comparison, if
all iSWAP-like gates are balanced with $\theta{\rm{=}}\pi/2$, the number of
paths needs to be considered is $F\times{4^{g}}$. Thus, imbalanced gates
provides a speedup equal to $\frac{S}{{F\times{4^{g}}}}$.

Figure S16: Cumulative probability distribution of $|{\delta_{\theta}}|$ for
iSWAP-like gates. In experiment, we have an average $|\delta_{\theta}|\approx
0.036$ for all iSWAP-like gates. The resulted speedup of classical simulation
is less than an order.  Figure S17: Classical speedup given by the imbalance
gates. We assume all iSWAP-like gates deviate from $\pi/2$ by the same
$\delta_{\theta}$ and calculate the speedup with given $g$ and $F$. Left:
speedup with varied fidelity $F$ and fixed $g=42$. Right: speedup with varied
g and fixed $F=0.0662\%$.  Figure S18: Runtime advantage region of different
error rates. The colored regions indicate classical runtime advantage beyond
the quantum computer within the limit of supercomputer memory. Runtime
advantage depends on the circuit depth $m$ and number of qubits $n$. Red and
blue region indicates SA advantage and SFA advantage, respectively. The black
contours indicate runtime of quantum computer. From (a) to (c), the average
error rates of quantum computer are $2\times,1\times,0.5\times$ our current
experimental error rates.

In our experiment, the iSWAP-like gate that need to be decomposed is iSWAP-
like$(\pi/2\pm{\delta_{\theta}},\phi\approx\pi/6)$, and $|{\delta_{\theta}}|$
has values of around 0.036 radians (see Fig. S16). The speedup can be achieved
from the imbalanced gates is shown in Fig. S17. For the case of random circuit
sampling with $n=56$ qubits and $m=20$ cycles, the fidelity is around
$F=0.0662\%$ and the number of iSWAP-like gate need to be decomposed is $g=42$
using SFA simulator, the speedup estimated would be well below an order of
magnitude (see Fig. S17).

###  VII.5 Quantum runtime advantage region

Tensor network algorithms may have higher simulation efficiency at low depths.
However, for large-scale quantum circuit with high depth, SFA is still the
most efficient algorithm at present. In this section, we first analyze the
scaling of the computational cost of SA and SFA, then we give a rough estimate
of the quantum runtime advantage region. There may be other classical
simulator with better performance, but this estimate is just to illustrate the
importance of improving the fidelity of quantum operations, including quantum
gates and readouts.

For a $n$-qubit quantum circuit with $m$ cycles, the runtime of SA is
estimated as

$T_{\text{SA}}=C_{\text{SA}}^{-1}\cdot mn\cdot 2^{n}$ (S15)

where the constant $C_{\text{SA}}$ is fit to the actual runtime of a state-of-
the-art supercomputer. SA needs $2^{n+1}$ bytes to store the complex state
vector. Considering that state-of-the-art supercomputers have less than 3 PB
of memory, the maximum number of qubits that can be simulated using the SA
simulator is 51 at most.

For SFA, the runtime is proportional to the number of paths and the time to
simulate patches. In Ref. Arute  _et al._ (2019), the circuit is cut into 2
patches. However, for larger-scale quantum circuits, we can cut the circuit
into more than 2 patches. According to the Ref. Zlokapa  _et al._ (2020), we
need to simulate the $2^{kpBm\sqrt{n}}F$ paths for $p$ patches, where
$k=1/2+1/p$, $B=0.24$, and $F$ is the fidelity of circuit. The time to
simulate each patch scales with $2^{n/p}$. In addition, we compute the partial
amplitudes of min$(F^{-2},2^{n})$ bitstrings after simulating each patch. In
total, the runtime is Zlokapa  _et al._ (2020)

$T_{\text{SFA}}=C_{\text{SFA}}^{-1}2^{kpBm\sqrt{n}}F(p2^{n/p}+\text{min}(F^{-2},2^{n})),$
(S16)

where $C_{\text{SFA}}$ is fit to the actual runtime of a state-of-the-art
supercomputer. We can optimize the runtime with $F^{-2}=p2^{n/p}$ for
$n>\text{log}_{2}(p)/(1-1/p)$. SFA requires $2p2^{n/p}$ bytes per path.
Assuming that each path is simulated by a single core, then we estimate the
total memory footprint to be $10^{6}\cdot 2p2^{n/p}$ for a supercomputer with
1M cores. Memory usage limits the number of patches, which should be taken
into account when optimizing the runtime of SFA.

We compare the runtime of classical simulation with quantum runtime to give a
rough estimate of the quantum runtime advantage region. For this purpose, we
use the classical fitting constants in Ref. Arute  _et al._ (2019) to continue
the discussion.

$\displaystyle C_{\text{SA}}=0.015\times 10^{6}\text{GHz}$ (S17)
$\displaystyle C_{\text{SFA}}=3.3\times 10^{6}\text{GHz}$

The runtime of quantum computer is proportional to the number of samples. To
ensure the standard deviation is less than the fidelity, i.e. $\sigma\leq
F_{\text{XEB}}$, at least $1/F^{2}$ samples are required. The runtime of
quantum computer scales as

$T_{\text{Q}}=\frac{1}{C_{\text{QC}}\cdot F^{2}}$ (S18)

where $C_{\text{QC}}=\frac{1}{230}$MHz is the actual sampling rate of our
quantum computer.

To compare the runtime of different methods, we fit constants in Eq. S17 and
$F$ from Eq. S4 into the runtime estimation discussed above and optimize the
runtime of SFA. In addition, the memory constraint is taken into account. The
result is shown in Fig.S18. The quantum advantage region (white) indicates the
ability of quantum computer beyond classical computer. It is worth mentioning
that the quantum advantage region enlarges rapidly when error rates decline,
indicating the importance of low error rates.

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